1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "rtl-error.h"
32 #include "insn-config.h"
39 #include "addresses.h"
40 #include "basic-block.h"
51 /* This file contains the reload pass of the compiler, which is
52 run after register allocation has been done. It checks that
53 each insn is valid (operands required to be in registers really
54 are in registers of the proper class) and fixes up invalid ones
55 by copying values temporarily into registers for the insns
58 The results of register allocation are described by the vector
59 reg_renumber; the insns still contain pseudo regs, but reg_renumber
60 can be used to find which hard reg, if any, a pseudo reg is in.
62 The technique we always use is to free up a few hard regs that are
63 called ``reload regs'', and for each place where a pseudo reg
64 must be in a hard reg, copy it temporarily into one of the reload regs.
66 Reload regs are allocated locally for every instruction that needs
67 reloads. When there are pseudos which are allocated to a register that
68 has been chosen as a reload reg, such pseudos must be ``spilled''.
69 This means that they go to other hard regs, or to stack slots if no other
70 available hard regs can be found. Spilling can invalidate more
71 insns, requiring additional need for reloads, so we must keep checking
72 until the process stabilizes.
74 For machines with different classes of registers, we must keep track
75 of the register class needed for each reload, and make sure that
76 we allocate enough reload registers of each class.
78 The file reload.c contains the code that checks one insn for
79 validity and reports the reloads that it needs. This file
80 is in charge of scanning the entire rtl code, accumulating the
81 reload needs, spilling, assigning reload registers to use for
82 fixing up each insn, and generating the new insns to copy values
83 into the reload registers. */
85 struct target_reload default_target_reload;
87 struct target_reload *this_target_reload = &default_target_reload;
90 #define spill_indirect_levels \
91 (this_target_reload->x_spill_indirect_levels)
93 /* During reload_as_needed, element N contains a REG rtx for the hard reg
94 into which reg N has been reloaded (perhaps for a previous insn). */
95 static rtx *reg_last_reload_reg;
97 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
98 for an output reload that stores into reg N. */
99 static regset_head reg_has_output_reload;
101 /* Indicates which hard regs are reload-registers for an output reload
102 in the current insn. */
103 static HARD_REG_SET reg_is_output_reload;
105 /* Widest width in which each pseudo reg is referred to (via subreg). */
106 static unsigned int *reg_max_ref_width;
108 /* Vector to remember old contents of reg_renumber before spilling. */
109 static short *reg_old_renumber;
111 /* During reload_as_needed, element N contains the last pseudo regno reloaded
112 into hard register N. If that pseudo reg occupied more than one register,
113 reg_reloaded_contents points to that pseudo for each spill register in
114 use; all of these must remain set for an inheritance to occur. */
115 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
117 /* During reload_as_needed, element N contains the insn for which
118 hard register N was last used. Its contents are significant only
119 when reg_reloaded_valid is set for this register. */
120 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
122 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
123 static HARD_REG_SET reg_reloaded_valid;
124 /* Indicate if the register was dead at the end of the reload.
125 This is only valid if reg_reloaded_contents is set and valid. */
126 static HARD_REG_SET reg_reloaded_dead;
128 /* Indicate whether the register's current value is one that is not
129 safe to retain across a call, even for registers that are normally
130 call-saved. This is only meaningful for members of reg_reloaded_valid. */
131 static HARD_REG_SET reg_reloaded_call_part_clobbered;
133 /* Number of spill-regs so far; number of valid elements of spill_regs. */
136 /* In parallel with spill_regs, contains REG rtx's for those regs.
137 Holds the last rtx used for any given reg, or 0 if it has never
138 been used for spilling yet. This rtx is reused, provided it has
140 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
142 /* In parallel with spill_regs, contains nonzero for a spill reg
143 that was stored after the last time it was used.
144 The precise value is the insn generated to do the store. */
145 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
147 /* This is the register that was stored with spill_reg_store. This is a
148 copy of reload_out / reload_out_reg when the value was stored; if
149 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
150 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
152 /* This table is the inverse mapping of spill_regs:
153 indexed by hard reg number,
154 it contains the position of that reg in spill_regs,
155 or -1 for something that is not in spill_regs.
157 ?!? This is no longer accurate. */
158 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
160 /* This reg set indicates registers that can't be used as spill registers for
161 the currently processed insn. These are the hard registers which are live
162 during the insn, but not allocated to pseudos, as well as fixed
164 static HARD_REG_SET bad_spill_regs;
166 /* These are the hard registers that can't be used as spill register for any
167 insn. This includes registers used for user variables and registers that
168 we can't eliminate. A register that appears in this set also can't be used
169 to retry register allocation. */
170 static HARD_REG_SET bad_spill_regs_global;
172 /* Describes order of use of registers for reloading
173 of spilled pseudo-registers. `n_spills' is the number of
174 elements that are actually valid; new ones are added at the end.
176 Both spill_regs and spill_reg_order are used on two occasions:
177 once during find_reload_regs, where they keep track of the spill registers
178 for a single insn, but also during reload_as_needed where they show all
179 the registers ever used by reload. For the latter case, the information
180 is calculated during finish_spills. */
181 static short spill_regs[FIRST_PSEUDO_REGISTER];
183 /* This vector of reg sets indicates, for each pseudo, which hard registers
184 may not be used for retrying global allocation because the register was
185 formerly spilled from one of them. If we allowed reallocating a pseudo to
186 a register that it was already allocated to, reload might not
188 static HARD_REG_SET *pseudo_previous_regs;
190 /* This vector of reg sets indicates, for each pseudo, which hard
191 registers may not be used for retrying global allocation because they
192 are used as spill registers during one of the insns in which the
194 static HARD_REG_SET *pseudo_forbidden_regs;
196 /* All hard regs that have been used as spill registers for any insn are
197 marked in this set. */
198 static HARD_REG_SET used_spill_regs;
200 /* Index of last register assigned as a spill register. We allocate in
201 a round-robin fashion. */
202 static int last_spill_reg;
204 /* Record the stack slot for each spilled hard register. */
205 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
207 /* Width allocated so far for that stack slot. */
208 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
210 /* Record which pseudos needed to be spilled. */
211 static regset_head spilled_pseudos;
213 /* Record which pseudos changed their allocation in finish_spills. */
214 static regset_head changed_allocation_pseudos;
216 /* Used for communication between order_regs_for_reload and count_pseudo.
217 Used to avoid counting one pseudo twice. */
218 static regset_head pseudos_counted;
220 /* First uid used by insns created by reload in this function.
221 Used in find_equiv_reg. */
222 int reload_first_uid;
224 /* Flag set by local-alloc or global-alloc if anything is live in
225 a call-clobbered reg across calls. */
226 int caller_save_needed;
228 /* Set to 1 while reload_as_needed is operating.
229 Required by some machines to handle any generated moves differently. */
230 int reload_in_progress = 0;
232 /* This obstack is used for allocation of rtl during register elimination.
233 The allocated storage can be freed once find_reloads has processed the
235 static struct obstack reload_obstack;
237 /* Points to the beginning of the reload_obstack. All insn_chain structures
238 are allocated first. */
239 static char *reload_startobj;
241 /* The point after all insn_chain structures. Used to quickly deallocate
242 memory allocated in copy_reloads during calculate_needs_all_insns. */
243 static char *reload_firstobj;
245 /* This points before all local rtl generated by register elimination.
246 Used to quickly free all memory after processing one insn. */
247 static char *reload_insn_firstobj;
249 /* List of insn_chain instructions, one for every insn that reload needs to
251 struct insn_chain *reload_insn_chain;
253 /* TRUE if we potentially left dead insns in the insn stream and want to
254 run DCE immediately after reload, FALSE otherwise. */
255 static bool need_dce;
257 /* List of all insns needing reloads. */
258 static struct insn_chain *insns_need_reload;
260 /* This structure is used to record information about register eliminations.
261 Each array entry describes one possible way of eliminating a register
262 in favor of another. If there is more than one way of eliminating a
263 particular register, the most preferred should be specified first. */
267 int from; /* Register number to be eliminated. */
268 int to; /* Register number used as replacement. */
269 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
270 int can_eliminate; /* Nonzero if this elimination can be done. */
271 int can_eliminate_previous; /* Value returned by TARGET_CAN_ELIMINATE
272 target hook in previous scan over insns
274 HOST_WIDE_INT offset; /* Current offset between the two regs. */
275 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
276 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
277 rtx from_rtx; /* REG rtx for the register to be eliminated.
278 We cannot simply compare the number since
279 we might then spuriously replace a hard
280 register corresponding to a pseudo
281 assigned to the reg to be eliminated. */
282 rtx to_rtx; /* REG rtx for the replacement. */
285 static struct elim_table *reg_eliminate = 0;
287 /* This is an intermediate structure to initialize the table. It has
288 exactly the members provided by ELIMINABLE_REGS. */
289 static const struct elim_table_1
293 } reg_eliminate_1[] =
295 /* If a set of eliminable registers was specified, define the table from it.
296 Otherwise, default to the normal case of the frame pointer being
297 replaced by the stack pointer. */
299 #ifdef ELIMINABLE_REGS
302 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
305 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
307 /* Record the number of pending eliminations that have an offset not equal
308 to their initial offset. If nonzero, we use a new copy of each
309 replacement result in any insns encountered. */
310 int num_not_at_initial_offset;
312 /* Count the number of registers that we may be able to eliminate. */
313 static int num_eliminable;
314 /* And the number of registers that are equivalent to a constant that
315 can be eliminated to frame_pointer / arg_pointer + constant. */
316 static int num_eliminable_invariants;
318 /* For each label, we record the offset of each elimination. If we reach
319 a label by more than one path and an offset differs, we cannot do the
320 elimination. This information is indexed by the difference of the
321 number of the label and the first label number. We can't offset the
322 pointer itself as this can cause problems on machines with segmented
323 memory. The first table is an array of flags that records whether we
324 have yet encountered a label and the second table is an array of arrays,
325 one entry in the latter array for each elimination. */
327 static int first_label_num;
328 static char *offsets_known_at;
329 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
331 VEC(reg_equivs_t,gc) *reg_equivs;
333 /* Stack of addresses where an rtx has been changed. We can undo the
334 changes by popping items off the stack and restoring the original
335 value at each location.
337 We use this simplistic undo capability rather than copy_rtx as copy_rtx
338 will not make a deep copy of a normally sharable rtx, such as
339 (const (plus (symbol_ref) (const_int))). If such an expression appears
340 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
341 rtx expression would be changed. See PR 42431. */
345 DEF_VEC_ALLOC_P(rtx_p,heap);
346 static VEC(rtx_p,heap) *substitute_stack;
348 /* Number of labels in the current function. */
350 static int num_labels;
352 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
353 static void maybe_fix_stack_asms (void);
354 static void copy_reloads (struct insn_chain *);
355 static void calculate_needs_all_insns (int);
356 static int find_reg (struct insn_chain *, int);
357 static void find_reload_regs (struct insn_chain *);
358 static void select_reload_regs (void);
359 static void delete_caller_save_insns (void);
361 static void spill_failure (rtx, enum reg_class);
362 static void count_spilled_pseudo (int, int, int);
363 static void delete_dead_insn (rtx);
364 static void alter_reg (int, int, bool);
365 static void set_label_offsets (rtx, rtx, int);
366 static void check_eliminable_occurrences (rtx);
367 static void elimination_effects (rtx, enum machine_mode);
368 static rtx eliminate_regs_1 (rtx, enum machine_mode, rtx, bool, bool);
369 static int eliminate_regs_in_insn (rtx, int);
370 static void update_eliminable_offsets (void);
371 static void mark_not_eliminable (rtx, const_rtx, void *);
372 static void set_initial_elim_offsets (void);
373 static bool verify_initial_elim_offsets (void);
374 static void set_initial_label_offsets (void);
375 static void set_offsets_for_label (rtx);
376 static void init_eliminable_invariants (rtx, bool);
377 static void init_elim_table (void);
378 static void free_reg_equiv (void);
379 static void update_eliminables (HARD_REG_SET *);
380 static void elimination_costs_in_insn (rtx);
381 static void spill_hard_reg (unsigned int, int);
382 static int finish_spills (int);
383 static void scan_paradoxical_subregs (rtx);
384 static void count_pseudo (int);
385 static void order_regs_for_reload (struct insn_chain *);
386 static void reload_as_needed (int);
387 static void forget_old_reloads_1 (rtx, const_rtx, void *);
388 static void forget_marked_reloads (regset);
389 static int reload_reg_class_lower (const void *, const void *);
390 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
392 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
394 static int reload_reg_free_p (unsigned int, int, enum reload_type);
395 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
397 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
399 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
400 static int allocate_reload_reg (struct insn_chain *, int, int);
401 static int conflicts_with_override (rtx);
402 static void failed_reload (rtx, int);
403 static int set_reload_reg (int, int);
404 static void choose_reload_regs_init (struct insn_chain *, rtx *);
405 static void choose_reload_regs (struct insn_chain *);
406 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
408 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
410 static void do_input_reload (struct insn_chain *, struct reload *, int);
411 static void do_output_reload (struct insn_chain *, struct reload *, int);
412 static void emit_reload_insns (struct insn_chain *);
413 static void delete_output_reload (rtx, int, int, rtx);
414 static void delete_address_reloads (rtx, rtx);
415 static void delete_address_reloads_1 (rtx, rtx, rtx);
416 static void inc_for_reload (rtx, rtx, rtx, int);
418 static void add_auto_inc_notes (rtx, rtx);
420 static void substitute (rtx *, const_rtx, rtx);
421 static bool gen_reload_chain_without_interm_reg_p (int, int);
422 static int reloads_conflict (int, int);
423 static rtx gen_reload (rtx, rtx, int, enum reload_type);
424 static rtx emit_insn_if_valid_for_reload (rtx);
426 /* Initialize the reload pass. This is called at the beginning of compilation
427 and may be called again if the target is reinitialized. */
434 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
435 Set spill_indirect_levels to the number of levels such addressing is
436 permitted, zero if it is not permitted at all. */
439 = gen_rtx_MEM (Pmode,
442 LAST_VIRTUAL_REGISTER + 1),
444 spill_indirect_levels = 0;
446 while (memory_address_p (QImode, tem))
448 spill_indirect_levels++;
449 tem = gen_rtx_MEM (Pmode, tem);
452 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
454 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
455 indirect_symref_ok = memory_address_p (QImode, tem);
457 /* See if reg+reg is a valid (and offsettable) address. */
459 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
461 tem = gen_rtx_PLUS (Pmode,
462 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
463 gen_rtx_REG (Pmode, i));
465 /* This way, we make sure that reg+reg is an offsettable address. */
466 tem = plus_constant (tem, 4);
468 if (memory_address_p (QImode, tem))
470 double_reg_address_ok = 1;
475 /* Initialize obstack for our rtl allocation. */
476 gcc_obstack_init (&reload_obstack);
477 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
479 INIT_REG_SET (&spilled_pseudos);
480 INIT_REG_SET (&changed_allocation_pseudos);
481 INIT_REG_SET (&pseudos_counted);
484 /* List of insn chains that are currently unused. */
485 static struct insn_chain *unused_insn_chains = 0;
487 /* Allocate an empty insn_chain structure. */
489 new_insn_chain (void)
491 struct insn_chain *c;
493 if (unused_insn_chains == 0)
495 c = XOBNEW (&reload_obstack, struct insn_chain);
496 INIT_REG_SET (&c->live_throughout);
497 INIT_REG_SET (&c->dead_or_set);
501 c = unused_insn_chains;
502 unused_insn_chains = c->next;
504 c->is_caller_save_insn = 0;
505 c->need_operand_change = 0;
511 /* Small utility function to set all regs in hard reg set TO which are
512 allocated to pseudos in regset FROM. */
515 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
518 reg_set_iterator rsi;
520 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
522 int r = reg_renumber[regno];
526 /* reload_combine uses the information from DF_LIVE_IN,
527 which might still contain registers that have not
528 actually been allocated since they have an
530 gcc_assert (ira_conflicts_p || reload_completed);
533 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
537 /* Replace all pseudos found in LOC with their corresponding
541 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
554 unsigned int regno = REGNO (x);
556 if (regno < FIRST_PSEUDO_REGISTER)
559 x = eliminate_regs_1 (x, mem_mode, usage, true, false);
563 replace_pseudos_in (loc, mem_mode, usage);
567 if (reg_equiv_constant (regno))
568 *loc = reg_equiv_constant (regno);
569 else if (reg_equiv_invariant (regno))
570 *loc = reg_equiv_invariant (regno);
571 else if (reg_equiv_mem (regno))
572 *loc = reg_equiv_mem (regno);
573 else if (reg_equiv_address (regno))
574 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address (regno));
577 gcc_assert (!REG_P (regno_reg_rtx[regno])
578 || REGNO (regno_reg_rtx[regno]) != regno);
579 *loc = regno_reg_rtx[regno];
584 else if (code == MEM)
586 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
590 /* Process each of our operands recursively. */
591 fmt = GET_RTX_FORMAT (code);
592 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
594 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
595 else if (*fmt == 'E')
596 for (j = 0; j < XVECLEN (x, i); j++)
597 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
600 /* Determine if the current function has an exception receiver block
601 that reaches the exit block via non-exceptional edges */
604 has_nonexceptional_receiver (void)
608 basic_block *tos, *worklist, bb;
610 /* If we're not optimizing, then just err on the safe side. */
614 /* First determine which blocks can reach exit via normal paths. */
615 tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1);
618 bb->flags &= ~BB_REACHABLE;
620 /* Place the exit block on our worklist. */
621 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
622 *tos++ = EXIT_BLOCK_PTR;
624 /* Iterate: find everything reachable from what we've already seen. */
625 while (tos != worklist)
629 FOR_EACH_EDGE (e, ei, bb->preds)
630 if (!(e->flags & EDGE_ABNORMAL))
632 basic_block src = e->src;
634 if (!(src->flags & BB_REACHABLE))
636 src->flags |= BB_REACHABLE;
643 /* Now see if there's a reachable block with an exceptional incoming
646 if (bb->flags & BB_REACHABLE && bb_has_abnormal_pred (bb))
649 /* No exceptional block reached exit unexceptionally. */
653 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
654 zero elements) to MAX_REG_NUM elements.
656 Initialize all new fields to NULL and update REG_EQUIVS_SIZE. */
658 grow_reg_equivs (void)
660 int old_size = VEC_length (reg_equivs_t, reg_equivs);
661 int max_regno = max_reg_num ();
664 VEC_reserve (reg_equivs_t, gc, reg_equivs, max_regno);
665 for (i = old_size; i < max_regno; i++)
667 VEC_quick_insert (reg_equivs_t, reg_equivs, i, 0);
668 memset (VEC_index (reg_equivs_t, reg_equivs, i), 0, sizeof (reg_equivs_t));
674 /* Global variables used by reload and its subroutines. */
676 /* The current basic block while in calculate_elim_costs_all_insns. */
677 static basic_block elim_bb;
679 /* Set during calculate_needs if an insn needs register elimination. */
680 static int something_needs_elimination;
681 /* Set during calculate_needs if an insn needs an operand changed. */
682 static int something_needs_operands_changed;
683 /* Set by alter_regs if we spilled a register to the stack. */
684 static bool something_was_spilled;
686 /* Nonzero means we couldn't get enough spill regs. */
689 /* Temporary array of pseudo-register number. */
690 static int *temp_pseudo_reg_arr;
692 /* Main entry point for the reload pass.
694 FIRST is the first insn of the function being compiled.
696 GLOBAL nonzero means we were called from global_alloc
697 and should attempt to reallocate any pseudoregs that we
698 displace from hard regs we will use for reloads.
699 If GLOBAL is zero, we do not have enough information to do that,
700 so any pseudo reg that is spilled must go to the stack.
702 Return value is TRUE if reload likely left dead insns in the
703 stream and a DCE pass should be run to elimiante them. Else the
704 return value is FALSE. */
707 reload (rtx first, int global)
711 struct elim_table *ep;
715 /* Make sure even insns with volatile mem refs are recognizable. */
720 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
722 /* Make sure that the last insn in the chain
723 is not something that needs reloading. */
724 emit_note (NOTE_INSN_DELETED);
726 /* Enable find_equiv_reg to distinguish insns made by reload. */
727 reload_first_uid = get_max_uid ();
729 #ifdef SECONDARY_MEMORY_NEEDED
730 /* Initialize the secondary memory table. */
731 clear_secondary_mem ();
734 /* We don't have a stack slot for any spill reg yet. */
735 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
736 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
738 /* Initialize the save area information for caller-save, in case some
742 /* Compute which hard registers are now in use
743 as homes for pseudo registers.
744 This is done here rather than (eg) in global_alloc
745 because this point is reached even if not optimizing. */
746 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
749 /* A function that has a nonlocal label that can reach the exit
750 block via non-exceptional paths must save all call-saved
752 if (cfun->has_nonlocal_label
753 && has_nonexceptional_receiver ())
754 crtl->saves_all_registers = 1;
756 if (crtl->saves_all_registers)
757 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
758 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
759 df_set_regs_ever_live (i, true);
761 /* Find all the pseudo registers that didn't get hard regs
762 but do have known equivalent constants or memory slots.
763 These include parameters (known equivalent to parameter slots)
764 and cse'd or loop-moved constant memory addresses.
766 Record constant equivalents in reg_equiv_constant
767 so they will be substituted by find_reloads.
768 Record memory equivalents in reg_mem_equiv so they can
769 be substituted eventually by altering the REG-rtx's. */
772 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
773 reg_old_renumber = XCNEWVEC (short, max_regno);
774 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
775 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
776 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
778 CLEAR_HARD_REG_SET (bad_spill_regs_global);
780 init_eliminable_invariants (first, true);
783 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
784 stack slots to the pseudos that lack hard regs or equivalents.
785 Do not touch virtual registers. */
787 temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
788 for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
789 temp_pseudo_reg_arr[n++] = i;
792 /* Ask IRA to order pseudo-registers for better stack slot
794 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
796 for (i = 0; i < n; i++)
797 alter_reg (temp_pseudo_reg_arr[i], -1, false);
799 /* If we have some registers we think can be eliminated, scan all insns to
800 see if there is an insn that sets one of these registers to something
801 other than itself plus a constant. If so, the register cannot be
802 eliminated. Doing this scan here eliminates an extra pass through the
803 main reload loop in the most common case where register elimination
805 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
807 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
809 maybe_fix_stack_asms ();
811 insns_need_reload = 0;
812 something_needs_elimination = 0;
814 /* Initialize to -1, which means take the first spill register. */
817 /* Spill any hard regs that we know we can't eliminate. */
818 CLEAR_HARD_REG_SET (used_spill_regs);
819 /* There can be multiple ways to eliminate a register;
820 they should be listed adjacently.
821 Elimination for any register fails only if all possible ways fail. */
822 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
825 int can_eliminate = 0;
828 can_eliminate |= ep->can_eliminate;
831 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
833 spill_hard_reg (from, 1);
836 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
837 if (frame_pointer_needed)
838 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
840 finish_spills (global);
842 /* From now on, we may need to generate moves differently. We may also
843 allow modifications of insns which cause them to not be recognized.
844 Any such modifications will be cleaned up during reload itself. */
845 reload_in_progress = 1;
847 /* This loop scans the entire function each go-round
848 and repeats until one repetition spills no additional hard regs. */
851 int something_changed;
853 HOST_WIDE_INT starting_frame_size;
855 starting_frame_size = get_frame_size ();
856 something_was_spilled = false;
858 set_initial_elim_offsets ();
859 set_initial_label_offsets ();
861 /* For each pseudo register that has an equivalent location defined,
862 try to eliminate any eliminable registers (such as the frame pointer)
863 assuming initial offsets for the replacement register, which
866 If the resulting location is directly addressable, substitute
867 the MEM we just got directly for the old REG.
869 If it is not addressable but is a constant or the sum of a hard reg
870 and constant, it is probably not addressable because the constant is
871 out of range, in that case record the address; we will generate
872 hairy code to compute the address in a register each time it is
873 needed. Similarly if it is a hard register, but one that is not
874 valid as an address register.
876 If the location is not addressable, but does not have one of the
877 above forms, assign a stack slot. We have to do this to avoid the
878 potential of producing lots of reloads if, e.g., a location involves
879 a pseudo that didn't get a hard register and has an equivalent memory
880 location that also involves a pseudo that didn't get a hard register.
882 Perhaps at some point we will improve reload_when_needed handling
883 so this problem goes away. But that's very hairy. */
885 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
886 if (reg_renumber[i] < 0 && reg_equiv_memory_loc (i))
888 rtx x = eliminate_regs (reg_equiv_memory_loc (i), VOIDmode,
891 if (strict_memory_address_addr_space_p
892 (GET_MODE (regno_reg_rtx[i]), XEXP (x, 0),
894 reg_equiv_mem (i) = x, reg_equiv_address (i) = 0;
895 else if (CONSTANT_P (XEXP (x, 0))
896 || (REG_P (XEXP (x, 0))
897 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
898 || (GET_CODE (XEXP (x, 0)) == PLUS
899 && REG_P (XEXP (XEXP (x, 0), 0))
900 && (REGNO (XEXP (XEXP (x, 0), 0))
901 < FIRST_PSEUDO_REGISTER)
902 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
903 reg_equiv_address (i) = XEXP (x, 0), reg_equiv_mem (i) = 0;
906 /* Make a new stack slot. Then indicate that something
907 changed so we go back and recompute offsets for
908 eliminable registers because the allocation of memory
909 below might change some offset. reg_equiv_{mem,address}
910 will be set up for this pseudo on the next pass around
912 reg_equiv_memory_loc (i) = 0;
913 reg_equiv_init (i) = 0;
914 alter_reg (i, -1, true);
918 if (caller_save_needed)
921 /* If we allocated another stack slot, redo elimination bookkeeping. */
922 if (something_was_spilled || starting_frame_size != get_frame_size ())
924 if (starting_frame_size && crtl->stack_alignment_needed)
926 /* If we have a stack frame, we must align it now. The
927 stack size may be a part of the offset computation for
928 register elimination. So if this changes the stack size,
929 then repeat the elimination bookkeeping. We don't
930 realign when there is no stack, as that will cause a
931 stack frame when none is needed should
932 STARTING_FRAME_OFFSET not be already aligned to
934 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
935 if (starting_frame_size != get_frame_size ())
939 if (caller_save_needed)
941 save_call_clobbered_regs ();
942 /* That might have allocated new insn_chain structures. */
943 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
946 calculate_needs_all_insns (global);
948 if (! ira_conflicts_p)
949 /* Don't do it for IRA. We need this info because we don't
950 change live_throughout and dead_or_set for chains when IRA
952 CLEAR_REG_SET (&spilled_pseudos);
956 something_changed = 0;
958 /* If we allocated any new memory locations, make another pass
959 since it might have changed elimination offsets. */
960 if (something_was_spilled || starting_frame_size != get_frame_size ())
961 something_changed = 1;
963 /* Even if the frame size remained the same, we might still have
964 changed elimination offsets, e.g. if find_reloads called
965 force_const_mem requiring the back end to allocate a constant
966 pool base register that needs to be saved on the stack. */
967 else if (!verify_initial_elim_offsets ())
968 something_changed = 1;
971 HARD_REG_SET to_spill;
972 CLEAR_HARD_REG_SET (to_spill);
973 update_eliminables (&to_spill);
974 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
976 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
977 if (TEST_HARD_REG_BIT (to_spill, i))
979 spill_hard_reg (i, 1);
982 /* Regardless of the state of spills, if we previously had
983 a register that we thought we could eliminate, but now can
984 not eliminate, we must run another pass.
986 Consider pseudos which have an entry in reg_equiv_* which
987 reference an eliminable register. We must make another pass
988 to update reg_equiv_* so that we do not substitute in the
989 old value from when we thought the elimination could be
991 something_changed = 1;
995 select_reload_regs ();
999 if (insns_need_reload != 0 || did_spill)
1000 something_changed |= finish_spills (global);
1002 if (! something_changed)
1005 if (caller_save_needed)
1006 delete_caller_save_insns ();
1008 obstack_free (&reload_obstack, reload_firstobj);
1011 /* If global-alloc was run, notify it of any register eliminations we have
1014 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1015 if (ep->can_eliminate)
1016 mark_elimination (ep->from, ep->to);
1018 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1019 If that insn didn't set the register (i.e., it copied the register to
1020 memory), just delete that insn instead of the equivalencing insn plus
1021 anything now dead. If we call delete_dead_insn on that insn, we may
1022 delete the insn that actually sets the register if the register dies
1023 there and that is incorrect. */
1025 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1027 if (reg_renumber[i] < 0 && reg_equiv_init (i) != 0)
1030 for (list = reg_equiv_init (i); list; list = XEXP (list, 1))
1032 rtx equiv_insn = XEXP (list, 0);
1034 /* If we already deleted the insn or if it may trap, we can't
1035 delete it. The latter case shouldn't happen, but can
1036 if an insn has a variable address, gets a REG_EH_REGION
1037 note added to it, and then gets converted into a load
1038 from a constant address. */
1039 if (NOTE_P (equiv_insn)
1040 || can_throw_internal (equiv_insn))
1042 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1043 delete_dead_insn (equiv_insn);
1045 SET_INSN_DELETED (equiv_insn);
1050 /* Use the reload registers where necessary
1051 by generating move instructions to move the must-be-register
1052 values into or out of the reload registers. */
1054 if (insns_need_reload != 0 || something_needs_elimination
1055 || something_needs_operands_changed)
1057 HOST_WIDE_INT old_frame_size = get_frame_size ();
1059 reload_as_needed (global);
1061 gcc_assert (old_frame_size == get_frame_size ());
1063 gcc_assert (verify_initial_elim_offsets ());
1066 /* If we were able to eliminate the frame pointer, show that it is no
1067 longer live at the start of any basic block. If it ls live by
1068 virtue of being in a pseudo, that pseudo will be marked live
1069 and hence the frame pointer will be known to be live via that
1072 if (! frame_pointer_needed)
1074 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1076 /* Come here (with failure set nonzero) if we can't get enough spill
1080 CLEAR_REG_SET (&changed_allocation_pseudos);
1081 CLEAR_REG_SET (&spilled_pseudos);
1082 reload_in_progress = 0;
1084 /* Now eliminate all pseudo regs by modifying them into
1085 their equivalent memory references.
1086 The REG-rtx's for the pseudos are modified in place,
1087 so all insns that used to refer to them now refer to memory.
1089 For a reg that has a reg_equiv_address, all those insns
1090 were changed by reloading so that no insns refer to it any longer;
1091 but the DECL_RTL of a variable decl may refer to it,
1092 and if so this causes the debugging info to mention the variable. */
1094 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1098 if (reg_equiv_mem (i))
1099 addr = XEXP (reg_equiv_mem (i), 0);
1101 if (reg_equiv_address (i))
1102 addr = reg_equiv_address (i);
1106 if (reg_renumber[i] < 0)
1108 rtx reg = regno_reg_rtx[i];
1110 REG_USERVAR_P (reg) = 0;
1111 PUT_CODE (reg, MEM);
1112 XEXP (reg, 0) = addr;
1113 if (reg_equiv_memory_loc (i))
1114 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc (i));
1117 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1118 MEM_ATTRS (reg) = 0;
1120 MEM_NOTRAP_P (reg) = 1;
1122 else if (reg_equiv_mem (i))
1123 XEXP (reg_equiv_mem (i), 0) = addr;
1126 /* We don't want complex addressing modes in debug insns
1127 if simpler ones will do, so delegitimize equivalences
1129 if (MAY_HAVE_DEBUG_INSNS && reg_renumber[i] < 0)
1131 rtx reg = regno_reg_rtx[i];
1135 if (reg_equiv_constant (i))
1136 equiv = reg_equiv_constant (i);
1137 else if (reg_equiv_invariant (i))
1138 equiv = reg_equiv_invariant (i);
1139 else if (reg && MEM_P (reg))
1140 equiv = targetm.delegitimize_address (reg);
1141 else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
1147 for (use = DF_REG_USE_CHAIN (i); use; use = next)
1149 insn = DF_REF_INSN (use);
1151 /* Make sure the next ref is for a different instruction,
1152 so that we're not affected by the rescan. */
1153 next = DF_REF_NEXT_REG (use);
1154 while (next && DF_REF_INSN (next) == insn)
1155 next = DF_REF_NEXT_REG (next);
1157 if (DEBUG_INSN_P (insn))
1161 INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
1162 df_insn_rescan_debug_internal (insn);
1165 INSN_VAR_LOCATION_LOC (insn)
1166 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn),
1173 /* We must set reload_completed now since the cleanup_subreg_operands call
1174 below will re-recognize each insn and reload may have generated insns
1175 which are only valid during and after reload. */
1176 reload_completed = 1;
1178 /* Make a pass over all the insns and delete all USEs which we inserted
1179 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1180 notes. Delete all CLOBBER insns, except those that refer to the return
1181 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1182 from misarranging variable-array code, and simplify (subreg (reg))
1183 operands. Strip and regenerate REG_INC notes that may have been moved
1186 for (insn = first; insn; insn = NEXT_INSN (insn))
1192 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1193 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1195 if ((GET_CODE (PATTERN (insn)) == USE
1196 /* We mark with QImode USEs introduced by reload itself. */
1197 && (GET_MODE (insn) == QImode
1198 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1199 || (GET_CODE (PATTERN (insn)) == CLOBBER
1200 && (!MEM_P (XEXP (PATTERN (insn), 0))
1201 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1202 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1203 && XEXP (XEXP (PATTERN (insn), 0), 0)
1204 != stack_pointer_rtx))
1205 && (!REG_P (XEXP (PATTERN (insn), 0))
1206 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1212 /* Some CLOBBERs may survive until here and still reference unassigned
1213 pseudos with const equivalent, which may in turn cause ICE in later
1214 passes if the reference remains in place. */
1215 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1216 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1217 VOIDmode, PATTERN (insn));
1219 /* Discard obvious no-ops, even without -O. This optimization
1220 is fast and doesn't interfere with debugging. */
1221 if (NONJUMP_INSN_P (insn)
1222 && GET_CODE (PATTERN (insn)) == SET
1223 && REG_P (SET_SRC (PATTERN (insn)))
1224 && REG_P (SET_DEST (PATTERN (insn)))
1225 && (REGNO (SET_SRC (PATTERN (insn)))
1226 == REGNO (SET_DEST (PATTERN (insn)))))
1232 pnote = ®_NOTES (insn);
1235 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1236 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1237 || REG_NOTE_KIND (*pnote) == REG_INC)
1238 *pnote = XEXP (*pnote, 1);
1240 pnote = &XEXP (*pnote, 1);
1244 add_auto_inc_notes (insn, PATTERN (insn));
1247 /* Simplify (subreg (reg)) if it appears as an operand. */
1248 cleanup_subreg_operands (insn);
1250 /* Clean up invalid ASMs so that they don't confuse later passes.
1252 if (asm_noperands (PATTERN (insn)) >= 0)
1254 extract_insn (insn);
1255 if (!constrain_operands (1))
1257 error_for_asm (insn,
1258 "%<asm%> operand has impossible constraints");
1265 /* If we are doing generic stack checking, give a warning if this
1266 function's frame size is larger than we expect. */
1267 if (flag_stack_check == GENERIC_STACK_CHECK)
1269 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1270 static int verbose_warned = 0;
1272 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1273 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1274 size += UNITS_PER_WORD;
1276 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1278 warning (0, "frame size too large for reliable stack checking");
1279 if (! verbose_warned)
1281 warning (0, "try reducing the number of local variables");
1287 free (temp_pseudo_reg_arr);
1289 /* Indicate that we no longer have known memory locations or constants. */
1292 free (reg_max_ref_width);
1293 free (reg_old_renumber);
1294 free (pseudo_previous_regs);
1295 free (pseudo_forbidden_regs);
1297 CLEAR_HARD_REG_SET (used_spill_regs);
1298 for (i = 0; i < n_spills; i++)
1299 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1301 /* Free all the insn_chain structures at once. */
1302 obstack_free (&reload_obstack, reload_startobj);
1303 unused_insn_chains = 0;
1305 inserted = fixup_abnormal_edges ();
1307 /* We've possibly turned single trapping insn into multiple ones. */
1308 if (cfun->can_throw_non_call_exceptions)
1311 blocks = sbitmap_alloc (last_basic_block);
1312 sbitmap_ones (blocks);
1313 find_many_sub_basic_blocks (blocks);
1314 sbitmap_free (blocks);
1318 commit_edge_insertions ();
1320 /* Replacing pseudos with their memory equivalents might have
1321 created shared rtx. Subsequent passes would get confused
1322 by this, so unshare everything here. */
1323 unshare_all_rtl_again (first);
1325 #ifdef STACK_BOUNDARY
1326 /* init_emit has set the alignment of the hard frame pointer
1327 to STACK_BOUNDARY. It is very likely no longer valid if
1328 the hard frame pointer was used for register allocation. */
1329 if (!frame_pointer_needed)
1330 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1333 VEC_free (rtx_p, heap, substitute_stack);
1335 gcc_assert (bitmap_empty_p (&spilled_pseudos));
1337 reload_completed = !failure;
1342 /* Yet another special case. Unfortunately, reg-stack forces people to
1343 write incorrect clobbers in asm statements. These clobbers must not
1344 cause the register to appear in bad_spill_regs, otherwise we'll call
1345 fatal_insn later. We clear the corresponding regnos in the live
1346 register sets to avoid this.
1347 The whole thing is rather sick, I'm afraid. */
1350 maybe_fix_stack_asms (void)
1353 const char *constraints[MAX_RECOG_OPERANDS];
1354 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1355 struct insn_chain *chain;
1357 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1360 HARD_REG_SET clobbered, allowed;
1363 if (! INSN_P (chain->insn)
1364 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1366 pat = PATTERN (chain->insn);
1367 if (GET_CODE (pat) != PARALLEL)
1370 CLEAR_HARD_REG_SET (clobbered);
1371 CLEAR_HARD_REG_SET (allowed);
1373 /* First, make a mask of all stack regs that are clobbered. */
1374 for (i = 0; i < XVECLEN (pat, 0); i++)
1376 rtx t = XVECEXP (pat, 0, i);
1377 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1378 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1381 /* Get the operand values and constraints out of the insn. */
1382 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1383 constraints, operand_mode, NULL);
1385 /* For every operand, see what registers are allowed. */
1386 for (i = 0; i < noperands; i++)
1388 const char *p = constraints[i];
1389 /* For every alternative, we compute the class of registers allowed
1390 for reloading in CLS, and merge its contents into the reg set
1392 int cls = (int) NO_REGS;
1398 if (c == '\0' || c == ',' || c == '#')
1400 /* End of one alternative - mark the regs in the current
1401 class, and reset the class. */
1402 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1408 } while (c != '\0' && c != ',');
1416 case '=': case '+': case '*': case '%': case '?': case '!':
1417 case '0': case '1': case '2': case '3': case '4': case '<':
1418 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1419 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1420 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1421 case TARGET_MEM_CONSTRAINT:
1425 cls = (int) reg_class_subunion[cls]
1426 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1431 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1435 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1436 cls = (int) reg_class_subunion[cls]
1437 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1439 cls = (int) reg_class_subunion[cls]
1440 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1442 p += CONSTRAINT_LEN (c, p);
1445 /* Those of the registers which are clobbered, but allowed by the
1446 constraints, must be usable as reload registers. So clear them
1447 out of the life information. */
1448 AND_HARD_REG_SET (allowed, clobbered);
1449 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1450 if (TEST_HARD_REG_BIT (allowed, i))
1452 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1453 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1460 /* Copy the global variables n_reloads and rld into the corresponding elts
1463 copy_reloads (struct insn_chain *chain)
1465 chain->n_reloads = n_reloads;
1466 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1467 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1468 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1471 /* Walk the chain of insns, and determine for each whether it needs reloads
1472 and/or eliminations. Build the corresponding insns_need_reload list, and
1473 set something_needs_elimination as appropriate. */
1475 calculate_needs_all_insns (int global)
1477 struct insn_chain **pprev_reload = &insns_need_reload;
1478 struct insn_chain *chain, *next = 0;
1480 something_needs_elimination = 0;
1482 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1483 for (chain = reload_insn_chain; chain != 0; chain = next)
1485 rtx insn = chain->insn;
1489 /* Clear out the shortcuts. */
1490 chain->n_reloads = 0;
1491 chain->need_elim = 0;
1492 chain->need_reload = 0;
1493 chain->need_operand_change = 0;
1495 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1496 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1497 what effects this has on the known offsets at labels. */
1499 if (LABEL_P (insn) || JUMP_P (insn)
1500 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1501 set_label_offsets (insn, insn, 0);
1505 rtx old_body = PATTERN (insn);
1506 int old_code = INSN_CODE (insn);
1507 rtx old_notes = REG_NOTES (insn);
1508 int did_elimination = 0;
1509 int operands_changed = 0;
1510 rtx set = single_set (insn);
1512 /* Skip insns that only set an equivalence. */
1513 if (set && REG_P (SET_DEST (set))
1514 && reg_renumber[REGNO (SET_DEST (set))] < 0
1515 && (reg_equiv_constant (REGNO (SET_DEST (set)))
1516 || (reg_equiv_invariant (REGNO (SET_DEST (set)))))
1517 && reg_equiv_init (REGNO (SET_DEST (set))))
1520 /* If needed, eliminate any eliminable registers. */
1521 if (num_eliminable || num_eliminable_invariants)
1522 did_elimination = eliminate_regs_in_insn (insn, 0);
1524 /* Analyze the instruction. */
1525 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1526 global, spill_reg_order);
1528 /* If a no-op set needs more than one reload, this is likely
1529 to be something that needs input address reloads. We
1530 can't get rid of this cleanly later, and it is of no use
1531 anyway, so discard it now.
1532 We only do this when expensive_optimizations is enabled,
1533 since this complements reload inheritance / output
1534 reload deletion, and it can make debugging harder. */
1535 if (flag_expensive_optimizations && n_reloads > 1)
1537 rtx set = single_set (insn);
1540 ((SET_SRC (set) == SET_DEST (set)
1541 && REG_P (SET_SRC (set))
1542 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1543 || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1544 && reg_renumber[REGNO (SET_SRC (set))] < 0
1545 && reg_renumber[REGNO (SET_DEST (set))] < 0
1546 && reg_equiv_memory_loc (REGNO (SET_SRC (set))) != NULL
1547 && reg_equiv_memory_loc (REGNO (SET_DEST (set))) != NULL
1548 && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set))),
1549 reg_equiv_memory_loc (REGNO (SET_DEST (set)))))))
1551 if (ira_conflicts_p)
1552 /* Inform IRA about the insn deletion. */
1553 ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1554 REGNO (SET_SRC (set)));
1556 /* Delete it from the reload chain. */
1558 chain->prev->next = next;
1560 reload_insn_chain = next;
1562 next->prev = chain->prev;
1563 chain->next = unused_insn_chains;
1564 unused_insn_chains = chain;
1569 update_eliminable_offsets ();
1571 /* Remember for later shortcuts which insns had any reloads or
1572 register eliminations. */
1573 chain->need_elim = did_elimination;
1574 chain->need_reload = n_reloads > 0;
1575 chain->need_operand_change = operands_changed;
1577 /* Discard any register replacements done. */
1578 if (did_elimination)
1580 obstack_free (&reload_obstack, reload_insn_firstobj);
1581 PATTERN (insn) = old_body;
1582 INSN_CODE (insn) = old_code;
1583 REG_NOTES (insn) = old_notes;
1584 something_needs_elimination = 1;
1587 something_needs_operands_changed |= operands_changed;
1591 copy_reloads (chain);
1592 *pprev_reload = chain;
1593 pprev_reload = &chain->next_need_reload;
1600 /* This function is called from the register allocator to set up estimates
1601 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1602 an invariant. The structure is similar to calculate_needs_all_insns. */
1605 calculate_elim_costs_all_insns (void)
1607 int *reg_equiv_init_cost;
1611 reg_equiv_init_cost = XCNEWVEC (int, max_regno);
1613 init_eliminable_invariants (get_insns (), false);
1615 set_initial_elim_offsets ();
1616 set_initial_label_offsets ();
1623 FOR_BB_INSNS (bb, insn)
1625 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1626 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1627 what effects this has on the known offsets at labels. */
1629 if (LABEL_P (insn) || JUMP_P (insn)
1630 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1631 set_label_offsets (insn, insn, 0);
1635 rtx set = single_set (insn);
1637 /* Skip insns that only set an equivalence. */
1638 if (set && REG_P (SET_DEST (set))
1639 && reg_renumber[REGNO (SET_DEST (set))] < 0
1640 && (reg_equiv_constant (REGNO (SET_DEST (set)))
1641 || reg_equiv_invariant (REGNO (SET_DEST (set)))))
1643 unsigned regno = REGNO (SET_DEST (set));
1644 rtx init = reg_equiv_init (regno);
1647 rtx t = eliminate_regs_1 (SET_SRC (set), VOIDmode, insn,
1649 int cost = rtx_cost (t, SET,
1650 optimize_bb_for_speed_p (bb));
1651 int freq = REG_FREQ_FROM_BB (bb);
1653 reg_equiv_init_cost[regno] = cost * freq;
1657 /* If needed, eliminate any eliminable registers. */
1658 if (num_eliminable || num_eliminable_invariants)
1659 elimination_costs_in_insn (insn);
1662 update_eliminable_offsets ();
1666 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1668 if (reg_equiv_invariant (i))
1670 if (reg_equiv_init (i))
1672 int cost = reg_equiv_init_cost[i];
1675 "Reg %d has equivalence, initial gains %d\n", i, cost);
1677 ira_adjust_equiv_reg_cost (i, cost);
1683 "Reg %d had equivalence, but can't be eliminated\n",
1685 ira_adjust_equiv_reg_cost (i, 0);
1690 free (reg_equiv_init_cost);
1693 /* Comparison function for qsort to decide which of two reloads
1694 should be handled first. *P1 and *P2 are the reload numbers. */
1697 reload_reg_class_lower (const void *r1p, const void *r2p)
1699 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1702 /* Consider required reloads before optional ones. */
1703 t = rld[r1].optional - rld[r2].optional;
1707 /* Count all solitary classes before non-solitary ones. */
1708 t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1709 - (reg_class_size[(int) rld[r1].rclass] == 1));
1713 /* Aside from solitaires, consider all multi-reg groups first. */
1714 t = rld[r2].nregs - rld[r1].nregs;
1718 /* Consider reloads in order of increasing reg-class number. */
1719 t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1723 /* If reloads are equally urgent, sort by reload number,
1724 so that the results of qsort leave nothing to chance. */
1728 /* The cost of spilling each hard reg. */
1729 static int spill_cost[FIRST_PSEUDO_REGISTER];
1731 /* When spilling multiple hard registers, we use SPILL_COST for the first
1732 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1733 only the first hard reg for a multi-reg pseudo. */
1734 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1736 /* Map of hard regno to pseudo regno currently occupying the hard
1738 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1740 /* Update the spill cost arrays, considering that pseudo REG is live. */
1743 count_pseudo (int reg)
1745 int freq = REG_FREQ (reg);
1746 int r = reg_renumber[reg];
1749 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1750 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1751 /* Ignore spilled pseudo-registers which can be here only if IRA
1753 || (ira_conflicts_p && r < 0))
1756 SET_REGNO_REG_SET (&pseudos_counted, reg);
1758 gcc_assert (r >= 0);
1760 spill_add_cost[r] += freq;
1761 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1764 hard_regno_to_pseudo_regno[r + nregs] = reg;
1765 spill_cost[r + nregs] += freq;
1769 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1770 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1773 order_regs_for_reload (struct insn_chain *chain)
1776 HARD_REG_SET used_by_pseudos;
1777 HARD_REG_SET used_by_pseudos2;
1778 reg_set_iterator rsi;
1780 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1782 memset (spill_cost, 0, sizeof spill_cost);
1783 memset (spill_add_cost, 0, sizeof spill_add_cost);
1784 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1785 hard_regno_to_pseudo_regno[i] = -1;
1787 /* Count number of uses of each hard reg by pseudo regs allocated to it
1788 and then order them by decreasing use. First exclude hard registers
1789 that are live in or across this insn. */
1791 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1792 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1793 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1794 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1796 /* Now find out which pseudos are allocated to it, and update
1798 CLEAR_REG_SET (&pseudos_counted);
1800 EXECUTE_IF_SET_IN_REG_SET
1801 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1805 EXECUTE_IF_SET_IN_REG_SET
1806 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1810 CLEAR_REG_SET (&pseudos_counted);
1813 /* Vector of reload-numbers showing the order in which the reloads should
1815 static short reload_order[MAX_RELOADS];
1817 /* This is used to keep track of the spill regs used in one insn. */
1818 static HARD_REG_SET used_spill_regs_local;
1820 /* We decided to spill hard register SPILLED, which has a size of
1821 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1822 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1823 update SPILL_COST/SPILL_ADD_COST. */
1826 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1828 int freq = REG_FREQ (reg);
1829 int r = reg_renumber[reg];
1830 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1832 /* Ignore spilled pseudo-registers which can be here only if IRA is
1834 if ((ira_conflicts_p && r < 0)
1835 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1836 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1839 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1841 spill_add_cost[r] -= freq;
1844 hard_regno_to_pseudo_regno[r + nregs] = -1;
1845 spill_cost[r + nregs] -= freq;
1849 /* Find reload register to use for reload number ORDER. */
1852 find_reg (struct insn_chain *chain, int order)
1854 int rnum = reload_order[order];
1855 struct reload *rl = rld + rnum;
1856 int best_cost = INT_MAX;
1858 unsigned int i, j, n;
1860 HARD_REG_SET not_usable;
1861 HARD_REG_SET used_by_other_reload;
1862 reg_set_iterator rsi;
1863 static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1864 static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1866 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1867 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1868 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1870 CLEAR_HARD_REG_SET (used_by_other_reload);
1871 for (k = 0; k < order; k++)
1873 int other = reload_order[k];
1875 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1876 for (j = 0; j < rld[other].nregs; j++)
1877 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1880 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1882 #ifdef REG_ALLOC_ORDER
1883 unsigned int regno = reg_alloc_order[i];
1885 unsigned int regno = i;
1888 if (! TEST_HARD_REG_BIT (not_usable, regno)
1889 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1890 && HARD_REGNO_MODE_OK (regno, rl->mode))
1892 int this_cost = spill_cost[regno];
1894 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1896 for (j = 1; j < this_nregs; j++)
1898 this_cost += spill_add_cost[regno + j];
1899 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1900 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1906 if (ira_conflicts_p)
1908 /* Ask IRA to find a better pseudo-register for
1910 for (n = j = 0; j < this_nregs; j++)
1912 int r = hard_regno_to_pseudo_regno[regno + j];
1916 if (n == 0 || regno_pseudo_regs[n - 1] != r)
1917 regno_pseudo_regs[n++] = r;
1919 regno_pseudo_regs[n++] = -1;
1921 || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1922 best_regno_pseudo_regs,
1929 best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1930 if (regno_pseudo_regs[j] < 0)
1937 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1939 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1941 if (this_cost < best_cost
1942 /* Among registers with equal cost, prefer caller-saved ones, or
1943 use REG_ALLOC_ORDER if it is defined. */
1944 || (this_cost == best_cost
1945 #ifdef REG_ALLOC_ORDER
1946 && (inv_reg_alloc_order[regno]
1947 < inv_reg_alloc_order[best_reg])
1949 && call_used_regs[regno]
1950 && ! call_used_regs[best_reg]
1955 best_cost = this_cost;
1963 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1965 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1966 rl->regno = best_reg;
1968 EXECUTE_IF_SET_IN_REG_SET
1969 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1971 count_spilled_pseudo (best_reg, rl->nregs, j);
1974 EXECUTE_IF_SET_IN_REG_SET
1975 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1977 count_spilled_pseudo (best_reg, rl->nregs, j);
1980 for (i = 0; i < rl->nregs; i++)
1982 gcc_assert (spill_cost[best_reg + i] == 0);
1983 gcc_assert (spill_add_cost[best_reg + i] == 0);
1984 gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
1985 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1990 /* Find more reload regs to satisfy the remaining need of an insn, which
1992 Do it by ascending class number, since otherwise a reg
1993 might be spilled for a big class and might fail to count
1994 for a smaller class even though it belongs to that class. */
1997 find_reload_regs (struct insn_chain *chain)
2001 /* In order to be certain of getting the registers we need,
2002 we must sort the reloads into order of increasing register class.
2003 Then our grabbing of reload registers will parallel the process
2004 that provided the reload registers. */
2005 for (i = 0; i < chain->n_reloads; i++)
2007 /* Show whether this reload already has a hard reg. */
2008 if (chain->rld[i].reg_rtx)
2010 int regno = REGNO (chain->rld[i].reg_rtx);
2011 chain->rld[i].regno = regno;
2013 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
2016 chain->rld[i].regno = -1;
2017 reload_order[i] = i;
2020 n_reloads = chain->n_reloads;
2021 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
2023 CLEAR_HARD_REG_SET (used_spill_regs_local);
2026 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
2028 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
2030 /* Compute the order of preference for hard registers to spill. */
2032 order_regs_for_reload (chain);
2034 for (i = 0; i < n_reloads; i++)
2036 int r = reload_order[i];
2038 /* Ignore reloads that got marked inoperative. */
2039 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2040 && ! rld[r].optional
2041 && rld[r].regno == -1)
2042 if (! find_reg (chain, i))
2045 fprintf (dump_file, "reload failure for reload %d\n", r);
2046 spill_failure (chain->insn, rld[r].rclass);
2052 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2053 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2055 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2059 select_reload_regs (void)
2061 struct insn_chain *chain;
2063 /* Try to satisfy the needs for each insn. */
2064 for (chain = insns_need_reload; chain != 0;
2065 chain = chain->next_need_reload)
2066 find_reload_regs (chain);
2069 /* Delete all insns that were inserted by emit_caller_save_insns during
2072 delete_caller_save_insns (void)
2074 struct insn_chain *c = reload_insn_chain;
2078 while (c != 0 && c->is_caller_save_insn)
2080 struct insn_chain *next = c->next;
2083 if (c == reload_insn_chain)
2084 reload_insn_chain = next;
2088 next->prev = c->prev;
2090 c->prev->next = next;
2091 c->next = unused_insn_chains;
2092 unused_insn_chains = c;
2100 /* Handle the failure to find a register to spill.
2101 INSN should be one of the insns which needed this particular spill reg. */
2104 spill_failure (rtx insn, enum reg_class rclass)
2106 if (asm_noperands (PATTERN (insn)) >= 0)
2107 error_for_asm (insn, "can%'t find a register in class %qs while "
2108 "reloading %<asm%>",
2109 reg_class_names[rclass]);
2112 error ("unable to find a register to spill in class %qs",
2113 reg_class_names[rclass]);
2117 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2118 debug_reload_to_stream (dump_file);
2120 fatal_insn ("this is the insn:", insn);
2124 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2125 data that is dead in INSN. */
2128 delete_dead_insn (rtx insn)
2130 rtx prev = prev_active_insn (insn);
2133 /* If the previous insn sets a register that dies in our insn make
2134 a note that we want to run DCE immediately after reload.
2136 We used to delete the previous insn & recurse, but that's wrong for
2137 block local equivalences. Instead of trying to figure out the exact
2138 circumstances where we can delete the potentially dead insns, just
2139 let DCE do the job. */
2140 if (prev && GET_CODE (PATTERN (prev)) == SET
2141 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2142 && reg_mentioned_p (prev_dest, PATTERN (insn))
2143 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2144 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2147 SET_INSN_DELETED (insn);
2150 /* Modify the home of pseudo-reg I.
2151 The new home is present in reg_renumber[I].
2153 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2154 or it may be -1, meaning there is none or it is not relevant.
2155 This is used so that all pseudos spilled from a given hard reg
2156 can share one stack slot. */
2159 alter_reg (int i, int from_reg, bool dont_share_p)
2161 /* When outputting an inline function, this can happen
2162 for a reg that isn't actually used. */
2163 if (regno_reg_rtx[i] == 0)
2166 /* If the reg got changed to a MEM at rtl-generation time,
2168 if (!REG_P (regno_reg_rtx[i]))
2171 /* Modify the reg-rtx to contain the new hard reg
2172 number or else to contain its pseudo reg number. */
2173 SET_REGNO (regno_reg_rtx[i],
2174 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2176 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2177 allocate a stack slot for it. */
2179 if (reg_renumber[i] < 0
2180 && REG_N_REFS (i) > 0
2181 && reg_equiv_constant (i) == 0
2182 && (reg_equiv_invariant (i) == 0
2183 || reg_equiv_init (i) == 0)
2184 && reg_equiv_memory_loc (i) == 0)
2187 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2188 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2189 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2190 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2191 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2194 something_was_spilled = true;
2196 if (ira_conflicts_p)
2198 /* Mark the spill for IRA. */
2199 SET_REGNO_REG_SET (&spilled_pseudos, i);
2201 x = ira_reuse_stack_slot (i, inherent_size, total_size);
2207 /* Each pseudo reg has an inherent size which comes from its own mode,
2208 and a total size which provides room for paradoxical subregs
2209 which refer to the pseudo reg in wider modes.
2211 We can use a slot already allocated if it provides both
2212 enough inherent space and enough total space.
2213 Otherwise, we allocate a new slot, making sure that it has no less
2214 inherent space, and no less total space, then the previous slot. */
2215 else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2219 /* No known place to spill from => no slot to reuse. */
2220 x = assign_stack_local (mode, total_size,
2221 min_align > inherent_align
2222 || total_size > inherent_size ? -1 : 0);
2226 /* Cancel the big-endian correction done in assign_stack_local.
2227 Get the address of the beginning of the slot. This is so we
2228 can do a big-endian correction unconditionally below. */
2229 if (BYTES_BIG_ENDIAN)
2231 adjust = inherent_size - total_size;
2234 = adjust_address_nv (x, mode_for_size (total_size
2240 if (! dont_share_p && ira_conflicts_p)
2241 /* Inform IRA about allocation a new stack slot. */
2242 ira_mark_new_stack_slot (stack_slot, i, total_size);
2245 /* Reuse a stack slot if possible. */
2246 else if (spill_stack_slot[from_reg] != 0
2247 && spill_stack_slot_width[from_reg] >= total_size
2248 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2250 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2251 x = spill_stack_slot[from_reg];
2253 /* Allocate a bigger slot. */
2256 /* Compute maximum size needed, both for inherent size
2257 and for total size. */
2260 if (spill_stack_slot[from_reg])
2262 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2264 mode = GET_MODE (spill_stack_slot[from_reg]);
2265 if (spill_stack_slot_width[from_reg] > total_size)
2266 total_size = spill_stack_slot_width[from_reg];
2267 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2268 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2271 /* Make a slot with that size. */
2272 x = assign_stack_local (mode, total_size,
2273 min_align > inherent_align
2274 || total_size > inherent_size ? -1 : 0);
2277 /* Cancel the big-endian correction done in assign_stack_local.
2278 Get the address of the beginning of the slot. This is so we
2279 can do a big-endian correction unconditionally below. */
2280 if (BYTES_BIG_ENDIAN)
2282 adjust = GET_MODE_SIZE (mode) - total_size;
2285 = adjust_address_nv (x, mode_for_size (total_size
2291 spill_stack_slot[from_reg] = stack_slot;
2292 spill_stack_slot_width[from_reg] = total_size;
2295 /* On a big endian machine, the "address" of the slot
2296 is the address of the low part that fits its inherent mode. */
2297 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2298 adjust += (total_size - inherent_size);
2300 /* If we have any adjustment to make, or if the stack slot is the
2301 wrong mode, make a new stack slot. */
2302 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2304 /* Set all of the memory attributes as appropriate for a spill. */
2305 set_mem_attrs_for_spill (x);
2307 /* Save the stack slot for later. */
2308 reg_equiv_memory_loc (i) = x;
2312 /* Mark the slots in regs_ever_live for the hard regs used by
2313 pseudo-reg number REGNO, accessed in MODE. */
2316 mark_home_live_1 (int regno, enum machine_mode mode)
2320 i = reg_renumber[regno];
2323 lim = end_hard_regno (mode, i);
2325 df_set_regs_ever_live(i++, true);
2328 /* Mark the slots in regs_ever_live for the hard regs
2329 used by pseudo-reg number REGNO. */
2332 mark_home_live (int regno)
2334 if (reg_renumber[regno] >= 0)
2335 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2338 /* This function handles the tracking of elimination offsets around branches.
2340 X is a piece of RTL being scanned.
2342 INSN is the insn that it came from, if any.
2344 INITIAL_P is nonzero if we are to set the offset to be the initial
2345 offset and zero if we are setting the offset of the label to be the
2349 set_label_offsets (rtx x, rtx insn, int initial_p)
2351 enum rtx_code code = GET_CODE (x);
2354 struct elim_table *p;
2359 if (LABEL_REF_NONLOCAL_P (x))
2364 /* ... fall through ... */
2367 /* If we know nothing about this label, set the desired offsets. Note
2368 that this sets the offset at a label to be the offset before a label
2369 if we don't know anything about the label. This is not correct for
2370 the label after a BARRIER, but is the best guess we can make. If
2371 we guessed wrong, we will suppress an elimination that might have
2372 been possible had we been able to guess correctly. */
2374 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2376 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2377 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2378 = (initial_p ? reg_eliminate[i].initial_offset
2379 : reg_eliminate[i].offset);
2380 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2383 /* Otherwise, if this is the definition of a label and it is
2384 preceded by a BARRIER, set our offsets to the known offset of
2388 && (tem = prev_nonnote_insn (insn)) != 0
2390 set_offsets_for_label (insn);
2392 /* If neither of the above cases is true, compare each offset
2393 with those previously recorded and suppress any eliminations
2394 where the offsets disagree. */
2396 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2397 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2398 != (initial_p ? reg_eliminate[i].initial_offset
2399 : reg_eliminate[i].offset))
2400 reg_eliminate[i].can_eliminate = 0;
2405 set_label_offsets (PATTERN (insn), insn, initial_p);
2407 /* ... fall through ... */
2411 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2412 to indirectly and hence must have all eliminations at their
2414 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2415 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2416 set_label_offsets (XEXP (tem, 0), insn, 1);
2422 /* Each of the labels in the parallel or address vector must be
2423 at their initial offsets. We want the first field for PARALLEL
2424 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2426 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2427 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2432 /* We only care about setting PC. If the source is not RETURN,
2433 IF_THEN_ELSE, or a label, disable any eliminations not at
2434 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2435 isn't one of those possibilities. For branches to a label,
2436 call ourselves recursively.
2438 Note that this can disable elimination unnecessarily when we have
2439 a non-local goto since it will look like a non-constant jump to
2440 someplace in the current function. This isn't a significant
2441 problem since such jumps will normally be when all elimination
2442 pairs are back to their initial offsets. */
2444 if (SET_DEST (x) != pc_rtx)
2447 switch (GET_CODE (SET_SRC (x)))
2454 set_label_offsets (SET_SRC (x), insn, initial_p);
2458 tem = XEXP (SET_SRC (x), 1);
2459 if (GET_CODE (tem) == LABEL_REF)
2460 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2461 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2464 tem = XEXP (SET_SRC (x), 2);
2465 if (GET_CODE (tem) == LABEL_REF)
2466 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2467 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2475 /* If we reach here, all eliminations must be at their initial
2476 offset because we are doing a jump to a variable address. */
2477 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2478 if (p->offset != p->initial_offset)
2479 p->can_eliminate = 0;
2487 /* Called through for_each_rtx, this function examines every reg that occurs
2488 in PX and adjusts the costs for its elimination which are gathered by IRA.
2489 DATA is the insn in which PX occurs. We do not recurse into MEM
2493 note_reg_elim_costly (rtx *px, void *data)
2495 rtx insn = (rtx)data;
2502 && REGNO (x) >= FIRST_PSEUDO_REGISTER
2503 && reg_equiv_init (REGNO (x))
2504 && reg_equiv_invariant (REGNO (x)))
2506 rtx t = reg_equiv_invariant (REGNO (x));
2507 rtx new_rtx = eliminate_regs_1 (t, Pmode, insn, true, true);
2508 int cost = rtx_cost (new_rtx, SET, optimize_bb_for_speed_p (elim_bb));
2509 int freq = REG_FREQ_FROM_BB (elim_bb);
2512 ira_adjust_equiv_reg_cost (REGNO (x), -cost * freq);
2517 /* Scan X and replace any eliminable registers (such as fp) with a
2518 replacement (such as sp), plus an offset.
2520 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2521 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2522 MEM, we are allowed to replace a sum of a register and the constant zero
2523 with the register, which we cannot do outside a MEM. In addition, we need
2524 to record the fact that a register is referenced outside a MEM.
2526 If INSN is an insn, it is the insn containing X. If we replace a REG
2527 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2528 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2529 the REG is being modified.
2531 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2532 That's used when we eliminate in expressions stored in notes.
2533 This means, do not set ref_outside_mem even if the reference
2536 If FOR_COSTS is true, we are being called before reload in order to
2537 estimate the costs of keeping registers with an equivalence unallocated.
2539 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2540 replacements done assuming all offsets are at their initial values. If
2541 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2542 encounter, return the actual location so that find_reloads will do
2543 the proper thing. */
2546 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2547 bool may_use_invariant, bool for_costs)
2549 enum rtx_code code = GET_CODE (x);
2550 struct elim_table *ep;
2557 if (! current_function_decl)
2580 /* First handle the case where we encounter a bare register that
2581 is eliminable. Replace it with a PLUS. */
2582 if (regno < FIRST_PSEUDO_REGISTER)
2584 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2586 if (ep->from_rtx == x && ep->can_eliminate)
2587 return plus_constant (ep->to_rtx, ep->previous_offset);
2590 else if (reg_renumber && reg_renumber[regno] < 0
2592 && reg_equiv_invariant (regno))
2594 if (may_use_invariant || (insn && DEBUG_INSN_P (insn)))
2595 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno)),
2596 mem_mode, insn, true, for_costs);
2597 /* There exists at least one use of REGNO that cannot be
2598 eliminated. Prevent the defining insn from being deleted. */
2599 reg_equiv_init (regno) = NULL_RTX;
2601 alter_reg (regno, -1, true);
2605 /* You might think handling MINUS in a manner similar to PLUS is a
2606 good idea. It is not. It has been tried multiple times and every
2607 time the change has had to have been reverted.
2609 Other parts of reload know a PLUS is special (gen_reload for example)
2610 and require special code to handle code a reloaded PLUS operand.
2612 Also consider backends where the flags register is clobbered by a
2613 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2614 lea instruction comes to mind). If we try to reload a MINUS, we
2615 may kill the flags register that was holding a useful value.
2617 So, please before trying to handle MINUS, consider reload as a
2618 whole instead of this little section as well as the backend issues. */
2620 /* If this is the sum of an eliminable register and a constant, rework
2622 if (REG_P (XEXP (x, 0))
2623 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2624 && CONSTANT_P (XEXP (x, 1)))
2626 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2628 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2630 /* The only time we want to replace a PLUS with a REG (this
2631 occurs when the constant operand of the PLUS is the negative
2632 of the offset) is when we are inside a MEM. We won't want
2633 to do so at other times because that would change the
2634 structure of the insn in a way that reload can't handle.
2635 We special-case the commonest situation in
2636 eliminate_regs_in_insn, so just replace a PLUS with a
2637 PLUS here, unless inside a MEM. */
2638 if (mem_mode != 0 && CONST_INT_P (XEXP (x, 1))
2639 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2642 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2643 plus_constant (XEXP (x, 1),
2644 ep->previous_offset));
2647 /* If the register is not eliminable, we are done since the other
2648 operand is a constant. */
2652 /* If this is part of an address, we want to bring any constant to the
2653 outermost PLUS. We will do this by doing register replacement in
2654 our operands and seeing if a constant shows up in one of them.
2656 Note that there is no risk of modifying the structure of the insn,
2657 since we only get called for its operands, thus we are either
2658 modifying the address inside a MEM, or something like an address
2659 operand of a load-address insn. */
2662 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2664 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2667 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2669 /* If one side is a PLUS and the other side is a pseudo that
2670 didn't get a hard register but has a reg_equiv_constant,
2671 we must replace the constant here since it may no longer
2672 be in the position of any operand. */
2673 if (GET_CODE (new0) == PLUS && REG_P (new1)
2674 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2675 && reg_renumber[REGNO (new1)] < 0
2677 && reg_equiv_constant (REGNO (new1)) != 0)
2678 new1 = reg_equiv_constant (REGNO (new1));
2679 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2680 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2681 && reg_renumber[REGNO (new0)] < 0
2682 && reg_equiv_constant (REGNO (new0)) != 0)
2683 new0 = reg_equiv_constant (REGNO (new0));
2685 new_rtx = form_sum (GET_MODE (x), new0, new1);
2687 /* As above, if we are not inside a MEM we do not want to
2688 turn a PLUS into something else. We might try to do so here
2689 for an addition of 0 if we aren't optimizing. */
2690 if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2691 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2699 /* If this is the product of an eliminable register and a
2700 constant, apply the distribute law and move the constant out
2701 so that we have (plus (mult ..) ..). This is needed in order
2702 to keep load-address insns valid. This case is pathological.
2703 We ignore the possibility of overflow here. */
2704 if (REG_P (XEXP (x, 0))
2705 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2706 && CONST_INT_P (XEXP (x, 1)))
2707 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2709 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2712 /* Refs inside notes or in DEBUG_INSNs don't count for
2714 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2715 || GET_CODE (insn) == INSN_LIST
2716 || DEBUG_INSN_P (insn))))
2717 ep->ref_outside_mem = 1;
2720 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2721 ep->previous_offset * INTVAL (XEXP (x, 1)));
2724 /* ... fall through ... */
2728 /* See comments before PLUS about handling MINUS. */
2730 case DIV: case UDIV:
2731 case MOD: case UMOD:
2732 case AND: case IOR: case XOR:
2733 case ROTATERT: case ROTATE:
2734 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2736 case GE: case GT: case GEU: case GTU:
2737 case LE: case LT: case LEU: case LTU:
2739 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2741 rtx new1 = XEXP (x, 1)
2742 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false,
2745 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2746 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2751 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2754 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2756 if (new_rtx != XEXP (x, 0))
2758 /* If this is a REG_DEAD note, it is not valid anymore.
2759 Using the eliminated version could result in creating a
2760 REG_DEAD note for the stack or frame pointer. */
2761 if (REG_NOTE_KIND (x) == REG_DEAD)
2763 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2767 x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2771 /* ... fall through ... */
2774 /* Now do eliminations in the rest of the chain. If this was
2775 an EXPR_LIST, this might result in allocating more memory than is
2776 strictly needed, but it simplifies the code. */
2779 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2781 if (new_rtx != XEXP (x, 1))
2783 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2791 /* We do not support elimination of a register that is modified.
2792 elimination_effects has already make sure that this does not
2798 /* We do not support elimination of a register that is modified.
2799 elimination_effects has already make sure that this does not
2800 happen. The only remaining case we need to consider here is
2801 that the increment value may be an eliminable register. */
2802 if (GET_CODE (XEXP (x, 1)) == PLUS
2803 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2805 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2806 insn, true, for_costs);
2808 if (new_rtx != XEXP (XEXP (x, 1), 1))
2809 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2810 gen_rtx_PLUS (GET_MODE (x),
2811 XEXP (x, 0), new_rtx));
2815 case STRICT_LOW_PART:
2817 case SIGN_EXTEND: case ZERO_EXTEND:
2818 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2819 case FLOAT: case FIX:
2820 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2829 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2831 if (new_rtx != XEXP (x, 0))
2832 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2836 /* Similar to above processing, but preserve SUBREG_BYTE.
2837 Convert (subreg (mem)) to (mem) if not paradoxical.
2838 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2839 pseudo didn't get a hard reg, we must replace this with the
2840 eliminated version of the memory location because push_reload
2841 may do the replacement in certain circumstances. */
2842 if (REG_P (SUBREG_REG (x))
2843 && (GET_MODE_SIZE (GET_MODE (x))
2844 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2846 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
2848 new_rtx = SUBREG_REG (x);
2851 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false, for_costs);
2853 if (new_rtx != SUBREG_REG (x))
2855 int x_size = GET_MODE_SIZE (GET_MODE (x));
2856 int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2859 && ((x_size < new_size
2860 #ifdef WORD_REGISTER_OPERATIONS
2861 /* On these machines, combine can create rtl of the form
2862 (set (subreg:m1 (reg:m2 R) 0) ...)
2863 where m1 < m2, and expects something interesting to
2864 happen to the entire word. Moreover, it will use the
2865 (reg:m2 R) later, expecting all bits to be preserved.
2866 So if the number of words is the same, preserve the
2867 subreg so that push_reload can see it. */
2868 && ! ((x_size - 1) / UNITS_PER_WORD
2869 == (new_size -1 ) / UNITS_PER_WORD)
2872 || x_size == new_size)
2874 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2876 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2882 /* Our only special processing is to pass the mode of the MEM to our
2883 recursive call and copy the flags. While we are here, handle this
2884 case more efficiently. */
2886 new_rtx = eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), insn, true,
2889 && memory_address_p (GET_MODE (x), XEXP (x, 0))
2890 && !memory_address_p (GET_MODE (x), new_rtx))
2891 for_each_rtx (&XEXP (x, 0), note_reg_elim_costly, insn);
2893 return replace_equiv_address_nv (x, new_rtx);
2896 /* Handle insn_list USE that a call to a pure function may generate. */
2897 new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false,
2899 if (new_rtx != XEXP (x, 0))
2900 return gen_rtx_USE (GET_MODE (x), new_rtx);
2905 gcc_assert (insn && DEBUG_INSN_P (insn));
2915 /* Process each of our operands recursively. If any have changed, make a
2917 fmt = GET_RTX_FORMAT (code);
2918 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2922 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false,
2924 if (new_rtx != XEXP (x, i) && ! copied)
2926 x = shallow_copy_rtx (x);
2929 XEXP (x, i) = new_rtx;
2931 else if (*fmt == 'E')
2934 for (j = 0; j < XVECLEN (x, i); j++)
2936 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false,
2938 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2940 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2944 x = shallow_copy_rtx (x);
2947 XVEC (x, i) = new_v;
2950 XVECEXP (x, i, j) = new_rtx;
2959 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2961 return eliminate_regs_1 (x, mem_mode, insn, false, false);
2964 /* Scan rtx X for modifications of elimination target registers. Update
2965 the table of eliminables to reflect the changed state. MEM_MODE is
2966 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2969 elimination_effects (rtx x, enum machine_mode mem_mode)
2971 enum rtx_code code = GET_CODE (x);
2972 struct elim_table *ep;
2997 /* First handle the case where we encounter a bare register that
2998 is eliminable. Replace it with a PLUS. */
2999 if (regno < FIRST_PSEUDO_REGISTER)
3001 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3003 if (ep->from_rtx == x && ep->can_eliminate)
3006 ep->ref_outside_mem = 1;
3011 else if (reg_renumber[regno] < 0
3013 && reg_equiv_constant (regno)
3014 && ! function_invariant_p (reg_equiv_constant (regno)))
3015 elimination_effects (reg_equiv_constant (regno), mem_mode);
3024 /* If we modify the source of an elimination rule, disable it. */
3025 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3026 if (ep->from_rtx == XEXP (x, 0))
3027 ep->can_eliminate = 0;
3029 /* If we modify the target of an elimination rule by adding a constant,
3030 update its offset. If we modify the target in any other way, we'll
3031 have to disable the rule as well. */
3032 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3033 if (ep->to_rtx == XEXP (x, 0))
3035 int size = GET_MODE_SIZE (mem_mode);
3037 /* If more bytes than MEM_MODE are pushed, account for them. */
3038 #ifdef PUSH_ROUNDING
3039 if (ep->to_rtx == stack_pointer_rtx)
3040 size = PUSH_ROUNDING (size);
3042 if (code == PRE_DEC || code == POST_DEC)
3044 else if (code == PRE_INC || code == POST_INC)
3046 else if (code == PRE_MODIFY || code == POST_MODIFY)
3048 if (GET_CODE (XEXP (x, 1)) == PLUS
3049 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
3050 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
3051 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
3053 ep->can_eliminate = 0;
3057 /* These two aren't unary operators. */
3058 if (code == POST_MODIFY || code == PRE_MODIFY)
3061 /* Fall through to generic unary operation case. */
3062 case STRICT_LOW_PART:
3064 case SIGN_EXTEND: case ZERO_EXTEND:
3065 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3066 case FLOAT: case FIX:
3067 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3076 elimination_effects (XEXP (x, 0), mem_mode);
3080 if (REG_P (SUBREG_REG (x))
3081 && (GET_MODE_SIZE (GET_MODE (x))
3082 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3084 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
3087 elimination_effects (SUBREG_REG (x), mem_mode);
3091 /* If using a register that is the source of an eliminate we still
3092 think can be performed, note it cannot be performed since we don't
3093 know how this register is used. */
3094 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3095 if (ep->from_rtx == XEXP (x, 0))
3096 ep->can_eliminate = 0;
3098 elimination_effects (XEXP (x, 0), mem_mode);
3102 /* If clobbering a register that is the replacement register for an
3103 elimination we still think can be performed, note that it cannot
3104 be performed. Otherwise, we need not be concerned about it. */
3105 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3106 if (ep->to_rtx == XEXP (x, 0))
3107 ep->can_eliminate = 0;
3109 elimination_effects (XEXP (x, 0), mem_mode);
3113 /* Check for setting a register that we know about. */
3114 if (REG_P (SET_DEST (x)))
3116 /* See if this is setting the replacement register for an
3119 If DEST is the hard frame pointer, we do nothing because we
3120 assume that all assignments to the frame pointer are for
3121 non-local gotos and are being done at a time when they are valid
3122 and do not disturb anything else. Some machines want to
3123 eliminate a fake argument pointer (or even a fake frame pointer)
3124 with either the real frame or the stack pointer. Assignments to
3125 the hard frame pointer must not prevent this elimination. */
3127 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3129 if (ep->to_rtx == SET_DEST (x)
3130 && SET_DEST (x) != hard_frame_pointer_rtx)
3132 /* If it is being incremented, adjust the offset. Otherwise,
3133 this elimination can't be done. */
3134 rtx src = SET_SRC (x);
3136 if (GET_CODE (src) == PLUS
3137 && XEXP (src, 0) == SET_DEST (x)
3138 && CONST_INT_P (XEXP (src, 1)))
3139 ep->offset -= INTVAL (XEXP (src, 1));
3141 ep->can_eliminate = 0;
3145 elimination_effects (SET_DEST (x), VOIDmode);
3146 elimination_effects (SET_SRC (x), VOIDmode);
3150 /* Our only special processing is to pass the mode of the MEM to our
3152 elimination_effects (XEXP (x, 0), GET_MODE (x));
3159 fmt = GET_RTX_FORMAT (code);
3160 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3163 elimination_effects (XEXP (x, i), mem_mode);
3164 else if (*fmt == 'E')
3165 for (j = 0; j < XVECLEN (x, i); j++)
3166 elimination_effects (XVECEXP (x, i, j), mem_mode);
3170 /* Descend through rtx X and verify that no references to eliminable registers
3171 remain. If any do remain, mark the involved register as not
3175 check_eliminable_occurrences (rtx x)
3184 code = GET_CODE (x);
3186 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3188 struct elim_table *ep;
3190 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3191 if (ep->from_rtx == x)
3192 ep->can_eliminate = 0;
3196 fmt = GET_RTX_FORMAT (code);
3197 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3200 check_eliminable_occurrences (XEXP (x, i));
3201 else if (*fmt == 'E')
3204 for (j = 0; j < XVECLEN (x, i); j++)
3205 check_eliminable_occurrences (XVECEXP (x, i, j));
3210 /* Scan INSN and eliminate all eliminable registers in it.
3212 If REPLACE is nonzero, do the replacement destructively. Also
3213 delete the insn as dead it if it is setting an eliminable register.
3215 If REPLACE is zero, do all our allocations in reload_obstack.
3217 If no eliminations were done and this insn doesn't require any elimination
3218 processing (these are not identical conditions: it might be updating sp,
3219 but not referencing fp; this needs to be seen during reload_as_needed so
3220 that the offset between fp and sp can be taken into consideration), zero
3221 is returned. Otherwise, 1 is returned. */
3224 eliminate_regs_in_insn (rtx insn, int replace)
3226 int icode = recog_memoized (insn);
3227 rtx old_body = PATTERN (insn);
3228 int insn_is_asm = asm_noperands (old_body) >= 0;
3229 rtx old_set = single_set (insn);
3233 rtx substed_operand[MAX_RECOG_OPERANDS];
3234 rtx orig_operand[MAX_RECOG_OPERANDS];
3235 struct elim_table *ep;
3236 rtx plus_src, plus_cst_src;
3238 if (! insn_is_asm && icode < 0)
3240 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3241 || GET_CODE (PATTERN (insn)) == CLOBBER
3242 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3243 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3244 || GET_CODE (PATTERN (insn)) == ASM_INPUT
3245 || DEBUG_INSN_P (insn));
3246 if (DEBUG_INSN_P (insn))
3247 INSN_VAR_LOCATION_LOC (insn)
3248 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn), VOIDmode, insn);
3252 if (old_set != 0 && REG_P (SET_DEST (old_set))
3253 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3255 /* Check for setting an eliminable register. */
3256 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3257 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3259 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
3260 /* If this is setting the frame pointer register to the
3261 hardware frame pointer register and this is an elimination
3262 that will be done (tested above), this insn is really
3263 adjusting the frame pointer downward to compensate for
3264 the adjustment done before a nonlocal goto. */
3265 if (ep->from == FRAME_POINTER_REGNUM
3266 && ep->to == HARD_FRAME_POINTER_REGNUM)
3268 rtx base = SET_SRC (old_set);
3269 rtx base_insn = insn;
3270 HOST_WIDE_INT offset = 0;
3272 while (base != ep->to_rtx)
3274 rtx prev_insn, prev_set;
3276 if (GET_CODE (base) == PLUS
3277 && CONST_INT_P (XEXP (base, 1)))
3279 offset += INTVAL (XEXP (base, 1));
3280 base = XEXP (base, 0);
3282 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3283 && (prev_set = single_set (prev_insn)) != 0
3284 && rtx_equal_p (SET_DEST (prev_set), base))
3286 base = SET_SRC (prev_set);
3287 base_insn = prev_insn;
3293 if (base == ep->to_rtx)
3296 = plus_constant (ep->to_rtx, offset - ep->offset);
3298 new_body = old_body;
3301 new_body = copy_insn (old_body);
3302 if (REG_NOTES (insn))
3303 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3305 PATTERN (insn) = new_body;
3306 old_set = single_set (insn);
3308 /* First see if this insn remains valid when we
3309 make the change. If not, keep the INSN_CODE
3310 the same and let reload fit it up. */
3311 validate_change (insn, &SET_SRC (old_set), src, 1);
3312 validate_change (insn, &SET_DEST (old_set),
3314 if (! apply_change_group ())
3316 SET_SRC (old_set) = src;
3317 SET_DEST (old_set) = ep->to_rtx;
3326 /* In this case this insn isn't serving a useful purpose. We
3327 will delete it in reload_as_needed once we know that this
3328 elimination is, in fact, being done.
3330 If REPLACE isn't set, we can't delete this insn, but needn't
3331 process it since it won't be used unless something changes. */
3334 delete_dead_insn (insn);
3342 /* We allow one special case which happens to work on all machines we
3343 currently support: a single set with the source or a REG_EQUAL
3344 note being a PLUS of an eliminable register and a constant. */
3345 plus_src = plus_cst_src = 0;
3346 if (old_set && REG_P (SET_DEST (old_set)))
3348 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3349 plus_src = SET_SRC (old_set);
3350 /* First see if the source is of the form (plus (...) CST). */
3352 && CONST_INT_P (XEXP (plus_src, 1)))
3353 plus_cst_src = plus_src;
3354 else if (REG_P (SET_SRC (old_set))
3357 /* Otherwise, see if we have a REG_EQUAL note of the form
3358 (plus (...) CST). */
3360 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3362 if ((REG_NOTE_KIND (links) == REG_EQUAL
3363 || REG_NOTE_KIND (links) == REG_EQUIV)
3364 && GET_CODE (XEXP (links, 0)) == PLUS
3365 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3367 plus_cst_src = XEXP (links, 0);
3373 /* Check that the first operand of the PLUS is a hard reg or
3374 the lowpart subreg of one. */
3377 rtx reg = XEXP (plus_cst_src, 0);
3378 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3379 reg = SUBREG_REG (reg);
3381 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3387 rtx reg = XEXP (plus_cst_src, 0);
3388 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3390 if (GET_CODE (reg) == SUBREG)
3391 reg = SUBREG_REG (reg);
3393 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3394 if (ep->from_rtx == reg && ep->can_eliminate)
3396 rtx to_rtx = ep->to_rtx;
3397 offset += ep->offset;
3398 offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3400 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3401 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3403 /* If we have a nonzero offset, and the source is already
3404 a simple REG, the following transformation would
3405 increase the cost of the insn by replacing a simple REG
3406 with (plus (reg sp) CST). So try only when we already
3407 had a PLUS before. */
3408 if (offset == 0 || plus_src)
3410 rtx new_src = plus_constant (to_rtx, offset);
3412 new_body = old_body;
3415 new_body = copy_insn (old_body);
3416 if (REG_NOTES (insn))
3417 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3419 PATTERN (insn) = new_body;
3420 old_set = single_set (insn);
3422 /* First see if this insn remains valid when we make the
3423 change. If not, try to replace the whole pattern with
3424 a simple set (this may help if the original insn was a
3425 PARALLEL that was only recognized as single_set due to
3426 REG_UNUSED notes). If this isn't valid either, keep
3427 the INSN_CODE the same and let reload fix it up. */
3428 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3430 rtx new_pat = gen_rtx_SET (VOIDmode,
3431 SET_DEST (old_set), new_src);
3433 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3434 SET_SRC (old_set) = new_src;
3441 /* This can't have an effect on elimination offsets, so skip right
3447 /* Determine the effects of this insn on elimination offsets. */
3448 elimination_effects (old_body, VOIDmode);
3450 /* Eliminate all eliminable registers occurring in operands that
3451 can be handled by reload. */
3452 extract_insn (insn);
3453 for (i = 0; i < recog_data.n_operands; i++)
3455 orig_operand[i] = recog_data.operand[i];
3456 substed_operand[i] = recog_data.operand[i];
3458 /* For an asm statement, every operand is eliminable. */
3459 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3461 bool is_set_src, in_plus;
3463 /* Check for setting a register that we know about. */
3464 if (recog_data.operand_type[i] != OP_IN
3465 && REG_P (orig_operand[i]))
3467 /* If we are assigning to a register that can be eliminated, it
3468 must be as part of a PARALLEL, since the code above handles
3469 single SETs. We must indicate that we can no longer
3470 eliminate this reg. */
3471 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3473 if (ep->from_rtx == orig_operand[i])
3474 ep->can_eliminate = 0;
3477 /* Companion to the above plus substitution, we can allow
3478 invariants as the source of a plain move. */
3481 && recog_data.operand_loc[i] == &SET_SRC (old_set))
3485 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3486 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3490 = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3491 replace ? insn : NULL_RTX,
3492 is_set_src || in_plus, false);
3493 if (substed_operand[i] != orig_operand[i])
3495 /* Terminate the search in check_eliminable_occurrences at
3497 *recog_data.operand_loc[i] = 0;
3499 /* If an output operand changed from a REG to a MEM and INSN is an
3500 insn, write a CLOBBER insn. */
3501 if (recog_data.operand_type[i] != OP_IN
3502 && REG_P (orig_operand[i])
3503 && MEM_P (substed_operand[i])
3505 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3509 for (i = 0; i < recog_data.n_dups; i++)
3510 *recog_data.dup_loc[i]
3511 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3513 /* If any eliminable remain, they aren't eliminable anymore. */
3514 check_eliminable_occurrences (old_body);
3516 /* Substitute the operands; the new values are in the substed_operand
3518 for (i = 0; i < recog_data.n_operands; i++)
3519 *recog_data.operand_loc[i] = substed_operand[i];
3520 for (i = 0; i < recog_data.n_dups; i++)
3521 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3523 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3524 re-recognize the insn. We do this in case we had a simple addition
3525 but now can do this as a load-address. This saves an insn in this
3527 If re-recognition fails, the old insn code number will still be used,
3528 and some register operands may have changed into PLUS expressions.
3529 These will be handled by find_reloads by loading them into a register
3534 /* If we aren't replacing things permanently and we changed something,
3535 make another copy to ensure that all the RTL is new. Otherwise
3536 things can go wrong if find_reload swaps commutative operands
3537 and one is inside RTL that has been copied while the other is not. */
3538 new_body = old_body;
3541 new_body = copy_insn (old_body);
3542 if (REG_NOTES (insn))
3543 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3545 PATTERN (insn) = new_body;
3547 /* If we had a move insn but now we don't, rerecognize it. This will
3548 cause spurious re-recognition if the old move had a PARALLEL since
3549 the new one still will, but we can't call single_set without
3550 having put NEW_BODY into the insn and the re-recognition won't
3551 hurt in this rare case. */
3552 /* ??? Why this huge if statement - why don't we just rerecognize the
3556 && ((REG_P (SET_SRC (old_set))
3557 && (GET_CODE (new_body) != SET
3558 || !REG_P (SET_SRC (new_body))))
3559 /* If this was a load from or store to memory, compare
3560 the MEM in recog_data.operand to the one in the insn.
3561 If they are not equal, then rerecognize the insn. */
3563 && ((MEM_P (SET_SRC (old_set))
3564 && SET_SRC (old_set) != recog_data.operand[1])
3565 || (MEM_P (SET_DEST (old_set))
3566 && SET_DEST (old_set) != recog_data.operand[0])))
3567 /* If this was an add insn before, rerecognize. */
3568 || GET_CODE (SET_SRC (old_set)) == PLUS))
3570 int new_icode = recog (PATTERN (insn), insn, 0);
3572 INSN_CODE (insn) = new_icode;
3576 /* Restore the old body. If there were any changes to it, we made a copy
3577 of it while the changes were still in place, so we'll correctly return
3578 a modified insn below. */
3581 /* Restore the old body. */
3582 for (i = 0; i < recog_data.n_operands; i++)
3583 /* Restoring a top-level match_parallel would clobber the new_body
3584 we installed in the insn. */
3585 if (recog_data.operand_loc[i] != &PATTERN (insn))
3586 *recog_data.operand_loc[i] = orig_operand[i];
3587 for (i = 0; i < recog_data.n_dups; i++)
3588 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3591 /* Update all elimination pairs to reflect the status after the current
3592 insn. The changes we make were determined by the earlier call to
3593 elimination_effects.
3595 We also detect cases where register elimination cannot be done,
3596 namely, if a register would be both changed and referenced outside a MEM
3597 in the resulting insn since such an insn is often undefined and, even if
3598 not, we cannot know what meaning will be given to it. Note that it is
3599 valid to have a register used in an address in an insn that changes it
3600 (presumably with a pre- or post-increment or decrement).
3602 If anything changes, return nonzero. */
3604 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3606 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3607 ep->can_eliminate = 0;
3609 ep->ref_outside_mem = 0;
3611 if (ep->previous_offset != ep->offset)
3616 /* If we changed something, perform elimination in REG_NOTES. This is
3617 needed even when REPLACE is zero because a REG_DEAD note might refer
3618 to a register that we eliminate and could cause a different number
3619 of spill registers to be needed in the final reload pass than in
3621 if (val && REG_NOTES (insn) != 0)
3623 = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true,
3629 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3630 register allocator. INSN is the instruction we need to examine, we perform
3631 eliminations in its operands and record cases where eliminating a reg with
3632 an invariant equivalence would add extra cost. */
3635 elimination_costs_in_insn (rtx insn)
3637 int icode = recog_memoized (insn);
3638 rtx old_body = PATTERN (insn);
3639 int insn_is_asm = asm_noperands (old_body) >= 0;
3640 rtx old_set = single_set (insn);
3642 rtx orig_operand[MAX_RECOG_OPERANDS];
3643 rtx orig_dup[MAX_RECOG_OPERANDS];
3644 struct elim_table *ep;
3645 rtx plus_src, plus_cst_src;
3648 if (! insn_is_asm && icode < 0)
3650 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3651 || GET_CODE (PATTERN (insn)) == CLOBBER
3652 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3653 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3654 || GET_CODE (PATTERN (insn)) == ASM_INPUT
3655 || DEBUG_INSN_P (insn));
3659 if (old_set != 0 && REG_P (SET_DEST (old_set))
3660 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3662 /* Check for setting an eliminable register. */
3663 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3664 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3668 /* We allow one special case which happens to work on all machines we
3669 currently support: a single set with the source or a REG_EQUAL
3670 note being a PLUS of an eliminable register and a constant. */
3671 plus_src = plus_cst_src = 0;
3673 if (old_set && REG_P (SET_DEST (old_set)))
3676 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3677 plus_src = SET_SRC (old_set);
3678 /* First see if the source is of the form (plus (...) CST). */
3680 && CONST_INT_P (XEXP (plus_src, 1)))
3681 plus_cst_src = plus_src;
3682 else if (REG_P (SET_SRC (old_set))
3685 /* Otherwise, see if we have a REG_EQUAL note of the form
3686 (plus (...) CST). */
3688 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3690 if ((REG_NOTE_KIND (links) == REG_EQUAL
3691 || REG_NOTE_KIND (links) == REG_EQUIV)
3692 && GET_CODE (XEXP (links, 0)) == PLUS
3693 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3695 plus_cst_src = XEXP (links, 0);
3702 /* Determine the effects of this insn on elimination offsets. */
3703 elimination_effects (old_body, VOIDmode);
3705 /* Eliminate all eliminable registers occurring in operands that
3706 can be handled by reload. */
3707 extract_insn (insn);
3708 for (i = 0; i < recog_data.n_dups; i++)
3709 orig_dup[i] = *recog_data.dup_loc[i];
3711 for (i = 0; i < recog_data.n_operands; i++)
3713 orig_operand[i] = recog_data.operand[i];
3715 /* For an asm statement, every operand is eliminable. */
3716 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3718 bool is_set_src, in_plus;
3720 /* Check for setting a register that we know about. */
3721 if (recog_data.operand_type[i] != OP_IN
3722 && REG_P (orig_operand[i]))
3724 /* If we are assigning to a register that can be eliminated, it
3725 must be as part of a PARALLEL, since the code above handles
3726 single SETs. We must indicate that we can no longer
3727 eliminate this reg. */
3728 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3730 if (ep->from_rtx == orig_operand[i])
3731 ep->can_eliminate = 0;
3734 /* Companion to the above plus substitution, we can allow
3735 invariants as the source of a plain move. */
3737 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3739 if (is_set_src && !sets_reg_p)
3740 note_reg_elim_costly (&SET_SRC (old_set), insn);
3742 if (plus_src && sets_reg_p
3743 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3744 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3747 eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3749 is_set_src || in_plus, true);
3750 /* Terminate the search in check_eliminable_occurrences at
3752 *recog_data.operand_loc[i] = 0;
3756 for (i = 0; i < recog_data.n_dups; i++)
3757 *recog_data.dup_loc[i]
3758 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3760 /* If any eliminable remain, they aren't eliminable anymore. */
3761 check_eliminable_occurrences (old_body);
3763 /* Restore the old body. */
3764 for (i = 0; i < recog_data.n_operands; i++)
3765 *recog_data.operand_loc[i] = orig_operand[i];
3766 for (i = 0; i < recog_data.n_dups; i++)
3767 *recog_data.dup_loc[i] = orig_dup[i];
3769 /* Update all elimination pairs to reflect the status after the current
3770 insn. The changes we make were determined by the earlier call to
3771 elimination_effects. */
3773 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3775 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3776 ep->can_eliminate = 0;
3778 ep->ref_outside_mem = 0;
3784 /* Loop through all elimination pairs.
3785 Recalculate the number not at initial offset.
3787 Compute the maximum offset (minimum offset if the stack does not
3788 grow downward) for each elimination pair. */
3791 update_eliminable_offsets (void)
3793 struct elim_table *ep;
3795 num_not_at_initial_offset = 0;
3796 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3798 ep->previous_offset = ep->offset;
3799 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3800 num_not_at_initial_offset++;
3804 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3805 replacement we currently believe is valid, mark it as not eliminable if X
3806 modifies DEST in any way other than by adding a constant integer to it.
3808 If DEST is the frame pointer, we do nothing because we assume that
3809 all assignments to the hard frame pointer are nonlocal gotos and are being
3810 done at a time when they are valid and do not disturb anything else.
3811 Some machines want to eliminate a fake argument pointer with either the
3812 frame or stack pointer. Assignments to the hard frame pointer must not
3813 prevent this elimination.
3815 Called via note_stores from reload before starting its passes to scan
3816 the insns of the function. */
3819 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3823 /* A SUBREG of a hard register here is just changing its mode. We should
3824 not see a SUBREG of an eliminable hard register, but check just in
3826 if (GET_CODE (dest) == SUBREG)
3827 dest = SUBREG_REG (dest);
3829 if (dest == hard_frame_pointer_rtx)
3832 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3833 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3834 && (GET_CODE (x) != SET
3835 || GET_CODE (SET_SRC (x)) != PLUS
3836 || XEXP (SET_SRC (x), 0) != dest
3837 || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
3839 reg_eliminate[i].can_eliminate_previous
3840 = reg_eliminate[i].can_eliminate = 0;
3845 /* Verify that the initial elimination offsets did not change since the
3846 last call to set_initial_elim_offsets. This is used to catch cases
3847 where something illegal happened during reload_as_needed that could
3848 cause incorrect code to be generated if we did not check for it. */
3851 verify_initial_elim_offsets (void)
3855 if (!num_eliminable)
3858 #ifdef ELIMINABLE_REGS
3860 struct elim_table *ep;
3862 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3864 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3865 if (t != ep->initial_offset)
3870 INITIAL_FRAME_POINTER_OFFSET (t);
3871 if (t != reg_eliminate[0].initial_offset)
3878 /* Reset all offsets on eliminable registers to their initial values. */
3881 set_initial_elim_offsets (void)
3883 struct elim_table *ep = reg_eliminate;
3885 #ifdef ELIMINABLE_REGS
3886 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3888 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3889 ep->previous_offset = ep->offset = ep->initial_offset;
3892 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3893 ep->previous_offset = ep->offset = ep->initial_offset;
3896 num_not_at_initial_offset = 0;
3899 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3902 set_initial_eh_label_offset (rtx label)
3904 set_label_offsets (label, NULL_RTX, 1);
3907 /* Initialize the known label offsets.
3908 Set a known offset for each forced label to be at the initial offset
3909 of each elimination. We do this because we assume that all
3910 computed jumps occur from a location where each elimination is
3911 at its initial offset.
3912 For all other labels, show that we don't know the offsets. */
3915 set_initial_label_offsets (void)
3918 memset (offsets_known_at, 0, num_labels);
3920 for (x = forced_labels; x; x = XEXP (x, 1))
3922 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3924 for_each_eh_label (set_initial_eh_label_offset);
3927 /* Set all elimination offsets to the known values for the code label given
3931 set_offsets_for_label (rtx insn)
3934 int label_nr = CODE_LABEL_NUMBER (insn);
3935 struct elim_table *ep;
3937 num_not_at_initial_offset = 0;
3938 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3940 ep->offset = ep->previous_offset
3941 = offsets_at[label_nr - first_label_num][i];
3942 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3943 num_not_at_initial_offset++;
3947 /* See if anything that happened changes which eliminations are valid.
3948 For example, on the SPARC, whether or not the frame pointer can
3949 be eliminated can depend on what registers have been used. We need
3950 not check some conditions again (such as flag_omit_frame_pointer)
3951 since they can't have changed. */
3954 update_eliminables (HARD_REG_SET *pset)
3956 int previous_frame_pointer_needed = frame_pointer_needed;
3957 struct elim_table *ep;
3959 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3960 if ((ep->from == HARD_FRAME_POINTER_REGNUM
3961 && targetm.frame_pointer_required ())
3962 #ifdef ELIMINABLE_REGS
3963 || ! targetm.can_eliminate (ep->from, ep->to)
3966 ep->can_eliminate = 0;
3968 /* Look for the case where we have discovered that we can't replace
3969 register A with register B and that means that we will now be
3970 trying to replace register A with register C. This means we can
3971 no longer replace register C with register B and we need to disable
3972 such an elimination, if it exists. This occurs often with A == ap,
3973 B == sp, and C == fp. */
3975 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3977 struct elim_table *op;
3980 if (! ep->can_eliminate && ep->can_eliminate_previous)
3982 /* Find the current elimination for ep->from, if there is a
3984 for (op = reg_eliminate;
3985 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3986 if (op->from == ep->from && op->can_eliminate)
3992 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3994 for (op = reg_eliminate;
3995 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3996 if (op->from == new_to && op->to == ep->to)
3997 op->can_eliminate = 0;
4001 /* See if any registers that we thought we could eliminate the previous
4002 time are no longer eliminable. If so, something has changed and we
4003 must spill the register. Also, recompute the number of eliminable
4004 registers and see if the frame pointer is needed; it is if there is
4005 no elimination of the frame pointer that we can perform. */
4007 frame_pointer_needed = 1;
4008 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4010 if (ep->can_eliminate
4011 && ep->from == FRAME_POINTER_REGNUM
4012 && ep->to != HARD_FRAME_POINTER_REGNUM
4013 && (! SUPPORTS_STACK_ALIGNMENT
4014 || ! crtl->stack_realign_needed))
4015 frame_pointer_needed = 0;
4017 if (! ep->can_eliminate && ep->can_eliminate_previous)
4019 ep->can_eliminate_previous = 0;
4020 SET_HARD_REG_BIT (*pset, ep->from);
4025 /* If we didn't need a frame pointer last time, but we do now, spill
4026 the hard frame pointer. */
4027 if (frame_pointer_needed && ! previous_frame_pointer_needed)
4028 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
4031 /* Return true if X is used as the target register of an elimination. */
4034 elimination_target_reg_p (rtx x)
4036 struct elim_table *ep;
4038 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4039 if (ep->to_rtx == x && ep->can_eliminate)
4045 /* Initialize the table of registers to eliminate.
4046 Pre-condition: global flag frame_pointer_needed has been set before
4047 calling this function. */
4050 init_elim_table (void)
4052 struct elim_table *ep;
4053 #ifdef ELIMINABLE_REGS
4054 const struct elim_table_1 *ep1;
4058 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
4062 #ifdef ELIMINABLE_REGS
4063 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
4064 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
4066 ep->from = ep1->from;
4068 ep->can_eliminate = ep->can_eliminate_previous
4069 = (targetm.can_eliminate (ep->from, ep->to)
4070 && ! (ep->to == STACK_POINTER_REGNUM
4071 && frame_pointer_needed
4072 && (! SUPPORTS_STACK_ALIGNMENT
4073 || ! stack_realign_fp)));
4076 reg_eliminate[0].from = reg_eliminate_1[0].from;
4077 reg_eliminate[0].to = reg_eliminate_1[0].to;
4078 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
4079 = ! frame_pointer_needed;
4082 /* Count the number of eliminable registers and build the FROM and TO
4083 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
4084 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4085 We depend on this. */
4086 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4088 num_eliminable += ep->can_eliminate;
4089 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
4090 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
4094 /* Find all the pseudo registers that didn't get hard regs
4095 but do have known equivalent constants or memory slots.
4096 These include parameters (known equivalent to parameter slots)
4097 and cse'd or loop-moved constant memory addresses.
4099 Record constant equivalents in reg_equiv_constant
4100 so they will be substituted by find_reloads.
4101 Record memory equivalents in reg_mem_equiv so they can
4102 be substituted eventually by altering the REG-rtx's. */
4105 init_eliminable_invariants (rtx first, bool do_subregs)
4112 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
4114 reg_max_ref_width = NULL;
4116 num_eliminable_invariants = 0;
4118 first_label_num = get_first_label_num ();
4119 num_labels = max_label_num () - first_label_num;
4121 /* Allocate the tables used to store offset information at labels. */
4122 offsets_known_at = XNEWVEC (char, num_labels);
4123 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
4125 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4126 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4127 find largest such for each pseudo. FIRST is the head of the insn
4130 for (insn = first; insn; insn = NEXT_INSN (insn))
4132 rtx set = single_set (insn);
4134 /* We may introduce USEs that we want to remove at the end, so
4135 we'll mark them with QImode. Make sure there are no
4136 previously-marked insns left by say regmove. */
4137 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
4138 && GET_MODE (insn) != VOIDmode)
4139 PUT_MODE (insn, VOIDmode);
4141 if (do_subregs && NONDEBUG_INSN_P (insn))
4142 scan_paradoxical_subregs (PATTERN (insn));
4144 if (set != 0 && REG_P (SET_DEST (set)))
4146 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
4152 i = REGNO (SET_DEST (set));
4155 if (i <= LAST_VIRTUAL_REGISTER)
4158 /* If flag_pic and we have constant, verify it's legitimate. */
4160 || !flag_pic || LEGITIMATE_PIC_OPERAND_P (x))
4162 /* It can happen that a REG_EQUIV note contains a MEM
4163 that is not a legitimate memory operand. As later
4164 stages of reload assume that all addresses found
4165 in the reg_equiv_* arrays were originally legitimate,
4166 we ignore such REG_EQUIV notes. */
4167 if (memory_operand (x, VOIDmode))
4169 /* Always unshare the equivalence, so we can
4170 substitute into this insn without touching the
4172 reg_equiv_memory_loc (i) = copy_rtx (x);
4174 else if (function_invariant_p (x))
4176 enum machine_mode mode;
4178 mode = GET_MODE (SET_DEST (set));
4179 if (GET_CODE (x) == PLUS)
4181 /* This is PLUS of frame pointer and a constant,
4182 and might be shared. Unshare it. */
4183 reg_equiv_invariant (i) = copy_rtx (x);
4184 num_eliminable_invariants++;
4186 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4188 reg_equiv_invariant (i) = x;
4189 num_eliminable_invariants++;
4191 else if (targetm.legitimate_constant_p (mode, x))
4192 reg_equiv_constant (i) = x;
4195 reg_equiv_memory_loc (i) = force_const_mem (mode, x);
4196 if (! reg_equiv_memory_loc (i))
4197 reg_equiv_init (i) = NULL_RTX;
4202 reg_equiv_init (i) = NULL_RTX;
4207 reg_equiv_init (i) = NULL_RTX;
4212 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4213 if (reg_equiv_init (i))
4215 fprintf (dump_file, "init_insns for %u: ", i);
4216 print_inline_rtx (dump_file, reg_equiv_init (i), 20);
4217 fprintf (dump_file, "\n");
4221 /* Indicate that we no longer have known memory locations or constants.
4222 Free all data involved in tracking these. */
4225 free_reg_equiv (void)
4230 free (offsets_known_at);
4233 offsets_known_at = 0;
4235 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4236 if (reg_equiv_alt_mem_list (i))
4237 free_EXPR_LIST_list (®_equiv_alt_mem_list (i));
4238 VEC_free (reg_equivs_t, gc, reg_equivs);
4243 /* Kick all pseudos out of hard register REGNO.
4245 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4246 because we found we can't eliminate some register. In the case, no pseudos
4247 are allowed to be in the register, even if they are only in a block that
4248 doesn't require spill registers, unlike the case when we are spilling this
4249 hard reg to produce another spill register.
4251 Return nonzero if any pseudos needed to be kicked out. */
4254 spill_hard_reg (unsigned int regno, int cant_eliminate)
4260 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
4261 df_set_regs_ever_live (regno, true);
4264 /* Spill every pseudo reg that was allocated to this reg
4265 or to something that overlaps this reg. */
4267 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4268 if (reg_renumber[i] >= 0
4269 && (unsigned int) reg_renumber[i] <= regno
4270 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
4271 SET_REGNO_REG_SET (&spilled_pseudos, i);
4274 /* After find_reload_regs has been run for all insn that need reloads,
4275 and/or spill_hard_regs was called, this function is used to actually
4276 spill pseudo registers and try to reallocate them. It also sets up the
4277 spill_regs array for use by choose_reload_regs. */
4280 finish_spills (int global)
4282 struct insn_chain *chain;
4283 int something_changed = 0;
4285 reg_set_iterator rsi;
4287 /* Build the spill_regs array for the function. */
4288 /* If there are some registers still to eliminate and one of the spill regs
4289 wasn't ever used before, additional stack space may have to be
4290 allocated to store this register. Thus, we may have changed the offset
4291 between the stack and frame pointers, so mark that something has changed.
4293 One might think that we need only set VAL to 1 if this is a call-used
4294 register. However, the set of registers that must be saved by the
4295 prologue is not identical to the call-used set. For example, the
4296 register used by the call insn for the return PC is a call-used register,
4297 but must be saved by the prologue. */
4300 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4301 if (TEST_HARD_REG_BIT (used_spill_regs, i))
4303 spill_reg_order[i] = n_spills;
4304 spill_regs[n_spills++] = i;
4305 if (num_eliminable && ! df_regs_ever_live_p (i))
4306 something_changed = 1;
4307 df_set_regs_ever_live (i, true);
4310 spill_reg_order[i] = -1;
4312 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
4313 if (! ira_conflicts_p || reg_renumber[i] >= 0)
4315 /* Record the current hard register the pseudo is allocated to
4316 in pseudo_previous_regs so we avoid reallocating it to the
4317 same hard reg in a later pass. */
4318 gcc_assert (reg_renumber[i] >= 0);
4320 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
4321 /* Mark it as no longer having a hard register home. */
4322 reg_renumber[i] = -1;
4323 if (ira_conflicts_p)
4324 /* Inform IRA about the change. */
4325 ira_mark_allocation_change (i);
4326 /* We will need to scan everything again. */
4327 something_changed = 1;
4330 /* Retry global register allocation if possible. */
4331 if (global && ira_conflicts_p)
4335 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
4336 /* For every insn that needs reloads, set the registers used as spill
4337 regs in pseudo_forbidden_regs for every pseudo live across the
4339 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
4341 EXECUTE_IF_SET_IN_REG_SET
4342 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
4344 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4345 chain->used_spill_regs);
4347 EXECUTE_IF_SET_IN_REG_SET
4348 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
4350 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4351 chain->used_spill_regs);
4355 /* Retry allocating the pseudos spilled in IRA and the
4356 reload. For each reg, merge the various reg sets that
4357 indicate which hard regs can't be used, and call
4358 ira_reassign_pseudos. */
4359 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4360 if (reg_old_renumber[i] != reg_renumber[i])
4362 if (reg_renumber[i] < 0)
4363 temp_pseudo_reg_arr[n++] = i;
4365 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4367 if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4368 bad_spill_regs_global,
4369 pseudo_forbidden_regs, pseudo_previous_regs,
4371 something_changed = 1;
4373 /* Fix up the register information in the insn chain.
4374 This involves deleting those of the spilled pseudos which did not get
4375 a new hard register home from the live_{before,after} sets. */
4376 for (chain = reload_insn_chain; chain; chain = chain->next)
4378 HARD_REG_SET used_by_pseudos;
4379 HARD_REG_SET used_by_pseudos2;
4381 if (! ira_conflicts_p)
4383 /* Don't do it for IRA because IRA and the reload still can
4384 assign hard registers to the spilled pseudos on next
4385 reload iterations. */
4386 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4387 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4389 /* Mark any unallocated hard regs as available for spills. That
4390 makes inheritance work somewhat better. */
4391 if (chain->need_reload)
4393 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4394 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4395 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4397 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4398 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4399 /* Value of chain->used_spill_regs from previous iteration
4400 may be not included in the value calculated here because
4401 of possible removing caller-saves insns (see function
4402 delete_caller_save_insns. */
4403 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4404 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4408 CLEAR_REG_SET (&changed_allocation_pseudos);
4409 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4410 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4412 int regno = reg_renumber[i];
4413 if (reg_old_renumber[i] == regno)
4416 SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4418 alter_reg (i, reg_old_renumber[i], false);
4419 reg_old_renumber[i] = regno;
4423 fprintf (dump_file, " Register %d now on stack.\n\n", i);
4425 fprintf (dump_file, " Register %d now in %d.\n\n",
4426 i, reg_renumber[i]);
4430 return something_changed;
4433 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4436 scan_paradoxical_subregs (rtx x)
4440 enum rtx_code code = GET_CODE (x);
4451 case CONST_VECTOR: /* shouldn't happen, but just in case. */
4459 if (REG_P (SUBREG_REG (x))
4460 && (GET_MODE_SIZE (GET_MODE (x))
4461 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
4463 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4464 = GET_MODE_SIZE (GET_MODE (x));
4465 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
4473 fmt = GET_RTX_FORMAT (code);
4474 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4477 scan_paradoxical_subregs (XEXP (x, i));
4478 else if (fmt[i] == 'E')
4481 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4482 scan_paradoxical_subregs (XVECEXP (x, i, j));
4487 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4488 If *OP_PTR is a paradoxical subreg, try to remove that subreg
4489 and apply the corresponding narrowing subreg to *OTHER_PTR.
4490 Return true if the operands were changed, false otherwise. */
4493 strip_paradoxical_subreg (rtx *op_ptr, rtx *other_ptr)
4495 rtx op, inner, other, tem;
4498 if (GET_CODE (op) != SUBREG)
4501 inner = SUBREG_REG (op);
4502 if (GET_MODE_SIZE (GET_MODE (op)) <= GET_MODE_SIZE (GET_MODE (inner)))
4506 tem = gen_lowpart_common (GET_MODE (inner), other);
4510 /* If the lowpart operation turned a hard register into a subreg,
4511 rather than simplifying it to another hard register, then the
4512 mode change cannot be properly represented. For example, OTHER
4513 might be valid in its current mode, but not in the new one. */
4514 if (GET_CODE (tem) == SUBREG
4516 && HARD_REGISTER_P (other))
4524 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4525 examine all of the reload insns between PREV and NEXT exclusive, and
4526 annotate all that may trap. */
4529 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
4531 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4534 if (!insn_could_throw_p (insn))
4535 remove_note (insn, note);
4536 copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next);
4539 /* Reload pseudo-registers into hard regs around each insn as needed.
4540 Additional register load insns are output before the insn that needs it
4541 and perhaps store insns after insns that modify the reloaded pseudo reg.
4543 reg_last_reload_reg and reg_reloaded_contents keep track of
4544 which registers are already available in reload registers.
4545 We update these for the reloads that we perform,
4546 as the insns are scanned. */
4549 reload_as_needed (int live_known)
4551 struct insn_chain *chain;
4552 #if defined (AUTO_INC_DEC)
4557 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4558 memset (spill_reg_store, 0, sizeof spill_reg_store);
4559 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4560 INIT_REG_SET (®_has_output_reload);
4561 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4562 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4564 set_initial_elim_offsets ();
4566 for (chain = reload_insn_chain; chain; chain = chain->next)
4569 rtx insn = chain->insn;
4570 rtx old_next = NEXT_INSN (insn);
4572 rtx old_prev = PREV_INSN (insn);
4575 /* If we pass a label, copy the offsets from the label information
4576 into the current offsets of each elimination. */
4578 set_offsets_for_label (insn);
4580 else if (INSN_P (insn))
4582 regset_head regs_to_forget;
4583 INIT_REG_SET (®s_to_forget);
4584 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4586 /* If this is a USE and CLOBBER of a MEM, ensure that any
4587 references to eliminable registers have been removed. */
4589 if ((GET_CODE (PATTERN (insn)) == USE
4590 || GET_CODE (PATTERN (insn)) == CLOBBER)
4591 && MEM_P (XEXP (PATTERN (insn), 0)))
4592 XEXP (XEXP (PATTERN (insn), 0), 0)
4593 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4594 GET_MODE (XEXP (PATTERN (insn), 0)),
4597 /* If we need to do register elimination processing, do so.
4598 This might delete the insn, in which case we are done. */
4599 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4601 eliminate_regs_in_insn (insn, 1);
4604 update_eliminable_offsets ();
4605 CLEAR_REG_SET (®s_to_forget);
4610 /* If need_elim is nonzero but need_reload is zero, one might think
4611 that we could simply set n_reloads to 0. However, find_reloads
4612 could have done some manipulation of the insn (such as swapping
4613 commutative operands), and these manipulations are lost during
4614 the first pass for every insn that needs register elimination.
4615 So the actions of find_reloads must be redone here. */
4617 if (! chain->need_elim && ! chain->need_reload
4618 && ! chain->need_operand_change)
4620 /* First find the pseudo regs that must be reloaded for this insn.
4621 This info is returned in the tables reload_... (see reload.h).
4622 Also modify the body of INSN by substituting RELOAD
4623 rtx's for those pseudo regs. */
4626 CLEAR_REG_SET (®_has_output_reload);
4627 CLEAR_HARD_REG_SET (reg_is_output_reload);
4629 find_reloads (insn, 1, spill_indirect_levels, live_known,
4635 rtx next = NEXT_INSN (insn);
4638 prev = PREV_INSN (insn);
4640 /* Now compute which reload regs to reload them into. Perhaps
4641 reusing reload regs from previous insns, or else output
4642 load insns to reload them. Maybe output store insns too.
4643 Record the choices of reload reg in reload_reg_rtx. */
4644 choose_reload_regs (chain);
4646 /* Generate the insns to reload operands into or out of
4647 their reload regs. */
4648 emit_reload_insns (chain);
4650 /* Substitute the chosen reload regs from reload_reg_rtx
4651 into the insn's body (or perhaps into the bodies of other
4652 load and store insn that we just made for reloading
4653 and that we moved the structure into). */
4654 subst_reloads (insn);
4656 /* Adjust the exception region notes for loads and stores. */
4657 if (cfun->can_throw_non_call_exceptions && !CALL_P (insn))
4658 fixup_eh_region_note (insn, prev, next);
4660 /* If this was an ASM, make sure that all the reload insns
4661 we have generated are valid. If not, give an error
4663 if (asm_noperands (PATTERN (insn)) >= 0)
4664 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4665 if (p != insn && INSN_P (p)
4666 && GET_CODE (PATTERN (p)) != USE
4667 && (recog_memoized (p) < 0
4668 || (extract_insn (p), ! constrain_operands (1))))
4670 error_for_asm (insn,
4671 "%<asm%> operand requires "
4672 "impossible reload");
4677 if (num_eliminable && chain->need_elim)
4678 update_eliminable_offsets ();
4680 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4681 is no longer validly lying around to save a future reload.
4682 Note that this does not detect pseudos that were reloaded
4683 for this insn in order to be stored in
4684 (obeying register constraints). That is correct; such reload
4685 registers ARE still valid. */
4686 forget_marked_reloads (®s_to_forget);
4687 CLEAR_REG_SET (®s_to_forget);
4689 /* There may have been CLOBBER insns placed after INSN. So scan
4690 between INSN and NEXT and use them to forget old reloads. */
4691 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4692 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4693 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4696 /* Likewise for regs altered by auto-increment in this insn.
4697 REG_INC notes have been changed by reloading:
4698 find_reloads_address_1 records substitutions for them,
4699 which have been performed by subst_reloads above. */
4700 for (i = n_reloads - 1; i >= 0; i--)
4702 rtx in_reg = rld[i].in_reg;
4705 enum rtx_code code = GET_CODE (in_reg);
4706 /* PRE_INC / PRE_DEC will have the reload register ending up
4707 with the same value as the stack slot, but that doesn't
4708 hold true for POST_INC / POST_DEC. Either we have to
4709 convert the memory access to a true POST_INC / POST_DEC,
4710 or we can't use the reload register for inheritance. */
4711 if ((code == POST_INC || code == POST_DEC)
4712 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4713 REGNO (rld[i].reg_rtx))
4714 /* Make sure it is the inc/dec pseudo, and not
4715 some other (e.g. output operand) pseudo. */
4716 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4717 == REGNO (XEXP (in_reg, 0))))
4720 rtx reload_reg = rld[i].reg_rtx;
4721 enum machine_mode mode = GET_MODE (reload_reg);
4725 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4727 /* We really want to ignore REG_INC notes here, so
4728 use PATTERN (p) as argument to reg_set_p . */
4729 if (reg_set_p (reload_reg, PATTERN (p)))
4731 n = count_occurrences (PATTERN (p), reload_reg, 0);
4737 = gen_rtx_fmt_e (code, mode, reload_reg);
4739 validate_replace_rtx_group (reload_reg,
4741 n = verify_changes (0);
4743 /* We must also verify that the constraints
4744 are met after the replacement. Make sure
4745 extract_insn is only called for an insn
4746 where the replacements were found to be
4751 n = constrain_operands (1);
4754 /* If the constraints were not met, then
4755 undo the replacement, else confirm it. */
4759 confirm_change_group ();
4765 add_reg_note (p, REG_INC, reload_reg);
4766 /* Mark this as having an output reload so that the
4767 REG_INC processing code below won't invalidate
4768 the reload for inheritance. */
4769 SET_HARD_REG_BIT (reg_is_output_reload,
4770 REGNO (reload_reg));
4771 SET_REGNO_REG_SET (®_has_output_reload,
4772 REGNO (XEXP (in_reg, 0)));
4775 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4778 else if ((code == PRE_INC || code == PRE_DEC)
4779 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4780 REGNO (rld[i].reg_rtx))
4781 /* Make sure it is the inc/dec pseudo, and not
4782 some other (e.g. output operand) pseudo. */
4783 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4784 == REGNO (XEXP (in_reg, 0))))
4786 SET_HARD_REG_BIT (reg_is_output_reload,
4787 REGNO (rld[i].reg_rtx));
4788 SET_REGNO_REG_SET (®_has_output_reload,
4789 REGNO (XEXP (in_reg, 0)));
4791 else if (code == PRE_INC || code == PRE_DEC
4792 || code == POST_INC || code == POST_DEC)
4794 int in_regno = REGNO (XEXP (in_reg, 0));
4796 if (reg_last_reload_reg[in_regno] != NULL_RTX)
4799 bool forget_p = true;
4801 in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4802 if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4805 for (x = old_prev ? NEXT_INSN (old_prev) : insn;
4808 if (x == reg_reloaded_insn[in_hard_regno])
4814 /* If for some reasons, we didn't set up
4815 reg_last_reload_reg in this insn,
4816 invalidate inheritance from previous
4817 insns for the incremented/decremented
4818 register. Such registers will be not in
4819 reg_has_output_reload. Invalidate it
4820 also if the corresponding element in
4821 reg_reloaded_insn is also
4824 forget_old_reloads_1 (XEXP (in_reg, 0),
4830 /* If a pseudo that got a hard register is auto-incremented,
4831 we must purge records of copying it into pseudos without
4833 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4834 if (REG_NOTE_KIND (x) == REG_INC)
4836 /* See if this pseudo reg was reloaded in this insn.
4837 If so, its last-reload info is still valid
4838 because it is based on this insn's reload. */
4839 for (i = 0; i < n_reloads; i++)
4840 if (rld[i].out == XEXP (x, 0))
4844 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4848 /* A reload reg's contents are unknown after a label. */
4850 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4852 /* Don't assume a reload reg is still good after a call insn
4853 if it is a call-used reg, or if it contains a value that will
4854 be partially clobbered by the call. */
4855 else if (CALL_P (insn))
4857 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4858 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4860 /* If this is a call to a setjmp-type function, we must not
4861 reuse any reload reg contents across the call; that will
4862 just be clobbered by other uses of the register in later
4863 code, before the longjmp. */
4864 if (find_reg_note (insn, REG_SETJMP, NULL_RTX))
4865 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4870 free (reg_last_reload_reg);
4871 CLEAR_REG_SET (®_has_output_reload);
4874 /* Discard all record of any value reloaded from X,
4875 or reloaded in X from someplace else;
4876 unless X is an output reload reg of the current insn.
4878 X may be a hard reg (the reload reg)
4879 or it may be a pseudo reg that was reloaded from.
4881 When DATA is non-NULL just mark the registers in regset
4882 to be forgotten later. */
4885 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4890 regset regs = (regset) data;
4892 /* note_stores does give us subregs of hard regs,
4893 subreg_regno_offset requires a hard reg. */
4894 while (GET_CODE (x) == SUBREG)
4896 /* We ignore the subreg offset when calculating the regno,
4897 because we are using the entire underlying hard register
4907 if (regno >= FIRST_PSEUDO_REGISTER)
4913 nr = hard_regno_nregs[regno][GET_MODE (x)];
4914 /* Storing into a spilled-reg invalidates its contents.
4915 This can happen if a block-local pseudo is allocated to that reg
4916 and it wasn't spilled because this block's total need is 0.
4917 Then some insn might have an optional reload and use this reg. */
4919 for (i = 0; i < nr; i++)
4920 /* But don't do this if the reg actually serves as an output
4921 reload reg in the current instruction. */
4923 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4925 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4926 spill_reg_store[regno + i] = 0;
4932 SET_REGNO_REG_SET (regs, regno + nr);
4935 /* Since value of X has changed,
4936 forget any value previously copied from it. */
4939 /* But don't forget a copy if this is the output reload
4940 that establishes the copy's validity. */
4942 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4943 reg_last_reload_reg[regno + nr] = 0;
4947 /* Forget the reloads marked in regset by previous function. */
4949 forget_marked_reloads (regset regs)
4952 reg_set_iterator rsi;
4953 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4955 if (reg < FIRST_PSEUDO_REGISTER
4956 /* But don't do this if the reg actually serves as an output
4957 reload reg in the current instruction. */
4959 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4961 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4962 spill_reg_store[reg] = 0;
4965 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4966 reg_last_reload_reg[reg] = 0;
4970 /* The following HARD_REG_SETs indicate when each hard register is
4971 used for a reload of various parts of the current insn. */
4973 /* If reg is unavailable for all reloads. */
4974 static HARD_REG_SET reload_reg_unavailable;
4975 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4976 static HARD_REG_SET reload_reg_used;
4977 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4978 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4979 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4980 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4981 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4982 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4983 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4984 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4985 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4986 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4987 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4988 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4989 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4990 static HARD_REG_SET reload_reg_used_in_op_addr;
4991 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4992 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4993 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4994 static HARD_REG_SET reload_reg_used_in_insn;
4995 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4996 static HARD_REG_SET reload_reg_used_in_other_addr;
4998 /* If reg is in use as a reload reg for any sort of reload. */
4999 static HARD_REG_SET reload_reg_used_at_all;
5001 /* If reg is use as an inherited reload. We just mark the first register
5003 static HARD_REG_SET reload_reg_used_for_inherit;
5005 /* Records which hard regs are used in any way, either as explicit use or
5006 by being allocated to a pseudo during any point of the current insn. */
5007 static HARD_REG_SET reg_used_in_insn;
5009 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
5010 TYPE. MODE is used to indicate how many consecutive regs are
5014 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
5015 enum machine_mode mode)
5020 add_to_hard_reg_set (&reload_reg_used, mode, regno);
5023 case RELOAD_FOR_INPUT_ADDRESS:
5024 add_to_hard_reg_set (&reload_reg_used_in_input_addr[opnum], mode, regno);
5027 case RELOAD_FOR_INPADDR_ADDRESS:
5028 add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr[opnum], mode, regno);
5031 case RELOAD_FOR_OUTPUT_ADDRESS:
5032 add_to_hard_reg_set (&reload_reg_used_in_output_addr[opnum], mode, regno);
5035 case RELOAD_FOR_OUTADDR_ADDRESS:
5036 add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr[opnum], mode, regno);
5039 case RELOAD_FOR_OPERAND_ADDRESS:
5040 add_to_hard_reg_set (&reload_reg_used_in_op_addr, mode, regno);
5043 case RELOAD_FOR_OPADDR_ADDR:
5044 add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload, mode, regno);
5047 case RELOAD_FOR_OTHER_ADDRESS:
5048 add_to_hard_reg_set (&reload_reg_used_in_other_addr, mode, regno);
5051 case RELOAD_FOR_INPUT:
5052 add_to_hard_reg_set (&reload_reg_used_in_input[opnum], mode, regno);
5055 case RELOAD_FOR_OUTPUT:
5056 add_to_hard_reg_set (&reload_reg_used_in_output[opnum], mode, regno);
5059 case RELOAD_FOR_INSN:
5060 add_to_hard_reg_set (&reload_reg_used_in_insn, mode, regno);
5064 add_to_hard_reg_set (&reload_reg_used_at_all, mode, regno);
5067 /* Similarly, but show REGNO is no longer in use for a reload. */
5070 clear_reload_reg_in_use (unsigned int regno, int opnum,
5071 enum reload_type type, enum machine_mode mode)
5073 unsigned int nregs = hard_regno_nregs[regno][mode];
5074 unsigned int start_regno, end_regno, r;
5076 /* A complication is that for some reload types, inheritance might
5077 allow multiple reloads of the same types to share a reload register.
5078 We set check_opnum if we have to check only reloads with the same
5079 operand number, and check_any if we have to check all reloads. */
5080 int check_opnum = 0;
5082 HARD_REG_SET *used_in_set;
5087 used_in_set = &reload_reg_used;
5090 case RELOAD_FOR_INPUT_ADDRESS:
5091 used_in_set = &reload_reg_used_in_input_addr[opnum];
5094 case RELOAD_FOR_INPADDR_ADDRESS:
5096 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
5099 case RELOAD_FOR_OUTPUT_ADDRESS:
5100 used_in_set = &reload_reg_used_in_output_addr[opnum];
5103 case RELOAD_FOR_OUTADDR_ADDRESS:
5105 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
5108 case RELOAD_FOR_OPERAND_ADDRESS:
5109 used_in_set = &reload_reg_used_in_op_addr;
5112 case RELOAD_FOR_OPADDR_ADDR:
5114 used_in_set = &reload_reg_used_in_op_addr_reload;
5117 case RELOAD_FOR_OTHER_ADDRESS:
5118 used_in_set = &reload_reg_used_in_other_addr;
5122 case RELOAD_FOR_INPUT:
5123 used_in_set = &reload_reg_used_in_input[opnum];
5126 case RELOAD_FOR_OUTPUT:
5127 used_in_set = &reload_reg_used_in_output[opnum];
5130 case RELOAD_FOR_INSN:
5131 used_in_set = &reload_reg_used_in_insn;
5136 /* We resolve conflicts with remaining reloads of the same type by
5137 excluding the intervals of reload registers by them from the
5138 interval of freed reload registers. Since we only keep track of
5139 one set of interval bounds, we might have to exclude somewhat
5140 more than what would be necessary if we used a HARD_REG_SET here.
5141 But this should only happen very infrequently, so there should
5142 be no reason to worry about it. */
5144 start_regno = regno;
5145 end_regno = regno + nregs;
5146 if (check_opnum || check_any)
5148 for (i = n_reloads - 1; i >= 0; i--)
5150 if (rld[i].when_needed == type
5151 && (check_any || rld[i].opnum == opnum)
5154 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
5155 unsigned int conflict_end
5156 = end_hard_regno (rld[i].mode, conflict_start);
5158 /* If there is an overlap with the first to-be-freed register,
5159 adjust the interval start. */
5160 if (conflict_start <= start_regno && conflict_end > start_regno)
5161 start_regno = conflict_end;
5162 /* Otherwise, if there is a conflict with one of the other
5163 to-be-freed registers, adjust the interval end. */
5164 if (conflict_start > start_regno && conflict_start < end_regno)
5165 end_regno = conflict_start;
5170 for (r = start_regno; r < end_regno; r++)
5171 CLEAR_HARD_REG_BIT (*used_in_set, r);
5174 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5175 specified by OPNUM and TYPE. */
5178 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
5182 /* In use for a RELOAD_OTHER means it's not available for anything. */
5183 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
5184 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5190 /* In use for anything means we can't use it for RELOAD_OTHER. */
5191 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
5192 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5193 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5194 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5197 for (i = 0; i < reload_n_operands; i++)
5198 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5199 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5200 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5201 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5202 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5203 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5208 case RELOAD_FOR_INPUT:
5209 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5210 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
5213 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5216 /* If it is used for some other input, can't use it. */
5217 for (i = 0; i < reload_n_operands; i++)
5218 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5221 /* If it is used in a later operand's address, can't use it. */
5222 for (i = opnum + 1; i < reload_n_operands; i++)
5223 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5224 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5229 case RELOAD_FOR_INPUT_ADDRESS:
5230 /* Can't use a register if it is used for an input address for this
5231 operand or used as an input in an earlier one. */
5232 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
5233 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5236 for (i = 0; i < opnum; i++)
5237 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5242 case RELOAD_FOR_INPADDR_ADDRESS:
5243 /* Can't use a register if it is used for an input address
5244 for this operand or used as an input in an earlier
5246 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5249 for (i = 0; i < opnum; i++)
5250 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5255 case RELOAD_FOR_OUTPUT_ADDRESS:
5256 /* Can't use a register if it is used for an output address for this
5257 operand or used as an output in this or a later operand. Note
5258 that multiple output operands are emitted in reverse order, so
5259 the conflicting ones are those with lower indices. */
5260 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
5263 for (i = 0; i <= opnum; i++)
5264 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5269 case RELOAD_FOR_OUTADDR_ADDRESS:
5270 /* Can't use a register if it is used for an output address
5271 for this operand or used as an output in this or a
5272 later operand. Note that multiple output operands are
5273 emitted in reverse order, so the conflicting ones are
5274 those with lower indices. */
5275 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5278 for (i = 0; i <= opnum; i++)
5279 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5284 case RELOAD_FOR_OPERAND_ADDRESS:
5285 for (i = 0; i < reload_n_operands; i++)
5286 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5289 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5290 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5292 case RELOAD_FOR_OPADDR_ADDR:
5293 for (i = 0; i < reload_n_operands; i++)
5294 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5297 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
5299 case RELOAD_FOR_OUTPUT:
5300 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5301 outputs, or an operand address for this or an earlier output.
5302 Note that multiple output operands are emitted in reverse order,
5303 so the conflicting ones are those with higher indices. */
5304 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5307 for (i = 0; i < reload_n_operands; i++)
5308 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5311 for (i = opnum; i < reload_n_operands; i++)
5312 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5313 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5318 case RELOAD_FOR_INSN:
5319 for (i = 0; i < reload_n_operands; i++)
5320 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5321 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5324 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5325 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5327 case RELOAD_FOR_OTHER_ADDRESS:
5328 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
5335 /* Return 1 if the value in reload reg REGNO, as used by a reload
5336 needed for the part of the insn specified by OPNUM and TYPE,
5337 is still available in REGNO at the end of the insn.
5339 We can assume that the reload reg was already tested for availability
5340 at the time it is needed, and we should not check this again,
5341 in case the reg has already been marked in use. */
5344 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
5351 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5352 its value must reach the end. */
5355 /* If this use is for part of the insn,
5356 its value reaches if no subsequent part uses the same register.
5357 Just like the above function, don't try to do this with lots
5360 case RELOAD_FOR_OTHER_ADDRESS:
5361 /* Here we check for everything else, since these don't conflict
5362 with anything else and everything comes later. */
5364 for (i = 0; i < reload_n_operands; i++)
5365 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5366 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5367 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
5368 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5369 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5370 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5373 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5374 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5375 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5376 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5378 case RELOAD_FOR_INPUT_ADDRESS:
5379 case RELOAD_FOR_INPADDR_ADDRESS:
5380 /* Similar, except that we check only for this and subsequent inputs
5381 and the address of only subsequent inputs and we do not need
5382 to check for RELOAD_OTHER objects since they are known not to
5385 for (i = opnum; i < reload_n_operands; i++)
5386 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5389 for (i = opnum + 1; i < reload_n_operands; i++)
5390 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5391 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5394 for (i = 0; i < reload_n_operands; i++)
5395 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5396 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5397 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5400 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5403 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5404 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5405 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5407 case RELOAD_FOR_INPUT:
5408 /* Similar to input address, except we start at the next operand for
5409 both input and input address and we do not check for
5410 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5413 for (i = opnum + 1; i < reload_n_operands; i++)
5414 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5415 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5416 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5419 /* ... fall through ... */
5421 case RELOAD_FOR_OPERAND_ADDRESS:
5422 /* Check outputs and their addresses. */
5424 for (i = 0; i < reload_n_operands; i++)
5425 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5426 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5427 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5430 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5432 case RELOAD_FOR_OPADDR_ADDR:
5433 for (i = 0; i < reload_n_operands; i++)
5434 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5435 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5436 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5439 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5440 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5441 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5443 case RELOAD_FOR_INSN:
5444 /* These conflict with other outputs with RELOAD_OTHER. So
5445 we need only check for output addresses. */
5447 opnum = reload_n_operands;
5449 /* ... fall through ... */
5451 case RELOAD_FOR_OUTPUT:
5452 case RELOAD_FOR_OUTPUT_ADDRESS:
5453 case RELOAD_FOR_OUTADDR_ADDRESS:
5454 /* We already know these can't conflict with a later output. So the
5455 only thing to check are later output addresses.
5456 Note that multiple output operands are emitted in reverse order,
5457 so the conflicting ones are those with lower indices. */
5458 for (i = 0; i < opnum; i++)
5459 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5460 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5470 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5471 every register in the range [REGNO, REGNO + NREGS). */
5474 reload_regs_reach_end_p (unsigned int regno, int nregs,
5475 int opnum, enum reload_type type)
5479 for (i = 0; i < nregs; i++)
5480 if (!reload_reg_reaches_end_p (regno + i, opnum, type))
5486 /* Returns whether R1 and R2 are uniquely chained: the value of one
5487 is used by the other, and that value is not used by any other
5488 reload for this insn. This is used to partially undo the decision
5489 made in find_reloads when in the case of multiple
5490 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5491 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5492 reloads. This code tries to avoid the conflict created by that
5493 change. It might be cleaner to explicitly keep track of which
5494 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5495 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5496 this after the fact. */
5498 reloads_unique_chain_p (int r1, int r2)
5502 /* We only check input reloads. */
5503 if (! rld[r1].in || ! rld[r2].in)
5506 /* Avoid anything with output reloads. */
5507 if (rld[r1].out || rld[r2].out)
5510 /* "chained" means one reload is a component of the other reload,
5511 not the same as the other reload. */
5512 if (rld[r1].opnum != rld[r2].opnum
5513 || rtx_equal_p (rld[r1].in, rld[r2].in)
5514 || rld[r1].optional || rld[r2].optional
5515 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5516 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5519 for (i = 0; i < n_reloads; i ++)
5520 /* Look for input reloads that aren't our two */
5521 if (i != r1 && i != r2 && rld[i].in)
5523 /* If our reload is mentioned at all, it isn't a simple chain. */
5524 if (reg_mentioned_p (rld[r1].in, rld[i].in))
5530 /* The recursive function change all occurrences of WHAT in *WHERE
5533 substitute (rtx *where, const_rtx what, rtx repl)
5542 if (*where == what || rtx_equal_p (*where, what))
5544 /* Record the location of the changed rtx. */
5545 VEC_safe_push (rtx_p, heap, substitute_stack, where);
5550 code = GET_CODE (*where);
5551 fmt = GET_RTX_FORMAT (code);
5552 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5558 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5559 substitute (&XVECEXP (*where, i, j), what, repl);
5561 else if (fmt[i] == 'e')
5562 substitute (&XEXP (*where, i), what, repl);
5566 /* The function returns TRUE if chain of reload R1 and R2 (in any
5567 order) can be evaluated without usage of intermediate register for
5568 the reload containing another reload. It is important to see
5569 gen_reload to understand what the function is trying to do. As an
5570 example, let us have reload chain
5573 r1: <something> + const
5575 and reload R2 got reload reg HR. The function returns true if
5576 there is a correct insn HR = HR + <something>. Otherwise,
5577 gen_reload will use intermediate register (and this is the reload
5578 reg for R1) to reload <something>.
5580 We need this function to find a conflict for chain reloads. In our
5581 example, if HR = HR + <something> is incorrect insn, then we cannot
5582 use HR as a reload register for R2. If we do use it then we get a
5591 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5593 /* Assume other cases in gen_reload are not possible for
5594 chain reloads or do need an intermediate hard registers. */
5598 rtx last = get_last_insn ();
5600 /* Make r2 a component of r1. */
5601 if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5607 gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5608 regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5609 gcc_assert (regno >= 0);
5610 out = gen_rtx_REG (rld[r1].mode, regno);
5612 substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5614 /* If IN is a paradoxical SUBREG, remove it and try to put the
5615 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5616 strip_paradoxical_subreg (&in, &out);
5618 if (GET_CODE (in) == PLUS
5619 && (REG_P (XEXP (in, 0))
5620 || GET_CODE (XEXP (in, 0)) == SUBREG
5621 || MEM_P (XEXP (in, 0)))
5622 && (REG_P (XEXP (in, 1))
5623 || GET_CODE (XEXP (in, 1)) == SUBREG
5624 || CONSTANT_P (XEXP (in, 1))
5625 || MEM_P (XEXP (in, 1))))
5627 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
5628 code = recog_memoized (insn);
5633 extract_insn (insn);
5634 /* We want constrain operands to treat this insn strictly in
5635 its validity determination, i.e., the way it would after
5636 reload has completed. */
5637 result = constrain_operands (1);
5640 delete_insns_since (last);
5643 /* Restore the original value at each changed address within R1. */
5644 while (!VEC_empty (rtx_p, substitute_stack))
5646 rtx *where = VEC_pop (rtx_p, substitute_stack);
5647 *where = rld[r2].in;
5653 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5656 This function uses the same algorithm as reload_reg_free_p above. */
5659 reloads_conflict (int r1, int r2)
5661 enum reload_type r1_type = rld[r1].when_needed;
5662 enum reload_type r2_type = rld[r2].when_needed;
5663 int r1_opnum = rld[r1].opnum;
5664 int r2_opnum = rld[r2].opnum;
5666 /* RELOAD_OTHER conflicts with everything. */
5667 if (r2_type == RELOAD_OTHER)
5670 /* Otherwise, check conflicts differently for each type. */
5674 case RELOAD_FOR_INPUT:
5675 return (r2_type == RELOAD_FOR_INSN
5676 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5677 || r2_type == RELOAD_FOR_OPADDR_ADDR
5678 || r2_type == RELOAD_FOR_INPUT
5679 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5680 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5681 && r2_opnum > r1_opnum));
5683 case RELOAD_FOR_INPUT_ADDRESS:
5684 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5685 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5687 case RELOAD_FOR_INPADDR_ADDRESS:
5688 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5689 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5691 case RELOAD_FOR_OUTPUT_ADDRESS:
5692 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5693 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5695 case RELOAD_FOR_OUTADDR_ADDRESS:
5696 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5697 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5699 case RELOAD_FOR_OPERAND_ADDRESS:
5700 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5701 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5702 && (!reloads_unique_chain_p (r1, r2)
5703 || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5705 case RELOAD_FOR_OPADDR_ADDR:
5706 return (r2_type == RELOAD_FOR_INPUT
5707 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5709 case RELOAD_FOR_OUTPUT:
5710 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5711 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5712 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5713 && r2_opnum >= r1_opnum));
5715 case RELOAD_FOR_INSN:
5716 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5717 || r2_type == RELOAD_FOR_INSN
5718 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5720 case RELOAD_FOR_OTHER_ADDRESS:
5721 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5731 /* Indexed by reload number, 1 if incoming value
5732 inherited from previous insns. */
5733 static char reload_inherited[MAX_RELOADS];
5735 /* For an inherited reload, this is the insn the reload was inherited from,
5736 if we know it. Otherwise, this is 0. */
5737 static rtx reload_inheritance_insn[MAX_RELOADS];
5739 /* If nonzero, this is a place to get the value of the reload,
5740 rather than using reload_in. */
5741 static rtx reload_override_in[MAX_RELOADS];
5743 /* For each reload, the hard register number of the register used,
5744 or -1 if we did not need a register for this reload. */
5745 static int reload_spill_index[MAX_RELOADS];
5747 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5748 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5750 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5751 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5753 /* Subroutine of free_for_value_p, used to check a single register.
5754 START_REGNO is the starting regno of the full reload register
5755 (possibly comprising multiple hard registers) that we are considering. */
5758 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5759 enum reload_type type, rtx value, rtx out,
5760 int reloadnum, int ignore_address_reloads)
5763 /* Set if we see an input reload that must not share its reload register
5764 with any new earlyclobber, but might otherwise share the reload
5765 register with an output or input-output reload. */
5766 int check_earlyclobber = 0;
5770 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5773 if (out == const0_rtx)
5779 /* We use some pseudo 'time' value to check if the lifetimes of the
5780 new register use would overlap with the one of a previous reload
5781 that is not read-only or uses a different value.
5782 The 'time' used doesn't have to be linear in any shape or form, just
5784 Some reload types use different 'buckets' for each operand.
5785 So there are MAX_RECOG_OPERANDS different time values for each
5787 We compute TIME1 as the time when the register for the prospective
5788 new reload ceases to be live, and TIME2 for each existing
5789 reload as the time when that the reload register of that reload
5791 Where there is little to be gained by exact lifetime calculations,
5792 we just make conservative assumptions, i.e. a longer lifetime;
5793 this is done in the 'default:' cases. */
5796 case RELOAD_FOR_OTHER_ADDRESS:
5797 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5798 time1 = copy ? 0 : 1;
5801 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5803 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5804 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5805 respectively, to the time values for these, we get distinct time
5806 values. To get distinct time values for each operand, we have to
5807 multiply opnum by at least three. We round that up to four because
5808 multiply by four is often cheaper. */
5809 case RELOAD_FOR_INPADDR_ADDRESS:
5810 time1 = opnum * 4 + 2;
5812 case RELOAD_FOR_INPUT_ADDRESS:
5813 time1 = opnum * 4 + 3;
5815 case RELOAD_FOR_INPUT:
5816 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5817 executes (inclusive). */
5818 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5820 case RELOAD_FOR_OPADDR_ADDR:
5822 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5823 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5825 case RELOAD_FOR_OPERAND_ADDRESS:
5826 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5828 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5830 case RELOAD_FOR_OUTADDR_ADDRESS:
5831 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5833 case RELOAD_FOR_OUTPUT_ADDRESS:
5834 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5837 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5840 for (i = 0; i < n_reloads; i++)
5842 rtx reg = rld[i].reg_rtx;
5843 if (reg && REG_P (reg)
5844 && ((unsigned) regno - true_regnum (reg)
5845 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5848 rtx other_input = rld[i].in;
5850 /* If the other reload loads the same input value, that
5851 will not cause a conflict only if it's loading it into
5852 the same register. */
5853 if (true_regnum (reg) != start_regno)
5854 other_input = NULL_RTX;
5855 if (! other_input || ! rtx_equal_p (other_input, value)
5856 || rld[i].out || out)
5859 switch (rld[i].when_needed)
5861 case RELOAD_FOR_OTHER_ADDRESS:
5864 case RELOAD_FOR_INPADDR_ADDRESS:
5865 /* find_reloads makes sure that a
5866 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5867 by at most one - the first -
5868 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5869 address reload is inherited, the address address reload
5870 goes away, so we can ignore this conflict. */
5871 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5872 && ignore_address_reloads
5873 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5874 Then the address address is still needed to store
5875 back the new address. */
5876 && ! rld[reloadnum].out)
5878 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5879 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5881 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5882 && ignore_address_reloads
5883 /* Unless we are reloading an auto_inc expression. */
5884 && ! rld[reloadnum].out)
5886 time2 = rld[i].opnum * 4 + 2;
5888 case RELOAD_FOR_INPUT_ADDRESS:
5889 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5890 && ignore_address_reloads
5891 && ! rld[reloadnum].out)
5893 time2 = rld[i].opnum * 4 + 3;
5895 case RELOAD_FOR_INPUT:
5896 time2 = rld[i].opnum * 4 + 4;
5897 check_earlyclobber = 1;
5899 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5900 == MAX_RECOG_OPERAND * 4 */
5901 case RELOAD_FOR_OPADDR_ADDR:
5902 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5903 && ignore_address_reloads
5904 && ! rld[reloadnum].out)
5906 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5908 case RELOAD_FOR_OPERAND_ADDRESS:
5909 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5910 check_earlyclobber = 1;
5912 case RELOAD_FOR_INSN:
5913 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5915 case RELOAD_FOR_OUTPUT:
5916 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5917 instruction is executed. */
5918 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5920 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5921 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5923 case RELOAD_FOR_OUTADDR_ADDRESS:
5924 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5925 && ignore_address_reloads
5926 && ! rld[reloadnum].out)
5928 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5930 case RELOAD_FOR_OUTPUT_ADDRESS:
5931 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5934 /* If there is no conflict in the input part, handle this
5935 like an output reload. */
5936 if (! rld[i].in || rtx_equal_p (other_input, value))
5938 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5939 /* Earlyclobbered outputs must conflict with inputs. */
5940 if (earlyclobber_operand_p (rld[i].out))
5941 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5946 /* RELOAD_OTHER might be live beyond instruction execution,
5947 but this is not obvious when we set time2 = 1. So check
5948 here if there might be a problem with the new reload
5949 clobbering the register used by the RELOAD_OTHER. */
5957 && (! rld[i].in || rld[i].out
5958 || ! rtx_equal_p (other_input, value)))
5959 || (out && rld[reloadnum].out_reg
5960 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5966 /* Earlyclobbered outputs must conflict with inputs. */
5967 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5973 /* Return 1 if the value in reload reg REGNO, as used by a reload
5974 needed for the part of the insn specified by OPNUM and TYPE,
5975 may be used to load VALUE into it.
5977 MODE is the mode in which the register is used, this is needed to
5978 determine how many hard regs to test.
5980 Other read-only reloads with the same value do not conflict
5981 unless OUT is nonzero and these other reloads have to live while
5982 output reloads live.
5983 If OUT is CONST0_RTX, this is a special case: it means that the
5984 test should not be for using register REGNO as reload register, but
5985 for copying from register REGNO into the reload register.
5987 RELOADNUM is the number of the reload we want to load this value for;
5988 a reload does not conflict with itself.
5990 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5991 reloads that load an address for the very reload we are considering.
5993 The caller has to make sure that there is no conflict with the return
5997 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5998 enum reload_type type, rtx value, rtx out, int reloadnum,
5999 int ignore_address_reloads)
6001 int nregs = hard_regno_nregs[regno][mode];
6003 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
6004 value, out, reloadnum,
6005 ignore_address_reloads))
6010 /* Return nonzero if the rtx X is invariant over the current function. */
6011 /* ??? Actually, the places where we use this expect exactly what is
6012 tested here, and not everything that is function invariant. In
6013 particular, the frame pointer and arg pointer are special cased;
6014 pic_offset_table_rtx is not, and we must not spill these things to
6018 function_invariant_p (const_rtx x)
6022 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
6024 if (GET_CODE (x) == PLUS
6025 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
6026 && GET_CODE (XEXP (x, 1)) == CONST_INT)
6031 /* Determine whether the reload reg X overlaps any rtx'es used for
6032 overriding inheritance. Return nonzero if so. */
6035 conflicts_with_override (rtx x)
6038 for (i = 0; i < n_reloads; i++)
6039 if (reload_override_in[i]
6040 && reg_overlap_mentioned_p (x, reload_override_in[i]))
6045 /* Give an error message saying we failed to find a reload for INSN,
6046 and clear out reload R. */
6048 failed_reload (rtx insn, int r)
6050 if (asm_noperands (PATTERN (insn)) < 0)
6051 /* It's the compiler's fault. */
6052 fatal_insn ("could not find a spill register", insn);
6054 /* It's the user's fault; the operand's mode and constraint
6055 don't match. Disable this reload so we don't crash in final. */
6056 error_for_asm (insn,
6057 "%<asm%> operand constraint incompatible with operand size");
6061 rld[r].optional = 1;
6062 rld[r].secondary_p = 1;
6065 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6066 for reload R. If it's valid, get an rtx for it. Return nonzero if
6069 set_reload_reg (int i, int r)
6071 /* regno is 'set but not used' if HARD_REGNO_MODE_OK doesn't use its first
6073 int regno ATTRIBUTE_UNUSED;
6074 rtx reg = spill_reg_rtx[i];
6076 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
6077 spill_reg_rtx[i] = reg
6078 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
6080 regno = true_regnum (reg);
6082 /* Detect when the reload reg can't hold the reload mode.
6083 This used to be one `if', but Sequent compiler can't handle that. */
6084 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
6086 enum machine_mode test_mode = VOIDmode;
6088 test_mode = GET_MODE (rld[r].in);
6089 /* If rld[r].in has VOIDmode, it means we will load it
6090 in whatever mode the reload reg has: to wit, rld[r].mode.
6091 We have already tested that for validity. */
6092 /* Aside from that, we need to test that the expressions
6093 to reload from or into have modes which are valid for this
6094 reload register. Otherwise the reload insns would be invalid. */
6095 if (! (rld[r].in != 0 && test_mode != VOIDmode
6096 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
6097 if (! (rld[r].out != 0
6098 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
6100 /* The reg is OK. */
6103 /* Mark as in use for this insn the reload regs we use
6105 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
6106 rld[r].when_needed, rld[r].mode);
6108 rld[r].reg_rtx = reg;
6109 reload_spill_index[r] = spill_regs[i];
6116 /* Find a spill register to use as a reload register for reload R.
6117 LAST_RELOAD is nonzero if this is the last reload for the insn being
6120 Set rld[R].reg_rtx to the register allocated.
6122 We return 1 if successful, or 0 if we couldn't find a spill reg and
6123 we didn't change anything. */
6126 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
6131 /* If we put this reload ahead, thinking it is a group,
6132 then insist on finding a group. Otherwise we can grab a
6133 reg that some other reload needs.
6134 (That can happen when we have a 68000 DATA_OR_FP_REG
6135 which is a group of data regs or one fp reg.)
6136 We need not be so restrictive if there are no more reloads
6139 ??? Really it would be nicer to have smarter handling
6140 for that kind of reg class, where a problem like this is normal.
6141 Perhaps those classes should be avoided for reloading
6142 by use of more alternatives. */
6144 int force_group = rld[r].nregs > 1 && ! last_reload;
6146 /* If we want a single register and haven't yet found one,
6147 take any reg in the right class and not in use.
6148 If we want a consecutive group, here is where we look for it.
6150 We use three passes so we can first look for reload regs to
6151 reuse, which are already in use for other reloads in this insn,
6152 and only then use additional registers which are not "bad", then
6153 finally any register.
6155 I think that maximizing reuse is needed to make sure we don't
6156 run out of reload regs. Suppose we have three reloads, and
6157 reloads A and B can share regs. These need two regs.
6158 Suppose A and B are given different regs.
6159 That leaves none for C. */
6160 for (pass = 0; pass < 3; pass++)
6162 /* I is the index in spill_regs.
6163 We advance it round-robin between insns to use all spill regs
6164 equally, so that inherited reloads have a chance
6165 of leapfrogging each other. */
6169 for (count = 0; count < n_spills; count++)
6171 int rclass = (int) rld[r].rclass;
6177 regnum = spill_regs[i];
6179 if ((reload_reg_free_p (regnum, rld[r].opnum,
6182 /* We check reload_reg_used to make sure we
6183 don't clobber the return register. */
6184 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
6185 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
6186 rld[r].when_needed, rld[r].in,
6188 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
6189 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
6190 /* Look first for regs to share, then for unshared. But
6191 don't share regs used for inherited reloads; they are
6192 the ones we want to preserve. */
6194 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
6196 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
6199 int nr = hard_regno_nregs[regnum][rld[r].mode];
6201 /* During the second pass we want to avoid reload registers
6202 which are "bad" for this reload. */
6204 && ira_bad_reload_regno (regnum, rld[r].in, rld[r].out))
6207 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6208 (on 68000) got us two FP regs. If NR is 1,
6209 we would reject both of them. */
6212 /* If we need only one reg, we have already won. */
6215 /* But reject a single reg if we demand a group. */
6220 /* Otherwise check that as many consecutive regs as we need
6221 are available here. */
6224 int regno = regnum + nr - 1;
6225 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
6226 && spill_reg_order[regno] >= 0
6227 && reload_reg_free_p (regno, rld[r].opnum,
6228 rld[r].when_needed)))
6237 /* If we found something on the current pass, omit later passes. */
6238 if (count < n_spills)
6242 /* We should have found a spill register by now. */
6243 if (count >= n_spills)
6246 /* I is the index in SPILL_REG_RTX of the reload register we are to
6247 allocate. Get an rtx for it and find its register number. */
6249 return set_reload_reg (i, r);
6252 /* Initialize all the tables needed to allocate reload registers.
6253 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6254 is the array we use to restore the reg_rtx field for every reload. */
6257 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
6261 for (i = 0; i < n_reloads; i++)
6262 rld[i].reg_rtx = save_reload_reg_rtx[i];
6264 memset (reload_inherited, 0, MAX_RELOADS);
6265 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
6266 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
6268 CLEAR_HARD_REG_SET (reload_reg_used);
6269 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
6270 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
6271 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
6272 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
6273 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
6275 CLEAR_HARD_REG_SET (reg_used_in_insn);
6278 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
6279 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6280 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
6281 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6282 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
6283 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
6286 for (i = 0; i < reload_n_operands; i++)
6288 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
6289 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
6290 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
6291 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
6292 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
6293 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
6296 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
6298 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
6300 for (i = 0; i < n_reloads; i++)
6301 /* If we have already decided to use a certain register,
6302 don't use it in another way. */
6304 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
6305 rld[i].when_needed, rld[i].mode);
6308 /* Assign hard reg targets for the pseudo-registers we must reload
6309 into hard regs for this insn.
6310 Also output the instructions to copy them in and out of the hard regs.
6312 For machines with register classes, we are responsible for
6313 finding a reload reg in the proper class. */
6316 choose_reload_regs (struct insn_chain *chain)
6318 rtx insn = chain->insn;
6320 unsigned int max_group_size = 1;
6321 enum reg_class group_class = NO_REGS;
6322 int pass, win, inheritance;
6324 rtx save_reload_reg_rtx[MAX_RELOADS];
6326 /* In order to be certain of getting the registers we need,
6327 we must sort the reloads into order of increasing register class.
6328 Then our grabbing of reload registers will parallel the process
6329 that provided the reload registers.
6331 Also note whether any of the reloads wants a consecutive group of regs.
6332 If so, record the maximum size of the group desired and what
6333 register class contains all the groups needed by this insn. */
6335 for (j = 0; j < n_reloads; j++)
6337 reload_order[j] = j;
6338 if (rld[j].reg_rtx != NULL_RTX)
6340 gcc_assert (REG_P (rld[j].reg_rtx)
6341 && HARD_REGISTER_P (rld[j].reg_rtx));
6342 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
6345 reload_spill_index[j] = -1;
6347 if (rld[j].nregs > 1)
6349 max_group_size = MAX (rld[j].nregs, max_group_size);
6351 = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
6354 save_reload_reg_rtx[j] = rld[j].reg_rtx;
6358 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
6360 /* If -O, try first with inheritance, then turning it off.
6361 If not -O, don't do inheritance.
6362 Using inheritance when not optimizing leads to paradoxes
6363 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6364 because one side of the comparison might be inherited. */
6366 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
6368 choose_reload_regs_init (chain, save_reload_reg_rtx);
6370 /* Process the reloads in order of preference just found.
6371 Beyond this point, subregs can be found in reload_reg_rtx.
6373 This used to look for an existing reloaded home for all of the
6374 reloads, and only then perform any new reloads. But that could lose
6375 if the reloads were done out of reg-class order because a later
6376 reload with a looser constraint might have an old home in a register
6377 needed by an earlier reload with a tighter constraint.
6379 To solve this, we make two passes over the reloads, in the order
6380 described above. In the first pass we try to inherit a reload
6381 from a previous insn. If there is a later reload that needs a
6382 class that is a proper subset of the class being processed, we must
6383 also allocate a spill register during the first pass.
6385 Then make a second pass over the reloads to allocate any reloads
6386 that haven't been given registers yet. */
6388 for (j = 0; j < n_reloads; j++)
6390 int r = reload_order[j];
6391 rtx search_equiv = NULL_RTX;
6393 /* Ignore reloads that got marked inoperative. */
6394 if (rld[r].out == 0 && rld[r].in == 0
6395 && ! rld[r].secondary_p)
6398 /* If find_reloads chose to use reload_in or reload_out as a reload
6399 register, we don't need to chose one. Otherwise, try even if it
6400 found one since we might save an insn if we find the value lying
6402 Try also when reload_in is a pseudo without a hard reg. */
6403 if (rld[r].in != 0 && rld[r].reg_rtx != 0
6404 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
6405 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
6406 && !MEM_P (rld[r].in)
6407 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
6410 #if 0 /* No longer needed for correct operation.
6411 It might give better code, or might not; worth an experiment? */
6412 /* If this is an optional reload, we can't inherit from earlier insns
6413 until we are sure that any non-optional reloads have been allocated.
6414 The following code takes advantage of the fact that optional reloads
6415 are at the end of reload_order. */
6416 if (rld[r].optional != 0)
6417 for (i = 0; i < j; i++)
6418 if ((rld[reload_order[i]].out != 0
6419 || rld[reload_order[i]].in != 0
6420 || rld[reload_order[i]].secondary_p)
6421 && ! rld[reload_order[i]].optional
6422 && rld[reload_order[i]].reg_rtx == 0)
6423 allocate_reload_reg (chain, reload_order[i], 0);
6426 /* First see if this pseudo is already available as reloaded
6427 for a previous insn. We cannot try to inherit for reloads
6428 that are smaller than the maximum number of registers needed
6429 for groups unless the register we would allocate cannot be used
6432 We could check here to see if this is a secondary reload for
6433 an object that is already in a register of the desired class.
6434 This would avoid the need for the secondary reload register.
6435 But this is complex because we can't easily determine what
6436 objects might want to be loaded via this reload. So let a
6437 register be allocated here. In `emit_reload_insns' we suppress
6438 one of the loads in the case described above. */
6444 enum machine_mode mode = VOIDmode;
6448 else if (REG_P (rld[r].in))
6450 regno = REGNO (rld[r].in);
6451 mode = GET_MODE (rld[r].in);
6453 else if (REG_P (rld[r].in_reg))
6455 regno = REGNO (rld[r].in_reg);
6456 mode = GET_MODE (rld[r].in_reg);
6458 else if (GET_CODE (rld[r].in_reg) == SUBREG
6459 && REG_P (SUBREG_REG (rld[r].in_reg)))
6461 regno = REGNO (SUBREG_REG (rld[r].in_reg));
6462 if (regno < FIRST_PSEUDO_REGISTER)
6463 regno = subreg_regno (rld[r].in_reg);
6465 byte = SUBREG_BYTE (rld[r].in_reg);
6466 mode = GET_MODE (rld[r].in_reg);
6469 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6470 && REG_P (XEXP (rld[r].in_reg, 0)))
6472 regno = REGNO (XEXP (rld[r].in_reg, 0));
6473 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6474 rld[r].out = rld[r].in;
6478 /* This won't work, since REGNO can be a pseudo reg number.
6479 Also, it takes much more hair to keep track of all the things
6480 that can invalidate an inherited reload of part of a pseudoreg. */
6481 else if (GET_CODE (rld[r].in) == SUBREG
6482 && REG_P (SUBREG_REG (rld[r].in)))
6483 regno = subreg_regno (rld[r].in);
6487 && reg_last_reload_reg[regno] != 0
6488 #ifdef CANNOT_CHANGE_MODE_CLASS
6489 /* Verify that the register it's in can be used in
6491 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
6492 GET_MODE (reg_last_reload_reg[regno]),
6497 enum reg_class rclass = rld[r].rclass, last_class;
6498 rtx last_reg = reg_last_reload_reg[regno];
6499 enum machine_mode need_mode;
6501 i = REGNO (last_reg);
6502 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6503 last_class = REGNO_REG_CLASS (i);
6509 = smallest_mode_for_size
6510 (GET_MODE_BITSIZE (mode) + byte * BITS_PER_UNIT,
6511 GET_MODE_CLASS (mode) == MODE_PARTIAL_INT
6512 ? MODE_INT : GET_MODE_CLASS (mode));
6514 if ((GET_MODE_SIZE (GET_MODE (last_reg))
6515 >= GET_MODE_SIZE (need_mode))
6516 && reg_reloaded_contents[i] == regno
6517 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6518 && HARD_REGNO_MODE_OK (i, rld[r].mode)
6519 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6520 /* Even if we can't use this register as a reload
6521 register, we might use it for reload_override_in,
6522 if copying it to the desired class is cheap
6524 || ((register_move_cost (mode, last_class, rclass)
6525 < memory_move_cost (mode, rclass, true))
6526 && (secondary_reload_class (1, rclass, mode,
6529 #ifdef SECONDARY_MEMORY_NEEDED
6530 && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
6535 && (rld[r].nregs == max_group_size
6536 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6538 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6539 rld[r].when_needed, rld[r].in,
6542 /* If a group is needed, verify that all the subsequent
6543 registers still have their values intact. */
6544 int nr = hard_regno_nregs[i][rld[r].mode];
6547 for (k = 1; k < nr; k++)
6548 if (reg_reloaded_contents[i + k] != regno
6549 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6557 last_reg = (GET_MODE (last_reg) == mode
6558 ? last_reg : gen_rtx_REG (mode, i));
6561 for (k = 0; k < nr; k++)
6562 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6565 /* We found a register that contains the
6566 value we need. If this register is the
6567 same as an `earlyclobber' operand of the
6568 current insn, just mark it as a place to
6569 reload from since we can't use it as the
6570 reload register itself. */
6572 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6573 if (reg_overlap_mentioned_for_reload_p
6574 (reg_last_reload_reg[regno],
6575 reload_earlyclobbers[i1]))
6578 if (i1 != n_earlyclobbers
6579 || ! (free_for_value_p (i, rld[r].mode,
6581 rld[r].when_needed, rld[r].in,
6583 /* Don't use it if we'd clobber a pseudo reg. */
6584 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6586 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6587 /* Don't clobber the frame pointer. */
6588 || (i == HARD_FRAME_POINTER_REGNUM
6589 && frame_pointer_needed
6591 /* Don't really use the inherited spill reg
6592 if we need it wider than we've got it. */
6593 || (GET_MODE_SIZE (rld[r].mode)
6594 > GET_MODE_SIZE (mode))
6597 /* If find_reloads chose reload_out as reload
6598 register, stay with it - that leaves the
6599 inherited register for subsequent reloads. */
6600 || (rld[r].out && rld[r].reg_rtx
6601 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6603 if (! rld[r].optional)
6605 reload_override_in[r] = last_reg;
6606 reload_inheritance_insn[r]
6607 = reg_reloaded_insn[i];
6613 /* We can use this as a reload reg. */
6614 /* Mark the register as in use for this part of
6616 mark_reload_reg_in_use (i,
6620 rld[r].reg_rtx = last_reg;
6621 reload_inherited[r] = 1;
6622 reload_inheritance_insn[r]
6623 = reg_reloaded_insn[i];
6624 reload_spill_index[r] = i;
6625 for (k = 0; k < nr; k++)
6626 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6634 /* Here's another way to see if the value is already lying around. */
6637 && ! reload_inherited[r]
6639 && (CONSTANT_P (rld[r].in)
6640 || GET_CODE (rld[r].in) == PLUS
6641 || REG_P (rld[r].in)
6642 || MEM_P (rld[r].in))
6643 && (rld[r].nregs == max_group_size
6644 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6645 search_equiv = rld[r].in;
6650 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6651 -1, NULL, 0, rld[r].mode);
6657 regno = REGNO (equiv);
6660 /* This must be a SUBREG of a hard register.
6661 Make a new REG since this might be used in an
6662 address and not all machines support SUBREGs
6664 gcc_assert (GET_CODE (equiv) == SUBREG);
6665 regno = subreg_regno (equiv);
6666 equiv = gen_rtx_REG (rld[r].mode, regno);
6667 /* If we choose EQUIV as the reload register, but the
6668 loop below decides to cancel the inheritance, we'll
6669 end up reloading EQUIV in rld[r].mode, not the mode
6670 it had originally. That isn't safe when EQUIV isn't
6671 available as a spill register since its value might
6672 still be live at this point. */
6673 for (i = regno; i < regno + (int) rld[r].nregs; i++)
6674 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6679 /* If we found a spill reg, reject it unless it is free
6680 and of the desired class. */
6684 int bad_for_class = 0;
6685 int max_regno = regno + rld[r].nregs;
6687 for (i = regno; i < max_regno; i++)
6689 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6691 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6696 && ! free_for_value_p (regno, rld[r].mode,
6697 rld[r].opnum, rld[r].when_needed,
6698 rld[r].in, rld[r].out, r, 1))
6703 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6706 /* We found a register that contains the value we need.
6707 If this register is the same as an `earlyclobber' operand
6708 of the current insn, just mark it as a place to reload from
6709 since we can't use it as the reload register itself. */
6712 for (i = 0; i < n_earlyclobbers; i++)
6713 if (reg_overlap_mentioned_for_reload_p (equiv,
6714 reload_earlyclobbers[i]))
6716 if (! rld[r].optional)
6717 reload_override_in[r] = equiv;
6722 /* If the equiv register we have found is explicitly clobbered
6723 in the current insn, it depends on the reload type if we
6724 can use it, use it for reload_override_in, or not at all.
6725 In particular, we then can't use EQUIV for a
6726 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6730 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6731 switch (rld[r].when_needed)
6733 case RELOAD_FOR_OTHER_ADDRESS:
6734 case RELOAD_FOR_INPADDR_ADDRESS:
6735 case RELOAD_FOR_INPUT_ADDRESS:
6736 case RELOAD_FOR_OPADDR_ADDR:
6739 case RELOAD_FOR_INPUT:
6740 case RELOAD_FOR_OPERAND_ADDRESS:
6741 if (! rld[r].optional)
6742 reload_override_in[r] = equiv;
6748 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6749 switch (rld[r].when_needed)
6751 case RELOAD_FOR_OTHER_ADDRESS:
6752 case RELOAD_FOR_INPADDR_ADDRESS:
6753 case RELOAD_FOR_INPUT_ADDRESS:
6754 case RELOAD_FOR_OPADDR_ADDR:
6755 case RELOAD_FOR_OPERAND_ADDRESS:
6756 case RELOAD_FOR_INPUT:
6759 if (! rld[r].optional)
6760 reload_override_in[r] = equiv;
6768 /* If we found an equivalent reg, say no code need be generated
6769 to load it, and use it as our reload reg. */
6771 && (regno != HARD_FRAME_POINTER_REGNUM
6772 || !frame_pointer_needed))
6774 int nr = hard_regno_nregs[regno][rld[r].mode];
6776 rld[r].reg_rtx = equiv;
6777 reload_spill_index[r] = regno;
6778 reload_inherited[r] = 1;
6780 /* If reg_reloaded_valid is not set for this register,
6781 there might be a stale spill_reg_store lying around.
6782 We must clear it, since otherwise emit_reload_insns
6783 might delete the store. */
6784 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6785 spill_reg_store[regno] = NULL_RTX;
6786 /* If any of the hard registers in EQUIV are spill
6787 registers, mark them as in use for this insn. */
6788 for (k = 0; k < nr; k++)
6790 i = spill_reg_order[regno + k];
6793 mark_reload_reg_in_use (regno, rld[r].opnum,
6796 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6803 /* If we found a register to use already, or if this is an optional
6804 reload, we are done. */
6805 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6809 /* No longer needed for correct operation. Might or might
6810 not give better code on the average. Want to experiment? */
6812 /* See if there is a later reload that has a class different from our
6813 class that intersects our class or that requires less register
6814 than our reload. If so, we must allocate a register to this
6815 reload now, since that reload might inherit a previous reload
6816 and take the only available register in our class. Don't do this
6817 for optional reloads since they will force all previous reloads
6818 to be allocated. Also don't do this for reloads that have been
6821 for (i = j + 1; i < n_reloads; i++)
6823 int s = reload_order[i];
6825 if ((rld[s].in == 0 && rld[s].out == 0
6826 && ! rld[s].secondary_p)
6830 if ((rld[s].rclass != rld[r].rclass
6831 && reg_classes_intersect_p (rld[r].rclass,
6833 || rld[s].nregs < rld[r].nregs)
6840 allocate_reload_reg (chain, r, j == n_reloads - 1);
6844 /* Now allocate reload registers for anything non-optional that
6845 didn't get one yet. */
6846 for (j = 0; j < n_reloads; j++)
6848 int r = reload_order[j];
6850 /* Ignore reloads that got marked inoperative. */
6851 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6854 /* Skip reloads that already have a register allocated or are
6856 if (rld[r].reg_rtx != 0 || rld[r].optional)
6859 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6863 /* If that loop got all the way, we have won. */
6870 /* Loop around and try without any inheritance. */
6875 /* First undo everything done by the failed attempt
6876 to allocate with inheritance. */
6877 choose_reload_regs_init (chain, save_reload_reg_rtx);
6879 /* Some sanity tests to verify that the reloads found in the first
6880 pass are identical to the ones we have now. */
6881 gcc_assert (chain->n_reloads == n_reloads);
6883 for (i = 0; i < n_reloads; i++)
6885 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6887 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6888 for (j = 0; j < n_spills; j++)
6889 if (spill_regs[j] == chain->rld[i].regno)
6890 if (! set_reload_reg (j, i))
6891 failed_reload (chain->insn, i);
6895 /* If we thought we could inherit a reload, because it seemed that
6896 nothing else wanted the same reload register earlier in the insn,
6897 verify that assumption, now that all reloads have been assigned.
6898 Likewise for reloads where reload_override_in has been set. */
6900 /* If doing expensive optimizations, do one preliminary pass that doesn't
6901 cancel any inheritance, but removes reloads that have been needed only
6902 for reloads that we know can be inherited. */
6903 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6905 for (j = 0; j < n_reloads; j++)
6907 int r = reload_order[j];
6909 if (reload_inherited[r] && rld[r].reg_rtx)
6910 check_reg = rld[r].reg_rtx;
6911 else if (reload_override_in[r]
6912 && (REG_P (reload_override_in[r])
6913 || GET_CODE (reload_override_in[r]) == SUBREG))
6914 check_reg = reload_override_in[r];
6917 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6918 rld[r].opnum, rld[r].when_needed, rld[r].in,
6919 (reload_inherited[r]
6920 ? rld[r].out : const0_rtx),
6925 reload_inherited[r] = 0;
6926 reload_override_in[r] = 0;
6928 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6929 reload_override_in, then we do not need its related
6930 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6931 likewise for other reload types.
6932 We handle this by removing a reload when its only replacement
6933 is mentioned in reload_in of the reload we are going to inherit.
6934 A special case are auto_inc expressions; even if the input is
6935 inherited, we still need the address for the output. We can
6936 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6937 If we succeeded removing some reload and we are doing a preliminary
6938 pass just to remove such reloads, make another pass, since the
6939 removal of one reload might allow us to inherit another one. */
6941 && rld[r].out != rld[r].in
6942 && remove_address_replacements (rld[r].in) && pass)
6947 /* Now that reload_override_in is known valid,
6948 actually override reload_in. */
6949 for (j = 0; j < n_reloads; j++)
6950 if (reload_override_in[j])
6951 rld[j].in = reload_override_in[j];
6953 /* If this reload won't be done because it has been canceled or is
6954 optional and not inherited, clear reload_reg_rtx so other
6955 routines (such as subst_reloads) don't get confused. */
6956 for (j = 0; j < n_reloads; j++)
6957 if (rld[j].reg_rtx != 0
6958 && ((rld[j].optional && ! reload_inherited[j])
6959 || (rld[j].in == 0 && rld[j].out == 0
6960 && ! rld[j].secondary_p)))
6962 int regno = true_regnum (rld[j].reg_rtx);
6964 if (spill_reg_order[regno] >= 0)
6965 clear_reload_reg_in_use (regno, rld[j].opnum,
6966 rld[j].when_needed, rld[j].mode);
6968 reload_spill_index[j] = -1;
6971 /* Record which pseudos and which spill regs have output reloads. */
6972 for (j = 0; j < n_reloads; j++)
6974 int r = reload_order[j];
6976 i = reload_spill_index[r];
6978 /* I is nonneg if this reload uses a register.
6979 If rld[r].reg_rtx is 0, this is an optional reload
6980 that we opted to ignore. */
6981 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6982 && rld[r].reg_rtx != 0)
6984 int nregno = REGNO (rld[r].out_reg);
6987 if (nregno < FIRST_PSEUDO_REGISTER)
6988 nr = hard_regno_nregs[nregno][rld[r].mode];
6991 SET_REGNO_REG_SET (®_has_output_reload,
6995 add_to_hard_reg_set (®_is_output_reload, rld[r].mode, i);
6997 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6998 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6999 || rld[r].when_needed == RELOAD_FOR_INSN);
7004 /* Deallocate the reload register for reload R. This is called from
7005 remove_address_replacements. */
7008 deallocate_reload_reg (int r)
7012 if (! rld[r].reg_rtx)
7014 regno = true_regnum (rld[r].reg_rtx);
7016 if (spill_reg_order[regno] >= 0)
7017 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
7019 reload_spill_index[r] = -1;
7022 /* These arrays are filled by emit_reload_insns and its subroutines. */
7023 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
7024 static rtx other_input_address_reload_insns = 0;
7025 static rtx other_input_reload_insns = 0;
7026 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
7027 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7028 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
7029 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
7030 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7031 static rtx operand_reload_insns = 0;
7032 static rtx other_operand_reload_insns = 0;
7033 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
7035 /* Values to be put in spill_reg_store are put here first. */
7036 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
7037 static HARD_REG_SET reg_reloaded_died;
7039 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7040 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7041 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7042 adjusted register, and return true. Otherwise, return false. */
7044 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
7045 enum reg_class new_class,
7046 enum machine_mode new_mode)
7051 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
7053 unsigned regno = REGNO (reg);
7055 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
7057 if (GET_MODE (reg) != new_mode)
7059 if (!HARD_REGNO_MODE_OK (regno, new_mode))
7061 if (hard_regno_nregs[regno][new_mode]
7062 > hard_regno_nregs[regno][GET_MODE (reg)])
7064 reg = reload_adjust_reg_for_mode (reg, new_mode);
7072 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7073 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7074 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7075 adjusted register, and return true. Otherwise, return false. */
7077 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
7078 enum insn_code icode)
7081 enum reg_class new_class = scratch_reload_class (icode);
7082 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
7084 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
7085 new_class, new_mode);
7088 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7089 has the number J. OLD contains the value to be used as input. */
7092 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
7095 rtx insn = chain->insn;
7097 rtx oldequiv_reg = 0;
7100 enum machine_mode mode;
7103 /* delete_output_reload is only invoked properly if old contains
7104 the original pseudo register. Since this is replaced with a
7105 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7106 find the pseudo in RELOAD_IN_REG. */
7107 if (reload_override_in[j]
7108 && REG_P (rl->in_reg))
7115 else if (REG_P (oldequiv))
7116 oldequiv_reg = oldequiv;
7117 else if (GET_CODE (oldequiv) == SUBREG)
7118 oldequiv_reg = SUBREG_REG (oldequiv);
7120 reloadreg = reload_reg_rtx_for_input[j];
7121 mode = GET_MODE (reloadreg);
7123 /* If we are reloading from a register that was recently stored in
7124 with an output-reload, see if we can prove there was
7125 actually no need to store the old value in it. */
7127 if (optimize && REG_P (oldequiv)
7128 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
7129 && spill_reg_store[REGNO (oldequiv)]
7131 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
7132 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
7134 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
7136 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7139 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
7140 oldequiv = SUBREG_REG (oldequiv);
7141 if (GET_MODE (oldequiv) != VOIDmode
7142 && mode != GET_MODE (oldequiv))
7143 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
7145 /* Switch to the right place to emit the reload insns. */
7146 switch (rl->when_needed)
7149 where = &other_input_reload_insns;
7151 case RELOAD_FOR_INPUT:
7152 where = &input_reload_insns[rl->opnum];
7154 case RELOAD_FOR_INPUT_ADDRESS:
7155 where = &input_address_reload_insns[rl->opnum];
7157 case RELOAD_FOR_INPADDR_ADDRESS:
7158 where = &inpaddr_address_reload_insns[rl->opnum];
7160 case RELOAD_FOR_OUTPUT_ADDRESS:
7161 where = &output_address_reload_insns[rl->opnum];
7163 case RELOAD_FOR_OUTADDR_ADDRESS:
7164 where = &outaddr_address_reload_insns[rl->opnum];
7166 case RELOAD_FOR_OPERAND_ADDRESS:
7167 where = &operand_reload_insns;
7169 case RELOAD_FOR_OPADDR_ADDR:
7170 where = &other_operand_reload_insns;
7172 case RELOAD_FOR_OTHER_ADDRESS:
7173 where = &other_input_address_reload_insns;
7179 push_to_sequence (*where);
7181 /* Auto-increment addresses must be reloaded in a special way. */
7182 if (rl->out && ! rl->out_reg)
7184 /* We are not going to bother supporting the case where a
7185 incremented register can't be copied directly from
7186 OLDEQUIV since this seems highly unlikely. */
7187 gcc_assert (rl->secondary_in_reload < 0);
7189 if (reload_inherited[j])
7190 oldequiv = reloadreg;
7192 old = XEXP (rl->in_reg, 0);
7194 /* Prevent normal processing of this reload. */
7196 /* Output a special code sequence for this case, and forget about
7197 spill reg information. */
7198 new_spill_reg_store[REGNO (reloadreg)] = NULL;
7199 inc_for_reload (reloadreg, oldequiv, rl->out, rl->inc);
7202 /* If we are reloading a pseudo-register that was set by the previous
7203 insn, see if we can get rid of that pseudo-register entirely
7204 by redirecting the previous insn into our reload register. */
7206 else if (optimize && REG_P (old)
7207 && REGNO (old) >= FIRST_PSEUDO_REGISTER
7208 && dead_or_set_p (insn, old)
7209 /* This is unsafe if some other reload
7210 uses the same reg first. */
7211 && ! conflicts_with_override (reloadreg)
7212 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
7213 rl->when_needed, old, rl->out, j, 0))
7215 rtx temp = PREV_INSN (insn);
7216 while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp)))
7217 temp = PREV_INSN (temp);
7219 && NONJUMP_INSN_P (temp)
7220 && GET_CODE (PATTERN (temp)) == SET
7221 && SET_DEST (PATTERN (temp)) == old
7222 /* Make sure we can access insn_operand_constraint. */
7223 && asm_noperands (PATTERN (temp)) < 0
7224 /* This is unsafe if operand occurs more than once in current
7225 insn. Perhaps some occurrences aren't reloaded. */
7226 && count_occurrences (PATTERN (insn), old, 0) == 1)
7228 rtx old = SET_DEST (PATTERN (temp));
7229 /* Store into the reload register instead of the pseudo. */
7230 SET_DEST (PATTERN (temp)) = reloadreg;
7232 /* Verify that resulting insn is valid. */
7233 extract_insn (temp);
7234 if (constrain_operands (1))
7236 /* If the previous insn is an output reload, the source is
7237 a reload register, and its spill_reg_store entry will
7238 contain the previous destination. This is now
7240 if (REG_P (SET_SRC (PATTERN (temp)))
7241 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
7243 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7244 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7247 /* If these are the only uses of the pseudo reg,
7248 pretend for GDB it lives in the reload reg we used. */
7249 if (REG_N_DEATHS (REGNO (old)) == 1
7250 && REG_N_SETS (REGNO (old)) == 1)
7252 reg_renumber[REGNO (old)] = REGNO (reloadreg);
7253 if (ira_conflicts_p)
7254 /* Inform IRA about the change. */
7255 ira_mark_allocation_change (REGNO (old));
7256 alter_reg (REGNO (old), -1, false);
7260 /* Adjust any debug insns between temp and insn. */
7261 while ((temp = NEXT_INSN (temp)) != insn)
7262 if (DEBUG_INSN_P (temp))
7263 replace_rtx (PATTERN (temp), old, reloadreg);
7265 gcc_assert (NOTE_P (temp));
7269 SET_DEST (PATTERN (temp)) = old;
7274 /* We can't do that, so output an insn to load RELOADREG. */
7276 /* If we have a secondary reload, pick up the secondary register
7277 and icode, if any. If OLDEQUIV and OLD are different or
7278 if this is an in-out reload, recompute whether or not we
7279 still need a secondary register and what the icode should
7280 be. If we still need a secondary register and the class or
7281 icode is different, go back to reloading from OLD if using
7282 OLDEQUIV means that we got the wrong type of register. We
7283 cannot have different class or icode due to an in-out reload
7284 because we don't make such reloads when both the input and
7285 output need secondary reload registers. */
7287 if (! special && rl->secondary_in_reload >= 0)
7289 rtx second_reload_reg = 0;
7290 rtx third_reload_reg = 0;
7291 int secondary_reload = rl->secondary_in_reload;
7292 rtx real_oldequiv = oldequiv;
7295 enum insn_code icode;
7296 enum insn_code tertiary_icode = CODE_FOR_nothing;
7298 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7299 and similarly for OLD.
7300 See comments in get_secondary_reload in reload.c. */
7301 /* If it is a pseudo that cannot be replaced with its
7302 equivalent MEM, we must fall back to reload_in, which
7303 will have all the necessary substitutions registered.
7304 Likewise for a pseudo that can't be replaced with its
7305 equivalent constant.
7307 Take extra care for subregs of such pseudos. Note that
7308 we cannot use reg_equiv_mem in this case because it is
7309 not in the right mode. */
7312 if (GET_CODE (tmp) == SUBREG)
7313 tmp = SUBREG_REG (tmp);
7315 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7316 && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7317 || reg_equiv_constant (REGNO (tmp)) != 0))
7319 if (! reg_equiv_mem (REGNO (tmp))
7320 || num_not_at_initial_offset
7321 || GET_CODE (oldequiv) == SUBREG)
7322 real_oldequiv = rl->in;
7324 real_oldequiv = reg_equiv_mem (REGNO (tmp));
7328 if (GET_CODE (tmp) == SUBREG)
7329 tmp = SUBREG_REG (tmp);
7331 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7332 && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7333 || reg_equiv_constant (REGNO (tmp)) != 0))
7335 if (! reg_equiv_mem (REGNO (tmp))
7336 || num_not_at_initial_offset
7337 || GET_CODE (old) == SUBREG)
7340 real_old = reg_equiv_mem (REGNO (tmp));
7343 second_reload_reg = rld[secondary_reload].reg_rtx;
7344 if (rld[secondary_reload].secondary_in_reload >= 0)
7346 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7348 third_reload_reg = rld[tertiary_reload].reg_rtx;
7349 tertiary_icode = rld[secondary_reload].secondary_in_icode;
7350 /* We'd have to add more code for quartary reloads. */
7351 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7353 icode = rl->secondary_in_icode;
7355 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7356 || (rl->in != 0 && rl->out != 0))
7358 secondary_reload_info sri, sri2;
7359 enum reg_class new_class, new_t_class;
7361 sri.icode = CODE_FOR_nothing;
7362 sri.prev_sri = NULL;
7364 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7368 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7369 second_reload_reg = 0;
7370 else if (new_class == NO_REGS)
7372 if (reload_adjust_reg_for_icode (&second_reload_reg,
7374 (enum insn_code) sri.icode))
7376 icode = (enum insn_code) sri.icode;
7377 third_reload_reg = 0;
7382 real_oldequiv = real_old;
7385 else if (sri.icode != CODE_FOR_nothing)
7386 /* We currently lack a way to express this in reloads. */
7390 sri2.icode = CODE_FOR_nothing;
7391 sri2.prev_sri = &sri;
7393 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7396 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7398 if (reload_adjust_reg_for_temp (&second_reload_reg,
7402 third_reload_reg = 0;
7403 tertiary_icode = (enum insn_code) sri2.icode;
7408 real_oldequiv = real_old;
7411 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7413 rtx intermediate = second_reload_reg;
7415 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7417 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7421 second_reload_reg = intermediate;
7422 tertiary_icode = (enum insn_code) sri2.icode;
7427 real_oldequiv = real_old;
7430 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7432 rtx intermediate = second_reload_reg;
7434 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7436 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7439 second_reload_reg = intermediate;
7440 tertiary_icode = (enum insn_code) sri2.icode;
7445 real_oldequiv = real_old;
7450 /* This could be handled more intelligently too. */
7452 real_oldequiv = real_old;
7457 /* If we still need a secondary reload register, check
7458 to see if it is being used as a scratch or intermediate
7459 register and generate code appropriately. If we need
7460 a scratch register, use REAL_OLDEQUIV since the form of
7461 the insn may depend on the actual address if it is
7464 if (second_reload_reg)
7466 if (icode != CODE_FOR_nothing)
7468 /* We'd have to add extra code to handle this case. */
7469 gcc_assert (!third_reload_reg);
7471 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7472 second_reload_reg));
7477 /* See if we need a scratch register to load the
7478 intermediate register (a tertiary reload). */
7479 if (tertiary_icode != CODE_FOR_nothing)
7481 emit_insn ((GEN_FCN (tertiary_icode)
7482 (second_reload_reg, real_oldequiv,
7483 third_reload_reg)));
7485 else if (third_reload_reg)
7487 gen_reload (third_reload_reg, real_oldequiv,
7490 gen_reload (second_reload_reg, third_reload_reg,
7495 gen_reload (second_reload_reg, real_oldequiv,
7499 oldequiv = second_reload_reg;
7504 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7506 rtx real_oldequiv = oldequiv;
7508 if ((REG_P (oldequiv)
7509 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7510 && (reg_equiv_memory_loc (REGNO (oldequiv)) != 0
7511 || reg_equiv_constant (REGNO (oldequiv)) != 0))
7512 || (GET_CODE (oldequiv) == SUBREG
7513 && REG_P (SUBREG_REG (oldequiv))
7514 && (REGNO (SUBREG_REG (oldequiv))
7515 >= FIRST_PSEUDO_REGISTER)
7516 && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv))) != 0)
7517 || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv))) != 0)))
7518 || (CONSTANT_P (oldequiv)
7519 && (targetm.preferred_reload_class (oldequiv,
7520 REGNO_REG_CLASS (REGNO (reloadreg)))
7522 real_oldequiv = rl->in;
7523 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7527 if (cfun->can_throw_non_call_exceptions)
7528 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7530 /* End this sequence. */
7531 *where = get_insns ();
7534 /* Update reload_override_in so that delete_address_reloads_1
7535 can see the actual register usage. */
7537 reload_override_in[j] = oldequiv;
7540 /* Generate insns to for the output reload RL, which is for the insn described
7541 by CHAIN and has the number J. */
7543 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7547 rtx insn = chain->insn;
7550 enum machine_mode mode;
7554 if (rl->when_needed == RELOAD_OTHER)
7557 push_to_sequence (output_reload_insns[rl->opnum]);
7559 rl_reg_rtx = reload_reg_rtx_for_output[j];
7560 mode = GET_MODE (rl_reg_rtx);
7562 reloadreg = rl_reg_rtx;
7564 /* If we need two reload regs, set RELOADREG to the intermediate
7565 one, since it will be stored into OLD. We might need a secondary
7566 register only for an input reload, so check again here. */
7568 if (rl->secondary_out_reload >= 0)
7571 int secondary_reload = rl->secondary_out_reload;
7572 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7574 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7575 && reg_equiv_mem (REGNO (old)) != 0)
7576 real_old = reg_equiv_mem (REGNO (old));
7578 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7580 rtx second_reloadreg = reloadreg;
7581 reloadreg = rld[secondary_reload].reg_rtx;
7583 /* See if RELOADREG is to be used as a scratch register
7584 or as an intermediate register. */
7585 if (rl->secondary_out_icode != CODE_FOR_nothing)
7587 /* We'd have to add extra code to handle this case. */
7588 gcc_assert (tertiary_reload < 0);
7590 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7591 (real_old, second_reloadreg, reloadreg)));
7596 /* See if we need both a scratch and intermediate reload
7599 enum insn_code tertiary_icode
7600 = rld[secondary_reload].secondary_out_icode;
7602 /* We'd have to add more code for quartary reloads. */
7603 gcc_assert (tertiary_reload < 0
7604 || rld[tertiary_reload].secondary_out_reload < 0);
7606 if (GET_MODE (reloadreg) != mode)
7607 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7609 if (tertiary_icode != CODE_FOR_nothing)
7611 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7613 /* Copy primary reload reg to secondary reload reg.
7614 (Note that these have been swapped above, then
7615 secondary reload reg to OLD using our insn.) */
7617 /* If REAL_OLD is a paradoxical SUBREG, remove it
7618 and try to put the opposite SUBREG on
7620 strip_paradoxical_subreg (&real_old, &reloadreg);
7622 gen_reload (reloadreg, second_reloadreg,
7623 rl->opnum, rl->when_needed);
7624 emit_insn ((GEN_FCN (tertiary_icode)
7625 (real_old, reloadreg, third_reloadreg)));
7631 /* Copy between the reload regs here and then to
7634 gen_reload (reloadreg, second_reloadreg,
7635 rl->opnum, rl->when_needed);
7636 if (tertiary_reload >= 0)
7638 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7640 gen_reload (third_reloadreg, reloadreg,
7641 rl->opnum, rl->when_needed);
7642 reloadreg = third_reloadreg;
7649 /* Output the last reload insn. */
7654 /* Don't output the last reload if OLD is not the dest of
7655 INSN and is in the src and is clobbered by INSN. */
7656 if (! flag_expensive_optimizations
7658 || !(set = single_set (insn))
7659 || rtx_equal_p (old, SET_DEST (set))
7660 || !reg_mentioned_p (old, SET_SRC (set))
7661 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7662 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7663 gen_reload (old, reloadreg, rl->opnum,
7667 /* Look at all insns we emitted, just to be safe. */
7668 for (p = get_insns (); p; p = NEXT_INSN (p))
7671 rtx pat = PATTERN (p);
7673 /* If this output reload doesn't come from a spill reg,
7674 clear any memory of reloaded copies of the pseudo reg.
7675 If this output reload comes from a spill reg,
7676 reg_has_output_reload will make this do nothing. */
7677 note_stores (pat, forget_old_reloads_1, NULL);
7679 if (reg_mentioned_p (rl_reg_rtx, pat))
7681 rtx set = single_set (insn);
7682 if (reload_spill_index[j] < 0
7684 && SET_SRC (set) == rl_reg_rtx)
7686 int src = REGNO (SET_SRC (set));
7688 reload_spill_index[j] = src;
7689 SET_HARD_REG_BIT (reg_is_output_reload, src);
7690 if (find_regno_note (insn, REG_DEAD, src))
7691 SET_HARD_REG_BIT (reg_reloaded_died, src);
7693 if (HARD_REGISTER_P (rl_reg_rtx))
7695 int s = rl->secondary_out_reload;
7696 set = single_set (p);
7697 /* If this reload copies only to the secondary reload
7698 register, the secondary reload does the actual
7700 if (s >= 0 && set == NULL_RTX)
7701 /* We can't tell what function the secondary reload
7702 has and where the actual store to the pseudo is
7703 made; leave new_spill_reg_store alone. */
7706 && SET_SRC (set) == rl_reg_rtx
7707 && SET_DEST (set) == rld[s].reg_rtx)
7709 /* Usually the next instruction will be the
7710 secondary reload insn; if we can confirm
7711 that it is, setting new_spill_reg_store to
7712 that insn will allow an extra optimization. */
7713 rtx s_reg = rld[s].reg_rtx;
7714 rtx next = NEXT_INSN (p);
7715 rld[s].out = rl->out;
7716 rld[s].out_reg = rl->out_reg;
7717 set = single_set (next);
7718 if (set && SET_SRC (set) == s_reg
7719 && ! new_spill_reg_store[REGNO (s_reg)])
7721 SET_HARD_REG_BIT (reg_is_output_reload,
7723 new_spill_reg_store[REGNO (s_reg)] = next;
7727 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7732 if (rl->when_needed == RELOAD_OTHER)
7734 emit_insn (other_output_reload_insns[rl->opnum]);
7735 other_output_reload_insns[rl->opnum] = get_insns ();
7738 output_reload_insns[rl->opnum] = get_insns ();
7740 if (cfun->can_throw_non_call_exceptions)
7741 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7746 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7747 and has the number J. */
7749 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7751 rtx insn = chain->insn;
7752 rtx old = (rl->in && MEM_P (rl->in)
7753 ? rl->in_reg : rl->in);
7754 rtx reg_rtx = rl->reg_rtx;
7758 enum machine_mode mode;
7760 /* Determine the mode to reload in.
7761 This is very tricky because we have three to choose from.
7762 There is the mode the insn operand wants (rl->inmode).
7763 There is the mode of the reload register RELOADREG.
7764 There is the intrinsic mode of the operand, which we could find
7765 by stripping some SUBREGs.
7766 It turns out that RELOADREG's mode is irrelevant:
7767 we can change that arbitrarily.
7769 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7770 then the reload reg may not support QImode moves, so use SImode.
7771 If foo is in memory due to spilling a pseudo reg, this is safe,
7772 because the QImode value is in the least significant part of a
7773 slot big enough for a SImode. If foo is some other sort of
7774 memory reference, then it is impossible to reload this case,
7775 so previous passes had better make sure this never happens.
7777 Then consider a one-word union which has SImode and one of its
7778 members is a float, being fetched as (SUBREG:SF union:SI).
7779 We must fetch that as SFmode because we could be loading into
7780 a float-only register. In this case OLD's mode is correct.
7782 Consider an immediate integer: it has VOIDmode. Here we need
7783 to get a mode from something else.
7785 In some cases, there is a fourth mode, the operand's
7786 containing mode. If the insn specifies a containing mode for
7787 this operand, it overrides all others.
7789 I am not sure whether the algorithm here is always right,
7790 but it does the right things in those cases. */
7792 mode = GET_MODE (old);
7793 if (mode == VOIDmode)
7796 /* We cannot use gen_lowpart_common since it can do the wrong thing
7797 when REG_RTX has a multi-word mode. Note that REG_RTX must
7798 always be a REG here. */
7799 if (GET_MODE (reg_rtx) != mode)
7800 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7802 reload_reg_rtx_for_input[j] = reg_rtx;
7805 /* AUTO_INC reloads need to be handled even if inherited. We got an
7806 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7807 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7808 && ! rtx_equal_p (reg_rtx, old)
7810 emit_input_reload_insns (chain, rld + j, old, j);
7812 /* When inheriting a wider reload, we have a MEM in rl->in,
7813 e.g. inheriting a SImode output reload for
7814 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7815 if (optimize && reload_inherited[j] && rl->in
7817 && MEM_P (rl->in_reg)
7818 && reload_spill_index[j] >= 0
7819 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7820 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7822 /* If we are reloading a register that was recently stored in with an
7823 output-reload, see if we can prove there was
7824 actually no need to store the old value in it. */
7827 && (reload_inherited[j] || reload_override_in[j])
7830 && spill_reg_store[REGNO (reg_rtx)] != 0
7832 /* There doesn't seem to be any reason to restrict this to pseudos
7833 and doing so loses in the case where we are copying from a
7834 register of the wrong class. */
7835 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7837 /* The insn might have already some references to stackslots
7838 replaced by MEMs, while reload_out_reg still names the
7840 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7841 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7842 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7845 /* Do output reloading for reload RL, which is for the insn described by
7846 CHAIN and has the number J.
7847 ??? At some point we need to support handling output reloads of
7848 JUMP_INSNs or insns that set cc0. */
7850 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7853 rtx insn = chain->insn;
7854 /* If this is an output reload that stores something that is
7855 not loaded in this same reload, see if we can eliminate a previous
7857 rtx pseudo = rl->out_reg;
7858 rtx reg_rtx = rl->reg_rtx;
7860 if (rl->out && reg_rtx)
7862 enum machine_mode mode;
7864 /* Determine the mode to reload in.
7865 See comments above (for input reloading). */
7866 mode = GET_MODE (rl->out);
7867 if (mode == VOIDmode)
7869 /* VOIDmode should never happen for an output. */
7870 if (asm_noperands (PATTERN (insn)) < 0)
7871 /* It's the compiler's fault. */
7872 fatal_insn ("VOIDmode on an output", insn);
7873 error_for_asm (insn, "output operand is constant in %<asm%>");
7874 /* Prevent crash--use something we know is valid. */
7876 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7878 if (GET_MODE (reg_rtx) != mode)
7879 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7881 reload_reg_rtx_for_output[j] = reg_rtx;
7886 && ! rtx_equal_p (rl->in_reg, pseudo)
7887 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7888 && reg_last_reload_reg[REGNO (pseudo)])
7890 int pseudo_no = REGNO (pseudo);
7891 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7893 /* We don't need to test full validity of last_regno for
7894 inherit here; we only want to know if the store actually
7895 matches the pseudo. */
7896 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7897 && reg_reloaded_contents[last_regno] == pseudo_no
7898 && spill_reg_store[last_regno]
7899 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7900 delete_output_reload (insn, j, last_regno, reg_rtx);
7906 || rtx_equal_p (old, reg_rtx))
7909 /* An output operand that dies right away does need a reload,
7910 but need not be copied from it. Show the new location in the
7912 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7913 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7915 XEXP (note, 0) = reg_rtx;
7918 /* Likewise for a SUBREG of an operand that dies. */
7919 else if (GET_CODE (old) == SUBREG
7920 && REG_P (SUBREG_REG (old))
7921 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7924 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7927 else if (GET_CODE (old) == SCRATCH)
7928 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7929 but we don't want to make an output reload. */
7932 /* If is a JUMP_INSN, we can't support output reloads yet. */
7933 gcc_assert (NONJUMP_INSN_P (insn));
7935 emit_output_reload_insns (chain, rld + j, j);
7938 /* A reload copies values of MODE from register SRC to register DEST.
7939 Return true if it can be treated for inheritance purposes like a
7940 group of reloads, each one reloading a single hard register. The
7941 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7942 occupy the same number of hard registers. */
7945 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
7946 int src ATTRIBUTE_UNUSED,
7947 enum machine_mode mode ATTRIBUTE_UNUSED)
7949 #ifdef CANNOT_CHANGE_MODE_CLASS
7950 return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
7951 && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
7957 /* Output insns to reload values in and out of the chosen reload regs. */
7960 emit_reload_insns (struct insn_chain *chain)
7962 rtx insn = chain->insn;
7966 CLEAR_HARD_REG_SET (reg_reloaded_died);
7968 for (j = 0; j < reload_n_operands; j++)
7969 input_reload_insns[j] = input_address_reload_insns[j]
7970 = inpaddr_address_reload_insns[j]
7971 = output_reload_insns[j] = output_address_reload_insns[j]
7972 = outaddr_address_reload_insns[j]
7973 = other_output_reload_insns[j] = 0;
7974 other_input_address_reload_insns = 0;
7975 other_input_reload_insns = 0;
7976 operand_reload_insns = 0;
7977 other_operand_reload_insns = 0;
7979 /* Dump reloads into the dump file. */
7982 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7983 debug_reload_to_stream (dump_file);
7986 /* Now output the instructions to copy the data into and out of the
7987 reload registers. Do these in the order that the reloads were reported,
7988 since reloads of base and index registers precede reloads of operands
7989 and the operands may need the base and index registers reloaded. */
7991 for (j = 0; j < n_reloads; j++)
7993 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
7997 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
7998 new_spill_reg_store[i] = 0;
8001 do_input_reload (chain, rld + j, j);
8002 do_output_reload (chain, rld + j, j);
8005 /* Now write all the insns we made for reloads in the order expected by
8006 the allocation functions. Prior to the insn being reloaded, we write
8007 the following reloads:
8009 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8011 RELOAD_OTHER reloads.
8013 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8014 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8015 RELOAD_FOR_INPUT reload for the operand.
8017 RELOAD_FOR_OPADDR_ADDRS reloads.
8019 RELOAD_FOR_OPERAND_ADDRESS reloads.
8021 After the insn being reloaded, we write the following:
8023 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8024 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8025 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8026 reloads for the operand. The RELOAD_OTHER output reloads are
8027 output in descending order by reload number. */
8029 emit_insn_before (other_input_address_reload_insns, insn);
8030 emit_insn_before (other_input_reload_insns, insn);
8032 for (j = 0; j < reload_n_operands; j++)
8034 emit_insn_before (inpaddr_address_reload_insns[j], insn);
8035 emit_insn_before (input_address_reload_insns[j], insn);
8036 emit_insn_before (input_reload_insns[j], insn);
8039 emit_insn_before (other_operand_reload_insns, insn);
8040 emit_insn_before (operand_reload_insns, insn);
8042 for (j = 0; j < reload_n_operands; j++)
8044 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
8045 x = emit_insn_after (output_address_reload_insns[j], x);
8046 x = emit_insn_after (output_reload_insns[j], x);
8047 emit_insn_after (other_output_reload_insns[j], x);
8050 /* For all the spill regs newly reloaded in this instruction,
8051 record what they were reloaded from, so subsequent instructions
8052 can inherit the reloads.
8054 Update spill_reg_store for the reloads of this insn.
8055 Copy the elements that were updated in the loop above. */
8057 for (j = 0; j < n_reloads; j++)
8059 int r = reload_order[j];
8060 int i = reload_spill_index[r];
8062 /* If this is a non-inherited input reload from a pseudo, we must
8063 clear any memory of a previous store to the same pseudo. Only do
8064 something if there will not be an output reload for the pseudo
8066 if (rld[r].in_reg != 0
8067 && ! (reload_inherited[r] || reload_override_in[r]))
8069 rtx reg = rld[r].in_reg;
8071 if (GET_CODE (reg) == SUBREG)
8072 reg = SUBREG_REG (reg);
8075 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
8076 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
8078 int nregno = REGNO (reg);
8080 if (reg_last_reload_reg[nregno])
8082 int last_regno = REGNO (reg_last_reload_reg[nregno]);
8084 if (reg_reloaded_contents[last_regno] == nregno)
8085 spill_reg_store[last_regno] = 0;
8090 /* I is nonneg if this reload used a register.
8091 If rld[r].reg_rtx is 0, this is an optional reload
8092 that we opted to ignore. */
8094 if (i >= 0 && rld[r].reg_rtx != 0)
8096 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
8099 /* For a multi register reload, we need to check if all or part
8100 of the value lives to the end. */
8101 for (k = 0; k < nr; k++)
8102 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
8103 rld[r].when_needed))
8104 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
8106 /* Maybe the spill reg contains a copy of reload_out. */
8108 && (REG_P (rld[r].out)
8110 ? REG_P (rld[r].out_reg)
8111 /* The reload value is an auto-modification of
8112 some kind. For PRE_INC, POST_INC, PRE_DEC
8113 and POST_DEC, we record an equivalence
8114 between the reload register and the operand
8115 on the optimistic assumption that we can make
8116 the equivalence hold. reload_as_needed must
8117 then either make it hold or invalidate the
8120 PRE_MODIFY and POST_MODIFY addresses are reloaded
8121 somewhat differently, and allowing them here leads
8123 : (GET_CODE (rld[r].out) != POST_MODIFY
8124 && GET_CODE (rld[r].out) != PRE_MODIFY))))
8127 enum machine_mode mode;
8130 reg = reload_reg_rtx_for_output[r];
8131 mode = GET_MODE (reg);
8132 regno = REGNO (reg);
8133 nregs = hard_regno_nregs[regno][mode];
8134 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
8135 rld[r].when_needed))
8137 rtx out = (REG_P (rld[r].out)
8141 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
8142 int out_regno = REGNO (out);
8143 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
8144 : hard_regno_nregs[out_regno][mode]);
8147 spill_reg_store[regno] = new_spill_reg_store[regno];
8148 spill_reg_stored_to[regno] = out;
8149 reg_last_reload_reg[out_regno] = reg;
8151 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
8152 && nregs == out_nregs
8153 && inherit_piecemeal_p (out_regno, regno, mode));
8155 /* If OUT_REGNO is a hard register, it may occupy more than
8156 one register. If it does, say what is in the
8157 rest of the registers assuming that both registers
8158 agree on how many words the object takes. If not,
8159 invalidate the subsequent registers. */
8161 if (HARD_REGISTER_NUM_P (out_regno))
8162 for (k = 1; k < out_nregs; k++)
8163 reg_last_reload_reg[out_regno + k]
8164 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8166 /* Now do the inverse operation. */
8167 for (k = 0; k < nregs; k++)
8169 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8170 reg_reloaded_contents[regno + k]
8171 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
8174 reg_reloaded_insn[regno + k] = insn;
8175 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8176 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8177 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8180 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8185 /* Maybe the spill reg contains a copy of reload_in. Only do
8186 something if there will not be an output reload for
8187 the register being reloaded. */
8188 else if (rld[r].out_reg == 0
8190 && ((REG_P (rld[r].in)
8191 && !HARD_REGISTER_P (rld[r].in)
8192 && !REGNO_REG_SET_P (®_has_output_reload,
8194 || (REG_P (rld[r].in_reg)
8195 && !REGNO_REG_SET_P (®_has_output_reload,
8196 REGNO (rld[r].in_reg))))
8197 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
8200 enum machine_mode mode;
8203 reg = reload_reg_rtx_for_input[r];
8204 mode = GET_MODE (reg);
8205 regno = REGNO (reg);
8206 nregs = hard_regno_nregs[regno][mode];
8207 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
8208 rld[r].when_needed))
8215 if (REG_P (rld[r].in)
8216 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
8218 else if (REG_P (rld[r].in_reg))
8221 in = XEXP (rld[r].in_reg, 0);
8222 in_regno = REGNO (in);
8224 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
8225 : hard_regno_nregs[in_regno][mode]);
8227 reg_last_reload_reg[in_regno] = reg;
8229 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
8230 && nregs == in_nregs
8231 && inherit_piecemeal_p (regno, in_regno, mode));
8233 if (HARD_REGISTER_NUM_P (in_regno))
8234 for (k = 1; k < in_nregs; k++)
8235 reg_last_reload_reg[in_regno + k]
8236 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8238 /* Unless we inherited this reload, show we haven't
8239 recently done a store.
8240 Previous stores of inherited auto_inc expressions
8241 also have to be discarded. */
8242 if (! reload_inherited[r]
8243 || (rld[r].out && ! rld[r].out_reg))
8244 spill_reg_store[regno] = 0;
8246 for (k = 0; k < nregs; k++)
8248 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8249 reg_reloaded_contents[regno + k]
8250 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
8253 reg_reloaded_insn[regno + k] = insn;
8254 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8255 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8256 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8259 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8266 /* The following if-statement was #if 0'd in 1.34 (or before...).
8267 It's reenabled in 1.35 because supposedly nothing else
8268 deals with this problem. */
8270 /* If a register gets output-reloaded from a non-spill register,
8271 that invalidates any previous reloaded copy of it.
8272 But forget_old_reloads_1 won't get to see it, because
8273 it thinks only about the original insn. So invalidate it here.
8274 Also do the same thing for RELOAD_OTHER constraints where the
8275 output is discarded. */
8277 && ((rld[r].out != 0
8278 && (REG_P (rld[r].out)
8279 || (MEM_P (rld[r].out)
8280 && REG_P (rld[r].out_reg))))
8281 || (rld[r].out == 0 && rld[r].out_reg
8282 && REG_P (rld[r].out_reg))))
8284 rtx out = ((rld[r].out && REG_P (rld[r].out))
8285 ? rld[r].out : rld[r].out_reg);
8286 int out_regno = REGNO (out);
8287 enum machine_mode mode = GET_MODE (out);
8289 /* REG_RTX is now set or clobbered by the main instruction.
8290 As the comment above explains, forget_old_reloads_1 only
8291 sees the original instruction, and there is no guarantee
8292 that the original instruction also clobbered REG_RTX.
8293 For example, if find_reloads sees that the input side of
8294 a matched operand pair dies in this instruction, it may
8295 use the input register as the reload register.
8297 Calling forget_old_reloads_1 is a waste of effort if
8298 REG_RTX is also the output register.
8300 If we know that REG_RTX holds the value of a pseudo
8301 register, the code after the call will record that fact. */
8302 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8303 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8305 if (!HARD_REGISTER_NUM_P (out_regno))
8307 rtx src_reg, store_insn = NULL_RTX;
8309 reg_last_reload_reg[out_regno] = 0;
8311 /* If we can find a hard register that is stored, record
8312 the storing insn so that we may delete this insn with
8313 delete_output_reload. */
8314 src_reg = reload_reg_rtx_for_output[r];
8316 /* If this is an optional reload, try to find the source reg
8317 from an input reload. */
8320 rtx set = single_set (insn);
8321 if (set && SET_DEST (set) == rld[r].out)
8325 src_reg = SET_SRC (set);
8327 for (k = 0; k < n_reloads; k++)
8329 if (rld[k].in == src_reg)
8331 src_reg = reload_reg_rtx_for_input[k];
8338 store_insn = new_spill_reg_store[REGNO (src_reg)];
8339 if (src_reg && REG_P (src_reg)
8340 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8342 int src_regno, src_nregs, k;
8345 gcc_assert (GET_MODE (src_reg) == mode);
8346 src_regno = REGNO (src_reg);
8347 src_nregs = hard_regno_nregs[src_regno][mode];
8348 /* The place where to find a death note varies with
8349 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8350 necessarily checked exactly in the code that moves
8351 notes, so just check both locations. */
8352 note = find_regno_note (insn, REG_DEAD, src_regno);
8353 if (! note && store_insn)
8354 note = find_regno_note (store_insn, REG_DEAD, src_regno);
8355 for (k = 0; k < src_nregs; k++)
8357 spill_reg_store[src_regno + k] = store_insn;
8358 spill_reg_stored_to[src_regno + k] = out;
8359 reg_reloaded_contents[src_regno + k] = out_regno;
8360 reg_reloaded_insn[src_regno + k] = store_insn;
8361 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8362 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8363 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
8365 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8368 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8370 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8372 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8374 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8376 reg_last_reload_reg[out_regno] = src_reg;
8377 /* We have to set reg_has_output_reload here, or else
8378 forget_old_reloads_1 will clear reg_last_reload_reg
8380 SET_REGNO_REG_SET (®_has_output_reload,
8386 int k, out_nregs = hard_regno_nregs[out_regno][mode];
8388 for (k = 0; k < out_nregs; k++)
8389 reg_last_reload_reg[out_regno + k] = 0;
8393 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8396 /* Go through the motions to emit INSN and test if it is strictly valid.
8397 Return the emitted insn if valid, else return NULL. */
8400 emit_insn_if_valid_for_reload (rtx insn)
8402 rtx last = get_last_insn ();
8405 insn = emit_insn (insn);
8406 code = recog_memoized (insn);
8410 extract_insn (insn);
8411 /* We want constrain operands to treat this insn strictly in its
8412 validity determination, i.e., the way it would after reload has
8414 if (constrain_operands (1))
8418 delete_insns_since (last);
8422 /* Emit code to perform a reload from IN (which may be a reload register) to
8423 OUT (which may also be a reload register). IN or OUT is from operand
8424 OPNUM with reload type TYPE.
8426 Returns first insn emitted. */
8429 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8431 rtx last = get_last_insn ();
8434 /* If IN is a paradoxical SUBREG, remove it and try to put the
8435 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8436 if (!strip_paradoxical_subreg (&in, &out))
8437 strip_paradoxical_subreg (&out, &in);
8439 /* How to do this reload can get quite tricky. Normally, we are being
8440 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8441 register that didn't get a hard register. In that case we can just
8442 call emit_move_insn.
8444 We can also be asked to reload a PLUS that adds a register or a MEM to
8445 another register, constant or MEM. This can occur during frame pointer
8446 elimination and while reloading addresses. This case is handled by
8447 trying to emit a single insn to perform the add. If it is not valid,
8448 we use a two insn sequence.
8450 Or we can be asked to reload an unary operand that was a fragment of
8451 an addressing mode, into a register. If it isn't recognized as-is,
8452 we try making the unop operand and the reload-register the same:
8453 (set reg:X (unop:X expr:Y))
8454 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8456 Finally, we could be called to handle an 'o' constraint by putting
8457 an address into a register. In that case, we first try to do this
8458 with a named pattern of "reload_load_address". If no such pattern
8459 exists, we just emit a SET insn and hope for the best (it will normally
8460 be valid on machines that use 'o').
8462 This entire process is made complex because reload will never
8463 process the insns we generate here and so we must ensure that
8464 they will fit their constraints and also by the fact that parts of
8465 IN might be being reloaded separately and replaced with spill registers.
8466 Because of this, we are, in some sense, just guessing the right approach
8467 here. The one listed above seems to work.
8469 ??? At some point, this whole thing needs to be rethought. */
8471 if (GET_CODE (in) == PLUS
8472 && (REG_P (XEXP (in, 0))
8473 || GET_CODE (XEXP (in, 0)) == SUBREG
8474 || MEM_P (XEXP (in, 0)))
8475 && (REG_P (XEXP (in, 1))
8476 || GET_CODE (XEXP (in, 1)) == SUBREG
8477 || CONSTANT_P (XEXP (in, 1))
8478 || MEM_P (XEXP (in, 1))))
8480 /* We need to compute the sum of a register or a MEM and another
8481 register, constant, or MEM, and put it into the reload
8482 register. The best possible way of doing this is if the machine
8483 has a three-operand ADD insn that accepts the required operands.
8485 The simplest approach is to try to generate such an insn and see if it
8486 is recognized and matches its constraints. If so, it can be used.
8488 It might be better not to actually emit the insn unless it is valid,
8489 but we need to pass the insn as an operand to `recog' and
8490 `extract_insn' and it is simpler to emit and then delete the insn if
8491 not valid than to dummy things up. */
8493 rtx op0, op1, tem, insn;
8494 enum insn_code code;
8496 op0 = find_replacement (&XEXP (in, 0));
8497 op1 = find_replacement (&XEXP (in, 1));
8499 /* Since constraint checking is strict, commutativity won't be
8500 checked, so we need to do that here to avoid spurious failure
8501 if the add instruction is two-address and the second operand
8502 of the add is the same as the reload reg, which is frequently
8503 the case. If the insn would be A = B + A, rearrange it so
8504 it will be A = A + B as constrain_operands expects. */
8506 if (REG_P (XEXP (in, 1))
8507 && REGNO (out) == REGNO (XEXP (in, 1)))
8508 tem = op0, op0 = op1, op1 = tem;
8510 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8511 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8513 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8517 /* If that failed, we must use a conservative two-insn sequence.
8519 Use a move to copy one operand into the reload register. Prefer
8520 to reload a constant, MEM or pseudo since the move patterns can
8521 handle an arbitrary operand. If OP1 is not a constant, MEM or
8522 pseudo and OP1 is not a valid operand for an add instruction, then
8525 After reloading one of the operands into the reload register, add
8526 the reload register to the output register.
8528 If there is another way to do this for a specific machine, a
8529 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8532 code = optab_handler (add_optab, GET_MODE (out));
8534 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8536 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8537 || (code != CODE_FOR_nothing
8538 && !insn_operand_matches (code, 2, op1)))
8539 tem = op0, op0 = op1, op1 = tem;
8541 gen_reload (out, op0, opnum, type);
8543 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8544 This fixes a problem on the 32K where the stack pointer cannot
8545 be used as an operand of an add insn. */
8547 if (rtx_equal_p (op0, op1))
8550 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8553 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8554 set_unique_reg_note (insn, REG_EQUIV, in);
8558 /* If that failed, copy the address register to the reload register.
8559 Then add the constant to the reload register. */
8561 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8562 gen_reload (out, op1, opnum, type);
8563 insn = emit_insn (gen_add2_insn (out, op0));
8564 set_unique_reg_note (insn, REG_EQUIV, in);
8567 #ifdef SECONDARY_MEMORY_NEEDED
8568 /* If we need a memory location to do the move, do it that way. */
8569 else if ((REG_P (in)
8570 || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
8571 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
8573 || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
8574 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
8575 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
8576 REGNO_REG_CLASS (reg_or_subregno (out)),
8579 /* Get the memory to use and rewrite both registers to its mode. */
8580 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8582 if (GET_MODE (loc) != GET_MODE (out))
8583 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
8585 if (GET_MODE (loc) != GET_MODE (in))
8586 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
8588 gen_reload (loc, in, opnum, type);
8589 gen_reload (out, loc, opnum, type);
8592 else if (REG_P (out) && UNARY_P (in))
8599 op1 = find_replacement (&XEXP (in, 0));
8600 if (op1 != XEXP (in, 0))
8601 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8603 /* First, try a plain SET. */
8604 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8608 /* If that failed, move the inner operand to the reload
8609 register, and try the same unop with the inner expression
8610 replaced with the reload register. */
8612 if (GET_MODE (op1) != GET_MODE (out))
8613 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8617 gen_reload (out_moded, op1, opnum, type);
8620 = gen_rtx_SET (VOIDmode, out,
8621 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8623 insn = emit_insn_if_valid_for_reload (insn);
8626 set_unique_reg_note (insn, REG_EQUIV, in);
8630 fatal_insn ("failure trying to reload:", set);
8632 /* If IN is a simple operand, use gen_move_insn. */
8633 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8635 tem = emit_insn (gen_move_insn (out, in));
8636 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8637 mark_jump_label (in, tem, 0);
8640 #ifdef HAVE_reload_load_address
8641 else if (HAVE_reload_load_address)
8642 emit_insn (gen_reload_load_address (out, in));
8645 /* Otherwise, just write (set OUT IN) and hope for the best. */
8647 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8649 /* Return the first insn emitted.
8650 We can not just return get_last_insn, because there may have
8651 been multiple instructions emitted. Also note that gen_move_insn may
8652 emit more than one insn itself, so we can not assume that there is one
8653 insn emitted per emit_insn_before call. */
8655 return last ? NEXT_INSN (last) : get_insns ();
8658 /* Delete a previously made output-reload whose result we now believe
8659 is not needed. First we double-check.
8661 INSN is the insn now being processed.
8662 LAST_RELOAD_REG is the hard register number for which we want to delete
8663 the last output reload.
8664 J is the reload-number that originally used REG. The caller has made
8665 certain that reload J doesn't use REG any longer for input.
8666 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8669 delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg)
8671 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8672 rtx reg = spill_reg_stored_to[last_reload_reg];
8675 int n_inherited = 0;
8681 /* It is possible that this reload has been only used to set another reload
8682 we eliminated earlier and thus deleted this instruction too. */
8683 if (INSN_DELETED_P (output_reload_insn))
8686 /* Get the raw pseudo-register referred to. */
8688 while (GET_CODE (reg) == SUBREG)
8689 reg = SUBREG_REG (reg);
8690 substed = reg_equiv_memory_loc (REGNO (reg));
8692 /* This is unsafe if the operand occurs more often in the current
8693 insn than it is inherited. */
8694 for (k = n_reloads - 1; k >= 0; k--)
8696 rtx reg2 = rld[k].in;
8699 if (MEM_P (reg2) || reload_override_in[k])
8700 reg2 = rld[k].in_reg;
8702 if (rld[k].out && ! rld[k].out_reg)
8703 reg2 = XEXP (rld[k].in_reg, 0);
8705 while (GET_CODE (reg2) == SUBREG)
8706 reg2 = SUBREG_REG (reg2);
8707 if (rtx_equal_p (reg2, reg))
8709 if (reload_inherited[k] || reload_override_in[k] || k == j)
8715 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8716 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8717 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8720 n_occurrences += count_occurrences (PATTERN (insn),
8721 eliminate_regs (substed, VOIDmode,
8723 for (i1 = reg_equiv_alt_mem_list (REGNO (reg)); i1; i1 = XEXP (i1, 1))
8725 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8726 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8728 if (n_occurrences > n_inherited)
8731 regno = REGNO (reg);
8732 if (regno >= FIRST_PSEUDO_REGISTER)
8735 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
8737 /* If the pseudo-reg we are reloading is no longer referenced
8738 anywhere between the store into it and here,
8739 and we're within the same basic block, then the value can only
8740 pass through the reload reg and end up here.
8741 Otherwise, give up--return. */
8742 for (i1 = NEXT_INSN (output_reload_insn);
8743 i1 != insn; i1 = NEXT_INSN (i1))
8745 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8747 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8748 && refers_to_regno_p (regno, regno + nregs, PATTERN (i1), NULL))
8750 /* If this is USE in front of INSN, we only have to check that
8751 there are no more references than accounted for by inheritance. */
8752 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8754 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8755 i1 = NEXT_INSN (i1);
8757 if (n_occurrences <= n_inherited && i1 == insn)
8763 /* We will be deleting the insn. Remove the spill reg information. */
8764 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8766 spill_reg_store[last_reload_reg + k] = 0;
8767 spill_reg_stored_to[last_reload_reg + k] = 0;
8770 /* The caller has already checked that REG dies or is set in INSN.
8771 It has also checked that we are optimizing, and thus some
8772 inaccuracies in the debugging information are acceptable.
8773 So we could just delete output_reload_insn. But in some cases
8774 we can improve the debugging information without sacrificing
8775 optimization - maybe even improving the code: See if the pseudo
8776 reg has been completely replaced with reload regs. If so, delete
8777 the store insn and forget we had a stack slot for the pseudo. */
8778 if (rld[j].out != rld[j].in
8779 && REG_N_DEATHS (REGNO (reg)) == 1
8780 && REG_N_SETS (REGNO (reg)) == 1
8781 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8782 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8786 /* We know that it was used only between here and the beginning of
8787 the current basic block. (We also know that the last use before
8788 INSN was the output reload we are thinking of deleting, but never
8789 mind that.) Search that range; see if any ref remains. */
8790 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8792 rtx set = single_set (i2);
8794 /* Uses which just store in the pseudo don't count,
8795 since if they are the only uses, they are dead. */
8796 if (set != 0 && SET_DEST (set) == reg)
8801 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8802 && reg_mentioned_p (reg, PATTERN (i2)))
8804 /* Some other ref remains; just delete the output reload we
8806 delete_address_reloads (output_reload_insn, insn);
8807 delete_insn (output_reload_insn);
8812 /* Delete the now-dead stores into this pseudo. Note that this
8813 loop also takes care of deleting output_reload_insn. */
8814 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8816 rtx set = single_set (i2);
8818 if (set != 0 && SET_DEST (set) == reg)
8820 delete_address_reloads (i2, insn);
8828 /* For the debugging info, say the pseudo lives in this reload reg. */
8829 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8830 if (ira_conflicts_p)
8831 /* Inform IRA about the change. */
8832 ira_mark_allocation_change (REGNO (reg));
8833 alter_reg (REGNO (reg), -1, false);
8837 delete_address_reloads (output_reload_insn, insn);
8838 delete_insn (output_reload_insn);
8842 /* We are going to delete DEAD_INSN. Recursively delete loads of
8843 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8844 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8846 delete_address_reloads (rtx dead_insn, rtx current_insn)
8848 rtx set = single_set (dead_insn);
8849 rtx set2, dst, prev, next;
8852 rtx dst = SET_DEST (set);
8854 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8856 /* If we deleted the store from a reloaded post_{in,de}c expression,
8857 we can delete the matching adds. */
8858 prev = PREV_INSN (dead_insn);
8859 next = NEXT_INSN (dead_insn);
8860 if (! prev || ! next)
8862 set = single_set (next);
8863 set2 = single_set (prev);
8865 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8866 || !CONST_INT_P (XEXP (SET_SRC (set), 1))
8867 || !CONST_INT_P (XEXP (SET_SRC (set2), 1)))
8869 dst = SET_DEST (set);
8870 if (! rtx_equal_p (dst, SET_DEST (set2))
8871 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8872 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8873 || (INTVAL (XEXP (SET_SRC (set), 1))
8874 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8876 delete_related_insns (prev);
8877 delete_related_insns (next);
8880 /* Subfunction of delete_address_reloads: process registers found in X. */
8882 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8884 rtx prev, set, dst, i2;
8886 enum rtx_code code = GET_CODE (x);
8890 const char *fmt = GET_RTX_FORMAT (code);
8891 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8894 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8895 else if (fmt[i] == 'E')
8897 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8898 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8905 if (spill_reg_order[REGNO (x)] < 0)
8908 /* Scan backwards for the insn that sets x. This might be a way back due
8910 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8912 code = GET_CODE (prev);
8913 if (code == CODE_LABEL || code == JUMP_INSN)
8917 if (reg_set_p (x, PATTERN (prev)))
8919 if (reg_referenced_p (x, PATTERN (prev)))
8922 if (! prev || INSN_UID (prev) < reload_first_uid)
8924 /* Check that PREV only sets the reload register. */
8925 set = single_set (prev);
8928 dst = SET_DEST (set);
8930 || ! rtx_equal_p (dst, x))
8932 if (! reg_set_p (dst, PATTERN (dead_insn)))
8934 /* Check if DST was used in a later insn -
8935 it might have been inherited. */
8936 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8942 if (reg_referenced_p (dst, PATTERN (i2)))
8944 /* If there is a reference to the register in the current insn,
8945 it might be loaded in a non-inherited reload. If no other
8946 reload uses it, that means the register is set before
8948 if (i2 == current_insn)
8950 for (j = n_reloads - 1; j >= 0; j--)
8951 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8952 || reload_override_in[j] == dst)
8954 for (j = n_reloads - 1; j >= 0; j--)
8955 if (rld[j].in && rld[j].reg_rtx == dst)
8964 /* If DST is still live at CURRENT_INSN, check if it is used for
8965 any reload. Note that even if CURRENT_INSN sets DST, we still
8966 have to check the reloads. */
8967 if (i2 == current_insn)
8969 for (j = n_reloads - 1; j >= 0; j--)
8970 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8971 || reload_override_in[j] == dst)
8973 /* ??? We can't finish the loop here, because dst might be
8974 allocated to a pseudo in this block if no reload in this
8975 block needs any of the classes containing DST - see
8976 spill_hard_reg. There is no easy way to tell this, so we
8977 have to scan till the end of the basic block. */
8979 if (reg_set_p (dst, PATTERN (i2)))
8983 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8984 reg_reloaded_contents[REGNO (dst)] = -1;
8988 /* Output reload-insns to reload VALUE into RELOADREG.
8989 VALUE is an autoincrement or autodecrement RTX whose operand
8990 is a register or memory location;
8991 so reloading involves incrementing that location.
8992 IN is either identical to VALUE, or some cheaper place to reload from.
8994 INC_AMOUNT is the number to increment or decrement by (always positive).
8995 This cannot be deduced from VALUE. */
8998 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
9000 /* REG or MEM to be copied and incremented. */
9001 rtx incloc = find_replacement (&XEXP (value, 0));
9002 /* Nonzero if increment after copying. */
9003 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
9004 || GET_CODE (value) == POST_MODIFY);
9009 rtx real_in = in == value ? incloc : in;
9011 /* No hard register is equivalent to this register after
9012 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9013 we could inc/dec that register as well (maybe even using it for
9014 the source), but I'm not sure it's worth worrying about. */
9016 reg_last_reload_reg[REGNO (incloc)] = 0;
9018 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
9020 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
9021 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
9025 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
9026 inc_amount = -inc_amount;
9028 inc = GEN_INT (inc_amount);
9031 /* If this is post-increment, first copy the location to the reload reg. */
9032 if (post && real_in != reloadreg)
9033 emit_insn (gen_move_insn (reloadreg, real_in));
9037 /* See if we can directly increment INCLOC. Use a method similar to
9038 that in gen_reload. */
9040 last = get_last_insn ();
9041 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
9042 gen_rtx_PLUS (GET_MODE (incloc),
9045 code = recog_memoized (add_insn);
9048 extract_insn (add_insn);
9049 if (constrain_operands (1))
9051 /* If this is a pre-increment and we have incremented the value
9052 where it lives, copy the incremented value to RELOADREG to
9053 be used as an address. */
9056 emit_insn (gen_move_insn (reloadreg, incloc));
9060 delete_insns_since (last);
9063 /* If couldn't do the increment directly, must increment in RELOADREG.
9064 The way we do this depends on whether this is pre- or post-increment.
9065 For pre-increment, copy INCLOC to the reload register, increment it
9066 there, then save back. */
9070 if (in != reloadreg)
9071 emit_insn (gen_move_insn (reloadreg, real_in));
9072 emit_insn (gen_add2_insn (reloadreg, inc));
9073 emit_insn (gen_move_insn (incloc, reloadreg));
9078 Because this might be a jump insn or a compare, and because RELOADREG
9079 may not be available after the insn in an input reload, we must do
9080 the incrementation before the insn being reloaded for.
9082 We have already copied IN to RELOADREG. Increment the copy in
9083 RELOADREG, save that back, then decrement RELOADREG so it has
9084 the original value. */
9086 emit_insn (gen_add2_insn (reloadreg, inc));
9087 emit_insn (gen_move_insn (incloc, reloadreg));
9088 if (CONST_INT_P (inc))
9089 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
9091 emit_insn (gen_sub2_insn (reloadreg, inc));
9097 add_auto_inc_notes (rtx insn, rtx x)
9099 enum rtx_code code = GET_CODE (x);
9103 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9105 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
9109 /* Scan all the operand sub-expressions. */
9110 fmt = GET_RTX_FORMAT (code);
9111 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9114 add_auto_inc_notes (insn, XEXP (x, i));
9115 else if (fmt[i] == 'E')
9116 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9117 add_auto_inc_notes (insn, XVECEXP (x, i, j));
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