1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 88, 89, 92-97, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "insn-flags.h"
31 #include "insn-codes.h"
35 #include "basic-block.h"
42 /* This file contains the reload pass of the compiler, which is
43 run after register allocation has been done. It checks that
44 each insn is valid (operands required to be in registers really
45 are in registers of the proper class) and fixes up invalid ones
46 by copying values temporarily into registers for the insns
49 The results of register allocation are described by the vector
50 reg_renumber; the insns still contain pseudo regs, but reg_renumber
51 can be used to find which hard reg, if any, a pseudo reg is in.
53 The technique we always use is to free up a few hard regs that are
54 called ``reload regs'', and for each place where a pseudo reg
55 must be in a hard reg, copy it temporarily into one of the reload regs.
57 Reload regs are allocated locally for every instruction that needs
58 reloads. When there are pseudos which are allocated to a register that
59 has been chosen as a reload reg, such pseudos must be ``spilled''.
60 This means that they go to other hard regs, or to stack slots if no other
61 available hard regs can be found. Spilling can invalidate more
62 insns, requiring additional need for reloads, so we must keep checking
63 until the process stabilizes.
65 For machines with different classes of registers, we must keep track
66 of the register class needed for each reload, and make sure that
67 we allocate enough reload registers of each class.
69 The file reload.c contains the code that checks one insn for
70 validity and reports the reloads that it needs. This file
71 is in charge of scanning the entire rtl code, accumulating the
72 reload needs, spilling, assigning reload registers to use for
73 fixing up each insn, and generating the new insns to copy values
74 into the reload registers. */
77 #ifndef REGISTER_MOVE_COST
78 #define REGISTER_MOVE_COST(x, y) 2
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
106 This is used when the address is not valid as a memory address
107 (because its displacement is too big for the machine.) */
108 rtx *reg_equiv_address;
110 /* Element N is the memory slot to which pseudo reg N is equivalent,
111 or zero if pseudo reg N is not equivalent to a memory slot. */
114 /* Widest width in which each pseudo reg is referred to (via subreg). */
115 static int *reg_max_ref_width;
117 /* Element N is the list of insns that initialized reg N from its equivalent
118 constant or memory slot. */
119 static rtx *reg_equiv_init;
121 /* Vector to remember old contents of reg_renumber before spilling. */
122 static short *reg_old_renumber;
124 /* During reload_as_needed, element N contains the last pseudo regno reloaded
125 into hard register N. If that pseudo reg occupied more than one register,
126 reg_reloaded_contents points to that pseudo for each spill register in
127 use; all of these must remain set for an inheritance to occur. */
128 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
130 /* During reload_as_needed, element N contains the insn for which
131 hard register N was last used. Its contents are significant only
132 when reg_reloaded_valid is set for this register. */
133 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
135 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
136 static HARD_REG_SET reg_reloaded_valid;
137 /* Indicate if the register was dead at the end of the reload.
138 This is only valid if reg_reloaded_contents is set and valid. */
139 static HARD_REG_SET reg_reloaded_dead;
141 /* Number of spill-regs so far; number of valid elements of spill_regs. */
144 /* In parallel with spill_regs, contains REG rtx's for those regs.
145 Holds the last rtx used for any given reg, or 0 if it has never
146 been used for spilling yet. This rtx is reused, provided it has
148 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
150 /* In parallel with spill_regs, contains nonzero for a spill reg
151 that was stored after the last time it was used.
152 The precise value is the insn generated to do the store. */
153 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
155 /* This is the register that was stored with spill_reg_store. This is a
156 copy of reload_out / reload_out_reg when the value was stored; if
157 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
158 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
160 /* This table is the inverse mapping of spill_regs:
161 indexed by hard reg number,
162 it contains the position of that reg in spill_regs,
163 or -1 for something that is not in spill_regs.
165 ?!? This is no longer accurate. */
166 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
168 /* This reg set indicates registers that can't be used as spill registers for
169 the currently processed insn. These are the hard registers which are live
170 during the insn, but not allocated to pseudos, as well as fixed
172 static HARD_REG_SET bad_spill_regs;
174 /* These are the hard registers that can't be used as spill register for any
175 insn. This includes registers used for user variables and registers that
176 we can't eliminate. A register that appears in this set also can't be used
177 to retry register allocation. */
178 static HARD_REG_SET bad_spill_regs_global;
180 /* Describes order of use of registers for reloading
181 of spilled pseudo-registers. `n_spills' is the number of
182 elements that are actually valid; new ones are added at the end.
184 Both spill_regs and spill_reg_order are used on two occasions:
185 once during find_reload_regs, where they keep track of the spill registers
186 for a single insn, but also during reload_as_needed where they show all
187 the registers ever used by reload. For the latter case, the information
188 is calculated during finish_spills. */
189 static short spill_regs[FIRST_PSEUDO_REGISTER];
191 /* This vector of reg sets indicates, for each pseudo, which hard registers
192 may not be used for retrying global allocation because the register was
193 formerly spilled from one of them. If we allowed reallocating a pseudo to
194 a register that it was already allocated to, reload might not
196 static HARD_REG_SET *pseudo_previous_regs;
198 /* This vector of reg sets indicates, for each pseudo, which hard
199 registers may not be used for retrying global allocation because they
200 are used as spill registers during one of the insns in which the
202 static HARD_REG_SET *pseudo_forbidden_regs;
204 /* All hard regs that have been used as spill registers for any insn are
205 marked in this set. */
206 static HARD_REG_SET used_spill_regs;
208 /* Index of last register assigned as a spill register. We allocate in
209 a round-robin fashion. */
210 static int last_spill_reg;
212 /* Describes order of preference for putting regs into spill_regs.
213 Contains the numbers of all the hard regs, in order most preferred first.
214 This order is different for each function.
215 It is set up by order_regs_for_reload.
216 Empty elements at the end contain -1. */
217 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
219 /* Nonzero if indirect addressing is supported on the machine; this means
220 that spilling (REG n) does not require reloading it into a register in
221 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
222 value indicates the level of indirect addressing supported, e.g., two
223 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
225 static char spill_indirect_levels;
227 /* Nonzero if indirect addressing is supported when the innermost MEM is
228 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
229 which these are valid is the same as spill_indirect_levels, above. */
230 char indirect_symref_ok;
232 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
233 char double_reg_address_ok;
235 /* Record the stack slot for each spilled hard register. */
236 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
238 /* Width allocated so far for that stack slot. */
239 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
241 /* Record which pseudos needed to be spilled. */
242 static regset spilled_pseudos;
244 /* First uid used by insns created by reload in this function.
245 Used in find_equiv_reg. */
246 int reload_first_uid;
248 /* Flag set by local-alloc or global-alloc if anything is live in
249 a call-clobbered reg across calls. */
250 int caller_save_needed;
252 /* Set to 1 while reload_as_needed is operating.
253 Required by some machines to handle any generated moves differently. */
254 int reload_in_progress = 0;
256 /* These arrays record the insn_code of insns that may be needed to
257 perform input and output reloads of special objects. They provide a
258 place to pass a scratch register. */
259 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
260 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
262 /* This obstack is used for allocation of rtl during register elimination.
263 The allocated storage can be freed once find_reloads has processed the
265 struct obstack reload_obstack;
267 /* Points to the beginning of the reload_obstack. All insn_chain structures
268 are allocated first. */
269 char *reload_startobj;
271 /* The point after all insn_chain structures. Used to quickly deallocate
272 memory used while processing one insn. */
273 char *reload_firstobj;
275 #define obstack_chunk_alloc xmalloc
276 #define obstack_chunk_free free
278 /* List of labels that must never be deleted. */
279 extern rtx forced_labels;
281 /* List of insn_chain instructions, one for every insn that reload needs to
283 struct insn_chain *reload_insn_chain;
286 extern tree current_function_decl;
288 extern union tree_node *current_function_decl;
291 /* List of all insns needing reloads. */
292 static struct insn_chain *insns_need_reload;
294 /* This structure is used to record information about register eliminations.
295 Each array entry describes one possible way of eliminating a register
296 in favor of another. If there is more than one way of eliminating a
297 particular register, the most preferred should be specified first. */
301 int from; /* Register number to be eliminated. */
302 int to; /* Register number used as replacement. */
303 int initial_offset; /* Initial difference between values. */
304 int can_eliminate; /* Non-zero if this elimination can be done. */
305 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
306 insns made by reload. */
307 int offset; /* Current offset between the two regs. */
308 int previous_offset; /* Offset at end of previous insn. */
309 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
310 rtx from_rtx; /* REG rtx for the register to be eliminated.
311 We cannot simply compare the number since
312 we might then spuriously replace a hard
313 register corresponding to a pseudo
314 assigned to the reg to be eliminated. */
315 rtx to_rtx; /* REG rtx for the replacement. */
318 static struct elim_table * reg_eliminate = 0;
320 /* This is an intermediate structure to initialize the table. It has
321 exactly the members provided by ELIMINABLE_REGS. */
322 static struct elim_table_1
326 } reg_eliminate_1[] =
328 /* If a set of eliminable registers was specified, define the table from it.
329 Otherwise, default to the normal case of the frame pointer being
330 replaced by the stack pointer. */
332 #ifdef ELIMINABLE_REGS
335 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
338 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate_1/sizeof reg_eliminate_1[0])
340 /* Record the number of pending eliminations that have an offset not equal
341 to their initial offset. If non-zero, we use a new copy of each
342 replacement result in any insns encountered. */
343 int num_not_at_initial_offset;
345 /* Count the number of registers that we may be able to eliminate. */
346 static int num_eliminable;
347 /* And the number of registers that are equivalent to a constant that
348 can be eliminated to frame_pointer / arg_pointer + constant. */
349 static int num_eliminable_invariants;
351 /* For each label, we record the offset of each elimination. If we reach
352 a label by more than one path and an offset differs, we cannot do the
353 elimination. This information is indexed by the number of the label.
354 The first table is an array of flags that records whether we have yet
355 encountered a label and the second table is an array of arrays, one
356 entry in the latter array for each elimination. */
358 static char *offsets_known_at;
359 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
361 /* Number of labels in the current function. */
363 static int num_labels;
365 struct hard_reg_n_uses
371 static void maybe_fix_stack_asms PROTO((void));
372 static void calculate_needs_all_insns PROTO((int));
373 static void calculate_needs PROTO((struct insn_chain *));
374 static void find_reload_regs PROTO((struct insn_chain *chain,
376 static void find_tworeg_group PROTO((struct insn_chain *, int,
378 static void find_group PROTO((struct insn_chain *, int,
380 static int possible_group_p PROTO((struct insn_chain *, int));
381 static void count_possible_groups PROTO((struct insn_chain *, int));
382 static int modes_equiv_for_class_p PROTO((enum machine_mode,
385 static void delete_caller_save_insns PROTO((void));
387 static void spill_failure PROTO((rtx));
388 static void new_spill_reg PROTO((struct insn_chain *, int, int,
390 static void maybe_mark_pseudo_spilled PROTO((int));
391 static void delete_dead_insn PROTO((rtx));
392 static void alter_reg PROTO((int, int));
393 static void set_label_offsets PROTO((rtx, rtx, int));
394 static int eliminate_regs_in_insn PROTO((rtx, int));
395 static void update_eliminable_offsets PROTO((void));
396 static void mark_not_eliminable PROTO((rtx, rtx));
397 static void set_initial_elim_offsets PROTO((void));
398 static void verify_initial_elim_offsets PROTO((void));
399 static void set_initial_label_offsets PROTO((void));
400 static void set_offsets_for_label PROTO((rtx));
401 static void init_elim_table PROTO((void));
402 static void update_eliminables PROTO((HARD_REG_SET *));
403 static void spill_hard_reg PROTO((int, FILE *, int));
404 static int finish_spills PROTO((int, FILE *));
405 static void ior_hard_reg_set PROTO((HARD_REG_SET *, HARD_REG_SET *));
406 static void scan_paradoxical_subregs PROTO((rtx));
407 static int hard_reg_use_compare PROTO((const GENERIC_PTR, const GENERIC_PTR));
408 static void count_pseudo PROTO((struct hard_reg_n_uses *, int));
409 static void order_regs_for_reload PROTO((struct insn_chain *));
410 static void reload_as_needed PROTO((int));
411 static void forget_old_reloads_1 PROTO((rtx, rtx));
412 static int reload_reg_class_lower PROTO((const GENERIC_PTR, const GENERIC_PTR));
413 static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
415 static void clear_reload_reg_in_use PROTO((int, int, enum reload_type,
417 static int reload_reg_free_p PROTO((int, int, enum reload_type));
418 static int reload_reg_free_for_value_p PROTO((int, int, enum reload_type, rtx, rtx, int, int));
419 static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
420 static int allocate_reload_reg PROTO((struct insn_chain *, int, int,
422 static void choose_reload_regs PROTO((struct insn_chain *));
423 static void merge_assigned_reloads PROTO((rtx));
424 static void emit_reload_insns PROTO((struct insn_chain *));
425 static void delete_output_reload PROTO((rtx, int, int));
426 static void delete_address_reloads PROTO((rtx, rtx));
427 static void delete_address_reloads_1 PROTO((rtx, rtx, rtx));
428 static rtx inc_for_reload PROTO((rtx, rtx, rtx, int));
429 static int constraint_accepts_reg_p PROTO((char *, rtx));
430 static void reload_cse_regs_1 PROTO((rtx));
431 static void reload_cse_invalidate_regno PROTO((int, enum machine_mode, int));
432 static int reload_cse_mem_conflict_p PROTO((rtx, rtx));
433 static void reload_cse_invalidate_mem PROTO((rtx));
434 static void reload_cse_invalidate_rtx PROTO((rtx, rtx));
435 static int reload_cse_regno_equal_p PROTO((int, rtx, enum machine_mode));
436 static int reload_cse_noop_set_p PROTO((rtx, rtx));
437 static int reload_cse_simplify_set PROTO((rtx, rtx));
438 static int reload_cse_simplify_operands PROTO((rtx));
439 static void reload_cse_check_clobber PROTO((rtx, rtx));
440 static void reload_cse_record_set PROTO((rtx, rtx));
441 static void reload_combine PROTO((void));
442 static void reload_combine_note_use PROTO((rtx *, rtx));
443 static void reload_combine_note_store PROTO((rtx, rtx));
444 static void reload_cse_move2add PROTO((rtx));
445 static void move2add_note_store PROTO((rtx, rtx));
447 /* Initialize the reload pass once per compilation. */
454 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
455 Set spill_indirect_levels to the number of levels such addressing is
456 permitted, zero if it is not permitted at all. */
459 = gen_rtx_MEM (Pmode,
461 gen_rtx_REG (Pmode, LAST_VIRTUAL_REGISTER + 1),
463 spill_indirect_levels = 0;
465 while (memory_address_p (QImode, tem))
467 spill_indirect_levels++;
468 tem = gen_rtx_MEM (Pmode, tem);
471 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
473 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
474 indirect_symref_ok = memory_address_p (QImode, tem);
476 /* See if reg+reg is a valid (and offsettable) address. */
478 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
480 tem = gen_rtx_PLUS (Pmode,
481 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
482 gen_rtx_REG (Pmode, i));
483 /* This way, we make sure that reg+reg is an offsettable address. */
484 tem = plus_constant (tem, 4);
486 if (memory_address_p (QImode, tem))
488 double_reg_address_ok = 1;
493 /* Initialize obstack for our rtl allocation. */
494 gcc_obstack_init (&reload_obstack);
495 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
498 /* List of insn chains that are currently unused. */
499 static struct insn_chain *unused_insn_chains = 0;
501 /* Allocate an empty insn_chain structure. */
505 struct insn_chain *c;
507 if (unused_insn_chains == 0)
509 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
510 c->live_before = OBSTACK_ALLOC_REG_SET (&reload_obstack);
511 c->live_after = OBSTACK_ALLOC_REG_SET (&reload_obstack);
515 c = unused_insn_chains;
516 unused_insn_chains = c->next;
518 c->is_caller_save_insn = 0;
519 c->need_operand_change = 0;
525 /* Small utility function to set all regs in hard reg set TO which are
526 allocated to pseudos in regset FROM. */
528 compute_use_by_pseudos (to, from)
533 EXECUTE_IF_SET_IN_REG_SET
534 (from, FIRST_PSEUDO_REGISTER, regno,
536 int r = reg_renumber[regno];
540 /* reload_combine uses the information from
541 basic_block_live_at_start, which might still contain registers
542 that have not actually been allocated since they have an
544 if (! reload_completed)
549 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
551 SET_HARD_REG_BIT (*to, r + nregs);
556 /* Global variables used by reload and its subroutines. */
558 /* Set during calculate_needs if an insn needs register elimination. */
559 static int something_needs_elimination;
560 /* Set during calculate_needs if an insn needs an operand changed. */
561 int something_needs_operands_changed;
563 /* Nonzero means we couldn't get enough spill regs. */
566 /* Main entry point for the reload pass.
568 FIRST is the first insn of the function being compiled.
570 GLOBAL nonzero means we were called from global_alloc
571 and should attempt to reallocate any pseudoregs that we
572 displace from hard regs we will use for reloads.
573 If GLOBAL is zero, we do not have enough information to do that,
574 so any pseudo reg that is spilled must go to the stack.
576 DUMPFILE is the global-reg debugging dump file stream, or 0.
577 If it is nonzero, messages are written to it to describe
578 which registers are seized as reload regs, which pseudo regs
579 are spilled from them, and where the pseudo regs are reallocated to.
581 Return value is nonzero if reload failed
582 and we must not do any more for this function. */
585 reload (first, global, dumpfile)
592 register struct elim_table *ep;
594 /* The two pointers used to track the true location of the memory used
595 for label offsets. */
596 char *real_known_ptr = NULL_PTR;
597 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
599 /* Make sure even insns with volatile mem refs are recognizable. */
604 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
606 /* Make sure that the last insn in the chain
607 is not something that needs reloading. */
608 emit_note (NULL_PTR, NOTE_INSN_DELETED);
610 /* Enable find_equiv_reg to distinguish insns made by reload. */
611 reload_first_uid = get_max_uid ();
613 #ifdef SECONDARY_MEMORY_NEEDED
614 /* Initialize the secondary memory table. */
615 clear_secondary_mem ();
618 /* We don't have a stack slot for any spill reg yet. */
619 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
620 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
622 /* Initialize the save area information for caller-save, in case some
626 /* Compute which hard registers are now in use
627 as homes for pseudo registers.
628 This is done here rather than (eg) in global_alloc
629 because this point is reached even if not optimizing. */
630 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
633 /* A function that receives a nonlocal goto must save all call-saved
635 if (current_function_has_nonlocal_label)
636 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
638 if (! call_used_regs[i] && ! fixed_regs[i])
639 regs_ever_live[i] = 1;
642 /* Find all the pseudo registers that didn't get hard regs
643 but do have known equivalent constants or memory slots.
644 These include parameters (known equivalent to parameter slots)
645 and cse'd or loop-moved constant memory addresses.
647 Record constant equivalents in reg_equiv_constant
648 so they will be substituted by find_reloads.
649 Record memory equivalents in reg_mem_equiv so they can
650 be substituted eventually by altering the REG-rtx's. */
652 reg_equiv_constant = (rtx *) xmalloc (max_regno * sizeof (rtx));
653 bzero ((char *) reg_equiv_constant, max_regno * sizeof (rtx));
654 reg_equiv_memory_loc = (rtx *) xmalloc (max_regno * sizeof (rtx));
655 bzero ((char *) reg_equiv_memory_loc, max_regno * sizeof (rtx));
656 reg_equiv_mem = (rtx *) xmalloc (max_regno * sizeof (rtx));
657 bzero ((char *) reg_equiv_mem, max_regno * sizeof (rtx));
658 reg_equiv_init = (rtx *) xmalloc (max_regno * sizeof (rtx));
659 bzero ((char *) reg_equiv_init, max_regno * sizeof (rtx));
660 reg_equiv_address = (rtx *) xmalloc (max_regno * sizeof (rtx));
661 bzero ((char *) reg_equiv_address, max_regno * sizeof (rtx));
662 reg_max_ref_width = (int *) xmalloc (max_regno * sizeof (int));
663 bzero ((char *) reg_max_ref_width, max_regno * sizeof (int));
664 reg_old_renumber = (short *) xmalloc (max_regno * sizeof (short));
665 bcopy (reg_renumber, reg_old_renumber, max_regno * sizeof (short));
666 pseudo_forbidden_regs
667 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
669 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
671 CLEAR_HARD_REG_SET (bad_spill_regs_global);
672 bzero ((char *) pseudo_previous_regs, max_regno * sizeof (HARD_REG_SET));
674 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
675 Also find all paradoxical subregs and find largest such for each pseudo.
676 On machines with small register classes, record hard registers that
677 are used for user variables. These can never be used for spills.
678 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
679 caller-saved registers must be marked live. */
681 num_eliminable_invariants = 0;
682 for (insn = first; insn; insn = NEXT_INSN (insn))
684 rtx set = single_set (insn);
686 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
687 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
688 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
689 if (! call_used_regs[i])
690 regs_ever_live[i] = 1;
692 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
694 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
696 #ifdef LEGITIMATE_PIC_OPERAND_P
697 && (! function_invariant_p (XEXP (note, 0))
699 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
703 rtx x = XEXP (note, 0);
704 i = REGNO (SET_DEST (set));
705 if (i > LAST_VIRTUAL_REGISTER)
707 if (GET_CODE (x) == MEM)
709 /* If the operand is a PLUS, the MEM may be shared,
710 so make sure we have an unshared copy here. */
711 if (GET_CODE (XEXP (x, 0)) == PLUS)
714 reg_equiv_memory_loc[i] = x;
716 else if (function_invariant_p (x))
718 if (GET_CODE (x) == PLUS)
720 /* This is PLUS of frame pointer and a constant,
721 and might be shared. Unshare it. */
722 reg_equiv_constant[i] = copy_rtx (x);
723 num_eliminable_invariants++;
725 else if (x == frame_pointer_rtx
726 || x == arg_pointer_rtx)
728 reg_equiv_constant[i] = x;
729 num_eliminable_invariants++;
731 else if (LEGITIMATE_CONSTANT_P (x))
732 reg_equiv_constant[i] = x;
734 reg_equiv_memory_loc[i]
735 = force_const_mem (GET_MODE (SET_DEST (set)), x);
740 /* If this register is being made equivalent to a MEM
741 and the MEM is not SET_SRC, the equivalencing insn
742 is one with the MEM as a SET_DEST and it occurs later.
743 So don't mark this insn now. */
744 if (GET_CODE (x) != MEM
745 || rtx_equal_p (SET_SRC (set), x))
747 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
752 /* If this insn is setting a MEM from a register equivalent to it,
753 this is the equivalencing insn. */
754 else if (set && GET_CODE (SET_DEST (set)) == MEM
755 && GET_CODE (SET_SRC (set)) == REG
756 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
757 && rtx_equal_p (SET_DEST (set),
758 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
759 reg_equiv_init[REGNO (SET_SRC (set))]
760 = gen_rtx_INSN_LIST (VOIDmode, insn,
761 reg_equiv_init[REGNO (SET_SRC (set))]);
763 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
764 scan_paradoxical_subregs (PATTERN (insn));
769 num_labels = max_label_num () - get_first_label_num ();
771 /* Allocate the tables used to store offset information at labels. */
772 /* We used to use alloca here, but the size of what it would try to
773 allocate would occasionally cause it to exceed the stack limit and
774 cause a core dump. */
775 real_known_ptr = xmalloc (num_labels);
777 = (int (*)[NUM_ELIMINABLE_REGS])
778 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
780 offsets_known_at = real_known_ptr - get_first_label_num ();
782 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
784 /* Alter each pseudo-reg rtx to contain its hard reg number.
785 Assign stack slots to the pseudos that lack hard regs or equivalents.
786 Do not touch virtual registers. */
788 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
791 /* If we have some registers we think can be eliminated, scan all insns to
792 see if there is an insn that sets one of these registers to something
793 other than itself plus a constant. If so, the register cannot be
794 eliminated. Doing this scan here eliminates an extra pass through the
795 main reload loop in the most common case where register elimination
797 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
798 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
799 || GET_CODE (insn) == CALL_INSN)
800 note_stores (PATTERN (insn), mark_not_eliminable);
802 #ifndef REGISTER_CONSTRAINTS
803 /* If all the pseudo regs have hard regs,
804 except for those that are never referenced,
805 we know that no reloads are needed. */
806 /* But that is not true if there are register constraints, since
807 in that case some pseudos might be in the wrong kind of hard reg. */
809 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
810 if (reg_renumber[i] == -1 && REG_N_REFS (i) != 0)
813 if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
815 free (real_known_ptr);
817 free (reg_equiv_constant);
818 free (reg_equiv_memory_loc);
819 free (reg_equiv_mem);
820 free (reg_equiv_init);
821 free (reg_equiv_address);
822 free (reg_max_ref_width);
823 free (reg_old_renumber);
824 free (pseudo_previous_regs);
825 free (pseudo_forbidden_regs);
830 maybe_fix_stack_asms ();
832 insns_need_reload = 0;
833 something_needs_elimination = 0;
835 /* Initialize to -1, which means take the first spill register. */
838 spilled_pseudos = ALLOCA_REG_SET ();
840 /* Spill any hard regs that we know we can't eliminate. */
841 CLEAR_HARD_REG_SET (used_spill_regs);
842 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
843 if (! ep->can_eliminate)
844 spill_hard_reg (ep->from, dumpfile, 1);
846 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
847 if (frame_pointer_needed)
848 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, dumpfile, 1);
850 finish_spills (global, dumpfile);
852 /* From now on, we may need to generate moves differently. We may also
853 allow modifications of insns which cause them to not be recognized.
854 Any such modifications will be cleaned up during reload itself. */
855 reload_in_progress = 1;
857 /* This loop scans the entire function each go-round
858 and repeats until one repetition spills no additional hard regs. */
861 int something_changed;
863 struct insn_chain *chain;
865 HOST_WIDE_INT starting_frame_size;
867 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done
868 here because the stack size may be a part of the offset computation
869 for register elimination, and there might have been new stack slots
870 created in the last iteration of this loop. */
871 assign_stack_local (BLKmode, 0, 0);
873 starting_frame_size = get_frame_size ();
875 set_initial_elim_offsets ();
876 set_initial_label_offsets ();
878 /* For each pseudo register that has an equivalent location defined,
879 try to eliminate any eliminable registers (such as the frame pointer)
880 assuming initial offsets for the replacement register, which
883 If the resulting location is directly addressable, substitute
884 the MEM we just got directly for the old REG.
886 If it is not addressable but is a constant or the sum of a hard reg
887 and constant, it is probably not addressable because the constant is
888 out of range, in that case record the address; we will generate
889 hairy code to compute the address in a register each time it is
890 needed. Similarly if it is a hard register, but one that is not
891 valid as an address register.
893 If the location is not addressable, but does not have one of the
894 above forms, assign a stack slot. We have to do this to avoid the
895 potential of producing lots of reloads if, e.g., a location involves
896 a pseudo that didn't get a hard register and has an equivalent memory
897 location that also involves a pseudo that didn't get a hard register.
899 Perhaps at some point we will improve reload_when_needed handling
900 so this problem goes away. But that's very hairy. */
902 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
903 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
905 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
907 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
909 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
910 else if (CONSTANT_P (XEXP (x, 0))
911 || (GET_CODE (XEXP (x, 0)) == REG
912 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
913 || (GET_CODE (XEXP (x, 0)) == PLUS
914 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
915 && (REGNO (XEXP (XEXP (x, 0), 0))
916 < FIRST_PSEUDO_REGISTER)
917 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
918 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
921 /* Make a new stack slot. Then indicate that something
922 changed so we go back and recompute offsets for
923 eliminable registers because the allocation of memory
924 below might change some offset. reg_equiv_{mem,address}
925 will be set up for this pseudo on the next pass around
927 reg_equiv_memory_loc[i] = 0;
928 reg_equiv_init[i] = 0;
933 if (caller_save_needed)
936 /* If we allocated another stack slot, redo elimination bookkeeping. */
937 if (starting_frame_size != get_frame_size ())
940 if (caller_save_needed)
942 save_call_clobbered_regs ();
943 /* That might have allocated new insn_chain structures. */
944 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
947 calculate_needs_all_insns (global);
949 CLEAR_REG_SET (spilled_pseudos);
952 something_changed = 0;
954 /* If we allocated any new memory locations, make another pass
955 since it might have changed elimination offsets. */
956 if (starting_frame_size != get_frame_size ())
957 something_changed = 1;
960 HARD_REG_SET to_spill;
961 CLEAR_HARD_REG_SET (to_spill);
962 update_eliminables (&to_spill);
963 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
964 if (TEST_HARD_REG_BIT (to_spill, i))
966 spill_hard_reg (i, dumpfile, 1);
969 /* Regardless of the state of spills, if we previously had
970 a register that we thought we could eliminate, but no can
971 not eliminate, we must run another pass.
973 Consider pseudos which have an entry in reg_equiv_* which
974 reference an eliminable register. We must make another pass
975 to update reg_equiv_* so that we do not substitute in the
976 old value from when we thought the elimination could be
978 something_changed = 1;
982 CLEAR_HARD_REG_SET (used_spill_regs);
983 /* Try to satisfy the needs for each insn. */
984 for (chain = insns_need_reload; chain != 0;
985 chain = chain->next_need_reload)
986 find_reload_regs (chain, dumpfile);
991 if (insns_need_reload != 0 || did_spill)
992 something_changed |= finish_spills (global, dumpfile);
994 if (! something_changed)
997 if (caller_save_needed)
998 delete_caller_save_insns ();
1001 /* If global-alloc was run, notify it of any register eliminations we have
1004 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1005 if (ep->can_eliminate)
1006 mark_elimination (ep->from, ep->to);
1008 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1009 If that insn didn't set the register (i.e., it copied the register to
1010 memory), just delete that insn instead of the equivalencing insn plus
1011 anything now dead. If we call delete_dead_insn on that insn, we may
1012 delete the insn that actually sets the register if the register dies
1013 there and that is incorrect. */
1015 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1017 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1020 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1022 rtx equiv_insn = XEXP (list, 0);
1023 if (GET_CODE (equiv_insn) == NOTE)
1025 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1026 delete_dead_insn (equiv_insn);
1029 PUT_CODE (equiv_insn, NOTE);
1030 NOTE_SOURCE_FILE (equiv_insn) = 0;
1031 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1037 /* Use the reload registers where necessary
1038 by generating move instructions to move the must-be-register
1039 values into or out of the reload registers. */
1041 if (insns_need_reload != 0 || something_needs_elimination
1042 || something_needs_operands_changed)
1044 int old_frame_size = get_frame_size ();
1046 reload_as_needed (global);
1048 if (old_frame_size != get_frame_size ())
1052 verify_initial_elim_offsets ();
1055 /* If we were able to eliminate the frame pointer, show that it is no
1056 longer live at the start of any basic block. If it ls live by
1057 virtue of being in a pseudo, that pseudo will be marked live
1058 and hence the frame pointer will be known to be live via that
1061 if (! frame_pointer_needed)
1062 for (i = 0; i < n_basic_blocks; i++)
1063 CLEAR_REGNO_REG_SET (basic_block_live_at_start[i],
1064 HARD_FRAME_POINTER_REGNUM);
1066 /* Come here (with failure set nonzero) if we can't get enough spill regs
1067 and we decide not to abort about it. */
1070 reload_in_progress = 0;
1072 /* Now eliminate all pseudo regs by modifying them into
1073 their equivalent memory references.
1074 The REG-rtx's for the pseudos are modified in place,
1075 so all insns that used to refer to them now refer to memory.
1077 For a reg that has a reg_equiv_address, all those insns
1078 were changed by reloading so that no insns refer to it any longer;
1079 but the DECL_RTL of a variable decl may refer to it,
1080 and if so this causes the debugging info to mention the variable. */
1082 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1086 int is_readonly = 0;
1088 if (reg_equiv_memory_loc[i])
1090 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1091 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1094 if (reg_equiv_mem[i])
1095 addr = XEXP (reg_equiv_mem[i], 0);
1097 if (reg_equiv_address[i])
1098 addr = reg_equiv_address[i];
1102 if (reg_renumber[i] < 0)
1104 rtx reg = regno_reg_rtx[i];
1105 XEXP (reg, 0) = addr;
1106 REG_USERVAR_P (reg) = 0;
1107 RTX_UNCHANGING_P (reg) = is_readonly;
1108 MEM_IN_STRUCT_P (reg) = in_struct;
1109 /* We have no alias information about this newly created
1111 MEM_ALIAS_SET (reg) = 0;
1112 PUT_CODE (reg, MEM);
1114 else if (reg_equiv_mem[i])
1115 XEXP (reg_equiv_mem[i], 0) = addr;
1119 /* Make a pass over all the insns and delete all USEs which we inserted
1120 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1121 notes. Delete all CLOBBER insns and simplify (subreg (reg)) operands.
1122 Also remove all REG_RETVAL and REG_LIBCALL notes since they are no longer
1123 useful or accurate. */
1125 for (insn = first; insn; insn = NEXT_INSN (insn))
1126 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1130 if ((GET_CODE (PATTERN (insn)) == USE
1131 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1132 || GET_CODE (PATTERN (insn)) == CLOBBER)
1134 PUT_CODE (insn, NOTE);
1135 NOTE_SOURCE_FILE (insn) = 0;
1136 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1140 pnote = ®_NOTES (insn);
1143 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1144 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1145 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1146 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1147 *pnote = XEXP (*pnote, 1);
1149 pnote = &XEXP (*pnote, 1);
1152 /* And simplify (subreg (reg)) if it appears as an operand. */
1153 cleanup_subreg_operands (insn);
1156 /* If we are doing stack checking, give a warning if this function's
1157 frame size is larger than we expect. */
1158 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1160 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1162 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1163 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1164 size += UNITS_PER_WORD;
1166 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1167 warning ("frame size too large for reliable stack checking");
1170 /* Indicate that we no longer have known memory locations or constants. */
1171 if (reg_equiv_constant)
1172 free (reg_equiv_constant);
1173 reg_equiv_constant = 0;
1174 if (reg_equiv_memory_loc)
1175 free (reg_equiv_memory_loc);
1176 reg_equiv_memory_loc = 0;
1179 free (real_known_ptr);
1183 free (reg_equiv_mem);
1184 free (reg_equiv_init);
1185 free (reg_equiv_address);
1186 free (reg_max_ref_width);
1187 free (reg_old_renumber);
1188 free (pseudo_previous_regs);
1189 free (pseudo_forbidden_regs);
1191 FREE_REG_SET (spilled_pseudos);
1193 CLEAR_HARD_REG_SET (used_spill_regs);
1194 for (i = 0; i < n_spills; i++)
1195 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1197 /* Free all the insn_chain structures at once. */
1198 obstack_free (&reload_obstack, reload_startobj);
1199 unused_insn_chains = 0;
1204 /* Yet another special case. Unfortunately, reg-stack forces people to
1205 write incorrect clobbers in asm statements. These clobbers must not
1206 cause the register to appear in bad_spill_regs, otherwise we'll call
1207 fatal_insn later. We clear the corresponding regnos in the live
1208 register sets to avoid this.
1209 The whole thing is rather sick, I'm afraid. */
1211 maybe_fix_stack_asms ()
1214 char *constraints[MAX_RECOG_OPERANDS];
1215 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1216 struct insn_chain *chain;
1218 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1221 HARD_REG_SET clobbered, allowed;
1224 if (GET_RTX_CLASS (GET_CODE (chain->insn)) != 'i'
1225 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1227 pat = PATTERN (chain->insn);
1228 if (GET_CODE (pat) != PARALLEL)
1231 CLEAR_HARD_REG_SET (clobbered);
1232 CLEAR_HARD_REG_SET (allowed);
1234 /* First, make a mask of all stack regs that are clobbered. */
1235 for (i = 0; i < XVECLEN (pat, 0); i++)
1237 rtx t = XVECEXP (pat, 0, i);
1238 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1239 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1242 /* Get the operand values and constraints out of the insn. */
1243 decode_asm_operands (pat, recog_operand, recog_operand_loc,
1244 constraints, operand_mode);
1246 /* For every operand, see what registers are allowed. */
1247 for (i = 0; i < noperands; i++)
1249 char *p = constraints[i];
1250 /* For every alternative, we compute the class of registers allowed
1251 for reloading in CLS, and merge its contents into the reg set
1253 int cls = (int) NO_REGS;
1259 if (c == '\0' || c == ',' || c == '#')
1261 /* End of one alternative - mark the regs in the current
1262 class, and reset the class. */
1263 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1268 } while (c != '\0' && c != ',');
1276 case '=': case '+': case '*': case '%': case '?': case '!':
1277 case '0': case '1': case '2': case '3': case '4': case 'm':
1278 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1279 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1280 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1282 #ifdef EXTRA_CONSTRAINT
1283 case 'Q': case 'R': case 'S': case 'T': case 'U':
1288 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1293 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1297 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1302 /* Those of the registers which are clobbered, but allowed by the
1303 constraints, must be usable as reload registers. So clear them
1304 out of the life information. */
1305 AND_HARD_REG_SET (allowed, clobbered);
1306 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1307 if (TEST_HARD_REG_BIT (allowed, i))
1309 CLEAR_REGNO_REG_SET (chain->live_before, i);
1310 CLEAR_REGNO_REG_SET (chain->live_after, i);
1318 /* Walk the chain of insns, and determine for each whether it needs reloads
1319 and/or eliminations. Build the corresponding insns_need_reload list, and
1320 set something_needs_elimination as appropriate. */
1322 calculate_needs_all_insns (global)
1325 struct insn_chain **pprev_reload = &insns_need_reload;
1326 struct insn_chain **pchain;
1328 something_needs_elimination = 0;
1330 for (pchain = &reload_insn_chain; *pchain != 0; pchain = &(*pchain)->next)
1333 struct insn_chain *chain;
1338 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1339 include REG_LABEL), we need to see what effects this has on the
1340 known offsets at labels. */
1342 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1343 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1344 && REG_NOTES (insn) != 0))
1345 set_label_offsets (insn, insn, 0);
1347 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1349 rtx old_body = PATTERN (insn);
1350 int old_code = INSN_CODE (insn);
1351 rtx old_notes = REG_NOTES (insn);
1352 int did_elimination = 0;
1353 int operands_changed = 0;
1354 rtx set = single_set (insn);
1356 /* Skip insns that only set an equivalence. */
1357 if (set && GET_CODE (SET_DEST (set)) == REG
1358 && reg_renumber[REGNO (SET_DEST (set))] < 0
1359 && reg_equiv_constant[REGNO (SET_DEST (set))])
1362 /* If needed, eliminate any eliminable registers. */
1363 if (num_eliminable || num_eliminable_invariants)
1364 did_elimination = eliminate_regs_in_insn (insn, 0);
1366 /* Analyze the instruction. */
1367 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1368 global, spill_reg_order);
1370 /* If a no-op set needs more than one reload, this is likely
1371 to be something that needs input address reloads. We
1372 can't get rid of this cleanly later, and it is of no use
1373 anyway, so discard it now.
1374 We only do this when expensive_optimizations is enabled,
1375 since this complements reload inheritance / output
1376 reload deletion, and it can make debugging harder. */
1377 if (flag_expensive_optimizations && n_reloads > 1)
1379 rtx set = single_set (insn);
1381 && SET_SRC (set) == SET_DEST (set)
1382 && GET_CODE (SET_SRC (set)) == REG
1383 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1385 PUT_CODE (insn, NOTE);
1386 NOTE_SOURCE_FILE (insn) = 0;
1387 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1392 update_eliminable_offsets ();
1394 /* Remember for later shortcuts which insns had any reloads or
1395 register eliminations. */
1396 chain->need_elim = did_elimination;
1397 chain->need_reload = n_reloads > 0;
1398 chain->need_operand_change = operands_changed;
1400 /* Discard any register replacements done. */
1401 if (did_elimination)
1403 obstack_free (&reload_obstack, reload_firstobj);
1404 PATTERN (insn) = old_body;
1405 INSN_CODE (insn) = old_code;
1406 REG_NOTES (insn) = old_notes;
1407 something_needs_elimination = 1;
1410 something_needs_operands_changed |= operands_changed;
1414 *pprev_reload = chain;
1415 pprev_reload = &chain->next_need_reload;
1417 calculate_needs (chain);
1424 /* Compute the most additional registers needed by one instruction,
1425 given by CHAIN. Collect information separately for each class of regs.
1427 To compute the number of reload registers of each class needed for an
1428 insn, we must simulate what choose_reload_regs can do. We do this by
1429 splitting an insn into an "input" and an "output" part. RELOAD_OTHER
1430 reloads are used in both. The input part uses those reloads,
1431 RELOAD_FOR_INPUT reloads, which must be live over the entire input section
1432 of reloads, and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
1433 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the inputs.
1435 The registers needed for output are RELOAD_OTHER and RELOAD_FOR_OUTPUT,
1436 which are live for the entire output portion, and the maximum of all the
1437 RELOAD_FOR_OUTPUT_ADDRESS reloads for each operand.
1439 The total number of registers needed is the maximum of the
1440 inputs and outputs. */
1443 calculate_needs (chain)
1444 struct insn_chain *chain;
1448 /* Each `struct needs' corresponds to one RELOAD_... type. */
1452 struct needs output;
1454 struct needs other_addr;
1455 struct needs op_addr;
1456 struct needs op_addr_reload;
1457 struct needs in_addr[MAX_RECOG_OPERANDS];
1458 struct needs in_addr_addr[MAX_RECOG_OPERANDS];
1459 struct needs out_addr[MAX_RECOG_OPERANDS];
1460 struct needs out_addr_addr[MAX_RECOG_OPERANDS];
1463 bzero ((char *) chain->group_size, sizeof chain->group_size);
1464 for (i = 0; i < N_REG_CLASSES; i++)
1465 chain->group_mode[i] = VOIDmode;
1466 bzero ((char *) &insn_needs, sizeof insn_needs);
1468 /* Count each reload once in every class
1469 containing the reload's own class. */
1471 for (i = 0; i < n_reloads; i++)
1473 register enum reg_class *p;
1474 enum reg_class class = reload_reg_class[i];
1476 enum machine_mode mode;
1477 struct needs *this_needs;
1479 /* Don't count the dummy reloads, for which one of the
1480 regs mentioned in the insn can be used for reloading.
1481 Don't count optional reloads.
1482 Don't count reloads that got combined with others. */
1483 if (reload_reg_rtx[i] != 0
1484 || reload_optional[i] != 0
1485 || (reload_out[i] == 0 && reload_in[i] == 0
1486 && ! reload_secondary_p[i]))
1489 mode = reload_inmode[i];
1490 if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1491 mode = reload_outmode[i];
1492 size = CLASS_MAX_NREGS (class, mode);
1494 /* Decide which time-of-use to count this reload for. */
1495 switch (reload_when_needed[i])
1498 this_needs = &insn_needs.other;
1500 case RELOAD_FOR_INPUT:
1501 this_needs = &insn_needs.input;
1503 case RELOAD_FOR_OUTPUT:
1504 this_needs = &insn_needs.output;
1506 case RELOAD_FOR_INSN:
1507 this_needs = &insn_needs.insn;
1509 case RELOAD_FOR_OTHER_ADDRESS:
1510 this_needs = &insn_needs.other_addr;
1512 case RELOAD_FOR_INPUT_ADDRESS:
1513 this_needs = &insn_needs.in_addr[reload_opnum[i]];
1515 case RELOAD_FOR_INPADDR_ADDRESS:
1516 this_needs = &insn_needs.in_addr_addr[reload_opnum[i]];
1518 case RELOAD_FOR_OUTPUT_ADDRESS:
1519 this_needs = &insn_needs.out_addr[reload_opnum[i]];
1521 case RELOAD_FOR_OUTADDR_ADDRESS:
1522 this_needs = &insn_needs.out_addr_addr[reload_opnum[i]];
1524 case RELOAD_FOR_OPERAND_ADDRESS:
1525 this_needs = &insn_needs.op_addr;
1527 case RELOAD_FOR_OPADDR_ADDR:
1528 this_needs = &insn_needs.op_addr_reload;
1534 enum machine_mode other_mode, allocate_mode;
1536 /* Count number of groups needed separately from
1537 number of individual regs needed. */
1538 this_needs->groups[(int) class]++;
1539 p = reg_class_superclasses[(int) class];
1540 while (*p != LIM_REG_CLASSES)
1541 this_needs->groups[(int) *p++]++;
1543 /* Record size and mode of a group of this class. */
1544 /* If more than one size group is needed,
1545 make all groups the largest needed size. */
1546 if (chain->group_size[(int) class] < size)
1548 other_mode = chain->group_mode[(int) class];
1549 allocate_mode = mode;
1551 chain->group_size[(int) class] = size;
1552 chain->group_mode[(int) class] = mode;
1557 allocate_mode = chain->group_mode[(int) class];
1560 /* Crash if two dissimilar machine modes both need
1561 groups of consecutive regs of the same class. */
1563 if (other_mode != VOIDmode && other_mode != allocate_mode
1564 && ! modes_equiv_for_class_p (allocate_mode,
1566 fatal_insn ("Two dissimilar machine modes both need groups of consecutive regs of the same class",
1571 this_needs->regs[(unsigned char)reload_nongroup[i]][(int) class] += 1;
1572 p = reg_class_superclasses[(int) class];
1573 while (*p != LIM_REG_CLASSES)
1574 this_needs->regs[(unsigned char)reload_nongroup[i]][(int) *p++] += 1;
1580 /* All reloads have been counted for this insn;
1581 now merge the various times of use.
1582 This sets insn_needs, etc., to the maximum total number
1583 of registers needed at any point in this insn. */
1585 for (i = 0; i < N_REG_CLASSES; i++)
1587 int j, in_max, out_max;
1589 /* Compute normal and nongroup needs. */
1590 for (j = 0; j <= 1; j++)
1593 for (in_max = 0, out_max = 0, k = 0; k < reload_n_operands; k++)
1595 in_max = MAX (in_max,
1596 (insn_needs.in_addr[k].regs[j][i]
1597 + insn_needs.in_addr_addr[k].regs[j][i]));
1598 out_max = MAX (out_max, insn_needs.out_addr[k].regs[j][i]);
1599 out_max = MAX (out_max,
1600 insn_needs.out_addr_addr[k].regs[j][i]);
1603 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1604 and operand addresses but not things used to reload
1605 them. Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads
1606 don't conflict with things needed to reload inputs or
1609 in_max = MAX (MAX (insn_needs.op_addr.regs[j][i],
1610 insn_needs.op_addr_reload.regs[j][i]),
1613 out_max = MAX (out_max, insn_needs.insn.regs[j][i]);
1615 insn_needs.input.regs[j][i]
1616 = MAX (insn_needs.input.regs[j][i]
1617 + insn_needs.op_addr.regs[j][i]
1618 + insn_needs.insn.regs[j][i],
1619 in_max + insn_needs.input.regs[j][i]);
1621 insn_needs.output.regs[j][i] += out_max;
1622 insn_needs.other.regs[j][i]
1623 += MAX (MAX (insn_needs.input.regs[j][i],
1624 insn_needs.output.regs[j][i]),
1625 insn_needs.other_addr.regs[j][i]);
1629 /* Now compute group needs. */
1630 for (in_max = 0, out_max = 0, j = 0; j < reload_n_operands; j++)
1632 in_max = MAX (in_max, insn_needs.in_addr[j].groups[i]);
1633 in_max = MAX (in_max, insn_needs.in_addr_addr[j].groups[i]);
1634 out_max = MAX (out_max, insn_needs.out_addr[j].groups[i]);
1635 out_max = MAX (out_max, insn_needs.out_addr_addr[j].groups[i]);
1638 in_max = MAX (MAX (insn_needs.op_addr.groups[i],
1639 insn_needs.op_addr_reload.groups[i]),
1641 out_max = MAX (out_max, insn_needs.insn.groups[i]);
1643 insn_needs.input.groups[i]
1644 = MAX (insn_needs.input.groups[i]
1645 + insn_needs.op_addr.groups[i]
1646 + insn_needs.insn.groups[i],
1647 in_max + insn_needs.input.groups[i]);
1649 insn_needs.output.groups[i] += out_max;
1650 insn_needs.other.groups[i]
1651 += MAX (MAX (insn_needs.input.groups[i],
1652 insn_needs.output.groups[i]),
1653 insn_needs.other_addr.groups[i]);
1656 /* Record the needs for later. */
1657 chain->need = insn_needs.other;
1660 /* Find a group of exactly 2 registers.
1662 First try to fill out the group by spilling a single register which
1663 would allow completion of the group.
1665 Then try to create a new group from a pair of registers, neither of
1666 which are explicitly used.
1668 Then try to create a group from any pair of registers. */
1671 find_tworeg_group (chain, class, dumpfile)
1672 struct insn_chain *chain;
1677 /* First, look for a register that will complete a group. */
1678 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1682 j = potential_reload_regs[i];
1683 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1684 && ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1685 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1686 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1687 && HARD_REGNO_MODE_OK (other, chain->group_mode[class])
1688 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, other)
1689 /* We don't want one part of another group.
1690 We could get "two groups" that overlap! */
1691 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, other))
1692 || (j < FIRST_PSEUDO_REGISTER - 1
1693 && (other = j + 1, spill_reg_order[other] >= 0)
1694 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1695 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1696 && HARD_REGNO_MODE_OK (j, chain->group_mode[class])
1697 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, other)
1698 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, other))))
1700 register enum reg_class *p;
1702 /* We have found one that will complete a group,
1703 so count off one group as provided. */
1704 chain->need.groups[class]--;
1705 p = reg_class_superclasses[class];
1706 while (*p != LIM_REG_CLASSES)
1708 if (chain->group_size [(int) *p] <= chain->group_size [class])
1709 chain->need.groups[(int) *p]--;
1713 /* Indicate both these regs are part of a group. */
1714 SET_HARD_REG_BIT (chain->counted_for_groups, j);
1715 SET_HARD_REG_BIT (chain->counted_for_groups, other);
1719 /* We can't complete a group, so start one. */
1720 if (i == FIRST_PSEUDO_REGISTER)
1721 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1724 j = potential_reload_regs[i];
1725 /* Verify that J+1 is a potential reload reg. */
1726 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1727 if (potential_reload_regs[k] == j + 1)
1729 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1730 && k < FIRST_PSEUDO_REGISTER
1731 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1732 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1733 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1734 && HARD_REGNO_MODE_OK (j, chain->group_mode[class])
1735 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, j + 1)
1736 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1))
1740 /* I should be the index in potential_reload_regs
1741 of the new reload reg we have found. */
1743 new_spill_reg (chain, i, class, 0, dumpfile);
1746 /* Find a group of more than 2 registers.
1747 Look for a sufficient sequence of unspilled registers, and spill them all
1751 find_group (chain, class, dumpfile)
1752 struct insn_chain *chain;
1758 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1760 int j = potential_reload_regs[i];
1763 && j + chain->group_size[class] <= FIRST_PSEUDO_REGISTER
1764 && HARD_REGNO_MODE_OK (j, chain->group_mode[class]))
1767 /* Check each reg in the sequence. */
1768 for (k = 0; k < chain->group_size[class]; k++)
1769 if (! (spill_reg_order[j + k] < 0
1770 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1771 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1773 /* We got a full sequence, so spill them all. */
1774 if (k == chain->group_size[class])
1776 register enum reg_class *p;
1777 for (k = 0; k < chain->group_size[class]; k++)
1780 SET_HARD_REG_BIT (chain->counted_for_groups, j + k);
1781 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1782 if (potential_reload_regs[idx] == j + k)
1784 new_spill_reg (chain, idx, class, 0, dumpfile);
1787 /* We have found one that will complete a group,
1788 so count off one group as provided. */
1789 chain->need.groups[class]--;
1790 p = reg_class_superclasses[class];
1791 while (*p != LIM_REG_CLASSES)
1793 if (chain->group_size [(int) *p]
1794 <= chain->group_size [class])
1795 chain->need.groups[(int) *p]--;
1802 /* There are no groups left. */
1803 spill_failure (chain->insn);
1807 /* If pseudo REG conflicts with one of our reload registers, mark it as
1810 maybe_mark_pseudo_spilled (reg)
1814 int r = reg_renumber[reg];
1819 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1820 for (i = 0; i < n_spills; i++)
1821 if (r <= spill_regs[i] && r + nregs > spill_regs[i])
1823 SET_REGNO_REG_SET (spilled_pseudos, reg);
1828 /* Find more reload regs to satisfy the remaining need of an insn, which
1830 Do it by ascending class number, since otherwise a reg
1831 might be spilled for a big class and might fail to count
1832 for a smaller class even though it belongs to that class.
1834 Count spilled regs in `spills', and add entries to
1835 `spill_regs' and `spill_reg_order'.
1837 ??? Note there is a problem here.
1838 When there is a need for a group in a high-numbered class,
1839 and also need for non-group regs that come from a lower class,
1840 the non-group regs are chosen first. If there aren't many regs,
1841 they might leave no room for a group.
1843 This was happening on the 386. To fix it, we added the code
1844 that calls possible_group_p, so that the lower class won't
1845 break up the last possible group.
1847 Really fixing the problem would require changes above
1848 in counting the regs already spilled, and in choose_reload_regs.
1849 It might be hard to avoid introducing bugs there. */
1852 find_reload_regs (chain, dumpfile)
1853 struct insn_chain *chain;
1857 short *group_needs = chain->need.groups;
1858 short *simple_needs = chain->need.regs[0];
1859 short *nongroup_needs = chain->need.regs[1];
1862 fprintf (dumpfile, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1864 /* Compute the order of preference for hard registers to spill.
1865 Store them by decreasing preference in potential_reload_regs. */
1867 order_regs_for_reload (chain);
1869 /* So far, no hard regs have been spilled. */
1871 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1872 spill_reg_order[i] = -1;
1874 CLEAR_HARD_REG_SET (chain->used_spill_regs);
1875 CLEAR_HARD_REG_SET (chain->counted_for_groups);
1876 CLEAR_HARD_REG_SET (chain->counted_for_nongroups);
1878 for (class = 0; class < N_REG_CLASSES; class++)
1880 /* First get the groups of registers.
1881 If we got single registers first, we might fragment
1883 while (group_needs[class] > 0)
1885 /* If any single spilled regs happen to form groups,
1886 count them now. Maybe we don't really need
1887 to spill another group. */
1888 count_possible_groups (chain, class);
1890 if (group_needs[class] <= 0)
1893 /* Groups of size 2, the only groups used on most machines,
1894 are treated specially. */
1895 if (chain->group_size[class] == 2)
1896 find_tworeg_group (chain, class, dumpfile);
1898 find_group (chain, class, dumpfile);
1903 /* Now similarly satisfy all need for single registers. */
1905 while (simple_needs[class] > 0 || nongroup_needs[class] > 0)
1907 /* If we spilled enough regs, but they weren't counted
1908 against the non-group need, see if we can count them now.
1909 If so, we can avoid some actual spilling. */
1910 if (simple_needs[class] <= 0 && nongroup_needs[class] > 0)
1911 for (i = 0; i < n_spills; i++)
1913 int regno = spill_regs[i];
1914 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1915 && !TEST_HARD_REG_BIT (chain->counted_for_groups, regno)
1916 && !TEST_HARD_REG_BIT (chain->counted_for_nongroups, regno)
1917 && nongroup_needs[class] > 0)
1919 register enum reg_class *p;
1921 SET_HARD_REG_BIT (chain->counted_for_nongroups, regno);
1922 nongroup_needs[class]--;
1923 p = reg_class_superclasses[class];
1924 while (*p != LIM_REG_CLASSES)
1925 nongroup_needs[(int) *p++]--;
1929 if (simple_needs[class] <= 0 && nongroup_needs[class] <= 0)
1932 /* Consider the potential reload regs that aren't
1933 yet in use as reload regs, in order of preference.
1934 Find the most preferred one that's in this class. */
1936 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1938 int regno = potential_reload_regs[i];
1940 && TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1941 /* If this reg will not be available for groups,
1942 pick one that does not foreclose possible groups.
1943 This is a kludge, and not very general,
1944 but it should be sufficient to make the 386 work,
1945 and the problem should not occur on machines with
1947 && (nongroup_needs[class] == 0
1948 || possible_group_p (chain, regno)))
1952 /* If we couldn't get a register, try to get one even if we
1953 might foreclose possible groups. This may cause problems
1954 later, but that's better than aborting now, since it is
1955 possible that we will, in fact, be able to form the needed
1956 group even with this allocation. */
1958 if (i >= FIRST_PSEUDO_REGISTER
1959 && asm_noperands (chain->insn) < 0)
1960 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1961 if (potential_reload_regs[i] >= 0
1962 && TEST_HARD_REG_BIT (reg_class_contents[class],
1963 potential_reload_regs[i]))
1966 /* I should be the index in potential_reload_regs
1967 of the new reload reg we have found. */
1969 new_spill_reg (chain, i, class, 1, dumpfile);
1975 /* We know which hard regs to use, now mark the pseudos that live in them
1976 as needing to be kicked out. */
1977 EXECUTE_IF_SET_IN_REG_SET
1978 (chain->live_before, FIRST_PSEUDO_REGISTER, i,
1980 maybe_mark_pseudo_spilled (i);
1982 EXECUTE_IF_SET_IN_REG_SET
1983 (chain->live_after, FIRST_PSEUDO_REGISTER, i,
1985 maybe_mark_pseudo_spilled (i);
1988 IOR_HARD_REG_SET (used_spill_regs, chain->used_spill_regs);
1992 dump_needs (chain, dumpfile)
1993 struct insn_chain *chain;
1996 static char *reg_class_names[] = REG_CLASS_NAMES;
1998 struct needs *n = &chain->need;
2000 for (i = 0; i < N_REG_CLASSES; i++)
2002 if (n->regs[i][0] > 0)
2004 ";; Need %d reg%s of class %s.\n",
2005 n->regs[i][0], n->regs[i][0] == 1 ? "" : "s",
2006 reg_class_names[i]);
2007 if (n->regs[i][1] > 0)
2009 ";; Need %d nongroup reg%s of class %s.\n",
2010 n->regs[i][1], n->regs[i][1] == 1 ? "" : "s",
2011 reg_class_names[i]);
2012 if (n->groups[i] > 0)
2014 ";; Need %d group%s (%smode) of class %s.\n",
2015 n->groups[i], n->groups[i] == 1 ? "" : "s",
2016 mode_name[(int) chain->group_mode[i]],
2017 reg_class_names[i]);
2021 /* Delete all insns that were inserted by emit_caller_save_insns during
2024 delete_caller_save_insns ()
2026 struct insn_chain *c = reload_insn_chain;
2030 while (c != 0 && c->is_caller_save_insn)
2032 struct insn_chain *next = c->next;
2035 if (insn == basic_block_head[c->block])
2036 basic_block_head[c->block] = NEXT_INSN (insn);
2037 if (insn == basic_block_end[c->block])
2038 basic_block_end[c->block] = PREV_INSN (insn);
2039 if (c == reload_insn_chain)
2040 reload_insn_chain = next;
2042 if (NEXT_INSN (insn) != 0)
2043 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2044 if (PREV_INSN (insn) != 0)
2045 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2048 next->prev = c->prev;
2050 c->prev->next = next;
2051 c->next = unused_insn_chains;
2052 unused_insn_chains = c;
2060 /* Nonzero if, after spilling reg REGNO for non-groups,
2061 it will still be possible to find a group if we still need one. */
2064 possible_group_p (chain, regno)
2065 struct insn_chain *chain;
2069 int class = (int) NO_REGS;
2071 for (i = 0; i < (int) N_REG_CLASSES; i++)
2072 if (chain->need.groups[i] > 0)
2078 if (class == (int) NO_REGS)
2081 /* Consider each pair of consecutive registers. */
2082 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
2084 /* Ignore pairs that include reg REGNO. */
2085 if (i == regno || i + 1 == regno)
2088 /* Ignore pairs that are outside the class that needs the group.
2089 ??? Here we fail to handle the case where two different classes
2090 independently need groups. But this never happens with our
2091 current machine descriptions. */
2092 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
2093 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
2096 /* A pair of consecutive regs we can still spill does the trick. */
2097 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
2098 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2099 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
2102 /* A pair of one already spilled and one we can spill does it
2103 provided the one already spilled is not otherwise reserved. */
2104 if (spill_reg_order[i] < 0
2105 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2106 && spill_reg_order[i + 1] >= 0
2107 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, i + 1)
2108 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, i + 1))
2110 if (spill_reg_order[i + 1] < 0
2111 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
2112 && spill_reg_order[i] >= 0
2113 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, i)
2114 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, i))
2121 /* Count any groups of CLASS that can be formed from the registers recently
2125 count_possible_groups (chain, class)
2126 struct insn_chain *chain;
2132 /* Now find all consecutive groups of spilled registers
2133 and mark each group off against the need for such groups.
2134 But don't count them against ordinary need, yet. */
2136 if (chain->group_size[class] == 0)
2139 CLEAR_HARD_REG_SET (new);
2141 /* Make a mask of all the regs that are spill regs in class I. */
2142 for (i = 0; i < n_spills; i++)
2144 int regno = spill_regs[i];
2146 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
2147 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, regno)
2148 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, regno))
2149 SET_HARD_REG_BIT (new, regno);
2152 /* Find each consecutive group of them. */
2153 for (i = 0; i < FIRST_PSEUDO_REGISTER && chain->need.groups[class] > 0; i++)
2154 if (TEST_HARD_REG_BIT (new, i)
2155 && i + chain->group_size[class] <= FIRST_PSEUDO_REGISTER
2156 && HARD_REGNO_MODE_OK (i, chain->group_mode[class]))
2158 for (j = 1; j < chain->group_size[class]; j++)
2159 if (! TEST_HARD_REG_BIT (new, i + j))
2162 if (j == chain->group_size[class])
2164 /* We found a group. Mark it off against this class's need for
2165 groups, and against each superclass too. */
2166 register enum reg_class *p;
2168 chain->need.groups[class]--;
2169 p = reg_class_superclasses[class];
2170 while (*p != LIM_REG_CLASSES)
2172 if (chain->group_size [(int) *p] <= chain->group_size [class])
2173 chain->need.groups[(int) *p]--;
2177 /* Don't count these registers again. */
2178 for (j = 0; j < chain->group_size[class]; j++)
2179 SET_HARD_REG_BIT (chain->counted_for_groups, i + j);
2182 /* Skip to the last reg in this group. When i is incremented above,
2183 it will then point to the first reg of the next possible group. */
2188 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2189 another mode that needs to be reloaded for the same register class CLASS.
2190 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2191 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2193 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2194 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2195 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2196 causes unnecessary failures on machines requiring alignment of register
2197 groups when the two modes are different sizes, because the larger mode has
2198 more strict alignment rules than the smaller mode. */
2201 modes_equiv_for_class_p (allocate_mode, other_mode, class)
2202 enum machine_mode allocate_mode, other_mode;
2203 enum reg_class class;
2206 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2208 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
2209 && HARD_REGNO_MODE_OK (regno, allocate_mode)
2210 && ! HARD_REGNO_MODE_OK (regno, other_mode))
2216 /* Handle the failure to find a register to spill.
2217 INSN should be one of the insns which needed this particular spill reg. */
2220 spill_failure (insn)
2223 if (asm_noperands (PATTERN (insn)) >= 0)
2224 error_for_asm (insn, "`asm' needs too many reloads");
2226 fatal_insn ("Unable to find a register to spill.", insn);
2229 /* Add a new register to the tables of available spill-registers.
2230 CHAIN is the insn for which the register will be used; we decrease the
2232 I is the index of this register in potential_reload_regs.
2233 CLASS is the regclass whose need is being satisfied.
2234 NONGROUP is 0 if this register is part of a group.
2235 DUMPFILE is the same as the one that `reload' got. */
2238 new_spill_reg (chain, i, class, nongroup, dumpfile)
2239 struct insn_chain *chain;
2245 register enum reg_class *p;
2246 int regno = potential_reload_regs[i];
2248 if (i >= FIRST_PSEUDO_REGISTER)
2250 spill_failure (chain->insn);
2255 if (TEST_HARD_REG_BIT (bad_spill_regs, regno))
2257 static char *reg_class_names[] = REG_CLASS_NAMES;
2259 if (asm_noperands (PATTERN (chain->insn)) < 0)
2261 /* The error message is still correct - we know only that it wasn't
2262 an asm statement that caused the problem, but one of the global
2263 registers declared by the users might have screwed us. */
2264 error ("fixed or forbidden register %d (%s) was spilled for class %s.",
2265 regno, reg_names[regno], reg_class_names[class]);
2266 error ("This may be due to a compiler bug or to impossible asm");
2267 error ("statements or clauses.");
2268 fatal_insn ("This is the instruction:", chain->insn);
2270 error_for_asm (chain->insn, "Invalid `asm' statement:");
2271 error_for_asm (chain->insn,
2272 "fixed or forbidden register %d (%s) was spilled for class %s.",
2273 regno, reg_names[regno], reg_class_names[class]);
2278 /* Make reg REGNO an additional reload reg. */
2280 potential_reload_regs[i] = -1;
2281 spill_regs[n_spills] = regno;
2282 spill_reg_order[regno] = n_spills;
2284 fprintf (dumpfile, "Spilling reg %d.\n", regno);
2285 SET_HARD_REG_BIT (chain->used_spill_regs, regno);
2287 /* Clear off the needs we just satisfied. */
2289 chain->need.regs[0][class]--;
2290 p = reg_class_superclasses[class];
2291 while (*p != LIM_REG_CLASSES)
2292 chain->need.regs[0][(int) *p++]--;
2294 if (nongroup && chain->need.regs[1][class] > 0)
2296 SET_HARD_REG_BIT (chain->counted_for_nongroups, regno);
2297 chain->need.regs[1][class]--;
2298 p = reg_class_superclasses[class];
2299 while (*p != LIM_REG_CLASSES)
2300 chain->need.regs[1][(int) *p++]--;
2306 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2307 data that is dead in INSN. */
2310 delete_dead_insn (insn)
2313 rtx prev = prev_real_insn (insn);
2316 /* If the previous insn sets a register that dies in our insn, delete it
2318 if (prev && GET_CODE (PATTERN (prev)) == SET
2319 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2320 && reg_mentioned_p (prev_dest, PATTERN (insn))
2321 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2322 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2323 delete_dead_insn (prev);
2325 PUT_CODE (insn, NOTE);
2326 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2327 NOTE_SOURCE_FILE (insn) = 0;
2330 /* Modify the home of pseudo-reg I.
2331 The new home is present in reg_renumber[I].
2333 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2334 or it may be -1, meaning there is none or it is not relevant.
2335 This is used so that all pseudos spilled from a given hard reg
2336 can share one stack slot. */
2339 alter_reg (i, from_reg)
2343 /* When outputting an inline function, this can happen
2344 for a reg that isn't actually used. */
2345 if (regno_reg_rtx[i] == 0)
2348 /* If the reg got changed to a MEM at rtl-generation time,
2350 if (GET_CODE (regno_reg_rtx[i]) != REG)
2353 /* Modify the reg-rtx to contain the new hard reg
2354 number or else to contain its pseudo reg number. */
2355 REGNO (regno_reg_rtx[i])
2356 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2358 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2359 allocate a stack slot for it. */
2361 if (reg_renumber[i] < 0
2362 && REG_N_REFS (i) > 0
2363 && reg_equiv_constant[i] == 0
2364 && reg_equiv_memory_loc[i] == 0)
2367 int inherent_size = PSEUDO_REGNO_BYTES (i);
2368 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2371 /* Each pseudo reg has an inherent size which comes from its own mode,
2372 and a total size which provides room for paradoxical subregs
2373 which refer to the pseudo reg in wider modes.
2375 We can use a slot already allocated if it provides both
2376 enough inherent space and enough total space.
2377 Otherwise, we allocate a new slot, making sure that it has no less
2378 inherent space, and no less total space, then the previous slot. */
2381 /* No known place to spill from => no slot to reuse. */
2382 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
2383 inherent_size == total_size ? 0 : -1);
2384 if (BYTES_BIG_ENDIAN)
2385 /* Cancel the big-endian correction done in assign_stack_local.
2386 Get the address of the beginning of the slot.
2387 This is so we can do a big-endian correction unconditionally
2389 adjust = inherent_size - total_size;
2391 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2393 /* Reuse a stack slot if possible. */
2394 else if (spill_stack_slot[from_reg] != 0
2395 && spill_stack_slot_width[from_reg] >= total_size
2396 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2398 x = spill_stack_slot[from_reg];
2399 /* Allocate a bigger slot. */
2402 /* Compute maximum size needed, both for inherent size
2403 and for total size. */
2404 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2406 if (spill_stack_slot[from_reg])
2408 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2410 mode = GET_MODE (spill_stack_slot[from_reg]);
2411 if (spill_stack_slot_width[from_reg] > total_size)
2412 total_size = spill_stack_slot_width[from_reg];
2414 /* Make a slot with that size. */
2415 x = assign_stack_local (mode, total_size,
2416 inherent_size == total_size ? 0 : -1);
2418 if (BYTES_BIG_ENDIAN)
2420 /* Cancel the big-endian correction done in assign_stack_local.
2421 Get the address of the beginning of the slot.
2422 This is so we can do a big-endian correction unconditionally
2424 adjust = GET_MODE_SIZE (mode) - total_size;
2426 stack_slot = gen_rtx_MEM (mode_for_size (total_size
2429 plus_constant (XEXP (x, 0), adjust));
2431 spill_stack_slot[from_reg] = stack_slot;
2432 spill_stack_slot_width[from_reg] = total_size;
2435 /* On a big endian machine, the "address" of the slot
2436 is the address of the low part that fits its inherent mode. */
2437 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2438 adjust += (total_size - inherent_size);
2440 /* If we have any adjustment to make, or if the stack slot is the
2441 wrong mode, make a new stack slot. */
2442 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2444 x = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
2445 plus_constant (XEXP (x, 0), adjust));
2447 /* If this was shared among registers, must ensure we never
2448 set it readonly since that can cause scheduling
2449 problems. Note we would only have in this adjustment
2450 case in any event, since the code above doesn't set it. */
2453 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2456 /* Save the stack slot for later. */
2457 reg_equiv_memory_loc[i] = x;
2461 /* Mark the slots in regs_ever_live for the hard regs
2462 used by pseudo-reg number REGNO. */
2465 mark_home_live (regno)
2468 register int i, lim;
2469 i = reg_renumber[regno];
2472 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2474 regs_ever_live[i++] = 1;
2477 /* This function handles the tracking of elimination offsets around branches.
2479 X is a piece of RTL being scanned.
2481 INSN is the insn that it came from, if any.
2483 INITIAL_P is non-zero if we are to set the offset to be the initial
2484 offset and zero if we are setting the offset of the label to be the
2488 set_label_offsets (x, insn, initial_p)
2493 enum rtx_code code = GET_CODE (x);
2496 struct elim_table *p;
2501 if (LABEL_REF_NONLOCAL_P (x))
2506 /* ... fall through ... */
2509 /* If we know nothing about this label, set the desired offsets. Note
2510 that this sets the offset at a label to be the offset before a label
2511 if we don't know anything about the label. This is not correct for
2512 the label after a BARRIER, but is the best guess we can make. If
2513 we guessed wrong, we will suppress an elimination that might have
2514 been possible had we been able to guess correctly. */
2516 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2518 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2519 offsets_at[CODE_LABEL_NUMBER (x)][i]
2520 = (initial_p ? reg_eliminate[i].initial_offset
2521 : reg_eliminate[i].offset);
2522 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2525 /* Otherwise, if this is the definition of a label and it is
2526 preceded by a BARRIER, set our offsets to the known offset of
2530 && (tem = prev_nonnote_insn (insn)) != 0
2531 && GET_CODE (tem) == BARRIER)
2532 set_offsets_for_label (insn);
2534 /* If neither of the above cases is true, compare each offset
2535 with those previously recorded and suppress any eliminations
2536 where the offsets disagree. */
2538 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2539 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2540 != (initial_p ? reg_eliminate[i].initial_offset
2541 : reg_eliminate[i].offset))
2542 reg_eliminate[i].can_eliminate = 0;
2547 set_label_offsets (PATTERN (insn), insn, initial_p);
2549 /* ... fall through ... */
2553 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2554 and hence must have all eliminations at their initial offsets. */
2555 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2556 if (REG_NOTE_KIND (tem) == REG_LABEL)
2557 set_label_offsets (XEXP (tem, 0), insn, 1);
2562 /* Each of the labels in the address vector must be at their initial
2563 offsets. We want the first field for ADDR_VEC and the second
2564 field for ADDR_DIFF_VEC. */
2566 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2567 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2572 /* We only care about setting PC. If the source is not RETURN,
2573 IF_THEN_ELSE, or a label, disable any eliminations not at
2574 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2575 isn't one of those possibilities. For branches to a label,
2576 call ourselves recursively.
2578 Note that this can disable elimination unnecessarily when we have
2579 a non-local goto since it will look like a non-constant jump to
2580 someplace in the current function. This isn't a significant
2581 problem since such jumps will normally be when all elimination
2582 pairs are back to their initial offsets. */
2584 if (SET_DEST (x) != pc_rtx)
2587 switch (GET_CODE (SET_SRC (x)))
2594 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2598 tem = XEXP (SET_SRC (x), 1);
2599 if (GET_CODE (tem) == LABEL_REF)
2600 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2601 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2604 tem = XEXP (SET_SRC (x), 2);
2605 if (GET_CODE (tem) == LABEL_REF)
2606 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2607 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2615 /* If we reach here, all eliminations must be at their initial
2616 offset because we are doing a jump to a variable address. */
2617 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2618 if (p->offset != p->initial_offset)
2619 p->can_eliminate = 0;
2627 /* Used for communication between the next two function to properly share
2628 the vector for an ASM_OPERANDS. */
2630 static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2632 /* Scan X and replace any eliminable registers (such as fp) with a
2633 replacement (such as sp), plus an offset.
2635 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2636 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2637 MEM, we are allowed to replace a sum of a register and the constant zero
2638 with the register, which we cannot do outside a MEM. In addition, we need
2639 to record the fact that a register is referenced outside a MEM.
2641 If INSN is an insn, it is the insn containing X. If we replace a REG
2642 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2643 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2644 the REG is being modified.
2646 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2647 That's used when we eliminate in expressions stored in notes.
2648 This means, do not set ref_outside_mem even if the reference
2651 If we see a modification to a register we know about, take the
2652 appropriate action (see case SET, below).
2654 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2655 replacements done assuming all offsets are at their initial values. If
2656 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2657 encounter, return the actual location so that find_reloads will do
2658 the proper thing. */
2661 eliminate_regs (x, mem_mode, insn)
2663 enum machine_mode mem_mode;
2666 enum rtx_code code = GET_CODE (x);
2667 struct elim_table *ep;
2674 if (! current_function_decl)
2693 /* This is only for the benefit of the debugging backends, which call
2694 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2695 removed after CSE. */
2696 new = eliminate_regs (XEXP (x, 0), 0, insn);
2697 if (GET_CODE (new) == MEM)
2698 return XEXP (new, 0);
2704 /* First handle the case where we encounter a bare register that
2705 is eliminable. Replace it with a PLUS. */
2706 if (regno < FIRST_PSEUDO_REGISTER)
2708 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2710 if (ep->from_rtx == x && ep->can_eliminate)
2713 /* Refs inside notes don't count for this purpose. */
2714 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2715 || GET_CODE (insn) == INSN_LIST)))
2716 ep->ref_outside_mem = 1;
2717 return plus_constant (ep->to_rtx, ep->previous_offset);
2721 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2722 && reg_equiv_constant[regno]
2723 && ! CONSTANT_P (reg_equiv_constant[regno]))
2724 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2729 /* If this is the sum of an eliminable register and a constant, rework
2731 if (GET_CODE (XEXP (x, 0)) == REG
2732 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2733 && CONSTANT_P (XEXP (x, 1)))
2735 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2737 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2740 /* Refs inside notes don't count for this purpose. */
2741 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2742 || GET_CODE (insn) == INSN_LIST)))
2743 ep->ref_outside_mem = 1;
2745 /* The only time we want to replace a PLUS with a REG (this
2746 occurs when the constant operand of the PLUS is the negative
2747 of the offset) is when we are inside a MEM. We won't want
2748 to do so at other times because that would change the
2749 structure of the insn in a way that reload can't handle.
2750 We special-case the commonest situation in
2751 eliminate_regs_in_insn, so just replace a PLUS with a
2752 PLUS here, unless inside a MEM. */
2753 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2754 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2757 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2758 plus_constant (XEXP (x, 1),
2759 ep->previous_offset));
2762 /* If the register is not eliminable, we are done since the other
2763 operand is a constant. */
2767 /* If this is part of an address, we want to bring any constant to the
2768 outermost PLUS. We will do this by doing register replacement in
2769 our operands and seeing if a constant shows up in one of them.
2771 We assume here this is part of an address (or a "load address" insn)
2772 since an eliminable register is not likely to appear in any other
2775 If we have (plus (eliminable) (reg)), we want to produce
2776 (plus (plus (replacement) (reg) (const))). If this was part of a
2777 normal add insn, (plus (replacement) (reg)) will be pushed as a
2778 reload. This is the desired action. */
2781 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2782 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2784 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2786 /* If one side is a PLUS and the other side is a pseudo that
2787 didn't get a hard register but has a reg_equiv_constant,
2788 we must replace the constant here since it may no longer
2789 be in the position of any operand. */
2790 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2791 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2792 && reg_renumber[REGNO (new1)] < 0
2793 && reg_equiv_constant != 0
2794 && reg_equiv_constant[REGNO (new1)] != 0)
2795 new1 = reg_equiv_constant[REGNO (new1)];
2796 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2797 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2798 && reg_renumber[REGNO (new0)] < 0
2799 && reg_equiv_constant[REGNO (new0)] != 0)
2800 new0 = reg_equiv_constant[REGNO (new0)];
2802 new = form_sum (new0, new1);
2804 /* As above, if we are not inside a MEM we do not want to
2805 turn a PLUS into something else. We might try to do so here
2806 for an addition of 0 if we aren't optimizing. */
2807 if (! mem_mode && GET_CODE (new) != PLUS)
2808 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2816 /* If this is the product of an eliminable register and a
2817 constant, apply the distribute law and move the constant out
2818 so that we have (plus (mult ..) ..). This is needed in order
2819 to keep load-address insns valid. This case is pathological.
2820 We ignore the possibility of overflow here. */
2821 if (GET_CODE (XEXP (x, 0)) == REG
2822 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2823 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2824 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2826 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2829 /* Refs inside notes don't count for this purpose. */
2830 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2831 || GET_CODE (insn) == INSN_LIST)))
2832 ep->ref_outside_mem = 1;
2835 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2836 ep->previous_offset * INTVAL (XEXP (x, 1)));
2839 /* ... fall through ... */
2844 case DIV: case UDIV:
2845 case MOD: case UMOD:
2846 case AND: case IOR: case XOR:
2847 case ROTATERT: case ROTATE:
2848 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2850 case GE: case GT: case GEU: case GTU:
2851 case LE: case LT: case LEU: case LTU:
2853 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2855 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2857 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2858 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2863 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2866 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2867 if (new != XEXP (x, 0))
2868 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2871 /* ... fall through ... */
2874 /* Now do eliminations in the rest of the chain. If this was
2875 an EXPR_LIST, this might result in allocating more memory than is
2876 strictly needed, but it simplifies the code. */
2879 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2880 if (new != XEXP (x, 1))
2881 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2889 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2890 if (ep->to_rtx == XEXP (x, 0))
2892 int size = GET_MODE_SIZE (mem_mode);
2894 /* If more bytes than MEM_MODE are pushed, account for them. */
2895 #ifdef PUSH_ROUNDING
2896 if (ep->to_rtx == stack_pointer_rtx)
2897 size = PUSH_ROUNDING (size);
2899 if (code == PRE_DEC || code == POST_DEC)
2905 /* Fall through to generic unary operation case. */
2906 case STRICT_LOW_PART:
2908 case SIGN_EXTEND: case ZERO_EXTEND:
2909 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2910 case FLOAT: case FIX:
2911 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2915 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2916 if (new != XEXP (x, 0))
2917 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2921 /* Similar to above processing, but preserve SUBREG_WORD.
2922 Convert (subreg (mem)) to (mem) if not paradoxical.
2923 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2924 pseudo didn't get a hard reg, we must replace this with the
2925 eliminated version of the memory location because push_reloads
2926 may do the replacement in certain circumstances. */
2927 if (GET_CODE (SUBREG_REG (x)) == REG
2928 && (GET_MODE_SIZE (GET_MODE (x))
2929 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2930 && reg_equiv_memory_loc != 0
2931 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2934 new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
2937 /* If we didn't change anything, we must retain the pseudo. */
2938 if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
2939 new = SUBREG_REG (x);
2942 /* In this case, we must show that the pseudo is used in this
2943 insn so that delete_output_reload will do the right thing. */
2944 if (insn != 0 && GET_CODE (insn) != EXPR_LIST
2945 && GET_CODE (insn) != INSN_LIST)
2946 REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode,
2949 = gen_rtx_EXPR_LIST (REG_EQUAL, new, NULL_RTX);
2951 /* Ensure NEW isn't shared in case we have to reload it. */
2952 new = copy_rtx (new);
2955 new = SUBREG_REG (x);
2959 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2961 if (new != XEXP (x, 0))
2963 int x_size = GET_MODE_SIZE (GET_MODE (x));
2964 int new_size = GET_MODE_SIZE (GET_MODE (new));
2966 if (GET_CODE (new) == MEM
2967 && ((x_size < new_size
2968 #ifdef WORD_REGISTER_OPERATIONS
2969 /* On these machines, combine can create rtl of the form
2970 (set (subreg:m1 (reg:m2 R) 0) ...)
2971 where m1 < m2, and expects something interesting to
2972 happen to the entire word. Moreover, it will use the
2973 (reg:m2 R) later, expecting all bits to be preserved.
2974 So if the number of words is the same, preserve the
2975 subreg so that push_reloads can see it. */
2976 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
2979 || (x_size == new_size))
2982 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2983 enum machine_mode mode = GET_MODE (x);
2985 if (BYTES_BIG_ENDIAN)
2986 offset += (MIN (UNITS_PER_WORD,
2987 GET_MODE_SIZE (GET_MODE (new)))
2988 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2990 PUT_MODE (new, mode);
2991 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2995 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
3001 /* If using a register that is the source of an eliminate we still
3002 think can be performed, note it cannot be performed since we don't
3003 know how this register is used. */
3004 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3005 if (ep->from_rtx == XEXP (x, 0))
3006 ep->can_eliminate = 0;
3008 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3009 if (new != XEXP (x, 0))
3010 return gen_rtx_fmt_e (code, GET_MODE (x), new);
3014 /* If clobbering a register that is the replacement register for an
3015 elimination we still think can be performed, note that it cannot
3016 be performed. Otherwise, we need not be concerned about it. */
3017 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3018 if (ep->to_rtx == XEXP (x, 0))
3019 ep->can_eliminate = 0;
3021 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3022 if (new != XEXP (x, 0))
3023 return gen_rtx_fmt_e (code, GET_MODE (x), new);
3029 /* Properly handle sharing input and constraint vectors. */
3030 if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
3032 /* When we come to a new vector not seen before,
3033 scan all its elements; keep the old vector if none
3034 of them changes; otherwise, make a copy. */
3035 old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
3036 temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
3037 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3038 temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
3041 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3042 if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
3045 if (i == ASM_OPERANDS_INPUT_LENGTH (x))
3046 new_asm_operands_vec = old_asm_operands_vec;
3048 new_asm_operands_vec
3049 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
3052 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
3053 if (new_asm_operands_vec == old_asm_operands_vec)
3056 new = gen_rtx_ASM_OPERANDS (VOIDmode, ASM_OPERANDS_TEMPLATE (x),
3057 ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
3058 ASM_OPERANDS_OUTPUT_IDX (x),
3059 new_asm_operands_vec,
3060 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
3061 ASM_OPERANDS_SOURCE_FILE (x),
3062 ASM_OPERANDS_SOURCE_LINE (x));
3063 new->volatil = x->volatil;
3068 /* Check for setting a register that we know about. */
3069 if (GET_CODE (SET_DEST (x)) == REG)
3071 /* See if this is setting the replacement register for an
3074 If DEST is the hard frame pointer, we do nothing because we
3075 assume that all assignments to the frame pointer are for
3076 non-local gotos and are being done at a time when they are valid
3077 and do not disturb anything else. Some machines want to
3078 eliminate a fake argument pointer (or even a fake frame pointer)
3079 with either the real frame or the stack pointer. Assignments to
3080 the hard frame pointer must not prevent this elimination. */
3082 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3084 if (ep->to_rtx == SET_DEST (x)
3085 && SET_DEST (x) != hard_frame_pointer_rtx)
3087 /* If it is being incremented, adjust the offset. Otherwise,
3088 this elimination can't be done. */
3089 rtx src = SET_SRC (x);
3091 if (GET_CODE (src) == PLUS
3092 && XEXP (src, 0) == SET_DEST (x)
3093 && GET_CODE (XEXP (src, 1)) == CONST_INT)
3094 ep->offset -= INTVAL (XEXP (src, 1));
3096 ep->can_eliminate = 0;
3099 /* Now check to see we are assigning to a register that can be
3100 eliminated. If so, it must be as part of a PARALLEL, since we
3101 will not have been called if this is a single SET. So indicate
3102 that we can no longer eliminate this reg. */
3103 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3105 if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
3106 ep->can_eliminate = 0;
3109 /* Now avoid the loop below in this common case. */
3111 rtx new0 = eliminate_regs (SET_DEST (x), 0, insn);
3112 rtx new1 = eliminate_regs (SET_SRC (x), 0, insn);
3114 /* If SET_DEST changed from a REG to a MEM and INSN is an insn,
3115 write a CLOBBER insn. */
3116 if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
3117 && insn != 0 && GET_CODE (insn) != EXPR_LIST
3118 && GET_CODE (insn) != INSN_LIST)
3119 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, SET_DEST (x)), insn);
3121 if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
3122 return gen_rtx_SET (VOIDmode, new0, new1);
3128 /* This is only for the benefit of the debugging backends, which call
3129 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
3130 removed after CSE. */
3131 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
3132 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
3134 /* Our only special processing is to pass the mode of the MEM to our
3135 recursive call and copy the flags. While we are here, handle this
3136 case more efficiently. */
3137 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
3138 if (new != XEXP (x, 0))
3140 new = gen_rtx_MEM (GET_MODE (x), new);
3141 new->volatil = x->volatil;
3142 new->unchanging = x->unchanging;
3143 new->in_struct = x->in_struct;
3153 /* Process each of our operands recursively. If any have changed, make a
3155 fmt = GET_RTX_FORMAT (code);
3156 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3160 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
3161 if (new != XEXP (x, i) && ! copied)
3163 rtx new_x = rtx_alloc (code);
3164 bcopy ((char *) x, (char *) new_x,
3165 (sizeof (*new_x) - sizeof (new_x->fld)
3166 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
3172 else if (*fmt == 'E')
3175 for (j = 0; j < XVECLEN (x, i); j++)
3177 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
3178 if (new != XVECEXP (x, i, j) && ! copied_vec)
3180 rtvec new_v = gen_rtvec_vv (XVECLEN (x, i),
3184 rtx new_x = rtx_alloc (code);
3185 bcopy ((char *) x, (char *) new_x,
3186 (sizeof (*new_x) - sizeof (new_x->fld)
3187 + (sizeof (new_x->fld[0])
3188 * GET_RTX_LENGTH (code))));
3192 XVEC (x, i) = new_v;
3195 XVECEXP (x, i, j) = new;
3203 /* Scan INSN and eliminate all eliminable registers in it.
3205 If REPLACE is nonzero, do the replacement destructively. Also
3206 delete the insn as dead it if it is setting an eliminable register.
3208 If REPLACE is zero, do all our allocations in reload_obstack.
3210 If no eliminations were done and this insn doesn't require any elimination
3211 processing (these are not identical conditions: it might be updating sp,
3212 but not referencing fp; this needs to be seen during reload_as_needed so
3213 that the offset between fp and sp can be taken into consideration), zero
3214 is returned. Otherwise, 1 is returned. */
3217 eliminate_regs_in_insn (insn, replace)
3221 rtx old_body = PATTERN (insn);
3222 rtx old_set = single_set (insn);
3225 struct elim_table *ep;
3228 push_obstacks (&reload_obstack, &reload_obstack);
3230 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
3231 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3233 /* Check for setting an eliminable register. */
3234 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3235 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3237 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3238 /* If this is setting the frame pointer register to the
3239 hardware frame pointer register and this is an elimination
3240 that will be done (tested above), this insn is really
3241 adjusting the frame pointer downward to compensate for
3242 the adjustment done before a nonlocal goto. */
3243 if (ep->from == FRAME_POINTER_REGNUM
3244 && ep->to == HARD_FRAME_POINTER_REGNUM)
3246 rtx src = SET_SRC (old_set);
3248 rtx prev_insn, prev_set;
3250 if (src == ep->to_rtx)
3252 else if (GET_CODE (src) == PLUS
3253 && GET_CODE (XEXP (src, 0)) == CONST_INT
3254 && XEXP (src, 1) == ep->to_rtx)
3255 offset = INTVAL (XEXP (src, 0)), ok = 1;
3256 else if (GET_CODE (src) == PLUS
3257 && GET_CODE (XEXP (src, 1)) == CONST_INT
3258 && XEXP (src, 0) == ep->to_rtx)
3259 offset = INTVAL (XEXP (src, 1)), ok = 1;
3260 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
3261 && (prev_set = single_set (prev_insn)) != 0
3262 && rtx_equal_p (SET_DEST (prev_set), src))
3264 src = SET_SRC (prev_set);
3265 if (src == ep->to_rtx)
3267 else if (GET_CODE (src) == PLUS
3268 && GET_CODE (XEXP (src, 0)) == CONST_INT
3269 && XEXP (src, 1) == ep->to_rtx)
3270 offset = INTVAL (XEXP (src, 0)), ok = 1;
3271 else if (GET_CODE (src) == PLUS
3272 && GET_CODE (XEXP (src, 1)) == CONST_INT
3273 && XEXP (src, 0) == ep->to_rtx)
3274 offset = INTVAL (XEXP (src, 1)), ok = 1;
3282 = plus_constant (ep->to_rtx, offset - ep->offset);
3284 /* First see if this insn remains valid when we
3285 make the change. If not, keep the INSN_CODE
3286 the same and let reload fit it up. */
3287 validate_change (insn, &SET_SRC (old_set), src, 1);
3288 validate_change (insn, &SET_DEST (old_set),
3290 if (! apply_change_group ())
3292 SET_SRC (old_set) = src;
3293 SET_DEST (old_set) = ep->to_rtx;
3303 /* In this case this insn isn't serving a useful purpose. We
3304 will delete it in reload_as_needed once we know that this
3305 elimination is, in fact, being done.
3307 If REPLACE isn't set, we can't delete this insn, but needn't
3308 process it since it won't be used unless something changes. */
3310 delete_dead_insn (insn);
3315 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3316 in the insn is the negative of the offset in FROM. Substitute
3317 (set (reg) (reg to)) for the insn and change its code.
3319 We have to do this here, rather than in eliminate_regs, so that we can
3320 change the insn code. */
3322 if (GET_CODE (SET_SRC (old_set)) == PLUS
3323 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3324 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT)
3325 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3327 if (ep->from_rtx == XEXP (SET_SRC (old_set), 0)
3328 && ep->can_eliminate)
3330 /* We must stop at the first elimination that will be used.
3331 If this one would replace the PLUS with a REG, do it
3332 now. Otherwise, quit the loop and let eliminate_regs
3333 do its normal replacement. */
3334 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_set), 1)))
3336 /* We assume here that we don't need a PARALLEL of
3337 any CLOBBERs for this assignment. There's not
3338 much we can do if we do need it. */
3339 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3342 INSN_CODE (insn) = -1;
3351 old_asm_operands_vec = 0;
3353 /* Replace the body of this insn with a substituted form. If we changed
3354 something, return non-zero.
3356 If we are replacing a body that was a (set X (plus Y Z)), try to
3357 re-recognize the insn. We do this in case we had a simple addition
3358 but now can do this as a load-address. This saves an insn in this
3361 new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX);
3362 if (new_body != old_body)
3364 /* If we aren't replacing things permanently and we changed something,
3365 make another copy to ensure that all the RTL is new. Otherwise
3366 things can go wrong if find_reload swaps commutative operands
3367 and one is inside RTL that has been copied while the other is not. */
3369 /* Don't copy an asm_operands because (1) there's no need and (2)
3370 copy_rtx can't do it properly when there are multiple outputs. */
3371 if (! replace && asm_noperands (old_body) < 0)
3372 new_body = copy_rtx (new_body);
3374 /* If we had a move insn but now we don't, rerecognize it. This will
3375 cause spurious re-recognition if the old move had a PARALLEL since
3376 the new one still will, but we can't call single_set without
3377 having put NEW_BODY into the insn and the re-recognition won't
3378 hurt in this rare case. */
3380 && ((GET_CODE (SET_SRC (old_set)) == REG
3381 && (GET_CODE (new_body) != SET
3382 || GET_CODE (SET_SRC (new_body)) != REG))
3383 /* If this was a load from or store to memory, compare
3384 the MEM in recog_operand to the one in the insn. If they
3385 are not equal, then rerecognize the insn. */
3387 && ((GET_CODE (SET_SRC (old_set)) == MEM
3388 && SET_SRC (old_set) != recog_operand[1])
3389 || (GET_CODE (SET_DEST (old_set)) == MEM
3390 && SET_DEST (old_set) != recog_operand[0])))
3391 /* If this was an add insn before, rerecognize. */
3392 || GET_CODE (SET_SRC (old_set)) == PLUS))
3394 if (! validate_change (insn, &PATTERN (insn), new_body, 0))
3395 /* If recognition fails, store the new body anyway.
3396 It's normal to have recognition failures here
3397 due to bizarre memory addresses; reloading will fix them. */
3398 PATTERN (insn) = new_body;
3401 PATTERN (insn) = new_body;
3406 /* Loop through all elimination pairs. See if any have changed.
3408 We also detect a cases where register elimination cannot be done,
3409 namely, if a register would be both changed and referenced outside a MEM
3410 in the resulting insn since such an insn is often undefined and, even if
3411 not, we cannot know what meaning will be given to it. Note that it is
3412 valid to have a register used in an address in an insn that changes it
3413 (presumably with a pre- or post-increment or decrement).
3415 If anything changes, return nonzero. */
3417 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3419 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3420 ep->can_eliminate = 0;
3422 ep->ref_outside_mem = 0;
3424 if (ep->previous_offset != ep->offset)
3429 /* If we changed something, perform elimination in REG_NOTES. This is
3430 needed even when REPLACE is zero because a REG_DEAD note might refer
3431 to a register that we eliminate and could cause a different number
3432 of spill registers to be needed in the final reload pass than in
3434 if (val && REG_NOTES (insn) != 0)
3435 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3443 /* Loop through all elimination pairs.
3444 Recalculate the number not at initial offset.
3446 Compute the maximum offset (minimum offset if the stack does not
3447 grow downward) for each elimination pair. */
3450 update_eliminable_offsets ()
3452 struct elim_table *ep;
3454 num_not_at_initial_offset = 0;
3455 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3457 ep->previous_offset = ep->offset;
3458 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3459 num_not_at_initial_offset++;
3463 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3464 replacement we currently believe is valid, mark it as not eliminable if X
3465 modifies DEST in any way other than by adding a constant integer to it.
3467 If DEST is the frame pointer, we do nothing because we assume that
3468 all assignments to the hard frame pointer are nonlocal gotos and are being
3469 done at a time when they are valid and do not disturb anything else.
3470 Some machines want to eliminate a fake argument pointer with either the
3471 frame or stack pointer. Assignments to the hard frame pointer must not
3472 prevent this elimination.
3474 Called via note_stores from reload before starting its passes to scan
3475 the insns of the function. */
3478 mark_not_eliminable (dest, x)
3482 register unsigned int i;
3484 /* A SUBREG of a hard register here is just changing its mode. We should
3485 not see a SUBREG of an eliminable hard register, but check just in
3487 if (GET_CODE (dest) == SUBREG)
3488 dest = SUBREG_REG (dest);
3490 if (dest == hard_frame_pointer_rtx)
3493 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3494 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3495 && (GET_CODE (x) != SET
3496 || GET_CODE (SET_SRC (x)) != PLUS
3497 || XEXP (SET_SRC (x), 0) != dest
3498 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3500 reg_eliminate[i].can_eliminate_previous
3501 = reg_eliminate[i].can_eliminate = 0;
3506 /* Verify that the initial elimination offsets did not change since the
3507 last call to set_initial_elim_offsets. This is used to catch cases
3508 where something illegal happened during reload_as_needed that could
3509 cause incorrect code to be generated if we did not check for it. */
3511 verify_initial_elim_offsets ()
3515 #ifdef ELIMINABLE_REGS
3516 struct elim_table *ep;
3518 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3520 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3521 if (t != ep->initial_offset)
3525 INITIAL_FRAME_POINTER_OFFSET (t);
3526 if (t != reg_eliminate[0].initial_offset)
3531 /* Reset all offsets on eliminable registers to their initial values. */
3533 set_initial_elim_offsets ()
3535 struct elim_table *ep = reg_eliminate;
3537 #ifdef ELIMINABLE_REGS
3538 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3540 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3541 ep->previous_offset = ep->offset = ep->initial_offset;
3544 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3545 ep->previous_offset = ep->offset = ep->initial_offset;
3548 num_not_at_initial_offset = 0;
3551 /* Initialize the known label offsets.
3552 Set a known offset for each forced label to be at the initial offset
3553 of each elimination. We do this because we assume that all
3554 computed jumps occur from a location where each elimination is
3555 at its initial offset.
3556 For all other labels, show that we don't know the offsets. */
3559 set_initial_label_offsets ()
3562 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
3564 for (x = forced_labels; x; x = XEXP (x, 1))
3566 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3569 /* Set all elimination offsets to the known values for the code label given
3572 set_offsets_for_label (insn)
3576 int label_nr = CODE_LABEL_NUMBER (insn);
3577 struct elim_table *ep;
3579 num_not_at_initial_offset = 0;
3580 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3582 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3583 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3584 num_not_at_initial_offset++;
3588 /* See if anything that happened changes which eliminations are valid.
3589 For example, on the Sparc, whether or not the frame pointer can
3590 be eliminated can depend on what registers have been used. We need
3591 not check some conditions again (such as flag_omit_frame_pointer)
3592 since they can't have changed. */
3595 update_eliminables (pset)
3598 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3599 int previous_frame_pointer_needed = frame_pointer_needed;
3601 struct elim_table *ep;
3603 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3604 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3605 #ifdef ELIMINABLE_REGS
3606 || ! CAN_ELIMINATE (ep->from, ep->to)
3609 ep->can_eliminate = 0;
3611 /* Look for the case where we have discovered that we can't replace
3612 register A with register B and that means that we will now be
3613 trying to replace register A with register C. This means we can
3614 no longer replace register C with register B and we need to disable
3615 such an elimination, if it exists. This occurs often with A == ap,
3616 B == sp, and C == fp. */
3618 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3620 struct elim_table *op;
3621 register int new_to = -1;
3623 if (! ep->can_eliminate && ep->can_eliminate_previous)
3625 /* Find the current elimination for ep->from, if there is a
3627 for (op = reg_eliminate;
3628 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3629 if (op->from == ep->from && op->can_eliminate)
3635 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3637 for (op = reg_eliminate;
3638 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3639 if (op->from == new_to && op->to == ep->to)
3640 op->can_eliminate = 0;
3644 /* See if any registers that we thought we could eliminate the previous
3645 time are no longer eliminable. If so, something has changed and we
3646 must spill the register. Also, recompute the number of eliminable
3647 registers and see if the frame pointer is needed; it is if there is
3648 no elimination of the frame pointer that we can perform. */
3650 frame_pointer_needed = 1;
3651 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3653 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3654 && ep->to != HARD_FRAME_POINTER_REGNUM)
3655 frame_pointer_needed = 0;
3657 if (! ep->can_eliminate && ep->can_eliminate_previous)
3659 ep->can_eliminate_previous = 0;
3660 SET_HARD_REG_BIT (*pset, ep->from);
3665 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3666 /* If we didn't need a frame pointer last time, but we do now, spill
3667 the hard frame pointer. */
3668 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3669 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3673 /* Initialize the table of registers to eliminate. */
3677 struct elim_table *ep;
3678 #ifdef ELIMINABLE_REGS
3679 struct elim_table_1 *ep1;
3684 reg_eliminate = (struct elim_table *)
3685 xmalloc(sizeof(struct elim_table) * NUM_ELIMINABLE_REGS);
3686 bzero ((PTR) reg_eliminate,
3687 sizeof(struct elim_table) * NUM_ELIMINABLE_REGS);
3690 /* Does this function require a frame pointer? */
3692 frame_pointer_needed = (! flag_omit_frame_pointer
3693 #ifdef EXIT_IGNORE_STACK
3694 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3695 and restore sp for alloca. So we can't eliminate
3696 the frame pointer in that case. At some point,
3697 we should improve this by emitting the
3698 sp-adjusting insns for this case. */
3699 || (current_function_calls_alloca
3700 && EXIT_IGNORE_STACK)
3702 || FRAME_POINTER_REQUIRED);
3706 #ifdef ELIMINABLE_REGS
3707 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3708 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3710 ep->from = ep1->from;
3712 ep->can_eliminate = ep->can_eliminate_previous
3713 = (CAN_ELIMINATE (ep->from, ep->to)
3714 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3717 reg_eliminate[0].from = reg_eliminate_1[0].from;
3718 reg_eliminate[0].to = reg_eliminate_1[0].to;
3719 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3720 = ! frame_pointer_needed;
3723 /* Count the number of eliminable registers and build the FROM and TO
3724 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3725 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3726 We depend on this. */
3727 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3729 num_eliminable += ep->can_eliminate;
3730 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3731 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3735 /* Kick all pseudos out of hard register REGNO.
3736 If DUMPFILE is nonzero, log actions taken on that file.
3738 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3739 because we found we can't eliminate some register. In the case, no pseudos
3740 are allowed to be in the register, even if they are only in a block that
3741 doesn't require spill registers, unlike the case when we are spilling this
3742 hard reg to produce another spill register.
3744 Return nonzero if any pseudos needed to be kicked out. */
3747 spill_hard_reg (regno, dumpfile, cant_eliminate)
3756 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3757 regs_ever_live[regno] = 1;
3760 /* Spill every pseudo reg that was allocated to this reg
3761 or to something that overlaps this reg. */
3763 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3764 if (reg_renumber[i] >= 0
3765 && reg_renumber[i] <= regno
3767 + HARD_REGNO_NREGS (reg_renumber[i],
3768 PSEUDO_REGNO_MODE (i))
3770 SET_REGNO_REG_SET (spilled_pseudos, i);
3773 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3774 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3776 ior_hard_reg_set (set1, set2)
3777 HARD_REG_SET *set1, *set2;
3779 IOR_HARD_REG_SET (*set1, *set2);
3782 /* After find_reload_regs has been run for all insn that need reloads,
3783 and/or spill_hard_regs was called, this function is used to actually
3784 spill pseudo registers and try to reallocate them. It also sets up the
3785 spill_regs array for use by choose_reload_regs. */
3788 finish_spills (global, dumpfile)
3792 struct insn_chain *chain;
3793 int something_changed = 0;
3796 /* Build the spill_regs array for the function. */
3797 /* If there are some registers still to eliminate and one of the spill regs
3798 wasn't ever used before, additional stack space may have to be
3799 allocated to store this register. Thus, we may have changed the offset
3800 between the stack and frame pointers, so mark that something has changed.
3802 One might think that we need only set VAL to 1 if this is a call-used
3803 register. However, the set of registers that must be saved by the
3804 prologue is not identical to the call-used set. For example, the
3805 register used by the call insn for the return PC is a call-used register,
3806 but must be saved by the prologue. */
3809 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3810 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3812 spill_reg_order[i] = n_spills;
3813 spill_regs[n_spills++] = i;
3814 if (num_eliminable && ! regs_ever_live[i])
3815 something_changed = 1;
3816 regs_ever_live[i] = 1;
3819 spill_reg_order[i] = -1;
3821 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3822 if (REGNO_REG_SET_P (spilled_pseudos, i))
3824 /* Record the current hard register the pseudo is allocated to in
3825 pseudo_previous_regs so we avoid reallocating it to the same
3826 hard reg in a later pass. */
3827 if (reg_renumber[i] < 0)
3829 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3830 /* Mark it as no longer having a hard register home. */
3831 reg_renumber[i] = -1;
3832 /* We will need to scan everything again. */
3833 something_changed = 1;
3836 /* Retry global register allocation if possible. */
3839 bzero ((char *) pseudo_forbidden_regs, max_regno * sizeof (HARD_REG_SET));
3840 /* For every insn that needs reloads, set the registers used as spill
3841 regs in pseudo_forbidden_regs for every pseudo live across the
3843 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3845 EXECUTE_IF_SET_IN_REG_SET
3846 (chain->live_before, FIRST_PSEUDO_REGISTER, i,
3848 ior_hard_reg_set (pseudo_forbidden_regs + i,
3849 &chain->used_spill_regs);
3851 EXECUTE_IF_SET_IN_REG_SET
3852 (chain->live_after, FIRST_PSEUDO_REGISTER, i,
3854 ior_hard_reg_set (pseudo_forbidden_regs + i,
3855 &chain->used_spill_regs);
3859 /* Retry allocating the spilled pseudos. For each reg, merge the
3860 various reg sets that indicate which hard regs can't be used,
3861 and call retry_global_alloc.
3862 We change spill_pseudos here to only contain pseudos that did not
3863 get a new hard register. */
3864 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3865 if (reg_old_renumber[i] != reg_renumber[i])
3867 HARD_REG_SET forbidden;
3868 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3869 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3870 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3871 retry_global_alloc (i, forbidden);
3872 if (reg_renumber[i] >= 0)
3873 CLEAR_REGNO_REG_SET (spilled_pseudos, i);
3877 /* Fix up the register information in the insn chain.
3878 This involves deleting those of the spilled pseudos which did not get
3879 a new hard register home from the live_{before,after} sets. */
3880 for (chain = reload_insn_chain; chain; chain = chain->next)
3882 HARD_REG_SET used_by_pseudos;
3883 HARD_REG_SET used_by_pseudos2;
3885 AND_COMPL_REG_SET (chain->live_before, spilled_pseudos);
3886 AND_COMPL_REG_SET (chain->live_after, spilled_pseudos);
3888 /* Mark any unallocated hard regs as available for spills. That
3889 makes inheritance work somewhat better. */
3890 if (chain->need_reload)
3892 REG_SET_TO_HARD_REG_SET (used_by_pseudos, chain->live_before);
3893 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, chain->live_after);
3894 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3896 /* Save the old value for the sanity test below. */
3897 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3899 compute_use_by_pseudos (&used_by_pseudos, chain->live_before);
3900 compute_use_by_pseudos (&used_by_pseudos, chain->live_after);
3901 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3902 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3904 /* Make sure we only enlarge the set. */
3905 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3911 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3912 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3914 int regno = reg_renumber[i];
3915 if (reg_old_renumber[i] == regno)
3918 alter_reg (i, reg_old_renumber[i]);
3919 reg_old_renumber[i] = regno;
3923 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3925 fprintf (dumpfile, " Register %d now in %d.\n\n",
3926 i, reg_renumber[i]);
3930 return something_changed;
3933 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3934 Also mark any hard registers used to store user variables as
3935 forbidden from being used for spill registers. */
3938 scan_paradoxical_subregs (x)
3943 register enum rtx_code code = GET_CODE (x);
3949 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3950 && REG_USERVAR_P (x))
3951 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3967 if (GET_CODE (SUBREG_REG (x)) == REG
3968 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3969 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3970 = GET_MODE_SIZE (GET_MODE (x));
3977 fmt = GET_RTX_FORMAT (code);
3978 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3981 scan_paradoxical_subregs (XEXP (x, i));
3982 else if (fmt[i] == 'E')
3985 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3986 scan_paradoxical_subregs (XVECEXP (x, i, j));
3992 hard_reg_use_compare (p1p, p2p)
3993 const GENERIC_PTR p1p;
3994 const GENERIC_PTR p2p;
3996 struct hard_reg_n_uses *p1 = (struct hard_reg_n_uses *)p1p;
3997 struct hard_reg_n_uses *p2 = (struct hard_reg_n_uses *)p2p;
3998 int bad1 = TEST_HARD_REG_BIT (bad_spill_regs, p1->regno);
3999 int bad2 = TEST_HARD_REG_BIT (bad_spill_regs, p2->regno);
4001 return p1->regno - p2->regno;
4006 if (p1->uses > p2->uses)
4008 if (p1->uses < p2->uses)
4010 /* If regs are equally good, sort by regno,
4011 so that the results of qsort leave nothing to chance. */
4012 return p1->regno - p2->regno;
4015 /* Used for communication between order_regs_for_reload and count_pseudo.
4016 Used to avoid counting one pseudo twice. */
4017 static regset pseudos_counted;
4019 /* Update the costs in N_USES, considering that pseudo REG is live. */
4021 count_pseudo (n_uses, reg)
4022 struct hard_reg_n_uses *n_uses;
4025 int r = reg_renumber[reg];
4028 if (REGNO_REG_SET_P (pseudos_counted, reg))
4030 SET_REGNO_REG_SET (pseudos_counted, reg);
4035 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
4037 n_uses[r++].uses += REG_N_REFS (reg);
4039 /* Choose the order to consider regs for use as reload registers
4040 based on how much trouble would be caused by spilling one.
4041 Store them in order of decreasing preference in potential_reload_regs. */
4044 order_regs_for_reload (chain)
4045 struct insn_chain *chain;
4049 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
4051 pseudos_counted = ALLOCA_REG_SET ();
4053 COPY_HARD_REG_SET (bad_spill_regs, bad_spill_regs_global);
4055 /* Count number of uses of each hard reg by pseudo regs allocated to it
4056 and then order them by decreasing use. */
4058 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4062 hard_reg_n_uses[i].regno = i;
4063 hard_reg_n_uses[i].uses = 0;
4065 /* Test the various reasons why we can't use a register for
4066 spilling in this insn. */
4068 || REGNO_REG_SET_P (chain->live_before, i)
4069 || REGNO_REG_SET_P (chain->live_after, i))
4071 SET_HARD_REG_BIT (bad_spill_regs, i);
4075 /* Now find out which pseudos are allocated to it, and update
4077 CLEAR_REG_SET (pseudos_counted);
4079 EXECUTE_IF_SET_IN_REG_SET
4080 (chain->live_before, FIRST_PSEUDO_REGISTER, j,
4082 count_pseudo (hard_reg_n_uses, j);
4084 EXECUTE_IF_SET_IN_REG_SET
4085 (chain->live_after, FIRST_PSEUDO_REGISTER, j,
4087 count_pseudo (hard_reg_n_uses, j);
4091 FREE_REG_SET (pseudos_counted);
4093 /* Prefer registers not so far used, for use in temporary loading.
4094 Among them, if REG_ALLOC_ORDER is defined, use that order.
4095 Otherwise, prefer registers not preserved by calls. */
4097 #ifdef REG_ALLOC_ORDER
4098 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4100 int regno = reg_alloc_order[i];
4102 if (hard_reg_n_uses[regno].uses == 0
4103 && ! TEST_HARD_REG_BIT (bad_spill_regs, regno))
4104 potential_reload_regs[o++] = regno;
4107 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4109 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i]
4110 && ! TEST_HARD_REG_BIT (bad_spill_regs, i))
4111 potential_reload_regs[o++] = i;
4113 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4115 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i]
4116 && ! TEST_HARD_REG_BIT (bad_spill_regs, i))
4117 potential_reload_regs[o++] = i;
4121 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
4122 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
4124 /* Now add the regs that are already used,
4125 preferring those used less often. The fixed and otherwise forbidden
4126 registers will be at the end of this list. */
4128 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4129 if (hard_reg_n_uses[i].uses != 0
4130 && ! TEST_HARD_REG_BIT (bad_spill_regs, hard_reg_n_uses[i].regno))
4131 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
4132 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4133 if (TEST_HARD_REG_BIT (bad_spill_regs, hard_reg_n_uses[i].regno))
4134 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
4137 /* Reload pseudo-registers into hard regs around each insn as needed.
4138 Additional register load insns are output before the insn that needs it
4139 and perhaps store insns after insns that modify the reloaded pseudo reg.
4141 reg_last_reload_reg and reg_reloaded_contents keep track of
4142 which registers are already available in reload registers.
4143 We update these for the reloads that we perform,
4144 as the insns are scanned. */
4147 reload_as_needed (live_known)
4150 struct insn_chain *chain;
4154 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
4155 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
4156 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
4157 bzero ((char *) reg_last_reload_reg, max_regno * sizeof (rtx));
4158 reg_has_output_reload = (char *) alloca (max_regno);
4159 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4161 set_initial_elim_offsets ();
4163 for (chain = reload_insn_chain; chain; chain = chain->next)
4166 rtx insn = chain->insn;
4167 rtx old_next = NEXT_INSN (insn);
4169 /* If we pass a label, copy the offsets from the label information
4170 into the current offsets of each elimination. */
4171 if (GET_CODE (insn) == CODE_LABEL)
4172 set_offsets_for_label (insn);
4174 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
4176 rtx oldpat = PATTERN (insn);
4178 /* If this is a USE and CLOBBER of a MEM, ensure that any
4179 references to eliminable registers have been removed. */
4181 if ((GET_CODE (PATTERN (insn)) == USE
4182 || GET_CODE (PATTERN (insn)) == CLOBBER)
4183 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
4184 XEXP (XEXP (PATTERN (insn), 0), 0)
4185 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4186 GET_MODE (XEXP (PATTERN (insn), 0)),
4189 /* If we need to do register elimination processing, do so.
4190 This might delete the insn, in which case we are done. */
4191 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4193 eliminate_regs_in_insn (insn, 1);
4194 if (GET_CODE (insn) == NOTE)
4196 update_eliminable_offsets ();
4201 /* If need_elim is nonzero but need_reload is zero, one might think
4202 that we could simply set n_reloads to 0. However, find_reloads
4203 could have done some manipulation of the insn (such as swapping
4204 commutative operands), and these manipulations are lost during
4205 the first pass for every insn that needs register elimination.
4206 So the actions of find_reloads must be redone here. */
4208 if (! chain->need_elim && ! chain->need_reload
4209 && ! chain->need_operand_change)
4211 /* First find the pseudo regs that must be reloaded for this insn.
4212 This info is returned in the tables reload_... (see reload.h).
4213 Also modify the body of INSN by substituting RELOAD
4214 rtx's for those pseudo regs. */
4217 bzero (reg_has_output_reload, max_regno);
4218 CLEAR_HARD_REG_SET (reg_is_output_reload);
4220 find_reloads (insn, 1, spill_indirect_levels, live_known,
4224 if (num_eliminable && chain->need_elim)
4225 update_eliminable_offsets ();
4229 rtx next = NEXT_INSN (insn);
4232 prev = PREV_INSN (insn);
4234 /* Now compute which reload regs to reload them into. Perhaps
4235 reusing reload regs from previous insns, or else output
4236 load insns to reload them. Maybe output store insns too.
4237 Record the choices of reload reg in reload_reg_rtx. */
4238 choose_reload_regs (chain);
4240 /* Merge any reloads that we didn't combine for fear of
4241 increasing the number of spill registers needed but now
4242 discover can be safely merged. */
4243 if (SMALL_REGISTER_CLASSES)
4244 merge_assigned_reloads (insn);
4246 /* Generate the insns to reload operands into or out of
4247 their reload regs. */
4248 emit_reload_insns (chain);
4250 /* Substitute the chosen reload regs from reload_reg_rtx
4251 into the insn's body (or perhaps into the bodies of other
4252 load and store insn that we just made for reloading
4253 and that we moved the structure into). */
4256 /* If this was an ASM, make sure that all the reload insns
4257 we have generated are valid. If not, give an error
4260 if (asm_noperands (PATTERN (insn)) >= 0)
4261 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4262 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
4263 && (recog_memoized (p) < 0
4264 || (extract_insn (p), ! constrain_operands (1))))
4266 error_for_asm (insn,
4267 "`asm' operand requires impossible reload");
4269 NOTE_SOURCE_FILE (p) = 0;
4270 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
4273 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4274 is no longer validly lying around to save a future reload.
4275 Note that this does not detect pseudos that were reloaded
4276 for this insn in order to be stored in
4277 (obeying register constraints). That is correct; such reload
4278 registers ARE still valid. */
4279 note_stores (oldpat, forget_old_reloads_1);
4281 /* There may have been CLOBBER insns placed after INSN. So scan
4282 between INSN and NEXT and use them to forget old reloads. */
4283 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4284 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
4285 note_stores (PATTERN (x), forget_old_reloads_1);
4288 /* Likewise for regs altered by auto-increment in this insn.
4289 REG_INC notes have been changed by reloading:
4290 find_reloads_address_1 records substitutions for them,
4291 which have been performed by subst_reloads above. */
4292 for (i = n_reloads - 1; i >= 0; i--)
4294 rtx in_reg = reload_in_reg[i];
4297 enum rtx_code code = GET_CODE (in_reg);
4298 /* PRE_INC / PRE_DEC will have the reload register ending up
4299 with the same value as the stack slot, but that doesn't
4300 hold true for POST_INC / POST_DEC. Either we have to
4301 convert the memory access to a true POST_INC / POST_DEC,
4302 or we can't use the reload register for inheritance. */
4303 if ((code == POST_INC || code == POST_DEC)
4304 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4305 REGNO (reload_reg_rtx[i]))
4306 /* Make sure it is the inc/dec pseudo, and not
4307 some other (e.g. output operand) pseudo. */
4308 && (reg_reloaded_contents[REGNO (reload_reg_rtx[i])]
4309 == REGNO (XEXP (in_reg, 0))))
4312 rtx reload_reg = reload_reg_rtx[i];
4313 enum machine_mode mode = GET_MODE (reload_reg);
4317 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4319 /* We really want to ignore REG_INC notes here, so
4320 use PATTERN (p) as argument to reg_set_p . */
4321 if (reg_set_p (reload_reg, PATTERN (p)))
4323 n = count_occurrences (PATTERN (p), reload_reg);
4327 n = validate_replace_rtx (reload_reg,
4328 gen_rtx (code, mode,
4333 REG_NOTES (p) = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4336 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX);
4340 #if 0 /* ??? Is this code obsolete now? Need to check carefully. */
4341 /* Likewise for regs altered by auto-increment in this insn.
4342 But note that the reg-notes are not changed by reloading:
4343 they still contain the pseudo-regs, not the spill regs. */
4344 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4345 if (REG_NOTE_KIND (x) == REG_INC)
4347 /* See if this pseudo reg was reloaded in this insn.
4348 If so, its last-reload info is still valid
4349 because it is based on this insn's reload. */
4350 for (i = 0; i < n_reloads; i++)
4351 if (reload_out[i] == XEXP (x, 0))
4355 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX);
4360 /* A reload reg's contents are unknown after a label. */
4361 if (GET_CODE (insn) == CODE_LABEL)
4362 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4364 /* Don't assume a reload reg is still good after a call insn
4365 if it is a call-used reg. */
4366 else if (GET_CODE (insn) == CALL_INSN)
4367 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
4369 /* In case registers overlap, allow certain insns to invalidate
4370 particular hard registers. */
4372 #ifdef INSN_CLOBBERS_REGNO_P
4373 for (i = 0 ; i < FIRST_PSEUDO_REGISTER; i++)
4374 if (TEST_HARD_REG_BIT (reg_reloaded_valid, i)
4375 && INSN_CLOBBERS_REGNO_P (insn, i))
4376 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i);
4385 /* Discard all record of any value reloaded from X,
4386 or reloaded in X from someplace else;
4387 unless X is an output reload reg of the current insn.
4389 X may be a hard reg (the reload reg)
4390 or it may be a pseudo reg that was reloaded from. */
4393 forget_old_reloads_1 (x, ignored)
4395 rtx ignored ATTRIBUTE_UNUSED;
4401 /* note_stores does give us subregs of hard regs. */
4402 while (GET_CODE (x) == SUBREG)
4404 offset += SUBREG_WORD (x);
4408 if (GET_CODE (x) != REG)
4411 regno = REGNO (x) + offset;
4413 if (regno >= FIRST_PSEUDO_REGISTER)
4418 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4419 /* Storing into a spilled-reg invalidates its contents.
4420 This can happen if a block-local pseudo is allocated to that reg
4421 and it wasn't spilled because this block's total need is 0.
4422 Then some insn might have an optional reload and use this reg. */
4423 for (i = 0; i < nr; i++)
4424 /* But don't do this if the reg actually serves as an output
4425 reload reg in the current instruction. */
4427 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4428 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4431 /* Since value of X has changed,
4432 forget any value previously copied from it. */
4435 /* But don't forget a copy if this is the output reload
4436 that establishes the copy's validity. */
4437 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4438 reg_last_reload_reg[regno + nr] = 0;
4441 /* For each reload, the mode of the reload register. */
4442 static enum machine_mode reload_mode[MAX_RELOADS];
4444 /* For each reload, the largest number of registers it will require. */
4445 static int reload_nregs[MAX_RELOADS];
4447 /* Comparison function for qsort to decide which of two reloads
4448 should be handled first. *P1 and *P2 are the reload numbers. */
4451 reload_reg_class_lower (r1p, r2p)
4452 const GENERIC_PTR r1p;
4453 const GENERIC_PTR r2p;
4455 register int r1 = *(short *)r1p, r2 = *(short *)r2p;
4458 /* Consider required reloads before optional ones. */
4459 t = reload_optional[r1] - reload_optional[r2];
4463 /* Count all solitary classes before non-solitary ones. */
4464 t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
4465 - (reg_class_size[(int) reload_reg_class[r1]] == 1));
4469 /* Aside from solitaires, consider all multi-reg groups first. */
4470 t = reload_nregs[r2] - reload_nregs[r1];
4474 /* Consider reloads in order of increasing reg-class number. */
4475 t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
4479 /* If reloads are equally urgent, sort by reload number,
4480 so that the results of qsort leave nothing to chance. */
4484 /* The following HARD_REG_SETs indicate when each hard register is
4485 used for a reload of various parts of the current insn. */
4487 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4488 static HARD_REG_SET reload_reg_used;
4489 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4490 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4491 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4492 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4493 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4494 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4495 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4496 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4497 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4498 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4499 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4500 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4501 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4502 static HARD_REG_SET reload_reg_used_in_op_addr;
4503 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4504 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4505 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4506 static HARD_REG_SET reload_reg_used_in_insn;
4507 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4508 static HARD_REG_SET reload_reg_used_in_other_addr;
4510 /* If reg is in use as a reload reg for any sort of reload. */
4511 static HARD_REG_SET reload_reg_used_at_all;
4513 /* If reg is use as an inherited reload. We just mark the first register
4515 static HARD_REG_SET reload_reg_used_for_inherit;
4517 /* Records which hard regs are used in any way, either as explicit use or
4518 by being allocated to a pseudo during any point of the current insn. */
4519 static HARD_REG_SET reg_used_in_insn;
4521 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4522 TYPE. MODE is used to indicate how many consecutive regs are
4526 mark_reload_reg_in_use (regno, opnum, type, mode)
4529 enum reload_type type;
4530 enum machine_mode mode;
4532 int nregs = HARD_REGNO_NREGS (regno, mode);
4535 for (i = regno; i < nregs + regno; i++)
4540 SET_HARD_REG_BIT (reload_reg_used, i);
4543 case RELOAD_FOR_INPUT_ADDRESS:
4544 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4547 case RELOAD_FOR_INPADDR_ADDRESS:
4548 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4551 case RELOAD_FOR_OUTPUT_ADDRESS:
4552 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4555 case RELOAD_FOR_OUTADDR_ADDRESS:
4556 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4559 case RELOAD_FOR_OPERAND_ADDRESS:
4560 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4563 case RELOAD_FOR_OPADDR_ADDR:
4564 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4567 case RELOAD_FOR_OTHER_ADDRESS:
4568 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4571 case RELOAD_FOR_INPUT:
4572 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4575 case RELOAD_FOR_OUTPUT:
4576 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4579 case RELOAD_FOR_INSN:
4580 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4584 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4588 /* Similarly, but show REGNO is no longer in use for a reload. */
4591 clear_reload_reg_in_use (regno, opnum, type, mode)
4594 enum reload_type type;
4595 enum machine_mode mode;
4597 int nregs = HARD_REGNO_NREGS (regno, mode);
4598 int start_regno, end_regno;
4600 /* A complication is that for some reload types, inheritance might
4601 allow multiple reloads of the same types to share a reload register.
4602 We set check_opnum if we have to check only reloads with the same
4603 operand number, and check_any if we have to check all reloads. */
4604 int check_opnum = 0;
4606 HARD_REG_SET *used_in_set;
4611 used_in_set = &reload_reg_used;
4614 case RELOAD_FOR_INPUT_ADDRESS:
4615 used_in_set = &reload_reg_used_in_input_addr[opnum];
4618 case RELOAD_FOR_INPADDR_ADDRESS:
4620 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4623 case RELOAD_FOR_OUTPUT_ADDRESS:
4624 used_in_set = &reload_reg_used_in_output_addr[opnum];
4627 case RELOAD_FOR_OUTADDR_ADDRESS:
4629 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4632 case RELOAD_FOR_OPERAND_ADDRESS:
4633 used_in_set = &reload_reg_used_in_op_addr;
4636 case RELOAD_FOR_OPADDR_ADDR:
4638 used_in_set = &reload_reg_used_in_op_addr_reload;
4641 case RELOAD_FOR_OTHER_ADDRESS:
4642 used_in_set = &reload_reg_used_in_other_addr;
4646 case RELOAD_FOR_INPUT:
4647 used_in_set = &reload_reg_used_in_input[opnum];
4650 case RELOAD_FOR_OUTPUT:
4651 used_in_set = &reload_reg_used_in_output[opnum];
4654 case RELOAD_FOR_INSN:
4655 used_in_set = &reload_reg_used_in_insn;
4660 /* We resolve conflicts with remaining reloads of the same type by
4661 excluding the intervals of of reload registers by them from the
4662 interval of freed reload registers. Since we only keep track of
4663 one set of interval bounds, we might have to exclude somewhat
4664 more then what would be necessary if we used a HARD_REG_SET here.
4665 But this should only happen very infrequently, so there should
4666 be no reason to worry about it. */
4668 start_regno = regno;
4669 end_regno = regno + nregs;
4670 if (check_opnum || check_any)
4672 for (i = n_reloads - 1; i >= 0; i--)
4674 if (reload_when_needed[i] == type
4675 && (check_any || reload_opnum[i] == opnum)
4676 && reload_reg_rtx[i])
4678 int conflict_start = true_regnum (reload_reg_rtx[i]);
4681 + HARD_REGNO_NREGS (conflict_start, reload_mode[i]));
4683 /* If there is an overlap with the first to-be-freed register,
4684 adjust the interval start. */
4685 if (conflict_start <= start_regno && conflict_end > start_regno)
4686 start_regno = conflict_end;
4687 /* Otherwise, if there is a conflict with one of the other
4688 to-be-freed registers, adjust the interval end. */
4689 if (conflict_start > start_regno && conflict_start < end_regno)
4690 end_regno = conflict_start;
4694 for (i = start_regno; i < end_regno; i++)
4695 CLEAR_HARD_REG_BIT (*used_in_set, i);
4698 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4699 specified by OPNUM and TYPE. */
4702 reload_reg_free_p (regno, opnum, type)
4705 enum reload_type type;
4709 /* In use for a RELOAD_OTHER means it's not available for anything. */
4710 if (TEST_HARD_REG_BIT (reload_reg_used, regno))
4716 /* In use for anything means we can't use it for RELOAD_OTHER. */
4717 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4718 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4719 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4722 for (i = 0; i < reload_n_operands; i++)
4723 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4724 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4725 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4726 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4727 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4728 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4733 case RELOAD_FOR_INPUT:
4734 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4735 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4738 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4741 /* If it is used for some other input, can't use it. */
4742 for (i = 0; i < reload_n_operands; i++)
4743 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4746 /* If it is used in a later operand's address, can't use it. */
4747 for (i = opnum + 1; i < reload_n_operands; i++)
4748 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4749 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4754 case RELOAD_FOR_INPUT_ADDRESS:
4755 /* Can't use a register if it is used for an input address for this
4756 operand or used as an input in an earlier one. */
4757 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4758 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4761 for (i = 0; i < opnum; i++)
4762 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4767 case RELOAD_FOR_INPADDR_ADDRESS:
4768 /* Can't use a register if it is used for an input address
4769 for this operand or used as an input in an earlier
4771 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4774 for (i = 0; i < opnum; i++)
4775 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4780 case RELOAD_FOR_OUTPUT_ADDRESS:
4781 /* Can't use a register if it is used for an output address for this
4782 operand or used as an output in this or a later operand. */
4783 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4786 for (i = opnum; i < reload_n_operands; i++)
4787 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4792 case RELOAD_FOR_OUTADDR_ADDRESS:
4793 /* Can't use a register if it is used for an output address
4794 for this operand or used as an output in this or a
4796 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4799 for (i = opnum; i < reload_n_operands; i++)
4800 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4805 case RELOAD_FOR_OPERAND_ADDRESS:
4806 for (i = 0; i < reload_n_operands; i++)
4807 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4810 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4811 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4813 case RELOAD_FOR_OPADDR_ADDR:
4814 for (i = 0; i < reload_n_operands; i++)
4815 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4818 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4820 case RELOAD_FOR_OUTPUT:
4821 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4822 outputs, or an operand address for this or an earlier output. */
4823 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4826 for (i = 0; i < reload_n_operands; i++)
4827 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4830 for (i = 0; i <= opnum; i++)
4831 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4832 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4837 case RELOAD_FOR_INSN:
4838 for (i = 0; i < reload_n_operands; i++)
4839 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4840 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4843 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4844 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4846 case RELOAD_FOR_OTHER_ADDRESS:
4847 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4852 /* Return 1 if the value in reload reg REGNO, as used by a reload
4853 needed for the part of the insn specified by OPNUM and TYPE,
4854 is still available in REGNO at the end of the insn.
4856 We can assume that the reload reg was already tested for availability
4857 at the time it is needed, and we should not check this again,
4858 in case the reg has already been marked in use. */
4861 reload_reg_reaches_end_p (regno, opnum, type)
4864 enum reload_type type;
4871 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4872 its value must reach the end. */
4875 /* If this use is for part of the insn,
4876 its value reaches if no subsequent part uses the same register.
4877 Just like the above function, don't try to do this with lots
4880 case RELOAD_FOR_OTHER_ADDRESS:
4881 /* Here we check for everything else, since these don't conflict
4882 with anything else and everything comes later. */
4884 for (i = 0; i < reload_n_operands; i++)
4885 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4886 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4887 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4888 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4889 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4890 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4893 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4894 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4895 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4897 case RELOAD_FOR_INPUT_ADDRESS:
4898 case RELOAD_FOR_INPADDR_ADDRESS:
4899 /* Similar, except that we check only for this and subsequent inputs
4900 and the address of only subsequent inputs and we do not need
4901 to check for RELOAD_OTHER objects since they are known not to
4904 for (i = opnum; i < reload_n_operands; i++)
4905 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4908 for (i = opnum + 1; i < reload_n_operands; i++)
4909 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4910 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4913 for (i = 0; i < reload_n_operands; i++)
4914 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4915 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4916 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4919 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4922 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4923 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4925 case RELOAD_FOR_INPUT:
4926 /* Similar to input address, except we start at the next operand for
4927 both input and input address and we do not check for
4928 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4931 for (i = opnum + 1; i < reload_n_operands; i++)
4932 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4933 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4934 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4937 /* ... fall through ... */
4939 case RELOAD_FOR_OPERAND_ADDRESS:
4940 /* Check outputs and their addresses. */
4942 for (i = 0; i < reload_n_operands; i++)
4943 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4944 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4945 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4950 case RELOAD_FOR_OPADDR_ADDR:
4951 for (i = 0; i < reload_n_operands; i++)
4952 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4953 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4954 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4957 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4958 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4960 case RELOAD_FOR_INSN:
4961 /* These conflict with other outputs with RELOAD_OTHER. So
4962 we need only check for output addresses. */
4966 /* ... fall through ... */
4968 case RELOAD_FOR_OUTPUT:
4969 case RELOAD_FOR_OUTPUT_ADDRESS:
4970 case RELOAD_FOR_OUTADDR_ADDRESS:
4971 /* We already know these can't conflict with a later output. So the
4972 only thing to check are later output addresses. */
4973 for (i = opnum + 1; i < reload_n_operands; i++)
4974 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4975 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4984 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4987 This function uses the same algorithm as reload_reg_free_p above. */
4990 reloads_conflict (r1, r2)
4993 enum reload_type r1_type = reload_when_needed[r1];
4994 enum reload_type r2_type = reload_when_needed[r2];
4995 int r1_opnum = reload_opnum[r1];
4996 int r2_opnum = reload_opnum[r2];
4998 /* RELOAD_OTHER conflicts with everything. */
4999 if (r2_type == RELOAD_OTHER)
5002 /* Otherwise, check conflicts differently for each type. */
5006 case RELOAD_FOR_INPUT:
5007 return (r2_type == RELOAD_FOR_INSN
5008 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5009 || r2_type == RELOAD_FOR_OPADDR_ADDR
5010 || r2_type == RELOAD_FOR_INPUT
5011 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5012 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5013 && r2_opnum > r1_opnum));
5015 case RELOAD_FOR_INPUT_ADDRESS:
5016 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5017 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5019 case RELOAD_FOR_INPADDR_ADDRESS:
5020 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5021 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5023 case RELOAD_FOR_OUTPUT_ADDRESS:
5024 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5025 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
5027 case RELOAD_FOR_OUTADDR_ADDRESS:
5028 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5029 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
5031 case RELOAD_FOR_OPERAND_ADDRESS:
5032 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5033 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5035 case RELOAD_FOR_OPADDR_ADDR:
5036 return (r2_type == RELOAD_FOR_INPUT
5037 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5039 case RELOAD_FOR_OUTPUT:
5040 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5041 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5042 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5043 && r2_opnum >= r1_opnum));
5045 case RELOAD_FOR_INSN:
5046 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5047 || r2_type == RELOAD_FOR_INSN
5048 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5050 case RELOAD_FOR_OTHER_ADDRESS:
5051 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5061 /* Vector of reload-numbers showing the order in which the reloads should
5063 short reload_order[MAX_RELOADS];
5065 /* Indexed by reload number, 1 if incoming value
5066 inherited from previous insns. */
5067 char reload_inherited[MAX_RELOADS];
5069 /* For an inherited reload, this is the insn the reload was inherited from,
5070 if we know it. Otherwise, this is 0. */
5071 rtx reload_inheritance_insn[MAX_RELOADS];
5073 /* If non-zero, this is a place to get the value of the reload,
5074 rather than using reload_in. */
5075 rtx reload_override_in[MAX_RELOADS];
5077 /* For each reload, the hard register number of the register used,
5078 or -1 if we did not need a register for this reload. */
5079 int reload_spill_index[MAX_RELOADS];
5081 /* Return 1 if the value in reload reg REGNO, as used by a reload
5082 needed for the part of the insn specified by OPNUM and TYPE,
5083 may be used to load VALUE into it.
5085 Other read-only reloads with the same value do not conflict
5086 unless OUT is non-zero and these other reloads have to live while
5087 output reloads live.
5088 If OUT is CONST0_RTX, this is a special case: it means that the
5089 test should not be for using register REGNO as reload register, but
5090 for copying from register REGNO into the reload register.
5092 RELOADNUM is the number of the reload we want to load this value for;
5093 a reload does not conflict with itself.
5095 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5096 reloads that load an address for the very reload we are considering.
5098 The caller has to make sure that there is no conflict with the return
5101 reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum,
5102 ignore_address_reloads)
5105 enum reload_type type;
5108 int ignore_address_reloads;
5114 if (out == const0_rtx)
5120 /* We use some pseudo 'time' value to check if the lifetimes of the
5121 new register use would overlap with the one of a previous reload
5122 that is not read-only or uses a different value.
5123 The 'time' used doesn't have to be linear in any shape or form, just
5125 Some reload types use different 'buckets' for each operand.
5126 So there are MAX_RECOG_OPERANDS different time values for each
5128 We compute TIME1 as the time when the register for the prospective
5129 new reload ceases to be live, and TIME2 for each existing
5130 reload as the time when that the reload register of that reload
5132 Where there is little to be gained by exact lifetime calculations,
5133 we just make conservative assumptions, i.e. a longer lifetime;
5134 this is done in the 'default:' cases. */
5137 case RELOAD_FOR_OTHER_ADDRESS:
5141 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5143 /* For each input, we might have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5144 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5145 respectively, to the time values for these, we get distinct time
5146 values. To get distinct time values for each operand, we have to
5147 multiply opnum by at least three. We round that up to four because
5148 multiply by four is often cheaper. */
5149 case RELOAD_FOR_INPADDR_ADDRESS:
5150 time1 = opnum * 4 + 2;
5152 case RELOAD_FOR_INPUT_ADDRESS:
5153 time1 = opnum * 4 + 3;
5155 case RELOAD_FOR_INPUT:
5156 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5157 executes (inclusive). */
5158 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5160 case RELOAD_FOR_OPADDR_ADDR:
5162 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5163 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5165 case RELOAD_FOR_OPERAND_ADDRESS:
5166 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5168 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5170 case RELOAD_FOR_OUTADDR_ADDRESS:
5171 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5173 case RELOAD_FOR_OUTPUT_ADDRESS:
5174 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5177 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5180 for (i = 0; i < n_reloads; i++)
5182 rtx reg = reload_reg_rtx[i];
5183 if (reg && GET_CODE (reg) == REG
5184 && ((unsigned) regno - true_regnum (reg)
5185 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
5188 if (! reload_in[i] || ! rtx_equal_p (reload_in[i], value)
5189 || reload_out[i] || out)
5192 switch (reload_when_needed[i])
5194 case RELOAD_FOR_OTHER_ADDRESS:
5197 case RELOAD_FOR_INPADDR_ADDRESS:
5198 /* find_reloads makes sure that a
5199 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5200 by at most one - the first -
5201 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5202 address reload is inherited, the address address reload
5203 goes away, so we can ignore this conflict. */
5204 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5205 && ignore_address_reloads
5206 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5207 Then the address address is still needed to store
5208 back the new address. */
5209 && ! reload_out[reloadnum])
5211 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5212 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5214 if (type == RELOAD_FOR_INPUT && opnum == reload_opnum[i]
5215 && ignore_address_reloads
5216 /* Unless we are reloading an auto_inc expression. */
5217 && ! reload_out[reloadnum])
5219 time2 = reload_opnum[i] * 4 + 2;
5221 case RELOAD_FOR_INPUT_ADDRESS:
5222 if (type == RELOAD_FOR_INPUT && opnum == reload_opnum[i]
5223 && ignore_address_reloads
5224 && ! reload_out[reloadnum])
5226 time2 = reload_opnum[i] * 4 + 3;
5228 case RELOAD_FOR_INPUT:
5229 time2 = reload_opnum[i] * 4 + 4;
5231 /* reload_opnum[i] * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5232 == MAX_RECOG_OPERAND * 4 */
5233 case RELOAD_FOR_OPADDR_ADDR:
5234 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5235 && ignore_address_reloads
5236 && ! reload_out[reloadnum])
5238 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5240 case RELOAD_FOR_OPERAND_ADDRESS:
5241 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5243 case RELOAD_FOR_INSN:
5244 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5246 case RELOAD_FOR_OUTPUT:
5247 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5248 instruction is executed. */
5249 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5251 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5252 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5254 case RELOAD_FOR_OUTADDR_ADDRESS:
5255 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5256 && ignore_address_reloads
5257 && ! reload_out[reloadnum])
5259 time2 = MAX_RECOG_OPERANDS * 4 + 4 + reload_opnum[i];
5261 case RELOAD_FOR_OUTPUT_ADDRESS:
5262 time2 = MAX_RECOG_OPERANDS * 4 + 5 + reload_opnum[i];
5265 /* If there is no conflict in the input part, handle this
5266 like an output reload. */
5267 if (! reload_in[i] || rtx_equal_p (reload_in[i], value))
5269 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5273 /* RELOAD_OTHER might be live beyond instruction execution,
5274 but this is not obvious when we set time2 = 1. So check
5275 here if there might be a problem with the new reload
5276 clobbering the register used by the RELOAD_OTHER. */
5284 && (! reload_in[i] || reload_out[i]
5285 || ! rtx_equal_p (reload_in[i], value)))
5286 || (out && reload_out_reg[reloadnum]
5287 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5295 /* Find a spill register to use as a reload register for reload R.
5296 LAST_RELOAD is non-zero if this is the last reload for the insn being
5299 Set reload_reg_rtx[R] to the register allocated.
5301 If NOERROR is nonzero, we return 1 if successful,
5302 or 0 if we couldn't find a spill reg and we didn't change anything. */
5305 allocate_reload_reg (chain, r, last_reload, noerror)
5306 struct insn_chain *chain;
5311 rtx insn = chain->insn;
5312 int i, pass, count, regno;
5315 /* If we put this reload ahead, thinking it is a group,
5316 then insist on finding a group. Otherwise we can grab a
5317 reg that some other reload needs.
5318 (That can happen when we have a 68000 DATA_OR_FP_REG
5319 which is a group of data regs or one fp reg.)
5320 We need not be so restrictive if there are no more reloads
5323 ??? Really it would be nicer to have smarter handling
5324 for that kind of reg class, where a problem like this is normal.
5325 Perhaps those classes should be avoided for reloading
5326 by use of more alternatives. */
5328 int force_group = reload_nregs[r] > 1 && ! last_reload;
5330 /* If we want a single register and haven't yet found one,
5331 take any reg in the right class and not in use.
5332 If we want a consecutive group, here is where we look for it.
5334 We use two passes so we can first look for reload regs to
5335 reuse, which are already in use for other reloads in this insn,
5336 and only then use additional registers.
5337 I think that maximizing reuse is needed to make sure we don't
5338 run out of reload regs. Suppose we have three reloads, and
5339 reloads A and B can share regs. These need two regs.
5340 Suppose A and B are given different regs.
5341 That leaves none for C. */
5342 for (pass = 0; pass < 2; pass++)
5344 /* I is the index in spill_regs.
5345 We advance it round-robin between insns to use all spill regs
5346 equally, so that inherited reloads have a chance
5347 of leapfrogging each other. Don't do this, however, when we have
5348 group needs and failure would be fatal; if we only have a relatively
5349 small number of spill registers, and more than one of them has
5350 group needs, then by starting in the middle, we may end up
5351 allocating the first one in such a way that we are not left with
5352 sufficient groups to handle the rest. */
5354 if (noerror || ! force_group)
5359 for (count = 0; count < n_spills; count++)
5361 int class = (int) reload_reg_class[r];
5367 regnum = spill_regs[i];
5369 if ((reload_reg_free_p (regnum, reload_opnum[r],
5370 reload_when_needed[r])
5372 /* We check reload_reg_used to make sure we
5373 don't clobber the return register. */
5374 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5375 && reload_reg_free_for_value_p (regnum,
5377 reload_when_needed[r],
5379 reload_out[r], r, 1)))
5380 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5381 && HARD_REGNO_MODE_OK (regnum, reload_mode[r])
5382 /* Look first for regs to share, then for unshared. But
5383 don't share regs used for inherited reloads; they are
5384 the ones we want to preserve. */
5386 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5388 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5391 int nr = HARD_REGNO_NREGS (regnum, reload_mode[r]);
5392 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5393 (on 68000) got us two FP regs. If NR is 1,
5394 we would reject both of them. */
5396 nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
5397 /* If we need only one reg, we have already won. */
5400 /* But reject a single reg if we demand a group. */
5405 /* Otherwise check that as many consecutive regs as we need
5407 Also, don't use for a group registers that are
5408 needed for nongroups. */
5409 if (! TEST_HARD_REG_BIT (chain->counted_for_nongroups, regnum))
5412 regno = regnum + nr - 1;
5413 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5414 && spill_reg_order[regno] >= 0
5415 && reload_reg_free_p (regno, reload_opnum[r],
5416 reload_when_needed[r])
5417 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups,
5427 /* If we found something on pass 1, omit pass 2. */
5428 if (count < n_spills)
5432 /* We should have found a spill register by now. */
5433 if (count == n_spills)
5440 /* I is the index in SPILL_REG_RTX of the reload register we are to
5441 allocate. Get an rtx for it and find its register number. */
5443 new = spill_reg_rtx[i];
5445 if (new == 0 || GET_MODE (new) != reload_mode[r])
5446 spill_reg_rtx[i] = new
5447 = gen_rtx_REG (reload_mode[r], spill_regs[i]);
5449 regno = true_regnum (new);
5451 /* Detect when the reload reg can't hold the reload mode.
5452 This used to be one `if', but Sequent compiler can't handle that. */
5453 if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5455 enum machine_mode test_mode = VOIDmode;
5457 test_mode = GET_MODE (reload_in[r]);
5458 /* If reload_in[r] has VOIDmode, it means we will load it
5459 in whatever mode the reload reg has: to wit, reload_mode[r].
5460 We have already tested that for validity. */
5461 /* Aside from that, we need to test that the expressions
5462 to reload from or into have modes which are valid for this
5463 reload register. Otherwise the reload insns would be invalid. */
5464 if (! (reload_in[r] != 0 && test_mode != VOIDmode
5465 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5466 if (! (reload_out[r] != 0
5467 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
5469 /* The reg is OK. */
5472 /* Mark as in use for this insn the reload regs we use
5474 mark_reload_reg_in_use (spill_regs[i], reload_opnum[r],
5475 reload_when_needed[r], reload_mode[r]);
5477 reload_reg_rtx[r] = new;
5478 reload_spill_index[r] = spill_regs[i];
5483 /* The reg is not OK. */
5488 if (asm_noperands (PATTERN (insn)) < 0)
5489 /* It's the compiler's fault. */
5490 fatal_insn ("Could not find a spill register", insn);
5492 /* It's the user's fault; the operand's mode and constraint
5493 don't match. Disable this reload so we don't crash in final. */
5494 error_for_asm (insn,
5495 "`asm' operand constraint incompatible with operand size");
5498 reload_reg_rtx[r] = 0;
5499 reload_optional[r] = 1;
5500 reload_secondary_p[r] = 1;
5505 /* Assign hard reg targets for the pseudo-registers we must reload
5506 into hard regs for this insn.
5507 Also output the instructions to copy them in and out of the hard regs.
5509 For machines with register classes, we are responsible for
5510 finding a reload reg in the proper class. */
5513 choose_reload_regs (chain)
5514 struct insn_chain *chain;
5516 rtx insn = chain->insn;
5518 int max_group_size = 1;
5519 enum reg_class group_class = NO_REGS;
5523 rtx save_reload_reg_rtx[MAX_RELOADS];
5524 char save_reload_inherited[MAX_RELOADS];
5525 rtx save_reload_inheritance_insn[MAX_RELOADS];
5526 rtx save_reload_override_in[MAX_RELOADS];
5527 int save_reload_spill_index[MAX_RELOADS];
5528 HARD_REG_SET save_reload_reg_used;
5529 HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
5530 HARD_REG_SET save_reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
5531 HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
5532 HARD_REG_SET save_reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
5533 HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS];
5534 HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS];
5535 HARD_REG_SET save_reload_reg_used_in_op_addr;
5536 HARD_REG_SET save_reload_reg_used_in_op_addr_reload;
5537 HARD_REG_SET save_reload_reg_used_in_insn;
5538 HARD_REG_SET save_reload_reg_used_in_other_addr;
5539 HARD_REG_SET save_reload_reg_used_at_all;
5541 bzero (reload_inherited, MAX_RELOADS);
5542 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5543 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5545 CLEAR_HARD_REG_SET (reload_reg_used);
5546 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5547 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5548 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5549 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5550 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5552 CLEAR_HARD_REG_SET (reg_used_in_insn);
5555 REG_SET_TO_HARD_REG_SET (tmp, chain->live_before);
5556 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5557 REG_SET_TO_HARD_REG_SET (tmp, chain->live_after);
5558 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5559 compute_use_by_pseudos (®_used_in_insn, chain->live_before);
5560 compute_use_by_pseudos (®_used_in_insn, chain->live_after);
5562 for (i = 0; i < reload_n_operands; i++)
5564 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5565 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5566 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5567 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5568 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5569 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5572 IOR_COMPL_HARD_REG_SET (reload_reg_used, chain->used_spill_regs);
5574 #if 0 /* Not needed, now that we can always retry without inheritance. */
5575 /* See if we have more mandatory reloads than spill regs.
5576 If so, then we cannot risk optimizations that could prevent
5577 reloads from sharing one spill register.
5579 Since we will try finding a better register than reload_reg_rtx
5580 unless it is equal to reload_in or reload_out, count such reloads. */
5584 for (j = 0; j < n_reloads; j++)
5585 if (! reload_optional[j]
5586 && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
5587 && (reload_reg_rtx[j] == 0
5588 || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
5589 && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
5596 /* In order to be certain of getting the registers we need,
5597 we must sort the reloads into order of increasing register class.
5598 Then our grabbing of reload registers will parallel the process
5599 that provided the reload registers.
5601 Also note whether any of the reloads wants a consecutive group of regs.
5602 If so, record the maximum size of the group desired and what
5603 register class contains all the groups needed by this insn. */
5605 for (j = 0; j < n_reloads; j++)
5607 reload_order[j] = j;
5608 reload_spill_index[j] = -1;
5611 = (reload_inmode[j] == VOIDmode
5612 || (GET_MODE_SIZE (reload_outmode[j])
5613 > GET_MODE_SIZE (reload_inmode[j])))
5614 ? reload_outmode[j] : reload_inmode[j];
5616 reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
5618 if (reload_nregs[j] > 1)
5620 max_group_size = MAX (reload_nregs[j], max_group_size);
5621 group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
5624 /* If we have already decided to use a certain register,
5625 don't use it in another way. */
5626 if (reload_reg_rtx[j])
5627 mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j],
5628 reload_when_needed[j], reload_mode[j]);
5632 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5634 bcopy ((char *) reload_reg_rtx, (char *) save_reload_reg_rtx,
5635 sizeof reload_reg_rtx);
5636 bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
5637 bcopy ((char *) reload_inheritance_insn,
5638 (char *) save_reload_inheritance_insn,
5639 sizeof reload_inheritance_insn);
5640 bcopy ((char *) reload_override_in, (char *) save_reload_override_in,
5641 sizeof reload_override_in);
5642 bcopy ((char *) reload_spill_index, (char *) save_reload_spill_index,
5643 sizeof reload_spill_index);
5644 COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
5645 COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
5646 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
5647 reload_reg_used_in_op_addr);
5649 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr_reload,
5650 reload_reg_used_in_op_addr_reload);
5652 COPY_HARD_REG_SET (save_reload_reg_used_in_insn,
5653 reload_reg_used_in_insn);
5654 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr,
5655 reload_reg_used_in_other_addr);
5657 for (i = 0; i < reload_n_operands; i++)
5659 COPY_HARD_REG_SET (save_reload_reg_used_in_output[i],
5660 reload_reg_used_in_output[i]);
5661 COPY_HARD_REG_SET (save_reload_reg_used_in_input[i],
5662 reload_reg_used_in_input[i]);
5663 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i],
5664 reload_reg_used_in_input_addr[i]);
5665 COPY_HARD_REG_SET (save_reload_reg_used_in_inpaddr_addr[i],
5666 reload_reg_used_in_inpaddr_addr[i]);
5667 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i],
5668 reload_reg_used_in_output_addr[i]);
5669 COPY_HARD_REG_SET (save_reload_reg_used_in_outaddr_addr[i],
5670 reload_reg_used_in_outaddr_addr[i]);
5673 /* If -O, try first with inheritance, then turning it off.
5674 If not -O, don't do inheritance.
5675 Using inheritance when not optimizing leads to paradoxes
5676 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5677 because one side of the comparison might be inherited. */
5679 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5681 /* Process the reloads in order of preference just found.
5682 Beyond this point, subregs can be found in reload_reg_rtx.
5684 This used to look for an existing reloaded home for all
5685 of the reloads, and only then perform any new reloads.
5686 But that could lose if the reloads were done out of reg-class order
5687 because a later reload with a looser constraint might have an old
5688 home in a register needed by an earlier reload with a tighter constraint.
5690 To solve this, we make two passes over the reloads, in the order
5691 described above. In the first pass we try to inherit a reload
5692 from a previous insn. If there is a later reload that needs a
5693 class that is a proper subset of the class being processed, we must
5694 also allocate a spill register during the first pass.
5696 Then make a second pass over the reloads to allocate any reloads
5697 that haven't been given registers yet. */
5699 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5701 for (j = 0; j < n_reloads; j++)
5703 register int r = reload_order[j];
5705 /* Ignore reloads that got marked inoperative. */
5706 if (reload_out[r] == 0 && reload_in[r] == 0
5707 && ! reload_secondary_p[r])
5710 /* If find_reloads chose to use reload_in or reload_out as a reload
5711 register, we don't need to chose one. Otherwise, try even if it
5712 found one since we might save an insn if we find the value lying
5714 Try also when reload_in is a pseudo without a hard reg. */
5715 if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
5716 && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
5717 || (rtx_equal_p (reload_out[r], reload_reg_rtx[r])
5718 && GET_CODE (reload_in[r]) != MEM
5719 && true_regnum (reload_in[r]) < FIRST_PSEUDO_REGISTER)))
5722 #if 0 /* No longer needed for correct operation.
5723 It might give better code, or might not; worth an experiment? */
5724 /* If this is an optional reload, we can't inherit from earlier insns
5725 until we are sure that any non-optional reloads have been allocated.
5726 The following code takes advantage of the fact that optional reloads
5727 are at the end of reload_order. */
5728 if (reload_optional[r] != 0)
5729 for (i = 0; i < j; i++)
5730 if ((reload_out[reload_order[i]] != 0
5731 || reload_in[reload_order[i]] != 0
5732 || reload_secondary_p[reload_order[i]])
5733 && ! reload_optional[reload_order[i]]
5734 && reload_reg_rtx[reload_order[i]] == 0)
5735 allocate_reload_reg (chain, reload_order[i], 0, inheritance);
5738 /* First see if this pseudo is already available as reloaded
5739 for a previous insn. We cannot try to inherit for reloads
5740 that are smaller than the maximum number of registers needed
5741 for groups unless the register we would allocate cannot be used
5744 We could check here to see if this is a secondary reload for
5745 an object that is already in a register of the desired class.
5746 This would avoid the need for the secondary reload register.
5747 But this is complex because we can't easily determine what
5748 objects might want to be loaded via this reload. So let a
5749 register be allocated here. In `emit_reload_insns' we suppress
5750 one of the loads in the case described above. */
5755 register int regno = -1;
5756 enum machine_mode mode;
5758 if (reload_in[r] == 0)
5760 else if (GET_CODE (reload_in[r]) == REG)
5762 regno = REGNO (reload_in[r]);
5763 mode = GET_MODE (reload_in[r]);
5765 else if (GET_CODE (reload_in_reg[r]) == REG)
5767 regno = REGNO (reload_in_reg[r]);
5768 mode = GET_MODE (reload_in_reg[r]);
5770 else if (GET_CODE (reload_in_reg[r]) == SUBREG
5771 && GET_CODE (SUBREG_REG (reload_in_reg[r])) == REG)
5773 word = SUBREG_WORD (reload_in_reg[r]);
5774 regno = REGNO (SUBREG_REG (reload_in_reg[r]));
5775 if (regno < FIRST_PSEUDO_REGISTER)
5777 mode = GET_MODE (reload_in_reg[r]);
5780 else if ((GET_CODE (reload_in_reg[r]) == PRE_INC
5781 || GET_CODE (reload_in_reg[r]) == PRE_DEC
5782 || GET_CODE (reload_in_reg[r]) == POST_INC
5783 || GET_CODE (reload_in_reg[r]) == POST_DEC)
5784 && GET_CODE (XEXP (reload_in_reg[r], 0)) == REG)
5786 regno = REGNO (XEXP (reload_in_reg[r], 0));
5787 mode = GET_MODE (XEXP (reload_in_reg[r], 0));
5788 reload_out[r] = reload_in[r];
5792 /* This won't work, since REGNO can be a pseudo reg number.
5793 Also, it takes much more hair to keep track of all the things
5794 that can invalidate an inherited reload of part of a pseudoreg. */
5795 else if (GET_CODE (reload_in[r]) == SUBREG
5796 && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
5797 regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
5800 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5802 enum reg_class class = reload_reg_class[r], last_class;
5803 rtx last_reg = reg_last_reload_reg[regno];
5805 i = REGNO (last_reg) + word;
5806 last_class = REGNO_REG_CLASS (i);
5807 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5808 >= GET_MODE_SIZE (mode) + word * UNITS_PER_WORD)
5809 && reg_reloaded_contents[i] == regno
5810 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5811 && HARD_REGNO_MODE_OK (i, reload_mode[r])
5812 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5813 /* Even if we can't use this register as a reload
5814 register, we might use it for reload_override_in,
5815 if copying it to the desired class is cheap
5817 || ((REGISTER_MOVE_COST (last_class, class)
5818 < MEMORY_MOVE_COST (mode, class, 1))
5819 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5820 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5824 #ifdef SECONDARY_MEMORY_NEEDED
5825 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5830 && (reload_nregs[r] == max_group_size
5831 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5833 && reload_reg_free_for_value_p (i, reload_opnum[r],
5834 reload_when_needed[r],
5838 /* If a group is needed, verify that all the subsequent
5839 registers still have their values intact. */
5841 = HARD_REGNO_NREGS (i, reload_mode[r]);
5844 for (k = 1; k < nr; k++)
5845 if (reg_reloaded_contents[i + k] != regno
5846 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5853 last_reg = (GET_MODE (last_reg) == mode
5854 ? last_reg : gen_rtx_REG (mode, i));
5856 /* We found a register that contains the
5857 value we need. If this register is the
5858 same as an `earlyclobber' operand of the
5859 current insn, just mark it as a place to
5860 reload from since we can't use it as the
5861 reload register itself. */
5863 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5864 if (reg_overlap_mentioned_for_reload_p
5865 (reg_last_reload_reg[regno],
5866 reload_earlyclobbers[i1]))
5869 if (i1 != n_earlyclobbers
5870 || ! (reload_reg_free_for_value_p
5871 (i, reload_opnum[r], reload_when_needed[r],
5872 reload_in[r], reload_out[r], r, 1))
5873 /* Don't use it if we'd clobber a pseudo reg. */
5874 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5876 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5877 /* Don't really use the inherited spill reg
5878 if we need it wider than we've got it. */
5879 || (GET_MODE_SIZE (reload_mode[r])
5880 > GET_MODE_SIZE (mode))
5881 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5884 /* If find_reloads chose reload_out as reload
5885 register, stay with it - that leaves the
5886 inherited register for subsequent reloads. */
5887 || (reload_out[r] && reload_reg_rtx[r]
5888 && rtx_equal_p (reload_out[r],
5889 reload_reg_rtx[r])))
5891 reload_override_in[r] = last_reg;
5892 reload_inheritance_insn[r]
5893 = reg_reloaded_insn[i];
5898 /* We can use this as a reload reg. */
5899 /* Mark the register as in use for this part of
5901 mark_reload_reg_in_use (i,
5903 reload_when_needed[r],
5905 reload_reg_rtx[r] = last_reg;
5906 reload_inherited[r] = 1;
5907 reload_inheritance_insn[r]
5908 = reg_reloaded_insn[i];
5909 reload_spill_index[r] = i;
5910 for (k = 0; k < nr; k++)
5911 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5919 /* Here's another way to see if the value is already lying around. */
5921 && reload_in[r] != 0
5922 && ! reload_inherited[r]
5923 && reload_out[r] == 0
5924 && (CONSTANT_P (reload_in[r])
5925 || GET_CODE (reload_in[r]) == PLUS
5926 || GET_CODE (reload_in[r]) == REG
5927 || GET_CODE (reload_in[r]) == MEM)
5928 && (reload_nregs[r] == max_group_size
5929 || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
5932 = find_equiv_reg (reload_in[r], insn, reload_reg_class[r],
5933 -1, NULL_PTR, 0, reload_mode[r]);
5938 if (GET_CODE (equiv) == REG)
5939 regno = REGNO (equiv);
5940 else if (GET_CODE (equiv) == SUBREG)
5942 /* This must be a SUBREG of a hard register.
5943 Make a new REG since this might be used in an
5944 address and not all machines support SUBREGs
5946 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5947 equiv = gen_rtx_REG (reload_mode[r], regno);
5953 /* If we found a spill reg, reject it unless it is free
5954 and of the desired class. */
5956 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5957 && ! reload_reg_free_for_value_p (regno, reload_opnum[r],
5958 reload_when_needed[r],
5960 reload_out[r], r, 1))
5961 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5965 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5968 /* We found a register that contains the value we need.
5969 If this register is the same as an `earlyclobber' operand
5970 of the current insn, just mark it as a place to reload from
5971 since we can't use it as the reload register itself. */
5974 for (i = 0; i < n_earlyclobbers; i++)
5975 if (reg_overlap_mentioned_for_reload_p (equiv,
5976 reload_earlyclobbers[i]))
5978 reload_override_in[r] = equiv;
5983 /* If the equiv register we have found is explicitly clobbered
5984 in the current insn, it depends on the reload type if we
5985 can use it, use it for reload_override_in, or not at all.
5986 In particular, we then can't use EQUIV for a
5987 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5989 if (equiv != 0 && regno_clobbered_p (regno, insn))
5991 switch (reload_when_needed[r])
5993 case RELOAD_FOR_OTHER_ADDRESS:
5994 case RELOAD_FOR_INPADDR_ADDRESS:
5995 case RELOAD_FOR_INPUT_ADDRESS:
5996 case RELOAD_FOR_OPADDR_ADDR:
5999 case RELOAD_FOR_INPUT:
6000 case RELOAD_FOR_OPERAND_ADDRESS:
6001 reload_override_in[r] = equiv;
6009 /* If we found an equivalent reg, say no code need be generated
6010 to load it, and use it as our reload reg. */
6011 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
6013 int nr = HARD_REGNO_NREGS (regno, reload_mode[r]);
6015 reload_reg_rtx[r] = equiv;
6016 reload_inherited[r] = 1;
6018 /* If reg_reloaded_valid is not set for this register,
6019 there might be a stale spill_reg_store lying around.
6020 We must clear it, since otherwise emit_reload_insns
6021 might delete the store. */
6022 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6023 spill_reg_store[regno] = NULL_RTX;
6024 /* If any of the hard registers in EQUIV are spill
6025 registers, mark them as in use for this insn. */
6026 for (k = 0; k < nr; k++)
6028 i = spill_reg_order[regno + k];
6031 mark_reload_reg_in_use (regno, reload_opnum[r],
6032 reload_when_needed[r],
6034 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6041 /* If we found a register to use already, or if this is an optional
6042 reload, we are done. */
6043 if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
6046 #if 0 /* No longer needed for correct operation. Might or might not
6047 give better code on the average. Want to experiment? */
6049 /* See if there is a later reload that has a class different from our
6050 class that intersects our class or that requires less register
6051 than our reload. If so, we must allocate a register to this
6052 reload now, since that reload might inherit a previous reload
6053 and take the only available register in our class. Don't do this
6054 for optional reloads since they will force all previous reloads
6055 to be allocated. Also don't do this for reloads that have been
6058 for (i = j + 1; i < n_reloads; i++)
6060 int s = reload_order[i];
6062 if ((reload_in[s] == 0 && reload_out[s] == 0
6063 && ! reload_secondary_p[s])
6064 || reload_optional[s])
6067 if ((reload_reg_class[s] != reload_reg_class[r]
6068 && reg_classes_intersect_p (reload_reg_class[r],
6069 reload_reg_class[s]))
6070 || reload_nregs[s] < reload_nregs[r])
6077 allocate_reload_reg (chain, r, j == n_reloads - 1, inheritance);
6081 /* Now allocate reload registers for anything non-optional that
6082 didn't get one yet. */
6083 for (j = 0; j < n_reloads; j++)
6085 register int r = reload_order[j];
6087 /* Ignore reloads that got marked inoperative. */
6088 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
6091 /* Skip reloads that already have a register allocated or are
6093 if (reload_reg_rtx[r] != 0 || reload_optional[r])
6096 if (! allocate_reload_reg (chain, r, j == n_reloads - 1, inheritance))
6100 /* If that loop got all the way, we have won. */
6104 /* Loop around and try without any inheritance. */
6105 /* First undo everything done by the failed attempt
6106 to allocate with inheritance. */
6107 bcopy ((char *) save_reload_reg_rtx, (char *) reload_reg_rtx,
6108 sizeof reload_reg_rtx);
6109 bcopy ((char *) save_reload_inherited, (char *) reload_inherited,
6110 sizeof reload_inherited);
6111 bcopy ((char *) save_reload_inheritance_insn,
6112 (char *) reload_inheritance_insn,
6113 sizeof reload_inheritance_insn);
6114 bcopy ((char *) save_reload_override_in, (char *) reload_override_in,
6115 sizeof reload_override_in);
6116 bcopy ((char *) save_reload_spill_index, (char *) reload_spill_index,
6117 sizeof reload_spill_index);
6118 COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
6119 COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
6120 COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
6121 save_reload_reg_used_in_op_addr);
6122 COPY_HARD_REG_SET (reload_reg_used_in_op_addr_reload,
6123 save_reload_reg_used_in_op_addr_reload);
6124 COPY_HARD_REG_SET (reload_reg_used_in_insn,
6125 save_reload_reg_used_in_insn);
6126 COPY_HARD_REG_SET (reload_reg_used_in_other_addr,
6127 save_reload_reg_used_in_other_addr);
6129 for (i = 0; i < reload_n_operands; i++)
6131 COPY_HARD_REG_SET (reload_reg_used_in_input[i],
6132 save_reload_reg_used_in_input[i]);
6133 COPY_HARD_REG_SET (reload_reg_used_in_output[i],
6134 save_reload_reg_used_in_output[i]);
6135 COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i],
6136 save_reload_reg_used_in_input_addr[i]);
6137 COPY_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i],
6138 save_reload_reg_used_in_inpaddr_addr[i]);
6139 COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i],
6140 save_reload_reg_used_in_output_addr[i]);
6141 COPY_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i],
6142 save_reload_reg_used_in_outaddr_addr[i]);
6146 /* If we thought we could inherit a reload, because it seemed that
6147 nothing else wanted the same reload register earlier in the insn,
6148 verify that assumption, now that all reloads have been assigned.
6149 Likewise for reloads where reload_override_in has been set. */
6151 /* If doing expensive optimizations, do one preliminary pass that doesn't
6152 cancel any inheritance, but removes reloads that have been needed only
6153 for reloads that we know can be inherited. */
6154 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6156 for (j = 0; j < n_reloads; j++)
6158 register int r = reload_order[j];
6160 if (reload_inherited[r] && reload_reg_rtx[r])
6161 check_reg = reload_reg_rtx[r];
6162 else if (reload_override_in[r]
6163 && (GET_CODE (reload_override_in[r]) == REG
6164 || GET_CODE (reload_override_in[r]) == SUBREG))
6165 check_reg = reload_override_in[r];
6168 if (! reload_reg_free_for_value_p (true_regnum (check_reg),
6170 reload_when_needed[r],
6172 (reload_inherited[r]
6173 ? reload_out[r] : const0_rtx),
6178 reload_inherited[r] = 0;
6179 reload_override_in[r] = 0;
6181 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6182 reload_override_in, then we do not need its related
6183 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6184 likewise for other reload types.
6185 We handle this by removing a reload when its only replacement
6186 is mentioned in reload_in of the reload we are going to inherit.
6187 A special case are auto_inc expressions; even if the input is
6188 inherited, we still need the address for the output. We can
6189 recognize them because they have RELOAD_OUT set but not
6191 If we suceeded removing some reload and we are doing a preliminary
6192 pass just to remove such reloads, make another pass, since the
6193 removal of one reload might allow us to inherit another one. */
6194 else if ((! reload_out[r] || reload_out_reg[r])
6195 && remove_address_replacements (reload_in[r]) && pass)
6200 /* Now that reload_override_in is known valid,
6201 actually override reload_in. */
6202 for (j = 0; j < n_reloads; j++)
6203 if (reload_override_in[j])
6204 reload_in[j] = reload_override_in[j];
6206 /* If this reload won't be done because it has been cancelled or is
6207 optional and not inherited, clear reload_reg_rtx so other
6208 routines (such as subst_reloads) don't get confused. */
6209 for (j = 0; j < n_reloads; j++)
6210 if (reload_reg_rtx[j] != 0
6211 && ((reload_optional[j] && ! reload_inherited[j])
6212 || (reload_in[j] == 0 && reload_out[j] == 0
6213 && ! reload_secondary_p[j])))
6215 int regno = true_regnum (reload_reg_rtx[j]);
6217 if (spill_reg_order[regno] >= 0)
6218 clear_reload_reg_in_use (regno, reload_opnum[j],
6219 reload_when_needed[j], reload_mode[j]);
6220 reload_reg_rtx[j] = 0;
6223 /* Record which pseudos and which spill regs have output reloads. */
6224 for (j = 0; j < n_reloads; j++)
6226 register int r = reload_order[j];
6228 i = reload_spill_index[r];
6230 /* I is nonneg if this reload uses a register.
6231 If reload_reg_rtx[r] is 0, this is an optional reload
6232 that we opted to ignore. */
6233 if (reload_out_reg[r] != 0 && GET_CODE (reload_out_reg[r]) == REG
6234 && reload_reg_rtx[r] != 0)
6236 register int nregno = REGNO (reload_out_reg[r]);
6239 if (nregno < FIRST_PSEUDO_REGISTER)
6240 nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
6243 reg_has_output_reload[nregno + nr] = 1;
6247 nr = HARD_REGNO_NREGS (i, reload_mode[r]);
6249 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6252 if (reload_when_needed[r] != RELOAD_OTHER
6253 && reload_when_needed[r] != RELOAD_FOR_OUTPUT
6254 && reload_when_needed[r] != RELOAD_FOR_INSN)
6260 /* Deallocate the reload register for reload R. This is called from
6261 remove_address_replacements. */
6263 deallocate_reload_reg (r)
6268 if (! reload_reg_rtx[r])
6270 regno = true_regnum (reload_reg_rtx[r]);
6271 reload_reg_rtx[r] = 0;
6272 if (spill_reg_order[regno] >= 0)
6273 clear_reload_reg_in_use (regno, reload_opnum[r], reload_when_needed[r],
6275 reload_spill_index[r] = -1;
6278 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
6279 reloads of the same item for fear that we might not have enough reload
6280 registers. However, normally they will get the same reload register
6281 and hence actually need not be loaded twice.
6283 Here we check for the most common case of this phenomenon: when we have
6284 a number of reloads for the same object, each of which were allocated
6285 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6286 reload, and is not modified in the insn itself. If we find such,
6287 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6288 This will not increase the number of spill registers needed and will
6289 prevent redundant code. */
6292 merge_assigned_reloads (insn)
6297 /* Scan all the reloads looking for ones that only load values and
6298 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6299 assigned and not modified by INSN. */
6301 for (i = 0; i < n_reloads; i++)
6303 int conflicting_input = 0;
6304 int max_input_address_opnum = -1;
6305 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6307 if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER
6308 || reload_out[i] != 0 || reload_reg_rtx[i] == 0
6309 || reg_set_p (reload_reg_rtx[i], insn))
6312 /* Look at all other reloads. Ensure that the only use of this
6313 reload_reg_rtx is in a reload that just loads the same value
6314 as we do. Note that any secondary reloads must be of the identical
6315 class since the values, modes, and result registers are the
6316 same, so we need not do anything with any secondary reloads. */
6318 for (j = 0; j < n_reloads; j++)
6320 if (i == j || reload_reg_rtx[j] == 0
6321 || ! reg_overlap_mentioned_p (reload_reg_rtx[j],
6325 if (reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS
6326 && reload_opnum[j] > max_input_address_opnum)
6327 max_input_address_opnum = reload_opnum[j];
6329 /* If the reload regs aren't exactly the same (e.g, different modes)
6330 or if the values are different, we can't merge this reload.
6331 But if it is an input reload, we might still merge
6332 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6334 if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
6335 || reload_out[j] != 0 || reload_in[j] == 0
6336 || ! rtx_equal_p (reload_in[i], reload_in[j]))
6338 if (reload_when_needed[j] != RELOAD_FOR_INPUT
6339 || ((reload_when_needed[i] != RELOAD_FOR_INPUT_ADDRESS
6340 || reload_opnum[i] > reload_opnum[j])
6341 && reload_when_needed[i] != RELOAD_FOR_OTHER_ADDRESS))
6343 conflicting_input = 1;
6344 if (min_conflicting_input_opnum > reload_opnum[j])
6345 min_conflicting_input_opnum = reload_opnum[j];
6349 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6350 we, in fact, found any matching reloads. */
6353 && max_input_address_opnum <= min_conflicting_input_opnum)
6355 for (j = 0; j < n_reloads; j++)
6356 if (i != j && reload_reg_rtx[j] != 0
6357 && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
6358 && (! conflicting_input
6359 || reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS
6360 || reload_when_needed[j] == RELOAD_FOR_OTHER_ADDRESS))
6362 reload_when_needed[i] = RELOAD_OTHER;
6364 reload_spill_index[j] = -1;
6365 transfer_replacements (i, j);
6368 /* If this is now RELOAD_OTHER, look for any reloads that load
6369 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6370 if they were for inputs, RELOAD_OTHER for outputs. Note that
6371 this test is equivalent to looking for reloads for this operand
6374 if (reload_when_needed[i] == RELOAD_OTHER)
6375 for (j = 0; j < n_reloads; j++)
6376 if (reload_in[j] != 0
6377 && reload_when_needed[i] != RELOAD_OTHER
6378 && reg_overlap_mentioned_for_reload_p (reload_in[j],
6380 reload_when_needed[j]
6381 = ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
6382 || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS)
6383 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6389 /* Output insns to reload values in and out of the chosen reload regs. */
6392 emit_reload_insns (chain)
6393 struct insn_chain *chain;
6395 rtx insn = chain->insn;
6398 rtx input_reload_insns[MAX_RECOG_OPERANDS];
6399 rtx other_input_address_reload_insns = 0;
6400 rtx other_input_reload_insns = 0;
6401 rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6402 rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6403 rtx output_reload_insns[MAX_RECOG_OPERANDS];
6404 rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6405 rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6406 rtx operand_reload_insns = 0;
6407 rtx other_operand_reload_insns = 0;
6408 rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6409 rtx following_insn = NEXT_INSN (insn);
6410 rtx before_insn = PREV_INSN (insn);
6412 /* Values to be put in spill_reg_store are put here first. */
6413 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6414 HARD_REG_SET reg_reloaded_died;
6416 CLEAR_HARD_REG_SET (reg_reloaded_died);
6418 for (j = 0; j < reload_n_operands; j++)
6419 input_reload_insns[j] = input_address_reload_insns[j]
6420 = inpaddr_address_reload_insns[j]
6421 = output_reload_insns[j] = output_address_reload_insns[j]
6422 = outaddr_address_reload_insns[j]
6423 = other_output_reload_insns[j] = 0;
6425 /* Now output the instructions to copy the data into and out of the
6426 reload registers. Do these in the order that the reloads were reported,
6427 since reloads of base and index registers precede reloads of operands
6428 and the operands may need the base and index registers reloaded. */
6430 for (j = 0; j < n_reloads; j++)
6433 rtx oldequiv_reg = 0;
6434 rtx this_reload_insn = 0;
6435 int expect_occurrences = 1;
6437 if (reload_reg_rtx[j]
6438 && REGNO (reload_reg_rtx[j]) < FIRST_PSEUDO_REGISTER)
6439 new_spill_reg_store[REGNO (reload_reg_rtx[j])] = 0;
6441 old = (reload_in[j] && GET_CODE (reload_in[j]) == MEM
6442 ? reload_in_reg[j] : reload_in[j]);
6445 /* AUTO_INC reloads need to be handled even if inherited. We got an
6446 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6447 && (! reload_inherited[j] || (reload_out[j] && ! reload_out_reg[j]))
6448 && ! rtx_equal_p (reload_reg_rtx[j], old)
6449 && reload_reg_rtx[j] != 0)
6451 register rtx reloadreg = reload_reg_rtx[j];
6453 enum machine_mode mode;
6456 /* Determine the mode to reload in.
6457 This is very tricky because we have three to choose from.
6458 There is the mode the insn operand wants (reload_inmode[J]).
6459 There is the mode of the reload register RELOADREG.
6460 There is the intrinsic mode of the operand, which we could find
6461 by stripping some SUBREGs.
6462 It turns out that RELOADREG's mode is irrelevant:
6463 we can change that arbitrarily.
6465 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6466 then the reload reg may not support QImode moves, so use SImode.
6467 If foo is in memory due to spilling a pseudo reg, this is safe,
6468 because the QImode value is in the least significant part of a
6469 slot big enough for a SImode. If foo is some other sort of
6470 memory reference, then it is impossible to reload this case,
6471 so previous passes had better make sure this never happens.
6473 Then consider a one-word union which has SImode and one of its
6474 members is a float, being fetched as (SUBREG:SF union:SI).
6475 We must fetch that as SFmode because we could be loading into
6476 a float-only register. In this case OLD's mode is correct.
6478 Consider an immediate integer: it has VOIDmode. Here we need
6479 to get a mode from something else.
6481 In some cases, there is a fourth mode, the operand's
6482 containing mode. If the insn specifies a containing mode for
6483 this operand, it overrides all others.
6485 I am not sure whether the algorithm here is always right,
6486 but it does the right things in those cases. */
6488 mode = GET_MODE (old);
6489 if (mode == VOIDmode)
6490 mode = reload_inmode[j];
6492 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6493 /* If we need a secondary register for this operation, see if
6494 the value is already in a register in that class. Don't
6495 do this if the secondary register will be used as a scratch
6498 if (reload_secondary_in_reload[j] >= 0
6499 && reload_secondary_in_icode[j] == CODE_FOR_nothing
6502 = find_equiv_reg (old, insn,
6503 reload_reg_class[reload_secondary_in_reload[j]],
6504 -1, NULL_PTR, 0, mode);
6507 /* If reloading from memory, see if there is a register
6508 that already holds the same value. If so, reload from there.
6509 We can pass 0 as the reload_reg_p argument because
6510 any other reload has either already been emitted,
6511 in which case find_equiv_reg will see the reload-insn,
6512 or has yet to be emitted, in which case it doesn't matter
6513 because we will use this equiv reg right away. */
6515 if (oldequiv == 0 && optimize
6516 && (GET_CODE (old) == MEM
6517 || (GET_CODE (old) == REG
6518 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6519 && reg_renumber[REGNO (old)] < 0)))
6520 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6521 -1, NULL_PTR, 0, mode);
6525 int regno = true_regnum (oldequiv);
6527 /* Don't use OLDEQUIV if any other reload changes it at an
6528 earlier stage of this insn or at this stage. */
6529 if (! reload_reg_free_for_value_p (regno, reload_opnum[j],
6530 reload_when_needed[j],
6531 reload_in[j], const0_rtx, j,
6535 /* If it is no cheaper to copy from OLDEQUIV into the
6536 reload register than it would be to move from memory,
6537 don't use it. Likewise, if we need a secondary register
6541 && ((REGNO_REG_CLASS (regno) != reload_reg_class[j]
6542 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
6543 reload_reg_class[j])
6544 >= MEMORY_MOVE_COST (mode, reload_reg_class[j], 1)))
6545 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6546 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6550 #ifdef SECONDARY_MEMORY_NEEDED
6551 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6552 reload_reg_class[j],
6559 /* delete_output_reload is only invoked properly if old contains
6560 the original pseudo register. Since this is replaced with a
6561 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6562 find the pseudo in RELOAD_IN_REG. */
6564 && reload_override_in[j]
6565 && GET_CODE (reload_in_reg[j]) == REG)
6568 old = reload_in_reg[j];
6572 else if (GET_CODE (oldequiv) == REG)
6573 oldequiv_reg = oldequiv;
6574 else if (GET_CODE (oldequiv) == SUBREG)
6575 oldequiv_reg = SUBREG_REG (oldequiv);
6577 /* If we are reloading from a register that was recently stored in
6578 with an output-reload, see if we can prove there was
6579 actually no need to store the old value in it. */
6581 if (optimize && GET_CODE (oldequiv) == REG
6582 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6583 && spill_reg_store[REGNO (oldequiv)]
6584 && GET_CODE (old) == REG
6585 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6586 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6587 reload_out_reg[j])))
6588 delete_output_reload (insn, j, REGNO (oldequiv));
6590 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6591 then load RELOADREG from OLDEQUIV. Note that we cannot use
6592 gen_lowpart_common since it can do the wrong thing when
6593 RELOADREG has a multi-word mode. Note that RELOADREG
6594 must always be a REG here. */
6596 if (GET_MODE (reloadreg) != mode)
6597 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6598 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6599 oldequiv = SUBREG_REG (oldequiv);
6600 if (GET_MODE (oldequiv) != VOIDmode
6601 && mode != GET_MODE (oldequiv))
6602 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6604 /* Switch to the right place to emit the reload insns. */
6605 switch (reload_when_needed[j])
6608 where = &other_input_reload_insns;
6610 case RELOAD_FOR_INPUT:
6611 where = &input_reload_insns[reload_opnum[j]];
6613 case RELOAD_FOR_INPUT_ADDRESS:
6614 where = &input_address_reload_insns[reload_opnum[j]];
6616 case RELOAD_FOR_INPADDR_ADDRESS:
6617 where = &inpaddr_address_reload_insns[reload_opnum[j]];
6619 case RELOAD_FOR_OUTPUT_ADDRESS:
6620 where = &output_address_reload_insns[reload_opnum[j]];
6622 case RELOAD_FOR_OUTADDR_ADDRESS:
6623 where = &outaddr_address_reload_insns[reload_opnum[j]];
6625 case RELOAD_FOR_OPERAND_ADDRESS:
6626 where = &operand_reload_insns;
6628 case RELOAD_FOR_OPADDR_ADDR:
6629 where = &other_operand_reload_insns;
6631 case RELOAD_FOR_OTHER_ADDRESS:
6632 where = &other_input_address_reload_insns;
6638 push_to_sequence (*where);
6641 /* Auto-increment addresses must be reloaded in a special way. */
6642 if (reload_out[j] && ! reload_out_reg[j])
6644 /* We are not going to bother supporting the case where a
6645 incremented register can't be copied directly from
6646 OLDEQUIV since this seems highly unlikely. */
6647 if (reload_secondary_in_reload[j] >= 0)
6650 if (reload_inherited[j])
6651 oldequiv = reloadreg;
6653 old = XEXP (reload_in_reg[j], 0);
6655 if (optimize && GET_CODE (oldequiv) == REG
6656 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6657 && spill_reg_store[REGNO (oldequiv)]
6658 && GET_CODE (old) == REG
6659 && (dead_or_set_p (insn,
6660 spill_reg_stored_to[REGNO (oldequiv)])
6661 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6663 delete_output_reload (insn, j, REGNO (oldequiv));
6665 /* Prevent normal processing of this reload. */
6667 /* Output a special code sequence for this case. */
6668 new_spill_reg_store[REGNO (reloadreg)]
6669 = inc_for_reload (reloadreg, oldequiv, reload_out[j],
6673 /* If we are reloading a pseudo-register that was set by the previous
6674 insn, see if we can get rid of that pseudo-register entirely
6675 by redirecting the previous insn into our reload register. */
6677 else if (optimize && GET_CODE (old) == REG
6678 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6679 && dead_or_set_p (insn, old)
6680 /* This is unsafe if some other reload
6681 uses the same reg first. */
6682 && reload_reg_free_for_value_p (REGNO (reloadreg),
6684 reload_when_needed[j],
6688 rtx temp = PREV_INSN (insn);
6689 while (temp && GET_CODE (temp) == NOTE)
6690 temp = PREV_INSN (temp);
6692 && GET_CODE (temp) == INSN
6693 && GET_CODE (PATTERN (temp)) == SET
6694 && SET_DEST (PATTERN (temp)) == old
6695 /* Make sure we can access insn_operand_constraint. */
6696 && asm_noperands (PATTERN (temp)) < 0
6697 /* This is unsafe if prev insn rejects our reload reg. */
6698 && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
6700 /* This is unsafe if operand occurs more than once in current
6701 insn. Perhaps some occurrences aren't reloaded. */
6702 && count_occurrences (PATTERN (insn), old) == 1
6703 /* Don't risk splitting a matching pair of operands. */
6704 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6706 /* Store into the reload register instead of the pseudo. */
6707 SET_DEST (PATTERN (temp)) = reloadreg;
6709 /* If the previous insn is an output reload, the source is
6710 a reload register, and its spill_reg_store entry will
6711 contain the previous destination. This is now
6713 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6714 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6716 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6717 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6720 /* If these are the only uses of the pseudo reg,
6721 pretend for GDB it lives in the reload reg we used. */
6722 if (REG_N_DEATHS (REGNO (old)) == 1
6723 && REG_N_SETS (REGNO (old)) == 1)
6725 reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
6726 alter_reg (REGNO (old), -1);
6732 /* We can't do that, so output an insn to load RELOADREG. */
6736 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6737 rtx second_reload_reg = 0;
6738 enum insn_code icode;
6740 /* If we have a secondary reload, pick up the secondary register
6741 and icode, if any. If OLDEQUIV and OLD are different or
6742 if this is an in-out reload, recompute whether or not we
6743 still need a secondary register and what the icode should
6744 be. If we still need a secondary register and the class or
6745 icode is different, go back to reloading from OLD if using
6746 OLDEQUIV means that we got the wrong type of register. We
6747 cannot have different class or icode due to an in-out reload
6748 because we don't make such reloads when both the input and
6749 output need secondary reload registers. */
6751 if (reload_secondary_in_reload[j] >= 0)
6753 int secondary_reload = reload_secondary_in_reload[j];
6754 rtx real_oldequiv = oldequiv;
6757 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6758 and similarly for OLD.
6759 See comments in get_secondary_reload in reload.c. */
6760 /* If it is a pseudo that cannot be replaced with its
6761 equivalent MEM, we must fall back to reload_in, which
6762 will have all the necessary substitutions registered. */
6764 if (GET_CODE (oldequiv) == REG
6765 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6766 && reg_equiv_memory_loc[REGNO (oldequiv)] != 0)
6768 if (reg_equiv_address[REGNO (oldequiv)]
6769 || num_not_at_initial_offset)
6770 real_oldequiv = reload_in[j];
6772 real_oldequiv = reg_equiv_mem[REGNO (oldequiv)];
6775 if (GET_CODE (old) == REG
6776 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6777 && reg_equiv_memory_loc[REGNO (old)] != 0)
6779 if (reg_equiv_address[REGNO (old)]
6780 || num_not_at_initial_offset)
6781 real_old = reload_in[j];
6783 real_old = reg_equiv_mem[REGNO (old)];
6786 second_reload_reg = reload_reg_rtx[secondary_reload];
6787 icode = reload_secondary_in_icode[j];
6789 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6790 || (reload_in[j] != 0 && reload_out[j] != 0))
6792 enum reg_class new_class
6793 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6794 mode, real_oldequiv);
6796 if (new_class == NO_REGS)
6797 second_reload_reg = 0;
6800 enum insn_code new_icode;
6801 enum machine_mode new_mode;
6803 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6804 REGNO (second_reload_reg)))
6805 oldequiv = old, real_oldequiv = real_old;
6808 new_icode = reload_in_optab[(int) mode];
6809 if (new_icode != CODE_FOR_nothing
6810 && ((insn_operand_predicate[(int) new_icode][0]
6811 && ! ((*insn_operand_predicate[(int) new_icode][0])
6813 || (insn_operand_predicate[(int) new_icode][1]
6814 && ! ((*insn_operand_predicate[(int) new_icode][1])
6815 (real_oldequiv, mode)))))
6816 new_icode = CODE_FOR_nothing;
6818 if (new_icode == CODE_FOR_nothing)
6821 new_mode = insn_operand_mode[(int) new_icode][2];
6823 if (GET_MODE (second_reload_reg) != new_mode)
6825 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6827 oldequiv = old, real_oldequiv = real_old;
6830 = gen_rtx_REG (new_mode,
6831 REGNO (second_reload_reg));
6837 /* If we still need a secondary reload register, check
6838 to see if it is being used as a scratch or intermediate
6839 register and generate code appropriately. If we need
6840 a scratch register, use REAL_OLDEQUIV since the form of
6841 the insn may depend on the actual address if it is
6844 if (second_reload_reg)
6846 if (icode != CODE_FOR_nothing)
6848 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6849 second_reload_reg));
6854 /* See if we need a scratch register to load the
6855 intermediate register (a tertiary reload). */
6856 enum insn_code tertiary_icode
6857 = reload_secondary_in_icode[secondary_reload];
6859 if (tertiary_icode != CODE_FOR_nothing)
6861 rtx third_reload_reg
6862 = reload_reg_rtx[reload_secondary_in_reload[secondary_reload]];
6864 emit_insn ((GEN_FCN (tertiary_icode)
6865 (second_reload_reg, real_oldequiv,
6866 third_reload_reg)));
6869 gen_reload (second_reload_reg, real_oldequiv,
6871 reload_when_needed[j]);
6873 oldequiv = second_reload_reg;
6879 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6881 rtx real_oldequiv = oldequiv;
6883 if ((GET_CODE (oldequiv) == REG
6884 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6885 && reg_equiv_memory_loc[REGNO (oldequiv)] != 0)
6886 || (GET_CODE (oldequiv) == SUBREG
6887 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6888 && (REGNO (SUBREG_REG (oldequiv))
6889 >= FIRST_PSEUDO_REGISTER)
6890 && (reg_equiv_memory_loc
6891 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6892 real_oldequiv = reload_in[j];
6893 gen_reload (reloadreg, real_oldequiv, reload_opnum[j],
6894 reload_when_needed[j]);
6899 this_reload_insn = get_last_insn ();
6900 /* End this sequence. */
6901 *where = get_insns ();
6904 /* Update reload_override_in so that delete_address_reloads_1
6905 can see the actual register usage. */
6907 reload_override_in[j] = oldequiv;
6910 /* When inheriting a wider reload, we have a MEM in reload_in[j],
6911 e.g. inheriting a SImode output reload for
6912 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6913 if (optimize && reload_inherited[j] && reload_in[j]
6914 && GET_CODE (reload_in[j]) == MEM
6915 && GET_CODE (reload_in_reg[j]) == MEM
6916 && reload_spill_index[j] >= 0
6917 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6920 = count_occurrences (PATTERN (insn), reload_in[j]) == 1 ? 0 : -1;
6922 = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6925 /* If we are reloading a register that was recently stored in with an
6926 output-reload, see if we can prove there was
6927 actually no need to store the old value in it. */
6930 && (reload_inherited[j] || reload_override_in[j])
6931 && reload_reg_rtx[j]
6932 && GET_CODE (reload_reg_rtx[j]) == REG
6933 && spill_reg_store[REGNO (reload_reg_rtx[j])] != 0
6935 /* There doesn't seem to be any reason to restrict this to pseudos
6936 and doing so loses in the case where we are copying from a
6937 register of the wrong class. */
6938 && REGNO (spill_reg_stored_to[REGNO (reload_reg_rtx[j])])
6939 >= FIRST_PSEUDO_REGISTER
6941 /* The insn might have already some references to stackslots
6942 replaced by MEMs, while reload_out_reg still names the
6944 && (dead_or_set_p (insn,
6945 spill_reg_stored_to[REGNO (reload_reg_rtx[j])])
6946 || rtx_equal_p (spill_reg_stored_to[REGNO (reload_reg_rtx[j])],
6947 reload_out_reg[j])))
6948 delete_output_reload (insn, j, REGNO (reload_reg_rtx[j]));
6950 /* Input-reloading is done. Now do output-reloading,
6951 storing the value from the reload-register after the main insn
6952 if reload_out[j] is nonzero.
6954 ??? At some point we need to support handling output reloads of
6955 JUMP_INSNs or insns that set cc0. */
6957 /* If this is an output reload that stores something that is
6958 not loaded in this same reload, see if we can eliminate a previous
6961 rtx pseudo = reload_out_reg[j];
6964 && GET_CODE (pseudo) == REG
6965 && ! rtx_equal_p (reload_in_reg[j], pseudo)
6966 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6967 && reg_last_reload_reg[REGNO (pseudo)])
6969 int pseudo_no = REGNO (pseudo);
6970 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6972 /* We don't need to test full validity of last_regno for
6973 inherit here; we only want to know if the store actually
6974 matches the pseudo. */
6975 if (reg_reloaded_contents[last_regno] == pseudo_no
6976 && spill_reg_store[last_regno]
6977 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6978 delete_output_reload (insn, j, last_regno);
6982 old = reload_out_reg[j];
6984 && reload_reg_rtx[j] != old
6985 && reload_reg_rtx[j] != 0)
6987 register rtx reloadreg = reload_reg_rtx[j];
6988 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6989 register rtx second_reloadreg = 0;
6992 enum machine_mode mode;
6995 /* An output operand that dies right away does need a reload,
6996 but need not be copied from it. Show the new location in the
6998 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6999 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7001 XEXP (note, 0) = reload_reg_rtx[j];
7004 /* Likewise for a SUBREG of an operand that dies. */
7005 else if (GET_CODE (old) == SUBREG
7006 && GET_CODE (SUBREG_REG (old)) == REG
7007 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7010 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7014 else if (GET_CODE (old) == SCRATCH)
7015 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7016 but we don't want to make an output reload. */
7020 /* Strip off of OLD any size-increasing SUBREGs such as
7021 (SUBREG:SI foo:QI 0). */
7023 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
7024 && (GET_MODE_SIZE (GET_MODE (old))
7025 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
7026 old = SUBREG_REG (old);
7029 /* If is a JUMP_INSN, we can't support output reloads yet. */
7030 if (GET_CODE (insn) == JUMP_INSN)
7033 if (reload_when_needed[j] == RELOAD_OTHER)
7036 push_to_sequence (output_reload_insns[reload_opnum[j]]);
7038 old = reload_out[j];
7040 /* Determine the mode to reload in.
7041 See comments above (for input reloading). */
7043 mode = GET_MODE (old);
7044 if (mode == VOIDmode)
7046 /* VOIDmode should never happen for an output. */
7047 if (asm_noperands (PATTERN (insn)) < 0)
7048 /* It's the compiler's fault. */
7049 fatal_insn ("VOIDmode on an output", insn);
7050 error_for_asm (insn, "output operand is constant in `asm'");
7051 /* Prevent crash--use something we know is valid. */
7053 old = gen_rtx_REG (mode, REGNO (reloadreg));
7056 if (GET_MODE (reloadreg) != mode)
7057 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
7059 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7061 /* If we need two reload regs, set RELOADREG to the intermediate
7062 one, since it will be stored into OLD. We might need a secondary
7063 register only for an input reload, so check again here. */
7065 if (reload_secondary_out_reload[j] >= 0)
7069 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
7070 && reg_equiv_mem[REGNO (old)] != 0)
7071 real_old = reg_equiv_mem[REGNO (old)];
7073 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
7077 second_reloadreg = reloadreg;
7078 reloadreg = reload_reg_rtx[reload_secondary_out_reload[j]];
7080 /* See if RELOADREG is to be used as a scratch register
7081 or as an intermediate register. */
7082 if (reload_secondary_out_icode[j] != CODE_FOR_nothing)
7084 emit_insn ((GEN_FCN (reload_secondary_out_icode[j])
7085 (real_old, second_reloadreg, reloadreg)));
7090 /* See if we need both a scratch and intermediate reload
7093 int secondary_reload = reload_secondary_out_reload[j];
7094 enum insn_code tertiary_icode
7095 = reload_secondary_out_icode[secondary_reload];
7097 if (GET_MODE (reloadreg) != mode)
7098 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
7100 if (tertiary_icode != CODE_FOR_nothing)
7103 = reload_reg_rtx[reload_secondary_out_reload[secondary_reload]];
7106 /* Copy primary reload reg to secondary reload reg.
7107 (Note that these have been swapped above, then
7108 secondary reload reg to OLD using our insn. */
7110 /* If REAL_OLD is a paradoxical SUBREG, remove it
7111 and try to put the opposite SUBREG on
7113 if (GET_CODE (real_old) == SUBREG
7114 && (GET_MODE_SIZE (GET_MODE (real_old))
7115 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7116 && 0 != (tem = gen_lowpart_common
7117 (GET_MODE (SUBREG_REG (real_old)),
7119 real_old = SUBREG_REG (real_old), reloadreg = tem;
7121 gen_reload (reloadreg, second_reloadreg,
7122 reload_opnum[j], reload_when_needed[j]);
7123 emit_insn ((GEN_FCN (tertiary_icode)
7124 (real_old, reloadreg, third_reloadreg)));
7129 /* Copy between the reload regs here and then to
7132 gen_reload (reloadreg, second_reloadreg,
7133 reload_opnum[j], reload_when_needed[j]);
7139 /* Output the last reload insn. */
7144 /* Don't output the last reload if OLD is not the dest of
7145 INSN and is in the src and is clobbered by INSN. */
7146 if (! flag_expensive_optimizations
7147 || GET_CODE (old) != REG
7148 || !(set = single_set (insn))
7149 || rtx_equal_p (old, SET_DEST (set))
7150 || !reg_mentioned_p (old, SET_SRC (set))
7151 || !regno_clobbered_p (REGNO (old), insn))
7152 gen_reload (old, reloadreg, reload_opnum[j],
7153 reload_when_needed[j]);
7156 /* Look at all insns we emitted, just to be safe. */
7157 for (p = get_insns (); p; p = NEXT_INSN (p))
7158 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
7160 rtx pat = PATTERN (p);
7162 /* If this output reload doesn't come from a spill reg,
7163 clear any memory of reloaded copies of the pseudo reg.
7164 If this output reload comes from a spill reg,
7165 reg_has_output_reload will make this do nothing. */
7166 note_stores (pat, forget_old_reloads_1);
7168 if (reg_mentioned_p (reload_reg_rtx[j], pat))
7170 rtx set = single_set (insn);
7171 if (reload_spill_index[j] < 0
7173 && SET_SRC (set) == reload_reg_rtx[j])
7175 int src = REGNO (SET_SRC (set));
7177 reload_spill_index[j] = src;
7178 SET_HARD_REG_BIT (reg_is_output_reload, src);
7179 if (find_regno_note (insn, REG_DEAD, src))
7180 SET_HARD_REG_BIT (reg_reloaded_died, src);
7182 if (REGNO (reload_reg_rtx[j]) < FIRST_PSEUDO_REGISTER)
7184 int s = reload_secondary_out_reload[j];
7185 set = single_set (p);
7186 /* If this reload copies only to the secondary reload
7187 register, the secondary reload does the actual
7189 if (s >= 0 && set == NULL_RTX)
7190 ; /* We can't tell what function the secondary reload
7191 has and where the actual store to the pseudo is
7192 made; leave new_spill_reg_store alone. */
7194 && SET_SRC (set) == reload_reg_rtx[j]
7195 && SET_DEST (set) == reload_reg_rtx[s])
7197 /* Usually the next instruction will be the
7198 secondary reload insn; if we can confirm
7199 that it is, setting new_spill_reg_store to
7200 that insn will allow an extra optimization. */
7201 rtx s_reg = reload_reg_rtx[s];
7202 rtx next = NEXT_INSN (p);
7203 reload_out[s] = reload_out[j];
7204 reload_out_reg[s] = reload_out_reg[j];
7205 set = single_set (next);
7206 if (set && SET_SRC (set) == s_reg
7207 && ! new_spill_reg_store[REGNO (s_reg)])
7209 SET_HARD_REG_BIT (reg_is_output_reload,
7211 new_spill_reg_store[REGNO (s_reg)] = next;
7215 new_spill_reg_store[REGNO (reload_reg_rtx[j])] = p;
7220 if (reload_when_needed[j] == RELOAD_OTHER)
7222 emit_insns (other_output_reload_insns[reload_opnum[j]]);
7223 other_output_reload_insns[reload_opnum[j]] = get_insns ();
7226 output_reload_insns[reload_opnum[j]] = get_insns ();
7232 /* Now write all the insns we made for reloads in the order expected by
7233 the allocation functions. Prior to the insn being reloaded, we write
7234 the following reloads:
7236 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7238 RELOAD_OTHER reloads.
7240 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7241 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7242 RELOAD_FOR_INPUT reload for the operand.
7244 RELOAD_FOR_OPADDR_ADDRS reloads.
7246 RELOAD_FOR_OPERAND_ADDRESS reloads.
7248 After the insn being reloaded, we write the following:
7250 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7251 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7252 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7253 reloads for the operand. The RELOAD_OTHER output reloads are
7254 output in descending order by reload number. */
7256 emit_insns_before (other_input_address_reload_insns, insn);
7257 emit_insns_before (other_input_reload_insns, insn);
7259 for (j = 0; j < reload_n_operands; j++)
7261 emit_insns_before (inpaddr_address_reload_insns[j], insn);
7262 emit_insns_before (input_address_reload_insns[j], insn);
7263 emit_insns_before (input_reload_insns[j], insn);
7266 emit_insns_before (other_operand_reload_insns, insn);
7267 emit_insns_before (operand_reload_insns, insn);
7269 for (j = 0; j < reload_n_operands; j++)
7271 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
7272 emit_insns_before (output_address_reload_insns[j], following_insn);
7273 emit_insns_before (output_reload_insns[j], following_insn);
7274 emit_insns_before (other_output_reload_insns[j], following_insn);
7277 /* Keep basic block info up to date. */
7280 if (basic_block_head[chain->block] == insn)
7281 basic_block_head[chain->block] = NEXT_INSN (before_insn);
7282 if (basic_block_end[chain->block] == insn)
7283 basic_block_end[chain->block] = PREV_INSN (following_insn);
7286 /* For all the spill regs newly reloaded in this instruction,
7287 record what they were reloaded from, so subsequent instructions
7288 can inherit the reloads.
7290 Update spill_reg_store for the reloads of this insn.
7291 Copy the elements that were updated in the loop above. */
7293 for (j = 0; j < n_reloads; j++)
7295 register int r = reload_order[j];
7296 register int i = reload_spill_index[r];
7298 /* If this is a non-inherited input reload from a pseudo, we must
7299 clear any memory of a previous store to the same pseudo. Only do
7300 something if there will not be an output reload for the pseudo
7302 if (reload_in_reg[r] != 0
7303 && ! (reload_inherited[r] || reload_override_in[r]))
7305 rtx reg = reload_in_reg[r];
7307 if (GET_CODE (reg) == SUBREG)
7308 reg = SUBREG_REG (reg);
7310 if (GET_CODE (reg) == REG
7311 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7312 && ! reg_has_output_reload[REGNO (reg)])
7314 int nregno = REGNO (reg);
7316 if (reg_last_reload_reg[nregno])
7318 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7320 if (reg_reloaded_contents[last_regno] == nregno)
7321 spill_reg_store[last_regno] = 0;
7326 /* I is nonneg if this reload used a register.
7327 If reload_reg_rtx[r] is 0, this is an optional reload
7328 that we opted to ignore. */
7330 if (i >= 0 && reload_reg_rtx[r] != 0)
7333 = HARD_REGNO_NREGS (i, GET_MODE (reload_reg_rtx[r]));
7335 int part_reaches_end = 0;
7336 int all_reaches_end = 1;
7338 /* For a multi register reload, we need to check if all or part
7339 of the value lives to the end. */
7340 for (k = 0; k < nr; k++)
7342 if (reload_reg_reaches_end_p (i + k, reload_opnum[r],
7343 reload_when_needed[r]))
7344 part_reaches_end = 1;
7346 all_reaches_end = 0;
7349 /* Ignore reloads that don't reach the end of the insn in
7351 if (all_reaches_end)
7353 /* First, clear out memory of what used to be in this spill reg.
7354 If consecutive registers are used, clear them all. */
7356 for (k = 0; k < nr; k++)
7357 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7359 /* Maybe the spill reg contains a copy of reload_out. */
7360 if (reload_out[r] != 0
7361 && (GET_CODE (reload_out[r]) == REG
7363 || ! reload_out_reg[r]
7365 || GET_CODE (reload_out_reg[r]) == REG))
7367 rtx out = (GET_CODE (reload_out[r]) == REG
7371 /* AUTO_INC */ : XEXP (reload_in_reg[r], 0));
7372 register int nregno = REGNO (out);
7373 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7374 : HARD_REGNO_NREGS (nregno,
7375 GET_MODE (reload_reg_rtx[r])));
7377 spill_reg_store[i] = new_spill_reg_store[i];
7378 spill_reg_stored_to[i] = out;
7379 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
7381 /* If NREGNO is a hard register, it may occupy more than
7382 one register. If it does, say what is in the
7383 rest of the registers assuming that both registers
7384 agree on how many words the object takes. If not,
7385 invalidate the subsequent registers. */
7387 if (nregno < FIRST_PSEUDO_REGISTER)
7388 for (k = 1; k < nnr; k++)
7389 reg_last_reload_reg[nregno + k]
7391 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
7392 REGNO (reload_reg_rtx[r]) + k)
7395 /* Now do the inverse operation. */
7396 for (k = 0; k < nr; k++)
7398 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7399 reg_reloaded_contents[i + k]
7400 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7403 reg_reloaded_insn[i + k] = insn;
7404 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7408 /* Maybe the spill reg contains a copy of reload_in. Only do
7409 something if there will not be an output reload for
7410 the register being reloaded. */
7411 else if (reload_out_reg[r] == 0
7412 && reload_in[r] != 0
7413 && ((GET_CODE (reload_in[r]) == REG
7414 && REGNO (reload_in[r]) >= FIRST_PSEUDO_REGISTER
7415 && ! reg_has_output_reload[REGNO (reload_in[r])])
7416 || (GET_CODE (reload_in_reg[r]) == REG
7417 && ! reg_has_output_reload[REGNO (reload_in_reg[r])]))
7418 && ! reg_set_p (reload_reg_rtx[r], PATTERN (insn)))
7420 register int nregno;
7423 if (GET_CODE (reload_in[r]) == REG
7424 && REGNO (reload_in[r]) >= FIRST_PSEUDO_REGISTER)
7425 nregno = REGNO (reload_in[r]);
7426 else if (GET_CODE (reload_in_reg[r]) == REG)
7427 nregno = REGNO (reload_in_reg[r]);
7429 nregno = REGNO (XEXP (reload_in_reg[r], 0));
7431 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7432 : HARD_REGNO_NREGS (nregno,
7433 GET_MODE (reload_reg_rtx[r])));
7435 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
7437 if (nregno < FIRST_PSEUDO_REGISTER)
7438 for (k = 1; k < nnr; k++)
7439 reg_last_reload_reg[nregno + k]
7441 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
7442 REGNO (reload_reg_rtx[r]) + k)
7445 /* Unless we inherited this reload, show we haven't
7446 recently done a store.
7447 Previous stores of inherited auto_inc expressions
7448 also have to be discarded. */
7449 if (! reload_inherited[r]
7450 || (reload_out[r] && ! reload_out_reg[r]))
7451 spill_reg_store[i] = 0;
7453 for (k = 0; k < nr; k++)
7455 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7456 reg_reloaded_contents[i + k]
7457 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7460 reg_reloaded_insn[i + k] = insn;
7461 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7466 /* However, if part of the reload reaches the end, then we must
7467 invalidate the old info for the part that survives to the end. */
7468 else if (part_reaches_end)
7470 for (k = 0; k < nr; k++)
7471 if (reload_reg_reaches_end_p (i + k,
7473 reload_when_needed[r]))
7474 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7478 /* The following if-statement was #if 0'd in 1.34 (or before...).
7479 It's reenabled in 1.35 because supposedly nothing else
7480 deals with this problem. */
7482 /* If a register gets output-reloaded from a non-spill register,
7483 that invalidates any previous reloaded copy of it.
7484 But forget_old_reloads_1 won't get to see it, because
7485 it thinks only about the original insn. So invalidate it here. */
7486 if (i < 0 && reload_out[r] != 0
7487 && (GET_CODE (reload_out[r]) == REG
7488 || (GET_CODE (reload_out[r]) == MEM
7489 && GET_CODE (reload_out_reg[r]) == REG)))
7491 rtx out = (GET_CODE (reload_out[r]) == REG
7492 ? reload_out[r] : reload_out_reg[r]);
7493 register int nregno = REGNO (out);
7494 if (nregno >= FIRST_PSEUDO_REGISTER)
7496 rtx src_reg, store_insn;
7498 reg_last_reload_reg[nregno] = 0;
7500 /* If we can find a hard register that is stored, record
7501 the storing insn so that we may delete this insn with
7502 delete_output_reload. */
7503 src_reg = reload_reg_rtx[r];
7505 /* If this is an optional reload, try to find the source reg
7506 from an input reload. */
7509 rtx set = single_set (insn);
7510 if (set && SET_DEST (set) == reload_out[r])
7514 src_reg = SET_SRC (set);
7516 for (k = 0; k < n_reloads; k++)
7518 if (reload_in[k] == src_reg)
7520 src_reg = reload_reg_rtx[k];
7527 store_insn = new_spill_reg_store[REGNO (src_reg)];
7528 if (src_reg && GET_CODE (src_reg) == REG
7529 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7531 int src_regno = REGNO (src_reg);
7532 int nr = HARD_REGNO_NREGS (src_regno, reload_mode[r]);
7533 /* The place where to find a death note varies with
7534 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7535 necessarily checked exactly in the code that moves
7536 notes, so just check both locations. */
7537 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7539 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7542 spill_reg_store[src_regno + nr] = store_insn;
7543 spill_reg_stored_to[src_regno + nr] = out;
7544 reg_reloaded_contents[src_regno + nr] = nregno;
7545 reg_reloaded_insn[src_regno + nr] = store_insn;
7546 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7547 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7548 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7550 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7552 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7554 reg_last_reload_reg[nregno] = src_reg;
7559 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (reload_out[r]));
7561 while (num_regs-- > 0)
7562 reg_last_reload_reg[nregno + num_regs] = 0;
7566 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7569 /* Emit code to perform a reload from IN (which may be a reload register) to
7570 OUT (which may also be a reload register). IN or OUT is from operand
7571 OPNUM with reload type TYPE.
7573 Returns first insn emitted. */
7576 gen_reload (out, in, opnum, type)
7580 enum reload_type type;
7582 rtx last = get_last_insn ();
7585 /* If IN is a paradoxical SUBREG, remove it and try to put the
7586 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7587 if (GET_CODE (in) == SUBREG
7588 && (GET_MODE_SIZE (GET_MODE (in))
7589 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7590 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7591 in = SUBREG_REG (in), out = tem;
7592 else if (GET_CODE (out) == SUBREG
7593 && (GET_MODE_SIZE (GET_MODE (out))
7594 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7595 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7596 out = SUBREG_REG (out), in = tem;
7598 /* How to do this reload can get quite tricky. Normally, we are being
7599 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7600 register that didn't get a hard register. In that case we can just
7601 call emit_move_insn.
7603 We can also be asked to reload a PLUS that adds a register or a MEM to
7604 another register, constant or MEM. This can occur during frame pointer
7605 elimination and while reloading addresses. This case is handled by
7606 trying to emit a single insn to perform the add. If it is not valid,
7607 we use a two insn sequence.
7609 Finally, we could be called to handle an 'o' constraint by putting
7610 an address into a register. In that case, we first try to do this
7611 with a named pattern of "reload_load_address". If no such pattern
7612 exists, we just emit a SET insn and hope for the best (it will normally
7613 be valid on machines that use 'o').
7615 This entire process is made complex because reload will never
7616 process the insns we generate here and so we must ensure that
7617 they will fit their constraints and also by the fact that parts of
7618 IN might be being reloaded separately and replaced with spill registers.
7619 Because of this, we are, in some sense, just guessing the right approach
7620 here. The one listed above seems to work.
7622 ??? At some point, this whole thing needs to be rethought. */
7624 if (GET_CODE (in) == PLUS
7625 && (GET_CODE (XEXP (in, 0)) == REG
7626 || GET_CODE (XEXP (in, 0)) == SUBREG
7627 || GET_CODE (XEXP (in, 0)) == MEM)
7628 && (GET_CODE (XEXP (in, 1)) == REG
7629 || GET_CODE (XEXP (in, 1)) == SUBREG
7630 || CONSTANT_P (XEXP (in, 1))
7631 || GET_CODE (XEXP (in, 1)) == MEM))
7633 /* We need to compute the sum of a register or a MEM and another
7634 register, constant, or MEM, and put it into the reload
7635 register. The best possible way of doing this is if the machine
7636 has a three-operand ADD insn that accepts the required operands.
7638 The simplest approach is to try to generate such an insn and see if it
7639 is recognized and matches its constraints. If so, it can be used.
7641 It might be better not to actually emit the insn unless it is valid,
7642 but we need to pass the insn as an operand to `recog' and
7643 `extract_insn' and it is simpler to emit and then delete the insn if
7644 not valid than to dummy things up. */
7646 rtx op0, op1, tem, insn;
7649 op0 = find_replacement (&XEXP (in, 0));
7650 op1 = find_replacement (&XEXP (in, 1));
7652 /* Since constraint checking is strict, commutativity won't be
7653 checked, so we need to do that here to avoid spurious failure
7654 if the add instruction is two-address and the second operand
7655 of the add is the same as the reload reg, which is frequently
7656 the case. If the insn would be A = B + A, rearrange it so
7657 it will be A = A + B as constrain_operands expects. */
7659 if (GET_CODE (XEXP (in, 1)) == REG
7660 && REGNO (out) == REGNO (XEXP (in, 1)))
7661 tem = op0, op0 = op1, op1 = tem;
7663 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7664 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7666 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7667 code = recog_memoized (insn);
7671 extract_insn (insn);
7672 /* We want constrain operands to treat this insn strictly in
7673 its validity determination, i.e., the way it would after reload
7675 if (constrain_operands (1))
7679 delete_insns_since (last);
7681 /* If that failed, we must use a conservative two-insn sequence.
7682 use move to copy constant, MEM, or pseudo register to the reload
7683 register since "move" will be able to handle an arbitrary operand,
7684 unlike add which can't, in general. Then add the registers.
7686 If there is another way to do this for a specific machine, a
7687 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7690 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7691 || (GET_CODE (op1) == REG
7692 && REGNO (op1) >= FIRST_PSEUDO_REGISTER))
7693 tem = op0, op0 = op1, op1 = tem;
7695 gen_reload (out, op0, opnum, type);
7697 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7698 This fixes a problem on the 32K where the stack pointer cannot
7699 be used as an operand of an add insn. */
7701 if (rtx_equal_p (op0, op1))
7704 insn = emit_insn (gen_add2_insn (out, op1));
7706 /* If that failed, copy the address register to the reload register.
7707 Then add the constant to the reload register. */
7709 code = recog_memoized (insn);
7713 extract_insn (insn);
7714 /* We want constrain operands to treat this insn strictly in
7715 its validity determination, i.e., the way it would after reload
7717 if (constrain_operands (1))
7719 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7721 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7726 delete_insns_since (last);
7728 gen_reload (out, op1, opnum, type);
7729 insn = emit_insn (gen_add2_insn (out, op0));
7730 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7733 #ifdef SECONDARY_MEMORY_NEEDED
7734 /* If we need a memory location to do the move, do it that way. */
7735 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7736 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7737 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7738 REGNO_REG_CLASS (REGNO (out)),
7741 /* Get the memory to use and rewrite both registers to its mode. */
7742 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7744 if (GET_MODE (loc) != GET_MODE (out))
7745 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7747 if (GET_MODE (loc) != GET_MODE (in))
7748 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7750 gen_reload (loc, in, opnum, type);
7751 gen_reload (out, loc, opnum, type);
7755 /* If IN is a simple operand, use gen_move_insn. */
7756 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7757 emit_insn (gen_move_insn (out, in));
7759 #ifdef HAVE_reload_load_address
7760 else if (HAVE_reload_load_address)
7761 emit_insn (gen_reload_load_address (out, in));
7764 /* Otherwise, just write (set OUT IN) and hope for the best. */
7766 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7768 /* Return the first insn emitted.
7769 We can not just return get_last_insn, because there may have
7770 been multiple instructions emitted. Also note that gen_move_insn may
7771 emit more than one insn itself, so we can not assume that there is one
7772 insn emitted per emit_insn_before call. */
7774 return last ? NEXT_INSN (last) : get_insns ();
7777 /* Delete a previously made output-reload
7778 whose result we now believe is not needed.
7779 First we double-check.
7781 INSN is the insn now being processed.
7782 LAST_RELOAD_REG is the hard register number for which we want to delete
7783 the last output reload.
7784 J is the reload-number that originally used REG. The caller has made
7785 certain that reload J doesn't use REG any longer for input. */
7788 delete_output_reload (insn, j, last_reload_reg)
7791 int last_reload_reg;
7793 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7794 rtx reg = spill_reg_stored_to[last_reload_reg];
7797 int n_inherited = 0;
7801 /* Get the raw pseudo-register referred to. */
7803 while (GET_CODE (reg) == SUBREG)
7804 reg = SUBREG_REG (reg);
7805 substed = reg_equiv_memory_loc[REGNO (reg)];
7807 /* This is unsafe if the operand occurs more often in the current
7808 insn than it is inherited. */
7809 for (k = n_reloads - 1; k >= 0; k--)
7811 rtx reg2 = reload_in[k];
7814 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7815 reg2 = reload_in_reg[k];
7817 if (reload_out[k] && ! reload_out_reg[k])
7818 reg2 = XEXP (reload_in_reg[k], 0);
7820 while (GET_CODE (reg2) == SUBREG)
7821 reg2 = SUBREG_REG (reg2);
7822 if (rtx_equal_p (reg2, reg))
7824 if (reload_inherited[k] || reload_override_in[k] || k == j)
7827 reg2 = reload_out_reg[k];
7830 while (GET_CODE (reg2) == SUBREG)
7831 reg2 = XEXP (reg2, 0);
7832 if (rtx_equal_p (reg2, reg))
7839 n_occurrences = count_occurrences (PATTERN (insn), reg);
7841 n_occurrences += count_occurrences (PATTERN (insn), substed);
7842 if (n_occurrences > n_inherited)
7845 /* If the pseudo-reg we are reloading is no longer referenced
7846 anywhere between the store into it and here,
7847 and no jumps or labels intervene, then the value can get
7848 here through the reload reg alone.
7849 Otherwise, give up--return. */
7850 for (i1 = NEXT_INSN (output_reload_insn);
7851 i1 != insn; i1 = NEXT_INSN (i1))
7853 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7855 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7856 && reg_mentioned_p (reg, PATTERN (i1)))
7858 /* If this is USE in front of INSN, we only have to check that
7859 there are no more references than accounted for by inheritance. */
7860 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7862 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7863 i1 = NEXT_INSN (i1);
7865 if (n_occurrences <= n_inherited && i1 == insn)
7871 /* The caller has already checked that REG dies or is set in INSN.
7872 It has also checked that we are optimizing, and thus some inaccurancies
7873 in the debugging information are acceptable.
7874 So we could just delete output_reload_insn.
7875 But in some cases we can improve the debugging information without
7876 sacrificing optimization - maybe even improving the code:
7877 See if the pseudo reg has been completely replaced
7878 with reload regs. If so, delete the store insn
7879 and forget we had a stack slot for the pseudo. */
7880 if (reload_out[j] != reload_in[j]
7881 && REG_N_DEATHS (REGNO (reg)) == 1
7882 && REG_N_SETS (REGNO (reg)) == 1
7883 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7884 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7888 /* We know that it was used only between here
7889 and the beginning of the current basic block.
7890 (We also know that the last use before INSN was
7891 the output reload we are thinking of deleting, but never mind that.)
7892 Search that range; see if any ref remains. */
7893 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7895 rtx set = single_set (i2);
7897 /* Uses which just store in the pseudo don't count,
7898 since if they are the only uses, they are dead. */
7899 if (set != 0 && SET_DEST (set) == reg)
7901 if (GET_CODE (i2) == CODE_LABEL
7902 || GET_CODE (i2) == JUMP_INSN)
7904 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7905 && reg_mentioned_p (reg, PATTERN (i2)))
7907 /* Some other ref remains; just delete the output reload we
7909 delete_address_reloads (output_reload_insn, insn);
7910 PUT_CODE (output_reload_insn, NOTE);
7911 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7912 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7917 /* Delete the now-dead stores into this pseudo. */
7918 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7920 rtx set = single_set (i2);
7922 if (set != 0 && SET_DEST (set) == reg)
7924 delete_address_reloads (i2, insn);
7925 /* This might be a basic block head,
7926 thus don't use delete_insn. */
7927 PUT_CODE (i2, NOTE);
7928 NOTE_SOURCE_FILE (i2) = 0;
7929 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7931 if (GET_CODE (i2) == CODE_LABEL
7932 || GET_CODE (i2) == JUMP_INSN)
7936 /* For the debugging info,
7937 say the pseudo lives in this reload reg. */
7938 reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
7939 alter_reg (REGNO (reg), -1);
7941 delete_address_reloads (output_reload_insn, insn);
7942 PUT_CODE (output_reload_insn, NOTE);
7943 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7944 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7948 /* We are going to delete DEAD_INSN. Recursively delete loads of
7949 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7950 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7952 delete_address_reloads (dead_insn, current_insn)
7953 rtx dead_insn, current_insn;
7955 rtx set = single_set (dead_insn);
7956 rtx set2, dst, prev, next;
7959 rtx dst = SET_DEST (set);
7960 if (GET_CODE (dst) == MEM)
7961 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7963 /* If we deleted the store from a reloaded post_{in,de}c expression,
7964 we can delete the matching adds. */
7965 prev = PREV_INSN (dead_insn);
7966 next = NEXT_INSN (dead_insn);
7967 if (! prev || ! next)
7969 set = single_set (next);
7970 set2 = single_set (prev);
7972 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7973 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7974 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7976 dst = SET_DEST (set);
7977 if (! rtx_equal_p (dst, SET_DEST (set2))
7978 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7979 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7980 || (INTVAL (XEXP (SET_SRC (set), 1))
7981 != - INTVAL (XEXP (SET_SRC (set2), 1))))
7987 /* Subfunction of delete_address_reloads: process registers found in X. */
7989 delete_address_reloads_1 (dead_insn, x, current_insn)
7990 rtx dead_insn, x, current_insn;
7992 rtx prev, set, dst, i2;
7994 enum rtx_code code = GET_CODE (x);
7998 char *fmt= GET_RTX_FORMAT (code);
7999 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8002 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8003 else if (fmt[i] == 'E')
8005 for (j = XVECLEN (x, i) - 1; j >=0; j--)
8006 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8013 if (spill_reg_order[REGNO (x)] < 0)
8016 /* Scan backwards for the insn that sets x. This might be a way back due
8018 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8020 code = GET_CODE (prev);
8021 if (code == CODE_LABEL || code == JUMP_INSN)
8023 if (GET_RTX_CLASS (code) != 'i')
8025 if (reg_set_p (x, PATTERN (prev)))
8027 if (reg_referenced_p (x, PATTERN (prev)))
8030 if (! prev || INSN_UID (prev) < reload_first_uid)
8032 /* Check that PREV only sets the reload register. */
8033 set = single_set (prev);
8036 dst = SET_DEST (set);
8037 if (GET_CODE (dst) != REG
8038 || ! rtx_equal_p (dst, x))
8040 if (! reg_set_p (dst, PATTERN (dead_insn)))
8042 /* Check if DST was used in a later insn -
8043 it might have been inherited. */
8044 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8046 if (GET_CODE (i2) == CODE_LABEL)
8048 if (GET_RTX_CLASS (GET_CODE (i2)) != 'i')
8050 if (reg_referenced_p (dst, PATTERN (i2)))
8052 /* If there is a reference to the register in the current insn,
8053 it might be loaded in a non-inherited reload. If no other
8054 reload uses it, that means the register is set before
8056 if (i2 == current_insn)
8058 for (j = n_reloads - 1; j >= 0; j--)
8059 if ((reload_reg_rtx[j] == dst && reload_inherited[j])
8060 || reload_override_in[j] == dst)
8062 for (j = n_reloads - 1; j >= 0; j--)
8063 if (reload_in[j] && reload_reg_rtx[j] == dst)
8070 if (GET_CODE (i2) == JUMP_INSN)
8072 if (reg_set_p (dst, PATTERN (i2)))
8074 /* If DST is still live at CURRENT_INSN, check if it is used for
8076 if (i2 == current_insn)
8078 for (j = n_reloads - 1; j >= 0; j--)
8079 if ((reload_reg_rtx[j] == dst && reload_inherited[j])
8080 || reload_override_in[j] == dst)
8082 /* ??? We can't finish the loop here, because dst might be
8083 allocated to a pseudo in this block if no reload in this
8084 block needs any of the clsses containing DST - see
8085 spill_hard_reg. There is no easy way to tell this, so we
8086 have to scan till the end of the basic block. */
8090 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8091 reg_reloaded_contents[REGNO (dst)] = -1;
8092 /* Can't use delete_insn here because PREV might be a basic block head. */
8093 PUT_CODE (prev, NOTE);
8094 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
8095 NOTE_SOURCE_FILE (prev) = 0;
8098 /* Output reload-insns to reload VALUE into RELOADREG.
8099 VALUE is an autoincrement or autodecrement RTX whose operand
8100 is a register or memory location;
8101 so reloading involves incrementing that location.
8102 IN is either identical to VALUE, or some cheaper place to reload from.
8104 INC_AMOUNT is the number to increment or decrement by (always positive).
8105 This cannot be deduced from VALUE.
8107 Return the instruction that stores into RELOADREG. */
8110 inc_for_reload (reloadreg, in, value, inc_amount)
8115 /* REG or MEM to be copied and incremented. */
8116 rtx incloc = XEXP (value, 0);
8117 /* Nonzero if increment after copying. */
8118 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
8124 rtx real_in = in == value ? XEXP (in, 0) : in;
8126 /* No hard register is equivalent to this register after
8127 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
8128 we could inc/dec that register as well (maybe even using it for
8129 the source), but I'm not sure it's worth worrying about. */
8130 if (GET_CODE (incloc) == REG)
8131 reg_last_reload_reg[REGNO (incloc)] = 0;
8133 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8134 inc_amount = - inc_amount;
8136 inc = GEN_INT (inc_amount);
8138 /* If this is post-increment, first copy the location to the reload reg. */
8139 if (post && real_in != reloadreg)
8140 emit_insn (gen_move_insn (reloadreg, real_in));
8144 /* See if we can directly increment INCLOC. Use a method similar to
8145 that in gen_reload. */
8147 last = get_last_insn ();
8148 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8149 gen_rtx_PLUS (GET_MODE (incloc),
8152 code = recog_memoized (add_insn);
8155 extract_insn (add_insn);
8156 if (constrain_operands (1))
8158 /* If this is a pre-increment and we have incremented the value
8159 where it lives, copy the incremented value to RELOADREG to
8160 be used as an address. */
8163 emit_insn (gen_move_insn (reloadreg, incloc));
8168 delete_insns_since (last);
8171 /* If couldn't do the increment directly, must increment in RELOADREG.
8172 The way we do this depends on whether this is pre- or post-increment.
8173 For pre-increment, copy INCLOC to the reload register, increment it
8174 there, then save back. */
8178 if (in != reloadreg)
8179 emit_insn (gen_move_insn (reloadreg, real_in));
8180 emit_insn (gen_add2_insn (reloadreg, inc));
8181 store = emit_insn (gen_move_insn (incloc, reloadreg));
8186 Because this might be a jump insn or a compare, and because RELOADREG
8187 may not be available after the insn in an input reload, we must do
8188 the incrementation before the insn being reloaded for.
8190 We have already copied IN to RELOADREG. Increment the copy in
8191 RELOADREG, save that back, then decrement RELOADREG so it has
8192 the original value. */
8194 emit_insn (gen_add2_insn (reloadreg, inc));
8195 store = emit_insn (gen_move_insn (incloc, reloadreg));
8196 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8202 /* Return 1 if we are certain that the constraint-string STRING allows
8203 the hard register REG. Return 0 if we can't be sure of this. */
8206 constraint_accepts_reg_p (string, reg)
8211 int regno = true_regnum (reg);
8214 /* Initialize for first alternative. */
8216 /* Check that each alternative contains `g' or `r'. */
8218 switch (c = *string++)
8221 /* If an alternative lacks `g' or `r', we lose. */
8224 /* If an alternative lacks `g' or `r', we lose. */
8227 /* Initialize for next alternative. */
8232 /* Any general reg wins for this alternative. */
8233 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
8237 /* Any reg in specified class wins for this alternative. */
8239 enum reg_class class = REG_CLASS_FROM_LETTER (c);
8241 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
8247 /* Return the number of places FIND appears within X, but don't count
8248 an occurrence if some SET_DEST is FIND. */
8251 count_occurrences (x, find)
8252 register rtx x, find;
8255 register enum rtx_code code;
8256 register char *format_ptr;
8264 code = GET_CODE (x);
8279 if (GET_CODE (find) == MEM && rtx_equal_p (x, find))
8283 if (SET_DEST (x) == find)
8284 return count_occurrences (SET_SRC (x), find);
8291 format_ptr = GET_RTX_FORMAT (code);
8294 for (i = 0; i < GET_RTX_LENGTH (code); i++)
8296 switch (*format_ptr++)
8299 count += count_occurrences (XEXP (x, i), find);
8303 if (XVEC (x, i) != NULL)
8305 for (j = 0; j < XVECLEN (x, i); j++)
8306 count += count_occurrences (XVECEXP (x, i, j), find);
8314 /* This array holds values which are equivalent to a hard register
8315 during reload_cse_regs. Each array element is an EXPR_LIST of
8316 values. Each time a hard register is set, we set the corresponding
8317 array element to the value. Each time a hard register is copied
8318 into memory, we add the memory location to the corresponding array
8319 element. We don't store values or memory addresses with side
8320 effects in this array.
8322 If the value is a CONST_INT, then the mode of the containing
8323 EXPR_LIST is the mode in which that CONST_INT was referenced.
8325 We sometimes clobber a specific entry in a list. In that case, we
8326 just set XEXP (list-entry, 0) to 0. */
8328 static rtx *reg_values;
8330 /* This is a preallocated REG rtx which we use as a temporary in
8331 reload_cse_invalidate_regno, so that we don't need to allocate a
8332 new one each time through a loop in that function. */
8334 static rtx invalidate_regno_rtx;
8336 /* Invalidate any entries in reg_values which depend on REGNO,
8337 including those for REGNO itself. This is called if REGNO is
8338 changing. If CLOBBER is true, then always forget anything we
8339 currently know about REGNO. MODE is the mode of the assignment to
8340 REGNO, which is used to determine how many hard registers are being
8341 changed. If MODE is VOIDmode, then only REGNO is being changed;
8342 this is used when invalidating call clobbered registers across a
8346 reload_cse_invalidate_regno (regno, mode, clobber)
8348 enum machine_mode mode;
8354 /* Our callers don't always go through true_regnum; we may see a
8355 pseudo-register here from a CLOBBER or the like. We probably
8356 won't ever see a pseudo-register that has a real register number,
8357 for we check anyhow for safety. */
8358 if (regno >= FIRST_PSEUDO_REGISTER)
8359 regno = reg_renumber[regno];
8363 if (mode == VOIDmode)
8364 endregno = regno + 1;
8366 endregno = regno + HARD_REGNO_NREGS (regno, mode);
8369 for (i = regno; i < endregno; i++)
8372 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8376 for (x = reg_values[i]; x; x = XEXP (x, 1))
8378 if (XEXP (x, 0) != 0
8379 && refers_to_regno_p (regno, endregno, XEXP (x, 0), NULL_PTR))
8381 /* If this is the only entry on the list, clear
8382 reg_values[i]. Otherwise, just clear this entry on
8384 if (XEXP (x, 1) == 0 && x == reg_values[i])
8394 /* We must look at earlier registers, in case REGNO is part of a
8395 multi word value but is not the first register. If an earlier
8396 register has a value in a mode which overlaps REGNO, then we must
8397 invalidate that earlier register. Note that we do not need to
8398 check REGNO or later registers (we must not check REGNO itself,
8399 because we would incorrectly conclude that there was a conflict). */
8401 for (i = 0; i < regno; i++)
8405 for (x = reg_values[i]; x; x = XEXP (x, 1))
8407 if (XEXP (x, 0) != 0)
8409 PUT_MODE (invalidate_regno_rtx, GET_MODE (x));
8410 REGNO (invalidate_regno_rtx) = i;
8411 if (refers_to_regno_p (regno, endregno, invalidate_regno_rtx,
8414 reload_cse_invalidate_regno (i, VOIDmode, 1);
8422 /* The memory at address MEM_BASE is being changed.
8423 Return whether this change will invalidate VAL. */
8426 reload_cse_mem_conflict_p (mem_base, val)
8434 code = GET_CODE (val);
8437 /* Get rid of a few simple cases quickly. */
8450 if (GET_MODE (mem_base) == BLKmode
8451 || GET_MODE (val) == BLKmode)
8453 if (anti_dependence (val, mem_base))
8455 /* The address may contain nested MEMs. */
8462 fmt = GET_RTX_FORMAT (code);
8464 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8468 if (reload_cse_mem_conflict_p (mem_base, XEXP (val, i)))
8471 else if (fmt[i] == 'E')
8475 for (j = 0; j < XVECLEN (val, i); j++)
8476 if (reload_cse_mem_conflict_p (mem_base, XVECEXP (val, i, j)))
8484 /* Invalidate any entries in reg_values which are changed because of a
8485 store to MEM_RTX. If this is called because of a non-const call
8486 instruction, MEM_RTX is (mem:BLK const0_rtx). */
8489 reload_cse_invalidate_mem (mem_rtx)
8494 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8498 for (x = reg_values[i]; x; x = XEXP (x, 1))
8500 if (XEXP (x, 0) != 0
8501 && reload_cse_mem_conflict_p (mem_rtx, XEXP (x, 0)))
8503 /* If this is the only entry on the list, clear
8504 reg_values[i]. Otherwise, just clear this entry on
8506 if (XEXP (x, 1) == 0 && x == reg_values[i])
8517 /* Invalidate DEST, which is being assigned to or clobbered. The
8518 second parameter exists so that this function can be passed to
8519 note_stores; it is ignored. */
8522 reload_cse_invalidate_rtx (dest, ignore)
8524 rtx ignore ATTRIBUTE_UNUSED;
8526 while (GET_CODE (dest) == STRICT_LOW_PART
8527 || GET_CODE (dest) == SIGN_EXTRACT
8528 || GET_CODE (dest) == ZERO_EXTRACT
8529 || GET_CODE (dest) == SUBREG)
8530 dest = XEXP (dest, 0);
8532 if (GET_CODE (dest) == REG)
8533 reload_cse_invalidate_regno (REGNO (dest), GET_MODE (dest), 1);
8534 else if (GET_CODE (dest) == MEM)
8535 reload_cse_invalidate_mem (dest);
8538 /* Do a very simple CSE pass over the hard registers.
8540 This function detects no-op moves where we happened to assign two
8541 different pseudo-registers to the same hard register, and then
8542 copied one to the other. Reload will generate a useless
8543 instruction copying a register to itself.
8545 This function also detects cases where we load a value from memory
8546 into two different registers, and (if memory is more expensive than
8547 registers) changes it to simply copy the first register into the
8550 Another optimization is performed that scans the operands of each
8551 instruction to see whether the value is already available in a
8552 hard register. It then replaces the operand with the hard register
8553 if possible, much like an optional reload would. */
8556 reload_cse_regs_1 (first)
8564 init_alias_analysis ();
8566 reg_values = (rtx *) alloca (FIRST_PSEUDO_REGISTER * sizeof (rtx));
8567 bzero ((char *)reg_values, FIRST_PSEUDO_REGISTER * sizeof (rtx));
8569 /* Create our EXPR_LIST structures on reload_obstack, so that we can
8570 free them when we are done. */
8571 push_obstacks (&reload_obstack, &reload_obstack);
8572 firstobj = (char *) obstack_alloc (&reload_obstack, 0);
8574 /* We pass this to reload_cse_invalidate_mem to invalidate all of
8575 memory for a non-const call instruction. */
8576 callmem = gen_rtx_MEM (BLKmode, const0_rtx);
8578 /* This is used in reload_cse_invalidate_regno to avoid consing a
8579 new REG in a loop in that function. */
8580 invalidate_regno_rtx = gen_rtx_REG (VOIDmode, 0);
8582 for (insn = first; insn; insn = NEXT_INSN (insn))
8586 if (GET_CODE (insn) == CODE_LABEL)
8588 /* Forget all the register values at a code label. We don't
8589 try to do anything clever around jumps. */
8590 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8596 #ifdef NON_SAVING_SETJMP
8597 if (NON_SAVING_SETJMP && GET_CODE (insn) == NOTE
8598 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
8600 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8607 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8610 /* If this is a call instruction, forget anything stored in a
8611 call clobbered register, or, if this is not a const call, in
8613 if (GET_CODE (insn) == CALL_INSN)
8615 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8616 if (call_used_regs[i])
8617 reload_cse_invalidate_regno (i, VOIDmode, 1);
8619 if (! CONST_CALL_P (insn))
8620 reload_cse_invalidate_mem (callmem);
8623 body = PATTERN (insn);
8624 if (GET_CODE (body) == SET)
8627 if (reload_cse_noop_set_p (body, insn))
8629 /* If this sets the return value of the function, we must keep
8630 a USE around, in case this is in a different basic block
8631 than the final USE. Otherwise, we could loose important
8632 register lifeness information on SMALL_REGISTER_CLASSES
8633 machines, where return registers might be used as spills:
8634 subsequent passes assume that spill registers are dead at
8635 the end of a basic block. */
8636 if (REG_FUNCTION_VALUE_P (SET_DEST (body)))
8639 PATTERN (insn) = gen_rtx_USE (VOIDmode, SET_DEST (body));
8640 INSN_CODE (insn) = -1;
8641 REG_NOTES (insn) = NULL_RTX;
8642 push_obstacks (&reload_obstack, &reload_obstack);
8646 PUT_CODE (insn, NOTE);
8647 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8648 NOTE_SOURCE_FILE (insn) = 0;
8651 /* We're done with this insn. */
8655 /* It's not a no-op, but we can try to simplify it. */
8656 count += reload_cse_simplify_set (body, insn);
8659 apply_change_group ();
8661 reload_cse_simplify_operands (insn);
8663 reload_cse_record_set (body, body);
8665 else if (GET_CODE (body) == PARALLEL)
8668 rtx value = NULL_RTX;
8670 /* If every action in a PARALLEL is a noop, we can delete
8671 the entire PARALLEL. */
8672 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8674 rtx part = XVECEXP (body, 0, i);
8675 if (GET_CODE (part) == SET)
8677 if (! reload_cse_noop_set_p (part, insn))
8679 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8683 value = SET_DEST (part);
8686 else if (GET_CODE (part) != CLOBBER)
8694 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
8695 INSN_CODE (insn) = -1;
8696 REG_NOTES (insn) = NULL_RTX;
8697 push_obstacks (&reload_obstack, &reload_obstack);
8701 PUT_CODE (insn, NOTE);
8702 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8703 NOTE_SOURCE_FILE (insn) = 0;
8706 /* We're done with this insn. */
8710 /* It's not a no-op, but we can try to simplify it. */
8711 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8712 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8713 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8716 apply_change_group ();
8718 reload_cse_simplify_operands (insn);
8720 /* Look through the PARALLEL and record the values being
8721 set, if possible. Also handle any CLOBBERs. */
8722 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8724 rtx x = XVECEXP (body, 0, i);
8726 if (GET_CODE (x) == SET)
8727 reload_cse_record_set (x, body);
8729 note_stores (x, reload_cse_invalidate_rtx);
8733 note_stores (body, reload_cse_invalidate_rtx);
8736 /* Clobber any registers which appear in REG_INC notes. We
8737 could keep track of the changes to their values, but it is
8738 unlikely to help. */
8742 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
8743 if (REG_NOTE_KIND (x) == REG_INC)
8744 reload_cse_invalidate_rtx (XEXP (x, 0), NULL_RTX);
8748 /* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only
8749 after we have processed the insn. */
8750 if (GET_CODE (insn) == CALL_INSN)
8754 for (x = CALL_INSN_FUNCTION_USAGE (insn); x; x = XEXP (x, 1))
8755 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
8756 reload_cse_invalidate_rtx (XEXP (XEXP (x, 0), 0), NULL_RTX);
8760 /* Free all the temporary structures we created, and go back to the
8761 regular obstacks. */
8762 obstack_free (&reload_obstack, firstobj);
8766 /* Call cse / combine like post-reload optimization phases.
8767 FIRST is the first instruction. */
8769 reload_cse_regs (first)
8772 reload_cse_regs_1 (first);
8774 reload_cse_move2add (first);
8775 if (flag_expensive_optimizations)
8776 reload_cse_regs_1 (first);
8779 /* Return whether the values known for REGNO are equal to VAL. MODE
8780 is the mode of the object that VAL is being copied to; this matters
8781 if VAL is a CONST_INT. */
8784 reload_cse_regno_equal_p (regno, val, mode)
8787 enum machine_mode mode;
8794 for (x = reg_values[regno]; x; x = XEXP (x, 1))
8795 if (XEXP (x, 0) != 0
8796 && rtx_equal_p (XEXP (x, 0), val)
8797 && (! flag_float_store || GET_CODE (XEXP (x, 0)) != MEM
8798 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
8799 && (GET_CODE (val) != CONST_INT
8800 || mode == GET_MODE (x)
8801 || (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8802 /* On a big endian machine if the value spans more than
8803 one register then this register holds the high part of
8804 it and we can't use it.
8806 ??? We should also compare with the high part of the
8808 && !(WORDS_BIG_ENDIAN
8809 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
8810 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
8811 GET_MODE_BITSIZE (GET_MODE (x))))))
8817 /* See whether a single set is a noop. SET is the set instruction we
8818 are should check, and INSN is the instruction from which it came. */
8821 reload_cse_noop_set_p (set, insn)
8826 enum machine_mode dest_mode;
8830 src = SET_SRC (set);
8831 dest = SET_DEST (set);
8832 dest_mode = GET_MODE (dest);
8834 if (side_effects_p (src))
8837 dreg = true_regnum (dest);
8838 sreg = true_regnum (src);
8840 /* Check for setting a register to itself. In this case, we don't
8841 have to worry about REG_DEAD notes. */
8842 if (dreg >= 0 && dreg == sreg)
8848 /* Check for setting a register to itself. */
8852 /* Check for setting a register to a value which we already know
8853 is in the register. */
8854 else if (reload_cse_regno_equal_p (dreg, src, dest_mode))
8857 /* Check for setting a register DREG to another register SREG
8858 where SREG is equal to a value which is already in DREG. */
8863 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
8867 if (XEXP (x, 0) == 0)
8870 if (dest_mode == GET_MODE (x))
8872 else if (GET_MODE_BITSIZE (dest_mode)
8873 < GET_MODE_BITSIZE (GET_MODE (x)))
8874 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
8879 && reload_cse_regno_equal_p (dreg, tmp, dest_mode))
8887 else if (GET_CODE (dest) == MEM)
8889 /* Check for storing a register to memory when we know that the
8890 register is equivalent to the memory location. */
8892 && reload_cse_regno_equal_p (sreg, dest, dest_mode)
8893 && ! side_effects_p (dest))
8900 /* Try to simplify a single SET instruction. SET is the set pattern.
8901 INSN is the instruction it came from.
8902 This function only handles one case: if we set a register to a value
8903 which is not a register, we try to find that value in some other register
8904 and change the set into a register copy. */
8907 reload_cse_simplify_set (set, insn)
8913 enum machine_mode dest_mode;
8914 enum reg_class dclass;
8917 dreg = true_regnum (SET_DEST (set));
8921 src = SET_SRC (set);
8922 if (side_effects_p (src) || true_regnum (src) >= 0)
8925 dclass = REGNO_REG_CLASS (dreg);
8927 /* If memory loads are cheaper than register copies, don't change them. */
8928 if (GET_CODE (src) == MEM
8929 && MEMORY_MOVE_COST (GET_MODE (src), dclass, 1) < 2)
8932 /* If the constant is cheaper than a register, don't change it. */
8933 if (CONSTANT_P (src)
8934 && rtx_cost (src, SET) < 2)
8937 dest_mode = GET_MODE (SET_DEST (set));
8938 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8941 && REGISTER_MOVE_COST (REGNO_REG_CLASS (i), dclass) == 2
8942 && reload_cse_regno_equal_p (i, src, dest_mode))
8946 /* Pop back to the real obstacks while changing the insn. */
8949 validated = validate_change (insn, &SET_SRC (set),
8950 gen_rtx_REG (dest_mode, i), 1);
8952 /* Go back to the obstack we are using for temporary
8954 push_obstacks (&reload_obstack, &reload_obstack);
8963 /* Try to replace operands in INSN with equivalent values that are already
8964 in registers. This can be viewed as optional reloading.
8966 For each non-register operand in the insn, see if any hard regs are
8967 known to be equivalent to that operand. Record the alternatives which
8968 can accept these hard registers. Among all alternatives, select the
8969 ones which are better or equal to the one currently matching, where
8970 "better" is in terms of '?' and '!' constraints. Among the remaining
8971 alternatives, select the one which replaces most operands with
8975 reload_cse_simplify_operands (insn)
8978 #ifdef REGISTER_CONSTRAINTS
8981 char *constraints[MAX_RECOG_OPERANDS];
8983 /* Vector recording how bad an alternative is. */
8984 int *alternative_reject;
8985 /* Vector recording how many registers can be introduced by choosing
8986 this alternative. */
8987 int *alternative_nregs;
8988 /* Array of vectors recording, for each operand and each alternative,
8989 which hard register to substitute, or -1 if the operand should be
8991 int *op_alt_regno[MAX_RECOG_OPERANDS];
8992 /* Array of alternatives, sorted in order of decreasing desirability. */
8993 int *alternative_order;
8994 rtx reg = gen_rtx_REG (VOIDmode, -1);
8996 extract_insn (insn);
8998 if (recog_n_alternatives == 0 || recog_n_operands == 0)
9001 /* Figure out which alternative currently matches. */
9002 if (! constrain_operands (1))
9003 fatal_insn_not_found (insn);
9005 alternative_reject = (int *) alloca (recog_n_alternatives * sizeof (int));
9006 alternative_nregs = (int *) alloca (recog_n_alternatives * sizeof (int));
9007 alternative_order = (int *) alloca (recog_n_alternatives * sizeof (int));
9008 bzero ((char *)alternative_reject, recog_n_alternatives * sizeof (int));
9009 bzero ((char *)alternative_nregs, recog_n_alternatives * sizeof (int));
9011 for (i = 0; i < recog_n_operands; i++)
9013 enum machine_mode mode;
9017 op_alt_regno[i] = (int *) alloca (recog_n_alternatives * sizeof (int));
9018 for (j = 0; j < recog_n_alternatives; j++)
9019 op_alt_regno[i][j] = -1;
9021 p = constraints[i] = recog_constraints[i];
9022 mode = recog_operand_mode[i];
9024 /* Add the reject values for each alternative given by the constraints
9025 for this operand. */
9033 alternative_reject[j] += 3;
9035 alternative_reject[j] += 300;
9038 /* We won't change operands which are already registers. We
9039 also don't want to modify output operands. */
9040 regno = true_regnum (recog_operand[i]);
9042 || constraints[i][0] == '='
9043 || constraints[i][0] == '+')
9046 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
9048 int class = (int) NO_REGS;
9050 if (! reload_cse_regno_equal_p (regno, recog_operand[i], mode))
9053 REGNO (reg) = regno;
9054 PUT_MODE (reg, mode);
9056 /* We found a register equal to this operand. Now look for all
9057 alternatives that can accept this register and have not been
9058 assigned a register they can use yet. */
9067 case '=': case '+': case '?':
9068 case '#': case '&': case '!':
9070 case '0': case '1': case '2': case '3': case '4':
9071 case 'm': case '<': case '>': case 'V': case 'o':
9072 case 'E': case 'F': case 'G': case 'H':
9073 case 's': case 'i': case 'n':
9074 case 'I': case 'J': case 'K': case 'L':
9075 case 'M': case 'N': case 'O': case 'P':
9076 #ifdef EXTRA_CONSTRAINT
9077 case 'Q': case 'R': case 'S': case 'T': case 'U':
9080 /* These don't say anything we care about. */
9084 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
9089 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
9092 case ',': case '\0':
9093 /* See if REGNO fits this alternative, and set it up as the
9094 replacement register if we don't have one for this
9095 alternative yet and the operand being replaced is not
9096 a cheap CONST_INT. */
9097 if (op_alt_regno[i][j] == -1
9098 && reg_fits_class_p (reg, class, 0, mode)
9099 && (GET_CODE (recog_operand[i]) != CONST_INT
9100 || rtx_cost (recog_operand[i], SET) > rtx_cost (reg, SET)))
9102 alternative_nregs[j]++;
9103 op_alt_regno[i][j] = regno;
9115 /* Record all alternatives which are better or equal to the currently
9116 matching one in the alternative_order array. */
9117 for (i = j = 0; i < recog_n_alternatives; i++)
9118 if (alternative_reject[i] <= alternative_reject[which_alternative])
9119 alternative_order[j++] = i;
9120 recog_n_alternatives = j;
9122 /* Sort it. Given a small number of alternatives, a dumb algorithm
9123 won't hurt too much. */
9124 for (i = 0; i < recog_n_alternatives - 1; i++)
9127 int best_reject = alternative_reject[alternative_order[i]];
9128 int best_nregs = alternative_nregs[alternative_order[i]];
9131 for (j = i + 1; j < recog_n_alternatives; j++)
9133 int this_reject = alternative_reject[alternative_order[j]];
9134 int this_nregs = alternative_nregs[alternative_order[j]];
9136 if (this_reject < best_reject
9137 || (this_reject == best_reject && this_nregs < best_nregs))
9140 best_reject = this_reject;
9141 best_nregs = this_nregs;
9145 tmp = alternative_order[best];
9146 alternative_order[best] = alternative_order[i];
9147 alternative_order[i] = tmp;
9150 /* Substitute the operands as determined by op_alt_regno for the best
9152 j = alternative_order[0];
9154 /* Pop back to the real obstacks while changing the insn. */
9157 for (i = 0; i < recog_n_operands; i++)
9159 enum machine_mode mode = recog_operand_mode[i];
9160 if (op_alt_regno[i][j] == -1)
9163 validate_change (insn, recog_operand_loc[i],
9164 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
9167 for (i = recog_n_dups - 1; i >= 0; i--)
9169 int op = recog_dup_num[i];
9170 enum machine_mode mode = recog_operand_mode[op];
9172 if (op_alt_regno[op][j] == -1)
9175 validate_change (insn, recog_dup_loc[i],
9176 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
9179 /* Go back to the obstack we are using for temporary
9181 push_obstacks (&reload_obstack, &reload_obstack);
9183 return apply_change_group ();
9189 /* These two variables are used to pass information from
9190 reload_cse_record_set to reload_cse_check_clobber. */
9192 static int reload_cse_check_clobbered;
9193 static rtx reload_cse_check_src;
9195 /* See if DEST overlaps with RELOAD_CSE_CHECK_SRC. If it does, set
9196 RELOAD_CSE_CHECK_CLOBBERED. This is called via note_stores. The
9197 second argument, which is passed by note_stores, is ignored. */
9200 reload_cse_check_clobber (dest, ignore)
9202 rtx ignore ATTRIBUTE_UNUSED;
9204 if (reg_overlap_mentioned_p (dest, reload_cse_check_src))
9205 reload_cse_check_clobbered = 1;
9208 /* Record the result of a SET instruction. SET is the set pattern.
9209 BODY is the pattern of the insn that it came from. */
9212 reload_cse_record_set (set, body)
9218 enum machine_mode dest_mode;
9220 dest = SET_DEST (set);
9221 src = SET_SRC (set);
9222 dreg = true_regnum (dest);
9223 sreg = true_regnum (src);
9224 dest_mode = GET_MODE (dest);
9226 /* Some machines don't define AUTO_INC_DEC, but they still use push
9227 instructions. We need to catch that case here in order to
9228 invalidate the stack pointer correctly. Note that invalidating
9229 the stack pointer is different from invalidating DEST. */
9231 while (GET_CODE (x) == SUBREG
9232 || GET_CODE (x) == ZERO_EXTRACT
9233 || GET_CODE (x) == SIGN_EXTRACT
9234 || GET_CODE (x) == STRICT_LOW_PART)
9236 if (push_operand (x, GET_MODE (x)))
9238 reload_cse_invalidate_rtx (stack_pointer_rtx, NULL_RTX);
9239 reload_cse_invalidate_rtx (dest, NULL_RTX);
9243 /* We can only handle an assignment to a register, or a store of a
9244 register to a memory location. For other cases, we just clobber
9245 the destination. We also have to just clobber if there are side
9246 effects in SRC or DEST. */
9247 if ((dreg < 0 && GET_CODE (dest) != MEM)
9248 || side_effects_p (src)
9249 || side_effects_p (dest))
9251 reload_cse_invalidate_rtx (dest, NULL_RTX);
9256 /* We don't try to handle values involving CC, because it's a pain
9257 to keep track of when they have to be invalidated. */
9258 if (reg_mentioned_p (cc0_rtx, src)
9259 || reg_mentioned_p (cc0_rtx, dest))
9261 reload_cse_invalidate_rtx (dest, NULL_RTX);
9266 /* If BODY is a PARALLEL, then we need to see whether the source of
9267 SET is clobbered by some other instruction in the PARALLEL. */
9268 if (GET_CODE (body) == PARALLEL)
9272 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
9276 x = XVECEXP (body, 0, i);
9280 reload_cse_check_clobbered = 0;
9281 reload_cse_check_src = src;
9282 note_stores (x, reload_cse_check_clobber);
9283 if (reload_cse_check_clobbered)
9285 reload_cse_invalidate_rtx (dest, NULL_RTX);
9295 /* This is an assignment to a register. Update the value we
9296 have stored for the register. */
9301 /* This is a copy from one register to another. Any values
9302 which were valid for SREG are now valid for DREG. If the
9303 mode changes, we use gen_lowpart_common to extract only
9304 the part of the value that is copied. */
9305 reg_values[dreg] = 0;
9306 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
9310 if (XEXP (x, 0) == 0)
9312 if (dest_mode == GET_MODE (XEXP (x, 0)))
9314 else if (GET_MODE_BITSIZE (dest_mode)
9315 > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
9318 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
9320 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, tmp,
9325 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, src, NULL_RTX);
9327 /* We've changed DREG, so invalidate any values held by other
9328 registers that depend upon it. */
9329 reload_cse_invalidate_regno (dreg, dest_mode, 0);
9331 /* If this assignment changes more than one hard register,
9332 forget anything we know about the others. */
9333 for (i = 1; i < HARD_REGNO_NREGS (dreg, dest_mode); i++)
9334 reg_values[dreg + i] = 0;
9336 else if (GET_CODE (dest) == MEM)
9338 /* Invalidate conflicting memory locations. */
9339 reload_cse_invalidate_mem (dest);
9341 /* If we're storing a register to memory, add DEST to the list
9343 if (sreg >= 0 && ! side_effects_p (dest))
9344 reg_values[sreg] = gen_rtx_EXPR_LIST (dest_mode, dest,
9349 /* We should have bailed out earlier. */
9354 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
9356 This code might also be useful when reload gave up on reg+reg addresssing
9357 because of clashes between the return register and INDEX_REG_CLASS. */
9359 /* The maximum number of uses of a register we can keep track of to
9360 replace them with reg+reg addressing. */
9361 #define RELOAD_COMBINE_MAX_USES 6
9363 /* INSN is the insn where a register has ben used, and USEP points to the
9364 location of the register within the rtl. */
9365 struct reg_use { rtx insn, *usep; };
9367 /* If the register is used in some unknown fashion, USE_INDEX is negative.
9368 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
9369 indicates where it becomes live again.
9370 Otherwise, USE_INDEX is the index of the last encountered use of the
9371 register (which is first among these we have seen since we scan backwards),
9372 OFFSET contains the constant offset that is added to the register in
9373 all encountered uses, and USE_RUID indicates the first encountered, i.e.
9374 last, of these uses.
9375 STORE_RUID is always meaningful if we only want to use a value in a
9376 register in a different place: it denotes the next insn in the insn
9377 stream (i.e. the last ecountered) that sets or clobbers the register. */
9380 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
9385 } reg_state[FIRST_PSEUDO_REGISTER];
9387 /* Reverse linear uid. This is increased in reload_combine while scanning
9388 the instructions from last to first. It is used to set last_label_ruid
9389 and the store_ruid / use_ruid fields in reg_state. */
9390 static int reload_combine_ruid;
9392 #define LABEL_LIVE(LABEL) \
9393 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
9399 int first_index_reg = 1, last_index_reg = 0;
9401 int last_label_ruid;
9402 int min_labelno, n_labels;
9403 HARD_REG_SET ever_live_at_start, *label_live;
9405 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
9406 reload has already used it where appropriate, so there is no use in
9407 trying to generate it now. */
9408 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
9411 /* To avoid wasting too much time later searching for an index register,
9412 determine the minimum and maximum index register numbers. */
9413 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9415 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i))
9417 if (! last_index_reg)
9419 first_index_reg = i;
9422 /* If no index register is available, we can quit now. */
9423 if (first_index_reg > last_index_reg)
9426 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
9427 information is a bit fuzzy immediately after reload, but it's
9428 still good enough to determine which registers are live at a jump
9430 min_labelno = get_first_label_num ();
9431 n_labels = max_label_num () - min_labelno;
9432 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
9433 CLEAR_HARD_REG_SET (ever_live_at_start);
9434 for (i = n_basic_blocks - 1; i >= 0; i--)
9436 insn = basic_block_head[i];
9437 if (GET_CODE (insn) == CODE_LABEL)
9441 REG_SET_TO_HARD_REG_SET (live, basic_block_live_at_start[i]);
9442 compute_use_by_pseudos (&live, basic_block_live_at_start[i]);
9443 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
9444 IOR_HARD_REG_SET (ever_live_at_start, live);
9448 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
9449 last_label_ruid = reload_combine_ruid = 0;
9450 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9452 reg_state[i].store_ruid = reload_combine_ruid;
9454 reg_state[i].use_index = -1;
9456 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9459 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
9463 /* We cannot do our optimization across labels. Invalidating all the use
9464 information we have would be costly, so we just note where the label
9465 is and then later disable any optimization that would cross it. */
9466 if (GET_CODE (insn) == CODE_LABEL)
9467 last_label_ruid = reload_combine_ruid;
9468 if (GET_CODE (insn) == BARRIER)
9470 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9471 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9473 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
9475 reload_combine_ruid++;
9477 /* Look for (set (REGX) (CONST_INT))
9478 (set (REGX) (PLUS (REGX) (REGY)))
9480 ... (MEM (REGX)) ...
9482 (set (REGZ) (CONST_INT))
9484 ... (MEM (PLUS (REGZ) (REGY)))... .
9486 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
9487 and that we know all uses of REGX before it dies. */
9488 set = single_set (insn);
9490 && GET_CODE (SET_DEST (set)) == REG
9491 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
9492 GET_MODE (SET_DEST (set)))
9494 && GET_CODE (SET_SRC (set)) == PLUS
9495 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
9496 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
9497 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
9499 rtx reg = SET_DEST (set);
9500 rtx plus = SET_SRC (set);
9501 rtx base = XEXP (plus, 1);
9502 rtx prev = prev_nonnote_insn (insn);
9503 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
9504 int regno = REGNO (reg);
9506 rtx reg_sum = NULL_RTX;
9508 /* Now, we need an index register.
9509 We'll set index_reg to this index register, const_reg to the
9510 register that is to be loaded with the constant
9511 (denoted as REGZ in the substitution illustration above),
9512 and reg_sum to the register-register that we want to use to
9513 substitute uses of REG (typically in MEMs) with.
9514 First check REG and BASE for being index registers;
9515 we can use them even if they are not dead. */
9516 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
9517 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
9525 /* Otherwise, look for a free index register. Since we have
9526 checked above that neiter REG nor BASE are index registers,
9527 if we find anything at all, it will be different from these
9529 for (i = first_index_reg; i <= last_index_reg; i++)
9531 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
9532 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
9533 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
9534 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
9536 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
9537 const_reg = index_reg;
9538 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
9543 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
9544 (REGY), i.e. BASE, is not clobbered before the last use we'll
9547 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
9548 && rtx_equal_p (SET_DEST (prev_set), reg)
9549 && reg_state[regno].use_index >= 0
9550 && reg_state[REGNO (base)].store_ruid <= reg_state[regno].use_ruid
9555 /* Change destination register and - if necessary - the
9556 constant value in PREV, the constant loading instruction. */
9557 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
9558 if (reg_state[regno].offset != const0_rtx)
9559 validate_change (prev,
9560 &SET_SRC (prev_set),
9561 GEN_INT (INTVAL (SET_SRC (prev_set))
9562 + INTVAL (reg_state[regno].offset)),
9564 /* Now for every use of REG that we have recorded, replace REG
9566 for (i = reg_state[regno].use_index;
9567 i < RELOAD_COMBINE_MAX_USES; i++)
9568 validate_change (reg_state[regno].reg_use[i].insn,
9569 reg_state[regno].reg_use[i].usep,
9572 if (apply_change_group ())
9576 /* Delete the reg-reg addition. */
9577 PUT_CODE (insn, NOTE);
9578 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9579 NOTE_SOURCE_FILE (insn) = 0;
9581 if (reg_state[regno].offset != const0_rtx)
9583 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
9585 for (np = ®_NOTES (prev); *np; )
9587 if (REG_NOTE_KIND (*np) == REG_EQUAL
9588 || REG_NOTE_KIND (*np) == REG_EQUIV)
9589 *np = XEXP (*np, 1);
9591 np = &XEXP (*np, 1);
9594 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9595 reg_state[REGNO (const_reg)].store_ruid = reload_combine_ruid;
9600 note_stores (PATTERN (insn), reload_combine_note_store);
9601 if (GET_CODE (insn) == CALL_INSN)
9605 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9607 if (call_used_regs[i])
9609 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9610 reg_state[i].store_ruid = reload_combine_ruid;
9613 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
9614 link = XEXP (link, 1))
9616 rtx use = XEXP (link, 0);
9617 int regno = REGNO (XEXP (use, 0));
9618 if (GET_CODE (use) == CLOBBER)
9620 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9621 reg_state[regno].store_ruid = reload_combine_ruid;
9624 reg_state[regno].use_index = -1;
9627 if (GET_CODE (insn) == JUMP_INSN && GET_CODE (PATTERN (insn)) != RETURN)
9629 /* Non-spill registers might be used at the call destination in
9630 some unknown fashion, so we have to mark the unknown use. */
9632 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
9633 && JUMP_LABEL (insn))
9634 live = &LABEL_LIVE (JUMP_LABEL (insn));
9636 live = &ever_live_at_start;
9637 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9639 if (TEST_HARD_REG_BIT (*live, i))
9640 reg_state[i].use_index = -1;
9643 reload_combine_note_use (&PATTERN (insn), insn);
9644 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9646 if (REG_NOTE_KIND (note) == REG_INC
9647 && GET_CODE (XEXP (note, 0)) == REG)
9649 int regno = REGNO (XEXP (note, 0));
9651 reg_state[regno].store_ruid = reload_combine_ruid;
9652 reg_state[regno].use_index = -1;
9659 /* Check if DST is a register or a subreg of a register; if it is,
9660 update reg_state[regno].store_ruid and reg_state[regno].use_index
9661 accordingly. Called via note_stores from reload_combine.
9662 The second argument, SET, is ignored. */
9664 reload_combine_note_store (dst, set)
9665 rtx dst, set ATTRIBUTE_UNUSED;
9669 unsigned size = GET_MODE_SIZE (GET_MODE (dst));
9671 if (GET_CODE (dst) == SUBREG)
9673 regno = SUBREG_WORD (dst);
9674 dst = SUBREG_REG (dst);
9676 if (GET_CODE (dst) != REG)
9678 regno += REGNO (dst);
9679 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
9680 careful with registers / register parts that are not full words. */
9681 if (size < (unsigned) UNITS_PER_WORD)
9683 reg_state[regno].use_index = -1;
9684 reg_state[regno].store_ruid = reload_combine_ruid;
9688 for (i = size / UNITS_PER_WORD - 1 + regno; i >= regno; i--)
9690 reg_state[i].store_ruid = reload_combine_ruid;
9691 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9696 /* XP points to a piece of rtl that has to be checked for any uses of
9698 *XP is the pattern of INSN, or a part of it.
9699 Called from reload_combine, and recursively by itself. */
9701 reload_combine_note_use (xp, insn)
9705 enum rtx_code code = x->code;
9708 rtx offset = const0_rtx; /* For the REG case below. */
9713 if (GET_CODE (SET_DEST (x)) == REG)
9715 reload_combine_note_use (&SET_SRC (x), insn);
9721 if (GET_CODE (SET_DEST (x)) == REG)
9726 /* We are interested in (plus (reg) (const_int)) . */
9727 if (GET_CODE (XEXP (x, 0)) != REG || GET_CODE (XEXP (x, 1)) != CONST_INT)
9729 offset = XEXP (x, 1);
9734 int regno = REGNO (x);
9737 /* Some spurious USEs of pseudo registers might remain.
9738 Just ignore them. */
9739 if (regno >= FIRST_PSEUDO_REGISTER)
9742 /* If this register is already used in some unknown fashion, we
9744 If we decrement the index from zero to -1, we can't store more
9745 uses, so this register becomes used in an unknown fashion. */
9746 use_index = --reg_state[regno].use_index;
9750 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
9752 /* We have found another use for a register that is already
9753 used later. Check if the offsets match; if not, mark the
9754 register as used in an unknown fashion. */
9755 if (! rtx_equal_p (offset, reg_state[regno].offset))
9757 reg_state[regno].use_index = -1;
9763 /* This is the first use of this register we have seen since we
9764 marked it as dead. */
9765 reg_state[regno].offset = offset;
9766 reg_state[regno].use_ruid = reload_combine_ruid;
9768 reg_state[regno].reg_use[use_index].insn = insn;
9769 reg_state[regno].reg_use[use_index].usep = xp;
9777 /* Recursively process the components of X. */
9778 fmt = GET_RTX_FORMAT (code);
9779 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9782 reload_combine_note_use (&XEXP (x, i), insn);
9783 else if (fmt[i] == 'E')
9785 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9786 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9791 /* See if we can reduce the cost of a constant by replacing a move with
9793 /* We cannot do our optimization across labels. Invalidating all the
9794 information about register contents we have would be costly, so we
9795 use last_label_luid (local variable of reload_cse_move2add) to note
9796 where the label is and then later disable any optimization that would
9798 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9799 reg_set_luid[n] is larger than last_label_luid[n] . */
9800 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9801 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
9802 reg_mode[n] to be valid.
9803 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
9804 has been set to reg_offset[n] in mode reg_mode[n] .
9805 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
9806 register n has been set to the sum of reg_offset[n] and register
9807 reg_base_reg[n], calculated in mode reg_mode[n] . */
9808 static rtx reg_offset[FIRST_PSEUDO_REGISTER];
9809 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9810 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9811 /* move2add_luid is linearily increased while scanning the instructions
9812 from first to last. It is used to set reg_set_luid in
9813 reload_cse_move2add and move2add_note_store. */
9814 static int move2add_luid;
9817 reload_cse_move2add (first)
9822 int last_label_luid;
9824 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
9825 reg_set_luid[i] = 0;
9827 last_label_luid = 0;
9829 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9833 if (GET_CODE (insn) == CODE_LABEL)
9834 last_label_luid = move2add_luid;
9835 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
9837 pat = PATTERN (insn);
9838 /* For simplicity, we only perform this optimization on
9839 straightforward SETs. */
9840 if (GET_CODE (pat) == SET
9841 && GET_CODE (SET_DEST (pat)) == REG)
9843 rtx reg = SET_DEST (pat);
9844 int regno = REGNO (reg);
9845 rtx src = SET_SRC (pat);
9847 /* Check if we have valid information on the contents of this
9848 register in the mode of REG. */
9849 /* ??? We don't know how zero / sign extension is handled, hence
9850 we can't go from a narrower to a wider mode. */
9851 if (reg_set_luid[regno] > last_label_luid
9852 && (GET_MODE_SIZE (GET_MODE (reg))
9853 <= GET_MODE_SIZE (reg_mode[regno]))
9854 && GET_CODE (reg_offset[regno]) == CONST_INT)
9856 /* Try to transform (set (REGX) (CONST_INT A))
9858 (set (REGX) (CONST_INT B))
9860 (set (REGX) (CONST_INT A))
9862 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9864 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9867 rtx new_src = GEN_INT (INTVAL (src)
9868 - INTVAL (reg_offset[regno]));
9869 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9870 use (set (reg) (reg)) instead.
9871 We don't delete this insn, nor do we convert it into a
9872 note, to avoid losing register notes or the return
9873 value flag. jump2 already knowns how to get rid of
9875 if (new_src == const0_rtx)
9876 success = validate_change (insn, &SET_SRC (pat), reg, 0);
9877 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9878 && have_add2_insn (GET_MODE (reg)))
9879 success = validate_change (insn, &PATTERN (insn),
9880 gen_add2_insn (reg, new_src), 0);
9881 reg_set_luid[regno] = move2add_luid;
9882 reg_mode[regno] = GET_MODE (reg);
9883 reg_offset[regno] = src;
9887 /* Try to transform (set (REGX) (REGY))
9888 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9891 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9894 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9896 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9897 else if (GET_CODE (src) == REG
9898 && reg_base_reg[regno] == REGNO (src)
9899 && reg_set_luid[regno] > reg_set_luid[REGNO (src)])
9901 rtx next = next_nonnote_insn (insn);
9904 set = single_set (next);
9907 && SET_DEST (set) == reg
9908 && GET_CODE (SET_SRC (set)) == PLUS
9909 && XEXP (SET_SRC (set), 0) == reg
9910 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9912 rtx src3 = XEXP (SET_SRC (set), 1);
9913 rtx new_src = GEN_INT (INTVAL (src3)
9914 - INTVAL (reg_offset[regno]));
9917 if (new_src == const0_rtx)
9918 /* See above why we create (set (reg) (reg)) here. */
9920 = validate_change (next, &SET_SRC (set), reg, 0);
9921 else if ((rtx_cost (new_src, PLUS)
9922 < 2 + rtx_cost (src3, SET))
9923 && have_add2_insn (GET_MODE (reg)))
9925 = validate_change (next, &PATTERN (next),
9926 gen_add2_insn (reg, new_src), 0);
9929 /* INSN might be the first insn in a basic block
9930 if the preceding insn is a conditional jump
9931 or a possible-throwing call. */
9932 PUT_CODE (insn, NOTE);
9933 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9934 NOTE_SOURCE_FILE (insn) = 0;
9937 reg_set_luid[regno] = move2add_luid;
9938 reg_mode[regno] = GET_MODE (reg);
9939 reg_offset[regno] = src3;
9946 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9948 if (REG_NOTE_KIND (note) == REG_INC
9949 && GET_CODE (XEXP (note, 0)) == REG)
9951 /* Indicate that this register has been recently written to,
9952 but the exact contents are not available. */
9953 int regno = REGNO (XEXP (note, 0));
9954 if (regno < FIRST_PSEUDO_REGISTER)
9956 reg_set_luid[regno] = move2add_luid;
9957 reg_offset[regno] = note;
9961 note_stores (PATTERN (insn), move2add_note_store);
9962 /* If this is a CALL_INSN, all call used registers are stored with
9964 if (GET_CODE (insn) == CALL_INSN)
9966 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
9968 if (call_used_regs[i])
9970 reg_set_luid[i] = move2add_luid;
9971 reg_offset[i] = insn; /* Invalidate contents. */
9978 /* SET is a SET or CLOBBER that sets DST.
9979 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9980 Called from reload_cse_move2add via note_stores. */
9982 move2add_note_store (dst, set)
9988 enum machine_mode mode = GET_MODE (dst);
9989 if (GET_CODE (dst) == SUBREG)
9991 regno = SUBREG_WORD (dst);
9992 dst = SUBREG_REG (dst);
9994 if (GET_CODE (dst) != REG)
9997 regno += REGNO (dst);
9999 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET)
10001 rtx src = SET_SRC (set);
10003 reg_mode[regno] = mode;
10004 switch (GET_CODE (src))
10008 rtx src0 = XEXP (src, 0);
10009 if (GET_CODE (src0) == REG)
10011 if (REGNO (src0) != regno
10012 || reg_offset[regno] != const0_rtx)
10014 reg_base_reg[regno] = REGNO (src0);
10015 reg_set_luid[regno] = move2add_luid;
10017 reg_offset[regno] = XEXP (src, 1);
10020 reg_set_luid[regno] = move2add_luid;
10021 reg_offset[regno] = set; /* Invalidate contents. */
10026 reg_base_reg[regno] = REGNO (SET_SRC (set));
10027 reg_offset[regno] = const0_rtx;
10028 reg_set_luid[regno] = move2add_luid;
10032 reg_base_reg[regno] = -1;
10033 reg_offset[regno] = SET_SRC (set);
10034 reg_set_luid[regno] = move2add_luid;
10040 for (i = regno + HARD_REGNO_NREGS (regno, mode) - 1; i >= regno; i--)
10042 /* Indicate that this register has been recently written to,
10043 but the exact contents are not available. */
10044 reg_set_luid[i] = move2add_luid;
10045 reg_offset[i] = dst;
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