1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 88, 89, 92-7 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "insn-config.h"
27 #include "insn-flags.h"
28 #include "insn-codes.h"
32 #include "hard-reg-set.h"
35 #include "basic-block.h"
39 /* This file contains the reload pass of the compiler, which is
40 run after register allocation has been done. It checks that
41 each insn is valid (operands required to be in registers really
42 are in registers of the proper class) and fixes up invalid ones
43 by copying values temporarily into registers for the insns
46 The results of register allocation are described by the vector
47 reg_renumber; the insns still contain pseudo regs, but reg_renumber
48 can be used to find which hard reg, if any, a pseudo reg is in.
50 The technique we always use is to free up a few hard regs that are
51 called ``reload regs'', and for each place where a pseudo reg
52 must be in a hard reg, copy it temporarily into one of the reload regs.
54 All the pseudos that were formerly allocated to the hard regs that
55 are now in use as reload regs must be ``spilled''. This means
56 that they go to other hard regs, or to stack slots if no other
57 available hard regs can be found. Spilling can invalidate more
58 insns, requiring additional need for reloads, so we must keep checking
59 until the process stabilizes.
61 For machines with different classes of registers, we must keep track
62 of the register class needed for each reload, and make sure that
63 we allocate enough reload registers of each class.
65 The file reload.c contains the code that checks one insn for
66 validity and reports the reloads that it needs. This file
67 is in charge of scanning the entire rtl code, accumulating the
68 reload needs, spilling, assigning reload registers to use for
69 fixing up each insn, and generating the new insns to copy values
70 into the reload registers. */
73 #ifndef REGISTER_MOVE_COST
74 #define REGISTER_MOVE_COST(x, y) 2
77 /* During reload_as_needed, element N contains a REG rtx for the hard reg
78 into which reg N has been reloaded (perhaps for a previous insn). */
79 static rtx *reg_last_reload_reg;
81 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
82 for an output reload that stores into reg N. */
83 static char *reg_has_output_reload;
85 /* Indicates which hard regs are reload-registers for an output reload
86 in the current insn. */
87 static HARD_REG_SET reg_is_output_reload;
89 /* Element N is the constant value to which pseudo reg N is equivalent,
90 or zero if pseudo reg N is not equivalent to a constant.
91 find_reloads looks at this in order to replace pseudo reg N
92 with the constant it stands for. */
93 rtx *reg_equiv_constant;
95 /* Element N is a memory location to which pseudo reg N is equivalent,
96 prior to any register elimination (such as frame pointer to stack
97 pointer). Depending on whether or not it is a valid address, this value
98 is transferred to either reg_equiv_address or reg_equiv_mem. */
99 rtx *reg_equiv_memory_loc;
101 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
102 This is used when the address is not valid as a memory address
103 (because its displacement is too big for the machine.) */
104 rtx *reg_equiv_address;
106 /* Element N is the memory slot to which pseudo reg N is equivalent,
107 or zero if pseudo reg N is not equivalent to a memory slot. */
110 /* Widest width in which each pseudo reg is referred to (via subreg). */
111 static int *reg_max_ref_width;
113 /* Element N is the insn that initialized reg N from its equivalent
114 constant or memory slot. */
115 static rtx *reg_equiv_init;
117 /* During reload_as_needed, element N contains the last pseudo regno reloaded
118 into hard register N. If that pseudo reg occupied more than one register,
119 reg_reloaded_contents points to that pseudo for each spill register in
120 use; all of these must remain set for an inheritance to occur. */
121 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
123 /* During reload_as_needed, element N contains the insn for which
124 hard register N was last used. Its contents are significant only
125 when reg_reloaded_valid is set for this register. */
126 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
128 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
129 static HARD_REG_SET reg_reloaded_valid;
130 /* Indicate if the register was dead at the end of the reload.
131 This is only valid if reg_reloaded_contents is set and valid. */
132 static HARD_REG_SET reg_reloaded_dead;
134 /* Number of spill-regs so far; number of valid elements of spill_regs. */
137 /* In parallel with spill_regs, contains REG rtx's for those regs.
138 Holds the last rtx used for any given reg, or 0 if it has never
139 been used for spilling yet. This rtx is reused, provided it has
141 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
143 /* In parallel with spill_regs, contains nonzero for a spill reg
144 that was stored after the last time it was used.
145 The precise value is the insn generated to do the store. */
146 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
148 /* This table is the inverse mapping of spill_regs:
149 indexed by hard reg number,
150 it contains the position of that reg in spill_regs,
151 or -1 for something that is not in spill_regs. */
152 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
154 /* This reg set indicates registers that may not be used for retrying global
155 allocation. The registers that may not be used include all spill registers
156 and the frame pointer (if we are using one). */
157 HARD_REG_SET forbidden_regs;
159 /* This reg set indicates registers that are not good for spill registers.
160 They will not be used to complete groups of spill registers. This includes
161 all fixed registers, registers that may be eliminated, and, if
162 SMALL_REGISTER_CLASSES is zero, registers explicitly used in the rtl.
164 (spill_reg_order prevents these registers from being used to start a
166 static HARD_REG_SET bad_spill_regs;
168 /* Describes order of use of registers for reloading
169 of spilled pseudo-registers. `spills' is the number of
170 elements that are actually valid; new ones are added at the end. */
171 static short spill_regs[FIRST_PSEUDO_REGISTER];
173 /* This reg set indicates those registers that have been used a spill
174 registers. This information is used in reorg.c, to help figure out
175 what registers are live at any point. It is assumed that all spill_regs
176 are dead at every CODE_LABEL. */
178 HARD_REG_SET used_spill_regs;
180 /* Index of last register assigned as a spill register. We allocate in
181 a round-robin fashion. */
183 static int last_spill_reg;
185 /* Describes order of preference for putting regs into spill_regs.
186 Contains the numbers of all the hard regs, in order most preferred first.
187 This order is different for each function.
188 It is set up by order_regs_for_reload.
189 Empty elements at the end contain -1. */
190 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
192 /* 1 for a hard register that appears explicitly in the rtl
193 (for example, function value registers, special registers
194 used by insns, structure value pointer registers). */
195 static char regs_explicitly_used[FIRST_PSEUDO_REGISTER];
197 /* Indicates if a register was counted against the need for
198 groups. 0 means it can count against max_nongroup instead. */
199 static HARD_REG_SET counted_for_groups;
201 /* Indicates if a register was counted against the need for
202 non-groups. 0 means it can become part of a new group.
203 During choose_reload_regs, 1 here means don't use this reg
204 as part of a group, even if it seems to be otherwise ok. */
205 static HARD_REG_SET counted_for_nongroups;
207 /* Nonzero if indirect addressing is supported on the machine; this means
208 that spilling (REG n) does not require reloading it into a register in
209 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
210 value indicates the level of indirect addressing supported, e.g., two
211 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
214 static char spill_indirect_levels;
216 /* Nonzero if indirect addressing is supported when the innermost MEM is
217 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
218 which these are valid is the same as spill_indirect_levels, above. */
220 char indirect_symref_ok;
222 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
224 char double_reg_address_ok;
226 /* Record the stack slot for each spilled hard register. */
228 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
230 /* Width allocated so far for that stack slot. */
232 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
234 /* Indexed by register class and basic block number, nonzero if there is
235 any need for a spill register of that class in that basic block.
236 The pointer is 0 if we did stupid allocation and don't know
237 the structure of basic blocks. */
239 char *basic_block_needs[N_REG_CLASSES];
241 /* First uid used by insns created by reload in this function.
242 Used in find_equiv_reg. */
243 int reload_first_uid;
245 /* Flag set by local-alloc or global-alloc if anything is live in
246 a call-clobbered reg across calls. */
248 int caller_save_needed;
250 /* The register class to use for a base register when reloading an
251 address. This is normally BASE_REG_CLASS, but it may be different
252 when using SMALL_REGISTER_CLASSES and passing parameters in
254 enum reg_class reload_address_base_reg_class;
256 /* The register class to use for an index register when reloading an
257 address. This is normally INDEX_REG_CLASS, but it may be different
258 when using SMALL_REGISTER_CLASSES and passing parameters in
260 enum reg_class reload_address_index_reg_class;
262 /* Set to 1 while reload_as_needed is operating.
263 Required by some machines to handle any generated moves differently. */
265 int reload_in_progress = 0;
267 /* These arrays record the insn_code of insns that may be needed to
268 perform input and output reloads of special objects. They provide a
269 place to pass a scratch register. */
271 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
272 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
274 /* This obstack is used for allocation of rtl during register elimination.
275 The allocated storage can be freed once find_reloads has processed the
278 struct obstack reload_obstack;
279 char *reload_firstobj;
281 #define obstack_chunk_alloc xmalloc
282 #define obstack_chunk_free free
284 /* List of labels that must never be deleted. */
285 extern rtx forced_labels;
287 /* Allocation number table from global register allocation. */
288 extern int *reg_allocno;
290 /* This structure is used to record information about register eliminations.
291 Each array entry describes one possible way of eliminating a register
292 in favor of another. If there is more than one way of eliminating a
293 particular register, the most preferred should be specified first. */
295 static struct elim_table
297 int from; /* Register number to be eliminated. */
298 int to; /* Register number used as replacement. */
299 int initial_offset; /* Initial difference between values. */
300 int can_eliminate; /* Non-zero if this elimination can be done. */
301 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
302 insns made by reload. */
303 int offset; /* Current offset between the two regs. */
304 int max_offset; /* Maximum offset between the two regs. */
305 int previous_offset; /* Offset at end of previous insn. */
306 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
307 rtx from_rtx; /* REG rtx for the register to be eliminated.
308 We cannot simply compare the number since
309 we might then spuriously replace a hard
310 register corresponding to a pseudo
311 assigned to the reg to be eliminated. */
312 rtx to_rtx; /* REG rtx for the replacement. */
315 /* If a set of eliminable registers was specified, define the table from it.
316 Otherwise, default to the normal case of the frame pointer being
317 replaced by the stack pointer. */
319 #ifdef ELIMINABLE_REGS
322 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
325 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0])
327 /* Record the number of pending eliminations that have an offset not equal
328 to their initial offset. If non-zero, we use a new copy of each
329 replacement result in any insns encountered. */
330 static int num_not_at_initial_offset;
332 /* Count the number of registers that we may be able to eliminate. */
333 static int num_eliminable;
335 /* For each label, we record the offset of each elimination. If we reach
336 a label by more than one path and an offset differs, we cannot do the
337 elimination. This information is indexed by the number of the label.
338 The first table is an array of flags that records whether we have yet
339 encountered a label and the second table is an array of arrays, one
340 entry in the latter array for each elimination. */
342 static char *offsets_known_at;
343 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
345 /* Number of labels in the current function. */
347 static int num_labels;
349 struct hard_reg_n_uses { int regno; int uses; };
351 static int possible_group_p PROTO((int, int *));
352 static void count_possible_groups PROTO((int *, enum machine_mode *,
354 static int modes_equiv_for_class_p PROTO((enum machine_mode,
357 static void spill_failure PROTO((rtx));
358 static int new_spill_reg PROTO((int, int, int *, int *, int,
360 static void delete_dead_insn PROTO((rtx));
361 static void alter_reg PROTO((int, int));
362 static void mark_scratch_live PROTO((rtx));
363 static void set_label_offsets PROTO((rtx, rtx, int));
364 static int eliminate_regs_in_insn PROTO((rtx, int));
365 static void mark_not_eliminable PROTO((rtx, rtx));
366 static int spill_hard_reg PROTO((int, int, FILE *, int));
367 static void scan_paradoxical_subregs PROTO((rtx));
368 static int hard_reg_use_compare PROTO((const GENERIC_PTR, const GENERIC_PTR));
369 static void order_regs_for_reload PROTO((int));
370 static int compare_spill_regs PROTO((const GENERIC_PTR, const GENERIC_PTR));
371 static void reload_as_needed PROTO((rtx, int));
372 static void forget_old_reloads_1 PROTO((rtx, rtx));
373 static int reload_reg_class_lower PROTO((const GENERIC_PTR, const GENERIC_PTR));
374 static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
376 static void clear_reload_reg_in_use PROTO((int, int, enum reload_type,
378 static int reload_reg_free_p PROTO((int, int, enum reload_type));
379 static int reload_reg_free_before_p PROTO((int, int, enum reload_type));
380 static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
381 static int reloads_conflict PROTO((int, int));
382 static int allocate_reload_reg PROTO((int, rtx, int, int));
383 static void choose_reload_regs PROTO((rtx, rtx));
384 static void merge_assigned_reloads PROTO((rtx));
385 static void emit_reload_insns PROTO((rtx));
386 static void delete_output_reload PROTO((rtx, int, rtx));
387 static void inc_for_reload PROTO((rtx, rtx, int));
388 static int constraint_accepts_reg_p PROTO((char *, rtx));
389 static void reload_cse_invalidate_regno PROTO((int, enum machine_mode, int));
390 static int reload_cse_mem_conflict_p PROTO((rtx, rtx));
391 static void reload_cse_invalidate_mem PROTO((rtx));
392 static void reload_cse_invalidate_rtx PROTO((rtx, rtx));
393 static int reload_cse_regno_equal_p PROTO((int, rtx, enum machine_mode));
394 static int reload_cse_noop_set_p PROTO((rtx, rtx));
395 static int reload_cse_simplify_set PROTO((rtx, rtx));
396 static int reload_cse_simplify_operands PROTO((rtx));
397 static void reload_cse_check_clobber PROTO((rtx, rtx));
398 static void reload_cse_record_set PROTO((rtx, rtx));
399 static void reload_cse_delete_death_notes PROTO((rtx));
400 static void reload_cse_no_longer_dead PROTO((int, enum machine_mode));
402 /* Initialize the reload pass once per compilation. */
409 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
410 Set spill_indirect_levels to the number of levels such addressing is
411 permitted, zero if it is not permitted at all. */
414 = gen_rtx_MEM (Pmode,
416 gen_rtx_REG (Pmode, LAST_VIRTUAL_REGISTER + 1),
418 spill_indirect_levels = 0;
420 while (memory_address_p (QImode, tem))
422 spill_indirect_levels++;
423 tem = gen_rtx_MEM (Pmode, tem);
426 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
428 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
429 indirect_symref_ok = memory_address_p (QImode, tem);
431 /* See if reg+reg is a valid (and offsettable) address. */
433 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
435 tem = gen_rtx_PLUS (Pmode,
436 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
437 gen_rtx_REG (Pmode, i));
438 /* This way, we make sure that reg+reg is an offsettable address. */
439 tem = plus_constant (tem, 4);
441 if (memory_address_p (QImode, tem))
443 double_reg_address_ok = 1;
448 /* Initialize obstack for our rtl allocation. */
449 gcc_obstack_init (&reload_obstack);
450 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
452 /* Decide which register class should be used when reloading
453 addresses. If we are using SMALL_REGISTER_CLASSES, and any
454 parameters are passed in registers, then we do not want to use
455 those registers when reloading an address. Otherwise, if a
456 function argument needs a reload, we may wind up clobbering
457 another argument to the function which was already computed. If
458 we find a subset class which simply avoids those registers, we
459 use it instead. ??? It would be better to only use the
460 restricted class when we actually are loading function arguments,
461 but that is hard to determine. */
462 reload_address_base_reg_class = BASE_REG_CLASS;
463 reload_address_index_reg_class = INDEX_REG_CLASS;
464 if (SMALL_REGISTER_CLASSES)
467 HARD_REG_SET base, index;
470 COPY_HARD_REG_SET (base, reg_class_contents[BASE_REG_CLASS]);
471 COPY_HARD_REG_SET (index, reg_class_contents[INDEX_REG_CLASS]);
472 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
474 if (FUNCTION_ARG_REGNO_P (regno))
476 CLEAR_HARD_REG_BIT (base, regno);
477 CLEAR_HARD_REG_BIT (index, regno);
481 GO_IF_HARD_REG_EQUAL (base, reg_class_contents[BASE_REG_CLASS],
483 for (p = reg_class_subclasses[BASE_REG_CLASS];
484 *p != LIM_REG_CLASSES;
487 GO_IF_HARD_REG_EQUAL (base, reg_class_contents[*p], usebase);
490 reload_address_base_reg_class = *p;
495 GO_IF_HARD_REG_EQUAL (index, reg_class_contents[INDEX_REG_CLASS],
497 for (p = reg_class_subclasses[INDEX_REG_CLASS];
498 *p != LIM_REG_CLASSES;
501 GO_IF_HARD_REG_EQUAL (index, reg_class_contents[*p], useindex);
504 reload_address_index_reg_class = *p;
511 /* Main entry point for the reload pass.
513 FIRST is the first insn of the function being compiled.
515 GLOBAL nonzero means we were called from global_alloc
516 and should attempt to reallocate any pseudoregs that we
517 displace from hard regs we will use for reloads.
518 If GLOBAL is zero, we do not have enough information to do that,
519 so any pseudo reg that is spilled must go to the stack.
521 DUMPFILE is the global-reg debugging dump file stream, or 0.
522 If it is nonzero, messages are written to it to describe
523 which registers are seized as reload regs, which pseudo regs
524 are spilled from them, and where the pseudo regs are reallocated to.
526 Return value is nonzero if reload failed
527 and we must not do any more for this function. */
530 reload (first, global, dumpfile)
536 register int i, j, k;
538 register struct elim_table *ep;
540 /* The two pointers used to track the true location of the memory used
541 for label offsets. */
542 char *real_known_ptr = NULL_PTR;
543 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
545 int something_changed;
546 int something_needs_reloads;
547 int something_needs_elimination;
548 int new_basic_block_needs;
549 enum reg_class caller_save_spill_class = NO_REGS;
550 int caller_save_group_size = 1;
552 /* Nonzero means we couldn't get enough spill regs. */
555 /* The basic block number currently being processed for INSN. */
558 /* Make sure even insns with volatile mem refs are recognizable. */
561 /* Enable find_equiv_reg to distinguish insns made by reload. */
562 reload_first_uid = get_max_uid ();
564 for (i = 0; i < N_REG_CLASSES; i++)
565 basic_block_needs[i] = 0;
567 #ifdef SECONDARY_MEMORY_NEEDED
568 /* Initialize the secondary memory table. */
569 clear_secondary_mem ();
572 /* Remember which hard regs appear explicitly
573 before we merge into `regs_ever_live' the ones in which
574 pseudo regs have been allocated. */
575 bcopy (regs_ever_live, regs_explicitly_used, sizeof regs_ever_live);
577 /* We don't have a stack slot for any spill reg yet. */
578 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
579 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
581 /* Initialize the save area information for caller-save, in case some
585 /* Compute which hard registers are now in use
586 as homes for pseudo registers.
587 This is done here rather than (eg) in global_alloc
588 because this point is reached even if not optimizing. */
589 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
592 /* A function that receives a nonlocal goto must save all call-saved
594 if (current_function_has_nonlocal_label)
595 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
597 if (! call_used_regs[i] && ! fixed_regs[i])
598 regs_ever_live[i] = 1;
601 for (i = 0; i < scratch_list_length; i++)
603 mark_scratch_live (scratch_list[i]);
605 /* Make sure that the last insn in the chain
606 is not something that needs reloading. */
607 emit_note (NULL_PTR, NOTE_INSN_DELETED);
609 /* Find all the pseudo registers that didn't get hard regs
610 but do have known equivalent constants or memory slots.
611 These include parameters (known equivalent to parameter slots)
612 and cse'd or loop-moved constant memory addresses.
614 Record constant equivalents in reg_equiv_constant
615 so they will be substituted by find_reloads.
616 Record memory equivalents in reg_mem_equiv so they can
617 be substituted eventually by altering the REG-rtx's. */
619 reg_equiv_constant = (rtx *) alloca (max_regno * sizeof (rtx));
620 bzero ((char *) reg_equiv_constant, max_regno * sizeof (rtx));
621 reg_equiv_memory_loc = (rtx *) alloca (max_regno * sizeof (rtx));
622 bzero ((char *) reg_equiv_memory_loc, max_regno * sizeof (rtx));
623 reg_equiv_mem = (rtx *) alloca (max_regno * sizeof (rtx));
624 bzero ((char *) reg_equiv_mem, max_regno * sizeof (rtx));
625 reg_equiv_init = (rtx *) alloca (max_regno * sizeof (rtx));
626 bzero ((char *) reg_equiv_init, max_regno * sizeof (rtx));
627 reg_equiv_address = (rtx *) alloca (max_regno * sizeof (rtx));
628 bzero ((char *) reg_equiv_address, max_regno * sizeof (rtx));
629 reg_max_ref_width = (int *) alloca (max_regno * sizeof (int));
630 bzero ((char *) reg_max_ref_width, max_regno * sizeof (int));
632 if (SMALL_REGISTER_CLASSES)
633 CLEAR_HARD_REG_SET (forbidden_regs);
635 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
636 Also find all paradoxical subregs and find largest such for each pseudo.
637 On machines with small register classes, record hard registers that
638 are used for user variables. These can never be used for spills.
639 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
640 caller-saved registers must be marked live. */
642 for (insn = first; insn; insn = NEXT_INSN (insn))
644 rtx set = single_set (insn);
646 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
647 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
648 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
649 if (! call_used_regs[i])
650 regs_ever_live[i] = 1;
652 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
654 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
656 #ifdef LEGITIMATE_PIC_OPERAND_P
657 && (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic
658 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
662 rtx x = XEXP (note, 0);
663 i = REGNO (SET_DEST (set));
664 if (i > LAST_VIRTUAL_REGISTER)
666 if (GET_CODE (x) == MEM)
668 /* If the operand is a PLUS, the MEM may be shared,
669 so make sure we have an unshared copy here. */
670 if (GET_CODE (XEXP (x, 0)) == PLUS)
673 reg_equiv_memory_loc[i] = x;
675 else if (CONSTANT_P (x))
677 if (LEGITIMATE_CONSTANT_P (x))
678 reg_equiv_constant[i] = x;
680 reg_equiv_memory_loc[i]
681 = force_const_mem (GET_MODE (SET_DEST (set)), x);
686 /* If this register is being made equivalent to a MEM
687 and the MEM is not SET_SRC, the equivalencing insn
688 is one with the MEM as a SET_DEST and it occurs later.
689 So don't mark this insn now. */
690 if (GET_CODE (x) != MEM
691 || rtx_equal_p (SET_SRC (set), x))
692 reg_equiv_init[i] = insn;
697 /* If this insn is setting a MEM from a register equivalent to it,
698 this is the equivalencing insn. */
699 else if (set && GET_CODE (SET_DEST (set)) == MEM
700 && GET_CODE (SET_SRC (set)) == REG
701 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
702 && rtx_equal_p (SET_DEST (set),
703 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
704 reg_equiv_init[REGNO (SET_SRC (set))] = insn;
706 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
707 scan_paradoxical_subregs (PATTERN (insn));
710 /* Does this function require a frame pointer? */
712 frame_pointer_needed = (! flag_omit_frame_pointer
713 #ifdef EXIT_IGNORE_STACK
714 /* ?? If EXIT_IGNORE_STACK is set, we will not save
715 and restore sp for alloca. So we can't eliminate
716 the frame pointer in that case. At some point,
717 we should improve this by emitting the
718 sp-adjusting insns for this case. */
719 || (current_function_calls_alloca
720 && EXIT_IGNORE_STACK)
722 || FRAME_POINTER_REQUIRED);
726 /* Initialize the table of registers to eliminate. The way we do this
727 depends on how the eliminable registers were defined. */
728 #ifdef ELIMINABLE_REGS
729 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
731 ep->can_eliminate = ep->can_eliminate_previous
732 = (CAN_ELIMINATE (ep->from, ep->to)
733 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
736 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
737 = ! frame_pointer_needed;
740 /* Count the number of eliminable registers and build the FROM and TO
741 REG rtx's. Note that code in gen_rtx will cause, e.g.,
742 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
743 We depend on this. */
744 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
746 num_eliminable += ep->can_eliminate;
747 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
748 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
751 num_labels = max_label_num () - get_first_label_num ();
753 /* Allocate the tables used to store offset information at labels. */
754 /* We used to use alloca here, but the size of what it would try to
755 allocate would occasionally cause it to exceed the stack limit and
756 cause a core dump. */
757 real_known_ptr = xmalloc (num_labels);
759 = (int (*)[NUM_ELIMINABLE_REGS])
760 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
762 offsets_known_at = real_known_ptr - get_first_label_num ();
764 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
766 /* Alter each pseudo-reg rtx to contain its hard reg number.
767 Assign stack slots to the pseudos that lack hard regs or equivalents.
768 Do not touch virtual registers. */
770 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
773 /* If we have some registers we think can be eliminated, scan all insns to
774 see if there is an insn that sets one of these registers to something
775 other than itself plus a constant. If so, the register cannot be
776 eliminated. Doing this scan here eliminates an extra pass through the
777 main reload loop in the most common case where register elimination
779 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
780 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
781 || GET_CODE (insn) == CALL_INSN)
782 note_stores (PATTERN (insn), mark_not_eliminable);
784 #ifndef REGISTER_CONSTRAINTS
785 /* If all the pseudo regs have hard regs,
786 except for those that are never referenced,
787 we know that no reloads are needed. */
788 /* But that is not true if there are register constraints, since
789 in that case some pseudos might be in the wrong kind of hard reg. */
791 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
792 if (reg_renumber[i] == -1 && REG_N_REFS (i) != 0)
795 if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
797 free (real_known_ptr);
803 /* Compute the order of preference for hard registers to spill.
804 Store them by decreasing preference in potential_reload_regs. */
806 order_regs_for_reload (global);
808 /* So far, no hard regs have been spilled. */
810 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
811 spill_reg_order[i] = -1;
813 /* Initialize to -1, which means take the first spill register. */
816 /* On most machines, we can't use any register explicitly used in the
817 rtl as a spill register. But on some, we have to. Those will have
818 taken care to keep the life of hard regs as short as possible. */
820 if (! SMALL_REGISTER_CLASSES)
821 COPY_HARD_REG_SET (forbidden_regs, bad_spill_regs);
823 /* Spill any hard regs that we know we can't eliminate. */
824 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
825 if (! ep->can_eliminate)
826 spill_hard_reg (ep->from, global, dumpfile, 1);
828 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
829 if (frame_pointer_needed)
830 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, global, dumpfile, 1);
834 for (i = 0; i < N_REG_CLASSES; i++)
836 basic_block_needs[i] = (char *) alloca (n_basic_blocks);
837 bzero (basic_block_needs[i], n_basic_blocks);
840 /* From now on, we need to emit any moves without making new pseudos. */
841 reload_in_progress = 1;
843 /* This loop scans the entire function each go-round
844 and repeats until one repetition spills no additional hard regs. */
846 /* This flag is set when a pseudo reg is spilled,
847 to require another pass. Note that getting an additional reload
848 reg does not necessarily imply any pseudo reg was spilled;
849 sometimes we find a reload reg that no pseudo reg was allocated in. */
850 something_changed = 1;
851 /* This flag is set if there are any insns that require reloading. */
852 something_needs_reloads = 0;
853 /* This flag is set if there are any insns that require register
855 something_needs_elimination = 0;
856 while (something_changed)
860 /* For each class, number of reload regs needed in that class.
861 This is the maximum over all insns of the needs in that class
862 of the individual insn. */
863 int max_needs[N_REG_CLASSES];
864 /* For each class, size of group of consecutive regs
865 that is needed for the reloads of this class. */
866 int group_size[N_REG_CLASSES];
867 /* For each class, max number of consecutive groups needed.
868 (Each group contains group_size[CLASS] consecutive registers.) */
869 int max_groups[N_REG_CLASSES];
870 /* For each class, max number needed of regs that don't belong
871 to any of the groups. */
872 int max_nongroups[N_REG_CLASSES];
873 /* For each class, the machine mode which requires consecutive
874 groups of regs of that class.
875 If two different modes ever require groups of one class,
876 they must be the same size and equally restrictive for that class,
877 otherwise we can't handle the complexity. */
878 enum machine_mode group_mode[N_REG_CLASSES];
879 /* Record the insn where each maximum need is first found. */
880 rtx max_needs_insn[N_REG_CLASSES];
881 rtx max_groups_insn[N_REG_CLASSES];
882 rtx max_nongroups_insn[N_REG_CLASSES];
884 HOST_WIDE_INT starting_frame_size;
885 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
886 int previous_frame_pointer_needed = frame_pointer_needed;
888 static char *reg_class_names[] = REG_CLASS_NAMES;
890 something_changed = 0;
891 bzero ((char *) max_needs, sizeof max_needs);
892 bzero ((char *) max_groups, sizeof max_groups);
893 bzero ((char *) max_nongroups, sizeof max_nongroups);
894 bzero ((char *) max_needs_insn, sizeof max_needs_insn);
895 bzero ((char *) max_groups_insn, sizeof max_groups_insn);
896 bzero ((char *) max_nongroups_insn, sizeof max_nongroups_insn);
897 bzero ((char *) group_size, sizeof group_size);
898 for (i = 0; i < N_REG_CLASSES; i++)
899 group_mode[i] = VOIDmode;
901 /* Keep track of which basic blocks are needing the reloads. */
904 /* Remember whether any element of basic_block_needs
905 changes from 0 to 1 in this pass. */
906 new_basic_block_needs = 0;
908 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done
909 here because the stack size may be a part of the offset computation
910 for register elimination, and there might have been new stack slots
911 created in the last iteration of this loop. */
912 assign_stack_local (BLKmode, 0, 0);
914 starting_frame_size = get_frame_size ();
916 /* Reset all offsets on eliminable registers to their initial values. */
917 #ifdef ELIMINABLE_REGS
918 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
920 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
921 ep->previous_offset = ep->offset
922 = ep->max_offset = ep->initial_offset;
925 #ifdef INITIAL_FRAME_POINTER_OFFSET
926 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
928 if (!FRAME_POINTER_REQUIRED)
930 reg_eliminate[0].initial_offset = 0;
932 reg_eliminate[0].previous_offset = reg_eliminate[0].max_offset
933 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
936 num_not_at_initial_offset = 0;
938 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
940 /* Set a known offset for each forced label to be at the initial offset
941 of each elimination. We do this because we assume that all
942 computed jumps occur from a location where each elimination is
943 at its initial offset. */
945 for (x = forced_labels; x; x = XEXP (x, 1))
947 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
949 /* For each pseudo register that has an equivalent location defined,
950 try to eliminate any eliminable registers (such as the frame pointer)
951 assuming initial offsets for the replacement register, which
954 If the resulting location is directly addressable, substitute
955 the MEM we just got directly for the old REG.
957 If it is not addressable but is a constant or the sum of a hard reg
958 and constant, it is probably not addressable because the constant is
959 out of range, in that case record the address; we will generate
960 hairy code to compute the address in a register each time it is
961 needed. Similarly if it is a hard register, but one that is not
962 valid as an address register.
964 If the location is not addressable, but does not have one of the
965 above forms, assign a stack slot. We have to do this to avoid the
966 potential of producing lots of reloads if, e.g., a location involves
967 a pseudo that didn't get a hard register and has an equivalent memory
968 location that also involves a pseudo that didn't get a hard register.
970 Perhaps at some point we will improve reload_when_needed handling
971 so this problem goes away. But that's very hairy. */
973 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
974 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
976 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
978 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
980 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
981 else if (CONSTANT_P (XEXP (x, 0))
982 || (GET_CODE (XEXP (x, 0)) == REG
983 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
984 || (GET_CODE (XEXP (x, 0)) == PLUS
985 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
986 && (REGNO (XEXP (XEXP (x, 0), 0))
987 < FIRST_PSEUDO_REGISTER)
988 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
989 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
992 /* Make a new stack slot. Then indicate that something
993 changed so we go back and recompute offsets for
994 eliminable registers because the allocation of memory
995 below might change some offset. reg_equiv_{mem,address}
996 will be set up for this pseudo on the next pass around
998 reg_equiv_memory_loc[i] = 0;
999 reg_equiv_init[i] = 0;
1001 something_changed = 1;
1005 /* If we allocated another pseudo to the stack, redo elimination
1007 if (something_changed)
1010 /* If caller-saves needs a group, initialize the group to include
1011 the size and mode required for caller-saves. */
1013 if (caller_save_group_size > 1)
1015 group_mode[(int) caller_save_spill_class] = Pmode;
1016 group_size[(int) caller_save_spill_class] = caller_save_group_size;
1019 /* Compute the most additional registers needed by any instruction.
1020 Collect information separately for each class of regs. */
1022 for (insn = first; insn; insn = NEXT_INSN (insn))
1024 if (global && this_block + 1 < n_basic_blocks
1025 && insn == basic_block_head[this_block+1])
1028 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which
1029 might include REG_LABEL), we need to see what effects this
1030 has on the known offsets at labels. */
1032 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1033 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1034 && REG_NOTES (insn) != 0))
1035 set_label_offsets (insn, insn, 0);
1037 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1039 /* Nonzero means don't use a reload reg that overlaps
1040 the place where a function value can be returned. */
1041 rtx avoid_return_reg = 0;
1043 rtx old_body = PATTERN (insn);
1044 int old_code = INSN_CODE (insn);
1045 rtx old_notes = REG_NOTES (insn);
1046 int did_elimination = 0;
1048 /* To compute the number of reload registers of each class
1049 needed for an insn, we must simulate what choose_reload_regs
1050 can do. We do this by splitting an insn into an "input" and
1051 an "output" part. RELOAD_OTHER reloads are used in both.
1052 The input part uses those reloads, RELOAD_FOR_INPUT reloads,
1053 which must be live over the entire input section of reloads,
1054 and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
1055 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the
1058 The registers needed for output are RELOAD_OTHER and
1059 RELOAD_FOR_OUTPUT, which are live for the entire output
1060 portion, and the maximum of all the RELOAD_FOR_OUTPUT_ADDRESS
1061 reloads for each operand.
1063 The total number of registers needed is the maximum of the
1064 inputs and outputs. */
1068 /* [0] is normal, [1] is nongroup. */
1069 int regs[2][N_REG_CLASSES];
1070 int groups[N_REG_CLASSES];
1073 /* Each `struct needs' corresponds to one RELOAD_... type. */
1077 struct needs output;
1079 struct needs other_addr;
1080 struct needs op_addr;
1081 struct needs op_addr_reload;
1082 struct needs in_addr[MAX_RECOG_OPERANDS];
1083 struct needs in_addr_addr[MAX_RECOG_OPERANDS];
1084 struct needs out_addr[MAX_RECOG_OPERANDS];
1085 struct needs out_addr_addr[MAX_RECOG_OPERANDS];
1088 /* If needed, eliminate any eliminable registers. */
1090 did_elimination = eliminate_regs_in_insn (insn, 0);
1092 /* Set avoid_return_reg if this is an insn
1093 that might use the value of a function call. */
1094 if (SMALL_REGISTER_CLASSES && GET_CODE (insn) == CALL_INSN)
1096 if (GET_CODE (PATTERN (insn)) == SET)
1097 after_call = SET_DEST (PATTERN (insn));
1098 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1099 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1100 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
1104 else if (SMALL_REGISTER_CLASSES && after_call != 0
1105 && !(GET_CODE (PATTERN (insn)) == SET
1106 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx)
1107 && GET_CODE (PATTERN (insn)) != USE)
1109 if (reg_referenced_p (after_call, PATTERN (insn)))
1110 avoid_return_reg = after_call;
1114 /* Analyze the instruction. */
1115 find_reloads (insn, 0, spill_indirect_levels, global,
1118 /* Remember for later shortcuts which insns had any reloads or
1119 register eliminations.
1121 One might think that it would be worthwhile to mark insns
1122 that need register replacements but not reloads, but this is
1123 not safe because find_reloads may do some manipulation of
1124 the insn (such as swapping commutative operands), which would
1125 be lost when we restore the old pattern after register
1126 replacement. So the actions of find_reloads must be redone in
1127 subsequent passes or in reload_as_needed.
1129 However, it is safe to mark insns that need reloads
1130 but not register replacement. */
1132 PUT_MODE (insn, (did_elimination ? QImode
1133 : n_reloads ? HImode
1134 : GET_MODE (insn) == DImode ? DImode
1137 /* Discard any register replacements done. */
1138 if (did_elimination)
1140 obstack_free (&reload_obstack, reload_firstobj);
1141 PATTERN (insn) = old_body;
1142 INSN_CODE (insn) = old_code;
1143 REG_NOTES (insn) = old_notes;
1144 something_needs_elimination = 1;
1147 /* If this insn has no reloads, we need not do anything except
1148 in the case of a CALL_INSN when we have caller-saves and
1149 caller-save needs reloads. */
1152 && ! (GET_CODE (insn) == CALL_INSN
1153 && caller_save_spill_class != NO_REGS))
1156 something_needs_reloads = 1;
1157 bzero ((char *) &insn_needs, sizeof insn_needs);
1159 /* Count each reload once in every class
1160 containing the reload's own class. */
1162 for (i = 0; i < n_reloads; i++)
1164 register enum reg_class *p;
1165 enum reg_class class = reload_reg_class[i];
1167 enum machine_mode mode;
1169 struct needs *this_needs;
1171 /* Don't count the dummy reloads, for which one of the
1172 regs mentioned in the insn can be used for reloading.
1173 Don't count optional reloads.
1174 Don't count reloads that got combined with others. */
1175 if (reload_reg_rtx[i] != 0
1176 || reload_optional[i] != 0
1177 || (reload_out[i] == 0 && reload_in[i] == 0
1178 && ! reload_secondary_p[i]))
1181 /* Show that a reload register of this class is needed
1182 in this basic block. We do not use insn_needs and
1183 insn_groups because they are overly conservative for
1185 if (global && ! basic_block_needs[(int) class][this_block])
1187 basic_block_needs[(int) class][this_block] = 1;
1188 new_basic_block_needs = 1;
1191 mode = reload_inmode[i];
1192 if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1193 mode = reload_outmode[i];
1194 size = CLASS_MAX_NREGS (class, mode);
1196 /* If this class doesn't want a group, determine if we have
1197 a nongroup need or a regular need. We have a nongroup
1198 need if this reload conflicts with a group reload whose
1199 class intersects with this reload's class. */
1203 for (j = 0; j < n_reloads; j++)
1204 if ((CLASS_MAX_NREGS (reload_reg_class[j],
1205 (GET_MODE_SIZE (reload_outmode[j])
1206 > GET_MODE_SIZE (reload_inmode[j]))
1210 && (!reload_optional[j])
1211 && (reload_in[j] != 0 || reload_out[j] != 0
1212 || reload_secondary_p[j])
1213 && reloads_conflict (i, j)
1214 && reg_classes_intersect_p (class,
1215 reload_reg_class[j]))
1221 /* Decide which time-of-use to count this reload for. */
1222 switch (reload_when_needed[i])
1225 this_needs = &insn_needs.other;
1227 case RELOAD_FOR_INPUT:
1228 this_needs = &insn_needs.input;
1230 case RELOAD_FOR_OUTPUT:
1231 this_needs = &insn_needs.output;
1233 case RELOAD_FOR_INSN:
1234 this_needs = &insn_needs.insn;
1236 case RELOAD_FOR_OTHER_ADDRESS:
1237 this_needs = &insn_needs.other_addr;
1239 case RELOAD_FOR_INPUT_ADDRESS:
1240 this_needs = &insn_needs.in_addr[reload_opnum[i]];
1242 case RELOAD_FOR_INPADDR_ADDRESS:
1243 this_needs = &insn_needs.in_addr_addr[reload_opnum[i]];
1245 case RELOAD_FOR_OUTPUT_ADDRESS:
1246 this_needs = &insn_needs.out_addr[reload_opnum[i]];
1248 case RELOAD_FOR_OUTADDR_ADDRESS:
1249 this_needs = &insn_needs.out_addr_addr[reload_opnum[i]];
1251 case RELOAD_FOR_OPERAND_ADDRESS:
1252 this_needs = &insn_needs.op_addr;
1254 case RELOAD_FOR_OPADDR_ADDR:
1255 this_needs = &insn_needs.op_addr_reload;
1261 enum machine_mode other_mode, allocate_mode;
1263 /* Count number of groups needed separately from
1264 number of individual regs needed. */
1265 this_needs->groups[(int) class]++;
1266 p = reg_class_superclasses[(int) class];
1267 while (*p != LIM_REG_CLASSES)
1268 this_needs->groups[(int) *p++]++;
1270 /* Record size and mode of a group of this class. */
1271 /* If more than one size group is needed,
1272 make all groups the largest needed size. */
1273 if (group_size[(int) class] < size)
1275 other_mode = group_mode[(int) class];
1276 allocate_mode = mode;
1278 group_size[(int) class] = size;
1279 group_mode[(int) class] = mode;
1284 allocate_mode = group_mode[(int) class];
1287 /* Crash if two dissimilar machine modes both need
1288 groups of consecutive regs of the same class. */
1290 if (other_mode != VOIDmode && other_mode != allocate_mode
1291 && ! modes_equiv_for_class_p (allocate_mode,
1293 fatal_insn ("Two dissimilar machine modes both need groups of consecutive regs of the same class",
1298 this_needs->regs[nongroup_need][(int) class] += 1;
1299 p = reg_class_superclasses[(int) class];
1300 while (*p != LIM_REG_CLASSES)
1301 this_needs->regs[nongroup_need][(int) *p++] += 1;
1307 /* All reloads have been counted for this insn;
1308 now merge the various times of use.
1309 This sets insn_needs, etc., to the maximum total number
1310 of registers needed at any point in this insn. */
1312 for (i = 0; i < N_REG_CLASSES; i++)
1314 int in_max, out_max;
1316 /* Compute normal and nongroup needs. */
1317 for (j = 0; j <= 1; j++)
1319 for (in_max = 0, out_max = 0, k = 0;
1320 k < reload_n_operands; k++)
1324 (insn_needs.in_addr[k].regs[j][i]
1325 + insn_needs.in_addr_addr[k].regs[j][i]));
1327 = MAX (out_max, insn_needs.out_addr[k].regs[j][i]);
1330 insn_needs.out_addr_addr[k].regs[j][i]);
1333 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1334 and operand addresses but not things used to reload
1335 them. Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads
1336 don't conflict with things needed to reload inputs or
1339 in_max = MAX (MAX (insn_needs.op_addr.regs[j][i],
1340 insn_needs.op_addr_reload.regs[j][i]),
1343 out_max = MAX (out_max, insn_needs.insn.regs[j][i]);
1345 insn_needs.input.regs[j][i]
1346 = MAX (insn_needs.input.regs[j][i]
1347 + insn_needs.op_addr.regs[j][i]
1348 + insn_needs.insn.regs[j][i],
1349 in_max + insn_needs.input.regs[j][i]);
1351 insn_needs.output.regs[j][i] += out_max;
1352 insn_needs.other.regs[j][i]
1353 += MAX (MAX (insn_needs.input.regs[j][i],
1354 insn_needs.output.regs[j][i]),
1355 insn_needs.other_addr.regs[j][i]);
1359 /* Now compute group needs. */
1360 for (in_max = 0, out_max = 0, j = 0;
1361 j < reload_n_operands; j++)
1363 in_max = MAX (in_max, insn_needs.in_addr[j].groups[i]);
1364 in_max = MAX (in_max,
1365 insn_needs.in_addr_addr[j].groups[i]);
1367 = MAX (out_max, insn_needs.out_addr[j].groups[i]);
1369 = MAX (out_max, insn_needs.out_addr_addr[j].groups[i]);
1372 in_max = MAX (MAX (insn_needs.op_addr.groups[i],
1373 insn_needs.op_addr_reload.groups[i]),
1375 out_max = MAX (out_max, insn_needs.insn.groups[i]);
1377 insn_needs.input.groups[i]
1378 = MAX (insn_needs.input.groups[i]
1379 + insn_needs.op_addr.groups[i]
1380 + insn_needs.insn.groups[i],
1381 in_max + insn_needs.input.groups[i]);
1383 insn_needs.output.groups[i] += out_max;
1384 insn_needs.other.groups[i]
1385 += MAX (MAX (insn_needs.input.groups[i],
1386 insn_needs.output.groups[i]),
1387 insn_needs.other_addr.groups[i]);
1390 /* If this is a CALL_INSN and caller-saves will need
1391 a spill register, act as if the spill register is
1392 needed for this insn. However, the spill register
1393 can be used by any reload of this insn, so we only
1394 need do something if no need for that class has
1397 The assumption that every CALL_INSN will trigger a
1398 caller-save is highly conservative, however, the number
1399 of cases where caller-saves will need a spill register but
1400 a block containing a CALL_INSN won't need a spill register
1401 of that class should be quite rare.
1403 If a group is needed, the size and mode of the group will
1404 have been set up at the beginning of this loop. */
1406 if (GET_CODE (insn) == CALL_INSN
1407 && caller_save_spill_class != NO_REGS)
1409 /* See if this register would conflict with any reload
1410 that needs a group. */
1411 int nongroup_need = 0;
1412 int *caller_save_needs;
1414 for (j = 0; j < n_reloads; j++)
1415 if ((CLASS_MAX_NREGS (reload_reg_class[j],
1416 (GET_MODE_SIZE (reload_outmode[j])
1417 > GET_MODE_SIZE (reload_inmode[j]))
1421 && reg_classes_intersect_p (caller_save_spill_class,
1422 reload_reg_class[j]))
1429 = (caller_save_group_size > 1
1430 ? insn_needs.other.groups
1431 : insn_needs.other.regs[nongroup_need]);
1433 if (caller_save_needs[(int) caller_save_spill_class] == 0)
1435 register enum reg_class *p
1436 = reg_class_superclasses[(int) caller_save_spill_class];
1438 caller_save_needs[(int) caller_save_spill_class]++;
1440 while (*p != LIM_REG_CLASSES)
1441 caller_save_needs[(int) *p++] += 1;
1444 /* Show that this basic block will need a register of
1448 && ! (basic_block_needs[(int) caller_save_spill_class]
1451 basic_block_needs[(int) caller_save_spill_class]
1453 new_basic_block_needs = 1;
1457 /* If this insn stores the value of a function call,
1458 and that value is in a register that has been spilled,
1459 and if the insn needs a reload in a class
1460 that might use that register as the reload register,
1461 then add add an extra need in that class.
1462 This makes sure we have a register available that does
1463 not overlap the return value. */
1465 if (SMALL_REGISTER_CLASSES && avoid_return_reg)
1467 int regno = REGNO (avoid_return_reg);
1469 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
1471 int basic_needs[N_REG_CLASSES], basic_groups[N_REG_CLASSES];
1473 /* First compute the "basic needs", which counts a
1474 need only in the smallest class in which it
1477 bcopy ((char *) insn_needs.other.regs[0],
1478 (char *) basic_needs, sizeof basic_needs);
1479 bcopy ((char *) insn_needs.other.groups,
1480 (char *) basic_groups, sizeof basic_groups);
1482 for (i = 0; i < N_REG_CLASSES; i++)
1486 if (basic_needs[i] >= 0)
1487 for (p = reg_class_superclasses[i];
1488 *p != LIM_REG_CLASSES; p++)
1489 basic_needs[(int) *p] -= basic_needs[i];
1491 if (basic_groups[i] >= 0)
1492 for (p = reg_class_superclasses[i];
1493 *p != LIM_REG_CLASSES; p++)
1494 basic_groups[(int) *p] -= basic_groups[i];
1497 /* Now count extra regs if there might be a conflict with
1498 the return value register. */
1500 for (r = regno; r < regno + nregs; r++)
1501 if (spill_reg_order[r] >= 0)
1502 for (i = 0; i < N_REG_CLASSES; i++)
1503 if (TEST_HARD_REG_BIT (reg_class_contents[i], r))
1505 if (basic_needs[i] > 0)
1509 insn_needs.other.regs[0][i]++;
1510 p = reg_class_superclasses[i];
1511 while (*p != LIM_REG_CLASSES)
1512 insn_needs.other.regs[0][(int) *p++]++;
1514 if (basic_groups[i] > 0)
1518 insn_needs.other.groups[i]++;
1519 p = reg_class_superclasses[i];
1520 while (*p != LIM_REG_CLASSES)
1521 insn_needs.other.groups[(int) *p++]++;
1526 /* For each class, collect maximum need of any insn. */
1528 for (i = 0; i < N_REG_CLASSES; i++)
1530 if (max_needs[i] < insn_needs.other.regs[0][i])
1532 max_needs[i] = insn_needs.other.regs[0][i];
1533 max_needs_insn[i] = insn;
1535 if (max_groups[i] < insn_needs.other.groups[i])
1537 max_groups[i] = insn_needs.other.groups[i];
1538 max_groups_insn[i] = insn;
1540 if (max_nongroups[i] < insn_needs.other.regs[1][i])
1542 max_nongroups[i] = insn_needs.other.regs[1][i];
1543 max_nongroups_insn[i] = insn;
1547 /* Note that there is a continue statement above. */
1550 /* If we allocated any new memory locations, make another pass
1551 since it might have changed elimination offsets. */
1552 if (starting_frame_size != get_frame_size ())
1553 something_changed = 1;
1556 for (i = 0; i < N_REG_CLASSES; i++)
1558 if (max_needs[i] > 0)
1560 ";; Need %d reg%s of class %s (for insn %d).\n",
1561 max_needs[i], max_needs[i] == 1 ? "" : "s",
1562 reg_class_names[i], INSN_UID (max_needs_insn[i]));
1563 if (max_nongroups[i] > 0)
1565 ";; Need %d nongroup reg%s of class %s (for insn %d).\n",
1566 max_nongroups[i], max_nongroups[i] == 1 ? "" : "s",
1567 reg_class_names[i], INSN_UID (max_nongroups_insn[i]));
1568 if (max_groups[i] > 0)
1570 ";; Need %d group%s (%smode) of class %s (for insn %d).\n",
1571 max_groups[i], max_groups[i] == 1 ? "" : "s",
1572 mode_name[(int) group_mode[i]],
1573 reg_class_names[i], INSN_UID (max_groups_insn[i]));
1576 /* If we have caller-saves, set up the save areas and see if caller-save
1577 will need a spill register. */
1579 if (caller_save_needed)
1581 /* Set the offsets for setup_save_areas. */
1582 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
1584 ep->previous_offset = ep->max_offset;
1586 if ( ! setup_save_areas (&something_changed)
1587 && caller_save_spill_class == NO_REGS)
1589 /* The class we will need depends on whether the machine
1590 supports the sum of two registers for an address; see
1591 find_address_reloads for details. */
1593 caller_save_spill_class
1594 = double_reg_address_ok ? INDEX_REG_CLASS : BASE_REG_CLASS;
1595 caller_save_group_size
1596 = CLASS_MAX_NREGS (caller_save_spill_class, Pmode);
1597 something_changed = 1;
1601 /* See if anything that happened changes which eliminations are valid.
1602 For example, on the Sparc, whether or not the frame pointer can
1603 be eliminated can depend on what registers have been used. We need
1604 not check some conditions again (such as flag_omit_frame_pointer)
1605 since they can't have changed. */
1607 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1608 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
1609 #ifdef ELIMINABLE_REGS
1610 || ! CAN_ELIMINATE (ep->from, ep->to)
1613 ep->can_eliminate = 0;
1615 /* Look for the case where we have discovered that we can't replace
1616 register A with register B and that means that we will now be
1617 trying to replace register A with register C. This means we can
1618 no longer replace register C with register B and we need to disable
1619 such an elimination, if it exists. This occurs often with A == ap,
1620 B == sp, and C == fp. */
1622 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1624 struct elim_table *op;
1625 register int new_to = -1;
1627 if (! ep->can_eliminate && ep->can_eliminate_previous)
1629 /* Find the current elimination for ep->from, if there is a
1631 for (op = reg_eliminate;
1632 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1633 if (op->from == ep->from && op->can_eliminate)
1639 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
1641 for (op = reg_eliminate;
1642 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1643 if (op->from == new_to && op->to == ep->to)
1644 op->can_eliminate = 0;
1648 /* See if any registers that we thought we could eliminate the previous
1649 time are no longer eliminable. If so, something has changed and we
1650 must spill the register. Also, recompute the number of eliminable
1651 registers and see if the frame pointer is needed; it is if there is
1652 no elimination of the frame pointer that we can perform. */
1654 frame_pointer_needed = 1;
1655 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1657 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
1658 && ep->to != HARD_FRAME_POINTER_REGNUM)
1659 frame_pointer_needed = 0;
1661 if (! ep->can_eliminate && ep->can_eliminate_previous)
1663 ep->can_eliminate_previous = 0;
1664 spill_hard_reg (ep->from, global, dumpfile, 1);
1665 something_changed = 1;
1670 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1671 /* If we didn't need a frame pointer last time, but we do now, spill
1672 the hard frame pointer. */
1673 if (frame_pointer_needed && ! previous_frame_pointer_needed)
1675 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, global, dumpfile, 1);
1676 something_changed = 1;
1680 /* If all needs are met, we win. */
1682 for (i = 0; i < N_REG_CLASSES; i++)
1683 if (max_needs[i] > 0 || max_groups[i] > 0 || max_nongroups[i] > 0)
1685 if (i == N_REG_CLASSES && !new_basic_block_needs && ! something_changed)
1688 /* Not all needs are met; must spill some hard regs. */
1690 /* Put all registers spilled so far back in potential_reload_regs, but
1691 put them at the front, since we've already spilled most of the
1692 pseudos in them (we might have left some pseudos unspilled if they
1693 were in a block that didn't need any spill registers of a conflicting
1694 class. We used to try to mark off the need for those registers,
1695 but doing so properly is very complex and reallocating them is the
1696 simpler approach. First, "pack" potential_reload_regs by pushing
1697 any nonnegative entries towards the end. That will leave room
1698 for the registers we already spilled.
1700 Also, undo the marking of the spill registers from the last time
1701 around in FORBIDDEN_REGS since we will be probably be allocating
1704 ??? It is theoretically possible that we might end up not using one
1705 of our previously-spilled registers in this allocation, even though
1706 they are at the head of the list. It's not clear what to do about
1707 this, but it was no better before, when we marked off the needs met
1708 by the previously-spilled registers. With the current code, globals
1709 can be allocated into these registers, but locals cannot. */
1713 for (i = j = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
1714 if (potential_reload_regs[i] != -1)
1715 potential_reload_regs[j--] = potential_reload_regs[i];
1717 for (i = 0; i < n_spills; i++)
1719 potential_reload_regs[i] = spill_regs[i];
1720 spill_reg_order[spill_regs[i]] = -1;
1721 CLEAR_HARD_REG_BIT (forbidden_regs, spill_regs[i]);
1727 /* Now find more reload regs to satisfy the remaining need
1728 Do it by ascending class number, since otherwise a reg
1729 might be spilled for a big class and might fail to count
1730 for a smaller class even though it belongs to that class.
1732 Count spilled regs in `spills', and add entries to
1733 `spill_regs' and `spill_reg_order'.
1735 ??? Note there is a problem here.
1736 When there is a need for a group in a high-numbered class,
1737 and also need for non-group regs that come from a lower class,
1738 the non-group regs are chosen first. If there aren't many regs,
1739 they might leave no room for a group.
1741 This was happening on the 386. To fix it, we added the code
1742 that calls possible_group_p, so that the lower class won't
1743 break up the last possible group.
1745 Really fixing the problem would require changes above
1746 in counting the regs already spilled, and in choose_reload_regs.
1747 It might be hard to avoid introducing bugs there. */
1749 CLEAR_HARD_REG_SET (counted_for_groups);
1750 CLEAR_HARD_REG_SET (counted_for_nongroups);
1752 for (class = 0; class < N_REG_CLASSES; class++)
1754 /* First get the groups of registers.
1755 If we got single registers first, we might fragment
1757 while (max_groups[class] > 0)
1759 /* If any single spilled regs happen to form groups,
1760 count them now. Maybe we don't really need
1761 to spill another group. */
1762 count_possible_groups (group_size, group_mode, max_groups,
1765 if (max_groups[class] <= 0)
1768 /* Groups of size 2 (the only groups used on most machines)
1769 are treated specially. */
1770 if (group_size[class] == 2)
1772 /* First, look for a register that will complete a group. */
1773 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1777 j = potential_reload_regs[i];
1778 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1780 ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1781 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1782 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1783 && HARD_REGNO_MODE_OK (other, group_mode[class])
1784 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1786 /* We don't want one part of another group.
1787 We could get "two groups" that overlap! */
1788 && ! TEST_HARD_REG_BIT (counted_for_groups, other))
1790 (j < FIRST_PSEUDO_REGISTER - 1
1791 && (other = j + 1, spill_reg_order[other] >= 0)
1792 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1793 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1794 && HARD_REGNO_MODE_OK (j, group_mode[class])
1795 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1797 && ! TEST_HARD_REG_BIT (counted_for_groups,
1800 register enum reg_class *p;
1802 /* We have found one that will complete a group,
1803 so count off one group as provided. */
1804 max_groups[class]--;
1805 p = reg_class_superclasses[class];
1806 while (*p != LIM_REG_CLASSES)
1808 if (group_size [(int) *p] <= group_size [class])
1809 max_groups[(int) *p]--;
1813 /* Indicate both these regs are part of a group. */
1814 SET_HARD_REG_BIT (counted_for_groups, j);
1815 SET_HARD_REG_BIT (counted_for_groups, other);
1819 /* We can't complete a group, so start one. */
1820 /* Look for a pair neither of which is explicitly used. */
1821 if (SMALL_REGISTER_CLASSES && i == FIRST_PSEUDO_REGISTER)
1822 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1825 j = potential_reload_regs[i];
1826 /* Verify that J+1 is a potential reload reg. */
1827 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1828 if (potential_reload_regs[k] == j + 1)
1830 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1831 && k < FIRST_PSEUDO_REGISTER
1832 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1833 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1834 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1835 && HARD_REGNO_MODE_OK (j, group_mode[class])
1836 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1838 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1)
1839 /* Reject J at this stage
1840 if J+1 was explicitly used. */
1841 && ! regs_explicitly_used[j + 1])
1844 /* Now try any group at all
1845 whose registers are not in bad_spill_regs. */
1846 if (i == FIRST_PSEUDO_REGISTER)
1847 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1850 j = potential_reload_regs[i];
1851 /* Verify that J+1 is a potential reload reg. */
1852 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1853 if (potential_reload_regs[k] == j + 1)
1855 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1856 && k < FIRST_PSEUDO_REGISTER
1857 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1858 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1859 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1860 && HARD_REGNO_MODE_OK (j, group_mode[class])
1861 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1863 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1))
1867 /* I should be the index in potential_reload_regs
1868 of the new reload reg we have found. */
1870 if (i >= FIRST_PSEUDO_REGISTER)
1872 /* There are no groups left to spill. */
1873 spill_failure (max_groups_insn[class]);
1879 |= new_spill_reg (i, class, max_needs, NULL_PTR,
1884 /* For groups of more than 2 registers,
1885 look for a sufficient sequence of unspilled registers,
1886 and spill them all at once. */
1887 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1891 j = potential_reload_regs[i];
1893 && j + group_size[class] <= FIRST_PSEUDO_REGISTER
1894 && HARD_REGNO_MODE_OK (j, group_mode[class]))
1896 /* Check each reg in the sequence. */
1897 for (k = 0; k < group_size[class]; k++)
1898 if (! (spill_reg_order[j + k] < 0
1899 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1900 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1902 /* We got a full sequence, so spill them all. */
1903 if (k == group_size[class])
1905 register enum reg_class *p;
1906 for (k = 0; k < group_size[class]; k++)
1909 SET_HARD_REG_BIT (counted_for_groups, j + k);
1910 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1911 if (potential_reload_regs[idx] == j + k)
1914 |= new_spill_reg (idx, class,
1915 max_needs, NULL_PTR,
1919 /* We have found one that will complete a group,
1920 so count off one group as provided. */
1921 max_groups[class]--;
1922 p = reg_class_superclasses[class];
1923 while (*p != LIM_REG_CLASSES)
1925 if (group_size [(int) *p]
1926 <= group_size [class])
1927 max_groups[(int) *p]--;
1934 /* We couldn't find any registers for this reload.
1935 Avoid going into an infinite loop. */
1936 if (i >= FIRST_PSEUDO_REGISTER)
1938 /* There are no groups left. */
1939 spill_failure (max_groups_insn[class]);
1946 /* Now similarly satisfy all need for single registers. */
1948 while (max_needs[class] > 0 || max_nongroups[class] > 0)
1950 /* If we spilled enough regs, but they weren't counted
1951 against the non-group need, see if we can count them now.
1952 If so, we can avoid some actual spilling. */
1953 if (max_needs[class] <= 0 && max_nongroups[class] > 0)
1954 for (i = 0; i < n_spills; i++)
1955 if (TEST_HARD_REG_BIT (reg_class_contents[class],
1957 && !TEST_HARD_REG_BIT (counted_for_groups,
1959 && !TEST_HARD_REG_BIT (counted_for_nongroups,
1961 && max_nongroups[class] > 0)
1963 register enum reg_class *p;
1965 SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]);
1966 max_nongroups[class]--;
1967 p = reg_class_superclasses[class];
1968 while (*p != LIM_REG_CLASSES)
1969 max_nongroups[(int) *p++]--;
1971 if (max_needs[class] <= 0 && max_nongroups[class] <= 0)
1974 /* Consider the potential reload regs that aren't
1975 yet in use as reload regs, in order of preference.
1976 Find the most preferred one that's in this class. */
1978 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1979 if (potential_reload_regs[i] >= 0
1980 && TEST_HARD_REG_BIT (reg_class_contents[class],
1981 potential_reload_regs[i])
1982 /* If this reg will not be available for groups,
1983 pick one that does not foreclose possible groups.
1984 This is a kludge, and not very general,
1985 but it should be sufficient to make the 386 work,
1986 and the problem should not occur on machines with
1988 && (max_nongroups[class] == 0
1989 || possible_group_p (potential_reload_regs[i], max_groups)))
1992 /* If we couldn't get a register, try to get one even if we
1993 might foreclose possible groups. This may cause problems
1994 later, but that's better than aborting now, since it is
1995 possible that we will, in fact, be able to form the needed
1996 group even with this allocation. */
1998 if (i >= FIRST_PSEUDO_REGISTER
1999 && (asm_noperands (max_needs[class] > 0
2000 ? max_needs_insn[class]
2001 : max_nongroups_insn[class])
2003 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2004 if (potential_reload_regs[i] >= 0
2005 && TEST_HARD_REG_BIT (reg_class_contents[class],
2006 potential_reload_regs[i]))
2009 /* I should be the index in potential_reload_regs
2010 of the new reload reg we have found. */
2012 if (i >= FIRST_PSEUDO_REGISTER)
2014 /* There are no possible registers left to spill. */
2015 spill_failure (max_needs[class] > 0 ? max_needs_insn[class]
2016 : max_nongroups_insn[class]);
2022 |= new_spill_reg (i, class, max_needs, max_nongroups,
2028 /* If global-alloc was run, notify it of any register eliminations we have
2031 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2032 if (ep->can_eliminate)
2033 mark_elimination (ep->from, ep->to);
2035 /* Insert code to save and restore call-clobbered hard regs
2036 around calls. Tell if what mode to use so that we will process
2037 those insns in reload_as_needed if we have to. */
2039 if (caller_save_needed)
2040 save_call_clobbered_regs (num_eliminable ? QImode
2041 : caller_save_spill_class != NO_REGS ? HImode
2044 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
2045 If that insn didn't set the register (i.e., it copied the register to
2046 memory), just delete that insn instead of the equivalencing insn plus
2047 anything now dead. If we call delete_dead_insn on that insn, we may
2048 delete the insn that actually sets the register if the register die
2049 there and that is incorrect. */
2051 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2052 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0
2053 && GET_CODE (reg_equiv_init[i]) != NOTE)
2055 if (reg_set_p (regno_reg_rtx[i], PATTERN (reg_equiv_init[i])))
2056 delete_dead_insn (reg_equiv_init[i]);
2059 PUT_CODE (reg_equiv_init[i], NOTE);
2060 NOTE_SOURCE_FILE (reg_equiv_init[i]) = 0;
2061 NOTE_LINE_NUMBER (reg_equiv_init[i]) = NOTE_INSN_DELETED;
2065 /* Use the reload registers where necessary
2066 by generating move instructions to move the must-be-register
2067 values into or out of the reload registers. */
2069 if (something_needs_reloads || something_needs_elimination
2070 || (caller_save_needed && num_eliminable)
2071 || caller_save_spill_class != NO_REGS)
2072 reload_as_needed (first, global);
2074 /* If we were able to eliminate the frame pointer, show that it is no
2075 longer live at the start of any basic block. If it ls live by
2076 virtue of being in a pseudo, that pseudo will be marked live
2077 and hence the frame pointer will be known to be live via that
2080 if (! frame_pointer_needed)
2081 for (i = 0; i < n_basic_blocks; i++)
2082 CLEAR_REGNO_REG_SET (basic_block_live_at_start[i],
2083 HARD_FRAME_POINTER_REGNUM);
2085 /* Come here (with failure set nonzero) if we can't get enough spill regs
2086 and we decide not to abort about it. */
2089 reload_in_progress = 0;
2091 /* Now eliminate all pseudo regs by modifying them into
2092 their equivalent memory references.
2093 The REG-rtx's for the pseudos are modified in place,
2094 so all insns that used to refer to them now refer to memory.
2096 For a reg that has a reg_equiv_address, all those insns
2097 were changed by reloading so that no insns refer to it any longer;
2098 but the DECL_RTL of a variable decl may refer to it,
2099 and if so this causes the debugging info to mention the variable. */
2101 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2105 if (reg_equiv_mem[i])
2107 addr = XEXP (reg_equiv_mem[i], 0);
2108 in_struct = MEM_IN_STRUCT_P (reg_equiv_mem[i]);
2110 if (reg_equiv_address[i])
2111 addr = reg_equiv_address[i];
2114 if (reg_renumber[i] < 0)
2116 rtx reg = regno_reg_rtx[i];
2117 XEXP (reg, 0) = addr;
2118 REG_USERVAR_P (reg) = 0;
2119 MEM_IN_STRUCT_P (reg) = in_struct;
2120 PUT_CODE (reg, MEM);
2122 else if (reg_equiv_mem[i])
2123 XEXP (reg_equiv_mem[i], 0) = addr;
2127 /* Make a pass over all the insns and delete all USEs which we inserted
2128 only to tag a REG_EQUAL note on them; if PRESERVE_DEATH_INFO_REGNO_P
2129 is defined, also remove death notes for things that are no longer
2130 registers or no longer die in the insn (e.g., an input and output
2131 pseudo being tied). */
2133 for (insn = first; insn; insn = NEXT_INSN (insn))
2134 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
2138 if (GET_CODE (insn) == USE
2139 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
2141 PUT_CODE (insn, NOTE);
2142 NOTE_SOURCE_FILE (insn) = 0;
2143 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2146 #ifdef PRESERVE_DEATH_INFO_REGNO_P
2147 for (note = REG_NOTES (insn); note; note = next)
2149 next = XEXP (note, 1);
2150 if (REG_NOTE_KIND (note) == REG_DEAD
2151 && (GET_CODE (XEXP (note, 0)) != REG
2152 || reg_set_p (XEXP (note, 0), PATTERN (insn))))
2153 remove_note (insn, note);
2158 /* If we are doing stack checking, give a warning if this function's
2159 frame size is larger than we expect. */
2160 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
2162 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
2164 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2165 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
2166 size += UNITS_PER_WORD;
2168 if (size > STACK_CHECK_MAX_FRAME_SIZE)
2169 warning ("frame size too large for reliable stack checking");
2172 /* Indicate that we no longer have known memory locations or constants. */
2173 reg_equiv_constant = 0;
2174 reg_equiv_memory_loc = 0;
2177 free (real_known_ptr);
2182 free (scratch_list);
2185 free (scratch_block);
2188 CLEAR_HARD_REG_SET (used_spill_regs);
2189 for (i = 0; i < n_spills; i++)
2190 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
2195 /* Nonzero if, after spilling reg REGNO for non-groups,
2196 it will still be possible to find a group if we still need one. */
2199 possible_group_p (regno, max_groups)
2204 int class = (int) NO_REGS;
2206 for (i = 0; i < (int) N_REG_CLASSES; i++)
2207 if (max_groups[i] > 0)
2213 if (class == (int) NO_REGS)
2216 /* Consider each pair of consecutive registers. */
2217 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
2219 /* Ignore pairs that include reg REGNO. */
2220 if (i == regno || i + 1 == regno)
2223 /* Ignore pairs that are outside the class that needs the group.
2224 ??? Here we fail to handle the case where two different classes
2225 independently need groups. But this never happens with our
2226 current machine descriptions. */
2227 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
2228 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
2231 /* A pair of consecutive regs we can still spill does the trick. */
2232 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
2233 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2234 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
2237 /* A pair of one already spilled and one we can spill does it
2238 provided the one already spilled is not otherwise reserved. */
2239 if (spill_reg_order[i] < 0
2240 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2241 && spill_reg_order[i + 1] >= 0
2242 && ! TEST_HARD_REG_BIT (counted_for_groups, i + 1)
2243 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i + 1))
2245 if (spill_reg_order[i + 1] < 0
2246 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
2247 && spill_reg_order[i] >= 0
2248 && ! TEST_HARD_REG_BIT (counted_for_groups, i)
2249 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i))
2256 /* Count any groups of CLASS that can be formed from the registers recently
2260 count_possible_groups (group_size, group_mode, max_groups, class)
2262 enum machine_mode *group_mode;
2269 /* Now find all consecutive groups of spilled registers
2270 and mark each group off against the need for such groups.
2271 But don't count them against ordinary need, yet. */
2273 if (group_size[class] == 0)
2276 CLEAR_HARD_REG_SET (new);
2278 /* Make a mask of all the regs that are spill regs in class I. */
2279 for (i = 0; i < n_spills; i++)
2280 if (TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
2281 && ! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[i])
2282 && ! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
2283 SET_HARD_REG_BIT (new, spill_regs[i]);
2285 /* Find each consecutive group of them. */
2286 for (i = 0; i < FIRST_PSEUDO_REGISTER && max_groups[class] > 0; i++)
2287 if (TEST_HARD_REG_BIT (new, i)
2288 && i + group_size[class] <= FIRST_PSEUDO_REGISTER
2289 && HARD_REGNO_MODE_OK (i, group_mode[class]))
2291 for (j = 1; j < group_size[class]; j++)
2292 if (! TEST_HARD_REG_BIT (new, i + j))
2295 if (j == group_size[class])
2297 /* We found a group. Mark it off against this class's need for
2298 groups, and against each superclass too. */
2299 register enum reg_class *p;
2301 max_groups[class]--;
2302 p = reg_class_superclasses[class];
2303 while (*p != LIM_REG_CLASSES)
2305 if (group_size [(int) *p] <= group_size [class])
2306 max_groups[(int) *p]--;
2310 /* Don't count these registers again. */
2311 for (j = 0; j < group_size[class]; j++)
2312 SET_HARD_REG_BIT (counted_for_groups, i + j);
2315 /* Skip to the last reg in this group. When i is incremented above,
2316 it will then point to the first reg of the next possible group. */
2321 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2322 another mode that needs to be reloaded for the same register class CLASS.
2323 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2324 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2326 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2327 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2328 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2329 causes unnecessary failures on machines requiring alignment of register
2330 groups when the two modes are different sizes, because the larger mode has
2331 more strict alignment rules than the smaller mode. */
2334 modes_equiv_for_class_p (allocate_mode, other_mode, class)
2335 enum machine_mode allocate_mode, other_mode;
2336 enum reg_class class;
2339 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2341 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
2342 && HARD_REGNO_MODE_OK (regno, allocate_mode)
2343 && ! HARD_REGNO_MODE_OK (regno, other_mode))
2349 /* Handle the failure to find a register to spill.
2350 INSN should be one of the insns which needed this particular spill reg. */
2353 spill_failure (insn)
2356 if (asm_noperands (PATTERN (insn)) >= 0)
2357 error_for_asm (insn, "`asm' needs too many reloads");
2359 fatal_insn ("Unable to find a register to spill.", insn);
2362 /* Add a new register to the tables of available spill-registers
2363 (as well as spilling all pseudos allocated to the register).
2364 I is the index of this register in potential_reload_regs.
2365 CLASS is the regclass whose need is being satisfied.
2366 MAX_NEEDS and MAX_NONGROUPS are the vectors of needs,
2367 so that this register can count off against them.
2368 MAX_NONGROUPS is 0 if this register is part of a group.
2369 GLOBAL and DUMPFILE are the same as the args that `reload' got. */
2372 new_spill_reg (i, class, max_needs, max_nongroups, global, dumpfile)
2380 register enum reg_class *p;
2382 int regno = potential_reload_regs[i];
2384 if (i >= FIRST_PSEUDO_REGISTER)
2385 abort (); /* Caller failed to find any register. */
2387 if (fixed_regs[regno] || TEST_HARD_REG_BIT (forbidden_regs, regno))
2389 static char *reg_class_names[] = REG_CLASS_NAMES;
2390 fatal ("fixed or forbidden register %d (%s) was spilled for class %s.\n\
2391 This may be due to a compiler bug or to impossible asm\n\
2392 statements or clauses.", regno, reg_names[regno], reg_class_names[class]);
2395 /* Make reg REGNO an additional reload reg. */
2397 potential_reload_regs[i] = -1;
2398 spill_regs[n_spills] = regno;
2399 spill_reg_order[regno] = n_spills;
2401 fprintf (dumpfile, "Spilling reg %d.\n", spill_regs[n_spills]);
2403 /* Clear off the needs we just satisfied. */
2406 p = reg_class_superclasses[class];
2407 while (*p != LIM_REG_CLASSES)
2408 max_needs[(int) *p++]--;
2410 if (max_nongroups && max_nongroups[class] > 0)
2412 SET_HARD_REG_BIT (counted_for_nongroups, regno);
2413 max_nongroups[class]--;
2414 p = reg_class_superclasses[class];
2415 while (*p != LIM_REG_CLASSES)
2416 max_nongroups[(int) *p++]--;
2419 /* Spill every pseudo reg that was allocated to this reg
2420 or to something that overlaps this reg. */
2422 val = spill_hard_reg (spill_regs[n_spills], global, dumpfile, 0);
2424 /* If there are some registers still to eliminate and this register
2425 wasn't ever used before, additional stack space may have to be
2426 allocated to store this register. Thus, we may have changed the offset
2427 between the stack and frame pointers, so mark that something has changed.
2428 (If new pseudos were spilled, thus requiring more space, VAL would have
2429 been set non-zero by the call to spill_hard_reg above since additional
2430 reloads may be needed in that case.
2432 One might think that we need only set VAL to 1 if this is a call-used
2433 register. However, the set of registers that must be saved by the
2434 prologue is not identical to the call-used set. For example, the
2435 register used by the call insn for the return PC is a call-used register,
2436 but must be saved by the prologue. */
2437 if (num_eliminable && ! regs_ever_live[spill_regs[n_spills]])
2440 regs_ever_live[spill_regs[n_spills]] = 1;
2446 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2447 data that is dead in INSN. */
2450 delete_dead_insn (insn)
2453 rtx prev = prev_real_insn (insn);
2456 /* If the previous insn sets a register that dies in our insn, delete it
2458 if (prev && GET_CODE (PATTERN (prev)) == SET
2459 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2460 && reg_mentioned_p (prev_dest, PATTERN (insn))
2461 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)))
2462 delete_dead_insn (prev);
2464 PUT_CODE (insn, NOTE);
2465 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2466 NOTE_SOURCE_FILE (insn) = 0;
2469 /* Modify the home of pseudo-reg I.
2470 The new home is present in reg_renumber[I].
2472 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2473 or it may be -1, meaning there is none or it is not relevant.
2474 This is used so that all pseudos spilled from a given hard reg
2475 can share one stack slot. */
2478 alter_reg (i, from_reg)
2482 /* When outputting an inline function, this can happen
2483 for a reg that isn't actually used. */
2484 if (regno_reg_rtx[i] == 0)
2487 /* If the reg got changed to a MEM at rtl-generation time,
2489 if (GET_CODE (regno_reg_rtx[i]) != REG)
2492 /* Modify the reg-rtx to contain the new hard reg
2493 number or else to contain its pseudo reg number. */
2494 REGNO (regno_reg_rtx[i])
2495 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2497 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2498 allocate a stack slot for it. */
2500 if (reg_renumber[i] < 0
2501 && REG_N_REFS (i) > 0
2502 && reg_equiv_constant[i] == 0
2503 && reg_equiv_memory_loc[i] == 0)
2506 int inherent_size = PSEUDO_REGNO_BYTES (i);
2507 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2510 /* Each pseudo reg has an inherent size which comes from its own mode,
2511 and a total size which provides room for paradoxical subregs
2512 which refer to the pseudo reg in wider modes.
2514 We can use a slot already allocated if it provides both
2515 enough inherent space and enough total space.
2516 Otherwise, we allocate a new slot, making sure that it has no less
2517 inherent space, and no less total space, then the previous slot. */
2520 /* No known place to spill from => no slot to reuse. */
2521 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
2522 inherent_size == total_size ? 0 : -1);
2523 if (BYTES_BIG_ENDIAN)
2524 /* Cancel the big-endian correction done in assign_stack_local.
2525 Get the address of the beginning of the slot.
2526 This is so we can do a big-endian correction unconditionally
2528 adjust = inherent_size - total_size;
2530 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2532 /* Reuse a stack slot if possible. */
2533 else if (spill_stack_slot[from_reg] != 0
2534 && spill_stack_slot_width[from_reg] >= total_size
2535 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2537 x = spill_stack_slot[from_reg];
2538 /* Allocate a bigger slot. */
2541 /* Compute maximum size needed, both for inherent size
2542 and for total size. */
2543 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2545 if (spill_stack_slot[from_reg])
2547 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2549 mode = GET_MODE (spill_stack_slot[from_reg]);
2550 if (spill_stack_slot_width[from_reg] > total_size)
2551 total_size = spill_stack_slot_width[from_reg];
2553 /* Make a slot with that size. */
2554 x = assign_stack_local (mode, total_size,
2555 inherent_size == total_size ? 0 : -1);
2557 if (BYTES_BIG_ENDIAN)
2559 /* Cancel the big-endian correction done in assign_stack_local.
2560 Get the address of the beginning of the slot.
2561 This is so we can do a big-endian correction unconditionally
2563 adjust = GET_MODE_SIZE (mode) - total_size;
2565 stack_slot = gen_rtx_MEM (mode_for_size (total_size
2568 plus_constant (XEXP (x, 0), adjust));
2570 spill_stack_slot[from_reg] = stack_slot;
2571 spill_stack_slot_width[from_reg] = total_size;
2574 /* On a big endian machine, the "address" of the slot
2575 is the address of the low part that fits its inherent mode. */
2576 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2577 adjust += (total_size - inherent_size);
2579 /* If we have any adjustment to make, or if the stack slot is the
2580 wrong mode, make a new stack slot. */
2581 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2583 x = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
2584 plus_constant (XEXP (x, 0), adjust));
2585 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2588 /* Save the stack slot for later. */
2589 reg_equiv_memory_loc[i] = x;
2593 /* Mark the slots in regs_ever_live for the hard regs
2594 used by pseudo-reg number REGNO. */
2597 mark_home_live (regno)
2600 register int i, lim;
2601 i = reg_renumber[regno];
2604 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2606 regs_ever_live[i++] = 1;
2609 /* Mark the registers used in SCRATCH as being live. */
2612 mark_scratch_live (scratch)
2616 int regno = REGNO (scratch);
2617 int lim = regno + HARD_REGNO_NREGS (regno, GET_MODE (scratch));
2619 for (i = regno; i < lim; i++)
2620 regs_ever_live[i] = 1;
2623 /* This function handles the tracking of elimination offsets around branches.
2625 X is a piece of RTL being scanned.
2627 INSN is the insn that it came from, if any.
2629 INITIAL_P is non-zero if we are to set the offset to be the initial
2630 offset and zero if we are setting the offset of the label to be the
2634 set_label_offsets (x, insn, initial_p)
2639 enum rtx_code code = GET_CODE (x);
2642 struct elim_table *p;
2647 if (LABEL_REF_NONLOCAL_P (x))
2652 /* ... fall through ... */
2655 /* If we know nothing about this label, set the desired offsets. Note
2656 that this sets the offset at a label to be the offset before a label
2657 if we don't know anything about the label. This is not correct for
2658 the label after a BARRIER, but is the best guess we can make. If
2659 we guessed wrong, we will suppress an elimination that might have
2660 been possible had we been able to guess correctly. */
2662 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2664 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2665 offsets_at[CODE_LABEL_NUMBER (x)][i]
2666 = (initial_p ? reg_eliminate[i].initial_offset
2667 : reg_eliminate[i].offset);
2668 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2671 /* Otherwise, if this is the definition of a label and it is
2672 preceded by a BARRIER, set our offsets to the known offset of
2676 && (tem = prev_nonnote_insn (insn)) != 0
2677 && GET_CODE (tem) == BARRIER)
2679 num_not_at_initial_offset = 0;
2680 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2682 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
2683 = offsets_at[CODE_LABEL_NUMBER (x)][i];
2684 if (reg_eliminate[i].can_eliminate
2685 && (reg_eliminate[i].offset
2686 != reg_eliminate[i].initial_offset))
2687 num_not_at_initial_offset++;
2692 /* If neither of the above cases is true, compare each offset
2693 with those previously recorded and suppress any eliminations
2694 where the offsets disagree. */
2696 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2697 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2698 != (initial_p ? reg_eliminate[i].initial_offset
2699 : reg_eliminate[i].offset))
2700 reg_eliminate[i].can_eliminate = 0;
2705 set_label_offsets (PATTERN (insn), insn, initial_p);
2707 /* ... fall through ... */
2711 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2712 and hence must have all eliminations at their initial offsets. */
2713 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2714 if (REG_NOTE_KIND (tem) == REG_LABEL)
2715 set_label_offsets (XEXP (tem, 0), insn, 1);
2720 /* Each of the labels in the address vector must be at their initial
2721 offsets. We want the first first for ADDR_VEC and the second
2722 field for ADDR_DIFF_VEC. */
2724 for (i = 0; i < XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2725 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2730 /* We only care about setting PC. If the source is not RETURN,
2731 IF_THEN_ELSE, or a label, disable any eliminations not at
2732 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2733 isn't one of those possibilities. For branches to a label,
2734 call ourselves recursively.
2736 Note that this can disable elimination unnecessarily when we have
2737 a non-local goto since it will look like a non-constant jump to
2738 someplace in the current function. This isn't a significant
2739 problem since such jumps will normally be when all elimination
2740 pairs are back to their initial offsets. */
2742 if (SET_DEST (x) != pc_rtx)
2745 switch (GET_CODE (SET_SRC (x)))
2752 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2756 tem = XEXP (SET_SRC (x), 1);
2757 if (GET_CODE (tem) == LABEL_REF)
2758 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2759 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2762 tem = XEXP (SET_SRC (x), 2);
2763 if (GET_CODE (tem) == LABEL_REF)
2764 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2765 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2773 /* If we reach here, all eliminations must be at their initial
2774 offset because we are doing a jump to a variable address. */
2775 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2776 if (p->offset != p->initial_offset)
2777 p->can_eliminate = 0;
2785 /* Used for communication between the next two function to properly share
2786 the vector for an ASM_OPERANDS. */
2788 static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2790 /* Scan X and replace any eliminable registers (such as fp) with a
2791 replacement (such as sp), plus an offset.
2793 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2794 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2795 MEM, we are allowed to replace a sum of a register and the constant zero
2796 with the register, which we cannot do outside a MEM. In addition, we need
2797 to record the fact that a register is referenced outside a MEM.
2799 If INSN is an insn, it is the insn containing X. If we replace a REG
2800 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2801 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2802 that the REG is being modified.
2804 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2805 That's used when we eliminate in expressions stored in notes.
2806 This means, do not set ref_outside_mem even if the reference
2809 If we see a modification to a register we know about, take the
2810 appropriate action (see case SET, below).
2812 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2813 replacements done assuming all offsets are at their initial values. If
2814 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2815 encounter, return the actual location so that find_reloads will do
2816 the proper thing. */
2819 eliminate_regs (x, mem_mode, insn)
2821 enum machine_mode mem_mode;
2824 enum rtx_code code = GET_CODE (x);
2825 struct elim_table *ep;
2848 /* This is only for the benefit of the debugging backends, which call
2849 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2850 removed after CSE. */
2851 new = eliminate_regs (XEXP (x, 0), 0, insn);
2852 if (GET_CODE (new) == MEM)
2853 return XEXP (new, 0);
2859 /* First handle the case where we encounter a bare register that
2860 is eliminable. Replace it with a PLUS. */
2861 if (regno < FIRST_PSEUDO_REGISTER)
2863 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2865 if (ep->from_rtx == x && ep->can_eliminate)
2868 /* Refs inside notes don't count for this purpose. */
2869 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2870 || GET_CODE (insn) == INSN_LIST)))
2871 ep->ref_outside_mem = 1;
2872 return plus_constant (ep->to_rtx, ep->previous_offset);
2876 else if (reg_equiv_memory_loc && reg_equiv_memory_loc[regno]
2877 && (reg_equiv_address[regno] || num_not_at_initial_offset))
2879 /* In this case, find_reloads would attempt to either use an
2880 incorrect address (if something is not at its initial offset)
2881 or substitute an replaced address into an insn (which loses
2882 if the offset is changed by some later action). So we simply
2883 return the replaced stack slot (assuming it is changed by
2884 elimination) and ignore the fact that this is actually a
2885 reference to the pseudo. Ensure we make a copy of the
2886 address in case it is shared. */
2887 new = eliminate_regs (reg_equiv_memory_loc[regno], mem_mode, insn);
2888 if (new != reg_equiv_memory_loc[regno])
2890 if (insn != 0 && GET_CODE (insn) != EXPR_LIST
2891 && GET_CODE (insn) != INSN_LIST)
2892 REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode, x), insn))
2893 = gen_rtx_EXPR_LIST (REG_EQUAL, new, NULL_RTX);
2894 return copy_rtx (new);
2900 /* If this is the sum of an eliminable register and a constant, rework
2902 if (GET_CODE (XEXP (x, 0)) == REG
2903 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2904 && CONSTANT_P (XEXP (x, 1)))
2906 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2908 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2911 /* Refs inside notes don't count for this purpose. */
2912 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2913 || GET_CODE (insn) == INSN_LIST)))
2914 ep->ref_outside_mem = 1;
2916 /* The only time we want to replace a PLUS with a REG (this
2917 occurs when the constant operand of the PLUS is the negative
2918 of the offset) is when we are inside a MEM. We won't want
2919 to do so at other times because that would change the
2920 structure of the insn in a way that reload can't handle.
2921 We special-case the commonest situation in
2922 eliminate_regs_in_insn, so just replace a PLUS with a
2923 PLUS here, unless inside a MEM. */
2924 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2925 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2928 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2929 plus_constant (XEXP (x, 1),
2930 ep->previous_offset));
2933 /* If the register is not eliminable, we are done since the other
2934 operand is a constant. */
2938 /* If this is part of an address, we want to bring any constant to the
2939 outermost PLUS. We will do this by doing register replacement in
2940 our operands and seeing if a constant shows up in one of them.
2942 We assume here this is part of an address (or a "load address" insn)
2943 since an eliminable register is not likely to appear in any other
2946 If we have (plus (eliminable) (reg)), we want to produce
2947 (plus (plus (replacement) (reg) (const))). If this was part of a
2948 normal add insn, (plus (replacement) (reg)) will be pushed as a
2949 reload. This is the desired action. */
2952 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2953 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2955 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2957 /* If one side is a PLUS and the other side is a pseudo that
2958 didn't get a hard register but has a reg_equiv_constant,
2959 we must replace the constant here since it may no longer
2960 be in the position of any operand. */
2961 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2962 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2963 && reg_renumber[REGNO (new1)] < 0
2964 && reg_equiv_constant != 0
2965 && reg_equiv_constant[REGNO (new1)] != 0)
2966 new1 = reg_equiv_constant[REGNO (new1)];
2967 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2968 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2969 && reg_renumber[REGNO (new0)] < 0
2970 && reg_equiv_constant[REGNO (new0)] != 0)
2971 new0 = reg_equiv_constant[REGNO (new0)];
2973 new = form_sum (new0, new1);
2975 /* As above, if we are not inside a MEM we do not want to
2976 turn a PLUS into something else. We might try to do so here
2977 for an addition of 0 if we aren't optimizing. */
2978 if (! mem_mode && GET_CODE (new) != PLUS)
2979 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2987 /* If this is the product of an eliminable register and a
2988 constant, apply the distribute law and move the constant out
2989 so that we have (plus (mult ..) ..). This is needed in order
2990 to keep load-address insns valid. This case is pathological.
2991 We ignore the possibility of overflow here. */
2992 if (GET_CODE (XEXP (x, 0)) == REG
2993 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2994 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2995 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2997 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
3000 /* Refs inside notes don't count for this purpose. */
3001 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
3002 || GET_CODE (insn) == INSN_LIST)))
3003 ep->ref_outside_mem = 1;
3006 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
3007 ep->previous_offset * INTVAL (XEXP (x, 1)));
3010 /* ... fall through ... */
3015 case DIV: case UDIV:
3016 case MOD: case UMOD:
3017 case AND: case IOR: case XOR:
3018 case ROTATERT: case ROTATE:
3019 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
3021 case GE: case GT: case GEU: case GTU:
3022 case LE: case LT: case LEU: case LTU:
3024 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3026 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
3028 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
3029 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
3034 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
3037 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3038 if (new != XEXP (x, 0))
3039 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
3042 /* ... fall through ... */
3045 /* Now do eliminations in the rest of the chain. If this was
3046 an EXPR_LIST, this might result in allocating more memory than is
3047 strictly needed, but it simplifies the code. */
3050 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
3051 if (new != XEXP (x, 1))
3052 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
3060 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3061 if (ep->to_rtx == XEXP (x, 0))
3063 int size = GET_MODE_SIZE (mem_mode);
3065 /* If more bytes than MEM_MODE are pushed, account for them. */
3066 #ifdef PUSH_ROUNDING
3067 if (ep->to_rtx == stack_pointer_rtx)
3068 size = PUSH_ROUNDING (size);
3070 if (code == PRE_DEC || code == POST_DEC)
3076 /* Fall through to generic unary operation case. */
3077 case STRICT_LOW_PART:
3079 case SIGN_EXTEND: case ZERO_EXTEND:
3080 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3081 case FLOAT: case FIX:
3082 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3086 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3087 if (new != XEXP (x, 0))
3088 return gen_rtx_fmt_e (code, GET_MODE (x), new);
3092 /* Similar to above processing, but preserve SUBREG_WORD.
3093 Convert (subreg (mem)) to (mem) if not paradoxical.
3094 Also, if we have a non-paradoxical (subreg (pseudo)) and the
3095 pseudo didn't get a hard reg, we must replace this with the
3096 eliminated version of the memory location because push_reloads
3097 may do the replacement in certain circumstances. */
3098 if (GET_CODE (SUBREG_REG (x)) == REG
3099 && (GET_MODE_SIZE (GET_MODE (x))
3100 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3101 && reg_equiv_memory_loc != 0
3102 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
3104 new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
3107 /* If we didn't change anything, we must retain the pseudo. */
3108 if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
3109 new = SUBREG_REG (x);
3112 /* In this case, we must show that the pseudo is used in this
3113 insn so that delete_output_reload will do the right thing. */
3114 if (insn != 0 && GET_CODE (insn) != EXPR_LIST
3115 && GET_CODE (insn) != INSN_LIST)
3116 REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode,
3119 = gen_rtx_EXPR_LIST (REG_EQUAL, new, NULL_RTX);
3121 /* Ensure NEW isn't shared in case we have to reload it. */
3122 new = copy_rtx (new);
3126 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
3128 if (new != XEXP (x, 0))
3130 int x_size = GET_MODE_SIZE (GET_MODE (x));
3131 int new_size = GET_MODE_SIZE (GET_MODE (new));
3133 if (GET_CODE (new) == MEM
3134 && ((x_size < new_size
3135 #ifdef WORD_REGISTER_OPERATIONS
3136 /* On these machines, combine can create rtl of the form
3137 (set (subreg:m1 (reg:m2 R) 0) ...)
3138 where m1 < m2, and expects something interesting to
3139 happen to the entire word. Moreover, it will use the
3140 (reg:m2 R) later, expecting all bits to be preserved.
3141 So if the number of words is the same, preserve the
3142 subreg so that push_reloads can see it. */
3143 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
3146 || (x_size == new_size))
3149 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
3150 enum machine_mode mode = GET_MODE (x);
3152 if (BYTES_BIG_ENDIAN)
3153 offset += (MIN (UNITS_PER_WORD,
3154 GET_MODE_SIZE (GET_MODE (new)))
3155 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
3157 PUT_MODE (new, mode);
3158 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
3162 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
3168 /* If using a register that is the source of an eliminate we still
3169 think can be performed, note it cannot be performed since we don't
3170 know how this register is used. */
3171 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3172 if (ep->from_rtx == XEXP (x, 0))
3173 ep->can_eliminate = 0;
3175 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3176 if (new != XEXP (x, 0))
3177 return gen_rtx_fmt_e (code, GET_MODE (x), new);
3181 /* If clobbering a register that is the replacement register for an
3182 elimination we still think can be performed, note that it cannot
3183 be performed. Otherwise, we need not be concerned about it. */
3184 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3185 if (ep->to_rtx == XEXP (x, 0))
3186 ep->can_eliminate = 0;
3188 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3189 if (new != XEXP (x, 0))
3190 return gen_rtx_fmt_e (code, GET_MODE (x), new);
3196 /* Properly handle sharing input and constraint vectors. */
3197 if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
3199 /* When we come to a new vector not seen before,
3200 scan all its elements; keep the old vector if none
3201 of them changes; otherwise, make a copy. */
3202 old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
3203 temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
3204 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3205 temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
3208 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3209 if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
3212 if (i == ASM_OPERANDS_INPUT_LENGTH (x))
3213 new_asm_operands_vec = old_asm_operands_vec;
3215 new_asm_operands_vec
3216 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
3219 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
3220 if (new_asm_operands_vec == old_asm_operands_vec)
3223 new = gen_rtx_ASM_OPERANDS (VOIDmode, ASM_OPERANDS_TEMPLATE (x),
3224 ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
3225 ASM_OPERANDS_OUTPUT_IDX (x),
3226 new_asm_operands_vec,
3227 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
3228 ASM_OPERANDS_SOURCE_FILE (x),
3229 ASM_OPERANDS_SOURCE_LINE (x));
3230 new->volatil = x->volatil;
3235 /* Check for setting a register that we know about. */
3236 if (GET_CODE (SET_DEST (x)) == REG)
3238 /* See if this is setting the replacement register for an
3241 If DEST is the hard frame pointer, we do nothing because we
3242 assume that all assignments to the frame pointer are for
3243 non-local gotos and are being done at a time when they are valid
3244 and do not disturb anything else. Some machines want to
3245 eliminate a fake argument pointer (or even a fake frame pointer)
3246 with either the real frame or the stack pointer. Assignments to
3247 the hard frame pointer must not prevent this elimination. */
3249 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3251 if (ep->to_rtx == SET_DEST (x)
3252 && SET_DEST (x) != hard_frame_pointer_rtx)
3254 /* If it is being incremented, adjust the offset. Otherwise,
3255 this elimination can't be done. */
3256 rtx src = SET_SRC (x);
3258 if (GET_CODE (src) == PLUS
3259 && XEXP (src, 0) == SET_DEST (x)
3260 && GET_CODE (XEXP (src, 1)) == CONST_INT)
3261 ep->offset -= INTVAL (XEXP (src, 1));
3263 ep->can_eliminate = 0;
3266 /* Now check to see we are assigning to a register that can be
3267 eliminated. If so, it must be as part of a PARALLEL, since we
3268 will not have been called if this is a single SET. So indicate
3269 that we can no longer eliminate this reg. */
3270 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3272 if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
3273 ep->can_eliminate = 0;
3276 /* Now avoid the loop below in this common case. */
3278 rtx new0 = eliminate_regs (SET_DEST (x), 0, insn);
3279 rtx new1 = eliminate_regs (SET_SRC (x), 0, insn);
3281 /* If SET_DEST changed from a REG to a MEM and INSN is an insn,
3282 write a CLOBBER insn. */
3283 if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
3284 && insn != 0 && GET_CODE (insn) != EXPR_LIST
3285 && GET_CODE (insn) != INSN_LIST)
3286 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, SET_DEST (x)), insn);
3288 if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
3289 return gen_rtx_SET (VOIDmode, new0, new1);
3295 /* This is only for the benefit of the debugging backends, which call
3296 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
3297 removed after CSE. */
3298 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
3299 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
3301 /* Our only special processing is to pass the mode of the MEM to our
3302 recursive call and copy the flags. While we are here, handle this
3303 case more efficiently. */
3304 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
3305 if (new != XEXP (x, 0))
3307 new = gen_rtx_MEM (GET_MODE (x), new);
3308 new->volatil = x->volatil;
3309 new->unchanging = x->unchanging;
3310 new->in_struct = x->in_struct;
3320 /* Process each of our operands recursively. If any have changed, make a
3322 fmt = GET_RTX_FORMAT (code);
3323 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3327 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
3328 if (new != XEXP (x, i) && ! copied)
3330 rtx new_x = rtx_alloc (code);
3331 bcopy ((char *) x, (char *) new_x,
3332 (sizeof (*new_x) - sizeof (new_x->fld)
3333 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
3339 else if (*fmt == 'E')
3342 for (j = 0; j < XVECLEN (x, i); j++)
3344 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
3345 if (new != XVECEXP (x, i, j) && ! copied_vec)
3347 rtvec new_v = gen_rtvec_vv (XVECLEN (x, i),
3351 rtx new_x = rtx_alloc (code);
3352 bcopy ((char *) x, (char *) new_x,
3353 (sizeof (*new_x) - sizeof (new_x->fld)
3354 + (sizeof (new_x->fld[0])
3355 * GET_RTX_LENGTH (code))));
3359 XVEC (x, i) = new_v;
3362 XVECEXP (x, i, j) = new;
3370 /* Scan INSN and eliminate all eliminable registers in it.
3372 If REPLACE is nonzero, do the replacement destructively. Also
3373 delete the insn as dead it if it is setting an eliminable register.
3375 If REPLACE is zero, do all our allocations in reload_obstack.
3377 If no eliminations were done and this insn doesn't require any elimination
3378 processing (these are not identical conditions: it might be updating sp,
3379 but not referencing fp; this needs to be seen during reload_as_needed so
3380 that the offset between fp and sp can be taken into consideration), zero
3381 is returned. Otherwise, 1 is returned. */
3384 eliminate_regs_in_insn (insn, replace)
3388 rtx old_body = PATTERN (insn);
3389 rtx old_set = single_set (insn);
3392 struct elim_table *ep;
3395 push_obstacks (&reload_obstack, &reload_obstack);
3397 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
3398 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3400 /* Check for setting an eliminable register. */
3401 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3402 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3404 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3405 /* If this is setting the frame pointer register to the
3406 hardware frame pointer register and this is an elimination
3407 that will be done (tested above), this insn is really
3408 adjusting the frame pointer downward to compensate for
3409 the adjustment done before a nonlocal goto. */
3410 if (ep->from == FRAME_POINTER_REGNUM
3411 && ep->to == HARD_FRAME_POINTER_REGNUM)
3413 rtx src = SET_SRC (old_set);
3415 rtx prev_insn, prev_set;
3417 if (src == ep->to_rtx)
3419 else if (GET_CODE (src) == PLUS
3420 && GET_CODE (XEXP (src, 0)) == CONST_INT)
3421 offset = INTVAL (XEXP (src, 0)), ok = 1;
3422 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
3423 && (prev_set = single_set (prev_insn)) != 0
3424 && rtx_equal_p (SET_DEST (prev_set), src))
3426 src = SET_SRC (prev_set);
3427 if (src == ep->to_rtx)
3429 else if (GET_CODE (src) == PLUS
3430 && GET_CODE (XEXP (src, 0)) == CONST_INT
3431 && XEXP (src, 1) == ep->to_rtx)
3432 offset = INTVAL (XEXP (src, 0)), ok = 1;
3433 else if (GET_CODE (src) == PLUS
3434 && GET_CODE (XEXP (src, 1)) == CONST_INT
3435 && XEXP (src, 0) == ep->to_rtx)
3436 offset = INTVAL (XEXP (src, 1)), ok = 1;
3444 = plus_constant (ep->to_rtx, offset - ep->offset);
3446 /* First see if this insn remains valid when we
3447 make the change. If not, keep the INSN_CODE
3448 the same and let reload fit it up. */
3449 validate_change (insn, &SET_SRC (old_set), src, 1);
3450 validate_change (insn, &SET_DEST (old_set),
3452 if (! apply_change_group ())
3454 SET_SRC (old_set) = src;
3455 SET_DEST (old_set) = ep->to_rtx;
3465 /* In this case this insn isn't serving a useful purpose. We
3466 will delete it in reload_as_needed once we know that this
3467 elimination is, in fact, being done.
3469 If REPLACE isn't set, we can't delete this insn, but needn't
3470 process it since it won't be used unless something changes. */
3472 delete_dead_insn (insn);
3477 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3478 in the insn is the negative of the offset in FROM. Substitute
3479 (set (reg) (reg to)) for the insn and change its code.
3481 We have to do this here, rather than in eliminate_regs, do that we can
3482 change the insn code. */
3484 if (GET_CODE (SET_SRC (old_set)) == PLUS
3485 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3486 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT)
3487 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3489 if (ep->from_rtx == XEXP (SET_SRC (old_set), 0)
3490 && ep->can_eliminate)
3492 /* We must stop at the first elimination that will be used.
3493 If this one would replace the PLUS with a REG, do it
3494 now. Otherwise, quit the loop and let eliminate_regs
3495 do its normal replacement. */
3496 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_set), 1)))
3498 /* We assume here that we don't need a PARALLEL of
3499 any CLOBBERs for this assignment. There's not
3500 much we can do if we do need it. */
3501 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3504 INSN_CODE (insn) = -1;
3513 old_asm_operands_vec = 0;
3515 /* Replace the body of this insn with a substituted form. If we changed
3516 something, return non-zero.
3518 If we are replacing a body that was a (set X (plus Y Z)), try to
3519 re-recognize the insn. We do this in case we had a simple addition
3520 but now can do this as a load-address. This saves an insn in this
3523 new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX);
3524 if (new_body != old_body)
3526 /* If we aren't replacing things permanently and we changed something,
3527 make another copy to ensure that all the RTL is new. Otherwise
3528 things can go wrong if find_reload swaps commutative operands
3529 and one is inside RTL that has been copied while the other is not. */
3531 /* Don't copy an asm_operands because (1) there's no need and (2)
3532 copy_rtx can't do it properly when there are multiple outputs. */
3533 if (! replace && asm_noperands (old_body) < 0)
3534 new_body = copy_rtx (new_body);
3536 /* If we had a move insn but now we don't, rerecognize it. This will
3537 cause spurious re-recognition if the old move had a PARALLEL since
3538 the new one still will, but we can't call single_set without
3539 having put NEW_BODY into the insn and the re-recognition won't
3540 hurt in this rare case. */
3542 && ((GET_CODE (SET_SRC (old_set)) == REG
3543 && (GET_CODE (new_body) != SET
3544 || GET_CODE (SET_SRC (new_body)) != REG))
3545 /* If this was a load from or store to memory, compare
3546 the MEM in recog_operand to the one in the insn. If they
3547 are not equal, then rerecognize the insn. */
3549 && ((GET_CODE (SET_SRC (old_set)) == MEM
3550 && SET_SRC (old_set) != recog_operand[1])
3551 || (GET_CODE (SET_DEST (old_set)) == MEM
3552 && SET_DEST (old_set) != recog_operand[0])))
3553 /* If this was an add insn before, rerecognize. */
3554 || GET_CODE (SET_SRC (old_set)) == PLUS))
3556 if (! validate_change (insn, &PATTERN (insn), new_body, 0))
3557 /* If recognition fails, store the new body anyway.
3558 It's normal to have recognition failures here
3559 due to bizarre memory addresses; reloading will fix them. */
3560 PATTERN (insn) = new_body;
3563 PATTERN (insn) = new_body;
3568 /* Loop through all elimination pairs. See if any have changed and
3569 recalculate the number not at initial offset.
3571 Compute the maximum offset (minimum offset if the stack does not
3572 grow downward) for each elimination pair.
3574 We also detect a cases where register elimination cannot be done,
3575 namely, if a register would be both changed and referenced outside a MEM
3576 in the resulting insn since such an insn is often undefined and, even if
3577 not, we cannot know what meaning will be given to it. Note that it is
3578 valid to have a register used in an address in an insn that changes it
3579 (presumably with a pre- or post-increment or decrement).
3581 If anything changes, return nonzero. */
3583 num_not_at_initial_offset = 0;
3584 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3586 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3587 ep->can_eliminate = 0;
3589 ep->ref_outside_mem = 0;
3591 if (ep->previous_offset != ep->offset)
3594 ep->previous_offset = ep->offset;
3595 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3596 num_not_at_initial_offset++;
3598 #ifdef STACK_GROWS_DOWNWARD
3599 ep->max_offset = MAX (ep->max_offset, ep->offset);
3601 ep->max_offset = MIN (ep->max_offset, ep->offset);
3606 /* If we changed something, perform elimination in REG_NOTES. This is
3607 needed even when REPLACE is zero because a REG_DEAD note might refer
3608 to a register that we eliminate and could cause a different number
3609 of spill registers to be needed in the final reload pass than in
3611 if (val && REG_NOTES (insn) != 0)
3612 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3620 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3621 replacement we currently believe is valid, mark it as not eliminable if X
3622 modifies DEST in any way other than by adding a constant integer to it.
3624 If DEST is the frame pointer, we do nothing because we assume that
3625 all assignments to the hard frame pointer are nonlocal gotos and are being
3626 done at a time when they are valid and do not disturb anything else.
3627 Some machines want to eliminate a fake argument pointer with either the
3628 frame or stack pointer. Assignments to the hard frame pointer must not
3629 prevent this elimination.
3631 Called via note_stores from reload before starting its passes to scan
3632 the insns of the function. */
3635 mark_not_eliminable (dest, x)
3641 /* A SUBREG of a hard register here is just changing its mode. We should
3642 not see a SUBREG of an eliminable hard register, but check just in
3644 if (GET_CODE (dest) == SUBREG)
3645 dest = SUBREG_REG (dest);
3647 if (dest == hard_frame_pointer_rtx)
3650 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3651 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3652 && (GET_CODE (x) != SET
3653 || GET_CODE (SET_SRC (x)) != PLUS
3654 || XEXP (SET_SRC (x), 0) != dest
3655 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3657 reg_eliminate[i].can_eliminate_previous
3658 = reg_eliminate[i].can_eliminate = 0;
3663 /* Kick all pseudos out of hard register REGNO.
3664 If GLOBAL is nonzero, try to find someplace else to put them.
3665 If DUMPFILE is nonzero, log actions taken on that file.
3667 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3668 because we found we can't eliminate some register. In the case, no pseudos
3669 are allowed to be in the register, even if they are only in a block that
3670 doesn't require spill registers, unlike the case when we are spilling this
3671 hard reg to produce another spill register.
3673 Return nonzero if any pseudos needed to be kicked out. */
3676 spill_hard_reg (regno, global, dumpfile, cant_eliminate)
3682 enum reg_class class = REGNO_REG_CLASS (regno);
3683 int something_changed = 0;
3686 SET_HARD_REG_BIT (forbidden_regs, regno);
3689 regs_ever_live[regno] = 1;
3691 /* Spill every pseudo reg that was allocated to this reg
3692 or to something that overlaps this reg. */
3694 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3695 if (reg_renumber[i] >= 0
3696 && reg_renumber[i] <= regno
3698 + HARD_REGNO_NREGS (reg_renumber[i],
3699 PSEUDO_REGNO_MODE (i))
3702 /* If this register belongs solely to a basic block which needed no
3703 spilling of any class that this register is contained in,
3704 leave it be, unless we are spilling this register because
3705 it was a hard register that can't be eliminated. */
3707 if (! cant_eliminate
3708 && basic_block_needs[0]
3709 && REG_BASIC_BLOCK (i) >= 0
3710 && basic_block_needs[(int) class][REG_BASIC_BLOCK (i)] == 0)
3714 for (p = reg_class_superclasses[(int) class];
3715 *p != LIM_REG_CLASSES; p++)
3716 if (basic_block_needs[(int) *p][REG_BASIC_BLOCK (i)] > 0)
3719 if (*p == LIM_REG_CLASSES)
3723 /* Mark it as no longer having a hard register home. */
3724 reg_renumber[i] = -1;
3725 /* We will need to scan everything again. */
3726 something_changed = 1;
3728 retry_global_alloc (i, forbidden_regs);
3730 alter_reg (i, regno);
3733 if (reg_renumber[i] == -1)
3734 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3736 fprintf (dumpfile, " Register %d now in %d.\n\n",
3737 i, reg_renumber[i]);
3740 for (i = 0; i < scratch_list_length; i++)
3742 if (scratch_list[i] && REGNO (scratch_list[i]) == regno)
3744 if (! cant_eliminate && basic_block_needs[0]
3745 && ! basic_block_needs[(int) class][scratch_block[i]])
3749 for (p = reg_class_superclasses[(int) class];
3750 *p != LIM_REG_CLASSES; p++)
3751 if (basic_block_needs[(int) *p][scratch_block[i]] > 0)
3754 if (*p == LIM_REG_CLASSES)
3757 PUT_CODE (scratch_list[i], SCRATCH);
3758 scratch_list[i] = 0;
3759 something_changed = 1;
3764 return something_changed;
3767 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3768 Also mark any hard registers used to store user variables as
3769 forbidden from being used for spill registers. */
3772 scan_paradoxical_subregs (x)
3777 register enum rtx_code code = GET_CODE (x);
3782 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3783 && REG_USERVAR_P (x))
3784 SET_HARD_REG_BIT (forbidden_regs, REGNO (x));
3799 if (GET_CODE (SUBREG_REG (x)) == REG
3800 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3801 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3802 = GET_MODE_SIZE (GET_MODE (x));
3809 fmt = GET_RTX_FORMAT (code);
3810 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3813 scan_paradoxical_subregs (XEXP (x, i));
3814 else if (fmt[i] == 'E')
3817 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3818 scan_paradoxical_subregs (XVECEXP (x, i, j));
3824 hard_reg_use_compare (p1p, p2p)
3825 const GENERIC_PTR p1p;
3826 const GENERIC_PTR p2p;
3828 struct hard_reg_n_uses *p1 = (struct hard_reg_n_uses *)p1p,
3829 *p2 = (struct hard_reg_n_uses *)p2p;
3830 int tem = p1->uses - p2->uses;
3831 if (tem != 0) return tem;
3832 /* If regs are equally good, sort by regno,
3833 so that the results of qsort leave nothing to chance. */
3834 return p1->regno - p2->regno;
3837 /* Choose the order to consider regs for use as reload registers
3838 based on how much trouble would be caused by spilling one.
3839 Store them in order of decreasing preference in potential_reload_regs. */
3842 order_regs_for_reload (global)
3849 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
3851 CLEAR_HARD_REG_SET (bad_spill_regs);
3853 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3854 potential_reload_regs[i] = -1;
3856 /* Count number of uses of each hard reg by pseudo regs allocated to it
3857 and then order them by decreasing use. */
3859 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3861 hard_reg_n_uses[i].uses = 0;
3862 hard_reg_n_uses[i].regno = i;
3865 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3867 int regno = reg_renumber[i];
3870 int lim = regno + HARD_REGNO_NREGS (regno, PSEUDO_REGNO_MODE (i));
3873 /* If allocated by local-alloc, show more uses since
3874 we're not going to be able to reallocate it, but
3875 we might if allocated by global alloc. */
3876 if (global && reg_allocno[i] < 0)
3877 hard_reg_n_uses[regno].uses += (REG_N_REFS (i) + 1) / 2;
3879 hard_reg_n_uses[regno++].uses += REG_N_REFS (i);
3882 large += REG_N_REFS (i);
3885 /* Now fixed registers (which cannot safely be used for reloading)
3886 get a very high use count so they will be considered least desirable.
3887 Registers used explicitly in the rtl code are almost as bad. */
3889 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3893 hard_reg_n_uses[i].uses += 2 * large + 2;
3894 SET_HARD_REG_BIT (bad_spill_regs, i);
3896 else if (regs_explicitly_used[i])
3898 hard_reg_n_uses[i].uses += large + 1;
3899 if (! SMALL_REGISTER_CLASSES)
3900 /* ??? We are doing this here because of the potential
3901 that bad code may be generated if a register explicitly
3902 used in an insn was used as a spill register for that
3903 insn. But not using these are spill registers may lose
3904 on some machine. We'll have to see how this works out. */
3905 SET_HARD_REG_BIT (bad_spill_regs, i);
3908 hard_reg_n_uses[HARD_FRAME_POINTER_REGNUM].uses += 2 * large + 2;
3909 SET_HARD_REG_BIT (bad_spill_regs, HARD_FRAME_POINTER_REGNUM);
3911 #ifdef ELIMINABLE_REGS
3912 /* If registers other than the frame pointer are eliminable, mark them as
3914 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3916 hard_reg_n_uses[reg_eliminate[i].from].uses += 2 * large + 2;
3917 SET_HARD_REG_BIT (bad_spill_regs, reg_eliminate[i].from);
3921 /* Prefer registers not so far used, for use in temporary loading.
3922 Among them, if REG_ALLOC_ORDER is defined, use that order.
3923 Otherwise, prefer registers not preserved by calls. */
3925 #ifdef REG_ALLOC_ORDER
3926 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3928 int regno = reg_alloc_order[i];
3930 if (hard_reg_n_uses[regno].uses == 0)
3931 potential_reload_regs[o++] = regno;
3934 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3936 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i])
3937 potential_reload_regs[o++] = i;
3939 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3941 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i])
3942 potential_reload_regs[o++] = i;
3946 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
3947 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
3949 /* Now add the regs that are already used,
3950 preferring those used less often. The fixed and otherwise forbidden
3951 registers will be at the end of this list. */
3953 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3954 if (hard_reg_n_uses[i].uses != 0)
3955 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
3958 /* Used in reload_as_needed to sort the spilled regs. */
3961 compare_spill_regs (r1p, r2p)
3962 const GENERIC_PTR r1p;
3963 const GENERIC_PTR r2p;
3965 short r1 = *(short *)r1p, r2 = *(short *)r2p;
3969 /* Reload pseudo-registers into hard regs around each insn as needed.
3970 Additional register load insns are output before the insn that needs it
3971 and perhaps store insns after insns that modify the reloaded pseudo reg.
3973 reg_last_reload_reg and reg_reloaded_contents keep track of
3974 which registers are already available in reload registers.
3975 We update these for the reloads that we perform,
3976 as the insns are scanned. */
3979 reload_as_needed (first, live_known)
3989 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
3990 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
3991 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
3992 bzero ((char *) reg_last_reload_reg, max_regno * sizeof (rtx));
3993 reg_has_output_reload = (char *) alloca (max_regno);
3994 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3996 /* Reset all offsets on eliminable registers to their initial values. */
3997 #ifdef ELIMINABLE_REGS
3998 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
4000 INITIAL_ELIMINATION_OFFSET (reg_eliminate[i].from, reg_eliminate[i].to,
4001 reg_eliminate[i].initial_offset);
4002 reg_eliminate[i].previous_offset
4003 = reg_eliminate[i].offset = reg_eliminate[i].initial_offset;
4006 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
4007 reg_eliminate[0].previous_offset
4008 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
4011 num_not_at_initial_offset = 0;
4013 /* Order the spilled regs, so that allocate_reload_regs can guarantee to
4014 pack registers with group needs. */
4017 qsort (spill_regs, n_spills, sizeof (short), compare_spill_regs);
4018 for (i = 0; i < n_spills; i++)
4019 spill_reg_order[spill_regs[i]] = i;
4022 for (insn = first; insn;)
4024 register rtx next = NEXT_INSN (insn);
4026 /* Notice when we move to a new basic block. */
4027 if (live_known && this_block + 1 < n_basic_blocks
4028 && insn == basic_block_head[this_block+1])
4031 /* If we pass a label, copy the offsets from the label information
4032 into the current offsets of each elimination. */
4033 if (GET_CODE (insn) == CODE_LABEL)
4035 num_not_at_initial_offset = 0;
4036 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
4038 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
4039 = offsets_at[CODE_LABEL_NUMBER (insn)][i];
4040 if (reg_eliminate[i].can_eliminate
4041 && (reg_eliminate[i].offset
4042 != reg_eliminate[i].initial_offset))
4043 num_not_at_initial_offset++;
4047 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
4049 rtx avoid_return_reg = 0;
4050 rtx oldpat = PATTERN (insn);
4052 /* Set avoid_return_reg if this is an insn
4053 that might use the value of a function call. */
4054 if (SMALL_REGISTER_CLASSES && GET_CODE (insn) == CALL_INSN)
4056 if (GET_CODE (PATTERN (insn)) == SET)
4057 after_call = SET_DEST (PATTERN (insn));
4058 else if (GET_CODE (PATTERN (insn)) == PARALLEL
4059 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
4060 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
4064 else if (SMALL_REGISTER_CLASSES && after_call != 0
4065 && !(GET_CODE (PATTERN (insn)) == SET
4066 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx)
4067 && GET_CODE (PATTERN (insn)) != USE)
4069 if (reg_referenced_p (after_call, PATTERN (insn)))
4070 avoid_return_reg = after_call;
4074 /* If this is a USE and CLOBBER of a MEM, ensure that any
4075 references to eliminable registers have been removed. */
4077 if ((GET_CODE (PATTERN (insn)) == USE
4078 || GET_CODE (PATTERN (insn)) == CLOBBER)
4079 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
4080 XEXP (XEXP (PATTERN (insn), 0), 0)
4081 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4082 GET_MODE (XEXP (PATTERN (insn), 0)),
4085 /* If we need to do register elimination processing, do so.
4086 This might delete the insn, in which case we are done. */
4087 if (num_eliminable && GET_MODE (insn) == QImode)
4089 eliminate_regs_in_insn (insn, 1);
4090 if (GET_CODE (insn) == NOTE)
4097 if (GET_MODE (insn) == VOIDmode)
4099 /* First find the pseudo regs that must be reloaded for this insn.
4100 This info is returned in the tables reload_... (see reload.h).
4101 Also modify the body of INSN by substituting RELOAD
4102 rtx's for those pseudo regs. */
4105 bzero (reg_has_output_reload, max_regno);
4106 CLEAR_HARD_REG_SET (reg_is_output_reload);
4108 find_reloads (insn, 1, spill_indirect_levels, live_known,
4114 rtx prev = PREV_INSN (insn), next = NEXT_INSN (insn);
4118 /* If this block has not had spilling done for a
4119 particular clas and we have any non-optionals that need a
4120 spill reg in that class, abort. */
4122 for (class = 0; class < N_REG_CLASSES; class++)
4123 if (basic_block_needs[class] != 0
4124 && basic_block_needs[class][this_block] == 0)
4125 for (i = 0; i < n_reloads; i++)
4126 if (class == (int) reload_reg_class[i]
4127 && reload_reg_rtx[i] == 0
4128 && ! reload_optional[i]
4129 && (reload_in[i] != 0 || reload_out[i] != 0
4130 || reload_secondary_p[i] != 0))
4131 fatal_insn ("Non-optional registers need a spill register", insn);
4133 /* Now compute which reload regs to reload them into. Perhaps
4134 reusing reload regs from previous insns, or else output
4135 load insns to reload them. Maybe output store insns too.
4136 Record the choices of reload reg in reload_reg_rtx. */
4137 choose_reload_regs (insn, avoid_return_reg);
4139 /* Merge any reloads that we didn't combine for fear of
4140 increasing the number of spill registers needed but now
4141 discover can be safely merged. */
4142 if (SMALL_REGISTER_CLASSES)
4143 merge_assigned_reloads (insn);
4145 /* Generate the insns to reload operands into or out of
4146 their reload regs. */
4147 emit_reload_insns (insn);
4149 /* Substitute the chosen reload regs from reload_reg_rtx
4150 into the insn's body (or perhaps into the bodies of other
4151 load and store insn that we just made for reloading
4152 and that we moved the structure into). */
4155 /* If this was an ASM, make sure that all the reload insns
4156 we have generated are valid. If not, give an error
4159 if (asm_noperands (PATTERN (insn)) >= 0)
4160 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4161 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
4162 && (recog_memoized (p) < 0
4163 || (insn_extract (p),
4164 ! constrain_operands (INSN_CODE (p), 1))))
4166 error_for_asm (insn,
4167 "`asm' operand requires impossible reload");
4169 NOTE_SOURCE_FILE (p) = 0;
4170 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
4173 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4174 is no longer validly lying around to save a future reload.
4175 Note that this does not detect pseudos that were reloaded
4176 for this insn in order to be stored in
4177 (obeying register constraints). That is correct; such reload
4178 registers ARE still valid. */
4179 note_stores (oldpat, forget_old_reloads_1);
4181 /* There may have been CLOBBER insns placed after INSN. So scan
4182 between INSN and NEXT and use them to forget old reloads. */
4183 for (x = NEXT_INSN (insn); x != next; x = NEXT_INSN (x))
4184 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
4185 note_stores (PATTERN (x), forget_old_reloads_1);
4188 /* Likewise for regs altered by auto-increment in this insn.
4189 But note that the reg-notes are not changed by reloading:
4190 they still contain the pseudo-regs, not the spill regs. */
4191 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4192 if (REG_NOTE_KIND (x) == REG_INC)
4194 /* See if this pseudo reg was reloaded in this insn.
4195 If so, its last-reload info is still valid
4196 because it is based on this insn's reload. */
4197 for (i = 0; i < n_reloads; i++)
4198 if (reload_out[i] == XEXP (x, 0))
4202 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX);
4206 /* A reload reg's contents are unknown after a label. */
4207 if (GET_CODE (insn) == CODE_LABEL)
4208 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4210 /* Don't assume a reload reg is still good after a call insn
4211 if it is a call-used reg. */
4212 else if (GET_CODE (insn) == CALL_INSN)
4213 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
4215 /* In case registers overlap, allow certain insns to invalidate
4216 particular hard registers. */
4218 #ifdef INSN_CLOBBERS_REGNO_P
4219 for (i = 0 ; i < FIRST_PSEUDO_REGISTER; i++)
4220 if (TEST_HARD_REG_BIT (reg_reloaded_valid, i)
4221 && INSN_CLOBBERS_REGNO_P (insn, i))
4222 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i);
4233 /* Discard all record of any value reloaded from X,
4234 or reloaded in X from someplace else;
4235 unless X is an output reload reg of the current insn.
4237 X may be a hard reg (the reload reg)
4238 or it may be a pseudo reg that was reloaded from. */
4241 forget_old_reloads_1 (x, ignored)
4249 /* note_stores does give us subregs of hard regs. */
4250 while (GET_CODE (x) == SUBREG)
4252 offset += SUBREG_WORD (x);
4256 if (GET_CODE (x) != REG)
4259 regno = REGNO (x) + offset;
4261 if (regno >= FIRST_PSEUDO_REGISTER)
4266 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4267 /* Storing into a spilled-reg invalidates its contents.
4268 This can happen if a block-local pseudo is allocated to that reg
4269 and it wasn't spilled because this block's total need is 0.
4270 Then some insn might have an optional reload and use this reg. */
4271 for (i = 0; i < nr; i++)
4272 /* But don't do this if the reg actually serves as an output
4273 reload reg in the current instruction. */
4275 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4276 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4279 /* Since value of X has changed,
4280 forget any value previously copied from it. */
4283 /* But don't forget a copy if this is the output reload
4284 that establishes the copy's validity. */
4285 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4286 reg_last_reload_reg[regno + nr] = 0;
4289 /* For each reload, the mode of the reload register. */
4290 static enum machine_mode reload_mode[MAX_RELOADS];
4292 /* For each reload, the largest number of registers it will require. */
4293 static int reload_nregs[MAX_RELOADS];
4295 /* Comparison function for qsort to decide which of two reloads
4296 should be handled first. *P1 and *P2 are the reload numbers. */
4299 reload_reg_class_lower (r1p, r2p)
4300 const GENERIC_PTR r1p;
4301 const GENERIC_PTR r2p;
4303 register int r1 = *(short *)r1p, r2 = *(short *)r2p;
4306 /* Consider required reloads before optional ones. */
4307 t = reload_optional[r1] - reload_optional[r2];
4311 /* Count all solitary classes before non-solitary ones. */
4312 t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
4313 - (reg_class_size[(int) reload_reg_class[r1]] == 1));
4317 /* Aside from solitaires, consider all multi-reg groups first. */
4318 t = reload_nregs[r2] - reload_nregs[r1];
4322 /* Consider reloads in order of increasing reg-class number. */
4323 t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
4327 /* If reloads are equally urgent, sort by reload number,
4328 so that the results of qsort leave nothing to chance. */
4332 /* The following HARD_REG_SETs indicate when each hard register is
4333 used for a reload of various parts of the current insn. */
4335 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4336 static HARD_REG_SET reload_reg_used;
4337 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4338 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4339 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4340 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4341 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4342 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4343 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4344 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4345 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4346 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4347 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4348 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4349 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4350 static HARD_REG_SET reload_reg_used_in_op_addr;
4351 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4352 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4353 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4354 static HARD_REG_SET reload_reg_used_in_insn;
4355 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4356 static HARD_REG_SET reload_reg_used_in_other_addr;
4358 /* If reg is in use as a reload reg for any sort of reload. */
4359 static HARD_REG_SET reload_reg_used_at_all;
4361 /* If reg is use as an inherited reload. We just mark the first register
4363 static HARD_REG_SET reload_reg_used_for_inherit;
4365 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4366 TYPE. MODE is used to indicate how many consecutive regs are
4370 mark_reload_reg_in_use (regno, opnum, type, mode)
4373 enum reload_type type;
4374 enum machine_mode mode;
4376 int nregs = HARD_REGNO_NREGS (regno, mode);
4379 for (i = regno; i < nregs + regno; i++)
4384 SET_HARD_REG_BIT (reload_reg_used, i);
4387 case RELOAD_FOR_INPUT_ADDRESS:
4388 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4391 case RELOAD_FOR_INPADDR_ADDRESS:
4392 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4395 case RELOAD_FOR_OUTPUT_ADDRESS:
4396 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4399 case RELOAD_FOR_OUTADDR_ADDRESS:
4400 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4403 case RELOAD_FOR_OPERAND_ADDRESS:
4404 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4407 case RELOAD_FOR_OPADDR_ADDR:
4408 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4411 case RELOAD_FOR_OTHER_ADDRESS:
4412 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4415 case RELOAD_FOR_INPUT:
4416 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4419 case RELOAD_FOR_OUTPUT:
4420 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4423 case RELOAD_FOR_INSN:
4424 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4428 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4432 /* Similarly, but show REGNO is no longer in use for a reload. */
4435 clear_reload_reg_in_use (regno, opnum, type, mode)
4438 enum reload_type type;
4439 enum machine_mode mode;
4441 int nregs = HARD_REGNO_NREGS (regno, mode);
4444 for (i = regno; i < nregs + regno; i++)
4449 CLEAR_HARD_REG_BIT (reload_reg_used, i);
4452 case RELOAD_FOR_INPUT_ADDRESS:
4453 CLEAR_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4456 case RELOAD_FOR_INPADDR_ADDRESS:
4457 CLEAR_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4460 case RELOAD_FOR_OUTPUT_ADDRESS:
4461 CLEAR_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4464 case RELOAD_FOR_OUTADDR_ADDRESS:
4465 CLEAR_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4468 case RELOAD_FOR_OPERAND_ADDRESS:
4469 CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4472 case RELOAD_FOR_OPADDR_ADDR:
4473 CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4476 case RELOAD_FOR_OTHER_ADDRESS:
4477 CLEAR_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4480 case RELOAD_FOR_INPUT:
4481 CLEAR_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4484 case RELOAD_FOR_OUTPUT:
4485 CLEAR_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4488 case RELOAD_FOR_INSN:
4489 CLEAR_HARD_REG_BIT (reload_reg_used_in_insn, i);
4495 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4496 specified by OPNUM and TYPE. */
4499 reload_reg_free_p (regno, opnum, type)
4502 enum reload_type type;
4506 /* In use for a RELOAD_OTHER means it's not available for anything. */
4507 if (TEST_HARD_REG_BIT (reload_reg_used, regno))
4513 /* In use for anything means we can't use it for RELOAD_OTHER. */
4514 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4515 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4516 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4519 for (i = 0; i < reload_n_operands; i++)
4520 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4521 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4522 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4523 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4524 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4525 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4530 case RELOAD_FOR_INPUT:
4531 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4532 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4535 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4538 /* If it is used for some other input, can't use it. */
4539 for (i = 0; i < reload_n_operands; i++)
4540 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4543 /* If it is used in a later operand's address, can't use it. */
4544 for (i = opnum + 1; i < reload_n_operands; i++)
4545 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4546 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4551 case RELOAD_FOR_INPUT_ADDRESS:
4552 /* Can't use a register if it is used for an input address for this
4553 operand or used as an input in an earlier one. */
4554 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4555 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4558 for (i = 0; i < opnum; i++)
4559 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4564 case RELOAD_FOR_INPADDR_ADDRESS:
4565 /* Can't use a register if it is used for an input address
4566 address for this operand or used as an input in an earlier
4568 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4571 for (i = 0; i < opnum; i++)
4572 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4577 case RELOAD_FOR_OUTPUT_ADDRESS:
4578 /* Can't use a register if it is used for an output address for this
4579 operand or used as an output in this or a later operand. */
4580 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4583 for (i = opnum; i < reload_n_operands; i++)
4584 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4589 case RELOAD_FOR_OUTADDR_ADDRESS:
4590 /* Can't use a register if it is used for an output address
4591 address for this operand or used as an output in this or a
4593 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4596 for (i = opnum; i < reload_n_operands; i++)
4597 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4602 case RELOAD_FOR_OPERAND_ADDRESS:
4603 for (i = 0; i < reload_n_operands; i++)
4604 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4607 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4608 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4610 case RELOAD_FOR_OPADDR_ADDR:
4611 for (i = 0; i < reload_n_operands; i++)
4612 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4615 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4617 case RELOAD_FOR_OUTPUT:
4618 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4619 outputs, or an operand address for this or an earlier output. */
4620 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4623 for (i = 0; i < reload_n_operands; i++)
4624 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4627 for (i = 0; i <= opnum; i++)
4628 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4629 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4634 case RELOAD_FOR_INSN:
4635 for (i = 0; i < reload_n_operands; i++)
4636 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4637 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4640 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4641 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4643 case RELOAD_FOR_OTHER_ADDRESS:
4644 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4649 /* Return 1 if the value in reload reg REGNO, as used by a reload
4650 needed for the part of the insn specified by OPNUM and TYPE,
4651 is not in use for a reload in any prior part of the insn.
4653 We can assume that the reload reg was already tested for availability
4654 at the time it is needed, and we should not check this again,
4655 in case the reg has already been marked in use. */
4658 reload_reg_free_before_p (regno, opnum, type)
4661 enum reload_type type;
4667 case RELOAD_FOR_OTHER_ADDRESS:
4668 /* These always come first. */
4672 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4674 /* If this use is for part of the insn,
4675 check the reg is not in use for any prior part. It is tempting
4676 to try to do this by falling through from objecs that occur
4677 later in the insn to ones that occur earlier, but that will not
4678 correctly take into account the fact that here we MUST ignore
4679 things that would prevent the register from being allocated in
4680 the first place, since we know that it was allocated. */
4682 case RELOAD_FOR_OUTPUT_ADDRESS:
4683 case RELOAD_FOR_OUTADDR_ADDRESS:
4684 /* Earlier reloads are for earlier outputs or their addresses,
4685 any RELOAD_FOR_INSN reloads, any inputs or their addresses, or any
4686 RELOAD_FOR_OTHER_ADDRESS reloads (we know it can't conflict with
4688 for (i = 0; i < opnum; i++)
4689 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4690 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4691 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4694 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4697 for (i = 0; i < reload_n_operands; i++)
4698 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4699 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4700 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4703 return (! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4704 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4705 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4707 case RELOAD_FOR_OUTPUT:
4708 /* This can't be used in the output address for this operand and
4709 anything that can't be used for it, except that we've already
4710 tested for RELOAD_FOR_INSN objects. */
4712 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno)
4713 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4716 for (i = 0; i < opnum; i++)
4717 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4718 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4719 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4722 for (i = 0; i < reload_n_operands; i++)
4723 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4724 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4725 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4726 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4729 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4731 case RELOAD_FOR_OPERAND_ADDRESS:
4732 /* Earlier reloads include RELOAD_FOR_OPADDR_ADDR reloads. */
4733 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4736 /* ... fall through ... */
4738 case RELOAD_FOR_OPADDR_ADDR:
4739 case RELOAD_FOR_INSN:
4740 /* These can't conflict with inputs, or each other, so all we have to
4741 test is input addresses and the addresses of OTHER items. */
4743 for (i = 0; i < reload_n_operands; i++)
4744 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4745 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4748 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4750 case RELOAD_FOR_INPUT:
4751 /* The only things earlier are the address for this and
4752 earlier inputs, other inputs (which we know we don't conflict
4753 with), and addresses of RELOAD_OTHER objects. */
4755 for (i = 0; i <= opnum; i++)
4756 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4757 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4760 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4762 case RELOAD_FOR_INPUT_ADDRESS:
4763 case RELOAD_FOR_INPADDR_ADDRESS:
4764 /* Similarly, all we have to check is for use in earlier inputs'
4766 for (i = 0; i < opnum; i++)
4767 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4768 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4771 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4776 /* Return 1 if the value in reload reg REGNO, as used by a reload
4777 needed for the part of the insn specified by OPNUM and TYPE,
4778 is still available in REGNO at the end of the insn.
4780 We can assume that the reload reg was already tested for availability
4781 at the time it is needed, and we should not check this again,
4782 in case the reg has already been marked in use. */
4785 reload_reg_reaches_end_p (regno, opnum, type)
4788 enum reload_type type;
4795 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4796 its value must reach the end. */
4799 /* If this use is for part of the insn,
4800 its value reaches if no subsequent part uses the same register.
4801 Just like the above function, don't try to do this with lots
4804 case RELOAD_FOR_OTHER_ADDRESS:
4805 /* Here we check for everything else, since these don't conflict
4806 with anything else and everything comes later. */
4808 for (i = 0; i < reload_n_operands; i++)
4809 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4810 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4811 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4812 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4813 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4814 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4817 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4818 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4819 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4821 case RELOAD_FOR_INPUT_ADDRESS:
4822 case RELOAD_FOR_INPADDR_ADDRESS:
4823 /* Similar, except that we check only for this and subsequent inputs
4824 and the address of only subsequent inputs and we do not need
4825 to check for RELOAD_OTHER objects since they are known not to
4828 for (i = opnum; i < reload_n_operands; i++)
4829 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4832 for (i = opnum + 1; i < reload_n_operands; i++)
4833 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4834 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4837 for (i = 0; i < reload_n_operands; i++)
4838 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4839 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4840 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4843 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4846 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4847 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4849 case RELOAD_FOR_INPUT:
4850 /* Similar to input address, except we start at the next operand for
4851 both input and input address and we do not check for
4852 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4855 for (i = opnum + 1; i < reload_n_operands; i++)
4856 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4857 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4858 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4861 /* ... fall through ... */
4863 case RELOAD_FOR_OPERAND_ADDRESS:
4864 /* Check outputs and their addresses. */
4866 for (i = 0; i < reload_n_operands; i++)
4867 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4868 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4869 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4874 case RELOAD_FOR_OPADDR_ADDR:
4875 for (i = 0; i < reload_n_operands; i++)
4876 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4877 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4878 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4881 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4882 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4884 case RELOAD_FOR_INSN:
4885 /* These conflict with other outputs with RELOAD_OTHER. So
4886 we need only check for output addresses. */
4890 /* ... fall through ... */
4892 case RELOAD_FOR_OUTPUT:
4893 case RELOAD_FOR_OUTPUT_ADDRESS:
4894 case RELOAD_FOR_OUTADDR_ADDRESS:
4895 /* We already know these can't conflict with a later output. So the
4896 only thing to check are later output addresses. */
4897 for (i = opnum + 1; i < reload_n_operands; i++)
4898 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4899 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4908 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4911 This function uses the same algorithm as reload_reg_free_p above. */
4914 reloads_conflict (r1, r2)
4917 enum reload_type r1_type = reload_when_needed[r1];
4918 enum reload_type r2_type = reload_when_needed[r2];
4919 int r1_opnum = reload_opnum[r1];
4920 int r2_opnum = reload_opnum[r2];
4922 /* RELOAD_OTHER conflicts with everything. */
4923 if (r2_type == RELOAD_OTHER)
4926 /* Otherwise, check conflicts differently for each type. */
4930 case RELOAD_FOR_INPUT:
4931 return (r2_type == RELOAD_FOR_INSN
4932 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4933 || r2_type == RELOAD_FOR_OPADDR_ADDR
4934 || r2_type == RELOAD_FOR_INPUT
4935 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4936 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4937 && r2_opnum > r1_opnum));
4939 case RELOAD_FOR_INPUT_ADDRESS:
4940 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4941 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4943 case RELOAD_FOR_INPADDR_ADDRESS:
4944 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4945 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4947 case RELOAD_FOR_OUTPUT_ADDRESS:
4948 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4949 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4951 case RELOAD_FOR_OUTADDR_ADDRESS:
4952 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4953 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4955 case RELOAD_FOR_OPERAND_ADDRESS:
4956 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4957 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4959 case RELOAD_FOR_OPADDR_ADDR:
4960 return (r2_type == RELOAD_FOR_INPUT
4961 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4963 case RELOAD_FOR_OUTPUT:
4964 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4965 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4966 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4967 && r2_opnum >= r1_opnum));
4969 case RELOAD_FOR_INSN:
4970 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4971 || r2_type == RELOAD_FOR_INSN
4972 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4974 case RELOAD_FOR_OTHER_ADDRESS:
4975 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4985 /* Vector of reload-numbers showing the order in which the reloads should
4987 short reload_order[MAX_RELOADS];
4989 /* Indexed by reload number, 1 if incoming value
4990 inherited from previous insns. */
4991 char reload_inherited[MAX_RELOADS];
4993 /* For an inherited reload, this is the insn the reload was inherited from,
4994 if we know it. Otherwise, this is 0. */
4995 rtx reload_inheritance_insn[MAX_RELOADS];
4997 /* If non-zero, this is a place to get the value of the reload,
4998 rather than using reload_in. */
4999 rtx reload_override_in[MAX_RELOADS];
5001 /* For each reload, the hard register number of the register used,
5002 or -1 if we did not need a register for this reload. */
5003 int reload_spill_index[MAX_RELOADS];
5005 /* Find a spill register to use as a reload register for reload R.
5006 LAST_RELOAD is non-zero if this is the last reload for the insn being
5009 Set reload_reg_rtx[R] to the register allocated.
5011 If NOERROR is nonzero, we return 1 if successful,
5012 or 0 if we couldn't find a spill reg and we didn't change anything. */
5015 allocate_reload_reg (r, insn, last_reload, noerror)
5027 /* If we put this reload ahead, thinking it is a group,
5028 then insist on finding a group. Otherwise we can grab a
5029 reg that some other reload needs.
5030 (That can happen when we have a 68000 DATA_OR_FP_REG
5031 which is a group of data regs or one fp reg.)
5032 We need not be so restrictive if there are no more reloads
5035 ??? Really it would be nicer to have smarter handling
5036 for that kind of reg class, where a problem like this is normal.
5037 Perhaps those classes should be avoided for reloading
5038 by use of more alternatives. */
5040 int force_group = reload_nregs[r] > 1 && ! last_reload;
5042 /* If we want a single register and haven't yet found one,
5043 take any reg in the right class and not in use.
5044 If we want a consecutive group, here is where we look for it.
5046 We use two passes so we can first look for reload regs to
5047 reuse, which are already in use for other reloads in this insn,
5048 and only then use additional registers.
5049 I think that maximizing reuse is needed to make sure we don't
5050 run out of reload regs. Suppose we have three reloads, and
5051 reloads A and B can share regs. These need two regs.
5052 Suppose A and B are given different regs.
5053 That leaves none for C. */
5054 for (pass = 0; pass < 2; pass++)
5056 /* I is the index in spill_regs.
5057 We advance it round-robin between insns to use all spill regs
5058 equally, so that inherited reloads have a chance
5059 of leapfrogging each other. Don't do this, however, when we have
5060 group needs and failure would be fatal; if we only have a relatively
5061 small number of spill registers, and more than one of them has
5062 group needs, then by starting in the middle, we may end up
5063 allocating the first one in such a way that we are not left with
5064 sufficient groups to handle the rest. */
5066 if (noerror || ! force_group)
5071 for (count = 0; count < n_spills; count++)
5073 int class = (int) reload_reg_class[r];
5075 i = (i + 1) % n_spills;
5077 if (reload_reg_free_p (spill_regs[i], reload_opnum[r],
5078 reload_when_needed[r])
5079 && TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
5080 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
5081 /* Look first for regs to share, then for unshared. But
5082 don't share regs used for inherited reloads; they are
5083 the ones we want to preserve. */
5085 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5087 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5090 int nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
5091 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5092 (on 68000) got us two FP regs. If NR is 1,
5093 we would reject both of them. */
5095 nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
5096 /* If we need only one reg, we have already won. */
5099 /* But reject a single reg if we demand a group. */
5104 /* Otherwise check that as many consecutive regs as we need
5106 Also, don't use for a group registers that are
5107 needed for nongroups. */
5108 if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
5111 regno = spill_regs[i] + nr - 1;
5112 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5113 && spill_reg_order[regno] >= 0
5114 && reload_reg_free_p (regno, reload_opnum[r],
5115 reload_when_needed[r])
5116 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
5126 /* If we found something on pass 1, omit pass 2. */
5127 if (count < n_spills)
5131 /* We should have found a spill register by now. */
5132 if (count == n_spills)
5139 /* I is the index in SPILL_REG_RTX of the reload register we are to
5140 allocate. Get an rtx for it and find its register number. */
5142 new = spill_reg_rtx[i];
5144 if (new == 0 || GET_MODE (new) != reload_mode[r])
5145 spill_reg_rtx[i] = new
5146 = gen_rtx_REG (reload_mode[r], spill_regs[i]);
5148 regno = true_regnum (new);
5150 /* Detect when the reload reg can't hold the reload mode.
5151 This used to be one `if', but Sequent compiler can't handle that. */
5152 if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5154 enum machine_mode test_mode = VOIDmode;
5156 test_mode = GET_MODE (reload_in[r]);
5157 /* If reload_in[r] has VOIDmode, it means we will load it
5158 in whatever mode the reload reg has: to wit, reload_mode[r].
5159 We have already tested that for validity. */
5160 /* Aside from that, we need to test that the expressions
5161 to reload from or into have modes which are valid for this
5162 reload register. Otherwise the reload insns would be invalid. */
5163 if (! (reload_in[r] != 0 && test_mode != VOIDmode
5164 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5165 if (! (reload_out[r] != 0
5166 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
5168 /* The reg is OK. */
5171 /* Mark as in use for this insn the reload regs we use
5173 mark_reload_reg_in_use (spill_regs[i], reload_opnum[r],
5174 reload_when_needed[r], reload_mode[r]);
5176 reload_reg_rtx[r] = new;
5177 reload_spill_index[r] = spill_regs[i];
5182 /* The reg is not OK. */
5187 if (asm_noperands (PATTERN (insn)) < 0)
5188 /* It's the compiler's fault. */
5189 fatal_insn ("Could not find a spill register", insn);
5191 /* It's the user's fault; the operand's mode and constraint
5192 don't match. Disable this reload so we don't crash in final. */
5193 error_for_asm (insn,
5194 "`asm' operand constraint incompatible with operand size");
5197 reload_reg_rtx[r] = 0;
5198 reload_optional[r] = 1;
5199 reload_secondary_p[r] = 1;
5204 /* Assign hard reg targets for the pseudo-registers we must reload
5205 into hard regs for this insn.
5206 Also output the instructions to copy them in and out of the hard regs.
5208 For machines with register classes, we are responsible for
5209 finding a reload reg in the proper class. */
5212 choose_reload_regs (insn, avoid_return_reg)
5214 rtx avoid_return_reg;
5217 int max_group_size = 1;
5218 enum reg_class group_class = NO_REGS;
5221 rtx save_reload_reg_rtx[MAX_RELOADS];
5222 char save_reload_inherited[MAX_RELOADS];
5223 rtx save_reload_inheritance_insn[MAX_RELOADS];
5224 rtx save_reload_override_in[MAX_RELOADS];
5225 int save_reload_spill_index[MAX_RELOADS];
5226 HARD_REG_SET save_reload_reg_used;
5227 HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
5228 HARD_REG_SET save_reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
5229 HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
5230 HARD_REG_SET save_reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
5231 HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS];
5232 HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS];
5233 HARD_REG_SET save_reload_reg_used_in_op_addr;
5234 HARD_REG_SET save_reload_reg_used_in_op_addr_reload;
5235 HARD_REG_SET save_reload_reg_used_in_insn;
5236 HARD_REG_SET save_reload_reg_used_in_other_addr;
5237 HARD_REG_SET save_reload_reg_used_at_all;
5239 bzero (reload_inherited, MAX_RELOADS);
5240 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5241 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5243 CLEAR_HARD_REG_SET (reload_reg_used);
5244 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5245 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5246 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5247 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5248 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5250 for (i = 0; i < reload_n_operands; i++)
5252 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5253 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5254 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5255 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5256 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5257 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5260 /* Don't bother with avoiding the return reg
5261 if we have no mandatory reload that could use it. */
5262 if (SMALL_REGISTER_CLASSES && avoid_return_reg)
5265 int regno = REGNO (avoid_return_reg);
5267 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
5270 for (r = regno; r < regno + nregs; r++)
5271 if (spill_reg_order[r] >= 0)
5272 for (j = 0; j < n_reloads; j++)
5273 if (!reload_optional[j] && reload_reg_rtx[j] == 0
5274 && (reload_in[j] != 0 || reload_out[j] != 0
5275 || reload_secondary_p[j])
5277 TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[j]], r))
5280 avoid_return_reg = 0;
5283 #if 0 /* Not needed, now that we can always retry without inheritance. */
5284 /* See if we have more mandatory reloads than spill regs.
5285 If so, then we cannot risk optimizations that could prevent
5286 reloads from sharing one spill register.
5288 Since we will try finding a better register than reload_reg_rtx
5289 unless it is equal to reload_in or reload_out, count such reloads. */
5292 int tem = SMALL_REGISTER_CLASSES? (avoid_return_reg != 0): 0;
5293 for (j = 0; j < n_reloads; j++)
5294 if (! reload_optional[j]
5295 && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
5296 && (reload_reg_rtx[j] == 0
5297 || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
5298 && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
5305 /* Don't use the subroutine call return reg for a reload
5306 if we are supposed to avoid it. */
5307 if (SMALL_REGISTER_CLASSES && avoid_return_reg)
5309 int regno = REGNO (avoid_return_reg);
5311 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
5314 for (r = regno; r < regno + nregs; r++)
5315 if (spill_reg_order[r] >= 0)
5316 SET_HARD_REG_BIT (reload_reg_used, r);
5319 /* In order to be certain of getting the registers we need,
5320 we must sort the reloads into order of increasing register class.
5321 Then our grabbing of reload registers will parallel the process
5322 that provided the reload registers.
5324 Also note whether any of the reloads wants a consecutive group of regs.
5325 If so, record the maximum size of the group desired and what
5326 register class contains all the groups needed by this insn. */
5328 for (j = 0; j < n_reloads; j++)
5330 reload_order[j] = j;
5331 reload_spill_index[j] = -1;
5334 = (reload_inmode[j] == VOIDmode
5335 || (GET_MODE_SIZE (reload_outmode[j])
5336 > GET_MODE_SIZE (reload_inmode[j])))
5337 ? reload_outmode[j] : reload_inmode[j];
5339 reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
5341 if (reload_nregs[j] > 1)
5343 max_group_size = MAX (reload_nregs[j], max_group_size);
5344 group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
5347 /* If we have already decided to use a certain register,
5348 don't use it in another way. */
5349 if (reload_reg_rtx[j])
5350 mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j],
5351 reload_when_needed[j], reload_mode[j]);
5355 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5357 bcopy ((char *) reload_reg_rtx, (char *) save_reload_reg_rtx,
5358 sizeof reload_reg_rtx);
5359 bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
5360 bcopy ((char *) reload_inheritance_insn,
5361 (char *) save_reload_inheritance_insn,
5362 sizeof reload_inheritance_insn);
5363 bcopy ((char *) reload_override_in, (char *) save_reload_override_in,
5364 sizeof reload_override_in);
5365 bcopy ((char *) reload_spill_index, (char *) save_reload_spill_index,
5366 sizeof reload_spill_index);
5367 COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
5368 COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
5369 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
5370 reload_reg_used_in_op_addr);
5372 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr_reload,
5373 reload_reg_used_in_op_addr_reload);
5375 COPY_HARD_REG_SET (save_reload_reg_used_in_insn,
5376 reload_reg_used_in_insn);
5377 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr,
5378 reload_reg_used_in_other_addr);
5380 for (i = 0; i < reload_n_operands; i++)
5382 COPY_HARD_REG_SET (save_reload_reg_used_in_output[i],
5383 reload_reg_used_in_output[i]);
5384 COPY_HARD_REG_SET (save_reload_reg_used_in_input[i],
5385 reload_reg_used_in_input[i]);
5386 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i],
5387 reload_reg_used_in_input_addr[i]);
5388 COPY_HARD_REG_SET (save_reload_reg_used_in_inpaddr_addr[i],
5389 reload_reg_used_in_inpaddr_addr[i]);
5390 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i],
5391 reload_reg_used_in_output_addr[i]);
5392 COPY_HARD_REG_SET (save_reload_reg_used_in_outaddr_addr[i],
5393 reload_reg_used_in_outaddr_addr[i]);
5396 /* If -O, try first with inheritance, then turning it off.
5397 If not -O, don't do inheritance.
5398 Using inheritance when not optimizing leads to paradoxes
5399 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5400 because one side of the comparison might be inherited. */
5402 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5404 /* Process the reloads in order of preference just found.
5405 Beyond this point, subregs can be found in reload_reg_rtx.
5407 This used to look for an existing reloaded home for all
5408 of the reloads, and only then perform any new reloads.
5409 But that could lose if the reloads were done out of reg-class order
5410 because a later reload with a looser constraint might have an old
5411 home in a register needed by an earlier reload with a tighter constraint.
5413 To solve this, we make two passes over the reloads, in the order
5414 described above. In the first pass we try to inherit a reload
5415 from a previous insn. If there is a later reload that needs a
5416 class that is a proper subset of the class being processed, we must
5417 also allocate a spill register during the first pass.
5419 Then make a second pass over the reloads to allocate any reloads
5420 that haven't been given registers yet. */
5422 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5424 for (j = 0; j < n_reloads; j++)
5426 register int r = reload_order[j];
5428 /* Ignore reloads that got marked inoperative. */
5429 if (reload_out[r] == 0 && reload_in[r] == 0
5430 && ! reload_secondary_p[r])
5433 /* If find_reloads chose a to use reload_in or reload_out as a reload
5434 register, we don't need to chose one. Otherwise, try even if it
5435 found one since we might save an insn if we find the value lying
5437 if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
5438 && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
5439 || rtx_equal_p (reload_out[r], reload_reg_rtx[r])))
5442 #if 0 /* No longer needed for correct operation.
5443 It might give better code, or might not; worth an experiment? */
5444 /* If this is an optional reload, we can't inherit from earlier insns
5445 until we are sure that any non-optional reloads have been allocated.
5446 The following code takes advantage of the fact that optional reloads
5447 are at the end of reload_order. */
5448 if (reload_optional[r] != 0)
5449 for (i = 0; i < j; i++)
5450 if ((reload_out[reload_order[i]] != 0
5451 || reload_in[reload_order[i]] != 0
5452 || reload_secondary_p[reload_order[i]])
5453 && ! reload_optional[reload_order[i]]
5454 && reload_reg_rtx[reload_order[i]] == 0)
5455 allocate_reload_reg (reload_order[i], insn, 0, inheritance);
5458 /* First see if this pseudo is already available as reloaded
5459 for a previous insn. We cannot try to inherit for reloads
5460 that are smaller than the maximum number of registers needed
5461 for groups unless the register we would allocate cannot be used
5464 We could check here to see if this is a secondary reload for
5465 an object that is already in a register of the desired class.
5466 This would avoid the need for the secondary reload register.
5467 But this is complex because we can't easily determine what
5468 objects might want to be loaded via this reload. So let a
5469 register be allocated here. In `emit_reload_insns' we suppress
5470 one of the loads in the case described above. */
5474 register int regno = -1;
5475 enum machine_mode mode;
5476 rtx in, use_insn = 0;
5478 if (reload_in[r] == 0)
5480 else if (GET_CODE (reload_in[r]) == REG)
5482 regno = REGNO (reload_in[r]);
5483 mode = GET_MODE (reload_in[r]);
5485 else if (GET_CODE (reload_in_reg[r]) == REG)
5487 regno = REGNO (reload_in_reg[r]);
5488 mode = GET_MODE (reload_in_reg[r]);
5490 else if (GET_CODE (reload_in[r]) == MEM)
5492 rtx prev = prev_nonnote_insn (insn), note;
5494 if (prev && GET_CODE (prev) == INSN
5495 && GET_CODE (PATTERN (prev)) == USE
5496 && GET_CODE (XEXP (PATTERN (prev), 0)) == REG
5497 && (REGNO (XEXP (PATTERN (prev), 0))
5498 >= FIRST_PSEUDO_REGISTER)
5499 && (note = find_reg_note (prev, REG_EQUAL, NULL_RTX))
5500 && GET_CODE (XEXP (note, 0)) == MEM)
5502 rtx addr = XEXP (XEXP (note, 0), 0);
5504 = (GET_MODE_SIZE (GET_MODE (addr))
5505 - GET_MODE_SIZE (GET_MODE (reload_in[r])));
5507 && rtx_equal_p ((BYTES_BIG_ENDIAN
5508 ? plus_constant (addr, size_diff)
5510 XEXP (reload_in[r], 0)))
5512 regno = REGNO (XEXP (PATTERN (prev), 0));
5513 mode = GET_MODE (reload_in[r]);
5519 /* This won't work, since REGNO can be a pseudo reg number.
5520 Also, it takes much more hair to keep track of all the things
5521 that can invalidate an inherited reload of part of a pseudoreg. */
5522 else if (GET_CODE (reload_in[r]) == SUBREG
5523 && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
5524 regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
5527 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5529 i = REGNO (reg_last_reload_reg[regno]);
5531 if (reg_reloaded_contents[i] == regno
5532 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5533 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
5534 >= GET_MODE_SIZE (mode))
5535 && HARD_REGNO_MODE_OK (i, reload_mode[r])
5536 && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5538 && (reload_nregs[r] == max_group_size
5539 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5541 && reload_reg_free_p (i, reload_opnum[r],
5542 reload_when_needed[r])
5543 && reload_reg_free_before_p (i, reload_opnum[r],
5544 reload_when_needed[r]))
5546 /* If a group is needed, verify that all the subsequent
5547 registers still have their values intact. */
5549 = HARD_REGNO_NREGS (i, reload_mode[r]);
5552 for (k = 1; k < nr; k++)
5553 if (reg_reloaded_contents[i + k] != regno
5554 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5561 /* We found a register that contains the
5562 value we need. If this register is the
5563 same as an `earlyclobber' operand of the
5564 current insn, just mark it as a place to
5565 reload from since we can't use it as the
5566 reload register itself. */
5568 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5569 if (reg_overlap_mentioned_for_reload_p
5570 (reg_last_reload_reg[regno],
5571 reload_earlyclobbers[i1]))
5574 if (i1 != n_earlyclobbers
5575 /* Don't use it if we'd clobber a pseudo reg. */
5576 || (spill_reg_order[i] < 0
5578 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5579 /* Don't really use the inherited spill reg
5580 if we need it wider than we've got it. */
5581 || (GET_MODE_SIZE (reload_mode[r])
5582 > GET_MODE_SIZE (mode)))
5583 reload_override_in[r] = reg_last_reload_reg[regno];
5587 /* We can use this as a reload reg. */
5588 /* Mark the register as in use for this part of
5590 mark_reload_reg_in_use (i,
5592 reload_when_needed[r],
5594 reload_reg_rtx[r] = reg_last_reload_reg[regno];
5595 reload_inherited[r] = 1;
5596 reload_inheritance_insn[r]
5597 = reg_reloaded_insn[i];
5598 reload_spill_index[r] = i;
5599 for (k = 0; k < nr; k++)
5600 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5608 /* Here's another way to see if the value is already lying around. */
5610 && reload_in[r] != 0
5611 && ! reload_inherited[r]
5612 && reload_out[r] == 0
5613 && (CONSTANT_P (reload_in[r])
5614 || GET_CODE (reload_in[r]) == PLUS
5615 || GET_CODE (reload_in[r]) == REG
5616 || GET_CODE (reload_in[r]) == MEM)
5617 && (reload_nregs[r] == max_group_size
5618 || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
5621 = find_equiv_reg (reload_in[r], insn, reload_reg_class[r],
5622 -1, NULL_PTR, 0, reload_mode[r]);
5627 if (GET_CODE (equiv) == REG)
5628 regno = REGNO (equiv);
5629 else if (GET_CODE (equiv) == SUBREG)
5631 /* This must be a SUBREG of a hard register.
5632 Make a new REG since this might be used in an
5633 address and not all machines support SUBREGs
5635 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5636 equiv = gen_rtx_REG (reload_mode[r], regno);
5642 /* If we found a spill reg, reject it unless it is free
5643 and of the desired class. */
5645 && ((spill_reg_order[regno] >= 0
5646 && ! reload_reg_free_before_p (regno, reload_opnum[r],
5647 reload_when_needed[r]))
5648 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5652 if (equiv != 0 && TEST_HARD_REG_BIT (reload_reg_used_at_all, regno))
5655 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5658 /* We found a register that contains the value we need.
5659 If this register is the same as an `earlyclobber' operand
5660 of the current insn, just mark it as a place to reload from
5661 since we can't use it as the reload register itself. */
5664 for (i = 0; i < n_earlyclobbers; i++)
5665 if (reg_overlap_mentioned_for_reload_p (equiv,
5666 reload_earlyclobbers[i]))
5668 reload_override_in[r] = equiv;
5673 /* JRV: If the equiv register we have found is
5674 explicitly clobbered in the current insn, mark but
5675 don't use, as above. */
5677 if (equiv != 0 && regno_clobbered_p (regno, insn))
5679 reload_override_in[r] = equiv;
5683 /* If we found an equivalent reg, say no code need be generated
5684 to load it, and use it as our reload reg. */
5685 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5687 int nr = HARD_REGNO_NREGS (regno, reload_mode[r]);
5689 reload_reg_rtx[r] = equiv;
5690 reload_inherited[r] = 1;
5692 /* If any of the hard registers in EQUIV are spill
5693 registers, mark them as in use for this insn. */
5694 for (k = 0; k < nr; k++)
5696 i = spill_reg_order[regno + k];
5699 mark_reload_reg_in_use (regno, reload_opnum[r],
5700 reload_when_needed[r],
5702 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5709 /* If we found a register to use already, or if this is an optional
5710 reload, we are done. */
5711 if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
5714 #if 0 /* No longer needed for correct operation. Might or might not
5715 give better code on the average. Want to experiment? */
5717 /* See if there is a later reload that has a class different from our
5718 class that intersects our class or that requires less register
5719 than our reload. If so, we must allocate a register to this
5720 reload now, since that reload might inherit a previous reload
5721 and take the only available register in our class. Don't do this
5722 for optional reloads since they will force all previous reloads
5723 to be allocated. Also don't do this for reloads that have been
5726 for (i = j + 1; i < n_reloads; i++)
5728 int s = reload_order[i];
5730 if ((reload_in[s] == 0 && reload_out[s] == 0
5731 && ! reload_secondary_p[s])
5732 || reload_optional[s])
5735 if ((reload_reg_class[s] != reload_reg_class[r]
5736 && reg_classes_intersect_p (reload_reg_class[r],
5737 reload_reg_class[s]))
5738 || reload_nregs[s] < reload_nregs[r])
5745 allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance);
5749 /* Now allocate reload registers for anything non-optional that
5750 didn't get one yet. */
5751 for (j = 0; j < n_reloads; j++)
5753 register int r = reload_order[j];
5755 /* Ignore reloads that got marked inoperative. */
5756 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
5759 /* Skip reloads that already have a register allocated or are
5761 if (reload_reg_rtx[r] != 0 || reload_optional[r])
5764 if (! allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance))
5768 /* If that loop got all the way, we have won. */
5773 /* Loop around and try without any inheritance. */
5774 /* First undo everything done by the failed attempt
5775 to allocate with inheritance. */
5776 bcopy ((char *) save_reload_reg_rtx, (char *) reload_reg_rtx,
5777 sizeof reload_reg_rtx);
5778 bcopy ((char *) save_reload_inherited, (char *) reload_inherited,
5779 sizeof reload_inherited);
5780 bcopy ((char *) save_reload_inheritance_insn,
5781 (char *) reload_inheritance_insn,
5782 sizeof reload_inheritance_insn);
5783 bcopy ((char *) save_reload_override_in, (char *) reload_override_in,
5784 sizeof reload_override_in);
5785 bcopy ((char *) save_reload_spill_index, (char *) reload_spill_index,
5786 sizeof reload_spill_index);
5787 COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
5788 COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
5789 COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
5790 save_reload_reg_used_in_op_addr);
5791 COPY_HARD_REG_SET (reload_reg_used_in_op_addr_reload,
5792 save_reload_reg_used_in_op_addr_reload);
5793 COPY_HARD_REG_SET (reload_reg_used_in_insn,
5794 save_reload_reg_used_in_insn);
5795 COPY_HARD_REG_SET (reload_reg_used_in_other_addr,
5796 save_reload_reg_used_in_other_addr);
5798 for (i = 0; i < reload_n_operands; i++)
5800 COPY_HARD_REG_SET (reload_reg_used_in_input[i],
5801 save_reload_reg_used_in_input[i]);
5802 COPY_HARD_REG_SET (reload_reg_used_in_output[i],
5803 save_reload_reg_used_in_output[i]);
5804 COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i],
5805 save_reload_reg_used_in_input_addr[i]);
5806 COPY_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i],
5807 save_reload_reg_used_in_inpaddr_addr[i]);
5808 COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i],
5809 save_reload_reg_used_in_output_addr[i]);
5810 COPY_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i],
5811 save_reload_reg_used_in_outaddr_addr[i]);
5815 /* If we thought we could inherit a reload, because it seemed that
5816 nothing else wanted the same reload register earlier in the insn,
5817 verify that assumption, now that all reloads have been assigned. */
5819 for (j = 0; j < n_reloads; j++)
5821 register int r = reload_order[j];
5823 if (reload_inherited[r] && reload_reg_rtx[r] != 0
5824 && ! reload_reg_free_before_p (true_regnum (reload_reg_rtx[r]),
5826 reload_when_needed[r]))
5827 reload_inherited[r] = 0;
5829 /* If we found a better place to reload from,
5830 validate it in the same fashion, if it is a reload reg. */
5831 if (reload_override_in[r]
5832 && (GET_CODE (reload_override_in[r]) == REG
5833 || GET_CODE (reload_override_in[r]) == SUBREG))
5835 int regno = true_regnum (reload_override_in[r]);
5836 if (spill_reg_order[regno] >= 0
5837 && ! reload_reg_free_before_p (regno, reload_opnum[r],
5838 reload_when_needed[r]))
5839 reload_override_in[r] = 0;
5843 /* Now that reload_override_in is known valid,
5844 actually override reload_in. */
5845 for (j = 0; j < n_reloads; j++)
5846 if (reload_override_in[j])
5847 reload_in[j] = reload_override_in[j];
5849 /* If this reload won't be done because it has been cancelled or is
5850 optional and not inherited, clear reload_reg_rtx so other
5851 routines (such as subst_reloads) don't get confused. */
5852 for (j = 0; j < n_reloads; j++)
5853 if (reload_reg_rtx[j] != 0
5854 && ((reload_optional[j] && ! reload_inherited[j])
5855 || (reload_in[j] == 0 && reload_out[j] == 0
5856 && ! reload_secondary_p[j])))
5858 int regno = true_regnum (reload_reg_rtx[j]);
5860 if (spill_reg_order[regno] >= 0)
5861 clear_reload_reg_in_use (regno, reload_opnum[j],
5862 reload_when_needed[j], reload_mode[j]);
5863 reload_reg_rtx[j] = 0;
5866 /* Record which pseudos and which spill regs have output reloads. */
5867 for (j = 0; j < n_reloads; j++)
5869 register int r = reload_order[j];
5871 i = reload_spill_index[r];
5873 /* I is nonneg if this reload uses a register.
5874 If reload_reg_rtx[r] is 0, this is an optional reload
5875 that we opted to ignore. */
5876 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG
5877 && reload_reg_rtx[r] != 0)
5879 register int nregno = REGNO (reload_out[r]);
5882 if (nregno < FIRST_PSEUDO_REGISTER)
5883 nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
5886 reg_has_output_reload[nregno + nr] = 1;
5890 nr = HARD_REGNO_NREGS (i, reload_mode[r]);
5892 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5895 if (reload_when_needed[r] != RELOAD_OTHER
5896 && reload_when_needed[r] != RELOAD_FOR_OUTPUT
5897 && reload_when_needed[r] != RELOAD_FOR_INSN)
5903 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5904 reloads of the same item for fear that we might not have enough reload
5905 registers. However, normally they will get the same reload register
5906 and hence actually need not be loaded twice.
5908 Here we check for the most common case of this phenomenon: when we have
5909 a number of reloads for the same object, each of which were allocated
5910 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5911 reload, and is not modified in the insn itself. If we find such,
5912 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5913 This will not increase the number of spill registers needed and will
5914 prevent redundant code. */
5917 merge_assigned_reloads (insn)
5922 /* Scan all the reloads looking for ones that only load values and
5923 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5924 assigned and not modified by INSN. */
5926 for (i = 0; i < n_reloads; i++)
5928 if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER
5929 || reload_out[i] != 0 || reload_reg_rtx[i] == 0
5930 || reg_set_p (reload_reg_rtx[i], insn))
5933 /* Look at all other reloads. Ensure that the only use of this
5934 reload_reg_rtx is in a reload that just loads the same value
5935 as we do. Note that any secondary reloads must be of the identical
5936 class since the values, modes, and result registers are the
5937 same, so we need not do anything with any secondary reloads. */
5939 for (j = 0; j < n_reloads; j++)
5941 if (i == j || reload_reg_rtx[j] == 0
5942 || ! reg_overlap_mentioned_p (reload_reg_rtx[j],
5946 /* If the reload regs aren't exactly the same (e.g, different modes)
5947 or if the values are different, we can't merge anything with this
5950 if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
5951 || reload_out[j] != 0 || reload_in[j] == 0
5952 || ! rtx_equal_p (reload_in[i], reload_in[j]))
5956 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5957 we, in fact, found any matching reloads. */
5961 for (j = 0; j < n_reloads; j++)
5962 if (i != j && reload_reg_rtx[j] != 0
5963 && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j]))
5965 reload_when_needed[i] = RELOAD_OTHER;
5967 transfer_replacements (i, j);
5970 /* If this is now RELOAD_OTHER, look for any reloads that load
5971 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5972 if they were for inputs, RELOAD_OTHER for outputs. Note that
5973 this test is equivalent to looking for reloads for this operand
5976 if (reload_when_needed[i] == RELOAD_OTHER)
5977 for (j = 0; j < n_reloads; j++)
5978 if (reload_in[j] != 0
5979 && reload_when_needed[i] != RELOAD_OTHER
5980 && reg_overlap_mentioned_for_reload_p (reload_in[j],
5982 reload_when_needed[j]
5983 = ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
5984 || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS)
5985 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
5991 /* Output insns to reload values in and out of the chosen reload regs. */
5994 emit_reload_insns (insn)
5998 rtx input_reload_insns[MAX_RECOG_OPERANDS];
5999 rtx other_input_address_reload_insns = 0;
6000 rtx other_input_reload_insns = 0;
6001 rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6002 rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6003 rtx output_reload_insns[MAX_RECOG_OPERANDS];
6004 rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6005 rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6006 rtx operand_reload_insns = 0;
6007 rtx other_operand_reload_insns = 0;
6008 rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6009 rtx following_insn = NEXT_INSN (insn);
6010 rtx before_insn = insn;
6012 /* Values to be put in spill_reg_store are put here first. */
6013 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6014 HARD_REG_SET reg_reloaded_died;
6016 CLEAR_HARD_REG_SET (reg_reloaded_died);
6018 for (j = 0; j < reload_n_operands; j++)
6019 input_reload_insns[j] = input_address_reload_insns[j]
6020 = inpaddr_address_reload_insns[j]
6021 = output_reload_insns[j] = output_address_reload_insns[j]
6022 = outaddr_address_reload_insns[j]
6023 = other_output_reload_insns[j] = 0;
6025 /* Now output the instructions to copy the data into and out of the
6026 reload registers. Do these in the order that the reloads were reported,
6027 since reloads of base and index registers precede reloads of operands
6028 and the operands may need the base and index registers reloaded. */
6030 for (j = 0; j < n_reloads; j++)
6033 rtx oldequiv_reg = 0;
6034 rtx this_reload_insn = 0;
6035 int expect_occurrences = 1;
6037 if (reload_spill_index[j] >= 0)
6038 new_spill_reg_store[reload_spill_index[j]] = 0;
6041 if (old != 0 && ! reload_inherited[j]
6042 && ! rtx_equal_p (reload_reg_rtx[j], old)
6043 && reload_reg_rtx[j] != 0)
6045 register rtx reloadreg = reload_reg_rtx[j];
6047 enum machine_mode mode;
6050 /* Determine the mode to reload in.
6051 This is very tricky because we have three to choose from.
6052 There is the mode the insn operand wants (reload_inmode[J]).
6053 There is the mode of the reload register RELOADREG.
6054 There is the intrinsic mode of the operand, which we could find
6055 by stripping some SUBREGs.
6056 It turns out that RELOADREG's mode is irrelevant:
6057 we can change that arbitrarily.
6059 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6060 then the reload reg may not support QImode moves, so use SImode.
6061 If foo is in memory due to spilling a pseudo reg, this is safe,
6062 because the QImode value is in the least significant part of a
6063 slot big enough for a SImode. If foo is some other sort of
6064 memory reference, then it is impossible to reload this case,
6065 so previous passes had better make sure this never happens.
6067 Then consider a one-word union which has SImode and one of its
6068 members is a float, being fetched as (SUBREG:SF union:SI).
6069 We must fetch that as SFmode because we could be loading into
6070 a float-only register. In this case OLD's mode is correct.
6072 Consider an immediate integer: it has VOIDmode. Here we need
6073 to get a mode from something else.
6075 In some cases, there is a fourth mode, the operand's
6076 containing mode. If the insn specifies a containing mode for
6077 this operand, it overrides all others.
6079 I am not sure whether the algorithm here is always right,
6080 but it does the right things in those cases. */
6082 mode = GET_MODE (old);
6083 if (mode == VOIDmode)
6084 mode = reload_inmode[j];
6086 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6087 /* If we need a secondary register for this operation, see if
6088 the value is already in a register in that class. Don't
6089 do this if the secondary register will be used as a scratch
6092 if (reload_secondary_in_reload[j] >= 0
6093 && reload_secondary_in_icode[j] == CODE_FOR_nothing
6096 = find_equiv_reg (old, insn,
6097 reload_reg_class[reload_secondary_in_reload[j]],
6098 -1, NULL_PTR, 0, mode);
6101 /* If reloading from memory, see if there is a register
6102 that already holds the same value. If so, reload from there.
6103 We can pass 0 as the reload_reg_p argument because
6104 any other reload has either already been emitted,
6105 in which case find_equiv_reg will see the reload-insn,
6106 or has yet to be emitted, in which case it doesn't matter
6107 because we will use this equiv reg right away. */
6109 if (oldequiv == 0 && optimize
6110 && (GET_CODE (old) == MEM
6111 || (GET_CODE (old) == REG
6112 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6113 && reg_renumber[REGNO (old)] < 0)))
6114 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6115 -1, NULL_PTR, 0, mode);
6119 int regno = true_regnum (oldequiv);
6121 /* If OLDEQUIV is a spill register, don't use it for this
6122 if any other reload needs it at an earlier stage of this insn
6123 or at this stage. */
6124 if (spill_reg_order[regno] >= 0
6125 && (! reload_reg_free_p (regno, reload_opnum[j],
6126 reload_when_needed[j])
6127 || ! reload_reg_free_before_p (regno, reload_opnum[j],
6128 reload_when_needed[j])))
6131 /* If OLDEQUIV is not a spill register,
6132 don't use it if any other reload wants it. */
6133 if (spill_reg_order[regno] < 0)
6136 for (k = 0; k < n_reloads; k++)
6137 if (reload_reg_rtx[k] != 0 && k != j
6138 && reg_overlap_mentioned_for_reload_p (reload_reg_rtx[k],
6146 /* If it is no cheaper to copy from OLDEQUIV into the
6147 reload register than it would be to move from memory,
6148 don't use it. Likewise, if we need a secondary register
6152 && ((REGNO_REG_CLASS (regno) != reload_reg_class[j]
6153 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
6154 reload_reg_class[j])
6155 >= MEMORY_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6157 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6158 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6162 #ifdef SECONDARY_MEMORY_NEEDED
6163 || SECONDARY_MEMORY_NEEDED (reload_reg_class[j],
6164 REGNO_REG_CLASS (regno),
6173 else if (GET_CODE (oldequiv) == REG)
6174 oldequiv_reg = oldequiv;
6175 else if (GET_CODE (oldequiv) == SUBREG)
6176 oldequiv_reg = SUBREG_REG (oldequiv);
6178 /* If we are reloading from a register that was recently stored in
6179 with an output-reload, see if we can prove there was
6180 actually no need to store the old value in it. */
6182 if (optimize && GET_CODE (oldequiv) == REG
6183 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6184 && spill_reg_store[REGNO (oldequiv)]
6185 && GET_CODE (old) == REG && dead_or_set_p (insn, old)
6186 /* This is unsafe if operand occurs more than once in current
6187 insn. Perhaps some occurrences weren't reloaded. */
6188 && count_occurrences (PATTERN (insn), old) == 1)
6189 delete_output_reload (insn, j, spill_reg_store[REGNO (oldequiv)]);
6191 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6192 then load RELOADREG from OLDEQUIV. Note that we cannot use
6193 gen_lowpart_common since it can do the wrong thing when
6194 RELOADREG has a multi-word mode. Note that RELOADREG
6195 must always be a REG here. */
6197 if (GET_MODE (reloadreg) != mode)
6198 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6199 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6200 oldequiv = SUBREG_REG (oldequiv);
6201 if (GET_MODE (oldequiv) != VOIDmode
6202 && mode != GET_MODE (oldequiv))
6203 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6205 /* Switch to the right place to emit the reload insns. */
6206 switch (reload_when_needed[j])
6209 where = &other_input_reload_insns;
6211 case RELOAD_FOR_INPUT:
6212 where = &input_reload_insns[reload_opnum[j]];
6214 case RELOAD_FOR_INPUT_ADDRESS:
6215 where = &input_address_reload_insns[reload_opnum[j]];
6217 case RELOAD_FOR_INPADDR_ADDRESS:
6218 where = &inpaddr_address_reload_insns[reload_opnum[j]];
6220 case RELOAD_FOR_OUTPUT_ADDRESS:
6221 where = &output_address_reload_insns[reload_opnum[j]];
6223 case RELOAD_FOR_OUTADDR_ADDRESS:
6224 where = &outaddr_address_reload_insns[reload_opnum[j]];
6226 case RELOAD_FOR_OPERAND_ADDRESS:
6227 where = &operand_reload_insns;
6229 case RELOAD_FOR_OPADDR_ADDR:
6230 where = &other_operand_reload_insns;
6232 case RELOAD_FOR_OTHER_ADDRESS:
6233 where = &other_input_address_reload_insns;
6239 push_to_sequence (*where);
6242 /* Auto-increment addresses must be reloaded in a special way. */
6243 if (GET_CODE (oldequiv) == POST_INC
6244 || GET_CODE (oldequiv) == POST_DEC
6245 || GET_CODE (oldequiv) == PRE_INC
6246 || GET_CODE (oldequiv) == PRE_DEC)
6248 /* We are not going to bother supporting the case where a
6249 incremented register can't be copied directly from
6250 OLDEQUIV since this seems highly unlikely. */
6251 if (reload_secondary_in_reload[j] >= 0)
6253 /* Prevent normal processing of this reload. */
6255 /* Output a special code sequence for this case. */
6256 inc_for_reload (reloadreg, oldequiv, reload_inc[j]);
6259 /* If we are reloading a pseudo-register that was set by the previous
6260 insn, see if we can get rid of that pseudo-register entirely
6261 by redirecting the previous insn into our reload register. */
6263 else if (optimize && GET_CODE (old) == REG
6264 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6265 && dead_or_set_p (insn, old)
6266 /* This is unsafe if some other reload
6267 uses the same reg first. */
6268 && reload_reg_free_before_p (REGNO (reloadreg),
6270 reload_when_needed[j]))
6272 rtx temp = PREV_INSN (insn);
6273 while (temp && GET_CODE (temp) == NOTE)
6274 temp = PREV_INSN (temp);
6276 && GET_CODE (temp) == INSN
6277 && GET_CODE (PATTERN (temp)) == SET
6278 && SET_DEST (PATTERN (temp)) == old
6279 /* Make sure we can access insn_operand_constraint. */
6280 && asm_noperands (PATTERN (temp)) < 0
6281 /* This is unsafe if prev insn rejects our reload reg. */
6282 && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
6284 /* This is unsafe if operand occurs more than once in current
6285 insn. Perhaps some occurrences aren't reloaded. */
6286 && count_occurrences (PATTERN (insn), old) == 1
6287 /* Don't risk splitting a matching pair of operands. */
6288 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6290 /* Store into the reload register instead of the pseudo. */
6291 SET_DEST (PATTERN (temp)) = reloadreg;
6292 /* If these are the only uses of the pseudo reg,
6293 pretend for GDB it lives in the reload reg we used. */
6294 if (REG_N_DEATHS (REGNO (old)) == 1
6295 && REG_N_SETS (REGNO (old)) == 1)
6297 reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
6298 alter_reg (REGNO (old), -1);
6304 /* We can't do that, so output an insn to load RELOADREG. */
6308 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6309 rtx second_reload_reg = 0;
6310 enum insn_code icode;
6312 /* If we have a secondary reload, pick up the secondary register
6313 and icode, if any. If OLDEQUIV and OLD are different or
6314 if this is an in-out reload, recompute whether or not we
6315 still need a secondary register and what the icode should
6316 be. If we still need a secondary register and the class or
6317 icode is different, go back to reloading from OLD if using
6318 OLDEQUIV means that we got the wrong type of register. We
6319 cannot have different class or icode due to an in-out reload
6320 because we don't make such reloads when both the input and
6321 output need secondary reload registers. */
6323 if (reload_secondary_in_reload[j] >= 0)
6325 int secondary_reload = reload_secondary_in_reload[j];
6326 rtx real_oldequiv = oldequiv;
6329 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6330 and similarly for OLD.
6331 See comments in get_secondary_reload in reload.c. */
6332 if (GET_CODE (oldequiv) == REG
6333 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6334 && reg_equiv_mem[REGNO (oldequiv)] != 0)
6335 real_oldequiv = reg_equiv_mem[REGNO (oldequiv)];
6337 if (GET_CODE (old) == REG
6338 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6339 && reg_equiv_mem[REGNO (old)] != 0)
6340 real_old = reg_equiv_mem[REGNO (old)];
6342 second_reload_reg = reload_reg_rtx[secondary_reload];
6343 icode = reload_secondary_in_icode[j];
6345 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6346 || (reload_in[j] != 0 && reload_out[j] != 0))
6348 enum reg_class new_class
6349 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6350 mode, real_oldequiv);
6352 if (new_class == NO_REGS)
6353 second_reload_reg = 0;
6356 enum insn_code new_icode;
6357 enum machine_mode new_mode;
6359 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6360 REGNO (second_reload_reg)))
6361 oldequiv = old, real_oldequiv = real_old;
6364 new_icode = reload_in_optab[(int) mode];
6365 if (new_icode != CODE_FOR_nothing
6366 && ((insn_operand_predicate[(int) new_icode][0]
6367 && ! ((*insn_operand_predicate[(int) new_icode][0])
6369 || (insn_operand_predicate[(int) new_icode][1]
6370 && ! ((*insn_operand_predicate[(int) new_icode][1])
6371 (real_oldequiv, mode)))))
6372 new_icode = CODE_FOR_nothing;
6374 if (new_icode == CODE_FOR_nothing)
6377 new_mode = insn_operand_mode[(int) new_icode][2];
6379 if (GET_MODE (second_reload_reg) != new_mode)
6381 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6383 oldequiv = old, real_oldequiv = real_old;
6386 = gen_rtx_REG (new_mode,
6387 REGNO (second_reload_reg));
6393 /* If we still need a secondary reload register, check
6394 to see if it is being used as a scratch or intermediate
6395 register and generate code appropriately. If we need
6396 a scratch register, use REAL_OLDEQUIV since the form of
6397 the insn may depend on the actual address if it is
6400 if (second_reload_reg)
6402 if (icode != CODE_FOR_nothing)
6404 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6405 second_reload_reg));
6410 /* See if we need a scratch register to load the
6411 intermediate register (a tertiary reload). */
6412 enum insn_code tertiary_icode
6413 = reload_secondary_in_icode[secondary_reload];
6415 if (tertiary_icode != CODE_FOR_nothing)
6417 rtx third_reload_reg
6418 = reload_reg_rtx[reload_secondary_in_reload[secondary_reload]];
6420 emit_insn ((GEN_FCN (tertiary_icode)
6421 (second_reload_reg, real_oldequiv,
6422 third_reload_reg)));
6425 gen_reload (second_reload_reg, oldequiv,
6427 reload_when_needed[j]);
6429 oldequiv = second_reload_reg;
6435 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6436 gen_reload (reloadreg, oldequiv, reload_opnum[j],
6437 reload_when_needed[j]);
6439 #if defined(SECONDARY_INPUT_RELOAD_CLASS) && defined(PRESERVE_DEATH_INFO_REGNO_P)
6440 /* We may have to make a REG_DEAD note for the secondary reload
6441 register in the insns we just made. Find the last insn that
6442 mentioned the register. */
6443 if (! special && second_reload_reg
6444 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reload_reg)))
6448 for (prev = get_last_insn (); prev;
6449 prev = PREV_INSN (prev))
6450 if (GET_RTX_CLASS (GET_CODE (prev) == 'i')
6451 && reg_overlap_mentioned_for_reload_p (second_reload_reg,
6454 REG_NOTES (prev) = gen_rtx_EXPR_LIST (REG_DEAD,
6463 this_reload_insn = get_last_insn ();
6464 /* End this sequence. */
6465 *where = get_insns ();
6469 /* When inheriting a wider reload, we have a MEM in reload_in[j],
6470 e.g. inheriting a SImode output reload for
6471 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6472 if (optimize && reload_inherited[j] && reload_in[j]
6473 && GET_CODE (reload_in[j]) == MEM
6474 && reload_spill_index[j] >= 0
6475 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6478 = count_occurrences (PATTERN (insn), reload_in[j]) == 1 ? 0 : -1;
6480 = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6482 /* Add a note saying the input reload reg
6483 dies in this insn, if anyone cares. */
6484 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6486 && reload_reg_rtx[j] != old
6487 && reload_reg_rtx[j] != 0
6488 && reload_out[j] == 0
6489 && ! reload_inherited[j]
6490 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j])))
6492 register rtx reloadreg = reload_reg_rtx[j];
6495 /* We can't abort here because we need to support this for sched.c.
6496 It's not terrible to miss a REG_DEAD note, but we should try
6497 to figure out how to do this correctly. */
6498 /* The code below is incorrect for address-only reloads. */
6499 if (reload_when_needed[j] != RELOAD_OTHER
6500 && reload_when_needed[j] != RELOAD_FOR_INPUT)
6504 /* Add a death note to this insn, for an input reload. */
6506 if ((reload_when_needed[j] == RELOAD_OTHER
6507 || reload_when_needed[j] == RELOAD_FOR_INPUT)
6508 && ! dead_or_set_p (insn, reloadreg))
6510 = gen_rtx_EXPR_LIST (REG_DEAD,
6511 reloadreg, REG_NOTES (insn));
6514 /* When we inherit a reload, the last marked death of the reload reg
6515 may no longer really be a death. */
6516 if (reload_reg_rtx[j] != 0
6517 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j]))
6518 && reload_inherited[j])
6520 /* Handle inheriting an output reload.
6521 Remove the death note from the output reload insn. */
6522 if (reload_spill_index[j] >= 0
6523 && GET_CODE (reload_in[j]) == REG
6524 && spill_reg_store[reload_spill_index[j]] != 0
6525 && find_regno_note (spill_reg_store[reload_spill_index[j]],
6526 REG_DEAD, REGNO (reload_reg_rtx[j])))
6527 remove_death (REGNO (reload_reg_rtx[j]),
6528 spill_reg_store[reload_spill_index[j]]);
6529 /* Likewise for input reloads that were inherited. */
6530 else if (reload_spill_index[j] >= 0
6531 && GET_CODE (reload_in[j]) == REG
6532 && spill_reg_store[reload_spill_index[j]] == 0
6533 && reload_inheritance_insn[j] != 0
6534 && find_regno_note (reload_inheritance_insn[j], REG_DEAD,
6535 REGNO (reload_reg_rtx[j])))
6536 remove_death (REGNO (reload_reg_rtx[j]),
6537 reload_inheritance_insn[j]);
6542 /* We got this register from find_equiv_reg.
6543 Search back for its last death note and get rid of it.
6544 But don't search back too far.
6545 Don't go past a place where this reg is set,
6546 since a death note before that remains valid. */
6547 for (prev = PREV_INSN (insn);
6548 prev && GET_CODE (prev) != CODE_LABEL;
6549 prev = PREV_INSN (prev))
6550 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
6551 && dead_or_set_p (prev, reload_reg_rtx[j]))
6553 if (find_regno_note (prev, REG_DEAD,
6554 REGNO (reload_reg_rtx[j])))
6555 remove_death (REGNO (reload_reg_rtx[j]), prev);
6561 /* We might have used find_equiv_reg above to choose an alternate
6562 place from which to reload. If so, and it died, we need to remove
6563 that death and move it to one of the insns we just made. */
6565 if (oldequiv_reg != 0
6566 && PRESERVE_DEATH_INFO_REGNO_P (true_regnum (oldequiv_reg)))
6570 for (prev = PREV_INSN (insn); prev && GET_CODE (prev) != CODE_LABEL;
6571 prev = PREV_INSN (prev))
6572 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
6573 && dead_or_set_p (prev, oldequiv_reg))
6575 if (find_regno_note (prev, REG_DEAD, REGNO (oldequiv_reg)))
6577 for (prev1 = this_reload_insn;
6578 prev1; prev1 = PREV_INSN (prev1))
6579 if (GET_RTX_CLASS (GET_CODE (prev1) == 'i')
6580 && reg_overlap_mentioned_for_reload_p (oldequiv_reg,
6583 REG_NOTES (prev1) = gen_rtx_EXPR_LIST (REG_DEAD,
6588 remove_death (REGNO (oldequiv_reg), prev);
6595 /* If we are reloading a register that was recently stored in with an
6596 output-reload, see if we can prove there was
6597 actually no need to store the old value in it. */
6599 if (optimize && reload_inherited[j] && reload_spill_index[j] >= 0
6600 && reload_in[j] != 0
6601 && GET_CODE (reload_in[j]) == REG
6603 /* There doesn't seem to be any reason to restrict this to pseudos
6604 and doing so loses in the case where we are copying from a
6605 register of the wrong class. */
6606 && REGNO (reload_in[j]) >= FIRST_PSEUDO_REGISTER
6608 && spill_reg_store[reload_spill_index[j]] != 0
6609 /* This is unsafe if some other reload uses the same reg first. */
6610 && reload_reg_free_before_p (reload_spill_index[j],
6611 reload_opnum[j], reload_when_needed[j])
6612 && dead_or_set_p (insn, reload_in[j])
6613 /* This is unsafe if operand occurs more than once in current
6614 insn. Perhaps some occurrences weren't reloaded. */
6615 && (count_occurrences (PATTERN (insn), reload_in[j])
6616 == expect_occurrences))
6617 delete_output_reload (insn, j,
6618 spill_reg_store[reload_spill_index[j]]);
6620 /* Input-reloading is done. Now do output-reloading,
6621 storing the value from the reload-register after the main insn
6622 if reload_out[j] is nonzero.
6624 ??? At some point we need to support handling output reloads of
6625 JUMP_INSNs or insns that set cc0. */
6626 old = reload_out[j];
6628 && reload_reg_rtx[j] != old
6629 && reload_reg_rtx[j] != 0)
6631 register rtx reloadreg = reload_reg_rtx[j];
6632 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6633 register rtx second_reloadreg = 0;
6636 enum machine_mode mode;
6639 /* An output operand that dies right away does need a reload,
6640 but need not be copied from it. Show the new location in the
6642 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6643 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6645 XEXP (note, 0) = reload_reg_rtx[j];
6648 /* Likewise for a SUBREG of an operand that dies. */
6649 else if (GET_CODE (old) == SUBREG
6650 && GET_CODE (SUBREG_REG (old)) == REG
6651 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6654 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6658 else if (GET_CODE (old) == SCRATCH)
6659 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6660 but we don't want to make an output reload. */
6664 /* Strip off of OLD any size-increasing SUBREGs such as
6665 (SUBREG:SI foo:QI 0). */
6667 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
6668 && (GET_MODE_SIZE (GET_MODE (old))
6669 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
6670 old = SUBREG_REG (old);
6673 /* If is a JUMP_INSN, we can't support output reloads yet. */
6674 if (GET_CODE (insn) == JUMP_INSN)
6677 if (reload_when_needed[j] == RELOAD_OTHER)
6680 push_to_sequence (output_reload_insns[reload_opnum[j]]);
6682 /* Determine the mode to reload in.
6683 See comments above (for input reloading). */
6685 mode = GET_MODE (old);
6686 if (mode == VOIDmode)
6688 /* VOIDmode should never happen for an output. */
6689 if (asm_noperands (PATTERN (insn)) < 0)
6690 /* It's the compiler's fault. */
6691 fatal_insn ("VOIDmode on an output", insn);
6692 error_for_asm (insn, "output operand is constant in `asm'");
6693 /* Prevent crash--use something we know is valid. */
6695 old = gen_rtx_REG (mode, REGNO (reloadreg));
6698 if (GET_MODE (reloadreg) != mode)
6699 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6701 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6703 /* If we need two reload regs, set RELOADREG to the intermediate
6704 one, since it will be stored into OLD. We might need a secondary
6705 register only for an input reload, so check again here. */
6707 if (reload_secondary_out_reload[j] >= 0)
6711 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6712 && reg_equiv_mem[REGNO (old)] != 0)
6713 real_old = reg_equiv_mem[REGNO (old)];
6715 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
6719 second_reloadreg = reloadreg;
6720 reloadreg = reload_reg_rtx[reload_secondary_out_reload[j]];
6722 /* See if RELOADREG is to be used as a scratch register
6723 or as an intermediate register. */
6724 if (reload_secondary_out_icode[j] != CODE_FOR_nothing)
6726 emit_insn ((GEN_FCN (reload_secondary_out_icode[j])
6727 (real_old, second_reloadreg, reloadreg)));
6732 /* See if we need both a scratch and intermediate reload
6735 int secondary_reload = reload_secondary_out_reload[j];
6736 enum insn_code tertiary_icode
6737 = reload_secondary_out_icode[secondary_reload];
6739 if (GET_MODE (reloadreg) != mode)
6740 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6742 if (tertiary_icode != CODE_FOR_nothing)
6745 = reload_reg_rtx[reload_secondary_out_reload[secondary_reload]];
6748 /* Copy primary reload reg to secondary reload reg.
6749 (Note that these have been swapped above, then
6750 secondary reload reg to OLD using our insn. */
6752 /* If REAL_OLD is a paradoxical SUBREG, remove it
6753 and try to put the opposite SUBREG on
6755 if (GET_CODE (real_old) == SUBREG
6756 && (GET_MODE_SIZE (GET_MODE (real_old))
6757 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6758 && 0 != (tem = gen_lowpart_common
6759 (GET_MODE (SUBREG_REG (real_old)),
6761 real_old = SUBREG_REG (real_old), reloadreg = tem;
6763 gen_reload (reloadreg, second_reloadreg,
6764 reload_opnum[j], reload_when_needed[j]);
6765 emit_insn ((GEN_FCN (tertiary_icode)
6766 (real_old, reloadreg, third_reloadreg)));
6771 /* Copy between the reload regs here and then to
6774 gen_reload (reloadreg, second_reloadreg,
6775 reload_opnum[j], reload_when_needed[j]);
6781 /* Output the last reload insn. */
6783 gen_reload (old, reloadreg, reload_opnum[j],
6784 reload_when_needed[j]);
6786 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6787 /* If final will look at death notes for this reg,
6788 put one on the last output-reload insn to use it. Similarly
6789 for any secondary register. */
6790 if (PRESERVE_DEATH_INFO_REGNO_P (REGNO (reloadreg)))
6791 for (p = get_last_insn (); p; p = PREV_INSN (p))
6792 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
6793 && reg_overlap_mentioned_for_reload_p (reloadreg,
6795 REG_NOTES (p) = gen_rtx_EXPR_LIST (REG_DEAD,
6796 reloadreg, REG_NOTES (p));
6798 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6799 if (! special && second_reloadreg
6800 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reloadreg)))
6801 for (p = get_last_insn (); p; p = PREV_INSN (p))
6802 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
6803 && reg_overlap_mentioned_for_reload_p (second_reloadreg,
6805 REG_NOTES (p) = gen_rtx_EXPR_LIST (REG_DEAD,
6810 /* Look at all insns we emitted, just to be safe. */
6811 for (p = get_insns (); p; p = NEXT_INSN (p))
6812 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
6814 rtx pat = PATTERN (p);
6816 /* If this output reload doesn't come from a spill reg,
6817 clear any memory of reloaded copies of the pseudo reg.
6818 If this output reload comes from a spill reg,
6819 reg_has_output_reload will make this do nothing. */
6820 note_stores (pat, forget_old_reloads_1);
6822 if (reg_mentioned_p (reload_reg_rtx[j], pat))
6824 if (reload_spill_index[j] < 0
6825 && GET_CODE (pat) == SET
6826 && SET_SRC (pat) == reload_reg_rtx[j])
6828 int src = REGNO (SET_SRC (pat));
6830 reload_spill_index[j] = src;
6831 SET_HARD_REG_BIT (reg_is_output_reload, src);
6832 if (find_regno_note (insn, REG_DEAD, src))
6833 SET_HARD_REG_BIT (reg_reloaded_died, src);
6835 if (reload_spill_index[j] >= 0)
6836 new_spill_reg_store[reload_spill_index[j]] = p;
6840 if (reload_when_needed[j] == RELOAD_OTHER)
6842 emit_insns (other_output_reload_insns[reload_opnum[j]]);
6843 other_output_reload_insns[reload_opnum[j]] = get_insns ();
6846 output_reload_insns[reload_opnum[j]] = get_insns ();
6852 /* Now write all the insns we made for reloads in the order expected by
6853 the allocation functions. Prior to the insn being reloaded, we write
6854 the following reloads:
6856 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6858 RELOAD_OTHER reloads.
6860 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6861 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6862 RELOAD_FOR_INPUT reload for the operand.
6864 RELOAD_FOR_OPADDR_ADDRS reloads.
6866 RELOAD_FOR_OPERAND_ADDRESS reloads.
6868 After the insn being reloaded, we write the following:
6870 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6871 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6872 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6873 reloads for the operand. The RELOAD_OTHER output reloads are
6874 output in descending order by reload number. */
6876 emit_insns_before (other_input_address_reload_insns, before_insn);
6877 emit_insns_before (other_input_reload_insns, before_insn);
6879 for (j = 0; j < reload_n_operands; j++)
6881 emit_insns_before (inpaddr_address_reload_insns[j], before_insn);
6882 emit_insns_before (input_address_reload_insns[j], before_insn);
6883 emit_insns_before (input_reload_insns[j], before_insn);
6886 emit_insns_before (other_operand_reload_insns, before_insn);
6887 emit_insns_before (operand_reload_insns, before_insn);
6889 for (j = 0; j < reload_n_operands; j++)
6891 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
6892 emit_insns_before (output_address_reload_insns[j], following_insn);
6893 emit_insns_before (output_reload_insns[j], following_insn);
6894 emit_insns_before (other_output_reload_insns[j], following_insn);
6897 /* Move death notes from INSN
6898 to output-operand-address and output reload insns. */
6899 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6902 /* Loop over those insns, last ones first. */
6903 for (insn1 = PREV_INSN (following_insn); insn1 != insn;
6904 insn1 = PREV_INSN (insn1))
6905 if (GET_CODE (insn1) == INSN && GET_CODE (PATTERN (insn1)) == SET)
6907 rtx source = SET_SRC (PATTERN (insn1));
6908 rtx dest = SET_DEST (PATTERN (insn1));
6910 /* The note we will examine next. */
6911 rtx reg_notes = REG_NOTES (insn);
6912 /* The place that pointed to this note. */
6913 rtx *prev_reg_note = ®_NOTES (insn);
6915 /* If the note is for something used in the source of this
6916 reload insn, or in the output address, move the note. */
6919 rtx next_reg_notes = XEXP (reg_notes, 1);
6920 if (REG_NOTE_KIND (reg_notes) == REG_DEAD
6921 && GET_CODE (XEXP (reg_notes, 0)) == REG
6922 && ((GET_CODE (dest) != REG
6923 && reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
6925 || reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
6928 *prev_reg_note = next_reg_notes;
6929 XEXP (reg_notes, 1) = REG_NOTES (insn1);
6930 REG_NOTES (insn1) = reg_notes;
6933 prev_reg_note = &XEXP (reg_notes, 1);
6935 reg_notes = next_reg_notes;
6941 /* For all the spill regs newly reloaded in this instruction,
6942 record what they were reloaded from, so subsequent instructions
6943 can inherit the reloads.
6945 Update spill_reg_store for the reloads of this insn.
6946 Copy the elements that were updated in the loop above. */
6948 for (j = 0; j < n_reloads; j++)
6950 register int r = reload_order[j];
6951 register int i = reload_spill_index[r];
6953 /* I is nonneg if this reload used a register.
6954 If reload_reg_rtx[r] is 0, this is an optional reload
6955 that we opted to ignore. */
6957 if (i >= 0 && reload_reg_rtx[r] != 0)
6960 = HARD_REGNO_NREGS (i, GET_MODE (reload_reg_rtx[r]));
6962 int part_reaches_end = 0;
6963 int all_reaches_end = 1;
6965 /* For a multi register reload, we need to check if all or part
6966 of the value lives to the end. */
6967 for (k = 0; k < nr; k++)
6969 if (reload_reg_reaches_end_p (i + k, reload_opnum[r],
6970 reload_when_needed[r]))
6971 part_reaches_end = 1;
6973 all_reaches_end = 0;
6976 /* Ignore reloads that don't reach the end of the insn in
6978 if (all_reaches_end)
6980 /* First, clear out memory of what used to be in this spill reg.
6981 If consecutive registers are used, clear them all. */
6983 for (k = 0; k < nr; k++)
6984 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
6986 /* Maybe the spill reg contains a copy of reload_out. */
6987 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
6989 register int nregno = REGNO (reload_out[r]);
6990 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6991 : HARD_REGNO_NREGS (nregno,
6992 GET_MODE (reload_reg_rtx[r])));
6994 spill_reg_store[i] = new_spill_reg_store[i];
6995 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
6997 /* If NREGNO is a hard register, it may occupy more than
6998 one register. If it does, say what is in the
6999 rest of the registers assuming that both registers
7000 agree on how many words the object takes. If not,
7001 invalidate the subsequent registers. */
7003 if (nregno < FIRST_PSEUDO_REGISTER)
7004 for (k = 1; k < nnr; k++)
7005 reg_last_reload_reg[nregno + k]
7007 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
7008 REGNO (reload_reg_rtx[r]) + k)
7011 /* Now do the inverse operation. */
7012 for (k = 0; k < nr; k++)
7014 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7015 reg_reloaded_contents[i + k]
7016 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7019 reg_reloaded_insn[i + k] = insn;
7020 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7024 /* Maybe the spill reg contains a copy of reload_in. Only do
7025 something if there will not be an output reload for
7026 the register being reloaded. */
7027 else if (reload_out[r] == 0
7028 && reload_in[r] != 0
7029 && spill_reg_order[i] >= 0
7030 && ((GET_CODE (reload_in[r]) == REG
7031 && ! reg_has_output_reload[REGNO (reload_in[r])])
7032 || (GET_CODE (reload_in_reg[r]) == REG
7033 && ! reg_has_output_reload[REGNO (reload_in_reg[r])])))
7035 register int nregno;
7038 if (GET_CODE (reload_in[r]) == REG)
7039 nregno = REGNO (reload_in[r]);
7041 nregno = REGNO (reload_in_reg[r]);
7043 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7044 : HARD_REGNO_NREGS (nregno,
7045 GET_MODE (reload_reg_rtx[r])));
7047 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
7049 if (nregno < FIRST_PSEUDO_REGISTER)
7050 for (k = 1; k < nnr; k++)
7051 reg_last_reload_reg[nregno + k]
7053 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
7054 REGNO (reload_reg_rtx[r]) + k)
7057 /* Unless we inherited this reload, show we haven't
7058 recently done a store. */
7059 if (! reload_inherited[r])
7060 spill_reg_store[i] = 0;
7062 for (k = 0; k < nr; k++)
7064 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7065 reg_reloaded_contents[i + k]
7066 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7069 reg_reloaded_insn[i + k] = insn;
7070 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7075 /* However, if part of the reload reaches the end, then we must
7076 invalidate the old info for the part that survives to the end. */
7077 else if (part_reaches_end)
7079 for (k = 0; k < nr; k++)
7080 if (reload_reg_reaches_end_p (i + k,
7082 reload_when_needed[r]))
7083 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7087 /* The following if-statement was #if 0'd in 1.34 (or before...).
7088 It's reenabled in 1.35 because supposedly nothing else
7089 deals with this problem. */
7091 /* If a register gets output-reloaded from a non-spill register,
7092 that invalidates any previous reloaded copy of it.
7093 But forget_old_reloads_1 won't get to see it, because
7094 it thinks only about the original insn. So invalidate it here. */
7095 if (i < 0 && reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
7097 register int nregno = REGNO (reload_out[r]);
7098 if (nregno >= FIRST_PSEUDO_REGISTER)
7099 reg_last_reload_reg[nregno] = 0;
7102 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (reload_out[r]));
7104 while (num_regs-- > 0)
7105 reg_last_reload_reg[nregno + num_regs] = 0;
7109 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7112 /* Emit code to perform a reload from IN (which may be a reload register) to
7113 OUT (which may also be a reload register). IN or OUT is from operand
7114 OPNUM with reload type TYPE.
7116 Returns first insn emitted. */
7119 gen_reload (out, in, opnum, type)
7123 enum reload_type type;
7125 rtx last = get_last_insn ();
7128 /* If IN is a paradoxical SUBREG, remove it and try to put the
7129 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7130 if (GET_CODE (in) == SUBREG
7131 && (GET_MODE_SIZE (GET_MODE (in))
7132 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7133 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7134 in = SUBREG_REG (in), out = tem;
7135 else if (GET_CODE (out) == SUBREG
7136 && (GET_MODE_SIZE (GET_MODE (out))
7137 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7138 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7139 out = SUBREG_REG (out), in = tem;
7141 /* How to do this reload can get quite tricky. Normally, we are being
7142 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7143 register that didn't get a hard register. In that case we can just
7144 call emit_move_insn.
7146 We can also be asked to reload a PLUS that adds a register or a MEM to
7147 another register, constant or MEM. This can occur during frame pointer
7148 elimination and while reloading addresses. This case is handled by
7149 trying to emit a single insn to perform the add. If it is not valid,
7150 we use a two insn sequence.
7152 Finally, we could be called to handle an 'o' constraint by putting
7153 an address into a register. In that case, we first try to do this
7154 with a named pattern of "reload_load_address". If no such pattern
7155 exists, we just emit a SET insn and hope for the best (it will normally
7156 be valid on machines that use 'o').
7158 This entire process is made complex because reload will never
7159 process the insns we generate here and so we must ensure that
7160 they will fit their constraints and also by the fact that parts of
7161 IN might be being reloaded separately and replaced with spill registers.
7162 Because of this, we are, in some sense, just guessing the right approach
7163 here. The one listed above seems to work.
7165 ??? At some point, this whole thing needs to be rethought. */
7167 if (GET_CODE (in) == PLUS
7168 && (GET_CODE (XEXP (in, 0)) == REG
7169 || GET_CODE (XEXP (in, 0)) == SUBREG
7170 || GET_CODE (XEXP (in, 0)) == MEM)
7171 && (GET_CODE (XEXP (in, 1)) == REG
7172 || GET_CODE (XEXP (in, 1)) == SUBREG
7173 || CONSTANT_P (XEXP (in, 1))
7174 || GET_CODE (XEXP (in, 1)) == MEM))
7176 /* We need to compute the sum of a register or a MEM and another
7177 register, constant, or MEM, and put it into the reload
7178 register. The best possible way of doing this is if the machine
7179 has a three-operand ADD insn that accepts the required operands.
7181 The simplest approach is to try to generate such an insn and see if it
7182 is recognized and matches its constraints. If so, it can be used.
7184 It might be better not to actually emit the insn unless it is valid,
7185 but we need to pass the insn as an operand to `recog' and
7186 `insn_extract' and it is simpler to emit and then delete the insn if
7187 not valid than to dummy things up. */
7189 rtx op0, op1, tem, insn;
7192 op0 = find_replacement (&XEXP (in, 0));
7193 op1 = find_replacement (&XEXP (in, 1));
7195 /* Since constraint checking is strict, commutativity won't be
7196 checked, so we need to do that here to avoid spurious failure
7197 if the add instruction is two-address and the second operand
7198 of the add is the same as the reload reg, which is frequently
7199 the case. If the insn would be A = B + A, rearrange it so
7200 it will be A = A + B as constrain_operands expects. */
7202 if (GET_CODE (XEXP (in, 1)) == REG
7203 && REGNO (out) == REGNO (XEXP (in, 1)))
7204 tem = op0, op0 = op1, op1 = tem;
7206 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7207 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7209 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7210 code = recog_memoized (insn);
7214 insn_extract (insn);
7215 /* We want constrain operands to treat this insn strictly in
7216 its validity determination, i.e., the way it would after reload
7218 if (constrain_operands (code, 1))
7222 delete_insns_since (last);
7224 /* If that failed, we must use a conservative two-insn sequence.
7225 use move to copy constant, MEM, or pseudo register to the reload
7226 register since "move" will be able to handle an arbitrary operand,
7227 unlike add which can't, in general. Then add the registers.
7229 If there is another way to do this for a specific machine, a
7230 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7233 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7234 || (GET_CODE (op1) == REG
7235 && REGNO (op1) >= FIRST_PSEUDO_REGISTER))
7236 tem = op0, op0 = op1, op1 = tem;
7238 gen_reload (out, op0, opnum, type);
7240 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7241 This fixes a problem on the 32K where the stack pointer cannot
7242 be used as an operand of an add insn. */
7244 if (rtx_equal_p (op0, op1))
7247 insn = emit_insn (gen_add2_insn (out, op1));
7249 /* If that failed, copy the address register to the reload register.
7250 Then add the constant to the reload register. */
7252 code = recog_memoized (insn);
7256 insn_extract (insn);
7257 /* We want constrain operands to treat this insn strictly in
7258 its validity determination, i.e., the way it would after reload
7260 if (constrain_operands (code, 1))
7264 delete_insns_since (last);
7266 gen_reload (out, op1, opnum, type);
7267 emit_insn (gen_add2_insn (out, op0));
7270 #ifdef SECONDARY_MEMORY_NEEDED
7271 /* If we need a memory location to do the move, do it that way. */
7272 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7273 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7274 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7275 REGNO_REG_CLASS (REGNO (out)),
7278 /* Get the memory to use and rewrite both registers to its mode. */
7279 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7281 if (GET_MODE (loc) != GET_MODE (out))
7282 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7284 if (GET_MODE (loc) != GET_MODE (in))
7285 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7287 gen_reload (loc, in, opnum, type);
7288 gen_reload (out, loc, opnum, type);
7292 /* If IN is a simple operand, use gen_move_insn. */
7293 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7294 emit_insn (gen_move_insn (out, in));
7296 #ifdef HAVE_reload_load_address
7297 else if (HAVE_reload_load_address)
7298 emit_insn (gen_reload_load_address (out, in));
7301 /* Otherwise, just write (set OUT IN) and hope for the best. */
7303 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7305 /* Return the first insn emitted.
7306 We can not just return get_last_insn, because there may have
7307 been multiple instructions emitted. Also note that gen_move_insn may
7308 emit more than one insn itself, so we can not assume that there is one
7309 insn emitted per emit_insn_before call. */
7311 return last ? NEXT_INSN (last) : get_insns ();
7314 /* Delete a previously made output-reload
7315 whose result we now believe is not needed.
7316 First we double-check.
7318 INSN is the insn now being processed.
7319 OUTPUT_RELOAD_INSN is the insn of the output reload.
7320 J is the reload-number for this insn. */
7323 delete_output_reload (insn, j, output_reload_insn)
7326 rtx output_reload_insn;
7330 /* Get the raw pseudo-register referred to. */
7332 rtx reg = reload_in[j];
7333 while (GET_CODE (reg) == SUBREG)
7334 reg = SUBREG_REG (reg);
7336 /* If the pseudo-reg we are reloading is no longer referenced
7337 anywhere between the store into it and here,
7338 and no jumps or labels intervene, then the value can get
7339 here through the reload reg alone.
7340 Otherwise, give up--return. */
7341 for (i1 = NEXT_INSN (output_reload_insn);
7342 i1 != insn; i1 = NEXT_INSN (i1))
7344 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7346 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7347 && reg_mentioned_p (reg, PATTERN (i1)))
7351 /* If this insn will store in the pseudo again,
7352 the previous store can be removed. */
7353 if (reload_out[j] == reload_in[j])
7354 delete_insn (output_reload_insn);
7356 /* See if the pseudo reg has been completely replaced
7357 with reload regs. If so, delete the store insn
7358 and forget we had a stack slot for the pseudo. */
7359 else if (REG_N_DEATHS (REGNO (reg)) == 1
7360 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7361 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7365 /* We know that it was used only between here
7366 and the beginning of the current basic block.
7367 (We also know that the last use before INSN was
7368 the output reload we are thinking of deleting, but never mind that.)
7369 Search that range; see if any ref remains. */
7370 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7372 rtx set = single_set (i2);
7374 /* Uses which just store in the pseudo don't count,
7375 since if they are the only uses, they are dead. */
7376 if (set != 0 && SET_DEST (set) == reg)
7378 if (GET_CODE (i2) == CODE_LABEL
7379 || GET_CODE (i2) == JUMP_INSN)
7381 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7382 && reg_mentioned_p (reg, PATTERN (i2)))
7383 /* Some other ref remains;
7384 we can't do anything. */
7388 /* Delete the now-dead stores into this pseudo. */
7389 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7391 rtx set = single_set (i2);
7393 if (set != 0 && SET_DEST (set) == reg)
7395 /* This might be a basic block head,
7396 thus don't use delete_insn. */
7397 PUT_CODE (i2, NOTE);
7398 NOTE_SOURCE_FILE (i2) = 0;
7399 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7401 if (GET_CODE (i2) == CODE_LABEL
7402 || GET_CODE (i2) == JUMP_INSN)
7406 /* For the debugging info,
7407 say the pseudo lives in this reload reg. */
7408 reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
7409 alter_reg (REGNO (reg), -1);
7413 /* Output reload-insns to reload VALUE into RELOADREG.
7414 VALUE is an autoincrement or autodecrement RTX whose operand
7415 is a register or memory location;
7416 so reloading involves incrementing that location.
7418 INC_AMOUNT is the number to increment or decrement by (always positive).
7419 This cannot be deduced from VALUE. */
7422 inc_for_reload (reloadreg, value, inc_amount)
7427 /* REG or MEM to be copied and incremented. */
7428 rtx incloc = XEXP (value, 0);
7429 /* Nonzero if increment after copying. */
7430 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7436 /* No hard register is equivalent to this register after
7437 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7438 we could inc/dec that register as well (maybe even using it for
7439 the source), but I'm not sure it's worth worrying about. */
7440 if (GET_CODE (incloc) == REG)
7441 reg_last_reload_reg[REGNO (incloc)] = 0;
7443 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7444 inc_amount = - inc_amount;
7446 inc = GEN_INT (inc_amount);
7448 /* If this is post-increment, first copy the location to the reload reg. */
7450 emit_insn (gen_move_insn (reloadreg, incloc));
7452 /* See if we can directly increment INCLOC. Use a method similar to that
7455 last = get_last_insn ();
7456 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7457 gen_rtx_PLUS (GET_MODE (incloc),
7460 code = recog_memoized (add_insn);
7463 insn_extract (add_insn);
7464 if (constrain_operands (code, 1))
7466 /* If this is a pre-increment and we have incremented the value
7467 where it lives, copy the incremented value to RELOADREG to
7468 be used as an address. */
7471 emit_insn (gen_move_insn (reloadreg, incloc));
7477 delete_insns_since (last);
7479 /* If couldn't do the increment directly, must increment in RELOADREG.
7480 The way we do this depends on whether this is pre- or post-increment.
7481 For pre-increment, copy INCLOC to the reload register, increment it
7482 there, then save back. */
7486 emit_insn (gen_move_insn (reloadreg, incloc));
7487 emit_insn (gen_add2_insn (reloadreg, inc));
7488 emit_insn (gen_move_insn (incloc, reloadreg));
7493 Because this might be a jump insn or a compare, and because RELOADREG
7494 may not be available after the insn in an input reload, we must do
7495 the incrementation before the insn being reloaded for.
7497 We have already copied INCLOC to RELOADREG. Increment the copy in
7498 RELOADREG, save that back, then decrement RELOADREG so it has
7499 the original value. */
7501 emit_insn (gen_add2_insn (reloadreg, inc));
7502 emit_insn (gen_move_insn (incloc, reloadreg));
7503 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7509 /* Return 1 if we are certain that the constraint-string STRING allows
7510 the hard register REG. Return 0 if we can't be sure of this. */
7513 constraint_accepts_reg_p (string, reg)
7518 int regno = true_regnum (reg);
7521 /* Initialize for first alternative. */
7523 /* Check that each alternative contains `g' or `r'. */
7525 switch (c = *string++)
7528 /* If an alternative lacks `g' or `r', we lose. */
7531 /* If an alternative lacks `g' or `r', we lose. */
7534 /* Initialize for next alternative. */
7539 /* Any general reg wins for this alternative. */
7540 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7544 /* Any reg in specified class wins for this alternative. */
7546 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7548 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
7554 /* Return the number of places FIND appears within X, but don't count
7555 an occurrence if some SET_DEST is FIND. */
7558 count_occurrences (x, find)
7559 register rtx x, find;
7562 register enum rtx_code code;
7563 register char *format_ptr;
7571 code = GET_CODE (x);
7586 if (SET_DEST (x) == find)
7587 return count_occurrences (SET_SRC (x), find);
7594 format_ptr = GET_RTX_FORMAT (code);
7597 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7599 switch (*format_ptr++)
7602 count += count_occurrences (XEXP (x, i), find);
7606 if (XVEC (x, i) != NULL)
7608 for (j = 0; j < XVECLEN (x, i); j++)
7609 count += count_occurrences (XVECEXP (x, i, j), find);
7617 /* This array holds values which are equivalent to a hard register
7618 during reload_cse_regs. Each array element is an EXPR_LIST of
7619 values. Each time a hard register is set, we set the corresponding
7620 array element to the value. Each time a hard register is copied
7621 into memory, we add the memory location to the corresponding array
7622 element. We don't store values or memory addresses with side
7623 effects in this array.
7625 If the value is a CONST_INT, then the mode of the containing
7626 EXPR_LIST is the mode in which that CONST_INT was referenced.
7628 We sometimes clobber a specific entry in a list. In that case, we
7629 just set XEXP (list-entry, 0) to 0. */
7631 static rtx *reg_values;
7633 /* This is a preallocated REG rtx which we use as a temporary in
7634 reload_cse_invalidate_regno, so that we don't need to allocate a
7635 new one each time through a loop in that function. */
7637 static rtx invalidate_regno_rtx;
7639 /* This is a set of registers for which we must remove REG_DEAD notes in
7640 previous insns, because our modifications made them invalid. That can
7641 happen if we introduced the register into the current insn, or we deleted
7642 the current insn which used to set the register. */
7644 static HARD_REG_SET no_longer_dead_regs;
7646 /* Invalidate any entries in reg_values which depend on REGNO,
7647 including those for REGNO itself. This is called if REGNO is
7648 changing. If CLOBBER is true, then always forget anything we
7649 currently know about REGNO. MODE is the mode of the assignment to
7650 REGNO, which is used to determine how many hard registers are being
7651 changed. If MODE is VOIDmode, then only REGNO is being changed;
7652 this is used when invalidating call clobbered registers across a
7656 reload_cse_invalidate_regno (regno, mode, clobber)
7658 enum machine_mode mode;
7664 /* Our callers don't always go through true_regnum; we may see a
7665 pseudo-register here from a CLOBBER or the like. We probably
7666 won't ever see a pseudo-register that has a real register number,
7667 for we check anyhow for safety. */
7668 if (regno >= FIRST_PSEUDO_REGISTER)
7669 regno = reg_renumber[regno];
7673 if (mode == VOIDmode)
7674 endregno = regno + 1;
7676 endregno = regno + HARD_REGNO_NREGS (regno, mode);
7679 for (i = regno; i < endregno; i++)
7682 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
7686 for (x = reg_values[i]; x; x = XEXP (x, 1))
7688 if (XEXP (x, 0) != 0
7689 && refers_to_regno_p (regno, endregno, XEXP (x, 0), NULL_PTR))
7691 /* If this is the only entry on the list, clear
7692 reg_values[i]. Otherwise, just clear this entry on
7694 if (XEXP (x, 1) == 0 && x == reg_values[i])
7704 /* We must look at earlier registers, in case REGNO is part of a
7705 multi word value but is not the first register. If an earlier
7706 register has a value in a mode which overlaps REGNO, then we must
7707 invalidate that earlier register. Note that we do not need to
7708 check REGNO or later registers (we must not check REGNO itself,
7709 because we would incorrectly conclude that there was a conflict). */
7711 for (i = 0; i < regno; i++)
7715 for (x = reg_values[i]; x; x = XEXP (x, 1))
7717 if (XEXP (x, 0) != 0)
7719 PUT_MODE (invalidate_regno_rtx, GET_MODE (x));
7720 REGNO (invalidate_regno_rtx) = i;
7721 if (refers_to_regno_p (regno, endregno, invalidate_regno_rtx,
7724 reload_cse_invalidate_regno (i, VOIDmode, 1);
7732 /* The memory at address MEM_BASE is being changed.
7733 Return whether this change will invalidate VAL. */
7736 reload_cse_mem_conflict_p (mem_base, val)
7744 code = GET_CODE (val);
7747 /* Get rid of a few simple cases quickly. */
7760 if (GET_MODE (mem_base) == BLKmode
7761 || GET_MODE (val) == BLKmode)
7763 if (anti_dependence (val, mem_base))
7765 /* The address may contain nested MEMs. */
7772 fmt = GET_RTX_FORMAT (code);
7774 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7778 if (reload_cse_mem_conflict_p (mem_base, XEXP (val, i)))
7781 else if (fmt[i] == 'E')
7785 for (j = 0; j < XVECLEN (val, i); j++)
7786 if (reload_cse_mem_conflict_p (mem_base, XVECEXP (val, i, j)))
7794 /* Invalidate any entries in reg_values which are changed because of a
7795 store to MEM_RTX. If this is called because of a non-const call
7796 instruction, MEM_RTX is (mem:BLK const0_rtx). */
7799 reload_cse_invalidate_mem (mem_rtx)
7804 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
7808 for (x = reg_values[i]; x; x = XEXP (x, 1))
7810 if (XEXP (x, 0) != 0
7811 && reload_cse_mem_conflict_p (mem_rtx, XEXP (x, 0)))
7813 /* If this is the only entry on the list, clear
7814 reg_values[i]. Otherwise, just clear this entry on
7816 if (XEXP (x, 1) == 0 && x == reg_values[i])
7827 /* Invalidate DEST, which is being assigned to or clobbered. The
7828 second parameter exists so that this function can be passed to
7829 note_stores; it is ignored. */
7832 reload_cse_invalidate_rtx (dest, ignore)
7836 while (GET_CODE (dest) == STRICT_LOW_PART
7837 || GET_CODE (dest) == SIGN_EXTRACT
7838 || GET_CODE (dest) == ZERO_EXTRACT
7839 || GET_CODE (dest) == SUBREG)
7840 dest = XEXP (dest, 0);
7842 if (GET_CODE (dest) == REG)
7843 reload_cse_invalidate_regno (REGNO (dest), GET_MODE (dest), 1);
7844 else if (GET_CODE (dest) == MEM)
7845 reload_cse_invalidate_mem (dest);
7848 /* Possibly delete death notes on the insns before INSN if modifying INSN
7849 extended the lifespan of the registers. */
7852 reload_cse_delete_death_notes (insn)
7857 for (dreg = 0; dreg < FIRST_PSEUDO_REGISTER; dreg++)
7861 if (! TEST_HARD_REG_BIT (no_longer_dead_regs, dreg))
7864 for (trial = prev_nonnote_insn (insn);
7866 && GET_CODE (trial) != CODE_LABEL
7867 && GET_CODE (trial) != BARRIER);
7868 trial = prev_nonnote_insn (trial))
7870 if (find_regno_note (trial, REG_DEAD, dreg))
7872 remove_death (dreg, trial);
7879 /* Record that the current insn uses hard reg REGNO in mode MODE. This
7880 will be used in reload_cse_delete_death_notes to delete prior REG_DEAD
7881 notes for this register. */
7884 reload_cse_no_longer_dead (regno, mode)
7886 enum machine_mode mode;
7888 int nregs = HARD_REGNO_NREGS (regno, mode);
7891 SET_HARD_REG_BIT (no_longer_dead_regs, regno);
7897 /* Do a very simple CSE pass over the hard registers.
7899 This function detects no-op moves where we happened to assign two
7900 different pseudo-registers to the same hard register, and then
7901 copied one to the other. Reload will generate a useless
7902 instruction copying a register to itself.
7904 This function also detects cases where we load a value from memory
7905 into two different registers, and (if memory is more expensive than
7906 registers) changes it to simply copy the first register into the
7909 Another optimization is performed that scans the operands of each
7910 instruction to see whether the value is already available in a
7911 hard register. It then replaces the operand with the hard register
7912 if possible, much like an optional reload would. */
7915 reload_cse_regs (first)
7923 init_alias_analysis ();
7925 reg_values = (rtx *) alloca (FIRST_PSEUDO_REGISTER * sizeof (rtx));
7926 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
7929 /* Create our EXPR_LIST structures on reload_obstack, so that we can
7930 free them when we are done. */
7931 push_obstacks (&reload_obstack, &reload_obstack);
7932 firstobj = (char *) obstack_alloc (&reload_obstack, 0);
7934 /* We pass this to reload_cse_invalidate_mem to invalidate all of
7935 memory for a non-const call instruction. */
7936 callmem = gen_rtx_MEM (BLKmode, const0_rtx);
7938 /* This is used in reload_cse_invalidate_regno to avoid consing a
7939 new REG in a loop in that function. */
7940 invalidate_regno_rtx = gen_rtx_REG (VOIDmode, 0);
7942 for (insn = first; insn; insn = NEXT_INSN (insn))
7946 if (GET_CODE (insn) == CODE_LABEL)
7948 /* Forget all the register values at a code label. We don't
7949 try to do anything clever around jumps. */
7950 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
7956 #ifdef NON_SAVING_SETJMP
7957 if (NON_SAVING_SETJMP && GET_CODE (insn) == NOTE
7958 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
7960 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
7967 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
7970 CLEAR_HARD_REG_SET (no_longer_dead_regs);
7972 /* If this is a call instruction, forget anything stored in a
7973 call clobbered register, or, if this is not a const call, in
7975 if (GET_CODE (insn) == CALL_INSN)
7977 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
7978 if (call_used_regs[i])
7979 reload_cse_invalidate_regno (i, VOIDmode, 1);
7981 if (! CONST_CALL_P (insn))
7982 reload_cse_invalidate_mem (callmem);
7985 body = PATTERN (insn);
7986 if (GET_CODE (body) == SET)
7989 if (reload_cse_noop_set_p (body, insn))
7991 PUT_CODE (insn, NOTE);
7992 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
7993 NOTE_SOURCE_FILE (insn) = 0;
7994 reload_cse_delete_death_notes (insn);
7996 /* We're done with this insn. */
8000 /* It's not a no-op, but we can try to simplify it. */
8001 CLEAR_HARD_REG_SET (no_longer_dead_regs);
8002 count += reload_cse_simplify_set (body, insn);
8004 if (count > 0 && apply_change_group ())
8005 reload_cse_delete_death_notes (insn);
8006 else if (reload_cse_simplify_operands (insn))
8007 reload_cse_delete_death_notes (insn);
8009 reload_cse_record_set (body, body);
8011 else if (GET_CODE (body) == PARALLEL)
8015 /* If every action in a PARALLEL is a noop, we can delete
8016 the entire PARALLEL. */
8017 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8018 if ((GET_CODE (XVECEXP (body, 0, i)) != SET
8019 || ! reload_cse_noop_set_p (XVECEXP (body, 0, i), insn))
8020 && GET_CODE (XVECEXP (body, 0, i)) != CLOBBER)
8024 PUT_CODE (insn, NOTE);
8025 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8026 NOTE_SOURCE_FILE (insn) = 0;
8027 reload_cse_delete_death_notes (insn);
8029 /* We're done with this insn. */
8033 /* It's not a no-op, but we can try to simplify it. */
8034 CLEAR_HARD_REG_SET (no_longer_dead_regs);
8035 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8036 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8037 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8039 if (count > 0 && apply_change_group ())
8040 reload_cse_delete_death_notes (insn);
8041 else if (reload_cse_simplify_operands (insn))
8042 reload_cse_delete_death_notes (insn);
8044 /* Look through the PARALLEL and record the values being
8045 set, if possible. Also handle any CLOBBERs. */
8046 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8048 rtx x = XVECEXP (body, 0, i);
8050 if (GET_CODE (x) == SET)
8051 reload_cse_record_set (x, body);
8053 note_stores (x, reload_cse_invalidate_rtx);
8057 note_stores (body, reload_cse_invalidate_rtx);
8060 /* Clobber any registers which appear in REG_INC notes. We
8061 could keep track of the changes to their values, but it is
8062 unlikely to help. */
8066 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
8067 if (REG_NOTE_KIND (x) == REG_INC)
8068 reload_cse_invalidate_rtx (XEXP (x, 0), NULL_RTX);
8072 /* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only
8073 after we have processed the insn. */
8074 if (GET_CODE (insn) == CALL_INSN)
8078 for (x = CALL_INSN_FUNCTION_USAGE (insn); x; x = XEXP (x, 1))
8079 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
8080 reload_cse_invalidate_rtx (XEXP (XEXP (x, 0), 0), NULL_RTX);
8084 /* Free all the temporary structures we created, and go back to the
8085 regular obstacks. */
8086 obstack_free (&reload_obstack, firstobj);
8090 /* Return whether the values known for REGNO are equal to VAL. MODE
8091 is the mode of the object that VAL is being copied to; this matters
8092 if VAL is a CONST_INT. */
8095 reload_cse_regno_equal_p (regno, val, mode)
8098 enum machine_mode mode;
8105 for (x = reg_values[regno]; x; x = XEXP (x, 1))
8106 if (XEXP (x, 0) != 0
8107 && rtx_equal_p (XEXP (x, 0), val)
8108 && (GET_CODE (val) != CONST_INT
8109 || mode == GET_MODE (x)
8110 || (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8111 /* On a big endian machine if the value spans more than
8112 one register then this register holds the high part of
8113 it and we can't use it.
8115 ??? We should also compare with the high part of the
8117 && !(WORDS_BIG_ENDIAN
8118 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
8119 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
8120 GET_MODE_BITSIZE (GET_MODE (x))))))
8126 /* See whether a single set is a noop. SET is the set instruction we
8127 are should check, and INSN is the instruction from which it came. */
8130 reload_cse_noop_set_p (set, insn)
8135 enum machine_mode dest_mode;
8139 src = SET_SRC (set);
8140 dest = SET_DEST (set);
8141 dest_mode = GET_MODE (dest);
8143 if (side_effects_p (src))
8146 dreg = true_regnum (dest);
8147 sreg = true_regnum (src);
8149 /* Check for setting a register to itself. In this case, we don't
8150 have to worry about REG_DEAD notes. */
8151 if (dreg >= 0 && dreg == sreg)
8157 /* Check for setting a register to itself. */
8161 /* Check for setting a register to a value which we already know
8162 is in the register. */
8163 else if (reload_cse_regno_equal_p (dreg, src, dest_mode))
8166 /* Check for setting a register DREG to another register SREG
8167 where SREG is equal to a value which is already in DREG. */
8172 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
8176 if (XEXP (x, 0) == 0)
8179 if (dest_mode == GET_MODE (x))
8181 else if (GET_MODE_BITSIZE (dest_mode)
8182 < GET_MODE_BITSIZE (GET_MODE (x)))
8183 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
8188 && reload_cse_regno_equal_p (dreg, tmp, dest_mode))
8196 else if (GET_CODE (dest) == MEM)
8198 /* Check for storing a register to memory when we know that the
8199 register is equivalent to the memory location. */
8201 && reload_cse_regno_equal_p (sreg, dest, dest_mode)
8202 && ! side_effects_p (dest))
8206 /* If we can delete this SET, then we need to look for an earlier
8207 REG_DEAD note on DREG, and remove it if it exists. */
8208 if (ret && dreg >= 0)
8210 if (! find_regno_note (insn, REG_UNUSED, dreg))
8211 reload_cse_no_longer_dead (dreg, dest_mode);
8217 /* Try to simplify a single SET instruction. SET is the set pattern.
8218 INSN is the instruction it came from.
8219 This function only handles one case: if we set a register to a value
8220 which is not a register, we try to find that value in some other register
8221 and change the set into a register copy. */
8224 reload_cse_simplify_set (set, insn)
8230 enum machine_mode dest_mode;
8231 enum reg_class dclass;
8234 dreg = true_regnum (SET_DEST (set));
8238 src = SET_SRC (set);
8239 if (side_effects_p (src) || true_regnum (src) >= 0)
8242 dclass = REGNO_REG_CLASS (dreg);
8244 /* If memory loads are cheaper than register copies, don't change
8246 if (GET_CODE (src) == MEM
8247 && MEMORY_MOVE_COST (GET_MODE (src), dclass, 1) < 2)
8250 dest_mode = GET_MODE (SET_DEST (set));
8251 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8254 && REGISTER_MOVE_COST (REGNO_REG_CLASS (i), dclass) == 2
8255 && reload_cse_regno_equal_p (i, src, dest_mode))
8259 /* Pop back to the real obstacks while changing the insn. */
8262 validated = validate_change (insn, &SET_SRC (set),
8263 gen_rtx_REG (dest_mode, i), 1);
8265 /* Go back to the obstack we are using for temporary
8267 push_obstacks (&reload_obstack, &reload_obstack);
8269 if (validated && ! find_regno_note (insn, REG_UNUSED, i))
8271 reload_cse_no_longer_dead (i, dest_mode);
8279 /* Try to replace operands in INSN with equivalent values that are already
8280 in registers. This can be viewed as optional reloading.
8282 For each non-register operand in the insn, see if any hard regs are
8283 known to be equivalent to that operand. Record the alternatives which
8284 can accept these hard registers. Among all alternatives, select the
8285 ones which are better or equal to the one currently matching, where
8286 "better" is in terms of '?' and '!' constraints. Among the remaining
8287 alternatives, select the one which replaces most operands with
8291 reload_cse_simplify_operands (insn)
8294 #ifdef REGISTER_CONSTRAINTS
8295 int insn_code_number, n_operands, n_alternatives;
8298 char *constraints[MAX_RECOG_OPERANDS];
8300 /* Vector recording how bad an alternative is. */
8301 int *alternative_reject;
8302 /* Vector recording how many registers can be introduced by choosing
8303 this alternative. */
8304 int *alternative_nregs;
8305 /* Array of vectors recording, for each operand and each alternative,
8306 which hard register to substitute, or -1 if the operand should be
8308 int *op_alt_regno[MAX_RECOG_OPERANDS];
8309 /* Array of alternatives, sorted in order of decreasing desirability. */
8310 int *alternative_order;
8312 /* Find out some information about this insn. */
8313 insn_code_number = recog_memoized (insn);
8314 /* We don't modify asm instructions. */
8315 if (insn_code_number < 0)
8318 n_operands = insn_n_operands[insn_code_number];
8319 n_alternatives = insn_n_alternatives[insn_code_number];
8321 if (n_alternatives == 0 || n_operands == 0)
8323 insn_extract (insn);
8325 /* Figure out which alternative currently matches. */
8326 if (! constrain_operands (insn_code_number, 1))
8329 alternative_reject = (int *) alloca (n_alternatives * sizeof (int));
8330 alternative_nregs = (int *) alloca (n_alternatives * sizeof (int));
8331 alternative_order = (int *) alloca (n_alternatives * sizeof (int));
8332 bzero ((char *)alternative_reject, n_alternatives * sizeof (int));
8333 bzero ((char *)alternative_nregs, n_alternatives * sizeof (int));
8335 for (i = 0; i < n_operands; i++)
8337 enum machine_mode mode;
8341 op_alt_regno[i] = (int *) alloca (n_alternatives * sizeof (int));
8342 for (j = 0; j < n_alternatives; j++)
8343 op_alt_regno[i][j] = -1;
8345 p = constraints[i] = insn_operand_constraint[insn_code_number][i];
8346 mode = insn_operand_mode[insn_code_number][i];
8348 /* Add the reject values for each alternative given by the constraints
8349 for this operand. */
8357 alternative_reject[j] += 3;
8359 alternative_reject[j] += 300;
8362 /* We won't change operands which are already registers. We
8363 also don't want to modify output operands. */
8364 regno = true_regnum (recog_operand[i]);
8366 || constraints[i][0] == '='
8367 || constraints[i][0] == '+')
8370 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8372 int class = (int) NO_REGS;
8374 if (! reload_cse_regno_equal_p (regno, recog_operand[i], mode))
8377 /* We found a register equal to this operand. Now look for all
8378 alternatives that can accept this register and have not been
8379 assigned a register they can use yet. */
8388 case '=': case '+': case '?':
8389 case '#': case '&': case '!':
8391 case '0': case '1': case '2': case '3': case '4':
8392 case 'm': case '<': case '>': case 'V': case 'o':
8393 case 'E': case 'F': case 'G': case 'H':
8394 case 's': case 'i': case 'n':
8395 case 'I': case 'J': case 'K': case 'L':
8396 case 'M': case 'N': case 'O': case 'P':
8397 #ifdef EXTRA_CONSTRAINT
8398 case 'Q': case 'R': case 'S': case 'T': case 'U':
8401 /* These don't say anything we care about. */
8405 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8410 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER (c)];
8413 case ',': case '\0':
8414 /* See if REGNO fits this alternative, and set it up as the
8415 replacement register if we don't have one for this
8417 if (op_alt_regno[i][j] == -1
8418 && reg_fits_class_p (gen_rtx_REG (mode, regno), class,
8421 alternative_nregs[j]++;
8422 op_alt_regno[i][j] = regno;
8434 /* Record all alternatives which are better or equal to the currently
8435 matching one in the alternative_order array. */
8436 for (i = j = 0; i < n_alternatives; i++)
8437 if (alternative_reject[i] <= alternative_reject[which_alternative])
8438 alternative_order[j++] = i;
8441 /* Sort it. Given a small number of alternatives, a dumb algorithm
8442 won't hurt too much. */
8443 for (i = 0; i < n_alternatives - 1; i++)
8446 int best_reject = alternative_reject[alternative_order[i]];
8447 int best_nregs = alternative_nregs[alternative_order[i]];
8450 for (j = i + 1; j < n_alternatives; j++)
8452 int this_reject = alternative_reject[alternative_order[j]];
8453 int this_nregs = alternative_nregs[alternative_order[j]];
8455 if (this_reject < best_reject
8456 || (this_reject == best_reject && this_nregs < best_nregs))
8459 best_reject = this_reject;
8460 best_nregs = this_nregs;
8464 tmp = alternative_order[best];
8465 alternative_order[best] = alternative_order[i];
8466 alternative_order[i] = tmp;
8469 /* Substitute the operands as determined by op_alt_regno for the best
8471 j = alternative_order[0];
8472 CLEAR_HARD_REG_SET (no_longer_dead_regs);
8474 /* Pop back to the real obstacks while changing the insn. */
8477 for (i = 0; i < n_operands; i++)
8479 enum machine_mode mode = insn_operand_mode[insn_code_number][i];
8480 if (op_alt_regno[i][j] == -1)
8483 reload_cse_no_longer_dead (op_alt_regno[i][j], mode);
8484 validate_change (insn, recog_operand_loc[i],
8485 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8488 for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--)
8490 int op = recog_dup_num[i];
8491 enum machine_mode mode = insn_operand_mode[insn_code_number][op];
8493 if (op_alt_regno[op][j] == -1)
8496 reload_cse_no_longer_dead (op_alt_regno[op][j], mode);
8497 validate_change (insn, recog_dup_loc[i],
8498 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8501 /* Go back to the obstack we are using for temporary
8503 push_obstacks (&reload_obstack, &reload_obstack);
8505 return apply_change_group ();
8511 /* These two variables are used to pass information from
8512 reload_cse_record_set to reload_cse_check_clobber. */
8514 static int reload_cse_check_clobbered;
8515 static rtx reload_cse_check_src;
8517 /* See if DEST overlaps with RELOAD_CSE_CHECK_SRC. If it does, set
8518 RELOAD_CSE_CHECK_CLOBBERED. This is called via note_stores. The
8519 second argument, which is passed by note_stores, is ignored. */
8522 reload_cse_check_clobber (dest, ignore)
8526 if (reg_overlap_mentioned_p (dest, reload_cse_check_src))
8527 reload_cse_check_clobbered = 1;
8530 /* Record the result of a SET instruction. SET is the set pattern.
8531 BODY is the pattern of the insn that it came from. */
8534 reload_cse_record_set (set, body)
8540 enum machine_mode dest_mode;
8542 dest = SET_DEST (set);
8543 src = SET_SRC (set);
8544 dreg = true_regnum (dest);
8545 sreg = true_regnum (src);
8546 dest_mode = GET_MODE (dest);
8548 /* Some machines don't define AUTO_INC_DEC, but they still use push
8549 instructions. We need to catch that case here in order to
8550 invalidate the stack pointer correctly. Note that invalidating
8551 the stack pointer is different from invalidating DEST. */
8553 while (GET_CODE (x) == SUBREG
8554 || GET_CODE (x) == ZERO_EXTRACT
8555 || GET_CODE (x) == SIGN_EXTRACT
8556 || GET_CODE (x) == STRICT_LOW_PART)
8558 if (push_operand (x, GET_MODE (x)))
8560 reload_cse_invalidate_rtx (stack_pointer_rtx, NULL_RTX);
8561 reload_cse_invalidate_rtx (dest, NULL_RTX);
8565 /* We can only handle an assignment to a register, or a store of a
8566 register to a memory location. For other cases, we just clobber
8567 the destination. We also have to just clobber if there are side
8568 effects in SRC or DEST. */
8569 if ((dreg < 0 && GET_CODE (dest) != MEM)
8570 || side_effects_p (src)
8571 || side_effects_p (dest))
8573 reload_cse_invalidate_rtx (dest, NULL_RTX);
8578 /* We don't try to handle values involving CC, because it's a pain
8579 to keep track of when they have to be invalidated. */
8580 if (reg_mentioned_p (cc0_rtx, src)
8581 || reg_mentioned_p (cc0_rtx, dest))
8583 reload_cse_invalidate_rtx (dest, NULL_RTX);
8588 /* If BODY is a PARALLEL, then we need to see whether the source of
8589 SET is clobbered by some other instruction in the PARALLEL. */
8590 if (GET_CODE (body) == PARALLEL)
8594 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8598 x = XVECEXP (body, 0, i);
8602 reload_cse_check_clobbered = 0;
8603 reload_cse_check_src = src;
8604 note_stores (x, reload_cse_check_clobber);
8605 if (reload_cse_check_clobbered)
8607 reload_cse_invalidate_rtx (dest, NULL_RTX);
8617 /* This is an assignment to a register. Update the value we
8618 have stored for the register. */
8623 /* This is a copy from one register to another. Any values
8624 which were valid for SREG are now valid for DREG. If the
8625 mode changes, we use gen_lowpart_common to extract only
8626 the part of the value that is copied. */
8627 reg_values[dreg] = 0;
8628 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
8632 if (XEXP (x, 0) == 0)
8634 if (dest_mode == GET_MODE (XEXP (x, 0)))
8636 else if (GET_MODE_BITSIZE (dest_mode)
8637 > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
8640 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
8642 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, tmp,
8647 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, src, NULL_RTX);
8649 /* We've changed DREG, so invalidate any values held by other
8650 registers that depend upon it. */
8651 reload_cse_invalidate_regno (dreg, dest_mode, 0);
8653 /* If this assignment changes more than one hard register,
8654 forget anything we know about the others. */
8655 for (i = 1; i < HARD_REGNO_NREGS (dreg, dest_mode); i++)
8656 reg_values[dreg + i] = 0;
8658 else if (GET_CODE (dest) == MEM)
8660 /* Invalidate conflicting memory locations. */
8661 reload_cse_invalidate_mem (dest);
8663 /* If we're storing a register to memory, add DEST to the list
8665 if (sreg >= 0 && ! side_effects_p (dest))
8666 reg_values[sreg] = gen_rtx_EXPR_LIST (dest_mode, dest,
8671 /* We should have bailed out earlier. */
OSDN Git Service
