1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "insn-flags.h"
32 #include "insn-codes.h"
37 #include "basic-block.h"
45 #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY
46 #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
49 /* This file contains the reload pass of the compiler, which is
50 run after register allocation has been done. It checks that
51 each insn is valid (operands required to be in registers really
52 are in registers of the proper class) and fixes up invalid ones
53 by copying values temporarily into registers for the insns
56 The results of register allocation are described by the vector
57 reg_renumber; the insns still contain pseudo regs, but reg_renumber
58 can be used to find which hard reg, if any, a pseudo reg is in.
60 The technique we always use is to free up a few hard regs that are
61 called ``reload regs'', and for each place where a pseudo reg
62 must be in a hard reg, copy it temporarily into one of the reload regs.
64 Reload regs are allocated locally for every instruction that needs
65 reloads. When there are pseudos which are allocated to a register that
66 has been chosen as a reload reg, such pseudos must be ``spilled''.
67 This means that they go to other hard regs, or to stack slots if no other
68 available hard regs can be found. Spilling can invalidate more
69 insns, requiring additional need for reloads, so we must keep checking
70 until the process stabilizes.
72 For machines with different classes of registers, we must keep track
73 of the register class needed for each reload, and make sure that
74 we allocate enough reload registers of each class.
76 The file reload.c contains the code that checks one insn for
77 validity and reports the reloads that it needs. This file
78 is in charge of scanning the entire rtl code, accumulating the
79 reload needs, spilling, assigning reload registers to use for
80 fixing up each insn, and generating the new insns to copy values
81 into the reload registers. */
83 #ifndef REGISTER_MOVE_COST
84 #define REGISTER_MOVE_COST(m, x, y) 2
88 #define LOCAL_REGNO(REGNO) 0
91 /* During reload_as_needed, element N contains a REG rtx for the hard reg
92 into which reg N has been reloaded (perhaps for a previous insn). */
93 static rtx *reg_last_reload_reg;
95 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
96 for an output reload that stores into reg N. */
97 static char *reg_has_output_reload;
99 /* Indicates which hard regs are reload-registers for an output reload
100 in the current insn. */
101 static HARD_REG_SET reg_is_output_reload;
103 /* Element N is the constant value to which pseudo reg N is equivalent,
104 or zero if pseudo reg N is not equivalent to a constant.
105 find_reloads looks at this in order to replace pseudo reg N
106 with the constant it stands for. */
107 rtx *reg_equiv_constant;
109 /* Element N is a memory location to which pseudo reg N is equivalent,
110 prior to any register elimination (such as frame pointer to stack
111 pointer). Depending on whether or not it is a valid address, this value
112 is transferred to either reg_equiv_address or reg_equiv_mem. */
113 rtx *reg_equiv_memory_loc;
115 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
116 This is used when the address is not valid as a memory address
117 (because its displacement is too big for the machine.) */
118 rtx *reg_equiv_address;
120 /* Element N is the memory slot to which pseudo reg N is equivalent,
121 or zero if pseudo reg N is not equivalent to a memory slot. */
124 /* Widest width in which each pseudo reg is referred to (via subreg). */
125 static unsigned int *reg_max_ref_width;
127 /* Element N is the list of insns that initialized reg N from its equivalent
128 constant or memory slot. */
129 static rtx *reg_equiv_init;
131 /* Vector to remember old contents of reg_renumber before spilling. */
132 static short *reg_old_renumber;
134 /* During reload_as_needed, element N contains the last pseudo regno reloaded
135 into hard register N. If that pseudo reg occupied more than one register,
136 reg_reloaded_contents points to that pseudo for each spill register in
137 use; all of these must remain set for an inheritance to occur. */
138 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
140 /* During reload_as_needed, element N contains the insn for which
141 hard register N was last used. Its contents are significant only
142 when reg_reloaded_valid is set for this register. */
143 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
145 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
146 static HARD_REG_SET reg_reloaded_valid;
147 /* Indicate if the register was dead at the end of the reload.
148 This is only valid if reg_reloaded_contents is set and valid. */
149 static HARD_REG_SET reg_reloaded_dead;
151 /* Number of spill-regs so far; number of valid elements of spill_regs. */
154 /* In parallel with spill_regs, contains REG rtx's for those regs.
155 Holds the last rtx used for any given reg, or 0 if it has never
156 been used for spilling yet. This rtx is reused, provided it has
158 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
160 /* In parallel with spill_regs, contains nonzero for a spill reg
161 that was stored after the last time it was used.
162 The precise value is the insn generated to do the store. */
163 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
165 /* This is the register that was stored with spill_reg_store. This is a
166 copy of reload_out / reload_out_reg when the value was stored; if
167 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
168 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
170 /* This table is the inverse mapping of spill_regs:
171 indexed by hard reg number,
172 it contains the position of that reg in spill_regs,
173 or -1 for something that is not in spill_regs.
175 ?!? This is no longer accurate. */
176 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
178 /* This reg set indicates registers that can't be used as spill registers for
179 the currently processed insn. These are the hard registers which are live
180 during the insn, but not allocated to pseudos, as well as fixed
182 static HARD_REG_SET bad_spill_regs;
184 /* These are the hard registers that can't be used as spill register for any
185 insn. This includes registers used for user variables and registers that
186 we can't eliminate. A register that appears in this set also can't be used
187 to retry register allocation. */
188 static HARD_REG_SET bad_spill_regs_global;
190 /* Describes order of use of registers for reloading
191 of spilled pseudo-registers. `n_spills' is the number of
192 elements that are actually valid; new ones are added at the end.
194 Both spill_regs and spill_reg_order are used on two occasions:
195 once during find_reload_regs, where they keep track of the spill registers
196 for a single insn, but also during reload_as_needed where they show all
197 the registers ever used by reload. For the latter case, the information
198 is calculated during finish_spills. */
199 static short spill_regs[FIRST_PSEUDO_REGISTER];
201 /* This vector of reg sets indicates, for each pseudo, which hard registers
202 may not be used for retrying global allocation because the register was
203 formerly spilled from one of them. If we allowed reallocating a pseudo to
204 a register that it was already allocated to, reload might not
206 static HARD_REG_SET *pseudo_previous_regs;
208 /* This vector of reg sets indicates, for each pseudo, which hard
209 registers may not be used for retrying global allocation because they
210 are used as spill registers during one of the insns in which the
212 static HARD_REG_SET *pseudo_forbidden_regs;
214 /* All hard regs that have been used as spill registers for any insn are
215 marked in this set. */
216 static HARD_REG_SET used_spill_regs;
218 /* Index of last register assigned as a spill register. We allocate in
219 a round-robin fashion. */
220 static int last_spill_reg;
222 /* Nonzero if indirect addressing is supported on the machine; this means
223 that spilling (REG n) does not require reloading it into a register in
224 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
225 value indicates the level of indirect addressing supported, e.g., two
226 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
228 static char spill_indirect_levels;
230 /* Nonzero if indirect addressing is supported when the innermost MEM is
231 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
232 which these are valid is the same as spill_indirect_levels, above. */
233 char indirect_symref_ok;
235 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
236 char double_reg_address_ok;
238 /* Record the stack slot for each spilled hard register. */
239 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
241 /* Width allocated so far for that stack slot. */
242 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
244 /* Record which pseudos needed to be spilled. */
245 static regset_head spilled_pseudos;
247 /* Used for communication between order_regs_for_reload and count_pseudo.
248 Used to avoid counting one pseudo twice. */
249 static regset_head pseudos_counted;
251 /* First uid used by insns created by reload in this function.
252 Used in find_equiv_reg. */
253 int reload_first_uid;
255 /* Flag set by local-alloc or global-alloc if anything is live in
256 a call-clobbered reg across calls. */
257 int caller_save_needed;
259 /* Set to 1 while reload_as_needed is operating.
260 Required by some machines to handle any generated moves differently. */
261 int reload_in_progress = 0;
263 /* These arrays record the insn_code of insns that may be needed to
264 perform input and output reloads of special objects. They provide a
265 place to pass a scratch register. */
266 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
267 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
269 /* This obstack is used for allocation of rtl during register elimination.
270 The allocated storage can be freed once find_reloads has processed the
272 struct obstack reload_obstack;
274 /* Points to the beginning of the reload_obstack. All insn_chain structures
275 are allocated first. */
276 char *reload_startobj;
278 /* The point after all insn_chain structures. Used to quickly deallocate
279 memory allocated in copy_reloads during calculate_needs_all_insns. */
280 char *reload_firstobj;
282 /* This points before all local rtl generated by register elimination.
283 Used to quickly free all memory after processing one insn. */
284 static char *reload_insn_firstobj;
286 #define obstack_chunk_alloc xmalloc
287 #define obstack_chunk_free free
289 /* List of insn_chain instructions, one for every insn that reload needs to
291 struct insn_chain *reload_insn_chain;
294 extern tree current_function_decl;
296 extern union tree_node *current_function_decl;
299 /* List of all insns needing reloads. */
300 static struct insn_chain *insns_need_reload;
302 /* This structure is used to record information about register eliminations.
303 Each array entry describes one possible way of eliminating a register
304 in favor of another. If there is more than one way of eliminating a
305 particular register, the most preferred should be specified first. */
309 int from; /* Register number to be eliminated. */
310 int to; /* Register number used as replacement. */
311 int initial_offset; /* Initial difference between values. */
312 int can_eliminate; /* Non-zero if this elimination can be done. */
313 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
314 insns made by reload. */
315 int offset; /* Current offset between the two regs. */
316 int previous_offset; /* Offset at end of previous insn. */
317 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
318 rtx from_rtx; /* REG rtx for the register to be eliminated.
319 We cannot simply compare the number since
320 we might then spuriously replace a hard
321 register corresponding to a pseudo
322 assigned to the reg to be eliminated. */
323 rtx to_rtx; /* REG rtx for the replacement. */
326 static struct elim_table *reg_eliminate = 0;
328 /* This is an intermediate structure to initialize the table. It has
329 exactly the members provided by ELIMINABLE_REGS. */
330 static struct elim_table_1
334 } reg_eliminate_1[] =
336 /* If a set of eliminable registers was specified, define the table from it.
337 Otherwise, default to the normal case of the frame pointer being
338 replaced by the stack pointer. */
340 #ifdef ELIMINABLE_REGS
343 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
346 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
348 /* Record the number of pending eliminations that have an offset not equal
349 to their initial offset. If non-zero, we use a new copy of each
350 replacement result in any insns encountered. */
351 int num_not_at_initial_offset;
353 /* Count the number of registers that we may be able to eliminate. */
354 static int num_eliminable;
355 /* And the number of registers that are equivalent to a constant that
356 can be eliminated to frame_pointer / arg_pointer + constant. */
357 static int num_eliminable_invariants;
359 /* For each label, we record the offset of each elimination. If we reach
360 a label by more than one path and an offset differs, we cannot do the
361 elimination. This information is indexed by the number of the label.
362 The first table is an array of flags that records whether we have yet
363 encountered a label and the second table is an array of arrays, one
364 entry in the latter array for each elimination. */
366 static char *offsets_known_at;
367 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
369 /* Number of labels in the current function. */
371 static int num_labels;
373 static void replace_pseudos_in_call_usage PARAMS((rtx *,
376 static void maybe_fix_stack_asms PARAMS ((void));
377 static void copy_reloads PARAMS ((struct insn_chain *));
378 static void calculate_needs_all_insns PARAMS ((int));
379 static int find_reg PARAMS ((struct insn_chain *, int));
380 static void find_reload_regs PARAMS ((struct insn_chain *));
381 static void select_reload_regs PARAMS ((void));
382 static void delete_caller_save_insns PARAMS ((void));
384 static void spill_failure PARAMS ((rtx, enum reg_class));
385 static void count_spilled_pseudo PARAMS ((int, int, int));
386 static void delete_dead_insn PARAMS ((rtx));
387 static void alter_reg PARAMS ((int, int));
388 static void set_label_offsets PARAMS ((rtx, rtx, int));
389 static void check_eliminable_occurrences PARAMS ((rtx));
390 static void elimination_effects PARAMS ((rtx, enum machine_mode));
391 static int eliminate_regs_in_insn PARAMS ((rtx, int));
392 static void update_eliminable_offsets PARAMS ((void));
393 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
394 static void set_initial_elim_offsets PARAMS ((void));
395 static void verify_initial_elim_offsets PARAMS ((void));
396 static void set_initial_label_offsets PARAMS ((void));
397 static void set_offsets_for_label PARAMS ((rtx));
398 static void init_elim_table PARAMS ((void));
399 static void update_eliminables PARAMS ((HARD_REG_SET *));
400 static void spill_hard_reg PARAMS ((unsigned int, int));
401 static int finish_spills PARAMS ((int));
402 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
403 static void scan_paradoxical_subregs PARAMS ((rtx));
404 static void count_pseudo PARAMS ((int));
405 static void order_regs_for_reload PARAMS ((struct insn_chain *));
406 static void reload_as_needed PARAMS ((int));
407 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
408 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
409 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
412 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
415 static int reload_reg_free_p PARAMS ((unsigned int, int,
417 static int reload_reg_free_for_value_p PARAMS ((int, int, int,
419 rtx, rtx, int, int));
420 static int free_for_value_p PARAMS ((int, enum machine_mode, int,
421 enum reload_type, rtx, rtx,
423 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
425 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
427 static int conflicts_with_override PARAMS ((rtx));
428 static void failed_reload PARAMS ((rtx, int));
429 static int set_reload_reg PARAMS ((int, int));
430 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
431 static void choose_reload_regs PARAMS ((struct insn_chain *));
432 static void merge_assigned_reloads PARAMS ((rtx));
433 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
434 struct reload *, rtx, int));
435 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
436 struct reload *, int));
437 static void do_input_reload PARAMS ((struct insn_chain *,
438 struct reload *, int));
439 static void do_output_reload PARAMS ((struct insn_chain *,
440 struct reload *, int));
441 static void emit_reload_insns PARAMS ((struct insn_chain *));
442 static void delete_output_reload PARAMS ((rtx, int, int));
443 static void delete_address_reloads PARAMS ((rtx, rtx));
444 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
445 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
446 static int constraint_accepts_reg_p PARAMS ((const char *, rtx));
447 static void reload_cse_regs_1 PARAMS ((rtx));
448 static int reload_cse_noop_set_p PARAMS ((rtx));
449 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
450 static int reload_cse_simplify_operands PARAMS ((rtx));
451 static void reload_combine PARAMS ((void));
452 static void reload_combine_note_use PARAMS ((rtx *, rtx));
453 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
454 static void reload_cse_move2add PARAMS ((rtx));
455 static void move2add_note_store PARAMS ((rtx, rtx, void *));
457 static void add_auto_inc_notes PARAMS ((rtx, rtx));
459 static HOST_WIDE_INT sext_for_mode PARAMS ((enum machine_mode,
461 static void failed_reload PARAMS ((rtx, int));
462 static int set_reload_reg PARAMS ((int, int));
463 static void reload_cse_delete_noop_set PARAMS ((rtx, rtx));
464 static void reload_cse_simplify PARAMS ((rtx));
465 extern void dump_needs PARAMS ((struct insn_chain *));
467 /* Initialize the reload pass once per compilation. */
474 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
475 Set spill_indirect_levels to the number of levels such addressing is
476 permitted, zero if it is not permitted at all. */
479 = gen_rtx_MEM (Pmode,
482 LAST_VIRTUAL_REGISTER + 1),
484 spill_indirect_levels = 0;
486 while (memory_address_p (QImode, tem))
488 spill_indirect_levels++;
489 tem = gen_rtx_MEM (Pmode, tem);
492 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
494 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
495 indirect_symref_ok = memory_address_p (QImode, tem);
497 /* See if reg+reg is a valid (and offsettable) address. */
499 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
501 tem = gen_rtx_PLUS (Pmode,
502 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
503 gen_rtx_REG (Pmode, i));
505 /* This way, we make sure that reg+reg is an offsettable address. */
506 tem = plus_constant (tem, 4);
508 if (memory_address_p (QImode, tem))
510 double_reg_address_ok = 1;
515 /* Initialize obstack for our rtl allocation. */
516 gcc_obstack_init (&reload_obstack);
517 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
519 INIT_REG_SET (&spilled_pseudos);
520 INIT_REG_SET (&pseudos_counted);
523 /* List of insn chains that are currently unused. */
524 static struct insn_chain *unused_insn_chains = 0;
526 /* Allocate an empty insn_chain structure. */
530 struct insn_chain *c;
532 if (unused_insn_chains == 0)
534 c = (struct insn_chain *)
535 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
536 INIT_REG_SET (&c->live_throughout);
537 INIT_REG_SET (&c->dead_or_set);
541 c = unused_insn_chains;
542 unused_insn_chains = c->next;
544 c->is_caller_save_insn = 0;
545 c->need_operand_change = 0;
551 /* Small utility function to set all regs in hard reg set TO which are
552 allocated to pseudos in regset FROM. */
555 compute_use_by_pseudos (to, from)
561 EXECUTE_IF_SET_IN_REG_SET
562 (from, FIRST_PSEUDO_REGISTER, regno,
564 int r = reg_renumber[regno];
569 /* reload_combine uses the information from
570 BASIC_BLOCK->global_live_at_start, which might still
571 contain registers that have not actually been allocated
572 since they have an equivalence. */
573 if (! reload_completed)
578 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
580 SET_HARD_REG_BIT (*to, r + nregs);
585 /* Replace all pseudos found in LOC with their corresponding
589 replace_pseudos_in_call_usage (loc, mem_mode, usage)
591 enum machine_mode mem_mode;
605 int regno = REGNO (x);
607 if (regno < FIRST_PSEUDO_REGISTER)
610 x = eliminate_regs (x, mem_mode, usage);
614 replace_pseudos_in_call_usage (loc, mem_mode, usage);
618 if (reg_equiv_constant[regno])
619 *loc = reg_equiv_constant[regno];
620 else if (reg_equiv_mem[regno])
621 *loc = reg_equiv_mem[regno];
622 else if (reg_equiv_address[regno])
623 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
624 else if (GET_CODE (regno_reg_rtx[regno]) != REG
625 || REGNO (regno_reg_rtx[regno]) != regno)
626 *loc = regno_reg_rtx[regno];
632 else if (code == MEM)
634 replace_pseudos_in_call_usage (& XEXP (x, 0), GET_MODE (x), usage);
638 /* Process each of our operands recursively. */
639 fmt = GET_RTX_FORMAT (code);
640 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
642 replace_pseudos_in_call_usage (&XEXP (x, i), mem_mode, usage);
643 else if (*fmt == 'E')
644 for (j = 0; j < XVECLEN (x, i); j++)
645 replace_pseudos_in_call_usage (& XVECEXP (x, i, j), mem_mode, usage);
649 /* Global variables used by reload and its subroutines. */
651 /* Set during calculate_needs if an insn needs register elimination. */
652 static int something_needs_elimination;
653 /* Set during calculate_needs if an insn needs an operand changed. */
654 int something_needs_operands_changed;
656 /* Nonzero means we couldn't get enough spill regs. */
659 /* Main entry point for the reload pass.
661 FIRST is the first insn of the function being compiled.
663 GLOBAL nonzero means we were called from global_alloc
664 and should attempt to reallocate any pseudoregs that we
665 displace from hard regs we will use for reloads.
666 If GLOBAL is zero, we do not have enough information to do that,
667 so any pseudo reg that is spilled must go to the stack.
669 Return value is nonzero if reload failed
670 and we must not do any more for this function. */
673 reload (first, global)
679 register struct elim_table *ep;
681 /* The two pointers used to track the true location of the memory used
682 for label offsets. */
683 char *real_known_ptr = NULL_PTR;
684 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
686 /* Make sure even insns with volatile mem refs are recognizable. */
691 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
693 /* Make sure that the last insn in the chain
694 is not something that needs reloading. */
695 emit_note (NULL_PTR, NOTE_INSN_DELETED);
697 /* Enable find_equiv_reg to distinguish insns made by reload. */
698 reload_first_uid = get_max_uid ();
700 #ifdef SECONDARY_MEMORY_NEEDED
701 /* Initialize the secondary memory table. */
702 clear_secondary_mem ();
705 /* We don't have a stack slot for any spill reg yet. */
706 memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot);
707 memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
709 /* Initialize the save area information for caller-save, in case some
713 /* Compute which hard registers are now in use
714 as homes for pseudo registers.
715 This is done here rather than (eg) in global_alloc
716 because this point is reached even if not optimizing. */
717 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
720 /* A function that receives a nonlocal goto must save all call-saved
722 if (current_function_has_nonlocal_label)
723 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
724 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
725 regs_ever_live[i] = 1;
727 /* Find all the pseudo registers that didn't get hard regs
728 but do have known equivalent constants or memory slots.
729 These include parameters (known equivalent to parameter slots)
730 and cse'd or loop-moved constant memory addresses.
732 Record constant equivalents in reg_equiv_constant
733 so they will be substituted by find_reloads.
734 Record memory equivalents in reg_mem_equiv so they can
735 be substituted eventually by altering the REG-rtx's. */
737 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
738 reg_equiv_memory_loc = (rtx *) xcalloc (max_regno, sizeof (rtx));
739 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
740 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
741 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
742 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
743 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
744 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
745 pseudo_forbidden_regs
746 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
748 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
750 CLEAR_HARD_REG_SET (bad_spill_regs_global);
752 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
753 Also find all paradoxical subregs and find largest such for each pseudo.
754 On machines with small register classes, record hard registers that
755 are used for user variables. These can never be used for spills.
756 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
757 caller-saved registers must be marked live. */
759 num_eliminable_invariants = 0;
760 for (insn = first; insn; insn = NEXT_INSN (insn))
762 rtx set = single_set (insn);
764 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
765 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
766 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
767 if (! call_used_regs[i])
768 regs_ever_live[i] = 1;
770 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
772 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
774 #ifdef LEGITIMATE_PIC_OPERAND_P
775 && (! function_invariant_p (XEXP (note, 0))
777 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
781 rtx x = XEXP (note, 0);
782 i = REGNO (SET_DEST (set));
783 if (i > LAST_VIRTUAL_REGISTER)
785 if (GET_CODE (x) == MEM)
787 /* If the operand is a PLUS, the MEM may be shared,
788 so make sure we have an unshared copy here. */
789 if (GET_CODE (XEXP (x, 0)) == PLUS)
792 reg_equiv_memory_loc[i] = x;
794 else if (function_invariant_p (x))
796 if (GET_CODE (x) == PLUS)
798 /* This is PLUS of frame pointer and a constant,
799 and might be shared. Unshare it. */
800 reg_equiv_constant[i] = copy_rtx (x);
801 num_eliminable_invariants++;
803 else if (x == frame_pointer_rtx
804 || x == arg_pointer_rtx)
806 reg_equiv_constant[i] = x;
807 num_eliminable_invariants++;
809 else if (LEGITIMATE_CONSTANT_P (x))
810 reg_equiv_constant[i] = x;
812 reg_equiv_memory_loc[i]
813 = force_const_mem (GET_MODE (SET_DEST (set)), x);
818 /* If this register is being made equivalent to a MEM
819 and the MEM is not SET_SRC, the equivalencing insn
820 is one with the MEM as a SET_DEST and it occurs later.
821 So don't mark this insn now. */
822 if (GET_CODE (x) != MEM
823 || rtx_equal_p (SET_SRC (set), x))
825 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
830 /* If this insn is setting a MEM from a register equivalent to it,
831 this is the equivalencing insn. */
832 else if (set && GET_CODE (SET_DEST (set)) == MEM
833 && GET_CODE (SET_SRC (set)) == REG
834 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
835 && rtx_equal_p (SET_DEST (set),
836 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
837 reg_equiv_init[REGNO (SET_SRC (set))]
838 = gen_rtx_INSN_LIST (VOIDmode, insn,
839 reg_equiv_init[REGNO (SET_SRC (set))]);
842 scan_paradoxical_subregs (PATTERN (insn));
847 num_labels = max_label_num () - get_first_label_num ();
849 /* Allocate the tables used to store offset information at labels. */
850 /* We used to use alloca here, but the size of what it would try to
851 allocate would occasionally cause it to exceed the stack limit and
852 cause a core dump. */
853 real_known_ptr = xmalloc (num_labels);
855 = (int (*)[NUM_ELIMINABLE_REGS])
856 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
858 offsets_known_at = real_known_ptr - get_first_label_num ();
860 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
862 /* Alter each pseudo-reg rtx to contain its hard reg number.
863 Assign stack slots to the pseudos that lack hard regs or equivalents.
864 Do not touch virtual registers. */
866 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
869 /* If we have some registers we think can be eliminated, scan all insns to
870 see if there is an insn that sets one of these registers to something
871 other than itself plus a constant. If so, the register cannot be
872 eliminated. Doing this scan here eliminates an extra pass through the
873 main reload loop in the most common case where register elimination
875 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
876 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
877 || GET_CODE (insn) == CALL_INSN)
878 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
880 maybe_fix_stack_asms ();
882 insns_need_reload = 0;
883 something_needs_elimination = 0;
885 /* Initialize to -1, which means take the first spill register. */
888 /* Spill any hard regs that we know we can't eliminate. */
889 CLEAR_HARD_REG_SET (used_spill_regs);
890 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
891 if (! ep->can_eliminate)
892 spill_hard_reg (ep->from, 1);
894 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
895 if (frame_pointer_needed)
896 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
898 finish_spills (global);
900 /* From now on, we may need to generate moves differently. We may also
901 allow modifications of insns which cause them to not be recognized.
902 Any such modifications will be cleaned up during reload itself. */
903 reload_in_progress = 1;
905 /* This loop scans the entire function each go-round
906 and repeats until one repetition spills no additional hard regs. */
909 int something_changed;
912 HOST_WIDE_INT starting_frame_size;
914 /* Round size of stack frame to stack_alignment_needed. This must be done
915 here because the stack size may be a part of the offset computation
916 for register elimination, and there might have been new stack slots
917 created in the last iteration of this loop. */
918 if (cfun->stack_alignment_needed)
919 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
921 starting_frame_size = get_frame_size ();
923 set_initial_elim_offsets ();
924 set_initial_label_offsets ();
926 /* For each pseudo register that has an equivalent location defined,
927 try to eliminate any eliminable registers (such as the frame pointer)
928 assuming initial offsets for the replacement register, which
931 If the resulting location is directly addressable, substitute
932 the MEM we just got directly for the old REG.
934 If it is not addressable but is a constant or the sum of a hard reg
935 and constant, it is probably not addressable because the constant is
936 out of range, in that case record the address; we will generate
937 hairy code to compute the address in a register each time it is
938 needed. Similarly if it is a hard register, but one that is not
939 valid as an address register.
941 If the location is not addressable, but does not have one of the
942 above forms, assign a stack slot. We have to do this to avoid the
943 potential of producing lots of reloads if, e.g., a location involves
944 a pseudo that didn't get a hard register and has an equivalent memory
945 location that also involves a pseudo that didn't get a hard register.
947 Perhaps at some point we will improve reload_when_needed handling
948 so this problem goes away. But that's very hairy. */
950 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
951 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
953 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
955 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
957 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
958 else if (CONSTANT_P (XEXP (x, 0))
959 || (GET_CODE (XEXP (x, 0)) == REG
960 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
961 || (GET_CODE (XEXP (x, 0)) == PLUS
962 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
963 && (REGNO (XEXP (XEXP (x, 0), 0))
964 < FIRST_PSEUDO_REGISTER)
965 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
966 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
969 /* Make a new stack slot. Then indicate that something
970 changed so we go back and recompute offsets for
971 eliminable registers because the allocation of memory
972 below might change some offset. reg_equiv_{mem,address}
973 will be set up for this pseudo on the next pass around
975 reg_equiv_memory_loc[i] = 0;
976 reg_equiv_init[i] = 0;
981 if (caller_save_needed)
984 /* If we allocated another stack slot, redo elimination bookkeeping. */
985 if (starting_frame_size != get_frame_size ())
988 if (caller_save_needed)
990 save_call_clobbered_regs ();
991 /* That might have allocated new insn_chain structures. */
992 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
995 calculate_needs_all_insns (global);
997 CLEAR_REG_SET (&spilled_pseudos);
1000 something_changed = 0;
1002 /* If we allocated any new memory locations, make another pass
1003 since it might have changed elimination offsets. */
1004 if (starting_frame_size != get_frame_size ())
1005 something_changed = 1;
1008 HARD_REG_SET to_spill;
1009 CLEAR_HARD_REG_SET (to_spill);
1010 update_eliminables (&to_spill);
1011 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1012 if (TEST_HARD_REG_BIT (to_spill, i))
1014 spill_hard_reg (i, 1);
1017 /* Regardless of the state of spills, if we previously had
1018 a register that we thought we could eliminate, but no can
1019 not eliminate, we must run another pass.
1021 Consider pseudos which have an entry in reg_equiv_* which
1022 reference an eliminable register. We must make another pass
1023 to update reg_equiv_* so that we do not substitute in the
1024 old value from when we thought the elimination could be
1026 something_changed = 1;
1030 select_reload_regs ();
1034 if (insns_need_reload != 0 || did_spill)
1035 something_changed |= finish_spills (global);
1037 if (! something_changed)
1040 if (caller_save_needed)
1041 delete_caller_save_insns ();
1043 obstack_free (&reload_obstack, reload_firstobj);
1046 /* If global-alloc was run, notify it of any register eliminations we have
1049 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1050 if (ep->can_eliminate)
1051 mark_elimination (ep->from, ep->to);
1053 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1054 If that insn didn't set the register (i.e., it copied the register to
1055 memory), just delete that insn instead of the equivalencing insn plus
1056 anything now dead. If we call delete_dead_insn on that insn, we may
1057 delete the insn that actually sets the register if the register dies
1058 there and that is incorrect. */
1060 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1062 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1065 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1067 rtx equiv_insn = XEXP (list, 0);
1068 if (GET_CODE (equiv_insn) == NOTE)
1070 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1071 delete_dead_insn (equiv_insn);
1074 PUT_CODE (equiv_insn, NOTE);
1075 NOTE_SOURCE_FILE (equiv_insn) = 0;
1076 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1082 /* Use the reload registers where necessary
1083 by generating move instructions to move the must-be-register
1084 values into or out of the reload registers. */
1086 if (insns_need_reload != 0 || something_needs_elimination
1087 || something_needs_operands_changed)
1089 HOST_WIDE_INT old_frame_size = get_frame_size ();
1091 reload_as_needed (global);
1093 if (old_frame_size != get_frame_size ())
1097 verify_initial_elim_offsets ();
1100 /* If we were able to eliminate the frame pointer, show that it is no
1101 longer live at the start of any basic block. If it ls live by
1102 virtue of being in a pseudo, that pseudo will be marked live
1103 and hence the frame pointer will be known to be live via that
1106 if (! frame_pointer_needed)
1107 for (i = 0; i < n_basic_blocks; i++)
1108 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1109 HARD_FRAME_POINTER_REGNUM);
1111 /* Come here (with failure set nonzero) if we can't get enough spill regs
1112 and we decide not to abort about it. */
1115 CLEAR_REG_SET (&spilled_pseudos);
1116 reload_in_progress = 0;
1118 /* Now eliminate all pseudo regs by modifying them into
1119 their equivalent memory references.
1120 The REG-rtx's for the pseudos are modified in place,
1121 so all insns that used to refer to them now refer to memory.
1123 For a reg that has a reg_equiv_address, all those insns
1124 were changed by reloading so that no insns refer to it any longer;
1125 but the DECL_RTL of a variable decl may refer to it,
1126 and if so this causes the debugging info to mention the variable. */
1128 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1133 int is_readonly = 0;
1135 if (reg_equiv_memory_loc[i])
1137 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1138 is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]);
1139 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1142 if (reg_equiv_mem[i])
1143 addr = XEXP (reg_equiv_mem[i], 0);
1145 if (reg_equiv_address[i])
1146 addr = reg_equiv_address[i];
1150 if (reg_renumber[i] < 0)
1152 rtx reg = regno_reg_rtx[i];
1153 PUT_CODE (reg, MEM);
1154 XEXP (reg, 0) = addr;
1155 REG_USERVAR_P (reg) = 0;
1156 RTX_UNCHANGING_P (reg) = is_readonly;
1157 MEM_IN_STRUCT_P (reg) = in_struct;
1158 MEM_SCALAR_P (reg) = is_scalar;
1159 /* We have no alias information about this newly created
1161 MEM_ALIAS_SET (reg) = 0;
1163 else if (reg_equiv_mem[i])
1164 XEXP (reg_equiv_mem[i], 0) = addr;
1168 /* We must set reload_completed now since the cleanup_subreg_operands call
1169 below will re-recognize each insn and reload may have generated insns
1170 which are only valid during and after reload. */
1171 reload_completed = 1;
1173 /* Make a pass over all the insns and delete all USEs which we inserted
1174 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1175 notes. Delete all CLOBBER insns that don't refer to the return value
1176 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1177 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1178 and regenerate REG_INC notes that may have been moved around. */
1180 for (insn = first; insn; insn = NEXT_INSN (insn))
1185 if (GET_CODE (insn) == CALL_INSN)
1186 replace_pseudos_in_call_usage (& CALL_INSN_FUNCTION_USAGE (insn),
1188 CALL_INSN_FUNCTION_USAGE (insn));
1190 if ((GET_CODE (PATTERN (insn)) == USE
1191 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1192 || (GET_CODE (PATTERN (insn)) == CLOBBER
1193 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1194 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1196 PUT_CODE (insn, NOTE);
1197 NOTE_SOURCE_FILE (insn) = 0;
1198 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1202 pnote = ®_NOTES (insn);
1205 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1206 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1207 || REG_NOTE_KIND (*pnote) == REG_INC
1208 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1209 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1210 *pnote = XEXP (*pnote, 1);
1212 pnote = &XEXP (*pnote, 1);
1216 add_auto_inc_notes (insn, PATTERN (insn));
1219 /* And simplify (subreg (reg)) if it appears as an operand. */
1220 cleanup_subreg_operands (insn);
1223 /* If we are doing stack checking, give a warning if this function's
1224 frame size is larger than we expect. */
1225 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1227 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1228 static int verbose_warned = 0;
1230 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1231 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1232 size += UNITS_PER_WORD;
1234 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1236 warning ("frame size too large for reliable stack checking");
1237 if (! verbose_warned)
1239 warning ("try reducing the number of local variables");
1245 /* Indicate that we no longer have known memory locations or constants. */
1246 if (reg_equiv_constant)
1247 free (reg_equiv_constant);
1248 reg_equiv_constant = 0;
1249 if (reg_equiv_memory_loc)
1250 free (reg_equiv_memory_loc);
1251 reg_equiv_memory_loc = 0;
1254 free (real_known_ptr);
1258 free (reg_equiv_mem);
1259 free (reg_equiv_init);
1260 free (reg_equiv_address);
1261 free (reg_max_ref_width);
1262 free (reg_old_renumber);
1263 free (pseudo_previous_regs);
1264 free (pseudo_forbidden_regs);
1266 CLEAR_HARD_REG_SET (used_spill_regs);
1267 for (i = 0; i < n_spills; i++)
1268 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1270 /* Free all the insn_chain structures at once. */
1271 obstack_free (&reload_obstack, reload_startobj);
1272 unused_insn_chains = 0;
1277 /* Yet another special case. Unfortunately, reg-stack forces people to
1278 write incorrect clobbers in asm statements. These clobbers must not
1279 cause the register to appear in bad_spill_regs, otherwise we'll call
1280 fatal_insn later. We clear the corresponding regnos in the live
1281 register sets to avoid this.
1282 The whole thing is rather sick, I'm afraid. */
1285 maybe_fix_stack_asms ()
1288 const char *constraints[MAX_RECOG_OPERANDS];
1289 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1290 struct insn_chain *chain;
1292 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1295 HARD_REG_SET clobbered, allowed;
1298 if (! INSN_P (chain->insn)
1299 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1301 pat = PATTERN (chain->insn);
1302 if (GET_CODE (pat) != PARALLEL)
1305 CLEAR_HARD_REG_SET (clobbered);
1306 CLEAR_HARD_REG_SET (allowed);
1308 /* First, make a mask of all stack regs that are clobbered. */
1309 for (i = 0; i < XVECLEN (pat, 0); i++)
1311 rtx t = XVECEXP (pat, 0, i);
1312 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1313 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1316 /* Get the operand values and constraints out of the insn. */
1317 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1318 constraints, operand_mode);
1320 /* For every operand, see what registers are allowed. */
1321 for (i = 0; i < noperands; i++)
1323 const char *p = constraints[i];
1324 /* For every alternative, we compute the class of registers allowed
1325 for reloading in CLS, and merge its contents into the reg set
1327 int cls = (int) NO_REGS;
1333 if (c == '\0' || c == ',' || c == '#')
1335 /* End of one alternative - mark the regs in the current
1336 class, and reset the class. */
1337 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1342 } while (c != '\0' && c != ',');
1350 case '=': case '+': case '*': case '%': case '?': case '!':
1351 case '0': case '1': case '2': case '3': case '4': case 'm':
1352 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1353 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1354 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1359 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1364 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1368 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1373 /* Those of the registers which are clobbered, but allowed by the
1374 constraints, must be usable as reload registers. So clear them
1375 out of the life information. */
1376 AND_HARD_REG_SET (allowed, clobbered);
1377 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1378 if (TEST_HARD_REG_BIT (allowed, i))
1380 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1381 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1388 /* Copy the global variables n_reloads and rld into the corresponding elts
1391 copy_reloads (chain)
1392 struct insn_chain *chain;
1394 chain->n_reloads = n_reloads;
1396 = (struct reload *) obstack_alloc (&reload_obstack,
1397 n_reloads * sizeof (struct reload));
1398 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1399 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1402 /* Walk the chain of insns, and determine for each whether it needs reloads
1403 and/or eliminations. Build the corresponding insns_need_reload list, and
1404 set something_needs_elimination as appropriate. */
1406 calculate_needs_all_insns (global)
1409 struct insn_chain **pprev_reload = &insns_need_reload;
1410 struct insn_chain *chain, *next = 0;
1412 something_needs_elimination = 0;
1414 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1415 for (chain = reload_insn_chain; chain != 0; chain = next)
1417 rtx insn = chain->insn;
1421 /* Clear out the shortcuts. */
1422 chain->n_reloads = 0;
1423 chain->need_elim = 0;
1424 chain->need_reload = 0;
1425 chain->need_operand_change = 0;
1427 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1428 include REG_LABEL), we need to see what effects this has on the
1429 known offsets at labels. */
1431 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1432 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1433 set_label_offsets (insn, insn, 0);
1437 rtx old_body = PATTERN (insn);
1438 int old_code = INSN_CODE (insn);
1439 rtx old_notes = REG_NOTES (insn);
1440 int did_elimination = 0;
1441 int operands_changed = 0;
1442 rtx set = single_set (insn);
1444 /* Skip insns that only set an equivalence. */
1445 if (set && GET_CODE (SET_DEST (set)) == REG
1446 && reg_renumber[REGNO (SET_DEST (set))] < 0
1447 && reg_equiv_constant[REGNO (SET_DEST (set))])
1450 /* If needed, eliminate any eliminable registers. */
1451 if (num_eliminable || num_eliminable_invariants)
1452 did_elimination = eliminate_regs_in_insn (insn, 0);
1454 /* Analyze the instruction. */
1455 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1456 global, spill_reg_order);
1458 /* If a no-op set needs more than one reload, this is likely
1459 to be something that needs input address reloads. We
1460 can't get rid of this cleanly later, and it is of no use
1461 anyway, so discard it now.
1462 We only do this when expensive_optimizations is enabled,
1463 since this complements reload inheritance / output
1464 reload deletion, and it can make debugging harder. */
1465 if (flag_expensive_optimizations && n_reloads > 1)
1467 rtx set = single_set (insn);
1469 && SET_SRC (set) == SET_DEST (set)
1470 && GET_CODE (SET_SRC (set)) == REG
1471 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1473 PUT_CODE (insn, NOTE);
1474 NOTE_SOURCE_FILE (insn) = 0;
1475 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1476 /* Delete it from the reload chain */
1478 chain->prev->next = next;
1480 reload_insn_chain = next;
1482 next->prev = chain->prev;
1483 chain->next = unused_insn_chains;
1484 unused_insn_chains = chain;
1489 update_eliminable_offsets ();
1491 /* Remember for later shortcuts which insns had any reloads or
1492 register eliminations. */
1493 chain->need_elim = did_elimination;
1494 chain->need_reload = n_reloads > 0;
1495 chain->need_operand_change = operands_changed;
1497 /* Discard any register replacements done. */
1498 if (did_elimination)
1500 obstack_free (&reload_obstack, reload_insn_firstobj);
1501 PATTERN (insn) = old_body;
1502 INSN_CODE (insn) = old_code;
1503 REG_NOTES (insn) = old_notes;
1504 something_needs_elimination = 1;
1507 something_needs_operands_changed |= operands_changed;
1511 copy_reloads (chain);
1512 *pprev_reload = chain;
1513 pprev_reload = &chain->next_need_reload;
1520 /* Comparison function for qsort to decide which of two reloads
1521 should be handled first. *P1 and *P2 are the reload numbers. */
1524 reload_reg_class_lower (r1p, r2p)
1528 register int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1531 /* Consider required reloads before optional ones. */
1532 t = rld[r1].optional - rld[r2].optional;
1536 /* Count all solitary classes before non-solitary ones. */
1537 t = ((reg_class_size[(int) rld[r2].class] == 1)
1538 - (reg_class_size[(int) rld[r1].class] == 1));
1542 /* Aside from solitaires, consider all multi-reg groups first. */
1543 t = rld[r2].nregs - rld[r1].nregs;
1547 /* Consider reloads in order of increasing reg-class number. */
1548 t = (int) rld[r1].class - (int) rld[r2].class;
1552 /* If reloads are equally urgent, sort by reload number,
1553 so that the results of qsort leave nothing to chance. */
1557 /* The cost of spilling each hard reg. */
1558 static int spill_cost[FIRST_PSEUDO_REGISTER];
1560 /* When spilling multiple hard registers, we use SPILL_COST for the first
1561 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1562 only the first hard reg for a multi-reg pseudo. */
1563 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1565 /* Update the spill cost arrays, considering that pseudo REG is live. */
1571 int n_refs = REG_N_REFS (reg);
1572 int r = reg_renumber[reg];
1575 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1576 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1579 SET_REGNO_REG_SET (&pseudos_counted, reg);
1584 spill_add_cost[r] += n_refs;
1586 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1588 spill_cost[r + nregs] += n_refs;
1591 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1592 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1595 order_regs_for_reload (chain)
1596 struct insn_chain *chain;
1599 HARD_REG_SET used_by_pseudos;
1600 HARD_REG_SET used_by_pseudos2;
1602 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1604 memset (spill_cost, 0, sizeof spill_cost);
1605 memset (spill_add_cost, 0, sizeof spill_add_cost);
1607 /* Count number of uses of each hard reg by pseudo regs allocated to it
1608 and then order them by decreasing use. First exclude hard registers
1609 that are live in or across this insn. */
1611 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1612 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1613 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1614 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1616 /* Now find out which pseudos are allocated to it, and update
1618 CLEAR_REG_SET (&pseudos_counted);
1620 EXECUTE_IF_SET_IN_REG_SET
1621 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1625 EXECUTE_IF_SET_IN_REG_SET
1626 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1630 CLEAR_REG_SET (&pseudos_counted);
1633 /* Vector of reload-numbers showing the order in which the reloads should
1635 static short reload_order[MAX_RELOADS];
1637 /* This is used to keep track of the spill regs used in one insn. */
1638 static HARD_REG_SET used_spill_regs_local;
1640 /* We decided to spill hard register SPILLED, which has a size of
1641 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1642 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1643 update SPILL_COST/SPILL_ADD_COST. */
1646 count_spilled_pseudo (spilled, spilled_nregs, reg)
1647 int spilled, spilled_nregs, reg;
1649 int r = reg_renumber[reg];
1650 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1652 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1653 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1656 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1658 spill_add_cost[r] -= REG_N_REFS (reg);
1660 spill_cost[r + nregs] -= REG_N_REFS (reg);
1663 /* Find reload register to use for reload number ORDER. */
1666 find_reg (chain, order)
1667 struct insn_chain *chain;
1670 int rnum = reload_order[order];
1671 struct reload *rl = rld + rnum;
1672 int best_cost = INT_MAX;
1676 HARD_REG_SET not_usable;
1677 HARD_REG_SET used_by_other_reload;
1679 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1680 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1681 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1683 CLEAR_HARD_REG_SET (used_by_other_reload);
1684 for (k = 0; k < order; k++)
1686 int other = reload_order[k];
1688 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1689 for (j = 0; j < rld[other].nregs; j++)
1690 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1693 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1695 unsigned int regno = i;
1697 if (! TEST_HARD_REG_BIT (not_usable, regno)
1698 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1699 && HARD_REGNO_MODE_OK (regno, rl->mode))
1701 int this_cost = spill_cost[regno];
1703 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1705 for (j = 1; j < this_nregs; j++)
1707 this_cost += spill_add_cost[regno + j];
1708 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1709 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1714 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1716 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1718 if (this_cost < best_cost
1719 /* Among registers with equal cost, prefer caller-saved ones, or
1720 use REG_ALLOC_ORDER if it is defined. */
1721 || (this_cost == best_cost
1722 #ifdef REG_ALLOC_ORDER
1723 && (inv_reg_alloc_order[regno]
1724 < inv_reg_alloc_order[best_reg])
1726 && call_used_regs[regno]
1727 && ! call_used_regs[best_reg]
1732 best_cost = this_cost;
1740 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1742 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1743 rl->regno = best_reg;
1745 EXECUTE_IF_SET_IN_REG_SET
1746 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1748 count_spilled_pseudo (best_reg, rl->nregs, j);
1751 EXECUTE_IF_SET_IN_REG_SET
1752 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1754 count_spilled_pseudo (best_reg, rl->nregs, j);
1757 for (i = 0; i < rl->nregs; i++)
1759 if (spill_cost[best_reg + i] != 0
1760 || spill_add_cost[best_reg + i] != 0)
1762 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1767 /* Find more reload regs to satisfy the remaining need of an insn, which
1769 Do it by ascending class number, since otherwise a reg
1770 might be spilled for a big class and might fail to count
1771 for a smaller class even though it belongs to that class. */
1774 find_reload_regs (chain)
1775 struct insn_chain *chain;
1779 /* In order to be certain of getting the registers we need,
1780 we must sort the reloads into order of increasing register class.
1781 Then our grabbing of reload registers will parallel the process
1782 that provided the reload registers. */
1783 for (i = 0; i < chain->n_reloads; i++)
1785 /* Show whether this reload already has a hard reg. */
1786 if (chain->rld[i].reg_rtx)
1788 int regno = REGNO (chain->rld[i].reg_rtx);
1789 chain->rld[i].regno = regno;
1791 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1794 chain->rld[i].regno = -1;
1795 reload_order[i] = i;
1798 n_reloads = chain->n_reloads;
1799 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1801 CLEAR_HARD_REG_SET (used_spill_regs_local);
1804 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1806 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1808 /* Compute the order of preference for hard registers to spill. */
1810 order_regs_for_reload (chain);
1812 for (i = 0; i < n_reloads; i++)
1814 int r = reload_order[i];
1816 /* Ignore reloads that got marked inoperative. */
1817 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1818 && ! rld[r].optional
1819 && rld[r].regno == -1)
1820 if (! find_reg (chain, i))
1822 spill_failure (chain->insn, rld[r].class);
1828 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1829 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1831 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1835 select_reload_regs ()
1837 struct insn_chain *chain;
1839 /* Try to satisfy the needs for each insn. */
1840 for (chain = insns_need_reload; chain != 0;
1841 chain = chain->next_need_reload)
1842 find_reload_regs (chain);
1845 /* Delete all insns that were inserted by emit_caller_save_insns during
1848 delete_caller_save_insns ()
1850 struct insn_chain *c = reload_insn_chain;
1854 while (c != 0 && c->is_caller_save_insn)
1856 struct insn_chain *next = c->next;
1859 if (insn == BLOCK_HEAD (c->block))
1860 BLOCK_HEAD (c->block) = NEXT_INSN (insn);
1861 if (insn == BLOCK_END (c->block))
1862 BLOCK_END (c->block) = PREV_INSN (insn);
1863 if (c == reload_insn_chain)
1864 reload_insn_chain = next;
1866 if (NEXT_INSN (insn) != 0)
1867 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
1868 if (PREV_INSN (insn) != 0)
1869 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
1872 next->prev = c->prev;
1874 c->prev->next = next;
1875 c->next = unused_insn_chains;
1876 unused_insn_chains = c;
1884 /* Handle the failure to find a register to spill.
1885 INSN should be one of the insns which needed this particular spill reg. */
1888 spill_failure (insn, class)
1890 enum reg_class class;
1892 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1893 if (asm_noperands (PATTERN (insn)) >= 0)
1894 error_for_asm (insn, "Can't find a register in class `%s' while reloading `asm'.",
1895 reg_class_names[class]);
1898 error ("Unable to find a register to spill in class `%s'.",
1899 reg_class_names[class]);
1900 fatal_insn ("This is the insn:", insn);
1904 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1905 data that is dead in INSN. */
1908 delete_dead_insn (insn)
1911 rtx prev = prev_real_insn (insn);
1914 /* If the previous insn sets a register that dies in our insn, delete it
1916 if (prev && GET_CODE (PATTERN (prev)) == SET
1917 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1918 && reg_mentioned_p (prev_dest, PATTERN (insn))
1919 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1920 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1921 delete_dead_insn (prev);
1923 PUT_CODE (insn, NOTE);
1924 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1925 NOTE_SOURCE_FILE (insn) = 0;
1928 /* Modify the home of pseudo-reg I.
1929 The new home is present in reg_renumber[I].
1931 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1932 or it may be -1, meaning there is none or it is not relevant.
1933 This is used so that all pseudos spilled from a given hard reg
1934 can share one stack slot. */
1937 alter_reg (i, from_reg)
1941 /* When outputting an inline function, this can happen
1942 for a reg that isn't actually used. */
1943 if (regno_reg_rtx[i] == 0)
1946 /* If the reg got changed to a MEM at rtl-generation time,
1948 if (GET_CODE (regno_reg_rtx[i]) != REG)
1951 /* Modify the reg-rtx to contain the new hard reg
1952 number or else to contain its pseudo reg number. */
1953 REGNO (regno_reg_rtx[i])
1954 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1956 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1957 allocate a stack slot for it. */
1959 if (reg_renumber[i] < 0
1960 && REG_N_REFS (i) > 0
1961 && reg_equiv_constant[i] == 0
1962 && reg_equiv_memory_loc[i] == 0)
1965 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1966 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1969 /* Each pseudo reg has an inherent size which comes from its own mode,
1970 and a total size which provides room for paradoxical subregs
1971 which refer to the pseudo reg in wider modes.
1973 We can use a slot already allocated if it provides both
1974 enough inherent space and enough total space.
1975 Otherwise, we allocate a new slot, making sure that it has no less
1976 inherent space, and no less total space, then the previous slot. */
1979 /* No known place to spill from => no slot to reuse. */
1980 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1981 inherent_size == total_size ? 0 : -1);
1982 if (BYTES_BIG_ENDIAN)
1983 /* Cancel the big-endian correction done in assign_stack_local.
1984 Get the address of the beginning of the slot.
1985 This is so we can do a big-endian correction unconditionally
1987 adjust = inherent_size - total_size;
1989 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1991 /* Nothing can alias this slot except this pseudo. */
1992 MEM_ALIAS_SET (x) = new_alias_set ();
1995 /* Reuse a stack slot if possible. */
1996 else if (spill_stack_slot[from_reg] != 0
1997 && spill_stack_slot_width[from_reg] >= total_size
1998 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2000 x = spill_stack_slot[from_reg];
2002 /* Allocate a bigger slot. */
2005 /* Compute maximum size needed, both for inherent size
2006 and for total size. */
2007 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2010 if (spill_stack_slot[from_reg])
2012 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2014 mode = GET_MODE (spill_stack_slot[from_reg]);
2015 if (spill_stack_slot_width[from_reg] > total_size)
2016 total_size = spill_stack_slot_width[from_reg];
2019 /* Make a slot with that size. */
2020 x = assign_stack_local (mode, total_size,
2021 inherent_size == total_size ? 0 : -1);
2024 /* All pseudos mapped to this slot can alias each other. */
2025 if (spill_stack_slot[from_reg])
2026 MEM_ALIAS_SET (x) = MEM_ALIAS_SET (spill_stack_slot[from_reg]);
2028 MEM_ALIAS_SET (x) = new_alias_set ();
2030 if (BYTES_BIG_ENDIAN)
2032 /* Cancel the big-endian correction done in assign_stack_local.
2033 Get the address of the beginning of the slot.
2034 This is so we can do a big-endian correction unconditionally
2036 adjust = GET_MODE_SIZE (mode) - total_size;
2038 stack_slot = gen_rtx_MEM (mode_for_size (total_size
2041 plus_constant (XEXP (x, 0), adjust));
2044 spill_stack_slot[from_reg] = stack_slot;
2045 spill_stack_slot_width[from_reg] = total_size;
2048 /* On a big endian machine, the "address" of the slot
2049 is the address of the low part that fits its inherent mode. */
2050 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2051 adjust += (total_size - inherent_size);
2053 /* If we have any adjustment to make, or if the stack slot is the
2054 wrong mode, make a new stack slot. */
2055 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2057 rtx new = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
2058 plus_constant (XEXP (x, 0), adjust));
2060 MEM_COPY_ATTRIBUTES (new, x);
2064 /* Save the stack slot for later. */
2065 reg_equiv_memory_loc[i] = x;
2069 /* Mark the slots in regs_ever_live for the hard regs
2070 used by pseudo-reg number REGNO. */
2073 mark_home_live (regno)
2076 register int i, lim;
2078 i = reg_renumber[regno];
2081 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2083 regs_ever_live[i++] = 1;
2086 /* This function handles the tracking of elimination offsets around branches.
2088 X is a piece of RTL being scanned.
2090 INSN is the insn that it came from, if any.
2092 INITIAL_P is non-zero if we are to set the offset to be the initial
2093 offset and zero if we are setting the offset of the label to be the
2097 set_label_offsets (x, insn, initial_p)
2102 enum rtx_code code = GET_CODE (x);
2105 struct elim_table *p;
2110 if (LABEL_REF_NONLOCAL_P (x))
2115 /* ... fall through ... */
2118 /* If we know nothing about this label, set the desired offsets. Note
2119 that this sets the offset at a label to be the offset before a label
2120 if we don't know anything about the label. This is not correct for
2121 the label after a BARRIER, but is the best guess we can make. If
2122 we guessed wrong, we will suppress an elimination that might have
2123 been possible had we been able to guess correctly. */
2125 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2127 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2128 offsets_at[CODE_LABEL_NUMBER (x)][i]
2129 = (initial_p ? reg_eliminate[i].initial_offset
2130 : reg_eliminate[i].offset);
2131 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2134 /* Otherwise, if this is the definition of a label and it is
2135 preceded by a BARRIER, set our offsets to the known offset of
2139 && (tem = prev_nonnote_insn (insn)) != 0
2140 && GET_CODE (tem) == BARRIER)
2141 set_offsets_for_label (insn);
2143 /* If neither of the above cases is true, compare each offset
2144 with those previously recorded and suppress any eliminations
2145 where the offsets disagree. */
2147 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2148 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2149 != (initial_p ? reg_eliminate[i].initial_offset
2150 : reg_eliminate[i].offset))
2151 reg_eliminate[i].can_eliminate = 0;
2156 set_label_offsets (PATTERN (insn), insn, initial_p);
2158 /* ... fall through ... */
2162 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2163 and hence must have all eliminations at their initial offsets. */
2164 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2165 if (REG_NOTE_KIND (tem) == REG_LABEL)
2166 set_label_offsets (XEXP (tem, 0), insn, 1);
2172 /* Each of the labels in the parallel or address vector must be
2173 at their initial offsets. We want the first field for PARALLEL
2174 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2176 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2177 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2182 /* We only care about setting PC. If the source is not RETURN,
2183 IF_THEN_ELSE, or a label, disable any eliminations not at
2184 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2185 isn't one of those possibilities. For branches to a label,
2186 call ourselves recursively.
2188 Note that this can disable elimination unnecessarily when we have
2189 a non-local goto since it will look like a non-constant jump to
2190 someplace in the current function. This isn't a significant
2191 problem since such jumps will normally be when all elimination
2192 pairs are back to their initial offsets. */
2194 if (SET_DEST (x) != pc_rtx)
2197 switch (GET_CODE (SET_SRC (x)))
2204 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2208 tem = XEXP (SET_SRC (x), 1);
2209 if (GET_CODE (tem) == LABEL_REF)
2210 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2211 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2214 tem = XEXP (SET_SRC (x), 2);
2215 if (GET_CODE (tem) == LABEL_REF)
2216 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2217 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2225 /* If we reach here, all eliminations must be at their initial
2226 offset because we are doing a jump to a variable address. */
2227 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2228 if (p->offset != p->initial_offset)
2229 p->can_eliminate = 0;
2237 /* Scan X and replace any eliminable registers (such as fp) with a
2238 replacement (such as sp), plus an offset.
2240 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2241 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2242 MEM, we are allowed to replace a sum of a register and the constant zero
2243 with the register, which we cannot do outside a MEM. In addition, we need
2244 to record the fact that a register is referenced outside a MEM.
2246 If INSN is an insn, it is the insn containing X. If we replace a REG
2247 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2248 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2249 the REG is being modified.
2251 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2252 That's used when we eliminate in expressions stored in notes.
2253 This means, do not set ref_outside_mem even if the reference
2256 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2257 replacements done assuming all offsets are at their initial values. If
2258 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2259 encounter, return the actual location so that find_reloads will do
2260 the proper thing. */
2263 eliminate_regs (x, mem_mode, insn)
2265 enum machine_mode mem_mode;
2268 enum rtx_code code = GET_CODE (x);
2269 struct elim_table *ep;
2276 if (! current_function_decl)
2295 /* This is only for the benefit of the debugging backends, which call
2296 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2297 removed after CSE. */
2298 new = eliminate_regs (XEXP (x, 0), 0, insn);
2299 if (GET_CODE (new) == MEM)
2300 return XEXP (new, 0);
2306 /* First handle the case where we encounter a bare register that
2307 is eliminable. Replace it with a PLUS. */
2308 if (regno < FIRST_PSEUDO_REGISTER)
2310 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2312 if (ep->from_rtx == x && ep->can_eliminate)
2313 return plus_constant (ep->to_rtx, ep->previous_offset);
2316 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2317 && reg_equiv_constant[regno]
2318 && ! CONSTANT_P (reg_equiv_constant[regno]))
2319 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2323 /* You might think handling MINUS in a manner similar to PLUS is a
2324 good idea. It is not. It has been tried multiple times and every
2325 time the change has had to have been reverted.
2327 Other parts of reload know a PLUS is special (gen_reload for example)
2328 and require special code to handle code a reloaded PLUS operand.
2330 Also consider backends where the flags register is clobbered by a
2331 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2332 lea instruction comes to mind). If we try to reload a MINUS, we
2333 may kill the flags register that was holding a useful value.
2335 So, please before trying to handle MINUS, consider reload as a
2336 whole instead of this little section as well as the backend issues. */
2338 /* If this is the sum of an eliminable register and a constant, rework
2340 if (GET_CODE (XEXP (x, 0)) == REG
2341 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2342 && CONSTANT_P (XEXP (x, 1)))
2344 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2346 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2348 /* The only time we want to replace a PLUS with a REG (this
2349 occurs when the constant operand of the PLUS is the negative
2350 of the offset) is when we are inside a MEM. We won't want
2351 to do so at other times because that would change the
2352 structure of the insn in a way that reload can't handle.
2353 We special-case the commonest situation in
2354 eliminate_regs_in_insn, so just replace a PLUS with a
2355 PLUS here, unless inside a MEM. */
2356 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2357 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2360 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2361 plus_constant (XEXP (x, 1),
2362 ep->previous_offset));
2365 /* If the register is not eliminable, we are done since the other
2366 operand is a constant. */
2370 /* If this is part of an address, we want to bring any constant to the
2371 outermost PLUS. We will do this by doing register replacement in
2372 our operands and seeing if a constant shows up in one of them.
2374 Note that there is no risk of modifying the structure of the insn,
2375 since we only get called for its operands, thus we are either
2376 modifying the address inside a MEM, or something like an address
2377 operand of a load-address insn. */
2380 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2381 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2383 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2385 /* If one side is a PLUS and the other side is a pseudo that
2386 didn't get a hard register but has a reg_equiv_constant,
2387 we must replace the constant here since it may no longer
2388 be in the position of any operand. */
2389 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2390 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2391 && reg_renumber[REGNO (new1)] < 0
2392 && reg_equiv_constant != 0
2393 && reg_equiv_constant[REGNO (new1)] != 0)
2394 new1 = reg_equiv_constant[REGNO (new1)];
2395 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2396 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2397 && reg_renumber[REGNO (new0)] < 0
2398 && reg_equiv_constant[REGNO (new0)] != 0)
2399 new0 = reg_equiv_constant[REGNO (new0)];
2401 new = form_sum (new0, new1);
2403 /* As above, if we are not inside a MEM we do not want to
2404 turn a PLUS into something else. We might try to do so here
2405 for an addition of 0 if we aren't optimizing. */
2406 if (! mem_mode && GET_CODE (new) != PLUS)
2407 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2415 /* If this is the product of an eliminable register and a
2416 constant, apply the distribute law and move the constant out
2417 so that we have (plus (mult ..) ..). This is needed in order
2418 to keep load-address insns valid. This case is pathological.
2419 We ignore the possibility of overflow here. */
2420 if (GET_CODE (XEXP (x, 0)) == REG
2421 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2422 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2423 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2425 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2428 /* Refs inside notes don't count for this purpose. */
2429 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2430 || GET_CODE (insn) == INSN_LIST)))
2431 ep->ref_outside_mem = 1;
2434 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2435 ep->previous_offset * INTVAL (XEXP (x, 1)));
2438 /* ... fall through ... */
2442 /* See comments before PLUS about handling MINUS. */
2444 case DIV: case UDIV:
2445 case MOD: case UMOD:
2446 case AND: case IOR: case XOR:
2447 case ROTATERT: case ROTATE:
2448 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2450 case GE: case GT: case GEU: case GTU:
2451 case LE: case LT: case LEU: case LTU:
2453 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2455 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2457 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2458 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2463 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2466 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2467 if (new != XEXP (x, 0))
2469 /* If this is a REG_DEAD note, it is not valid anymore.
2470 Using the eliminated version could result in creating a
2471 REG_DEAD note for the stack or frame pointer. */
2472 if (GET_MODE (x) == REG_DEAD)
2474 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2477 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2481 /* ... fall through ... */
2484 /* Now do eliminations in the rest of the chain. If this was
2485 an EXPR_LIST, this might result in allocating more memory than is
2486 strictly needed, but it simplifies the code. */
2489 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2490 if (new != XEXP (x, 1))
2491 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2499 case STRICT_LOW_PART:
2501 case SIGN_EXTEND: case ZERO_EXTEND:
2502 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2503 case FLOAT: case FIX:
2504 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2508 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2509 if (new != XEXP (x, 0))
2510 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2514 /* Similar to above processing, but preserve SUBREG_WORD.
2515 Convert (subreg (mem)) to (mem) if not paradoxical.
2516 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2517 pseudo didn't get a hard reg, we must replace this with the
2518 eliminated version of the memory location because push_reloads
2519 may do the replacement in certain circumstances. */
2520 if (GET_CODE (SUBREG_REG (x)) == REG
2521 && (GET_MODE_SIZE (GET_MODE (x))
2522 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2523 && reg_equiv_memory_loc != 0
2524 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2526 new = SUBREG_REG (x);
2529 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2531 if (new != XEXP (x, 0))
2533 int x_size = GET_MODE_SIZE (GET_MODE (x));
2534 int new_size = GET_MODE_SIZE (GET_MODE (new));
2536 if (GET_CODE (new) == MEM
2537 && ((x_size < new_size
2538 #ifdef WORD_REGISTER_OPERATIONS
2539 /* On these machines, combine can create rtl of the form
2540 (set (subreg:m1 (reg:m2 R) 0) ...)
2541 where m1 < m2, and expects something interesting to
2542 happen to the entire word. Moreover, it will use the
2543 (reg:m2 R) later, expecting all bits to be preserved.
2544 So if the number of words is the same, preserve the
2545 subreg so that push_reloads can see it. */
2546 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
2549 || (x_size == new_size))
2552 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2553 enum machine_mode mode = GET_MODE (x);
2555 if (BYTES_BIG_ENDIAN)
2556 offset += (MIN (UNITS_PER_WORD,
2557 GET_MODE_SIZE (GET_MODE (new)))
2558 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2560 PUT_MODE (new, mode);
2561 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2565 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
2571 /* This is only for the benefit of the debugging backends, which call
2572 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2573 removed after CSE. */
2574 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2575 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2577 /* Our only special processing is to pass the mode of the MEM to our
2578 recursive call and copy the flags. While we are here, handle this
2579 case more efficiently. */
2580 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
2581 if (new != XEXP (x, 0))
2583 new = gen_rtx_MEM (GET_MODE (x), new);
2584 MEM_COPY_ATTRIBUTES (new, x);
2600 /* Process each of our operands recursively. If any have changed, make a
2602 fmt = GET_RTX_FORMAT (code);
2603 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2607 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2608 if (new != XEXP (x, i) && ! copied)
2610 rtx new_x = rtx_alloc (code);
2612 (sizeof (*new_x) - sizeof (new_x->fld)
2613 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2619 else if (*fmt == 'E')
2622 for (j = 0; j < XVECLEN (x, i); j++)
2624 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2625 if (new != XVECEXP (x, i, j) && ! copied_vec)
2627 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2631 rtx new_x = rtx_alloc (code);
2633 (sizeof (*new_x) - sizeof (new_x->fld)
2634 + (sizeof (new_x->fld[0])
2635 * GET_RTX_LENGTH (code))));
2639 XVEC (x, i) = new_v;
2642 XVECEXP (x, i, j) = new;
2650 /* Scan rtx X for modifications of elimination target registers. Update
2651 the table of eliminables to reflect the changed state. MEM_MODE is
2652 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2655 elimination_effects (x, mem_mode)
2657 enum machine_mode mem_mode;
2660 enum rtx_code code = GET_CODE (x);
2661 struct elim_table *ep;
2687 /* First handle the case where we encounter a bare register that
2688 is eliminable. Replace it with a PLUS. */
2689 if (regno < FIRST_PSEUDO_REGISTER)
2691 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2693 if (ep->from_rtx == x && ep->can_eliminate)
2696 ep->ref_outside_mem = 1;
2701 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2702 && reg_equiv_constant[regno]
2703 && ! CONSTANT_P (reg_equiv_constant[regno]))
2704 elimination_effects (reg_equiv_constant[regno], mem_mode);
2713 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2714 if (ep->to_rtx == XEXP (x, 0))
2716 int size = GET_MODE_SIZE (mem_mode);
2718 /* If more bytes than MEM_MODE are pushed, account for them. */
2719 #ifdef PUSH_ROUNDING
2720 if (ep->to_rtx == stack_pointer_rtx)
2721 size = PUSH_ROUNDING (size);
2723 if (code == PRE_DEC || code == POST_DEC)
2725 else if (code == PRE_INC || code == POST_INC)
2727 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2728 && GET_CODE (XEXP (x, 1)) == PLUS
2729 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2730 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2731 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2734 /* These two aren't unary operators. */
2735 if (code == POST_MODIFY || code == PRE_MODIFY)
2738 /* Fall through to generic unary operation case. */
2739 case STRICT_LOW_PART:
2741 case SIGN_EXTEND: case ZERO_EXTEND:
2742 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2743 case FLOAT: case FIX:
2744 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2748 elimination_effects (XEXP (x, 0), mem_mode);
2752 if (GET_CODE (SUBREG_REG (x)) == REG
2753 && (GET_MODE_SIZE (GET_MODE (x))
2754 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2755 && reg_equiv_memory_loc != 0
2756 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2759 elimination_effects (SUBREG_REG (x), mem_mode);
2763 /* If using a register that is the source of an eliminate we still
2764 think can be performed, note it cannot be performed since we don't
2765 know how this register is used. */
2766 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2767 if (ep->from_rtx == XEXP (x, 0))
2768 ep->can_eliminate = 0;
2770 elimination_effects (XEXP (x, 0), mem_mode);
2774 /* If clobbering a register that is the replacement register for an
2775 elimination we still think can be performed, note that it cannot
2776 be performed. Otherwise, we need not be concerned about it. */
2777 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2778 if (ep->to_rtx == XEXP (x, 0))
2779 ep->can_eliminate = 0;
2781 elimination_effects (XEXP (x, 0), mem_mode);
2785 /* Check for setting a register that we know about. */
2786 if (GET_CODE (SET_DEST (x)) == REG)
2788 /* See if this is setting the replacement register for an
2791 If DEST is the hard frame pointer, we do nothing because we
2792 assume that all assignments to the frame pointer are for
2793 non-local gotos and are being done at a time when they are valid
2794 and do not disturb anything else. Some machines want to
2795 eliminate a fake argument pointer (or even a fake frame pointer)
2796 with either the real frame or the stack pointer. Assignments to
2797 the hard frame pointer must not prevent this elimination. */
2799 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2801 if (ep->to_rtx == SET_DEST (x)
2802 && SET_DEST (x) != hard_frame_pointer_rtx)
2804 /* If it is being incremented, adjust the offset. Otherwise,
2805 this elimination can't be done. */
2806 rtx src = SET_SRC (x);
2808 if (GET_CODE (src) == PLUS
2809 && XEXP (src, 0) == SET_DEST (x)
2810 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2811 ep->offset -= INTVAL (XEXP (src, 1));
2813 ep->can_eliminate = 0;
2817 elimination_effects (SET_DEST (x), 0);
2818 elimination_effects (SET_SRC (x), 0);
2822 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2825 /* Our only special processing is to pass the mode of the MEM to our
2827 elimination_effects (XEXP (x, 0), GET_MODE (x));
2834 fmt = GET_RTX_FORMAT (code);
2835 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2838 elimination_effects (XEXP (x, i), mem_mode);
2839 else if (*fmt == 'E')
2840 for (j = 0; j < XVECLEN (x, i); j++)
2841 elimination_effects (XVECEXP (x, i, j), mem_mode);
2845 /* Descend through rtx X and verify that no references to eliminable registers
2846 remain. If any do remain, mark the involved register as not
2850 check_eliminable_occurrences (x)
2860 code = GET_CODE (x);
2862 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2864 struct elim_table *ep;
2866 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2867 if (ep->from_rtx == x && ep->can_eliminate)
2868 ep->can_eliminate = 0;
2872 fmt = GET_RTX_FORMAT (code);
2873 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2876 check_eliminable_occurrences (XEXP (x, i));
2877 else if (*fmt == 'E')
2880 for (j = 0; j < XVECLEN (x, i); j++)
2881 check_eliminable_occurrences (XVECEXP (x, i, j));
2886 /* Scan INSN and eliminate all eliminable registers in it.
2888 If REPLACE is nonzero, do the replacement destructively. Also
2889 delete the insn as dead it if it is setting an eliminable register.
2891 If REPLACE is zero, do all our allocations in reload_obstack.
2893 If no eliminations were done and this insn doesn't require any elimination
2894 processing (these are not identical conditions: it might be updating sp,
2895 but not referencing fp; this needs to be seen during reload_as_needed so
2896 that the offset between fp and sp can be taken into consideration), zero
2897 is returned. Otherwise, 1 is returned. */
2900 eliminate_regs_in_insn (insn, replace)
2904 int icode = recog_memoized (insn);
2905 rtx old_body = PATTERN (insn);
2906 int insn_is_asm = asm_noperands (old_body) >= 0;
2907 rtx old_set = single_set (insn);
2911 rtx substed_operand[MAX_RECOG_OPERANDS];
2912 rtx orig_operand[MAX_RECOG_OPERANDS];
2913 struct elim_table *ep;
2915 if (! insn_is_asm && icode < 0)
2917 if (GET_CODE (PATTERN (insn)) == USE
2918 || GET_CODE (PATTERN (insn)) == CLOBBER
2919 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2920 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2921 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2926 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2927 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2929 /* Check for setting an eliminable register. */
2930 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2931 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2933 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2934 /* If this is setting the frame pointer register to the
2935 hardware frame pointer register and this is an elimination
2936 that will be done (tested above), this insn is really
2937 adjusting the frame pointer downward to compensate for
2938 the adjustment done before a nonlocal goto. */
2939 if (ep->from == FRAME_POINTER_REGNUM
2940 && ep->to == HARD_FRAME_POINTER_REGNUM)
2942 rtx src = SET_SRC (old_set);
2943 int offset = 0, ok = 0;
2944 rtx prev_insn, prev_set;
2946 if (src == ep->to_rtx)
2948 else if (GET_CODE (src) == PLUS
2949 && GET_CODE (XEXP (src, 0)) == CONST_INT
2950 && XEXP (src, 1) == ep->to_rtx)
2951 offset = INTVAL (XEXP (src, 0)), ok = 1;
2952 else if (GET_CODE (src) == PLUS
2953 && GET_CODE (XEXP (src, 1)) == CONST_INT
2954 && XEXP (src, 0) == ep->to_rtx)
2955 offset = INTVAL (XEXP (src, 1)), ok = 1;
2956 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
2957 && (prev_set = single_set (prev_insn)) != 0
2958 && rtx_equal_p (SET_DEST (prev_set), src))
2960 src = SET_SRC (prev_set);
2961 if (src == ep->to_rtx)
2963 else if (GET_CODE (src) == PLUS
2964 && GET_CODE (XEXP (src, 0)) == CONST_INT
2965 && XEXP (src, 1) == ep->to_rtx)
2966 offset = INTVAL (XEXP (src, 0)), ok = 1;
2967 else if (GET_CODE (src) == PLUS
2968 && GET_CODE (XEXP (src, 1)) == CONST_INT
2969 && XEXP (src, 0) == ep->to_rtx)
2970 offset = INTVAL (XEXP (src, 1)), ok = 1;
2978 = plus_constant (ep->to_rtx, offset - ep->offset);
2980 /* First see if this insn remains valid when we
2981 make the change. If not, keep the INSN_CODE
2982 the same and let reload fit it up. */
2983 validate_change (insn, &SET_SRC (old_set), src, 1);
2984 validate_change (insn, &SET_DEST (old_set),
2986 if (! apply_change_group ())
2988 SET_SRC (old_set) = src;
2989 SET_DEST (old_set) = ep->to_rtx;
2999 /* In this case this insn isn't serving a useful purpose. We
3000 will delete it in reload_as_needed once we know that this
3001 elimination is, in fact, being done.
3003 If REPLACE isn't set, we can't delete this insn, but needn't
3004 process it since it won't be used unless something changes. */
3007 delete_dead_insn (insn);
3015 /* We allow one special case which happens to work on all machines we
3016 currently support: a single set with the source being a PLUS of an
3017 eliminable register and a constant. */
3019 && GET_CODE (SET_DEST (old_set)) == REG
3020 && GET_CODE (SET_SRC (old_set)) == PLUS
3021 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3022 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
3023 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
3025 rtx reg = XEXP (SET_SRC (old_set), 0);
3026 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
3028 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3029 if (ep->from_rtx == reg && ep->can_eliminate)
3031 offset += ep->offset;
3036 /* We assume here that if we need a PARALLEL with
3037 CLOBBERs for this assignment, we can do with the
3038 MATCH_SCRATCHes that add_clobbers allocates.
3039 There's not much we can do if that doesn't work. */
3040 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3044 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3047 rtvec vec = rtvec_alloc (num_clobbers + 1);
3049 vec->elem[0] = PATTERN (insn);
3050 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3051 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3053 if (INSN_CODE (insn) < 0)
3058 new_body = old_body;
3061 new_body = copy_insn (old_body);
3062 if (REG_NOTES (insn))
3063 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3065 PATTERN (insn) = new_body;
3066 old_set = single_set (insn);
3068 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3069 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3072 /* This can't have an effect on elimination offsets, so skip right
3078 /* Determine the effects of this insn on elimination offsets. */
3079 elimination_effects (old_body, 0);
3081 /* Eliminate all eliminable registers occurring in operands that
3082 can be handled by reload. */
3083 extract_insn (insn);
3085 for (i = 0; i < recog_data.n_operands; i++)
3087 orig_operand[i] = recog_data.operand[i];
3088 substed_operand[i] = recog_data.operand[i];
3090 /* For an asm statement, every operand is eliminable. */
3091 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3093 /* Check for setting a register that we know about. */
3094 if (recog_data.operand_type[i] != OP_IN
3095 && GET_CODE (orig_operand[i]) == REG)
3097 /* If we are assigning to a register that can be eliminated, it
3098 must be as part of a PARALLEL, since the code above handles
3099 single SETs. We must indicate that we can no longer
3100 eliminate this reg. */
3101 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3103 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3104 ep->can_eliminate = 0;
3107 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3108 replace ? insn : NULL_RTX);
3109 if (substed_operand[i] != orig_operand[i])
3110 val = any_changes = 1;
3111 /* Terminate the search in check_eliminable_occurrences at
3113 *recog_data.operand_loc[i] = 0;
3115 /* If an output operand changed from a REG to a MEM and INSN is an
3116 insn, write a CLOBBER insn. */
3117 if (recog_data.operand_type[i] != OP_IN
3118 && GET_CODE (orig_operand[i]) == REG
3119 && GET_CODE (substed_operand[i]) == MEM
3121 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3126 for (i = 0; i < recog_data.n_dups; i++)
3127 *recog_data.dup_loc[i]
3128 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3130 /* If any eliminable remain, they aren't eliminable anymore. */
3131 check_eliminable_occurrences (old_body);
3133 /* Substitute the operands; the new values are in the substed_operand
3135 for (i = 0; i < recog_data.n_operands; i++)
3136 *recog_data.operand_loc[i] = substed_operand[i];
3137 for (i = 0; i < recog_data.n_dups; i++)
3138 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3140 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3141 re-recognize the insn. We do this in case we had a simple addition
3142 but now can do this as a load-address. This saves an insn in this
3144 If re-recognition fails, the old insn code number will still be used,
3145 and some register operands may have changed into PLUS expressions.
3146 These will be handled by find_reloads by loading them into a register
3151 /* If we aren't replacing things permanently and we changed something,
3152 make another copy to ensure that all the RTL is new. Otherwise
3153 things can go wrong if find_reload swaps commutative operands
3154 and one is inside RTL that has been copied while the other is not. */
3155 new_body = old_body;
3158 new_body = copy_insn (old_body);
3159 if (REG_NOTES (insn))
3160 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3162 PATTERN (insn) = new_body;
3164 /* If we had a move insn but now we don't, rerecognize it. This will
3165 cause spurious re-recognition if the old move had a PARALLEL since
3166 the new one still will, but we can't call single_set without
3167 having put NEW_BODY into the insn and the re-recognition won't
3168 hurt in this rare case. */
3169 /* ??? Why this huge if statement - why don't we just rerecognize the
3173 && ((GET_CODE (SET_SRC (old_set)) == REG
3174 && (GET_CODE (new_body) != SET
3175 || GET_CODE (SET_SRC (new_body)) != REG))
3176 /* If this was a load from or store to memory, compare
3177 the MEM in recog_data.operand to the one in the insn.
3178 If they are not equal, then rerecognize the insn. */
3180 && ((GET_CODE (SET_SRC (old_set)) == MEM
3181 && SET_SRC (old_set) != recog_data.operand[1])
3182 || (GET_CODE (SET_DEST (old_set)) == MEM
3183 && SET_DEST (old_set) != recog_data.operand[0])))
3184 /* If this was an add insn before, rerecognize. */
3185 || GET_CODE (SET_SRC (old_set)) == PLUS))
3187 int new_icode = recog (PATTERN (insn), insn, 0);
3189 INSN_CODE (insn) = icode;
3193 /* Restore the old body. If there were any changes to it, we made a copy
3194 of it while the changes were still in place, so we'll correctly return
3195 a modified insn below. */
3198 /* Restore the old body. */
3199 for (i = 0; i < recog_data.n_operands; i++)
3200 *recog_data.operand_loc[i] = orig_operand[i];
3201 for (i = 0; i < recog_data.n_dups; i++)
3202 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3205 /* Update all elimination pairs to reflect the status after the current
3206 insn. The changes we make were determined by the earlier call to
3207 elimination_effects.
3209 We also detect a cases where register elimination cannot be done,
3210 namely, if a register would be both changed and referenced outside a MEM
3211 in the resulting insn since such an insn is often undefined and, even if
3212 not, we cannot know what meaning will be given to it. Note that it is
3213 valid to have a register used in an address in an insn that changes it
3214 (presumably with a pre- or post-increment or decrement).
3216 If anything changes, return nonzero. */
3218 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3220 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3221 ep->can_eliminate = 0;
3223 ep->ref_outside_mem = 0;
3225 if (ep->previous_offset != ep->offset)
3230 /* If we changed something, perform elimination in REG_NOTES. This is
3231 needed even when REPLACE is zero because a REG_DEAD note might refer
3232 to a register that we eliminate and could cause a different number
3233 of spill registers to be needed in the final reload pass than in
3235 if (val && REG_NOTES (insn) != 0)
3236 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3241 /* Loop through all elimination pairs.
3242 Recalculate the number not at initial offset.
3244 Compute the maximum offset (minimum offset if the stack does not
3245 grow downward) for each elimination pair. */
3248 update_eliminable_offsets ()
3250 struct elim_table *ep;
3252 num_not_at_initial_offset = 0;
3253 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3255 ep->previous_offset = ep->offset;
3256 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3257 num_not_at_initial_offset++;
3261 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3262 replacement we currently believe is valid, mark it as not eliminable if X
3263 modifies DEST in any way other than by adding a constant integer to it.
3265 If DEST is the frame pointer, we do nothing because we assume that
3266 all assignments to the hard frame pointer are nonlocal gotos and are being
3267 done at a time when they are valid and do not disturb anything else.
3268 Some machines want to eliminate a fake argument pointer with either the
3269 frame or stack pointer. Assignments to the hard frame pointer must not
3270 prevent this elimination.
3272 Called via note_stores from reload before starting its passes to scan
3273 the insns of the function. */
3276 mark_not_eliminable (dest, x, data)
3279 void *data ATTRIBUTE_UNUSED;
3281 register unsigned int i;
3283 /* A SUBREG of a hard register here is just changing its mode. We should
3284 not see a SUBREG of an eliminable hard register, but check just in
3286 if (GET_CODE (dest) == SUBREG)
3287 dest = SUBREG_REG (dest);
3289 if (dest == hard_frame_pointer_rtx)
3292 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3293 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3294 && (GET_CODE (x) != SET
3295 || GET_CODE (SET_SRC (x)) != PLUS
3296 || XEXP (SET_SRC (x), 0) != dest
3297 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3299 reg_eliminate[i].can_eliminate_previous
3300 = reg_eliminate[i].can_eliminate = 0;
3305 /* Verify that the initial elimination offsets did not change since the
3306 last call to set_initial_elim_offsets. This is used to catch cases
3307 where something illegal happened during reload_as_needed that could
3308 cause incorrect code to be generated if we did not check for it. */
3311 verify_initial_elim_offsets ()
3315 #ifdef ELIMINABLE_REGS
3316 struct elim_table *ep;
3318 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3320 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3321 if (t != ep->initial_offset)
3325 INITIAL_FRAME_POINTER_OFFSET (t);
3326 if (t != reg_eliminate[0].initial_offset)
3331 /* Reset all offsets on eliminable registers to their initial values. */
3334 set_initial_elim_offsets ()
3336 struct elim_table *ep = reg_eliminate;
3338 #ifdef ELIMINABLE_REGS
3339 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3341 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3342 ep->previous_offset = ep->offset = ep->initial_offset;
3345 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3346 ep->previous_offset = ep->offset = ep->initial_offset;
3349 num_not_at_initial_offset = 0;
3352 /* Initialize the known label offsets.
3353 Set a known offset for each forced label to be at the initial offset
3354 of each elimination. We do this because we assume that all
3355 computed jumps occur from a location where each elimination is
3356 at its initial offset.
3357 For all other labels, show that we don't know the offsets. */
3360 set_initial_label_offsets ()
3363 memset ((char *) &offsets_known_at[get_first_label_num ()], 0, num_labels);
3365 for (x = forced_labels; x; x = XEXP (x, 1))
3367 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3370 /* Set all elimination offsets to the known values for the code label given
3374 set_offsets_for_label (insn)
3378 int label_nr = CODE_LABEL_NUMBER (insn);
3379 struct elim_table *ep;
3381 num_not_at_initial_offset = 0;
3382 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3384 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3385 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3386 num_not_at_initial_offset++;
3390 /* See if anything that happened changes which eliminations are valid.
3391 For example, on the Sparc, whether or not the frame pointer can
3392 be eliminated can depend on what registers have been used. We need
3393 not check some conditions again (such as flag_omit_frame_pointer)
3394 since they can't have changed. */
3397 update_eliminables (pset)
3400 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3401 int previous_frame_pointer_needed = frame_pointer_needed;
3403 struct elim_table *ep;
3405 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3406 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3407 #ifdef ELIMINABLE_REGS
3408 || ! CAN_ELIMINATE (ep->from, ep->to)
3411 ep->can_eliminate = 0;
3413 /* Look for the case where we have discovered that we can't replace
3414 register A with register B and that means that we will now be
3415 trying to replace register A with register C. This means we can
3416 no longer replace register C with register B and we need to disable
3417 such an elimination, if it exists. This occurs often with A == ap,
3418 B == sp, and C == fp. */
3420 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3422 struct elim_table *op;
3423 register int new_to = -1;
3425 if (! ep->can_eliminate && ep->can_eliminate_previous)
3427 /* Find the current elimination for ep->from, if there is a
3429 for (op = reg_eliminate;
3430 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3431 if (op->from == ep->from && op->can_eliminate)
3437 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3439 for (op = reg_eliminate;
3440 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3441 if (op->from == new_to && op->to == ep->to)
3442 op->can_eliminate = 0;
3446 /* See if any registers that we thought we could eliminate the previous
3447 time are no longer eliminable. If so, something has changed and we
3448 must spill the register. Also, recompute the number of eliminable
3449 registers and see if the frame pointer is needed; it is if there is
3450 no elimination of the frame pointer that we can perform. */
3452 frame_pointer_needed = 1;
3453 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3455 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3456 && ep->to != HARD_FRAME_POINTER_REGNUM)
3457 frame_pointer_needed = 0;
3459 if (! ep->can_eliminate && ep->can_eliminate_previous)
3461 ep->can_eliminate_previous = 0;
3462 SET_HARD_REG_BIT (*pset, ep->from);
3467 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3468 /* If we didn't need a frame pointer last time, but we do now, spill
3469 the hard frame pointer. */
3470 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3471 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3475 /* Initialize the table of registers to eliminate. */
3480 struct elim_table *ep;
3481 #ifdef ELIMINABLE_REGS
3482 struct elim_table_1 *ep1;
3486 reg_eliminate = (struct elim_table *)
3487 xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3489 /* Does this function require a frame pointer? */
3491 frame_pointer_needed = (! flag_omit_frame_pointer
3492 #ifdef EXIT_IGNORE_STACK
3493 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3494 and restore sp for alloca. So we can't eliminate
3495 the frame pointer in that case. At some point,
3496 we should improve this by emitting the
3497 sp-adjusting insns for this case. */
3498 || (current_function_calls_alloca
3499 && EXIT_IGNORE_STACK)
3501 || FRAME_POINTER_REQUIRED);
3505 #ifdef ELIMINABLE_REGS
3506 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3507 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3509 ep->from = ep1->from;
3511 ep->can_eliminate = ep->can_eliminate_previous
3512 = (CAN_ELIMINATE (ep->from, ep->to)
3513 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3516 reg_eliminate[0].from = reg_eliminate_1[0].from;
3517 reg_eliminate[0].to = reg_eliminate_1[0].to;
3518 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3519 = ! frame_pointer_needed;
3522 /* Count the number of eliminable registers and build the FROM and TO
3523 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3524 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3525 We depend on this. */
3526 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3528 num_eliminable += ep->can_eliminate;
3529 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3530 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3534 /* Kick all pseudos out of hard register REGNO.
3536 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3537 because we found we can't eliminate some register. In the case, no pseudos
3538 are allowed to be in the register, even if they are only in a block that
3539 doesn't require spill registers, unlike the case when we are spilling this
3540 hard reg to produce another spill register.
3542 Return nonzero if any pseudos needed to be kicked out. */
3545 spill_hard_reg (regno, cant_eliminate)
3553 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3554 regs_ever_live[regno] = 1;
3557 /* Spill every pseudo reg that was allocated to this reg
3558 or to something that overlaps this reg. */
3560 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3561 if (reg_renumber[i] >= 0
3562 && (unsigned int) reg_renumber[i] <= regno
3563 && ((unsigned int) reg_renumber[i]
3564 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3565 PSEUDO_REGNO_MODE (i))
3567 SET_REGNO_REG_SET (&spilled_pseudos, i);
3570 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3571 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3574 ior_hard_reg_set (set1, set2)
3575 HARD_REG_SET *set1, *set2;
3577 IOR_HARD_REG_SET (*set1, *set2);
3580 /* After find_reload_regs has been run for all insn that need reloads,
3581 and/or spill_hard_regs was called, this function is used to actually
3582 spill pseudo registers and try to reallocate them. It also sets up the
3583 spill_regs array for use by choose_reload_regs. */
3586 finish_spills (global)
3589 struct insn_chain *chain;
3590 int something_changed = 0;
3593 /* Build the spill_regs array for the function. */
3594 /* If there are some registers still to eliminate and one of the spill regs
3595 wasn't ever used before, additional stack space may have to be
3596 allocated to store this register. Thus, we may have changed the offset
3597 between the stack and frame pointers, so mark that something has changed.
3599 One might think that we need only set VAL to 1 if this is a call-used
3600 register. However, the set of registers that must be saved by the
3601 prologue is not identical to the call-used set. For example, the
3602 register used by the call insn for the return PC is a call-used register,
3603 but must be saved by the prologue. */
3606 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3607 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3609 spill_reg_order[i] = n_spills;
3610 spill_regs[n_spills++] = i;
3611 if (num_eliminable && ! regs_ever_live[i])
3612 something_changed = 1;
3613 regs_ever_live[i] = 1;
3616 spill_reg_order[i] = -1;
3618 EXECUTE_IF_SET_IN_REG_SET
3619 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3621 /* Record the current hard register the pseudo is allocated to in
3622 pseudo_previous_regs so we avoid reallocating it to the same
3623 hard reg in a later pass. */
3624 if (reg_renumber[i] < 0)
3627 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3628 /* Mark it as no longer having a hard register home. */
3629 reg_renumber[i] = -1;
3630 /* We will need to scan everything again. */
3631 something_changed = 1;
3634 /* Retry global register allocation if possible. */
3637 memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3638 /* For every insn that needs reloads, set the registers used as spill
3639 regs in pseudo_forbidden_regs for every pseudo live across the
3641 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3643 EXECUTE_IF_SET_IN_REG_SET
3644 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3646 ior_hard_reg_set (pseudo_forbidden_regs + i,
3647 &chain->used_spill_regs);
3649 EXECUTE_IF_SET_IN_REG_SET
3650 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3652 ior_hard_reg_set (pseudo_forbidden_regs + i,
3653 &chain->used_spill_regs);
3657 /* Retry allocating the spilled pseudos. For each reg, merge the
3658 various reg sets that indicate which hard regs can't be used,
3659 and call retry_global_alloc.
3660 We change spill_pseudos here to only contain pseudos that did not
3661 get a new hard register. */
3662 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3663 if (reg_old_renumber[i] != reg_renumber[i])
3665 HARD_REG_SET forbidden;
3666 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3667 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3668 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3669 retry_global_alloc (i, forbidden);
3670 if (reg_renumber[i] >= 0)
3671 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3675 /* Fix up the register information in the insn chain.
3676 This involves deleting those of the spilled pseudos which did not get
3677 a new hard register home from the live_{before,after} sets. */
3678 for (chain = reload_insn_chain; chain; chain = chain->next)
3680 HARD_REG_SET used_by_pseudos;
3681 HARD_REG_SET used_by_pseudos2;
3683 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3684 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3686 /* Mark any unallocated hard regs as available for spills. That
3687 makes inheritance work somewhat better. */
3688 if (chain->need_reload)
3690 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3691 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3692 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3694 /* Save the old value for the sanity test below. */
3695 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3697 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3698 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3699 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3700 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3702 /* Make sure we only enlarge the set. */
3703 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3709 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3710 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3712 int regno = reg_renumber[i];
3713 if (reg_old_renumber[i] == regno)
3716 alter_reg (i, reg_old_renumber[i]);
3717 reg_old_renumber[i] = regno;
3721 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3723 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3724 i, reg_renumber[i]);
3728 return something_changed;
3731 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3732 Also mark any hard registers used to store user variables as
3733 forbidden from being used for spill registers. */
3736 scan_paradoxical_subregs (x)
3740 register const char *fmt;
3741 register enum rtx_code code = GET_CODE (x);
3747 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3748 && REG_USERVAR_P (x))
3749 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3765 if (GET_CODE (SUBREG_REG (x)) == REG
3766 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3767 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3768 = GET_MODE_SIZE (GET_MODE (x));
3775 fmt = GET_RTX_FORMAT (code);
3776 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3779 scan_paradoxical_subregs (XEXP (x, i));
3780 else if (fmt[i] == 'E')
3783 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3784 scan_paradoxical_subregs (XVECEXP (x, i, j));
3789 /* Reload pseudo-registers into hard regs around each insn as needed.
3790 Additional register load insns are output before the insn that needs it
3791 and perhaps store insns after insns that modify the reloaded pseudo reg.
3793 reg_last_reload_reg and reg_reloaded_contents keep track of
3794 which registers are already available in reload registers.
3795 We update these for the reloads that we perform,
3796 as the insns are scanned. */
3799 reload_as_needed (live_known)
3802 struct insn_chain *chain;
3803 #if defined (AUTO_INC_DEC)
3808 memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx);
3809 memset ((char *) spill_reg_store, 0, sizeof spill_reg_store);
3810 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3811 reg_has_output_reload = (char *) xmalloc (max_regno);
3812 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3814 set_initial_elim_offsets ();
3816 for (chain = reload_insn_chain; chain; chain = chain->next)
3819 rtx insn = chain->insn;
3820 rtx old_next = NEXT_INSN (insn);
3822 /* If we pass a label, copy the offsets from the label information
3823 into the current offsets of each elimination. */
3824 if (GET_CODE (insn) == CODE_LABEL)
3825 set_offsets_for_label (insn);
3827 else if (INSN_P (insn))
3829 rtx oldpat = PATTERN (insn);
3831 /* If this is a USE and CLOBBER of a MEM, ensure that any
3832 references to eliminable registers have been removed. */
3834 if ((GET_CODE (PATTERN (insn)) == USE
3835 || GET_CODE (PATTERN (insn)) == CLOBBER)
3836 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3837 XEXP (XEXP (PATTERN (insn), 0), 0)
3838 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3839 GET_MODE (XEXP (PATTERN (insn), 0)),
3842 /* If we need to do register elimination processing, do so.
3843 This might delete the insn, in which case we are done. */
3844 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3846 eliminate_regs_in_insn (insn, 1);
3847 if (GET_CODE (insn) == NOTE)
3849 update_eliminable_offsets ();
3854 /* If need_elim is nonzero but need_reload is zero, one might think
3855 that we could simply set n_reloads to 0. However, find_reloads
3856 could have done some manipulation of the insn (such as swapping
3857 commutative operands), and these manipulations are lost during
3858 the first pass for every insn that needs register elimination.
3859 So the actions of find_reloads must be redone here. */
3861 if (! chain->need_elim && ! chain->need_reload
3862 && ! chain->need_operand_change)
3864 /* First find the pseudo regs that must be reloaded for this insn.
3865 This info is returned in the tables reload_... (see reload.h).
3866 Also modify the body of INSN by substituting RELOAD
3867 rtx's for those pseudo regs. */
3870 memset (reg_has_output_reload, 0, max_regno);
3871 CLEAR_HARD_REG_SET (reg_is_output_reload);
3873 find_reloads (insn, 1, spill_indirect_levels, live_known,
3877 if (num_eliminable && chain->need_elim)
3878 update_eliminable_offsets ();
3882 rtx next = NEXT_INSN (insn);
3885 prev = PREV_INSN (insn);
3887 /* Now compute which reload regs to reload them into. Perhaps
3888 reusing reload regs from previous insns, or else output
3889 load insns to reload them. Maybe output store insns too.
3890 Record the choices of reload reg in reload_reg_rtx. */
3891 choose_reload_regs (chain);
3893 /* Merge any reloads that we didn't combine for fear of
3894 increasing the number of spill registers needed but now
3895 discover can be safely merged. */
3896 if (SMALL_REGISTER_CLASSES)
3897 merge_assigned_reloads (insn);
3899 /* Generate the insns to reload operands into or out of
3900 their reload regs. */
3901 emit_reload_insns (chain);
3903 /* Substitute the chosen reload regs from reload_reg_rtx
3904 into the insn's body (or perhaps into the bodies of other
3905 load and store insn that we just made for reloading
3906 and that we moved the structure into). */
3907 subst_reloads (insn);
3909 /* If this was an ASM, make sure that all the reload insns
3910 we have generated are valid. If not, give an error
3913 if (asm_noperands (PATTERN (insn)) >= 0)
3914 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3915 if (p != insn && INSN_P (p)
3916 && (recog_memoized (p) < 0
3917 || (extract_insn (p), ! constrain_operands (1))))
3919 error_for_asm (insn,
3920 "`asm' operand requires impossible reload");
3922 NOTE_SOURCE_FILE (p) = 0;
3923 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3926 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3927 is no longer validly lying around to save a future reload.
3928 Note that this does not detect pseudos that were reloaded
3929 for this insn in order to be stored in
3930 (obeying register constraints). That is correct; such reload
3931 registers ARE still valid. */
3932 note_stores (oldpat, forget_old_reloads_1, NULL);
3934 /* There may have been CLOBBER insns placed after INSN. So scan
3935 between INSN and NEXT and use them to forget old reloads. */
3936 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3937 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3938 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3941 /* Likewise for regs altered by auto-increment in this insn.
3942 REG_INC notes have been changed by reloading:
3943 find_reloads_address_1 records substitutions for them,
3944 which have been performed by subst_reloads above. */
3945 for (i = n_reloads - 1; i >= 0; i--)
3947 rtx in_reg = rld[i].in_reg;
3950 enum rtx_code code = GET_CODE (in_reg);
3951 /* PRE_INC / PRE_DEC will have the reload register ending up
3952 with the same value as the stack slot, but that doesn't
3953 hold true for POST_INC / POST_DEC. Either we have to
3954 convert the memory access to a true POST_INC / POST_DEC,
3955 or we can't use the reload register for inheritance. */
3956 if ((code == POST_INC || code == POST_DEC)
3957 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3958 REGNO (rld[i].reg_rtx))
3959 /* Make sure it is the inc/dec pseudo, and not
3960 some other (e.g. output operand) pseudo. */
3961 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3962 == REGNO (XEXP (in_reg, 0))))
3965 rtx reload_reg = rld[i].reg_rtx;
3966 enum machine_mode mode = GET_MODE (reload_reg);
3970 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3972 /* We really want to ignore REG_INC notes here, so
3973 use PATTERN (p) as argument to reg_set_p . */
3974 if (reg_set_p (reload_reg, PATTERN (p)))
3976 n = count_occurrences (PATTERN (p), reload_reg, 0);
3981 n = validate_replace_rtx (reload_reg,
3982 gen_rtx (code, mode,
3986 /* We must also verify that the constraints
3987 are met after the replacement. */
3990 n = constrain_operands (1);
3994 /* If the constraints were not met, then
3995 undo the replacement. */
3998 validate_replace_rtx (gen_rtx (code, mode,
4010 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4012 /* Mark this as having an output reload so that the
4013 REG_INC processing code below won't invalidate
4014 the reload for inheritance. */
4015 SET_HARD_REG_BIT (reg_is_output_reload,
4016 REGNO (reload_reg));
4017 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4020 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4023 else if ((code == PRE_INC || code == PRE_DEC)
4024 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4025 REGNO (rld[i].reg_rtx))
4026 /* Make sure it is the inc/dec pseudo, and not
4027 some other (e.g. output operand) pseudo. */
4028 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4029 == REGNO (XEXP (in_reg, 0))))
4031 SET_HARD_REG_BIT (reg_is_output_reload,
4032 REGNO (rld[i].reg_rtx));
4033 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4037 /* If a pseudo that got a hard register is auto-incremented,
4038 we must purge records of copying it into pseudos without
4040 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4041 if (REG_NOTE_KIND (x) == REG_INC)
4043 /* See if this pseudo reg was reloaded in this insn.
4044 If so, its last-reload info is still valid
4045 because it is based on this insn's reload. */
4046 for (i = 0; i < n_reloads; i++)
4047 if (rld[i].out == XEXP (x, 0))
4051 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4055 /* A reload reg's contents are unknown after a label. */
4056 if (GET_CODE (insn) == CODE_LABEL)
4057 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4059 /* Don't assume a reload reg is still good after a call insn
4060 if it is a call-used reg. */
4061 else if (GET_CODE (insn) == CALL_INSN)
4062 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
4066 free (reg_last_reload_reg);
4067 free (reg_has_output_reload);
4070 /* Discard all record of any value reloaded from X,
4071 or reloaded in X from someplace else;
4072 unless X is an output reload reg of the current insn.
4074 X may be a hard reg (the reload reg)
4075 or it may be a pseudo reg that was reloaded from. */
4078 forget_old_reloads_1 (x, ignored, data)
4080 rtx ignored ATTRIBUTE_UNUSED;
4081 void *data ATTRIBUTE_UNUSED;
4087 /* note_stores does give us subregs of hard regs. */
4088 while (GET_CODE (x) == SUBREG)
4090 offset += SUBREG_WORD (x);
4094 if (GET_CODE (x) != REG)
4097 regno = REGNO (x) + offset;
4099 if (regno >= FIRST_PSEUDO_REGISTER)
4105 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4106 /* Storing into a spilled-reg invalidates its contents.
4107 This can happen if a block-local pseudo is allocated to that reg
4108 and it wasn't spilled because this block's total need is 0.
4109 Then some insn might have an optional reload and use this reg. */
4110 for (i = 0; i < nr; i++)
4111 /* But don't do this if the reg actually serves as an output
4112 reload reg in the current instruction. */
4114 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4116 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4117 spill_reg_store[regno + i] = 0;
4121 /* Since value of X has changed,
4122 forget any value previously copied from it. */
4125 /* But don't forget a copy if this is the output reload
4126 that establishes the copy's validity. */
4127 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4128 reg_last_reload_reg[regno + nr] = 0;
4131 /* The following HARD_REG_SETs indicate when each hard register is
4132 used for a reload of various parts of the current insn. */
4134 /* If reg is unavailable for all reloads. */
4135 static HARD_REG_SET reload_reg_unavailable;
4136 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4137 static HARD_REG_SET reload_reg_used;
4138 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4139 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4140 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4141 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4142 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4143 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4144 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4145 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4146 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4147 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4148 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4149 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4150 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4151 static HARD_REG_SET reload_reg_used_in_op_addr;
4152 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4153 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4154 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4155 static HARD_REG_SET reload_reg_used_in_insn;
4156 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4157 static HARD_REG_SET reload_reg_used_in_other_addr;
4159 /* If reg is in use as a reload reg for any sort of reload. */
4160 static HARD_REG_SET reload_reg_used_at_all;
4162 /* If reg is use as an inherited reload. We just mark the first register
4164 static HARD_REG_SET reload_reg_used_for_inherit;
4166 /* Records which hard regs are used in any way, either as explicit use or
4167 by being allocated to a pseudo during any point of the current insn. */
4168 static HARD_REG_SET reg_used_in_insn;
4170 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4171 TYPE. MODE is used to indicate how many consecutive regs are
4175 mark_reload_reg_in_use (regno, opnum, type, mode)
4178 enum reload_type type;
4179 enum machine_mode mode;
4181 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4184 for (i = regno; i < nregs + regno; i++)
4189 SET_HARD_REG_BIT (reload_reg_used, i);
4192 case RELOAD_FOR_INPUT_ADDRESS:
4193 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4196 case RELOAD_FOR_INPADDR_ADDRESS:
4197 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4200 case RELOAD_FOR_OUTPUT_ADDRESS:
4201 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4204 case RELOAD_FOR_OUTADDR_ADDRESS:
4205 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4208 case RELOAD_FOR_OPERAND_ADDRESS:
4209 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4212 case RELOAD_FOR_OPADDR_ADDR:
4213 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4216 case RELOAD_FOR_OTHER_ADDRESS:
4217 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4220 case RELOAD_FOR_INPUT:
4221 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4224 case RELOAD_FOR_OUTPUT:
4225 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4228 case RELOAD_FOR_INSN:
4229 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4233 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4237 /* Similarly, but show REGNO is no longer in use for a reload. */
4240 clear_reload_reg_in_use (regno, opnum, type, mode)
4243 enum reload_type type;
4244 enum machine_mode mode;
4246 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4247 unsigned int start_regno, end_regno, r;
4249 /* A complication is that for some reload types, inheritance might
4250 allow multiple reloads of the same types to share a reload register.
4251 We set check_opnum if we have to check only reloads with the same
4252 operand number, and check_any if we have to check all reloads. */
4253 int check_opnum = 0;
4255 HARD_REG_SET *used_in_set;
4260 used_in_set = &reload_reg_used;
4263 case RELOAD_FOR_INPUT_ADDRESS:
4264 used_in_set = &reload_reg_used_in_input_addr[opnum];
4267 case RELOAD_FOR_INPADDR_ADDRESS:
4269 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4272 case RELOAD_FOR_OUTPUT_ADDRESS:
4273 used_in_set = &reload_reg_used_in_output_addr[opnum];
4276 case RELOAD_FOR_OUTADDR_ADDRESS:
4278 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4281 case RELOAD_FOR_OPERAND_ADDRESS:
4282 used_in_set = &reload_reg_used_in_op_addr;
4285 case RELOAD_FOR_OPADDR_ADDR:
4287 used_in_set = &reload_reg_used_in_op_addr_reload;
4290 case RELOAD_FOR_OTHER_ADDRESS:
4291 used_in_set = &reload_reg_used_in_other_addr;
4295 case RELOAD_FOR_INPUT:
4296 used_in_set = &reload_reg_used_in_input[opnum];
4299 case RELOAD_FOR_OUTPUT:
4300 used_in_set = &reload_reg_used_in_output[opnum];
4303 case RELOAD_FOR_INSN:
4304 used_in_set = &reload_reg_used_in_insn;
4309 /* We resolve conflicts with remaining reloads of the same type by
4310 excluding the intervals of of reload registers by them from the
4311 interval of freed reload registers. Since we only keep track of
4312 one set of interval bounds, we might have to exclude somewhat
4313 more then what would be necessary if we used a HARD_REG_SET here.
4314 But this should only happen very infrequently, so there should
4315 be no reason to worry about it. */
4317 start_regno = regno;
4318 end_regno = regno + nregs;
4319 if (check_opnum || check_any)
4321 for (i = n_reloads - 1; i >= 0; i--)
4323 if (rld[i].when_needed == type
4324 && (check_any || rld[i].opnum == opnum)
4327 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4328 unsigned int conflict_end
4330 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4332 /* If there is an overlap with the first to-be-freed register,
4333 adjust the interval start. */
4334 if (conflict_start <= start_regno && conflict_end > start_regno)
4335 start_regno = conflict_end;
4336 /* Otherwise, if there is a conflict with one of the other
4337 to-be-freed registers, adjust the interval end. */
4338 if (conflict_start > start_regno && conflict_start < end_regno)
4339 end_regno = conflict_start;
4344 for (r = start_regno; r < end_regno; r++)
4345 CLEAR_HARD_REG_BIT (*used_in_set, r);
4348 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4349 specified by OPNUM and TYPE. */
4352 reload_reg_free_p (regno, opnum, type)
4355 enum reload_type type;
4359 /* In use for a RELOAD_OTHER means it's not available for anything. */
4360 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4361 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4367 /* In use for anything means we can't use it for RELOAD_OTHER. */
4368 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4369 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4370 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4373 for (i = 0; i < reload_n_operands; i++)
4374 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4375 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4376 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4377 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4378 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4379 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4384 case RELOAD_FOR_INPUT:
4385 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4386 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4389 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4392 /* If it is used for some other input, can't use it. */
4393 for (i = 0; i < reload_n_operands; i++)
4394 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4397 /* If it is used in a later operand's address, can't use it. */
4398 for (i = opnum + 1; i < reload_n_operands; i++)
4399 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4400 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4405 case RELOAD_FOR_INPUT_ADDRESS:
4406 /* Can't use a register if it is used for an input address for this
4407 operand or used as an input in an earlier one. */
4408 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4409 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4412 for (i = 0; i < opnum; i++)
4413 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4418 case RELOAD_FOR_INPADDR_ADDRESS:
4419 /* Can't use a register if it is used for an input address
4420 for this operand or used as an input in an earlier
4422 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4425 for (i = 0; i < opnum; i++)
4426 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4431 case RELOAD_FOR_OUTPUT_ADDRESS:
4432 /* Can't use a register if it is used for an output address for this
4433 operand or used as an output in this or a later operand. */
4434 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4437 for (i = opnum; i < reload_n_operands; i++)
4438 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4443 case RELOAD_FOR_OUTADDR_ADDRESS:
4444 /* Can't use a register if it is used for an output address
4445 for this operand or used as an output in this or a
4447 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4450 for (i = opnum; i < reload_n_operands; i++)
4451 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4456 case RELOAD_FOR_OPERAND_ADDRESS:
4457 for (i = 0; i < reload_n_operands; i++)
4458 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4461 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4462 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4464 case RELOAD_FOR_OPADDR_ADDR:
4465 for (i = 0; i < reload_n_operands; i++)
4466 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4469 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4471 case RELOAD_FOR_OUTPUT:
4472 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4473 outputs, or an operand address for this or an earlier output. */
4474 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4477 for (i = 0; i < reload_n_operands; i++)
4478 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4481 for (i = 0; i <= opnum; i++)
4482 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4483 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4488 case RELOAD_FOR_INSN:
4489 for (i = 0; i < reload_n_operands; i++)
4490 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4491 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4494 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4495 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4497 case RELOAD_FOR_OTHER_ADDRESS:
4498 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4503 /* Return 1 if the value in reload reg REGNO, as used by a reload
4504 needed for the part of the insn specified by OPNUM and TYPE,
4505 is still available in REGNO at the end of the insn.
4507 We can assume that the reload reg was already tested for availability
4508 at the time it is needed, and we should not check this again,
4509 in case the reg has already been marked in use. */
4512 reload_reg_reaches_end_p (regno, opnum, type)
4515 enum reload_type type;
4522 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4523 its value must reach the end. */
4526 /* If this use is for part of the insn,
4527 its value reaches if no subsequent part uses the same register.
4528 Just like the above function, don't try to do this with lots
4531 case RELOAD_FOR_OTHER_ADDRESS:
4532 /* Here we check for everything else, since these don't conflict
4533 with anything else and everything comes later. */
4535 for (i = 0; i < reload_n_operands; i++)
4536 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4537 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4538 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4539 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4540 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4541 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4544 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4545 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4546 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4548 case RELOAD_FOR_INPUT_ADDRESS:
4549 case RELOAD_FOR_INPADDR_ADDRESS:
4550 /* Similar, except that we check only for this and subsequent inputs
4551 and the address of only subsequent inputs and we do not need
4552 to check for RELOAD_OTHER objects since they are known not to
4555 for (i = opnum; i < reload_n_operands; i++)
4556 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4559 for (i = opnum + 1; i < reload_n_operands; i++)
4560 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4561 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4564 for (i = 0; i < reload_n_operands; i++)
4565 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4566 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4567 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4570 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4573 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4574 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4575 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4577 case RELOAD_FOR_INPUT:
4578 /* Similar to input address, except we start at the next operand for
4579 both input and input address and we do not check for
4580 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4583 for (i = opnum + 1; i < reload_n_operands; i++)
4584 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4585 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4586 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4589 /* ... fall through ... */
4591 case RELOAD_FOR_OPERAND_ADDRESS:
4592 /* Check outputs and their addresses. */
4594 for (i = 0; i < reload_n_operands; i++)
4595 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4596 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4597 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4600 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4602 case RELOAD_FOR_OPADDR_ADDR:
4603 for (i = 0; i < reload_n_operands; i++)
4604 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4605 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4606 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4609 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4610 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4611 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4613 case RELOAD_FOR_INSN:
4614 /* These conflict with other outputs with RELOAD_OTHER. So
4615 we need only check for output addresses. */
4619 /* ... fall through ... */
4621 case RELOAD_FOR_OUTPUT:
4622 case RELOAD_FOR_OUTPUT_ADDRESS:
4623 case RELOAD_FOR_OUTADDR_ADDRESS:
4624 /* We already know these can't conflict with a later output. So the
4625 only thing to check are later output addresses. */
4626 for (i = opnum + 1; i < reload_n_operands; i++)
4627 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4628 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4637 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4640 This function uses the same algorithm as reload_reg_free_p above. */
4643 reloads_conflict (r1, r2)
4646 enum reload_type r1_type = rld[r1].when_needed;
4647 enum reload_type r2_type = rld[r2].when_needed;
4648 int r1_opnum = rld[r1].opnum;
4649 int r2_opnum = rld[r2].opnum;
4651 /* RELOAD_OTHER conflicts with everything. */
4652 if (r2_type == RELOAD_OTHER)
4655 /* Otherwise, check conflicts differently for each type. */
4659 case RELOAD_FOR_INPUT:
4660 return (r2_type == RELOAD_FOR_INSN
4661 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4662 || r2_type == RELOAD_FOR_OPADDR_ADDR
4663 || r2_type == RELOAD_FOR_INPUT
4664 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4665 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4666 && r2_opnum > r1_opnum));
4668 case RELOAD_FOR_INPUT_ADDRESS:
4669 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4670 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4672 case RELOAD_FOR_INPADDR_ADDRESS:
4673 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4674 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4676 case RELOAD_FOR_OUTPUT_ADDRESS:
4677 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4678 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4680 case RELOAD_FOR_OUTADDR_ADDRESS:
4681 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4682 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4684 case RELOAD_FOR_OPERAND_ADDRESS:
4685 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4686 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4688 case RELOAD_FOR_OPADDR_ADDR:
4689 return (r2_type == RELOAD_FOR_INPUT
4690 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4692 case RELOAD_FOR_OUTPUT:
4693 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4694 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4695 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4696 && r2_opnum <= r1_opnum));
4698 case RELOAD_FOR_INSN:
4699 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4700 || r2_type == RELOAD_FOR_INSN
4701 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4703 case RELOAD_FOR_OTHER_ADDRESS:
4704 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4714 /* Indexed by reload number, 1 if incoming value
4715 inherited from previous insns. */
4716 char reload_inherited[MAX_RELOADS];
4718 /* For an inherited reload, this is the insn the reload was inherited from,
4719 if we know it. Otherwise, this is 0. */
4720 rtx reload_inheritance_insn[MAX_RELOADS];
4722 /* If non-zero, this is a place to get the value of the reload,
4723 rather than using reload_in. */
4724 rtx reload_override_in[MAX_RELOADS];
4726 /* For each reload, the hard register number of the register used,
4727 or -1 if we did not need a register for this reload. */
4728 int reload_spill_index[MAX_RELOADS];
4730 /* Subroutine of free_for_value_p, used to check a single register.
4731 START_REGNO is the starting regno of the full reload register
4732 (possibly comprising multiple hard registers) that we are considering. */
4735 reload_reg_free_for_value_p (start_regno, regno, opnum, type, value, out,
4736 reloadnum, ignore_address_reloads)
4737 int start_regno, regno;
4739 enum reload_type type;
4742 int ignore_address_reloads;
4745 /* Set if we see an input reload that must not share its reload register
4746 with any new earlyclobber, but might otherwise share the reload
4747 register with an output or input-output reload. */
4748 int check_earlyclobber = 0;
4752 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4755 if (out == const0_rtx)
4761 /* We use some pseudo 'time' value to check if the lifetimes of the
4762 new register use would overlap with the one of a previous reload
4763 that is not read-only or uses a different value.
4764 The 'time' used doesn't have to be linear in any shape or form, just
4766 Some reload types use different 'buckets' for each operand.
4767 So there are MAX_RECOG_OPERANDS different time values for each
4769 We compute TIME1 as the time when the register for the prospective
4770 new reload ceases to be live, and TIME2 for each existing
4771 reload as the time when that the reload register of that reload
4773 Where there is little to be gained by exact lifetime calculations,
4774 we just make conservative assumptions, i.e. a longer lifetime;
4775 this is done in the 'default:' cases. */
4778 case RELOAD_FOR_OTHER_ADDRESS:
4779 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4780 time1 = copy ? 0 : 1;
4783 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4785 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4786 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4787 respectively, to the time values for these, we get distinct time
4788 values. To get distinct time values for each operand, we have to
4789 multiply opnum by at least three. We round that up to four because
4790 multiply by four is often cheaper. */
4791 case RELOAD_FOR_INPADDR_ADDRESS:
4792 time1 = opnum * 4 + 2;
4794 case RELOAD_FOR_INPUT_ADDRESS:
4795 time1 = opnum * 4 + 3;
4797 case RELOAD_FOR_INPUT:
4798 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4799 executes (inclusive). */
4800 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4802 case RELOAD_FOR_OPADDR_ADDR:
4804 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4805 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4807 case RELOAD_FOR_OPERAND_ADDRESS:
4808 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4810 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4812 case RELOAD_FOR_OUTADDR_ADDRESS:
4813 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4815 case RELOAD_FOR_OUTPUT_ADDRESS:
4816 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4819 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4822 for (i = 0; i < n_reloads; i++)
4824 rtx reg = rld[i].reg_rtx;
4825 if (reg && GET_CODE (reg) == REG
4826 && ((unsigned) regno - true_regnum (reg)
4827 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
4830 rtx other_input = rld[i].in;
4832 /* If the other reload loads the same input value, that
4833 will not cause a conflict only if it's loading it into
4834 the same register. */
4835 if (true_regnum (reg) != start_regno)
4836 other_input = NULL_RTX;
4837 if (! other_input || ! rtx_equal_p (other_input, value)
4838 || rld[i].out || out)
4841 switch (rld[i].when_needed)
4843 case RELOAD_FOR_OTHER_ADDRESS:
4846 case RELOAD_FOR_INPADDR_ADDRESS:
4847 /* find_reloads makes sure that a
4848 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4849 by at most one - the first -
4850 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4851 address reload is inherited, the address address reload
4852 goes away, so we can ignore this conflict. */
4853 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4854 && ignore_address_reloads
4855 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4856 Then the address address is still needed to store
4857 back the new address. */
4858 && ! rld[reloadnum].out)
4860 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4861 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4863 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4864 && ignore_address_reloads
4865 /* Unless we are reloading an auto_inc expression. */
4866 && ! rld[reloadnum].out)
4868 time2 = rld[i].opnum * 4 + 2;
4870 case RELOAD_FOR_INPUT_ADDRESS:
4871 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4872 && ignore_address_reloads
4873 && ! rld[reloadnum].out)
4875 time2 = rld[i].opnum * 4 + 3;
4877 case RELOAD_FOR_INPUT:
4878 time2 = rld[i].opnum * 4 + 4;
4879 check_earlyclobber = 1;
4881 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4882 == MAX_RECOG_OPERAND * 4 */
4883 case RELOAD_FOR_OPADDR_ADDR:
4884 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4885 && ignore_address_reloads
4886 && ! rld[reloadnum].out)
4888 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4890 case RELOAD_FOR_OPERAND_ADDRESS:
4891 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4892 check_earlyclobber = 1;
4894 case RELOAD_FOR_INSN:
4895 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4897 case RELOAD_FOR_OUTPUT:
4898 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4899 instruction is executed. */
4900 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4902 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4903 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4905 case RELOAD_FOR_OUTADDR_ADDRESS:
4906 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4907 && ignore_address_reloads
4908 && ! rld[reloadnum].out)
4910 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4912 case RELOAD_FOR_OUTPUT_ADDRESS:
4913 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4916 /* If there is no conflict in the input part, handle this
4917 like an output reload. */
4918 if (! rld[i].in || rtx_equal_p (other_input, value))
4920 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4921 /* Earlyclobbered outputs must conflict with inputs. */
4922 if (earlyclobber_operand_p (rld[i].out))
4923 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4928 /* RELOAD_OTHER might be live beyond instruction execution,
4929 but this is not obvious when we set time2 = 1. So check
4930 here if there might be a problem with the new reload
4931 clobbering the register used by the RELOAD_OTHER. */
4939 && (! rld[i].in || rld[i].out
4940 || ! rtx_equal_p (other_input, value)))
4941 || (out && rld[reloadnum].out_reg
4942 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4948 /* Earlyclobbered outputs must conflict with inputs. */
4949 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4955 /* Return 1 if the value in reload reg REGNO, as used by a reload
4956 needed for the part of the insn specified by OPNUM and TYPE,
4957 may be used to load VALUE into it.
4959 MODE is the mode in which the register is used, this is needed to
4960 determine how many hard regs to test.
4962 Other read-only reloads with the same value do not conflict
4963 unless OUT is non-zero and these other reloads have to live while
4964 output reloads live.
4965 If OUT is CONST0_RTX, this is a special case: it means that the
4966 test should not be for using register REGNO as reload register, but
4967 for copying from register REGNO into the reload register.
4969 RELOADNUM is the number of the reload we want to load this value for;
4970 a reload does not conflict with itself.
4972 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4973 reloads that load an address for the very reload we are considering.
4975 The caller has to make sure that there is no conflict with the return
4979 free_for_value_p (regno, mode, opnum, type, value, out, reloadnum,
4980 ignore_address_reloads)
4982 enum machine_mode mode;
4984 enum reload_type type;
4987 int ignore_address_reloads;
4989 int nregs = HARD_REGNO_NREGS (regno, mode);
4991 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4992 value, out, reloadnum,
4993 ignore_address_reloads))
4998 /* Determine whether the reload reg X overlaps any rtx'es used for
4999 overriding inheritance. Return nonzero if so. */
5002 conflicts_with_override (x)
5006 for (i = 0; i < n_reloads; i++)
5007 if (reload_override_in[i]
5008 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5013 /* Give an error message saying we failed to find a reload for INSN,
5014 and clear out reload R. */
5016 failed_reload (insn, r)
5020 if (asm_noperands (PATTERN (insn)) < 0)
5021 /* It's the compiler's fault. */
5022 fatal_insn ("Could not find a spill register", insn);
5024 /* It's the user's fault; the operand's mode and constraint
5025 don't match. Disable this reload so we don't crash in final. */
5026 error_for_asm (insn,
5027 "`asm' operand constraint incompatible with operand size");
5031 rld[r].optional = 1;
5032 rld[r].secondary_p = 1;
5035 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5036 for reload R. If it's valid, get an rtx for it. Return nonzero if
5039 set_reload_reg (i, r)
5043 rtx reg = spill_reg_rtx[i];
5045 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5046 spill_reg_rtx[i] = reg
5047 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5049 regno = true_regnum (reg);
5051 /* Detect when the reload reg can't hold the reload mode.
5052 This used to be one `if', but Sequent compiler can't handle that. */
5053 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5055 enum machine_mode test_mode = VOIDmode;
5057 test_mode = GET_MODE (rld[r].in);
5058 /* If rld[r].in has VOIDmode, it means we will load it
5059 in whatever mode the reload reg has: to wit, rld[r].mode.
5060 We have already tested that for validity. */
5061 /* Aside from that, we need to test that the expressions
5062 to reload from or into have modes which are valid for this
5063 reload register. Otherwise the reload insns would be invalid. */
5064 if (! (rld[r].in != 0 && test_mode != VOIDmode
5065 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5066 if (! (rld[r].out != 0
5067 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5069 /* The reg is OK. */
5072 /* Mark as in use for this insn the reload regs we use
5074 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5075 rld[r].when_needed, rld[r].mode);
5077 rld[r].reg_rtx = reg;
5078 reload_spill_index[r] = spill_regs[i];
5085 /* Find a spill register to use as a reload register for reload R.
5086 LAST_RELOAD is non-zero if this is the last reload for the insn being
5089 Set rld[R].reg_rtx to the register allocated.
5091 We return 1 if successful, or 0 if we couldn't find a spill reg and
5092 we didn't change anything. */
5095 allocate_reload_reg (chain, r, last_reload)
5096 struct insn_chain *chain ATTRIBUTE_UNUSED;
5102 /* If we put this reload ahead, thinking it is a group,
5103 then insist on finding a group. Otherwise we can grab a
5104 reg that some other reload needs.
5105 (That can happen when we have a 68000 DATA_OR_FP_REG
5106 which is a group of data regs or one fp reg.)
5107 We need not be so restrictive if there are no more reloads
5110 ??? Really it would be nicer to have smarter handling
5111 for that kind of reg class, where a problem like this is normal.
5112 Perhaps those classes should be avoided for reloading
5113 by use of more alternatives. */
5115 int force_group = rld[r].nregs > 1 && ! last_reload;
5117 /* If we want a single register and haven't yet found one,
5118 take any reg in the right class and not in use.
5119 If we want a consecutive group, here is where we look for it.
5121 We use two passes so we can first look for reload regs to
5122 reuse, which are already in use for other reloads in this insn,
5123 and only then use additional registers.
5124 I think that maximizing reuse is needed to make sure we don't
5125 run out of reload regs. Suppose we have three reloads, and
5126 reloads A and B can share regs. These need two regs.
5127 Suppose A and B are given different regs.
5128 That leaves none for C. */
5129 for (pass = 0; pass < 2; pass++)
5131 /* I is the index in spill_regs.
5132 We advance it round-robin between insns to use all spill regs
5133 equally, so that inherited reloads have a chance
5134 of leapfrogging each other. */
5138 for (count = 0; count < n_spills; count++)
5140 int class = (int) rld[r].class;
5146 regnum = spill_regs[i];
5148 if ((reload_reg_free_p (regnum, rld[r].opnum,
5151 /* We check reload_reg_used to make sure we
5152 don't clobber the return register. */
5153 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5154 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5155 rld[r].when_needed, rld[r].in,
5157 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5158 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5159 /* Look first for regs to share, then for unshared. But
5160 don't share regs used for inherited reloads; they are
5161 the ones we want to preserve. */
5163 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5165 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5168 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5169 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5170 (on 68000) got us two FP regs. If NR is 1,
5171 we would reject both of them. */
5174 /* If we need only one reg, we have already won. */
5177 /* But reject a single reg if we demand a group. */
5182 /* Otherwise check that as many consecutive regs as we need
5183 are available here. */
5186 int regno = regnum + nr - 1;
5187 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5188 && spill_reg_order[regno] >= 0
5189 && reload_reg_free_p (regno, rld[r].opnum,
5190 rld[r].when_needed)))
5199 /* If we found something on pass 1, omit pass 2. */
5200 if (count < n_spills)
5204 /* We should have found a spill register by now. */
5205 if (count >= n_spills)
5208 /* I is the index in SPILL_REG_RTX of the reload register we are to
5209 allocate. Get an rtx for it and find its register number. */
5211 return set_reload_reg (i, r);
5214 /* Initialize all the tables needed to allocate reload registers.
5215 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5216 is the array we use to restore the reg_rtx field for every reload. */
5219 choose_reload_regs_init (chain, save_reload_reg_rtx)
5220 struct insn_chain *chain;
5221 rtx *save_reload_reg_rtx;
5225 for (i = 0; i < n_reloads; i++)
5226 rld[i].reg_rtx = save_reload_reg_rtx[i];
5228 memset (reload_inherited, 0, MAX_RELOADS);
5229 memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5230 memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5232 CLEAR_HARD_REG_SET (reload_reg_used);
5233 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5234 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5235 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5236 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5237 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5239 CLEAR_HARD_REG_SET (reg_used_in_insn);
5242 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5243 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5244 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5245 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5246 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5247 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5250 for (i = 0; i < reload_n_operands; i++)
5252 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5253 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5254 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5255 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5256 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5257 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5260 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5262 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5264 for (i = 0; i < n_reloads; i++)
5265 /* If we have already decided to use a certain register,
5266 don't use it in another way. */
5268 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5269 rld[i].when_needed, rld[i].mode);
5272 /* Assign hard reg targets for the pseudo-registers we must reload
5273 into hard regs for this insn.
5274 Also output the instructions to copy them in and out of the hard regs.
5276 For machines with register classes, we are responsible for
5277 finding a reload reg in the proper class. */
5280 choose_reload_regs (chain)
5281 struct insn_chain *chain;
5283 rtx insn = chain->insn;
5285 unsigned int max_group_size = 1;
5286 enum reg_class group_class = NO_REGS;
5287 int pass, win, inheritance;
5289 rtx save_reload_reg_rtx[MAX_RELOADS];
5291 /* In order to be certain of getting the registers we need,
5292 we must sort the reloads into order of increasing register class.
5293 Then our grabbing of reload registers will parallel the process
5294 that provided the reload registers.
5296 Also note whether any of the reloads wants a consecutive group of regs.
5297 If so, record the maximum size of the group desired and what
5298 register class contains all the groups needed by this insn. */
5300 for (j = 0; j < n_reloads; j++)
5302 reload_order[j] = j;
5303 reload_spill_index[j] = -1;
5305 if (rld[j].nregs > 1)
5307 max_group_size = MAX (rld[j].nregs, max_group_size);
5309 = reg_class_superunion[(int) rld[j].class][(int)group_class];
5312 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5316 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5318 /* If -O, try first with inheritance, then turning it off.
5319 If not -O, don't do inheritance.
5320 Using inheritance when not optimizing leads to paradoxes
5321 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5322 because one side of the comparison might be inherited. */
5324 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5326 choose_reload_regs_init (chain, save_reload_reg_rtx);
5328 /* Process the reloads in order of preference just found.
5329 Beyond this point, subregs can be found in reload_reg_rtx.
5331 This used to look for an existing reloaded home for all of the
5332 reloads, and only then perform any new reloads. But that could lose
5333 if the reloads were done out of reg-class order because a later
5334 reload with a looser constraint might have an old home in a register
5335 needed by an earlier reload with a tighter constraint.
5337 To solve this, we make two passes over the reloads, in the order
5338 described above. In the first pass we try to inherit a reload
5339 from a previous insn. If there is a later reload that needs a
5340 class that is a proper subset of the class being processed, we must
5341 also allocate a spill register during the first pass.
5343 Then make a second pass over the reloads to allocate any reloads
5344 that haven't been given registers yet. */
5346 for (j = 0; j < n_reloads; j++)
5348 register int r = reload_order[j];
5349 rtx search_equiv = NULL_RTX;
5351 /* Ignore reloads that got marked inoperative. */
5352 if (rld[r].out == 0 && rld[r].in == 0
5353 && ! rld[r].secondary_p)
5356 /* If find_reloads chose to use reload_in or reload_out as a reload
5357 register, we don't need to chose one. Otherwise, try even if it
5358 found one since we might save an insn if we find the value lying
5360 Try also when reload_in is a pseudo without a hard reg. */
5361 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5362 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5363 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5364 && GET_CODE (rld[r].in) != MEM
5365 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5368 #if 0 /* No longer needed for correct operation.
5369 It might give better code, or might not; worth an experiment? */
5370 /* If this is an optional reload, we can't inherit from earlier insns
5371 until we are sure that any non-optional reloads have been allocated.
5372 The following code takes advantage of the fact that optional reloads
5373 are at the end of reload_order. */
5374 if (rld[r].optional != 0)
5375 for (i = 0; i < j; i++)
5376 if ((rld[reload_order[i]].out != 0
5377 || rld[reload_order[i]].in != 0
5378 || rld[reload_order[i]].secondary_p)
5379 && ! rld[reload_order[i]].optional
5380 && rld[reload_order[i]].reg_rtx == 0)
5381 allocate_reload_reg (chain, reload_order[i], 0);
5384 /* First see if this pseudo is already available as reloaded
5385 for a previous insn. We cannot try to inherit for reloads
5386 that are smaller than the maximum number of registers needed
5387 for groups unless the register we would allocate cannot be used
5390 We could check here to see if this is a secondary reload for
5391 an object that is already in a register of the desired class.
5392 This would avoid the need for the secondary reload register.
5393 But this is complex because we can't easily determine what
5394 objects might want to be loaded via this reload. So let a
5395 register be allocated here. In `emit_reload_insns' we suppress
5396 one of the loads in the case described above. */
5401 register int regno = -1;
5402 enum machine_mode mode = VOIDmode;
5406 else if (GET_CODE (rld[r].in) == REG)
5408 regno = REGNO (rld[r].in);
5409 mode = GET_MODE (rld[r].in);
5411 else if (GET_CODE (rld[r].in_reg) == REG)
5413 regno = REGNO (rld[r].in_reg);
5414 mode = GET_MODE (rld[r].in_reg);
5416 else if (GET_CODE (rld[r].in_reg) == SUBREG
5417 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5419 word = SUBREG_WORD (rld[r].in_reg);
5420 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5421 if (regno < FIRST_PSEUDO_REGISTER)
5423 mode = GET_MODE (rld[r].in_reg);
5426 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5427 || GET_CODE (rld[r].in_reg) == PRE_DEC
5428 || GET_CODE (rld[r].in_reg) == POST_INC
5429 || GET_CODE (rld[r].in_reg) == POST_DEC)
5430 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5432 regno = REGNO (XEXP (rld[r].in_reg, 0));
5433 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5434 rld[r].out = rld[r].in;
5438 /* This won't work, since REGNO can be a pseudo reg number.
5439 Also, it takes much more hair to keep track of all the things
5440 that can invalidate an inherited reload of part of a pseudoreg. */
5441 else if (GET_CODE (rld[r].in) == SUBREG
5442 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5443 regno = REGNO (SUBREG_REG (rld[r].in)) + SUBREG_WORD (rld[r].in);
5446 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5448 enum reg_class class = rld[r].class, last_class;
5449 rtx last_reg = reg_last_reload_reg[regno];
5450 enum machine_mode need_mode;
5452 i = REGNO (last_reg) + word;
5453 last_class = REGNO_REG_CLASS (i);
5459 = smallest_mode_for_size (GET_MODE_SIZE (mode)
5460 + word * UNITS_PER_WORD,
5461 GET_MODE_CLASS (mode));
5464 #ifdef CLASS_CANNOT_CHANGE_MODE
5466 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], i)
5467 ? ! CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (last_reg),
5469 : (GET_MODE_SIZE (GET_MODE (last_reg))
5470 >= GET_MODE_SIZE (need_mode)))
5472 (GET_MODE_SIZE (GET_MODE (last_reg))
5473 >= GET_MODE_SIZE (need_mode))
5475 && reg_reloaded_contents[i] == regno
5476 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5477 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5478 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5479 /* Even if we can't use this register as a reload
5480 register, we might use it for reload_override_in,
5481 if copying it to the desired class is cheap
5483 || ((REGISTER_MOVE_COST (mode, last_class, class)
5484 < MEMORY_MOVE_COST (mode, class, 1))
5485 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5486 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5490 #ifdef SECONDARY_MEMORY_NEEDED
5491 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5496 && (rld[r].nregs == max_group_size
5497 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5499 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5500 rld[r].when_needed, rld[r].in,
5503 /* If a group is needed, verify that all the subsequent
5504 registers still have their values intact. */
5505 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5508 for (k = 1; k < nr; k++)
5509 if (reg_reloaded_contents[i + k] != regno
5510 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5517 last_reg = (GET_MODE (last_reg) == mode
5518 ? last_reg : gen_rtx_REG (mode, i));
5520 /* We found a register that contains the
5521 value we need. If this register is the
5522 same as an `earlyclobber' operand of the
5523 current insn, just mark it as a place to
5524 reload from since we can't use it as the
5525 reload register itself. */
5527 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5528 if (reg_overlap_mentioned_for_reload_p
5529 (reg_last_reload_reg[regno],
5530 reload_earlyclobbers[i1]))
5533 if (i1 != n_earlyclobbers
5534 || ! (free_for_value_p (i, rld[r].mode,
5536 rld[r].when_needed, rld[r].in,
5538 /* Don't use it if we'd clobber a pseudo reg. */
5539 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5541 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5542 /* Don't clobber the frame pointer. */
5543 || (i == HARD_FRAME_POINTER_REGNUM
5545 /* Don't really use the inherited spill reg
5546 if we need it wider than we've got it. */
5547 || (GET_MODE_SIZE (rld[r].mode)
5548 > GET_MODE_SIZE (mode))
5549 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5552 /* If find_reloads chose reload_out as reload
5553 register, stay with it - that leaves the
5554 inherited register for subsequent reloads. */
5555 || (rld[r].out && rld[r].reg_rtx
5556 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5558 if (! rld[r].optional)
5560 reload_override_in[r] = last_reg;
5561 reload_inheritance_insn[r]
5562 = reg_reloaded_insn[i];
5568 /* We can use this as a reload reg. */
5569 /* Mark the register as in use for this part of
5571 mark_reload_reg_in_use (i,
5575 rld[r].reg_rtx = last_reg;
5576 reload_inherited[r] = 1;
5577 reload_inheritance_insn[r]
5578 = reg_reloaded_insn[i];
5579 reload_spill_index[r] = i;
5580 for (k = 0; k < nr; k++)
5581 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5589 /* Here's another way to see if the value is already lying around. */
5592 && ! reload_inherited[r]
5594 && (CONSTANT_P (rld[r].in)
5595 || GET_CODE (rld[r].in) == PLUS
5596 || GET_CODE (rld[r].in) == REG
5597 || GET_CODE (rld[r].in) == MEM)
5598 && (rld[r].nregs == max_group_size
5599 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5600 search_equiv = rld[r].in;
5601 /* If this is an output reload from a simple move insn, look
5602 if an equivalence for the input is available. */
5603 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5605 rtx set = single_set (insn);
5608 && rtx_equal_p (rld[r].out, SET_DEST (set))
5609 && CONSTANT_P (SET_SRC (set)))
5610 search_equiv = SET_SRC (set);
5616 = find_equiv_reg (search_equiv, insn, rld[r].class,
5617 -1, NULL_PTR, 0, rld[r].mode);
5622 if (GET_CODE (equiv) == REG)
5623 regno = REGNO (equiv);
5624 else if (GET_CODE (equiv) == SUBREG)
5626 /* This must be a SUBREG of a hard register.
5627 Make a new REG since this might be used in an
5628 address and not all machines support SUBREGs
5630 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5631 equiv = gen_rtx_REG (rld[r].mode, regno);
5637 /* If we found a spill reg, reject it unless it is free
5638 and of the desired class. */
5640 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5641 && ! free_for_value_p (regno, rld[r].mode,
5642 rld[r].opnum, rld[r].when_needed,
5643 rld[r].in, rld[r].out, r, 1))
5644 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5648 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5651 /* We found a register that contains the value we need.
5652 If this register is the same as an `earlyclobber' operand
5653 of the current insn, just mark it as a place to reload from
5654 since we can't use it as the reload register itself. */
5657 for (i = 0; i < n_earlyclobbers; i++)
5658 if (reg_overlap_mentioned_for_reload_p (equiv,
5659 reload_earlyclobbers[i]))
5661 if (! rld[r].optional)
5662 reload_override_in[r] = equiv;
5667 /* If the equiv register we have found is explicitly clobbered
5668 in the current insn, it depends on the reload type if we
5669 can use it, use it for reload_override_in, or not at all.
5670 In particular, we then can't use EQUIV for a
5671 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5675 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5676 switch (rld[r].when_needed)
5678 case RELOAD_FOR_OTHER_ADDRESS:
5679 case RELOAD_FOR_INPADDR_ADDRESS:
5680 case RELOAD_FOR_INPUT_ADDRESS:
5681 case RELOAD_FOR_OPADDR_ADDR:
5684 case RELOAD_FOR_INPUT:
5685 case RELOAD_FOR_OPERAND_ADDRESS:
5686 if (! rld[r].optional)
5687 reload_override_in[r] = equiv;
5693 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5694 switch (rld[r].when_needed)
5696 case RELOAD_FOR_OTHER_ADDRESS:
5697 case RELOAD_FOR_INPADDR_ADDRESS:
5698 case RELOAD_FOR_INPUT_ADDRESS:
5699 case RELOAD_FOR_OPADDR_ADDR:
5700 case RELOAD_FOR_OPERAND_ADDRESS:
5701 case RELOAD_FOR_INPUT:
5704 if (! rld[r].optional)
5705 reload_override_in[r] = equiv;
5713 /* If we found an equivalent reg, say no code need be generated
5714 to load it, and use it as our reload reg. */
5715 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5717 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5719 rld[r].reg_rtx = equiv;
5720 reload_inherited[r] = 1;
5722 /* If reg_reloaded_valid is not set for this register,
5723 there might be a stale spill_reg_store lying around.
5724 We must clear it, since otherwise emit_reload_insns
5725 might delete the store. */
5726 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5727 spill_reg_store[regno] = NULL_RTX;
5728 /* If any of the hard registers in EQUIV are spill
5729 registers, mark them as in use for this insn. */
5730 for (k = 0; k < nr; k++)
5732 i = spill_reg_order[regno + k];
5735 mark_reload_reg_in_use (regno, rld[r].opnum,
5738 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5745 /* If we found a register to use already, or if this is an optional
5746 reload, we are done. */
5747 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5751 /* No longer needed for correct operation. Might or might
5752 not give better code on the average. Want to experiment? */
5754 /* See if there is a later reload that has a class different from our
5755 class that intersects our class or that requires less register
5756 than our reload. If so, we must allocate a register to this
5757 reload now, since that reload might inherit a previous reload
5758 and take the only available register in our class. Don't do this
5759 for optional reloads since they will force all previous reloads
5760 to be allocated. Also don't do this for reloads that have been
5763 for (i = j + 1; i < n_reloads; i++)
5765 int s = reload_order[i];
5767 if ((rld[s].in == 0 && rld[s].out == 0
5768 && ! rld[s].secondary_p)
5772 if ((rld[s].class != rld[r].class
5773 && reg_classes_intersect_p (rld[r].class,
5775 || rld[s].nregs < rld[r].nregs)
5782 allocate_reload_reg (chain, r, j == n_reloads - 1);
5786 /* Now allocate reload registers for anything non-optional that
5787 didn't get one yet. */
5788 for (j = 0; j < n_reloads; j++)
5790 register int r = reload_order[j];
5792 /* Ignore reloads that got marked inoperative. */
5793 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5796 /* Skip reloads that already have a register allocated or are
5798 if (rld[r].reg_rtx != 0 || rld[r].optional)
5801 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5805 /* If that loop got all the way, we have won. */
5812 /* Loop around and try without any inheritance. */
5817 /* First undo everything done by the failed attempt
5818 to allocate with inheritance. */
5819 choose_reload_regs_init (chain, save_reload_reg_rtx);
5821 /* Some sanity tests to verify that the reloads found in the first
5822 pass are identical to the ones we have now. */
5823 if (chain->n_reloads != n_reloads)
5826 for (i = 0; i < n_reloads; i++)
5828 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5830 if (chain->rld[i].when_needed != rld[i].when_needed)
5832 for (j = 0; j < n_spills; j++)
5833 if (spill_regs[j] == chain->rld[i].regno)
5834 if (! set_reload_reg (j, i))
5835 failed_reload (chain->insn, i);
5839 /* If we thought we could inherit a reload, because it seemed that
5840 nothing else wanted the same reload register earlier in the insn,
5841 verify that assumption, now that all reloads have been assigned.
5842 Likewise for reloads where reload_override_in has been set. */
5844 /* If doing expensive optimizations, do one preliminary pass that doesn't
5845 cancel any inheritance, but removes reloads that have been needed only
5846 for reloads that we know can be inherited. */
5847 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5849 for (j = 0; j < n_reloads; j++)
5851 register int r = reload_order[j];
5853 if (reload_inherited[r] && rld[r].reg_rtx)
5854 check_reg = rld[r].reg_rtx;
5855 else if (reload_override_in[r]
5856 && (GET_CODE (reload_override_in[r]) == REG
5857 || GET_CODE (reload_override_in[r]) == SUBREG))
5858 check_reg = reload_override_in[r];
5861 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5862 rld[r].opnum, rld[r].when_needed, rld[r].in,
5863 (reload_inherited[r]
5864 ? rld[r].out : const0_rtx),
5869 reload_inherited[r] = 0;
5870 reload_override_in[r] = 0;
5872 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5873 reload_override_in, then we do not need its related
5874 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5875 likewise for other reload types.
5876 We handle this by removing a reload when its only replacement
5877 is mentioned in reload_in of the reload we are going to inherit.
5878 A special case are auto_inc expressions; even if the input is
5879 inherited, we still need the address for the output. We can
5880 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5881 If we suceeded removing some reload and we are doing a preliminary
5882 pass just to remove such reloads, make another pass, since the
5883 removal of one reload might allow us to inherit another one. */
5885 && rld[r].out != rld[r].in
5886 && remove_address_replacements (rld[r].in) && pass)
5891 /* Now that reload_override_in is known valid,
5892 actually override reload_in. */
5893 for (j = 0; j < n_reloads; j++)
5894 if (reload_override_in[j])
5895 rld[j].in = reload_override_in[j];
5897 /* If this reload won't be done because it has been cancelled or is
5898 optional and not inherited, clear reload_reg_rtx so other
5899 routines (such as subst_reloads) don't get confused. */
5900 for (j = 0; j < n_reloads; j++)
5901 if (rld[j].reg_rtx != 0
5902 && ((rld[j].optional && ! reload_inherited[j])
5903 || (rld[j].in == 0 && rld[j].out == 0
5904 && ! rld[j].secondary_p)))
5906 int regno = true_regnum (rld[j].reg_rtx);
5908 if (spill_reg_order[regno] >= 0)
5909 clear_reload_reg_in_use (regno, rld[j].opnum,
5910 rld[j].when_needed, rld[j].mode);
5912 reload_spill_index[j] = -1;
5915 /* Record which pseudos and which spill regs have output reloads. */
5916 for (j = 0; j < n_reloads; j++)
5918 register int r = reload_order[j];
5920 i = reload_spill_index[r];
5922 /* I is nonneg if this reload uses a register.
5923 If rld[r].reg_rtx is 0, this is an optional reload
5924 that we opted to ignore. */
5925 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5926 && rld[r].reg_rtx != 0)
5928 register int nregno = REGNO (rld[r].out_reg);
5931 if (nregno < FIRST_PSEUDO_REGISTER)
5932 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5935 reg_has_output_reload[nregno + nr] = 1;
5939 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5941 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5944 if (rld[r].when_needed != RELOAD_OTHER
5945 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5946 && rld[r].when_needed != RELOAD_FOR_INSN)
5952 /* Deallocate the reload register for reload R. This is called from
5953 remove_address_replacements. */
5956 deallocate_reload_reg (r)
5961 if (! rld[r].reg_rtx)
5963 regno = true_regnum (rld[r].reg_rtx);
5965 if (spill_reg_order[regno] >= 0)
5966 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5968 reload_spill_index[r] = -1;
5971 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5972 reloads of the same item for fear that we might not have enough reload
5973 registers. However, normally they will get the same reload register
5974 and hence actually need not be loaded twice.
5976 Here we check for the most common case of this phenomenon: when we have
5977 a number of reloads for the same object, each of which were allocated
5978 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5979 reload, and is not modified in the insn itself. If we find such,
5980 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5981 This will not increase the number of spill registers needed and will
5982 prevent redundant code. */
5985 merge_assigned_reloads (insn)
5990 /* Scan all the reloads looking for ones that only load values and
5991 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5992 assigned and not modified by INSN. */
5994 for (i = 0; i < n_reloads; i++)
5996 int conflicting_input = 0;
5997 int max_input_address_opnum = -1;
5998 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6000 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6001 || rld[i].out != 0 || rld[i].reg_rtx == 0
6002 || reg_set_p (rld[i].reg_rtx, insn))
6005 /* Look at all other reloads. Ensure that the only use of this
6006 reload_reg_rtx is in a reload that just loads the same value
6007 as we do. Note that any secondary reloads must be of the identical
6008 class since the values, modes, and result registers are the
6009 same, so we need not do anything with any secondary reloads. */
6011 for (j = 0; j < n_reloads; j++)
6013 if (i == j || rld[j].reg_rtx == 0
6014 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6018 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6019 && rld[j].opnum > max_input_address_opnum)
6020 max_input_address_opnum = rld[j].opnum;
6022 /* If the reload regs aren't exactly the same (e.g, different modes)
6023 or if the values are different, we can't merge this reload.
6024 But if it is an input reload, we might still merge
6025 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6027 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6028 || rld[j].out != 0 || rld[j].in == 0
6029 || ! rtx_equal_p (rld[i].in, rld[j].in))
6031 if (rld[j].when_needed != RELOAD_FOR_INPUT
6032 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6033 || rld[i].opnum > rld[j].opnum)
6034 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6036 conflicting_input = 1;
6037 if (min_conflicting_input_opnum > rld[j].opnum)
6038 min_conflicting_input_opnum = rld[j].opnum;
6042 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6043 we, in fact, found any matching reloads. */
6046 && max_input_address_opnum <= min_conflicting_input_opnum)
6048 for (j = 0; j < n_reloads; j++)
6049 if (i != j && rld[j].reg_rtx != 0
6050 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6051 && (! conflicting_input
6052 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6053 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6055 rld[i].when_needed = RELOAD_OTHER;
6057 reload_spill_index[j] = -1;
6058 transfer_replacements (i, j);
6061 /* If this is now RELOAD_OTHER, look for any reloads that load
6062 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6063 if they were for inputs, RELOAD_OTHER for outputs. Note that
6064 this test is equivalent to looking for reloads for this operand
6067 if (rld[i].when_needed == RELOAD_OTHER)
6068 for (j = 0; j < n_reloads; j++)
6070 && rld[i].when_needed != RELOAD_OTHER
6071 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6074 = ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
6075 || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6076 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6081 /* These arrays are filled by emit_reload_insns and its subroutines. */
6082 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6083 static rtx other_input_address_reload_insns = 0;
6084 static rtx other_input_reload_insns = 0;
6085 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6086 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6087 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6088 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6089 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6090 static rtx operand_reload_insns = 0;
6091 static rtx other_operand_reload_insns = 0;
6092 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6094 /* Values to be put in spill_reg_store are put here first. */
6095 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6096 static HARD_REG_SET reg_reloaded_died;
6098 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6099 has the number J. OLD contains the value to be used as input. */
6102 emit_input_reload_insns (chain, rl, old, j)
6103 struct insn_chain *chain;
6108 rtx insn = chain->insn;
6109 register rtx reloadreg = rl->reg_rtx;
6110 rtx oldequiv_reg = 0;
6113 enum machine_mode mode;
6116 /* Determine the mode to reload in.
6117 This is very tricky because we have three to choose from.
6118 There is the mode the insn operand wants (rl->inmode).
6119 There is the mode of the reload register RELOADREG.
6120 There is the intrinsic mode of the operand, which we could find
6121 by stripping some SUBREGs.
6122 It turns out that RELOADREG's mode is irrelevant:
6123 we can change that arbitrarily.
6125 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6126 then the reload reg may not support QImode moves, so use SImode.
6127 If foo is in memory due to spilling a pseudo reg, this is safe,
6128 because the QImode value is in the least significant part of a
6129 slot big enough for a SImode. If foo is some other sort of
6130 memory reference, then it is impossible to reload this case,
6131 so previous passes had better make sure this never happens.
6133 Then consider a one-word union which has SImode and one of its
6134 members is a float, being fetched as (SUBREG:SF union:SI).
6135 We must fetch that as SFmode because we could be loading into
6136 a float-only register. In this case OLD's mode is correct.
6138 Consider an immediate integer: it has VOIDmode. Here we need
6139 to get a mode from something else.
6141 In some cases, there is a fourth mode, the operand's
6142 containing mode. If the insn specifies a containing mode for
6143 this operand, it overrides all others.
6145 I am not sure whether the algorithm here is always right,
6146 but it does the right things in those cases. */
6148 mode = GET_MODE (old);
6149 if (mode == VOIDmode)
6152 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6153 /* If we need a secondary register for this operation, see if
6154 the value is already in a register in that class. Don't
6155 do this if the secondary register will be used as a scratch
6158 if (rl->secondary_in_reload >= 0
6159 && rl->secondary_in_icode == CODE_FOR_nothing
6162 = find_equiv_reg (old, insn,
6163 rld[rl->secondary_in_reload].class,
6164 -1, NULL_PTR, 0, mode);
6167 /* If reloading from memory, see if there is a register
6168 that already holds the same value. If so, reload from there.
6169 We can pass 0 as the reload_reg_p argument because
6170 any other reload has either already been emitted,
6171 in which case find_equiv_reg will see the reload-insn,
6172 or has yet to be emitted, in which case it doesn't matter
6173 because we will use this equiv reg right away. */
6175 if (oldequiv == 0 && optimize
6176 && (GET_CODE (old) == MEM
6177 || (GET_CODE (old) == REG
6178 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6179 && reg_renumber[REGNO (old)] < 0)))
6180 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6181 -1, NULL_PTR, 0, mode);
6185 unsigned int regno = true_regnum (oldequiv);
6187 /* Don't use OLDEQUIV if any other reload changes it at an
6188 earlier stage of this insn or at this stage. */
6189 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6190 rl->in, const0_rtx, j, 0))
6193 /* If it is no cheaper to copy from OLDEQUIV into the
6194 reload register than it would be to move from memory,
6195 don't use it. Likewise, if we need a secondary register
6199 && ((REGNO_REG_CLASS (regno) != rl->class
6200 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6202 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6203 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6204 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6208 #ifdef SECONDARY_MEMORY_NEEDED
6209 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6217 /* delete_output_reload is only invoked properly if old contains
6218 the original pseudo register. Since this is replaced with a
6219 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6220 find the pseudo in RELOAD_IN_REG. */
6222 && reload_override_in[j]
6223 && GET_CODE (rl->in_reg) == REG)
6230 else if (GET_CODE (oldequiv) == REG)
6231 oldequiv_reg = oldequiv;
6232 else if (GET_CODE (oldequiv) == SUBREG)
6233 oldequiv_reg = SUBREG_REG (oldequiv);
6235 /* If we are reloading from a register that was recently stored in
6236 with an output-reload, see if we can prove there was
6237 actually no need to store the old value in it. */
6239 if (optimize && GET_CODE (oldequiv) == REG
6240 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6241 && spill_reg_store[REGNO (oldequiv)]
6242 && GET_CODE (old) == REG
6243 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6244 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6246 delete_output_reload (insn, j, REGNO (oldequiv));
6248 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6249 then load RELOADREG from OLDEQUIV. Note that we cannot use
6250 gen_lowpart_common since it can do the wrong thing when
6251 RELOADREG has a multi-word mode. Note that RELOADREG
6252 must always be a REG here. */
6254 if (GET_MODE (reloadreg) != mode)
6255 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6256 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6257 oldequiv = SUBREG_REG (oldequiv);
6258 if (GET_MODE (oldequiv) != VOIDmode
6259 && mode != GET_MODE (oldequiv))
6260 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6262 /* Switch to the right place to emit the reload insns. */
6263 switch (rl->when_needed)
6266 where = &other_input_reload_insns;
6268 case RELOAD_FOR_INPUT:
6269 where = &input_reload_insns[rl->opnum];
6271 case RELOAD_FOR_INPUT_ADDRESS:
6272 where = &input_address_reload_insns[rl->opnum];
6274 case RELOAD_FOR_INPADDR_ADDRESS:
6275 where = &inpaddr_address_reload_insns[rl->opnum];
6277 case RELOAD_FOR_OUTPUT_ADDRESS:
6278 where = &output_address_reload_insns[rl->opnum];
6280 case RELOAD_FOR_OUTADDR_ADDRESS:
6281 where = &outaddr_address_reload_insns[rl->opnum];
6283 case RELOAD_FOR_OPERAND_ADDRESS:
6284 where = &operand_reload_insns;
6286 case RELOAD_FOR_OPADDR_ADDR:
6287 where = &other_operand_reload_insns;
6289 case RELOAD_FOR_OTHER_ADDRESS:
6290 where = &other_input_address_reload_insns;
6296 push_to_sequence (*where);
6298 /* Auto-increment addresses must be reloaded in a special way. */
6299 if (rl->out && ! rl->out_reg)
6301 /* We are not going to bother supporting the case where a
6302 incremented register can't be copied directly from
6303 OLDEQUIV since this seems highly unlikely. */
6304 if (rl->secondary_in_reload >= 0)
6307 if (reload_inherited[j])
6308 oldequiv = reloadreg;
6310 old = XEXP (rl->in_reg, 0);
6312 if (optimize && GET_CODE (oldequiv) == REG
6313 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6314 && spill_reg_store[REGNO (oldequiv)]
6315 && GET_CODE (old) == REG
6316 && (dead_or_set_p (insn,
6317 spill_reg_stored_to[REGNO (oldequiv)])
6318 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6320 delete_output_reload (insn, j, REGNO (oldequiv));
6322 /* Prevent normal processing of this reload. */
6324 /* Output a special code sequence for this case. */
6325 new_spill_reg_store[REGNO (reloadreg)]
6326 = inc_for_reload (reloadreg, oldequiv, rl->out,
6330 /* If we are reloading a pseudo-register that was set by the previous
6331 insn, see if we can get rid of that pseudo-register entirely
6332 by redirecting the previous insn into our reload register. */
6334 else if (optimize && GET_CODE (old) == REG
6335 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6336 && dead_or_set_p (insn, old)
6337 /* This is unsafe if some other reload
6338 uses the same reg first. */
6339 && ! conflicts_with_override (reloadreg)
6340 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6341 rl->when_needed, old, rl->out, j, 0))
6343 rtx temp = PREV_INSN (insn);
6344 while (temp && GET_CODE (temp) == NOTE)
6345 temp = PREV_INSN (temp);
6347 && GET_CODE (temp) == INSN
6348 && GET_CODE (PATTERN (temp)) == SET
6349 && SET_DEST (PATTERN (temp)) == old
6350 /* Make sure we can access insn_operand_constraint. */
6351 && asm_noperands (PATTERN (temp)) < 0
6352 /* This is unsafe if prev insn rejects our reload reg. */
6353 && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint,
6355 /* This is unsafe if operand occurs more than once in current
6356 insn. Perhaps some occurrences aren't reloaded. */
6357 && count_occurrences (PATTERN (insn), old, 0) == 1
6358 /* Don't risk splitting a matching pair of operands. */
6359 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6361 /* Store into the reload register instead of the pseudo. */
6362 SET_DEST (PATTERN (temp)) = reloadreg;
6364 /* If the previous insn is an output reload, the source is
6365 a reload register, and its spill_reg_store entry will
6366 contain the previous destination. This is now
6368 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6369 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6371 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6372 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6375 /* If these are the only uses of the pseudo reg,
6376 pretend for GDB it lives in the reload reg we used. */
6377 if (REG_N_DEATHS (REGNO (old)) == 1
6378 && REG_N_SETS (REGNO (old)) == 1)
6380 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6381 alter_reg (REGNO (old), -1);
6387 /* We can't do that, so output an insn to load RELOADREG. */
6389 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6390 /* If we have a secondary reload, pick up the secondary register
6391 and icode, if any. If OLDEQUIV and OLD are different or
6392 if this is an in-out reload, recompute whether or not we
6393 still need a secondary register and what the icode should
6394 be. If we still need a secondary register and the class or
6395 icode is different, go back to reloading from OLD if using
6396 OLDEQUIV means that we got the wrong type of register. We
6397 cannot have different class or icode due to an in-out reload
6398 because we don't make such reloads when both the input and
6399 output need secondary reload registers. */
6401 if (! special && rl->secondary_in_reload >= 0)
6403 rtx second_reload_reg = 0;
6404 int secondary_reload = rl->secondary_in_reload;
6405 rtx real_oldequiv = oldequiv;
6408 enum insn_code icode;
6410 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6411 and similarly for OLD.
6412 See comments in get_secondary_reload in reload.c. */
6413 /* If it is a pseudo that cannot be replaced with its
6414 equivalent MEM, we must fall back to reload_in, which
6415 will have all the necessary substitutions registered.
6416 Likewise for a pseudo that can't be replaced with its
6417 equivalent constant.
6419 Take extra care for subregs of such pseudos. Note that
6420 we cannot use reg_equiv_mem in this case because it is
6421 not in the right mode. */
6424 if (GET_CODE (tmp) == SUBREG)
6425 tmp = SUBREG_REG (tmp);
6426 if (GET_CODE (tmp) == REG
6427 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6428 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6429 || reg_equiv_constant[REGNO (tmp)] != 0))
6431 if (! reg_equiv_mem[REGNO (tmp)]
6432 || num_not_at_initial_offset
6433 || GET_CODE (oldequiv) == SUBREG)
6434 real_oldequiv = rl->in;
6436 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6440 if (GET_CODE (tmp) == SUBREG)
6441 tmp = SUBREG_REG (tmp);
6442 if (GET_CODE (tmp) == REG
6443 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6444 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6445 || reg_equiv_constant[REGNO (tmp)] != 0))
6447 if (! reg_equiv_mem[REGNO (tmp)]
6448 || num_not_at_initial_offset
6449 || GET_CODE (old) == SUBREG)
6452 real_old = reg_equiv_mem[REGNO (tmp)];
6455 second_reload_reg = rld[secondary_reload].reg_rtx;
6456 icode = rl->secondary_in_icode;
6458 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6459 || (rl->in != 0 && rl->out != 0))
6461 enum reg_class new_class
6462 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6463 mode, real_oldequiv);
6465 if (new_class == NO_REGS)
6466 second_reload_reg = 0;
6469 enum insn_code new_icode;
6470 enum machine_mode new_mode;
6472 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6473 REGNO (second_reload_reg)))
6474 oldequiv = old, real_oldequiv = real_old;
6477 new_icode = reload_in_optab[(int) mode];
6478 if (new_icode != CODE_FOR_nothing
6479 && ((insn_data[(int) new_icode].operand[0].predicate
6480 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6482 || (insn_data[(int) new_icode].operand[1].predicate
6483 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6484 (real_oldequiv, mode)))))
6485 new_icode = CODE_FOR_nothing;
6487 if (new_icode == CODE_FOR_nothing)
6490 new_mode = insn_data[(int) new_icode].operand[2].mode;
6492 if (GET_MODE (second_reload_reg) != new_mode)
6494 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6496 oldequiv = old, real_oldequiv = real_old;
6499 = gen_rtx_REG (new_mode,
6500 REGNO (second_reload_reg));
6506 /* If we still need a secondary reload register, check
6507 to see if it is being used as a scratch or intermediate
6508 register and generate code appropriately. If we need
6509 a scratch register, use REAL_OLDEQUIV since the form of
6510 the insn may depend on the actual address if it is
6513 if (second_reload_reg)
6515 if (icode != CODE_FOR_nothing)
6517 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6518 second_reload_reg));
6523 /* See if we need a scratch register to load the
6524 intermediate register (a tertiary reload). */
6525 enum insn_code tertiary_icode
6526 = rld[secondary_reload].secondary_in_icode;
6528 if (tertiary_icode != CODE_FOR_nothing)
6530 rtx third_reload_reg
6531 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6533 emit_insn ((GEN_FCN (tertiary_icode)
6534 (second_reload_reg, real_oldequiv,
6535 third_reload_reg)));
6538 gen_reload (second_reload_reg, real_oldequiv,
6542 oldequiv = second_reload_reg;
6548 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6550 rtx real_oldequiv = oldequiv;
6552 if ((GET_CODE (oldequiv) == REG
6553 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6554 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6555 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6556 || (GET_CODE (oldequiv) == SUBREG
6557 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6558 && (REGNO (SUBREG_REG (oldequiv))
6559 >= FIRST_PSEUDO_REGISTER)
6560 && ((reg_equiv_memory_loc
6561 [REGNO (SUBREG_REG (oldequiv))] != 0)
6562 || (reg_equiv_constant
6563 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6564 || (CONSTANT_P (oldequiv)
6565 && PREFERRED_RELOAD_CLASS (oldequiv,
6566 REGNO_REG_CLASS (REGNO (reloadreg))) == NO_REGS))
6567 real_oldequiv = rl->in;
6568 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6572 /* End this sequence. */
6573 *where = get_insns ();
6576 /* Update reload_override_in so that delete_address_reloads_1
6577 can see the actual register usage. */
6579 reload_override_in[j] = oldequiv;
6582 /* Generate insns to for the output reload RL, which is for the insn described
6583 by CHAIN and has the number J. */
6585 emit_output_reload_insns (chain, rl, j)
6586 struct insn_chain *chain;
6590 rtx reloadreg = rl->reg_rtx;
6591 rtx insn = chain->insn;
6594 enum machine_mode mode = GET_MODE (old);
6597 if (rl->when_needed == RELOAD_OTHER)
6600 push_to_sequence (output_reload_insns[rl->opnum]);
6602 /* Determine the mode to reload in.
6603 See comments above (for input reloading). */
6605 if (mode == VOIDmode)
6607 /* VOIDmode should never happen for an output. */
6608 if (asm_noperands (PATTERN (insn)) < 0)
6609 /* It's the compiler's fault. */
6610 fatal_insn ("VOIDmode on an output", insn);
6611 error_for_asm (insn, "output operand is constant in `asm'");
6612 /* Prevent crash--use something we know is valid. */
6614 old = gen_rtx_REG (mode, REGNO (reloadreg));
6617 if (GET_MODE (reloadreg) != mode)
6618 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6620 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6622 /* If we need two reload regs, set RELOADREG to the intermediate
6623 one, since it will be stored into OLD. We might need a secondary
6624 register only for an input reload, so check again here. */
6626 if (rl->secondary_out_reload >= 0)
6630 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6631 && reg_equiv_mem[REGNO (old)] != 0)
6632 real_old = reg_equiv_mem[REGNO (old)];
6634 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6638 rtx second_reloadreg = reloadreg;
6639 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6641 /* See if RELOADREG is to be used as a scratch register
6642 or as an intermediate register. */
6643 if (rl->secondary_out_icode != CODE_FOR_nothing)
6645 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6646 (real_old, second_reloadreg, reloadreg)));
6651 /* See if we need both a scratch and intermediate reload
6654 int secondary_reload = rl->secondary_out_reload;
6655 enum insn_code tertiary_icode
6656 = rld[secondary_reload].secondary_out_icode;
6658 if (GET_MODE (reloadreg) != mode)
6659 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6661 if (tertiary_icode != CODE_FOR_nothing)
6664 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6667 /* Copy primary reload reg to secondary reload reg.
6668 (Note that these have been swapped above, then
6669 secondary reload reg to OLD using our insn.) */
6671 /* If REAL_OLD is a paradoxical SUBREG, remove it
6672 and try to put the opposite SUBREG on
6674 if (GET_CODE (real_old) == SUBREG
6675 && (GET_MODE_SIZE (GET_MODE (real_old))
6676 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6677 && 0 != (tem = gen_lowpart_common
6678 (GET_MODE (SUBREG_REG (real_old)),
6680 real_old = SUBREG_REG (real_old), reloadreg = tem;
6682 gen_reload (reloadreg, second_reloadreg,
6683 rl->opnum, rl->when_needed);
6684 emit_insn ((GEN_FCN (tertiary_icode)
6685 (real_old, reloadreg, third_reloadreg)));
6690 /* Copy between the reload regs here and then to
6693 gen_reload (reloadreg, second_reloadreg,
6694 rl->opnum, rl->when_needed);
6700 /* Output the last reload insn. */
6705 /* Don't output the last reload if OLD is not the dest of
6706 INSN and is in the src and is clobbered by INSN. */
6707 if (! flag_expensive_optimizations
6708 || GET_CODE (old) != REG
6709 || !(set = single_set (insn))
6710 || rtx_equal_p (old, SET_DEST (set))
6711 || !reg_mentioned_p (old, SET_SRC (set))
6712 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6713 gen_reload (old, reloadreg, rl->opnum,
6717 /* Look at all insns we emitted, just to be safe. */
6718 for (p = get_insns (); p; p = NEXT_INSN (p))
6721 rtx pat = PATTERN (p);
6723 /* If this output reload doesn't come from a spill reg,
6724 clear any memory of reloaded copies of the pseudo reg.
6725 If this output reload comes from a spill reg,
6726 reg_has_output_reload will make this do nothing. */
6727 note_stores (pat, forget_old_reloads_1, NULL);
6729 if (reg_mentioned_p (rl->reg_rtx, pat))
6731 rtx set = single_set (insn);
6732 if (reload_spill_index[j] < 0
6734 && SET_SRC (set) == rl->reg_rtx)
6736 int src = REGNO (SET_SRC (set));
6738 reload_spill_index[j] = src;
6739 SET_HARD_REG_BIT (reg_is_output_reload, src);
6740 if (find_regno_note (insn, REG_DEAD, src))
6741 SET_HARD_REG_BIT (reg_reloaded_died, src);
6743 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6745 int s = rl->secondary_out_reload;
6746 set = single_set (p);
6747 /* If this reload copies only to the secondary reload
6748 register, the secondary reload does the actual
6750 if (s >= 0 && set == NULL_RTX)
6751 /* We can't tell what function the secondary reload
6752 has and where the actual store to the pseudo is
6753 made; leave new_spill_reg_store alone. */
6756 && SET_SRC (set) == rl->reg_rtx
6757 && SET_DEST (set) == rld[s].reg_rtx)
6759 /* Usually the next instruction will be the
6760 secondary reload insn; if we can confirm
6761 that it is, setting new_spill_reg_store to
6762 that insn will allow an extra optimization. */
6763 rtx s_reg = rld[s].reg_rtx;
6764 rtx next = NEXT_INSN (p);
6765 rld[s].out = rl->out;
6766 rld[s].out_reg = rl->out_reg;
6767 set = single_set (next);
6768 if (set && SET_SRC (set) == s_reg
6769 && ! new_spill_reg_store[REGNO (s_reg)])
6771 SET_HARD_REG_BIT (reg_is_output_reload,
6773 new_spill_reg_store[REGNO (s_reg)] = next;
6777 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6782 if (rl->when_needed == RELOAD_OTHER)
6784 emit_insns (other_output_reload_insns[rl->opnum]);
6785 other_output_reload_insns[rl->opnum] = get_insns ();
6788 output_reload_insns[rl->opnum] = get_insns ();
6793 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6794 and has the number J. */
6796 do_input_reload (chain, rl, j)
6797 struct insn_chain *chain;
6801 int expect_occurrences = 1;
6802 rtx insn = chain->insn;
6803 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6804 ? rl->in_reg : rl->in);
6807 /* AUTO_INC reloads need to be handled even if inherited. We got an
6808 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6809 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6810 && ! rtx_equal_p (rl->reg_rtx, old)
6811 && rl->reg_rtx != 0)
6812 emit_input_reload_insns (chain, rld + j, old, j);
6814 /* When inheriting a wider reload, we have a MEM in rl->in,
6815 e.g. inheriting a SImode output reload for
6816 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6817 if (optimize && reload_inherited[j] && rl->in
6818 && GET_CODE (rl->in) == MEM
6819 && GET_CODE (rl->in_reg) == MEM
6820 && reload_spill_index[j] >= 0
6821 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6824 = count_occurrences (PATTERN (insn), rl->in, 0) == 1 ? 0 : -1;
6825 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6828 /* If we are reloading a register that was recently stored in with an
6829 output-reload, see if we can prove there was
6830 actually no need to store the old value in it. */
6833 && (reload_inherited[j] || reload_override_in[j])
6835 && GET_CODE (rl->reg_rtx) == REG
6836 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6838 /* There doesn't seem to be any reason to restrict this to pseudos
6839 and doing so loses in the case where we are copying from a
6840 register of the wrong class. */
6841 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6842 >= FIRST_PSEUDO_REGISTER)
6844 /* The insn might have already some references to stackslots
6845 replaced by MEMs, while reload_out_reg still names the
6847 && (dead_or_set_p (insn,
6848 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6849 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6851 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6854 /* Do output reloading for reload RL, which is for the insn described by
6855 CHAIN and has the number J.
6856 ??? At some point we need to support handling output reloads of
6857 JUMP_INSNs or insns that set cc0. */
6859 do_output_reload (chain, rl, j)
6860 struct insn_chain *chain;
6865 rtx insn = chain->insn;
6866 /* If this is an output reload that stores something that is
6867 not loaded in this same reload, see if we can eliminate a previous
6869 rtx pseudo = rl->out_reg;
6872 && GET_CODE (pseudo) == REG
6873 && ! rtx_equal_p (rl->in_reg, pseudo)
6874 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6875 && reg_last_reload_reg[REGNO (pseudo)])
6877 int pseudo_no = REGNO (pseudo);
6878 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6880 /* We don't need to test full validity of last_regno for
6881 inherit here; we only want to know if the store actually
6882 matches the pseudo. */
6883 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6884 && reg_reloaded_contents[last_regno] == pseudo_no
6885 && spill_reg_store[last_regno]
6886 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6887 delete_output_reload (insn, j, last_regno);
6892 || rl->reg_rtx == old
6893 || rl->reg_rtx == 0)
6896 /* An output operand that dies right away does need a reload,
6897 but need not be copied from it. Show the new location in the
6899 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6900 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6902 XEXP (note, 0) = rl->reg_rtx;
6905 /* Likewise for a SUBREG of an operand that dies. */
6906 else if (GET_CODE (old) == SUBREG
6907 && GET_CODE (SUBREG_REG (old)) == REG
6908 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6911 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6915 else if (GET_CODE (old) == SCRATCH)
6916 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6917 but we don't want to make an output reload. */
6920 /* If is a JUMP_INSN, we can't support output reloads yet. */
6921 if (GET_CODE (insn) == JUMP_INSN)
6924 emit_output_reload_insns (chain, rld + j, j);
6927 /* Output insns to reload values in and out of the chosen reload regs. */
6930 emit_reload_insns (chain)
6931 struct insn_chain *chain;
6933 rtx insn = chain->insn;
6936 rtx following_insn = NEXT_INSN (insn);
6937 rtx before_insn = PREV_INSN (insn);
6939 CLEAR_HARD_REG_SET (reg_reloaded_died);
6941 for (j = 0; j < reload_n_operands; j++)
6942 input_reload_insns[j] = input_address_reload_insns[j]
6943 = inpaddr_address_reload_insns[j]
6944 = output_reload_insns[j] = output_address_reload_insns[j]
6945 = outaddr_address_reload_insns[j]
6946 = other_output_reload_insns[j] = 0;
6947 other_input_address_reload_insns = 0;
6948 other_input_reload_insns = 0;
6949 operand_reload_insns = 0;
6950 other_operand_reload_insns = 0;
6952 /* Dump reloads into the dump file. */
6955 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6956 debug_reload_to_stream (rtl_dump_file);
6959 /* Now output the instructions to copy the data into and out of the
6960 reload registers. Do these in the order that the reloads were reported,
6961 since reloads of base and index registers precede reloads of operands
6962 and the operands may need the base and index registers reloaded. */
6964 for (j = 0; j < n_reloads; j++)
6967 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6968 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6970 do_input_reload (chain, rld + j, j);
6971 do_output_reload (chain, rld + j, j);
6974 /* Now write all the insns we made for reloads in the order expected by
6975 the allocation functions. Prior to the insn being reloaded, we write
6976 the following reloads:
6978 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6980 RELOAD_OTHER reloads.
6982 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6983 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6984 RELOAD_FOR_INPUT reload for the operand.
6986 RELOAD_FOR_OPADDR_ADDRS reloads.
6988 RELOAD_FOR_OPERAND_ADDRESS reloads.
6990 After the insn being reloaded, we write the following:
6992 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6993 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6994 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6995 reloads for the operand. The RELOAD_OTHER output reloads are
6996 output in descending order by reload number. */
6998 emit_insns_before (other_input_address_reload_insns, insn);
6999 emit_insns_before (other_input_reload_insns, insn);
7001 for (j = 0; j < reload_n_operands; j++)
7003 emit_insns_before (inpaddr_address_reload_insns[j], insn);
7004 emit_insns_before (input_address_reload_insns[j], insn);
7005 emit_insns_before (input_reload_insns[j], insn);
7008 emit_insns_before (other_operand_reload_insns, insn);
7009 emit_insns_before (operand_reload_insns, insn);
7011 for (j = 0; j < reload_n_operands; j++)
7013 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
7014 emit_insns_before (output_address_reload_insns[j], following_insn);
7015 emit_insns_before (output_reload_insns[j], following_insn);
7016 emit_insns_before (other_output_reload_insns[j], following_insn);
7019 /* Keep basic block info up to date. */
7022 if (BLOCK_HEAD (chain->block) == insn)
7023 BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
7024 if (BLOCK_END (chain->block) == insn)
7025 BLOCK_END (chain->block) = PREV_INSN (following_insn);
7028 /* For all the spill regs newly reloaded in this instruction,
7029 record what they were reloaded from, so subsequent instructions
7030 can inherit the reloads.
7032 Update spill_reg_store for the reloads of this insn.
7033 Copy the elements that were updated in the loop above. */
7035 for (j = 0; j < n_reloads; j++)
7037 register int r = reload_order[j];
7038 register int i = reload_spill_index[r];
7040 /* If this is a non-inherited input reload from a pseudo, we must
7041 clear any memory of a previous store to the same pseudo. Only do
7042 something if there will not be an output reload for the pseudo
7044 if (rld[r].in_reg != 0
7045 && ! (reload_inherited[r] || reload_override_in[r]))
7047 rtx reg = rld[r].in_reg;
7049 if (GET_CODE (reg) == SUBREG)
7050 reg = SUBREG_REG (reg);
7052 if (GET_CODE (reg) == REG
7053 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7054 && ! reg_has_output_reload[REGNO (reg)])
7056 int nregno = REGNO (reg);
7058 if (reg_last_reload_reg[nregno])
7060 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7062 if (reg_reloaded_contents[last_regno] == nregno)
7063 spill_reg_store[last_regno] = 0;
7068 /* I is nonneg if this reload used a register.
7069 If rld[r].reg_rtx is 0, this is an optional reload
7070 that we opted to ignore. */
7072 if (i >= 0 && rld[r].reg_rtx != 0)
7074 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7076 int part_reaches_end = 0;
7077 int all_reaches_end = 1;
7079 /* For a multi register reload, we need to check if all or part
7080 of the value lives to the end. */
7081 for (k = 0; k < nr; k++)
7083 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7084 rld[r].when_needed))
7085 part_reaches_end = 1;
7087 all_reaches_end = 0;
7090 /* Ignore reloads that don't reach the end of the insn in
7092 if (all_reaches_end)
7094 /* First, clear out memory of what used to be in this spill reg.
7095 If consecutive registers are used, clear them all. */
7097 for (k = 0; k < nr; k++)
7098 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7100 /* Maybe the spill reg contains a copy of reload_out. */
7102 && (GET_CODE (rld[r].out) == REG
7106 || GET_CODE (rld[r].out_reg) == REG))
7108 rtx out = (GET_CODE (rld[r].out) == REG
7112 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7113 register int nregno = REGNO (out);
7114 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7115 : HARD_REGNO_NREGS (nregno,
7116 GET_MODE (rld[r].reg_rtx)));
7118 spill_reg_store[i] = new_spill_reg_store[i];
7119 spill_reg_stored_to[i] = out;
7120 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7122 /* If NREGNO is a hard register, it may occupy more than
7123 one register. If it does, say what is in the
7124 rest of the registers assuming that both registers
7125 agree on how many words the object takes. If not,
7126 invalidate the subsequent registers. */
7128 if (nregno < FIRST_PSEUDO_REGISTER)
7129 for (k = 1; k < nnr; k++)
7130 reg_last_reload_reg[nregno + k]
7132 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7133 REGNO (rld[r].reg_rtx) + k)
7136 /* Now do the inverse operation. */
7137 for (k = 0; k < nr; k++)
7139 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7140 reg_reloaded_contents[i + k]
7141 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7144 reg_reloaded_insn[i + k] = insn;
7145 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7149 /* Maybe the spill reg contains a copy of reload_in. Only do
7150 something if there will not be an output reload for
7151 the register being reloaded. */
7152 else if (rld[r].out_reg == 0
7154 && ((GET_CODE (rld[r].in) == REG
7155 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7156 && ! reg_has_output_reload[REGNO (rld[r].in)])
7157 || (GET_CODE (rld[r].in_reg) == REG
7158 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7159 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7161 register int nregno;
7164 if (GET_CODE (rld[r].in) == REG
7165 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7166 nregno = REGNO (rld[r].in);
7167 else if (GET_CODE (rld[r].in_reg) == REG)
7168 nregno = REGNO (rld[r].in_reg);
7170 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7172 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7173 : HARD_REGNO_NREGS (nregno,
7174 GET_MODE (rld[r].reg_rtx)));
7176 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7178 if (nregno < FIRST_PSEUDO_REGISTER)
7179 for (k = 1; k < nnr; k++)
7180 reg_last_reload_reg[nregno + k]
7182 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7183 REGNO (rld[r].reg_rtx) + k)
7186 /* Unless we inherited this reload, show we haven't
7187 recently done a store.
7188 Previous stores of inherited auto_inc expressions
7189 also have to be discarded. */
7190 if (! reload_inherited[r]
7191 || (rld[r].out && ! rld[r].out_reg))
7192 spill_reg_store[i] = 0;
7194 for (k = 0; k < nr; k++)
7196 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7197 reg_reloaded_contents[i + k]
7198 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7201 reg_reloaded_insn[i + k] = insn;
7202 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7207 /* However, if part of the reload reaches the end, then we must
7208 invalidate the old info for the part that survives to the end. */
7209 else if (part_reaches_end)
7211 for (k = 0; k < nr; k++)
7212 if (reload_reg_reaches_end_p (i + k,
7214 rld[r].when_needed))
7215 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7219 /* The following if-statement was #if 0'd in 1.34 (or before...).
7220 It's reenabled in 1.35 because supposedly nothing else
7221 deals with this problem. */
7223 /* If a register gets output-reloaded from a non-spill register,
7224 that invalidates any previous reloaded copy of it.
7225 But forget_old_reloads_1 won't get to see it, because
7226 it thinks only about the original insn. So invalidate it here. */
7227 if (i < 0 && rld[r].out != 0
7228 && (GET_CODE (rld[r].out) == REG
7229 || (GET_CODE (rld[r].out) == MEM
7230 && GET_CODE (rld[r].out_reg) == REG)))
7232 rtx out = (GET_CODE (rld[r].out) == REG
7233 ? rld[r].out : rld[r].out_reg);
7234 register int nregno = REGNO (out);
7235 if (nregno >= FIRST_PSEUDO_REGISTER)
7237 rtx src_reg, store_insn = NULL_RTX;
7239 reg_last_reload_reg[nregno] = 0;
7241 /* If we can find a hard register that is stored, record
7242 the storing insn so that we may delete this insn with
7243 delete_output_reload. */
7244 src_reg = rld[r].reg_rtx;
7246 /* If this is an optional reload, try to find the source reg
7247 from an input reload. */
7250 rtx set = single_set (insn);
7251 if (set && SET_DEST (set) == rld[r].out)
7255 src_reg = SET_SRC (set);
7257 for (k = 0; k < n_reloads; k++)
7259 if (rld[k].in == src_reg)
7261 src_reg = rld[k].reg_rtx;
7268 store_insn = new_spill_reg_store[REGNO (src_reg)];
7269 if (src_reg && GET_CODE (src_reg) == REG
7270 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7272 int src_regno = REGNO (src_reg);
7273 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7274 /* The place where to find a death note varies with
7275 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7276 necessarily checked exactly in the code that moves
7277 notes, so just check both locations. */
7278 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7280 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7283 spill_reg_store[src_regno + nr] = store_insn;
7284 spill_reg_stored_to[src_regno + nr] = out;
7285 reg_reloaded_contents[src_regno + nr] = nregno;
7286 reg_reloaded_insn[src_regno + nr] = store_insn;
7287 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7288 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7289 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7291 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7293 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7295 reg_last_reload_reg[nregno] = src_reg;
7300 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7302 while (num_regs-- > 0)
7303 reg_last_reload_reg[nregno + num_regs] = 0;
7307 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7310 /* Emit code to perform a reload from IN (which may be a reload register) to
7311 OUT (which may also be a reload register). IN or OUT is from operand
7312 OPNUM with reload type TYPE.
7314 Returns first insn emitted. */
7317 gen_reload (out, in, opnum, type)
7321 enum reload_type type;
7323 rtx last = get_last_insn ();
7326 /* If IN is a paradoxical SUBREG, remove it and try to put the
7327 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7328 if (GET_CODE (in) == SUBREG
7329 && (GET_MODE_SIZE (GET_MODE (in))
7330 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7331 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7332 in = SUBREG_REG (in), out = tem;
7333 else if (GET_CODE (out) == SUBREG
7334 && (GET_MODE_SIZE (GET_MODE (out))
7335 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7336 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7337 out = SUBREG_REG (out), in = tem;
7339 /* How to do this reload can get quite tricky. Normally, we are being
7340 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7341 register that didn't get a hard register. In that case we can just
7342 call emit_move_insn.
7344 We can also be asked to reload a PLUS that adds a register or a MEM to
7345 another register, constant or MEM. This can occur during frame pointer
7346 elimination and while reloading addresses. This case is handled by
7347 trying to emit a single insn to perform the add. If it is not valid,
7348 we use a two insn sequence.
7350 Finally, we could be called to handle an 'o' constraint by putting
7351 an address into a register. In that case, we first try to do this
7352 with a named pattern of "reload_load_address". If no such pattern
7353 exists, we just emit a SET insn and hope for the best (it will normally
7354 be valid on machines that use 'o').
7356 This entire process is made complex because reload will never
7357 process the insns we generate here and so we must ensure that
7358 they will fit their constraints and also by the fact that parts of
7359 IN might be being reloaded separately and replaced with spill registers.
7360 Because of this, we are, in some sense, just guessing the right approach
7361 here. The one listed above seems to work.
7363 ??? At some point, this whole thing needs to be rethought. */
7365 if (GET_CODE (in) == PLUS
7366 && (GET_CODE (XEXP (in, 0)) == REG
7367 || GET_CODE (XEXP (in, 0)) == SUBREG
7368 || GET_CODE (XEXP (in, 0)) == MEM)
7369 && (GET_CODE (XEXP (in, 1)) == REG
7370 || GET_CODE (XEXP (in, 1)) == SUBREG
7371 || CONSTANT_P (XEXP (in, 1))
7372 || GET_CODE (XEXP (in, 1)) == MEM))
7374 /* We need to compute the sum of a register or a MEM and another
7375 register, constant, or MEM, and put it into the reload
7376 register. The best possible way of doing this is if the machine
7377 has a three-operand ADD insn that accepts the required operands.
7379 The simplest approach is to try to generate such an insn and see if it
7380 is recognized and matches its constraints. If so, it can be used.
7382 It might be better not to actually emit the insn unless it is valid,
7383 but we need to pass the insn as an operand to `recog' and
7384 `extract_insn' and it is simpler to emit and then delete the insn if
7385 not valid than to dummy things up. */
7387 rtx op0, op1, tem, insn;
7390 op0 = find_replacement (&XEXP (in, 0));
7391 op1 = find_replacement (&XEXP (in, 1));
7393 /* Since constraint checking is strict, commutativity won't be
7394 checked, so we need to do that here to avoid spurious failure
7395 if the add instruction is two-address and the second operand
7396 of the add is the same as the reload reg, which is frequently
7397 the case. If the insn would be A = B + A, rearrange it so
7398 it will be A = A + B as constrain_operands expects. */
7400 if (GET_CODE (XEXP (in, 1)) == REG
7401 && REGNO (out) == REGNO (XEXP (in, 1)))
7402 tem = op0, op0 = op1, op1 = tem;
7404 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7405 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7407 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7408 code = recog_memoized (insn);
7412 extract_insn (insn);
7413 /* We want constrain operands to treat this insn strictly in
7414 its validity determination, i.e., the way it would after reload
7416 if (constrain_operands (1))
7420 delete_insns_since (last);
7422 /* If that failed, we must use a conservative two-insn sequence.
7424 Use a move to copy one operand into the reload register. Prefer
7425 to reload a constant, MEM or pseudo since the move patterns can
7426 handle an arbitrary operand. If OP1 is not a constant, MEM or
7427 pseudo and OP1 is not a valid operand for an add instruction, then
7430 After reloading one of the operands into the reload register, add
7431 the reload register to the output register.
7433 If there is another way to do this for a specific machine, a
7434 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7437 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7439 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7440 || (GET_CODE (op1) == REG
7441 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7442 || (code != CODE_FOR_nothing
7443 && ! ((*insn_data[code].operand[2].predicate)
7444 (op1, insn_data[code].operand[2].mode))))
7445 tem = op0, op0 = op1, op1 = tem;
7447 gen_reload (out, op0, opnum, type);
7449 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7450 This fixes a problem on the 32K where the stack pointer cannot
7451 be used as an operand of an add insn. */
7453 if (rtx_equal_p (op0, op1))
7456 insn = emit_insn (gen_add2_insn (out, op1));
7458 /* If that failed, copy the address register to the reload register.
7459 Then add the constant to the reload register. */
7461 code = recog_memoized (insn);
7465 extract_insn (insn);
7466 /* We want constrain operands to treat this insn strictly in
7467 its validity determination, i.e., the way it would after reload
7469 if (constrain_operands (1))
7471 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7473 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7478 delete_insns_since (last);
7480 gen_reload (out, op1, opnum, type);
7481 insn = emit_insn (gen_add2_insn (out, op0));
7482 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7485 #ifdef SECONDARY_MEMORY_NEEDED
7486 /* If we need a memory location to do the move, do it that way. */
7487 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7488 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7489 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7490 REGNO_REG_CLASS (REGNO (out)),
7493 /* Get the memory to use and rewrite both registers to its mode. */
7494 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7496 if (GET_MODE (loc) != GET_MODE (out))
7497 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7499 if (GET_MODE (loc) != GET_MODE (in))
7500 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7502 gen_reload (loc, in, opnum, type);
7503 gen_reload (out, loc, opnum, type);
7507 /* If IN is a simple operand, use gen_move_insn. */
7508 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7509 emit_insn (gen_move_insn (out, in));
7511 #ifdef HAVE_reload_load_address
7512 else if (HAVE_reload_load_address)
7513 emit_insn (gen_reload_load_address (out, in));
7516 /* Otherwise, just write (set OUT IN) and hope for the best. */
7518 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7520 /* Return the first insn emitted.
7521 We can not just return get_last_insn, because there may have
7522 been multiple instructions emitted. Also note that gen_move_insn may
7523 emit more than one insn itself, so we can not assume that there is one
7524 insn emitted per emit_insn_before call. */
7526 return last ? NEXT_INSN (last) : get_insns ();
7529 /* Delete a previously made output-reload
7530 whose result we now believe is not needed.
7531 First we double-check.
7533 INSN is the insn now being processed.
7534 LAST_RELOAD_REG is the hard register number for which we want to delete
7535 the last output reload.
7536 J is the reload-number that originally used REG. The caller has made
7537 certain that reload J doesn't use REG any longer for input. */
7540 delete_output_reload (insn, j, last_reload_reg)
7543 int last_reload_reg;
7545 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7546 rtx reg = spill_reg_stored_to[last_reload_reg];
7549 int n_inherited = 0;
7553 /* Get the raw pseudo-register referred to. */
7555 while (GET_CODE (reg) == SUBREG)
7556 reg = SUBREG_REG (reg);
7557 substed = reg_equiv_memory_loc[REGNO (reg)];
7559 /* This is unsafe if the operand occurs more often in the current
7560 insn than it is inherited. */
7561 for (k = n_reloads - 1; k >= 0; k--)
7563 rtx reg2 = rld[k].in;
7566 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7567 reg2 = rld[k].in_reg;
7569 if (rld[k].out && ! rld[k].out_reg)
7570 reg2 = XEXP (rld[k].in_reg, 0);
7572 while (GET_CODE (reg2) == SUBREG)
7573 reg2 = SUBREG_REG (reg2);
7574 if (rtx_equal_p (reg2, reg))
7576 if (reload_inherited[k] || reload_override_in[k] || k == j)
7579 reg2 = rld[k].out_reg;
7582 while (GET_CODE (reg2) == SUBREG)
7583 reg2 = XEXP (reg2, 0);
7584 if (rtx_equal_p (reg2, reg))
7591 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7593 n_occurrences += count_occurrences (PATTERN (insn), substed, 0);
7594 if (n_occurrences > n_inherited)
7597 /* If the pseudo-reg we are reloading is no longer referenced
7598 anywhere between the store into it and here,
7599 and no jumps or labels intervene, then the value can get
7600 here through the reload reg alone.
7601 Otherwise, give up--return. */
7602 for (i1 = NEXT_INSN (output_reload_insn);
7603 i1 != insn; i1 = NEXT_INSN (i1))
7605 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7607 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7608 && reg_mentioned_p (reg, PATTERN (i1)))
7610 /* If this is USE in front of INSN, we only have to check that
7611 there are no more references than accounted for by inheritance. */
7612 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7614 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7615 i1 = NEXT_INSN (i1);
7617 if (n_occurrences <= n_inherited && i1 == insn)
7623 /* The caller has already checked that REG dies or is set in INSN.
7624 It has also checked that we are optimizing, and thus some inaccurancies
7625 in the debugging information are acceptable.
7626 So we could just delete output_reload_insn.
7627 But in some cases we can improve the debugging information without
7628 sacrificing optimization - maybe even improving the code:
7629 See if the pseudo reg has been completely replaced
7630 with reload regs. If so, delete the store insn
7631 and forget we had a stack slot for the pseudo. */
7632 if (rld[j].out != rld[j].in
7633 && REG_N_DEATHS (REGNO (reg)) == 1
7634 && REG_N_SETS (REGNO (reg)) == 1
7635 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7636 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7640 /* We know that it was used only between here
7641 and the beginning of the current basic block.
7642 (We also know that the last use before INSN was
7643 the output reload we are thinking of deleting, but never mind that.)
7644 Search that range; see if any ref remains. */
7645 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7647 rtx set = single_set (i2);
7649 /* Uses which just store in the pseudo don't count,
7650 since if they are the only uses, they are dead. */
7651 if (set != 0 && SET_DEST (set) == reg)
7653 if (GET_CODE (i2) == CODE_LABEL
7654 || GET_CODE (i2) == JUMP_INSN)
7656 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7657 && reg_mentioned_p (reg, PATTERN (i2)))
7659 /* Some other ref remains; just delete the output reload we
7661 delete_address_reloads (output_reload_insn, insn);
7662 PUT_CODE (output_reload_insn, NOTE);
7663 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7664 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7669 /* Delete the now-dead stores into this pseudo. */
7670 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7672 rtx set = single_set (i2);
7674 if (set != 0 && SET_DEST (set) == reg)
7676 delete_address_reloads (i2, insn);
7677 /* This might be a basic block head,
7678 thus don't use delete_insn. */
7679 PUT_CODE (i2, NOTE);
7680 NOTE_SOURCE_FILE (i2) = 0;
7681 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7683 if (GET_CODE (i2) == CODE_LABEL
7684 || GET_CODE (i2) == JUMP_INSN)
7688 /* For the debugging info,
7689 say the pseudo lives in this reload reg. */
7690 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7691 alter_reg (REGNO (reg), -1);
7693 delete_address_reloads (output_reload_insn, insn);
7694 PUT_CODE (output_reload_insn, NOTE);
7695 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7696 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7700 /* We are going to delete DEAD_INSN. Recursively delete loads of
7701 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7702 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7704 delete_address_reloads (dead_insn, current_insn)
7705 rtx dead_insn, current_insn;
7707 rtx set = single_set (dead_insn);
7708 rtx set2, dst, prev, next;
7711 rtx dst = SET_DEST (set);
7712 if (GET_CODE (dst) == MEM)
7713 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7715 /* If we deleted the store from a reloaded post_{in,de}c expression,
7716 we can delete the matching adds. */
7717 prev = PREV_INSN (dead_insn);
7718 next = NEXT_INSN (dead_insn);
7719 if (! prev || ! next)
7721 set = single_set (next);
7722 set2 = single_set (prev);
7724 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7725 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7726 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7728 dst = SET_DEST (set);
7729 if (! rtx_equal_p (dst, SET_DEST (set2))
7730 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7731 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7732 || (INTVAL (XEXP (SET_SRC (set), 1))
7733 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7739 /* Subfunction of delete_address_reloads: process registers found in X. */
7741 delete_address_reloads_1 (dead_insn, x, current_insn)
7742 rtx dead_insn, x, current_insn;
7744 rtx prev, set, dst, i2;
7746 enum rtx_code code = GET_CODE (x);
7750 const char *fmt = GET_RTX_FORMAT (code);
7751 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7754 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7755 else if (fmt[i] == 'E')
7757 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7758 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7765 if (spill_reg_order[REGNO (x)] < 0)
7768 /* Scan backwards for the insn that sets x. This might be a way back due
7770 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7772 code = GET_CODE (prev);
7773 if (code == CODE_LABEL || code == JUMP_INSN)
7775 if (GET_RTX_CLASS (code) != 'i')
7777 if (reg_set_p (x, PATTERN (prev)))
7779 if (reg_referenced_p (x, PATTERN (prev)))
7782 if (! prev || INSN_UID (prev) < reload_first_uid)
7784 /* Check that PREV only sets the reload register. */
7785 set = single_set (prev);
7788 dst = SET_DEST (set);
7789 if (GET_CODE (dst) != REG
7790 || ! rtx_equal_p (dst, x))
7792 if (! reg_set_p (dst, PATTERN (dead_insn)))
7794 /* Check if DST was used in a later insn -
7795 it might have been inherited. */
7796 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7798 if (GET_CODE (i2) == CODE_LABEL)
7802 if (reg_referenced_p (dst, PATTERN (i2)))
7804 /* If there is a reference to the register in the current insn,
7805 it might be loaded in a non-inherited reload. If no other
7806 reload uses it, that means the register is set before
7808 if (i2 == current_insn)
7810 for (j = n_reloads - 1; j >= 0; j--)
7811 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7812 || reload_override_in[j] == dst)
7814 for (j = n_reloads - 1; j >= 0; j--)
7815 if (rld[j].in && rld[j].reg_rtx == dst)
7822 if (GET_CODE (i2) == JUMP_INSN)
7824 /* If DST is still live at CURRENT_INSN, check if it is used for
7825 any reload. Note that even if CURRENT_INSN sets DST, we still
7826 have to check the reloads. */
7827 if (i2 == current_insn)
7829 for (j = n_reloads - 1; j >= 0; j--)
7830 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7831 || reload_override_in[j] == dst)
7833 /* ??? We can't finish the loop here, because dst might be
7834 allocated to a pseudo in this block if no reload in this
7835 block needs any of the clsses containing DST - see
7836 spill_hard_reg. There is no easy way to tell this, so we
7837 have to scan till the end of the basic block. */
7839 if (reg_set_p (dst, PATTERN (i2)))
7843 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7844 reg_reloaded_contents[REGNO (dst)] = -1;
7845 /* Can't use delete_insn here because PREV might be a basic block head. */
7846 PUT_CODE (prev, NOTE);
7847 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
7848 NOTE_SOURCE_FILE (prev) = 0;
7851 /* Output reload-insns to reload VALUE into RELOADREG.
7852 VALUE is an autoincrement or autodecrement RTX whose operand
7853 is a register or memory location;
7854 so reloading involves incrementing that location.
7855 IN is either identical to VALUE, or some cheaper place to reload from.
7857 INC_AMOUNT is the number to increment or decrement by (always positive).
7858 This cannot be deduced from VALUE.
7860 Return the instruction that stores into RELOADREG. */
7863 inc_for_reload (reloadreg, in, value, inc_amount)
7868 /* REG or MEM to be copied and incremented. */
7869 rtx incloc = XEXP (value, 0);
7870 /* Nonzero if increment after copying. */
7871 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7877 rtx real_in = in == value ? XEXP (in, 0) : in;
7879 /* No hard register is equivalent to this register after
7880 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7881 we could inc/dec that register as well (maybe even using it for
7882 the source), but I'm not sure it's worth worrying about. */
7883 if (GET_CODE (incloc) == REG)
7884 reg_last_reload_reg[REGNO (incloc)] = 0;
7886 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7887 inc_amount = -inc_amount;
7889 inc = GEN_INT (inc_amount);
7891 /* If this is post-increment, first copy the location to the reload reg. */
7892 if (post && real_in != reloadreg)
7893 emit_insn (gen_move_insn (reloadreg, real_in));
7897 /* See if we can directly increment INCLOC. Use a method similar to
7898 that in gen_reload. */
7900 last = get_last_insn ();
7901 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7902 gen_rtx_PLUS (GET_MODE (incloc),
7905 code = recog_memoized (add_insn);
7908 extract_insn (add_insn);
7909 if (constrain_operands (1))
7911 /* If this is a pre-increment and we have incremented the value
7912 where it lives, copy the incremented value to RELOADREG to
7913 be used as an address. */
7916 emit_insn (gen_move_insn (reloadreg, incloc));
7921 delete_insns_since (last);
7924 /* If couldn't do the increment directly, must increment in RELOADREG.
7925 The way we do this depends on whether this is pre- or post-increment.
7926 For pre-increment, copy INCLOC to the reload register, increment it
7927 there, then save back. */
7931 if (in != reloadreg)
7932 emit_insn (gen_move_insn (reloadreg, real_in));
7933 emit_insn (gen_add2_insn (reloadreg, inc));
7934 store = emit_insn (gen_move_insn (incloc, reloadreg));
7939 Because this might be a jump insn or a compare, and because RELOADREG
7940 may not be available after the insn in an input reload, we must do
7941 the incrementation before the insn being reloaded for.
7943 We have already copied IN to RELOADREG. Increment the copy in
7944 RELOADREG, save that back, then decrement RELOADREG so it has
7945 the original value. */
7947 emit_insn (gen_add2_insn (reloadreg, inc));
7948 store = emit_insn (gen_move_insn (incloc, reloadreg));
7949 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7955 /* Return 1 if we are certain that the constraint-string STRING allows
7956 the hard register REG. Return 0 if we can't be sure of this. */
7959 constraint_accepts_reg_p (string, reg)
7964 int regno = true_regnum (reg);
7967 /* Initialize for first alternative. */
7969 /* Check that each alternative contains `g' or `r'. */
7971 switch (c = *string++)
7974 /* If an alternative lacks `g' or `r', we lose. */
7977 /* If an alternative lacks `g' or `r', we lose. */
7980 /* Initialize for next alternative. */
7985 /* Any general reg wins for this alternative. */
7986 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7990 /* Any reg in specified class wins for this alternative. */
7992 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7994 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
8000 /* INSN is a no-op; delete it.
8001 If this sets the return value of the function, we must keep a USE around,
8002 in case this is in a different basic block than the final USE. Otherwise,
8003 we could loose important register lifeness information on
8004 SMALL_REGISTER_CLASSES machines, where return registers might be used as
8005 spills: subsequent passes assume that spill registers are dead at the end
8007 VALUE must be the return value in such a case, NULL otherwise. */
8009 reload_cse_delete_noop_set (insn, value)
8014 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
8015 INSN_CODE (insn) = -1;
8016 REG_NOTES (insn) = NULL_RTX;
8020 PUT_CODE (insn, NOTE);
8021 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8022 NOTE_SOURCE_FILE (insn) = 0;
8026 /* See whether a single set SET is a noop. */
8028 reload_cse_noop_set_p (set)
8031 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
8034 /* Try to simplify INSN. */
8036 reload_cse_simplify (insn)
8039 rtx body = PATTERN (insn);
8041 if (GET_CODE (body) == SET)
8044 if (reload_cse_noop_set_p (body))
8046 rtx value = SET_DEST (body);
8047 if (! REG_FUNCTION_VALUE_P (SET_DEST (body)))
8049 reload_cse_delete_noop_set (insn, value);
8053 /* It's not a no-op, but we can try to simplify it. */
8054 count += reload_cse_simplify_set (body, insn);
8057 apply_change_group ();
8059 reload_cse_simplify_operands (insn);
8061 else if (GET_CODE (body) == PARALLEL)
8065 rtx value = NULL_RTX;
8067 /* If every action in a PARALLEL is a noop, we can delete
8068 the entire PARALLEL. */
8069 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8071 rtx part = XVECEXP (body, 0, i);
8072 if (GET_CODE (part) == SET)
8074 if (! reload_cse_noop_set_p (part))
8076 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8080 value = SET_DEST (part);
8083 else if (GET_CODE (part) != CLOBBER)
8089 reload_cse_delete_noop_set (insn, value);
8090 /* We're done with this insn. */
8094 /* It's not a no-op, but we can try to simplify it. */
8095 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8096 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8097 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8100 apply_change_group ();
8102 reload_cse_simplify_operands (insn);
8106 /* Do a very simple CSE pass over the hard registers.
8108 This function detects no-op moves where we happened to assign two
8109 different pseudo-registers to the same hard register, and then
8110 copied one to the other. Reload will generate a useless
8111 instruction copying a register to itself.
8113 This function also detects cases where we load a value from memory
8114 into two different registers, and (if memory is more expensive than
8115 registers) changes it to simply copy the first register into the
8118 Another optimization is performed that scans the operands of each
8119 instruction to see whether the value is already available in a
8120 hard register. It then replaces the operand with the hard register
8121 if possible, much like an optional reload would. */
8124 reload_cse_regs_1 (first)
8130 init_alias_analysis ();
8132 for (insn = first; insn; insn = NEXT_INSN (insn))
8135 reload_cse_simplify (insn);
8137 cselib_process_insn (insn);
8141 end_alias_analysis ();
8145 /* Call cse / combine like post-reload optimization phases.
8146 FIRST is the first instruction. */
8148 reload_cse_regs (first)
8151 reload_cse_regs_1 (first);
8153 reload_cse_move2add (first);
8154 if (flag_expensive_optimizations)
8155 reload_cse_regs_1 (first);
8158 /* Try to simplify a single SET instruction. SET is the set pattern.
8159 INSN is the instruction it came from.
8160 This function only handles one case: if we set a register to a value
8161 which is not a register, we try to find that value in some other register
8162 and change the set into a register copy. */
8165 reload_cse_simplify_set (set, insn)
8172 enum reg_class dclass;
8175 struct elt_loc_list *l;
8176 #ifdef LOAD_EXTEND_OP
8177 enum rtx_code extend_op = NIL;
8180 dreg = true_regnum (SET_DEST (set));
8184 src = SET_SRC (set);
8185 if (side_effects_p (src) || true_regnum (src) >= 0)
8188 dclass = REGNO_REG_CLASS (dreg);
8190 #ifdef LOAD_EXTEND_OP
8191 /* When replacing a memory with a register, we need to honor assumptions
8192 that combine made wrt the contents of sign bits. We'll do this by
8193 generating an extend instruction instead of a reg->reg copy. Thus
8194 the destination must be a register that we can widen. */
8195 if (GET_CODE (src) == MEM
8196 && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD
8197 && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != NIL
8198 && GET_CODE (SET_DEST (set)) != REG)
8202 /* If memory loads are cheaper than register copies, don't change them. */
8203 if (GET_CODE (src) == MEM)
8204 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8205 else if (CONSTANT_P (src))
8206 old_cost = rtx_cost (src, SET);
8207 else if (GET_CODE (src) == REG)
8208 old_cost = REGISTER_MOVE_COST (GET_MODE (src),
8209 REGNO_REG_CLASS (REGNO (src)), dclass);
8212 old_cost = rtx_cost (src, SET);
8214 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0);
8217 for (l = val->locs; l; l = l->next)
8219 rtx this_rtx = l->loc;
8222 if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
8224 #ifdef LOAD_EXTEND_OP
8225 if (extend_op != NIL)
8227 HOST_WIDE_INT this_val;
8229 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
8230 constants, such as SYMBOL_REF, cannot be extended. */
8231 if (GET_CODE (this_rtx) != CONST_INT)
8234 this_val = INTVAL (this_rtx);
8238 this_val &= GET_MODE_MASK (GET_MODE (src));
8241 /* ??? In theory we're already extended. */
8242 if (this_val == trunc_int_for_mode (this_val, GET_MODE (src)))
8247 this_rtx = GEN_INT (this_val);
8250 this_cost = rtx_cost (this_rtx, SET);
8252 else if (GET_CODE (this_rtx) == REG)
8254 #ifdef LOAD_EXTEND_OP
8255 if (extend_op != NIL)
8257 this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
8258 this_cost = rtx_cost (this_rtx, SET);
8262 this_cost = REGISTER_MOVE_COST (GET_MODE (this_rtx),
8263 REGNO_REG_CLASS (REGNO (this_rtx)),
8269 /* If equal costs, prefer registers over anything else. That
8270 tends to lead to smaller instructions on some machines. */
8271 if (this_cost < old_cost
8272 || (this_cost == old_cost
8273 && GET_CODE (this_rtx) == REG
8274 && GET_CODE (SET_SRC (set)) != REG))
8276 #ifdef LOAD_EXTEND_OP
8277 rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set)));
8278 ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
8279 validate_change (insn, &SET_DEST (set), wide_dest, 1);
8282 validate_change (insn, &SET_SRC (set), copy_rtx (this_rtx), 1);
8283 old_cost = this_cost, did_change = 1;
8290 /* Try to replace operands in INSN with equivalent values that are already
8291 in registers. This can be viewed as optional reloading.
8293 For each non-register operand in the insn, see if any hard regs are
8294 known to be equivalent to that operand. Record the alternatives which
8295 can accept these hard registers. Among all alternatives, select the
8296 ones which are better or equal to the one currently matching, where
8297 "better" is in terms of '?' and '!' constraints. Among the remaining
8298 alternatives, select the one which replaces most operands with
8302 reload_cse_simplify_operands (insn)
8307 /* For each operand, all registers that are equivalent to it. */
8308 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8310 const char *constraints[MAX_RECOG_OPERANDS];
8312 /* Vector recording how bad an alternative is. */
8313 int *alternative_reject;
8314 /* Vector recording how many registers can be introduced by choosing
8315 this alternative. */
8316 int *alternative_nregs;
8317 /* Array of vectors recording, for each operand and each alternative,
8318 which hard register to substitute, or -1 if the operand should be
8320 int *op_alt_regno[MAX_RECOG_OPERANDS];
8321 /* Array of alternatives, sorted in order of decreasing desirability. */
8322 int *alternative_order;
8323 rtx reg = gen_rtx_REG (VOIDmode, -1);
8325 extract_insn (insn);
8327 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8330 /* Figure out which alternative currently matches. */
8331 if (! constrain_operands (1))
8332 fatal_insn_not_found (insn);
8334 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8335 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8336 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8337 memset ((char *)alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
8338 memset ((char *)alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
8340 /* For each operand, find out which regs are equivalent. */
8341 for (i = 0; i < recog_data.n_operands; i++)
8344 struct elt_loc_list *l;
8346 CLEAR_HARD_REG_SET (equiv_regs[i]);
8348 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8349 right, so avoid the problem here. Likewise if we have a constant
8350 and the insn pattern doesn't tell us the mode we need. */
8351 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL
8352 || (CONSTANT_P (recog_data.operand[i])
8353 && recog_data.operand_mode[i] == VOIDmode))
8356 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8360 for (l = v->locs; l; l = l->next)
8361 if (GET_CODE (l->loc) == REG)
8362 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8365 for (i = 0; i < recog_data.n_operands; i++)
8367 enum machine_mode mode;
8371 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8372 for (j = 0; j < recog_data.n_alternatives; j++)
8373 op_alt_regno[i][j] = -1;
8375 p = constraints[i] = recog_data.constraints[i];
8376 mode = recog_data.operand_mode[i];
8378 /* Add the reject values for each alternative given by the constraints
8379 for this operand. */
8387 alternative_reject[j] += 3;
8389 alternative_reject[j] += 300;
8392 /* We won't change operands which are already registers. We
8393 also don't want to modify output operands. */
8394 regno = true_regnum (recog_data.operand[i]);
8396 || constraints[i][0] == '='
8397 || constraints[i][0] == '+')
8400 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8402 int class = (int) NO_REGS;
8404 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8407 REGNO (reg) = regno;
8408 PUT_MODE (reg, mode);
8410 /* We found a register equal to this operand. Now look for all
8411 alternatives that can accept this register and have not been
8412 assigned a register they can use yet. */
8421 case '=': case '+': case '?':
8422 case '#': case '&': case '!':
8424 case '0': case '1': case '2': case '3': case '4':
8425 case '5': case '6': case '7': case '8': case '9':
8426 case 'm': case '<': case '>': case 'V': case 'o':
8427 case 'E': case 'F': case 'G': case 'H':
8428 case 's': case 'i': case 'n':
8429 case 'I': case 'J': case 'K': case 'L':
8430 case 'M': case 'N': case 'O': case 'P':
8432 /* These don't say anything we care about. */
8436 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8441 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
8444 case ',': case '\0':
8445 /* See if REGNO fits this alternative, and set it up as the
8446 replacement register if we don't have one for this
8447 alternative yet and the operand being replaced is not
8448 a cheap CONST_INT. */
8449 if (op_alt_regno[i][j] == -1
8450 && reg_fits_class_p (reg, class, 0, mode)
8451 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8452 || (rtx_cost (recog_data.operand[i], SET)
8453 > rtx_cost (reg, SET))))
8455 alternative_nregs[j]++;
8456 op_alt_regno[i][j] = regno;
8468 /* Record all alternatives which are better or equal to the currently
8469 matching one in the alternative_order array. */
8470 for (i = j = 0; i < recog_data.n_alternatives; i++)
8471 if (alternative_reject[i] <= alternative_reject[which_alternative])
8472 alternative_order[j++] = i;
8473 recog_data.n_alternatives = j;
8475 /* Sort it. Given a small number of alternatives, a dumb algorithm
8476 won't hurt too much. */
8477 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8480 int best_reject = alternative_reject[alternative_order[i]];
8481 int best_nregs = alternative_nregs[alternative_order[i]];
8484 for (j = i + 1; j < recog_data.n_alternatives; j++)
8486 int this_reject = alternative_reject[alternative_order[j]];
8487 int this_nregs = alternative_nregs[alternative_order[j]];
8489 if (this_reject < best_reject
8490 || (this_reject == best_reject && this_nregs < best_nregs))
8493 best_reject = this_reject;
8494 best_nregs = this_nregs;
8498 tmp = alternative_order[best];
8499 alternative_order[best] = alternative_order[i];
8500 alternative_order[i] = tmp;
8503 /* Substitute the operands as determined by op_alt_regno for the best
8505 j = alternative_order[0];
8507 for (i = 0; i < recog_data.n_operands; i++)
8509 enum machine_mode mode = recog_data.operand_mode[i];
8510 if (op_alt_regno[i][j] == -1)
8513 validate_change (insn, recog_data.operand_loc[i],
8514 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8517 for (i = recog_data.n_dups - 1; i >= 0; i--)
8519 int op = recog_data.dup_num[i];
8520 enum machine_mode mode = recog_data.operand_mode[op];
8522 if (op_alt_regno[op][j] == -1)
8525 validate_change (insn, recog_data.dup_loc[i],
8526 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8529 return apply_change_group ();
8532 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8534 This code might also be useful when reload gave up on reg+reg addresssing
8535 because of clashes between the return register and INDEX_REG_CLASS. */
8537 /* The maximum number of uses of a register we can keep track of to
8538 replace them with reg+reg addressing. */
8539 #define RELOAD_COMBINE_MAX_USES 6
8541 /* INSN is the insn where a register has ben used, and USEP points to the
8542 location of the register within the rtl. */
8543 struct reg_use { rtx insn, *usep; };
8545 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8546 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8547 indicates where it becomes live again.
8548 Otherwise, USE_INDEX is the index of the last encountered use of the
8549 register (which is first among these we have seen since we scan backwards),
8550 OFFSET contains the constant offset that is added to the register in
8551 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8552 last, of these uses.
8553 STORE_RUID is always meaningful if we only want to use a value in a
8554 register in a different place: it denotes the next insn in the insn
8555 stream (i.e. the last ecountered) that sets or clobbers the register. */
8558 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8563 } reg_state[FIRST_PSEUDO_REGISTER];
8565 /* Reverse linear uid. This is increased in reload_combine while scanning
8566 the instructions from last to first. It is used to set last_label_ruid
8567 and the store_ruid / use_ruid fields in reg_state. */
8568 static int reload_combine_ruid;
8570 #define LABEL_LIVE(LABEL) \
8571 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8577 int first_index_reg = -1, last_index_reg;
8580 int last_label_ruid;
8581 int min_labelno, n_labels;
8582 HARD_REG_SET ever_live_at_start, *label_live;
8584 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
8585 reload has already used it where appropriate, so there is no use in
8586 trying to generate it now. */
8587 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8590 /* To avoid wasting too much time later searching for an index register,
8591 determine the minimum and maximum index register numbers. */
8592 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8593 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
8595 if (first_index_reg == -1)
8596 first_index_reg = r;
8601 /* If no index register is available, we can quit now. */
8602 if (first_index_reg == -1)
8605 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8606 information is a bit fuzzy immediately after reload, but it's
8607 still good enough to determine which registers are live at a jump
8609 min_labelno = get_first_label_num ();
8610 n_labels = max_label_num () - min_labelno;
8611 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8612 CLEAR_HARD_REG_SET (ever_live_at_start);
8614 for (i = n_basic_blocks - 1; i >= 0; i--)
8616 insn = BLOCK_HEAD (i);
8617 if (GET_CODE (insn) == CODE_LABEL)
8621 REG_SET_TO_HARD_REG_SET (live,
8622 BASIC_BLOCK (i)->global_live_at_start);
8623 compute_use_by_pseudos (&live,
8624 BASIC_BLOCK (i)->global_live_at_start);
8625 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8626 IOR_HARD_REG_SET (ever_live_at_start, live);
8630 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8631 last_label_ruid = reload_combine_ruid = 0;
8632 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8634 reg_state[r].store_ruid = reload_combine_ruid;
8636 reg_state[r].use_index = -1;
8638 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8641 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8645 /* We cannot do our optimization across labels. Invalidating all the use
8646 information we have would be costly, so we just note where the label
8647 is and then later disable any optimization that would cross it. */
8648 if (GET_CODE (insn) == CODE_LABEL)
8649 last_label_ruid = reload_combine_ruid;
8650 else if (GET_CODE (insn) == BARRIER)
8651 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8652 if (! fixed_regs[r])
8653 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8655 if (! INSN_P (insn))
8658 reload_combine_ruid++;
8660 /* Look for (set (REGX) (CONST_INT))
8661 (set (REGX) (PLUS (REGX) (REGY)))
8663 ... (MEM (REGX)) ...
8665 (set (REGZ) (CONST_INT))
8667 ... (MEM (PLUS (REGZ) (REGY)))... .
8669 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8670 and that we know all uses of REGX before it dies. */
8671 set = single_set (insn);
8673 && GET_CODE (SET_DEST (set)) == REG
8674 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8675 GET_MODE (SET_DEST (set)))
8677 && GET_CODE (SET_SRC (set)) == PLUS
8678 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8679 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8680 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8682 rtx reg = SET_DEST (set);
8683 rtx plus = SET_SRC (set);
8684 rtx base = XEXP (plus, 1);
8685 rtx prev = prev_nonnote_insn (insn);
8686 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8687 unsigned int regno = REGNO (reg);
8688 rtx const_reg = NULL_RTX;
8689 rtx reg_sum = NULL_RTX;
8691 /* Now, we need an index register.
8692 We'll set index_reg to this index register, const_reg to the
8693 register that is to be loaded with the constant
8694 (denoted as REGZ in the substitution illustration above),
8695 and reg_sum to the register-register that we want to use to
8696 substitute uses of REG (typically in MEMs) with.
8697 First check REG and BASE for being index registers;
8698 we can use them even if they are not dead. */
8699 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8700 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8708 /* Otherwise, look for a free index register. Since we have
8709 checked above that neiter REG nor BASE are index registers,
8710 if we find anything at all, it will be different from these
8712 for (i = first_index_reg; i <= last_index_reg; i++)
8714 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8716 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8717 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8718 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8720 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8722 const_reg = index_reg;
8723 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8729 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8730 (REGY), i.e. BASE, is not clobbered before the last use we'll
8733 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8734 && rtx_equal_p (SET_DEST (prev_set), reg)
8735 && reg_state[regno].use_index >= 0
8736 && (reg_state[REGNO (base)].store_ruid
8737 <= reg_state[regno].use_ruid)
8742 /* Change destination register and, if necessary, the
8743 constant value in PREV, the constant loading instruction. */
8744 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8745 if (reg_state[regno].offset != const0_rtx)
8746 validate_change (prev,
8747 &SET_SRC (prev_set),
8748 GEN_INT (INTVAL (SET_SRC (prev_set))
8749 + INTVAL (reg_state[regno].offset)),
8752 /* Now for every use of REG that we have recorded, replace REG
8754 for (i = reg_state[regno].use_index;
8755 i < RELOAD_COMBINE_MAX_USES; i++)
8756 validate_change (reg_state[regno].reg_use[i].insn,
8757 reg_state[regno].reg_use[i].usep,
8760 if (apply_change_group ())
8764 /* Delete the reg-reg addition. */
8765 PUT_CODE (insn, NOTE);
8766 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8767 NOTE_SOURCE_FILE (insn) = 0;
8769 if (reg_state[regno].offset != const0_rtx)
8770 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8772 for (np = ®_NOTES (prev); *np;)
8774 if (REG_NOTE_KIND (*np) == REG_EQUAL
8775 || REG_NOTE_KIND (*np) == REG_EQUIV)
8776 *np = XEXP (*np, 1);
8778 np = &XEXP (*np, 1);
8781 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8782 reg_state[REGNO (const_reg)].store_ruid
8783 = reload_combine_ruid;
8789 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8791 if (GET_CODE (insn) == CALL_INSN)
8795 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8796 if (call_used_regs[r])
8798 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8799 reg_state[r].store_ruid = reload_combine_ruid;
8802 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8803 link = XEXP (link, 1))
8805 rtx usage_rtx = XEXP (XEXP (link, 0), 0);
8806 if (GET_CODE (usage_rtx) == REG)
8809 unsigned int start_reg = REGNO (usage_rtx);
8810 unsigned int num_regs =
8811 HARD_REGNO_NREGS (start_reg, GET_MODE (usage_rtx));
8812 unsigned int end_reg = start_reg + num_regs - 1;
8813 for (i = start_reg; i <= end_reg; i++)
8814 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
8816 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8817 reg_state[i].store_ruid = reload_combine_ruid;
8820 reg_state[i].use_index = -1;
8825 else if (GET_CODE (insn) == JUMP_INSN
8826 && GET_CODE (PATTERN (insn)) != RETURN)
8828 /* Non-spill registers might be used at the call destination in
8829 some unknown fashion, so we have to mark the unknown use. */
8832 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8833 && JUMP_LABEL (insn))
8834 live = &LABEL_LIVE (JUMP_LABEL (insn));
8836 live = &ever_live_at_start;
8838 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8839 if (TEST_HARD_REG_BIT (*live, i))
8840 reg_state[i].use_index = -1;
8843 reload_combine_note_use (&PATTERN (insn), insn);
8844 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8846 if (REG_NOTE_KIND (note) == REG_INC
8847 && GET_CODE (XEXP (note, 0)) == REG)
8849 int regno = REGNO (XEXP (note, 0));
8851 reg_state[regno].store_ruid = reload_combine_ruid;
8852 reg_state[regno].use_index = -1;
8860 /* Check if DST is a register or a subreg of a register; if it is,
8861 update reg_state[regno].store_ruid and reg_state[regno].use_index
8862 accordingly. Called via note_stores from reload_combine. */
8865 reload_combine_note_store (dst, set, data)
8867 void *data ATTRIBUTE_UNUSED;
8871 enum machine_mode mode = GET_MODE (dst);
8873 if (GET_CODE (dst) == SUBREG)
8875 regno = SUBREG_WORD (dst);
8876 dst = SUBREG_REG (dst);
8878 if (GET_CODE (dst) != REG)
8880 regno += REGNO (dst);
8882 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8883 careful with registers / register parts that are not full words.
8885 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8886 if (GET_CODE (set) != SET
8887 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8888 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8889 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8891 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8893 reg_state[i].use_index = -1;
8894 reg_state[i].store_ruid = reload_combine_ruid;
8899 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8901 reg_state[i].store_ruid = reload_combine_ruid;
8902 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8907 /* XP points to a piece of rtl that has to be checked for any uses of
8909 *XP is the pattern of INSN, or a part of it.
8910 Called from reload_combine, and recursively by itself. */
8912 reload_combine_note_use (xp, insn)
8916 enum rtx_code code = x->code;
8919 rtx offset = const0_rtx; /* For the REG case below. */
8924 if (GET_CODE (SET_DEST (x)) == REG)
8926 reload_combine_note_use (&SET_SRC (x), insn);
8932 /* If this is the USE of a return value, we can't change it. */
8933 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8935 /* Mark the return register as used in an unknown fashion. */
8936 rtx reg = XEXP (x, 0);
8937 int regno = REGNO (reg);
8938 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8940 while (--nregs >= 0)
8941 reg_state[regno + nregs].use_index = -1;
8947 if (GET_CODE (SET_DEST (x)) == REG)
8952 /* We are interested in (plus (reg) (const_int)) . */
8953 if (GET_CODE (XEXP (x, 0)) != REG
8954 || GET_CODE (XEXP (x, 1)) != CONST_INT)
8956 offset = XEXP (x, 1);
8961 int regno = REGNO (x);
8965 /* Some spurious USEs of pseudo registers might remain.
8966 Just ignore them. */
8967 if (regno >= FIRST_PSEUDO_REGISTER)
8970 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
8972 /* We can't substitute into multi-hard-reg uses. */
8975 while (--nregs >= 0)
8976 reg_state[regno + nregs].use_index = -1;
8980 /* If this register is already used in some unknown fashion, we
8982 If we decrement the index from zero to -1, we can't store more
8983 uses, so this register becomes used in an unknown fashion. */
8984 use_index = --reg_state[regno].use_index;
8988 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
8990 /* We have found another use for a register that is already
8991 used later. Check if the offsets match; if not, mark the
8992 register as used in an unknown fashion. */
8993 if (! rtx_equal_p (offset, reg_state[regno].offset))
8995 reg_state[regno].use_index = -1;
9001 /* This is the first use of this register we have seen since we
9002 marked it as dead. */
9003 reg_state[regno].offset = offset;
9004 reg_state[regno].use_ruid = reload_combine_ruid;
9006 reg_state[regno].reg_use[use_index].insn = insn;
9007 reg_state[regno].reg_use[use_index].usep = xp;
9015 /* Recursively process the components of X. */
9016 fmt = GET_RTX_FORMAT (code);
9017 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9020 reload_combine_note_use (&XEXP (x, i), insn);
9021 else if (fmt[i] == 'E')
9023 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9024 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9029 /* See if we can reduce the cost of a constant by replacing a move
9030 with an add. We track situations in which a register is set to a
9031 constant or to a register plus a constant. */
9032 /* We cannot do our optimization across labels. Invalidating all the
9033 information about register contents we have would be costly, so we
9034 use move2add_last_label_luid to note where the label is and then
9035 later disable any optimization that would cross it.
9036 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9037 reg_set_luid[n] is greater than last_label_luid[n] . */
9038 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9040 /* If reg_base_reg[n] is negative, register n has been set to
9041 reg_offset[n] in mode reg_mode[n] .
9042 If reg_base_reg[n] is non-negative, register n has been set to the
9043 sum of reg_offset[n] and the value of register reg_base_reg[n]
9044 before reg_set_luid[n], calculated in mode reg_mode[n] . */
9045 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
9046 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9047 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9049 /* move2add_luid is linearily increased while scanning the instructions
9050 from first to last. It is used to set reg_set_luid in
9051 reload_cse_move2add and move2add_note_store. */
9052 static int move2add_luid;
9054 /* move2add_last_label_luid is set whenever a label is found. Labels
9055 invalidate all previously collected reg_offset data. */
9056 static int move2add_last_label_luid;
9058 /* Generate a CONST_INT and force it in the range of MODE. */
9060 static HOST_WIDE_INT
9061 sext_for_mode (mode, value)
9062 enum machine_mode mode;
9063 HOST_WIDE_INT value;
9065 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
9066 int width = GET_MODE_BITSIZE (mode);
9068 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
9070 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
9071 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
9072 cval |= (HOST_WIDE_INT) -1 << width;
9077 /* ??? We don't know how zero / sign extension is handled, hence we
9078 can't go from a narrower to a wider mode. */
9079 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
9080 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
9081 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
9082 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
9083 GET_MODE_BITSIZE (INMODE))))
9086 reload_cse_move2add (first)
9092 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9093 reg_set_luid[i] = 0;
9095 move2add_last_label_luid = 0;
9097 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9101 if (GET_CODE (insn) == CODE_LABEL)
9103 move2add_last_label_luid = move2add_luid;
9104 /* We're going to increment move2add_luid twice after a
9105 label, so that we can use move2add_last_label_luid + 1 as
9106 the luid for constants. */
9110 if (! INSN_P (insn))
9112 pat = PATTERN (insn);
9113 /* For simplicity, we only perform this optimization on
9114 straightforward SETs. */
9115 if (GET_CODE (pat) == SET
9116 && GET_CODE (SET_DEST (pat)) == REG)
9118 rtx reg = SET_DEST (pat);
9119 int regno = REGNO (reg);
9120 rtx src = SET_SRC (pat);
9122 /* Check if we have valid information on the contents of this
9123 register in the mode of REG. */
9124 if (reg_set_luid[regno] > move2add_last_label_luid
9125 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno]))
9127 /* Try to transform (set (REGX) (CONST_INT A))
9129 (set (REGX) (CONST_INT B))
9131 (set (REGX) (CONST_INT A))
9133 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9135 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9138 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9140 - reg_offset[regno]));
9141 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9142 use (set (reg) (reg)) instead.
9143 We don't delete this insn, nor do we convert it into a
9144 note, to avoid losing register notes or the return
9145 value flag. jump2 already knowns how to get rid of
9147 if (new_src == const0_rtx)
9148 success = validate_change (insn, &SET_SRC (pat), reg, 0);
9149 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9150 && have_add2_insn (GET_MODE (reg)))
9151 success = validate_change (insn, &PATTERN (insn),
9152 gen_add2_insn (reg, new_src), 0);
9153 reg_set_luid[regno] = move2add_luid;
9154 reg_mode[regno] = GET_MODE (reg);
9155 reg_offset[regno] = INTVAL (src);
9159 /* Try to transform (set (REGX) (REGY))
9160 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9163 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9166 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9168 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9169 else if (GET_CODE (src) == REG
9170 && reg_set_luid[regno] == reg_set_luid[REGNO (src)]
9171 && reg_base_reg[regno] == reg_base_reg[REGNO (src)]
9172 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg),
9173 reg_mode[REGNO (src)]))
9175 rtx next = next_nonnote_insn (insn);
9178 set = single_set (next);
9180 && SET_DEST (set) == reg
9181 && GET_CODE (SET_SRC (set)) == PLUS
9182 && XEXP (SET_SRC (set), 0) == reg
9183 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9185 rtx src3 = XEXP (SET_SRC (set), 1);
9186 HOST_WIDE_INT added_offset = INTVAL (src3);
9187 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)];
9188 HOST_WIDE_INT regno_offset = reg_offset[regno];
9189 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9195 if (new_src == const0_rtx)
9196 /* See above why we create (set (reg) (reg)) here. */
9198 = validate_change (next, &SET_SRC (set), reg, 0);
9199 else if ((rtx_cost (new_src, PLUS)
9200 < COSTS_N_INSNS (1) + rtx_cost (src3, SET))
9201 && have_add2_insn (GET_MODE (reg)))
9203 = validate_change (next, &PATTERN (next),
9204 gen_add2_insn (reg, new_src), 0);
9207 /* INSN might be the first insn in a basic block
9208 if the preceding insn is a conditional jump
9209 or a possible-throwing call. */
9210 PUT_CODE (insn, NOTE);
9211 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9212 NOTE_SOURCE_FILE (insn) = 0;
9215 reg_mode[regno] = GET_MODE (reg);
9216 reg_offset[regno] = sext_for_mode (GET_MODE (reg),
9225 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9227 if (REG_NOTE_KIND (note) == REG_INC
9228 && GET_CODE (XEXP (note, 0)) == REG)
9230 /* Reset the information about this register. */
9231 int regno = REGNO (XEXP (note, 0));
9232 if (regno < FIRST_PSEUDO_REGISTER)
9233 reg_set_luid[regno] = 0;
9236 note_stores (PATTERN (insn), move2add_note_store, NULL);
9237 /* If this is a CALL_INSN, all call used registers are stored with
9239 if (GET_CODE (insn) == CALL_INSN)
9241 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9243 if (call_used_regs[i])
9244 /* Reset the information about this register. */
9245 reg_set_luid[i] = 0;
9251 /* SET is a SET or CLOBBER that sets DST.
9252 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9253 Called from reload_cse_move2add via note_stores. */
9256 move2add_note_store (dst, set, data)
9258 void *data ATTRIBUTE_UNUSED;
9260 unsigned int regno = 0;
9262 enum machine_mode mode = GET_MODE (dst);
9264 if (GET_CODE (dst) == SUBREG)
9266 regno = SUBREG_WORD (dst);
9267 dst = SUBREG_REG (dst);
9270 /* Some targets do argument pushes without adding REG_INC notes. */
9272 if (GET_CODE (dst) == MEM)
9274 dst = XEXP (dst, 0);
9275 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_DEC
9276 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
9277 reg_set_luid[REGNO (XEXP (dst, 0))] = 0;
9280 if (GET_CODE (dst) != REG)
9283 regno += REGNO (dst);
9285 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9286 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9287 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9288 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9290 rtx src = SET_SRC (set);
9292 HOST_WIDE_INT offset;
9294 /* This may be different from mode, if SET_DEST (set) is a
9296 enum machine_mode dst_mode = GET_MODE (dst);
9298 switch (GET_CODE (src))
9301 if (GET_CODE (XEXP (src, 0)) == REG)
9303 base_reg = XEXP (src, 0);
9305 if (GET_CODE (XEXP (src, 1)) == CONST_INT)
9306 offset = INTVAL (XEXP (src, 1));
9307 else if (GET_CODE (XEXP (src, 1)) == REG
9308 && (reg_set_luid[REGNO (XEXP (src, 1))]
9309 > move2add_last_label_luid)
9310 && (MODES_OK_FOR_MOVE2ADD
9311 (dst_mode, reg_mode[REGNO (XEXP (src, 1))])))
9313 if (reg_base_reg[REGNO (XEXP (src, 1))] < 0)
9314 offset = reg_offset[REGNO (XEXP (src, 1))];
9315 /* Maybe the first register is known to be a
9317 else if (reg_set_luid[REGNO (base_reg)]
9318 > move2add_last_label_luid
9319 && (MODES_OK_FOR_MOVE2ADD
9320 (dst_mode, reg_mode[REGNO (XEXP (src, 1))]))
9321 && reg_base_reg[REGNO (base_reg)] < 0)
9323 offset = reg_offset[REGNO (base_reg)];
9324 base_reg = XEXP (src, 1);
9343 /* Start tracking the register as a constant. */
9344 reg_base_reg[regno] = -1;
9345 reg_offset[regno] = INTVAL (SET_SRC (set));
9346 /* We assign the same luid to all registers set to constants. */
9347 reg_set_luid[regno] = move2add_last_label_luid + 1;
9348 reg_mode[regno] = mode;
9353 /* Invalidate the contents of the register. */
9354 reg_set_luid[regno] = 0;
9358 base_regno = REGNO (base_reg);
9359 /* If information about the base register is not valid, set it
9360 up as a new base register, pretending its value is known
9361 starting from the current insn. */
9362 if (reg_set_luid[base_regno] <= move2add_last_label_luid)
9364 reg_base_reg[base_regno] = base_regno;
9365 reg_offset[base_regno] = 0;
9366 reg_set_luid[base_regno] = move2add_luid;
9367 reg_mode[base_regno] = mode;
9369 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode,
9370 reg_mode[base_regno]))
9373 reg_mode[regno] = mode;
9375 /* Copy base information from our base register. */
9376 reg_set_luid[regno] = reg_set_luid[base_regno];
9377 reg_base_reg[regno] = reg_base_reg[base_regno];
9379 /* Compute the sum of the offsets or constants. */
9380 reg_offset[regno] = sext_for_mode (dst_mode,
9382 + reg_offset[base_regno]);
9386 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9388 for (i = regno; i < endregno; i++)
9389 /* Reset the information about this register. */
9390 reg_set_luid[i] = 0;
9396 add_auto_inc_notes (insn, x)
9400 enum rtx_code code = GET_CODE (x);
9404 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9407 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9411 /* Scan all the operand sub-expressions. */
9412 fmt = GET_RTX_FORMAT (code);
9413 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9416 add_auto_inc_notes (insn, XEXP (x, i));
9417 else if (fmt[i] == 'E')
9418 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9419 add_auto_inc_notes (insn, XVECEXP (x, i, j));
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