1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
36 #include "basic-block.h"
46 /* This file contains the reload pass of the compiler, which is
47 run after register allocation has been done. It checks that
48 each insn is valid (operands required to be in registers really
49 are in registers of the proper class) and fixes up invalid ones
50 by copying values temporarily into registers for the insns
53 The results of register allocation are described by the vector
54 reg_renumber; the insns still contain pseudo regs, but reg_renumber
55 can be used to find which hard reg, if any, a pseudo reg is in.
57 The technique we always use is to free up a few hard regs that are
58 called ``reload regs'', and for each place where a pseudo reg
59 must be in a hard reg, copy it temporarily into one of the reload regs.
61 Reload regs are allocated locally for every instruction that needs
62 reloads. When there are pseudos which are allocated to a register that
63 has been chosen as a reload reg, such pseudos must be ``spilled''.
64 This means that they go to other hard regs, or to stack slots if no other
65 available hard regs can be found. Spilling can invalidate more
66 insns, requiring additional need for reloads, so we must keep checking
67 until the process stabilizes.
69 For machines with different classes of registers, we must keep track
70 of the register class needed for each reload, and make sure that
71 we allocate enough reload registers of each class.
73 The file reload.c contains the code that checks one insn for
74 validity and reports the reloads that it needs. This file
75 is in charge of scanning the entire rtl code, accumulating the
76 reload needs, spilling, assigning reload registers to use for
77 fixing up each insn, and generating the new insns to copy values
78 into the reload registers. */
80 #ifndef REGISTER_MOVE_COST
81 #define REGISTER_MOVE_COST(m, x, y) 2
85 #define LOCAL_REGNO(REGNO) 0
88 /* During reload_as_needed, element N contains a REG rtx for the hard reg
89 into which reg N has been reloaded (perhaps for a previous insn). */
90 static rtx *reg_last_reload_reg;
92 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
93 for an output reload that stores into reg N. */
94 static char *reg_has_output_reload;
96 /* Indicates which hard regs are reload-registers for an output reload
97 in the current insn. */
98 static HARD_REG_SET reg_is_output_reload;
100 /* Element N is the constant value to which pseudo reg N is equivalent,
101 or zero if pseudo reg N is not equivalent to a constant.
102 find_reloads looks at this in order to replace pseudo reg N
103 with the constant it stands for. */
104 rtx *reg_equiv_constant;
106 /* Element N is a memory location to which pseudo reg N is equivalent,
107 prior to any register elimination (such as frame pointer to stack
108 pointer). Depending on whether or not it is a valid address, this value
109 is transferred to either reg_equiv_address or reg_equiv_mem. */
110 rtx *reg_equiv_memory_loc;
112 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
113 This is used when the address is not valid as a memory address
114 (because its displacement is too big for the machine.) */
115 rtx *reg_equiv_address;
117 /* Element N is the memory slot to which pseudo reg N is equivalent,
118 or zero if pseudo reg N is not equivalent to a memory slot. */
121 /* Widest width in which each pseudo reg is referred to (via subreg). */
122 static unsigned int *reg_max_ref_width;
124 /* Element N is the list of insns that initialized reg N from its equivalent
125 constant or memory slot. */
126 static rtx *reg_equiv_init;
128 /* Vector to remember old contents of reg_renumber before spilling. */
129 static short *reg_old_renumber;
131 /* During reload_as_needed, element N contains the last pseudo regno reloaded
132 into hard register N. If that pseudo reg occupied more than one register,
133 reg_reloaded_contents points to that pseudo for each spill register in
134 use; all of these must remain set for an inheritance to occur. */
135 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
137 /* During reload_as_needed, element N contains the insn for which
138 hard register N was last used. Its contents are significant only
139 when reg_reloaded_valid is set for this register. */
140 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
142 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
143 static HARD_REG_SET reg_reloaded_valid;
144 /* Indicate if the register was dead at the end of the reload.
145 This is only valid if reg_reloaded_contents is set and valid. */
146 static HARD_REG_SET reg_reloaded_dead;
148 /* Number of spill-regs so far; number of valid elements of spill_regs. */
151 /* In parallel with spill_regs, contains REG rtx's for those regs.
152 Holds the last rtx used for any given reg, or 0 if it has never
153 been used for spilling yet. This rtx is reused, provided it has
155 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
157 /* In parallel with spill_regs, contains nonzero for a spill reg
158 that was stored after the last time it was used.
159 The precise value is the insn generated to do the store. */
160 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
162 /* This is the register that was stored with spill_reg_store. This is a
163 copy of reload_out / reload_out_reg when the value was stored; if
164 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
165 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
167 /* This table is the inverse mapping of spill_regs:
168 indexed by hard reg number,
169 it contains the position of that reg in spill_regs,
170 or -1 for something that is not in spill_regs.
172 ?!? This is no longer accurate. */
173 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
175 /* This reg set indicates registers that can't be used as spill registers for
176 the currently processed insn. These are the hard registers which are live
177 during the insn, but not allocated to pseudos, as well as fixed
179 static HARD_REG_SET bad_spill_regs;
181 /* These are the hard registers that can't be used as spill register for any
182 insn. This includes registers used for user variables and registers that
183 we can't eliminate. A register that appears in this set also can't be used
184 to retry register allocation. */
185 static HARD_REG_SET bad_spill_regs_global;
187 /* Describes order of use of registers for reloading
188 of spilled pseudo-registers. `n_spills' is the number of
189 elements that are actually valid; new ones are added at the end.
191 Both spill_regs and spill_reg_order are used on two occasions:
192 once during find_reload_regs, where they keep track of the spill registers
193 for a single insn, but also during reload_as_needed where they show all
194 the registers ever used by reload. For the latter case, the information
195 is calculated during finish_spills. */
196 static short spill_regs[FIRST_PSEUDO_REGISTER];
198 /* This vector of reg sets indicates, for each pseudo, which hard registers
199 may not be used for retrying global allocation because the register was
200 formerly spilled from one of them. If we allowed reallocating a pseudo to
201 a register that it was already allocated to, reload might not
203 static HARD_REG_SET *pseudo_previous_regs;
205 /* This vector of reg sets indicates, for each pseudo, which hard
206 registers may not be used for retrying global allocation because they
207 are used as spill registers during one of the insns in which the
209 static HARD_REG_SET *pseudo_forbidden_regs;
211 /* All hard regs that have been used as spill registers for any insn are
212 marked in this set. */
213 static HARD_REG_SET used_spill_regs;
215 /* Index of last register assigned as a spill register. We allocate in
216 a round-robin fashion. */
217 static int last_spill_reg;
219 /* Nonzero if indirect addressing is supported on the machine; this means
220 that spilling (REG n) does not require reloading it into a register in
221 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
222 value indicates the level of indirect addressing supported, e.g., two
223 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
225 static char spill_indirect_levels;
227 /* Nonzero if indirect addressing is supported when the innermost MEM is
228 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
229 which these are valid is the same as spill_indirect_levels, above. */
230 char indirect_symref_ok;
232 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
233 char double_reg_address_ok;
235 /* Record the stack slot for each spilled hard register. */
236 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
238 /* Width allocated so far for that stack slot. */
239 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
241 /* Record which pseudos needed to be spilled. */
242 static regset_head spilled_pseudos;
244 /* Used for communication between order_regs_for_reload and count_pseudo.
245 Used to avoid counting one pseudo twice. */
246 static regset_head pseudos_counted;
248 /* First uid used by insns created by reload in this function.
249 Used in find_equiv_reg. */
250 int reload_first_uid;
252 /* Flag set by local-alloc or global-alloc if anything is live in
253 a call-clobbered reg across calls. */
254 int caller_save_needed;
256 /* Set to 1 while reload_as_needed is operating.
257 Required by some machines to handle any generated moves differently. */
258 int reload_in_progress = 0;
260 /* These arrays record the insn_code of insns that may be needed to
261 perform input and output reloads of special objects. They provide a
262 place to pass a scratch register. */
263 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
264 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
266 /* This obstack is used for allocation of rtl during register elimination.
267 The allocated storage can be freed once find_reloads has processed the
269 struct obstack reload_obstack;
271 /* Points to the beginning of the reload_obstack. All insn_chain structures
272 are allocated first. */
273 char *reload_startobj;
275 /* The point after all insn_chain structures. Used to quickly deallocate
276 memory allocated in copy_reloads during calculate_needs_all_insns. */
277 char *reload_firstobj;
279 /* This points before all local rtl generated by register elimination.
280 Used to quickly free all memory after processing one insn. */
281 static char *reload_insn_firstobj;
283 #define obstack_chunk_alloc xmalloc
284 #define obstack_chunk_free free
286 /* List of insn_chain instructions, one for every insn that reload needs to
288 struct insn_chain *reload_insn_chain;
291 extern tree current_function_decl;
293 extern union tree_node *current_function_decl;
296 /* List of all insns needing reloads. */
297 static struct insn_chain *insns_need_reload;
299 /* This structure is used to record information about register eliminations.
300 Each array entry describes one possible way of eliminating a register
301 in favor of another. If there is more than one way of eliminating a
302 particular register, the most preferred should be specified first. */
306 int from; /* Register number to be eliminated. */
307 int to; /* Register number used as replacement. */
308 int initial_offset; /* Initial difference between values. */
309 int can_eliminate; /* Non-zero if this elimination can be done. */
310 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
311 insns made by reload. */
312 int offset; /* Current offset between the two regs. */
313 int previous_offset; /* Offset at end of previous insn. */
314 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
315 rtx from_rtx; /* REG rtx for the register to be eliminated.
316 We cannot simply compare the number since
317 we might then spuriously replace a hard
318 register corresponding to a pseudo
319 assigned to the reg to be eliminated. */
320 rtx to_rtx; /* REG rtx for the replacement. */
323 static struct elim_table *reg_eliminate = 0;
325 /* This is an intermediate structure to initialize the table. It has
326 exactly the members provided by ELIMINABLE_REGS. */
327 static const struct elim_table_1
331 } reg_eliminate_1[] =
333 /* If a set of eliminable registers was specified, define the table from it.
334 Otherwise, default to the normal case of the frame pointer being
335 replaced by the stack pointer. */
337 #ifdef ELIMINABLE_REGS
340 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
343 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
345 /* Record the number of pending eliminations that have an offset not equal
346 to their initial offset. If non-zero, we use a new copy of each
347 replacement result in any insns encountered. */
348 int num_not_at_initial_offset;
350 /* Count the number of registers that we may be able to eliminate. */
351 static int num_eliminable;
352 /* And the number of registers that are equivalent to a constant that
353 can be eliminated to frame_pointer / arg_pointer + constant. */
354 static int num_eliminable_invariants;
356 /* For each label, we record the offset of each elimination. If we reach
357 a label by more than one path and an offset differs, we cannot do the
358 elimination. This information is indexed by the number of the label.
359 The first table is an array of flags that records whether we have yet
360 encountered a label and the second table is an array of arrays, one
361 entry in the latter array for each elimination. */
363 static char *offsets_known_at;
364 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
366 /* Number of labels in the current function. */
368 static int num_labels;
370 static void replace_pseudos_in_call_usage PARAMS ((rtx *,
373 static void maybe_fix_stack_asms PARAMS ((void));
374 static void copy_reloads PARAMS ((struct insn_chain *));
375 static void calculate_needs_all_insns PARAMS ((int));
376 static int find_reg PARAMS ((struct insn_chain *, int));
377 static void find_reload_regs PARAMS ((struct insn_chain *));
378 static void select_reload_regs PARAMS ((void));
379 static void delete_caller_save_insns PARAMS ((void));
381 static void spill_failure PARAMS ((rtx, enum reg_class));
382 static void count_spilled_pseudo PARAMS ((int, int, int));
383 static void delete_dead_insn PARAMS ((rtx));
384 static void alter_reg PARAMS ((int, int));
385 static void set_label_offsets PARAMS ((rtx, rtx, int));
386 static void check_eliminable_occurrences PARAMS ((rtx));
387 static void elimination_effects PARAMS ((rtx, enum machine_mode));
388 static int eliminate_regs_in_insn PARAMS ((rtx, int));
389 static void update_eliminable_offsets PARAMS ((void));
390 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
391 static void set_initial_elim_offsets PARAMS ((void));
392 static void verify_initial_elim_offsets PARAMS ((void));
393 static void set_initial_label_offsets PARAMS ((void));
394 static void set_offsets_for_label PARAMS ((rtx));
395 static void init_elim_table PARAMS ((void));
396 static void update_eliminables PARAMS ((HARD_REG_SET *));
397 static void spill_hard_reg PARAMS ((unsigned int, int));
398 static int finish_spills PARAMS ((int));
399 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
400 static void scan_paradoxical_subregs PARAMS ((rtx));
401 static void count_pseudo PARAMS ((int));
402 static void order_regs_for_reload PARAMS ((struct insn_chain *));
403 static void reload_as_needed PARAMS ((int));
404 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
405 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
406 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
409 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
412 static int reload_reg_free_p PARAMS ((unsigned int, int,
414 static int reload_reg_free_for_value_p PARAMS ((int, int, int,
416 rtx, rtx, int, int));
417 static int free_for_value_p PARAMS ((int, enum machine_mode, int,
418 enum reload_type, rtx, rtx,
420 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
422 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
424 static int conflicts_with_override PARAMS ((rtx));
425 static void failed_reload PARAMS ((rtx, int));
426 static int set_reload_reg PARAMS ((int, int));
427 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
428 static void choose_reload_regs PARAMS ((struct insn_chain *));
429 static void merge_assigned_reloads PARAMS ((rtx));
430 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
431 struct reload *, rtx, int));
432 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
433 struct reload *, int));
434 static void do_input_reload PARAMS ((struct insn_chain *,
435 struct reload *, int));
436 static void do_output_reload PARAMS ((struct insn_chain *,
437 struct reload *, int));
438 static void emit_reload_insns PARAMS ((struct insn_chain *));
439 static void delete_output_reload PARAMS ((rtx, int, int));
440 static void delete_address_reloads PARAMS ((rtx, rtx));
441 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
442 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
443 static int constraint_accepts_reg_p PARAMS ((const char *, rtx));
444 static void reload_cse_regs_1 PARAMS ((rtx));
445 static int reload_cse_noop_set_p PARAMS ((rtx));
446 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
447 static int reload_cse_simplify_operands PARAMS ((rtx));
448 static void reload_combine PARAMS ((void));
449 static void reload_combine_note_use PARAMS ((rtx *, rtx));
450 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
451 static void reload_cse_move2add PARAMS ((rtx));
452 static void move2add_note_store PARAMS ((rtx, rtx, void *));
454 static void add_auto_inc_notes PARAMS ((rtx, rtx));
456 static void copy_eh_notes PARAMS ((rtx, rtx));
457 static HOST_WIDE_INT sext_for_mode PARAMS ((enum machine_mode,
459 static void failed_reload PARAMS ((rtx, int));
460 static int set_reload_reg PARAMS ((int, int));
461 static void reload_cse_delete_noop_set PARAMS ((rtx, rtx));
462 static void reload_cse_simplify PARAMS ((rtx));
463 void fixup_abnormal_edges PARAMS ((void));
464 extern void dump_needs PARAMS ((struct insn_chain *));
466 /* Initialize the reload pass once per compilation. */
473 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
474 Set spill_indirect_levels to the number of levels such addressing is
475 permitted, zero if it is not permitted at all. */
478 = gen_rtx_MEM (Pmode,
481 LAST_VIRTUAL_REGISTER + 1),
483 spill_indirect_levels = 0;
485 while (memory_address_p (QImode, tem))
487 spill_indirect_levels++;
488 tem = gen_rtx_MEM (Pmode, tem);
491 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
493 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
494 indirect_symref_ok = memory_address_p (QImode, tem);
496 /* See if reg+reg is a valid (and offsettable) address. */
498 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
500 tem = gen_rtx_PLUS (Pmode,
501 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
502 gen_rtx_REG (Pmode, i));
504 /* This way, we make sure that reg+reg is an offsettable address. */
505 tem = plus_constant (tem, 4);
507 if (memory_address_p (QImode, tem))
509 double_reg_address_ok = 1;
514 /* Initialize obstack for our rtl allocation. */
515 gcc_obstack_init (&reload_obstack);
516 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
518 INIT_REG_SET (&spilled_pseudos);
519 INIT_REG_SET (&pseudos_counted);
522 /* List of insn chains that are currently unused. */
523 static struct insn_chain *unused_insn_chains = 0;
525 /* Allocate an empty insn_chain structure. */
529 struct insn_chain *c;
531 if (unused_insn_chains == 0)
533 c = (struct insn_chain *)
534 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
535 INIT_REG_SET (&c->live_throughout);
536 INIT_REG_SET (&c->dead_or_set);
540 c = unused_insn_chains;
541 unused_insn_chains = c->next;
543 c->is_caller_save_insn = 0;
544 c->need_operand_change = 0;
550 /* Small utility function to set all regs in hard reg set TO which are
551 allocated to pseudos in regset FROM. */
554 compute_use_by_pseudos (to, from)
560 EXECUTE_IF_SET_IN_REG_SET
561 (from, FIRST_PSEUDO_REGISTER, regno,
563 int r = reg_renumber[regno];
568 /* reload_combine uses the information from
569 BASIC_BLOCK->global_live_at_start, which might still
570 contain registers that have not actually been allocated
571 since they have an equivalence. */
572 if (! reload_completed)
577 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
579 SET_HARD_REG_BIT (*to, r + nregs);
584 /* Replace all pseudos found in LOC with their corresponding
588 replace_pseudos_in_call_usage (loc, mem_mode, usage)
590 enum machine_mode mem_mode;
604 unsigned int regno = REGNO (x);
606 if (regno < FIRST_PSEUDO_REGISTER)
609 x = eliminate_regs (x, mem_mode, usage);
613 replace_pseudos_in_call_usage (loc, mem_mode, usage);
617 if (reg_equiv_constant[regno])
618 *loc = reg_equiv_constant[regno];
619 else if (reg_equiv_mem[regno])
620 *loc = reg_equiv_mem[regno];
621 else if (reg_equiv_address[regno])
622 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
623 else if (GET_CODE (regno_reg_rtx[regno]) != REG
624 || REGNO (regno_reg_rtx[regno]) != regno)
625 *loc = regno_reg_rtx[regno];
631 else if (code == MEM)
633 replace_pseudos_in_call_usage (& XEXP (x, 0), GET_MODE (x), usage);
637 /* Process each of our operands recursively. */
638 fmt = GET_RTX_FORMAT (code);
639 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
641 replace_pseudos_in_call_usage (&XEXP (x, i), mem_mode, usage);
642 else if (*fmt == 'E')
643 for (j = 0; j < XVECLEN (x, i); j++)
644 replace_pseudos_in_call_usage (& XVECEXP (x, i, j), mem_mode, usage);
648 /* Global variables used by reload and its subroutines. */
650 /* Set during calculate_needs if an insn needs register elimination. */
651 static int something_needs_elimination;
652 /* Set during calculate_needs if an insn needs an operand changed. */
653 int something_needs_operands_changed;
655 /* Nonzero means we couldn't get enough spill regs. */
658 /* Main entry point for the reload pass.
660 FIRST is the first insn of the function being compiled.
662 GLOBAL nonzero means we were called from global_alloc
663 and should attempt to reallocate any pseudoregs that we
664 displace from hard regs we will use for reloads.
665 If GLOBAL is zero, we do not have enough information to do that,
666 so any pseudo reg that is spilled must go to the stack.
668 Return value is nonzero if reload failed
669 and we must not do any more for this function. */
672 reload (first, global)
678 struct elim_table *ep;
680 /* The two pointers used to track the true location of the memory used
681 for label offsets. */
682 char *real_known_ptr = NULL;
683 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
685 /* Make sure even insns with volatile mem refs are recognizable. */
690 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
692 /* Make sure that the last insn in the chain
693 is not something that needs reloading. */
694 emit_note (NULL, NOTE_INSN_DELETED);
696 /* Enable find_equiv_reg to distinguish insns made by reload. */
697 reload_first_uid = get_max_uid ();
699 #ifdef SECONDARY_MEMORY_NEEDED
700 /* Initialize the secondary memory table. */
701 clear_secondary_mem ();
704 /* We don't have a stack slot for any spill reg yet. */
705 memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot);
706 memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
708 /* Initialize the save area information for caller-save, in case some
712 /* Compute which hard registers are now in use
713 as homes for pseudo registers.
714 This is done here rather than (eg) in global_alloc
715 because this point is reached even if not optimizing. */
716 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
719 /* A function that receives a nonlocal goto must save all call-saved
721 if (current_function_has_nonlocal_label)
722 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
723 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
724 regs_ever_live[i] = 1;
726 /* Find all the pseudo registers that didn't get hard regs
727 but do have known equivalent constants or memory slots.
728 These include parameters (known equivalent to parameter slots)
729 and cse'd or loop-moved constant memory addresses.
731 Record constant equivalents in reg_equiv_constant
732 so they will be substituted by find_reloads.
733 Record memory equivalents in reg_mem_equiv so they can
734 be substituted eventually by altering the REG-rtx's. */
736 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
737 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
738 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
739 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
740 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
741 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
742 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
743 pseudo_forbidden_regs
744 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
746 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
748 CLEAR_HARD_REG_SET (bad_spill_regs_global);
750 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
751 Also find all paradoxical subregs and find largest such for each pseudo.
752 On machines with small register classes, record hard registers that
753 are used for user variables. These can never be used for spills.
754 Also look for a "constant" REG_SETJMP. This means that all
755 caller-saved registers must be marked live. */
757 num_eliminable_invariants = 0;
758 for (insn = first; insn; insn = NEXT_INSN (insn))
760 rtx set = single_set (insn);
762 /* We may introduce USEs that we want to remove at the end, so
763 we'll mark them with QImode. Make sure there are no
764 previously-marked insns left by say regmove. */
765 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
766 && GET_MODE (insn) != VOIDmode)
767 PUT_MODE (insn, VOIDmode);
769 if (GET_CODE (insn) == CALL_INSN
770 && find_reg_note (insn, REG_SETJMP, NULL))
771 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
772 if (! call_used_regs[i])
773 regs_ever_live[i] = 1;
775 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
777 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
779 #ifdef LEGITIMATE_PIC_OPERAND_P
780 && (! function_invariant_p (XEXP (note, 0))
782 /* A function invariant is often CONSTANT_P but may
783 include a register. We promise to only pass
784 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
785 || (CONSTANT_P (XEXP (note, 0))
786 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))))
790 rtx x = XEXP (note, 0);
791 i = REGNO (SET_DEST (set));
792 if (i > LAST_VIRTUAL_REGISTER)
794 /* It can happen that a REG_EQUIV note contains a MEM
795 that is not a legitimate memory operand. As later
796 stages of reload assume that all addresses found
797 in the reg_equiv_* arrays were originally legitimate,
798 we ignore such REG_EQUIV notes. */
799 if (memory_operand (x, VOIDmode))
801 /* Always unshare the equivalence, so we can
802 substitute into this insn without touching the
804 reg_equiv_memory_loc[i] = copy_rtx (x);
806 else if (function_invariant_p (x))
808 if (GET_CODE (x) == PLUS)
810 /* This is PLUS of frame pointer and a constant,
811 and might be shared. Unshare it. */
812 reg_equiv_constant[i] = copy_rtx (x);
813 num_eliminable_invariants++;
815 else if (x == frame_pointer_rtx
816 || x == arg_pointer_rtx)
818 reg_equiv_constant[i] = x;
819 num_eliminable_invariants++;
821 else if (LEGITIMATE_CONSTANT_P (x))
822 reg_equiv_constant[i] = x;
824 reg_equiv_memory_loc[i]
825 = force_const_mem (GET_MODE (SET_DEST (set)), x);
830 /* If this register is being made equivalent to a MEM
831 and the MEM is not SET_SRC, the equivalencing insn
832 is one with the MEM as a SET_DEST and it occurs later.
833 So don't mark this insn now. */
834 if (GET_CODE (x) != MEM
835 || rtx_equal_p (SET_SRC (set), x))
837 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
842 /* If this insn is setting a MEM from a register equivalent to it,
843 this is the equivalencing insn. */
844 else if (set && GET_CODE (SET_DEST (set)) == MEM
845 && GET_CODE (SET_SRC (set)) == REG
846 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
847 && rtx_equal_p (SET_DEST (set),
848 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
849 reg_equiv_init[REGNO (SET_SRC (set))]
850 = gen_rtx_INSN_LIST (VOIDmode, insn,
851 reg_equiv_init[REGNO (SET_SRC (set))]);
854 scan_paradoxical_subregs (PATTERN (insn));
859 num_labels = max_label_num () - get_first_label_num ();
861 /* Allocate the tables used to store offset information at labels. */
862 /* We used to use alloca here, but the size of what it would try to
863 allocate would occasionally cause it to exceed the stack limit and
864 cause a core dump. */
865 real_known_ptr = xmalloc (num_labels);
867 = (int (*)[NUM_ELIMINABLE_REGS])
868 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
870 offsets_known_at = real_known_ptr - get_first_label_num ();
872 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
874 /* Alter each pseudo-reg rtx to contain its hard reg number.
875 Assign stack slots to the pseudos that lack hard regs or equivalents.
876 Do not touch virtual registers. */
878 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
881 /* If we have some registers we think can be eliminated, scan all insns to
882 see if there is an insn that sets one of these registers to something
883 other than itself plus a constant. If so, the register cannot be
884 eliminated. Doing this scan here eliminates an extra pass through the
885 main reload loop in the most common case where register elimination
887 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
888 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
889 || GET_CODE (insn) == CALL_INSN)
890 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
892 maybe_fix_stack_asms ();
894 insns_need_reload = 0;
895 something_needs_elimination = 0;
897 /* Initialize to -1, which means take the first spill register. */
900 /* Spill any hard regs that we know we can't eliminate. */
901 CLEAR_HARD_REG_SET (used_spill_regs);
902 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
903 if (! ep->can_eliminate)
904 spill_hard_reg (ep->from, 1);
906 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
907 if (frame_pointer_needed)
908 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
910 finish_spills (global);
912 /* From now on, we may need to generate moves differently. We may also
913 allow modifications of insns which cause them to not be recognized.
914 Any such modifications will be cleaned up during reload itself. */
915 reload_in_progress = 1;
917 /* This loop scans the entire function each go-round
918 and repeats until one repetition spills no additional hard regs. */
921 int something_changed;
924 HOST_WIDE_INT starting_frame_size;
926 /* Round size of stack frame to stack_alignment_needed. This must be done
927 here because the stack size may be a part of the offset computation
928 for register elimination, and there might have been new stack slots
929 created in the last iteration of this loop. */
930 if (cfun->stack_alignment_needed)
931 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
933 starting_frame_size = get_frame_size ();
935 set_initial_elim_offsets ();
936 set_initial_label_offsets ();
938 /* For each pseudo register that has an equivalent location defined,
939 try to eliminate any eliminable registers (such as the frame pointer)
940 assuming initial offsets for the replacement register, which
943 If the resulting location is directly addressable, substitute
944 the MEM we just got directly for the old REG.
946 If it is not addressable but is a constant or the sum of a hard reg
947 and constant, it is probably not addressable because the constant is
948 out of range, in that case record the address; we will generate
949 hairy code to compute the address in a register each time it is
950 needed. Similarly if it is a hard register, but one that is not
951 valid as an address register.
953 If the location is not addressable, but does not have one of the
954 above forms, assign a stack slot. We have to do this to avoid the
955 potential of producing lots of reloads if, e.g., a location involves
956 a pseudo that didn't get a hard register and has an equivalent memory
957 location that also involves a pseudo that didn't get a hard register.
959 Perhaps at some point we will improve reload_when_needed handling
960 so this problem goes away. But that's very hairy. */
962 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
963 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
965 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
967 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
969 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
970 else if (CONSTANT_P (XEXP (x, 0))
971 || (GET_CODE (XEXP (x, 0)) == REG
972 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
973 || (GET_CODE (XEXP (x, 0)) == PLUS
974 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
975 && (REGNO (XEXP (XEXP (x, 0), 0))
976 < FIRST_PSEUDO_REGISTER)
977 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
978 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
981 /* Make a new stack slot. Then indicate that something
982 changed so we go back and recompute offsets for
983 eliminable registers because the allocation of memory
984 below might change some offset. reg_equiv_{mem,address}
985 will be set up for this pseudo on the next pass around
987 reg_equiv_memory_loc[i] = 0;
988 reg_equiv_init[i] = 0;
993 if (caller_save_needed)
996 /* If we allocated another stack slot, redo elimination bookkeeping. */
997 if (starting_frame_size != get_frame_size ())
1000 if (caller_save_needed)
1002 save_call_clobbered_regs ();
1003 /* That might have allocated new insn_chain structures. */
1004 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1007 calculate_needs_all_insns (global);
1009 CLEAR_REG_SET (&spilled_pseudos);
1012 something_changed = 0;
1014 /* If we allocated any new memory locations, make another pass
1015 since it might have changed elimination offsets. */
1016 if (starting_frame_size != get_frame_size ())
1017 something_changed = 1;
1020 HARD_REG_SET to_spill;
1021 CLEAR_HARD_REG_SET (to_spill);
1022 update_eliminables (&to_spill);
1023 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1024 if (TEST_HARD_REG_BIT (to_spill, i))
1026 spill_hard_reg (i, 1);
1029 /* Regardless of the state of spills, if we previously had
1030 a register that we thought we could eliminate, but no can
1031 not eliminate, we must run another pass.
1033 Consider pseudos which have an entry in reg_equiv_* which
1034 reference an eliminable register. We must make another pass
1035 to update reg_equiv_* so that we do not substitute in the
1036 old value from when we thought the elimination could be
1038 something_changed = 1;
1042 select_reload_regs ();
1046 if (insns_need_reload != 0 || did_spill)
1047 something_changed |= finish_spills (global);
1049 if (! something_changed)
1052 if (caller_save_needed)
1053 delete_caller_save_insns ();
1055 obstack_free (&reload_obstack, reload_firstobj);
1058 /* If global-alloc was run, notify it of any register eliminations we have
1061 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1062 if (ep->can_eliminate)
1063 mark_elimination (ep->from, ep->to);
1065 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1066 If that insn didn't set the register (i.e., it copied the register to
1067 memory), just delete that insn instead of the equivalencing insn plus
1068 anything now dead. If we call delete_dead_insn on that insn, we may
1069 delete the insn that actually sets the register if the register dies
1070 there and that is incorrect. */
1072 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1074 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1077 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1079 rtx equiv_insn = XEXP (list, 0);
1081 /* If we already deleted the insn or if it may trap, we can't
1082 delete it. The latter case shouldn't happen, but can
1083 if an insn has a variable address, gets a REG_EH_REGION
1084 note added to it, and then gets converted into an load
1085 from a constant address. */
1086 if (GET_CODE (equiv_insn) == NOTE
1087 || can_throw_internal (equiv_insn))
1089 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1090 delete_dead_insn (equiv_insn);
1093 PUT_CODE (equiv_insn, NOTE);
1094 NOTE_SOURCE_FILE (equiv_insn) = 0;
1095 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1101 /* Use the reload registers where necessary
1102 by generating move instructions to move the must-be-register
1103 values into or out of the reload registers. */
1105 if (insns_need_reload != 0 || something_needs_elimination
1106 || something_needs_operands_changed)
1108 HOST_WIDE_INT old_frame_size = get_frame_size ();
1110 reload_as_needed (global);
1112 if (old_frame_size != get_frame_size ())
1116 verify_initial_elim_offsets ();
1119 /* If we were able to eliminate the frame pointer, show that it is no
1120 longer live at the start of any basic block. If it ls live by
1121 virtue of being in a pseudo, that pseudo will be marked live
1122 and hence the frame pointer will be known to be live via that
1125 if (! frame_pointer_needed)
1126 for (i = 0; i < n_basic_blocks; i++)
1127 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1128 HARD_FRAME_POINTER_REGNUM);
1130 /* Come here (with failure set nonzero) if we can't get enough spill regs
1131 and we decide not to abort about it. */
1134 CLEAR_REG_SET (&spilled_pseudos);
1135 reload_in_progress = 0;
1137 /* Now eliminate all pseudo regs by modifying them into
1138 their equivalent memory references.
1139 The REG-rtx's for the pseudos are modified in place,
1140 so all insns that used to refer to them now refer to memory.
1142 For a reg that has a reg_equiv_address, all those insns
1143 were changed by reloading so that no insns refer to it any longer;
1144 but the DECL_RTL of a variable decl may refer to it,
1145 and if so this causes the debugging info to mention the variable. */
1147 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1151 if (reg_equiv_mem[i])
1152 addr = XEXP (reg_equiv_mem[i], 0);
1154 if (reg_equiv_address[i])
1155 addr = reg_equiv_address[i];
1159 if (reg_renumber[i] < 0)
1161 rtx reg = regno_reg_rtx[i];
1163 PUT_CODE (reg, MEM);
1164 XEXP (reg, 0) = addr;
1165 REG_USERVAR_P (reg) = 0;
1166 if (reg_equiv_memory_loc[i])
1167 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1170 RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg)
1171 = MEM_SCALAR_P (reg) = 0;
1172 MEM_ATTRS (reg) = 0;
1175 else if (reg_equiv_mem[i])
1176 XEXP (reg_equiv_mem[i], 0) = addr;
1180 /* We must set reload_completed now since the cleanup_subreg_operands call
1181 below will re-recognize each insn and reload may have generated insns
1182 which are only valid during and after reload. */
1183 reload_completed = 1;
1185 /* Make a pass over all the insns and delete all USEs which we inserted
1186 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1187 notes. Delete all CLOBBER insns that don't refer to the return value
1188 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1189 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1190 and regenerate REG_INC notes that may have been moved around. */
1192 for (insn = first; insn; insn = NEXT_INSN (insn))
1197 if (GET_CODE (insn) == CALL_INSN)
1198 replace_pseudos_in_call_usage (& CALL_INSN_FUNCTION_USAGE (insn),
1200 CALL_INSN_FUNCTION_USAGE (insn));
1202 if ((GET_CODE (PATTERN (insn)) == USE
1203 /* We mark with QImode USEs introduced by reload itself. */
1204 && (GET_MODE (insn) == QImode
1205 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1206 || (GET_CODE (PATTERN (insn)) == CLOBBER
1207 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1208 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1214 pnote = ®_NOTES (insn);
1217 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1218 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1219 || REG_NOTE_KIND (*pnote) == REG_INC
1220 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1221 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1222 *pnote = XEXP (*pnote, 1);
1224 pnote = &XEXP (*pnote, 1);
1228 add_auto_inc_notes (insn, PATTERN (insn));
1231 /* And simplify (subreg (reg)) if it appears as an operand. */
1232 cleanup_subreg_operands (insn);
1235 /* If we are doing stack checking, give a warning if this function's
1236 frame size is larger than we expect. */
1237 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1239 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1240 static int verbose_warned = 0;
1242 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1243 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1244 size += UNITS_PER_WORD;
1246 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1248 warning ("frame size too large for reliable stack checking");
1249 if (! verbose_warned)
1251 warning ("try reducing the number of local variables");
1257 /* Indicate that we no longer have known memory locations or constants. */
1258 if (reg_equiv_constant)
1259 free (reg_equiv_constant);
1260 reg_equiv_constant = 0;
1261 if (reg_equiv_memory_loc)
1262 free (reg_equiv_memory_loc);
1263 reg_equiv_memory_loc = 0;
1266 free (real_known_ptr);
1270 free (reg_equiv_mem);
1271 free (reg_equiv_init);
1272 free (reg_equiv_address);
1273 free (reg_max_ref_width);
1274 free (reg_old_renumber);
1275 free (pseudo_previous_regs);
1276 free (pseudo_forbidden_regs);
1278 CLEAR_HARD_REG_SET (used_spill_regs);
1279 for (i = 0; i < n_spills; i++)
1280 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1282 /* Free all the insn_chain structures at once. */
1283 obstack_free (&reload_obstack, reload_startobj);
1284 unused_insn_chains = 0;
1285 fixup_abnormal_edges ();
1287 /* Replacing pseudos with their memory equivalents might have
1288 created shared rtx. Subsequent passes would get confused
1289 by this, so unshare everything here. */
1290 unshare_all_rtl_again (first);
1295 /* Yet another special case. Unfortunately, reg-stack forces people to
1296 write incorrect clobbers in asm statements. These clobbers must not
1297 cause the register to appear in bad_spill_regs, otherwise we'll call
1298 fatal_insn later. We clear the corresponding regnos in the live
1299 register sets to avoid this.
1300 The whole thing is rather sick, I'm afraid. */
1303 maybe_fix_stack_asms ()
1306 const char *constraints[MAX_RECOG_OPERANDS];
1307 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1308 struct insn_chain *chain;
1310 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1313 HARD_REG_SET clobbered, allowed;
1316 if (! INSN_P (chain->insn)
1317 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1319 pat = PATTERN (chain->insn);
1320 if (GET_CODE (pat) != PARALLEL)
1323 CLEAR_HARD_REG_SET (clobbered);
1324 CLEAR_HARD_REG_SET (allowed);
1326 /* First, make a mask of all stack regs that are clobbered. */
1327 for (i = 0; i < XVECLEN (pat, 0); i++)
1329 rtx t = XVECEXP (pat, 0, i);
1330 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1331 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1334 /* Get the operand values and constraints out of the insn. */
1335 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1336 constraints, operand_mode);
1338 /* For every operand, see what registers are allowed. */
1339 for (i = 0; i < noperands; i++)
1341 const char *p = constraints[i];
1342 /* For every alternative, we compute the class of registers allowed
1343 for reloading in CLS, and merge its contents into the reg set
1345 int cls = (int) NO_REGS;
1351 if (c == '\0' || c == ',' || c == '#')
1353 /* End of one alternative - mark the regs in the current
1354 class, and reset the class. */
1355 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1360 } while (c != '\0' && c != ',');
1368 case '=': case '+': case '*': case '%': case '?': case '!':
1369 case '0': case '1': case '2': case '3': case '4': case 'm':
1370 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1371 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1372 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1377 cls = (int) reg_class_subunion[cls]
1378 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1383 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1387 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1392 /* Those of the registers which are clobbered, but allowed by the
1393 constraints, must be usable as reload registers. So clear them
1394 out of the life information. */
1395 AND_HARD_REG_SET (allowed, clobbered);
1396 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1397 if (TEST_HARD_REG_BIT (allowed, i))
1399 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1400 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1407 /* Copy the global variables n_reloads and rld into the corresponding elts
1410 copy_reloads (chain)
1411 struct insn_chain *chain;
1413 chain->n_reloads = n_reloads;
1415 = (struct reload *) obstack_alloc (&reload_obstack,
1416 n_reloads * sizeof (struct reload));
1417 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1418 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1421 /* Walk the chain of insns, and determine for each whether it needs reloads
1422 and/or eliminations. Build the corresponding insns_need_reload list, and
1423 set something_needs_elimination as appropriate. */
1425 calculate_needs_all_insns (global)
1428 struct insn_chain **pprev_reload = &insns_need_reload;
1429 struct insn_chain *chain, *next = 0;
1431 something_needs_elimination = 0;
1433 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1434 for (chain = reload_insn_chain; chain != 0; chain = next)
1436 rtx insn = chain->insn;
1440 /* Clear out the shortcuts. */
1441 chain->n_reloads = 0;
1442 chain->need_elim = 0;
1443 chain->need_reload = 0;
1444 chain->need_operand_change = 0;
1446 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1447 include REG_LABEL), we need to see what effects this has on the
1448 known offsets at labels. */
1450 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1451 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1452 set_label_offsets (insn, insn, 0);
1456 rtx old_body = PATTERN (insn);
1457 int old_code = INSN_CODE (insn);
1458 rtx old_notes = REG_NOTES (insn);
1459 int did_elimination = 0;
1460 int operands_changed = 0;
1461 rtx set = single_set (insn);
1463 /* Skip insns that only set an equivalence. */
1464 if (set && GET_CODE (SET_DEST (set)) == REG
1465 && reg_renumber[REGNO (SET_DEST (set))] < 0
1466 && reg_equiv_constant[REGNO (SET_DEST (set))])
1469 /* If needed, eliminate any eliminable registers. */
1470 if (num_eliminable || num_eliminable_invariants)
1471 did_elimination = eliminate_regs_in_insn (insn, 0);
1473 /* Analyze the instruction. */
1474 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1475 global, spill_reg_order);
1477 /* If a no-op set needs more than one reload, this is likely
1478 to be something that needs input address reloads. We
1479 can't get rid of this cleanly later, and it is of no use
1480 anyway, so discard it now.
1481 We only do this when expensive_optimizations is enabled,
1482 since this complements reload inheritance / output
1483 reload deletion, and it can make debugging harder. */
1484 if (flag_expensive_optimizations && n_reloads > 1)
1486 rtx set = single_set (insn);
1488 && SET_SRC (set) == SET_DEST (set)
1489 && GET_CODE (SET_SRC (set)) == REG
1490 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1493 /* Delete it from the reload chain */
1495 chain->prev->next = next;
1497 reload_insn_chain = next;
1499 next->prev = chain->prev;
1500 chain->next = unused_insn_chains;
1501 unused_insn_chains = chain;
1506 update_eliminable_offsets ();
1508 /* Remember for later shortcuts which insns had any reloads or
1509 register eliminations. */
1510 chain->need_elim = did_elimination;
1511 chain->need_reload = n_reloads > 0;
1512 chain->need_operand_change = operands_changed;
1514 /* Discard any register replacements done. */
1515 if (did_elimination)
1517 obstack_free (&reload_obstack, reload_insn_firstobj);
1518 PATTERN (insn) = old_body;
1519 INSN_CODE (insn) = old_code;
1520 REG_NOTES (insn) = old_notes;
1521 something_needs_elimination = 1;
1524 something_needs_operands_changed |= operands_changed;
1528 copy_reloads (chain);
1529 *pprev_reload = chain;
1530 pprev_reload = &chain->next_need_reload;
1537 /* Comparison function for qsort to decide which of two reloads
1538 should be handled first. *P1 and *P2 are the reload numbers. */
1541 reload_reg_class_lower (r1p, r2p)
1545 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1548 /* Consider required reloads before optional ones. */
1549 t = rld[r1].optional - rld[r2].optional;
1553 /* Count all solitary classes before non-solitary ones. */
1554 t = ((reg_class_size[(int) rld[r2].class] == 1)
1555 - (reg_class_size[(int) rld[r1].class] == 1));
1559 /* Aside from solitaires, consider all multi-reg groups first. */
1560 t = rld[r2].nregs - rld[r1].nregs;
1564 /* Consider reloads in order of increasing reg-class number. */
1565 t = (int) rld[r1].class - (int) rld[r2].class;
1569 /* If reloads are equally urgent, sort by reload number,
1570 so that the results of qsort leave nothing to chance. */
1574 /* The cost of spilling each hard reg. */
1575 static int spill_cost[FIRST_PSEUDO_REGISTER];
1577 /* When spilling multiple hard registers, we use SPILL_COST for the first
1578 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1579 only the first hard reg for a multi-reg pseudo. */
1580 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1582 /* Update the spill cost arrays, considering that pseudo REG is live. */
1588 int freq = REG_FREQ (reg);
1589 int r = reg_renumber[reg];
1592 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1593 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1596 SET_REGNO_REG_SET (&pseudos_counted, reg);
1601 spill_add_cost[r] += freq;
1603 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1605 spill_cost[r + nregs] += freq;
1608 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1609 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1612 order_regs_for_reload (chain)
1613 struct insn_chain *chain;
1616 HARD_REG_SET used_by_pseudos;
1617 HARD_REG_SET used_by_pseudos2;
1619 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1621 memset (spill_cost, 0, sizeof spill_cost);
1622 memset (spill_add_cost, 0, sizeof spill_add_cost);
1624 /* Count number of uses of each hard reg by pseudo regs allocated to it
1625 and then order them by decreasing use. First exclude hard registers
1626 that are live in or across this insn. */
1628 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1629 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1630 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1631 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1633 /* Now find out which pseudos are allocated to it, and update
1635 CLEAR_REG_SET (&pseudos_counted);
1637 EXECUTE_IF_SET_IN_REG_SET
1638 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1642 EXECUTE_IF_SET_IN_REG_SET
1643 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1647 CLEAR_REG_SET (&pseudos_counted);
1650 /* Vector of reload-numbers showing the order in which the reloads should
1652 static short reload_order[MAX_RELOADS];
1654 /* This is used to keep track of the spill regs used in one insn. */
1655 static HARD_REG_SET used_spill_regs_local;
1657 /* We decided to spill hard register SPILLED, which has a size of
1658 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1659 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1660 update SPILL_COST/SPILL_ADD_COST. */
1663 count_spilled_pseudo (spilled, spilled_nregs, reg)
1664 int spilled, spilled_nregs, reg;
1666 int r = reg_renumber[reg];
1667 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1669 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1670 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1673 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1675 spill_add_cost[r] -= REG_FREQ (reg);
1677 spill_cost[r + nregs] -= REG_FREQ (reg);
1680 /* Find reload register to use for reload number ORDER. */
1683 find_reg (chain, order)
1684 struct insn_chain *chain;
1687 int rnum = reload_order[order];
1688 struct reload *rl = rld + rnum;
1689 int best_cost = INT_MAX;
1693 HARD_REG_SET not_usable;
1694 HARD_REG_SET used_by_other_reload;
1696 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1697 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1698 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1700 CLEAR_HARD_REG_SET (used_by_other_reload);
1701 for (k = 0; k < order; k++)
1703 int other = reload_order[k];
1705 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1706 for (j = 0; j < rld[other].nregs; j++)
1707 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1710 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1712 unsigned int regno = i;
1714 if (! TEST_HARD_REG_BIT (not_usable, regno)
1715 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1716 && HARD_REGNO_MODE_OK (regno, rl->mode))
1718 int this_cost = spill_cost[regno];
1720 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1722 for (j = 1; j < this_nregs; j++)
1724 this_cost += spill_add_cost[regno + j];
1725 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1726 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1731 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1733 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1735 if (this_cost < best_cost
1736 /* Among registers with equal cost, prefer caller-saved ones, or
1737 use REG_ALLOC_ORDER if it is defined. */
1738 || (this_cost == best_cost
1739 #ifdef REG_ALLOC_ORDER
1740 && (inv_reg_alloc_order[regno]
1741 < inv_reg_alloc_order[best_reg])
1743 && call_used_regs[regno]
1744 && ! call_used_regs[best_reg]
1749 best_cost = this_cost;
1757 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1759 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1760 rl->regno = best_reg;
1762 EXECUTE_IF_SET_IN_REG_SET
1763 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1765 count_spilled_pseudo (best_reg, rl->nregs, j);
1768 EXECUTE_IF_SET_IN_REG_SET
1769 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1771 count_spilled_pseudo (best_reg, rl->nregs, j);
1774 for (i = 0; i < rl->nregs; i++)
1776 if (spill_cost[best_reg + i] != 0
1777 || spill_add_cost[best_reg + i] != 0)
1779 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1784 /* Find more reload regs to satisfy the remaining need of an insn, which
1786 Do it by ascending class number, since otherwise a reg
1787 might be spilled for a big class and might fail to count
1788 for a smaller class even though it belongs to that class. */
1791 find_reload_regs (chain)
1792 struct insn_chain *chain;
1796 /* In order to be certain of getting the registers we need,
1797 we must sort the reloads into order of increasing register class.
1798 Then our grabbing of reload registers will parallel the process
1799 that provided the reload registers. */
1800 for (i = 0; i < chain->n_reloads; i++)
1802 /* Show whether this reload already has a hard reg. */
1803 if (chain->rld[i].reg_rtx)
1805 int regno = REGNO (chain->rld[i].reg_rtx);
1806 chain->rld[i].regno = regno;
1808 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1811 chain->rld[i].regno = -1;
1812 reload_order[i] = i;
1815 n_reloads = chain->n_reloads;
1816 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1818 CLEAR_HARD_REG_SET (used_spill_regs_local);
1821 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1823 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1825 /* Compute the order of preference for hard registers to spill. */
1827 order_regs_for_reload (chain);
1829 for (i = 0; i < n_reloads; i++)
1831 int r = reload_order[i];
1833 /* Ignore reloads that got marked inoperative. */
1834 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1835 && ! rld[r].optional
1836 && rld[r].regno == -1)
1837 if (! find_reg (chain, i))
1839 spill_failure (chain->insn, rld[r].class);
1845 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1846 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1848 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1852 select_reload_regs ()
1854 struct insn_chain *chain;
1856 /* Try to satisfy the needs for each insn. */
1857 for (chain = insns_need_reload; chain != 0;
1858 chain = chain->next_need_reload)
1859 find_reload_regs (chain);
1862 /* Delete all insns that were inserted by emit_caller_save_insns during
1865 delete_caller_save_insns ()
1867 struct insn_chain *c = reload_insn_chain;
1871 while (c != 0 && c->is_caller_save_insn)
1873 struct insn_chain *next = c->next;
1876 if (c == reload_insn_chain)
1877 reload_insn_chain = next;
1881 next->prev = c->prev;
1883 c->prev->next = next;
1884 c->next = unused_insn_chains;
1885 unused_insn_chains = c;
1893 /* Handle the failure to find a register to spill.
1894 INSN should be one of the insns which needed this particular spill reg. */
1897 spill_failure (insn, class)
1899 enum reg_class class;
1901 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1902 if (asm_noperands (PATTERN (insn)) >= 0)
1903 error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'",
1904 reg_class_names[class]);
1907 error ("unable to find a register to spill in class `%s'",
1908 reg_class_names[class]);
1909 fatal_insn ("this is the insn:", insn);
1913 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1914 data that is dead in INSN. */
1917 delete_dead_insn (insn)
1920 rtx prev = prev_real_insn (insn);
1923 /* If the previous insn sets a register that dies in our insn, delete it
1925 if (prev && GET_CODE (PATTERN (prev)) == SET
1926 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1927 && reg_mentioned_p (prev_dest, PATTERN (insn))
1928 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1929 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1930 delete_dead_insn (prev);
1932 PUT_CODE (insn, NOTE);
1933 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1934 NOTE_SOURCE_FILE (insn) = 0;
1937 /* Modify the home of pseudo-reg I.
1938 The new home is present in reg_renumber[I].
1940 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1941 or it may be -1, meaning there is none or it is not relevant.
1942 This is used so that all pseudos spilled from a given hard reg
1943 can share one stack slot. */
1946 alter_reg (i, from_reg)
1950 /* When outputting an inline function, this can happen
1951 for a reg that isn't actually used. */
1952 if (regno_reg_rtx[i] == 0)
1955 /* If the reg got changed to a MEM at rtl-generation time,
1957 if (GET_CODE (regno_reg_rtx[i]) != REG)
1960 /* Modify the reg-rtx to contain the new hard reg
1961 number or else to contain its pseudo reg number. */
1962 REGNO (regno_reg_rtx[i])
1963 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1965 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1966 allocate a stack slot for it. */
1968 if (reg_renumber[i] < 0
1969 && REG_N_REFS (i) > 0
1970 && reg_equiv_constant[i] == 0
1971 && reg_equiv_memory_loc[i] == 0)
1974 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1975 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1978 /* Each pseudo reg has an inherent size which comes from its own mode,
1979 and a total size which provides room for paradoxical subregs
1980 which refer to the pseudo reg in wider modes.
1982 We can use a slot already allocated if it provides both
1983 enough inherent space and enough total space.
1984 Otherwise, we allocate a new slot, making sure that it has no less
1985 inherent space, and no less total space, then the previous slot. */
1988 /* No known place to spill from => no slot to reuse. */
1989 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1990 inherent_size == total_size ? 0 : -1);
1991 if (BYTES_BIG_ENDIAN)
1992 /* Cancel the big-endian correction done in assign_stack_local.
1993 Get the address of the beginning of the slot.
1994 This is so we can do a big-endian correction unconditionally
1996 adjust = inherent_size - total_size;
1998 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2000 /* Nothing can alias this slot except this pseudo. */
2001 set_mem_alias_set (x, new_alias_set ());
2004 /* Reuse a stack slot if possible. */
2005 else if (spill_stack_slot[from_reg] != 0
2006 && spill_stack_slot_width[from_reg] >= total_size
2007 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2009 x = spill_stack_slot[from_reg];
2011 /* Allocate a bigger slot. */
2014 /* Compute maximum size needed, both for inherent size
2015 and for total size. */
2016 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2019 if (spill_stack_slot[from_reg])
2021 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2023 mode = GET_MODE (spill_stack_slot[from_reg]);
2024 if (spill_stack_slot_width[from_reg] > total_size)
2025 total_size = spill_stack_slot_width[from_reg];
2028 /* Make a slot with that size. */
2029 x = assign_stack_local (mode, total_size,
2030 inherent_size == total_size ? 0 : -1);
2033 /* All pseudos mapped to this slot can alias each other. */
2034 if (spill_stack_slot[from_reg])
2035 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2037 set_mem_alias_set (x, new_alias_set ());
2039 if (BYTES_BIG_ENDIAN)
2041 /* Cancel the big-endian correction done in assign_stack_local.
2042 Get the address of the beginning of the slot.
2043 This is so we can do a big-endian correction unconditionally
2045 adjust = GET_MODE_SIZE (mode) - total_size;
2048 = adjust_address_nv (x, mode_for_size (total_size
2054 spill_stack_slot[from_reg] = stack_slot;
2055 spill_stack_slot_width[from_reg] = total_size;
2058 /* On a big endian machine, the "address" of the slot
2059 is the address of the low part that fits its inherent mode. */
2060 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2061 adjust += (total_size - inherent_size);
2063 /* If we have any adjustment to make, or if the stack slot is the
2064 wrong mode, make a new stack slot. */
2065 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2067 /* If we have a decl for the original register, set it for the
2068 memory. If this is a shared MEM, make a copy. */
2071 rtx decl = DECL_RTL_IF_SET (REGNO_DECL (i));
2073 /* We can do this only for the DECLs home pseudo, not for
2074 any copies of it, since otherwise when the stack slot
2075 is reused, nonoverlapping_memrefs_p might think they
2077 if (decl && GET_CODE (decl) == REG && REGNO (decl) == (unsigned) i)
2079 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2082 set_mem_expr (x, REGNO_DECL (i));
2086 /* Save the stack slot for later. */
2087 reg_equiv_memory_loc[i] = x;
2091 /* Mark the slots in regs_ever_live for the hard regs
2092 used by pseudo-reg number REGNO. */
2095 mark_home_live (regno)
2100 i = reg_renumber[regno];
2103 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2105 regs_ever_live[i++] = 1;
2108 /* This function handles the tracking of elimination offsets around branches.
2110 X is a piece of RTL being scanned.
2112 INSN is the insn that it came from, if any.
2114 INITIAL_P is non-zero if we are to set the offset to be the initial
2115 offset and zero if we are setting the offset of the label to be the
2119 set_label_offsets (x, insn, initial_p)
2124 enum rtx_code code = GET_CODE (x);
2127 struct elim_table *p;
2132 if (LABEL_REF_NONLOCAL_P (x))
2137 /* ... fall through ... */
2140 /* If we know nothing about this label, set the desired offsets. Note
2141 that this sets the offset at a label to be the offset before a label
2142 if we don't know anything about the label. This is not correct for
2143 the label after a BARRIER, but is the best guess we can make. If
2144 we guessed wrong, we will suppress an elimination that might have
2145 been possible had we been able to guess correctly. */
2147 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2149 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2150 offsets_at[CODE_LABEL_NUMBER (x)][i]
2151 = (initial_p ? reg_eliminate[i].initial_offset
2152 : reg_eliminate[i].offset);
2153 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2156 /* Otherwise, if this is the definition of a label and it is
2157 preceded by a BARRIER, set our offsets to the known offset of
2161 && (tem = prev_nonnote_insn (insn)) != 0
2162 && GET_CODE (tem) == BARRIER)
2163 set_offsets_for_label (insn);
2165 /* If neither of the above cases is true, compare each offset
2166 with those previously recorded and suppress any eliminations
2167 where the offsets disagree. */
2169 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2170 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2171 != (initial_p ? reg_eliminate[i].initial_offset
2172 : reg_eliminate[i].offset))
2173 reg_eliminate[i].can_eliminate = 0;
2178 set_label_offsets (PATTERN (insn), insn, initial_p);
2180 /* ... fall through ... */
2184 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2185 and hence must have all eliminations at their initial offsets. */
2186 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2187 if (REG_NOTE_KIND (tem) == REG_LABEL)
2188 set_label_offsets (XEXP (tem, 0), insn, 1);
2194 /* Each of the labels in the parallel or address vector must be
2195 at their initial offsets. We want the first field for PARALLEL
2196 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2198 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2199 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2204 /* We only care about setting PC. If the source is not RETURN,
2205 IF_THEN_ELSE, or a label, disable any eliminations not at
2206 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2207 isn't one of those possibilities. For branches to a label,
2208 call ourselves recursively.
2210 Note that this can disable elimination unnecessarily when we have
2211 a non-local goto since it will look like a non-constant jump to
2212 someplace in the current function. This isn't a significant
2213 problem since such jumps will normally be when all elimination
2214 pairs are back to their initial offsets. */
2216 if (SET_DEST (x) != pc_rtx)
2219 switch (GET_CODE (SET_SRC (x)))
2226 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2230 tem = XEXP (SET_SRC (x), 1);
2231 if (GET_CODE (tem) == LABEL_REF)
2232 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2233 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2236 tem = XEXP (SET_SRC (x), 2);
2237 if (GET_CODE (tem) == LABEL_REF)
2238 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2239 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2247 /* If we reach here, all eliminations must be at their initial
2248 offset because we are doing a jump to a variable address. */
2249 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2250 if (p->offset != p->initial_offset)
2251 p->can_eliminate = 0;
2259 /* Scan X and replace any eliminable registers (such as fp) with a
2260 replacement (such as sp), plus an offset.
2262 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2263 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2264 MEM, we are allowed to replace a sum of a register and the constant zero
2265 with the register, which we cannot do outside a MEM. In addition, we need
2266 to record the fact that a register is referenced outside a MEM.
2268 If INSN is an insn, it is the insn containing X. If we replace a REG
2269 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2270 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2271 the REG is being modified.
2273 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2274 That's used when we eliminate in expressions stored in notes.
2275 This means, do not set ref_outside_mem even if the reference
2278 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2279 replacements done assuming all offsets are at their initial values. If
2280 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2281 encounter, return the actual location so that find_reloads will do
2282 the proper thing. */
2285 eliminate_regs (x, mem_mode, insn)
2287 enum machine_mode mem_mode;
2290 enum rtx_code code = GET_CODE (x);
2291 struct elim_table *ep;
2298 if (! current_function_decl)
2318 /* This is only for the benefit of the debugging backends, which call
2319 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2320 removed after CSE. */
2321 new = eliminate_regs (XEXP (x, 0), 0, insn);
2322 if (GET_CODE (new) == MEM)
2323 return XEXP (new, 0);
2329 /* First handle the case where we encounter a bare register that
2330 is eliminable. Replace it with a PLUS. */
2331 if (regno < FIRST_PSEUDO_REGISTER)
2333 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2335 if (ep->from_rtx == x && ep->can_eliminate)
2336 return plus_constant (ep->to_rtx, ep->previous_offset);
2339 else if (reg_renumber && reg_renumber[regno] < 0
2340 && reg_equiv_constant && reg_equiv_constant[regno]
2341 && ! CONSTANT_P (reg_equiv_constant[regno]))
2342 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2346 /* You might think handling MINUS in a manner similar to PLUS is a
2347 good idea. It is not. It has been tried multiple times and every
2348 time the change has had to have been reverted.
2350 Other parts of reload know a PLUS is special (gen_reload for example)
2351 and require special code to handle code a reloaded PLUS operand.
2353 Also consider backends where the flags register is clobbered by a
2354 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2355 lea instruction comes to mind). If we try to reload a MINUS, we
2356 may kill the flags register that was holding a useful value.
2358 So, please before trying to handle MINUS, consider reload as a
2359 whole instead of this little section as well as the backend issues. */
2361 /* If this is the sum of an eliminable register and a constant, rework
2363 if (GET_CODE (XEXP (x, 0)) == REG
2364 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2365 && CONSTANT_P (XEXP (x, 1)))
2367 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2369 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2371 /* The only time we want to replace a PLUS with a REG (this
2372 occurs when the constant operand of the PLUS is the negative
2373 of the offset) is when we are inside a MEM. We won't want
2374 to do so at other times because that would change the
2375 structure of the insn in a way that reload can't handle.
2376 We special-case the commonest situation in
2377 eliminate_regs_in_insn, so just replace a PLUS with a
2378 PLUS here, unless inside a MEM. */
2379 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2380 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2383 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2384 plus_constant (XEXP (x, 1),
2385 ep->previous_offset));
2388 /* If the register is not eliminable, we are done since the other
2389 operand is a constant. */
2393 /* If this is part of an address, we want to bring any constant to the
2394 outermost PLUS. We will do this by doing register replacement in
2395 our operands and seeing if a constant shows up in one of them.
2397 Note that there is no risk of modifying the structure of the insn,
2398 since we only get called for its operands, thus we are either
2399 modifying the address inside a MEM, or something like an address
2400 operand of a load-address insn. */
2403 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2404 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2406 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2408 /* If one side is a PLUS and the other side is a pseudo that
2409 didn't get a hard register but has a reg_equiv_constant,
2410 we must replace the constant here since it may no longer
2411 be in the position of any operand. */
2412 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2413 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2414 && reg_renumber[REGNO (new1)] < 0
2415 && reg_equiv_constant != 0
2416 && reg_equiv_constant[REGNO (new1)] != 0)
2417 new1 = reg_equiv_constant[REGNO (new1)];
2418 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2419 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2420 && reg_renumber[REGNO (new0)] < 0
2421 && reg_equiv_constant[REGNO (new0)] != 0)
2422 new0 = reg_equiv_constant[REGNO (new0)];
2424 new = form_sum (new0, new1);
2426 /* As above, if we are not inside a MEM we do not want to
2427 turn a PLUS into something else. We might try to do so here
2428 for an addition of 0 if we aren't optimizing. */
2429 if (! mem_mode && GET_CODE (new) != PLUS)
2430 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2438 /* If this is the product of an eliminable register and a
2439 constant, apply the distribute law and move the constant out
2440 so that we have (plus (mult ..) ..). This is needed in order
2441 to keep load-address insns valid. This case is pathological.
2442 We ignore the possibility of overflow here. */
2443 if (GET_CODE (XEXP (x, 0)) == REG
2444 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2445 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2446 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2448 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2451 /* Refs inside notes don't count for this purpose. */
2452 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2453 || GET_CODE (insn) == INSN_LIST)))
2454 ep->ref_outside_mem = 1;
2457 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2458 ep->previous_offset * INTVAL (XEXP (x, 1)));
2461 /* ... fall through ... */
2465 /* See comments before PLUS about handling MINUS. */
2467 case DIV: case UDIV:
2468 case MOD: case UMOD:
2469 case AND: case IOR: case XOR:
2470 case ROTATERT: case ROTATE:
2471 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2473 case GE: case GT: case GEU: case GTU:
2474 case LE: case LT: case LEU: case LTU:
2476 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2478 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2480 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2481 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2486 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2489 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2490 if (new != XEXP (x, 0))
2492 /* If this is a REG_DEAD note, it is not valid anymore.
2493 Using the eliminated version could result in creating a
2494 REG_DEAD note for the stack or frame pointer. */
2495 if (GET_MODE (x) == REG_DEAD)
2497 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2500 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2504 /* ... fall through ... */
2507 /* Now do eliminations in the rest of the chain. If this was
2508 an EXPR_LIST, this might result in allocating more memory than is
2509 strictly needed, but it simplifies the code. */
2512 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2513 if (new != XEXP (x, 1))
2515 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2523 case STRICT_LOW_PART:
2525 case SIGN_EXTEND: case ZERO_EXTEND:
2526 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2527 case FLOAT: case FIX:
2528 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2532 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2533 if (new != XEXP (x, 0))
2534 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2538 /* Similar to above processing, but preserve SUBREG_BYTE.
2539 Convert (subreg (mem)) to (mem) if not paradoxical.
2540 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2541 pseudo didn't get a hard reg, we must replace this with the
2542 eliminated version of the memory location because push_reloads
2543 may do the replacement in certain circumstances. */
2544 if (GET_CODE (SUBREG_REG (x)) == REG
2545 && (GET_MODE_SIZE (GET_MODE (x))
2546 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2547 && reg_equiv_memory_loc != 0
2548 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2550 new = SUBREG_REG (x);
2553 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2555 if (new != SUBREG_REG (x))
2557 int x_size = GET_MODE_SIZE (GET_MODE (x));
2558 int new_size = GET_MODE_SIZE (GET_MODE (new));
2560 if (GET_CODE (new) == MEM
2561 && ((x_size < new_size
2562 #ifdef WORD_REGISTER_OPERATIONS
2563 /* On these machines, combine can create rtl of the form
2564 (set (subreg:m1 (reg:m2 R) 0) ...)
2565 where m1 < m2, and expects something interesting to
2566 happen to the entire word. Moreover, it will use the
2567 (reg:m2 R) later, expecting all bits to be preserved.
2568 So if the number of words is the same, preserve the
2569 subreg so that push_reloads can see it. */
2570 && ! ((x_size - 1) / UNITS_PER_WORD
2571 == (new_size -1 ) / UNITS_PER_WORD)
2574 || x_size == new_size)
2576 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2578 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2584 /* This is only for the benefit of the debugging backends, which call
2585 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2586 removed after CSE. */
2587 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2588 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2590 /* Our only special processing is to pass the mode of the MEM to our
2591 recursive call and copy the flags. While we are here, handle this
2592 case more efficiently. */
2594 replace_equiv_address_nv (x,
2595 eliminate_regs (XEXP (x, 0),
2596 GET_MODE (x), insn));
2599 /* Handle insn_list USE that a call to a pure function may generate. */
2600 new = eliminate_regs (XEXP (x, 0), 0, insn);
2601 if (new != XEXP (x, 0))
2602 return gen_rtx_USE (GET_MODE (x), new);
2614 /* Process each of our operands recursively. If any have changed, make a
2616 fmt = GET_RTX_FORMAT (code);
2617 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2621 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2622 if (new != XEXP (x, i) && ! copied)
2624 rtx new_x = rtx_alloc (code);
2626 (sizeof (*new_x) - sizeof (new_x->fld)
2627 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2633 else if (*fmt == 'E')
2636 for (j = 0; j < XVECLEN (x, i); j++)
2638 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2639 if (new != XVECEXP (x, i, j) && ! copied_vec)
2641 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2645 rtx new_x = rtx_alloc (code);
2647 (sizeof (*new_x) - sizeof (new_x->fld)
2648 + (sizeof (new_x->fld[0])
2649 * GET_RTX_LENGTH (code))));
2653 XVEC (x, i) = new_v;
2656 XVECEXP (x, i, j) = new;
2664 /* Scan rtx X for modifications of elimination target registers. Update
2665 the table of eliminables to reflect the changed state. MEM_MODE is
2666 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2669 elimination_effects (x, mem_mode)
2671 enum machine_mode mem_mode;
2674 enum rtx_code code = GET_CODE (x);
2675 struct elim_table *ep;
2702 /* First handle the case where we encounter a bare register that
2703 is eliminable. Replace it with a PLUS. */
2704 if (regno < FIRST_PSEUDO_REGISTER)
2706 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2708 if (ep->from_rtx == x && ep->can_eliminate)
2711 ep->ref_outside_mem = 1;
2716 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2717 && reg_equiv_constant[regno]
2718 && ! function_invariant_p (reg_equiv_constant[regno]))
2719 elimination_effects (reg_equiv_constant[regno], mem_mode);
2728 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2729 if (ep->to_rtx == XEXP (x, 0))
2731 int size = GET_MODE_SIZE (mem_mode);
2733 /* If more bytes than MEM_MODE are pushed, account for them. */
2734 #ifdef PUSH_ROUNDING
2735 if (ep->to_rtx == stack_pointer_rtx)
2736 size = PUSH_ROUNDING (size);
2738 if (code == PRE_DEC || code == POST_DEC)
2740 else if (code == PRE_INC || code == POST_INC)
2742 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2743 && GET_CODE (XEXP (x, 1)) == PLUS
2744 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2745 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2746 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2749 /* These two aren't unary operators. */
2750 if (code == POST_MODIFY || code == PRE_MODIFY)
2753 /* Fall through to generic unary operation case. */
2754 case STRICT_LOW_PART:
2756 case SIGN_EXTEND: case ZERO_EXTEND:
2757 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2758 case FLOAT: case FIX:
2759 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2763 elimination_effects (XEXP (x, 0), mem_mode);
2767 if (GET_CODE (SUBREG_REG (x)) == REG
2768 && (GET_MODE_SIZE (GET_MODE (x))
2769 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2770 && reg_equiv_memory_loc != 0
2771 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2774 elimination_effects (SUBREG_REG (x), mem_mode);
2778 /* If using a register that is the source of an eliminate we still
2779 think can be performed, note it cannot be performed since we don't
2780 know how this register is used. */
2781 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2782 if (ep->from_rtx == XEXP (x, 0))
2783 ep->can_eliminate = 0;
2785 elimination_effects (XEXP (x, 0), mem_mode);
2789 /* If clobbering a register that is the replacement register for an
2790 elimination we still think can be performed, note that it cannot
2791 be performed. Otherwise, we need not be concerned about it. */
2792 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2793 if (ep->to_rtx == XEXP (x, 0))
2794 ep->can_eliminate = 0;
2796 elimination_effects (XEXP (x, 0), mem_mode);
2800 /* Check for setting a register that we know about. */
2801 if (GET_CODE (SET_DEST (x)) == REG)
2803 /* See if this is setting the replacement register for an
2806 If DEST is the hard frame pointer, we do nothing because we
2807 assume that all assignments to the frame pointer are for
2808 non-local gotos and are being done at a time when they are valid
2809 and do not disturb anything else. Some machines want to
2810 eliminate a fake argument pointer (or even a fake frame pointer)
2811 with either the real frame or the stack pointer. Assignments to
2812 the hard frame pointer must not prevent this elimination. */
2814 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2816 if (ep->to_rtx == SET_DEST (x)
2817 && SET_DEST (x) != hard_frame_pointer_rtx)
2819 /* If it is being incremented, adjust the offset. Otherwise,
2820 this elimination can't be done. */
2821 rtx src = SET_SRC (x);
2823 if (GET_CODE (src) == PLUS
2824 && XEXP (src, 0) == SET_DEST (x)
2825 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2826 ep->offset -= INTVAL (XEXP (src, 1));
2828 ep->can_eliminate = 0;
2832 elimination_effects (SET_DEST (x), 0);
2833 elimination_effects (SET_SRC (x), 0);
2837 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2840 /* Our only special processing is to pass the mode of the MEM to our
2842 elimination_effects (XEXP (x, 0), GET_MODE (x));
2849 fmt = GET_RTX_FORMAT (code);
2850 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2853 elimination_effects (XEXP (x, i), mem_mode);
2854 else if (*fmt == 'E')
2855 for (j = 0; j < XVECLEN (x, i); j++)
2856 elimination_effects (XVECEXP (x, i, j), mem_mode);
2860 /* Descend through rtx X and verify that no references to eliminable registers
2861 remain. If any do remain, mark the involved register as not
2865 check_eliminable_occurrences (x)
2875 code = GET_CODE (x);
2877 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2879 struct elim_table *ep;
2881 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2882 if (ep->from_rtx == x && ep->can_eliminate)
2883 ep->can_eliminate = 0;
2887 fmt = GET_RTX_FORMAT (code);
2888 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2891 check_eliminable_occurrences (XEXP (x, i));
2892 else if (*fmt == 'E')
2895 for (j = 0; j < XVECLEN (x, i); j++)
2896 check_eliminable_occurrences (XVECEXP (x, i, j));
2901 /* Scan INSN and eliminate all eliminable registers in it.
2903 If REPLACE is nonzero, do the replacement destructively. Also
2904 delete the insn as dead it if it is setting an eliminable register.
2906 If REPLACE is zero, do all our allocations in reload_obstack.
2908 If no eliminations were done and this insn doesn't require any elimination
2909 processing (these are not identical conditions: it might be updating sp,
2910 but not referencing fp; this needs to be seen during reload_as_needed so
2911 that the offset between fp and sp can be taken into consideration), zero
2912 is returned. Otherwise, 1 is returned. */
2915 eliminate_regs_in_insn (insn, replace)
2919 int icode = recog_memoized (insn);
2920 rtx old_body = PATTERN (insn);
2921 int insn_is_asm = asm_noperands (old_body) >= 0;
2922 rtx old_set = single_set (insn);
2926 rtx substed_operand[MAX_RECOG_OPERANDS];
2927 rtx orig_operand[MAX_RECOG_OPERANDS];
2928 struct elim_table *ep;
2930 if (! insn_is_asm && icode < 0)
2932 if (GET_CODE (PATTERN (insn)) == USE
2933 || GET_CODE (PATTERN (insn)) == CLOBBER
2934 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2935 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2936 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2941 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2942 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2944 /* Check for setting an eliminable register. */
2945 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2946 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2948 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2949 /* If this is setting the frame pointer register to the
2950 hardware frame pointer register and this is an elimination
2951 that will be done (tested above), this insn is really
2952 adjusting the frame pointer downward to compensate for
2953 the adjustment done before a nonlocal goto. */
2954 if (ep->from == FRAME_POINTER_REGNUM
2955 && ep->to == HARD_FRAME_POINTER_REGNUM)
2957 rtx base = SET_SRC (old_set);
2958 rtx base_insn = insn;
2961 while (base != ep->to_rtx)
2963 rtx prev_insn, prev_set;
2965 if (GET_CODE (base) == PLUS
2966 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2968 offset += INTVAL (XEXP (base, 1));
2969 base = XEXP (base, 0);
2971 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2972 && (prev_set = single_set (prev_insn)) != 0
2973 && rtx_equal_p (SET_DEST (prev_set), base))
2975 base = SET_SRC (prev_set);
2976 base_insn = prev_insn;
2982 if (base == ep->to_rtx)
2985 = plus_constant (ep->to_rtx, offset - ep->offset);
2987 new_body = old_body;
2990 new_body = copy_insn (old_body);
2991 if (REG_NOTES (insn))
2992 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2994 PATTERN (insn) = new_body;
2995 old_set = single_set (insn);
2997 /* First see if this insn remains valid when we
2998 make the change. If not, keep the INSN_CODE
2999 the same and let reload fit it up. */
3000 validate_change (insn, &SET_SRC (old_set), src, 1);
3001 validate_change (insn, &SET_DEST (old_set),
3003 if (! apply_change_group ())
3005 SET_SRC (old_set) = src;
3006 SET_DEST (old_set) = ep->to_rtx;
3015 /* In this case this insn isn't serving a useful purpose. We
3016 will delete it in reload_as_needed once we know that this
3017 elimination is, in fact, being done.
3019 If REPLACE isn't set, we can't delete this insn, but needn't
3020 process it since it won't be used unless something changes. */
3023 delete_dead_insn (insn);
3031 /* We allow one special case which happens to work on all machines we
3032 currently support: a single set with the source being a PLUS of an
3033 eliminable register and a constant. */
3035 && GET_CODE (SET_DEST (old_set)) == REG
3036 && GET_CODE (SET_SRC (old_set)) == PLUS
3037 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3038 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
3039 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
3041 rtx reg = XEXP (SET_SRC (old_set), 0);
3042 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
3044 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3045 if (ep->from_rtx == reg && ep->can_eliminate)
3047 offset += ep->offset;
3052 /* We assume here that if we need a PARALLEL with
3053 CLOBBERs for this assignment, we can do with the
3054 MATCH_SCRATCHes that add_clobbers allocates.
3055 There's not much we can do if that doesn't work. */
3056 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3060 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3063 rtvec vec = rtvec_alloc (num_clobbers + 1);
3065 vec->elem[0] = PATTERN (insn);
3066 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3067 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3069 if (INSN_CODE (insn) < 0)
3074 new_body = old_body;
3077 new_body = copy_insn (old_body);
3078 if (REG_NOTES (insn))
3079 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3081 PATTERN (insn) = new_body;
3082 old_set = single_set (insn);
3084 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3085 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3088 /* This can't have an effect on elimination offsets, so skip right
3094 /* Determine the effects of this insn on elimination offsets. */
3095 elimination_effects (old_body, 0);
3097 /* Eliminate all eliminable registers occurring in operands that
3098 can be handled by reload. */
3099 extract_insn (insn);
3101 for (i = 0; i < recog_data.n_operands; i++)
3103 orig_operand[i] = recog_data.operand[i];
3104 substed_operand[i] = recog_data.operand[i];
3106 /* For an asm statement, every operand is eliminable. */
3107 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3109 /* Check for setting a register that we know about. */
3110 if (recog_data.operand_type[i] != OP_IN
3111 && GET_CODE (orig_operand[i]) == REG)
3113 /* If we are assigning to a register that can be eliminated, it
3114 must be as part of a PARALLEL, since the code above handles
3115 single SETs. We must indicate that we can no longer
3116 eliminate this reg. */
3117 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3119 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3120 ep->can_eliminate = 0;
3123 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3124 replace ? insn : NULL_RTX);
3125 if (substed_operand[i] != orig_operand[i])
3126 val = any_changes = 1;
3127 /* Terminate the search in check_eliminable_occurrences at
3129 *recog_data.operand_loc[i] = 0;
3131 /* If an output operand changed from a REG to a MEM and INSN is an
3132 insn, write a CLOBBER insn. */
3133 if (recog_data.operand_type[i] != OP_IN
3134 && GET_CODE (orig_operand[i]) == REG
3135 && GET_CODE (substed_operand[i]) == MEM
3137 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3142 for (i = 0; i < recog_data.n_dups; i++)
3143 *recog_data.dup_loc[i]
3144 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3146 /* If any eliminable remain, they aren't eliminable anymore. */
3147 check_eliminable_occurrences (old_body);
3149 /* Substitute the operands; the new values are in the substed_operand
3151 for (i = 0; i < recog_data.n_operands; i++)
3152 *recog_data.operand_loc[i] = substed_operand[i];
3153 for (i = 0; i < recog_data.n_dups; i++)
3154 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3156 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3157 re-recognize the insn. We do this in case we had a simple addition
3158 but now can do this as a load-address. This saves an insn in this
3160 If re-recognition fails, the old insn code number will still be used,
3161 and some register operands may have changed into PLUS expressions.
3162 These will be handled by find_reloads by loading them into a register
3167 /* If we aren't replacing things permanently and we changed something,
3168 make another copy to ensure that all the RTL is new. Otherwise
3169 things can go wrong if find_reload swaps commutative operands
3170 and one is inside RTL that has been copied while the other is not. */
3171 new_body = old_body;
3174 new_body = copy_insn (old_body);
3175 if (REG_NOTES (insn))
3176 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3178 PATTERN (insn) = new_body;
3180 /* If we had a move insn but now we don't, rerecognize it. This will
3181 cause spurious re-recognition if the old move had a PARALLEL since
3182 the new one still will, but we can't call single_set without
3183 having put NEW_BODY into the insn and the re-recognition won't
3184 hurt in this rare case. */
3185 /* ??? Why this huge if statement - why don't we just rerecognize the
3189 && ((GET_CODE (SET_SRC (old_set)) == REG
3190 && (GET_CODE (new_body) != SET
3191 || GET_CODE (SET_SRC (new_body)) != REG))
3192 /* If this was a load from or store to memory, compare
3193 the MEM in recog_data.operand to the one in the insn.
3194 If they are not equal, then rerecognize the insn. */
3196 && ((GET_CODE (SET_SRC (old_set)) == MEM
3197 && SET_SRC (old_set) != recog_data.operand[1])
3198 || (GET_CODE (SET_DEST (old_set)) == MEM
3199 && SET_DEST (old_set) != recog_data.operand[0])))
3200 /* If this was an add insn before, rerecognize. */
3201 || GET_CODE (SET_SRC (old_set)) == PLUS))
3203 int new_icode = recog (PATTERN (insn), insn, 0);
3205 INSN_CODE (insn) = icode;
3209 /* Restore the old body. If there were any changes to it, we made a copy
3210 of it while the changes were still in place, so we'll correctly return
3211 a modified insn below. */
3214 /* Restore the old body. */
3215 for (i = 0; i < recog_data.n_operands; i++)
3216 *recog_data.operand_loc[i] = orig_operand[i];
3217 for (i = 0; i < recog_data.n_dups; i++)
3218 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3221 /* Update all elimination pairs to reflect the status after the current
3222 insn. The changes we make were determined by the earlier call to
3223 elimination_effects.
3225 We also detect a cases where register elimination cannot be done,
3226 namely, if a register would be both changed and referenced outside a MEM
3227 in the resulting insn since such an insn is often undefined and, even if
3228 not, we cannot know what meaning will be given to it. Note that it is
3229 valid to have a register used in an address in an insn that changes it
3230 (presumably with a pre- or post-increment or decrement).
3232 If anything changes, return nonzero. */
3234 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3236 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3237 ep->can_eliminate = 0;
3239 ep->ref_outside_mem = 0;
3241 if (ep->previous_offset != ep->offset)
3246 /* If we changed something, perform elimination in REG_NOTES. This is
3247 needed even when REPLACE is zero because a REG_DEAD note might refer
3248 to a register that we eliminate and could cause a different number
3249 of spill registers to be needed in the final reload pass than in
3251 if (val && REG_NOTES (insn) != 0)
3252 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3257 /* Loop through all elimination pairs.
3258 Recalculate the number not at initial offset.
3260 Compute the maximum offset (minimum offset if the stack does not
3261 grow downward) for each elimination pair. */
3264 update_eliminable_offsets ()
3266 struct elim_table *ep;
3268 num_not_at_initial_offset = 0;
3269 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3271 ep->previous_offset = ep->offset;
3272 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3273 num_not_at_initial_offset++;
3277 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3278 replacement we currently believe is valid, mark it as not eliminable if X
3279 modifies DEST in any way other than by adding a constant integer to it.
3281 If DEST is the frame pointer, we do nothing because we assume that
3282 all assignments to the hard frame pointer are nonlocal gotos and are being
3283 done at a time when they are valid and do not disturb anything else.
3284 Some machines want to eliminate a fake argument pointer with either the
3285 frame or stack pointer. Assignments to the hard frame pointer must not
3286 prevent this elimination.
3288 Called via note_stores from reload before starting its passes to scan
3289 the insns of the function. */
3292 mark_not_eliminable (dest, x, data)
3295 void *data ATTRIBUTE_UNUSED;
3299 /* A SUBREG of a hard register here is just changing its mode. We should
3300 not see a SUBREG of an eliminable hard register, but check just in
3302 if (GET_CODE (dest) == SUBREG)
3303 dest = SUBREG_REG (dest);
3305 if (dest == hard_frame_pointer_rtx)
3308 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3309 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3310 && (GET_CODE (x) != SET
3311 || GET_CODE (SET_SRC (x)) != PLUS
3312 || XEXP (SET_SRC (x), 0) != dest
3313 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3315 reg_eliminate[i].can_eliminate_previous
3316 = reg_eliminate[i].can_eliminate = 0;
3321 /* Verify that the initial elimination offsets did not change since the
3322 last call to set_initial_elim_offsets. This is used to catch cases
3323 where something illegal happened during reload_as_needed that could
3324 cause incorrect code to be generated if we did not check for it. */
3327 verify_initial_elim_offsets ()
3331 #ifdef ELIMINABLE_REGS
3332 struct elim_table *ep;
3334 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3336 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3337 if (t != ep->initial_offset)
3341 INITIAL_FRAME_POINTER_OFFSET (t);
3342 if (t != reg_eliminate[0].initial_offset)
3347 /* Reset all offsets on eliminable registers to their initial values. */
3350 set_initial_elim_offsets ()
3352 struct elim_table *ep = reg_eliminate;
3354 #ifdef ELIMINABLE_REGS
3355 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3357 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3358 ep->previous_offset = ep->offset = ep->initial_offset;
3361 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3362 ep->previous_offset = ep->offset = ep->initial_offset;
3365 num_not_at_initial_offset = 0;
3368 /* Initialize the known label offsets.
3369 Set a known offset for each forced label to be at the initial offset
3370 of each elimination. We do this because we assume that all
3371 computed jumps occur from a location where each elimination is
3372 at its initial offset.
3373 For all other labels, show that we don't know the offsets. */
3376 set_initial_label_offsets ()
3379 memset ((char *) &offsets_known_at[get_first_label_num ()], 0, num_labels);
3381 for (x = forced_labels; x; x = XEXP (x, 1))
3383 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3386 /* Set all elimination offsets to the known values for the code label given
3390 set_offsets_for_label (insn)
3394 int label_nr = CODE_LABEL_NUMBER (insn);
3395 struct elim_table *ep;
3397 num_not_at_initial_offset = 0;
3398 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3400 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3401 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3402 num_not_at_initial_offset++;
3406 /* See if anything that happened changes which eliminations are valid.
3407 For example, on the Sparc, whether or not the frame pointer can
3408 be eliminated can depend on what registers have been used. We need
3409 not check some conditions again (such as flag_omit_frame_pointer)
3410 since they can't have changed. */
3413 update_eliminables (pset)
3416 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3417 int previous_frame_pointer_needed = frame_pointer_needed;
3419 struct elim_table *ep;
3421 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3422 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3423 #ifdef ELIMINABLE_REGS
3424 || ! CAN_ELIMINATE (ep->from, ep->to)
3427 ep->can_eliminate = 0;
3429 /* Look for the case where we have discovered that we can't replace
3430 register A with register B and that means that we will now be
3431 trying to replace register A with register C. This means we can
3432 no longer replace register C with register B and we need to disable
3433 such an elimination, if it exists. This occurs often with A == ap,
3434 B == sp, and C == fp. */
3436 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3438 struct elim_table *op;
3441 if (! ep->can_eliminate && ep->can_eliminate_previous)
3443 /* Find the current elimination for ep->from, if there is a
3445 for (op = reg_eliminate;
3446 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3447 if (op->from == ep->from && op->can_eliminate)
3453 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3455 for (op = reg_eliminate;
3456 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3457 if (op->from == new_to && op->to == ep->to)
3458 op->can_eliminate = 0;
3462 /* See if any registers that we thought we could eliminate the previous
3463 time are no longer eliminable. If so, something has changed and we
3464 must spill the register. Also, recompute the number of eliminable
3465 registers and see if the frame pointer is needed; it is if there is
3466 no elimination of the frame pointer that we can perform. */
3468 frame_pointer_needed = 1;
3469 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3471 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3472 && ep->to != HARD_FRAME_POINTER_REGNUM)
3473 frame_pointer_needed = 0;
3475 if (! ep->can_eliminate && ep->can_eliminate_previous)
3477 ep->can_eliminate_previous = 0;
3478 SET_HARD_REG_BIT (*pset, ep->from);
3483 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3484 /* If we didn't need a frame pointer last time, but we do now, spill
3485 the hard frame pointer. */
3486 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3487 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3491 /* Initialize the table of registers to eliminate. */
3496 struct elim_table *ep;
3497 #ifdef ELIMINABLE_REGS
3498 const struct elim_table_1 *ep1;
3502 reg_eliminate = (struct elim_table *)
3503 xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3505 /* Does this function require a frame pointer? */
3507 frame_pointer_needed = (! flag_omit_frame_pointer
3508 #ifdef EXIT_IGNORE_STACK
3509 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3510 and restore sp for alloca. So we can't eliminate
3511 the frame pointer in that case. At some point,
3512 we should improve this by emitting the
3513 sp-adjusting insns for this case. */
3514 || (current_function_calls_alloca
3515 && EXIT_IGNORE_STACK)
3517 || FRAME_POINTER_REQUIRED);
3521 #ifdef ELIMINABLE_REGS
3522 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3523 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3525 ep->from = ep1->from;
3527 ep->can_eliminate = ep->can_eliminate_previous
3528 = (CAN_ELIMINATE (ep->from, ep->to)
3529 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3532 reg_eliminate[0].from = reg_eliminate_1[0].from;
3533 reg_eliminate[0].to = reg_eliminate_1[0].to;
3534 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3535 = ! frame_pointer_needed;
3538 /* Count the number of eliminable registers and build the FROM and TO
3539 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3540 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3541 We depend on this. */
3542 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3544 num_eliminable += ep->can_eliminate;
3545 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3546 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3550 /* Kick all pseudos out of hard register REGNO.
3552 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3553 because we found we can't eliminate some register. In the case, no pseudos
3554 are allowed to be in the register, even if they are only in a block that
3555 doesn't require spill registers, unlike the case when we are spilling this
3556 hard reg to produce another spill register.
3558 Return nonzero if any pseudos needed to be kicked out. */
3561 spill_hard_reg (regno, cant_eliminate)
3569 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3570 regs_ever_live[regno] = 1;
3573 /* Spill every pseudo reg that was allocated to this reg
3574 or to something that overlaps this reg. */
3576 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3577 if (reg_renumber[i] >= 0
3578 && (unsigned int) reg_renumber[i] <= regno
3579 && ((unsigned int) reg_renumber[i]
3580 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3581 PSEUDO_REGNO_MODE (i))
3583 SET_REGNO_REG_SET (&spilled_pseudos, i);
3586 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3587 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3590 ior_hard_reg_set (set1, set2)
3591 HARD_REG_SET *set1, *set2;
3593 IOR_HARD_REG_SET (*set1, *set2);
3596 /* After find_reload_regs has been run for all insn that need reloads,
3597 and/or spill_hard_regs was called, this function is used to actually
3598 spill pseudo registers and try to reallocate them. It also sets up the
3599 spill_regs array for use by choose_reload_regs. */
3602 finish_spills (global)
3605 struct insn_chain *chain;
3606 int something_changed = 0;
3609 /* Build the spill_regs array for the function. */
3610 /* If there are some registers still to eliminate and one of the spill regs
3611 wasn't ever used before, additional stack space may have to be
3612 allocated to store this register. Thus, we may have changed the offset
3613 between the stack and frame pointers, so mark that something has changed.
3615 One might think that we need only set VAL to 1 if this is a call-used
3616 register. However, the set of registers that must be saved by the
3617 prologue is not identical to the call-used set. For example, the
3618 register used by the call insn for the return PC is a call-used register,
3619 but must be saved by the prologue. */
3622 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3623 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3625 spill_reg_order[i] = n_spills;
3626 spill_regs[n_spills++] = i;
3627 if (num_eliminable && ! regs_ever_live[i])
3628 something_changed = 1;
3629 regs_ever_live[i] = 1;
3632 spill_reg_order[i] = -1;
3634 EXECUTE_IF_SET_IN_REG_SET
3635 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3637 /* Record the current hard register the pseudo is allocated to in
3638 pseudo_previous_regs so we avoid reallocating it to the same
3639 hard reg in a later pass. */
3640 if (reg_renumber[i] < 0)
3643 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3644 /* Mark it as no longer having a hard register home. */
3645 reg_renumber[i] = -1;
3646 /* We will need to scan everything again. */
3647 something_changed = 1;
3650 /* Retry global register allocation if possible. */
3653 memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3654 /* For every insn that needs reloads, set the registers used as spill
3655 regs in pseudo_forbidden_regs for every pseudo live across the
3657 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3659 EXECUTE_IF_SET_IN_REG_SET
3660 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3662 ior_hard_reg_set (pseudo_forbidden_regs + i,
3663 &chain->used_spill_regs);
3665 EXECUTE_IF_SET_IN_REG_SET
3666 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3668 ior_hard_reg_set (pseudo_forbidden_regs + i,
3669 &chain->used_spill_regs);
3673 /* Retry allocating the spilled pseudos. For each reg, merge the
3674 various reg sets that indicate which hard regs can't be used,
3675 and call retry_global_alloc.
3676 We change spill_pseudos here to only contain pseudos that did not
3677 get a new hard register. */
3678 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3679 if (reg_old_renumber[i] != reg_renumber[i])
3681 HARD_REG_SET forbidden;
3682 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3683 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3684 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3685 retry_global_alloc (i, forbidden);
3686 if (reg_renumber[i] >= 0)
3687 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3691 /* Fix up the register information in the insn chain.
3692 This involves deleting those of the spilled pseudos which did not get
3693 a new hard register home from the live_{before,after} sets. */
3694 for (chain = reload_insn_chain; chain; chain = chain->next)
3696 HARD_REG_SET used_by_pseudos;
3697 HARD_REG_SET used_by_pseudos2;
3699 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3700 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3702 /* Mark any unallocated hard regs as available for spills. That
3703 makes inheritance work somewhat better. */
3704 if (chain->need_reload)
3706 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3707 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3708 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3710 /* Save the old value for the sanity test below. */
3711 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3713 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3714 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3715 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3716 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3718 /* Make sure we only enlarge the set. */
3719 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3725 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3726 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3728 int regno = reg_renumber[i];
3729 if (reg_old_renumber[i] == regno)
3732 alter_reg (i, reg_old_renumber[i]);
3733 reg_old_renumber[i] = regno;
3737 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3739 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3740 i, reg_renumber[i]);
3744 return something_changed;
3747 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3748 Also mark any hard registers used to store user variables as
3749 forbidden from being used for spill registers. */
3752 scan_paradoxical_subregs (x)
3757 enum rtx_code code = GET_CODE (x);
3763 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3764 && REG_USERVAR_P (x))
3765 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3774 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3782 if (GET_CODE (SUBREG_REG (x)) == REG
3783 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3784 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3785 = GET_MODE_SIZE (GET_MODE (x));
3792 fmt = GET_RTX_FORMAT (code);
3793 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3796 scan_paradoxical_subregs (XEXP (x, i));
3797 else if (fmt[i] == 'E')
3800 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3801 scan_paradoxical_subregs (XVECEXP (x, i, j));
3806 /* Reload pseudo-registers into hard regs around each insn as needed.
3807 Additional register load insns are output before the insn that needs it
3808 and perhaps store insns after insns that modify the reloaded pseudo reg.
3810 reg_last_reload_reg and reg_reloaded_contents keep track of
3811 which registers are already available in reload registers.
3812 We update these for the reloads that we perform,
3813 as the insns are scanned. */
3816 reload_as_needed (live_known)
3819 struct insn_chain *chain;
3820 #if defined (AUTO_INC_DEC)
3825 memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx);
3826 memset ((char *) spill_reg_store, 0, sizeof spill_reg_store);
3827 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3828 reg_has_output_reload = (char *) xmalloc (max_regno);
3829 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3831 set_initial_elim_offsets ();
3833 for (chain = reload_insn_chain; chain; chain = chain->next)
3836 rtx insn = chain->insn;
3837 rtx old_next = NEXT_INSN (insn);
3839 /* If we pass a label, copy the offsets from the label information
3840 into the current offsets of each elimination. */
3841 if (GET_CODE (insn) == CODE_LABEL)
3842 set_offsets_for_label (insn);
3844 else if (INSN_P (insn))
3846 rtx oldpat = PATTERN (insn);
3848 /* If this is a USE and CLOBBER of a MEM, ensure that any
3849 references to eliminable registers have been removed. */
3851 if ((GET_CODE (PATTERN (insn)) == USE
3852 || GET_CODE (PATTERN (insn)) == CLOBBER)
3853 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3854 XEXP (XEXP (PATTERN (insn), 0), 0)
3855 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3856 GET_MODE (XEXP (PATTERN (insn), 0)),
3859 /* If we need to do register elimination processing, do so.
3860 This might delete the insn, in which case we are done. */
3861 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3863 eliminate_regs_in_insn (insn, 1);
3864 if (GET_CODE (insn) == NOTE)
3866 update_eliminable_offsets ();
3871 /* If need_elim is nonzero but need_reload is zero, one might think
3872 that we could simply set n_reloads to 0. However, find_reloads
3873 could have done some manipulation of the insn (such as swapping
3874 commutative operands), and these manipulations are lost during
3875 the first pass for every insn that needs register elimination.
3876 So the actions of find_reloads must be redone here. */
3878 if (! chain->need_elim && ! chain->need_reload
3879 && ! chain->need_operand_change)
3881 /* First find the pseudo regs that must be reloaded for this insn.
3882 This info is returned in the tables reload_... (see reload.h).
3883 Also modify the body of INSN by substituting RELOAD
3884 rtx's for those pseudo regs. */
3887 memset (reg_has_output_reload, 0, max_regno);
3888 CLEAR_HARD_REG_SET (reg_is_output_reload);
3890 find_reloads (insn, 1, spill_indirect_levels, live_known,
3896 rtx next = NEXT_INSN (insn);
3899 prev = PREV_INSN (insn);
3901 /* Now compute which reload regs to reload them into. Perhaps
3902 reusing reload regs from previous insns, or else output
3903 load insns to reload them. Maybe output store insns too.
3904 Record the choices of reload reg in reload_reg_rtx. */
3905 choose_reload_regs (chain);
3907 /* Merge any reloads that we didn't combine for fear of
3908 increasing the number of spill registers needed but now
3909 discover can be safely merged. */
3910 if (SMALL_REGISTER_CLASSES)
3911 merge_assigned_reloads (insn);
3913 /* Generate the insns to reload operands into or out of
3914 their reload regs. */
3915 emit_reload_insns (chain);
3917 /* Substitute the chosen reload regs from reload_reg_rtx
3918 into the insn's body (or perhaps into the bodies of other
3919 load and store insn that we just made for reloading
3920 and that we moved the structure into). */
3921 subst_reloads (insn);
3923 /* If this was an ASM, make sure that all the reload insns
3924 we have generated are valid. If not, give an error
3927 if (asm_noperands (PATTERN (insn)) >= 0)
3928 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3929 if (p != insn && INSN_P (p)
3930 && (recog_memoized (p) < 0
3931 || (extract_insn (p), ! constrain_operands (1))))
3933 error_for_asm (insn,
3934 "`asm' operand requires impossible reload");
3939 if (num_eliminable && chain->need_elim)
3940 update_eliminable_offsets ();
3942 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3943 is no longer validly lying around to save a future reload.
3944 Note that this does not detect pseudos that were reloaded
3945 for this insn in order to be stored in
3946 (obeying register constraints). That is correct; such reload
3947 registers ARE still valid. */
3948 note_stores (oldpat, forget_old_reloads_1, NULL);
3950 /* There may have been CLOBBER insns placed after INSN. So scan
3951 between INSN and NEXT and use them to forget old reloads. */
3952 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3953 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3954 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3957 /* Likewise for regs altered by auto-increment in this insn.
3958 REG_INC notes have been changed by reloading:
3959 find_reloads_address_1 records substitutions for them,
3960 which have been performed by subst_reloads above. */
3961 for (i = n_reloads - 1; i >= 0; i--)
3963 rtx in_reg = rld[i].in_reg;
3966 enum rtx_code code = GET_CODE (in_reg);
3967 /* PRE_INC / PRE_DEC will have the reload register ending up
3968 with the same value as the stack slot, but that doesn't
3969 hold true for POST_INC / POST_DEC. Either we have to
3970 convert the memory access to a true POST_INC / POST_DEC,
3971 or we can't use the reload register for inheritance. */
3972 if ((code == POST_INC || code == POST_DEC)
3973 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3974 REGNO (rld[i].reg_rtx))
3975 /* Make sure it is the inc/dec pseudo, and not
3976 some other (e.g. output operand) pseudo. */
3977 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3978 == REGNO (XEXP (in_reg, 0))))
3981 rtx reload_reg = rld[i].reg_rtx;
3982 enum machine_mode mode = GET_MODE (reload_reg);
3986 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3988 /* We really want to ignore REG_INC notes here, so
3989 use PATTERN (p) as argument to reg_set_p . */
3990 if (reg_set_p (reload_reg, PATTERN (p)))
3992 n = count_occurrences (PATTERN (p), reload_reg, 0);
3997 n = validate_replace_rtx (reload_reg,
3998 gen_rtx (code, mode,
4002 /* We must also verify that the constraints
4003 are met after the replacement. */
4006 n = constrain_operands (1);
4010 /* If the constraints were not met, then
4011 undo the replacement. */
4014 validate_replace_rtx (gen_rtx (code, mode,
4026 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4028 /* Mark this as having an output reload so that the
4029 REG_INC processing code below won't invalidate
4030 the reload for inheritance. */
4031 SET_HARD_REG_BIT (reg_is_output_reload,
4032 REGNO (reload_reg));
4033 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4036 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4039 else if ((code == PRE_INC || code == PRE_DEC)
4040 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4041 REGNO (rld[i].reg_rtx))
4042 /* Make sure it is the inc/dec pseudo, and not
4043 some other (e.g. output operand) pseudo. */
4044 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4045 == REGNO (XEXP (in_reg, 0))))
4047 SET_HARD_REG_BIT (reg_is_output_reload,
4048 REGNO (rld[i].reg_rtx));
4049 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4053 /* If a pseudo that got a hard register is auto-incremented,
4054 we must purge records of copying it into pseudos without
4056 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4057 if (REG_NOTE_KIND (x) == REG_INC)
4059 /* See if this pseudo reg was reloaded in this insn.
4060 If so, its last-reload info is still valid
4061 because it is based on this insn's reload. */
4062 for (i = 0; i < n_reloads; i++)
4063 if (rld[i].out == XEXP (x, 0))
4067 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4071 /* A reload reg's contents are unknown after a label. */
4072 if (GET_CODE (insn) == CODE_LABEL)
4073 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4075 /* Don't assume a reload reg is still good after a call insn
4076 if it is a call-used reg. */
4077 else if (GET_CODE (insn) == CALL_INSN)
4078 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4082 free (reg_last_reload_reg);
4083 free (reg_has_output_reload);
4086 /* Discard all record of any value reloaded from X,
4087 or reloaded in X from someplace else;
4088 unless X is an output reload reg of the current insn.
4090 X may be a hard reg (the reload reg)
4091 or it may be a pseudo reg that was reloaded from. */
4094 forget_old_reloads_1 (x, ignored, data)
4096 rtx ignored ATTRIBUTE_UNUSED;
4097 void *data ATTRIBUTE_UNUSED;
4103 /* note_stores does give us subregs of hard regs,
4104 subreg_regno_offset will abort if it is not a hard reg. */
4105 while (GET_CODE (x) == SUBREG)
4107 offset += subreg_regno_offset (REGNO (SUBREG_REG (x)),
4108 GET_MODE (SUBREG_REG (x)),
4114 if (GET_CODE (x) != REG)
4117 regno = REGNO (x) + offset;
4119 if (regno >= FIRST_PSEUDO_REGISTER)
4125 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4126 /* Storing into a spilled-reg invalidates its contents.
4127 This can happen if a block-local pseudo is allocated to that reg
4128 and it wasn't spilled because this block's total need is 0.
4129 Then some insn might have an optional reload and use this reg. */
4130 for (i = 0; i < nr; i++)
4131 /* But don't do this if the reg actually serves as an output
4132 reload reg in the current instruction. */
4134 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4136 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4137 spill_reg_store[regno + i] = 0;
4141 /* Since value of X has changed,
4142 forget any value previously copied from it. */
4145 /* But don't forget a copy if this is the output reload
4146 that establishes the copy's validity. */
4147 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4148 reg_last_reload_reg[regno + nr] = 0;
4151 /* The following HARD_REG_SETs indicate when each hard register is
4152 used for a reload of various parts of the current insn. */
4154 /* If reg is unavailable for all reloads. */
4155 static HARD_REG_SET reload_reg_unavailable;
4156 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4157 static HARD_REG_SET reload_reg_used;
4158 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4159 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4160 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4161 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4162 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4163 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4164 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4165 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4166 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4167 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4168 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4169 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4170 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4171 static HARD_REG_SET reload_reg_used_in_op_addr;
4172 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4173 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4174 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4175 static HARD_REG_SET reload_reg_used_in_insn;
4176 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4177 static HARD_REG_SET reload_reg_used_in_other_addr;
4179 /* If reg is in use as a reload reg for any sort of reload. */
4180 static HARD_REG_SET reload_reg_used_at_all;
4182 /* If reg is use as an inherited reload. We just mark the first register
4184 static HARD_REG_SET reload_reg_used_for_inherit;
4186 /* Records which hard regs are used in any way, either as explicit use or
4187 by being allocated to a pseudo during any point of the current insn. */
4188 static HARD_REG_SET reg_used_in_insn;
4190 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4191 TYPE. MODE is used to indicate how many consecutive regs are
4195 mark_reload_reg_in_use (regno, opnum, type, mode)
4198 enum reload_type type;
4199 enum machine_mode mode;
4201 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4204 for (i = regno; i < nregs + regno; i++)
4209 SET_HARD_REG_BIT (reload_reg_used, i);
4212 case RELOAD_FOR_INPUT_ADDRESS:
4213 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4216 case RELOAD_FOR_INPADDR_ADDRESS:
4217 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4220 case RELOAD_FOR_OUTPUT_ADDRESS:
4221 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4224 case RELOAD_FOR_OUTADDR_ADDRESS:
4225 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4228 case RELOAD_FOR_OPERAND_ADDRESS:
4229 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4232 case RELOAD_FOR_OPADDR_ADDR:
4233 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4236 case RELOAD_FOR_OTHER_ADDRESS:
4237 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4240 case RELOAD_FOR_INPUT:
4241 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4244 case RELOAD_FOR_OUTPUT:
4245 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4248 case RELOAD_FOR_INSN:
4249 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4253 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4257 /* Similarly, but show REGNO is no longer in use for a reload. */
4260 clear_reload_reg_in_use (regno, opnum, type, mode)
4263 enum reload_type type;
4264 enum machine_mode mode;
4266 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4267 unsigned int start_regno, end_regno, r;
4269 /* A complication is that for some reload types, inheritance might
4270 allow multiple reloads of the same types to share a reload register.
4271 We set check_opnum if we have to check only reloads with the same
4272 operand number, and check_any if we have to check all reloads. */
4273 int check_opnum = 0;
4275 HARD_REG_SET *used_in_set;
4280 used_in_set = &reload_reg_used;
4283 case RELOAD_FOR_INPUT_ADDRESS:
4284 used_in_set = &reload_reg_used_in_input_addr[opnum];
4287 case RELOAD_FOR_INPADDR_ADDRESS:
4289 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4292 case RELOAD_FOR_OUTPUT_ADDRESS:
4293 used_in_set = &reload_reg_used_in_output_addr[opnum];
4296 case RELOAD_FOR_OUTADDR_ADDRESS:
4298 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4301 case RELOAD_FOR_OPERAND_ADDRESS:
4302 used_in_set = &reload_reg_used_in_op_addr;
4305 case RELOAD_FOR_OPADDR_ADDR:
4307 used_in_set = &reload_reg_used_in_op_addr_reload;
4310 case RELOAD_FOR_OTHER_ADDRESS:
4311 used_in_set = &reload_reg_used_in_other_addr;
4315 case RELOAD_FOR_INPUT:
4316 used_in_set = &reload_reg_used_in_input[opnum];
4319 case RELOAD_FOR_OUTPUT:
4320 used_in_set = &reload_reg_used_in_output[opnum];
4323 case RELOAD_FOR_INSN:
4324 used_in_set = &reload_reg_used_in_insn;
4329 /* We resolve conflicts with remaining reloads of the same type by
4330 excluding the intervals of of reload registers by them from the
4331 interval of freed reload registers. Since we only keep track of
4332 one set of interval bounds, we might have to exclude somewhat
4333 more than what would be necessary if we used a HARD_REG_SET here.
4334 But this should only happen very infrequently, so there should
4335 be no reason to worry about it. */
4337 start_regno = regno;
4338 end_regno = regno + nregs;
4339 if (check_opnum || check_any)
4341 for (i = n_reloads - 1; i >= 0; i--)
4343 if (rld[i].when_needed == type
4344 && (check_any || rld[i].opnum == opnum)
4347 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4348 unsigned int conflict_end
4350 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4352 /* If there is an overlap with the first to-be-freed register,
4353 adjust the interval start. */
4354 if (conflict_start <= start_regno && conflict_end > start_regno)
4355 start_regno = conflict_end;
4356 /* Otherwise, if there is a conflict with one of the other
4357 to-be-freed registers, adjust the interval end. */
4358 if (conflict_start > start_regno && conflict_start < end_regno)
4359 end_regno = conflict_start;
4364 for (r = start_regno; r < end_regno; r++)
4365 CLEAR_HARD_REG_BIT (*used_in_set, r);
4368 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4369 specified by OPNUM and TYPE. */
4372 reload_reg_free_p (regno, opnum, type)
4375 enum reload_type type;
4379 /* In use for a RELOAD_OTHER means it's not available for anything. */
4380 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4381 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4387 /* In use for anything means we can't use it for RELOAD_OTHER. */
4388 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4389 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4390 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4393 for (i = 0; i < reload_n_operands; i++)
4394 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4395 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4396 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4397 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4398 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4399 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4404 case RELOAD_FOR_INPUT:
4405 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4406 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4409 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4412 /* If it is used for some other input, can't use it. */
4413 for (i = 0; i < reload_n_operands; i++)
4414 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4417 /* If it is used in a later operand's address, can't use it. */
4418 for (i = opnum + 1; i < reload_n_operands; i++)
4419 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4420 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4425 case RELOAD_FOR_INPUT_ADDRESS:
4426 /* Can't use a register if it is used for an input address for this
4427 operand or used as an input in an earlier one. */
4428 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4429 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4432 for (i = 0; i < opnum; i++)
4433 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4438 case RELOAD_FOR_INPADDR_ADDRESS:
4439 /* Can't use a register if it is used for an input address
4440 for this operand or used as an input in an earlier
4442 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4445 for (i = 0; i < opnum; i++)
4446 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4451 case RELOAD_FOR_OUTPUT_ADDRESS:
4452 /* Can't use a register if it is used for an output address for this
4453 operand or used as an output in this or a later operand. Note
4454 that multiple output operands are emitted in reverse order, so
4455 the conflicting ones are those with lower indices. */
4456 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4459 for (i = 0; i <= opnum; i++)
4460 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4465 case RELOAD_FOR_OUTADDR_ADDRESS:
4466 /* Can't use a register if it is used for an output address
4467 for this operand or used as an output in this or a
4468 later operand. Note that multiple output operands are
4469 emitted in reverse order, so the conflicting ones are
4470 those with lower indices. */
4471 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4474 for (i = 0; i <= opnum; i++)
4475 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4480 case RELOAD_FOR_OPERAND_ADDRESS:
4481 for (i = 0; i < reload_n_operands; i++)
4482 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4485 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4486 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4488 case RELOAD_FOR_OPADDR_ADDR:
4489 for (i = 0; i < reload_n_operands; i++)
4490 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4493 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4495 case RELOAD_FOR_OUTPUT:
4496 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4497 outputs, or an operand address for this or an earlier output.
4498 Note that multiple output operands are emitted in reverse order,
4499 so the conflicting ones are those with higher indices. */
4500 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4503 for (i = 0; i < reload_n_operands; i++)
4504 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4507 for (i = opnum; i < reload_n_operands; i++)
4508 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4509 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4514 case RELOAD_FOR_INSN:
4515 for (i = 0; i < reload_n_operands; i++)
4516 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4517 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4520 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4521 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4523 case RELOAD_FOR_OTHER_ADDRESS:
4524 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4529 /* Return 1 if the value in reload reg REGNO, as used by a reload
4530 needed for the part of the insn specified by OPNUM and TYPE,
4531 is still available in REGNO at the end of the insn.
4533 We can assume that the reload reg was already tested for availability
4534 at the time it is needed, and we should not check this again,
4535 in case the reg has already been marked in use. */
4538 reload_reg_reaches_end_p (regno, opnum, type)
4541 enum reload_type type;
4548 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4549 its value must reach the end. */
4552 /* If this use is for part of the insn,
4553 its value reaches if no subsequent part uses the same register.
4554 Just like the above function, don't try to do this with lots
4557 case RELOAD_FOR_OTHER_ADDRESS:
4558 /* Here we check for everything else, since these don't conflict
4559 with anything else and everything comes later. */
4561 for (i = 0; i < reload_n_operands; i++)
4562 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4563 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4564 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4565 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4566 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4567 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4570 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4571 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4572 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4574 case RELOAD_FOR_INPUT_ADDRESS:
4575 case RELOAD_FOR_INPADDR_ADDRESS:
4576 /* Similar, except that we check only for this and subsequent inputs
4577 and the address of only subsequent inputs and we do not need
4578 to check for RELOAD_OTHER objects since they are known not to
4581 for (i = opnum; i < reload_n_operands; i++)
4582 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4585 for (i = opnum + 1; i < reload_n_operands; i++)
4586 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4587 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4590 for (i = 0; i < reload_n_operands; i++)
4591 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4592 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4593 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4596 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4599 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4600 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4601 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4603 case RELOAD_FOR_INPUT:
4604 /* Similar to input address, except we start at the next operand for
4605 both input and input address and we do not check for
4606 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4609 for (i = opnum + 1; i < reload_n_operands; i++)
4610 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4611 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4612 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4615 /* ... fall through ... */
4617 case RELOAD_FOR_OPERAND_ADDRESS:
4618 /* Check outputs and their addresses. */
4620 for (i = 0; i < reload_n_operands; i++)
4621 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4622 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4623 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4626 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4628 case RELOAD_FOR_OPADDR_ADDR:
4629 for (i = 0; i < reload_n_operands; i++)
4630 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4631 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4632 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4635 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4636 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4637 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4639 case RELOAD_FOR_INSN:
4640 /* These conflict with other outputs with RELOAD_OTHER. So
4641 we need only check for output addresses. */
4643 opnum = reload_n_operands;
4645 /* ... fall through ... */
4647 case RELOAD_FOR_OUTPUT:
4648 case RELOAD_FOR_OUTPUT_ADDRESS:
4649 case RELOAD_FOR_OUTADDR_ADDRESS:
4650 /* We already know these can't conflict with a later output. So the
4651 only thing to check are later output addresses.
4652 Note that multiple output operands are emitted in reverse order,
4653 so the conflicting ones are those with lower indices. */
4654 for (i = 0; i < opnum; i++)
4655 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4656 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4665 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4668 This function uses the same algorithm as reload_reg_free_p above. */
4671 reloads_conflict (r1, r2)
4674 enum reload_type r1_type = rld[r1].when_needed;
4675 enum reload_type r2_type = rld[r2].when_needed;
4676 int r1_opnum = rld[r1].opnum;
4677 int r2_opnum = rld[r2].opnum;
4679 /* RELOAD_OTHER conflicts with everything. */
4680 if (r2_type == RELOAD_OTHER)
4683 /* Otherwise, check conflicts differently for each type. */
4687 case RELOAD_FOR_INPUT:
4688 return (r2_type == RELOAD_FOR_INSN
4689 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4690 || r2_type == RELOAD_FOR_OPADDR_ADDR
4691 || r2_type == RELOAD_FOR_INPUT
4692 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4693 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4694 && r2_opnum > r1_opnum));
4696 case RELOAD_FOR_INPUT_ADDRESS:
4697 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4698 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4700 case RELOAD_FOR_INPADDR_ADDRESS:
4701 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4702 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4704 case RELOAD_FOR_OUTPUT_ADDRESS:
4705 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4706 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4708 case RELOAD_FOR_OUTADDR_ADDRESS:
4709 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4710 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4712 case RELOAD_FOR_OPERAND_ADDRESS:
4713 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4714 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4716 case RELOAD_FOR_OPADDR_ADDR:
4717 return (r2_type == RELOAD_FOR_INPUT
4718 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4720 case RELOAD_FOR_OUTPUT:
4721 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4722 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4723 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4724 && r2_opnum >= r1_opnum));
4726 case RELOAD_FOR_INSN:
4727 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4728 || r2_type == RELOAD_FOR_INSN
4729 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4731 case RELOAD_FOR_OTHER_ADDRESS:
4732 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4742 /* Indexed by reload number, 1 if incoming value
4743 inherited from previous insns. */
4744 char reload_inherited[MAX_RELOADS];
4746 /* For an inherited reload, this is the insn the reload was inherited from,
4747 if we know it. Otherwise, this is 0. */
4748 rtx reload_inheritance_insn[MAX_RELOADS];
4750 /* If non-zero, this is a place to get the value of the reload,
4751 rather than using reload_in. */
4752 rtx reload_override_in[MAX_RELOADS];
4754 /* For each reload, the hard register number of the register used,
4755 or -1 if we did not need a register for this reload. */
4756 int reload_spill_index[MAX_RELOADS];
4758 /* Subroutine of free_for_value_p, used to check a single register.
4759 START_REGNO is the starting regno of the full reload register
4760 (possibly comprising multiple hard registers) that we are considering. */
4763 reload_reg_free_for_value_p (start_regno, regno, opnum, type, value, out,
4764 reloadnum, ignore_address_reloads)
4765 int start_regno, regno;
4767 enum reload_type type;
4770 int ignore_address_reloads;
4773 /* Set if we see an input reload that must not share its reload register
4774 with any new earlyclobber, but might otherwise share the reload
4775 register with an output or input-output reload. */
4776 int check_earlyclobber = 0;
4780 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4783 if (out == const0_rtx)
4789 /* We use some pseudo 'time' value to check if the lifetimes of the
4790 new register use would overlap with the one of a previous reload
4791 that is not read-only or uses a different value.
4792 The 'time' used doesn't have to be linear in any shape or form, just
4794 Some reload types use different 'buckets' for each operand.
4795 So there are MAX_RECOG_OPERANDS different time values for each
4797 We compute TIME1 as the time when the register for the prospective
4798 new reload ceases to be live, and TIME2 for each existing
4799 reload as the time when that the reload register of that reload
4801 Where there is little to be gained by exact lifetime calculations,
4802 we just make conservative assumptions, i.e. a longer lifetime;
4803 this is done in the 'default:' cases. */
4806 case RELOAD_FOR_OTHER_ADDRESS:
4807 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4808 time1 = copy ? 0 : 1;
4811 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4813 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4814 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4815 respectively, to the time values for these, we get distinct time
4816 values. To get distinct time values for each operand, we have to
4817 multiply opnum by at least three. We round that up to four because
4818 multiply by four is often cheaper. */
4819 case RELOAD_FOR_INPADDR_ADDRESS:
4820 time1 = opnum * 4 + 2;
4822 case RELOAD_FOR_INPUT_ADDRESS:
4823 time1 = opnum * 4 + 3;
4825 case RELOAD_FOR_INPUT:
4826 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4827 executes (inclusive). */
4828 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4830 case RELOAD_FOR_OPADDR_ADDR:
4832 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4833 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4835 case RELOAD_FOR_OPERAND_ADDRESS:
4836 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4838 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4840 case RELOAD_FOR_OUTADDR_ADDRESS:
4841 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4843 case RELOAD_FOR_OUTPUT_ADDRESS:
4844 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4847 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4850 for (i = 0; i < n_reloads; i++)
4852 rtx reg = rld[i].reg_rtx;
4853 if (reg && GET_CODE (reg) == REG
4854 && ((unsigned) regno - true_regnum (reg)
4855 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned) 1)
4858 rtx other_input = rld[i].in;
4860 /* If the other reload loads the same input value, that
4861 will not cause a conflict only if it's loading it into
4862 the same register. */
4863 if (true_regnum (reg) != start_regno)
4864 other_input = NULL_RTX;
4865 if (! other_input || ! rtx_equal_p (other_input, value)
4866 || rld[i].out || out)
4869 switch (rld[i].when_needed)
4871 case RELOAD_FOR_OTHER_ADDRESS:
4874 case RELOAD_FOR_INPADDR_ADDRESS:
4875 /* find_reloads makes sure that a
4876 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4877 by at most one - the first -
4878 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4879 address reload is inherited, the address address reload
4880 goes away, so we can ignore this conflict. */
4881 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4882 && ignore_address_reloads
4883 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4884 Then the address address is still needed to store
4885 back the new address. */
4886 && ! rld[reloadnum].out)
4888 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4889 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4891 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4892 && ignore_address_reloads
4893 /* Unless we are reloading an auto_inc expression. */
4894 && ! rld[reloadnum].out)
4896 time2 = rld[i].opnum * 4 + 2;
4898 case RELOAD_FOR_INPUT_ADDRESS:
4899 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4900 && ignore_address_reloads
4901 && ! rld[reloadnum].out)
4903 time2 = rld[i].opnum * 4 + 3;
4905 case RELOAD_FOR_INPUT:
4906 time2 = rld[i].opnum * 4 + 4;
4907 check_earlyclobber = 1;
4909 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4910 == MAX_RECOG_OPERAND * 4 */
4911 case RELOAD_FOR_OPADDR_ADDR:
4912 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4913 && ignore_address_reloads
4914 && ! rld[reloadnum].out)
4916 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4918 case RELOAD_FOR_OPERAND_ADDRESS:
4919 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4920 check_earlyclobber = 1;
4922 case RELOAD_FOR_INSN:
4923 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4925 case RELOAD_FOR_OUTPUT:
4926 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4927 instruction is executed. */
4928 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4930 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4931 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4933 case RELOAD_FOR_OUTADDR_ADDRESS:
4934 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4935 && ignore_address_reloads
4936 && ! rld[reloadnum].out)
4938 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4940 case RELOAD_FOR_OUTPUT_ADDRESS:
4941 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4944 /* If there is no conflict in the input part, handle this
4945 like an output reload. */
4946 if (! rld[i].in || rtx_equal_p (other_input, value))
4948 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4949 /* Earlyclobbered outputs must conflict with inputs. */
4950 if (earlyclobber_operand_p (rld[i].out))
4951 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4956 /* RELOAD_OTHER might be live beyond instruction execution,
4957 but this is not obvious when we set time2 = 1. So check
4958 here if there might be a problem with the new reload
4959 clobbering the register used by the RELOAD_OTHER. */
4967 && (! rld[i].in || rld[i].out
4968 || ! rtx_equal_p (other_input, value)))
4969 || (out && rld[reloadnum].out_reg
4970 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4976 /* Earlyclobbered outputs must conflict with inputs. */
4977 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4983 /* Return 1 if the value in reload reg REGNO, as used by a reload
4984 needed for the part of the insn specified by OPNUM and TYPE,
4985 may be used to load VALUE into it.
4987 MODE is the mode in which the register is used, this is needed to
4988 determine how many hard regs to test.
4990 Other read-only reloads with the same value do not conflict
4991 unless OUT is non-zero and these other reloads have to live while
4992 output reloads live.
4993 If OUT is CONST0_RTX, this is a special case: it means that the
4994 test should not be for using register REGNO as reload register, but
4995 for copying from register REGNO into the reload register.
4997 RELOADNUM is the number of the reload we want to load this value for;
4998 a reload does not conflict with itself.
5000 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5001 reloads that load an address for the very reload we are considering.
5003 The caller has to make sure that there is no conflict with the return
5007 free_for_value_p (regno, mode, opnum, type, value, out, reloadnum,
5008 ignore_address_reloads)
5010 enum machine_mode mode;
5012 enum reload_type type;
5015 int ignore_address_reloads;
5017 int nregs = HARD_REGNO_NREGS (regno, mode);
5019 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5020 value, out, reloadnum,
5021 ignore_address_reloads))
5026 /* Determine whether the reload reg X overlaps any rtx'es used for
5027 overriding inheritance. Return nonzero if so. */
5030 conflicts_with_override (x)
5034 for (i = 0; i < n_reloads; i++)
5035 if (reload_override_in[i]
5036 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5041 /* Give an error message saying we failed to find a reload for INSN,
5042 and clear out reload R. */
5044 failed_reload (insn, r)
5048 if (asm_noperands (PATTERN (insn)) < 0)
5049 /* It's the compiler's fault. */
5050 fatal_insn ("could not find a spill register", insn);
5052 /* It's the user's fault; the operand's mode and constraint
5053 don't match. Disable this reload so we don't crash in final. */
5054 error_for_asm (insn,
5055 "`asm' operand constraint incompatible with operand size");
5059 rld[r].optional = 1;
5060 rld[r].secondary_p = 1;
5063 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5064 for reload R. If it's valid, get an rtx for it. Return nonzero if
5067 set_reload_reg (i, r)
5071 rtx reg = spill_reg_rtx[i];
5073 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5074 spill_reg_rtx[i] = reg
5075 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5077 regno = true_regnum (reg);
5079 /* Detect when the reload reg can't hold the reload mode.
5080 This used to be one `if', but Sequent compiler can't handle that. */
5081 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5083 enum machine_mode test_mode = VOIDmode;
5085 test_mode = GET_MODE (rld[r].in);
5086 /* If rld[r].in has VOIDmode, it means we will load it
5087 in whatever mode the reload reg has: to wit, rld[r].mode.
5088 We have already tested that for validity. */
5089 /* Aside from that, we need to test that the expressions
5090 to reload from or into have modes which are valid for this
5091 reload register. Otherwise the reload insns would be invalid. */
5092 if (! (rld[r].in != 0 && test_mode != VOIDmode
5093 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5094 if (! (rld[r].out != 0
5095 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5097 /* The reg is OK. */
5100 /* Mark as in use for this insn the reload regs we use
5102 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5103 rld[r].when_needed, rld[r].mode);
5105 rld[r].reg_rtx = reg;
5106 reload_spill_index[r] = spill_regs[i];
5113 /* Find a spill register to use as a reload register for reload R.
5114 LAST_RELOAD is non-zero if this is the last reload for the insn being
5117 Set rld[R].reg_rtx to the register allocated.
5119 We return 1 if successful, or 0 if we couldn't find a spill reg and
5120 we didn't change anything. */
5123 allocate_reload_reg (chain, r, last_reload)
5124 struct insn_chain *chain ATTRIBUTE_UNUSED;
5130 /* If we put this reload ahead, thinking it is a group,
5131 then insist on finding a group. Otherwise we can grab a
5132 reg that some other reload needs.
5133 (That can happen when we have a 68000 DATA_OR_FP_REG
5134 which is a group of data regs or one fp reg.)
5135 We need not be so restrictive if there are no more reloads
5138 ??? Really it would be nicer to have smarter handling
5139 for that kind of reg class, where a problem like this is normal.
5140 Perhaps those classes should be avoided for reloading
5141 by use of more alternatives. */
5143 int force_group = rld[r].nregs > 1 && ! last_reload;
5145 /* If we want a single register and haven't yet found one,
5146 take any reg in the right class and not in use.
5147 If we want a consecutive group, here is where we look for it.
5149 We use two passes so we can first look for reload regs to
5150 reuse, which are already in use for other reloads in this insn,
5151 and only then use additional registers.
5152 I think that maximizing reuse is needed to make sure we don't
5153 run out of reload regs. Suppose we have three reloads, and
5154 reloads A and B can share regs. These need two regs.
5155 Suppose A and B are given different regs.
5156 That leaves none for C. */
5157 for (pass = 0; pass < 2; pass++)
5159 /* I is the index in spill_regs.
5160 We advance it round-robin between insns to use all spill regs
5161 equally, so that inherited reloads have a chance
5162 of leapfrogging each other. */
5166 for (count = 0; count < n_spills; count++)
5168 int class = (int) rld[r].class;
5174 regnum = spill_regs[i];
5176 if ((reload_reg_free_p (regnum, rld[r].opnum,
5179 /* We check reload_reg_used to make sure we
5180 don't clobber the return register. */
5181 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5182 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5183 rld[r].when_needed, rld[r].in,
5185 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5186 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5187 /* Look first for regs to share, then for unshared. But
5188 don't share regs used for inherited reloads; they are
5189 the ones we want to preserve. */
5191 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5193 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5196 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5197 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5198 (on 68000) got us two FP regs. If NR is 1,
5199 we would reject both of them. */
5202 /* If we need only one reg, we have already won. */
5205 /* But reject a single reg if we demand a group. */
5210 /* Otherwise check that as many consecutive regs as we need
5211 are available here. */
5214 int regno = regnum + nr - 1;
5215 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5216 && spill_reg_order[regno] >= 0
5217 && reload_reg_free_p (regno, rld[r].opnum,
5218 rld[r].when_needed)))
5227 /* If we found something on pass 1, omit pass 2. */
5228 if (count < n_spills)
5232 /* We should have found a spill register by now. */
5233 if (count >= n_spills)
5236 /* I is the index in SPILL_REG_RTX of the reload register we are to
5237 allocate. Get an rtx for it and find its register number. */
5239 return set_reload_reg (i, r);
5242 /* Initialize all the tables needed to allocate reload registers.
5243 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5244 is the array we use to restore the reg_rtx field for every reload. */
5247 choose_reload_regs_init (chain, save_reload_reg_rtx)
5248 struct insn_chain *chain;
5249 rtx *save_reload_reg_rtx;
5253 for (i = 0; i < n_reloads; i++)
5254 rld[i].reg_rtx = save_reload_reg_rtx[i];
5256 memset (reload_inherited, 0, MAX_RELOADS);
5257 memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5258 memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5260 CLEAR_HARD_REG_SET (reload_reg_used);
5261 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5262 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5263 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5264 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5265 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5267 CLEAR_HARD_REG_SET (reg_used_in_insn);
5270 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5271 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5272 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5273 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5274 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5275 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5278 for (i = 0; i < reload_n_operands; i++)
5280 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5281 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5282 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5283 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5284 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5285 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5288 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5290 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5292 for (i = 0; i < n_reloads; i++)
5293 /* If we have already decided to use a certain register,
5294 don't use it in another way. */
5296 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5297 rld[i].when_needed, rld[i].mode);
5300 /* Assign hard reg targets for the pseudo-registers we must reload
5301 into hard regs for this insn.
5302 Also output the instructions to copy them in and out of the hard regs.
5304 For machines with register classes, we are responsible for
5305 finding a reload reg in the proper class. */
5308 choose_reload_regs (chain)
5309 struct insn_chain *chain;
5311 rtx insn = chain->insn;
5313 unsigned int max_group_size = 1;
5314 enum reg_class group_class = NO_REGS;
5315 int pass, win, inheritance;
5317 rtx save_reload_reg_rtx[MAX_RELOADS];
5319 /* In order to be certain of getting the registers we need,
5320 we must sort the reloads into order of increasing register class.
5321 Then our grabbing of reload registers will parallel the process
5322 that provided the reload registers.
5324 Also note whether any of the reloads wants a consecutive group of regs.
5325 If so, record the maximum size of the group desired and what
5326 register class contains all the groups needed by this insn. */
5328 for (j = 0; j < n_reloads; j++)
5330 reload_order[j] = j;
5331 reload_spill_index[j] = -1;
5333 if (rld[j].nregs > 1)
5335 max_group_size = MAX (rld[j].nregs, max_group_size);
5337 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5340 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5344 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5346 /* If -O, try first with inheritance, then turning it off.
5347 If not -O, don't do inheritance.
5348 Using inheritance when not optimizing leads to paradoxes
5349 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5350 because one side of the comparison might be inherited. */
5352 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5354 choose_reload_regs_init (chain, save_reload_reg_rtx);
5356 /* Process the reloads in order of preference just found.
5357 Beyond this point, subregs can be found in reload_reg_rtx.
5359 This used to look for an existing reloaded home for all of the
5360 reloads, and only then perform any new reloads. But that could lose
5361 if the reloads were done out of reg-class order because a later
5362 reload with a looser constraint might have an old home in a register
5363 needed by an earlier reload with a tighter constraint.
5365 To solve this, we make two passes over the reloads, in the order
5366 described above. In the first pass we try to inherit a reload
5367 from a previous insn. If there is a later reload that needs a
5368 class that is a proper subset of the class being processed, we must
5369 also allocate a spill register during the first pass.
5371 Then make a second pass over the reloads to allocate any reloads
5372 that haven't been given registers yet. */
5374 for (j = 0; j < n_reloads; j++)
5376 int r = reload_order[j];
5377 rtx search_equiv = NULL_RTX;
5379 /* Ignore reloads that got marked inoperative. */
5380 if (rld[r].out == 0 && rld[r].in == 0
5381 && ! rld[r].secondary_p)
5384 /* If find_reloads chose to use reload_in or reload_out as a reload
5385 register, we don't need to chose one. Otherwise, try even if it
5386 found one since we might save an insn if we find the value lying
5388 Try also when reload_in is a pseudo without a hard reg. */
5389 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5390 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5391 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5392 && GET_CODE (rld[r].in) != MEM
5393 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5396 #if 0 /* No longer needed for correct operation.
5397 It might give better code, or might not; worth an experiment? */
5398 /* If this is an optional reload, we can't inherit from earlier insns
5399 until we are sure that any non-optional reloads have been allocated.
5400 The following code takes advantage of the fact that optional reloads
5401 are at the end of reload_order. */
5402 if (rld[r].optional != 0)
5403 for (i = 0; i < j; i++)
5404 if ((rld[reload_order[i]].out != 0
5405 || rld[reload_order[i]].in != 0
5406 || rld[reload_order[i]].secondary_p)
5407 && ! rld[reload_order[i]].optional
5408 && rld[reload_order[i]].reg_rtx == 0)
5409 allocate_reload_reg (chain, reload_order[i], 0);
5412 /* First see if this pseudo is already available as reloaded
5413 for a previous insn. We cannot try to inherit for reloads
5414 that are smaller than the maximum number of registers needed
5415 for groups unless the register we would allocate cannot be used
5418 We could check here to see if this is a secondary reload for
5419 an object that is already in a register of the desired class.
5420 This would avoid the need for the secondary reload register.
5421 But this is complex because we can't easily determine what
5422 objects might want to be loaded via this reload. So let a
5423 register be allocated here. In `emit_reload_insns' we suppress
5424 one of the loads in the case described above. */
5430 enum machine_mode mode = VOIDmode;
5434 else if (GET_CODE (rld[r].in) == REG)
5436 regno = REGNO (rld[r].in);
5437 mode = GET_MODE (rld[r].in);
5439 else if (GET_CODE (rld[r].in_reg) == REG)
5441 regno = REGNO (rld[r].in_reg);
5442 mode = GET_MODE (rld[r].in_reg);
5444 else if (GET_CODE (rld[r].in_reg) == SUBREG
5445 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5447 byte = SUBREG_BYTE (rld[r].in_reg);
5448 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5449 if (regno < FIRST_PSEUDO_REGISTER)
5450 regno = subreg_regno (rld[r].in_reg);
5451 mode = GET_MODE (rld[r].in_reg);
5454 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5455 || GET_CODE (rld[r].in_reg) == PRE_DEC
5456 || GET_CODE (rld[r].in_reg) == POST_INC
5457 || GET_CODE (rld[r].in_reg) == POST_DEC)
5458 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5460 regno = REGNO (XEXP (rld[r].in_reg, 0));
5461 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5462 rld[r].out = rld[r].in;
5466 /* This won't work, since REGNO can be a pseudo reg number.
5467 Also, it takes much more hair to keep track of all the things
5468 that can invalidate an inherited reload of part of a pseudoreg. */
5469 else if (GET_CODE (rld[r].in) == SUBREG
5470 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5471 regno = subreg_regno (rld[r].in);
5474 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5476 enum reg_class class = rld[r].class, last_class;
5477 rtx last_reg = reg_last_reload_reg[regno];
5478 enum machine_mode need_mode;
5480 i = REGNO (last_reg);
5481 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5482 last_class = REGNO_REG_CLASS (i);
5488 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5489 GET_MODE_CLASS (mode));
5492 #ifdef CLASS_CANNOT_CHANGE_MODE
5494 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], i)
5495 ? ! CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (last_reg),
5497 : (GET_MODE_SIZE (GET_MODE (last_reg))
5498 >= GET_MODE_SIZE (need_mode)))
5500 (GET_MODE_SIZE (GET_MODE (last_reg))
5501 >= GET_MODE_SIZE (need_mode))
5503 && reg_reloaded_contents[i] == regno
5504 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5505 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5506 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5507 /* Even if we can't use this register as a reload
5508 register, we might use it for reload_override_in,
5509 if copying it to the desired class is cheap
5511 || ((REGISTER_MOVE_COST (mode, last_class, class)
5512 < MEMORY_MOVE_COST (mode, class, 1))
5513 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5514 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5518 #ifdef SECONDARY_MEMORY_NEEDED
5519 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5524 && (rld[r].nregs == max_group_size
5525 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5527 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5528 rld[r].when_needed, rld[r].in,
5531 /* If a group is needed, verify that all the subsequent
5532 registers still have their values intact. */
5533 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5536 for (k = 1; k < nr; k++)
5537 if (reg_reloaded_contents[i + k] != regno
5538 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5546 last_reg = (GET_MODE (last_reg) == mode
5547 ? last_reg : gen_rtx_REG (mode, i));
5550 for (k = 0; k < nr; k++)
5551 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5554 /* We found a register that contains the
5555 value we need. If this register is the
5556 same as an `earlyclobber' operand of the
5557 current insn, just mark it as a place to
5558 reload from since we can't use it as the
5559 reload register itself. */
5561 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5562 if (reg_overlap_mentioned_for_reload_p
5563 (reg_last_reload_reg[regno],
5564 reload_earlyclobbers[i1]))
5567 if (i1 != n_earlyclobbers
5568 || ! (free_for_value_p (i, rld[r].mode,
5570 rld[r].when_needed, rld[r].in,
5572 /* Don't use it if we'd clobber a pseudo reg. */
5573 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5575 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5576 /* Don't clobber the frame pointer. */
5577 || (i == HARD_FRAME_POINTER_REGNUM
5578 && frame_pointer_needed
5580 /* Don't really use the inherited spill reg
5581 if we need it wider than we've got it. */
5582 || (GET_MODE_SIZE (rld[r].mode)
5583 > GET_MODE_SIZE (mode))
5586 /* If find_reloads chose reload_out as reload
5587 register, stay with it - that leaves the
5588 inherited register for subsequent reloads. */
5589 || (rld[r].out && rld[r].reg_rtx
5590 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5592 if (! rld[r].optional)
5594 reload_override_in[r] = last_reg;
5595 reload_inheritance_insn[r]
5596 = reg_reloaded_insn[i];
5602 /* We can use this as a reload reg. */
5603 /* Mark the register as in use for this part of
5605 mark_reload_reg_in_use (i,
5609 rld[r].reg_rtx = last_reg;
5610 reload_inherited[r] = 1;
5611 reload_inheritance_insn[r]
5612 = reg_reloaded_insn[i];
5613 reload_spill_index[r] = i;
5614 for (k = 0; k < nr; k++)
5615 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5623 /* Here's another way to see if the value is already lying around. */
5626 && ! reload_inherited[r]
5628 && (CONSTANT_P (rld[r].in)
5629 || GET_CODE (rld[r].in) == PLUS
5630 || GET_CODE (rld[r].in) == REG
5631 || GET_CODE (rld[r].in) == MEM)
5632 && (rld[r].nregs == max_group_size
5633 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5634 search_equiv = rld[r].in;
5635 /* If this is an output reload from a simple move insn, look
5636 if an equivalence for the input is available. */
5637 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5639 rtx set = single_set (insn);
5642 && rtx_equal_p (rld[r].out, SET_DEST (set))
5643 && CONSTANT_P (SET_SRC (set)))
5644 search_equiv = SET_SRC (set);
5650 = find_equiv_reg (search_equiv, insn, rld[r].class,
5651 -1, NULL, 0, rld[r].mode);
5656 if (GET_CODE (equiv) == REG)
5657 regno = REGNO (equiv);
5658 else if (GET_CODE (equiv) == SUBREG)
5660 /* This must be a SUBREG of a hard register.
5661 Make a new REG since this might be used in an
5662 address and not all machines support SUBREGs
5664 regno = subreg_regno (equiv);
5665 equiv = gen_rtx_REG (rld[r].mode, regno);
5671 /* If we found a spill reg, reject it unless it is free
5672 and of the desired class. */
5674 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5675 && ! free_for_value_p (regno, rld[r].mode,
5676 rld[r].opnum, rld[r].when_needed,
5677 rld[r].in, rld[r].out, r, 1))
5678 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5682 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5685 /* We found a register that contains the value we need.
5686 If this register is the same as an `earlyclobber' operand
5687 of the current insn, just mark it as a place to reload from
5688 since we can't use it as the reload register itself. */
5691 for (i = 0; i < n_earlyclobbers; i++)
5692 if (reg_overlap_mentioned_for_reload_p (equiv,
5693 reload_earlyclobbers[i]))
5695 if (! rld[r].optional)
5696 reload_override_in[r] = equiv;
5701 /* If the equiv register we have found is explicitly clobbered
5702 in the current insn, it depends on the reload type if we
5703 can use it, use it for reload_override_in, or not at all.
5704 In particular, we then can't use EQUIV for a
5705 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5709 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5710 switch (rld[r].when_needed)
5712 case RELOAD_FOR_OTHER_ADDRESS:
5713 case RELOAD_FOR_INPADDR_ADDRESS:
5714 case RELOAD_FOR_INPUT_ADDRESS:
5715 case RELOAD_FOR_OPADDR_ADDR:
5718 case RELOAD_FOR_INPUT:
5719 case RELOAD_FOR_OPERAND_ADDRESS:
5720 if (! rld[r].optional)
5721 reload_override_in[r] = equiv;
5727 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5728 switch (rld[r].when_needed)
5730 case RELOAD_FOR_OTHER_ADDRESS:
5731 case RELOAD_FOR_INPADDR_ADDRESS:
5732 case RELOAD_FOR_INPUT_ADDRESS:
5733 case RELOAD_FOR_OPADDR_ADDR:
5734 case RELOAD_FOR_OPERAND_ADDRESS:
5735 case RELOAD_FOR_INPUT:
5738 if (! rld[r].optional)
5739 reload_override_in[r] = equiv;
5747 /* If we found an equivalent reg, say no code need be generated
5748 to load it, and use it as our reload reg. */
5750 && (regno != HARD_FRAME_POINTER_REGNUM
5751 || !frame_pointer_needed))
5753 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5755 rld[r].reg_rtx = equiv;
5756 reload_inherited[r] = 1;
5758 /* If reg_reloaded_valid is not set for this register,
5759 there might be a stale spill_reg_store lying around.
5760 We must clear it, since otherwise emit_reload_insns
5761 might delete the store. */
5762 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5763 spill_reg_store[regno] = NULL_RTX;
5764 /* If any of the hard registers in EQUIV are spill
5765 registers, mark them as in use for this insn. */
5766 for (k = 0; k < nr; k++)
5768 i = spill_reg_order[regno + k];
5771 mark_reload_reg_in_use (regno, rld[r].opnum,
5774 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5781 /* If we found a register to use already, or if this is an optional
5782 reload, we are done. */
5783 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5787 /* No longer needed for correct operation. Might or might
5788 not give better code on the average. Want to experiment? */
5790 /* See if there is a later reload that has a class different from our
5791 class that intersects our class or that requires less register
5792 than our reload. If so, we must allocate a register to this
5793 reload now, since that reload might inherit a previous reload
5794 and take the only available register in our class. Don't do this
5795 for optional reloads since they will force all previous reloads
5796 to be allocated. Also don't do this for reloads that have been
5799 for (i = j + 1; i < n_reloads; i++)
5801 int s = reload_order[i];
5803 if ((rld[s].in == 0 && rld[s].out == 0
5804 && ! rld[s].secondary_p)
5808 if ((rld[s].class != rld[r].class
5809 && reg_classes_intersect_p (rld[r].class,
5811 || rld[s].nregs < rld[r].nregs)
5818 allocate_reload_reg (chain, r, j == n_reloads - 1);
5822 /* Now allocate reload registers for anything non-optional that
5823 didn't get one yet. */
5824 for (j = 0; j < n_reloads; j++)
5826 int r = reload_order[j];
5828 /* Ignore reloads that got marked inoperative. */
5829 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5832 /* Skip reloads that already have a register allocated or are
5834 if (rld[r].reg_rtx != 0 || rld[r].optional)
5837 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5841 /* If that loop got all the way, we have won. */
5848 /* Loop around and try without any inheritance. */
5853 /* First undo everything done by the failed attempt
5854 to allocate with inheritance. */
5855 choose_reload_regs_init (chain, save_reload_reg_rtx);
5857 /* Some sanity tests to verify that the reloads found in the first
5858 pass are identical to the ones we have now. */
5859 if (chain->n_reloads != n_reloads)
5862 for (i = 0; i < n_reloads; i++)
5864 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5866 if (chain->rld[i].when_needed != rld[i].when_needed)
5868 for (j = 0; j < n_spills; j++)
5869 if (spill_regs[j] == chain->rld[i].regno)
5870 if (! set_reload_reg (j, i))
5871 failed_reload (chain->insn, i);
5875 /* If we thought we could inherit a reload, because it seemed that
5876 nothing else wanted the same reload register earlier in the insn,
5877 verify that assumption, now that all reloads have been assigned.
5878 Likewise for reloads where reload_override_in has been set. */
5880 /* If doing expensive optimizations, do one preliminary pass that doesn't
5881 cancel any inheritance, but removes reloads that have been needed only
5882 for reloads that we know can be inherited. */
5883 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5885 for (j = 0; j < n_reloads; j++)
5887 int r = reload_order[j];
5889 if (reload_inherited[r] && rld[r].reg_rtx)
5890 check_reg = rld[r].reg_rtx;
5891 else if (reload_override_in[r]
5892 && (GET_CODE (reload_override_in[r]) == REG
5893 || GET_CODE (reload_override_in[r]) == SUBREG))
5894 check_reg = reload_override_in[r];
5897 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5898 rld[r].opnum, rld[r].when_needed, rld[r].in,
5899 (reload_inherited[r]
5900 ? rld[r].out : const0_rtx),
5905 reload_inherited[r] = 0;
5906 reload_override_in[r] = 0;
5908 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5909 reload_override_in, then we do not need its related
5910 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5911 likewise for other reload types.
5912 We handle this by removing a reload when its only replacement
5913 is mentioned in reload_in of the reload we are going to inherit.
5914 A special case are auto_inc expressions; even if the input is
5915 inherited, we still need the address for the output. We can
5916 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5917 If we succeeded removing some reload and we are doing a preliminary
5918 pass just to remove such reloads, make another pass, since the
5919 removal of one reload might allow us to inherit another one. */
5921 && rld[r].out != rld[r].in
5922 && remove_address_replacements (rld[r].in) && pass)
5927 /* Now that reload_override_in is known valid,
5928 actually override reload_in. */
5929 for (j = 0; j < n_reloads; j++)
5930 if (reload_override_in[j])
5931 rld[j].in = reload_override_in[j];
5933 /* If this reload won't be done because it has been cancelled or is
5934 optional and not inherited, clear reload_reg_rtx so other
5935 routines (such as subst_reloads) don't get confused. */
5936 for (j = 0; j < n_reloads; j++)
5937 if (rld[j].reg_rtx != 0
5938 && ((rld[j].optional && ! reload_inherited[j])
5939 || (rld[j].in == 0 && rld[j].out == 0
5940 && ! rld[j].secondary_p)))
5942 int regno = true_regnum (rld[j].reg_rtx);
5944 if (spill_reg_order[regno] >= 0)
5945 clear_reload_reg_in_use (regno, rld[j].opnum,
5946 rld[j].when_needed, rld[j].mode);
5948 reload_spill_index[j] = -1;
5951 /* Record which pseudos and which spill regs have output reloads. */
5952 for (j = 0; j < n_reloads; j++)
5954 int r = reload_order[j];
5956 i = reload_spill_index[r];
5958 /* I is nonneg if this reload uses a register.
5959 If rld[r].reg_rtx is 0, this is an optional reload
5960 that we opted to ignore. */
5961 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5962 && rld[r].reg_rtx != 0)
5964 int nregno = REGNO (rld[r].out_reg);
5967 if (nregno < FIRST_PSEUDO_REGISTER)
5968 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5971 reg_has_output_reload[nregno + nr] = 1;
5975 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5977 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5980 if (rld[r].when_needed != RELOAD_OTHER
5981 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5982 && rld[r].when_needed != RELOAD_FOR_INSN)
5988 /* Deallocate the reload register for reload R. This is called from
5989 remove_address_replacements. */
5992 deallocate_reload_reg (r)
5997 if (! rld[r].reg_rtx)
5999 regno = true_regnum (rld[r].reg_rtx);
6001 if (spill_reg_order[regno] >= 0)
6002 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6004 reload_spill_index[r] = -1;
6007 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
6008 reloads of the same item for fear that we might not have enough reload
6009 registers. However, normally they will get the same reload register
6010 and hence actually need not be loaded twice.
6012 Here we check for the most common case of this phenomenon: when we have
6013 a number of reloads for the same object, each of which were allocated
6014 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6015 reload, and is not modified in the insn itself. If we find such,
6016 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6017 This will not increase the number of spill registers needed and will
6018 prevent redundant code. */
6021 merge_assigned_reloads (insn)
6026 /* Scan all the reloads looking for ones that only load values and
6027 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6028 assigned and not modified by INSN. */
6030 for (i = 0; i < n_reloads; i++)
6032 int conflicting_input = 0;
6033 int max_input_address_opnum = -1;
6034 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6036 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6037 || rld[i].out != 0 || rld[i].reg_rtx == 0
6038 || reg_set_p (rld[i].reg_rtx, insn))
6041 /* Look at all other reloads. Ensure that the only use of this
6042 reload_reg_rtx is in a reload that just loads the same value
6043 as we do. Note that any secondary reloads must be of the identical
6044 class since the values, modes, and result registers are the
6045 same, so we need not do anything with any secondary reloads. */
6047 for (j = 0; j < n_reloads; j++)
6049 if (i == j || rld[j].reg_rtx == 0
6050 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6054 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6055 && rld[j].opnum > max_input_address_opnum)
6056 max_input_address_opnum = rld[j].opnum;
6058 /* If the reload regs aren't exactly the same (e.g, different modes)
6059 or if the values are different, we can't merge this reload.
6060 But if it is an input reload, we might still merge
6061 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6063 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6064 || rld[j].out != 0 || rld[j].in == 0
6065 || ! rtx_equal_p (rld[i].in, rld[j].in))
6067 if (rld[j].when_needed != RELOAD_FOR_INPUT
6068 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6069 || rld[i].opnum > rld[j].opnum)
6070 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6072 conflicting_input = 1;
6073 if (min_conflicting_input_opnum > rld[j].opnum)
6074 min_conflicting_input_opnum = rld[j].opnum;
6078 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6079 we, in fact, found any matching reloads. */
6082 && max_input_address_opnum <= min_conflicting_input_opnum)
6084 for (j = 0; j < n_reloads; j++)
6085 if (i != j && rld[j].reg_rtx != 0
6086 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6087 && (! conflicting_input
6088 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6089 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6091 rld[i].when_needed = RELOAD_OTHER;
6093 reload_spill_index[j] = -1;
6094 transfer_replacements (i, j);
6097 /* If this is now RELOAD_OTHER, look for any reloads that load
6098 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6099 if they were for inputs, RELOAD_OTHER for outputs. Note that
6100 this test is equivalent to looking for reloads for this operand
6103 if (rld[i].when_needed == RELOAD_OTHER)
6104 for (j = 0; j < n_reloads; j++)
6106 && rld[j].when_needed != RELOAD_OTHER
6107 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6110 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6111 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6112 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6117 /* These arrays are filled by emit_reload_insns and its subroutines. */
6118 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6119 static rtx other_input_address_reload_insns = 0;
6120 static rtx other_input_reload_insns = 0;
6121 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6122 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6123 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6124 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6125 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6126 static rtx operand_reload_insns = 0;
6127 static rtx other_operand_reload_insns = 0;
6128 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6130 /* Values to be put in spill_reg_store are put here first. */
6131 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6132 static HARD_REG_SET reg_reloaded_died;
6134 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6135 has the number J. OLD contains the value to be used as input. */
6138 emit_input_reload_insns (chain, rl, old, j)
6139 struct insn_chain *chain;
6144 rtx insn = chain->insn;
6145 rtx reloadreg = rl->reg_rtx;
6146 rtx oldequiv_reg = 0;
6149 enum machine_mode mode;
6152 /* Determine the mode to reload in.
6153 This is very tricky because we have three to choose from.
6154 There is the mode the insn operand wants (rl->inmode).
6155 There is the mode of the reload register RELOADREG.
6156 There is the intrinsic mode of the operand, which we could find
6157 by stripping some SUBREGs.
6158 It turns out that RELOADREG's mode is irrelevant:
6159 we can change that arbitrarily.
6161 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6162 then the reload reg may not support QImode moves, so use SImode.
6163 If foo is in memory due to spilling a pseudo reg, this is safe,
6164 because the QImode value is in the least significant part of a
6165 slot big enough for a SImode. If foo is some other sort of
6166 memory reference, then it is impossible to reload this case,
6167 so previous passes had better make sure this never happens.
6169 Then consider a one-word union which has SImode and one of its
6170 members is a float, being fetched as (SUBREG:SF union:SI).
6171 We must fetch that as SFmode because we could be loading into
6172 a float-only register. In this case OLD's mode is correct.
6174 Consider an immediate integer: it has VOIDmode. Here we need
6175 to get a mode from something else.
6177 In some cases, there is a fourth mode, the operand's
6178 containing mode. If the insn specifies a containing mode for
6179 this operand, it overrides all others.
6181 I am not sure whether the algorithm here is always right,
6182 but it does the right things in those cases. */
6184 mode = GET_MODE (old);
6185 if (mode == VOIDmode)
6188 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6189 /* If we need a secondary register for this operation, see if
6190 the value is already in a register in that class. Don't
6191 do this if the secondary register will be used as a scratch
6194 if (rl->secondary_in_reload >= 0
6195 && rl->secondary_in_icode == CODE_FOR_nothing
6198 = find_equiv_reg (old, insn,
6199 rld[rl->secondary_in_reload].class,
6203 /* If reloading from memory, see if there is a register
6204 that already holds the same value. If so, reload from there.
6205 We can pass 0 as the reload_reg_p argument because
6206 any other reload has either already been emitted,
6207 in which case find_equiv_reg will see the reload-insn,
6208 or has yet to be emitted, in which case it doesn't matter
6209 because we will use this equiv reg right away. */
6211 if (oldequiv == 0 && optimize
6212 && (GET_CODE (old) == MEM
6213 || (GET_CODE (old) == REG
6214 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6215 && reg_renumber[REGNO (old)] < 0)))
6216 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6220 unsigned int regno = true_regnum (oldequiv);
6222 /* Don't use OLDEQUIV if any other reload changes it at an
6223 earlier stage of this insn or at this stage. */
6224 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6225 rl->in, const0_rtx, j, 0))
6228 /* If it is no cheaper to copy from OLDEQUIV into the
6229 reload register than it would be to move from memory,
6230 don't use it. Likewise, if we need a secondary register
6234 && ((REGNO_REG_CLASS (regno) != rl->class
6235 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6237 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6238 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6239 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6243 #ifdef SECONDARY_MEMORY_NEEDED
6244 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6252 /* delete_output_reload is only invoked properly if old contains
6253 the original pseudo register. Since this is replaced with a
6254 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6255 find the pseudo in RELOAD_IN_REG. */
6257 && reload_override_in[j]
6258 && GET_CODE (rl->in_reg) == REG)
6265 else if (GET_CODE (oldequiv) == REG)
6266 oldequiv_reg = oldequiv;
6267 else if (GET_CODE (oldequiv) == SUBREG)
6268 oldequiv_reg = SUBREG_REG (oldequiv);
6270 /* If we are reloading from a register that was recently stored in
6271 with an output-reload, see if we can prove there was
6272 actually no need to store the old value in it. */
6274 if (optimize && GET_CODE (oldequiv) == REG
6275 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6276 && spill_reg_store[REGNO (oldequiv)]
6277 && GET_CODE (old) == REG
6278 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6279 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6281 delete_output_reload (insn, j, REGNO (oldequiv));
6283 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6284 then load RELOADREG from OLDEQUIV. Note that we cannot use
6285 gen_lowpart_common since it can do the wrong thing when
6286 RELOADREG has a multi-word mode. Note that RELOADREG
6287 must always be a REG here. */
6289 if (GET_MODE (reloadreg) != mode)
6290 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6291 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6292 oldequiv = SUBREG_REG (oldequiv);
6293 if (GET_MODE (oldequiv) != VOIDmode
6294 && mode != GET_MODE (oldequiv))
6295 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6297 /* Switch to the right place to emit the reload insns. */
6298 switch (rl->when_needed)
6301 where = &other_input_reload_insns;
6303 case RELOAD_FOR_INPUT:
6304 where = &input_reload_insns[rl->opnum];
6306 case RELOAD_FOR_INPUT_ADDRESS:
6307 where = &input_address_reload_insns[rl->opnum];
6309 case RELOAD_FOR_INPADDR_ADDRESS:
6310 where = &inpaddr_address_reload_insns[rl->opnum];
6312 case RELOAD_FOR_OUTPUT_ADDRESS:
6313 where = &output_address_reload_insns[rl->opnum];
6315 case RELOAD_FOR_OUTADDR_ADDRESS:
6316 where = &outaddr_address_reload_insns[rl->opnum];
6318 case RELOAD_FOR_OPERAND_ADDRESS:
6319 where = &operand_reload_insns;
6321 case RELOAD_FOR_OPADDR_ADDR:
6322 where = &other_operand_reload_insns;
6324 case RELOAD_FOR_OTHER_ADDRESS:
6325 where = &other_input_address_reload_insns;
6331 push_to_sequence (*where);
6333 /* Auto-increment addresses must be reloaded in a special way. */
6334 if (rl->out && ! rl->out_reg)
6336 /* We are not going to bother supporting the case where a
6337 incremented register can't be copied directly from
6338 OLDEQUIV since this seems highly unlikely. */
6339 if (rl->secondary_in_reload >= 0)
6342 if (reload_inherited[j])
6343 oldequiv = reloadreg;
6345 old = XEXP (rl->in_reg, 0);
6347 if (optimize && GET_CODE (oldequiv) == REG
6348 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6349 && spill_reg_store[REGNO (oldequiv)]
6350 && GET_CODE (old) == REG
6351 && (dead_or_set_p (insn,
6352 spill_reg_stored_to[REGNO (oldequiv)])
6353 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6355 delete_output_reload (insn, j, REGNO (oldequiv));
6357 /* Prevent normal processing of this reload. */
6359 /* Output a special code sequence for this case. */
6360 new_spill_reg_store[REGNO (reloadreg)]
6361 = inc_for_reload (reloadreg, oldequiv, rl->out,
6365 /* If we are reloading a pseudo-register that was set by the previous
6366 insn, see if we can get rid of that pseudo-register entirely
6367 by redirecting the previous insn into our reload register. */
6369 else if (optimize && GET_CODE (old) == REG
6370 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6371 && dead_or_set_p (insn, old)
6372 /* This is unsafe if some other reload
6373 uses the same reg first. */
6374 && ! conflicts_with_override (reloadreg)
6375 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6376 rl->when_needed, old, rl->out, j, 0))
6378 rtx temp = PREV_INSN (insn);
6379 while (temp && GET_CODE (temp) == NOTE)
6380 temp = PREV_INSN (temp);
6382 && GET_CODE (temp) == INSN
6383 && GET_CODE (PATTERN (temp)) == SET
6384 && SET_DEST (PATTERN (temp)) == old
6385 /* Make sure we can access insn_operand_constraint. */
6386 && asm_noperands (PATTERN (temp)) < 0
6387 /* This is unsafe if prev insn rejects our reload reg. */
6388 && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint,
6390 /* This is unsafe if operand occurs more than once in current
6391 insn. Perhaps some occurrences aren't reloaded. */
6392 && count_occurrences (PATTERN (insn), old, 0) == 1
6393 /* Don't risk splitting a matching pair of operands. */
6394 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6396 /* Store into the reload register instead of the pseudo. */
6397 SET_DEST (PATTERN (temp)) = reloadreg;
6399 /* If the previous insn is an output reload, the source is
6400 a reload register, and its spill_reg_store entry will
6401 contain the previous destination. This is now
6403 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6404 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6406 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6407 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6410 /* If these are the only uses of the pseudo reg,
6411 pretend for GDB it lives in the reload reg we used. */
6412 if (REG_N_DEATHS (REGNO (old)) == 1
6413 && REG_N_SETS (REGNO (old)) == 1)
6415 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6416 alter_reg (REGNO (old), -1);
6422 /* We can't do that, so output an insn to load RELOADREG. */
6424 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6425 /* If we have a secondary reload, pick up the secondary register
6426 and icode, if any. If OLDEQUIV and OLD are different or
6427 if this is an in-out reload, recompute whether or not we
6428 still need a secondary register and what the icode should
6429 be. If we still need a secondary register and the class or
6430 icode is different, go back to reloading from OLD if using
6431 OLDEQUIV means that we got the wrong type of register. We
6432 cannot have different class or icode due to an in-out reload
6433 because we don't make such reloads when both the input and
6434 output need secondary reload registers. */
6436 if (! special && rl->secondary_in_reload >= 0)
6438 rtx second_reload_reg = 0;
6439 int secondary_reload = rl->secondary_in_reload;
6440 rtx real_oldequiv = oldequiv;
6443 enum insn_code icode;
6445 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6446 and similarly for OLD.
6447 See comments in get_secondary_reload in reload.c. */
6448 /* If it is a pseudo that cannot be replaced with its
6449 equivalent MEM, we must fall back to reload_in, which
6450 will have all the necessary substitutions registered.
6451 Likewise for a pseudo that can't be replaced with its
6452 equivalent constant.
6454 Take extra care for subregs of such pseudos. Note that
6455 we cannot use reg_equiv_mem in this case because it is
6456 not in the right mode. */
6459 if (GET_CODE (tmp) == SUBREG)
6460 tmp = SUBREG_REG (tmp);
6461 if (GET_CODE (tmp) == REG
6462 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6463 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6464 || reg_equiv_constant[REGNO (tmp)] != 0))
6466 if (! reg_equiv_mem[REGNO (tmp)]
6467 || num_not_at_initial_offset
6468 || GET_CODE (oldequiv) == SUBREG)
6469 real_oldequiv = rl->in;
6471 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6475 if (GET_CODE (tmp) == SUBREG)
6476 tmp = SUBREG_REG (tmp);
6477 if (GET_CODE (tmp) == REG
6478 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6479 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6480 || reg_equiv_constant[REGNO (tmp)] != 0))
6482 if (! reg_equiv_mem[REGNO (tmp)]
6483 || num_not_at_initial_offset
6484 || GET_CODE (old) == SUBREG)
6487 real_old = reg_equiv_mem[REGNO (tmp)];
6490 second_reload_reg = rld[secondary_reload].reg_rtx;
6491 icode = rl->secondary_in_icode;
6493 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6494 || (rl->in != 0 && rl->out != 0))
6496 enum reg_class new_class
6497 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6498 mode, real_oldequiv);
6500 if (new_class == NO_REGS)
6501 second_reload_reg = 0;
6504 enum insn_code new_icode;
6505 enum machine_mode new_mode;
6507 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6508 REGNO (second_reload_reg)))
6509 oldequiv = old, real_oldequiv = real_old;
6512 new_icode = reload_in_optab[(int) mode];
6513 if (new_icode != CODE_FOR_nothing
6514 && ((insn_data[(int) new_icode].operand[0].predicate
6515 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6517 || (insn_data[(int) new_icode].operand[1].predicate
6518 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6519 (real_oldequiv, mode)))))
6520 new_icode = CODE_FOR_nothing;
6522 if (new_icode == CODE_FOR_nothing)
6525 new_mode = insn_data[(int) new_icode].operand[2].mode;
6527 if (GET_MODE (second_reload_reg) != new_mode)
6529 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6531 oldequiv = old, real_oldequiv = real_old;
6534 = gen_rtx_REG (new_mode,
6535 REGNO (second_reload_reg));
6541 /* If we still need a secondary reload register, check
6542 to see if it is being used as a scratch or intermediate
6543 register and generate code appropriately. If we need
6544 a scratch register, use REAL_OLDEQUIV since the form of
6545 the insn may depend on the actual address if it is
6548 if (second_reload_reg)
6550 if (icode != CODE_FOR_nothing)
6552 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6553 second_reload_reg));
6558 /* See if we need a scratch register to load the
6559 intermediate register (a tertiary reload). */
6560 enum insn_code tertiary_icode
6561 = rld[secondary_reload].secondary_in_icode;
6563 if (tertiary_icode != CODE_FOR_nothing)
6565 rtx third_reload_reg
6566 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6568 emit_insn ((GEN_FCN (tertiary_icode)
6569 (second_reload_reg, real_oldequiv,
6570 third_reload_reg)));
6573 gen_reload (second_reload_reg, real_oldequiv,
6577 oldequiv = second_reload_reg;
6583 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6585 rtx real_oldequiv = oldequiv;
6587 if ((GET_CODE (oldequiv) == REG
6588 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6589 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6590 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6591 || (GET_CODE (oldequiv) == SUBREG
6592 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6593 && (REGNO (SUBREG_REG (oldequiv))
6594 >= FIRST_PSEUDO_REGISTER)
6595 && ((reg_equiv_memory_loc
6596 [REGNO (SUBREG_REG (oldequiv))] != 0)
6597 || (reg_equiv_constant
6598 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6599 || (CONSTANT_P (oldequiv)
6600 && (PREFERRED_RELOAD_CLASS (oldequiv,
6601 REGNO_REG_CLASS (REGNO (reloadreg)))
6603 real_oldequiv = rl->in;
6604 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6608 if (flag_non_call_exceptions)
6609 copy_eh_notes (insn, get_insns ());
6611 /* End this sequence. */
6612 *where = get_insns ();
6615 /* Update reload_override_in so that delete_address_reloads_1
6616 can see the actual register usage. */
6618 reload_override_in[j] = oldequiv;
6621 /* Generate insns to for the output reload RL, which is for the insn described
6622 by CHAIN and has the number J. */
6624 emit_output_reload_insns (chain, rl, j)
6625 struct insn_chain *chain;
6629 rtx reloadreg = rl->reg_rtx;
6630 rtx insn = chain->insn;
6633 enum machine_mode mode = GET_MODE (old);
6636 if (rl->when_needed == RELOAD_OTHER)
6639 push_to_sequence (output_reload_insns[rl->opnum]);
6641 /* Determine the mode to reload in.
6642 See comments above (for input reloading). */
6644 if (mode == VOIDmode)
6646 /* VOIDmode should never happen for an output. */
6647 if (asm_noperands (PATTERN (insn)) < 0)
6648 /* It's the compiler's fault. */
6649 fatal_insn ("VOIDmode on an output", insn);
6650 error_for_asm (insn, "output operand is constant in `asm'");
6651 /* Prevent crash--use something we know is valid. */
6653 old = gen_rtx_REG (mode, REGNO (reloadreg));
6656 if (GET_MODE (reloadreg) != mode)
6657 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6659 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6661 /* If we need two reload regs, set RELOADREG to the intermediate
6662 one, since it will be stored into OLD. We might need a secondary
6663 register only for an input reload, so check again here. */
6665 if (rl->secondary_out_reload >= 0)
6669 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6670 && reg_equiv_mem[REGNO (old)] != 0)
6671 real_old = reg_equiv_mem[REGNO (old)];
6673 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6677 rtx second_reloadreg = reloadreg;
6678 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6680 /* See if RELOADREG is to be used as a scratch register
6681 or as an intermediate register. */
6682 if (rl->secondary_out_icode != CODE_FOR_nothing)
6684 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6685 (real_old, second_reloadreg, reloadreg)));
6690 /* See if we need both a scratch and intermediate reload
6693 int secondary_reload = rl->secondary_out_reload;
6694 enum insn_code tertiary_icode
6695 = rld[secondary_reload].secondary_out_icode;
6697 if (GET_MODE (reloadreg) != mode)
6698 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6700 if (tertiary_icode != CODE_FOR_nothing)
6703 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6706 /* Copy primary reload reg to secondary reload reg.
6707 (Note that these have been swapped above, then
6708 secondary reload reg to OLD using our insn.) */
6710 /* If REAL_OLD is a paradoxical SUBREG, remove it
6711 and try to put the opposite SUBREG on
6713 if (GET_CODE (real_old) == SUBREG
6714 && (GET_MODE_SIZE (GET_MODE (real_old))
6715 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6716 && 0 != (tem = gen_lowpart_common
6717 (GET_MODE (SUBREG_REG (real_old)),
6719 real_old = SUBREG_REG (real_old), reloadreg = tem;
6721 gen_reload (reloadreg, second_reloadreg,
6722 rl->opnum, rl->when_needed);
6723 emit_insn ((GEN_FCN (tertiary_icode)
6724 (real_old, reloadreg, third_reloadreg)));
6729 /* Copy between the reload regs here and then to
6732 gen_reload (reloadreg, second_reloadreg,
6733 rl->opnum, rl->when_needed);
6739 /* Output the last reload insn. */
6744 /* Don't output the last reload if OLD is not the dest of
6745 INSN and is in the src and is clobbered by INSN. */
6746 if (! flag_expensive_optimizations
6747 || GET_CODE (old) != REG
6748 || !(set = single_set (insn))
6749 || rtx_equal_p (old, SET_DEST (set))
6750 || !reg_mentioned_p (old, SET_SRC (set))
6751 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6752 gen_reload (old, reloadreg, rl->opnum,
6756 /* Look at all insns we emitted, just to be safe. */
6757 for (p = get_insns (); p; p = NEXT_INSN (p))
6760 rtx pat = PATTERN (p);
6762 /* If this output reload doesn't come from a spill reg,
6763 clear any memory of reloaded copies of the pseudo reg.
6764 If this output reload comes from a spill reg,
6765 reg_has_output_reload will make this do nothing. */
6766 note_stores (pat, forget_old_reloads_1, NULL);
6768 if (reg_mentioned_p (rl->reg_rtx, pat))
6770 rtx set = single_set (insn);
6771 if (reload_spill_index[j] < 0
6773 && SET_SRC (set) == rl->reg_rtx)
6775 int src = REGNO (SET_SRC (set));
6777 reload_spill_index[j] = src;
6778 SET_HARD_REG_BIT (reg_is_output_reload, src);
6779 if (find_regno_note (insn, REG_DEAD, src))
6780 SET_HARD_REG_BIT (reg_reloaded_died, src);
6782 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6784 int s = rl->secondary_out_reload;
6785 set = single_set (p);
6786 /* If this reload copies only to the secondary reload
6787 register, the secondary reload does the actual
6789 if (s >= 0 && set == NULL_RTX)
6790 /* We can't tell what function the secondary reload
6791 has and where the actual store to the pseudo is
6792 made; leave new_spill_reg_store alone. */
6795 && SET_SRC (set) == rl->reg_rtx
6796 && SET_DEST (set) == rld[s].reg_rtx)
6798 /* Usually the next instruction will be the
6799 secondary reload insn; if we can confirm
6800 that it is, setting new_spill_reg_store to
6801 that insn will allow an extra optimization. */
6802 rtx s_reg = rld[s].reg_rtx;
6803 rtx next = NEXT_INSN (p);
6804 rld[s].out = rl->out;
6805 rld[s].out_reg = rl->out_reg;
6806 set = single_set (next);
6807 if (set && SET_SRC (set) == s_reg
6808 && ! new_spill_reg_store[REGNO (s_reg)])
6810 SET_HARD_REG_BIT (reg_is_output_reload,
6812 new_spill_reg_store[REGNO (s_reg)] = next;
6816 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6821 if (rl->when_needed == RELOAD_OTHER)
6823 emit_insns (other_output_reload_insns[rl->opnum]);
6824 other_output_reload_insns[rl->opnum] = get_insns ();
6827 output_reload_insns[rl->opnum] = get_insns ();
6829 if (flag_non_call_exceptions)
6830 copy_eh_notes (insn, get_insns ());
6835 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6836 and has the number J. */
6838 do_input_reload (chain, rl, j)
6839 struct insn_chain *chain;
6843 int expect_occurrences = 1;
6844 rtx insn = chain->insn;
6845 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6846 ? rl->in_reg : rl->in);
6849 /* AUTO_INC reloads need to be handled even if inherited. We got an
6850 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6851 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6852 && ! rtx_equal_p (rl->reg_rtx, old)
6853 && rl->reg_rtx != 0)
6854 emit_input_reload_insns (chain, rld + j, old, j);
6856 /* When inheriting a wider reload, we have a MEM in rl->in,
6857 e.g. inheriting a SImode output reload for
6858 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6859 if (optimize && reload_inherited[j] && rl->in
6860 && GET_CODE (rl->in) == MEM
6861 && GET_CODE (rl->in_reg) == MEM
6862 && reload_spill_index[j] >= 0
6863 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6866 = count_occurrences (PATTERN (insn), rl->in, 0) == 1 ? 0 : -1;
6867 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6870 /* If we are reloading a register that was recently stored in with an
6871 output-reload, see if we can prove there was
6872 actually no need to store the old value in it. */
6875 && (reload_inherited[j] || reload_override_in[j])
6877 && GET_CODE (rl->reg_rtx) == REG
6878 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6880 /* There doesn't seem to be any reason to restrict this to pseudos
6881 and doing so loses in the case where we are copying from a
6882 register of the wrong class. */
6883 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6884 >= FIRST_PSEUDO_REGISTER)
6886 /* The insn might have already some references to stackslots
6887 replaced by MEMs, while reload_out_reg still names the
6889 && (dead_or_set_p (insn,
6890 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6891 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6893 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6896 /* Do output reloading for reload RL, which is for the insn described by
6897 CHAIN and has the number J.
6898 ??? At some point we need to support handling output reloads of
6899 JUMP_INSNs or insns that set cc0. */
6901 do_output_reload (chain, rl, j)
6902 struct insn_chain *chain;
6907 rtx insn = chain->insn;
6908 /* If this is an output reload that stores something that is
6909 not loaded in this same reload, see if we can eliminate a previous
6911 rtx pseudo = rl->out_reg;
6914 && GET_CODE (pseudo) == REG
6915 && ! rtx_equal_p (rl->in_reg, pseudo)
6916 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6917 && reg_last_reload_reg[REGNO (pseudo)])
6919 int pseudo_no = REGNO (pseudo);
6920 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6922 /* We don't need to test full validity of last_regno for
6923 inherit here; we only want to know if the store actually
6924 matches the pseudo. */
6925 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6926 && reg_reloaded_contents[last_regno] == pseudo_no
6927 && spill_reg_store[last_regno]
6928 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6929 delete_output_reload (insn, j, last_regno);
6934 || rl->reg_rtx == old
6935 || rl->reg_rtx == 0)
6938 /* An output operand that dies right away does need a reload,
6939 but need not be copied from it. Show the new location in the
6941 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6942 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6944 XEXP (note, 0) = rl->reg_rtx;
6947 /* Likewise for a SUBREG of an operand that dies. */
6948 else if (GET_CODE (old) == SUBREG
6949 && GET_CODE (SUBREG_REG (old)) == REG
6950 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6953 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6957 else if (GET_CODE (old) == SCRATCH)
6958 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6959 but we don't want to make an output reload. */
6962 /* If is a JUMP_INSN, we can't support output reloads yet. */
6963 if (GET_CODE (insn) == JUMP_INSN)
6966 emit_output_reload_insns (chain, rld + j, j);
6969 /* Output insns to reload values in and out of the chosen reload regs. */
6972 emit_reload_insns (chain)
6973 struct insn_chain *chain;
6975 rtx insn = chain->insn;
6979 CLEAR_HARD_REG_SET (reg_reloaded_died);
6981 for (j = 0; j < reload_n_operands; j++)
6982 input_reload_insns[j] = input_address_reload_insns[j]
6983 = inpaddr_address_reload_insns[j]
6984 = output_reload_insns[j] = output_address_reload_insns[j]
6985 = outaddr_address_reload_insns[j]
6986 = other_output_reload_insns[j] = 0;
6987 other_input_address_reload_insns = 0;
6988 other_input_reload_insns = 0;
6989 operand_reload_insns = 0;
6990 other_operand_reload_insns = 0;
6992 /* Dump reloads into the dump file. */
6995 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6996 debug_reload_to_stream (rtl_dump_file);
6999 /* Now output the instructions to copy the data into and out of the
7000 reload registers. Do these in the order that the reloads were reported,
7001 since reloads of base and index registers precede reloads of operands
7002 and the operands may need the base and index registers reloaded. */
7004 for (j = 0; j < n_reloads; j++)
7007 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7008 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7010 do_input_reload (chain, rld + j, j);
7011 do_output_reload (chain, rld + j, j);
7014 /* Now write all the insns we made for reloads in the order expected by
7015 the allocation functions. Prior to the insn being reloaded, we write
7016 the following reloads:
7018 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7020 RELOAD_OTHER reloads.
7022 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7023 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7024 RELOAD_FOR_INPUT reload for the operand.
7026 RELOAD_FOR_OPADDR_ADDRS reloads.
7028 RELOAD_FOR_OPERAND_ADDRESS reloads.
7030 After the insn being reloaded, we write the following:
7032 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7033 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7034 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7035 reloads for the operand. The RELOAD_OTHER output reloads are
7036 output in descending order by reload number. */
7038 emit_insns_before (other_input_address_reload_insns, insn);
7039 emit_insns_before (other_input_reload_insns, insn);
7041 for (j = 0; j < reload_n_operands; j++)
7043 emit_insns_before (inpaddr_address_reload_insns[j], insn);
7044 emit_insns_before (input_address_reload_insns[j], insn);
7045 emit_insns_before (input_reload_insns[j], insn);
7048 emit_insns_before (other_operand_reload_insns, insn);
7049 emit_insns_before (operand_reload_insns, insn);
7051 for (j = 0; j < reload_n_operands; j++)
7053 rtx x = emit_insns_after (outaddr_address_reload_insns[j], insn);
7054 x = emit_insns_after (output_address_reload_insns[j], x);
7055 x = emit_insns_after (output_reload_insns[j], x);
7056 emit_insns_after (other_output_reload_insns[j], x);
7059 /* For all the spill regs newly reloaded in this instruction,
7060 record what they were reloaded from, so subsequent instructions
7061 can inherit the reloads.
7063 Update spill_reg_store for the reloads of this insn.
7064 Copy the elements that were updated in the loop above. */
7066 for (j = 0; j < n_reloads; j++)
7068 int r = reload_order[j];
7069 int i = reload_spill_index[r];
7071 /* If this is a non-inherited input reload from a pseudo, we must
7072 clear any memory of a previous store to the same pseudo. Only do
7073 something if there will not be an output reload for the pseudo
7075 if (rld[r].in_reg != 0
7076 && ! (reload_inherited[r] || reload_override_in[r]))
7078 rtx reg = rld[r].in_reg;
7080 if (GET_CODE (reg) == SUBREG)
7081 reg = SUBREG_REG (reg);
7083 if (GET_CODE (reg) == REG
7084 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7085 && ! reg_has_output_reload[REGNO (reg)])
7087 int nregno = REGNO (reg);
7089 if (reg_last_reload_reg[nregno])
7091 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7093 if (reg_reloaded_contents[last_regno] == nregno)
7094 spill_reg_store[last_regno] = 0;
7099 /* I is nonneg if this reload used a register.
7100 If rld[r].reg_rtx is 0, this is an optional reload
7101 that we opted to ignore. */
7103 if (i >= 0 && rld[r].reg_rtx != 0)
7105 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7107 int part_reaches_end = 0;
7108 int all_reaches_end = 1;
7110 /* For a multi register reload, we need to check if all or part
7111 of the value lives to the end. */
7112 for (k = 0; k < nr; k++)
7114 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7115 rld[r].when_needed))
7116 part_reaches_end = 1;
7118 all_reaches_end = 0;
7121 /* Ignore reloads that don't reach the end of the insn in
7123 if (all_reaches_end)
7125 /* First, clear out memory of what used to be in this spill reg.
7126 If consecutive registers are used, clear them all. */
7128 for (k = 0; k < nr; k++)
7129 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7131 /* Maybe the spill reg contains a copy of reload_out. */
7133 && (GET_CODE (rld[r].out) == REG
7137 || GET_CODE (rld[r].out_reg) == REG))
7139 rtx out = (GET_CODE (rld[r].out) == REG
7143 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7144 int nregno = REGNO (out);
7145 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7146 : HARD_REGNO_NREGS (nregno,
7147 GET_MODE (rld[r].reg_rtx)));
7149 spill_reg_store[i] = new_spill_reg_store[i];
7150 spill_reg_stored_to[i] = out;
7151 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7153 /* If NREGNO is a hard register, it may occupy more than
7154 one register. If it does, say what is in the
7155 rest of the registers assuming that both registers
7156 agree on how many words the object takes. If not,
7157 invalidate the subsequent registers. */
7159 if (nregno < FIRST_PSEUDO_REGISTER)
7160 for (k = 1; k < nnr; k++)
7161 reg_last_reload_reg[nregno + k]
7163 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7164 REGNO (rld[r].reg_rtx) + k)
7167 /* Now do the inverse operation. */
7168 for (k = 0; k < nr; k++)
7170 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7171 reg_reloaded_contents[i + k]
7172 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7175 reg_reloaded_insn[i + k] = insn;
7176 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7180 /* Maybe the spill reg contains a copy of reload_in. Only do
7181 something if there will not be an output reload for
7182 the register being reloaded. */
7183 else if (rld[r].out_reg == 0
7185 && ((GET_CODE (rld[r].in) == REG
7186 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7187 && ! reg_has_output_reload[REGNO (rld[r].in)])
7188 || (GET_CODE (rld[r].in_reg) == REG
7189 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7190 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7195 if (GET_CODE (rld[r].in) == REG
7196 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7197 nregno = REGNO (rld[r].in);
7198 else if (GET_CODE (rld[r].in_reg) == REG)
7199 nregno = REGNO (rld[r].in_reg);
7201 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7203 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7204 : HARD_REGNO_NREGS (nregno,
7205 GET_MODE (rld[r].reg_rtx)));
7207 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7209 if (nregno < FIRST_PSEUDO_REGISTER)
7210 for (k = 1; k < nnr; k++)
7211 reg_last_reload_reg[nregno + k]
7213 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7214 REGNO (rld[r].reg_rtx) + k)
7217 /* Unless we inherited this reload, show we haven't
7218 recently done a store.
7219 Previous stores of inherited auto_inc expressions
7220 also have to be discarded. */
7221 if (! reload_inherited[r]
7222 || (rld[r].out && ! rld[r].out_reg))
7223 spill_reg_store[i] = 0;
7225 for (k = 0; k < nr; k++)
7227 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7228 reg_reloaded_contents[i + k]
7229 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7232 reg_reloaded_insn[i + k] = insn;
7233 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7238 /* However, if part of the reload reaches the end, then we must
7239 invalidate the old info for the part that survives to the end. */
7240 else if (part_reaches_end)
7242 for (k = 0; k < nr; k++)
7243 if (reload_reg_reaches_end_p (i + k,
7245 rld[r].when_needed))
7246 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7250 /* The following if-statement was #if 0'd in 1.34 (or before...).
7251 It's reenabled in 1.35 because supposedly nothing else
7252 deals with this problem. */
7254 /* If a register gets output-reloaded from a non-spill register,
7255 that invalidates any previous reloaded copy of it.
7256 But forget_old_reloads_1 won't get to see it, because
7257 it thinks only about the original insn. So invalidate it here. */
7258 if (i < 0 && rld[r].out != 0
7259 && (GET_CODE (rld[r].out) == REG
7260 || (GET_CODE (rld[r].out) == MEM
7261 && GET_CODE (rld[r].out_reg) == REG)))
7263 rtx out = (GET_CODE (rld[r].out) == REG
7264 ? rld[r].out : rld[r].out_reg);
7265 int nregno = REGNO (out);
7266 if (nregno >= FIRST_PSEUDO_REGISTER)
7268 rtx src_reg, store_insn = NULL_RTX;
7270 reg_last_reload_reg[nregno] = 0;
7272 /* If we can find a hard register that is stored, record
7273 the storing insn so that we may delete this insn with
7274 delete_output_reload. */
7275 src_reg = rld[r].reg_rtx;
7277 /* If this is an optional reload, try to find the source reg
7278 from an input reload. */
7281 rtx set = single_set (insn);
7282 if (set && SET_DEST (set) == rld[r].out)
7286 src_reg = SET_SRC (set);
7288 for (k = 0; k < n_reloads; k++)
7290 if (rld[k].in == src_reg)
7292 src_reg = rld[k].reg_rtx;
7299 store_insn = new_spill_reg_store[REGNO (src_reg)];
7300 if (src_reg && GET_CODE (src_reg) == REG
7301 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7303 int src_regno = REGNO (src_reg);
7304 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7305 /* The place where to find a death note varies with
7306 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7307 necessarily checked exactly in the code that moves
7308 notes, so just check both locations. */
7309 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7310 if (! note && store_insn)
7311 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7314 spill_reg_store[src_regno + nr] = store_insn;
7315 spill_reg_stored_to[src_regno + nr] = out;
7316 reg_reloaded_contents[src_regno + nr] = nregno;
7317 reg_reloaded_insn[src_regno + nr] = store_insn;
7318 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7319 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7320 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7322 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7324 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7326 reg_last_reload_reg[nregno] = src_reg;
7331 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7333 while (num_regs-- > 0)
7334 reg_last_reload_reg[nregno + num_regs] = 0;
7338 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7341 /* Emit code to perform a reload from IN (which may be a reload register) to
7342 OUT (which may also be a reload register). IN or OUT is from operand
7343 OPNUM with reload type TYPE.
7345 Returns first insn emitted. */
7348 gen_reload (out, in, opnum, type)
7352 enum reload_type type;
7354 rtx last = get_last_insn ();
7357 /* If IN is a paradoxical SUBREG, remove it and try to put the
7358 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7359 if (GET_CODE (in) == SUBREG
7360 && (GET_MODE_SIZE (GET_MODE (in))
7361 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7362 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7363 in = SUBREG_REG (in), out = tem;
7364 else if (GET_CODE (out) == SUBREG
7365 && (GET_MODE_SIZE (GET_MODE (out))
7366 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7367 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7368 out = SUBREG_REG (out), in = tem;
7370 /* How to do this reload can get quite tricky. Normally, we are being
7371 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7372 register that didn't get a hard register. In that case we can just
7373 call emit_move_insn.
7375 We can also be asked to reload a PLUS that adds a register or a MEM to
7376 another register, constant or MEM. This can occur during frame pointer
7377 elimination and while reloading addresses. This case is handled by
7378 trying to emit a single insn to perform the add. If it is not valid,
7379 we use a two insn sequence.
7381 Finally, we could be called to handle an 'o' constraint by putting
7382 an address into a register. In that case, we first try to do this
7383 with a named pattern of "reload_load_address". If no such pattern
7384 exists, we just emit a SET insn and hope for the best (it will normally
7385 be valid on machines that use 'o').
7387 This entire process is made complex because reload will never
7388 process the insns we generate here and so we must ensure that
7389 they will fit their constraints and also by the fact that parts of
7390 IN might be being reloaded separately and replaced with spill registers.
7391 Because of this, we are, in some sense, just guessing the right approach
7392 here. The one listed above seems to work.
7394 ??? At some point, this whole thing needs to be rethought. */
7396 if (GET_CODE (in) == PLUS
7397 && (GET_CODE (XEXP (in, 0)) == REG
7398 || GET_CODE (XEXP (in, 0)) == SUBREG
7399 || GET_CODE (XEXP (in, 0)) == MEM)
7400 && (GET_CODE (XEXP (in, 1)) == REG
7401 || GET_CODE (XEXP (in, 1)) == SUBREG
7402 || CONSTANT_P (XEXP (in, 1))
7403 || GET_CODE (XEXP (in, 1)) == MEM))
7405 /* We need to compute the sum of a register or a MEM and another
7406 register, constant, or MEM, and put it into the reload
7407 register. The best possible way of doing this is if the machine
7408 has a three-operand ADD insn that accepts the required operands.
7410 The simplest approach is to try to generate such an insn and see if it
7411 is recognized and matches its constraints. If so, it can be used.
7413 It might be better not to actually emit the insn unless it is valid,
7414 but we need to pass the insn as an operand to `recog' and
7415 `extract_insn' and it is simpler to emit and then delete the insn if
7416 not valid than to dummy things up. */
7418 rtx op0, op1, tem, insn;
7421 op0 = find_replacement (&XEXP (in, 0));
7422 op1 = find_replacement (&XEXP (in, 1));
7424 /* Since constraint checking is strict, commutativity won't be
7425 checked, so we need to do that here to avoid spurious failure
7426 if the add instruction is two-address and the second operand
7427 of the add is the same as the reload reg, which is frequently
7428 the case. If the insn would be A = B + A, rearrange it so
7429 it will be A = A + B as constrain_operands expects. */
7431 if (GET_CODE (XEXP (in, 1)) == REG
7432 && REGNO (out) == REGNO (XEXP (in, 1)))
7433 tem = op0, op0 = op1, op1 = tem;
7435 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7436 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7438 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7439 code = recog_memoized (insn);
7443 extract_insn (insn);
7444 /* We want constrain operands to treat this insn strictly in
7445 its validity determination, i.e., the way it would after reload
7447 if (constrain_operands (1))
7451 delete_insns_since (last);
7453 /* If that failed, we must use a conservative two-insn sequence.
7455 Use a move to copy one operand into the reload register. Prefer
7456 to reload a constant, MEM or pseudo since the move patterns can
7457 handle an arbitrary operand. If OP1 is not a constant, MEM or
7458 pseudo and OP1 is not a valid operand for an add instruction, then
7461 After reloading one of the operands into the reload register, add
7462 the reload register to the output register.
7464 If there is another way to do this for a specific machine, a
7465 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7468 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7470 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7471 || (GET_CODE (op1) == REG
7472 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7473 || (code != CODE_FOR_nothing
7474 && ! ((*insn_data[code].operand[2].predicate)
7475 (op1, insn_data[code].operand[2].mode))))
7476 tem = op0, op0 = op1, op1 = tem;
7478 gen_reload (out, op0, opnum, type);
7480 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7481 This fixes a problem on the 32K where the stack pointer cannot
7482 be used as an operand of an add insn. */
7484 if (rtx_equal_p (op0, op1))
7487 insn = emit_insn (gen_add2_insn (out, op1));
7489 /* If that failed, copy the address register to the reload register.
7490 Then add the constant to the reload register. */
7492 code = recog_memoized (insn);
7496 extract_insn (insn);
7497 /* We want constrain operands to treat this insn strictly in
7498 its validity determination, i.e., the way it would after reload
7500 if (constrain_operands (1))
7502 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7504 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7509 delete_insns_since (last);
7511 gen_reload (out, op1, opnum, type);
7512 insn = emit_insn (gen_add2_insn (out, op0));
7513 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7516 #ifdef SECONDARY_MEMORY_NEEDED
7517 /* If we need a memory location to do the move, do it that way. */
7518 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7519 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7520 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7521 REGNO_REG_CLASS (REGNO (out)),
7524 /* Get the memory to use and rewrite both registers to its mode. */
7525 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7527 if (GET_MODE (loc) != GET_MODE (out))
7528 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7530 if (GET_MODE (loc) != GET_MODE (in))
7531 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7533 gen_reload (loc, in, opnum, type);
7534 gen_reload (out, loc, opnum, type);
7538 /* If IN is a simple operand, use gen_move_insn. */
7539 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7540 emit_insn (gen_move_insn (out, in));
7542 #ifdef HAVE_reload_load_address
7543 else if (HAVE_reload_load_address)
7544 emit_insn (gen_reload_load_address (out, in));
7547 /* Otherwise, just write (set OUT IN) and hope for the best. */
7549 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7551 /* Return the first insn emitted.
7552 We can not just return get_last_insn, because there may have
7553 been multiple instructions emitted. Also note that gen_move_insn may
7554 emit more than one insn itself, so we can not assume that there is one
7555 insn emitted per emit_insn_before call. */
7557 return last ? NEXT_INSN (last) : get_insns ();
7560 /* Delete a previously made output-reload whose result we now believe
7561 is not needed. First we double-check.
7563 INSN is the insn now being processed.
7564 LAST_RELOAD_REG is the hard register number for which we want to delete
7565 the last output reload.
7566 J is the reload-number that originally used REG. The caller has made
7567 certain that reload J doesn't use REG any longer for input. */
7570 delete_output_reload (insn, j, last_reload_reg)
7573 int last_reload_reg;
7575 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7576 rtx reg = spill_reg_stored_to[last_reload_reg];
7579 int n_inherited = 0;
7583 /* Get the raw pseudo-register referred to. */
7585 while (GET_CODE (reg) == SUBREG)
7586 reg = SUBREG_REG (reg);
7587 substed = reg_equiv_memory_loc[REGNO (reg)];
7589 /* This is unsafe if the operand occurs more often in the current
7590 insn than it is inherited. */
7591 for (k = n_reloads - 1; k >= 0; k--)
7593 rtx reg2 = rld[k].in;
7596 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7597 reg2 = rld[k].in_reg;
7599 if (rld[k].out && ! rld[k].out_reg)
7600 reg2 = XEXP (rld[k].in_reg, 0);
7602 while (GET_CODE (reg2) == SUBREG)
7603 reg2 = SUBREG_REG (reg2);
7604 if (rtx_equal_p (reg2, reg))
7606 if (reload_inherited[k] || reload_override_in[k] || k == j)
7609 reg2 = rld[k].out_reg;
7612 while (GET_CODE (reg2) == SUBREG)
7613 reg2 = XEXP (reg2, 0);
7614 if (rtx_equal_p (reg2, reg))
7621 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7623 n_occurrences += count_occurrences (PATTERN (insn),
7624 eliminate_regs (substed, 0,
7626 if (n_occurrences > n_inherited)
7629 /* If the pseudo-reg we are reloading is no longer referenced
7630 anywhere between the store into it and here,
7631 and no jumps or labels intervene, then the value can get
7632 here through the reload reg alone.
7633 Otherwise, give up--return. */
7634 for (i1 = NEXT_INSN (output_reload_insn);
7635 i1 != insn; i1 = NEXT_INSN (i1))
7637 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7639 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7640 && reg_mentioned_p (reg, PATTERN (i1)))
7642 /* If this is USE in front of INSN, we only have to check that
7643 there are no more references than accounted for by inheritance. */
7644 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7646 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7647 i1 = NEXT_INSN (i1);
7649 if (n_occurrences <= n_inherited && i1 == insn)
7655 /* We will be deleting the insn. Remove the spill reg information. */
7656 for (k = HARD_REGNO_NREGS (last_reload_reg, GET_MODE (reg)); k-- > 0; )
7658 spill_reg_store[last_reload_reg + k] = 0;
7659 spill_reg_stored_to[last_reload_reg + k] = 0;
7662 /* The caller has already checked that REG dies or is set in INSN.
7663 It has also checked that we are optimizing, and thus some
7664 inaccurancies in the debugging information are acceptable.
7665 So we could just delete output_reload_insn. But in some cases
7666 we can improve the debugging information without sacrificing
7667 optimization - maybe even improving the code: See if the pseudo
7668 reg has been completely replaced with reload regs. If so, delete
7669 the store insn and forget we had a stack slot for the pseudo. */
7670 if (rld[j].out != rld[j].in
7671 && REG_N_DEATHS (REGNO (reg)) == 1
7672 && REG_N_SETS (REGNO (reg)) == 1
7673 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7674 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7678 /* We know that it was used only between here and the beginning of
7679 the current basic block. (We also know that the last use before
7680 INSN was the output reload we are thinking of deleting, but never
7681 mind that.) Search that range; see if any ref remains. */
7682 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7684 rtx set = single_set (i2);
7686 /* Uses which just store in the pseudo don't count,
7687 since if they are the only uses, they are dead. */
7688 if (set != 0 && SET_DEST (set) == reg)
7690 if (GET_CODE (i2) == CODE_LABEL
7691 || GET_CODE (i2) == JUMP_INSN)
7693 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7694 && reg_mentioned_p (reg, PATTERN (i2)))
7696 /* Some other ref remains; just delete the output reload we
7698 delete_address_reloads (output_reload_insn, insn);
7699 delete_insn (output_reload_insn);
7704 /* Delete the now-dead stores into this pseudo. Note that this
7705 loop also takes care of deleting output_reload_insn. */
7706 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7708 rtx set = single_set (i2);
7710 if (set != 0 && SET_DEST (set) == reg)
7712 delete_address_reloads (i2, insn);
7715 if (GET_CODE (i2) == CODE_LABEL
7716 || GET_CODE (i2) == JUMP_INSN)
7720 /* For the debugging info, say the pseudo lives in this reload reg. */
7721 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7722 alter_reg (REGNO (reg), -1);
7726 delete_address_reloads (output_reload_insn, insn);
7727 delete_insn (output_reload_insn);
7731 /* We are going to delete DEAD_INSN. Recursively delete loads of
7732 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7733 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7735 delete_address_reloads (dead_insn, current_insn)
7736 rtx dead_insn, current_insn;
7738 rtx set = single_set (dead_insn);
7739 rtx set2, dst, prev, next;
7742 rtx dst = SET_DEST (set);
7743 if (GET_CODE (dst) == MEM)
7744 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7746 /* If we deleted the store from a reloaded post_{in,de}c expression,
7747 we can delete the matching adds. */
7748 prev = PREV_INSN (dead_insn);
7749 next = NEXT_INSN (dead_insn);
7750 if (! prev || ! next)
7752 set = single_set (next);
7753 set2 = single_set (prev);
7755 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7756 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7757 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7759 dst = SET_DEST (set);
7760 if (! rtx_equal_p (dst, SET_DEST (set2))
7761 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7762 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7763 || (INTVAL (XEXP (SET_SRC (set), 1))
7764 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7766 delete_related_insns (prev);
7767 delete_related_insns (next);
7770 /* Subfunction of delete_address_reloads: process registers found in X. */
7772 delete_address_reloads_1 (dead_insn, x, current_insn)
7773 rtx dead_insn, x, current_insn;
7775 rtx prev, set, dst, i2;
7777 enum rtx_code code = GET_CODE (x);
7781 const char *fmt = GET_RTX_FORMAT (code);
7782 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7785 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7786 else if (fmt[i] == 'E')
7788 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7789 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7796 if (spill_reg_order[REGNO (x)] < 0)
7799 /* Scan backwards for the insn that sets x. This might be a way back due
7801 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7803 code = GET_CODE (prev);
7804 if (code == CODE_LABEL || code == JUMP_INSN)
7806 if (GET_RTX_CLASS (code) != 'i')
7808 if (reg_set_p (x, PATTERN (prev)))
7810 if (reg_referenced_p (x, PATTERN (prev)))
7813 if (! prev || INSN_UID (prev) < reload_first_uid)
7815 /* Check that PREV only sets the reload register. */
7816 set = single_set (prev);
7819 dst = SET_DEST (set);
7820 if (GET_CODE (dst) != REG
7821 || ! rtx_equal_p (dst, x))
7823 if (! reg_set_p (dst, PATTERN (dead_insn)))
7825 /* Check if DST was used in a later insn -
7826 it might have been inherited. */
7827 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7829 if (GET_CODE (i2) == CODE_LABEL)
7833 if (reg_referenced_p (dst, PATTERN (i2)))
7835 /* If there is a reference to the register in the current insn,
7836 it might be loaded in a non-inherited reload. If no other
7837 reload uses it, that means the register is set before
7839 if (i2 == current_insn)
7841 for (j = n_reloads - 1; j >= 0; j--)
7842 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7843 || reload_override_in[j] == dst)
7845 for (j = n_reloads - 1; j >= 0; j--)
7846 if (rld[j].in && rld[j].reg_rtx == dst)
7853 if (GET_CODE (i2) == JUMP_INSN)
7855 /* If DST is still live at CURRENT_INSN, check if it is used for
7856 any reload. Note that even if CURRENT_INSN sets DST, we still
7857 have to check the reloads. */
7858 if (i2 == current_insn)
7860 for (j = n_reloads - 1; j >= 0; j--)
7861 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7862 || reload_override_in[j] == dst)
7864 /* ??? We can't finish the loop here, because dst might be
7865 allocated to a pseudo in this block if no reload in this
7866 block needs any of the clsses containing DST - see
7867 spill_hard_reg. There is no easy way to tell this, so we
7868 have to scan till the end of the basic block. */
7870 if (reg_set_p (dst, PATTERN (i2)))
7874 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7875 reg_reloaded_contents[REGNO (dst)] = -1;
7879 /* Output reload-insns to reload VALUE into RELOADREG.
7880 VALUE is an autoincrement or autodecrement RTX whose operand
7881 is a register or memory location;
7882 so reloading involves incrementing that location.
7883 IN is either identical to VALUE, or some cheaper place to reload from.
7885 INC_AMOUNT is the number to increment or decrement by (always positive).
7886 This cannot be deduced from VALUE.
7888 Return the instruction that stores into RELOADREG. */
7891 inc_for_reload (reloadreg, in, value, inc_amount)
7896 /* REG or MEM to be copied and incremented. */
7897 rtx incloc = XEXP (value, 0);
7898 /* Nonzero if increment after copying. */
7899 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7905 rtx real_in = in == value ? XEXP (in, 0) : in;
7907 /* No hard register is equivalent to this register after
7908 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7909 we could inc/dec that register as well (maybe even using it for
7910 the source), but I'm not sure it's worth worrying about. */
7911 if (GET_CODE (incloc) == REG)
7912 reg_last_reload_reg[REGNO (incloc)] = 0;
7914 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7915 inc_amount = -inc_amount;
7917 inc = GEN_INT (inc_amount);
7919 /* If this is post-increment, first copy the location to the reload reg. */
7920 if (post && real_in != reloadreg)
7921 emit_insn (gen_move_insn (reloadreg, real_in));
7925 /* See if we can directly increment INCLOC. Use a method similar to
7926 that in gen_reload. */
7928 last = get_last_insn ();
7929 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7930 gen_rtx_PLUS (GET_MODE (incloc),
7933 code = recog_memoized (add_insn);
7936 extract_insn (add_insn);
7937 if (constrain_operands (1))
7939 /* If this is a pre-increment and we have incremented the value
7940 where it lives, copy the incremented value to RELOADREG to
7941 be used as an address. */
7944 emit_insn (gen_move_insn (reloadreg, incloc));
7949 delete_insns_since (last);
7952 /* If couldn't do the increment directly, must increment in RELOADREG.
7953 The way we do this depends on whether this is pre- or post-increment.
7954 For pre-increment, copy INCLOC to the reload register, increment it
7955 there, then save back. */
7959 if (in != reloadreg)
7960 emit_insn (gen_move_insn (reloadreg, real_in));
7961 emit_insn (gen_add2_insn (reloadreg, inc));
7962 store = emit_insn (gen_move_insn (incloc, reloadreg));
7967 Because this might be a jump insn or a compare, and because RELOADREG
7968 may not be available after the insn in an input reload, we must do
7969 the incrementation before the insn being reloaded for.
7971 We have already copied IN to RELOADREG. Increment the copy in
7972 RELOADREG, save that back, then decrement RELOADREG so it has
7973 the original value. */
7975 emit_insn (gen_add2_insn (reloadreg, inc));
7976 store = emit_insn (gen_move_insn (incloc, reloadreg));
7977 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7983 /* Return 1 if we are certain that the constraint-string STRING allows
7984 the hard register REG. Return 0 if we can't be sure of this. */
7987 constraint_accepts_reg_p (string, reg)
7992 int regno = true_regnum (reg);
7995 /* Initialize for first alternative. */
7997 /* Check that each alternative contains `g' or `r'. */
7999 switch (c = *string++)
8002 /* If an alternative lacks `g' or `r', we lose. */
8005 /* If an alternative lacks `g' or `r', we lose. */
8008 /* Initialize for next alternative. */
8013 /* Any general reg wins for this alternative. */
8014 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
8018 /* Any reg in specified class wins for this alternative. */
8020 enum reg_class class = REG_CLASS_FROM_LETTER (c);
8022 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
8028 /* INSN is a no-op; delete it.
8029 If this sets the return value of the function, we must keep a USE around,
8030 in case this is in a different basic block than the final USE. Otherwise,
8031 we could loose important register lifeness information on
8032 SMALL_REGISTER_CLASSES machines, where return registers might be used as
8033 spills: subsequent passes assume that spill registers are dead at the end
8035 VALUE must be the return value in such a case, NULL otherwise. */
8037 reload_cse_delete_noop_set (insn, value)
8040 bool purge = BLOCK_FOR_INSN (insn)->end == insn;
8043 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
8044 INSN_CODE (insn) = -1;
8045 REG_NOTES (insn) = NULL_RTX;
8050 purge_dead_edges (BLOCK_FOR_INSN (insn));
8053 /* See whether a single set SET is a noop. */
8055 reload_cse_noop_set_p (set)
8058 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
8061 /* Try to simplify INSN. */
8063 reload_cse_simplify (insn)
8066 rtx body = PATTERN (insn);
8068 if (GET_CODE (body) == SET)
8072 /* Simplify even if we may think it is a no-op.
8073 We may think a memory load of a value smaller than WORD_SIZE
8074 is redundant because we haven't taken into account possible
8075 implicit extension. reload_cse_simplify_set() will bring
8076 this out, so it's safer to simplify before we delete. */
8077 count += reload_cse_simplify_set (body, insn);
8079 if (!count && reload_cse_noop_set_p (body))
8081 rtx value = SET_DEST (body);
8082 if (! REG_FUNCTION_VALUE_P (SET_DEST (body)))
8084 reload_cse_delete_noop_set (insn, value);
8089 apply_change_group ();
8091 reload_cse_simplify_operands (insn);
8093 else if (GET_CODE (body) == PARALLEL)
8097 rtx value = NULL_RTX;
8099 /* If every action in a PARALLEL is a noop, we can delete
8100 the entire PARALLEL. */
8101 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8103 rtx part = XVECEXP (body, 0, i);
8104 if (GET_CODE (part) == SET)
8106 if (! reload_cse_noop_set_p (part))
8108 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8112 value = SET_DEST (part);
8115 else if (GET_CODE (part) != CLOBBER)
8121 reload_cse_delete_noop_set (insn, value);
8122 /* We're done with this insn. */
8126 /* It's not a no-op, but we can try to simplify it. */
8127 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8128 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8129 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8132 apply_change_group ();
8134 reload_cse_simplify_operands (insn);
8138 /* Do a very simple CSE pass over the hard registers.
8140 This function detects no-op moves where we happened to assign two
8141 different pseudo-registers to the same hard register, and then
8142 copied one to the other. Reload will generate a useless
8143 instruction copying a register to itself.
8145 This function also detects cases where we load a value from memory
8146 into two different registers, and (if memory is more expensive than
8147 registers) changes it to simply copy the first register into the
8150 Another optimization is performed that scans the operands of each
8151 instruction to see whether the value is already available in a
8152 hard register. It then replaces the operand with the hard register
8153 if possible, much like an optional reload would. */
8156 reload_cse_regs_1 (first)
8162 init_alias_analysis ();
8164 for (insn = first; insn; insn = NEXT_INSN (insn))
8167 reload_cse_simplify (insn);
8169 cselib_process_insn (insn);
8173 end_alias_analysis ();
8177 /* Call cse / combine like post-reload optimization phases.
8178 FIRST is the first instruction. */
8180 reload_cse_regs (first)
8183 reload_cse_regs_1 (first);
8185 reload_cse_move2add (first);
8186 if (flag_expensive_optimizations)
8187 reload_cse_regs_1 (first);
8190 /* Try to simplify a single SET instruction. SET is the set pattern.
8191 INSN is the instruction it came from.
8192 This function only handles one case: if we set a register to a value
8193 which is not a register, we try to find that value in some other register
8194 and change the set into a register copy. */
8197 reload_cse_simplify_set (set, insn)
8204 enum reg_class dclass;
8207 struct elt_loc_list *l;
8208 #ifdef LOAD_EXTEND_OP
8209 enum rtx_code extend_op = NIL;
8212 dreg = true_regnum (SET_DEST (set));
8216 src = SET_SRC (set);
8217 if (side_effects_p (src) || true_regnum (src) >= 0)
8220 dclass = REGNO_REG_CLASS (dreg);
8222 #ifdef LOAD_EXTEND_OP
8223 /* When replacing a memory with a register, we need to honor assumptions
8224 that combine made wrt the contents of sign bits. We'll do this by
8225 generating an extend instruction instead of a reg->reg copy. Thus
8226 the destination must be a register that we can widen. */
8227 if (GET_CODE (src) == MEM
8228 && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD
8229 && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != NIL
8230 && GET_CODE (SET_DEST (set)) != REG)
8234 /* If memory loads are cheaper than register copies, don't change them. */
8235 if (GET_CODE (src) == MEM)
8236 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8237 else if (CONSTANT_P (src))
8238 old_cost = rtx_cost (src, SET);
8239 else if (GET_CODE (src) == REG)
8240 old_cost = REGISTER_MOVE_COST (GET_MODE (src),
8241 REGNO_REG_CLASS (REGNO (src)), dclass);
8244 old_cost = rtx_cost (src, SET);
8246 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0);
8249 for (l = val->locs; l; l = l->next)
8251 rtx this_rtx = l->loc;
8254 if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
8256 #ifdef LOAD_EXTEND_OP
8257 if (extend_op != NIL)
8259 HOST_WIDE_INT this_val;
8261 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
8262 constants, such as SYMBOL_REF, cannot be extended. */
8263 if (GET_CODE (this_rtx) != CONST_INT)
8266 this_val = INTVAL (this_rtx);
8270 this_val &= GET_MODE_MASK (GET_MODE (src));
8273 /* ??? In theory we're already extended. */
8274 if (this_val == trunc_int_for_mode (this_val, GET_MODE (src)))
8279 this_rtx = GEN_INT (this_val);
8282 this_cost = rtx_cost (this_rtx, SET);
8284 else if (GET_CODE (this_rtx) == REG)
8286 #ifdef LOAD_EXTEND_OP
8287 if (extend_op != NIL)
8289 this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
8290 this_cost = rtx_cost (this_rtx, SET);
8294 this_cost = REGISTER_MOVE_COST (GET_MODE (this_rtx),
8295 REGNO_REG_CLASS (REGNO (this_rtx)),
8301 /* If equal costs, prefer registers over anything else. That
8302 tends to lead to smaller instructions on some machines. */
8303 if (this_cost < old_cost
8304 || (this_cost == old_cost
8305 && GET_CODE (this_rtx) == REG
8306 && GET_CODE (SET_SRC (set)) != REG))
8308 #ifdef LOAD_EXTEND_OP
8309 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD
8310 && extend_op != NIL)
8312 rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set)));
8313 ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
8314 validate_change (insn, &SET_DEST (set), wide_dest, 1);
8318 validate_change (insn, &SET_SRC (set), copy_rtx (this_rtx), 1);
8319 old_cost = this_cost, did_change = 1;
8326 /* Try to replace operands in INSN with equivalent values that are already
8327 in registers. This can be viewed as optional reloading.
8329 For each non-register operand in the insn, see if any hard regs are
8330 known to be equivalent to that operand. Record the alternatives which
8331 can accept these hard registers. Among all alternatives, select the
8332 ones which are better or equal to the one currently matching, where
8333 "better" is in terms of '?' and '!' constraints. Among the remaining
8334 alternatives, select the one which replaces most operands with
8338 reload_cse_simplify_operands (insn)
8343 /* For each operand, all registers that are equivalent to it. */
8344 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8346 const char *constraints[MAX_RECOG_OPERANDS];
8348 /* Vector recording how bad an alternative is. */
8349 int *alternative_reject;
8350 /* Vector recording how many registers can be introduced by choosing
8351 this alternative. */
8352 int *alternative_nregs;
8353 /* Array of vectors recording, for each operand and each alternative,
8354 which hard register to substitute, or -1 if the operand should be
8356 int *op_alt_regno[MAX_RECOG_OPERANDS];
8357 /* Array of alternatives, sorted in order of decreasing desirability. */
8358 int *alternative_order;
8359 rtx reg = gen_rtx_REG (VOIDmode, -1);
8361 extract_insn (insn);
8363 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8366 /* Figure out which alternative currently matches. */
8367 if (! constrain_operands (1))
8368 fatal_insn_not_found (insn);
8370 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8371 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8372 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8373 memset ((char *) alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
8374 memset ((char *) alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
8376 /* For each operand, find out which regs are equivalent. */
8377 for (i = 0; i < recog_data.n_operands; i++)
8380 struct elt_loc_list *l;
8382 CLEAR_HARD_REG_SET (equiv_regs[i]);
8384 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8385 right, so avoid the problem here. Likewise if we have a constant
8386 and the insn pattern doesn't tell us the mode we need. */
8387 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL
8388 || (CONSTANT_P (recog_data.operand[i])
8389 && recog_data.operand_mode[i] == VOIDmode))
8392 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8396 for (l = v->locs; l; l = l->next)
8397 if (GET_CODE (l->loc) == REG)
8398 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8401 for (i = 0; i < recog_data.n_operands; i++)
8403 enum machine_mode mode;
8407 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8408 for (j = 0; j < recog_data.n_alternatives; j++)
8409 op_alt_regno[i][j] = -1;
8411 p = constraints[i] = recog_data.constraints[i];
8412 mode = recog_data.operand_mode[i];
8414 /* Add the reject values for each alternative given by the constraints
8415 for this operand. */
8423 alternative_reject[j] += 3;
8425 alternative_reject[j] += 300;
8428 /* We won't change operands which are already registers. We
8429 also don't want to modify output operands. */
8430 regno = true_regnum (recog_data.operand[i]);
8432 || constraints[i][0] == '='
8433 || constraints[i][0] == '+')
8436 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8438 int class = (int) NO_REGS;
8440 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8443 REGNO (reg) = regno;
8444 PUT_MODE (reg, mode);
8446 /* We found a register equal to this operand. Now look for all
8447 alternatives that can accept this register and have not been
8448 assigned a register they can use yet. */
8457 case '=': case '+': case '?':
8458 case '#': case '&': case '!':
8460 case '0': case '1': case '2': case '3': case '4':
8461 case '5': case '6': case '7': case '8': case '9':
8462 case 'm': case '<': case '>': case 'V': case 'o':
8463 case 'E': case 'F': case 'G': case 'H':
8464 case 's': case 'i': case 'n':
8465 case 'I': case 'J': case 'K': case 'L':
8466 case 'M': case 'N': case 'O': case 'P':
8468 /* These don't say anything we care about. */
8472 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8477 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char) c)];
8480 case ',': case '\0':
8481 /* See if REGNO fits this alternative, and set it up as the
8482 replacement register if we don't have one for this
8483 alternative yet and the operand being replaced is not
8484 a cheap CONST_INT. */
8485 if (op_alt_regno[i][j] == -1
8486 && reg_fits_class_p (reg, class, 0, mode)
8487 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8488 || (rtx_cost (recog_data.operand[i], SET)
8489 > rtx_cost (reg, SET))))
8491 alternative_nregs[j]++;
8492 op_alt_regno[i][j] = regno;
8504 /* Record all alternatives which are better or equal to the currently
8505 matching one in the alternative_order array. */
8506 for (i = j = 0; i < recog_data.n_alternatives; i++)
8507 if (alternative_reject[i] <= alternative_reject[which_alternative])
8508 alternative_order[j++] = i;
8509 recog_data.n_alternatives = j;
8511 /* Sort it. Given a small number of alternatives, a dumb algorithm
8512 won't hurt too much. */
8513 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8516 int best_reject = alternative_reject[alternative_order[i]];
8517 int best_nregs = alternative_nregs[alternative_order[i]];
8520 for (j = i + 1; j < recog_data.n_alternatives; j++)
8522 int this_reject = alternative_reject[alternative_order[j]];
8523 int this_nregs = alternative_nregs[alternative_order[j]];
8525 if (this_reject < best_reject
8526 || (this_reject == best_reject && this_nregs < best_nregs))
8529 best_reject = this_reject;
8530 best_nregs = this_nregs;
8534 tmp = alternative_order[best];
8535 alternative_order[best] = alternative_order[i];
8536 alternative_order[i] = tmp;
8539 /* Substitute the operands as determined by op_alt_regno for the best
8541 j = alternative_order[0];
8543 for (i = 0; i < recog_data.n_operands; i++)
8545 enum machine_mode mode = recog_data.operand_mode[i];
8546 if (op_alt_regno[i][j] == -1)
8549 validate_change (insn, recog_data.operand_loc[i],
8550 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8553 for (i = recog_data.n_dups - 1; i >= 0; i--)
8555 int op = recog_data.dup_num[i];
8556 enum machine_mode mode = recog_data.operand_mode[op];
8558 if (op_alt_regno[op][j] == -1)
8561 validate_change (insn, recog_data.dup_loc[i],
8562 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8565 return apply_change_group ();
8568 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8570 This code might also be useful when reload gave up on reg+reg addresssing
8571 because of clashes between the return register and INDEX_REG_CLASS. */
8573 /* The maximum number of uses of a register we can keep track of to
8574 replace them with reg+reg addressing. */
8575 #define RELOAD_COMBINE_MAX_USES 6
8577 /* INSN is the insn where a register has ben used, and USEP points to the
8578 location of the register within the rtl. */
8579 struct reg_use { rtx insn, *usep; };
8581 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8582 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8583 indicates where it becomes live again.
8584 Otherwise, USE_INDEX is the index of the last encountered use of the
8585 register (which is first among these we have seen since we scan backwards),
8586 OFFSET contains the constant offset that is added to the register in
8587 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8588 last, of these uses.
8589 STORE_RUID is always meaningful if we only want to use a value in a
8590 register in a different place: it denotes the next insn in the insn
8591 stream (i.e. the last ecountered) that sets or clobbers the register. */
8594 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8599 } reg_state[FIRST_PSEUDO_REGISTER];
8601 /* Reverse linear uid. This is increased in reload_combine while scanning
8602 the instructions from last to first. It is used to set last_label_ruid
8603 and the store_ruid / use_ruid fields in reg_state. */
8604 static int reload_combine_ruid;
8606 #define LABEL_LIVE(LABEL) \
8607 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8613 int first_index_reg = -1;
8614 int last_index_reg = 0;
8617 int last_label_ruid;
8618 int min_labelno, n_labels;
8619 HARD_REG_SET ever_live_at_start, *label_live;
8621 /* If reg+reg can be used in offsetable memory addresses, the main chunk of
8622 reload has already used it where appropriate, so there is no use in
8623 trying to generate it now. */
8624 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8627 /* To avoid wasting too much time later searching for an index register,
8628 determine the minimum and maximum index register numbers. */
8629 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8630 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
8632 if (first_index_reg == -1)
8633 first_index_reg = r;
8638 /* If no index register is available, we can quit now. */
8639 if (first_index_reg == -1)
8642 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8643 information is a bit fuzzy immediately after reload, but it's
8644 still good enough to determine which registers are live at a jump
8646 min_labelno = get_first_label_num ();
8647 n_labels = max_label_num () - min_labelno;
8648 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8649 CLEAR_HARD_REG_SET (ever_live_at_start);
8651 for (i = n_basic_blocks - 1; i >= 0; i--)
8653 insn = BLOCK_HEAD (i);
8654 if (GET_CODE (insn) == CODE_LABEL)
8658 REG_SET_TO_HARD_REG_SET (live,
8659 BASIC_BLOCK (i)->global_live_at_start);
8660 compute_use_by_pseudos (&live,
8661 BASIC_BLOCK (i)->global_live_at_start);
8662 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8663 IOR_HARD_REG_SET (ever_live_at_start, live);
8667 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8668 last_label_ruid = reload_combine_ruid = 0;
8669 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8671 reg_state[r].store_ruid = reload_combine_ruid;
8673 reg_state[r].use_index = -1;
8675 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8678 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8682 /* We cannot do our optimization across labels. Invalidating all the use
8683 information we have would be costly, so we just note where the label
8684 is and then later disable any optimization that would cross it. */
8685 if (GET_CODE (insn) == CODE_LABEL)
8686 last_label_ruid = reload_combine_ruid;
8687 else if (GET_CODE (insn) == BARRIER)
8688 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8689 if (! fixed_regs[r])
8690 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8692 if (! INSN_P (insn))
8695 reload_combine_ruid++;
8697 /* Look for (set (REGX) (CONST_INT))
8698 (set (REGX) (PLUS (REGX) (REGY)))
8700 ... (MEM (REGX)) ...
8702 (set (REGZ) (CONST_INT))
8704 ... (MEM (PLUS (REGZ) (REGY)))... .
8706 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8707 and that we know all uses of REGX before it dies. */
8708 set = single_set (insn);
8710 && GET_CODE (SET_DEST (set)) == REG
8711 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8712 GET_MODE (SET_DEST (set)))
8714 && GET_CODE (SET_SRC (set)) == PLUS
8715 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8716 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8717 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8719 rtx reg = SET_DEST (set);
8720 rtx plus = SET_SRC (set);
8721 rtx base = XEXP (plus, 1);
8722 rtx prev = prev_nonnote_insn (insn);
8723 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8724 unsigned int regno = REGNO (reg);
8725 rtx const_reg = NULL_RTX;
8726 rtx reg_sum = NULL_RTX;
8728 /* Now, we need an index register.
8729 We'll set index_reg to this index register, const_reg to the
8730 register that is to be loaded with the constant
8731 (denoted as REGZ in the substitution illustration above),
8732 and reg_sum to the register-register that we want to use to
8733 substitute uses of REG (typically in MEMs) with.
8734 First check REG and BASE for being index registers;
8735 we can use them even if they are not dead. */
8736 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8737 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8745 /* Otherwise, look for a free index register. Since we have
8746 checked above that neiter REG nor BASE are index registers,
8747 if we find anything at all, it will be different from these
8749 for (i = first_index_reg; i <= last_index_reg; i++)
8751 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8753 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8754 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8755 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8757 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8759 const_reg = index_reg;
8760 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8766 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8767 (REGY), i.e. BASE, is not clobbered before the last use we'll
8770 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8771 && rtx_equal_p (SET_DEST (prev_set), reg)
8772 && reg_state[regno].use_index >= 0
8773 && (reg_state[REGNO (base)].store_ruid
8774 <= reg_state[regno].use_ruid)
8779 /* Change destination register and, if necessary, the
8780 constant value in PREV, the constant loading instruction. */
8781 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8782 if (reg_state[regno].offset != const0_rtx)
8783 validate_change (prev,
8784 &SET_SRC (prev_set),
8785 GEN_INT (INTVAL (SET_SRC (prev_set))
8786 + INTVAL (reg_state[regno].offset)),
8789 /* Now for every use of REG that we have recorded, replace REG
8791 for (i = reg_state[regno].use_index;
8792 i < RELOAD_COMBINE_MAX_USES; i++)
8793 validate_change (reg_state[regno].reg_use[i].insn,
8794 reg_state[regno].reg_use[i].usep,
8795 /* Each change must have its own
8797 copy_rtx (reg_sum), 1);
8799 if (apply_change_group ())
8803 /* Delete the reg-reg addition. */
8806 if (reg_state[regno].offset != const0_rtx)
8807 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8809 for (np = ®_NOTES (prev); *np;)
8811 if (REG_NOTE_KIND (*np) == REG_EQUAL
8812 || REG_NOTE_KIND (*np) == REG_EQUIV)
8813 *np = XEXP (*np, 1);
8815 np = &XEXP (*np, 1);
8818 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8819 reg_state[REGNO (const_reg)].store_ruid
8820 = reload_combine_ruid;
8826 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8828 if (GET_CODE (insn) == CALL_INSN)
8832 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8833 if (call_used_regs[r])
8835 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8836 reg_state[r].store_ruid = reload_combine_ruid;
8839 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8840 link = XEXP (link, 1))
8842 rtx usage_rtx = XEXP (XEXP (link, 0), 0);
8843 if (GET_CODE (usage_rtx) == REG)
8846 unsigned int start_reg = REGNO (usage_rtx);
8847 unsigned int num_regs =
8848 HARD_REGNO_NREGS (start_reg, GET_MODE (usage_rtx));
8849 unsigned int end_reg = start_reg + num_regs - 1;
8850 for (i = start_reg; i <= end_reg; i++)
8851 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
8853 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8854 reg_state[i].store_ruid = reload_combine_ruid;
8857 reg_state[i].use_index = -1;
8862 else if (GET_CODE (insn) == JUMP_INSN
8863 && GET_CODE (PATTERN (insn)) != RETURN)
8865 /* Non-spill registers might be used at the call destination in
8866 some unknown fashion, so we have to mark the unknown use. */
8869 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8870 && JUMP_LABEL (insn))
8871 live = &LABEL_LIVE (JUMP_LABEL (insn));
8873 live = &ever_live_at_start;
8875 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8876 if (TEST_HARD_REG_BIT (*live, i))
8877 reg_state[i].use_index = -1;
8880 reload_combine_note_use (&PATTERN (insn), insn);
8881 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8883 if (REG_NOTE_KIND (note) == REG_INC
8884 && GET_CODE (XEXP (note, 0)) == REG)
8886 int regno = REGNO (XEXP (note, 0));
8888 reg_state[regno].store_ruid = reload_combine_ruid;
8889 reg_state[regno].use_index = -1;
8897 /* Check if DST is a register or a subreg of a register; if it is,
8898 update reg_state[regno].store_ruid and reg_state[regno].use_index
8899 accordingly. Called via note_stores from reload_combine. */
8902 reload_combine_note_store (dst, set, data)
8904 void *data ATTRIBUTE_UNUSED;
8908 enum machine_mode mode = GET_MODE (dst);
8910 if (GET_CODE (dst) == SUBREG)
8912 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
8913 GET_MODE (SUBREG_REG (dst)),
8916 dst = SUBREG_REG (dst);
8918 if (GET_CODE (dst) != REG)
8920 regno += REGNO (dst);
8922 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8923 careful with registers / register parts that are not full words.
8925 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8926 if (GET_CODE (set) != SET
8927 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8928 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8929 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8931 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8933 reg_state[i].use_index = -1;
8934 reg_state[i].store_ruid = reload_combine_ruid;
8939 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8941 reg_state[i].store_ruid = reload_combine_ruid;
8942 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8947 /* XP points to a piece of rtl that has to be checked for any uses of
8949 *XP is the pattern of INSN, or a part of it.
8950 Called from reload_combine, and recursively by itself. */
8952 reload_combine_note_use (xp, insn)
8956 enum rtx_code code = x->code;
8959 rtx offset = const0_rtx; /* For the REG case below. */
8964 if (GET_CODE (SET_DEST (x)) == REG)
8966 reload_combine_note_use (&SET_SRC (x), insn);
8972 /* If this is the USE of a return value, we can't change it. */
8973 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8975 /* Mark the return register as used in an unknown fashion. */
8976 rtx reg = XEXP (x, 0);
8977 int regno = REGNO (reg);
8978 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8980 while (--nregs >= 0)
8981 reg_state[regno + nregs].use_index = -1;
8987 if (GET_CODE (SET_DEST (x)) == REG)
8989 /* No spurious CLOBBERs of pseudo registers may remain. */
8990 if (REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER)
8997 /* We are interested in (plus (reg) (const_int)) . */
8998 if (GET_CODE (XEXP (x, 0)) != REG
8999 || GET_CODE (XEXP (x, 1)) != CONST_INT)
9001 offset = XEXP (x, 1);
9006 int regno = REGNO (x);
9010 /* No spurious USEs of pseudo registers may remain. */
9011 if (regno >= FIRST_PSEUDO_REGISTER)
9014 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
9016 /* We can't substitute into multi-hard-reg uses. */
9019 while (--nregs >= 0)
9020 reg_state[regno + nregs].use_index = -1;
9024 /* If this register is already used in some unknown fashion, we
9026 If we decrement the index from zero to -1, we can't store more
9027 uses, so this register becomes used in an unknown fashion. */
9028 use_index = --reg_state[regno].use_index;
9032 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
9034 /* We have found another use for a register that is already
9035 used later. Check if the offsets match; if not, mark the
9036 register as used in an unknown fashion. */
9037 if (! rtx_equal_p (offset, reg_state[regno].offset))
9039 reg_state[regno].use_index = -1;
9045 /* This is the first use of this register we have seen since we
9046 marked it as dead. */
9047 reg_state[regno].offset = offset;
9048 reg_state[regno].use_ruid = reload_combine_ruid;
9050 reg_state[regno].reg_use[use_index].insn = insn;
9051 reg_state[regno].reg_use[use_index].usep = xp;
9059 /* Recursively process the components of X. */
9060 fmt = GET_RTX_FORMAT (code);
9061 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9064 reload_combine_note_use (&XEXP (x, i), insn);
9065 else if (fmt[i] == 'E')
9067 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9068 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9073 /* See if we can reduce the cost of a constant by replacing a move
9074 with an add. We track situations in which a register is set to a
9075 constant or to a register plus a constant. */
9076 /* We cannot do our optimization across labels. Invalidating all the
9077 information about register contents we have would be costly, so we
9078 use move2add_last_label_luid to note where the label is and then
9079 later disable any optimization that would cross it.
9080 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9081 reg_set_luid[n] is greater than last_label_luid[n] . */
9082 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9084 /* If reg_base_reg[n] is negative, register n has been set to
9085 reg_offset[n] in mode reg_mode[n] .
9086 If reg_base_reg[n] is non-negative, register n has been set to the
9087 sum of reg_offset[n] and the value of register reg_base_reg[n]
9088 before reg_set_luid[n], calculated in mode reg_mode[n] . */
9089 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
9090 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9091 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9093 /* move2add_luid is linearily increased while scanning the instructions
9094 from first to last. It is used to set reg_set_luid in
9095 reload_cse_move2add and move2add_note_store. */
9096 static int move2add_luid;
9098 /* move2add_last_label_luid is set whenever a label is found. Labels
9099 invalidate all previously collected reg_offset data. */
9100 static int move2add_last_label_luid;
9102 /* Generate a CONST_INT and force it in the range of MODE. */
9104 static HOST_WIDE_INT
9105 sext_for_mode (mode, value)
9106 enum machine_mode mode;
9107 HOST_WIDE_INT value;
9109 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
9110 int width = GET_MODE_BITSIZE (mode);
9112 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
9114 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
9115 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
9116 cval |= (HOST_WIDE_INT) -1 << width;
9121 /* ??? We don't know how zero / sign extension is handled, hence we
9122 can't go from a narrower to a wider mode. */
9123 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
9124 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
9125 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
9126 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
9127 GET_MODE_BITSIZE (INMODE))))
9130 reload_cse_move2add (first)
9136 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9137 reg_set_luid[i] = 0;
9139 move2add_last_label_luid = 0;
9141 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9145 if (GET_CODE (insn) == CODE_LABEL)
9147 move2add_last_label_luid = move2add_luid;
9148 /* We're going to increment move2add_luid twice after a
9149 label, so that we can use move2add_last_label_luid + 1 as
9150 the luid for constants. */
9154 if (! INSN_P (insn))
9156 pat = PATTERN (insn);
9157 /* For simplicity, we only perform this optimization on
9158 straightforward SETs. */
9159 if (GET_CODE (pat) == SET
9160 && GET_CODE (SET_DEST (pat)) == REG)
9162 rtx reg = SET_DEST (pat);
9163 int regno = REGNO (reg);
9164 rtx src = SET_SRC (pat);
9166 /* Check if we have valid information on the contents of this
9167 register in the mode of REG. */
9168 if (reg_set_luid[regno] > move2add_last_label_luid
9169 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno]))
9171 /* Try to transform (set (REGX) (CONST_INT A))
9173 (set (REGX) (CONST_INT B))
9175 (set (REGX) (CONST_INT A))
9177 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9179 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9182 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9184 - reg_offset[regno]));
9185 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9186 use (set (reg) (reg)) instead.
9187 We don't delete this insn, nor do we convert it into a
9188 note, to avoid losing register notes or the return
9189 value flag. jump2 already knowns how to get rid of
9191 if (new_src == const0_rtx)
9192 success = validate_change (insn, &SET_SRC (pat), reg, 0);
9193 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9194 && have_add2_insn (reg, new_src))
9195 success = validate_change (insn, &PATTERN (insn),
9196 gen_add2_insn (reg, new_src), 0);
9197 reg_set_luid[regno] = move2add_luid;
9198 reg_mode[regno] = GET_MODE (reg);
9199 reg_offset[regno] = INTVAL (src);
9203 /* Try to transform (set (REGX) (REGY))
9204 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9207 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9210 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9212 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9213 else if (GET_CODE (src) == REG
9214 && reg_set_luid[regno] == reg_set_luid[REGNO (src)]
9215 && reg_base_reg[regno] == reg_base_reg[REGNO (src)]
9216 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg),
9217 reg_mode[REGNO (src)]))
9219 rtx next = next_nonnote_insn (insn);
9222 set = single_set (next);
9224 && SET_DEST (set) == reg
9225 && GET_CODE (SET_SRC (set)) == PLUS
9226 && XEXP (SET_SRC (set), 0) == reg
9227 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9229 rtx src3 = XEXP (SET_SRC (set), 1);
9230 HOST_WIDE_INT added_offset = INTVAL (src3);
9231 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)];
9232 HOST_WIDE_INT regno_offset = reg_offset[regno];
9233 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9239 if (new_src == const0_rtx)
9240 /* See above why we create (set (reg) (reg)) here. */
9242 = validate_change (next, &SET_SRC (set), reg, 0);
9243 else if ((rtx_cost (new_src, PLUS)
9244 < COSTS_N_INSNS (1) + rtx_cost (src3, SET))
9245 && have_add2_insn (reg, new_src))
9247 = validate_change (next, &PATTERN (next),
9248 gen_add2_insn (reg, new_src), 0);
9252 reg_mode[regno] = GET_MODE (reg);
9253 reg_offset[regno] = sext_for_mode (GET_MODE (reg),
9262 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9264 if (REG_NOTE_KIND (note) == REG_INC
9265 && GET_CODE (XEXP (note, 0)) == REG)
9267 /* Reset the information about this register. */
9268 int regno = REGNO (XEXP (note, 0));
9269 if (regno < FIRST_PSEUDO_REGISTER)
9270 reg_set_luid[regno] = 0;
9273 note_stores (PATTERN (insn), move2add_note_store, NULL);
9274 /* If this is a CALL_INSN, all call used registers are stored with
9276 if (GET_CODE (insn) == CALL_INSN)
9278 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9280 if (call_used_regs[i])
9281 /* Reset the information about this register. */
9282 reg_set_luid[i] = 0;
9288 /* SET is a SET or CLOBBER that sets DST.
9289 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9290 Called from reload_cse_move2add via note_stores. */
9293 move2add_note_store (dst, set, data)
9295 void *data ATTRIBUTE_UNUSED;
9297 unsigned int regno = 0;
9299 enum machine_mode mode = GET_MODE (dst);
9301 if (GET_CODE (dst) == SUBREG)
9303 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
9304 GET_MODE (SUBREG_REG (dst)),
9307 dst = SUBREG_REG (dst);
9310 /* Some targets do argument pushes without adding REG_INC notes. */
9312 if (GET_CODE (dst) == MEM)
9314 dst = XEXP (dst, 0);
9315 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC
9316 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
9317 reg_set_luid[REGNO (XEXP (dst, 0))] = 0;
9320 if (GET_CODE (dst) != REG)
9323 regno += REGNO (dst);
9325 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9326 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9327 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9328 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9330 rtx src = SET_SRC (set);
9332 HOST_WIDE_INT offset;
9334 /* This may be different from mode, if SET_DEST (set) is a
9336 enum machine_mode dst_mode = GET_MODE (dst);
9338 switch (GET_CODE (src))
9341 if (GET_CODE (XEXP (src, 0)) == REG)
9343 base_reg = XEXP (src, 0);
9345 if (GET_CODE (XEXP (src, 1)) == CONST_INT)
9346 offset = INTVAL (XEXP (src, 1));
9347 else if (GET_CODE (XEXP (src, 1)) == REG
9348 && (reg_set_luid[REGNO (XEXP (src, 1))]
9349 > move2add_last_label_luid)
9350 && (MODES_OK_FOR_MOVE2ADD
9351 (dst_mode, reg_mode[REGNO (XEXP (src, 1))])))
9353 if (reg_base_reg[REGNO (XEXP (src, 1))] < 0)
9354 offset = reg_offset[REGNO (XEXP (src, 1))];
9355 /* Maybe the first register is known to be a
9357 else if (reg_set_luid[REGNO (base_reg)]
9358 > move2add_last_label_luid
9359 && (MODES_OK_FOR_MOVE2ADD
9360 (dst_mode, reg_mode[REGNO (XEXP (src, 1))]))
9361 && reg_base_reg[REGNO (base_reg)] < 0)
9363 offset = reg_offset[REGNO (base_reg)];
9364 base_reg = XEXP (src, 1);
9383 /* Start tracking the register as a constant. */
9384 reg_base_reg[regno] = -1;
9385 reg_offset[regno] = INTVAL (SET_SRC (set));
9386 /* We assign the same luid to all registers set to constants. */
9387 reg_set_luid[regno] = move2add_last_label_luid + 1;
9388 reg_mode[regno] = mode;
9393 /* Invalidate the contents of the register. */
9394 reg_set_luid[regno] = 0;
9398 base_regno = REGNO (base_reg);
9399 /* If information about the base register is not valid, set it
9400 up as a new base register, pretending its value is known
9401 starting from the current insn. */
9402 if (reg_set_luid[base_regno] <= move2add_last_label_luid)
9404 reg_base_reg[base_regno] = base_regno;
9405 reg_offset[base_regno] = 0;
9406 reg_set_luid[base_regno] = move2add_luid;
9407 reg_mode[base_regno] = mode;
9409 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode,
9410 reg_mode[base_regno]))
9413 reg_mode[regno] = mode;
9415 /* Copy base information from our base register. */
9416 reg_set_luid[regno] = reg_set_luid[base_regno];
9417 reg_base_reg[regno] = reg_base_reg[base_regno];
9419 /* Compute the sum of the offsets or constants. */
9420 reg_offset[regno] = sext_for_mode (dst_mode,
9422 + reg_offset[base_regno]);
9426 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9428 for (i = regno; i < endregno; i++)
9429 /* Reset the information about this register. */
9430 reg_set_luid[i] = 0;
9436 add_auto_inc_notes (insn, x)
9440 enum rtx_code code = GET_CODE (x);
9444 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9447 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9451 /* Scan all the operand sub-expressions. */
9452 fmt = GET_RTX_FORMAT (code);
9453 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9456 add_auto_inc_notes (insn, XEXP (x, i));
9457 else if (fmt[i] == 'E')
9458 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9459 add_auto_inc_notes (insn, XVECEXP (x, i, j));
9464 /* Copy EH notes from an insn to its reloads. */
9466 copy_eh_notes (insn, x)
9470 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
9473 for (; x != 0; x = NEXT_INSN (x))
9475 if (may_trap_p (PATTERN (x)))
9477 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
9483 /* This is used by reload pass, that does emit some instructions after
9484 abnormal calls moving basic block end, but in fact it wants to emit
9485 them on the edge. Looks for abnormal call edges, find backward the
9486 proper call and fix the damage.
9488 Similar handle instructions throwing exceptions internally. */
9490 fixup_abnormal_edges ()
9493 bool inserted = false;
9495 for (i = 0; i < n_basic_blocks; i++)
9497 basic_block bb = BASIC_BLOCK (i);
9500 /* Look for cases we are interested in - an calls or instructions causing
9502 for (e = bb->succ; e; e = e->succ_next)
9504 if (e->flags & EDGE_ABNORMAL_CALL)
9506 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
9507 == (EDGE_ABNORMAL | EDGE_EH))
9510 if (e && GET_CODE (bb->end) != CALL_INSN && !can_throw_internal (bb->end))
9512 rtx insn = bb->end, stop = NEXT_INSN (bb->end);
9514 for (e = bb->succ; e; e = e->succ_next)
9515 if (e->flags & EDGE_FALLTHRU)
9517 /* Get past the new insns generated. Allow notes, as the insns may
9518 be already deleted. */
9519 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE)
9520 && !can_throw_internal (insn)
9521 && insn != bb->head)
9522 insn = PREV_INSN (insn);
9523 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn))
9527 insn = NEXT_INSN (insn);
9528 while (insn && insn != stop)
9530 next = NEXT_INSN (insn);
9537 /* We're not deleting it, we're moving it. */
9538 INSN_DELETED_P (insn) = 0;
9540 /* Emit a sequence, rather than scarfing the pattern, so
9541 that we don't lose REG_NOTES etc. */
9542 /* ??? Could copy the test from gen_sequence, but don't
9543 think it's worth the bother. */
9544 seq = gen_rtx_SEQUENCE (VOIDmode, gen_rtvec (1, insn));
9545 insert_insn_on_edge (seq, e);
9552 commit_edge_insertions ();
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