1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 88, 89, 92-97, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "insn-flags.h"
31 #include "insn-codes.h"
35 #include "basic-block.h"
42 /* This file contains the reload pass of the compiler, which is
43 run after register allocation has been done. It checks that
44 each insn is valid (operands required to be in registers really
45 are in registers of the proper class) and fixes up invalid ones
46 by copying values temporarily into registers for the insns
49 The results of register allocation are described by the vector
50 reg_renumber; the insns still contain pseudo regs, but reg_renumber
51 can be used to find which hard reg, if any, a pseudo reg is in.
53 The technique we always use is to free up a few hard regs that are
54 called ``reload regs'', and for each place where a pseudo reg
55 must be in a hard reg, copy it temporarily into one of the reload regs.
57 Reload regs are allocated locally for every instruction that needs
58 reloads. When there are pseudos which are allocated to a register that
59 has been chosen as a reload reg, such pseudos must be ``spilled''.
60 This means that they go to other hard regs, or to stack slots if no other
61 available hard regs can be found. Spilling can invalidate more
62 insns, requiring additional need for reloads, so we must keep checking
63 until the process stabilizes.
65 For machines with different classes of registers, we must keep track
66 of the register class needed for each reload, and make sure that
67 we allocate enough reload registers of each class.
69 The file reload.c contains the code that checks one insn for
70 validity and reports the reloads that it needs. This file
71 is in charge of scanning the entire rtl code, accumulating the
72 reload needs, spilling, assigning reload registers to use for
73 fixing up each insn, and generating the new insns to copy values
74 into the reload registers. */
77 #ifndef REGISTER_MOVE_COST
78 #define REGISTER_MOVE_COST(x, y) 2
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
106 This is used when the address is not valid as a memory address
107 (because its displacement is too big for the machine.) */
108 rtx *reg_equiv_address;
110 /* Element N is the memory slot to which pseudo reg N is equivalent,
111 or zero if pseudo reg N is not equivalent to a memory slot. */
114 /* Widest width in which each pseudo reg is referred to (via subreg). */
115 static int *reg_max_ref_width;
117 /* Element N is the insn that initialized reg N from its equivalent
118 constant or memory slot. */
119 static rtx *reg_equiv_init;
121 /* Vector to remember old contents of reg_renumber before spilling. */
122 static short *reg_old_renumber;
124 /* During reload_as_needed, element N contains the last pseudo regno reloaded
125 into hard register N. If that pseudo reg occupied more than one register,
126 reg_reloaded_contents points to that pseudo for each spill register in
127 use; all of these must remain set for an inheritance to occur. */
128 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
130 /* During reload_as_needed, element N contains the insn for which
131 hard register N was last used. Its contents are significant only
132 when reg_reloaded_valid is set for this register. */
133 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
135 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
136 static HARD_REG_SET reg_reloaded_valid;
137 /* Indicate if the register was dead at the end of the reload.
138 This is only valid if reg_reloaded_contents is set and valid. */
139 static HARD_REG_SET reg_reloaded_dead;
141 /* Number of spill-regs so far; number of valid elements of spill_regs. */
144 /* In parallel with spill_regs, contains REG rtx's for those regs.
145 Holds the last rtx used for any given reg, or 0 if it has never
146 been used for spilling yet. This rtx is reused, provided it has
148 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
150 /* In parallel with spill_regs, contains nonzero for a spill reg
151 that was stored after the last time it was used.
152 The precise value is the insn generated to do the store. */
153 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
155 /* This is the register that was stored with spill_reg_store. This is a
156 copy of reload_out / reload_out_reg when the value was stored; if
157 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
158 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
160 /* This table is the inverse mapping of spill_regs:
161 indexed by hard reg number,
162 it contains the position of that reg in spill_regs,
163 or -1 for something that is not in spill_regs.
165 ?!? This is no longer accurate. */
166 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
168 /* This reg set indicates registers that can't be used as spill registers for
169 the currently processed insn. These are the hard registers which are live
170 during the insn, but not allocated to pseudos, as well as fixed
172 static HARD_REG_SET bad_spill_regs;
174 /* These are the hard registers that can't be used as spill register for any
175 insn. This includes registers used for user variables and registers that
176 we can't eliminate. A register that appears in this set also can't be used
177 to retry register allocation. */
178 static HARD_REG_SET bad_spill_regs_global;
180 /* Describes order of use of registers for reloading
181 of spilled pseudo-registers. `n_spills' is the number of
182 elements that are actually valid; new ones are added at the end.
184 Both spill_regs and spill_reg_order are used on two occasions:
185 once during find_reload_regs, where they keep track of the spill registers
186 for a single insn, but also during reload_as_needed where they show all
187 the registers ever used by reload. For the latter case, the information
188 is calculated during finish_spills. */
189 static short spill_regs[FIRST_PSEUDO_REGISTER];
191 /* This vector of reg sets indicates, for each pseudo, which hard registers
192 may not be used for retrying global allocation because the register was
193 formerly spilled from one of them. If we allowed reallocating a pseudo to
194 a register that it was already allocated to, reload might not
196 static HARD_REG_SET *pseudo_previous_regs;
198 /* This vector of reg sets indicates, for each pseudo, which hard
199 registers may not be used for retrying global allocation because they
200 are used as spill registers during one of the insns in which the
202 static HARD_REG_SET *pseudo_forbidden_regs;
204 /* All hard regs that have been used as spill registers for any insn are
205 marked in this set. */
206 static HARD_REG_SET used_spill_regs;
208 /* Index of last register assigned as a spill register. We allocate in
209 a round-robin fashion. */
210 static int last_spill_reg;
212 /* Describes order of preference for putting regs into spill_regs.
213 Contains the numbers of all the hard regs, in order most preferred first.
214 This order is different for each function.
215 It is set up by order_regs_for_reload.
216 Empty elements at the end contain -1. */
217 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
219 /* Nonzero if indirect addressing is supported on the machine; this means
220 that spilling (REG n) does not require reloading it into a register in
221 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
222 value indicates the level of indirect addressing supported, e.g., two
223 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
225 static char spill_indirect_levels;
227 /* Nonzero if indirect addressing is supported when the innermost MEM is
228 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
229 which these are valid is the same as spill_indirect_levels, above. */
230 char indirect_symref_ok;
232 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
233 char double_reg_address_ok;
235 /* Record the stack slot for each spilled hard register. */
236 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
238 /* Width allocated so far for that stack slot. */
239 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
241 /* Record which pseudos needed to be spilled. */
242 static regset spilled_pseudos;
244 /* First uid used by insns created by reload in this function.
245 Used in find_equiv_reg. */
246 int reload_first_uid;
248 /* Flag set by local-alloc or global-alloc if anything is live in
249 a call-clobbered reg across calls. */
250 int caller_save_needed;
252 /* Set to 1 while reload_as_needed is operating.
253 Required by some machines to handle any generated moves differently. */
254 int reload_in_progress = 0;
256 /* These arrays record the insn_code of insns that may be needed to
257 perform input and output reloads of special objects. They provide a
258 place to pass a scratch register. */
259 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
260 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
262 /* This obstack is used for allocation of rtl during register elimination.
263 The allocated storage can be freed once find_reloads has processed the
265 struct obstack reload_obstack;
267 /* Points to the beginning of the reload_obstack. All insn_chain structures
268 are allocated first. */
269 char *reload_startobj;
271 /* The point after all insn_chain structures. Used to quickly deallocate
272 memory used while processing one insn. */
273 char *reload_firstobj;
275 #define obstack_chunk_alloc xmalloc
276 #define obstack_chunk_free free
278 /* List of labels that must never be deleted. */
279 extern rtx forced_labels;
281 /* List of insn_chain instructions, one for every insn that reload needs to
283 struct insn_chain *reload_insn_chain;
285 /* List of all insns needing reloads. */
286 static struct insn_chain *insns_need_reload;
288 /* This structure is used to record information about register eliminations.
289 Each array entry describes one possible way of eliminating a register
290 in favor of another. If there is more than one way of eliminating a
291 particular register, the most preferred should be specified first. */
295 int from; /* Register number to be eliminated. */
296 int to; /* Register number used as replacement. */
297 int initial_offset; /* Initial difference between values. */
298 int can_eliminate; /* Non-zero if this elimination can be done. */
299 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
300 insns made by reload. */
301 int offset; /* Current offset between the two regs. */
302 int previous_offset; /* Offset at end of previous insn. */
303 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
304 rtx from_rtx; /* REG rtx for the register to be eliminated.
305 We cannot simply compare the number since
306 we might then spuriously replace a hard
307 register corresponding to a pseudo
308 assigned to the reg to be eliminated. */
309 rtx to_rtx; /* REG rtx for the replacement. */
312 static struct elim_table * reg_eliminate = 0;
314 /* This is an intermediate structure to initialize the table. It has
315 exactly the members provided by ELIMINABLE_REGS. */
316 static struct elim_table_1
320 } reg_eliminate_1[] =
322 /* If a set of eliminable registers was specified, define the table from it.
323 Otherwise, default to the normal case of the frame pointer being
324 replaced by the stack pointer. */
326 #ifdef ELIMINABLE_REGS
329 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
332 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate_1/sizeof reg_eliminate_1[0])
334 /* Record the number of pending eliminations that have an offset not equal
335 to their initial offset. If non-zero, we use a new copy of each
336 replacement result in any insns encountered. */
337 int num_not_at_initial_offset;
339 /* Count the number of registers that we may be able to eliminate. */
340 static int num_eliminable;
342 /* For each label, we record the offset of each elimination. If we reach
343 a label by more than one path and an offset differs, we cannot do the
344 elimination. This information is indexed by the number of the label.
345 The first table is an array of flags that records whether we have yet
346 encountered a label and the second table is an array of arrays, one
347 entry in the latter array for each elimination. */
349 static char *offsets_known_at;
350 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
352 /* Number of labels in the current function. */
354 static int num_labels;
356 struct hard_reg_n_uses
362 static void maybe_fix_stack_asms PROTO((void));
363 static void calculate_needs_all_insns PROTO((int));
364 static void calculate_needs PROTO((struct insn_chain *));
365 static void find_reload_regs PROTO((struct insn_chain *chain,
367 static void find_tworeg_group PROTO((struct insn_chain *, int,
369 static void find_group PROTO((struct insn_chain *, int,
371 static int possible_group_p PROTO((struct insn_chain *, int));
372 static void count_possible_groups PROTO((struct insn_chain *, int));
373 static int modes_equiv_for_class_p PROTO((enum machine_mode,
376 static void delete_caller_save_insns PROTO((void));
378 static void spill_failure PROTO((rtx));
379 static void new_spill_reg PROTO((struct insn_chain *, int, int,
381 static void maybe_mark_pseudo_spilled PROTO((int));
382 static void delete_dead_insn PROTO((rtx));
383 static void alter_reg PROTO((int, int));
384 static void set_label_offsets PROTO((rtx, rtx, int));
385 static int eliminate_regs_in_insn PROTO((rtx, int));
386 static void update_eliminable_offsets PROTO((void));
387 static void mark_not_eliminable PROTO((rtx, rtx));
388 static void set_initial_elim_offsets PROTO((void));
389 static void verify_initial_elim_offsets PROTO((void));
390 static void set_initial_label_offsets PROTO((void));
391 static void set_offsets_for_label PROTO((rtx));
392 static void init_elim_table PROTO((void));
393 static void update_eliminables PROTO((HARD_REG_SET *));
394 static void spill_hard_reg PROTO((int, FILE *, int));
395 static int finish_spills PROTO((int, FILE *));
396 static void ior_hard_reg_set PROTO((HARD_REG_SET *, HARD_REG_SET *));
397 static void scan_paradoxical_subregs PROTO((rtx));
398 static int hard_reg_use_compare PROTO((const GENERIC_PTR, const GENERIC_PTR));
399 static void count_pseudo PROTO((struct hard_reg_n_uses *, int));
400 static void order_regs_for_reload PROTO((struct insn_chain *));
401 static void reload_as_needed PROTO((int));
402 static void forget_old_reloads_1 PROTO((rtx, rtx));
403 static int reload_reg_class_lower PROTO((const GENERIC_PTR, const GENERIC_PTR));
404 static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
406 static void clear_reload_reg_in_use PROTO((int, int, enum reload_type,
408 static int reload_reg_free_p PROTO((int, int, enum reload_type));
409 static int reload_reg_free_before_p PROTO((int, int, enum reload_type, int));
410 static int reload_reg_free_for_value_p PROTO((int, int, enum reload_type, rtx, rtx, int));
411 static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
412 static int allocate_reload_reg PROTO((struct insn_chain *, int, int,
414 static void choose_reload_regs PROTO((struct insn_chain *));
415 static void merge_assigned_reloads PROTO((rtx));
416 static void emit_reload_insns PROTO((struct insn_chain *));
417 static void delete_output_reload PROTO((rtx, int, int));
418 static void delete_address_reloads PROTO((rtx, rtx));
419 static void delete_address_reloads_1 PROTO((rtx, rtx, rtx));
420 static rtx inc_for_reload PROTO((rtx, rtx, rtx, int));
421 static int constraint_accepts_reg_p PROTO((char *, rtx));
422 static void reload_cse_regs_1 PROTO((rtx));
423 static void reload_cse_invalidate_regno PROTO((int, enum machine_mode, int));
424 static int reload_cse_mem_conflict_p PROTO((rtx, rtx));
425 static void reload_cse_invalidate_mem PROTO((rtx));
426 static void reload_cse_invalidate_rtx PROTO((rtx, rtx));
427 static int reload_cse_regno_equal_p PROTO((int, rtx, enum machine_mode));
428 static int reload_cse_noop_set_p PROTO((rtx, rtx));
429 static int reload_cse_simplify_set PROTO((rtx, rtx));
430 static int reload_cse_simplify_operands PROTO((rtx));
431 static void reload_cse_check_clobber PROTO((rtx, rtx));
432 static void reload_cse_record_set PROTO((rtx, rtx));
433 static void reload_combine PROTO((void));
434 static void reload_combine_note_use PROTO((rtx *, rtx));
435 static void reload_combine_note_store PROTO((rtx, rtx));
436 static void reload_cse_move2add PROTO((rtx));
437 static void move2add_note_store PROTO((rtx, rtx));
439 /* Initialize the reload pass once per compilation. */
446 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
447 Set spill_indirect_levels to the number of levels such addressing is
448 permitted, zero if it is not permitted at all. */
451 = gen_rtx_MEM (Pmode,
453 gen_rtx_REG (Pmode, LAST_VIRTUAL_REGISTER + 1),
455 spill_indirect_levels = 0;
457 while (memory_address_p (QImode, tem))
459 spill_indirect_levels++;
460 tem = gen_rtx_MEM (Pmode, tem);
463 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
465 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
466 indirect_symref_ok = memory_address_p (QImode, tem);
468 /* See if reg+reg is a valid (and offsettable) address. */
470 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
472 tem = gen_rtx_PLUS (Pmode,
473 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
474 gen_rtx_REG (Pmode, i));
475 /* This way, we make sure that reg+reg is an offsettable address. */
476 tem = plus_constant (tem, 4);
478 if (memory_address_p (QImode, tem))
480 double_reg_address_ok = 1;
485 /* Initialize obstack for our rtl allocation. */
486 gcc_obstack_init (&reload_obstack);
487 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
490 /* List of insn chains that are currently unused. */
491 static struct insn_chain *unused_insn_chains = 0;
493 /* Allocate an empty insn_chain structure. */
497 struct insn_chain *c;
499 if (unused_insn_chains == 0)
501 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
502 c->live_before = OBSTACK_ALLOC_REG_SET (&reload_obstack);
503 c->live_after = OBSTACK_ALLOC_REG_SET (&reload_obstack);
507 c = unused_insn_chains;
508 unused_insn_chains = c->next;
510 c->is_caller_save_insn = 0;
511 c->need_operand_change = 0;
517 /* Small utility function to set all regs in hard reg set TO which are
518 allocated to pseudos in regset FROM. */
520 compute_use_by_pseudos (to, from)
525 EXECUTE_IF_SET_IN_REG_SET
526 (from, FIRST_PSEUDO_REGISTER, regno,
528 int r = reg_renumber[regno];
532 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
534 SET_HARD_REG_BIT (*to, r + nregs);
538 /* Global variables used by reload and its subroutines. */
540 /* Set during calculate_needs if an insn needs register elimination. */
541 static int something_needs_elimination;
542 /* Set during calculate_needs if an insn needs an operand changed. */
543 int something_needs_operands_changed;
545 /* Nonzero means we couldn't get enough spill regs. */
548 /* Main entry point for the reload pass.
550 FIRST is the first insn of the function being compiled.
552 GLOBAL nonzero means we were called from global_alloc
553 and should attempt to reallocate any pseudoregs that we
554 displace from hard regs we will use for reloads.
555 If GLOBAL is zero, we do not have enough information to do that,
556 so any pseudo reg that is spilled must go to the stack.
558 DUMPFILE is the global-reg debugging dump file stream, or 0.
559 If it is nonzero, messages are written to it to describe
560 which registers are seized as reload regs, which pseudo regs
561 are spilled from them, and where the pseudo regs are reallocated to.
563 Return value is nonzero if reload failed
564 and we must not do any more for this function. */
567 reload (first, global, dumpfile)
574 register struct elim_table *ep;
576 /* The two pointers used to track the true location of the memory used
577 for label offsets. */
578 char *real_known_ptr = NULL_PTR;
579 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
581 /* Make sure even insns with volatile mem refs are recognizable. */
586 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
588 /* Make sure that the last insn in the chain
589 is not something that needs reloading. */
590 emit_note (NULL_PTR, NOTE_INSN_DELETED);
592 /* Enable find_equiv_reg to distinguish insns made by reload. */
593 reload_first_uid = get_max_uid ();
595 #ifdef SECONDARY_MEMORY_NEEDED
596 /* Initialize the secondary memory table. */
597 clear_secondary_mem ();
600 /* We don't have a stack slot for any spill reg yet. */
601 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
602 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
604 /* Initialize the save area information for caller-save, in case some
608 /* Compute which hard registers are now in use
609 as homes for pseudo registers.
610 This is done here rather than (eg) in global_alloc
611 because this point is reached even if not optimizing. */
612 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
615 /* A function that receives a nonlocal goto must save all call-saved
617 if (current_function_has_nonlocal_label)
618 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
620 if (! call_used_regs[i] && ! fixed_regs[i])
621 regs_ever_live[i] = 1;
624 /* Find all the pseudo registers that didn't get hard regs
625 but do have known equivalent constants or memory slots.
626 These include parameters (known equivalent to parameter slots)
627 and cse'd or loop-moved constant memory addresses.
629 Record constant equivalents in reg_equiv_constant
630 so they will be substituted by find_reloads.
631 Record memory equivalents in reg_mem_equiv so they can
632 be substituted eventually by altering the REG-rtx's. */
634 reg_equiv_constant = (rtx *) xmalloc (max_regno * sizeof (rtx));
635 bzero ((char *) reg_equiv_constant, max_regno * sizeof (rtx));
636 reg_equiv_memory_loc = (rtx *) xmalloc (max_regno * sizeof (rtx));
637 bzero ((char *) reg_equiv_memory_loc, max_regno * sizeof (rtx));
638 reg_equiv_mem = (rtx *) xmalloc (max_regno * sizeof (rtx));
639 bzero ((char *) reg_equiv_mem, max_regno * sizeof (rtx));
640 reg_equiv_init = (rtx *) xmalloc (max_regno * sizeof (rtx));
641 bzero ((char *) reg_equiv_init, max_regno * sizeof (rtx));
642 reg_equiv_address = (rtx *) xmalloc (max_regno * sizeof (rtx));
643 bzero ((char *) reg_equiv_address, max_regno * sizeof (rtx));
644 reg_max_ref_width = (int *) xmalloc (max_regno * sizeof (int));
645 bzero ((char *) reg_max_ref_width, max_regno * sizeof (int));
646 reg_old_renumber = (short *) xmalloc (max_regno * sizeof (short));
647 bcopy (reg_renumber, reg_old_renumber, max_regno * sizeof (short));
648 pseudo_forbidden_regs
649 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
651 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
653 CLEAR_HARD_REG_SET (bad_spill_regs_global);
654 bzero ((char *) pseudo_previous_regs, max_regno * sizeof (HARD_REG_SET));
656 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
657 Also find all paradoxical subregs and find largest such for each pseudo.
658 On machines with small register classes, record hard registers that
659 are used for user variables. These can never be used for spills.
660 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
661 caller-saved registers must be marked live. */
663 for (insn = first; insn; insn = NEXT_INSN (insn))
665 rtx set = single_set (insn);
667 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
668 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
669 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
670 if (! call_used_regs[i])
671 regs_ever_live[i] = 1;
673 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
675 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
677 #ifdef LEGITIMATE_PIC_OPERAND_P
678 && (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic
679 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
683 rtx x = XEXP (note, 0);
684 i = REGNO (SET_DEST (set));
685 if (i > LAST_VIRTUAL_REGISTER)
687 if (GET_CODE (x) == MEM)
689 /* If the operand is a PLUS, the MEM may be shared,
690 so make sure we have an unshared copy here. */
691 if (GET_CODE (XEXP (x, 0)) == PLUS)
694 reg_equiv_memory_loc[i] = x;
696 else if (CONSTANT_P (x))
698 if (LEGITIMATE_CONSTANT_P (x))
699 reg_equiv_constant[i] = x;
701 reg_equiv_memory_loc[i]
702 = force_const_mem (GET_MODE (SET_DEST (set)), x);
707 /* If this register is being made equivalent to a MEM
708 and the MEM is not SET_SRC, the equivalencing insn
709 is one with the MEM as a SET_DEST and it occurs later.
710 So don't mark this insn now. */
711 if (GET_CODE (x) != MEM
712 || rtx_equal_p (SET_SRC (set), x))
713 reg_equiv_init[i] = insn;
718 /* If this insn is setting a MEM from a register equivalent to it,
719 this is the equivalencing insn. */
720 else if (set && GET_CODE (SET_DEST (set)) == MEM
721 && GET_CODE (SET_SRC (set)) == REG
722 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
723 && rtx_equal_p (SET_DEST (set),
724 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
725 reg_equiv_init[REGNO (SET_SRC (set))] = insn;
727 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
728 scan_paradoxical_subregs (PATTERN (insn));
733 num_labels = max_label_num () - get_first_label_num ();
735 /* Allocate the tables used to store offset information at labels. */
736 /* We used to use alloca here, but the size of what it would try to
737 allocate would occasionally cause it to exceed the stack limit and
738 cause a core dump. */
739 real_known_ptr = xmalloc (num_labels);
741 = (int (*)[NUM_ELIMINABLE_REGS])
742 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
744 offsets_known_at = real_known_ptr - get_first_label_num ();
746 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
748 /* Alter each pseudo-reg rtx to contain its hard reg number.
749 Assign stack slots to the pseudos that lack hard regs or equivalents.
750 Do not touch virtual registers. */
752 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
755 /* If we have some registers we think can be eliminated, scan all insns to
756 see if there is an insn that sets one of these registers to something
757 other than itself plus a constant. If so, the register cannot be
758 eliminated. Doing this scan here eliminates an extra pass through the
759 main reload loop in the most common case where register elimination
761 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
762 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
763 || GET_CODE (insn) == CALL_INSN)
764 note_stores (PATTERN (insn), mark_not_eliminable);
766 #ifndef REGISTER_CONSTRAINTS
767 /* If all the pseudo regs have hard regs,
768 except for those that are never referenced,
769 we know that no reloads are needed. */
770 /* But that is not true if there are register constraints, since
771 in that case some pseudos might be in the wrong kind of hard reg. */
773 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
774 if (reg_renumber[i] == -1 && REG_N_REFS (i) != 0)
777 if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
779 free (real_known_ptr);
781 free (reg_equiv_constant);
782 free (reg_equiv_memory_loc);
783 free (reg_equiv_mem);
784 free (reg_equiv_init);
785 free (reg_equiv_address);
786 free (reg_max_ref_width);
787 free (reg_old_renumber);
788 free (pseudo_previous_regs);
789 free (pseudo_forbidden_regs);
794 maybe_fix_stack_asms ();
796 insns_need_reload = 0;
797 something_needs_elimination = 0;
799 /* Initialize to -1, which means take the first spill register. */
802 spilled_pseudos = ALLOCA_REG_SET ();
804 /* Spill any hard regs that we know we can't eliminate. */
805 CLEAR_HARD_REG_SET (used_spill_regs);
806 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
807 if (! ep->can_eliminate)
808 spill_hard_reg (ep->from, dumpfile, 1);
810 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
811 if (frame_pointer_needed)
812 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, dumpfile, 1);
814 finish_spills (global, dumpfile);
816 /* From now on, we need to emit any moves without making new pseudos. */
817 reload_in_progress = 1;
819 /* This loop scans the entire function each go-round
820 and repeats until one repetition spills no additional hard regs. */
823 int something_changed;
825 struct insn_chain *chain;
827 HOST_WIDE_INT starting_frame_size;
829 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done
830 here because the stack size may be a part of the offset computation
831 for register elimination, and there might have been new stack slots
832 created in the last iteration of this loop. */
833 assign_stack_local (BLKmode, 0, 0);
835 starting_frame_size = get_frame_size ();
837 set_initial_elim_offsets ();
838 set_initial_label_offsets ();
840 /* For each pseudo register that has an equivalent location defined,
841 try to eliminate any eliminable registers (such as the frame pointer)
842 assuming initial offsets for the replacement register, which
845 If the resulting location is directly addressable, substitute
846 the MEM we just got directly for the old REG.
848 If it is not addressable but is a constant or the sum of a hard reg
849 and constant, it is probably not addressable because the constant is
850 out of range, in that case record the address; we will generate
851 hairy code to compute the address in a register each time it is
852 needed. Similarly if it is a hard register, but one that is not
853 valid as an address register.
855 If the location is not addressable, but does not have one of the
856 above forms, assign a stack slot. We have to do this to avoid the
857 potential of producing lots of reloads if, e.g., a location involves
858 a pseudo that didn't get a hard register and has an equivalent memory
859 location that also involves a pseudo that didn't get a hard register.
861 Perhaps at some point we will improve reload_when_needed handling
862 so this problem goes away. But that's very hairy. */
864 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
865 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
867 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
869 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
871 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
872 else if (CONSTANT_P (XEXP (x, 0))
873 || (GET_CODE (XEXP (x, 0)) == REG
874 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
875 || (GET_CODE (XEXP (x, 0)) == PLUS
876 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
877 && (REGNO (XEXP (XEXP (x, 0), 0))
878 < FIRST_PSEUDO_REGISTER)
879 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
880 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
883 /* Make a new stack slot. Then indicate that something
884 changed so we go back and recompute offsets for
885 eliminable registers because the allocation of memory
886 below might change some offset. reg_equiv_{mem,address}
887 will be set up for this pseudo on the next pass around
889 reg_equiv_memory_loc[i] = 0;
890 reg_equiv_init[i] = 0;
895 if (caller_save_needed)
898 /* If we allocated another stack slot, redo elimination bookkeeping. */
899 if (starting_frame_size != get_frame_size ())
902 if (caller_save_needed)
904 save_call_clobbered_regs ();
905 /* That might have allocated new insn_chain structures. */
906 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
909 calculate_needs_all_insns (global);
911 CLEAR_REG_SET (spilled_pseudos);
914 something_changed = 0;
916 /* If we allocated any new memory locations, make another pass
917 since it might have changed elimination offsets. */
918 if (starting_frame_size != get_frame_size ())
919 something_changed = 1;
922 HARD_REG_SET to_spill;
923 CLEAR_HARD_REG_SET (to_spill);
924 update_eliminables (&to_spill);
925 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
926 if (TEST_HARD_REG_BIT (to_spill, i))
928 spill_hard_reg (i, dumpfile, 1);
931 /* Regardless of the state of spills, if we previously had
932 a register that we thought we could eliminate, but no can
933 not eliminate, we must run another pass.
935 Consider pseudos which have an entry in reg_equiv_* which
936 reference an eliminable register. We must make another pass
937 to update reg_equiv_* so that we do not substitute in the
938 old value from when we thought the elimination could be
940 something_changed = 1;
944 CLEAR_HARD_REG_SET (used_spill_regs);
945 /* Try to satisfy the needs for each insn. */
946 for (chain = insns_need_reload; chain != 0;
947 chain = chain->next_need_reload)
948 find_reload_regs (chain, dumpfile);
953 if (insns_need_reload != 0 || did_spill)
954 something_changed |= finish_spills (global, dumpfile);
956 if (! something_changed)
959 if (caller_save_needed)
960 delete_caller_save_insns ();
963 /* If global-alloc was run, notify it of any register eliminations we have
966 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
967 if (ep->can_eliminate)
968 mark_elimination (ep->from, ep->to);
970 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
971 If that insn didn't set the register (i.e., it copied the register to
972 memory), just delete that insn instead of the equivalencing insn plus
973 anything now dead. If we call delete_dead_insn on that insn, we may
974 delete the insn that actually sets the register if the register die
975 there and that is incorrect. */
977 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
978 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0
979 && GET_CODE (reg_equiv_init[i]) != NOTE)
981 if (reg_set_p (regno_reg_rtx[i], PATTERN (reg_equiv_init[i])))
982 delete_dead_insn (reg_equiv_init[i]);
985 PUT_CODE (reg_equiv_init[i], NOTE);
986 NOTE_SOURCE_FILE (reg_equiv_init[i]) = 0;
987 NOTE_LINE_NUMBER (reg_equiv_init[i]) = NOTE_INSN_DELETED;
991 /* Use the reload registers where necessary
992 by generating move instructions to move the must-be-register
993 values into or out of the reload registers. */
995 if (insns_need_reload != 0 || something_needs_elimination
996 || something_needs_operands_changed)
998 int old_frame_size = get_frame_size ();
1000 reload_as_needed (global);
1002 if (old_frame_size != get_frame_size ())
1006 verify_initial_elim_offsets ();
1009 /* If we were able to eliminate the frame pointer, show that it is no
1010 longer live at the start of any basic block. If it ls live by
1011 virtue of being in a pseudo, that pseudo will be marked live
1012 and hence the frame pointer will be known to be live via that
1015 if (! frame_pointer_needed)
1016 for (i = 0; i < n_basic_blocks; i++)
1017 CLEAR_REGNO_REG_SET (basic_block_live_at_start[i],
1018 HARD_FRAME_POINTER_REGNUM);
1020 /* Come here (with failure set nonzero) if we can't get enough spill regs
1021 and we decide not to abort about it. */
1024 reload_in_progress = 0;
1026 /* Now eliminate all pseudo regs by modifying them into
1027 their equivalent memory references.
1028 The REG-rtx's for the pseudos are modified in place,
1029 so all insns that used to refer to them now refer to memory.
1031 For a reg that has a reg_equiv_address, all those insns
1032 were changed by reloading so that no insns refer to it any longer;
1033 but the DECL_RTL of a variable decl may refer to it,
1034 and if so this causes the debugging info to mention the variable. */
1036 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1040 int is_readonly = 0;
1042 if (reg_equiv_memory_loc[i])
1044 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1045 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1048 if (reg_equiv_mem[i])
1049 addr = XEXP (reg_equiv_mem[i], 0);
1051 if (reg_equiv_address[i])
1052 addr = reg_equiv_address[i];
1056 if (reg_renumber[i] < 0)
1058 rtx reg = regno_reg_rtx[i];
1059 XEXP (reg, 0) = addr;
1060 REG_USERVAR_P (reg) = 0;
1061 RTX_UNCHANGING_P (reg) = is_readonly;
1062 MEM_IN_STRUCT_P (reg) = in_struct;
1063 /* We have no alias information about this newly created
1065 MEM_ALIAS_SET (reg) = 0;
1066 PUT_CODE (reg, MEM);
1068 else if (reg_equiv_mem[i])
1069 XEXP (reg_equiv_mem[i], 0) = addr;
1073 /* We've finished reloading. This reload_completed must be set before we
1074 perform instruction splitting below. */
1075 reload_completed = 1;
1077 /* Make a pass over all the insns and delete all USEs which we inserted
1078 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1079 notes. Delete all CLOBBER insns and simplify (subreg (reg)) operands. */
1081 for (insn = first; insn; insn = NEXT_INSN (insn))
1082 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1086 if ((GET_CODE (PATTERN (insn)) == USE
1087 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1088 || GET_CODE (PATTERN (insn)) == CLOBBER)
1090 PUT_CODE (insn, NOTE);
1091 NOTE_SOURCE_FILE (insn) = 0;
1092 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1096 pnote = ®_NOTES (insn);
1099 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1100 || REG_NOTE_KIND (*pnote) == REG_UNUSED)
1101 *pnote = XEXP (*pnote, 1);
1103 pnote = &XEXP (*pnote, 1);
1106 /* And simplify (subreg (reg)) if it appears as an operand. */
1107 cleanup_subreg_operands (insn);
1109 /* If optimizing and we are performing instruction scheduling after
1110 reload, then go ahead and split insns now since we are about to
1111 recompute flow information anyway. */
1112 if (optimize && flag_schedule_insns_after_reload)
1116 last = try_split (PATTERN (insn), insn, 1);
1120 PUT_CODE (insn, NOTE);
1121 NOTE_SOURCE_FILE (insn) = 0;
1122 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1128 /* If we are doing stack checking, give a warning if this function's
1129 frame size is larger than we expect. */
1130 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1132 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1134 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1135 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1136 size += UNITS_PER_WORD;
1138 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1139 warning ("frame size too large for reliable stack checking");
1142 /* Indicate that we no longer have known memory locations or constants. */
1143 if (reg_equiv_constant)
1144 free (reg_equiv_constant);
1145 reg_equiv_constant = 0;
1146 if (reg_equiv_memory_loc)
1147 free (reg_equiv_memory_loc);
1148 reg_equiv_memory_loc = 0;
1151 free (real_known_ptr);
1155 free (reg_equiv_mem);
1156 free (reg_equiv_init);
1157 free (reg_equiv_address);
1158 free (reg_max_ref_width);
1159 free (reg_old_renumber);
1160 free (pseudo_previous_regs);
1161 free (pseudo_forbidden_regs);
1163 FREE_REG_SET (spilled_pseudos);
1165 CLEAR_HARD_REG_SET (used_spill_regs);
1166 for (i = 0; i < n_spills; i++)
1167 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1169 /* Free all the insn_chain structures at once. */
1170 obstack_free (&reload_obstack, reload_startobj);
1171 unused_insn_chains = 0;
1176 /* Yet another special case. Unfortunately, reg-stack forces people to
1177 write incorrect clobbers in asm statements. These clobbers must not
1178 cause the register to appear in bad_spill_regs, otherwise we'll call
1179 fatal_insn later. We clear the corresponding regnos in the live
1180 register sets to avoid this.
1181 The whole thing is rather sick, I'm afraid. */
1183 maybe_fix_stack_asms ()
1186 char *constraints[MAX_RECOG_OPERANDS];
1187 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1188 struct insn_chain *chain;
1190 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1193 HARD_REG_SET clobbered, allowed;
1196 if (GET_RTX_CLASS (GET_CODE (chain->insn)) != 'i'
1197 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1199 pat = PATTERN (chain->insn);
1200 if (GET_CODE (pat) != PARALLEL)
1203 CLEAR_HARD_REG_SET (clobbered);
1204 CLEAR_HARD_REG_SET (allowed);
1206 /* First, make a mask of all stack regs that are clobbered. */
1207 for (i = 0; i < XVECLEN (pat, 0); i++)
1209 rtx t = XVECEXP (pat, 0, i);
1210 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1211 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1214 /* Get the operand values and constraints out of the insn. */
1215 decode_asm_operands (pat, recog_operand, recog_operand_loc,
1216 constraints, operand_mode);
1218 /* For every operand, see what registers are allowed. */
1219 for (i = 0; i < noperands; i++)
1221 char *p = constraints[i];
1222 /* For every alternative, we compute the class of registers allowed
1223 for reloading in CLS, and merge its contents into the reg set
1225 int cls = (int) NO_REGS;
1231 if (c == '\0' || c == ',' || c == '#')
1233 /* End of one alternative - mark the regs in the current
1234 class, and reset the class. */
1235 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1240 } while (c != '\0' && c != ',');
1248 case '=': case '+': case '*': case '%': case '?': case '!':
1249 case '0': case '1': case '2': case '3': case '4': case 'm':
1250 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1251 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1252 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1254 #ifdef EXTRA_CONSTRAINT
1255 case 'Q': case 'R': case 'S': case 'T': case 'U':
1260 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1265 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1269 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1274 /* Those of the registers which are clobbered, but allowed by the
1275 constraints, must be usable as reload registers. So clear them
1276 out of the life information. */
1277 AND_HARD_REG_SET (allowed, clobbered);
1278 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1279 if (TEST_HARD_REG_BIT (allowed, i))
1281 CLEAR_REGNO_REG_SET (chain->live_before, i);
1282 CLEAR_REGNO_REG_SET (chain->live_after, i);
1290 /* Walk the chain of insns, and determine for each whether it needs reloads
1291 and/or eliminations. Build the corresponding insns_need_reload list, and
1292 set something_needs_elimination as appropriate. */
1294 calculate_needs_all_insns (global)
1297 struct insn_chain **pprev_reload = &insns_need_reload;
1298 struct insn_chain **pchain;
1300 something_needs_elimination = 0;
1302 for (pchain = &reload_insn_chain; *pchain != 0; pchain = &(*pchain)->next)
1305 struct insn_chain *chain;
1310 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1311 include REG_LABEL), we need to see what effects this has on the
1312 known offsets at labels. */
1314 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1315 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1316 && REG_NOTES (insn) != 0))
1317 set_label_offsets (insn, insn, 0);
1319 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1321 rtx old_body = PATTERN (insn);
1322 int old_code = INSN_CODE (insn);
1323 rtx old_notes = REG_NOTES (insn);
1324 int did_elimination = 0;
1325 int operands_changed = 0;
1327 /* If needed, eliminate any eliminable registers. */
1329 did_elimination = eliminate_regs_in_insn (insn, 0);
1331 /* Analyze the instruction. */
1332 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1333 global, spill_reg_order);
1335 /* If a no-op set needs more than one reload, this is likely
1336 to be something that needs input address reloads. We
1337 can't get rid of this cleanly later, and it is of no use
1338 anyway, so discard it now.
1339 We only do this when expensive_optimizations is enabled,
1340 since this complements reload inheritance / output
1341 reload deletion, and it can make debugging harder. */
1342 if (flag_expensive_optimizations && n_reloads > 1)
1344 rtx set = single_set (insn);
1346 && SET_SRC (set) == SET_DEST (set)
1347 && GET_CODE (SET_SRC (set)) == REG
1348 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1350 PUT_CODE (insn, NOTE);
1351 NOTE_SOURCE_FILE (insn) = 0;
1352 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1357 update_eliminable_offsets ();
1359 /* Remember for later shortcuts which insns had any reloads or
1360 register eliminations. */
1361 chain->need_elim = did_elimination;
1362 chain->need_reload = n_reloads > 0;
1363 chain->need_operand_change = operands_changed;
1365 /* Discard any register replacements done. */
1366 if (did_elimination)
1368 obstack_free (&reload_obstack, reload_firstobj);
1369 PATTERN (insn) = old_body;
1370 INSN_CODE (insn) = old_code;
1371 REG_NOTES (insn) = old_notes;
1372 something_needs_elimination = 1;
1375 something_needs_operands_changed |= operands_changed;
1379 *pprev_reload = chain;
1380 pprev_reload = &chain->next_need_reload;
1382 calculate_needs (chain);
1389 /* Compute the most additional registers needed by one instruction,
1390 given by CHAIN. Collect information separately for each class of regs.
1392 To compute the number of reload registers of each class needed for an
1393 insn, we must simulate what choose_reload_regs can do. We do this by
1394 splitting an insn into an "input" and an "output" part. RELOAD_OTHER
1395 reloads are used in both. The input part uses those reloads,
1396 RELOAD_FOR_INPUT reloads, which must be live over the entire input section
1397 of reloads, and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
1398 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the inputs.
1400 The registers needed for output are RELOAD_OTHER and RELOAD_FOR_OUTPUT,
1401 which are live for the entire output portion, and the maximum of all the
1402 RELOAD_FOR_OUTPUT_ADDRESS reloads for each operand.
1404 The total number of registers needed is the maximum of the
1405 inputs and outputs. */
1408 calculate_needs (chain)
1409 struct insn_chain *chain;
1413 /* Each `struct needs' corresponds to one RELOAD_... type. */
1417 struct needs output;
1419 struct needs other_addr;
1420 struct needs op_addr;
1421 struct needs op_addr_reload;
1422 struct needs in_addr[MAX_RECOG_OPERANDS];
1423 struct needs in_addr_addr[MAX_RECOG_OPERANDS];
1424 struct needs out_addr[MAX_RECOG_OPERANDS];
1425 struct needs out_addr_addr[MAX_RECOG_OPERANDS];
1428 bzero ((char *) chain->group_size, sizeof chain->group_size);
1429 for (i = 0; i < N_REG_CLASSES; i++)
1430 chain->group_mode[i] = VOIDmode;
1431 bzero ((char *) &insn_needs, sizeof insn_needs);
1433 /* Count each reload once in every class
1434 containing the reload's own class. */
1436 for (i = 0; i < n_reloads; i++)
1438 register enum reg_class *p;
1439 enum reg_class class = reload_reg_class[i];
1441 enum machine_mode mode;
1442 struct needs *this_needs;
1444 /* Don't count the dummy reloads, for which one of the
1445 regs mentioned in the insn can be used for reloading.
1446 Don't count optional reloads.
1447 Don't count reloads that got combined with others. */
1448 if (reload_reg_rtx[i] != 0
1449 || reload_optional[i] != 0
1450 || (reload_out[i] == 0 && reload_in[i] == 0
1451 && ! reload_secondary_p[i]))
1454 mode = reload_inmode[i];
1455 if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1456 mode = reload_outmode[i];
1457 size = CLASS_MAX_NREGS (class, mode);
1459 /* Decide which time-of-use to count this reload for. */
1460 switch (reload_when_needed[i])
1463 this_needs = &insn_needs.other;
1465 case RELOAD_FOR_INPUT:
1466 this_needs = &insn_needs.input;
1468 case RELOAD_FOR_OUTPUT:
1469 this_needs = &insn_needs.output;
1471 case RELOAD_FOR_INSN:
1472 this_needs = &insn_needs.insn;
1474 case RELOAD_FOR_OTHER_ADDRESS:
1475 this_needs = &insn_needs.other_addr;
1477 case RELOAD_FOR_INPUT_ADDRESS:
1478 this_needs = &insn_needs.in_addr[reload_opnum[i]];
1480 case RELOAD_FOR_INPADDR_ADDRESS:
1481 this_needs = &insn_needs.in_addr_addr[reload_opnum[i]];
1483 case RELOAD_FOR_OUTPUT_ADDRESS:
1484 this_needs = &insn_needs.out_addr[reload_opnum[i]];
1486 case RELOAD_FOR_OUTADDR_ADDRESS:
1487 this_needs = &insn_needs.out_addr_addr[reload_opnum[i]];
1489 case RELOAD_FOR_OPERAND_ADDRESS:
1490 this_needs = &insn_needs.op_addr;
1492 case RELOAD_FOR_OPADDR_ADDR:
1493 this_needs = &insn_needs.op_addr_reload;
1499 enum machine_mode other_mode, allocate_mode;
1501 /* Count number of groups needed separately from
1502 number of individual regs needed. */
1503 this_needs->groups[(int) class]++;
1504 p = reg_class_superclasses[(int) class];
1505 while (*p != LIM_REG_CLASSES)
1506 this_needs->groups[(int) *p++]++;
1508 /* Record size and mode of a group of this class. */
1509 /* If more than one size group is needed,
1510 make all groups the largest needed size. */
1511 if (chain->group_size[(int) class] < size)
1513 other_mode = chain->group_mode[(int) class];
1514 allocate_mode = mode;
1516 chain->group_size[(int) class] = size;
1517 chain->group_mode[(int) class] = mode;
1522 allocate_mode = chain->group_mode[(int) class];
1525 /* Crash if two dissimilar machine modes both need
1526 groups of consecutive regs of the same class. */
1528 if (other_mode != VOIDmode && other_mode != allocate_mode
1529 && ! modes_equiv_for_class_p (allocate_mode,
1531 fatal_insn ("Two dissimilar machine modes both need groups of consecutive regs of the same class",
1536 this_needs->regs[(unsigned char)reload_nongroup[i]][(int) class] += 1;
1537 p = reg_class_superclasses[(int) class];
1538 while (*p != LIM_REG_CLASSES)
1539 this_needs->regs[(unsigned char)reload_nongroup[i]][(int) *p++] += 1;
1545 /* All reloads have been counted for this insn;
1546 now merge the various times of use.
1547 This sets insn_needs, etc., to the maximum total number
1548 of registers needed at any point in this insn. */
1550 for (i = 0; i < N_REG_CLASSES; i++)
1552 int j, in_max, out_max;
1554 /* Compute normal and nongroup needs. */
1555 for (j = 0; j <= 1; j++)
1558 for (in_max = 0, out_max = 0, k = 0; k < reload_n_operands; k++)
1560 in_max = MAX (in_max,
1561 (insn_needs.in_addr[k].regs[j][i]
1562 + insn_needs.in_addr_addr[k].regs[j][i]));
1563 out_max = MAX (out_max, insn_needs.out_addr[k].regs[j][i]);
1564 out_max = MAX (out_max,
1565 insn_needs.out_addr_addr[k].regs[j][i]);
1568 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1569 and operand addresses but not things used to reload
1570 them. Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads
1571 don't conflict with things needed to reload inputs or
1574 in_max = MAX (MAX (insn_needs.op_addr.regs[j][i],
1575 insn_needs.op_addr_reload.regs[j][i]),
1578 out_max = MAX (out_max, insn_needs.insn.regs[j][i]);
1580 insn_needs.input.regs[j][i]
1581 = MAX (insn_needs.input.regs[j][i]
1582 + insn_needs.op_addr.regs[j][i]
1583 + insn_needs.insn.regs[j][i],
1584 in_max + insn_needs.input.regs[j][i]);
1586 insn_needs.output.regs[j][i] += out_max;
1587 insn_needs.other.regs[j][i]
1588 += MAX (MAX (insn_needs.input.regs[j][i],
1589 insn_needs.output.regs[j][i]),
1590 insn_needs.other_addr.regs[j][i]);
1594 /* Now compute group needs. */
1595 for (in_max = 0, out_max = 0, j = 0; j < reload_n_operands; j++)
1597 in_max = MAX (in_max, insn_needs.in_addr[j].groups[i]);
1598 in_max = MAX (in_max, insn_needs.in_addr_addr[j].groups[i]);
1599 out_max = MAX (out_max, insn_needs.out_addr[j].groups[i]);
1600 out_max = MAX (out_max, insn_needs.out_addr_addr[j].groups[i]);
1603 in_max = MAX (MAX (insn_needs.op_addr.groups[i],
1604 insn_needs.op_addr_reload.groups[i]),
1606 out_max = MAX (out_max, insn_needs.insn.groups[i]);
1608 insn_needs.input.groups[i]
1609 = MAX (insn_needs.input.groups[i]
1610 + insn_needs.op_addr.groups[i]
1611 + insn_needs.insn.groups[i],
1612 in_max + insn_needs.input.groups[i]);
1614 insn_needs.output.groups[i] += out_max;
1615 insn_needs.other.groups[i]
1616 += MAX (MAX (insn_needs.input.groups[i],
1617 insn_needs.output.groups[i]),
1618 insn_needs.other_addr.groups[i]);
1621 /* Record the needs for later. */
1622 chain->need = insn_needs.other;
1625 /* Find a group of exactly 2 registers.
1627 First try to fill out the group by spilling a single register which
1628 would allow completion of the group.
1630 Then try to create a new group from a pair of registers, neither of
1631 which are explicitly used.
1633 Then try to create a group from any pair of registers. */
1636 find_tworeg_group (chain, class, dumpfile)
1637 struct insn_chain *chain;
1642 /* First, look for a register that will complete a group. */
1643 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1647 j = potential_reload_regs[i];
1648 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1649 && ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1650 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1651 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1652 && HARD_REGNO_MODE_OK (other, chain->group_mode[class])
1653 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, other)
1654 /* We don't want one part of another group.
1655 We could get "two groups" that overlap! */
1656 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, other))
1657 || (j < FIRST_PSEUDO_REGISTER - 1
1658 && (other = j + 1, spill_reg_order[other] >= 0)
1659 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1660 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1661 && HARD_REGNO_MODE_OK (j, chain->group_mode[class])
1662 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, other)
1663 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, other))))
1665 register enum reg_class *p;
1667 /* We have found one that will complete a group,
1668 so count off one group as provided. */
1669 chain->need.groups[class]--;
1670 p = reg_class_superclasses[class];
1671 while (*p != LIM_REG_CLASSES)
1673 if (chain->group_size [(int) *p] <= chain->group_size [class])
1674 chain->need.groups[(int) *p]--;
1678 /* Indicate both these regs are part of a group. */
1679 SET_HARD_REG_BIT (chain->counted_for_groups, j);
1680 SET_HARD_REG_BIT (chain->counted_for_groups, other);
1684 /* We can't complete a group, so start one. */
1685 if (i == FIRST_PSEUDO_REGISTER)
1686 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1689 j = potential_reload_regs[i];
1690 /* Verify that J+1 is a potential reload reg. */
1691 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1692 if (potential_reload_regs[k] == j + 1)
1694 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1695 && k < FIRST_PSEUDO_REGISTER
1696 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1697 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1698 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1699 && HARD_REGNO_MODE_OK (j, chain->group_mode[class])
1700 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, j + 1)
1701 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1))
1705 /* I should be the index in potential_reload_regs
1706 of the new reload reg we have found. */
1708 new_spill_reg (chain, i, class, 0, dumpfile);
1711 /* Find a group of more than 2 registers.
1712 Look for a sufficient sequence of unspilled registers, and spill them all
1716 find_group (chain, class, dumpfile)
1717 struct insn_chain *chain;
1723 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1725 int j = potential_reload_regs[i];
1728 && j + chain->group_size[class] <= FIRST_PSEUDO_REGISTER
1729 && HARD_REGNO_MODE_OK (j, chain->group_mode[class]))
1732 /* Check each reg in the sequence. */
1733 for (k = 0; k < chain->group_size[class]; k++)
1734 if (! (spill_reg_order[j + k] < 0
1735 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1736 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1738 /* We got a full sequence, so spill them all. */
1739 if (k == chain->group_size[class])
1741 register enum reg_class *p;
1742 for (k = 0; k < chain->group_size[class]; k++)
1745 SET_HARD_REG_BIT (chain->counted_for_groups, j + k);
1746 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1747 if (potential_reload_regs[idx] == j + k)
1749 new_spill_reg (chain, idx, class, 0, dumpfile);
1752 /* We have found one that will complete a group,
1753 so count off one group as provided. */
1754 chain->need.groups[class]--;
1755 p = reg_class_superclasses[class];
1756 while (*p != LIM_REG_CLASSES)
1758 if (chain->group_size [(int) *p]
1759 <= chain->group_size [class])
1760 chain->need.groups[(int) *p]--;
1767 /* There are no groups left. */
1768 spill_failure (chain->insn);
1772 /* If pseudo REG conflicts with one of our reload registers, mark it as
1775 maybe_mark_pseudo_spilled (reg)
1779 int r = reg_renumber[reg];
1784 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1785 for (i = 0; i < n_spills; i++)
1786 if (r <= spill_regs[i] && r + nregs > spill_regs[i])
1788 SET_REGNO_REG_SET (spilled_pseudos, reg);
1793 /* Find more reload regs to satisfy the remaining need of an insn, which
1795 Do it by ascending class number, since otherwise a reg
1796 might be spilled for a big class and might fail to count
1797 for a smaller class even though it belongs to that class.
1799 Count spilled regs in `spills', and add entries to
1800 `spill_regs' and `spill_reg_order'.
1802 ??? Note there is a problem here.
1803 When there is a need for a group in a high-numbered class,
1804 and also need for non-group regs that come from a lower class,
1805 the non-group regs are chosen first. If there aren't many regs,
1806 they might leave no room for a group.
1808 This was happening on the 386. To fix it, we added the code
1809 that calls possible_group_p, so that the lower class won't
1810 break up the last possible group.
1812 Really fixing the problem would require changes above
1813 in counting the regs already spilled, and in choose_reload_regs.
1814 It might be hard to avoid introducing bugs there. */
1817 find_reload_regs (chain, dumpfile)
1818 struct insn_chain *chain;
1822 short *group_needs = chain->need.groups;
1823 short *simple_needs = chain->need.regs[0];
1824 short *nongroup_needs = chain->need.regs[1];
1827 fprintf (dumpfile, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1829 /* Compute the order of preference for hard registers to spill.
1830 Store them by decreasing preference in potential_reload_regs. */
1832 order_regs_for_reload (chain);
1834 /* So far, no hard regs have been spilled. */
1836 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1837 spill_reg_order[i] = -1;
1839 CLEAR_HARD_REG_SET (chain->used_spill_regs);
1840 CLEAR_HARD_REG_SET (chain->counted_for_groups);
1841 CLEAR_HARD_REG_SET (chain->counted_for_nongroups);
1843 for (class = 0; class < N_REG_CLASSES; class++)
1845 /* First get the groups of registers.
1846 If we got single registers first, we might fragment
1848 while (group_needs[class] > 0)
1850 /* If any single spilled regs happen to form groups,
1851 count them now. Maybe we don't really need
1852 to spill another group. */
1853 count_possible_groups (chain, class);
1855 if (group_needs[class] <= 0)
1858 /* Groups of size 2, the only groups used on most machines,
1859 are treated specially. */
1860 if (chain->group_size[class] == 2)
1861 find_tworeg_group (chain, class, dumpfile);
1863 find_group (chain, class, dumpfile);
1868 /* Now similarly satisfy all need for single registers. */
1870 while (simple_needs[class] > 0 || nongroup_needs[class] > 0)
1872 /* If we spilled enough regs, but they weren't counted
1873 against the non-group need, see if we can count them now.
1874 If so, we can avoid some actual spilling. */
1875 if (simple_needs[class] <= 0 && nongroup_needs[class] > 0)
1876 for (i = 0; i < n_spills; i++)
1878 int regno = spill_regs[i];
1879 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1880 && !TEST_HARD_REG_BIT (chain->counted_for_groups, regno)
1881 && !TEST_HARD_REG_BIT (chain->counted_for_nongroups, regno)
1882 && nongroup_needs[class] > 0)
1884 register enum reg_class *p;
1886 SET_HARD_REG_BIT (chain->counted_for_nongroups, regno);
1887 nongroup_needs[class]--;
1888 p = reg_class_superclasses[class];
1889 while (*p != LIM_REG_CLASSES)
1890 nongroup_needs[(int) *p++]--;
1894 if (simple_needs[class] <= 0 && nongroup_needs[class] <= 0)
1897 /* Consider the potential reload regs that aren't
1898 yet in use as reload regs, in order of preference.
1899 Find the most preferred one that's in this class. */
1901 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1903 int regno = potential_reload_regs[i];
1905 && TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1906 /* If this reg will not be available for groups,
1907 pick one that does not foreclose possible groups.
1908 This is a kludge, and not very general,
1909 but it should be sufficient to make the 386 work,
1910 and the problem should not occur on machines with
1912 && (nongroup_needs[class] == 0
1913 || possible_group_p (chain, regno)))
1917 /* If we couldn't get a register, try to get one even if we
1918 might foreclose possible groups. This may cause problems
1919 later, but that's better than aborting now, since it is
1920 possible that we will, in fact, be able to form the needed
1921 group even with this allocation. */
1923 if (i >= FIRST_PSEUDO_REGISTER
1924 && asm_noperands (chain->insn) < 0)
1925 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1926 if (potential_reload_regs[i] >= 0
1927 && TEST_HARD_REG_BIT (reg_class_contents[class],
1928 potential_reload_regs[i]))
1931 /* I should be the index in potential_reload_regs
1932 of the new reload reg we have found. */
1934 new_spill_reg (chain, i, class, 1, dumpfile);
1940 /* We know which hard regs to use, now mark the pseudos that live in them
1941 as needing to be kicked out. */
1942 EXECUTE_IF_SET_IN_REG_SET
1943 (chain->live_before, FIRST_PSEUDO_REGISTER, i,
1945 maybe_mark_pseudo_spilled (i);
1947 EXECUTE_IF_SET_IN_REG_SET
1948 (chain->live_after, FIRST_PSEUDO_REGISTER, i,
1950 maybe_mark_pseudo_spilled (i);
1953 IOR_HARD_REG_SET (used_spill_regs, chain->used_spill_regs);
1957 dump_needs (chain, dumpfile)
1958 struct insn_chain *chain;
1961 static char *reg_class_names[] = REG_CLASS_NAMES;
1963 struct needs *n = &chain->need;
1965 for (i = 0; i < N_REG_CLASSES; i++)
1967 if (n->regs[i][0] > 0)
1969 ";; Need %d reg%s of class %s.\n",
1970 n->regs[i][0], n->regs[i][0] == 1 ? "" : "s",
1971 reg_class_names[i]);
1972 if (n->regs[i][1] > 0)
1974 ";; Need %d nongroup reg%s of class %s.\n",
1975 n->regs[i][1], n->regs[i][1] == 1 ? "" : "s",
1976 reg_class_names[i]);
1977 if (n->groups[i] > 0)
1979 ";; Need %d group%s (%smode) of class %s.\n",
1980 n->groups[i], n->groups[i] == 1 ? "" : "s",
1981 mode_name[(int) chain->group_mode[i]],
1982 reg_class_names[i]);
1986 /* Delete all insns that were inserted by emit_caller_save_insns during
1989 delete_caller_save_insns ()
1991 struct insn_chain *c = reload_insn_chain;
1995 while (c != 0 && c->is_caller_save_insn)
1997 struct insn_chain *next = c->next;
2000 if (insn == basic_block_head[c->block])
2001 basic_block_head[c->block] = NEXT_INSN (insn);
2002 if (insn == basic_block_end[c->block])
2003 basic_block_end[c->block] = PREV_INSN (insn);
2004 if (c == reload_insn_chain)
2005 reload_insn_chain = next;
2007 if (NEXT_INSN (insn) != 0)
2008 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2009 if (PREV_INSN (insn) != 0)
2010 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2013 next->prev = c->prev;
2015 c->prev->next = next;
2016 c->next = unused_insn_chains;
2017 unused_insn_chains = c;
2025 /* Nonzero if, after spilling reg REGNO for non-groups,
2026 it will still be possible to find a group if we still need one. */
2029 possible_group_p (chain, regno)
2030 struct insn_chain *chain;
2034 int class = (int) NO_REGS;
2036 for (i = 0; i < (int) N_REG_CLASSES; i++)
2037 if (chain->need.groups[i] > 0)
2043 if (class == (int) NO_REGS)
2046 /* Consider each pair of consecutive registers. */
2047 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
2049 /* Ignore pairs that include reg REGNO. */
2050 if (i == regno || i + 1 == regno)
2053 /* Ignore pairs that are outside the class that needs the group.
2054 ??? Here we fail to handle the case where two different classes
2055 independently need groups. But this never happens with our
2056 current machine descriptions. */
2057 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
2058 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
2061 /* A pair of consecutive regs we can still spill does the trick. */
2062 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
2063 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2064 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
2067 /* A pair of one already spilled and one we can spill does it
2068 provided the one already spilled is not otherwise reserved. */
2069 if (spill_reg_order[i] < 0
2070 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2071 && spill_reg_order[i + 1] >= 0
2072 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, i + 1)
2073 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, i + 1))
2075 if (spill_reg_order[i + 1] < 0
2076 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
2077 && spill_reg_order[i] >= 0
2078 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, i)
2079 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, i))
2086 /* Count any groups of CLASS that can be formed from the registers recently
2090 count_possible_groups (chain, class)
2091 struct insn_chain *chain;
2097 /* Now find all consecutive groups of spilled registers
2098 and mark each group off against the need for such groups.
2099 But don't count them against ordinary need, yet. */
2101 if (chain->group_size[class] == 0)
2104 CLEAR_HARD_REG_SET (new);
2106 /* Make a mask of all the regs that are spill regs in class I. */
2107 for (i = 0; i < n_spills; i++)
2109 int regno = spill_regs[i];
2111 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
2112 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, regno)
2113 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, regno))
2114 SET_HARD_REG_BIT (new, regno);
2117 /* Find each consecutive group of them. */
2118 for (i = 0; i < FIRST_PSEUDO_REGISTER && chain->need.groups[class] > 0; i++)
2119 if (TEST_HARD_REG_BIT (new, i)
2120 && i + chain->group_size[class] <= FIRST_PSEUDO_REGISTER
2121 && HARD_REGNO_MODE_OK (i, chain->group_mode[class]))
2123 for (j = 1; j < chain->group_size[class]; j++)
2124 if (! TEST_HARD_REG_BIT (new, i + j))
2127 if (j == chain->group_size[class])
2129 /* We found a group. Mark it off against this class's need for
2130 groups, and against each superclass too. */
2131 register enum reg_class *p;
2133 chain->need.groups[class]--;
2134 p = reg_class_superclasses[class];
2135 while (*p != LIM_REG_CLASSES)
2137 if (chain->group_size [(int) *p] <= chain->group_size [class])
2138 chain->need.groups[(int) *p]--;
2142 /* Don't count these registers again. */
2143 for (j = 0; j < chain->group_size[class]; j++)
2144 SET_HARD_REG_BIT (chain->counted_for_groups, i + j);
2147 /* Skip to the last reg in this group. When i is incremented above,
2148 it will then point to the first reg of the next possible group. */
2153 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2154 another mode that needs to be reloaded for the same register class CLASS.
2155 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2156 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2158 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2159 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2160 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2161 causes unnecessary failures on machines requiring alignment of register
2162 groups when the two modes are different sizes, because the larger mode has
2163 more strict alignment rules than the smaller mode. */
2166 modes_equiv_for_class_p (allocate_mode, other_mode, class)
2167 enum machine_mode allocate_mode, other_mode;
2168 enum reg_class class;
2171 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2173 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
2174 && HARD_REGNO_MODE_OK (regno, allocate_mode)
2175 && ! HARD_REGNO_MODE_OK (regno, other_mode))
2181 /* Handle the failure to find a register to spill.
2182 INSN should be one of the insns which needed this particular spill reg. */
2185 spill_failure (insn)
2188 if (asm_noperands (PATTERN (insn)) >= 0)
2189 error_for_asm (insn, "`asm' needs too many reloads");
2191 fatal_insn ("Unable to find a register to spill.", insn);
2194 /* Add a new register to the tables of available spill-registers.
2195 CHAIN is the insn for which the register will be used; we decrease the
2197 I is the index of this register in potential_reload_regs.
2198 CLASS is the regclass whose need is being satisfied.
2199 NONGROUP is 0 if this register is part of a group.
2200 DUMPFILE is the same as the one that `reload' got. */
2203 new_spill_reg (chain, i, class, nongroup, dumpfile)
2204 struct insn_chain *chain;
2210 register enum reg_class *p;
2211 int regno = potential_reload_regs[i];
2213 if (i >= FIRST_PSEUDO_REGISTER)
2215 spill_failure (chain->insn);
2220 if (TEST_HARD_REG_BIT (bad_spill_regs, regno))
2222 static char *reg_class_names[] = REG_CLASS_NAMES;
2224 if (asm_noperands (PATTERN (chain->insn)) < 0)
2226 /* The error message is still correct - we know only that it wasn't
2227 an asm statement that caused the problem, but one of the global
2228 registers declared by the users might have screwed us. */
2229 error ("fixed or forbidden register %d (%s) was spilled for class %s.",
2230 regno, reg_names[regno], reg_class_names[class]);
2231 error ("This may be due to a compiler bug or to impossible asm");
2232 error ("statements or clauses.");
2233 fatal_insn ("This is the instruction:", chain->insn);
2235 error_for_asm (chain->insn, "Invalid `asm' statement:");
2236 error_for_asm (chain->insn,
2237 "fixed or forbidden register %d (%s) was spilled for class %s.",
2238 regno, reg_names[regno], reg_class_names[class]);
2243 /* Make reg REGNO an additional reload reg. */
2245 potential_reload_regs[i] = -1;
2246 spill_regs[n_spills] = regno;
2247 spill_reg_order[regno] = n_spills;
2249 fprintf (dumpfile, "Spilling reg %d.\n", regno);
2250 SET_HARD_REG_BIT (chain->used_spill_regs, regno);
2252 /* Clear off the needs we just satisfied. */
2254 chain->need.regs[0][class]--;
2255 p = reg_class_superclasses[class];
2256 while (*p != LIM_REG_CLASSES)
2257 chain->need.regs[0][(int) *p++]--;
2259 if (nongroup && chain->need.regs[1][class] > 0)
2261 SET_HARD_REG_BIT (chain->counted_for_nongroups, regno);
2262 chain->need.regs[1][class]--;
2263 p = reg_class_superclasses[class];
2264 while (*p != LIM_REG_CLASSES)
2265 chain->need.regs[1][(int) *p++]--;
2271 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2272 data that is dead in INSN. */
2275 delete_dead_insn (insn)
2278 rtx prev = prev_real_insn (insn);
2281 /* If the previous insn sets a register that dies in our insn, delete it
2283 if (prev && GET_CODE (PATTERN (prev)) == SET
2284 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2285 && reg_mentioned_p (prev_dest, PATTERN (insn))
2286 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2287 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2288 delete_dead_insn (prev);
2290 PUT_CODE (insn, NOTE);
2291 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2292 NOTE_SOURCE_FILE (insn) = 0;
2295 /* Modify the home of pseudo-reg I.
2296 The new home is present in reg_renumber[I].
2298 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2299 or it may be -1, meaning there is none or it is not relevant.
2300 This is used so that all pseudos spilled from a given hard reg
2301 can share one stack slot. */
2304 alter_reg (i, from_reg)
2308 /* When outputting an inline function, this can happen
2309 for a reg that isn't actually used. */
2310 if (regno_reg_rtx[i] == 0)
2313 /* If the reg got changed to a MEM at rtl-generation time,
2315 if (GET_CODE (regno_reg_rtx[i]) != REG)
2318 /* Modify the reg-rtx to contain the new hard reg
2319 number or else to contain its pseudo reg number. */
2320 REGNO (regno_reg_rtx[i])
2321 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2323 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2324 allocate a stack slot for it. */
2326 if (reg_renumber[i] < 0
2327 && REG_N_REFS (i) > 0
2328 && reg_equiv_constant[i] == 0
2329 && reg_equiv_memory_loc[i] == 0)
2332 int inherent_size = PSEUDO_REGNO_BYTES (i);
2333 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2336 /* Each pseudo reg has an inherent size which comes from its own mode,
2337 and a total size which provides room for paradoxical subregs
2338 which refer to the pseudo reg in wider modes.
2340 We can use a slot already allocated if it provides both
2341 enough inherent space and enough total space.
2342 Otherwise, we allocate a new slot, making sure that it has no less
2343 inherent space, and no less total space, then the previous slot. */
2346 /* No known place to spill from => no slot to reuse. */
2347 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
2348 inherent_size == total_size ? 0 : -1);
2349 if (BYTES_BIG_ENDIAN)
2350 /* Cancel the big-endian correction done in assign_stack_local.
2351 Get the address of the beginning of the slot.
2352 This is so we can do a big-endian correction unconditionally
2354 adjust = inherent_size - total_size;
2356 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2358 /* Reuse a stack slot if possible. */
2359 else if (spill_stack_slot[from_reg] != 0
2360 && spill_stack_slot_width[from_reg] >= total_size
2361 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2363 x = spill_stack_slot[from_reg];
2364 /* Allocate a bigger slot. */
2367 /* Compute maximum size needed, both for inherent size
2368 and for total size. */
2369 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2371 if (spill_stack_slot[from_reg])
2373 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2375 mode = GET_MODE (spill_stack_slot[from_reg]);
2376 if (spill_stack_slot_width[from_reg] > total_size)
2377 total_size = spill_stack_slot_width[from_reg];
2379 /* Make a slot with that size. */
2380 x = assign_stack_local (mode, total_size,
2381 inherent_size == total_size ? 0 : -1);
2383 if (BYTES_BIG_ENDIAN)
2385 /* Cancel the big-endian correction done in assign_stack_local.
2386 Get the address of the beginning of the slot.
2387 This is so we can do a big-endian correction unconditionally
2389 adjust = GET_MODE_SIZE (mode) - total_size;
2391 stack_slot = gen_rtx_MEM (mode_for_size (total_size
2394 plus_constant (XEXP (x, 0), adjust));
2396 spill_stack_slot[from_reg] = stack_slot;
2397 spill_stack_slot_width[from_reg] = total_size;
2400 /* On a big endian machine, the "address" of the slot
2401 is the address of the low part that fits its inherent mode. */
2402 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2403 adjust += (total_size - inherent_size);
2405 /* If we have any adjustment to make, or if the stack slot is the
2406 wrong mode, make a new stack slot. */
2407 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2409 x = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
2410 plus_constant (XEXP (x, 0), adjust));
2412 /* If this was shared among registers, must ensure we never
2413 set it readonly since that can cause scheduling
2414 problems. Note we would only have in this adjustment
2415 case in any event, since the code above doesn't set it. */
2418 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2421 /* Save the stack slot for later. */
2422 reg_equiv_memory_loc[i] = x;
2426 /* Mark the slots in regs_ever_live for the hard regs
2427 used by pseudo-reg number REGNO. */
2430 mark_home_live (regno)
2433 register int i, lim;
2434 i = reg_renumber[regno];
2437 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2439 regs_ever_live[i++] = 1;
2442 /* This function handles the tracking of elimination offsets around branches.
2444 X is a piece of RTL being scanned.
2446 INSN is the insn that it came from, if any.
2448 INITIAL_P is non-zero if we are to set the offset to be the initial
2449 offset and zero if we are setting the offset of the label to be the
2453 set_label_offsets (x, insn, initial_p)
2458 enum rtx_code code = GET_CODE (x);
2461 struct elim_table *p;
2466 if (LABEL_REF_NONLOCAL_P (x))
2471 /* ... fall through ... */
2474 /* If we know nothing about this label, set the desired offsets. Note
2475 that this sets the offset at a label to be the offset before a label
2476 if we don't know anything about the label. This is not correct for
2477 the label after a BARRIER, but is the best guess we can make. If
2478 we guessed wrong, we will suppress an elimination that might have
2479 been possible had we been able to guess correctly. */
2481 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2483 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2484 offsets_at[CODE_LABEL_NUMBER (x)][i]
2485 = (initial_p ? reg_eliminate[i].initial_offset
2486 : reg_eliminate[i].offset);
2487 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2490 /* Otherwise, if this is the definition of a label and it is
2491 preceded by a BARRIER, set our offsets to the known offset of
2495 && (tem = prev_nonnote_insn (insn)) != 0
2496 && GET_CODE (tem) == BARRIER)
2497 set_offsets_for_label (insn);
2499 /* If neither of the above cases is true, compare each offset
2500 with those previously recorded and suppress any eliminations
2501 where the offsets disagree. */
2503 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2504 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2505 != (initial_p ? reg_eliminate[i].initial_offset
2506 : reg_eliminate[i].offset))
2507 reg_eliminate[i].can_eliminate = 0;
2512 set_label_offsets (PATTERN (insn), insn, initial_p);
2514 /* ... fall through ... */
2518 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2519 and hence must have all eliminations at their initial offsets. */
2520 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2521 if (REG_NOTE_KIND (tem) == REG_LABEL)
2522 set_label_offsets (XEXP (tem, 0), insn, 1);
2527 /* Each of the labels in the address vector must be at their initial
2528 offsets. We want the first field for ADDR_VEC and the second
2529 field for ADDR_DIFF_VEC. */
2531 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2532 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2537 /* We only care about setting PC. If the source is not RETURN,
2538 IF_THEN_ELSE, or a label, disable any eliminations not at
2539 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2540 isn't one of those possibilities. For branches to a label,
2541 call ourselves recursively.
2543 Note that this can disable elimination unnecessarily when we have
2544 a non-local goto since it will look like a non-constant jump to
2545 someplace in the current function. This isn't a significant
2546 problem since such jumps will normally be when all elimination
2547 pairs are back to their initial offsets. */
2549 if (SET_DEST (x) != pc_rtx)
2552 switch (GET_CODE (SET_SRC (x)))
2559 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2563 tem = XEXP (SET_SRC (x), 1);
2564 if (GET_CODE (tem) == LABEL_REF)
2565 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2566 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2569 tem = XEXP (SET_SRC (x), 2);
2570 if (GET_CODE (tem) == LABEL_REF)
2571 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2572 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2580 /* If we reach here, all eliminations must be at their initial
2581 offset because we are doing a jump to a variable address. */
2582 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2583 if (p->offset != p->initial_offset)
2584 p->can_eliminate = 0;
2592 /* Used for communication between the next two function to properly share
2593 the vector for an ASM_OPERANDS. */
2595 static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2597 /* Scan X and replace any eliminable registers (such as fp) with a
2598 replacement (such as sp), plus an offset.
2600 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2601 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2602 MEM, we are allowed to replace a sum of a register and the constant zero
2603 with the register, which we cannot do outside a MEM. In addition, we need
2604 to record the fact that a register is referenced outside a MEM.
2606 If INSN is an insn, it is the insn containing X. If we replace a REG
2607 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2608 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2609 the REG is being modified.
2611 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2612 That's used when we eliminate in expressions stored in notes.
2613 This means, do not set ref_outside_mem even if the reference
2616 If we see a modification to a register we know about, take the
2617 appropriate action (see case SET, below).
2619 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2620 replacements done assuming all offsets are at their initial values. If
2621 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2622 encounter, return the actual location so that find_reloads will do
2623 the proper thing. */
2626 eliminate_regs (x, mem_mode, insn)
2628 enum machine_mode mem_mode;
2631 enum rtx_code code = GET_CODE (x);
2632 struct elim_table *ep;
2655 /* This is only for the benefit of the debugging backends, which call
2656 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2657 removed after CSE. */
2658 new = eliminate_regs (XEXP (x, 0), 0, insn);
2659 if (GET_CODE (new) == MEM)
2660 return XEXP (new, 0);
2666 /* First handle the case where we encounter a bare register that
2667 is eliminable. Replace it with a PLUS. */
2668 if (regno < FIRST_PSEUDO_REGISTER)
2670 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2672 if (ep->from_rtx == x && ep->can_eliminate)
2675 /* Refs inside notes don't count for this purpose. */
2676 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2677 || GET_CODE (insn) == INSN_LIST)))
2678 ep->ref_outside_mem = 1;
2679 return plus_constant (ep->to_rtx, ep->previous_offset);
2686 /* If this is the sum of an eliminable register and a constant, rework
2688 if (GET_CODE (XEXP (x, 0)) == REG
2689 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2690 && CONSTANT_P (XEXP (x, 1)))
2692 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2694 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2697 /* Refs inside notes don't count for this purpose. */
2698 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2699 || GET_CODE (insn) == INSN_LIST)))
2700 ep->ref_outside_mem = 1;
2702 /* The only time we want to replace a PLUS with a REG (this
2703 occurs when the constant operand of the PLUS is the negative
2704 of the offset) is when we are inside a MEM. We won't want
2705 to do so at other times because that would change the
2706 structure of the insn in a way that reload can't handle.
2707 We special-case the commonest situation in
2708 eliminate_regs_in_insn, so just replace a PLUS with a
2709 PLUS here, unless inside a MEM. */
2710 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2711 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2714 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2715 plus_constant (XEXP (x, 1),
2716 ep->previous_offset));
2719 /* If the register is not eliminable, we are done since the other
2720 operand is a constant. */
2724 /* If this is part of an address, we want to bring any constant to the
2725 outermost PLUS. We will do this by doing register replacement in
2726 our operands and seeing if a constant shows up in one of them.
2728 We assume here this is part of an address (or a "load address" insn)
2729 since an eliminable register is not likely to appear in any other
2732 If we have (plus (eliminable) (reg)), we want to produce
2733 (plus (plus (replacement) (reg) (const))). If this was part of a
2734 normal add insn, (plus (replacement) (reg)) will be pushed as a
2735 reload. This is the desired action. */
2738 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2739 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2741 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2743 /* If one side is a PLUS and the other side is a pseudo that
2744 didn't get a hard register but has a reg_equiv_constant,
2745 we must replace the constant here since it may no longer
2746 be in the position of any operand. */
2747 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2748 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2749 && reg_renumber[REGNO (new1)] < 0
2750 && reg_equiv_constant != 0
2751 && reg_equiv_constant[REGNO (new1)] != 0)
2752 new1 = reg_equiv_constant[REGNO (new1)];
2753 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2754 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2755 && reg_renumber[REGNO (new0)] < 0
2756 && reg_equiv_constant[REGNO (new0)] != 0)
2757 new0 = reg_equiv_constant[REGNO (new0)];
2759 new = form_sum (new0, new1);
2761 /* As above, if we are not inside a MEM we do not want to
2762 turn a PLUS into something else. We might try to do so here
2763 for an addition of 0 if we aren't optimizing. */
2764 if (! mem_mode && GET_CODE (new) != PLUS)
2765 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2773 /* If this is the product of an eliminable register and a
2774 constant, apply the distribute law and move the constant out
2775 so that we have (plus (mult ..) ..). This is needed in order
2776 to keep load-address insns valid. This case is pathological.
2777 We ignore the possibility of overflow here. */
2778 if (GET_CODE (XEXP (x, 0)) == REG
2779 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2780 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2781 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2783 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2786 /* Refs inside notes don't count for this purpose. */
2787 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2788 || GET_CODE (insn) == INSN_LIST)))
2789 ep->ref_outside_mem = 1;
2792 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2793 ep->previous_offset * INTVAL (XEXP (x, 1)));
2796 /* ... fall through ... */
2801 case DIV: case UDIV:
2802 case MOD: case UMOD:
2803 case AND: case IOR: case XOR:
2804 case ROTATERT: case ROTATE:
2805 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2807 case GE: case GT: case GEU: case GTU:
2808 case LE: case LT: case LEU: case LTU:
2810 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2812 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2814 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2815 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2820 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2823 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2824 if (new != XEXP (x, 0))
2825 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2828 /* ... fall through ... */
2831 /* Now do eliminations in the rest of the chain. If this was
2832 an EXPR_LIST, this might result in allocating more memory than is
2833 strictly needed, but it simplifies the code. */
2836 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2837 if (new != XEXP (x, 1))
2838 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2846 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2847 if (ep->to_rtx == XEXP (x, 0))
2849 int size = GET_MODE_SIZE (mem_mode);
2851 /* If more bytes than MEM_MODE are pushed, account for them. */
2852 #ifdef PUSH_ROUNDING
2853 if (ep->to_rtx == stack_pointer_rtx)
2854 size = PUSH_ROUNDING (size);
2856 if (code == PRE_DEC || code == POST_DEC)
2862 /* Fall through to generic unary operation case. */
2863 case STRICT_LOW_PART:
2865 case SIGN_EXTEND: case ZERO_EXTEND:
2866 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2867 case FLOAT: case FIX:
2868 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2872 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2873 if (new != XEXP (x, 0))
2874 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2878 /* Similar to above processing, but preserve SUBREG_WORD.
2879 Convert (subreg (mem)) to (mem) if not paradoxical.
2880 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2881 pseudo didn't get a hard reg, we must replace this with the
2882 eliminated version of the memory location because push_reloads
2883 may do the replacement in certain circumstances. */
2884 if (GET_CODE (SUBREG_REG (x)) == REG
2885 && (GET_MODE_SIZE (GET_MODE (x))
2886 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2887 && reg_equiv_memory_loc != 0
2888 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2891 new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
2894 /* If we didn't change anything, we must retain the pseudo. */
2895 if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
2896 new = SUBREG_REG (x);
2899 /* In this case, we must show that the pseudo is used in this
2900 insn so that delete_output_reload will do the right thing. */
2901 if (insn != 0 && GET_CODE (insn) != EXPR_LIST
2902 && GET_CODE (insn) != INSN_LIST)
2903 REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode,
2906 = gen_rtx_EXPR_LIST (REG_EQUAL, new, NULL_RTX);
2908 /* Ensure NEW isn't shared in case we have to reload it. */
2909 new = copy_rtx (new);
2912 new = SUBREG_REG (x);
2916 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2918 if (new != XEXP (x, 0))
2920 int x_size = GET_MODE_SIZE (GET_MODE (x));
2921 int new_size = GET_MODE_SIZE (GET_MODE (new));
2923 if (GET_CODE (new) == MEM
2924 && ((x_size < new_size
2925 #ifdef WORD_REGISTER_OPERATIONS
2926 /* On these machines, combine can create rtl of the form
2927 (set (subreg:m1 (reg:m2 R) 0) ...)
2928 where m1 < m2, and expects something interesting to
2929 happen to the entire word. Moreover, it will use the
2930 (reg:m2 R) later, expecting all bits to be preserved.
2931 So if the number of words is the same, preserve the
2932 subreg so that push_reloads can see it. */
2933 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
2936 || (x_size == new_size))
2939 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2940 enum machine_mode mode = GET_MODE (x);
2942 if (BYTES_BIG_ENDIAN)
2943 offset += (MIN (UNITS_PER_WORD,
2944 GET_MODE_SIZE (GET_MODE (new)))
2945 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2947 PUT_MODE (new, mode);
2948 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2952 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
2958 /* If using a register that is the source of an eliminate we still
2959 think can be performed, note it cannot be performed since we don't
2960 know how this register is used. */
2961 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2962 if (ep->from_rtx == XEXP (x, 0))
2963 ep->can_eliminate = 0;
2965 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2966 if (new != XEXP (x, 0))
2967 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2971 /* If clobbering a register that is the replacement register for an
2972 elimination we still think can be performed, note that it cannot
2973 be performed. Otherwise, we need not be concerned about it. */
2974 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2975 if (ep->to_rtx == XEXP (x, 0))
2976 ep->can_eliminate = 0;
2978 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2979 if (new != XEXP (x, 0))
2980 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2986 /* Properly handle sharing input and constraint vectors. */
2987 if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
2989 /* When we come to a new vector not seen before,
2990 scan all its elements; keep the old vector if none
2991 of them changes; otherwise, make a copy. */
2992 old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
2993 temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
2994 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
2995 temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
2998 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
2999 if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
3002 if (i == ASM_OPERANDS_INPUT_LENGTH (x))
3003 new_asm_operands_vec = old_asm_operands_vec;
3005 new_asm_operands_vec
3006 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
3009 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
3010 if (new_asm_operands_vec == old_asm_operands_vec)
3013 new = gen_rtx_ASM_OPERANDS (VOIDmode, ASM_OPERANDS_TEMPLATE (x),
3014 ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
3015 ASM_OPERANDS_OUTPUT_IDX (x),
3016 new_asm_operands_vec,
3017 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
3018 ASM_OPERANDS_SOURCE_FILE (x),
3019 ASM_OPERANDS_SOURCE_LINE (x));
3020 new->volatil = x->volatil;
3025 /* Check for setting a register that we know about. */
3026 if (GET_CODE (SET_DEST (x)) == REG)
3028 /* See if this is setting the replacement register for an
3031 If DEST is the hard frame pointer, we do nothing because we
3032 assume that all assignments to the frame pointer are for
3033 non-local gotos and are being done at a time when they are valid
3034 and do not disturb anything else. Some machines want to
3035 eliminate a fake argument pointer (or even a fake frame pointer)
3036 with either the real frame or the stack pointer. Assignments to
3037 the hard frame pointer must not prevent this elimination. */
3039 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3041 if (ep->to_rtx == SET_DEST (x)
3042 && SET_DEST (x) != hard_frame_pointer_rtx)
3044 /* If it is being incremented, adjust the offset. Otherwise,
3045 this elimination can't be done. */
3046 rtx src = SET_SRC (x);
3048 if (GET_CODE (src) == PLUS
3049 && XEXP (src, 0) == SET_DEST (x)
3050 && GET_CODE (XEXP (src, 1)) == CONST_INT)
3051 ep->offset -= INTVAL (XEXP (src, 1));
3053 ep->can_eliminate = 0;
3056 /* Now check to see we are assigning to a register that can be
3057 eliminated. If so, it must be as part of a PARALLEL, since we
3058 will not have been called if this is a single SET. So indicate
3059 that we can no longer eliminate this reg. */
3060 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3062 if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
3063 ep->can_eliminate = 0;
3066 /* Now avoid the loop below in this common case. */
3068 rtx new0 = eliminate_regs (SET_DEST (x), 0, insn);
3069 rtx new1 = eliminate_regs (SET_SRC (x), 0, insn);
3071 /* If SET_DEST changed from a REG to a MEM and INSN is an insn,
3072 write a CLOBBER insn. */
3073 if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
3074 && insn != 0 && GET_CODE (insn) != EXPR_LIST
3075 && GET_CODE (insn) != INSN_LIST)
3076 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, SET_DEST (x)), insn);
3078 if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
3079 return gen_rtx_SET (VOIDmode, new0, new1);
3085 /* This is only for the benefit of the debugging backends, which call
3086 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
3087 removed after CSE. */
3088 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
3089 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
3091 /* Our only special processing is to pass the mode of the MEM to our
3092 recursive call and copy the flags. While we are here, handle this
3093 case more efficiently. */
3094 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
3095 if (new != XEXP (x, 0))
3097 new = gen_rtx_MEM (GET_MODE (x), new);
3098 new->volatil = x->volatil;
3099 new->unchanging = x->unchanging;
3100 new->in_struct = x->in_struct;
3110 /* Process each of our operands recursively. If any have changed, make a
3112 fmt = GET_RTX_FORMAT (code);
3113 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3117 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
3118 if (new != XEXP (x, i) && ! copied)
3120 rtx new_x = rtx_alloc (code);
3121 bcopy ((char *) x, (char *) new_x,
3122 (sizeof (*new_x) - sizeof (new_x->fld)
3123 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
3129 else if (*fmt == 'E')
3132 for (j = 0; j < XVECLEN (x, i); j++)
3134 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
3135 if (new != XVECEXP (x, i, j) && ! copied_vec)
3137 rtvec new_v = gen_rtvec_vv (XVECLEN (x, i),
3141 rtx new_x = rtx_alloc (code);
3142 bcopy ((char *) x, (char *) new_x,
3143 (sizeof (*new_x) - sizeof (new_x->fld)
3144 + (sizeof (new_x->fld[0])
3145 * GET_RTX_LENGTH (code))));
3149 XVEC (x, i) = new_v;
3152 XVECEXP (x, i, j) = new;
3160 /* Scan INSN and eliminate all eliminable registers in it.
3162 If REPLACE is nonzero, do the replacement destructively. Also
3163 delete the insn as dead it if it is setting an eliminable register.
3165 If REPLACE is zero, do all our allocations in reload_obstack.
3167 If no eliminations were done and this insn doesn't require any elimination
3168 processing (these are not identical conditions: it might be updating sp,
3169 but not referencing fp; this needs to be seen during reload_as_needed so
3170 that the offset between fp and sp can be taken into consideration), zero
3171 is returned. Otherwise, 1 is returned. */
3174 eliminate_regs_in_insn (insn, replace)
3178 rtx old_body = PATTERN (insn);
3179 rtx old_set = single_set (insn);
3182 struct elim_table *ep;
3185 push_obstacks (&reload_obstack, &reload_obstack);
3187 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
3188 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3190 /* Check for setting an eliminable register. */
3191 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3192 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3194 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3195 /* If this is setting the frame pointer register to the
3196 hardware frame pointer register and this is an elimination
3197 that will be done (tested above), this insn is really
3198 adjusting the frame pointer downward to compensate for
3199 the adjustment done before a nonlocal goto. */
3200 if (ep->from == FRAME_POINTER_REGNUM
3201 && ep->to == HARD_FRAME_POINTER_REGNUM)
3203 rtx src = SET_SRC (old_set);
3205 rtx prev_insn, prev_set;
3207 if (src == ep->to_rtx)
3209 else if (GET_CODE (src) == PLUS
3210 && GET_CODE (XEXP (src, 0)) == CONST_INT
3211 && XEXP (src, 1) == ep->to_rtx)
3212 offset = INTVAL (XEXP (src, 0)), ok = 1;
3213 else if (GET_CODE (src) == PLUS
3214 && GET_CODE (XEXP (src, 1)) == CONST_INT
3215 && XEXP (src, 0) == ep->to_rtx)
3216 offset = INTVAL (XEXP (src, 1)), ok = 1;
3217 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
3218 && (prev_set = single_set (prev_insn)) != 0
3219 && rtx_equal_p (SET_DEST (prev_set), src))
3221 src = SET_SRC (prev_set);
3222 if (src == ep->to_rtx)
3224 else if (GET_CODE (src) == PLUS
3225 && GET_CODE (XEXP (src, 0)) == CONST_INT
3226 && XEXP (src, 1) == ep->to_rtx)
3227 offset = INTVAL (XEXP (src, 0)), ok = 1;
3228 else if (GET_CODE (src) == PLUS
3229 && GET_CODE (XEXP (src, 1)) == CONST_INT
3230 && XEXP (src, 0) == ep->to_rtx)
3231 offset = INTVAL (XEXP (src, 1)), ok = 1;
3239 = plus_constant (ep->to_rtx, offset - ep->offset);
3241 /* First see if this insn remains valid when we
3242 make the change. If not, keep the INSN_CODE
3243 the same and let reload fit it up. */
3244 validate_change (insn, &SET_SRC (old_set), src, 1);
3245 validate_change (insn, &SET_DEST (old_set),
3247 if (! apply_change_group ())
3249 SET_SRC (old_set) = src;
3250 SET_DEST (old_set) = ep->to_rtx;
3260 /* In this case this insn isn't serving a useful purpose. We
3261 will delete it in reload_as_needed once we know that this
3262 elimination is, in fact, being done.
3264 If REPLACE isn't set, we can't delete this insn, but needn't
3265 process it since it won't be used unless something changes. */
3267 delete_dead_insn (insn);
3272 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3273 in the insn is the negative of the offset in FROM. Substitute
3274 (set (reg) (reg to)) for the insn and change its code.
3276 We have to do this here, rather than in eliminate_regs, so that we can
3277 change the insn code. */
3279 if (GET_CODE (SET_SRC (old_set)) == PLUS
3280 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3281 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT)
3282 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3284 if (ep->from_rtx == XEXP (SET_SRC (old_set), 0)
3285 && ep->can_eliminate)
3287 /* We must stop at the first elimination that will be used.
3288 If this one would replace the PLUS with a REG, do it
3289 now. Otherwise, quit the loop and let eliminate_regs
3290 do its normal replacement. */
3291 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_set), 1)))
3293 /* We assume here that we don't need a PARALLEL of
3294 any CLOBBERs for this assignment. There's not
3295 much we can do if we do need it. */
3296 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3299 INSN_CODE (insn) = -1;
3308 old_asm_operands_vec = 0;
3310 /* Replace the body of this insn with a substituted form. If we changed
3311 something, return non-zero.
3313 If we are replacing a body that was a (set X (plus Y Z)), try to
3314 re-recognize the insn. We do this in case we had a simple addition
3315 but now can do this as a load-address. This saves an insn in this
3318 new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX);
3319 if (new_body != old_body)
3321 /* If we aren't replacing things permanently and we changed something,
3322 make another copy to ensure that all the RTL is new. Otherwise
3323 things can go wrong if find_reload swaps commutative operands
3324 and one is inside RTL that has been copied while the other is not. */
3326 /* Don't copy an asm_operands because (1) there's no need and (2)
3327 copy_rtx can't do it properly when there are multiple outputs. */
3328 if (! replace && asm_noperands (old_body) < 0)
3329 new_body = copy_rtx (new_body);
3331 /* If we had a move insn but now we don't, rerecognize it. This will
3332 cause spurious re-recognition if the old move had a PARALLEL since
3333 the new one still will, but we can't call single_set without
3334 having put NEW_BODY into the insn and the re-recognition won't
3335 hurt in this rare case. */
3337 && ((GET_CODE (SET_SRC (old_set)) == REG
3338 && (GET_CODE (new_body) != SET
3339 || GET_CODE (SET_SRC (new_body)) != REG))
3340 /* If this was a load from or store to memory, compare
3341 the MEM in recog_operand to the one in the insn. If they
3342 are not equal, then rerecognize the insn. */
3344 && ((GET_CODE (SET_SRC (old_set)) == MEM
3345 && SET_SRC (old_set) != recog_operand[1])
3346 || (GET_CODE (SET_DEST (old_set)) == MEM
3347 && SET_DEST (old_set) != recog_operand[0])))
3348 /* If this was an add insn before, rerecognize. */
3349 || GET_CODE (SET_SRC (old_set)) == PLUS))
3351 if (! validate_change (insn, &PATTERN (insn), new_body, 0))
3352 /* If recognition fails, store the new body anyway.
3353 It's normal to have recognition failures here
3354 due to bizarre memory addresses; reloading will fix them. */
3355 PATTERN (insn) = new_body;
3358 PATTERN (insn) = new_body;
3363 /* Loop through all elimination pairs. See if any have changed.
3365 We also detect a cases where register elimination cannot be done,
3366 namely, if a register would be both changed and referenced outside a MEM
3367 in the resulting insn since such an insn is often undefined and, even if
3368 not, we cannot know what meaning will be given to it. Note that it is
3369 valid to have a register used in an address in an insn that changes it
3370 (presumably with a pre- or post-increment or decrement).
3372 If anything changes, return nonzero. */
3374 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3376 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3377 ep->can_eliminate = 0;
3379 ep->ref_outside_mem = 0;
3381 if (ep->previous_offset != ep->offset)
3386 /* If we changed something, perform elimination in REG_NOTES. This is
3387 needed even when REPLACE is zero because a REG_DEAD note might refer
3388 to a register that we eliminate and could cause a different number
3389 of spill registers to be needed in the final reload pass than in
3391 if (val && REG_NOTES (insn) != 0)
3392 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3400 /* Loop through all elimination pairs.
3401 Recalculate the number not at initial offset.
3403 Compute the maximum offset (minimum offset if the stack does not
3404 grow downward) for each elimination pair. */
3407 update_eliminable_offsets ()
3409 struct elim_table *ep;
3411 num_not_at_initial_offset = 0;
3412 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3414 ep->previous_offset = ep->offset;
3415 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3416 num_not_at_initial_offset++;
3420 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3421 replacement we currently believe is valid, mark it as not eliminable if X
3422 modifies DEST in any way other than by adding a constant integer to it.
3424 If DEST is the frame pointer, we do nothing because we assume that
3425 all assignments to the hard frame pointer are nonlocal gotos and are being
3426 done at a time when they are valid and do not disturb anything else.
3427 Some machines want to eliminate a fake argument pointer with either the
3428 frame or stack pointer. Assignments to the hard frame pointer must not
3429 prevent this elimination.
3431 Called via note_stores from reload before starting its passes to scan
3432 the insns of the function. */
3435 mark_not_eliminable (dest, x)
3439 register unsigned int i;
3441 /* A SUBREG of a hard register here is just changing its mode. We should
3442 not see a SUBREG of an eliminable hard register, but check just in
3444 if (GET_CODE (dest) == SUBREG)
3445 dest = SUBREG_REG (dest);
3447 if (dest == hard_frame_pointer_rtx)
3450 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3451 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3452 && (GET_CODE (x) != SET
3453 || GET_CODE (SET_SRC (x)) != PLUS
3454 || XEXP (SET_SRC (x), 0) != dest
3455 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3457 reg_eliminate[i].can_eliminate_previous
3458 = reg_eliminate[i].can_eliminate = 0;
3463 /* Verify that the initial elimination offsets did not change since the
3464 last call to set_initial_elim_offsets. This is used to catch cases
3465 where something illegal happened during reload_as_needed that could
3466 cause incorrect code to be generated if we did not check for it. */
3468 verify_initial_elim_offsets ()
3472 #ifdef ELIMINABLE_REGS
3473 struct elim_table *ep;
3475 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3477 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3478 if (t != ep->initial_offset)
3482 INITIAL_FRAME_POINTER_OFFSET (t);
3483 if (t != reg_eliminate[0].initial_offset)
3488 /* Reset all offsets on eliminable registers to their initial values. */
3490 set_initial_elim_offsets ()
3492 struct elim_table *ep = reg_eliminate;
3494 #ifdef ELIMINABLE_REGS
3495 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3497 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3498 ep->previous_offset = ep->offset = ep->initial_offset;
3501 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3502 ep->previous_offset = ep->offset = ep->initial_offset;
3505 num_not_at_initial_offset = 0;
3508 /* Initialize the known label offsets.
3509 Set a known offset for each forced label to be at the initial offset
3510 of each elimination. We do this because we assume that all
3511 computed jumps occur from a location where each elimination is
3512 at its initial offset.
3513 For all other labels, show that we don't know the offsets. */
3516 set_initial_label_offsets ()
3519 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
3521 for (x = forced_labels; x; x = XEXP (x, 1))
3523 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3526 /* Set all elimination offsets to the known values for the code label given
3529 set_offsets_for_label (insn)
3533 int label_nr = CODE_LABEL_NUMBER (insn);
3534 struct elim_table *ep;
3536 num_not_at_initial_offset = 0;
3537 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3539 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3540 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3541 num_not_at_initial_offset++;
3545 /* See if anything that happened changes which eliminations are valid.
3546 For example, on the Sparc, whether or not the frame pointer can
3547 be eliminated can depend on what registers have been used. We need
3548 not check some conditions again (such as flag_omit_frame_pointer)
3549 since they can't have changed. */
3552 update_eliminables (pset)
3555 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3556 int previous_frame_pointer_needed = frame_pointer_needed;
3558 struct elim_table *ep;
3560 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3561 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3562 #ifdef ELIMINABLE_REGS
3563 || ! CAN_ELIMINATE (ep->from, ep->to)
3566 ep->can_eliminate = 0;
3568 /* Look for the case where we have discovered that we can't replace
3569 register A with register B and that means that we will now be
3570 trying to replace register A with register C. This means we can
3571 no longer replace register C with register B and we need to disable
3572 such an elimination, if it exists. This occurs often with A == ap,
3573 B == sp, and C == fp. */
3575 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3577 struct elim_table *op;
3578 register int new_to = -1;
3580 if (! ep->can_eliminate && ep->can_eliminate_previous)
3582 /* Find the current elimination for ep->from, if there is a
3584 for (op = reg_eliminate;
3585 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3586 if (op->from == ep->from && op->can_eliminate)
3592 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3594 for (op = reg_eliminate;
3595 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3596 if (op->from == new_to && op->to == ep->to)
3597 op->can_eliminate = 0;
3601 /* See if any registers that we thought we could eliminate the previous
3602 time are no longer eliminable. If so, something has changed and we
3603 must spill the register. Also, recompute the number of eliminable
3604 registers and see if the frame pointer is needed; it is if there is
3605 no elimination of the frame pointer that we can perform. */
3607 frame_pointer_needed = 1;
3608 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3610 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3611 && ep->to != HARD_FRAME_POINTER_REGNUM)
3612 frame_pointer_needed = 0;
3614 if (! ep->can_eliminate && ep->can_eliminate_previous)
3616 ep->can_eliminate_previous = 0;
3617 SET_HARD_REG_BIT (*pset, ep->from);
3622 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3623 /* If we didn't need a frame pointer last time, but we do now, spill
3624 the hard frame pointer. */
3625 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3626 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3630 /* Initialize the table of registers to eliminate. */
3634 struct elim_table *ep;
3635 #ifdef ELIMINABLE_REGS
3636 struct elim_table_1 *ep1;
3641 reg_eliminate = (struct elim_table *)
3642 xmalloc(sizeof(struct elim_table) * NUM_ELIMINABLE_REGS);
3643 bzero ((PTR) reg_eliminate,
3644 sizeof(struct elim_table) * NUM_ELIMINABLE_REGS);
3647 /* Does this function require a frame pointer? */
3649 frame_pointer_needed = (! flag_omit_frame_pointer
3650 #ifdef EXIT_IGNORE_STACK
3651 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3652 and restore sp for alloca. So we can't eliminate
3653 the frame pointer in that case. At some point,
3654 we should improve this by emitting the
3655 sp-adjusting insns for this case. */
3656 || (current_function_calls_alloca
3657 && EXIT_IGNORE_STACK)
3659 || FRAME_POINTER_REQUIRED);
3663 #ifdef ELIMINABLE_REGS
3664 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3665 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3667 ep->from = ep1->from;
3669 ep->can_eliminate = ep->can_eliminate_previous
3670 = (CAN_ELIMINATE (ep->from, ep->to)
3671 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3674 reg_eliminate[0].from = reg_eliminate_1[0].from;
3675 reg_eliminate[0].to = reg_eliminate_1[0].to;
3676 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3677 = ! frame_pointer_needed;
3680 /* Count the number of eliminable registers and build the FROM and TO
3681 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3682 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3683 We depend on this. */
3684 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3686 num_eliminable += ep->can_eliminate;
3687 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3688 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3692 /* Kick all pseudos out of hard register REGNO.
3693 If DUMPFILE is nonzero, log actions taken on that file.
3695 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3696 because we found we can't eliminate some register. In the case, no pseudos
3697 are allowed to be in the register, even if they are only in a block that
3698 doesn't require spill registers, unlike the case when we are spilling this
3699 hard reg to produce another spill register.
3701 Return nonzero if any pseudos needed to be kicked out. */
3704 spill_hard_reg (regno, dumpfile, cant_eliminate)
3713 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3714 regs_ever_live[regno] = 1;
3717 /* Spill every pseudo reg that was allocated to this reg
3718 or to something that overlaps this reg. */
3720 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3721 if (reg_renumber[i] >= 0
3722 && reg_renumber[i] <= regno
3724 + HARD_REGNO_NREGS (reg_renumber[i],
3725 PSEUDO_REGNO_MODE (i))
3727 SET_REGNO_REG_SET (spilled_pseudos, i);
3730 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3731 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3733 ior_hard_reg_set (set1, set2)
3734 HARD_REG_SET *set1, *set2;
3736 IOR_HARD_REG_SET (*set1, *set2);
3739 /* After find_reload_regs has been run for all insn that need reloads,
3740 and/or spill_hard_regs was called, this function is used to actually
3741 spill pseudo registers and try to reallocate them. It also sets up the
3742 spill_regs array for use by choose_reload_regs. */
3745 finish_spills (global, dumpfile)
3749 struct insn_chain *chain;
3750 int something_changed = 0;
3753 /* Build the spill_regs array for the function. */
3754 /* If there are some registers still to eliminate and one of the spill regs
3755 wasn't ever used before, additional stack space may have to be
3756 allocated to store this register. Thus, we may have changed the offset
3757 between the stack and frame pointers, so mark that something has changed.
3759 One might think that we need only set VAL to 1 if this is a call-used
3760 register. However, the set of registers that must be saved by the
3761 prologue is not identical to the call-used set. For example, the
3762 register used by the call insn for the return PC is a call-used register,
3763 but must be saved by the prologue. */
3766 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3767 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3769 spill_reg_order[i] = n_spills;
3770 spill_regs[n_spills++] = i;
3771 if (num_eliminable && ! regs_ever_live[i])
3772 something_changed = 1;
3773 regs_ever_live[i] = 1;
3776 spill_reg_order[i] = -1;
3778 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3779 if (REGNO_REG_SET_P (spilled_pseudos, i))
3781 /* Record the current hard register the pseudo is allocated to in
3782 pseudo_previous_regs so we avoid reallocating it to the same
3783 hard reg in a later pass. */
3784 if (reg_renumber[i] < 0)
3786 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3787 /* Mark it as no longer having a hard register home. */
3788 reg_renumber[i] = -1;
3789 /* We will need to scan everything again. */
3790 something_changed = 1;
3793 /* Retry global register allocation if possible. */
3796 bzero ((char *) pseudo_forbidden_regs, max_regno * sizeof (HARD_REG_SET));
3797 /* For every insn that needs reloads, set the registers used as spill
3798 regs in pseudo_forbidden_regs for every pseudo live across the
3800 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3802 EXECUTE_IF_SET_IN_REG_SET
3803 (chain->live_before, FIRST_PSEUDO_REGISTER, i,
3805 ior_hard_reg_set (pseudo_forbidden_regs + i,
3806 &chain->used_spill_regs);
3808 EXECUTE_IF_SET_IN_REG_SET
3809 (chain->live_after, FIRST_PSEUDO_REGISTER, i,
3811 ior_hard_reg_set (pseudo_forbidden_regs + i,
3812 &chain->used_spill_regs);
3816 /* Retry allocating the spilled pseudos. For each reg, merge the
3817 various reg sets that indicate which hard regs can't be used,
3818 and call retry_global_alloc.
3819 We change spill_pseudos here to only contain pseudos that did not
3820 get a new hard register. */
3821 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3822 if (reg_old_renumber[i] != reg_renumber[i])
3824 HARD_REG_SET forbidden;
3825 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3826 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3827 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3828 retry_global_alloc (i, forbidden);
3829 if (reg_renumber[i] >= 0)
3830 CLEAR_REGNO_REG_SET (spilled_pseudos, i);
3834 /* Fix up the register information in the insn chain.
3835 This involves deleting those of the spilled pseudos which did not get
3836 a new hard register home from the live_{before,after} sets. */
3837 for (chain = reload_insn_chain; chain; chain = chain->next)
3839 HARD_REG_SET used_by_pseudos;
3840 HARD_REG_SET used_by_pseudos2;
3842 AND_COMPL_REG_SET (chain->live_before, spilled_pseudos);
3843 AND_COMPL_REG_SET (chain->live_after, spilled_pseudos);
3845 /* Mark any unallocated hard regs as available for spills. That
3846 makes inheritance work somewhat better. */
3847 if (chain->need_reload)
3849 REG_SET_TO_HARD_REG_SET (used_by_pseudos, chain->live_before);
3850 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, chain->live_after);
3851 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3853 /* Save the old value for the sanity test below. */
3854 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3856 compute_use_by_pseudos (&used_by_pseudos, chain->live_before);
3857 compute_use_by_pseudos (&used_by_pseudos, chain->live_after);
3858 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3859 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3861 /* Make sure we only enlarge the set. */
3862 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3868 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3869 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3871 int regno = reg_renumber[i];
3872 if (reg_old_renumber[i] == regno)
3875 alter_reg (i, reg_old_renumber[i]);
3876 reg_old_renumber[i] = regno;
3880 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3882 fprintf (dumpfile, " Register %d now in %d.\n\n",
3883 i, reg_renumber[i]);
3887 return something_changed;
3890 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3891 Also mark any hard registers used to store user variables as
3892 forbidden from being used for spill registers. */
3895 scan_paradoxical_subregs (x)
3900 register enum rtx_code code = GET_CODE (x);
3906 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3907 && REG_USERVAR_P (x))
3908 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3924 if (GET_CODE (SUBREG_REG (x)) == REG
3925 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3926 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3927 = GET_MODE_SIZE (GET_MODE (x));
3934 fmt = GET_RTX_FORMAT (code);
3935 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3938 scan_paradoxical_subregs (XEXP (x, i));
3939 else if (fmt[i] == 'E')
3942 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3943 scan_paradoxical_subregs (XVECEXP (x, i, j));
3949 hard_reg_use_compare (p1p, p2p)
3950 const GENERIC_PTR p1p;
3951 const GENERIC_PTR p2p;
3953 struct hard_reg_n_uses *p1 = (struct hard_reg_n_uses *)p1p;
3954 struct hard_reg_n_uses *p2 = (struct hard_reg_n_uses *)p2p;
3955 int bad1 = TEST_HARD_REG_BIT (bad_spill_regs, p1->regno);
3956 int bad2 = TEST_HARD_REG_BIT (bad_spill_regs, p2->regno);
3958 return p1->regno - p2->regno;
3963 if (p1->uses > p2->uses)
3965 if (p1->uses < p2->uses)
3967 /* If regs are equally good, sort by regno,
3968 so that the results of qsort leave nothing to chance. */
3969 return p1->regno - p2->regno;
3972 /* Used for communication between order_regs_for_reload and count_pseudo.
3973 Used to avoid counting one pseudo twice. */
3974 static regset pseudos_counted;
3976 /* Update the costs in N_USES, considering that pseudo REG is live. */
3978 count_pseudo (n_uses, reg)
3979 struct hard_reg_n_uses *n_uses;
3982 int r = reg_renumber[reg];
3985 if (REGNO_REG_SET_P (pseudos_counted, reg))
3987 SET_REGNO_REG_SET (pseudos_counted, reg);
3992 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
3994 n_uses[r++].uses += REG_N_REFS (reg);
3996 /* Choose the order to consider regs for use as reload registers
3997 based on how much trouble would be caused by spilling one.
3998 Store them in order of decreasing preference in potential_reload_regs. */
4001 order_regs_for_reload (chain)
4002 struct insn_chain *chain;
4006 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
4008 pseudos_counted = ALLOCA_REG_SET ();
4010 COPY_HARD_REG_SET (bad_spill_regs, bad_spill_regs_global);
4012 /* Count number of uses of each hard reg by pseudo regs allocated to it
4013 and then order them by decreasing use. */
4015 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4019 hard_reg_n_uses[i].regno = i;
4020 hard_reg_n_uses[i].uses = 0;
4022 /* Test the various reasons why we can't use a register for
4023 spilling in this insn. */
4025 || REGNO_REG_SET_P (chain->live_before, i)
4026 || REGNO_REG_SET_P (chain->live_after, i))
4028 SET_HARD_REG_BIT (bad_spill_regs, i);
4032 /* Now find out which pseudos are allocated to it, and update
4034 CLEAR_REG_SET (pseudos_counted);
4036 EXECUTE_IF_SET_IN_REG_SET
4037 (chain->live_before, FIRST_PSEUDO_REGISTER, j,
4039 count_pseudo (hard_reg_n_uses, j);
4041 EXECUTE_IF_SET_IN_REG_SET
4042 (chain->live_after, FIRST_PSEUDO_REGISTER, j,
4044 count_pseudo (hard_reg_n_uses, j);
4048 FREE_REG_SET (pseudos_counted);
4050 /* Prefer registers not so far used, for use in temporary loading.
4051 Among them, if REG_ALLOC_ORDER is defined, use that order.
4052 Otherwise, prefer registers not preserved by calls. */
4054 #ifdef REG_ALLOC_ORDER
4055 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4057 int regno = reg_alloc_order[i];
4059 if (hard_reg_n_uses[regno].uses == 0
4060 && ! TEST_HARD_REG_BIT (bad_spill_regs, regno))
4061 potential_reload_regs[o++] = regno;
4064 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4066 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i]
4067 && ! TEST_HARD_REG_BIT (bad_spill_regs, i))
4068 potential_reload_regs[o++] = i;
4070 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4072 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i]
4073 && ! TEST_HARD_REG_BIT (bad_spill_regs, i))
4074 potential_reload_regs[o++] = i;
4078 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
4079 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
4081 /* Now add the regs that are already used,
4082 preferring those used less often. The fixed and otherwise forbidden
4083 registers will be at the end of this list. */
4085 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4086 if (hard_reg_n_uses[i].uses != 0
4087 && ! TEST_HARD_REG_BIT (bad_spill_regs, hard_reg_n_uses[i].regno))
4088 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
4089 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4090 if (TEST_HARD_REG_BIT (bad_spill_regs, hard_reg_n_uses[i].regno))
4091 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
4094 /* Reload pseudo-registers into hard regs around each insn as needed.
4095 Additional register load insns are output before the insn that needs it
4096 and perhaps store insns after insns that modify the reloaded pseudo reg.
4098 reg_last_reload_reg and reg_reloaded_contents keep track of
4099 which registers are already available in reload registers.
4100 We update these for the reloads that we perform,
4101 as the insns are scanned. */
4104 reload_as_needed (live_known)
4107 struct insn_chain *chain;
4111 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
4112 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
4113 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
4114 bzero ((char *) reg_last_reload_reg, max_regno * sizeof (rtx));
4115 reg_has_output_reload = (char *) alloca (max_regno);
4116 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4118 set_initial_elim_offsets ();
4120 for (chain = reload_insn_chain; chain; chain = chain->next)
4123 rtx insn = chain->insn;
4124 rtx old_next = NEXT_INSN (insn);
4126 /* If we pass a label, copy the offsets from the label information
4127 into the current offsets of each elimination. */
4128 if (GET_CODE (insn) == CODE_LABEL)
4129 set_offsets_for_label (insn);
4131 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
4133 rtx oldpat = PATTERN (insn);
4135 /* If this is a USE and CLOBBER of a MEM, ensure that any
4136 references to eliminable registers have been removed. */
4138 if ((GET_CODE (PATTERN (insn)) == USE
4139 || GET_CODE (PATTERN (insn)) == CLOBBER)
4140 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
4141 XEXP (XEXP (PATTERN (insn), 0), 0)
4142 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4143 GET_MODE (XEXP (PATTERN (insn), 0)),
4146 /* If we need to do register elimination processing, do so.
4147 This might delete the insn, in which case we are done. */
4148 if (num_eliminable && chain->need_elim)
4150 eliminate_regs_in_insn (insn, 1);
4151 if (GET_CODE (insn) == NOTE)
4153 update_eliminable_offsets ();
4158 /* If need_elim is nonzero but need_reload is zero, one might think
4159 that we could simply set n_reloads to 0. However, find_reloads
4160 could have done some manipulation of the insn (such as swapping
4161 commutative operands), and these manipulations are lost during
4162 the first pass for every insn that needs register elimination.
4163 So the actions of find_reloads must be redone here. */
4165 if (! chain->need_elim && ! chain->need_reload
4166 && ! chain->need_operand_change)
4168 /* First find the pseudo regs that must be reloaded for this insn.
4169 This info is returned in the tables reload_... (see reload.h).
4170 Also modify the body of INSN by substituting RELOAD
4171 rtx's for those pseudo regs. */
4174 bzero (reg_has_output_reload, max_regno);
4175 CLEAR_HARD_REG_SET (reg_is_output_reload);
4177 find_reloads (insn, 1, spill_indirect_levels, live_known,
4181 if (num_eliminable && chain->need_elim)
4182 update_eliminable_offsets ();
4186 rtx next = NEXT_INSN (insn);
4189 prev = PREV_INSN (insn);
4191 /* Now compute which reload regs to reload them into. Perhaps
4192 reusing reload regs from previous insns, or else output
4193 load insns to reload them. Maybe output store insns too.
4194 Record the choices of reload reg in reload_reg_rtx. */
4195 choose_reload_regs (chain);
4197 /* Merge any reloads that we didn't combine for fear of
4198 increasing the number of spill registers needed but now
4199 discover can be safely merged. */
4200 if (SMALL_REGISTER_CLASSES)
4201 merge_assigned_reloads (insn);
4203 /* Generate the insns to reload operands into or out of
4204 their reload regs. */
4205 emit_reload_insns (chain);
4207 /* Substitute the chosen reload regs from reload_reg_rtx
4208 into the insn's body (or perhaps into the bodies of other
4209 load and store insn that we just made for reloading
4210 and that we moved the structure into). */
4213 /* If this was an ASM, make sure that all the reload insns
4214 we have generated are valid. If not, give an error
4217 if (asm_noperands (PATTERN (insn)) >= 0)
4218 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4219 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
4220 && (recog_memoized (p) < 0
4221 || (extract_insn (p), ! constrain_operands (1))))
4223 error_for_asm (insn,
4224 "`asm' operand requires impossible reload");
4226 NOTE_SOURCE_FILE (p) = 0;
4227 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
4230 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4231 is no longer validly lying around to save a future reload.
4232 Note that this does not detect pseudos that were reloaded
4233 for this insn in order to be stored in
4234 (obeying register constraints). That is correct; such reload
4235 registers ARE still valid. */
4236 note_stores (oldpat, forget_old_reloads_1);
4238 /* There may have been CLOBBER insns placed after INSN. So scan
4239 between INSN and NEXT and use them to forget old reloads. */
4240 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4241 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
4242 note_stores (PATTERN (x), forget_old_reloads_1);
4245 /* Likewise for regs altered by auto-increment in this insn.
4246 REG_INC notes have been changed by reloading:
4247 find_reloads_address_1 records substitutions for them,
4248 which have been performed by subst_reloads above. */
4249 for (i = n_reloads - 1; i >= 0; i--)
4251 rtx in_reg = reload_in_reg[i];
4254 enum rtx_code code = GET_CODE (in_reg);
4255 /* PRE_INC / PRE_DEC will have the reload register ending up
4256 with the same value as the stack slot, but that doesn't
4257 hold true for POST_INC / POST_DEC. Either we have to
4258 convert the memory access to a true POST_INC / POST_DEC,
4259 or we can't use the reload register for inheritance. */
4260 if ((code == POST_INC || code == POST_DEC)
4261 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4262 REGNO (reload_reg_rtx[i]))
4263 /* Make sure it is the inc/dec pseudo, and not
4264 some other (e.g. output operand) pseudo. */
4265 && (reg_reloaded_contents[REGNO (reload_reg_rtx[i])]
4266 == REGNO (XEXP (in_reg, 0))))
4269 rtx reload_reg = reload_reg_rtx[i];
4270 enum machine_mode mode = GET_MODE (reload_reg);
4274 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4276 /* We really want to ignore REG_INC notes here, so
4277 use PATTERN (p) as argument to reg_set_p . */
4278 if (reg_set_p (reload_reg, PATTERN (p)))
4280 n = count_occurrences (PATTERN (p), reload_reg);
4284 n = validate_replace_rtx (reload_reg,
4285 gen_rtx (code, mode,
4290 REG_NOTES (p) = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4293 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX);
4297 #if 0 /* ??? Is this code obsolete now? Need to check carefully. */
4298 /* Likewise for regs altered by auto-increment in this insn.
4299 But note that the reg-notes are not changed by reloading:
4300 they still contain the pseudo-regs, not the spill regs. */
4301 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4302 if (REG_NOTE_KIND (x) == REG_INC)
4304 /* See if this pseudo reg was reloaded in this insn.
4305 If so, its last-reload info is still valid
4306 because it is based on this insn's reload. */
4307 for (i = 0; i < n_reloads; i++)
4308 if (reload_out[i] == XEXP (x, 0))
4312 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX);
4317 /* A reload reg's contents are unknown after a label. */
4318 if (GET_CODE (insn) == CODE_LABEL)
4319 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4321 /* Don't assume a reload reg is still good after a call insn
4322 if it is a call-used reg. */
4323 else if (GET_CODE (insn) == CALL_INSN)
4324 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
4326 /* In case registers overlap, allow certain insns to invalidate
4327 particular hard registers. */
4329 #ifdef INSN_CLOBBERS_REGNO_P
4330 for (i = 0 ; i < FIRST_PSEUDO_REGISTER; i++)
4331 if (TEST_HARD_REG_BIT (reg_reloaded_valid, i)
4332 && INSN_CLOBBERS_REGNO_P (insn, i))
4333 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i);
4342 /* Discard all record of any value reloaded from X,
4343 or reloaded in X from someplace else;
4344 unless X is an output reload reg of the current insn.
4346 X may be a hard reg (the reload reg)
4347 or it may be a pseudo reg that was reloaded from. */
4350 forget_old_reloads_1 (x, ignored)
4352 rtx ignored ATTRIBUTE_UNUSED;
4358 /* note_stores does give us subregs of hard regs. */
4359 while (GET_CODE (x) == SUBREG)
4361 offset += SUBREG_WORD (x);
4365 if (GET_CODE (x) != REG)
4368 regno = REGNO (x) + offset;
4370 if (regno >= FIRST_PSEUDO_REGISTER)
4375 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4376 /* Storing into a spilled-reg invalidates its contents.
4377 This can happen if a block-local pseudo is allocated to that reg
4378 and it wasn't spilled because this block's total need is 0.
4379 Then some insn might have an optional reload and use this reg. */
4380 for (i = 0; i < nr; i++)
4381 /* But don't do this if the reg actually serves as an output
4382 reload reg in the current instruction. */
4384 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4385 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4388 /* Since value of X has changed,
4389 forget any value previously copied from it. */
4392 /* But don't forget a copy if this is the output reload
4393 that establishes the copy's validity. */
4394 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4395 reg_last_reload_reg[regno + nr] = 0;
4398 /* For each reload, the mode of the reload register. */
4399 static enum machine_mode reload_mode[MAX_RELOADS];
4401 /* For each reload, the largest number of registers it will require. */
4402 static int reload_nregs[MAX_RELOADS];
4404 /* Comparison function for qsort to decide which of two reloads
4405 should be handled first. *P1 and *P2 are the reload numbers. */
4408 reload_reg_class_lower (r1p, r2p)
4409 const GENERIC_PTR r1p;
4410 const GENERIC_PTR r2p;
4412 register int r1 = *(short *)r1p, r2 = *(short *)r2p;
4415 /* Consider required reloads before optional ones. */
4416 t = reload_optional[r1] - reload_optional[r2];
4420 /* Count all solitary classes before non-solitary ones. */
4421 t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
4422 - (reg_class_size[(int) reload_reg_class[r1]] == 1));
4426 /* Aside from solitaires, consider all multi-reg groups first. */
4427 t = reload_nregs[r2] - reload_nregs[r1];
4431 /* Consider reloads in order of increasing reg-class number. */
4432 t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
4436 /* If reloads are equally urgent, sort by reload number,
4437 so that the results of qsort leave nothing to chance. */
4441 /* The following HARD_REG_SETs indicate when each hard register is
4442 used for a reload of various parts of the current insn. */
4444 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4445 static HARD_REG_SET reload_reg_used;
4446 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4447 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4448 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4449 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4450 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4451 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4452 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4453 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4454 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4455 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4456 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4457 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4458 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4459 static HARD_REG_SET reload_reg_used_in_op_addr;
4460 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4461 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4462 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4463 static HARD_REG_SET reload_reg_used_in_insn;
4464 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4465 static HARD_REG_SET reload_reg_used_in_other_addr;
4467 /* If reg is in use as a reload reg for any sort of reload. */
4468 static HARD_REG_SET reload_reg_used_at_all;
4470 /* If reg is use as an inherited reload. We just mark the first register
4472 static HARD_REG_SET reload_reg_used_for_inherit;
4474 /* Records which hard regs are allocated to a pseudo during any point of the
4476 static HARD_REG_SET reg_used_by_pseudo;
4478 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4479 TYPE. MODE is used to indicate how many consecutive regs are
4483 mark_reload_reg_in_use (regno, opnum, type, mode)
4486 enum reload_type type;
4487 enum machine_mode mode;
4489 int nregs = HARD_REGNO_NREGS (regno, mode);
4492 for (i = regno; i < nregs + regno; i++)
4497 SET_HARD_REG_BIT (reload_reg_used, i);
4500 case RELOAD_FOR_INPUT_ADDRESS:
4501 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4504 case RELOAD_FOR_INPADDR_ADDRESS:
4505 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4508 case RELOAD_FOR_OUTPUT_ADDRESS:
4509 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4512 case RELOAD_FOR_OUTADDR_ADDRESS:
4513 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4516 case RELOAD_FOR_OPERAND_ADDRESS:
4517 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4520 case RELOAD_FOR_OPADDR_ADDR:
4521 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4524 case RELOAD_FOR_OTHER_ADDRESS:
4525 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4528 case RELOAD_FOR_INPUT:
4529 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4532 case RELOAD_FOR_OUTPUT:
4533 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4536 case RELOAD_FOR_INSN:
4537 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4541 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4545 /* Similarly, but show REGNO is no longer in use for a reload. */
4548 clear_reload_reg_in_use (regno, opnum, type, mode)
4551 enum reload_type type;
4552 enum machine_mode mode;
4554 int nregs = HARD_REGNO_NREGS (regno, mode);
4555 int start_regno, end_regno;
4557 /* A complication is that for some reload types, inheritance might
4558 allow multiple reloads of the same types to share a reload register.
4559 We set check_opnum if we have to check only reloads with the same
4560 operand number, and check_any if we have to check all reloads. */
4561 int check_opnum = 0;
4563 HARD_REG_SET *used_in_set;
4568 used_in_set = &reload_reg_used;
4571 case RELOAD_FOR_INPUT_ADDRESS:
4572 used_in_set = &reload_reg_used_in_input_addr[opnum];
4575 case RELOAD_FOR_INPADDR_ADDRESS:
4577 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4580 case RELOAD_FOR_OUTPUT_ADDRESS:
4581 used_in_set = &reload_reg_used_in_output_addr[opnum];
4584 case RELOAD_FOR_OUTADDR_ADDRESS:
4586 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4589 case RELOAD_FOR_OPERAND_ADDRESS:
4590 used_in_set = &reload_reg_used_in_op_addr;
4593 case RELOAD_FOR_OPADDR_ADDR:
4595 used_in_set = &reload_reg_used_in_op_addr_reload;
4598 case RELOAD_FOR_OTHER_ADDRESS:
4599 used_in_set = &reload_reg_used_in_other_addr;
4603 case RELOAD_FOR_INPUT:
4604 used_in_set = &reload_reg_used_in_input[opnum];
4607 case RELOAD_FOR_OUTPUT:
4608 used_in_set = &reload_reg_used_in_output[opnum];
4611 case RELOAD_FOR_INSN:
4612 used_in_set = &reload_reg_used_in_insn;
4617 /* We resolve conflicts with remaining reloads of the same type by
4618 excluding the intervals of of reload registers by them from the
4619 interval of freed reload registers. Since we only keep track of
4620 one set of interval bounds, we might have to exclude somewhat
4621 more then what would be necessary if we used a HARD_REG_SET here.
4622 But this should only happen very infrequently, so there should
4623 be no reason to worry about it. */
4625 start_regno = regno;
4626 end_regno = regno + nregs;
4627 if (check_opnum || check_any)
4629 for (i = n_reloads - 1; i >= 0; i--)
4631 if (reload_when_needed[i] == type
4632 && (check_any || reload_opnum[i] == opnum)
4633 && reload_reg_rtx[i])
4635 int conflict_start = true_regnum (reload_reg_rtx[i]);
4638 + HARD_REGNO_NREGS (conflict_start, reload_mode[i]));
4640 /* If there is an overlap with the first to-be-freed register,
4641 adjust the interval start. */
4642 if (conflict_start <= start_regno && conflict_end > start_regno)
4643 start_regno = conflict_end;
4644 /* Otherwise, if there is a conflict with one of the other
4645 to-be-freed registers, adjust the interval end. */
4646 if (conflict_start > start_regno && conflict_start < end_regno)
4647 end_regno = conflict_start;
4651 for (i = start_regno; i < end_regno; i++)
4652 CLEAR_HARD_REG_BIT (*used_in_set, i);
4655 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4656 specified by OPNUM and TYPE. */
4659 reload_reg_free_p (regno, opnum, type)
4662 enum reload_type type;
4666 /* In use for a RELOAD_OTHER means it's not available for anything. */
4667 if (TEST_HARD_REG_BIT (reload_reg_used, regno))
4673 /* In use for anything means we can't use it for RELOAD_OTHER. */
4674 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4675 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4676 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4679 for (i = 0; i < reload_n_operands; i++)
4680 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4681 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4682 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4683 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4684 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4685 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4690 case RELOAD_FOR_INPUT:
4691 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4692 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4695 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4698 /* If it is used for some other input, can't use it. */
4699 for (i = 0; i < reload_n_operands; i++)
4700 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4703 /* If it is used in a later operand's address, can't use it. */
4704 for (i = opnum + 1; i < reload_n_operands; i++)
4705 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4706 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4711 case RELOAD_FOR_INPUT_ADDRESS:
4712 /* Can't use a register if it is used for an input address for this
4713 operand or used as an input in an earlier one. */
4714 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4715 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4718 for (i = 0; i < opnum; i++)
4719 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4724 case RELOAD_FOR_INPADDR_ADDRESS:
4725 /* Can't use a register if it is used for an input address
4726 for this operand or used as an input in an earlier
4728 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4731 for (i = 0; i < opnum; i++)
4732 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4737 case RELOAD_FOR_OUTPUT_ADDRESS:
4738 /* Can't use a register if it is used for an output address for this
4739 operand or used as an output in this or a later operand. */
4740 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4743 for (i = opnum; i < reload_n_operands; i++)
4744 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4749 case RELOAD_FOR_OUTADDR_ADDRESS:
4750 /* Can't use a register if it is used for an output address
4751 for this operand or used as an output in this or a
4753 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4756 for (i = opnum; i < reload_n_operands; i++)
4757 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4762 case RELOAD_FOR_OPERAND_ADDRESS:
4763 for (i = 0; i < reload_n_operands; i++)
4764 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4767 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4768 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4770 case RELOAD_FOR_OPADDR_ADDR:
4771 for (i = 0; i < reload_n_operands; i++)
4772 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4775 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4777 case RELOAD_FOR_OUTPUT:
4778 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4779 outputs, or an operand address for this or an earlier output. */
4780 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4783 for (i = 0; i < reload_n_operands; i++)
4784 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4787 for (i = 0; i <= opnum; i++)
4788 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4789 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4794 case RELOAD_FOR_INSN:
4795 for (i = 0; i < reload_n_operands; i++)
4796 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4797 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4800 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4801 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4803 case RELOAD_FOR_OTHER_ADDRESS:
4804 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4809 /* Return 1 if the value in reload reg REGNO, as used by a reload
4810 needed for the part of the insn specified by OPNUM and TYPE,
4811 is not in use for a reload in any prior part of the insn.
4813 We can assume that the reload reg was already tested for availability
4814 at the time it is needed, and we should not check this again,
4815 in case the reg has already been marked in use.
4817 However, if EQUIV is set, we are checking the availability of a register
4818 holding an equivalence to the value to be loaded into the reload register,
4819 not the availability of the reload register itself.
4821 This is still less stringent than what reload_reg_free_p checks; for
4822 example, compare the checks for RELOAD_OTHER. */
4825 reload_reg_free_before_p (regno, opnum, type, equiv)
4828 enum reload_type type;
4833 /* The code to handle EQUIV below is wrong.
4835 If we wnat to know if a value in a particular reload register is available
4836 at a particular point in time during reloading, we must check *all*
4837 prior reloads to see if they clobber the value.
4839 Note this is significantly different from determining when a register is
4840 free for usage in a reload!
4842 This change is temporary. It will go away. */
4848 case RELOAD_FOR_OTHER_ADDRESS:
4849 /* These always come first. */
4850 if (equiv && TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno))
4855 if (equiv && TEST_HARD_REG_BIT (reload_reg_used, regno))
4857 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4859 /* If this use is for part of the insn,
4860 check the reg is not in use for any prior part. It is tempting
4861 to try to do this by falling through from objecs that occur
4862 later in the insn to ones that occur earlier, but that will not
4863 correctly take into account the fact that here we MUST ignore
4864 things that would prevent the register from being allocated in
4865 the first place, since we know that it was allocated. */
4867 case RELOAD_FOR_OUTPUT_ADDRESS:
4869 && TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4871 /* Earlier reloads include RELOAD_FOR_OUTADDR_ADDRESS reloads. */
4872 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4874 /* ... fall through ... */
4875 case RELOAD_FOR_OUTADDR_ADDRESS:
4877 && (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno)
4878 || TEST_HARD_REG_BIT (reload_reg_used, regno)))
4880 /* Earlier reloads are for earlier outputs or their addresses,
4881 any RELOAD_FOR_INSN reloads, any inputs or their addresses, or any
4882 RELOAD_FOR_OTHER_ADDRESS reloads (we know it can't conflict with
4884 for (i = 0; i < opnum; i++)
4885 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4886 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4889 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4892 for (i = 0; i < reload_n_operands; i++)
4893 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4894 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4895 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4896 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4899 return (! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4900 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4901 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4902 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4904 case RELOAD_FOR_OUTPUT:
4905 case RELOAD_FOR_INSN:
4906 /* There is no reason to call this function for output reloads, thus
4907 anything we'd put here wouldn't be tested. So just abort. */
4910 case RELOAD_FOR_OPERAND_ADDRESS:
4911 if (equiv && TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4914 /* Earlier reloads include RELOAD_FOR_OPADDR_ADDR reloads. */
4915 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4918 /* ... fall through ... */
4920 case RELOAD_FOR_OPADDR_ADDR:
4923 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4924 || TEST_HARD_REG_BIT (reload_reg_used, regno))
4926 for (i = 0; i < reload_n_operands; i++)
4927 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4930 /* These can't conflict with inputs, or each other, so all we have to
4931 test is input addresses and the addresses of OTHER items. */
4933 for (i = 0; i < reload_n_operands; i++)
4934 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4935 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4938 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4940 case RELOAD_FOR_INPUT:
4941 if (equiv && TEST_HARD_REG_BIT (reload_reg_used, regno))
4944 /* The only things earlier are the address for this and
4945 earlier inputs, other inputs (which we know we don't conflict
4946 with), and addresses of RELOAD_OTHER objects.
4947 We can ignore the conflict with addresses of this operand, since
4948 when we inherit this operand, its address reloads are discarded. */
4950 for (i = 0; i < opnum; i++)
4951 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4952 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4955 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4957 case RELOAD_FOR_INPUT_ADDRESS:
4958 /* Earlier reloads include RELOAD_FOR_INPADDR_ADDRESS reloads. */
4959 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4961 /* ... fall through ... */
4962 case RELOAD_FOR_INPADDR_ADDRESS:
4963 if (equiv && TEST_HARD_REG_BIT (reload_reg_used, regno))
4966 /* Similarly, all we have to check is for use in earlier inputs'
4968 for (i = 0; i < opnum; i++)
4969 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4970 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4973 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4978 /* Return 1 if the value in reload reg REGNO, as used by a reload
4979 needed for the part of the insn specified by OPNUM and TYPE,
4980 is still available in REGNO at the end of the insn.
4982 We can assume that the reload reg was already tested for availability
4983 at the time it is needed, and we should not check this again,
4984 in case the reg has already been marked in use. */
4987 reload_reg_reaches_end_p (regno, opnum, type)
4990 enum reload_type type;
4997 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4998 its value must reach the end. */
5001 /* If this use is for part of the insn,
5002 its value reaches if no subsequent part uses the same register.
5003 Just like the above function, don't try to do this with lots
5006 case RELOAD_FOR_OTHER_ADDRESS:
5007 /* Here we check for everything else, since these don't conflict
5008 with anything else and everything comes later. */
5010 for (i = 0; i < reload_n_operands; i++)
5011 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5012 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5013 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
5014 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5015 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5016 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5019 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5020 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5021 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5023 case RELOAD_FOR_INPUT_ADDRESS:
5024 case RELOAD_FOR_INPADDR_ADDRESS:
5025 /* Similar, except that we check only for this and subsequent inputs
5026 and the address of only subsequent inputs and we do not need
5027 to check for RELOAD_OTHER objects since they are known not to
5030 for (i = opnum; i < reload_n_operands; i++)
5031 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5034 for (i = opnum + 1; i < reload_n_operands; i++)
5035 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5036 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5039 for (i = 0; i < reload_n_operands; i++)
5040 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5041 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5042 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5045 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5048 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5049 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
5051 case RELOAD_FOR_INPUT:
5052 /* Similar to input address, except we start at the next operand for
5053 both input and input address and we do not check for
5054 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5057 for (i = opnum + 1; i < reload_n_operands; i++)
5058 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5059 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5060 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5063 /* ... fall through ... */
5065 case RELOAD_FOR_OPERAND_ADDRESS:
5066 /* Check outputs and their addresses. */
5068 for (i = 0; i < reload_n_operands; i++)
5069 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5070 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5071 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5076 case RELOAD_FOR_OPADDR_ADDR:
5077 for (i = 0; i < reload_n_operands; i++)
5078 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5079 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5080 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5083 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5084 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
5086 case RELOAD_FOR_INSN:
5087 /* These conflict with other outputs with RELOAD_OTHER. So
5088 we need only check for output addresses. */
5092 /* ... fall through ... */
5094 case RELOAD_FOR_OUTPUT:
5095 case RELOAD_FOR_OUTPUT_ADDRESS:
5096 case RELOAD_FOR_OUTADDR_ADDRESS:
5097 /* We already know these can't conflict with a later output. So the
5098 only thing to check are later output addresses. */
5099 for (i = opnum + 1; i < reload_n_operands; i++)
5100 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5101 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5110 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5113 This function uses the same algorithm as reload_reg_free_p above. */
5116 reloads_conflict (r1, r2)
5119 enum reload_type r1_type = reload_when_needed[r1];
5120 enum reload_type r2_type = reload_when_needed[r2];
5121 int r1_opnum = reload_opnum[r1];
5122 int r2_opnum = reload_opnum[r2];
5124 /* RELOAD_OTHER conflicts with everything. */
5125 if (r2_type == RELOAD_OTHER)
5128 /* Otherwise, check conflicts differently for each type. */
5132 case RELOAD_FOR_INPUT:
5133 return (r2_type == RELOAD_FOR_INSN
5134 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5135 || r2_type == RELOAD_FOR_OPADDR_ADDR
5136 || r2_type == RELOAD_FOR_INPUT
5137 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5138 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5139 && r2_opnum > r1_opnum));
5141 case RELOAD_FOR_INPUT_ADDRESS:
5142 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5143 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5145 case RELOAD_FOR_INPADDR_ADDRESS:
5146 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5147 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5149 case RELOAD_FOR_OUTPUT_ADDRESS:
5150 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5151 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
5153 case RELOAD_FOR_OUTADDR_ADDRESS:
5154 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5155 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
5157 case RELOAD_FOR_OPERAND_ADDRESS:
5158 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5159 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5161 case RELOAD_FOR_OPADDR_ADDR:
5162 return (r2_type == RELOAD_FOR_INPUT
5163 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5165 case RELOAD_FOR_OUTPUT:
5166 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5167 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5168 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5169 && r2_opnum >= r1_opnum));
5171 case RELOAD_FOR_INSN:
5172 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5173 || r2_type == RELOAD_FOR_INSN
5174 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5176 case RELOAD_FOR_OTHER_ADDRESS:
5177 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5187 /* Vector of reload-numbers showing the order in which the reloads should
5189 short reload_order[MAX_RELOADS];
5191 /* Indexed by reload number, 1 if incoming value
5192 inherited from previous insns. */
5193 char reload_inherited[MAX_RELOADS];
5195 /* For an inherited reload, this is the insn the reload was inherited from,
5196 if we know it. Otherwise, this is 0. */
5197 rtx reload_inheritance_insn[MAX_RELOADS];
5199 /* If non-zero, this is a place to get the value of the reload,
5200 rather than using reload_in. */
5201 rtx reload_override_in[MAX_RELOADS];
5203 /* For each reload, the hard register number of the register used,
5204 or -1 if we did not need a register for this reload. */
5205 int reload_spill_index[MAX_RELOADS];
5207 /* Return 1 if the value in reload reg REGNO, as used by a reload
5208 needed for the part of the insn specified by OPNUM and TYPE,
5209 may be used to load VALUE into it.
5211 Other read-only reloads with the same value do not conflict
5212 unless OUT is non-zero and these other reloads have to live while
5213 output reloads live.
5215 RELOADNUM is the number of the reload we want to load this value for;
5216 a reload does not conflict with itself.
5218 The caller has to make sure that there is no conflict with the return
5221 reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum)
5224 enum reload_type type;
5231 /* We use some pseudo 'time' value to check if the lifetimes of the
5232 new register use would overlap with the one of a previous reload
5233 that is not read-only or uses a different value.
5234 The 'time' used doesn't have to be linear in any shape or form, just
5236 Some reload types use different 'buckets' for each operand.
5237 So there are MAX_RECOG_OPERANDS different time values for each
5239 We compute TIME1 as the time when the register for the prospective
5240 new reload ceases to be live, and TIME2 for each existing
5241 reload as the time when that the reload register of that reload
5243 Where there is little to be gained by exact lifetime calculations,
5244 we just make conservative assumptions, i.e. a longer lifetime;
5245 this is done in the 'default:' cases. */
5248 case RELOAD_FOR_OTHER_ADDRESS:
5251 /* For each input, we might have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5252 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5253 respectively, to the time values for these, we get distinct time
5254 values. To get distinct time values for each operand, we have to
5255 multiply opnum by at least three. We round that up to four because
5256 multiply by four is often cheaper. */
5257 case RELOAD_FOR_INPADDR_ADDRESS:
5258 time1 = opnum * 4 + 1;
5260 case RELOAD_FOR_INPUT_ADDRESS:
5261 time1 = opnum * 4 + 2;
5263 case RELOAD_FOR_OPADDR_ADDR:
5264 /* opnum * 4 + 3 < opnum * 4 + 4
5265 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5266 time1 = MAX_RECOG_OPERANDS * 4;
5268 case RELOAD_FOR_INPUT:
5269 /* All RELOAD_FOR_INPUT reloads remain live till just before the
5270 instruction is executed. */
5271 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5273 case RELOAD_FOR_OPERAND_ADDRESS:
5274 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5276 time1 = MAX_RECOG_OPERANDS * 4 + 2;
5278 case RELOAD_FOR_OUTPUT_ADDRESS:
5279 time1 = MAX_RECOG_OPERANDS * 4 + 3 + opnum;
5282 time1 = MAX_RECOG_OPERANDS * 5 + 3;
5285 for (i = 0; i < n_reloads; i++)
5287 rtx reg = reload_reg_rtx[i];
5288 if (reg && GET_CODE (reg) == REG
5289 && ((unsigned) regno - true_regnum (reg)
5290 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
5294 && reload_when_needed[i] != RELOAD_FOR_INPUT
5295 && reload_when_needed[i] != RELOAD_FOR_INPUT_ADDRESS
5296 && reload_when_needed[i] != RELOAD_FOR_INPADDR_ADDRESS)
5298 if (! reload_in[i] || ! rtx_equal_p (reload_in[i], value)
5302 switch (reload_when_needed[i])
5304 case RELOAD_FOR_OTHER_ADDRESS:
5307 case RELOAD_FOR_INPADDR_ADDRESS:
5308 /* find_reloads makes sure that a
5309 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5310 by at most one - the first -
5311 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5312 address reload is inherited, the address address reload
5313 goes away, so we can ignore this conflict. */
5314 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1)
5316 time2 = reload_opnum[i] * 4 + 1;
5318 case RELOAD_FOR_INPUT_ADDRESS:
5319 time2 = reload_opnum[i] * 4 + 2;
5321 case RELOAD_FOR_INPUT:
5322 time2 = reload_opnum[i] * 4 + 3;
5324 case RELOAD_FOR_OPADDR_ADDR:
5325 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1)
5327 time2 = MAX_RECOG_OPERANDS * 4;
5329 case RELOAD_FOR_OPERAND_ADDRESS:
5330 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5332 case RELOAD_FOR_OUTPUT:
5333 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5334 instruction is executed. */
5335 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5337 case RELOAD_FOR_OUTADDR_ADDRESS:
5338 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1)
5341 /* The first RELOAD_FOR_OUTPUT_ADDRESS reload conflicts with the
5342 RELOAD_FOR_OUTPUT reloads, so assign it the same time value. */
5343 case RELOAD_FOR_OUTPUT_ADDRESS:
5344 time2 = MAX_RECOG_OPERANDS * 4 + 3 + reload_opnum[i];
5347 if (! reload_in[i] || rtx_equal_p (reload_in[i], value))
5349 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5363 /* Find a spill register to use as a reload register for reload R.
5364 LAST_RELOAD is non-zero if this is the last reload for the insn being
5367 Set reload_reg_rtx[R] to the register allocated.
5369 If NOERROR is nonzero, we return 1 if successful,
5370 or 0 if we couldn't find a spill reg and we didn't change anything. */
5373 allocate_reload_reg (chain, r, last_reload, noerror)
5374 struct insn_chain *chain;
5379 rtx insn = chain->insn;
5380 int i, pass, count, regno;
5383 /* If we put this reload ahead, thinking it is a group,
5384 then insist on finding a group. Otherwise we can grab a
5385 reg that some other reload needs.
5386 (That can happen when we have a 68000 DATA_OR_FP_REG
5387 which is a group of data regs or one fp reg.)
5388 We need not be so restrictive if there are no more reloads
5391 ??? Really it would be nicer to have smarter handling
5392 for that kind of reg class, where a problem like this is normal.
5393 Perhaps those classes should be avoided for reloading
5394 by use of more alternatives. */
5396 int force_group = reload_nregs[r] > 1 && ! last_reload;
5398 /* If we want a single register and haven't yet found one,
5399 take any reg in the right class and not in use.
5400 If we want a consecutive group, here is where we look for it.
5402 We use two passes so we can first look for reload regs to
5403 reuse, which are already in use for other reloads in this insn,
5404 and only then use additional registers.
5405 I think that maximizing reuse is needed to make sure we don't
5406 run out of reload regs. Suppose we have three reloads, and
5407 reloads A and B can share regs. These need two regs.
5408 Suppose A and B are given different regs.
5409 That leaves none for C. */
5410 for (pass = 0; pass < 2; pass++)
5412 /* I is the index in spill_regs.
5413 We advance it round-robin between insns to use all spill regs
5414 equally, so that inherited reloads have a chance
5415 of leapfrogging each other. Don't do this, however, when we have
5416 group needs and failure would be fatal; if we only have a relatively
5417 small number of spill registers, and more than one of them has
5418 group needs, then by starting in the middle, we may end up
5419 allocating the first one in such a way that we are not left with
5420 sufficient groups to handle the rest. */
5422 if (noerror || ! force_group)
5427 for (count = 0; count < n_spills; count++)
5429 int class = (int) reload_reg_class[r];
5435 regnum = spill_regs[i];
5437 if ((reload_reg_free_p (regnum, reload_opnum[r],
5438 reload_when_needed[r])
5440 /* We check reload_reg_used to make sure we
5441 don't clobber the return register. */
5442 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5443 && reload_reg_free_for_value_p (regnum,
5445 reload_when_needed[r],
5448 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5449 && HARD_REGNO_MODE_OK (regnum, reload_mode[r])
5450 /* Look first for regs to share, then for unshared. But
5451 don't share regs used for inherited reloads; they are
5452 the ones we want to preserve. */
5454 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5456 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5459 int nr = HARD_REGNO_NREGS (regnum, reload_mode[r]);
5460 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5461 (on 68000) got us two FP regs. If NR is 1,
5462 we would reject both of them. */
5464 nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
5465 /* If we need only one reg, we have already won. */
5468 /* But reject a single reg if we demand a group. */
5473 /* Otherwise check that as many consecutive regs as we need
5475 Also, don't use for a group registers that are
5476 needed for nongroups. */
5477 if (! TEST_HARD_REG_BIT (chain->counted_for_nongroups, regnum))
5480 regno = regnum + nr - 1;
5481 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5482 && spill_reg_order[regno] >= 0
5483 && reload_reg_free_p (regno, reload_opnum[r],
5484 reload_when_needed[r])
5485 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups,
5495 /* If we found something on pass 1, omit pass 2. */
5496 if (count < n_spills)
5500 /* We should have found a spill register by now. */
5501 if (count == n_spills)
5508 /* I is the index in SPILL_REG_RTX of the reload register we are to
5509 allocate. Get an rtx for it and find its register number. */
5511 new = spill_reg_rtx[i];
5513 if (new == 0 || GET_MODE (new) != reload_mode[r])
5514 spill_reg_rtx[i] = new
5515 = gen_rtx_REG (reload_mode[r], spill_regs[i]);
5517 regno = true_regnum (new);
5519 /* Detect when the reload reg can't hold the reload mode.
5520 This used to be one `if', but Sequent compiler can't handle that. */
5521 if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5523 enum machine_mode test_mode = VOIDmode;
5525 test_mode = GET_MODE (reload_in[r]);
5526 /* If reload_in[r] has VOIDmode, it means we will load it
5527 in whatever mode the reload reg has: to wit, reload_mode[r].
5528 We have already tested that for validity. */
5529 /* Aside from that, we need to test that the expressions
5530 to reload from or into have modes which are valid for this
5531 reload register. Otherwise the reload insns would be invalid. */
5532 if (! (reload_in[r] != 0 && test_mode != VOIDmode
5533 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5534 if (! (reload_out[r] != 0
5535 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
5537 /* The reg is OK. */
5540 /* Mark as in use for this insn the reload regs we use
5542 mark_reload_reg_in_use (spill_regs[i], reload_opnum[r],
5543 reload_when_needed[r], reload_mode[r]);
5545 reload_reg_rtx[r] = new;
5546 reload_spill_index[r] = spill_regs[i];
5551 /* The reg is not OK. */
5556 if (asm_noperands (PATTERN (insn)) < 0)
5557 /* It's the compiler's fault. */
5558 fatal_insn ("Could not find a spill register", insn);
5560 /* It's the user's fault; the operand's mode and constraint
5561 don't match. Disable this reload so we don't crash in final. */
5562 error_for_asm (insn,
5563 "`asm' operand constraint incompatible with operand size");
5566 reload_reg_rtx[r] = 0;
5567 reload_optional[r] = 1;
5568 reload_secondary_p[r] = 1;
5573 /* Assign hard reg targets for the pseudo-registers we must reload
5574 into hard regs for this insn.
5575 Also output the instructions to copy them in and out of the hard regs.
5577 For machines with register classes, we are responsible for
5578 finding a reload reg in the proper class. */
5581 choose_reload_regs (chain)
5582 struct insn_chain *chain;
5584 rtx insn = chain->insn;
5586 int max_group_size = 1;
5587 enum reg_class group_class = NO_REGS;
5591 rtx save_reload_reg_rtx[MAX_RELOADS];
5592 char save_reload_inherited[MAX_RELOADS];
5593 rtx save_reload_inheritance_insn[MAX_RELOADS];
5594 rtx save_reload_override_in[MAX_RELOADS];
5595 int save_reload_spill_index[MAX_RELOADS];
5596 HARD_REG_SET save_reload_reg_used;
5597 HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
5598 HARD_REG_SET save_reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
5599 HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
5600 HARD_REG_SET save_reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
5601 HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS];
5602 HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS];
5603 HARD_REG_SET save_reload_reg_used_in_op_addr;
5604 HARD_REG_SET save_reload_reg_used_in_op_addr_reload;
5605 HARD_REG_SET save_reload_reg_used_in_insn;
5606 HARD_REG_SET save_reload_reg_used_in_other_addr;
5607 HARD_REG_SET save_reload_reg_used_at_all;
5609 bzero (reload_inherited, MAX_RELOADS);
5610 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5611 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5613 CLEAR_HARD_REG_SET (reload_reg_used);
5614 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5615 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5616 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5617 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5618 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5620 CLEAR_HARD_REG_SET (reg_used_by_pseudo);
5621 compute_use_by_pseudos (®_used_by_pseudo, chain->live_before);
5622 compute_use_by_pseudos (®_used_by_pseudo, chain->live_after);
5624 for (i = 0; i < reload_n_operands; i++)
5626 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5627 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5628 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5629 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5630 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5631 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5634 IOR_COMPL_HARD_REG_SET (reload_reg_used, chain->used_spill_regs);
5636 #if 0 /* Not needed, now that we can always retry without inheritance. */
5637 /* See if we have more mandatory reloads than spill regs.
5638 If so, then we cannot risk optimizations that could prevent
5639 reloads from sharing one spill register.
5641 Since we will try finding a better register than reload_reg_rtx
5642 unless it is equal to reload_in or reload_out, count such reloads. */
5646 for (j = 0; j < n_reloads; j++)
5647 if (! reload_optional[j]
5648 && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
5649 && (reload_reg_rtx[j] == 0
5650 || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
5651 && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
5658 /* In order to be certain of getting the registers we need,
5659 we must sort the reloads into order of increasing register class.
5660 Then our grabbing of reload registers will parallel the process
5661 that provided the reload registers.
5663 Also note whether any of the reloads wants a consecutive group of regs.
5664 If so, record the maximum size of the group desired and what
5665 register class contains all the groups needed by this insn. */
5667 for (j = 0; j < n_reloads; j++)
5669 reload_order[j] = j;
5670 reload_spill_index[j] = -1;
5673 = (reload_inmode[j] == VOIDmode
5674 || (GET_MODE_SIZE (reload_outmode[j])
5675 > GET_MODE_SIZE (reload_inmode[j])))
5676 ? reload_outmode[j] : reload_inmode[j];
5678 reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
5680 if (reload_nregs[j] > 1)
5682 max_group_size = MAX (reload_nregs[j], max_group_size);
5683 group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
5686 /* If we have already decided to use a certain register,
5687 don't use it in another way. */
5688 if (reload_reg_rtx[j])
5689 mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j],
5690 reload_when_needed[j], reload_mode[j]);
5694 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5696 bcopy ((char *) reload_reg_rtx, (char *) save_reload_reg_rtx,
5697 sizeof reload_reg_rtx);
5698 bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
5699 bcopy ((char *) reload_inheritance_insn,
5700 (char *) save_reload_inheritance_insn,
5701 sizeof reload_inheritance_insn);
5702 bcopy ((char *) reload_override_in, (char *) save_reload_override_in,
5703 sizeof reload_override_in);
5704 bcopy ((char *) reload_spill_index, (char *) save_reload_spill_index,
5705 sizeof reload_spill_index);
5706 COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
5707 COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
5708 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
5709 reload_reg_used_in_op_addr);
5711 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr_reload,
5712 reload_reg_used_in_op_addr_reload);
5714 COPY_HARD_REG_SET (save_reload_reg_used_in_insn,
5715 reload_reg_used_in_insn);
5716 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr,
5717 reload_reg_used_in_other_addr);
5719 for (i = 0; i < reload_n_operands; i++)
5721 COPY_HARD_REG_SET (save_reload_reg_used_in_output[i],
5722 reload_reg_used_in_output[i]);
5723 COPY_HARD_REG_SET (save_reload_reg_used_in_input[i],
5724 reload_reg_used_in_input[i]);
5725 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i],
5726 reload_reg_used_in_input_addr[i]);
5727 COPY_HARD_REG_SET (save_reload_reg_used_in_inpaddr_addr[i],
5728 reload_reg_used_in_inpaddr_addr[i]);
5729 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i],
5730 reload_reg_used_in_output_addr[i]);
5731 COPY_HARD_REG_SET (save_reload_reg_used_in_outaddr_addr[i],
5732 reload_reg_used_in_outaddr_addr[i]);
5735 /* If -O, try first with inheritance, then turning it off.
5736 If not -O, don't do inheritance.
5737 Using inheritance when not optimizing leads to paradoxes
5738 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5739 because one side of the comparison might be inherited. */
5741 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5743 /* Process the reloads in order of preference just found.
5744 Beyond this point, subregs can be found in reload_reg_rtx.
5746 This used to look for an existing reloaded home for all
5747 of the reloads, and only then perform any new reloads.
5748 But that could lose if the reloads were done out of reg-class order
5749 because a later reload with a looser constraint might have an old
5750 home in a register needed by an earlier reload with a tighter constraint.
5752 To solve this, we make two passes over the reloads, in the order
5753 described above. In the first pass we try to inherit a reload
5754 from a previous insn. If there is a later reload that needs a
5755 class that is a proper subset of the class being processed, we must
5756 also allocate a spill register during the first pass.
5758 Then make a second pass over the reloads to allocate any reloads
5759 that haven't been given registers yet. */
5761 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5763 for (j = 0; j < n_reloads; j++)
5765 register int r = reload_order[j];
5767 /* Ignore reloads that got marked inoperative. */
5768 if (reload_out[r] == 0 && reload_in[r] == 0
5769 && ! reload_secondary_p[r])
5772 /* If find_reloads chose to use reload_in or reload_out as a reload
5773 register, we don't need to chose one. Otherwise, try even if it
5774 found one since we might save an insn if we find the value lying
5776 Try also when reload_in is a pseudo without a hard reg. */
5777 if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
5778 && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
5779 || (rtx_equal_p (reload_out[r], reload_reg_rtx[r])
5780 && GET_CODE (reload_in[r]) != MEM
5781 && true_regnum (reload_in[r]) < FIRST_PSEUDO_REGISTER)))
5784 #if 0 /* No longer needed for correct operation.
5785 It might give better code, or might not; worth an experiment? */
5786 /* If this is an optional reload, we can't inherit from earlier insns
5787 until we are sure that any non-optional reloads have been allocated.
5788 The following code takes advantage of the fact that optional reloads
5789 are at the end of reload_order. */
5790 if (reload_optional[r] != 0)
5791 for (i = 0; i < j; i++)
5792 if ((reload_out[reload_order[i]] != 0
5793 || reload_in[reload_order[i]] != 0
5794 || reload_secondary_p[reload_order[i]])
5795 && ! reload_optional[reload_order[i]]
5796 && reload_reg_rtx[reload_order[i]] == 0)
5797 allocate_reload_reg (chain, reload_order[i], 0, inheritance);
5800 /* First see if this pseudo is already available as reloaded
5801 for a previous insn. We cannot try to inherit for reloads
5802 that are smaller than the maximum number of registers needed
5803 for groups unless the register we would allocate cannot be used
5806 We could check here to see if this is a secondary reload for
5807 an object that is already in a register of the desired class.
5808 This would avoid the need for the secondary reload register.
5809 But this is complex because we can't easily determine what
5810 objects might want to be loaded via this reload. So let a
5811 register be allocated here. In `emit_reload_insns' we suppress
5812 one of the loads in the case described above. */
5817 register int regno = -1;
5818 enum machine_mode mode;
5820 if (reload_in[r] == 0)
5822 else if (GET_CODE (reload_in[r]) == REG)
5824 regno = REGNO (reload_in[r]);
5825 mode = GET_MODE (reload_in[r]);
5827 else if (GET_CODE (reload_in_reg[r]) == REG)
5829 regno = REGNO (reload_in_reg[r]);
5830 mode = GET_MODE (reload_in_reg[r]);
5832 else if (GET_CODE (reload_in_reg[r]) == SUBREG
5833 && GET_CODE (SUBREG_REG (reload_in_reg[r])) == REG)
5835 word = SUBREG_WORD (reload_in_reg[r]);
5836 regno = REGNO (SUBREG_REG (reload_in_reg[r]));
5837 if (regno < FIRST_PSEUDO_REGISTER)
5839 mode = GET_MODE (reload_in_reg[r]);
5842 else if ((GET_CODE (reload_in_reg[r]) == PRE_INC
5843 || GET_CODE (reload_in_reg[r]) == PRE_DEC
5844 || GET_CODE (reload_in_reg[r]) == POST_INC
5845 || GET_CODE (reload_in_reg[r]) == POST_DEC)
5846 && GET_CODE (XEXP (reload_in_reg[r], 0)) == REG)
5848 regno = REGNO (XEXP (reload_in_reg[r], 0));
5849 mode = GET_MODE (XEXP (reload_in_reg[r], 0));
5850 reload_out[r] = reload_in[r];
5854 /* This won't work, since REGNO can be a pseudo reg number.
5855 Also, it takes much more hair to keep track of all the things
5856 that can invalidate an inherited reload of part of a pseudoreg. */
5857 else if (GET_CODE (reload_in[r]) == SUBREG
5858 && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
5859 regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
5862 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5864 enum reg_class class = reload_reg_class[r], last_class;
5865 rtx last_reg = reg_last_reload_reg[regno];
5867 i = REGNO (last_reg) + word;
5868 last_class = REGNO_REG_CLASS (i);
5869 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5870 >= GET_MODE_SIZE (mode) + word * UNITS_PER_WORD)
5871 && reg_reloaded_contents[i] == regno
5872 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5873 && HARD_REGNO_MODE_OK (i, reload_mode[r])
5874 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5875 /* Even if we can't use this register as a reload
5876 register, we might use it for reload_override_in,
5877 if copying it to the desired class is cheap
5879 || ((REGISTER_MOVE_COST (last_class, class)
5880 < MEMORY_MOVE_COST (mode, class, 1))
5881 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5882 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5886 #ifdef SECONDARY_MEMORY_NEEDED
5887 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5892 && (reload_nregs[r] == max_group_size
5893 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5895 && ((reload_reg_free_p (i, reload_opnum[r],
5896 reload_when_needed[r])
5897 && reload_reg_free_before_p (i, reload_opnum[r],
5898 reload_when_needed[r],
5900 || reload_reg_free_for_value_p (i, reload_opnum[r],
5901 reload_when_needed[r],
5905 /* If a group is needed, verify that all the subsequent
5906 registers still have their values intact. */
5908 = HARD_REGNO_NREGS (i, reload_mode[r]);
5911 for (k = 1; k < nr; k++)
5912 if (reg_reloaded_contents[i + k] != regno
5913 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5920 last_reg = (GET_MODE (last_reg) == mode
5921 ? last_reg : gen_rtx_REG (mode, i));
5923 /* We found a register that contains the
5924 value we need. If this register is the
5925 same as an `earlyclobber' operand of the
5926 current insn, just mark it as a place to
5927 reload from since we can't use it as the
5928 reload register itself. */
5930 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5931 if (reg_overlap_mentioned_for_reload_p
5932 (reg_last_reload_reg[regno],
5933 reload_earlyclobbers[i1]))
5936 if (i1 != n_earlyclobbers
5937 /* Don't use it if we'd clobber a pseudo reg. */
5938 || (TEST_HARD_REG_BIT (reg_used_by_pseudo, i)
5940 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5941 /* Don't really use the inherited spill reg
5942 if we need it wider than we've got it. */
5943 || (GET_MODE_SIZE (reload_mode[r])
5944 > GET_MODE_SIZE (mode))
5945 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5948 /* If find_reloads chose reload_out as reload
5949 register, stay with it - that leaves the
5950 inherited register for subsequent reloads. */
5951 || (reload_out[r] && reload_reg_rtx[r]
5952 && rtx_equal_p (reload_out[r],
5953 reload_reg_rtx[r])))
5955 reload_override_in[r] = last_reg;
5956 reload_inheritance_insn[r]
5957 = reg_reloaded_insn[i];
5962 /* We can use this as a reload reg. */
5963 /* Mark the register as in use for this part of
5965 mark_reload_reg_in_use (i,
5967 reload_when_needed[r],
5969 reload_reg_rtx[r] = last_reg;
5970 reload_inherited[r] = 1;
5971 reload_inheritance_insn[r]
5972 = reg_reloaded_insn[i];
5973 reload_spill_index[r] = i;
5974 for (k = 0; k < nr; k++)
5975 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5983 /* Here's another way to see if the value is already lying around. */
5985 && reload_in[r] != 0
5986 && ! reload_inherited[r]
5987 && reload_out[r] == 0
5988 && (CONSTANT_P (reload_in[r])
5989 || GET_CODE (reload_in[r]) == PLUS
5990 || GET_CODE (reload_in[r]) == REG
5991 || GET_CODE (reload_in[r]) == MEM)
5992 && (reload_nregs[r] == max_group_size
5993 || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
5996 = find_equiv_reg (reload_in[r], insn, reload_reg_class[r],
5997 -1, NULL_PTR, 0, reload_mode[r]);
6002 if (GET_CODE (equiv) == REG)
6003 regno = REGNO (equiv);
6004 else if (GET_CODE (equiv) == SUBREG)
6006 /* This must be a SUBREG of a hard register.
6007 Make a new REG since this might be used in an
6008 address and not all machines support SUBREGs
6010 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
6011 equiv = gen_rtx_REG (reload_mode[r], regno);
6017 /* If we found a spill reg, reject it unless it is free
6018 and of the desired class. */
6020 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
6021 && ! reload_reg_free_for_value_p (regno, reload_opnum[r],
6022 reload_when_needed[r],
6025 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
6029 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
6032 /* We found a register that contains the value we need.
6033 If this register is the same as an `earlyclobber' operand
6034 of the current insn, just mark it as a place to reload from
6035 since we can't use it as the reload register itself. */
6038 for (i = 0; i < n_earlyclobbers; i++)
6039 if (reg_overlap_mentioned_for_reload_p (equiv,
6040 reload_earlyclobbers[i]))
6042 reload_override_in[r] = equiv;
6047 /* If the equiv register we have found is explicitly clobbered
6048 in the current insn, it depends on the reload type if we
6049 can use it, use it for reload_override_in, or not at all.
6050 In particular, we then can't use EQUIV for a
6051 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6053 if (equiv != 0 && regno_clobbered_p (regno, insn))
6055 switch (reload_when_needed[r])
6057 case RELOAD_FOR_OTHER_ADDRESS:
6058 case RELOAD_FOR_INPADDR_ADDRESS:
6059 case RELOAD_FOR_INPUT_ADDRESS:
6060 case RELOAD_FOR_OPADDR_ADDR:
6063 case RELOAD_FOR_INPUT:
6064 case RELOAD_FOR_OPERAND_ADDRESS:
6065 reload_override_in[r] = equiv;
6073 /* If we found an equivalent reg, say no code need be generated
6074 to load it, and use it as our reload reg. */
6075 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
6077 int nr = HARD_REGNO_NREGS (regno, reload_mode[r]);
6079 reload_reg_rtx[r] = equiv;
6080 reload_inherited[r] = 1;
6082 /* If reg_reloaded_valid is not set for this register,
6083 there might be a stale spill_reg_store lying around.
6084 We must clear it, since otherwise emit_reload_insns
6085 might delete the store. */
6086 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6087 spill_reg_store[regno] = NULL_RTX;
6088 /* If any of the hard registers in EQUIV are spill
6089 registers, mark them as in use for this insn. */
6090 for (k = 0; k < nr; k++)
6092 i = spill_reg_order[regno + k];
6095 mark_reload_reg_in_use (regno, reload_opnum[r],
6096 reload_when_needed[r],
6098 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6105 /* If we found a register to use already, or if this is an optional
6106 reload, we are done. */
6107 if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
6110 #if 0 /* No longer needed for correct operation. Might or might not
6111 give better code on the average. Want to experiment? */
6113 /* See if there is a later reload that has a class different from our
6114 class that intersects our class or that requires less register
6115 than our reload. If so, we must allocate a register to this
6116 reload now, since that reload might inherit a previous reload
6117 and take the only available register in our class. Don't do this
6118 for optional reloads since they will force all previous reloads
6119 to be allocated. Also don't do this for reloads that have been
6122 for (i = j + 1; i < n_reloads; i++)
6124 int s = reload_order[i];
6126 if ((reload_in[s] == 0 && reload_out[s] == 0
6127 && ! reload_secondary_p[s])
6128 || reload_optional[s])
6131 if ((reload_reg_class[s] != reload_reg_class[r]
6132 && reg_classes_intersect_p (reload_reg_class[r],
6133 reload_reg_class[s]))
6134 || reload_nregs[s] < reload_nregs[r])
6141 allocate_reload_reg (chain, r, j == n_reloads - 1, inheritance);
6145 /* Now allocate reload registers for anything non-optional that
6146 didn't get one yet. */
6147 for (j = 0; j < n_reloads; j++)
6149 register int r = reload_order[j];
6151 /* Ignore reloads that got marked inoperative. */
6152 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
6155 /* Skip reloads that already have a register allocated or are
6157 if (reload_reg_rtx[r] != 0 || reload_optional[r])
6160 if (! allocate_reload_reg (chain, r, j == n_reloads - 1, inheritance))
6164 /* If that loop got all the way, we have won. */
6168 /* Loop around and try without any inheritance. */
6169 /* First undo everything done by the failed attempt
6170 to allocate with inheritance. */
6171 bcopy ((char *) save_reload_reg_rtx, (char *) reload_reg_rtx,
6172 sizeof reload_reg_rtx);
6173 bcopy ((char *) save_reload_inherited, (char *) reload_inherited,
6174 sizeof reload_inherited);
6175 bcopy ((char *) save_reload_inheritance_insn,
6176 (char *) reload_inheritance_insn,
6177 sizeof reload_inheritance_insn);
6178 bcopy ((char *) save_reload_override_in, (char *) reload_override_in,
6179 sizeof reload_override_in);
6180 bcopy ((char *) save_reload_spill_index, (char *) reload_spill_index,
6181 sizeof reload_spill_index);
6182 COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
6183 COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
6184 COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
6185 save_reload_reg_used_in_op_addr);
6186 COPY_HARD_REG_SET (reload_reg_used_in_op_addr_reload,
6187 save_reload_reg_used_in_op_addr_reload);
6188 COPY_HARD_REG_SET (reload_reg_used_in_insn,
6189 save_reload_reg_used_in_insn);
6190 COPY_HARD_REG_SET (reload_reg_used_in_other_addr,
6191 save_reload_reg_used_in_other_addr);
6193 for (i = 0; i < reload_n_operands; i++)
6195 COPY_HARD_REG_SET (reload_reg_used_in_input[i],
6196 save_reload_reg_used_in_input[i]);
6197 COPY_HARD_REG_SET (reload_reg_used_in_output[i],
6198 save_reload_reg_used_in_output[i]);
6199 COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i],
6200 save_reload_reg_used_in_input_addr[i]);
6201 COPY_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i],
6202 save_reload_reg_used_in_inpaddr_addr[i]);
6203 COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i],
6204 save_reload_reg_used_in_output_addr[i]);
6205 COPY_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i],
6206 save_reload_reg_used_in_outaddr_addr[i]);
6210 /* If we thought we could inherit a reload, because it seemed that
6211 nothing else wanted the same reload register earlier in the insn,
6212 verify that assumption, now that all reloads have been assigned.
6213 Likewise for reloads where reload_override_in has been set. */
6215 /* If doing expensive optimizations, do one preliminary pass that doesn't
6216 cancel any inheritance, but removes reloads that have been needed only
6217 for reloads that we know can be inherited. */
6218 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6220 for (j = 0; j < n_reloads; j++)
6222 register int r = reload_order[j];
6224 if (reload_inherited[r] && reload_reg_rtx[r])
6225 check_reg = reload_reg_rtx[r];
6226 else if (reload_override_in[r]
6227 && (GET_CODE (reload_override_in[r]) == REG
6228 || GET_CODE (reload_override_in[r]) == SUBREG))
6229 check_reg = reload_override_in[r];
6232 if (! (reload_reg_free_before_p (true_regnum (check_reg),
6233 reload_opnum[r], reload_when_needed[r],
6234 ! reload_inherited[r])
6235 || reload_reg_free_for_value_p (true_regnum (check_reg),
6237 reload_when_needed[r],
6243 reload_inherited[r] = 0;
6244 reload_override_in[r] = 0;
6246 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6247 reload_override_in, then we do not need its related
6248 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6249 likewise for other reload types.
6250 We handle this by removing a reload when its only replacement
6251 is mentioned in reload_in of the reload we are going to inherit.
6252 A special case are auto_inc expressions; even if the input is
6253 inherited, we still need the address for the output. We can
6254 recognize them because they have RELOAD_OUT set but not
6256 If we suceeded removing some reload and we are doing a preliminary
6257 pass just to remove such reloads, make another pass, since the
6258 removal of one reload might allow us to inherit another one. */
6259 else if ((! reload_out[r] || reload_out_reg[r])
6260 && remove_address_replacements (reload_in[r]) && pass)
6265 /* Now that reload_override_in is known valid,
6266 actually override reload_in. */
6267 for (j = 0; j < n_reloads; j++)
6268 if (reload_override_in[j])
6269 reload_in[j] = reload_override_in[j];
6271 /* If this reload won't be done because it has been cancelled or is
6272 optional and not inherited, clear reload_reg_rtx so other
6273 routines (such as subst_reloads) don't get confused. */
6274 for (j = 0; j < n_reloads; j++)
6275 if (reload_reg_rtx[j] != 0
6276 && ((reload_optional[j] && ! reload_inherited[j])
6277 || (reload_in[j] == 0 && reload_out[j] == 0
6278 && ! reload_secondary_p[j])))
6280 int regno = true_regnum (reload_reg_rtx[j]);
6282 if (spill_reg_order[regno] >= 0)
6283 clear_reload_reg_in_use (regno, reload_opnum[j],
6284 reload_when_needed[j], reload_mode[j]);
6285 reload_reg_rtx[j] = 0;
6288 /* Record which pseudos and which spill regs have output reloads. */
6289 for (j = 0; j < n_reloads; j++)
6291 register int r = reload_order[j];
6293 i = reload_spill_index[r];
6295 /* I is nonneg if this reload uses a register.
6296 If reload_reg_rtx[r] is 0, this is an optional reload
6297 that we opted to ignore. */
6298 if (reload_out_reg[r] != 0 && GET_CODE (reload_out_reg[r]) == REG
6299 && reload_reg_rtx[r] != 0)
6301 register int nregno = REGNO (reload_out_reg[r]);
6304 if (nregno < FIRST_PSEUDO_REGISTER)
6305 nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
6308 reg_has_output_reload[nregno + nr] = 1;
6312 nr = HARD_REGNO_NREGS (i, reload_mode[r]);
6314 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6317 if (reload_when_needed[r] != RELOAD_OTHER
6318 && reload_when_needed[r] != RELOAD_FOR_OUTPUT
6319 && reload_when_needed[r] != RELOAD_FOR_INSN)
6325 /* Deallocate the reload register for reload R. This is called from
6326 remove_address_replacements. */
6328 deallocate_reload_reg (r)
6333 if (! reload_reg_rtx[r])
6335 regno = true_regnum (reload_reg_rtx[r]);
6336 reload_reg_rtx[r] = 0;
6337 if (spill_reg_order[regno] >= 0)
6338 clear_reload_reg_in_use (regno, reload_opnum[r], reload_when_needed[r],
6340 reload_spill_index[r] = -1;
6343 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
6344 reloads of the same item for fear that we might not have enough reload
6345 registers. However, normally they will get the same reload register
6346 and hence actually need not be loaded twice.
6348 Here we check for the most common case of this phenomenon: when we have
6349 a number of reloads for the same object, each of which were allocated
6350 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6351 reload, and is not modified in the insn itself. If we find such,
6352 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6353 This will not increase the number of spill registers needed and will
6354 prevent redundant code. */
6357 merge_assigned_reloads (insn)
6362 /* Scan all the reloads looking for ones that only load values and
6363 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6364 assigned and not modified by INSN. */
6366 for (i = 0; i < n_reloads; i++)
6368 int conflicting_input = 0;
6369 int max_input_address_opnum = -1;
6370 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6372 if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER
6373 || reload_out[i] != 0 || reload_reg_rtx[i] == 0
6374 || reg_set_p (reload_reg_rtx[i], insn))
6377 /* Look at all other reloads. Ensure that the only use of this
6378 reload_reg_rtx is in a reload that just loads the same value
6379 as we do. Note that any secondary reloads must be of the identical
6380 class since the values, modes, and result registers are the
6381 same, so we need not do anything with any secondary reloads. */
6383 for (j = 0; j < n_reloads; j++)
6385 if (i == j || reload_reg_rtx[j] == 0
6386 || ! reg_overlap_mentioned_p (reload_reg_rtx[j],
6390 if (reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS
6391 && reload_opnum[j] > max_input_address_opnum)
6392 max_input_address_opnum = reload_opnum[j];
6394 /* If the reload regs aren't exactly the same (e.g, different modes)
6395 or if the values are different, we can't merge this reload.
6396 But if it is an input reload, we might still merge
6397 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6399 if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
6400 || reload_out[j] != 0 || reload_in[j] == 0
6401 || ! rtx_equal_p (reload_in[i], reload_in[j]))
6403 if (reload_when_needed[j] != RELOAD_FOR_INPUT
6404 || ((reload_when_needed[i] != RELOAD_FOR_INPUT_ADDRESS
6405 || reload_opnum[i] > reload_opnum[j])
6406 && reload_when_needed[i] != RELOAD_FOR_OTHER_ADDRESS))
6408 conflicting_input = 1;
6409 if (min_conflicting_input_opnum > reload_opnum[j])
6410 min_conflicting_input_opnum = reload_opnum[j];
6414 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6415 we, in fact, found any matching reloads. */
6418 && max_input_address_opnum <= min_conflicting_input_opnum)
6420 for (j = 0; j < n_reloads; j++)
6421 if (i != j && reload_reg_rtx[j] != 0
6422 && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
6423 && (! conflicting_input
6424 || reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS
6425 || reload_when_needed[j] == RELOAD_FOR_OTHER_ADDRESS))
6427 reload_when_needed[i] = RELOAD_OTHER;
6429 reload_spill_index[j] = -1;
6430 transfer_replacements (i, j);
6433 /* If this is now RELOAD_OTHER, look for any reloads that load
6434 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6435 if they were for inputs, RELOAD_OTHER for outputs. Note that
6436 this test is equivalent to looking for reloads for this operand
6439 if (reload_when_needed[i] == RELOAD_OTHER)
6440 for (j = 0; j < n_reloads; j++)
6441 if (reload_in[j] != 0
6442 && reload_when_needed[i] != RELOAD_OTHER
6443 && reg_overlap_mentioned_for_reload_p (reload_in[j],
6445 reload_when_needed[j]
6446 = ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
6447 || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS)
6448 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6454 /* Output insns to reload values in and out of the chosen reload regs. */
6457 emit_reload_insns (chain)
6458 struct insn_chain *chain;
6460 rtx insn = chain->insn;
6463 rtx input_reload_insns[MAX_RECOG_OPERANDS];
6464 rtx other_input_address_reload_insns = 0;
6465 rtx other_input_reload_insns = 0;
6466 rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6467 rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6468 rtx output_reload_insns[MAX_RECOG_OPERANDS];
6469 rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6470 rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6471 rtx operand_reload_insns = 0;
6472 rtx other_operand_reload_insns = 0;
6473 rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6474 rtx following_insn = NEXT_INSN (insn);
6475 rtx before_insn = PREV_INSN (insn);
6477 /* Values to be put in spill_reg_store are put here first. */
6478 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6479 HARD_REG_SET reg_reloaded_died;
6481 CLEAR_HARD_REG_SET (reg_reloaded_died);
6483 for (j = 0; j < reload_n_operands; j++)
6484 input_reload_insns[j] = input_address_reload_insns[j]
6485 = inpaddr_address_reload_insns[j]
6486 = output_reload_insns[j] = output_address_reload_insns[j]
6487 = outaddr_address_reload_insns[j]
6488 = other_output_reload_insns[j] = 0;
6490 /* Now output the instructions to copy the data into and out of the
6491 reload registers. Do these in the order that the reloads were reported,
6492 since reloads of base and index registers precede reloads of operands
6493 and the operands may need the base and index registers reloaded. */
6495 for (j = 0; j < n_reloads; j++)
6498 rtx oldequiv_reg = 0;
6499 rtx this_reload_insn = 0;
6500 int expect_occurrences = 1;
6502 if (reload_reg_rtx[j]
6503 && REGNO (reload_reg_rtx[j]) < FIRST_PSEUDO_REGISTER)
6504 new_spill_reg_store[REGNO (reload_reg_rtx[j])] = 0;
6506 old = (reload_in[j] && GET_CODE (reload_in[j]) == MEM
6507 ? reload_in_reg[j] : reload_in[j]);
6510 /* AUTO_INC reloads need to be handled even if inherited. We got an
6511 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6512 && (! reload_inherited[j] || (reload_out[j] && ! reload_out_reg[j]))
6513 && ! rtx_equal_p (reload_reg_rtx[j], old)
6514 && reload_reg_rtx[j] != 0)
6516 register rtx reloadreg = reload_reg_rtx[j];
6518 enum machine_mode mode;
6521 /* Determine the mode to reload in.
6522 This is very tricky because we have three to choose from.
6523 There is the mode the insn operand wants (reload_inmode[J]).
6524 There is the mode of the reload register RELOADREG.
6525 There is the intrinsic mode of the operand, which we could find
6526 by stripping some SUBREGs.
6527 It turns out that RELOADREG's mode is irrelevant:
6528 we can change that arbitrarily.
6530 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6531 then the reload reg may not support QImode moves, so use SImode.
6532 If foo is in memory due to spilling a pseudo reg, this is safe,
6533 because the QImode value is in the least significant part of a
6534 slot big enough for a SImode. If foo is some other sort of
6535 memory reference, then it is impossible to reload this case,
6536 so previous passes had better make sure this never happens.
6538 Then consider a one-word union which has SImode and one of its
6539 members is a float, being fetched as (SUBREG:SF union:SI).
6540 We must fetch that as SFmode because we could be loading into
6541 a float-only register. In this case OLD's mode is correct.
6543 Consider an immediate integer: it has VOIDmode. Here we need
6544 to get a mode from something else.
6546 In some cases, there is a fourth mode, the operand's
6547 containing mode. If the insn specifies a containing mode for
6548 this operand, it overrides all others.
6550 I am not sure whether the algorithm here is always right,
6551 but it does the right things in those cases. */
6553 mode = GET_MODE (old);
6554 if (mode == VOIDmode)
6555 mode = reload_inmode[j];
6557 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6558 /* If we need a secondary register for this operation, see if
6559 the value is already in a register in that class. Don't
6560 do this if the secondary register will be used as a scratch
6563 if (reload_secondary_in_reload[j] >= 0
6564 && reload_secondary_in_icode[j] == CODE_FOR_nothing
6567 = find_equiv_reg (old, insn,
6568 reload_reg_class[reload_secondary_in_reload[j]],
6569 -1, NULL_PTR, 0, mode);
6572 /* If reloading from memory, see if there is a register
6573 that already holds the same value. If so, reload from there.
6574 We can pass 0 as the reload_reg_p argument because
6575 any other reload has either already been emitted,
6576 in which case find_equiv_reg will see the reload-insn,
6577 or has yet to be emitted, in which case it doesn't matter
6578 because we will use this equiv reg right away. */
6580 if (oldequiv == 0 && optimize
6581 && (GET_CODE (old) == MEM
6582 || (GET_CODE (old) == REG
6583 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6584 && reg_renumber[REGNO (old)] < 0)))
6585 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6586 -1, NULL_PTR, 0, mode);
6590 int regno = true_regnum (oldequiv);
6592 /* If OLDEQUIV is a spill register, don't use it for this
6593 if any other reload needs it at an earlier stage of this insn
6594 or at this stage. */
6595 if (spill_reg_order[regno] >= 0
6596 && (! reload_reg_free_p (regno, reload_opnum[j],
6597 reload_when_needed[j])
6598 || ! reload_reg_free_before_p (regno, reload_opnum[j],
6599 reload_when_needed[j], 1)))
6602 /* If OLDEQUIV is not a spill register,
6603 don't use it if any other reload wants it. */
6604 if (spill_reg_order[regno] < 0)
6607 for (k = 0; k < n_reloads; k++)
6608 if (reload_reg_rtx[k] != 0 && k != j
6609 && reg_overlap_mentioned_for_reload_p (reload_reg_rtx[k],
6617 /* If it is no cheaper to copy from OLDEQUIV into the
6618 reload register than it would be to move from memory,
6619 don't use it. Likewise, if we need a secondary register
6623 && ((REGNO_REG_CLASS (regno) != reload_reg_class[j]
6624 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
6625 reload_reg_class[j])
6626 >= MEMORY_MOVE_COST (mode, reload_reg_class[j], 1)))
6627 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6628 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6632 #ifdef SECONDARY_MEMORY_NEEDED
6633 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6634 reload_reg_class[j],
6641 /* delete_output_reload is only invoked properly if old contains
6642 the original pseudo register. Since this is replaced with a
6643 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6644 find the pseudo in RELOAD_IN_REG. */
6646 && reload_override_in[j]
6647 && GET_CODE (reload_in_reg[j]) == REG)
6650 old = reload_in_reg[j];
6654 else if (GET_CODE (oldequiv) == REG)
6655 oldequiv_reg = oldequiv;
6656 else if (GET_CODE (oldequiv) == SUBREG)
6657 oldequiv_reg = SUBREG_REG (oldequiv);
6659 /* If we are reloading from a register that was recently stored in
6660 with an output-reload, see if we can prove there was
6661 actually no need to store the old value in it. */
6663 if (optimize && GET_CODE (oldequiv) == REG
6664 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6665 && spill_reg_store[REGNO (oldequiv)]
6666 && GET_CODE (old) == REG
6667 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6668 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6669 reload_out_reg[j])))
6670 delete_output_reload (insn, j, REGNO (oldequiv));
6672 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6673 then load RELOADREG from OLDEQUIV. Note that we cannot use
6674 gen_lowpart_common since it can do the wrong thing when
6675 RELOADREG has a multi-word mode. Note that RELOADREG
6676 must always be a REG here. */
6678 if (GET_MODE (reloadreg) != mode)
6679 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6680 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6681 oldequiv = SUBREG_REG (oldequiv);
6682 if (GET_MODE (oldequiv) != VOIDmode
6683 && mode != GET_MODE (oldequiv))
6684 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6686 /* Switch to the right place to emit the reload insns. */
6687 switch (reload_when_needed[j])
6690 where = &other_input_reload_insns;
6692 case RELOAD_FOR_INPUT:
6693 where = &input_reload_insns[reload_opnum[j]];
6695 case RELOAD_FOR_INPUT_ADDRESS:
6696 where = &input_address_reload_insns[reload_opnum[j]];
6698 case RELOAD_FOR_INPADDR_ADDRESS:
6699 where = &inpaddr_address_reload_insns[reload_opnum[j]];
6701 case RELOAD_FOR_OUTPUT_ADDRESS:
6702 where = &output_address_reload_insns[reload_opnum[j]];
6704 case RELOAD_FOR_OUTADDR_ADDRESS:
6705 where = &outaddr_address_reload_insns[reload_opnum[j]];
6707 case RELOAD_FOR_OPERAND_ADDRESS:
6708 where = &operand_reload_insns;
6710 case RELOAD_FOR_OPADDR_ADDR:
6711 where = &other_operand_reload_insns;
6713 case RELOAD_FOR_OTHER_ADDRESS:
6714 where = &other_input_address_reload_insns;
6720 push_to_sequence (*where);
6723 /* Auto-increment addresses must be reloaded in a special way. */
6724 if (reload_out[j] && ! reload_out_reg[j])
6726 /* We are not going to bother supporting the case where a
6727 incremented register can't be copied directly from
6728 OLDEQUIV since this seems highly unlikely. */
6729 if (reload_secondary_in_reload[j] >= 0)
6732 if (reload_inherited[j])
6733 oldequiv = reloadreg;
6735 old = XEXP (reload_in_reg[j], 0);
6737 if (optimize && GET_CODE (oldequiv) == REG
6738 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6739 && spill_reg_store[REGNO (oldequiv)]
6740 && GET_CODE (old) == REG
6741 && (dead_or_set_p (insn,
6742 spill_reg_stored_to[REGNO (oldequiv)])
6743 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6745 delete_output_reload (insn, j, REGNO (oldequiv));
6747 /* Prevent normal processing of this reload. */
6749 /* Output a special code sequence for this case. */
6750 new_spill_reg_store[REGNO (reloadreg)]
6751 = inc_for_reload (reloadreg, oldequiv, reload_out[j],
6755 /* If we are reloading a pseudo-register that was set by the previous
6756 insn, see if we can get rid of that pseudo-register entirely
6757 by redirecting the previous insn into our reload register. */
6759 else if (optimize && GET_CODE (old) == REG
6760 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6761 && dead_or_set_p (insn, old)
6762 /* This is unsafe if some other reload
6763 uses the same reg first. */
6764 && reload_reg_free_before_p (REGNO (reloadreg),
6766 reload_when_needed[j], 0))
6768 rtx temp = PREV_INSN (insn);
6769 while (temp && GET_CODE (temp) == NOTE)
6770 temp = PREV_INSN (temp);
6772 && GET_CODE (temp) == INSN
6773 && GET_CODE (PATTERN (temp)) == SET
6774 && SET_DEST (PATTERN (temp)) == old
6775 /* Make sure we can access insn_operand_constraint. */
6776 && asm_noperands (PATTERN (temp)) < 0
6777 /* This is unsafe if prev insn rejects our reload reg. */
6778 && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
6780 /* This is unsafe if operand occurs more than once in current
6781 insn. Perhaps some occurrences aren't reloaded. */
6782 && count_occurrences (PATTERN (insn), old) == 1
6783 /* Don't risk splitting a matching pair of operands. */
6784 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6786 /* Store into the reload register instead of the pseudo. */
6787 SET_DEST (PATTERN (temp)) = reloadreg;
6789 /* If the previous insn is an output reload, the source is
6790 a reload register, and its spill_reg_store entry will
6791 contain the previous destination. This is now
6793 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6794 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6796 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6797 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6800 /* If these are the only uses of the pseudo reg,
6801 pretend for GDB it lives in the reload reg we used. */
6802 if (REG_N_DEATHS (REGNO (old)) == 1
6803 && REG_N_SETS (REGNO (old)) == 1)
6805 reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
6806 alter_reg (REGNO (old), -1);
6812 /* We can't do that, so output an insn to load RELOADREG. */
6816 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6817 rtx second_reload_reg = 0;
6818 enum insn_code icode;
6820 /* If we have a secondary reload, pick up the secondary register
6821 and icode, if any. If OLDEQUIV and OLD are different or
6822 if this is an in-out reload, recompute whether or not we
6823 still need a secondary register and what the icode should
6824 be. If we still need a secondary register and the class or
6825 icode is different, go back to reloading from OLD if using
6826 OLDEQUIV means that we got the wrong type of register. We
6827 cannot have different class or icode due to an in-out reload
6828 because we don't make such reloads when both the input and
6829 output need secondary reload registers. */
6831 if (reload_secondary_in_reload[j] >= 0)
6833 int secondary_reload = reload_secondary_in_reload[j];
6834 rtx real_oldequiv = oldequiv;
6837 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6838 and similarly for OLD.
6839 See comments in get_secondary_reload in reload.c. */
6840 /* If it is a pseudo that cannot be replaced with its
6841 equivalent MEM, we must fall back to reload_in, which
6842 will have all the necessary substitutions registered. */
6844 if (GET_CODE (oldequiv) == REG
6845 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6846 && reg_equiv_memory_loc[REGNO (oldequiv)] != 0)
6848 if (reg_equiv_address[REGNO (oldequiv)]
6849 || num_not_at_initial_offset)
6850 real_oldequiv = reload_in[j];
6852 real_oldequiv = reg_equiv_mem[REGNO (oldequiv)];
6855 if (GET_CODE (old) == REG
6856 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6857 && reg_equiv_memory_loc[REGNO (old)] != 0)
6859 if (reg_equiv_address[REGNO (old)]
6860 || num_not_at_initial_offset)
6861 real_old = reload_in[j];
6863 real_old = reg_equiv_mem[REGNO (old)];
6866 second_reload_reg = reload_reg_rtx[secondary_reload];
6867 icode = reload_secondary_in_icode[j];
6869 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6870 || (reload_in[j] != 0 && reload_out[j] != 0))
6872 enum reg_class new_class
6873 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6874 mode, real_oldequiv);
6876 if (new_class == NO_REGS)
6877 second_reload_reg = 0;
6880 enum insn_code new_icode;
6881 enum machine_mode new_mode;
6883 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6884 REGNO (second_reload_reg)))
6885 oldequiv = old, real_oldequiv = real_old;
6888 new_icode = reload_in_optab[(int) mode];
6889 if (new_icode != CODE_FOR_nothing
6890 && ((insn_operand_predicate[(int) new_icode][0]
6891 && ! ((*insn_operand_predicate[(int) new_icode][0])
6893 || (insn_operand_predicate[(int) new_icode][1]
6894 && ! ((*insn_operand_predicate[(int) new_icode][1])
6895 (real_oldequiv, mode)))))
6896 new_icode = CODE_FOR_nothing;
6898 if (new_icode == CODE_FOR_nothing)
6901 new_mode = insn_operand_mode[(int) new_icode][2];
6903 if (GET_MODE (second_reload_reg) != new_mode)
6905 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6907 oldequiv = old, real_oldequiv = real_old;
6910 = gen_rtx_REG (new_mode,
6911 REGNO (second_reload_reg));
6917 /* If we still need a secondary reload register, check
6918 to see if it is being used as a scratch or intermediate
6919 register and generate code appropriately. If we need
6920 a scratch register, use REAL_OLDEQUIV since the form of
6921 the insn may depend on the actual address if it is
6924 if (second_reload_reg)
6926 if (icode != CODE_FOR_nothing)
6928 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6929 second_reload_reg));
6934 /* See if we need a scratch register to load the
6935 intermediate register (a tertiary reload). */
6936 enum insn_code tertiary_icode
6937 = reload_secondary_in_icode[secondary_reload];
6939 if (tertiary_icode != CODE_FOR_nothing)
6941 rtx third_reload_reg
6942 = reload_reg_rtx[reload_secondary_in_reload[secondary_reload]];
6944 emit_insn ((GEN_FCN (tertiary_icode)
6945 (second_reload_reg, real_oldequiv,
6946 third_reload_reg)));
6949 gen_reload (second_reload_reg, real_oldequiv,
6951 reload_when_needed[j]);
6953 oldequiv = second_reload_reg;
6959 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6961 rtx real_oldequiv = oldequiv;
6963 if ((GET_CODE (oldequiv) == REG
6964 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6965 && reg_equiv_memory_loc[REGNO (oldequiv)] != 0)
6966 || (GET_CODE (oldequiv) == SUBREG
6967 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6968 && (REGNO (SUBREG_REG (oldequiv))
6969 >= FIRST_PSEUDO_REGISTER)
6970 && (reg_equiv_memory_loc
6971 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6972 real_oldequiv = reload_in[j];
6973 gen_reload (reloadreg, real_oldequiv, reload_opnum[j],
6974 reload_when_needed[j]);
6979 this_reload_insn = get_last_insn ();
6980 /* End this sequence. */
6981 *where = get_insns ();
6984 /* Update reload_override_in so that delete_address_reloads_1
6985 can see the actual register usage. */
6987 reload_override_in[j] = oldequiv;
6990 /* When inheriting a wider reload, we have a MEM in reload_in[j],
6991 e.g. inheriting a SImode output reload for
6992 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6993 if (optimize && reload_inherited[j] && reload_in[j]
6994 && GET_CODE (reload_in[j]) == MEM
6995 && GET_CODE (reload_in_reg[j]) == MEM
6996 && reload_spill_index[j] >= 0
6997 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7000 = count_occurrences (PATTERN (insn), reload_in[j]) == 1 ? 0 : -1;
7002 = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7005 /* If we are reloading a register that was recently stored in with an
7006 output-reload, see if we can prove there was
7007 actually no need to store the old value in it. */
7010 && (reload_inherited[j] || reload_override_in[j])
7011 && reload_reg_rtx[j]
7012 && GET_CODE (reload_reg_rtx[j]) == REG
7013 && spill_reg_store[REGNO (reload_reg_rtx[j])] != 0
7015 /* There doesn't seem to be any reason to restrict this to pseudos
7016 and doing so loses in the case where we are copying from a
7017 register of the wrong class. */
7018 && REGNO (spill_reg_stored_to[REGNO (reload_reg_rtx[j])])
7019 >= FIRST_PSEUDO_REGISTER
7021 /* The insn might have already some references to stackslots
7022 replaced by MEMs, while reload_out_reg still names the
7024 && (dead_or_set_p (insn,
7025 spill_reg_stored_to[REGNO (reload_reg_rtx[j])])
7026 || rtx_equal_p (spill_reg_stored_to[REGNO (reload_reg_rtx[j])],
7027 reload_out_reg[j])))
7028 delete_output_reload (insn, j, REGNO (reload_reg_rtx[j]));
7030 /* Input-reloading is done. Now do output-reloading,
7031 storing the value from the reload-register after the main insn
7032 if reload_out[j] is nonzero.
7034 ??? At some point we need to support handling output reloads of
7035 JUMP_INSNs or insns that set cc0. */
7037 /* If this is an output reload that stores something that is
7038 not loaded in this same reload, see if we can eliminate a previous
7041 rtx pseudo = reload_out_reg[j];
7044 && GET_CODE (pseudo) == REG
7045 && ! rtx_equal_p (reload_in_reg[j], pseudo)
7046 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7047 && reg_last_reload_reg[REGNO (pseudo)])
7049 int pseudo_no = REGNO (pseudo);
7050 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7052 /* We don't need to test full validity of last_regno for
7053 inherit here; we only want to know if the store actually
7054 matches the pseudo. */
7055 if (reg_reloaded_contents[last_regno] == pseudo_no
7056 && spill_reg_store[last_regno]
7057 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7058 delete_output_reload (insn, j, last_regno);
7062 old = reload_out_reg[j];
7064 && reload_reg_rtx[j] != old
7065 && reload_reg_rtx[j] != 0)
7067 register rtx reloadreg = reload_reg_rtx[j];
7068 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7069 register rtx second_reloadreg = 0;
7072 enum machine_mode mode;
7075 /* An output operand that dies right away does need a reload,
7076 but need not be copied from it. Show the new location in the
7078 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
7079 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7081 XEXP (note, 0) = reload_reg_rtx[j];
7084 /* Likewise for a SUBREG of an operand that dies. */
7085 else if (GET_CODE (old) == SUBREG
7086 && GET_CODE (SUBREG_REG (old)) == REG
7087 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7090 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7094 else if (GET_CODE (old) == SCRATCH)
7095 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7096 but we don't want to make an output reload. */
7100 /* Strip off of OLD any size-increasing SUBREGs such as
7101 (SUBREG:SI foo:QI 0). */
7103 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
7104 && (GET_MODE_SIZE (GET_MODE (old))
7105 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
7106 old = SUBREG_REG (old);
7109 /* If is a JUMP_INSN, we can't support output reloads yet. */
7110 if (GET_CODE (insn) == JUMP_INSN)
7113 if (reload_when_needed[j] == RELOAD_OTHER)
7116 push_to_sequence (output_reload_insns[reload_opnum[j]]);
7118 old = reload_out[j];
7120 /* Determine the mode to reload in.
7121 See comments above (for input reloading). */
7123 mode = GET_MODE (old);
7124 if (mode == VOIDmode)
7126 /* VOIDmode should never happen for an output. */
7127 if (asm_noperands (PATTERN (insn)) < 0)
7128 /* It's the compiler's fault. */
7129 fatal_insn ("VOIDmode on an output", insn);
7130 error_for_asm (insn, "output operand is constant in `asm'");
7131 /* Prevent crash--use something we know is valid. */
7133 old = gen_rtx_REG (mode, REGNO (reloadreg));
7136 if (GET_MODE (reloadreg) != mode)
7137 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
7139 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7141 /* If we need two reload regs, set RELOADREG to the intermediate
7142 one, since it will be stored into OLD. We might need a secondary
7143 register only for an input reload, so check again here. */
7145 if (reload_secondary_out_reload[j] >= 0)
7149 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
7150 && reg_equiv_mem[REGNO (old)] != 0)
7151 real_old = reg_equiv_mem[REGNO (old)];
7153 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
7157 second_reloadreg = reloadreg;
7158 reloadreg = reload_reg_rtx[reload_secondary_out_reload[j]];
7160 /* See if RELOADREG is to be used as a scratch register
7161 or as an intermediate register. */
7162 if (reload_secondary_out_icode[j] != CODE_FOR_nothing)
7164 emit_insn ((GEN_FCN (reload_secondary_out_icode[j])
7165 (real_old, second_reloadreg, reloadreg)));
7170 /* See if we need both a scratch and intermediate reload
7173 int secondary_reload = reload_secondary_out_reload[j];
7174 enum insn_code tertiary_icode
7175 = reload_secondary_out_icode[secondary_reload];
7177 if (GET_MODE (reloadreg) != mode)
7178 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
7180 if (tertiary_icode != CODE_FOR_nothing)
7183 = reload_reg_rtx[reload_secondary_out_reload[secondary_reload]];
7186 /* Copy primary reload reg to secondary reload reg.
7187 (Note that these have been swapped above, then
7188 secondary reload reg to OLD using our insn. */
7190 /* If REAL_OLD is a paradoxical SUBREG, remove it
7191 and try to put the opposite SUBREG on
7193 if (GET_CODE (real_old) == SUBREG
7194 && (GET_MODE_SIZE (GET_MODE (real_old))
7195 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7196 && 0 != (tem = gen_lowpart_common
7197 (GET_MODE (SUBREG_REG (real_old)),
7199 real_old = SUBREG_REG (real_old), reloadreg = tem;
7201 gen_reload (reloadreg, second_reloadreg,
7202 reload_opnum[j], reload_when_needed[j]);
7203 emit_insn ((GEN_FCN (tertiary_icode)
7204 (real_old, reloadreg, third_reloadreg)));
7209 /* Copy between the reload regs here and then to
7212 gen_reload (reloadreg, second_reloadreg,
7213 reload_opnum[j], reload_when_needed[j]);
7219 /* Output the last reload insn. */
7224 /* Don't output the last reload if OLD is not the dest of
7225 INSN and is in the src and is clobbered by INSN. */
7226 if (! flag_expensive_optimizations
7227 || GET_CODE (old) != REG
7228 || !(set = single_set (insn))
7229 || rtx_equal_p (old, SET_DEST (set))
7230 || !reg_mentioned_p (old, SET_SRC (set))
7231 || !regno_clobbered_p (REGNO (old), insn))
7232 gen_reload (old, reloadreg, reload_opnum[j],
7233 reload_when_needed[j]);
7236 /* Look at all insns we emitted, just to be safe. */
7237 for (p = get_insns (); p; p = NEXT_INSN (p))
7238 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
7240 rtx pat = PATTERN (p);
7242 /* If this output reload doesn't come from a spill reg,
7243 clear any memory of reloaded copies of the pseudo reg.
7244 If this output reload comes from a spill reg,
7245 reg_has_output_reload will make this do nothing. */
7246 note_stores (pat, forget_old_reloads_1);
7248 if (reg_mentioned_p (reload_reg_rtx[j], pat))
7250 rtx set = single_set (insn);
7251 if (reload_spill_index[j] < 0
7253 && SET_SRC (set) == reload_reg_rtx[j])
7255 int src = REGNO (SET_SRC (set));
7257 reload_spill_index[j] = src;
7258 SET_HARD_REG_BIT (reg_is_output_reload, src);
7259 if (find_regno_note (insn, REG_DEAD, src))
7260 SET_HARD_REG_BIT (reg_reloaded_died, src);
7262 if (REGNO (reload_reg_rtx[j]) < FIRST_PSEUDO_REGISTER)
7264 int s = reload_secondary_out_reload[j];
7265 set = single_set (p);
7266 /* If this reload copies only to the secondary reload
7267 register, the secondary reload does the actual
7269 if (s >= 0 && set == NULL_RTX)
7270 ; /* We can't tell what function the secondary reload
7271 has and where the actual store to the pseudo is
7272 made; leave new_spill_reg_store alone. */
7274 && SET_SRC (set) == reload_reg_rtx[j]
7275 && SET_DEST (set) == reload_reg_rtx[s])
7277 /* Usually the next instruction will be the
7278 secondary reload insn; if we can confirm
7279 that it is, setting new_spill_reg_store to
7280 that insn will allow an extra optimization. */
7281 rtx s_reg = reload_reg_rtx[s];
7282 rtx next = NEXT_INSN (p);
7283 reload_out[s] = reload_out[j];
7284 reload_out_reg[s] = reload_out_reg[j];
7285 set = single_set (next);
7286 if (set && SET_SRC (set) == s_reg
7287 && ! new_spill_reg_store[REGNO (s_reg)])
7289 SET_HARD_REG_BIT (reg_is_output_reload,
7291 new_spill_reg_store[REGNO (s_reg)] = next;
7295 new_spill_reg_store[REGNO (reload_reg_rtx[j])] = p;
7300 if (reload_when_needed[j] == RELOAD_OTHER)
7302 emit_insns (other_output_reload_insns[reload_opnum[j]]);
7303 other_output_reload_insns[reload_opnum[j]] = get_insns ();
7306 output_reload_insns[reload_opnum[j]] = get_insns ();
7312 /* Now write all the insns we made for reloads in the order expected by
7313 the allocation functions. Prior to the insn being reloaded, we write
7314 the following reloads:
7316 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7318 RELOAD_OTHER reloads.
7320 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7321 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7322 RELOAD_FOR_INPUT reload for the operand.
7324 RELOAD_FOR_OPADDR_ADDRS reloads.
7326 RELOAD_FOR_OPERAND_ADDRESS reloads.
7328 After the insn being reloaded, we write the following:
7330 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7331 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7332 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7333 reloads for the operand. The RELOAD_OTHER output reloads are
7334 output in descending order by reload number. */
7336 emit_insns_before (other_input_address_reload_insns, insn);
7337 emit_insns_before (other_input_reload_insns, insn);
7339 for (j = 0; j < reload_n_operands; j++)
7341 emit_insns_before (inpaddr_address_reload_insns[j], insn);
7342 emit_insns_before (input_address_reload_insns[j], insn);
7343 emit_insns_before (input_reload_insns[j], insn);
7346 emit_insns_before (other_operand_reload_insns, insn);
7347 emit_insns_before (operand_reload_insns, insn);
7349 for (j = 0; j < reload_n_operands; j++)
7351 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
7352 emit_insns_before (output_address_reload_insns[j], following_insn);
7353 emit_insns_before (output_reload_insns[j], following_insn);
7354 emit_insns_before (other_output_reload_insns[j], following_insn);
7357 /* Keep basic block info up to date. */
7360 if (basic_block_head[chain->block] == insn)
7361 basic_block_head[chain->block] = NEXT_INSN (before_insn);
7362 if (basic_block_end[chain->block] == insn)
7363 basic_block_end[chain->block] = PREV_INSN (following_insn);
7366 /* For all the spill regs newly reloaded in this instruction,
7367 record what they were reloaded from, so subsequent instructions
7368 can inherit the reloads.
7370 Update spill_reg_store for the reloads of this insn.
7371 Copy the elements that were updated in the loop above. */
7373 for (j = 0; j < n_reloads; j++)
7375 register int r = reload_order[j];
7376 register int i = reload_spill_index[r];
7378 /* I is nonneg if this reload used a register.
7379 If reload_reg_rtx[r] is 0, this is an optional reload
7380 that we opted to ignore. */
7382 if (i >= 0 && reload_reg_rtx[r] != 0)
7385 = HARD_REGNO_NREGS (i, GET_MODE (reload_reg_rtx[r]));
7387 int part_reaches_end = 0;
7388 int all_reaches_end = 1;
7390 /* For a multi register reload, we need to check if all or part
7391 of the value lives to the end. */
7392 for (k = 0; k < nr; k++)
7394 if (reload_reg_reaches_end_p (i + k, reload_opnum[r],
7395 reload_when_needed[r]))
7396 part_reaches_end = 1;
7398 all_reaches_end = 0;
7401 /* Ignore reloads that don't reach the end of the insn in
7403 if (all_reaches_end)
7405 /* First, clear out memory of what used to be in this spill reg.
7406 If consecutive registers are used, clear them all. */
7408 for (k = 0; k < nr; k++)
7409 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7411 /* Maybe the spill reg contains a copy of reload_out. */
7412 if (reload_out[r] != 0
7413 && (GET_CODE (reload_out[r]) == REG
7415 || ! reload_out_reg[r]
7417 || GET_CODE (reload_out_reg[r]) == REG))
7419 rtx out = (GET_CODE (reload_out[r]) == REG
7423 /* AUTO_INC */ : XEXP (reload_in_reg[r], 0));
7424 register int nregno = REGNO (out);
7425 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7426 : HARD_REGNO_NREGS (nregno,
7427 GET_MODE (reload_reg_rtx[r])));
7429 spill_reg_store[i] = new_spill_reg_store[i];
7430 spill_reg_stored_to[i] = out;
7431 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
7433 /* If NREGNO is a hard register, it may occupy more than
7434 one register. If it does, say what is in the
7435 rest of the registers assuming that both registers
7436 agree on how many words the object takes. If not,
7437 invalidate the subsequent registers. */
7439 if (nregno < FIRST_PSEUDO_REGISTER)
7440 for (k = 1; k < nnr; k++)
7441 reg_last_reload_reg[nregno + k]
7443 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
7444 REGNO (reload_reg_rtx[r]) + k)
7447 /* Now do the inverse operation. */
7448 for (k = 0; k < nr; k++)
7450 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7451 reg_reloaded_contents[i + k]
7452 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7455 reg_reloaded_insn[i + k] = insn;
7456 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7460 /* Maybe the spill reg contains a copy of reload_in. Only do
7461 something if there will not be an output reload for
7462 the register being reloaded. */
7463 else if (reload_out_reg[r] == 0
7464 && reload_in[r] != 0
7465 && ((GET_CODE (reload_in[r]) == REG
7466 && REGNO (reload_in[r]) >= FIRST_PSEUDO_REGISTER
7467 && ! reg_has_output_reload[REGNO (reload_in[r])])
7468 || (GET_CODE (reload_in_reg[r]) == REG
7469 && ! reg_has_output_reload[REGNO (reload_in_reg[r])]))
7470 && ! reg_set_p (reload_reg_rtx[r], PATTERN (insn)))
7472 register int nregno;
7475 if (GET_CODE (reload_in[r]) == REG
7476 && REGNO (reload_in[r]) >= FIRST_PSEUDO_REGISTER)
7477 nregno = REGNO (reload_in[r]);
7478 else if (GET_CODE (reload_in_reg[r]) == REG)
7479 nregno = REGNO (reload_in_reg[r]);
7481 nregno = REGNO (XEXP (reload_in_reg[r], 0));
7483 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7484 : HARD_REGNO_NREGS (nregno,
7485 GET_MODE (reload_reg_rtx[r])));
7487 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
7489 if (nregno < FIRST_PSEUDO_REGISTER)
7490 for (k = 1; k < nnr; k++)
7491 reg_last_reload_reg[nregno + k]
7493 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
7494 REGNO (reload_reg_rtx[r]) + k)
7497 /* Unless we inherited this reload, show we haven't
7498 recently done a store.
7499 Previous stores of inherited auto_inc expressions
7500 also have to be discarded. */
7501 if (! reload_inherited[r]
7502 || (reload_out[r] && ! reload_out_reg[r]))
7503 spill_reg_store[i] = 0;
7505 for (k = 0; k < nr; k++)
7507 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7508 reg_reloaded_contents[i + k]
7509 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7512 reg_reloaded_insn[i + k] = insn;
7513 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7518 /* However, if part of the reload reaches the end, then we must
7519 invalidate the old info for the part that survives to the end. */
7520 else if (part_reaches_end)
7522 for (k = 0; k < nr; k++)
7523 if (reload_reg_reaches_end_p (i + k,
7525 reload_when_needed[r]))
7526 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7530 /* The following if-statement was #if 0'd in 1.34 (or before...).
7531 It's reenabled in 1.35 because supposedly nothing else
7532 deals with this problem. */
7534 /* If a register gets output-reloaded from a non-spill register,
7535 that invalidates any previous reloaded copy of it.
7536 But forget_old_reloads_1 won't get to see it, because
7537 it thinks only about the original insn. So invalidate it here. */
7538 if (i < 0 && reload_out[r] != 0
7539 && (GET_CODE (reload_out[r]) == REG
7540 || (GET_CODE (reload_out[r]) == MEM
7541 && GET_CODE (reload_out_reg[r]) == REG)))
7543 rtx out = (GET_CODE (reload_out[r]) == REG
7544 ? reload_out[r] : reload_out_reg[r]);
7545 register int nregno = REGNO (out);
7546 if (nregno >= FIRST_PSEUDO_REGISTER)
7548 rtx src_reg, store_insn;
7550 reg_last_reload_reg[nregno] = 0;
7552 /* If we can find a hard register that is stored, record
7553 the storing insn so that we may delete this insn with
7554 delete_output_reload. */
7555 src_reg = reload_reg_rtx[r];
7557 /* If this is an optional reload, try to find the source reg
7558 from an input reload. */
7561 rtx set = single_set (insn);
7562 if (SET_DEST (set) == reload_out[r])
7566 src_reg = SET_SRC (set);
7568 for (k = 0; k < n_reloads; k++)
7570 if (reload_in[k] == src_reg)
7572 src_reg = reload_reg_rtx[k];
7579 store_insn = new_spill_reg_store[REGNO (src_reg)];
7580 if (src_reg && GET_CODE (src_reg) == REG
7581 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7583 int src_regno = REGNO (src_reg);
7584 int nr = HARD_REGNO_NREGS (src_regno, reload_mode[r]);
7585 /* The place where to find a death note varies with
7586 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7587 necessarily checked exactly in the code that moves
7588 notes, so just check both locations. */
7589 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7591 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7594 spill_reg_store[src_regno + nr] = store_insn;
7595 spill_reg_stored_to[src_regno + nr] = out;
7596 reg_reloaded_contents[src_regno + nr] = nregno;
7597 reg_reloaded_insn[src_regno + nr] = store_insn;
7598 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7599 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7600 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7602 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7604 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7606 reg_last_reload_reg[nregno] = src_reg;
7611 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (reload_out[r]));
7613 while (num_regs-- > 0)
7614 reg_last_reload_reg[nregno + num_regs] = 0;
7618 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7621 /* Emit code to perform a reload from IN (which may be a reload register) to
7622 OUT (which may also be a reload register). IN or OUT is from operand
7623 OPNUM with reload type TYPE.
7625 Returns first insn emitted. */
7628 gen_reload (out, in, opnum, type)
7632 enum reload_type type;
7634 rtx last = get_last_insn ();
7637 /* If IN is a paradoxical SUBREG, remove it and try to put the
7638 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7639 if (GET_CODE (in) == SUBREG
7640 && (GET_MODE_SIZE (GET_MODE (in))
7641 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7642 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7643 in = SUBREG_REG (in), out = tem;
7644 else if (GET_CODE (out) == SUBREG
7645 && (GET_MODE_SIZE (GET_MODE (out))
7646 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7647 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7648 out = SUBREG_REG (out), in = tem;
7650 /* How to do this reload can get quite tricky. Normally, we are being
7651 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7652 register that didn't get a hard register. In that case we can just
7653 call emit_move_insn.
7655 We can also be asked to reload a PLUS that adds a register or a MEM to
7656 another register, constant or MEM. This can occur during frame pointer
7657 elimination and while reloading addresses. This case is handled by
7658 trying to emit a single insn to perform the add. If it is not valid,
7659 we use a two insn sequence.
7661 Finally, we could be called to handle an 'o' constraint by putting
7662 an address into a register. In that case, we first try to do this
7663 with a named pattern of "reload_load_address". If no such pattern
7664 exists, we just emit a SET insn and hope for the best (it will normally
7665 be valid on machines that use 'o').
7667 This entire process is made complex because reload will never
7668 process the insns we generate here and so we must ensure that
7669 they will fit their constraints and also by the fact that parts of
7670 IN might be being reloaded separately and replaced with spill registers.
7671 Because of this, we are, in some sense, just guessing the right approach
7672 here. The one listed above seems to work.
7674 ??? At some point, this whole thing needs to be rethought. */
7676 if (GET_CODE (in) == PLUS
7677 && (GET_CODE (XEXP (in, 0)) == REG
7678 || GET_CODE (XEXP (in, 0)) == SUBREG
7679 || GET_CODE (XEXP (in, 0)) == MEM)
7680 && (GET_CODE (XEXP (in, 1)) == REG
7681 || GET_CODE (XEXP (in, 1)) == SUBREG
7682 || CONSTANT_P (XEXP (in, 1))
7683 || GET_CODE (XEXP (in, 1)) == MEM))
7685 /* We need to compute the sum of a register or a MEM and another
7686 register, constant, or MEM, and put it into the reload
7687 register. The best possible way of doing this is if the machine
7688 has a three-operand ADD insn that accepts the required operands.
7690 The simplest approach is to try to generate such an insn and see if it
7691 is recognized and matches its constraints. If so, it can be used.
7693 It might be better not to actually emit the insn unless it is valid,
7694 but we need to pass the insn as an operand to `recog' and
7695 `extract_insn' and it is simpler to emit and then delete the insn if
7696 not valid than to dummy things up. */
7698 rtx op0, op1, tem, insn;
7701 op0 = find_replacement (&XEXP (in, 0));
7702 op1 = find_replacement (&XEXP (in, 1));
7704 /* Since constraint checking is strict, commutativity won't be
7705 checked, so we need to do that here to avoid spurious failure
7706 if the add instruction is two-address and the second operand
7707 of the add is the same as the reload reg, which is frequently
7708 the case. If the insn would be A = B + A, rearrange it so
7709 it will be A = A + B as constrain_operands expects. */
7711 if (GET_CODE (XEXP (in, 1)) == REG
7712 && REGNO (out) == REGNO (XEXP (in, 1)))
7713 tem = op0, op0 = op1, op1 = tem;
7715 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7716 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7718 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7719 code = recog_memoized (insn);
7723 extract_insn (insn);
7724 /* We want constrain operands to treat this insn strictly in
7725 its validity determination, i.e., the way it would after reload
7727 if (constrain_operands (1))
7731 delete_insns_since (last);
7733 /* If that failed, we must use a conservative two-insn sequence.
7734 use move to copy constant, MEM, or pseudo register to the reload
7735 register since "move" will be able to handle an arbitrary operand,
7736 unlike add which can't, in general. Then add the registers.
7738 If there is another way to do this for a specific machine, a
7739 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7742 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7743 || (GET_CODE (op1) == REG
7744 && REGNO (op1) >= FIRST_PSEUDO_REGISTER))
7745 tem = op0, op0 = op1, op1 = tem;
7747 gen_reload (out, op0, opnum, type);
7749 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7750 This fixes a problem on the 32K where the stack pointer cannot
7751 be used as an operand of an add insn. */
7753 if (rtx_equal_p (op0, op1))
7756 insn = emit_insn (gen_add2_insn (out, op1));
7758 /* If that failed, copy the address register to the reload register.
7759 Then add the constant to the reload register. */
7761 code = recog_memoized (insn);
7765 extract_insn (insn);
7766 /* We want constrain operands to treat this insn strictly in
7767 its validity determination, i.e., the way it would after reload
7769 if (constrain_operands (1))
7771 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7773 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7778 delete_insns_since (last);
7780 gen_reload (out, op1, opnum, type);
7781 insn = emit_insn (gen_add2_insn (out, op0));
7782 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7785 #ifdef SECONDARY_MEMORY_NEEDED
7786 /* If we need a memory location to do the move, do it that way. */
7787 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7788 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7789 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7790 REGNO_REG_CLASS (REGNO (out)),
7793 /* Get the memory to use and rewrite both registers to its mode. */
7794 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7796 if (GET_MODE (loc) != GET_MODE (out))
7797 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7799 if (GET_MODE (loc) != GET_MODE (in))
7800 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7802 gen_reload (loc, in, opnum, type);
7803 gen_reload (out, loc, opnum, type);
7807 /* If IN is a simple operand, use gen_move_insn. */
7808 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7809 emit_insn (gen_move_insn (out, in));
7811 #ifdef HAVE_reload_load_address
7812 else if (HAVE_reload_load_address)
7813 emit_insn (gen_reload_load_address (out, in));
7816 /* Otherwise, just write (set OUT IN) and hope for the best. */
7818 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7820 /* Return the first insn emitted.
7821 We can not just return get_last_insn, because there may have
7822 been multiple instructions emitted. Also note that gen_move_insn may
7823 emit more than one insn itself, so we can not assume that there is one
7824 insn emitted per emit_insn_before call. */
7826 return last ? NEXT_INSN (last) : get_insns ();
7829 /* Delete a previously made output-reload
7830 whose result we now believe is not needed.
7831 First we double-check.
7833 INSN is the insn now being processed.
7834 LAST_RELOAD_REG is the hard register number for which we want to delete
7835 the last output reload.
7836 J is the reload-number that originally used REG. The caller has made
7837 certain that reload J doesn't use REG any longer for input. */
7840 delete_output_reload (insn, j, last_reload_reg)
7843 int last_reload_reg;
7845 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7846 rtx reg = spill_reg_stored_to[last_reload_reg];
7849 int n_inherited = 0;
7853 /* Get the raw pseudo-register referred to. */
7855 while (GET_CODE (reg) == SUBREG)
7856 reg = SUBREG_REG (reg);
7857 substed = reg_equiv_memory_loc[REGNO (reg)];
7859 /* This is unsafe if the operand occurs more often in the current
7860 insn than it is inherited. */
7861 for (k = n_reloads - 1; k >= 0; k--)
7863 rtx reg2 = reload_in[k];
7866 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7867 reg2 = reload_in_reg[k];
7869 if (reload_out[k] && ! reload_out_reg[k])
7870 reg2 = XEXP (reload_in_reg[k], 0);
7872 while (GET_CODE (reg2) == SUBREG)
7873 reg2 = SUBREG_REG (reg2);
7874 if (rtx_equal_p (reg2, reg))
7876 if (reload_inherited[k] || reload_override_in[k] || k == j)
7879 reg2 = reload_out_reg[k];
7882 while (GET_CODE (reg2) == SUBREG)
7883 reg2 = XEXP (reg2, 0);
7884 if (rtx_equal_p (reg2, reg))
7891 n_occurrences = count_occurrences (PATTERN (insn), reg);
7893 n_occurrences += count_occurrences (PATTERN (insn), substed);
7894 if (n_occurrences > n_inherited)
7897 /* If the pseudo-reg we are reloading is no longer referenced
7898 anywhere between the store into it and here,
7899 and no jumps or labels intervene, then the value can get
7900 here through the reload reg alone.
7901 Otherwise, give up--return. */
7902 for (i1 = NEXT_INSN (output_reload_insn);
7903 i1 != insn; i1 = NEXT_INSN (i1))
7905 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7907 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7908 && reg_mentioned_p (reg, PATTERN (i1)))
7910 /* If this is USE in front of INSN, we only have to check that
7911 there are no more references than accounted for by inheritance. */
7912 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7914 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7915 i1 = NEXT_INSN (i1);
7917 if (n_occurrences <= n_inherited && i1 == insn)
7923 /* The caller has already checked that REG dies or is set in INSN.
7924 It has also checked that we are optimizing, and thus some inaccurancies
7925 in the debugging information are acceptable.
7926 So we could just delete output_reload_insn.
7927 But in some cases we can improve the debugging information without
7928 sacrificing optimization - maybe even improving the code:
7929 See if the pseudo reg has been completely replaced
7930 with reload regs. If so, delete the store insn
7931 and forget we had a stack slot for the pseudo. */
7932 if (reload_out[j] != reload_in[j]
7933 && REG_N_DEATHS (REGNO (reg)) == 1
7934 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7935 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7939 /* We know that it was used only between here
7940 and the beginning of the current basic block.
7941 (We also know that the last use before INSN was
7942 the output reload we are thinking of deleting, but never mind that.)
7943 Search that range; see if any ref remains. */
7944 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7946 rtx set = single_set (i2);
7948 /* Uses which just store in the pseudo don't count,
7949 since if they are the only uses, they are dead. */
7950 if (set != 0 && SET_DEST (set) == reg)
7952 if (GET_CODE (i2) == CODE_LABEL
7953 || GET_CODE (i2) == JUMP_INSN)
7955 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7956 && reg_mentioned_p (reg, PATTERN (i2)))
7958 /* Some other ref remains; just delete the output reload we
7960 delete_address_reloads (output_reload_insn, insn);
7961 PUT_CODE (output_reload_insn, NOTE);
7962 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7963 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7968 /* Delete the now-dead stores into this pseudo. */
7969 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7971 rtx set = single_set (i2);
7973 if (set != 0 && SET_DEST (set) == reg)
7975 delete_address_reloads (i2, insn);
7976 /* This might be a basic block head,
7977 thus don't use delete_insn. */
7978 PUT_CODE (i2, NOTE);
7979 NOTE_SOURCE_FILE (i2) = 0;
7980 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7982 if (GET_CODE (i2) == CODE_LABEL
7983 || GET_CODE (i2) == JUMP_INSN)
7987 /* For the debugging info,
7988 say the pseudo lives in this reload reg. */
7989 reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
7990 alter_reg (REGNO (reg), -1);
7992 delete_address_reloads (output_reload_insn, insn);
7993 PUT_CODE (output_reload_insn, NOTE);
7994 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7995 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7999 /* We are going to delete DEAD_INSN. Recursively delete loads of
8000 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8001 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8003 delete_address_reloads (dead_insn, current_insn)
8004 rtx dead_insn, current_insn;
8006 rtx set = single_set (dead_insn);
8007 rtx set2, dst, prev, next;
8010 rtx dst = SET_DEST (set);
8011 if (GET_CODE (dst) == MEM)
8012 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8014 /* If we deleted the store from a reloaded post_{in,de}c expression,
8015 we can delete the matching adds. */
8016 prev = PREV_INSN (dead_insn);
8017 next = NEXT_INSN (dead_insn);
8018 if (! prev || ! next)
8020 set = single_set (next);
8021 set2 = single_set (prev);
8023 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8024 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8025 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8027 dst = SET_DEST (set);
8028 if (! rtx_equal_p (dst, SET_DEST (set2))
8029 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8030 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8031 || (INTVAL (XEXP (SET_SRC (set), 1))
8032 != - INTVAL (XEXP (SET_SRC (set2), 1))))
8038 /* Subfunction of delete_address_reloads: process registers found in X. */
8040 delete_address_reloads_1 (dead_insn, x, current_insn)
8041 rtx dead_insn, x, current_insn;
8043 rtx prev, set, dst, i2;
8045 enum rtx_code code = GET_CODE (x);
8049 char *fmt= GET_RTX_FORMAT (code);
8050 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8053 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8054 else if (fmt[i] == 'E')
8056 for (j = XVECLEN (x, i) - 1; j >=0; j--)
8057 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8064 if (spill_reg_order[REGNO (x)] < 0)
8067 /* Scan backwards for the insn that sets x. This might be a way back due
8069 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8071 code = GET_CODE (prev);
8072 if (code == CODE_LABEL || code == JUMP_INSN)
8074 if (GET_RTX_CLASS (code) != 'i')
8076 if (reg_set_p (x, PATTERN (prev)))
8078 if (reg_referenced_p (x, PATTERN (prev)))
8081 if (! prev || INSN_UID (prev) < reload_first_uid)
8083 /* Check that PREV only sets the reload register. */
8084 set = single_set (prev);
8087 dst = SET_DEST (set);
8088 if (GET_CODE (dst) != REG
8089 || ! rtx_equal_p (dst, x))
8091 if (! reg_set_p (dst, PATTERN (dead_insn)))
8093 /* Check if DST was used in a later insn -
8094 it might have been inherited. */
8095 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8097 if (GET_CODE (i2) == CODE_LABEL)
8099 if (GET_RTX_CLASS (GET_CODE (i2)) != 'i')
8101 if (reg_referenced_p (dst, PATTERN (i2)))
8103 /* If there is a reference to the register in the current insn,
8104 it might be loaded in a non-inherited reload. If no other
8105 reload uses it, that means the register is set before
8107 if (i2 == current_insn)
8109 for (j = n_reloads - 1; j >= 0; j--)
8110 if ((reload_reg_rtx[j] == dst && reload_inherited[j])
8111 || reload_override_in[j] == dst)
8113 for (j = n_reloads - 1; j >= 0; j--)
8114 if (reload_in[j] && reload_reg_rtx[j] == dst)
8121 if (GET_CODE (i2) == JUMP_INSN)
8123 if (reg_set_p (dst, PATTERN (i2)))
8125 /* If DST is still live at CURRENT_INSN, check if it is used for
8127 if (i2 == current_insn)
8129 for (j = n_reloads - 1; j >= 0; j--)
8130 if ((reload_reg_rtx[j] == dst && reload_inherited[j])
8131 || reload_override_in[j] == dst)
8133 /* ??? We can't finish the loop here, because dst might be
8134 allocated to a pseudo in this block if no reload in this
8135 block needs any of the clsses containing DST - see
8136 spill_hard_reg. There is no easy way to tell this, so we
8137 have to scan till the end of the basic block. */
8141 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8142 reg_reloaded_contents[REGNO (dst)] = -1;
8143 /* Can't use delete_insn here because PREV might be a basic block head. */
8144 PUT_CODE (prev, NOTE);
8145 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
8146 NOTE_SOURCE_FILE (prev) = 0;
8149 /* Output reload-insns to reload VALUE into RELOADREG.
8150 VALUE is an autoincrement or autodecrement RTX whose operand
8151 is a register or memory location;
8152 so reloading involves incrementing that location.
8153 IN is either identical to VALUE, or some cheaper place to reload from.
8155 INC_AMOUNT is the number to increment or decrement by (always positive).
8156 This cannot be deduced from VALUE.
8158 Return the instruction that stores into RELOADREG. */
8161 inc_for_reload (reloadreg, in, value, inc_amount)
8166 /* REG or MEM to be copied and incremented. */
8167 rtx incloc = XEXP (value, 0);
8168 /* Nonzero if increment after copying. */
8169 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
8175 rtx real_in = in == value ? XEXP (in, 0) : in;
8177 /* No hard register is equivalent to this register after
8178 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
8179 we could inc/dec that register as well (maybe even using it for
8180 the source), but I'm not sure it's worth worrying about. */
8181 if (GET_CODE (incloc) == REG)
8182 reg_last_reload_reg[REGNO (incloc)] = 0;
8184 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8185 inc_amount = - inc_amount;
8187 inc = GEN_INT (inc_amount);
8189 /* If this is post-increment, first copy the location to the reload reg. */
8190 if (post && real_in != reloadreg)
8191 emit_insn (gen_move_insn (reloadreg, real_in));
8195 /* See if we can directly increment INCLOC. Use a method similar to
8196 that in gen_reload. */
8198 last = get_last_insn ();
8199 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8200 gen_rtx_PLUS (GET_MODE (incloc),
8203 code = recog_memoized (add_insn);
8206 extract_insn (add_insn);
8207 if (constrain_operands (1))
8209 /* If this is a pre-increment and we have incremented the value
8210 where it lives, copy the incremented value to RELOADREG to
8211 be used as an address. */
8214 emit_insn (gen_move_insn (reloadreg, incloc));
8219 delete_insns_since (last);
8222 /* If couldn't do the increment directly, must increment in RELOADREG.
8223 The way we do this depends on whether this is pre- or post-increment.
8224 For pre-increment, copy INCLOC to the reload register, increment it
8225 there, then save back. */
8229 if (in != reloadreg)
8230 emit_insn (gen_move_insn (reloadreg, real_in));
8231 emit_insn (gen_add2_insn (reloadreg, inc));
8232 store = emit_insn (gen_move_insn (incloc, reloadreg));
8237 Because this might be a jump insn or a compare, and because RELOADREG
8238 may not be available after the insn in an input reload, we must do
8239 the incrementation before the insn being reloaded for.
8241 We have already copied IN to RELOADREG. Increment the copy in
8242 RELOADREG, save that back, then decrement RELOADREG so it has
8243 the original value. */
8245 emit_insn (gen_add2_insn (reloadreg, inc));
8246 store = emit_insn (gen_move_insn (incloc, reloadreg));
8247 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8253 /* Return 1 if we are certain that the constraint-string STRING allows
8254 the hard register REG. Return 0 if we can't be sure of this. */
8257 constraint_accepts_reg_p (string, reg)
8262 int regno = true_regnum (reg);
8265 /* Initialize for first alternative. */
8267 /* Check that each alternative contains `g' or `r'. */
8269 switch (c = *string++)
8272 /* If an alternative lacks `g' or `r', we lose. */
8275 /* If an alternative lacks `g' or `r', we lose. */
8278 /* Initialize for next alternative. */
8283 /* Any general reg wins for this alternative. */
8284 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
8288 /* Any reg in specified class wins for this alternative. */
8290 enum reg_class class = REG_CLASS_FROM_LETTER (c);
8292 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
8298 /* Return the number of places FIND appears within X, but don't count
8299 an occurrence if some SET_DEST is FIND. */
8302 count_occurrences (x, find)
8303 register rtx x, find;
8306 register enum rtx_code code;
8307 register char *format_ptr;
8315 code = GET_CODE (x);
8330 if (GET_CODE (find) == MEM && rtx_equal_p (x, find))
8334 if (SET_DEST (x) == find)
8335 return count_occurrences (SET_SRC (x), find);
8342 format_ptr = GET_RTX_FORMAT (code);
8345 for (i = 0; i < GET_RTX_LENGTH (code); i++)
8347 switch (*format_ptr++)
8350 count += count_occurrences (XEXP (x, i), find);
8354 if (XVEC (x, i) != NULL)
8356 for (j = 0; j < XVECLEN (x, i); j++)
8357 count += count_occurrences (XVECEXP (x, i, j), find);
8365 /* This array holds values which are equivalent to a hard register
8366 during reload_cse_regs. Each array element is an EXPR_LIST of
8367 values. Each time a hard register is set, we set the corresponding
8368 array element to the value. Each time a hard register is copied
8369 into memory, we add the memory location to the corresponding array
8370 element. We don't store values or memory addresses with side
8371 effects in this array.
8373 If the value is a CONST_INT, then the mode of the containing
8374 EXPR_LIST is the mode in which that CONST_INT was referenced.
8376 We sometimes clobber a specific entry in a list. In that case, we
8377 just set XEXP (list-entry, 0) to 0. */
8379 static rtx *reg_values;
8381 /* This is a preallocated REG rtx which we use as a temporary in
8382 reload_cse_invalidate_regno, so that we don't need to allocate a
8383 new one each time through a loop in that function. */
8385 static rtx invalidate_regno_rtx;
8387 /* Invalidate any entries in reg_values which depend on REGNO,
8388 including those for REGNO itself. This is called if REGNO is
8389 changing. If CLOBBER is true, then always forget anything we
8390 currently know about REGNO. MODE is the mode of the assignment to
8391 REGNO, which is used to determine how many hard registers are being
8392 changed. If MODE is VOIDmode, then only REGNO is being changed;
8393 this is used when invalidating call clobbered registers across a
8397 reload_cse_invalidate_regno (regno, mode, clobber)
8399 enum machine_mode mode;
8405 /* Our callers don't always go through true_regnum; we may see a
8406 pseudo-register here from a CLOBBER or the like. We probably
8407 won't ever see a pseudo-register that has a real register number,
8408 for we check anyhow for safety. */
8409 if (regno >= FIRST_PSEUDO_REGISTER)
8410 regno = reg_renumber[regno];
8414 if (mode == VOIDmode)
8415 endregno = regno + 1;
8417 endregno = regno + HARD_REGNO_NREGS (regno, mode);
8420 for (i = regno; i < endregno; i++)
8423 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8427 for (x = reg_values[i]; x; x = XEXP (x, 1))
8429 if (XEXP (x, 0) != 0
8430 && refers_to_regno_p (regno, endregno, XEXP (x, 0), NULL_PTR))
8432 /* If this is the only entry on the list, clear
8433 reg_values[i]. Otherwise, just clear this entry on
8435 if (XEXP (x, 1) == 0 && x == reg_values[i])
8445 /* We must look at earlier registers, in case REGNO is part of a
8446 multi word value but is not the first register. If an earlier
8447 register has a value in a mode which overlaps REGNO, then we must
8448 invalidate that earlier register. Note that we do not need to
8449 check REGNO or later registers (we must not check REGNO itself,
8450 because we would incorrectly conclude that there was a conflict). */
8452 for (i = 0; i < regno; i++)
8456 for (x = reg_values[i]; x; x = XEXP (x, 1))
8458 if (XEXP (x, 0) != 0)
8460 PUT_MODE (invalidate_regno_rtx, GET_MODE (x));
8461 REGNO (invalidate_regno_rtx) = i;
8462 if (refers_to_regno_p (regno, endregno, invalidate_regno_rtx,
8465 reload_cse_invalidate_regno (i, VOIDmode, 1);
8473 /* The memory at address MEM_BASE is being changed.
8474 Return whether this change will invalidate VAL. */
8477 reload_cse_mem_conflict_p (mem_base, val)
8485 code = GET_CODE (val);
8488 /* Get rid of a few simple cases quickly. */
8501 if (GET_MODE (mem_base) == BLKmode
8502 || GET_MODE (val) == BLKmode)
8504 if (anti_dependence (val, mem_base))
8506 /* The address may contain nested MEMs. */
8513 fmt = GET_RTX_FORMAT (code);
8515 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8519 if (reload_cse_mem_conflict_p (mem_base, XEXP (val, i)))
8522 else if (fmt[i] == 'E')
8526 for (j = 0; j < XVECLEN (val, i); j++)
8527 if (reload_cse_mem_conflict_p (mem_base, XVECEXP (val, i, j)))
8535 /* Invalidate any entries in reg_values which are changed because of a
8536 store to MEM_RTX. If this is called because of a non-const call
8537 instruction, MEM_RTX is (mem:BLK const0_rtx). */
8540 reload_cse_invalidate_mem (mem_rtx)
8545 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8549 for (x = reg_values[i]; x; x = XEXP (x, 1))
8551 if (XEXP (x, 0) != 0
8552 && reload_cse_mem_conflict_p (mem_rtx, XEXP (x, 0)))
8554 /* If this is the only entry on the list, clear
8555 reg_values[i]. Otherwise, just clear this entry on
8557 if (XEXP (x, 1) == 0 && x == reg_values[i])
8568 /* Invalidate DEST, which is being assigned to or clobbered. The
8569 second parameter exists so that this function can be passed to
8570 note_stores; it is ignored. */
8573 reload_cse_invalidate_rtx (dest, ignore)
8575 rtx ignore ATTRIBUTE_UNUSED;
8577 while (GET_CODE (dest) == STRICT_LOW_PART
8578 || GET_CODE (dest) == SIGN_EXTRACT
8579 || GET_CODE (dest) == ZERO_EXTRACT
8580 || GET_CODE (dest) == SUBREG)
8581 dest = XEXP (dest, 0);
8583 if (GET_CODE (dest) == REG)
8584 reload_cse_invalidate_regno (REGNO (dest), GET_MODE (dest), 1);
8585 else if (GET_CODE (dest) == MEM)
8586 reload_cse_invalidate_mem (dest);
8589 /* Do a very simple CSE pass over the hard registers.
8591 This function detects no-op moves where we happened to assign two
8592 different pseudo-registers to the same hard register, and then
8593 copied one to the other. Reload will generate a useless
8594 instruction copying a register to itself.
8596 This function also detects cases where we load a value from memory
8597 into two different registers, and (if memory is more expensive than
8598 registers) changes it to simply copy the first register into the
8601 Another optimization is performed that scans the operands of each
8602 instruction to see whether the value is already available in a
8603 hard register. It then replaces the operand with the hard register
8604 if possible, much like an optional reload would. */
8607 reload_cse_regs_1 (first)
8615 init_alias_analysis ();
8617 reg_values = (rtx *) alloca (FIRST_PSEUDO_REGISTER * sizeof (rtx));
8618 bzero ((char *)reg_values, FIRST_PSEUDO_REGISTER * sizeof (rtx));
8620 /* Create our EXPR_LIST structures on reload_obstack, so that we can
8621 free them when we are done. */
8622 push_obstacks (&reload_obstack, &reload_obstack);
8623 firstobj = (char *) obstack_alloc (&reload_obstack, 0);
8625 /* We pass this to reload_cse_invalidate_mem to invalidate all of
8626 memory for a non-const call instruction. */
8627 callmem = gen_rtx_MEM (BLKmode, const0_rtx);
8629 /* This is used in reload_cse_invalidate_regno to avoid consing a
8630 new REG in a loop in that function. */
8631 invalidate_regno_rtx = gen_rtx_REG (VOIDmode, 0);
8633 for (insn = first; insn; insn = NEXT_INSN (insn))
8637 if (GET_CODE (insn) == CODE_LABEL)
8639 /* Forget all the register values at a code label. We don't
8640 try to do anything clever around jumps. */
8641 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8647 #ifdef NON_SAVING_SETJMP
8648 if (NON_SAVING_SETJMP && GET_CODE (insn) == NOTE
8649 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
8651 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8658 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8661 /* If this is a call instruction, forget anything stored in a
8662 call clobbered register, or, if this is not a const call, in
8664 if (GET_CODE (insn) == CALL_INSN)
8666 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8667 if (call_used_regs[i])
8668 reload_cse_invalidate_regno (i, VOIDmode, 1);
8670 if (! CONST_CALL_P (insn))
8671 reload_cse_invalidate_mem (callmem);
8674 body = PATTERN (insn);
8675 if (GET_CODE (body) == SET)
8678 if (reload_cse_noop_set_p (body, insn))
8680 /* If this sets the return value of the function, we must keep
8681 a USE around, in case this is in a different basic block
8682 than the final USE. Otherwise, we could loose important
8683 register lifeness information on SMALL_REGISTER_CLASSES
8684 machines, where return registers might be used as spills:
8685 subsequent passes assume that spill registers are dead at
8686 the end of a basic block. */
8687 if (REG_FUNCTION_VALUE_P (SET_DEST (body)))
8690 PATTERN (insn) = gen_rtx_USE (VOIDmode, SET_DEST (body));
8691 INSN_CODE (insn) = -1;
8692 REG_NOTES (insn) = NULL_RTX;
8693 push_obstacks (&reload_obstack, &reload_obstack);
8697 PUT_CODE (insn, NOTE);
8698 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8699 NOTE_SOURCE_FILE (insn) = 0;
8702 /* We're done with this insn. */
8706 /* It's not a no-op, but we can try to simplify it. */
8707 count += reload_cse_simplify_set (body, insn);
8710 apply_change_group ();
8712 reload_cse_simplify_operands (insn);
8714 reload_cse_record_set (body, body);
8716 else if (GET_CODE (body) == PARALLEL)
8719 rtx value = NULL_RTX;
8721 /* If every action in a PARALLEL is a noop, we can delete
8722 the entire PARALLEL. */
8723 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8725 rtx part = XVECEXP (body, 0, i);
8726 if (GET_CODE (part) == SET)
8728 if (! reload_cse_noop_set_p (part, insn))
8730 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8734 value = SET_DEST (part);
8737 else if (GET_CODE (part) != CLOBBER)
8745 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
8746 INSN_CODE (insn) = -1;
8747 REG_NOTES (insn) = NULL_RTX;
8748 push_obstacks (&reload_obstack, &reload_obstack);
8752 PUT_CODE (insn, NOTE);
8753 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8754 NOTE_SOURCE_FILE (insn) = 0;
8757 /* We're done with this insn. */
8761 /* It's not a no-op, but we can try to simplify it. */
8762 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8763 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8764 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8767 apply_change_group ();
8769 reload_cse_simplify_operands (insn);
8771 /* Look through the PARALLEL and record the values being
8772 set, if possible. Also handle any CLOBBERs. */
8773 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8775 rtx x = XVECEXP (body, 0, i);
8777 if (GET_CODE (x) == SET)
8778 reload_cse_record_set (x, body);
8780 note_stores (x, reload_cse_invalidate_rtx);
8784 note_stores (body, reload_cse_invalidate_rtx);
8787 /* Clobber any registers which appear in REG_INC notes. We
8788 could keep track of the changes to their values, but it is
8789 unlikely to help. */
8793 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
8794 if (REG_NOTE_KIND (x) == REG_INC)
8795 reload_cse_invalidate_rtx (XEXP (x, 0), NULL_RTX);
8799 /* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only
8800 after we have processed the insn. */
8801 if (GET_CODE (insn) == CALL_INSN)
8805 for (x = CALL_INSN_FUNCTION_USAGE (insn); x; x = XEXP (x, 1))
8806 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
8807 reload_cse_invalidate_rtx (XEXP (XEXP (x, 0), 0), NULL_RTX);
8811 /* Free all the temporary structures we created, and go back to the
8812 regular obstacks. */
8813 obstack_free (&reload_obstack, firstobj);
8817 /* Call cse / combine like post-reload optimization phases.
8818 FIRST is the first instruction. */
8820 reload_cse_regs (first)
8823 reload_cse_regs_1 (first);
8825 reload_cse_move2add (first);
8826 if (flag_expensive_optimizations)
8827 reload_cse_regs_1 (first);
8830 /* Return whether the values known for REGNO are equal to VAL. MODE
8831 is the mode of the object that VAL is being copied to; this matters
8832 if VAL is a CONST_INT. */
8835 reload_cse_regno_equal_p (regno, val, mode)
8838 enum machine_mode mode;
8845 for (x = reg_values[regno]; x; x = XEXP (x, 1))
8846 if (XEXP (x, 0) != 0
8847 && rtx_equal_p (XEXP (x, 0), val)
8848 && (! flag_float_store || GET_CODE (XEXP (x, 0)) != MEM
8849 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
8850 && (GET_CODE (val) != CONST_INT
8851 || mode == GET_MODE (x)
8852 || (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8853 /* On a big endian machine if the value spans more than
8854 one register then this register holds the high part of
8855 it and we can't use it.
8857 ??? We should also compare with the high part of the
8859 && !(WORDS_BIG_ENDIAN
8860 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
8861 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
8862 GET_MODE_BITSIZE (GET_MODE (x))))))
8868 /* See whether a single set is a noop. SET is the set instruction we
8869 are should check, and INSN is the instruction from which it came. */
8872 reload_cse_noop_set_p (set, insn)
8877 enum machine_mode dest_mode;
8881 src = SET_SRC (set);
8882 dest = SET_DEST (set);
8883 dest_mode = GET_MODE (dest);
8885 if (side_effects_p (src))
8888 dreg = true_regnum (dest);
8889 sreg = true_regnum (src);
8891 /* Check for setting a register to itself. In this case, we don't
8892 have to worry about REG_DEAD notes. */
8893 if (dreg >= 0 && dreg == sreg)
8899 /* Check for setting a register to itself. */
8903 /* Check for setting a register to a value which we already know
8904 is in the register. */
8905 else if (reload_cse_regno_equal_p (dreg, src, dest_mode))
8908 /* Check for setting a register DREG to another register SREG
8909 where SREG is equal to a value which is already in DREG. */
8914 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
8918 if (XEXP (x, 0) == 0)
8921 if (dest_mode == GET_MODE (x))
8923 else if (GET_MODE_BITSIZE (dest_mode)
8924 < GET_MODE_BITSIZE (GET_MODE (x)))
8925 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
8930 && reload_cse_regno_equal_p (dreg, tmp, dest_mode))
8938 else if (GET_CODE (dest) == MEM)
8940 /* Check for storing a register to memory when we know that the
8941 register is equivalent to the memory location. */
8943 && reload_cse_regno_equal_p (sreg, dest, dest_mode)
8944 && ! side_effects_p (dest))
8951 /* Try to simplify a single SET instruction. SET is the set pattern.
8952 INSN is the instruction it came from.
8953 This function only handles one case: if we set a register to a value
8954 which is not a register, we try to find that value in some other register
8955 and change the set into a register copy. */
8958 reload_cse_simplify_set (set, insn)
8964 enum machine_mode dest_mode;
8965 enum reg_class dclass;
8968 dreg = true_regnum (SET_DEST (set));
8972 src = SET_SRC (set);
8973 if (side_effects_p (src) || true_regnum (src) >= 0)
8976 dclass = REGNO_REG_CLASS (dreg);
8978 /* If memory loads are cheaper than register copies, don't change them. */
8979 if (GET_CODE (src) == MEM
8980 && MEMORY_MOVE_COST (GET_MODE (src), dclass, 1) < 2)
8983 /* If the constant is cheaper than a register, don't change it. */
8984 if (CONSTANT_P (src)
8985 && rtx_cost (src, SET) < 2)
8988 dest_mode = GET_MODE (SET_DEST (set));
8989 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8992 && REGISTER_MOVE_COST (REGNO_REG_CLASS (i), dclass) == 2
8993 && reload_cse_regno_equal_p (i, src, dest_mode))
8997 /* Pop back to the real obstacks while changing the insn. */
9000 validated = validate_change (insn, &SET_SRC (set),
9001 gen_rtx_REG (dest_mode, i), 1);
9003 /* Go back to the obstack we are using for temporary
9005 push_obstacks (&reload_obstack, &reload_obstack);
9014 /* Try to replace operands in INSN with equivalent values that are already
9015 in registers. This can be viewed as optional reloading.
9017 For each non-register operand in the insn, see if any hard regs are
9018 known to be equivalent to that operand. Record the alternatives which
9019 can accept these hard registers. Among all alternatives, select the
9020 ones which are better or equal to the one currently matching, where
9021 "better" is in terms of '?' and '!' constraints. Among the remaining
9022 alternatives, select the one which replaces most operands with
9026 reload_cse_simplify_operands (insn)
9029 #ifdef REGISTER_CONSTRAINTS
9032 char *constraints[MAX_RECOG_OPERANDS];
9034 /* Vector recording how bad an alternative is. */
9035 int *alternative_reject;
9036 /* Vector recording how many registers can be introduced by choosing
9037 this alternative. */
9038 int *alternative_nregs;
9039 /* Array of vectors recording, for each operand and each alternative,
9040 which hard register to substitute, or -1 if the operand should be
9042 int *op_alt_regno[MAX_RECOG_OPERANDS];
9043 /* Array of alternatives, sorted in order of decreasing desirability. */
9044 int *alternative_order;
9045 rtx reg = gen_rtx_REG (VOIDmode, -1);
9047 extract_insn (insn);
9049 if (recog_n_alternatives == 0 || recog_n_operands == 0)
9052 /* Figure out which alternative currently matches. */
9053 if (! constrain_operands (1))
9054 fatal_insn_not_found (insn);
9056 alternative_reject = (int *) alloca (recog_n_alternatives * sizeof (int));
9057 alternative_nregs = (int *) alloca (recog_n_alternatives * sizeof (int));
9058 alternative_order = (int *) alloca (recog_n_alternatives * sizeof (int));
9059 bzero ((char *)alternative_reject, recog_n_alternatives * sizeof (int));
9060 bzero ((char *)alternative_nregs, recog_n_alternatives * sizeof (int));
9062 for (i = 0; i < recog_n_operands; i++)
9064 enum machine_mode mode;
9068 op_alt_regno[i] = (int *) alloca (recog_n_alternatives * sizeof (int));
9069 for (j = 0; j < recog_n_alternatives; j++)
9070 op_alt_regno[i][j] = -1;
9072 p = constraints[i] = recog_constraints[i];
9073 mode = recog_operand_mode[i];
9075 /* Add the reject values for each alternative given by the constraints
9076 for this operand. */
9084 alternative_reject[j] += 3;
9086 alternative_reject[j] += 300;
9089 /* We won't change operands which are already registers. We
9090 also don't want to modify output operands. */
9091 regno = true_regnum (recog_operand[i]);
9093 || constraints[i][0] == '='
9094 || constraints[i][0] == '+')
9097 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
9099 int class = (int) NO_REGS;
9101 if (! reload_cse_regno_equal_p (regno, recog_operand[i], mode))
9104 REGNO (reg) = regno;
9105 PUT_MODE (reg, mode);
9107 /* We found a register equal to this operand. Now look for all
9108 alternatives that can accept this register and have not been
9109 assigned a register they can use yet. */
9118 case '=': case '+': case '?':
9119 case '#': case '&': case '!':
9121 case '0': case '1': case '2': case '3': case '4':
9122 case 'm': case '<': case '>': case 'V': case 'o':
9123 case 'E': case 'F': case 'G': case 'H':
9124 case 's': case 'i': case 'n':
9125 case 'I': case 'J': case 'K': case 'L':
9126 case 'M': case 'N': case 'O': case 'P':
9127 #ifdef EXTRA_CONSTRAINT
9128 case 'Q': case 'R': case 'S': case 'T': case 'U':
9131 /* These don't say anything we care about. */
9135 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
9140 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
9143 case ',': case '\0':
9144 /* See if REGNO fits this alternative, and set it up as the
9145 replacement register if we don't have one for this
9146 alternative yet and the operand being replaced is not
9147 a cheap CONST_INT. */
9148 if (op_alt_regno[i][j] == -1
9149 && reg_fits_class_p (reg, class, 0, mode)
9150 && (GET_CODE (recog_operand[i]) != CONST_INT
9151 || rtx_cost (recog_operand[i], SET) > rtx_cost (reg, SET)))
9153 alternative_nregs[j]++;
9154 op_alt_regno[i][j] = regno;
9166 /* Record all alternatives which are better or equal to the currently
9167 matching one in the alternative_order array. */
9168 for (i = j = 0; i < recog_n_alternatives; i++)
9169 if (alternative_reject[i] <= alternative_reject[which_alternative])
9170 alternative_order[j++] = i;
9171 recog_n_alternatives = j;
9173 /* Sort it. Given a small number of alternatives, a dumb algorithm
9174 won't hurt too much. */
9175 for (i = 0; i < recog_n_alternatives - 1; i++)
9178 int best_reject = alternative_reject[alternative_order[i]];
9179 int best_nregs = alternative_nregs[alternative_order[i]];
9182 for (j = i + 1; j < recog_n_alternatives; j++)
9184 int this_reject = alternative_reject[alternative_order[j]];
9185 int this_nregs = alternative_nregs[alternative_order[j]];
9187 if (this_reject < best_reject
9188 || (this_reject == best_reject && this_nregs < best_nregs))
9191 best_reject = this_reject;
9192 best_nregs = this_nregs;
9196 tmp = alternative_order[best];
9197 alternative_order[best] = alternative_order[i];
9198 alternative_order[i] = tmp;
9201 /* Substitute the operands as determined by op_alt_regno for the best
9203 j = alternative_order[0];
9205 /* Pop back to the real obstacks while changing the insn. */
9208 for (i = 0; i < recog_n_operands; i++)
9210 enum machine_mode mode = recog_operand_mode[i];
9211 if (op_alt_regno[i][j] == -1)
9214 validate_change (insn, recog_operand_loc[i],
9215 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
9218 for (i = recog_n_dups - 1; i >= 0; i--)
9220 int op = recog_dup_num[i];
9221 enum machine_mode mode = recog_operand_mode[op];
9223 if (op_alt_regno[op][j] == -1)
9226 validate_change (insn, recog_dup_loc[i],
9227 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
9230 /* Go back to the obstack we are using for temporary
9232 push_obstacks (&reload_obstack, &reload_obstack);
9234 return apply_change_group ();
9240 /* These two variables are used to pass information from
9241 reload_cse_record_set to reload_cse_check_clobber. */
9243 static int reload_cse_check_clobbered;
9244 static rtx reload_cse_check_src;
9246 /* See if DEST overlaps with RELOAD_CSE_CHECK_SRC. If it does, set
9247 RELOAD_CSE_CHECK_CLOBBERED. This is called via note_stores. The
9248 second argument, which is passed by note_stores, is ignored. */
9251 reload_cse_check_clobber (dest, ignore)
9253 rtx ignore ATTRIBUTE_UNUSED;
9255 if (reg_overlap_mentioned_p (dest, reload_cse_check_src))
9256 reload_cse_check_clobbered = 1;
9259 /* Record the result of a SET instruction. SET is the set pattern.
9260 BODY is the pattern of the insn that it came from. */
9263 reload_cse_record_set (set, body)
9269 enum machine_mode dest_mode;
9271 dest = SET_DEST (set);
9272 src = SET_SRC (set);
9273 dreg = true_regnum (dest);
9274 sreg = true_regnum (src);
9275 dest_mode = GET_MODE (dest);
9277 /* Some machines don't define AUTO_INC_DEC, but they still use push
9278 instructions. We need to catch that case here in order to
9279 invalidate the stack pointer correctly. Note that invalidating
9280 the stack pointer is different from invalidating DEST. */
9282 while (GET_CODE (x) == SUBREG
9283 || GET_CODE (x) == ZERO_EXTRACT
9284 || GET_CODE (x) == SIGN_EXTRACT
9285 || GET_CODE (x) == STRICT_LOW_PART)
9287 if (push_operand (x, GET_MODE (x)))
9289 reload_cse_invalidate_rtx (stack_pointer_rtx, NULL_RTX);
9290 reload_cse_invalidate_rtx (dest, NULL_RTX);
9294 /* We can only handle an assignment to a register, or a store of a
9295 register to a memory location. For other cases, we just clobber
9296 the destination. We also have to just clobber if there are side
9297 effects in SRC or DEST. */
9298 if ((dreg < 0 && GET_CODE (dest) != MEM)
9299 || side_effects_p (src)
9300 || side_effects_p (dest))
9302 reload_cse_invalidate_rtx (dest, NULL_RTX);
9307 /* We don't try to handle values involving CC, because it's a pain
9308 to keep track of when they have to be invalidated. */
9309 if (reg_mentioned_p (cc0_rtx, src)
9310 || reg_mentioned_p (cc0_rtx, dest))
9312 reload_cse_invalidate_rtx (dest, NULL_RTX);
9317 /* If BODY is a PARALLEL, then we need to see whether the source of
9318 SET is clobbered by some other instruction in the PARALLEL. */
9319 if (GET_CODE (body) == PARALLEL)
9323 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
9327 x = XVECEXP (body, 0, i);
9331 reload_cse_check_clobbered = 0;
9332 reload_cse_check_src = src;
9333 note_stores (x, reload_cse_check_clobber);
9334 if (reload_cse_check_clobbered)
9336 reload_cse_invalidate_rtx (dest, NULL_RTX);
9346 /* This is an assignment to a register. Update the value we
9347 have stored for the register. */
9352 /* This is a copy from one register to another. Any values
9353 which were valid for SREG are now valid for DREG. If the
9354 mode changes, we use gen_lowpart_common to extract only
9355 the part of the value that is copied. */
9356 reg_values[dreg] = 0;
9357 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
9361 if (XEXP (x, 0) == 0)
9363 if (dest_mode == GET_MODE (XEXP (x, 0)))
9365 else if (GET_MODE_BITSIZE (dest_mode)
9366 > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
9369 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
9371 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, tmp,
9376 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, src, NULL_RTX);
9378 /* We've changed DREG, so invalidate any values held by other
9379 registers that depend upon it. */
9380 reload_cse_invalidate_regno (dreg, dest_mode, 0);
9382 /* If this assignment changes more than one hard register,
9383 forget anything we know about the others. */
9384 for (i = 1; i < HARD_REGNO_NREGS (dreg, dest_mode); i++)
9385 reg_values[dreg + i] = 0;
9387 else if (GET_CODE (dest) == MEM)
9389 /* Invalidate conflicting memory locations. */
9390 reload_cse_invalidate_mem (dest);
9392 /* If we're storing a register to memory, add DEST to the list
9394 if (sreg >= 0 && ! side_effects_p (dest))
9395 reg_values[sreg] = gen_rtx_EXPR_LIST (dest_mode, dest,
9400 /* We should have bailed out earlier. */
9405 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
9407 This code might also be useful when reload gave up on reg+reg addresssing
9408 because of clashes between the return register and INDEX_REG_CLASS. */
9410 /* The maximum number of uses of a register we can keep track of to
9411 replace them with reg+reg addressing. */
9412 #define RELOAD_COMBINE_MAX_USES 6
9414 /* INSN is the insn where a register has ben used, and USEP points to the
9415 location of the register within the rtl. */
9416 struct reg_use { rtx insn, *usep; };
9418 /* If the register is used in some unknown fashion, USE_INDEX is negative.
9419 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
9420 indicates where it becomes live again.
9421 Otherwise, USE_INDEX is the index of the last encountered use of the
9422 register (which is first among these we have seen since we scan backwards),
9423 OFFSET contains the constant offset that is added to the register in
9424 all encountered uses, and USE_RUID indicates the first encountered, i.e.
9425 last, of these uses. */
9428 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
9433 } reg_state[FIRST_PSEUDO_REGISTER];
9435 /* Reverse linear uid. This is increased in reload_combine while scanning
9436 the instructions from last to first. It is used to set last_label_ruid
9437 and the store_ruid / use_ruid fields in reg_state. */
9438 static int reload_combine_ruid;
9444 int first_index_reg = 1, last_index_reg = 0;
9446 int last_label_ruid;
9448 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
9449 reload has already used it where appropriate, so there is no use in
9450 trying to generate it now. */
9451 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
9454 /* To avoid wasting too much time later searching for an index register,
9455 determine the minimum and maximum index register numbers. */
9456 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9458 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i))
9460 if (! last_index_reg)
9462 first_index_reg = i;
9465 /* If no index register is available, we can quit now. */
9466 if (first_index_reg > last_index_reg)
9469 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
9470 last_label_ruid = reload_combine_ruid = 0;
9471 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9474 reg_state[i].use_index = -1;
9477 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9478 reg_state[i].store_ruid = reload_combine_ruid;
9482 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
9486 /* We cannot do our optimization across labels. Invalidating all the use
9487 information we have would be costly, so we just note where the label
9488 is and then later disable any optimization that would cross it. */
9489 if (GET_CODE (insn) == CODE_LABEL)
9490 last_label_ruid = reload_combine_ruid;
9491 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
9493 reload_combine_ruid++;
9495 /* Look for (set (REGX) (CONST_INT))
9496 (set (REGX) (PLUS (REGX) (REGY)))
9498 ... (MEM (REGX)) ...
9500 (set (REGZ) (CONST_INT))
9502 ... (MEM (PLUS (REGZ) (REGY)))... .
9504 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
9505 and that we know all uses of REGX before it dies. */
9506 set = single_set (insn);
9508 && GET_CODE (SET_DEST (set)) == REG
9509 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
9510 GET_MODE (SET_DEST (set)))
9512 && GET_CODE (SET_SRC (set)) == PLUS
9513 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
9514 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
9515 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
9517 rtx reg = SET_DEST (set);
9518 rtx plus = SET_SRC (set);
9519 rtx base = XEXP (plus, 1);
9520 rtx prev = prev_nonnote_insn (insn);
9521 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
9522 int regno = REGNO (reg);
9524 rtx reg_sum = NULL_RTX;
9526 /* Now, we need an index register.
9527 We'll set index_reg to this index register, const_reg to the
9528 register that is to be loaded with the constant
9529 (denoted as REGZ in the substitution illustration above),
9530 and reg_sum to the register-register that we want to use to
9531 substitute uses of REG (typically in MEMs) with.
9532 First check REG and BASE for being index registers;
9533 we can use them even if they are not dead. */
9534 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
9535 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
9543 /* Otherwise, look for a free index register. Since we have
9544 checked above that neiter REG nor BASE are index registers,
9545 if we find anything at all, it will be different from these
9547 for (i = first_index_reg; i <= last_index_reg; i++)
9549 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
9550 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
9551 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
9552 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
9554 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
9555 const_reg = index_reg;
9556 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
9562 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
9563 && rtx_equal_p (SET_DEST (prev_set), reg)
9564 && reg_state[regno].use_index >= 0
9569 /* Change destination register and - if necessary - the
9570 constant value in PREV, the constant loading instruction. */
9571 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
9572 if (reg_state[regno].offset != const0_rtx)
9573 validate_change (prev,
9574 &SET_SRC (prev_set),
9575 GEN_INT (INTVAL (SET_SRC (prev_set))
9576 + INTVAL (reg_state[regno].offset)),
9578 /* Now for every use of REG that we have recorded, replace REG
9580 for (i = reg_state[regno].use_index;
9581 i < RELOAD_COMBINE_MAX_USES; i++)
9582 validate_change (reg_state[regno].reg_use[i].insn,
9583 reg_state[regno].reg_use[i].usep,
9586 if (apply_change_group ())
9590 /* Delete the reg-reg addition. */
9591 PUT_CODE (insn, NOTE);
9592 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9593 NOTE_SOURCE_FILE (insn) = 0;
9595 if (reg_state[regno].offset != const0_rtx)
9597 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
9599 for (np = ®_NOTES (prev); *np; )
9601 if (REG_NOTE_KIND (*np) == REG_EQUAL
9602 || REG_NOTE_KIND (*np) == REG_EQUIV)
9603 *np = XEXP (*np, 1);
9605 np = &XEXP (*np, 1);
9608 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9609 reg_state[REGNO (const_reg)].store_ruid = reload_combine_ruid;
9614 note_stores (PATTERN (insn), reload_combine_note_store);
9615 if (GET_CODE (insn) == CALL_INSN)
9619 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9621 if (call_used_regs[i])
9623 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9624 reg_state[i].store_ruid = reload_combine_ruid;
9627 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
9628 link = XEXP (link, 1))
9630 rtx use = XEXP (link, 0);
9631 int regno = REGNO (XEXP (use, 0));
9632 if (GET_CODE (use) == CLOBBER)
9634 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9635 reg_state[regno].store_ruid = reload_combine_ruid;
9638 reg_state[regno].use_index = -1;
9641 if (GET_CODE (insn) == JUMP_INSN)
9643 /* Non-spill registers might be used at the call destination in
9644 some unknown fashion, so we have to mark the unknown use. */
9645 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9648 reg_state[i].use_index = -1;
9651 reload_combine_note_use (&PATTERN (insn), insn);
9652 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9654 if (REG_NOTE_KIND (note) == REG_INC
9655 && GET_CODE (XEXP (note, 0)) == REG)
9656 reg_state[REGNO (XEXP (note, 0))].use_index = -1;
9661 /* Check if DST is a register or a subreg of a register; if it is,
9662 update reg_state[regno].store_ruid and reg_state[regno].use_index
9663 accordingly. Called via note_stores from reload_combine.
9664 The second argument, SET, is ignored. */
9666 reload_combine_note_store (dst, set)
9667 rtx dst, set ATTRIBUTE_UNUSED;
9671 unsigned size = GET_MODE_SIZE (GET_MODE (dst));
9673 if (GET_CODE (dst) == SUBREG)
9675 regno = SUBREG_WORD (dst);
9676 dst = SUBREG_REG (dst);
9678 if (GET_CODE (dst) != REG)
9680 regno += REGNO (dst);
9681 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
9682 careful with registers / register parts that are not full words. */
9683 if (size < (unsigned) UNITS_PER_WORD)
9684 reg_state[regno].use_index = -1;
9687 for (i = size / UNITS_PER_WORD - 1 + regno; i >= regno; i--)
9689 reg_state[i].store_ruid = reload_combine_ruid;
9690 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9695 /* XP points to a piece of rtl that has to be checked for any uses of
9697 *XP is the pattern of INSN, or a part of it.
9698 Called from reload_combine, and recursively by itself. */
9700 reload_combine_note_use (xp, insn)
9704 enum rtx_code code = x->code;
9707 rtx offset = const0_rtx; /* For the REG case below. */
9712 if (GET_CODE (SET_DEST (x)) == REG)
9714 reload_combine_note_use (&SET_SRC (x), insn);
9720 if (GET_CODE (SET_DEST (x)) == REG)
9725 /* We are interested in (plus (reg) (const_int)) . */
9726 if (GET_CODE (XEXP (x, 0)) != REG || GET_CODE (XEXP (x, 1)) != CONST_INT)
9728 offset = XEXP (x, 1);
9733 int regno = REGNO (x);
9736 /* Some spurious USEs of pseudo registers might remain.
9737 Just ignore them. */
9738 if (regno >= FIRST_PSEUDO_REGISTER)
9741 /* If this register is already used in some unknown fashion, we
9743 If we decrement the index from zero to -1, we can't store more
9744 uses, so this register becomes used in an unknown fashion. */
9745 use_index = --reg_state[regno].use_index;
9749 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
9751 /* We have found another use for a register that is already
9752 used later. Check if the offsets match; if not, mark the
9753 register as used in an unknown fashion. */
9754 if (! rtx_equal_p (offset, reg_state[regno].offset))
9756 reg_state[regno].use_index = -1;
9762 /* This is the first use of this register we have seen since we
9763 marked it as dead. */
9764 reg_state[regno].offset = offset;
9765 reg_state[regno].use_ruid = reload_combine_ruid;
9767 reg_state[regno].reg_use[use_index].insn = insn;
9768 reg_state[regno].reg_use[use_index].usep = xp;
9776 /* Recursively process the components of X. */
9777 fmt = GET_RTX_FORMAT (code);
9778 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9781 reload_combine_note_use (&XEXP (x, i), insn);
9782 else if (fmt[i] == 'E')
9784 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9785 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9790 /* See if we can reduce the cost of a constant by replacing a move with
9792 /* We cannot do our optimization across labels. Invalidating all the
9793 information about register contents we have would be costly, so we
9794 use last_label_luid (local variable of reload_cse_move2add) to note
9795 where the label is and then later disable any optimization that would
9797 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9798 reg_set_luid[n] is larger than last_label_luid[n] . */
9799 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9800 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
9801 reg_mode[n] to be valid.
9802 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
9803 has been set to reg_offset[n] in mode reg_mode[n] .
9804 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
9805 register n has been set to the sum of reg_offset[n] and register
9806 reg_base_reg[n], calculated in mode reg_mode[n] . */
9807 static rtx reg_offset[FIRST_PSEUDO_REGISTER];
9808 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9809 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9810 /* move2add_luid is linearily increased while scanning the instructions
9811 from first to last. It is used to set reg_set_luid in
9812 reload_cse_move2add and move2add_note_store. */
9813 static int move2add_luid;
9816 reload_cse_move2add (first)
9821 int last_label_luid;
9823 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
9824 reg_set_luid[i] = 0;
9826 last_label_luid = 0;
9828 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9832 if (GET_CODE (insn) == CODE_LABEL)
9833 last_label_luid = move2add_luid;
9834 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
9836 pat = PATTERN (insn);
9837 /* For simplicity, we only perform this optimization on
9838 straightforward SETs. */
9839 if (GET_CODE (pat) == SET
9840 && GET_CODE (SET_DEST (pat)) == REG)
9842 rtx reg = SET_DEST (pat);
9843 int regno = REGNO (reg);
9844 rtx src = SET_SRC (pat);
9846 /* Check if we have valid information on the contents of this
9847 register in the mode of REG. */
9848 /* ??? We don't know how zero / sign extension is handled, hence
9849 we can't go from a narrower to a wider mode. */
9850 if (reg_set_luid[regno] > last_label_luid
9851 && (GET_MODE_SIZE (GET_MODE (reg))
9852 <= GET_MODE_SIZE (reg_mode[regno]))
9853 && GET_CODE (reg_offset[regno]) == CONST_INT)
9855 /* Try to transform (set (REGX) (CONST_INT A))
9857 (set (REGX) (CONST_INT B))
9859 (set (REGX) (CONST_INT A))
9861 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9863 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9866 rtx new_src = GEN_INT (INTVAL (src)
9867 - INTVAL (reg_offset[regno]));
9868 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9869 use (set (reg) (reg)) instead.
9870 We don't delete this insn, nor do we convert it into a
9871 note, to avoid losing register notes or the return
9872 value flag. jump2 already knowns how to get rid of
9874 if (new_src == const0_rtx)
9875 success = validate_change (insn, &SET_SRC (pat), reg, 0);
9876 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9877 && have_add2_insn (GET_MODE (reg)))
9878 success = validate_change (insn, &PATTERN (insn),
9879 gen_add2_insn (reg, new_src), 0);
9880 reg_set_luid[regno] = move2add_luid;
9881 reg_mode[regno] = GET_MODE (reg);
9882 reg_offset[regno] = src;
9886 /* Try to transform (set (REGX) (REGY))
9887 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9890 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9893 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9895 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9896 else if (GET_CODE (src) == REG
9897 && reg_base_reg[regno] == REGNO (src)
9898 && reg_set_luid[regno] > reg_set_luid[REGNO (src)])
9900 rtx next = next_nonnote_insn (insn);
9903 set = single_set (next);
9906 && SET_DEST (set) == reg
9907 && GET_CODE (SET_SRC (set)) == PLUS
9908 && XEXP (SET_SRC (set), 0) == reg
9909 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9911 rtx src3 = XEXP (SET_SRC (set), 1);
9912 rtx new_src = GEN_INT (INTVAL (src3)
9913 - INTVAL (reg_offset[regno]));
9916 if (new_src == const0_rtx)
9917 /* See above why we create (set (reg) (reg)) here. */
9919 = validate_change (next, &SET_SRC (set), reg, 0);
9920 else if ((rtx_cost (new_src, PLUS)
9921 < 2 + rtx_cost (src3, SET))
9922 && have_add2_insn (GET_MODE (reg)))
9924 = validate_change (next, &PATTERN (next),
9925 gen_add2_insn (reg, new_src), 0);
9928 /* INSN might be the first insn in a basic block
9929 if the preceding insn is a conditional jump
9930 or a possible-throwing call. */
9931 PUT_CODE (insn, NOTE);
9932 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9933 NOTE_SOURCE_FILE (insn) = 0;
9936 reg_set_luid[regno] = move2add_luid;
9937 reg_mode[regno] = GET_MODE (reg);
9938 reg_offset[regno] = src3;
9945 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9947 if (REG_NOTE_KIND (note) == REG_INC
9948 && GET_CODE (XEXP (note, 0)) == REG)
9950 /* Indicate that this register has been recently written to,
9951 but the exact contents are not available. */
9952 int regno = REGNO (XEXP (note, 0));
9953 if (regno < FIRST_PSEUDO_REGISTER)
9955 reg_set_luid[regno] = move2add_luid;
9956 reg_offset[regno] = note;
9960 note_stores (PATTERN (insn), move2add_note_store);
9961 /* If this is a CALL_INSN, all call used registers are stored with
9963 if (GET_CODE (insn) == CALL_INSN)
9965 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
9967 if (call_used_regs[i])
9969 reg_set_luid[i] = move2add_luid;
9970 reg_offset[i] = insn; /* Invalidate contents. */
9977 /* SET is a SET or CLOBBER that sets DST.
9978 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9979 Called from reload_cse_move2add via note_stores. */
9981 move2add_note_store (dst, set)
9987 enum machine_mode mode = GET_MODE (dst);
9988 if (GET_CODE (dst) == SUBREG)
9990 regno = SUBREG_WORD (dst);
9991 dst = SUBREG_REG (dst);
9993 if (GET_CODE (dst) != REG)
9996 regno += REGNO (dst);
9998 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET)
10000 rtx src = SET_SRC (set);
10002 reg_mode[regno] = mode;
10003 switch (GET_CODE (src))
10007 rtx src0 = XEXP (src, 0);
10008 if (GET_CODE (src0) == REG)
10010 if (REGNO (src0) != regno
10011 || reg_offset[regno] != const0_rtx)
10013 reg_base_reg[regno] = REGNO (src0);
10014 reg_set_luid[regno] = move2add_luid;
10016 reg_offset[regno] = XEXP (src, 1);
10019 reg_set_luid[regno] = move2add_luid;
10020 reg_offset[regno] = set; /* Invalidate contents. */
10025 reg_base_reg[regno] = REGNO (SET_SRC (set));
10026 reg_offset[regno] = const0_rtx;
10027 reg_set_luid[regno] = move2add_luid;
10031 reg_base_reg[regno] = -1;
10032 reg_offset[regno] = SET_SRC (set);
10033 reg_set_luid[regno] = move2add_luid;
10039 for (i = regno + HARD_REGNO_NREGS (regno, mode) - 1; i >= regno; i--)
10041 /* Indicate that this register has been recently written to,
10042 but the exact contents are not available. */
10043 reg_set_luid[i] = move2add_luid;
10044 reg_offset[i] = dst;
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