1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
25 #include "insn-config.h"
26 #include "insn-flags.h"
27 #include "insn-codes.h"
31 #include "hard-reg-set.h"
34 #include "basic-block.h"
37 /* This file contains the reload pass of the compiler, which is
38 run after register allocation has been done. It checks that
39 each insn is valid (operands required to be in registers really
40 are in registers of the proper class) and fixes up invalid ones
41 by copying values temporarily into registers for the insns
44 The results of register allocation are described by the vector
45 reg_renumber; the insns still contain pseudo regs, but reg_renumber
46 can be used to find which hard reg, if any, a pseudo reg is in.
48 The technique we always use is to free up a few hard regs that are
49 called ``reload regs'', and for each place where a pseudo reg
50 must be in a hard reg, copy it temporarily into one of the reload regs.
52 All the pseudos that were formerly allocated to the hard regs that
53 are now in use as reload regs must be ``spilled''. This means
54 that they go to other hard regs, or to stack slots if no other
55 available hard regs can be found. Spilling can invalidate more
56 insns, requiring additional need for reloads, so we must keep checking
57 until the process stabilizes.
59 For machines with different classes of registers, we must keep track
60 of the register class needed for each reload, and make sure that
61 we allocate enough reload registers of each class.
63 The file reload.c contains the code that checks one insn for
64 validity and reports the reloads that it needs. This file
65 is in charge of scanning the entire rtl code, accumulating the
66 reload needs, spilling, assigning reload registers to use for
67 fixing up each insn, and generating the new insns to copy values
68 into the reload registers. */
70 /* During reload_as_needed, element N contains a REG rtx for the hard reg
71 into which pseudo reg N has been reloaded (perhaps for a previous insn). */
72 static rtx *reg_last_reload_reg;
74 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
75 for an output reload that stores into reg N. */
76 static char *reg_has_output_reload;
78 /* Indicates which hard regs are reload-registers for an output reload
79 in the current insn. */
80 static HARD_REG_SET reg_is_output_reload;
82 /* Element N is the constant value to which pseudo reg N is equivalent,
83 or zero if pseudo reg N is not equivalent to a constant.
84 find_reloads looks at this in order to replace pseudo reg N
85 with the constant it stands for. */
86 rtx *reg_equiv_constant;
88 /* Element N is a memory location to which pseudo reg N is equivalent,
89 prior to any register elimination (such as frame pointer to stack
90 pointer). Depending on whether or not it is a valid address, this value
91 is transferred to either reg_equiv_address or reg_equiv_mem. */
92 rtx *reg_equiv_memory_loc;
94 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
95 This is used when the address is not valid as a memory address
96 (because its displacement is too big for the machine.) */
97 rtx *reg_equiv_address;
99 /* Element N is the memory slot to which pseudo reg N is equivalent,
100 or zero if pseudo reg N is not equivalent to a memory slot. */
103 /* Widest width in which each pseudo reg is referred to (via subreg). */
104 static int *reg_max_ref_width;
106 /* Element N is the insn that initialized reg N from its equivalent
107 constant or memory slot. */
108 static rtx *reg_equiv_init;
110 /* During reload_as_needed, element N contains the last pseudo regno
111 reloaded into the Nth reload register. This vector is in parallel
112 with spill_regs. If that pseudo reg occupied more than one register,
113 reg_reloaded_contents points to that pseudo for each spill register in
114 use; all of these must remain set for an inheritance to occur. */
115 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
117 /* During reload_as_needed, element N contains the insn for which
118 the Nth reload register was last used. This vector is in parallel
119 with spill_regs, and its contents are significant only when
120 reg_reloaded_contents is significant. */
121 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
123 /* Number of spill-regs so far; number of valid elements of spill_regs. */
126 /* In parallel with spill_regs, contains REG rtx's for those regs.
127 Holds the last rtx used for any given reg, or 0 if it has never
128 been used for spilling yet. This rtx is reused, provided it has
130 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
132 /* In parallel with spill_regs, contains nonzero for a spill reg
133 that was stored after the last time it was used.
134 The precise value is the insn generated to do the store. */
135 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
137 /* This table is the inverse mapping of spill_regs:
138 indexed by hard reg number,
139 it contains the position of that reg in spill_regs,
140 or -1 for something that is not in spill_regs. */
141 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
143 /* This reg set indicates registers that may not be used for retrying global
144 allocation. The registers that may not be used include all spill registers
145 and the frame pointer (if we are using one). */
146 HARD_REG_SET forbidden_regs;
148 /* This reg set indicates registers that are not good for spill registers.
149 They will not be used to complete groups of spill registers. This includes
150 all fixed registers, registers that may be eliminated, and registers
151 explicitly used in the rtl.
153 (spill_reg_order prevents these registers from being used to start a
155 static HARD_REG_SET bad_spill_regs;
157 /* Describes order of use of registers for reloading
158 of spilled pseudo-registers. `spills' is the number of
159 elements that are actually valid; new ones are added at the end. */
160 static short spill_regs[FIRST_PSEUDO_REGISTER];
162 /* Describes order of preference for putting regs into spill_regs.
163 Contains the numbers of all the hard regs, in order most preferred first.
164 This order is different for each function.
165 It is set up by order_regs_for_reload.
166 Empty elements at the end contain -1. */
167 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
169 /* 1 for a hard register that appears explicitly in the rtl
170 (for example, function value registers, special registers
171 used by insns, structure value pointer registers). */
172 static char regs_explicitly_used[FIRST_PSEUDO_REGISTER];
174 /* Indicates if a register was counted against the need for
175 groups. 0 means it can count against max_nongroup instead. */
176 static HARD_REG_SET counted_for_groups;
178 /* Indicates if a register was counted against the need for
179 non-groups. 0 means it can become part of a new group.
180 During choose_reload_regs, 1 here means don't use this reg
181 as part of a group, even if it seems to be otherwise ok. */
182 static HARD_REG_SET counted_for_nongroups;
184 /* Nonzero if indirect addressing is supported on the machine; this means
185 that spilling (REG n) does not require reloading it into a register in
186 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
187 value indicates the level of indirect addressing supported, e.g., two
188 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
191 static char spill_indirect_levels;
193 /* Nonzero if indirect addressing is supported when the innermost MEM is
194 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
195 which these are valid is the same as spill_indirect_levels, above. */
197 char indirect_symref_ok;
199 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
201 char double_reg_address_ok;
203 /* Record the stack slot for each spilled hard register. */
205 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
207 /* Width allocated so far for that stack slot. */
209 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
211 /* Indexed by register class and basic block number, nonzero if there is
212 any need for a spill register of that class in that basic block.
213 The pointer is 0 if we did stupid allocation and don't know
214 the structure of basic blocks. */
216 char *basic_block_needs[N_REG_CLASSES];
218 /* First uid used by insns created by reload in this function.
219 Used in find_equiv_reg. */
220 int reload_first_uid;
222 /* Flag set by local-alloc or global-alloc if anything is live in
223 a call-clobbered reg across calls. */
225 int caller_save_needed;
227 /* Set to 1 while reload_as_needed is operating.
228 Required by some machines to handle any generated moves differently. */
230 int reload_in_progress = 0;
232 /* These arrays record the insn_code of insns that may be needed to
233 perform input and output reloads of special objects. They provide a
234 place to pass a scratch register. */
236 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
237 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
239 /* This obstack is used for allocation of rtl during register elimination.
240 The allocated storage can be freed once find_reloads has processed the
243 struct obstack reload_obstack;
244 char *reload_firstobj;
246 #define obstack_chunk_alloc xmalloc
247 #define obstack_chunk_free free
249 /* List of labels that must never be deleted. */
250 extern rtx forced_labels;
252 /* This structure is used to record information about register eliminations.
253 Each array entry describes one possible way of eliminating a register
254 in favor of another. If there is more than one way of eliminating a
255 particular register, the most preferred should be specified first. */
257 static struct elim_table
259 int from; /* Register number to be eliminated. */
260 int to; /* Register number used as replacement. */
261 int initial_offset; /* Initial difference between values. */
262 int can_eliminate; /* Non-zero if this elimination can be done. */
263 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
264 insns made by reload. */
265 int offset; /* Current offset between the two regs. */
266 int max_offset; /* Maximum offset between the two regs. */
267 int previous_offset; /* Offset at end of previous insn. */
268 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
269 rtx from_rtx; /* REG rtx for the register to be eliminated.
270 We cannot simply compare the number since
271 we might then spuriously replace a hard
272 register corresponding to a pseudo
273 assigned to the reg to be eliminated. */
274 rtx to_rtx; /* REG rtx for the replacement. */
277 /* If a set of eliminable registers was specified, define the table from it.
278 Otherwise, default to the normal case of the frame pointer being
279 replaced by the stack pointer. */
281 #ifdef ELIMINABLE_REGS
284 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
287 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0])
289 /* Record the number of pending eliminations that have an offset not equal
290 to their initial offset. If non-zero, we use a new copy of each
291 replacement result in any insns encountered. */
292 static int num_not_at_initial_offset;
294 /* Count the number of registers that we may be able to eliminate. */
295 static int num_eliminable;
297 /* For each label, we record the offset of each elimination. If we reach
298 a label by more than one path and an offset differs, we cannot do the
299 elimination. This information is indexed by the number of the label.
300 The first table is an array of flags that records whether we have yet
301 encountered a label and the second table is an array of arrays, one
302 entry in the latter array for each elimination. */
304 static char *offsets_known_at;
305 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
307 /* Number of labels in the current function. */
309 static int num_labels;
311 void mark_home_live ();
312 static void count_possible_groups ();
313 static int possible_group_p ();
314 static void scan_paradoxical_subregs ();
315 static void reload_as_needed ();
316 static int modes_equiv_for_class_p ();
317 static void alter_reg ();
318 static void delete_dead_insn ();
319 static void spill_failure ();
320 static int new_spill_reg();
321 static void set_label_offsets ();
322 static int eliminate_regs_in_insn ();
323 static void mark_not_eliminable ();
324 static int spill_hard_reg ();
325 static void choose_reload_regs ();
326 static void emit_reload_insns ();
327 static void delete_output_reload ();
328 static void forget_old_reloads_1 ();
329 static void order_regs_for_reload ();
330 static rtx inc_for_reload ();
331 static int constraint_accepts_reg_p ();
332 static int count_occurrences ();
334 extern void remove_death ();
335 extern rtx adj_offsettable_operand ();
336 extern rtx form_sum ();
343 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
344 Set spill_indirect_levels to the number of levels such addressing is
345 permitted, zero if it is not permitted at all. */
348 = gen_rtx (MEM, Pmode,
349 gen_rtx (PLUS, Pmode,
350 gen_rtx (REG, Pmode, LAST_VIRTUAL_REGISTER + 1),
352 spill_indirect_levels = 0;
354 while (memory_address_p (QImode, tem))
356 spill_indirect_levels++;
357 tem = gen_rtx (MEM, Pmode, tem);
360 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
362 tem = gen_rtx (MEM, Pmode, gen_rtx (SYMBOL_REF, Pmode, "foo"));
363 indirect_symref_ok = memory_address_p (QImode, tem);
365 /* See if reg+reg is a valid (and offsettable) address. */
367 tem = gen_rtx (PLUS, Pmode,
368 gen_rtx (REG, Pmode, FRAME_POINTER_REGNUM),
369 gen_rtx (REG, Pmode, FRAME_POINTER_REGNUM));
370 /* This way, we make sure that reg+reg is an offsettable address. */
371 tem = plus_constant (tem, 4);
373 double_reg_address_ok = memory_address_p (QImode, tem);
375 /* Initialize obstack for our rtl allocation. */
376 gcc_obstack_init (&reload_obstack);
377 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
379 #ifdef HAVE_SECONDARY_RELOADS
381 /* Initialize the optabs for doing special input and output reloads. */
383 for (i = 0; i < NUM_MACHINE_MODES; i++)
384 reload_in_optab[i] = reload_out_optab[i] = CODE_FOR_nothing;
386 #ifdef HAVE_reload_inqi
387 if (HAVE_reload_inqi)
388 reload_in_optab[(int) QImode] = CODE_FOR_reload_inqi;
390 #ifdef HAVE_reload_inhi
391 if (HAVE_reload_inhi)
392 reload_in_optab[(int) HImode] = CODE_FOR_reload_inhi;
394 #ifdef HAVE_reload_insi
395 if (HAVE_reload_insi)
396 reload_in_optab[(int) SImode] = CODE_FOR_reload_insi;
398 #ifdef HAVE_reload_indi
399 if (HAVE_reload_indi)
400 reload_in_optab[(int) DImode] = CODE_FOR_reload_indi;
402 #ifdef HAVE_reload_inti
403 if (HAVE_reload_inti)
404 reload_in_optab[(int) TImode] = CODE_FOR_reload_inti;
406 #ifdef HAVE_reload_insf
407 if (HAVE_reload_insf)
408 reload_in_optab[(int) SFmode] = CODE_FOR_reload_insf;
410 #ifdef HAVE_reload_indf
411 if (HAVE_reload_indf)
412 reload_in_optab[(int) DFmode] = CODE_FOR_reload_indf;
414 #ifdef HAVE_reload_inxf
415 if (HAVE_reload_inxf)
416 reload_in_optab[(int) XFmode] = CODE_FOR_reload_inxf;
418 #ifdef HAVE_reload_intf
419 if (HAVE_reload_intf)
420 reload_in_optab[(int) TFmode] = CODE_FOR_reload_intf;
423 #ifdef HAVE_reload_outqi
424 if (HAVE_reload_outqi)
425 reload_out_optab[(int) QImode] = CODE_FOR_reload_outqi;
427 #ifdef HAVE_reload_outhi
428 if (HAVE_reload_outhi)
429 reload_out_optab[(int) HImode] = CODE_FOR_reload_outhi;
431 #ifdef HAVE_reload_outsi
432 if (HAVE_reload_outsi)
433 reload_out_optab[(int) SImode] = CODE_FOR_reload_outsi;
435 #ifdef HAVE_reload_outdi
436 if (HAVE_reload_outdi)
437 reload_out_optab[(int) DImode] = CODE_FOR_reload_outdi;
439 #ifdef HAVE_reload_outti
440 if (HAVE_reload_outti)
441 reload_out_optab[(int) TImode] = CODE_FOR_reload_outti;
443 #ifdef HAVE_reload_outsf
444 if (HAVE_reload_outsf)
445 reload_out_optab[(int) SFmode] = CODE_FOR_reload_outsf;
447 #ifdef HAVE_reload_outdf
448 if (HAVE_reload_outdf)
449 reload_out_optab[(int) DFmode] = CODE_FOR_reload_outdf;
451 #ifdef HAVE_reload_outxf
452 if (HAVE_reload_outxf)
453 reload_out_optab[(int) XFmode] = CODE_FOR_reload_outxf;
455 #ifdef HAVE_reload_outtf
456 if (HAVE_reload_outtf)
457 reload_out_optab[(int) TFmode] = CODE_FOR_reload_outtf;
460 #endif /* HAVE_SECONDARY_RELOADS */
464 /* Main entry point for the reload pass, and only entry point
467 FIRST is the first insn of the function being compiled.
469 GLOBAL nonzero means we were called from global_alloc
470 and should attempt to reallocate any pseudoregs that we
471 displace from hard regs we will use for reloads.
472 If GLOBAL is zero, we do not have enough information to do that,
473 so any pseudo reg that is spilled must go to the stack.
475 DUMPFILE is the global-reg debugging dump file stream, or 0.
476 If it is nonzero, messages are written to it to describe
477 which registers are seized as reload regs, which pseudo regs
478 are spilled from them, and where the pseudo regs are reallocated to.
480 Return value is nonzero if reload failed
481 and we must not do any more for this function. */
484 reload (first, global, dumpfile)
492 register struct elim_table *ep;
494 int something_changed;
495 int something_needs_reloads;
496 int something_needs_elimination;
497 int new_basic_block_needs;
498 enum reg_class caller_save_spill_class = NO_REGS;
499 int caller_save_group_size = 1;
501 /* Nonzero means we couldn't get enough spill regs. */
504 /* The basic block number currently being processed for INSN. */
507 /* Make sure even insns with volatile mem refs are recognizable. */
510 /* Enable find_equiv_reg to distinguish insns made by reload. */
511 reload_first_uid = get_max_uid ();
513 for (i = 0; i < N_REG_CLASSES; i++)
514 basic_block_needs[i] = 0;
516 #ifdef SECONDARY_MEMORY_NEEDED
517 /* Initialize the secondary memory table. */
518 clear_secondary_mem ();
521 /* Remember which hard regs appear explicitly
522 before we merge into `regs_ever_live' the ones in which
523 pseudo regs have been allocated. */
524 bcopy (regs_ever_live, regs_explicitly_used, sizeof regs_ever_live);
526 /* We don't have a stack slot for any spill reg yet. */
527 bzero (spill_stack_slot, sizeof spill_stack_slot);
528 bzero (spill_stack_slot_width, sizeof spill_stack_slot_width);
530 /* Initialize the save area information for caller-save, in case some
534 /* Compute which hard registers are now in use
535 as homes for pseudo registers.
536 This is done here rather than (eg) in global_alloc
537 because this point is reached even if not optimizing. */
539 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
542 /* Make sure that the last insn in the chain
543 is not something that needs reloading. */
544 emit_note (NULL_PTR, NOTE_INSN_DELETED);
546 /* Find all the pseudo registers that didn't get hard regs
547 but do have known equivalent constants or memory slots.
548 These include parameters (known equivalent to parameter slots)
549 and cse'd or loop-moved constant memory addresses.
551 Record constant equivalents in reg_equiv_constant
552 so they will be substituted by find_reloads.
553 Record memory equivalents in reg_mem_equiv so they can
554 be substituted eventually by altering the REG-rtx's. */
556 reg_equiv_constant = (rtx *) alloca (max_regno * sizeof (rtx));
557 bzero (reg_equiv_constant, max_regno * sizeof (rtx));
558 reg_equiv_memory_loc = (rtx *) alloca (max_regno * sizeof (rtx));
559 bzero (reg_equiv_memory_loc, max_regno * sizeof (rtx));
560 reg_equiv_mem = (rtx *) alloca (max_regno * sizeof (rtx));
561 bzero (reg_equiv_mem, max_regno * sizeof (rtx));
562 reg_equiv_init = (rtx *) alloca (max_regno * sizeof (rtx));
563 bzero (reg_equiv_init, max_regno * sizeof (rtx));
564 reg_equiv_address = (rtx *) alloca (max_regno * sizeof (rtx));
565 bzero (reg_equiv_address, max_regno * sizeof (rtx));
566 reg_max_ref_width = (int *) alloca (max_regno * sizeof (int));
567 bzero (reg_max_ref_width, max_regno * sizeof (int));
569 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
570 Also find all paradoxical subregs
571 and find largest such for each pseudo. */
573 for (insn = first; insn; insn = NEXT_INSN (insn))
575 rtx set = single_set (insn);
577 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
579 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
581 #ifdef LEGITIMATE_PIC_OPERAND_P
582 && (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic
583 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
587 rtx x = XEXP (note, 0);
588 i = REGNO (SET_DEST (set));
589 if (i > LAST_VIRTUAL_REGISTER)
591 if (GET_CODE (x) == MEM)
592 reg_equiv_memory_loc[i] = x;
593 else if (CONSTANT_P (x))
595 if (LEGITIMATE_CONSTANT_P (x))
596 reg_equiv_constant[i] = x;
598 reg_equiv_memory_loc[i]
599 = force_const_mem (GET_MODE (SET_DEST (set)), x);
604 /* If this register is being made equivalent to a MEM
605 and the MEM is not SET_SRC, the equivalencing insn
606 is one with the MEM as a SET_DEST and it occurs later.
607 So don't mark this insn now. */
608 if (GET_CODE (x) != MEM
609 || rtx_equal_p (SET_SRC (set), x))
610 reg_equiv_init[i] = insn;
615 /* If this insn is setting a MEM from a register equivalent to it,
616 this is the equivalencing insn. */
617 else if (set && GET_CODE (SET_DEST (set)) == MEM
618 && GET_CODE (SET_SRC (set)) == REG
619 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
620 && rtx_equal_p (SET_DEST (set),
621 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
622 reg_equiv_init[REGNO (SET_SRC (set))] = insn;
624 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
625 scan_paradoxical_subregs (PATTERN (insn));
628 /* Does this function require a frame pointer? */
630 frame_pointer_needed = (! flag_omit_frame_pointer
631 #ifdef EXIT_IGNORE_STACK
632 /* ?? If EXIT_IGNORE_STACK is set, we will not save
633 and restore sp for alloca. So we can't eliminate
634 the frame pointer in that case. At some point,
635 we should improve this by emitting the
636 sp-adjusting insns for this case. */
637 || (current_function_calls_alloca
638 && EXIT_IGNORE_STACK)
640 || FRAME_POINTER_REQUIRED);
644 /* Initialize the table of registers to eliminate. The way we do this
645 depends on how the eliminable registers were defined. */
646 #ifdef ELIMINABLE_REGS
647 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
649 ep->can_eliminate = ep->can_eliminate_previous
650 = (CAN_ELIMINATE (ep->from, ep->to)
651 && (ep->from != FRAME_POINTER_REGNUM || ! frame_pointer_needed));
654 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
655 = ! frame_pointer_needed;
658 /* Count the number of eliminable registers and build the FROM and TO
659 REG rtx's. Note that code in gen_rtx will cause, e.g.,
660 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
661 We depend on this. */
662 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
664 num_eliminable += ep->can_eliminate;
665 ep->from_rtx = gen_rtx (REG, Pmode, ep->from);
666 ep->to_rtx = gen_rtx (REG, Pmode, ep->to);
669 num_labels = max_label_num () - get_first_label_num ();
671 /* Allocate the tables used to store offset information at labels. */
672 offsets_known_at = (char *) alloca (num_labels);
674 = (int (*)[NUM_ELIMINABLE_REGS])
675 alloca (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
677 offsets_known_at -= get_first_label_num ();
678 offsets_at -= get_first_label_num ();
680 /* Alter each pseudo-reg rtx to contain its hard reg number.
681 Assign stack slots to the pseudos that lack hard regs or equivalents.
682 Do not touch virtual registers. */
684 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
687 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done here
688 because the stack size may be a part of the offset computation for
689 register elimination. */
690 assign_stack_local (BLKmode, 0, 0);
692 /* If we have some registers we think can be eliminated, scan all insns to
693 see if there is an insn that sets one of these registers to something
694 other than itself plus a constant. If so, the register cannot be
695 eliminated. Doing this scan here eliminates an extra pass through the
696 main reload loop in the most common case where register elimination
698 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
699 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
700 || GET_CODE (insn) == CALL_INSN)
701 note_stores (PATTERN (insn), mark_not_eliminable);
703 #ifndef REGISTER_CONSTRAINTS
704 /* If all the pseudo regs have hard regs,
705 except for those that are never referenced,
706 we know that no reloads are needed. */
707 /* But that is not true if there are register constraints, since
708 in that case some pseudos might be in the wrong kind of hard reg. */
710 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
711 if (reg_renumber[i] == -1 && reg_n_refs[i] != 0)
714 if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
718 /* Compute the order of preference for hard registers to spill.
719 Store them by decreasing preference in potential_reload_regs. */
721 order_regs_for_reload ();
723 /* So far, no hard regs have been spilled. */
725 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
726 spill_reg_order[i] = -1;
728 /* On most machines, we can't use any register explicitly used in the
729 rtl as a spill register. But on some, we have to. Those will have
730 taken care to keep the life of hard regs as short as possible. */
732 #ifdef SMALL_REGISTER_CLASSES
733 CLEAR_HARD_REG_SET (forbidden_regs);
735 COPY_HARD_REG_SET (forbidden_regs, bad_spill_regs);
738 /* Spill any hard regs that we know we can't eliminate. */
739 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
740 if (! ep->can_eliminate)
742 spill_hard_reg (ep->from, global, dumpfile, 1);
743 regs_ever_live[ep->from] = 1;
747 for (i = 0; i < N_REG_CLASSES; i++)
749 basic_block_needs[i] = (char *)alloca (n_basic_blocks);
750 bzero (basic_block_needs[i], n_basic_blocks);
753 /* This loop scans the entire function each go-round
754 and repeats until one repetition spills no additional hard regs. */
756 /* This flag is set when a pseudo reg is spilled,
757 to require another pass. Note that getting an additional reload
758 reg does not necessarily imply any pseudo reg was spilled;
759 sometimes we find a reload reg that no pseudo reg was allocated in. */
760 something_changed = 1;
761 /* This flag is set if there are any insns that require reloading. */
762 something_needs_reloads = 0;
763 /* This flag is set if there are any insns that require register
765 something_needs_elimination = 0;
766 while (something_changed)
770 /* For each class, number of reload regs needed in that class.
771 This is the maximum over all insns of the needs in that class
772 of the individual insn. */
773 int max_needs[N_REG_CLASSES];
774 /* For each class, size of group of consecutive regs
775 that is needed for the reloads of this class. */
776 int group_size[N_REG_CLASSES];
777 /* For each class, max number of consecutive groups needed.
778 (Each group contains group_size[CLASS] consecutive registers.) */
779 int max_groups[N_REG_CLASSES];
780 /* For each class, max number needed of regs that don't belong
781 to any of the groups. */
782 int max_nongroups[N_REG_CLASSES];
783 /* For each class, the machine mode which requires consecutive
784 groups of regs of that class.
785 If two different modes ever require groups of one class,
786 they must be the same size and equally restrictive for that class,
787 otherwise we can't handle the complexity. */
788 enum machine_mode group_mode[N_REG_CLASSES];
789 /* Record the insn where each maximum need is first found. */
790 rtx max_needs_insn[N_REG_CLASSES];
791 rtx max_groups_insn[N_REG_CLASSES];
792 rtx max_nongroups_insn[N_REG_CLASSES];
794 int starting_frame_size = get_frame_size ();
796 something_changed = 0;
797 bzero (max_needs, sizeof max_needs);
798 bzero (max_groups, sizeof max_groups);
799 bzero (max_nongroups, sizeof max_nongroups);
800 bzero (max_needs_insn, sizeof max_needs_insn);
801 bzero (max_groups_insn, sizeof max_groups_insn);
802 bzero (max_nongroups_insn, sizeof max_nongroups_insn);
803 bzero (group_size, sizeof group_size);
804 for (i = 0; i < N_REG_CLASSES; i++)
805 group_mode[i] = VOIDmode;
807 /* Keep track of which basic blocks are needing the reloads. */
810 /* Remember whether any element of basic_block_needs
811 changes from 0 to 1 in this pass. */
812 new_basic_block_needs = 0;
814 /* Reset all offsets on eliminable registers to their initial values. */
815 #ifdef ELIMINABLE_REGS
816 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
818 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
819 ep->previous_offset = ep->offset
820 = ep->max_offset = ep->initial_offset;
823 #ifdef INITIAL_FRAME_POINTER_OFFSET
824 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
826 if (!FRAME_POINTER_REQUIRED)
828 reg_eliminate[0].initial_offset = 0;
830 reg_eliminate[0].previous_offset = reg_eliminate[0].max_offset
831 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
834 num_not_at_initial_offset = 0;
836 bzero (&offsets_known_at[get_first_label_num ()], num_labels);
838 /* Set a known offset for each forced label to be at the initial offset
839 of each elimination. We do this because we assume that all
840 computed jumps occur from a location where each elimination is
841 at its initial offset. */
843 for (x = forced_labels; x; x = XEXP (x, 1))
845 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
847 /* For each pseudo register that has an equivalent location defined,
848 try to eliminate any eliminable registers (such as the frame pointer)
849 assuming initial offsets for the replacement register, which
852 If the resulting location is directly addressable, substitute
853 the MEM we just got directly for the old REG.
855 If it is not addressable but is a constant or the sum of a hard reg
856 and constant, it is probably not addressable because the constant is
857 out of range, in that case record the address; we will generate
858 hairy code to compute the address in a register each time it is
861 If the location is not addressable, but does not have one of the
862 above forms, assign a stack slot. We have to do this to avoid the
863 potential of producing lots of reloads if, e.g., a location involves
864 a pseudo that didn't get a hard register and has an equivalent memory
865 location that also involves a pseudo that didn't get a hard register.
867 Perhaps at some point we will improve reload_when_needed handling
868 so this problem goes away. But that's very hairy. */
870 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
871 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
873 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
875 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
877 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
878 else if (CONSTANT_P (XEXP (x, 0))
879 || (GET_CODE (XEXP (x, 0)) == PLUS
880 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
881 && (REGNO (XEXP (XEXP (x, 0), 0))
882 < FIRST_PSEUDO_REGISTER)
883 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
884 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
887 /* Make a new stack slot. Then indicate that something
888 changed so we go back and recompute offsets for
889 eliminable registers because the allocation of memory
890 below might change some offset. reg_equiv_{mem,address}
891 will be set up for this pseudo on the next pass around
893 reg_equiv_memory_loc[i] = 0;
894 reg_equiv_init[i] = 0;
896 something_changed = 1;
900 /* If we allocated another pseudo to the stack, redo elimination
902 if (something_changed)
905 /* If caller-saves needs a group, initialize the group to include
906 the size and mode required for caller-saves. */
908 if (caller_save_group_size > 1)
910 group_mode[(int) caller_save_spill_class] = Pmode;
911 group_size[(int) caller_save_spill_class] = caller_save_group_size;
914 /* Compute the most additional registers needed by any instruction.
915 Collect information separately for each class of regs. */
917 for (insn = first; insn; insn = NEXT_INSN (insn))
919 if (global && this_block + 1 < n_basic_blocks
920 && insn == basic_block_head[this_block+1])
923 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which
924 might include REG_LABEL), we need to see what effects this
925 has on the known offsets at labels. */
927 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
928 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
929 && REG_NOTES (insn) != 0))
930 set_label_offsets (insn, insn, 0);
932 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
934 /* Nonzero means don't use a reload reg that overlaps
935 the place where a function value can be returned. */
936 rtx avoid_return_reg = 0;
938 rtx old_body = PATTERN (insn);
939 int old_code = INSN_CODE (insn);
940 rtx old_notes = REG_NOTES (insn);
941 int did_elimination = 0;
943 /* Initially, count RELOAD_OTHER reloads.
944 Later, merge in the other kinds. */
945 int insn_needs[N_REG_CLASSES];
946 int insn_groups[N_REG_CLASSES];
947 int insn_total_groups = 0;
949 /* Count RELOAD_FOR_INPUT_RELOAD_ADDRESS reloads. */
950 int insn_needs_for_inputs[N_REG_CLASSES];
951 int insn_groups_for_inputs[N_REG_CLASSES];
952 int insn_total_groups_for_inputs = 0;
954 /* Count RELOAD_FOR_OUTPUT_RELOAD_ADDRESS reloads. */
955 int insn_needs_for_outputs[N_REG_CLASSES];
956 int insn_groups_for_outputs[N_REG_CLASSES];
957 int insn_total_groups_for_outputs = 0;
959 /* Count RELOAD_FOR_OPERAND_ADDRESS reloads. */
960 int insn_needs_for_operands[N_REG_CLASSES];
961 int insn_groups_for_operands[N_REG_CLASSES];
962 int insn_total_groups_for_operands = 0;
964 #if 0 /* This wouldn't work nowadays, since optimize_bit_field
965 looks for non-strict memory addresses. */
966 /* Optimization: a bit-field instruction whose field
967 happens to be a byte or halfword in memory
968 can be changed to a move instruction. */
970 if (GET_CODE (PATTERN (insn)) == SET)
972 rtx dest = SET_DEST (PATTERN (insn));
973 rtx src = SET_SRC (PATTERN (insn));
975 if (GET_CODE (dest) == ZERO_EXTRACT
976 || GET_CODE (dest) == SIGN_EXTRACT)
977 optimize_bit_field (PATTERN (insn), insn, reg_equiv_mem);
978 if (GET_CODE (src) == ZERO_EXTRACT
979 || GET_CODE (src) == SIGN_EXTRACT)
980 optimize_bit_field (PATTERN (insn), insn, reg_equiv_mem);
984 /* If needed, eliminate any eliminable registers. */
986 did_elimination = eliminate_regs_in_insn (insn, 0);
988 #ifdef SMALL_REGISTER_CLASSES
989 /* Set avoid_return_reg if this is an insn
990 that might use the value of a function call. */
991 if (GET_CODE (insn) == CALL_INSN)
993 if (GET_CODE (PATTERN (insn)) == SET)
994 after_call = SET_DEST (PATTERN (insn));
995 else if (GET_CODE (PATTERN (insn)) == PARALLEL
996 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
997 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
1001 else if (after_call != 0
1002 && !(GET_CODE (PATTERN (insn)) == SET
1003 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
1005 if (reg_mentioned_p (after_call, PATTERN (insn)))
1006 avoid_return_reg = after_call;
1009 #endif /* SMALL_REGISTER_CLASSES */
1011 /* Analyze the instruction. */
1012 find_reloads (insn, 0, spill_indirect_levels, global,
1015 /* Remember for later shortcuts which insns had any reloads or
1016 register eliminations.
1018 One might think that it would be worthwhile to mark insns
1019 that need register replacements but not reloads, but this is
1020 not safe because find_reloads may do some manipulation of
1021 the insn (such as swapping commutative operands), which would
1022 be lost when we restore the old pattern after register
1023 replacement. So the actions of find_reloads must be redone in
1024 subsequent passes or in reload_as_needed.
1026 However, it is safe to mark insns that need reloads
1027 but not register replacement. */
1029 PUT_MODE (insn, (did_elimination ? QImode
1030 : n_reloads ? HImode
1033 /* Discard any register replacements done. */
1034 if (did_elimination)
1036 obstack_free (&reload_obstack, reload_firstobj);
1037 PATTERN (insn) = old_body;
1038 INSN_CODE (insn) = old_code;
1039 REG_NOTES (insn) = old_notes;
1040 something_needs_elimination = 1;
1043 /* If this insn has no reloads, we need not do anything except
1044 in the case of a CALL_INSN when we have caller-saves and
1045 caller-save needs reloads. */
1048 && ! (GET_CODE (insn) == CALL_INSN
1049 && caller_save_spill_class != NO_REGS))
1052 something_needs_reloads = 1;
1054 for (i = 0; i < N_REG_CLASSES; i++)
1056 insn_needs[i] = 0, insn_groups[i] = 0;
1057 insn_needs_for_inputs[i] = 0, insn_groups_for_inputs[i] = 0;
1058 insn_needs_for_outputs[i] = 0, insn_groups_for_outputs[i] = 0;
1059 insn_needs_for_operands[i] = 0, insn_groups_for_operands[i] = 0;
1062 /* Count each reload once in every class
1063 containing the reload's own class. */
1065 for (i = 0; i < n_reloads; i++)
1067 register enum reg_class *p;
1068 enum reg_class class = reload_reg_class[i];
1070 enum machine_mode mode;
1073 int *this_total_groups;
1075 /* Don't count the dummy reloads, for which one of the
1076 regs mentioned in the insn can be used for reloading.
1077 Don't count optional reloads.
1078 Don't count reloads that got combined with others. */
1079 if (reload_reg_rtx[i] != 0
1080 || reload_optional[i] != 0
1081 || (reload_out[i] == 0 && reload_in[i] == 0
1082 && ! reload_secondary_p[i]))
1085 /* Show that a reload register of this class is needed
1086 in this basic block. We do not use insn_needs and
1087 insn_groups because they are overly conservative for
1089 if (global && ! basic_block_needs[(int) class][this_block])
1091 basic_block_needs[(int) class][this_block] = 1;
1092 new_basic_block_needs = 1;
1095 /* Decide which time-of-use to count this reload for. */
1096 switch (reload_when_needed[i])
1099 case RELOAD_FOR_OUTPUT:
1100 case RELOAD_FOR_INPUT:
1101 this_needs = insn_needs;
1102 this_groups = insn_groups;
1103 this_total_groups = &insn_total_groups;
1106 case RELOAD_FOR_INPUT_RELOAD_ADDRESS:
1107 this_needs = insn_needs_for_inputs;
1108 this_groups = insn_groups_for_inputs;
1109 this_total_groups = &insn_total_groups_for_inputs;
1112 case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS:
1113 this_needs = insn_needs_for_outputs;
1114 this_groups = insn_groups_for_outputs;
1115 this_total_groups = &insn_total_groups_for_outputs;
1118 case RELOAD_FOR_OPERAND_ADDRESS:
1119 this_needs = insn_needs_for_operands;
1120 this_groups = insn_groups_for_operands;
1121 this_total_groups = &insn_total_groups_for_operands;
1125 mode = reload_inmode[i];
1126 if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1127 mode = reload_outmode[i];
1128 size = CLASS_MAX_NREGS (class, mode);
1131 enum machine_mode other_mode, allocate_mode;
1133 /* Count number of groups needed separately from
1134 number of individual regs needed. */
1135 this_groups[(int) class]++;
1136 p = reg_class_superclasses[(int) class];
1137 while (*p != LIM_REG_CLASSES)
1138 this_groups[(int) *p++]++;
1139 (*this_total_groups)++;
1141 /* Record size and mode of a group of this class. */
1142 /* If more than one size group is needed,
1143 make all groups the largest needed size. */
1144 if (group_size[(int) class] < size)
1146 other_mode = group_mode[(int) class];
1147 allocate_mode = mode;
1149 group_size[(int) class] = size;
1150 group_mode[(int) class] = mode;
1155 allocate_mode = group_mode[(int) class];
1158 /* Crash if two dissimilar machine modes both need
1159 groups of consecutive regs of the same class. */
1161 if (other_mode != VOIDmode
1162 && other_mode != allocate_mode
1163 && ! modes_equiv_for_class_p (allocate_mode,
1170 this_needs[(int) class] += 1;
1171 p = reg_class_superclasses[(int) class];
1172 while (*p != LIM_REG_CLASSES)
1173 this_needs[(int) *p++] += 1;
1179 /* All reloads have been counted for this insn;
1180 now merge the various times of use.
1181 This sets insn_needs, etc., to the maximum total number
1182 of registers needed at any point in this insn. */
1184 for (i = 0; i < N_REG_CLASSES; i++)
1187 this_max = insn_needs_for_inputs[i];
1188 if (insn_needs_for_outputs[i] > this_max)
1189 this_max = insn_needs_for_outputs[i];
1190 if (insn_needs_for_operands[i] > this_max)
1191 this_max = insn_needs_for_operands[i];
1192 insn_needs[i] += this_max;
1193 this_max = insn_groups_for_inputs[i];
1194 if (insn_groups_for_outputs[i] > this_max)
1195 this_max = insn_groups_for_outputs[i];
1196 if (insn_groups_for_operands[i] > this_max)
1197 this_max = insn_groups_for_operands[i];
1198 insn_groups[i] += this_max;
1201 insn_total_groups += MAX (insn_total_groups_for_inputs,
1202 MAX (insn_total_groups_for_outputs,
1203 insn_total_groups_for_operands));
1205 /* If this is a CALL_INSN and caller-saves will need
1206 a spill register, act as if the spill register is
1207 needed for this insn. However, the spill register
1208 can be used by any reload of this insn, so we only
1209 need do something if no need for that class has
1212 The assumption that every CALL_INSN will trigger a
1213 caller-save is highly conservative, however, the number
1214 of cases where caller-saves will need a spill register but
1215 a block containing a CALL_INSN won't need a spill register
1216 of that class should be quite rare.
1218 If a group is needed, the size and mode of the group will
1219 have been set up at the beginning of this loop. */
1221 if (GET_CODE (insn) == CALL_INSN
1222 && caller_save_spill_class != NO_REGS)
1224 int *caller_save_needs
1225 = (caller_save_group_size > 1 ? insn_groups : insn_needs);
1227 if (caller_save_needs[(int) caller_save_spill_class] == 0)
1229 register enum reg_class *p
1230 = reg_class_superclasses[(int) caller_save_spill_class];
1232 caller_save_needs[(int) caller_save_spill_class]++;
1234 while (*p != LIM_REG_CLASSES)
1235 caller_save_needs[(int) *p++] += 1;
1238 if (caller_save_group_size > 1)
1239 insn_total_groups = MAX (insn_total_groups, 1);
1242 /* Show that this basic block will need a register of
1246 && ! (basic_block_needs[(int) caller_save_spill_class]
1249 basic_block_needs[(int) caller_save_spill_class]
1251 new_basic_block_needs = 1;
1255 #ifdef SMALL_REGISTER_CLASSES
1256 /* If this insn stores the value of a function call,
1257 and that value is in a register that has been spilled,
1258 and if the insn needs a reload in a class
1259 that might use that register as the reload register,
1260 then add add an extra need in that class.
1261 This makes sure we have a register available that does
1262 not overlap the return value. */
1263 if (avoid_return_reg)
1265 int regno = REGNO (avoid_return_reg);
1267 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
1270 for (r = regno; r < regno + nregs; r++)
1271 if (spill_reg_order[r] >= 0)
1272 for (i = 0; i < N_REG_CLASSES; i++)
1273 if (TEST_HARD_REG_BIT (reg_class_contents[i], r))
1275 if (insn_needs[i] > 0)
1277 if (insn_groups[i] > 0
1284 #endif /* SMALL_REGISTER_CLASSES */
1286 /* For each class, collect maximum need of any insn. */
1288 for (i = 0; i < N_REG_CLASSES; i++)
1290 if (max_needs[i] < insn_needs[i])
1292 max_needs[i] = insn_needs[i];
1293 max_needs_insn[i] = insn;
1295 if (max_groups[i] < insn_groups[i])
1297 max_groups[i] = insn_groups[i];
1298 max_groups_insn[i] = insn;
1300 if (insn_total_groups > 0)
1301 if (max_nongroups[i] < insn_needs[i])
1303 max_nongroups[i] = insn_needs[i];
1304 max_nongroups_insn[i] = insn;
1308 /* Note that there is a continue statement above. */
1311 /* If we allocated any new memory locations, make another pass
1312 since it might have changed elimination offsets. */
1313 if (starting_frame_size != get_frame_size ())
1314 something_changed = 1;
1316 /* If we have caller-saves, set up the save areas and see if caller-save
1317 will need a spill register. */
1319 if (caller_save_needed
1320 && ! setup_save_areas (&something_changed)
1321 && caller_save_spill_class == NO_REGS)
1323 /* The class we will need depends on whether the machine
1324 supports the sum of two registers for an address; see
1325 find_address_reloads for details. */
1327 caller_save_spill_class
1328 = double_reg_address_ok ? INDEX_REG_CLASS : BASE_REG_CLASS;
1329 caller_save_group_size
1330 = CLASS_MAX_NREGS (caller_save_spill_class, Pmode);
1331 something_changed = 1;
1334 /* Now deduct from the needs for the registers already
1335 available (already spilled). */
1337 CLEAR_HARD_REG_SET (counted_for_groups);
1338 CLEAR_HARD_REG_SET (counted_for_nongroups);
1340 /* First find all regs alone in their class
1341 and count them (if desired) for non-groups.
1342 We would be screwed if a group took the only reg in a class
1343 for which a non-group reload is needed.
1344 (Note there is still a bug; if a class has 2 regs,
1345 both could be stolen by groups and we would lose the same way.
1346 With luck, no machine will need a nongroup in a 2-reg class.) */
1348 for (i = 0; i < n_spills; i++)
1350 register enum reg_class *p;
1351 class = (int) REGNO_REG_CLASS (spill_regs[i]);
1353 if (reg_class_size[class] == 1 && max_nongroups[class] > 0)
1356 p = reg_class_superclasses[class];
1357 while (*p != LIM_REG_CLASSES)
1358 max_needs[(int) *p++]--;
1360 SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]);
1361 max_nongroups[class]--;
1362 p = reg_class_superclasses[class];
1363 while (*p != LIM_REG_CLASSES)
1365 if (max_nongroups[(int) *p] > 0)
1366 SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]);
1367 max_nongroups[(int) *p++]--;
1372 /* Now find all consecutive groups of spilled registers
1373 and mark each group off against the need for such groups.
1374 But don't count them against ordinary need, yet. */
1376 count_possible_groups (group_size, group_mode, max_groups);
1378 /* Now count all spill regs against the individual need,
1379 This includes those counted above for groups,
1380 but not those previously counted for nongroups.
1382 Those that weren't counted_for_groups can also count against
1383 the not-in-group need. */
1385 for (i = 0; i < n_spills; i++)
1387 register enum reg_class *p;
1388 class = (int) REGNO_REG_CLASS (spill_regs[i]);
1390 /* Those counted at the beginning shouldn't be counted twice. */
1391 if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
1394 p = reg_class_superclasses[class];
1395 while (*p != LIM_REG_CLASSES)
1396 max_needs[(int) *p++]--;
1398 if (! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[i]))
1400 if (max_nongroups[class] > 0)
1401 SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]);
1402 max_nongroups[class]--;
1403 p = reg_class_superclasses[class];
1404 while (*p != LIM_REG_CLASSES)
1406 if (max_nongroups[(int) *p] > 0)
1407 SET_HARD_REG_BIT (counted_for_nongroups,
1409 max_nongroups[(int) *p++]--;
1415 /* See if anything that happened changes which eliminations are valid.
1416 For example, on the Sparc, whether or not the frame pointer can
1417 be eliminated can depend on what registers have been used. We need
1418 not check some conditions again (such as flag_omit_frame_pointer)
1419 since they can't have changed. */
1421 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1422 if ((ep->from == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
1423 #ifdef ELIMINABLE_REGS
1424 || ! CAN_ELIMINATE (ep->from, ep->to)
1427 ep->can_eliminate = 0;
1429 /* Look for the case where we have discovered that we can't replace
1430 register A with register B and that means that we will now be
1431 trying to replace register A with register C. This means we can
1432 no longer replace register C with register B and we need to disable
1433 such an elimination, if it exists. This occurs often with A == ap,
1434 B == sp, and C == fp. */
1436 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1438 struct elim_table *op;
1439 register int new_to = -1;
1441 if (! ep->can_eliminate && ep->can_eliminate_previous)
1443 /* Find the current elimination for ep->from, if there is a
1445 for (op = reg_eliminate;
1446 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1447 if (op->from == ep->from && op->can_eliminate)
1453 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
1455 for (op = reg_eliminate;
1456 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1457 if (op->from == new_to && op->to == ep->to)
1458 op->can_eliminate = 0;
1462 /* See if any registers that we thought we could eliminate the previous
1463 time are no longer eliminable. If so, something has changed and we
1464 must spill the register. Also, recompute the number of eliminable
1465 registers and see if the frame pointer is needed; it is if there is
1466 no elimination of the frame pointer that we can perform. */
1468 frame_pointer_needed = 1;
1469 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1471 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM)
1472 frame_pointer_needed = 0;
1474 if (! ep->can_eliminate && ep->can_eliminate_previous)
1476 ep->can_eliminate_previous = 0;
1477 spill_hard_reg (ep->from, global, dumpfile, 1);
1478 regs_ever_live[ep->from] = 1;
1479 something_changed = 1;
1484 /* If all needs are met, we win. */
1486 for (i = 0; i < N_REG_CLASSES; i++)
1487 if (max_needs[i] > 0 || max_groups[i] > 0 || max_nongroups[i] > 0)
1489 if (i == N_REG_CLASSES && !new_basic_block_needs && ! something_changed)
1492 /* Not all needs are met; must spill more hard regs. */
1494 /* If any element of basic_block_needs changed from 0 to 1,
1495 re-spill all the regs already spilled. This may spill
1496 additional pseudos that didn't spill before. */
1498 if (new_basic_block_needs)
1499 for (i = 0; i < n_spills; i++)
1501 |= spill_hard_reg (spill_regs[i], global, dumpfile, 0);
1503 /* Now find more reload regs to satisfy the remaining need
1504 Do it by ascending class number, since otherwise a reg
1505 might be spilled for a big class and might fail to count
1506 for a smaller class even though it belongs to that class.
1508 Count spilled regs in `spills', and add entries to
1509 `spill_regs' and `spill_reg_order'.
1511 ??? Note there is a problem here.
1512 When there is a need for a group in a high-numbered class,
1513 and also need for non-group regs that come from a lower class,
1514 the non-group regs are chosen first. If there aren't many regs,
1515 they might leave no room for a group.
1517 This was happening on the 386. To fix it, we added the code
1518 that calls possible_group_p, so that the lower class won't
1519 break up the last possible group.
1521 Really fixing the problem would require changes above
1522 in counting the regs already spilled, and in choose_reload_regs.
1523 It might be hard to avoid introducing bugs there. */
1525 for (class = 0; class < N_REG_CLASSES; class++)
1527 /* First get the groups of registers.
1528 If we got single registers first, we might fragment
1530 while (max_groups[class] > 0)
1532 /* If any single spilled regs happen to form groups,
1533 count them now. Maybe we don't really need
1534 to spill another group. */
1535 count_possible_groups (group_size, group_mode, max_groups);
1537 /* Groups of size 2 (the only groups used on most machines)
1538 are treated specially. */
1539 if (group_size[class] == 2)
1541 /* First, look for a register that will complete a group. */
1542 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1544 int j = potential_reload_regs[i];
1546 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1548 ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1549 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1550 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1551 && HARD_REGNO_MODE_OK (other, group_mode[class])
1552 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1554 /* We don't want one part of another group.
1555 We could get "two groups" that overlap! */
1556 && ! TEST_HARD_REG_BIT (counted_for_groups, other))
1558 (j < FIRST_PSEUDO_REGISTER - 1
1559 && (other = j + 1, spill_reg_order[other] >= 0)
1560 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1561 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1562 && HARD_REGNO_MODE_OK (j, group_mode[class])
1563 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1565 && ! TEST_HARD_REG_BIT (counted_for_groups,
1568 register enum reg_class *p;
1570 /* We have found one that will complete a group,
1571 so count off one group as provided. */
1572 max_groups[class]--;
1573 p = reg_class_superclasses[class];
1574 while (*p != LIM_REG_CLASSES)
1575 max_groups[(int) *p++]--;
1577 /* Indicate both these regs are part of a group. */
1578 SET_HARD_REG_BIT (counted_for_groups, j);
1579 SET_HARD_REG_BIT (counted_for_groups, other);
1583 /* We can't complete a group, so start one. */
1584 if (i == FIRST_PSEUDO_REGISTER)
1585 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1587 int j = potential_reload_regs[i];
1588 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1589 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1590 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1591 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1592 && HARD_REGNO_MODE_OK (j, group_mode[class])
1593 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1598 /* I should be the index in potential_reload_regs
1599 of the new reload reg we have found. */
1601 if (i >= FIRST_PSEUDO_REGISTER)
1603 /* There are no groups left to spill. */
1604 spill_failure (max_groups_insn[class]);
1610 |= new_spill_reg (i, class, max_needs, NULL_PTR,
1615 /* For groups of more than 2 registers,
1616 look for a sufficient sequence of unspilled registers,
1617 and spill them all at once. */
1618 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1620 int j = potential_reload_regs[i];
1622 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1623 && HARD_REGNO_MODE_OK (j, group_mode[class]))
1625 /* Check each reg in the sequence. */
1626 for (k = 0; k < group_size[class]; k++)
1627 if (! (spill_reg_order[j + k] < 0
1628 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1629 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1631 /* We got a full sequence, so spill them all. */
1632 if (k == group_size[class])
1634 register enum reg_class *p;
1635 for (k = 0; k < group_size[class]; k++)
1638 SET_HARD_REG_BIT (counted_for_groups, j + k);
1639 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1640 if (potential_reload_regs[idx] == j + k)
1642 if (i >= FIRST_PSEUDO_REGISTER)
1644 /* There are no groups left. */
1645 spill_failure (max_groups_insn[class]);
1651 |= new_spill_reg (idx, class,
1652 max_needs, NULL_PTR,
1656 /* We have found one that will complete a group,
1657 so count off one group as provided. */
1658 max_groups[class]--;
1659 p = reg_class_superclasses[class];
1660 while (*p != LIM_REG_CLASSES)
1661 max_groups[(int) *p++]--;
1667 /* We couldn't find any registers for this reload.
1668 Abort to avoid going into an infinite loop. */
1669 if (i == FIRST_PSEUDO_REGISTER)
1674 /* Now similarly satisfy all need for single registers. */
1676 while (max_needs[class] > 0 || max_nongroups[class] > 0)
1678 /* Consider the potential reload regs that aren't
1679 yet in use as reload regs, in order of preference.
1680 Find the most preferred one that's in this class. */
1682 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1683 if (potential_reload_regs[i] >= 0
1684 && TEST_HARD_REG_BIT (reg_class_contents[class],
1685 potential_reload_regs[i])
1686 /* If this reg will not be available for groups,
1687 pick one that does not foreclose possible groups.
1688 This is a kludge, and not very general,
1689 but it should be sufficient to make the 386 work,
1690 and the problem should not occur on machines with
1692 && (max_nongroups[class] == 0
1693 || possible_group_p (potential_reload_regs[i], max_groups)))
1696 /* I should be the index in potential_reload_regs
1697 of the new reload reg we have found. */
1699 if (i >= FIRST_PSEUDO_REGISTER)
1701 /* There are no possible registers left to spill. */
1702 spill_failure (max_needs[class] > 0 ? max_needs_insn[class]
1703 : max_nongroups_insn[class]);
1709 |= new_spill_reg (i, class, max_needs, max_nongroups,
1715 /* If global-alloc was run, notify it of any register eliminations we have
1718 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1719 if (ep->can_eliminate)
1720 mark_elimination (ep->from, ep->to);
1722 /* From now on, we need to emit any moves without making new pseudos. */
1723 reload_in_progress = 1;
1725 /* Insert code to save and restore call-clobbered hard regs
1726 around calls. Tell if what mode to use so that we will process
1727 those insns in reload_as_needed if we have to. */
1729 if (caller_save_needed)
1730 save_call_clobbered_regs (num_eliminable ? QImode
1731 : caller_save_spill_class != NO_REGS ? HImode
1734 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1735 If that insn didn't set the register (i.e., it copied the register to
1736 memory), just delete that insn instead of the equivalencing insn plus
1737 anything now dead. If we call delete_dead_insn on that insn, we may
1738 delete the insn that actually sets the register if the register die
1739 there and that is incorrect. */
1741 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1742 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0
1743 && GET_CODE (reg_equiv_init[i]) != NOTE)
1745 if (reg_set_p (regno_reg_rtx[i], PATTERN (reg_equiv_init[i])))
1746 delete_dead_insn (reg_equiv_init[i]);
1749 PUT_CODE (reg_equiv_init[i], NOTE);
1750 NOTE_SOURCE_FILE (reg_equiv_init[i]) = 0;
1751 NOTE_LINE_NUMBER (reg_equiv_init[i]) = NOTE_INSN_DELETED;
1755 /* Use the reload registers where necessary
1756 by generating move instructions to move the must-be-register
1757 values into or out of the reload registers. */
1759 if (something_needs_reloads || something_needs_elimination
1760 || (caller_save_needed && num_eliminable)
1761 || caller_save_spill_class != NO_REGS)
1762 reload_as_needed (first, global);
1764 reload_in_progress = 0;
1766 /* Come here (with failure set nonzero) if we can't get enough spill regs
1767 and we decide not to abort about it. */
1770 /* Now eliminate all pseudo regs by modifying them into
1771 their equivalent memory references.
1772 The REG-rtx's for the pseudos are modified in place,
1773 so all insns that used to refer to them now refer to memory.
1775 For a reg that has a reg_equiv_address, all those insns
1776 were changed by reloading so that no insns refer to it any longer;
1777 but the DECL_RTL of a variable decl may refer to it,
1778 and if so this causes the debugging info to mention the variable. */
1780 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1784 if (reg_equiv_mem[i])
1786 addr = XEXP (reg_equiv_mem[i], 0);
1787 in_struct = MEM_IN_STRUCT_P (reg_equiv_mem[i]);
1789 if (reg_equiv_address[i])
1790 addr = reg_equiv_address[i];
1793 if (reg_renumber[i] < 0)
1795 rtx reg = regno_reg_rtx[i];
1796 XEXP (reg, 0) = addr;
1797 REG_USERVAR_P (reg) = 0;
1798 MEM_IN_STRUCT_P (reg) = in_struct;
1799 PUT_CODE (reg, MEM);
1801 else if (reg_equiv_mem[i])
1802 XEXP (reg_equiv_mem[i], 0) = addr;
1806 #ifdef PRESERVE_DEATH_INFO_REGNO_P
1807 /* Make a pass over all the insns and remove death notes for things that
1808 are no longer registers or no longer die in the insn (e.g., an input
1809 and output pseudo being tied). */
1811 for (insn = first; insn; insn = NEXT_INSN (insn))
1812 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1816 for (note = REG_NOTES (insn); note; note = next)
1818 next = XEXP (note, 1);
1819 if (REG_NOTE_KIND (note) == REG_DEAD
1820 && (GET_CODE (XEXP (note, 0)) != REG
1821 || reg_set_p (XEXP (note, 0), PATTERN (insn))))
1822 remove_note (insn, note);
1827 /* Indicate that we no longer have known memory locations or constants. */
1828 reg_equiv_constant = 0;
1829 reg_equiv_memory_loc = 0;
1834 /* Nonzero if, after spilling reg REGNO for non-groups,
1835 it will still be possible to find a group if we still need one. */
1838 possible_group_p (regno, max_groups)
1843 int class = (int) NO_REGS;
1845 for (i = 0; i < (int) N_REG_CLASSES; i++)
1846 if (max_groups[i] > 0)
1852 if (class == (int) NO_REGS)
1855 /* Consider each pair of consecutive registers. */
1856 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
1858 /* Ignore pairs that include reg REGNO. */
1859 if (i == regno || i + 1 == regno)
1862 /* Ignore pairs that are outside the class that needs the group.
1863 ??? Here we fail to handle the case where two different classes
1864 independently need groups. But this never happens with our
1865 current machine descriptions. */
1866 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
1867 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
1870 /* A pair of consecutive regs we can still spill does the trick. */
1871 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
1872 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
1873 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
1876 /* A pair of one already spilled and one we can spill does it
1877 provided the one already spilled is not otherwise reserved. */
1878 if (spill_reg_order[i] < 0
1879 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
1880 && spill_reg_order[i + 1] >= 0
1881 && ! TEST_HARD_REG_BIT (counted_for_groups, i + 1)
1882 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i + 1))
1884 if (spill_reg_order[i + 1] < 0
1885 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
1886 && spill_reg_order[i] >= 0
1887 && ! TEST_HARD_REG_BIT (counted_for_groups, i)
1888 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i))
1895 /* Count any groups that can be formed from the registers recently spilled.
1896 This is done class by class, in order of ascending class number. */
1899 count_possible_groups (group_size, group_mode, max_groups)
1900 int *group_size, *max_groups;
1901 enum machine_mode *group_mode;
1904 /* Now find all consecutive groups of spilled registers
1905 and mark each group off against the need for such groups.
1906 But don't count them against ordinary need, yet. */
1908 for (i = 0; i < N_REG_CLASSES; i++)
1909 if (group_size[i] > 1)
1911 char regmask[FIRST_PSEUDO_REGISTER];
1914 bzero (regmask, sizeof regmask);
1915 /* Make a mask of all the regs that are spill regs in class I. */
1916 for (j = 0; j < n_spills; j++)
1917 if (TEST_HARD_REG_BIT (reg_class_contents[i], spill_regs[j])
1918 && ! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[j])
1919 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1921 regmask[spill_regs[j]] = 1;
1922 /* Find each consecutive group of them. */
1923 for (j = 0; j < FIRST_PSEUDO_REGISTER && max_groups[i] > 0; j++)
1924 if (regmask[j] && j + group_size[i] <= FIRST_PSEUDO_REGISTER
1925 /* Next line in case group-mode for this class
1926 demands an even-odd pair. */
1927 && HARD_REGNO_MODE_OK (j, group_mode[i]))
1930 for (k = 1; k < group_size[i]; k++)
1931 if (! regmask[j + k])
1933 if (k == group_size[i])
1935 /* We found a group. Mark it off against this class's
1936 need for groups, and against each superclass too. */
1937 register enum reg_class *p;
1939 p = reg_class_superclasses[i];
1940 while (*p != LIM_REG_CLASSES)
1941 max_groups[(int) *p++]--;
1942 /* Don't count these registers again. */
1943 for (k = 0; k < group_size[i]; k++)
1944 SET_HARD_REG_BIT (counted_for_groups, j + k);
1946 /* Skip to the last reg in this group. When j is incremented
1947 above, it will then point to the first reg of the next
1955 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
1956 another mode that needs to be reloaded for the same register class CLASS.
1957 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
1958 ALLOCATE_MODE will never be smaller than OTHER_MODE.
1960 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
1961 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
1962 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
1963 causes unnecessary failures on machines requiring alignment of register
1964 groups when the two modes are different sizes, because the larger mode has
1965 more strict alignment rules than the smaller mode. */
1968 modes_equiv_for_class_p (allocate_mode, other_mode, class)
1969 enum machine_mode allocate_mode, other_mode;
1970 enum reg_class class;
1973 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1975 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
1976 && HARD_REGNO_MODE_OK (regno, allocate_mode)
1977 && ! HARD_REGNO_MODE_OK (regno, other_mode))
1983 /* Handle the failure to find a register to spill.
1984 INSN should be one of the insns which needed this particular spill reg. */
1987 spill_failure (insn)
1990 if (asm_noperands (PATTERN (insn)) >= 0)
1991 error_for_asm (insn, "`asm' needs too many reloads");
1996 /* Add a new register to the tables of available spill-registers
1997 (as well as spilling all pseudos allocated to the register).
1998 I is the index of this register in potential_reload_regs.
1999 CLASS is the regclass whose need is being satisfied.
2000 MAX_NEEDS and MAX_NONGROUPS are the vectors of needs,
2001 so that this register can count off against them.
2002 MAX_NONGROUPS is 0 if this register is part of a group.
2003 GLOBAL and DUMPFILE are the same as the args that `reload' got. */
2006 new_spill_reg (i, class, max_needs, max_nongroups, global, dumpfile)
2014 register enum reg_class *p;
2016 int regno = potential_reload_regs[i];
2018 if (i >= FIRST_PSEUDO_REGISTER)
2019 abort (); /* Caller failed to find any register. */
2021 if (fixed_regs[regno] || TEST_HARD_REG_BIT (forbidden_regs, regno))
2022 fatal ("fixed or forbidden register was spilled.\n\
2023 This may be due to a compiler bug or to impossible asm statements.");
2025 /* Make reg REGNO an additional reload reg. */
2027 potential_reload_regs[i] = -1;
2028 spill_regs[n_spills] = regno;
2029 spill_reg_order[regno] = n_spills;
2031 fprintf (dumpfile, "Spilling reg %d.\n", spill_regs[n_spills]);
2033 /* Clear off the needs we just satisfied. */
2036 p = reg_class_superclasses[class];
2037 while (*p != LIM_REG_CLASSES)
2038 max_needs[(int) *p++]--;
2040 if (max_nongroups && max_nongroups[class] > 0)
2042 SET_HARD_REG_BIT (counted_for_nongroups, regno);
2043 max_nongroups[class]--;
2044 p = reg_class_superclasses[class];
2045 while (*p != LIM_REG_CLASSES)
2046 max_nongroups[(int) *p++]--;
2049 /* Spill every pseudo reg that was allocated to this reg
2050 or to something that overlaps this reg. */
2052 val = spill_hard_reg (spill_regs[n_spills], global, dumpfile, 0);
2054 /* If there are some registers still to eliminate and this register
2055 wasn't ever used before, additional stack space may have to be
2056 allocated to store this register. Thus, we may have changed the offset
2057 between the stack and frame pointers, so mark that something has changed.
2058 (If new pseudos were spilled, thus requiring more space, VAL would have
2059 been set non-zero by the call to spill_hard_reg above since additional
2060 reloads may be needed in that case.
2062 One might think that we need only set VAL to 1 if this is a call-used
2063 register. However, the set of registers that must be saved by the
2064 prologue is not identical to the call-used set. For example, the
2065 register used by the call insn for the return PC is a call-used register,
2066 but must be saved by the prologue. */
2067 if (num_eliminable && ! regs_ever_live[spill_regs[n_spills]])
2070 regs_ever_live[spill_regs[n_spills]] = 1;
2076 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2077 data that is dead in INSN. */
2080 delete_dead_insn (insn)
2083 rtx prev = prev_real_insn (insn);
2086 /* If the previous insn sets a register that dies in our insn, delete it
2088 if (prev && GET_CODE (PATTERN (prev)) == SET
2089 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2090 && reg_mentioned_p (prev_dest, PATTERN (insn))
2091 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)))
2092 delete_dead_insn (prev);
2094 PUT_CODE (insn, NOTE);
2095 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2096 NOTE_SOURCE_FILE (insn) = 0;
2099 /* Modify the home of pseudo-reg I.
2100 The new home is present in reg_renumber[I].
2102 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2103 or it may be -1, meaning there is none or it is not relevant.
2104 This is used so that all pseudos spilled from a given hard reg
2105 can share one stack slot. */
2108 alter_reg (i, from_reg)
2112 /* When outputting an inline function, this can happen
2113 for a reg that isn't actually used. */
2114 if (regno_reg_rtx[i] == 0)
2117 /* If the reg got changed to a MEM at rtl-generation time,
2119 if (GET_CODE (regno_reg_rtx[i]) != REG)
2122 /* Modify the reg-rtx to contain the new hard reg
2123 number or else to contain its pseudo reg number. */
2124 REGNO (regno_reg_rtx[i])
2125 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2127 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2128 allocate a stack slot for it. */
2130 if (reg_renumber[i] < 0
2131 && reg_n_refs[i] > 0
2132 && reg_equiv_constant[i] == 0
2133 && reg_equiv_memory_loc[i] == 0)
2136 int inherent_size = PSEUDO_REGNO_BYTES (i);
2137 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2140 /* Each pseudo reg has an inherent size which comes from its own mode,
2141 and a total size which provides room for paradoxical subregs
2142 which refer to the pseudo reg in wider modes.
2144 We can use a slot already allocated if it provides both
2145 enough inherent space and enough total space.
2146 Otherwise, we allocate a new slot, making sure that it has no less
2147 inherent space, and no less total space, then the previous slot. */
2150 /* No known place to spill from => no slot to reuse. */
2151 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size, -1);
2152 #if BYTES_BIG_ENDIAN
2153 /* Cancel the big-endian correction done in assign_stack_local.
2154 Get the address of the beginning of the slot.
2155 This is so we can do a big-endian correction unconditionally
2157 adjust = inherent_size - total_size;
2160 /* Reuse a stack slot if possible. */
2161 else if (spill_stack_slot[from_reg] != 0
2162 && spill_stack_slot_width[from_reg] >= total_size
2163 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2165 x = spill_stack_slot[from_reg];
2166 /* Allocate a bigger slot. */
2169 /* Compute maximum size needed, both for inherent size
2170 and for total size. */
2171 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2172 if (spill_stack_slot[from_reg])
2174 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2176 mode = GET_MODE (spill_stack_slot[from_reg]);
2177 if (spill_stack_slot_width[from_reg] > total_size)
2178 total_size = spill_stack_slot_width[from_reg];
2180 /* Make a slot with that size. */
2181 x = assign_stack_local (mode, total_size, -1);
2182 #if BYTES_BIG_ENDIAN
2183 /* Cancel the big-endian correction done in assign_stack_local.
2184 Get the address of the beginning of the slot.
2185 This is so we can do a big-endian correction unconditionally
2187 adjust = GET_MODE_SIZE (mode) - total_size;
2189 spill_stack_slot[from_reg] = x;
2190 spill_stack_slot_width[from_reg] = total_size;
2193 #if BYTES_BIG_ENDIAN
2194 /* On a big endian machine, the "address" of the slot
2195 is the address of the low part that fits its inherent mode. */
2196 if (inherent_size < total_size)
2197 adjust += (total_size - inherent_size);
2198 #endif /* BYTES_BIG_ENDIAN */
2200 /* If we have any adjustment to make, or if the stack slot is the
2201 wrong mode, make a new stack slot. */
2202 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2204 x = gen_rtx (MEM, GET_MODE (regno_reg_rtx[i]),
2205 plus_constant (XEXP (x, 0), adjust));
2206 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2209 /* Save the stack slot for later. */
2210 reg_equiv_memory_loc[i] = x;
2214 /* Mark the slots in regs_ever_live for the hard regs
2215 used by pseudo-reg number REGNO. */
2218 mark_home_live (regno)
2221 register int i, lim;
2222 i = reg_renumber[regno];
2225 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2227 regs_ever_live[i++] = 1;
2230 /* This function handles the tracking of elimination offsets around branches.
2232 X is a piece of RTL being scanned.
2234 INSN is the insn that it came from, if any.
2236 INITIAL_P is non-zero if we are to set the offset to be the initial
2237 offset and zero if we are setting the offset of the label to be the
2241 set_label_offsets (x, insn, initial_p)
2246 enum rtx_code code = GET_CODE (x);
2249 struct elim_table *p;
2254 if (LABEL_REF_NONLOCAL_P (x))
2259 /* ... fall through ... */
2262 /* If we know nothing about this label, set the desired offsets. Note
2263 that this sets the offset at a label to be the offset before a label
2264 if we don't know anything about the label. This is not correct for
2265 the label after a BARRIER, but is the best guess we can make. If
2266 we guessed wrong, we will suppress an elimination that might have
2267 been possible had we been able to guess correctly. */
2269 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2271 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2272 offsets_at[CODE_LABEL_NUMBER (x)][i]
2273 = (initial_p ? reg_eliminate[i].initial_offset
2274 : reg_eliminate[i].offset);
2275 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2278 /* Otherwise, if this is the definition of a label and it is
2279 preceded by a BARRIER, set our offsets to the known offset of
2283 && (tem = prev_nonnote_insn (insn)) != 0
2284 && GET_CODE (tem) == BARRIER)
2286 num_not_at_initial_offset = 0;
2287 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2289 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
2290 = offsets_at[CODE_LABEL_NUMBER (x)][i];
2291 if (reg_eliminate[i].can_eliminate
2292 && (reg_eliminate[i].offset
2293 != reg_eliminate[i].initial_offset))
2294 num_not_at_initial_offset++;
2299 /* If neither of the above cases is true, compare each offset
2300 with those previously recorded and suppress any eliminations
2301 where the offsets disagree. */
2303 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2304 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2305 != (initial_p ? reg_eliminate[i].initial_offset
2306 : reg_eliminate[i].offset))
2307 reg_eliminate[i].can_eliminate = 0;
2312 set_label_offsets (PATTERN (insn), insn, initial_p);
2314 /* ... fall through ... */
2318 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2319 and hence must have all eliminations at their initial offsets. */
2320 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2321 if (REG_NOTE_KIND (tem) == REG_LABEL)
2322 set_label_offsets (XEXP (tem, 0), insn, 1);
2327 /* Each of the labels in the address vector must be at their initial
2328 offsets. We want the first first for ADDR_VEC and the second
2329 field for ADDR_DIFF_VEC. */
2331 for (i = 0; i < XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2332 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2337 /* We only care about setting PC. If the source is not RETURN,
2338 IF_THEN_ELSE, or a label, disable any eliminations not at
2339 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2340 isn't one of those possibilities. For branches to a label,
2341 call ourselves recursively.
2343 Note that this can disable elimination unnecessarily when we have
2344 a non-local goto since it will look like a non-constant jump to
2345 someplace in the current function. This isn't a significant
2346 problem since such jumps will normally be when all elimination
2347 pairs are back to their initial offsets. */
2349 if (SET_DEST (x) != pc_rtx)
2352 switch (GET_CODE (SET_SRC (x)))
2359 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2363 tem = XEXP (SET_SRC (x), 1);
2364 if (GET_CODE (tem) == LABEL_REF)
2365 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2366 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2369 tem = XEXP (SET_SRC (x), 2);
2370 if (GET_CODE (tem) == LABEL_REF)
2371 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2372 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2377 /* If we reach here, all eliminations must be at their initial
2378 offset because we are doing a jump to a variable address. */
2379 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2380 if (p->offset != p->initial_offset)
2381 p->can_eliminate = 0;
2385 /* Used for communication between the next two function to properly share
2386 the vector for an ASM_OPERANDS. */
2388 static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2390 /* Scan X and replace any eliminable registers (such as fp) with a
2391 replacement (such as sp), plus an offset.
2393 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2394 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2395 MEM, we are allowed to replace a sum of a register and the constant zero
2396 with the register, which we cannot do outside a MEM. In addition, we need
2397 to record the fact that a register is referenced outside a MEM.
2399 If INSN is nonzero, it is the insn containing X. If we replace a REG
2400 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2401 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2402 that the REG is being modified.
2404 If we see a modification to a register we know about, take the
2405 appropriate action (see case SET, below).
2407 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2408 replacements done assuming all offsets are at their initial values. If
2409 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2410 encounter, return the actual location so that find_reloads will do
2411 the proper thing. */
2414 eliminate_regs (x, mem_mode, insn)
2416 enum machine_mode mem_mode;
2419 enum rtx_code code = GET_CODE (x);
2420 struct elim_table *ep;
2445 /* First handle the case where we encounter a bare register that
2446 is eliminable. Replace it with a PLUS. */
2447 if (regno < FIRST_PSEUDO_REGISTER)
2449 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2451 if (ep->from_rtx == x && ep->can_eliminate)
2454 ep->ref_outside_mem = 1;
2455 return plus_constant (ep->to_rtx, ep->previous_offset);
2459 else if (reg_equiv_memory_loc && reg_equiv_memory_loc[regno]
2460 && (reg_equiv_address[regno] || num_not_at_initial_offset))
2462 /* In this case, find_reloads would attempt to either use an
2463 incorrect address (if something is not at its initial offset)
2464 or substitute an replaced address into an insn (which loses
2465 if the offset is changed by some later action). So we simply
2466 return the replaced stack slot (assuming it is changed by
2467 elimination) and ignore the fact that this is actually a
2468 reference to the pseudo. Ensure we make a copy of the
2469 address in case it is shared. */
2470 new = eliminate_regs (reg_equiv_memory_loc[regno],
2471 mem_mode, NULL_RTX);
2472 if (new != reg_equiv_memory_loc[regno])
2473 return copy_rtx (new);
2478 /* If this is the sum of an eliminable register and a constant, rework
2480 if (GET_CODE (XEXP (x, 0)) == REG
2481 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2482 && CONSTANT_P (XEXP (x, 1)))
2484 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2486 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2489 ep->ref_outside_mem = 1;
2491 /* The only time we want to replace a PLUS with a REG (this
2492 occurs when the constant operand of the PLUS is the negative
2493 of the offset) is when we are inside a MEM. We won't want
2494 to do so at other times because that would change the
2495 structure of the insn in a way that reload can't handle.
2496 We special-case the commonest situation in
2497 eliminate_regs_in_insn, so just replace a PLUS with a
2498 PLUS here, unless inside a MEM. */
2499 if (mem_mode && GET_CODE (XEXP (x, 1)) == CONST_INT
2500 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2503 return gen_rtx (PLUS, Pmode, ep->to_rtx,
2504 plus_constant (XEXP (x, 1),
2505 ep->previous_offset));
2508 /* If the register is not eliminable, we are done since the other
2509 operand is a constant. */
2513 /* If this is part of an address, we want to bring any constant to the
2514 outermost PLUS. We will do this by doing register replacement in
2515 our operands and seeing if a constant shows up in one of them.
2517 We assume here this is part of an address (or a "load address" insn)
2518 since an eliminable register is not likely to appear in any other
2521 If we have (plus (eliminable) (reg)), we want to produce
2522 (plus (plus (replacement) (reg) (const))). If this was part of a
2523 normal add insn, (plus (replacement) (reg)) will be pushed as a
2524 reload. This is the desired action. */
2527 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2528 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, NULL_RTX);
2530 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2532 /* If one side is a PLUS and the other side is a pseudo that
2533 didn't get a hard register but has a reg_equiv_constant,
2534 we must replace the constant here since it may no longer
2535 be in the position of any operand. */
2536 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2537 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2538 && reg_renumber[REGNO (new1)] < 0
2539 && reg_equiv_constant != 0
2540 && reg_equiv_constant[REGNO (new1)] != 0)
2541 new1 = reg_equiv_constant[REGNO (new1)];
2542 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2543 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2544 && reg_renumber[REGNO (new0)] < 0
2545 && reg_equiv_constant[REGNO (new0)] != 0)
2546 new0 = reg_equiv_constant[REGNO (new0)];
2548 new = form_sum (new0, new1);
2550 /* As above, if we are not inside a MEM we do not want to
2551 turn a PLUS into something else. We might try to do so here
2552 for an addition of 0 if we aren't optimizing. */
2553 if (! mem_mode && GET_CODE (new) != PLUS)
2554 return gen_rtx (PLUS, GET_MODE (x), new, const0_rtx);
2562 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2565 new = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2566 if (new != XEXP (x, 0))
2567 x = gen_rtx (EXPR_LIST, REG_NOTE_KIND (x), new, XEXP (x, 1));
2570 /* ... fall through ... */
2573 /* Now do eliminations in the rest of the chain. If this was
2574 an EXPR_LIST, this might result in allocating more memory than is
2575 strictly needed, but it simplifies the code. */
2578 new = eliminate_regs (XEXP (x, 1), mem_mode, NULL_RTX);
2579 if (new != XEXP (x, 1))
2580 return gen_rtx (INSN_LIST, GET_MODE (x), XEXP (x, 0), new);
2588 case DIV: case UDIV:
2589 case MOD: case UMOD:
2590 case AND: case IOR: case XOR:
2591 case LSHIFT: case ASHIFT: case ROTATE:
2592 case ASHIFTRT: case LSHIFTRT: case ROTATERT:
2594 case GE: case GT: case GEU: case GTU:
2595 case LE: case LT: case LEU: case LTU:
2597 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2599 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, NULL_RTX) : 0;
2601 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2602 return gen_rtx (code, GET_MODE (x), new0, new1);
2610 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2611 if (ep->to_rtx == XEXP (x, 0))
2613 if (code == PRE_DEC || code == POST_DEC)
2614 ep->offset += GET_MODE_SIZE (mem_mode);
2616 ep->offset -= GET_MODE_SIZE (mem_mode);
2619 /* Fall through to generic unary operation case. */
2621 case STRICT_LOW_PART:
2623 case SIGN_EXTEND: case ZERO_EXTEND:
2624 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2625 case FLOAT: case FIX:
2626 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2630 new = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2631 if (new != XEXP (x, 0))
2632 return gen_rtx (code, GET_MODE (x), new);
2636 /* Similar to above processing, but preserve SUBREG_WORD.
2637 Convert (subreg (mem)) to (mem) if not paradoxical.
2638 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2639 pseudo didn't get a hard reg, we must replace this with the
2640 eliminated version of the memory location because push_reloads
2641 may do the replacement in certain circumstances. */
2642 if (GET_CODE (SUBREG_REG (x)) == REG
2643 && (GET_MODE_SIZE (GET_MODE (x))
2644 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2645 && reg_equiv_memory_loc != 0
2646 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2648 new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
2649 mem_mode, NULL_RTX);
2651 /* If we didn't change anything, we must retain the pseudo. */
2652 if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
2655 /* Otherwise, ensure NEW isn't shared in case we have to reload
2657 new = copy_rtx (new);
2660 new = eliminate_regs (SUBREG_REG (x), mem_mode, NULL_RTX);
2662 if (new != XEXP (x, 0))
2664 if (GET_CODE (new) == MEM
2665 && (GET_MODE_SIZE (GET_MODE (x))
2666 <= GET_MODE_SIZE (GET_MODE (new))))
2668 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2669 enum machine_mode mode = GET_MODE (x);
2671 #if BYTES_BIG_ENDIAN
2672 offset += (MIN (UNITS_PER_WORD,
2673 GET_MODE_SIZE (GET_MODE (new)))
2674 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2677 PUT_MODE (new, mode);
2678 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2682 return gen_rtx (SUBREG, GET_MODE (x), new, SUBREG_WORD (x));
2688 /* If clobbering a register that is the replacement register for an
2689 elimination we still think can be performed, note that it cannot
2690 be performed. Otherwise, we need not be concerned about it. */
2691 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2692 if (ep->to_rtx == XEXP (x, 0))
2693 ep->can_eliminate = 0;
2700 /* Properly handle sharing input and constraint vectors. */
2701 if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
2703 /* When we come to a new vector not seen before,
2704 scan all its elements; keep the old vector if none
2705 of them changes; otherwise, make a copy. */
2706 old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
2707 temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
2708 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
2709 temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
2710 mem_mode, NULL_RTX);
2712 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
2713 if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
2716 if (i == ASM_OPERANDS_INPUT_LENGTH (x))
2717 new_asm_operands_vec = old_asm_operands_vec;
2719 new_asm_operands_vec
2720 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
2723 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
2724 if (new_asm_operands_vec == old_asm_operands_vec)
2727 new = gen_rtx (ASM_OPERANDS, VOIDmode, ASM_OPERANDS_TEMPLATE (x),
2728 ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
2729 ASM_OPERANDS_OUTPUT_IDX (x), new_asm_operands_vec,
2730 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
2731 ASM_OPERANDS_SOURCE_FILE (x),
2732 ASM_OPERANDS_SOURCE_LINE (x));
2733 new->volatil = x->volatil;
2738 /* Check for setting a register that we know about. */
2739 if (GET_CODE (SET_DEST (x)) == REG)
2741 /* See if this is setting the replacement register for an
2744 If DEST is the frame pointer, we do nothing because we assume that
2745 all assignments to the frame pointer are for non-local gotos and
2746 are being done at a time when they are valid and do not disturb
2747 anything else. Some machines want to eliminate a fake argument
2748 pointer with either the frame or stack pointer. Assignments to
2749 the frame pointer must not prevent this elimination. */
2751 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2753 if (ep->to_rtx == SET_DEST (x)
2754 && SET_DEST (x) != frame_pointer_rtx)
2756 /* If it is being incremented, adjust the offset. Otherwise,
2757 this elimination can't be done. */
2758 rtx src = SET_SRC (x);
2760 if (GET_CODE (src) == PLUS
2761 && XEXP (src, 0) == SET_DEST (x)
2762 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2763 ep->offset -= INTVAL (XEXP (src, 1));
2765 ep->can_eliminate = 0;
2768 /* Now check to see we are assigning to a register that can be
2769 eliminated. If so, it must be as part of a PARALLEL, since we
2770 will not have been called if this is a single SET. So indicate
2771 that we can no longer eliminate this reg. */
2772 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2774 if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
2775 ep->can_eliminate = 0;
2778 /* Now avoid the loop below in this common case. */
2780 rtx new0 = eliminate_regs (SET_DEST (x), 0, NULL_RTX);
2781 rtx new1 = eliminate_regs (SET_SRC (x), 0, NULL_RTX);
2783 /* If SET_DEST changed from a REG to a MEM and INSN is non-zero,
2784 write a CLOBBER insn. */
2785 if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
2787 emit_insn_after (gen_rtx (CLOBBER, VOIDmode, SET_DEST (x)), insn);
2789 if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
2790 return gen_rtx (SET, VOIDmode, new0, new1);
2796 /* Our only special processing is to pass the mode of the MEM to our
2797 recursive call and copy the flags. While we are here, handle this
2798 case more efficiently. */
2799 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), NULL_RTX);
2800 if (new != XEXP (x, 0))
2802 new = gen_rtx (MEM, GET_MODE (x), new);
2803 new->volatil = x->volatil;
2804 new->unchanging = x->unchanging;
2805 new->in_struct = x->in_struct;
2812 /* Process each of our operands recursively. If any have changed, make a
2814 fmt = GET_RTX_FORMAT (code);
2815 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2819 new = eliminate_regs (XEXP (x, i), mem_mode, NULL_RTX);
2820 if (new != XEXP (x, i) && ! copied)
2822 rtx new_x = rtx_alloc (code);
2823 bcopy (x, new_x, (sizeof (*new_x) - sizeof (new_x->fld)
2824 + (sizeof (new_x->fld[0])
2825 * GET_RTX_LENGTH (code))));
2831 else if (*fmt == 'E')
2834 for (j = 0; j < XVECLEN (x, i); j++)
2836 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2837 if (new != XVECEXP (x, i, j) && ! copied_vec)
2839 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2840 &XVECEXP (x, i, 0));
2843 rtx new_x = rtx_alloc (code);
2844 bcopy (x, new_x, (sizeof (*new_x) - sizeof (new_x->fld)
2845 + (sizeof (new_x->fld[0])
2846 * GET_RTX_LENGTH (code))));
2850 XVEC (x, i) = new_v;
2853 XVECEXP (x, i, j) = new;
2861 /* Scan INSN and eliminate all eliminable registers in it.
2863 If REPLACE is nonzero, do the replacement destructively. Also
2864 delete the insn as dead it if it is setting an eliminable register.
2866 If REPLACE is zero, do all our allocations in reload_obstack.
2868 If no eliminations were done and this insn doesn't require any elimination
2869 processing (these are not identical conditions: it might be updating sp,
2870 but not referencing fp; this needs to be seen during reload_as_needed so
2871 that the offset between fp and sp can be taken into consideration), zero
2872 is returned. Otherwise, 1 is returned. */
2875 eliminate_regs_in_insn (insn, replace)
2879 rtx old_body = PATTERN (insn);
2882 struct elim_table *ep;
2885 push_obstacks (&reload_obstack, &reload_obstack);
2887 if (GET_CODE (old_body) == SET && GET_CODE (SET_DEST (old_body)) == REG
2888 && REGNO (SET_DEST (old_body)) < FIRST_PSEUDO_REGISTER)
2890 /* Check for setting an eliminable register. */
2891 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2892 if (ep->from_rtx == SET_DEST (old_body) && ep->can_eliminate)
2894 /* In this case this insn isn't serving a useful purpose. We
2895 will delete it in reload_as_needed once we know that this
2896 elimination is, in fact, being done.
2898 If REPLACE isn't set, we can't delete this insn, but neededn't
2899 process it since it won't be used unless something changes. */
2901 delete_dead_insn (insn);
2906 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
2907 in the insn is the negative of the offset in FROM. Substitute
2908 (set (reg) (reg to)) for the insn and change its code.
2910 We have to do this here, rather than in eliminate_regs, do that we can
2911 change the insn code. */
2913 if (GET_CODE (SET_SRC (old_body)) == PLUS
2914 && GET_CODE (XEXP (SET_SRC (old_body), 0)) == REG
2915 && GET_CODE (XEXP (SET_SRC (old_body), 1)) == CONST_INT)
2916 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2918 if (ep->from_rtx == XEXP (SET_SRC (old_body), 0)
2919 && ep->can_eliminate
2920 && ep->offset == - INTVAL (XEXP (SET_SRC (old_body), 1)))
2922 PATTERN (insn) = gen_rtx (SET, VOIDmode,
2923 SET_DEST (old_body), ep->to_rtx);
2924 INSN_CODE (insn) = -1;
2930 old_asm_operands_vec = 0;
2932 /* Replace the body of this insn with a substituted form. If we changed
2933 something, return non-zero. If this is the final call for this
2934 insn (REPLACE is non-zero), do the elimination in REG_NOTES as well.
2936 If we are replacing a body that was a (set X (plus Y Z)), try to
2937 re-recognize the insn. We do this in case we had a simple addition
2938 but now can do this as a load-address. This saves an insn in this
2941 new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX);
2942 if (new_body != old_body)
2944 if (GET_CODE (old_body) != SET || GET_CODE (SET_SRC (old_body)) != PLUS
2945 || ! validate_change (insn, &PATTERN (insn), new_body, 0))
2946 PATTERN (insn) = new_body;
2948 if (replace && REG_NOTES (insn))
2949 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, NULL_RTX);
2953 /* Loop through all elimination pairs. See if any have changed and
2954 recalculate the number not at initial offset.
2956 Compute the maximum offset (minimum offset if the stack does not
2957 grow downward) for each elimination pair.
2959 We also detect a cases where register elimination cannot be done,
2960 namely, if a register would be both changed and referenced outside a MEM
2961 in the resulting insn since such an insn is often undefined and, even if
2962 not, we cannot know what meaning will be given to it. Note that it is
2963 valid to have a register used in an address in an insn that changes it
2964 (presumably with a pre- or post-increment or decrement).
2966 If anything changes, return nonzero. */
2968 num_not_at_initial_offset = 0;
2969 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2971 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
2972 ep->can_eliminate = 0;
2974 ep->ref_outside_mem = 0;
2976 if (ep->previous_offset != ep->offset)
2979 ep->previous_offset = ep->offset;
2980 if (ep->can_eliminate && ep->offset != ep->initial_offset)
2981 num_not_at_initial_offset++;
2983 #ifdef STACK_GROWS_DOWNWARD
2984 ep->max_offset = MAX (ep->max_offset, ep->offset);
2986 ep->max_offset = MIN (ep->max_offset, ep->offset);
2997 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
2998 replacement we currently believe is valid, mark it as not eliminable if X
2999 modifies DEST in any way other than by adding a constant integer to it.
3001 If DEST is the frame pointer, we do nothing because we assume that
3002 all assignments to the frame pointer are nonlocal gotos and are being done
3003 at a time when they are valid and do not disturb anything else.
3004 Some machines want to eliminate a fake argument pointer with either the
3005 frame or stack pointer. Assignments to the frame pointer must not prevent
3008 Called via note_stores from reload before starting its passes to scan
3009 the insns of the function. */
3012 mark_not_eliminable (dest, x)
3018 /* A SUBREG of a hard register here is just changing its mode. We should
3019 not see a SUBREG of an eliminable hard register, but check just in
3021 if (GET_CODE (dest) == SUBREG)
3022 dest = SUBREG_REG (dest);
3024 if (dest == frame_pointer_rtx)
3027 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3028 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3029 && (GET_CODE (x) != SET
3030 || GET_CODE (SET_SRC (x)) != PLUS
3031 || XEXP (SET_SRC (x), 0) != dest
3032 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3034 reg_eliminate[i].can_eliminate_previous
3035 = reg_eliminate[i].can_eliminate = 0;
3040 /* Kick all pseudos out of hard register REGNO.
3041 If GLOBAL is nonzero, try to find someplace else to put them.
3042 If DUMPFILE is nonzero, log actions taken on that file.
3044 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3045 because we found we can't eliminate some register. In the case, no pseudos
3046 are allowed to be in the register, even if they are only in a block that
3047 doesn't require spill registers, unlike the case when we are spilling this
3048 hard reg to produce another spill register.
3050 Return nonzero if any pseudos needed to be kicked out. */
3053 spill_hard_reg (regno, global, dumpfile, cant_eliminate)
3059 int something_changed = 0;
3062 SET_HARD_REG_BIT (forbidden_regs, regno);
3064 /* Spill every pseudo reg that was allocated to this reg
3065 or to something that overlaps this reg. */
3067 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3068 if (reg_renumber[i] >= 0
3069 && reg_renumber[i] <= regno
3071 + HARD_REGNO_NREGS (reg_renumber[i],
3072 PSEUDO_REGNO_MODE (i))
3075 enum reg_class class = REGNO_REG_CLASS (regno);
3077 /* If this register belongs solely to a basic block which needed no
3078 spilling of any class that this register is contained in,
3079 leave it be, unless we are spilling this register because
3080 it was a hard register that can't be eliminated. */
3082 if (! cant_eliminate
3083 && basic_block_needs[0]
3084 && reg_basic_block[i] >= 0
3085 && basic_block_needs[(int) class][reg_basic_block[i]] == 0)
3089 for (p = reg_class_superclasses[(int) class];
3090 *p != LIM_REG_CLASSES; p++)
3091 if (basic_block_needs[(int) *p][reg_basic_block[i]] > 0)
3094 if (*p == LIM_REG_CLASSES)
3098 /* Mark it as no longer having a hard register home. */
3099 reg_renumber[i] = -1;
3100 /* We will need to scan everything again. */
3101 something_changed = 1;
3103 retry_global_alloc (i, forbidden_regs);
3105 alter_reg (i, regno);
3108 if (reg_renumber[i] == -1)
3109 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3111 fprintf (dumpfile, " Register %d now in %d.\n\n",
3112 i, reg_renumber[i]);
3116 return something_changed;
3119 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3122 scan_paradoxical_subregs (x)
3127 register enum rtx_code code = GET_CODE (x);
3144 if (GET_CODE (SUBREG_REG (x)) == REG
3145 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3146 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3147 = GET_MODE_SIZE (GET_MODE (x));
3151 fmt = GET_RTX_FORMAT (code);
3152 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3155 scan_paradoxical_subregs (XEXP (x, i));
3156 else if (fmt[i] == 'E')
3159 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3160 scan_paradoxical_subregs (XVECEXP (x, i, j));
3165 struct hard_reg_n_uses { int regno; int uses; };
3168 hard_reg_use_compare (p1, p2)
3169 struct hard_reg_n_uses *p1, *p2;
3171 int tem = p1->uses - p2->uses;
3172 if (tem != 0) return tem;
3173 /* If regs are equally good, sort by regno,
3174 so that the results of qsort leave nothing to chance. */
3175 return p1->regno - p2->regno;
3178 /* Choose the order to consider regs for use as reload registers
3179 based on how much trouble would be caused by spilling one.
3180 Store them in order of decreasing preference in potential_reload_regs. */
3183 order_regs_for_reload ()
3189 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
3191 CLEAR_HARD_REG_SET (bad_spill_regs);
3193 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3194 potential_reload_regs[i] = -1;
3196 /* Count number of uses of each hard reg by pseudo regs allocated to it
3197 and then order them by decreasing use. */
3199 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3201 hard_reg_n_uses[i].uses = 0;
3202 hard_reg_n_uses[i].regno = i;
3205 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3207 int regno = reg_renumber[i];
3210 int lim = regno + HARD_REGNO_NREGS (regno, PSEUDO_REGNO_MODE (i));
3212 hard_reg_n_uses[regno++].uses += reg_n_refs[i];
3214 large += reg_n_refs[i];
3217 /* Now fixed registers (which cannot safely be used for reloading)
3218 get a very high use count so they will be considered least desirable.
3219 Registers used explicitly in the rtl code are almost as bad. */
3221 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3225 hard_reg_n_uses[i].uses += 2 * large + 2;
3226 SET_HARD_REG_BIT (bad_spill_regs, i);
3228 else if (regs_explicitly_used[i])
3230 hard_reg_n_uses[i].uses += large + 1;
3231 /* ??? We are doing this here because of the potential that
3232 bad code may be generated if a register explicitly used in
3233 an insn was used as a spill register for that insn. But
3234 not using these are spill registers may lose on some machine.
3235 We'll have to see how this works out. */
3236 SET_HARD_REG_BIT (bad_spill_regs, i);
3239 hard_reg_n_uses[FRAME_POINTER_REGNUM].uses += 2 * large + 2;
3240 SET_HARD_REG_BIT (bad_spill_regs, FRAME_POINTER_REGNUM);
3242 #ifdef ELIMINABLE_REGS
3243 /* If registers other than the frame pointer are eliminable, mark them as
3245 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3247 hard_reg_n_uses[reg_eliminate[i].from].uses += 2 * large + 2;
3248 SET_HARD_REG_BIT (bad_spill_regs, reg_eliminate[i].from);
3252 /* Prefer registers not so far used, for use in temporary loading.
3253 Among them, if REG_ALLOC_ORDER is defined, use that order.
3254 Otherwise, prefer registers not preserved by calls. */
3256 #ifdef REG_ALLOC_ORDER
3257 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3259 int regno = reg_alloc_order[i];
3261 if (hard_reg_n_uses[regno].uses == 0)
3262 potential_reload_regs[o++] = regno;
3265 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3267 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i])
3268 potential_reload_regs[o++] = i;
3270 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3272 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i])
3273 potential_reload_regs[o++] = i;
3277 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
3278 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
3280 /* Now add the regs that are already used,
3281 preferring those used less often. The fixed and otherwise forbidden
3282 registers will be at the end of this list. */
3284 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3285 if (hard_reg_n_uses[i].uses != 0)
3286 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
3289 /* Reload pseudo-registers into hard regs around each insn as needed.
3290 Additional register load insns are output before the insn that needs it
3291 and perhaps store insns after insns that modify the reloaded pseudo reg.
3293 reg_last_reload_reg and reg_reloaded_contents keep track of
3294 which pseudo-registers are already available in reload registers.
3295 We update these for the reloads that we perform,
3296 as the insns are scanned. */
3299 reload_as_needed (first, live_known)
3309 bzero (spill_reg_rtx, sizeof spill_reg_rtx);
3310 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
3311 bzero (reg_last_reload_reg, max_regno * sizeof (rtx));
3312 reg_has_output_reload = (char *) alloca (max_regno);
3313 for (i = 0; i < n_spills; i++)
3315 reg_reloaded_contents[i] = -1;
3316 reg_reloaded_insn[i] = 0;
3319 /* Reset all offsets on eliminable registers to their initial values. */
3320 #ifdef ELIMINABLE_REGS
3321 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3323 INITIAL_ELIMINATION_OFFSET (reg_eliminate[i].from, reg_eliminate[i].to,
3324 reg_eliminate[i].initial_offset);
3325 reg_eliminate[i].previous_offset
3326 = reg_eliminate[i].offset = reg_eliminate[i].initial_offset;
3329 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
3330 reg_eliminate[0].previous_offset
3331 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
3334 num_not_at_initial_offset = 0;
3336 for (insn = first; insn;)
3338 register rtx next = NEXT_INSN (insn);
3340 /* Notice when we move to a new basic block. */
3341 if (live_known && this_block + 1 < n_basic_blocks
3342 && insn == basic_block_head[this_block+1])
3345 /* If we pass a label, copy the offsets from the label information
3346 into the current offsets of each elimination. */
3347 if (GET_CODE (insn) == CODE_LABEL)
3349 num_not_at_initial_offset = 0;
3350 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3352 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
3353 = offsets_at[CODE_LABEL_NUMBER (insn)][i];
3354 if (reg_eliminate[i].can_eliminate
3355 && (reg_eliminate[i].offset
3356 != reg_eliminate[i].initial_offset))
3357 num_not_at_initial_offset++;
3361 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3363 rtx avoid_return_reg = 0;
3365 #ifdef SMALL_REGISTER_CLASSES
3366 /* Set avoid_return_reg if this is an insn
3367 that might use the value of a function call. */
3368 if (GET_CODE (insn) == CALL_INSN)
3370 if (GET_CODE (PATTERN (insn)) == SET)
3371 after_call = SET_DEST (PATTERN (insn));
3372 else if (GET_CODE (PATTERN (insn)) == PARALLEL
3373 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
3374 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
3378 else if (after_call != 0
3379 && !(GET_CODE (PATTERN (insn)) == SET
3380 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
3382 if (reg_mentioned_p (after_call, PATTERN (insn)))
3383 avoid_return_reg = after_call;
3386 #endif /* SMALL_REGISTER_CLASSES */
3388 /* If this is a USE and CLOBBER of a MEM, ensure that any
3389 references to eliminable registers have been removed. */
3391 if ((GET_CODE (PATTERN (insn)) == USE
3392 || GET_CODE (PATTERN (insn)) == CLOBBER)
3393 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3394 XEXP (XEXP (PATTERN (insn), 0), 0)
3395 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3396 GET_MODE (XEXP (PATTERN (insn), 0)), NULL_RTX);
3398 /* If we need to do register elimination processing, do so.
3399 This might delete the insn, in which case we are done. */
3400 if (num_eliminable && GET_MODE (insn) == QImode)
3402 eliminate_regs_in_insn (insn, 1);
3403 if (GET_CODE (insn) == NOTE)
3410 if (GET_MODE (insn) == VOIDmode)
3412 /* First find the pseudo regs that must be reloaded for this insn.
3413 This info is returned in the tables reload_... (see reload.h).
3414 Also modify the body of INSN by substituting RELOAD
3415 rtx's for those pseudo regs. */
3418 bzero (reg_has_output_reload, max_regno);
3419 CLEAR_HARD_REG_SET (reg_is_output_reload);
3421 find_reloads (insn, 1, spill_indirect_levels, live_known,
3427 rtx prev = PREV_INSN (insn), next = NEXT_INSN (insn);
3431 /* If this block has not had spilling done for a
3432 particular class, deactivate any optional reloads
3433 of that class lest they try to use a spill-reg which isn't
3434 available here. If we have any non-optionals that need a
3435 spill reg, abort. */
3437 for (class = 0; class < N_REG_CLASSES; class++)
3438 if (basic_block_needs[class] != 0
3439 && basic_block_needs[class][this_block] == 0)
3440 for (i = 0; i < n_reloads; i++)
3441 if (class == (int) reload_reg_class[i])
3443 if (reload_optional[i])
3445 reload_in[i] = reload_out[i] = 0;
3446 reload_secondary_p[i] = 0;
3448 else if (reload_reg_rtx[i] == 0
3449 && (reload_in[i] != 0 || reload_out[i] != 0
3450 || reload_secondary_p[i] != 0))
3454 /* Now compute which reload regs to reload them into. Perhaps
3455 reusing reload regs from previous insns, or else output
3456 load insns to reload them. Maybe output store insns too.
3457 Record the choices of reload reg in reload_reg_rtx. */
3458 choose_reload_regs (insn, avoid_return_reg);
3460 /* Generate the insns to reload operands into or out of
3461 their reload regs. */
3462 emit_reload_insns (insn);
3464 /* Substitute the chosen reload regs from reload_reg_rtx
3465 into the insn's body (or perhaps into the bodies of other
3466 load and store insn that we just made for reloading
3467 and that we moved the structure into). */
3470 /* If this was an ASM, make sure that all the reload insns
3471 we have generated are valid. If not, give an error
3474 if (asm_noperands (PATTERN (insn)) >= 0)
3475 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3476 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
3477 && (recog_memoized (p) < 0
3478 || (insn_extract (p),
3479 ! constrain_operands (INSN_CODE (p), 1))))
3481 error_for_asm (insn,
3482 "`asm' operand requires impossible reload");
3484 NOTE_SOURCE_FILE (p) = 0;
3485 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3488 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3489 is no longer validly lying around to save a future reload.
3490 Note that this does not detect pseudos that were reloaded
3491 for this insn in order to be stored in
3492 (obeying register constraints). That is correct; such reload
3493 registers ARE still valid. */
3494 note_stores (PATTERN (insn), forget_old_reloads_1);
3496 /* There may have been CLOBBER insns placed after INSN. So scan
3497 between INSN and NEXT and use them to forget old reloads. */
3498 for (x = NEXT_INSN (insn); x != next; x = NEXT_INSN (x))
3499 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3500 note_stores (PATTERN (x), forget_old_reloads_1);
3503 /* Likewise for regs altered by auto-increment in this insn.
3504 But note that the reg-notes are not changed by reloading:
3505 they still contain the pseudo-regs, not the spill regs. */
3506 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3507 if (REG_NOTE_KIND (x) == REG_INC)
3509 /* See if this pseudo reg was reloaded in this insn.
3510 If so, its last-reload info is still valid
3511 because it is based on this insn's reload. */
3512 for (i = 0; i < n_reloads; i++)
3513 if (reload_out[i] == XEXP (x, 0))
3517 forget_old_reloads_1 (XEXP (x, 0));
3521 /* A reload reg's contents are unknown after a label. */
3522 if (GET_CODE (insn) == CODE_LABEL)
3523 for (i = 0; i < n_spills; i++)
3525 reg_reloaded_contents[i] = -1;
3526 reg_reloaded_insn[i] = 0;
3529 /* Don't assume a reload reg is still good after a call insn
3530 if it is a call-used reg. */
3531 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == CALL_INSN)
3532 for (i = 0; i < n_spills; i++)
3533 if (call_used_regs[spill_regs[i]])
3535 reg_reloaded_contents[i] = -1;
3536 reg_reloaded_insn[i] = 0;
3539 /* In case registers overlap, allow certain insns to invalidate
3540 particular hard registers. */
3542 #ifdef INSN_CLOBBERS_REGNO_P
3543 for (i = 0 ; i < n_spills ; i++)
3544 if (INSN_CLOBBERS_REGNO_P (insn, spill_regs[i]))
3546 reg_reloaded_contents[i] = -1;
3547 reg_reloaded_insn[i] = 0;
3559 /* Discard all record of any value reloaded from X,
3560 or reloaded in X from someplace else;
3561 unless X is an output reload reg of the current insn.
3563 X may be a hard reg (the reload reg)
3564 or it may be a pseudo reg that was reloaded from. */
3567 forget_old_reloads_1 (x)
3574 /* note_stores does give us subregs of hard regs. */
3575 while (GET_CODE (x) == SUBREG)
3577 offset += SUBREG_WORD (x);
3581 if (GET_CODE (x) != REG)
3584 regno = REGNO (x) + offset;
3586 if (regno >= FIRST_PSEUDO_REGISTER)
3591 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
3592 /* Storing into a spilled-reg invalidates its contents.
3593 This can happen if a block-local pseudo is allocated to that reg
3594 and it wasn't spilled because this block's total need is 0.
3595 Then some insn might have an optional reload and use this reg. */
3596 for (i = 0; i < nr; i++)
3597 if (spill_reg_order[regno + i] >= 0
3598 /* But don't do this if the reg actually serves as an output
3599 reload reg in the current instruction. */
3601 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)))
3603 reg_reloaded_contents[spill_reg_order[regno + i]] = -1;
3604 reg_reloaded_insn[spill_reg_order[regno + i]] = 0;
3608 /* Since value of X has changed,
3609 forget any value previously copied from it. */
3612 /* But don't forget a copy if this is the output reload
3613 that establishes the copy's validity. */
3614 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
3615 reg_last_reload_reg[regno + nr] = 0;
3618 /* For each reload, the mode of the reload register. */
3619 static enum machine_mode reload_mode[MAX_RELOADS];
3621 /* For each reload, the largest number of registers it will require. */
3622 static int reload_nregs[MAX_RELOADS];
3624 /* Comparison function for qsort to decide which of two reloads
3625 should be handled first. *P1 and *P2 are the reload numbers. */
3628 reload_reg_class_lower (p1, p2)
3631 register int r1 = *p1, r2 = *p2;
3634 /* Consider required reloads before optional ones. */
3635 t = reload_optional[r1] - reload_optional[r2];
3639 /* Count all solitary classes before non-solitary ones. */
3640 t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
3641 - (reg_class_size[(int) reload_reg_class[r1]] == 1));
3645 /* Aside from solitaires, consider all multi-reg groups first. */
3646 t = reload_nregs[r2] - reload_nregs[r1];
3650 /* Consider reloads in order of increasing reg-class number. */
3651 t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
3655 /* If reloads are equally urgent, sort by reload number,
3656 so that the results of qsort leave nothing to chance. */
3660 /* The following HARD_REG_SETs indicate when each hard register is
3661 used for a reload of various parts of the current insn. */
3663 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
3664 static HARD_REG_SET reload_reg_used;
3665 /* If reg is in use for a RELOAD_FOR_INPUT_RELOAD_ADDRESS reload. */
3666 static HARD_REG_SET reload_reg_used_in_input_addr;
3667 /* If reg is in use for a RELOAD_FOR_OUTPUT_RELOAD_ADDRESS reload. */
3668 static HARD_REG_SET reload_reg_used_in_output_addr;
3669 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
3670 static HARD_REG_SET reload_reg_used_in_op_addr;
3671 /* If reg is in use for a RELOAD_FOR_INPUT reload. */
3672 static HARD_REG_SET reload_reg_used_in_input;
3673 /* If reg is in use for a RELOAD_FOR_OUTPUT reload. */
3674 static HARD_REG_SET reload_reg_used_in_output;
3676 /* If reg is in use as a reload reg for any sort of reload. */
3677 static HARD_REG_SET reload_reg_used_at_all;
3679 /* Mark reg REGNO as in use for a reload of the sort spec'd by WHEN_NEEDED.
3680 MODE is used to indicate how many consecutive regs are actually used. */
3683 mark_reload_reg_in_use (regno, when_needed, mode)
3685 enum reload_when_needed when_needed;
3686 enum machine_mode mode;
3688 int nregs = HARD_REGNO_NREGS (regno, mode);
3691 for (i = regno; i < nregs + regno; i++)
3693 switch (when_needed)
3696 SET_HARD_REG_BIT (reload_reg_used, i);
3699 case RELOAD_FOR_INPUT_RELOAD_ADDRESS:
3700 SET_HARD_REG_BIT (reload_reg_used_in_input_addr, i);
3703 case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS:
3704 SET_HARD_REG_BIT (reload_reg_used_in_output_addr, i);
3707 case RELOAD_FOR_OPERAND_ADDRESS:
3708 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
3711 case RELOAD_FOR_INPUT:
3712 SET_HARD_REG_BIT (reload_reg_used_in_input, i);
3715 case RELOAD_FOR_OUTPUT:
3716 SET_HARD_REG_BIT (reload_reg_used_in_output, i);
3720 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
3724 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
3725 specified by WHEN_NEEDED. */
3728 reload_reg_free_p (regno, when_needed)
3730 enum reload_when_needed when_needed;
3732 /* In use for a RELOAD_OTHER means it's not available for anything. */
3733 if (TEST_HARD_REG_BIT (reload_reg_used, regno))
3735 switch (when_needed)
3738 /* In use for anything means not available for a RELOAD_OTHER. */
3739 return ! TEST_HARD_REG_BIT (reload_reg_used_at_all, regno);
3741 /* The other kinds of use can sometimes share a register. */
3742 case RELOAD_FOR_INPUT:
3743 return (! TEST_HARD_REG_BIT (reload_reg_used_in_input, regno)
3744 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
3745 && ! TEST_HARD_REG_BIT (reload_reg_used_in_input_addr, regno));
3746 case RELOAD_FOR_INPUT_RELOAD_ADDRESS:
3747 return (! TEST_HARD_REG_BIT (reload_reg_used_in_input_addr, regno)
3748 && ! TEST_HARD_REG_BIT (reload_reg_used_in_input, regno));
3749 case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS:
3750 return (! TEST_HARD_REG_BIT (reload_reg_used_in_output_addr, regno)
3751 && ! TEST_HARD_REG_BIT (reload_reg_used_in_output, regno));
3752 case RELOAD_FOR_OPERAND_ADDRESS:
3753 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
3754 && ! TEST_HARD_REG_BIT (reload_reg_used_in_input, regno)
3755 && ! TEST_HARD_REG_BIT (reload_reg_used_in_output, regno));
3756 case RELOAD_FOR_OUTPUT:
3757 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
3758 && ! TEST_HARD_REG_BIT (reload_reg_used_in_output_addr, regno)
3759 && ! TEST_HARD_REG_BIT (reload_reg_used_in_output, regno));
3764 /* Return 1 if the value in reload reg REGNO, as used by a reload
3765 needed for the part of the insn specified by WHEN_NEEDED,
3766 is not in use for a reload in any prior part of the insn.
3768 We can assume that the reload reg was already tested for availability
3769 at the time it is needed, and we should not check this again,
3770 in case the reg has already been marked in use. */
3773 reload_reg_free_before_p (regno, when_needed)
3775 enum reload_when_needed when_needed;
3777 switch (when_needed)
3780 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
3781 its use starts from the beginning, so nothing can use it earlier. */
3784 /* If this use is for part of the insn,
3785 check the reg is not in use for any prior part. */
3786 case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS:
3787 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
3789 case RELOAD_FOR_OUTPUT:
3790 if (TEST_HARD_REG_BIT (reload_reg_used_in_input, regno))
3792 case RELOAD_FOR_OPERAND_ADDRESS:
3793 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr, regno))
3795 case RELOAD_FOR_INPUT_RELOAD_ADDRESS:
3796 case RELOAD_FOR_INPUT:
3802 /* Return 1 if the value in reload reg REGNO, as used by a reload
3803 needed for the part of the insn specified by WHEN_NEEDED,
3804 is still available in REGNO at the end of the insn.
3806 We can assume that the reload reg was already tested for availability
3807 at the time it is needed, and we should not check this again,
3808 in case the reg has already been marked in use. */
3811 reload_reg_reaches_end_p (regno, when_needed)
3813 enum reload_when_needed when_needed;
3815 switch (when_needed)
3818 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
3819 its value must reach the end. */
3822 /* If this use is for part of the insn,
3823 its value reaches if no subsequent part uses the same register. */
3824 case RELOAD_FOR_INPUT_RELOAD_ADDRESS:
3825 case RELOAD_FOR_INPUT:
3826 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
3827 || TEST_HARD_REG_BIT (reload_reg_used_in_output, regno))
3829 case RELOAD_FOR_OPERAND_ADDRESS:
3830 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr, regno))
3832 case RELOAD_FOR_OUTPUT:
3833 case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS:
3839 /* Vector of reload-numbers showing the order in which the reloads should
3841 short reload_order[MAX_RELOADS];
3843 /* Indexed by reload number, 1 if incoming value
3844 inherited from previous insns. */
3845 char reload_inherited[MAX_RELOADS];
3847 /* For an inherited reload, this is the insn the reload was inherited from,
3848 if we know it. Otherwise, this is 0. */
3849 rtx reload_inheritance_insn[MAX_RELOADS];
3851 /* If non-zero, this is a place to get the value of the reload,
3852 rather than using reload_in. */
3853 rtx reload_override_in[MAX_RELOADS];
3855 /* For each reload, the index in spill_regs of the spill register used,
3856 or -1 if we did not need one of the spill registers for this reload. */
3857 int reload_spill_index[MAX_RELOADS];
3859 /* Index of last register assigned as a spill register. We allocate in
3860 a round-robin fashio. */
3862 static last_spill_reg = 0;
3864 /* Find a spill register to use as a reload register for reload R.
3865 LAST_RELOAD is non-zero if this is the last reload for the insn being
3868 Set reload_reg_rtx[R] to the register allocated.
3870 If NOERROR is nonzero, we return 1 if successful,
3871 or 0 if we couldn't find a spill reg and we didn't change anything. */
3874 allocate_reload_reg (r, insn, last_reload, noerror)
3886 /* If we put this reload ahead, thinking it is a group,
3887 then insist on finding a group. Otherwise we can grab a
3888 reg that some other reload needs.
3889 (That can happen when we have a 68000 DATA_OR_FP_REG
3890 which is a group of data regs or one fp reg.)
3891 We need not be so restrictive if there are no more reloads
3894 ??? Really it would be nicer to have smarter handling
3895 for that kind of reg class, where a problem like this is normal.
3896 Perhaps those classes should be avoided for reloading
3897 by use of more alternatives. */
3899 int force_group = reload_nregs[r] > 1 && ! last_reload;
3901 /* If we want a single register and haven't yet found one,
3902 take any reg in the right class and not in use.
3903 If we want a consecutive group, here is where we look for it.
3905 We use two passes so we can first look for reload regs to
3906 reuse, which are already in use for other reloads in this insn,
3907 and only then use additional registers.
3908 I think that maximizing reuse is needed to make sure we don't
3909 run out of reload regs. Suppose we have three reloads, and
3910 reloads A and B can share regs. These need two regs.
3911 Suppose A and B are given different regs.
3912 That leaves none for C. */
3913 for (pass = 0; pass < 2; pass++)
3915 /* I is the index in spill_regs.
3916 We advance it round-robin between insns to use all spill regs
3917 equally, so that inherited reloads have a chance
3918 of leapfrogging each other. */
3920 for (count = 0, i = last_spill_reg; count < n_spills; count++)
3922 int class = (int) reload_reg_class[r];
3924 i = (i + 1) % n_spills;
3926 if (reload_reg_free_p (spill_regs[i], reload_when_needed[r])
3927 && TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
3928 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
3929 /* Look first for regs to share, then for unshared. */
3930 && (pass || TEST_HARD_REG_BIT (reload_reg_used_at_all,
3933 int nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
3934 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
3935 (on 68000) got us two FP regs. If NR is 1,
3936 we would reject both of them. */
3938 nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
3939 /* If we need only one reg, we have already won. */
3942 /* But reject a single reg if we demand a group. */
3947 /* Otherwise check that as many consecutive regs as we need
3949 Also, don't use for a group registers that are
3950 needed for nongroups. */
3951 if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
3954 regno = spill_regs[i] + nr - 1;
3955 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
3956 && spill_reg_order[regno] >= 0
3957 && reload_reg_free_p (regno, reload_when_needed[r])
3958 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
3968 /* If we found something on pass 1, omit pass 2. */
3969 if (count < n_spills)
3973 /* We should have found a spill register by now. */
3974 if (count == n_spills)
3983 /* Mark as in use for this insn the reload regs we use for this. */
3984 mark_reload_reg_in_use (spill_regs[i], reload_when_needed[r],
3987 new = spill_reg_rtx[i];
3989 if (new == 0 || GET_MODE (new) != reload_mode[r])
3990 spill_reg_rtx[i] = new = gen_rtx (REG, reload_mode[r], spill_regs[i]);
3992 reload_reg_rtx[r] = new;
3993 reload_spill_index[r] = i;
3994 regno = true_regnum (new);
3996 /* Detect when the reload reg can't hold the reload mode.
3997 This used to be one `if', but Sequent compiler can't handle that. */
3998 if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
4000 enum machine_mode test_mode = VOIDmode;
4002 test_mode = GET_MODE (reload_in[r]);
4003 /* If reload_in[r] has VOIDmode, it means we will load it
4004 in whatever mode the reload reg has: to wit, reload_mode[r].
4005 We have already tested that for validity. */
4006 /* Aside from that, we need to test that the expressions
4007 to reload from or into have modes which are valid for this
4008 reload register. Otherwise the reload insns would be invalid. */
4009 if (! (reload_in[r] != 0 && test_mode != VOIDmode
4010 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
4011 if (! (reload_out[r] != 0
4012 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
4013 /* The reg is OK. */
4017 /* The reg is not OK. */
4021 if (asm_noperands (PATTERN (insn)) < 0)
4022 /* It's the compiler's fault. */
4025 /* It's the user's fault; the operand's mode and constraint
4026 don't match. Disable this reload so we don't crash in final. */
4027 error_for_asm (insn,
4028 "`asm' operand constraint incompatible with operand size");
4031 reload_reg_rtx[r] = 0;
4032 reload_optional[r] = 1;
4033 reload_secondary_p[r] = 1;
4038 /* Assign hard reg targets for the pseudo-registers we must reload
4039 into hard regs for this insn.
4040 Also output the instructions to copy them in and out of the hard regs.
4042 For machines with register classes, we are responsible for
4043 finding a reload reg in the proper class. */
4046 choose_reload_regs (insn, avoid_return_reg)
4048 /* This argument is currently ignored. */
4049 rtx avoid_return_reg;
4052 int max_group_size = 1;
4053 enum reg_class group_class = NO_REGS;
4056 rtx save_reload_reg_rtx[MAX_RELOADS];
4057 char save_reload_inherited[MAX_RELOADS];
4058 rtx save_reload_inheritance_insn[MAX_RELOADS];
4059 rtx save_reload_override_in[MAX_RELOADS];
4060 int save_reload_spill_index[MAX_RELOADS];
4061 HARD_REG_SET save_reload_reg_used;
4062 HARD_REG_SET save_reload_reg_used_in_input_addr;
4063 HARD_REG_SET save_reload_reg_used_in_output_addr;
4064 HARD_REG_SET save_reload_reg_used_in_op_addr;
4065 HARD_REG_SET save_reload_reg_used_in_input;
4066 HARD_REG_SET save_reload_reg_used_in_output;
4067 HARD_REG_SET save_reload_reg_used_at_all;
4069 bzero (reload_inherited, MAX_RELOADS);
4070 bzero (reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
4071 bzero (reload_override_in, MAX_RELOADS * sizeof (rtx));
4073 CLEAR_HARD_REG_SET (reload_reg_used);
4074 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
4075 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr);
4076 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr);
4077 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
4078 CLEAR_HARD_REG_SET (reload_reg_used_in_output);
4079 CLEAR_HARD_REG_SET (reload_reg_used_in_input);
4081 /* Distinguish output-only and input-only reloads
4082 because they can overlap with other things. */
4083 for (j = 0; j < n_reloads; j++)
4084 if (reload_when_needed[j] == RELOAD_OTHER
4085 && ! reload_needed_for_multiple[j])
4087 if (reload_in[j] == 0)
4089 /* But earlyclobber operands must stay as RELOAD_OTHER. */
4090 for (i = 0; i < n_earlyclobbers; i++)
4091 if (rtx_equal_p (reload_out[j], reload_earlyclobbers[i]))
4093 if (i == n_earlyclobbers)
4094 reload_when_needed[j] = RELOAD_FOR_OUTPUT;
4096 if (reload_out[j] == 0)
4097 reload_when_needed[j] = RELOAD_FOR_INPUT;
4099 if (reload_secondary_reload[j] >= 0
4100 && ! reload_needed_for_multiple[reload_secondary_reload[j]])
4101 reload_when_needed[reload_secondary_reload[j]]
4102 = reload_when_needed[j];
4105 #ifdef SMALL_REGISTER_CLASSES
4106 /* Don't bother with avoiding the return reg
4107 if we have no mandatory reload that could use it. */
4108 if (avoid_return_reg)
4111 int regno = REGNO (avoid_return_reg);
4113 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
4116 for (r = regno; r < regno + nregs; r++)
4117 if (spill_reg_order[r] >= 0)
4118 for (j = 0; j < n_reloads; j++)
4119 if (!reload_optional[j] && reload_reg_rtx[j] == 0
4120 && (reload_in[j] != 0 || reload_out[j] != 0
4121 || reload_secondary_p[j])
4123 TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[j]], r))
4126 avoid_return_reg = 0;
4128 #endif /* SMALL_REGISTER_CLASSES */
4130 #if 0 /* Not needed, now that we can always retry without inheritance. */
4131 /* See if we have more mandatory reloads than spill regs.
4132 If so, then we cannot risk optimizations that could prevent
4133 reloads from sharing one spill register.
4135 Since we will try finding a better register than reload_reg_rtx
4136 unless it is equal to reload_in or reload_out, count such reloads. */
4140 #ifdef SMALL_REGISTER_CLASSES
4141 int tem = (avoid_return_reg != 0);
4143 for (j = 0; j < n_reloads; j++)
4144 if (! reload_optional[j]
4145 && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
4146 && (reload_reg_rtx[j] == 0
4147 || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
4148 && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
4155 #ifdef SMALL_REGISTER_CLASSES
4156 /* Don't use the subroutine call return reg for a reload
4157 if we are supposed to avoid it. */
4158 if (avoid_return_reg)
4160 int regno = REGNO (avoid_return_reg);
4162 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
4165 for (r = regno; r < regno + nregs; r++)
4166 if (spill_reg_order[r] >= 0)
4167 SET_HARD_REG_BIT (reload_reg_used, r);
4169 #endif /* SMALL_REGISTER_CLASSES */
4171 /* In order to be certain of getting the registers we need,
4172 we must sort the reloads into order of increasing register class.
4173 Then our grabbing of reload registers will parallel the process
4174 that provided the reload registers.
4176 Also note whether any of the reloads wants a consecutive group of regs.
4177 If so, record the maximum size of the group desired and what
4178 register class contains all the groups needed by this insn. */
4180 for (j = 0; j < n_reloads; j++)
4182 reload_order[j] = j;
4183 reload_spill_index[j] = -1;
4186 = (reload_strict_low[j] && reload_out[j]
4187 ? GET_MODE (SUBREG_REG (reload_out[j]))
4188 : (reload_inmode[j] == VOIDmode
4189 || (GET_MODE_SIZE (reload_outmode[j])
4190 > GET_MODE_SIZE (reload_inmode[j])))
4191 ? reload_outmode[j] : reload_inmode[j]);
4193 reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
4195 if (reload_nregs[j] > 1)
4197 max_group_size = MAX (reload_nregs[j], max_group_size);
4198 group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
4201 /* If we have already decided to use a certain register,
4202 don't use it in another way. */
4203 if (reload_reg_rtx[j])
4204 mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]),
4205 reload_when_needed[j], reload_mode[j]);
4209 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
4211 bcopy (reload_reg_rtx, save_reload_reg_rtx, sizeof reload_reg_rtx);
4212 bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
4213 bcopy (reload_inheritance_insn, save_reload_inheritance_insn,
4214 sizeof reload_inheritance_insn);
4215 bcopy (reload_override_in, save_reload_override_in,
4216 sizeof reload_override_in);
4217 bcopy (reload_spill_index, save_reload_spill_index,
4218 sizeof reload_spill_index);
4219 COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
4220 COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
4221 COPY_HARD_REG_SET (save_reload_reg_used_in_output,
4222 reload_reg_used_in_output);
4223 COPY_HARD_REG_SET (save_reload_reg_used_in_input,
4224 reload_reg_used_in_input);
4225 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr,
4226 reload_reg_used_in_input_addr);
4227 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr,
4228 reload_reg_used_in_output_addr);
4229 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
4230 reload_reg_used_in_op_addr);
4232 /* Try first with inheritance, then turning it off. */
4234 for (inheritance = 1; inheritance >= 0; inheritance--)
4236 /* Process the reloads in order of preference just found.
4237 Beyond this point, subregs can be found in reload_reg_rtx.
4239 This used to look for an existing reloaded home for all
4240 of the reloads, and only then perform any new reloads.
4241 But that could lose if the reloads were done out of reg-class order
4242 because a later reload with a looser constraint might have an old
4243 home in a register needed by an earlier reload with a tighter constraint.
4245 To solve this, we make two passes over the reloads, in the order
4246 described above. In the first pass we try to inherit a reload
4247 from a previous insn. If there is a later reload that needs a
4248 class that is a proper subset of the class being processed, we must
4249 also allocate a spill register during the first pass.
4251 Then make a second pass over the reloads to allocate any reloads
4252 that haven't been given registers yet. */
4254 for (j = 0; j < n_reloads; j++)
4256 register int r = reload_order[j];
4258 /* Ignore reloads that got marked inoperative. */
4259 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
4262 /* If find_reloads chose a to use reload_in or reload_out as a reload
4263 register, we don't need to chose one. Otherwise, try even if it found
4264 one since we might save an insn if we find the value lying around. */
4265 if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
4266 && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
4267 || rtx_equal_p (reload_out[r], reload_reg_rtx[r])))
4270 #if 0 /* No longer needed for correct operation.
4271 It might give better code, or might not; worth an experiment? */
4272 /* If this is an optional reload, we can't inherit from earlier insns
4273 until we are sure that any non-optional reloads have been allocated.
4274 The following code takes advantage of the fact that optional reloads
4275 are at the end of reload_order. */
4276 if (reload_optional[r] != 0)
4277 for (i = 0; i < j; i++)
4278 if ((reload_out[reload_order[i]] != 0
4279 || reload_in[reload_order[i]] != 0
4280 || reload_secondary_p[reload_order[i]])
4281 && ! reload_optional[reload_order[i]]
4282 && reload_reg_rtx[reload_order[i]] == 0)
4283 allocate_reload_reg (reload_order[i], insn, 0, inheritance);
4286 /* First see if this pseudo is already available as reloaded
4287 for a previous insn. We cannot try to inherit for reloads
4288 that are smaller than the maximum number of registers needed
4289 for groups unless the register we would allocate cannot be used
4292 We could check here to see if this is a secondary reload for
4293 an object that is already in a register of the desired class.
4294 This would avoid the need for the secondary reload register.
4295 But this is complex because we can't easily determine what
4296 objects might want to be loaded via this reload. So let a register
4297 be allocated here. In `emit_reload_insns' we suppress one of the
4298 loads in the case described above. */
4302 register int regno = -1;
4304 if (reload_in[r] == 0)
4306 else if (GET_CODE (reload_in[r]) == REG)
4307 regno = REGNO (reload_in[r]);
4308 else if (GET_CODE (reload_in_reg[r]) == REG)
4309 regno = REGNO (reload_in_reg[r]);
4311 /* This won't work, since REGNO can be a pseudo reg number.
4312 Also, it takes much more hair to keep track of all the things
4313 that can invalidate an inherited reload of part of a pseudoreg. */
4314 else if (GET_CODE (reload_in[r]) == SUBREG
4315 && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
4316 regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
4319 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
4321 i = spill_reg_order[REGNO (reg_last_reload_reg[regno])];
4323 if (reg_reloaded_contents[i] == regno
4324 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
4325 && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
4327 && (reload_nregs[r] == max_group_size
4328 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
4330 && reload_reg_free_p (spill_regs[i], reload_when_needed[r])
4331 && reload_reg_free_before_p (spill_regs[i],
4332 reload_when_needed[r]))
4334 /* If a group is needed, verify that all the subsequent
4335 registers still have their values intact. */
4337 = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
4340 for (k = 1; k < nr; k++)
4341 if (reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
4347 /* Mark the register as in use for this part of
4349 mark_reload_reg_in_use (spill_regs[i],
4350 reload_when_needed[r],
4352 reload_reg_rtx[r] = reg_last_reload_reg[regno];
4353 reload_inherited[r] = 1;
4354 reload_inheritance_insn[r] = reg_reloaded_insn[i];
4355 reload_spill_index[r] = i;
4361 /* Here's another way to see if the value is already lying around. */
4363 && reload_in[r] != 0
4364 && ! reload_inherited[r]
4365 && reload_out[r] == 0
4366 && (CONSTANT_P (reload_in[r])
4367 || GET_CODE (reload_in[r]) == PLUS
4368 || GET_CODE (reload_in[r]) == REG
4369 || GET_CODE (reload_in[r]) == MEM)
4370 && (reload_nregs[r] == max_group_size
4371 || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
4374 = find_equiv_reg (reload_in[r], insn, reload_reg_class[r],
4375 -1, NULL_PTR, 0, reload_mode[r]);
4380 if (GET_CODE (equiv) == REG)
4381 regno = REGNO (equiv);
4382 else if (GET_CODE (equiv) == SUBREG)
4384 regno = REGNO (SUBREG_REG (equiv));
4385 if (regno < FIRST_PSEUDO_REGISTER)
4386 regno += SUBREG_WORD (equiv);
4392 /* If we found a spill reg, reject it unless it is free
4393 and of the desired class. */
4395 && ((spill_reg_order[regno] >= 0
4396 && ! reload_reg_free_before_p (regno,
4397 reload_when_needed[r]))
4398 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
4402 if (equiv != 0 && TEST_HARD_REG_BIT (reload_reg_used_at_all, regno))
4405 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
4408 /* We found a register that contains the value we need.
4409 If this register is the same as an `earlyclobber' operand
4410 of the current insn, just mark it as a place to reload from
4411 since we can't use it as the reload register itself. */
4414 for (i = 0; i < n_earlyclobbers; i++)
4415 if (reg_overlap_mentioned_for_reload_p (equiv,
4416 reload_earlyclobbers[i]))
4418 reload_override_in[r] = equiv;
4423 /* JRV: If the equiv register we have found is explicitly
4424 clobbered in the current insn, mark but don't use, as above. */
4426 if (equiv != 0 && regno_clobbered_p (regno, insn))
4428 reload_override_in[r] = equiv;
4432 /* If we found an equivalent reg, say no code need be generated
4433 to load it, and use it as our reload reg. */
4434 if (equiv != 0 && regno != FRAME_POINTER_REGNUM)
4436 reload_reg_rtx[r] = equiv;
4437 reload_inherited[r] = 1;
4438 /* If it is a spill reg,
4439 mark the spill reg as in use for this insn. */
4440 i = spill_reg_order[regno];
4442 mark_reload_reg_in_use (regno, reload_when_needed[r],
4447 /* If we found a register to use already, or if this is an optional
4448 reload, we are done. */
4449 if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
4452 #if 0 /* No longer needed for correct operation. Might or might not
4453 give better code on the average. Want to experiment? */
4455 /* See if there is a later reload that has a class different from our
4456 class that intersects our class or that requires less register
4457 than our reload. If so, we must allocate a register to this
4458 reload now, since that reload might inherit a previous reload
4459 and take the only available register in our class. Don't do this
4460 for optional reloads since they will force all previous reloads
4461 to be allocated. Also don't do this for reloads that have been
4464 for (i = j + 1; i < n_reloads; i++)
4466 int s = reload_order[i];
4468 if ((reload_in[s] == 0 && reload_out[s] == 0
4469 && ! reload_secondary_p[s])
4470 || reload_optional[s])
4473 if ((reload_reg_class[s] != reload_reg_class[r]
4474 && reg_classes_intersect_p (reload_reg_class[r],
4475 reload_reg_class[s]))
4476 || reload_nregs[s] < reload_nregs[r])
4483 allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance);
4487 /* Now allocate reload registers for anything non-optional that
4488 didn't get one yet. */
4489 for (j = 0; j < n_reloads; j++)
4491 register int r = reload_order[j];
4493 /* Ignore reloads that got marked inoperative. */
4494 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
4497 /* Skip reloads that already have a register allocated or are
4499 if (reload_reg_rtx[r] != 0 || reload_optional[r])
4502 if (! allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance))
4506 /* If that loop got all the way, we have won. */
4511 /* Loop around and try without any inheritance. */
4512 /* First undo everything done by the failed attempt
4513 to allocate with inheritance. */
4514 bcopy (save_reload_reg_rtx, reload_reg_rtx, sizeof reload_reg_rtx);
4515 bcopy (save_reload_inherited, reload_inherited, sizeof reload_inherited);
4516 bcopy (save_reload_inheritance_insn, reload_inheritance_insn,
4517 sizeof reload_inheritance_insn);
4518 bcopy (save_reload_override_in, reload_override_in,
4519 sizeof reload_override_in);
4520 bcopy (save_reload_spill_index, reload_spill_index,
4521 sizeof reload_spill_index);
4522 COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
4523 COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
4524 COPY_HARD_REG_SET (reload_reg_used_in_input,
4525 save_reload_reg_used_in_input);
4526 COPY_HARD_REG_SET (reload_reg_used_in_output,
4527 save_reload_reg_used_in_output);
4528 COPY_HARD_REG_SET (reload_reg_used_in_input_addr,
4529 save_reload_reg_used_in_input_addr);
4530 COPY_HARD_REG_SET (reload_reg_used_in_output_addr,
4531 save_reload_reg_used_in_output_addr);
4532 COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
4533 save_reload_reg_used_in_op_addr);
4536 /* If we thought we could inherit a reload, because it seemed that
4537 nothing else wanted the same reload register earlier in the insn,
4538 verify that assumption, now that all reloads have been assigned. */
4540 for (j = 0; j < n_reloads; j++)
4542 register int r = reload_order[j];
4544 if (reload_inherited[r] && reload_reg_rtx[r] != 0
4545 && ! reload_reg_free_before_p (true_regnum (reload_reg_rtx[r]),
4546 reload_when_needed[r]))
4547 reload_inherited[r] = 0;
4549 /* If we found a better place to reload from,
4550 validate it in the same fashion, if it is a reload reg. */
4551 if (reload_override_in[r]
4552 && (GET_CODE (reload_override_in[r]) == REG
4553 || GET_CODE (reload_override_in[r]) == SUBREG))
4555 int regno = true_regnum (reload_override_in[r]);
4556 if (spill_reg_order[regno] >= 0
4557 && ! reload_reg_free_before_p (regno, reload_when_needed[r]))
4558 reload_override_in[r] = 0;
4562 /* Now that reload_override_in is known valid,
4563 actually override reload_in. */
4564 for (j = 0; j < n_reloads; j++)
4565 if (reload_override_in[j])
4566 reload_in[j] = reload_override_in[j];
4568 /* If this reload won't be done because it has been cancelled or is
4569 optional and not inherited, clear reload_reg_rtx so other
4570 routines (such as subst_reloads) don't get confused. */
4571 for (j = 0; j < n_reloads; j++)
4572 if ((reload_optional[j] && ! reload_inherited[j])
4573 || (reload_in[j] == 0 && reload_out[j] == 0
4574 && ! reload_secondary_p[j]))
4575 reload_reg_rtx[j] = 0;
4577 /* Record which pseudos and which spill regs have output reloads. */
4578 for (j = 0; j < n_reloads; j++)
4580 register int r = reload_order[j];
4582 i = reload_spill_index[r];
4584 /* I is nonneg if this reload used one of the spill regs.
4585 If reload_reg_rtx[r] is 0, this is an optional reload
4586 that we opted to ignore. */
4587 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG
4588 && reload_reg_rtx[r] != 0)
4590 register int nregno = REGNO (reload_out[r]);
4591 int nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
4595 reg_has_output_reload[nregno + nr] = 1;
4597 SET_HARD_REG_BIT (reg_is_output_reload, spill_regs[i] + nr);
4600 if (reload_when_needed[r] != RELOAD_OTHER
4601 && reload_when_needed[r] != RELOAD_FOR_OUTPUT)
4607 /* Output insns to reload values in and out of the chosen reload regs. */
4610 emit_reload_insns (insn)
4614 rtx following_insn = NEXT_INSN (insn);
4615 rtx before_insn = insn;
4616 rtx first_output_reload_insn = NEXT_INSN (insn);
4617 rtx first_other_reload_insn = insn;
4618 rtx first_operand_address_reload_insn = insn;
4620 /* Values to be put in spill_reg_store are put here first. */
4621 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
4623 /* If this is a CALL_INSN preceded by USE insns, any reload insns
4624 must go in front of the first USE insn, not in front of INSN. */
4626 if (GET_CODE (insn) == CALL_INSN && GET_CODE (PREV_INSN (insn)) == INSN
4627 && GET_CODE (PATTERN (PREV_INSN (insn))) == USE)
4628 while (GET_CODE (PREV_INSN (before_insn)) == INSN
4629 && GET_CODE (PATTERN (PREV_INSN (before_insn))) == USE)
4630 first_other_reload_insn = first_operand_address_reload_insn
4631 = before_insn = PREV_INSN (before_insn);
4633 /* Now output the instructions to copy the data into and out of the
4634 reload registers. Do these in the order that the reloads were reported,
4635 since reloads of base and index registers precede reloads of operands
4636 and the operands may need the base and index registers reloaded. */
4638 for (j = 0; j < n_reloads; j++)
4641 rtx oldequiv_reg = 0;
4642 rtx this_reload_insn = 0;
4646 if (old != 0 && ! reload_inherited[j]
4647 && ! rtx_equal_p (reload_reg_rtx[j], old)
4648 && reload_reg_rtx[j] != 0)
4650 register rtx reloadreg = reload_reg_rtx[j];
4652 enum machine_mode mode;
4656 /* Determine the mode to reload in.
4657 This is very tricky because we have three to choose from.
4658 There is the mode the insn operand wants (reload_inmode[J]).
4659 There is the mode of the reload register RELOADREG.
4660 There is the intrinsic mode of the operand, which we could find
4661 by stripping some SUBREGs.
4662 It turns out that RELOADREG's mode is irrelevant:
4663 we can change that arbitrarily.
4665 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
4666 then the reload reg may not support QImode moves, so use SImode.
4667 If foo is in memory due to spilling a pseudo reg, this is safe,
4668 because the QImode value is in the least significant part of a
4669 slot big enough for a SImode. If foo is some other sort of
4670 memory reference, then it is impossible to reload this case,
4671 so previous passes had better make sure this never happens.
4673 Then consider a one-word union which has SImode and one of its
4674 members is a float, being fetched as (SUBREG:SF union:SI).
4675 We must fetch that as SFmode because we could be loading into
4676 a float-only register. In this case OLD's mode is correct.
4678 Consider an immediate integer: it has VOIDmode. Here we need
4679 to get a mode from something else.
4681 In some cases, there is a fourth mode, the operand's
4682 containing mode. If the insn specifies a containing mode for
4683 this operand, it overrides all others.
4685 I am not sure whether the algorithm here is always right,
4686 but it does the right things in those cases. */
4688 mode = GET_MODE (old);
4689 if (mode == VOIDmode)
4690 mode = reload_inmode[j];
4691 if (reload_strict_low[j])
4692 mode = GET_MODE (SUBREG_REG (reload_in[j]));
4694 #ifdef SECONDARY_INPUT_RELOAD_CLASS
4695 /* If we need a secondary register for this operation, see if
4696 the value is already in a register in that class. Don't
4697 do this if the secondary register will be used as a scratch
4700 if (reload_secondary_reload[j] >= 0
4701 && reload_secondary_icode[j] == CODE_FOR_nothing)
4703 = find_equiv_reg (old, insn,
4704 reload_reg_class[reload_secondary_reload[j]],
4705 -1, NULL_PTR, 0, mode);
4708 /* If reloading from memory, see if there is a register
4709 that already holds the same value. If so, reload from there.
4710 We can pass 0 as the reload_reg_p argument because
4711 any other reload has either already been emitted,
4712 in which case find_equiv_reg will see the reload-insn,
4713 or has yet to be emitted, in which case it doesn't matter
4714 because we will use this equiv reg right away. */
4717 && (GET_CODE (old) == MEM
4718 || (GET_CODE (old) == REG
4719 && REGNO (old) >= FIRST_PSEUDO_REGISTER
4720 && reg_renumber[REGNO (old)] < 0)))
4721 oldequiv = find_equiv_reg (old, insn, GENERAL_REGS,
4722 -1, NULL_PTR, 0, mode);
4726 int regno = true_regnum (oldequiv);
4728 /* If OLDEQUIV is a spill register, don't use it for this
4729 if any other reload needs it at an earlier stage of this insn
4730 or at this stage. */
4731 if (spill_reg_order[regno] >= 0
4732 && (! reload_reg_free_p (regno, reload_when_needed[j])
4733 || ! reload_reg_free_before_p (regno,
4734 reload_when_needed[j])))
4737 /* If OLDEQUIV is not a spill register,
4738 don't use it if any other reload wants it. */
4739 if (spill_reg_order[regno] < 0)
4742 for (k = 0; k < n_reloads; k++)
4743 if (reload_reg_rtx[k] != 0 && k != j
4744 && reg_overlap_mentioned_for_reload_p (reload_reg_rtx[k],
4755 else if (GET_CODE (oldequiv) == REG)
4756 oldequiv_reg = oldequiv;
4757 else if (GET_CODE (oldequiv) == SUBREG)
4758 oldequiv_reg = SUBREG_REG (oldequiv);
4760 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
4761 then load RELOADREG from OLDEQUIV. */
4763 if (GET_MODE (reloadreg) != mode)
4764 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
4765 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
4766 oldequiv = SUBREG_REG (oldequiv);
4767 if (GET_MODE (oldequiv) != VOIDmode
4768 && mode != GET_MODE (oldequiv))
4769 oldequiv = gen_rtx (SUBREG, mode, oldequiv, 0);
4771 /* Decide where to put reload insn for this reload. */
4772 switch (reload_when_needed[j])
4774 case RELOAD_FOR_INPUT:
4776 where = first_operand_address_reload_insn;
4778 case RELOAD_FOR_INPUT_RELOAD_ADDRESS:
4779 where = first_other_reload_insn;
4781 case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS:
4782 where = first_output_reload_insn;
4784 case RELOAD_FOR_OPERAND_ADDRESS:
4785 where = before_insn;
4790 /* Auto-increment addresses must be reloaded in a special way. */
4791 if (GET_CODE (oldequiv) == POST_INC
4792 || GET_CODE (oldequiv) == POST_DEC
4793 || GET_CODE (oldequiv) == PRE_INC
4794 || GET_CODE (oldequiv) == PRE_DEC)
4796 /* We are not going to bother supporting the case where a
4797 incremented register can't be copied directly from
4798 OLDEQUIV since this seems highly unlikely. */
4799 if (reload_secondary_reload[j] >= 0)
4801 /* Prevent normal processing of this reload. */
4803 /* Output a special code sequence for this case. */
4805 = inc_for_reload (reloadreg, oldequiv, reload_inc[j], where);
4808 /* If we are reloading a pseudo-register that was set by the previous
4809 insn, see if we can get rid of that pseudo-register entirely
4810 by redirecting the previous insn into our reload register. */
4812 else if (optimize && GET_CODE (old) == REG
4813 && REGNO (old) >= FIRST_PSEUDO_REGISTER
4814 && dead_or_set_p (insn, old)
4815 /* This is unsafe if some other reload
4816 uses the same reg first. */
4817 && (reload_when_needed[j] == RELOAD_OTHER
4818 || reload_when_needed[j] == RELOAD_FOR_INPUT
4819 || reload_when_needed[j] == RELOAD_FOR_INPUT_RELOAD_ADDRESS))
4821 rtx temp = PREV_INSN (insn);
4822 while (temp && GET_CODE (temp) == NOTE)
4823 temp = PREV_INSN (temp);
4825 && GET_CODE (temp) == INSN
4826 && GET_CODE (PATTERN (temp)) == SET
4827 && SET_DEST (PATTERN (temp)) == old
4828 /* Make sure we can access insn_operand_constraint. */
4829 && asm_noperands (PATTERN (temp)) < 0
4830 /* This is unsafe if prev insn rejects our reload reg. */
4831 && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
4833 /* This is unsafe if operand occurs more than once in current
4834 insn. Perhaps some occurrences aren't reloaded. */
4835 && count_occurrences (PATTERN (insn), old) == 1
4836 /* Don't risk splitting a matching pair of operands. */
4837 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
4839 /* Store into the reload register instead of the pseudo. */
4840 SET_DEST (PATTERN (temp)) = reloadreg;
4841 /* If these are the only uses of the pseudo reg,
4842 pretend for GDB it lives in the reload reg we used. */
4843 if (reg_n_deaths[REGNO (old)] == 1
4844 && reg_n_sets[REGNO (old)] == 1)
4846 reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
4847 alter_reg (REGNO (old), -1);
4853 /* We can't do that, so output an insn to load RELOADREG.
4854 Keep them in the following order:
4855 all reloads for input reload addresses,
4856 all reloads for ordinary input operands,
4857 all reloads for addresses of non-reloaded operands,
4858 the insn being reloaded,
4859 all reloads for addresses of output reloads,
4860 the output reloads. */
4863 #ifdef SECONDARY_INPUT_RELOAD_CLASS
4864 rtx second_reload_reg = 0;
4865 enum insn_code icode;
4867 /* If we have a secondary reload, pick up the secondary register
4868 and icode, if any. If OLDEQUIV and OLD are different or
4869 if this is an in-out reload, recompute whether or not we
4870 still need a secondary register and what the icode should
4871 be. If we still need a secondary register and the class or
4872 icode is different, go back to reloading from OLD if using
4873 OLDEQUIV means that we got the wrong type of register. We
4874 cannot have different class or icode due to an in-out reload
4875 because we don't make such reloads when both the input and
4876 output need secondary reload registers. */
4878 if (reload_secondary_reload[j] >= 0)
4880 int secondary_reload = reload_secondary_reload[j];
4881 rtx real_oldequiv = oldequiv;
4884 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
4885 and similarly for OLD.
4886 See comments in find_secondary_reload in reload.c. */
4887 if (GET_CODE (oldequiv) == REG
4888 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
4889 && reg_equiv_mem[REGNO (oldequiv)] != 0)
4890 real_oldequiv = reg_equiv_mem[REGNO (oldequiv)];
4892 if (GET_CODE (old) == REG
4893 && REGNO (old) >= FIRST_PSEUDO_REGISTER
4894 && reg_equiv_mem[REGNO (old)] != 0)
4895 real_old = reg_equiv_mem[REGNO (old)];
4897 second_reload_reg = reload_reg_rtx[secondary_reload];
4898 icode = reload_secondary_icode[j];
4900 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
4901 || (reload_in[j] != 0 && reload_out[j] != 0))
4903 enum reg_class new_class
4904 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
4905 mode, real_oldequiv);
4907 if (new_class == NO_REGS)
4908 second_reload_reg = 0;
4911 enum insn_code new_icode;
4912 enum machine_mode new_mode;
4914 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
4915 REGNO (second_reload_reg)))
4916 oldequiv = old, real_oldequiv = real_old;
4919 new_icode = reload_in_optab[(int) mode];
4920 if (new_icode != CODE_FOR_nothing
4921 && ((insn_operand_predicate[(int) new_icode][0]
4922 && ! ((*insn_operand_predicate[(int) new_icode][0])
4924 || (insn_operand_predicate[(int) new_icode][1]
4925 && ! ((*insn_operand_predicate[(int) new_icode][1])
4926 (real_oldequiv, mode)))))
4927 new_icode = CODE_FOR_nothing;
4929 if (new_icode == CODE_FOR_nothing)
4932 new_mode = insn_operand_mode[new_icode][2];
4934 if (GET_MODE (second_reload_reg) != new_mode)
4936 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
4938 oldequiv = old, real_oldequiv = real_old;
4941 = gen_reg_rtx (REG, new_mode,
4942 REGNO (second_reload_reg));
4948 /* If we still need a secondary reload register, check
4949 to see if it is being used as a scratch or intermediate
4950 register and generate code appropriately. If we need
4951 a scratch register, use REAL_OLDEQUIV since the form of
4952 the insn may depend on the actual address if it is
4955 if (second_reload_reg)
4957 if (icode != CODE_FOR_nothing)
4959 reload_insn = emit_insn_before (GEN_FCN (icode)
4964 if (this_reload_insn == 0)
4965 this_reload_insn = reload_insn;
4970 /* See if we need a scratch register to load the
4971 intermediate register (a tertiary reload). */
4972 enum insn_code tertiary_icode
4973 = reload_secondary_icode[secondary_reload];
4975 if (tertiary_icode != CODE_FOR_nothing)
4977 rtx third_reload_reg
4978 = reload_reg_rtx[reload_secondary_reload[secondary_reload]];
4981 = emit_insn_before ((GEN_FCN (tertiary_icode)
4986 if (this_reload_insn == 0)
4987 this_reload_insn = reload_insn;
4992 = gen_input_reload (second_reload_reg,
4994 if (this_reload_insn == 0)
4995 this_reload_insn = reload_insn;
4996 oldequiv = second_reload_reg;
5005 reload_insn = gen_input_reload (reloadreg, oldequiv, where);
5006 if (this_reload_insn == 0)
5007 this_reload_insn = reload_insn;
5010 #if defined(SECONDARY_INPUT_RELOAD_CLASS) && defined(PRESERVE_DEATH_INFO_REGNO_P)
5011 /* We may have to make a REG_DEAD note for the secondary reload
5012 register in the insns we just made. Find the last insn that
5013 mentioned the register. */
5014 if (! special && second_reload_reg
5015 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reload_reg)))
5020 prev != PREV_INSN (this_reload_insn);
5021 prev = PREV_INSN (prev))
5022 if (GET_RTX_CLASS (GET_CODE (prev) == 'i')
5023 && reg_overlap_mentioned_for_reload_p (second_reload_reg,
5026 REG_NOTES (prev) = gen_rtx (EXPR_LIST, REG_DEAD,
5035 /* Update where to put other reload insns. */
5036 if (this_reload_insn)
5037 switch (reload_when_needed[j])
5039 case RELOAD_FOR_INPUT:
5041 if (first_other_reload_insn == first_operand_address_reload_insn)
5042 first_other_reload_insn = this_reload_insn;
5044 case RELOAD_FOR_OPERAND_ADDRESS:
5045 if (first_operand_address_reload_insn == before_insn)
5046 first_operand_address_reload_insn = this_reload_insn;
5047 if (first_other_reload_insn == before_insn)
5048 first_other_reload_insn = this_reload_insn;
5051 /* reload_inc[j] was formerly processed here. */
5054 /* Add a note saying the input reload reg
5055 dies in this insn, if anyone cares. */
5056 #ifdef PRESERVE_DEATH_INFO_REGNO_P
5058 && reload_reg_rtx[j] != old
5059 && reload_reg_rtx[j] != 0
5060 && reload_out[j] == 0
5061 && ! reload_inherited[j]
5062 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j])))
5064 register rtx reloadreg = reload_reg_rtx[j];
5067 /* We can't abort here because we need to support this for sched.c.
5068 It's not terrible to miss a REG_DEAD note, but we should try
5069 to figure out how to do this correctly. */
5070 /* The code below is incorrect for address-only reloads. */
5071 if (reload_when_needed[j] != RELOAD_OTHER
5072 && reload_when_needed[j] != RELOAD_FOR_INPUT)
5076 /* Add a death note to this insn, for an input reload. */
5078 if ((reload_when_needed[j] == RELOAD_OTHER
5079 || reload_when_needed[j] == RELOAD_FOR_INPUT)
5080 && ! dead_or_set_p (insn, reloadreg))
5082 = gen_rtx (EXPR_LIST, REG_DEAD,
5083 reloadreg, REG_NOTES (insn));
5086 /* When we inherit a reload, the last marked death of the reload reg
5087 may no longer really be a death. */
5088 if (reload_reg_rtx[j] != 0
5089 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j]))
5090 && reload_inherited[j])
5092 /* Handle inheriting an output reload.
5093 Remove the death note from the output reload insn. */
5094 if (reload_spill_index[j] >= 0
5095 && GET_CODE (reload_in[j]) == REG
5096 && spill_reg_store[reload_spill_index[j]] != 0
5097 && find_regno_note (spill_reg_store[reload_spill_index[j]],
5098 REG_DEAD, REGNO (reload_reg_rtx[j])))
5099 remove_death (REGNO (reload_reg_rtx[j]),
5100 spill_reg_store[reload_spill_index[j]]);
5101 /* Likewise for input reloads that were inherited. */
5102 else if (reload_spill_index[j] >= 0
5103 && GET_CODE (reload_in[j]) == REG
5104 && spill_reg_store[reload_spill_index[j]] == 0
5105 && reload_inheritance_insn[j] != 0
5106 && find_regno_note (reload_inheritance_insn[j], REG_DEAD,
5107 REGNO (reload_reg_rtx[j])))
5108 remove_death (REGNO (reload_reg_rtx[j]),
5109 reload_inheritance_insn[j]);
5114 /* We got this register from find_equiv_reg.
5115 Search back for its last death note and get rid of it.
5116 But don't search back too far.
5117 Don't go past a place where this reg is set,
5118 since a death note before that remains valid. */
5119 for (prev = PREV_INSN (insn);
5120 prev && GET_CODE (prev) != CODE_LABEL;
5121 prev = PREV_INSN (prev))
5122 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
5123 && dead_or_set_p (prev, reload_reg_rtx[j]))
5125 if (find_regno_note (prev, REG_DEAD,
5126 REGNO (reload_reg_rtx[j])))
5127 remove_death (REGNO (reload_reg_rtx[j]), prev);
5133 /* We might have used find_equiv_reg above to choose an alternate
5134 place from which to reload. If so, and it died, we need to remove
5135 that death and move it to one of the insns we just made. */
5137 if (oldequiv_reg != 0
5138 && PRESERVE_DEATH_INFO_REGNO_P (true_regnum (oldequiv_reg)))
5142 for (prev = PREV_INSN (insn); prev && GET_CODE (prev) != CODE_LABEL;
5143 prev = PREV_INSN (prev))
5144 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
5145 && dead_or_set_p (prev, oldequiv_reg))
5147 if (find_regno_note (prev, REG_DEAD, REGNO (oldequiv_reg)))
5149 for (prev1 = this_reload_insn;
5150 prev1; prev1 = PREV_INSN (prev1))
5151 if (GET_RTX_CLASS (GET_CODE (prev1) == 'i')
5152 && reg_overlap_mentioned_for_reload_p (oldequiv_reg,
5155 REG_NOTES (prev1) = gen_rtx (EXPR_LIST, REG_DEAD,
5160 remove_death (REGNO (oldequiv_reg), prev);
5167 /* If we are reloading a register that was recently stored in with an
5168 output-reload, see if we can prove there was
5169 actually no need to store the old value in it. */
5171 if (optimize && reload_inherited[j] && reload_spill_index[j] >= 0
5172 /* This is unsafe if some other reload uses the same reg first. */
5173 && (reload_when_needed[j] == RELOAD_OTHER
5174 || reload_when_needed[j] == RELOAD_FOR_INPUT
5175 || reload_when_needed[j] == RELOAD_FOR_INPUT_RELOAD_ADDRESS)
5176 && GET_CODE (reload_in[j]) == REG
5178 /* There doesn't seem to be any reason to restrict this to pseudos
5179 and doing so loses in the case where we are copying from a
5180 register of the wrong class. */
5181 && REGNO (reload_in[j]) >= FIRST_PSEUDO_REGISTER
5183 && spill_reg_store[reload_spill_index[j]] != 0
5184 && dead_or_set_p (insn, reload_in[j])
5185 /* This is unsafe if operand occurs more than once in current
5186 insn. Perhaps some occurrences weren't reloaded. */
5187 && count_occurrences (PATTERN (insn), reload_in[j]) == 1)
5188 delete_output_reload (insn, j,
5189 spill_reg_store[reload_spill_index[j]]);
5191 /* Input-reloading is done. Now do output-reloading,
5192 storing the value from the reload-register after the main insn
5193 if reload_out[j] is nonzero.
5195 ??? At some point we need to support handling output reloads of
5196 JUMP_INSNs or insns that set cc0. */
5197 old = reload_out[j];
5199 && reload_reg_rtx[j] != old
5200 && reload_reg_rtx[j] != 0)
5202 register rtx reloadreg = reload_reg_rtx[j];
5203 register rtx second_reloadreg = 0;
5204 rtx prev_insn = PREV_INSN (first_output_reload_insn);
5206 enum machine_mode mode;
5209 /* An output operand that dies right away does need a reload,
5210 but need not be copied from it. Show the new location in the
5212 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
5213 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
5215 XEXP (note, 0) = reload_reg_rtx[j];
5218 else if (GET_CODE (old) == SCRATCH)
5219 /* If we aren't optimizing, there won't be a REG_UNUSED note,
5220 but we don't want to make an output reload. */
5224 /* Strip off of OLD any size-increasing SUBREGs such as
5225 (SUBREG:SI foo:QI 0). */
5227 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
5228 && (GET_MODE_SIZE (GET_MODE (old))
5229 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
5230 old = SUBREG_REG (old);
5233 /* If is a JUMP_INSN, we can't support output reloads yet. */
5234 if (GET_CODE (insn) == JUMP_INSN)
5237 /* Determine the mode to reload in.
5238 See comments above (for input reloading). */
5240 mode = GET_MODE (old);
5241 if (mode == VOIDmode)
5242 abort (); /* Should never happen for an output. */
5244 /* A strict-low-part output operand needs to be reloaded
5245 in the mode of the entire value. */
5246 if (reload_strict_low[j])
5248 mode = GET_MODE (SUBREG_REG (reload_out[j]));
5249 /* Encapsulate OLD into that mode. */
5250 /* If OLD is a subreg, then strip it, since the subreg will
5251 be altered by this very reload. */
5252 while (GET_CODE (old) == SUBREG && GET_MODE (old) != mode)
5253 old = SUBREG_REG (old);
5254 if (GET_MODE (old) != VOIDmode
5255 && mode != GET_MODE (old))
5256 old = gen_rtx (SUBREG, mode, old, 0);
5259 if (GET_MODE (reloadreg) != mode)
5260 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
5262 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
5264 /* If we need two reload regs, set RELOADREG to the intermediate
5265 one, since it will be stored into OUT. We might need a secondary
5266 register only for an input reload, so check again here. */
5268 if (reload_secondary_reload[j] >= 0)
5272 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
5273 && reg_equiv_mem[REGNO (old)] != 0)
5274 real_old = reg_equiv_mem[REGNO (old)];
5276 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
5280 second_reloadreg = reloadreg;
5281 reloadreg = reload_reg_rtx[reload_secondary_reload[j]];
5283 /* See if RELOADREG is to be used as a scratch register
5284 or as an intermediate register. */
5285 if (reload_secondary_icode[j] != CODE_FOR_nothing)
5287 emit_insn_before ((GEN_FCN (reload_secondary_icode[j])
5288 (real_old, second_reloadreg,
5290 first_output_reload_insn);
5295 /* See if we need both a scratch and intermediate reload
5297 int secondary_reload = reload_secondary_reload[j];
5298 enum insn_code tertiary_icode
5299 = reload_secondary_icode[secondary_reload];
5302 if (GET_MODE (reloadreg) != mode)
5303 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
5305 if (tertiary_icode != CODE_FOR_nothing)
5308 = reload_reg_rtx[reload_secondary_reload[secondary_reload]];
5309 pat = (GEN_FCN (tertiary_icode)
5310 (reloadreg, second_reloadreg, third_reloadreg));
5313 pat = gen_move_insn (reloadreg, second_reloadreg);
5315 emit_insn_before (pat, first_output_reload_insn);
5321 /* Output the last reload insn. */
5324 #ifdef SECONDARY_MEMORY_NEEDED
5325 /* If we need a memory location to do the move, do it that way. */
5326 if (GET_CODE (old) == REG && REGNO (old) < FIRST_PSEUDO_REGISTER
5327 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (old)),
5328 REGNO_REG_CLASS (REGNO (reloadreg)),
5329 GET_MODE (reloadreg)))
5331 /* Get the memory to use and rewrite both registers to
5333 rtx loc = get_secondary_mem (old, GET_MODE (reloadreg));
5335 if (GET_MODE (loc) != GET_MODE (reloadreg))
5336 reloadreg = gen_rtx (REG, GET_MODE (loc),
5339 if (GET_MODE (loc) != GET_MODE (old))
5340 old = gen_rtx (REG, GET_MODE (loc), REGNO (old));
5342 emit_insn_before (gen_move_insn (loc, reloadreg),
5343 first_output_reload_insn);
5344 emit_insn_before (gen_move_insn (old, loc),
5345 first_output_reload_insn);
5349 emit_insn_before (gen_move_insn (old, reloadreg),
5350 first_output_reload_insn);
5353 #ifdef PRESERVE_DEATH_INFO_REGNO_P
5354 /* If final will look at death notes for this reg,
5355 put one on the last output-reload insn to use it. Similarly
5356 for any secondary register. */
5357 if (PRESERVE_DEATH_INFO_REGNO_P (REGNO (reloadreg)))
5358 for (p = PREV_INSN (first_output_reload_insn);
5359 p != prev_insn; p = PREV_INSN (p))
5360 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
5361 && reg_overlap_mentioned_for_reload_p (reloadreg,
5363 REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
5364 reloadreg, REG_NOTES (p));
5366 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
5368 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reloadreg)))
5369 for (p = PREV_INSN (first_output_reload_insn);
5370 p != prev_insn; p = PREV_INSN (p))
5371 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
5372 && reg_overlap_mentioned_for_reload_p (second_reloadreg,
5374 REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
5375 second_reloadreg, REG_NOTES (p));
5378 /* Look at all insns we emitted, just to be safe. */
5379 for (p = NEXT_INSN (prev_insn); p != first_output_reload_insn;
5381 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
5383 /* If this output reload doesn't come from a spill reg,
5384 clear any memory of reloaded copies of the pseudo reg.
5385 If this output reload comes from a spill reg,
5386 reg_has_output_reload will make this do nothing. */
5387 note_stores (PATTERN (p), forget_old_reloads_1);
5389 if (reg_mentioned_p (reload_reg_rtx[j], PATTERN (p)))
5393 first_output_reload_insn = NEXT_INSN (prev_insn);
5396 if (reload_spill_index[j] >= 0)
5397 new_spill_reg_store[reload_spill_index[j]] = store_insn;
5400 /* Move death notes from INSN
5401 to output-operand-address and output reload insns. */
5402 #ifdef PRESERVE_DEATH_INFO_REGNO_P
5405 /* Loop over those insns, last ones first. */
5406 for (insn1 = PREV_INSN (following_insn); insn1 != insn;
5407 insn1 = PREV_INSN (insn1))
5408 if (GET_CODE (insn1) == INSN && GET_CODE (PATTERN (insn1)) == SET)
5410 rtx source = SET_SRC (PATTERN (insn1));
5411 rtx dest = SET_DEST (PATTERN (insn1));
5413 /* The note we will examine next. */
5414 rtx reg_notes = REG_NOTES (insn);
5415 /* The place that pointed to this note. */
5416 rtx *prev_reg_note = ®_NOTES (insn);
5418 /* If the note is for something used in the source of this
5419 reload insn, or in the output address, move the note. */
5422 rtx next_reg_notes = XEXP (reg_notes, 1);
5423 if (REG_NOTE_KIND (reg_notes) == REG_DEAD
5424 && GET_CODE (XEXP (reg_notes, 0)) == REG
5425 && ((GET_CODE (dest) != REG
5426 && reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
5428 || reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
5431 *prev_reg_note = next_reg_notes;
5432 XEXP (reg_notes, 1) = REG_NOTES (insn1);
5433 REG_NOTES (insn1) = reg_notes;
5436 prev_reg_note = &XEXP (reg_notes, 1);
5438 reg_notes = next_reg_notes;
5444 /* For all the spill regs newly reloaded in this instruction,
5445 record what they were reloaded from, so subsequent instructions
5446 can inherit the reloads.
5448 Update spill_reg_store for the reloads of this insn.
5449 Copy the elements that were updated in the loop above. */
5451 for (j = 0; j < n_reloads; j++)
5453 register int r = reload_order[j];
5454 register int i = reload_spill_index[r];
5456 /* I is nonneg if this reload used one of the spill regs.
5457 If reload_reg_rtx[r] is 0, this is an optional reload
5458 that we opted to ignore. */
5460 if (i >= 0 && reload_reg_rtx[r] != 0)
5462 /* First, clear out memory of what used to be in this spill reg.
5463 If consecutive registers are used, clear them all. */
5465 = HARD_REGNO_NREGS (spill_regs[i], GET_MODE (reload_reg_rtx[r]));
5468 for (k = 0; k < nr; k++)
5470 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] = -1;
5471 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = 0;
5474 /* Maybe the spill reg contains a copy of reload_out. */
5475 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
5477 register int nregno = REGNO (reload_out[r]);
5479 spill_reg_store[i] = new_spill_reg_store[i];
5480 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
5482 for (k = 0; k < nr; k++)
5484 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
5486 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = insn;
5490 /* Maybe the spill reg contains a copy of reload_in. */
5491 else if (reload_out[r] == 0
5492 && reload_in[r] != 0
5493 && (GET_CODE (reload_in[r]) == REG
5494 || GET_CODE (reload_in_reg[r]) == REG))
5496 register int nregno;
5497 if (GET_CODE (reload_in[r]) == REG)
5498 nregno = REGNO (reload_in[r]);
5500 nregno = REGNO (reload_in_reg[r]);
5502 /* If there are two separate reloads (one in and one out)
5503 for the same (hard or pseudo) reg,
5504 leave reg_last_reload_reg set
5505 based on the output reload.
5506 Otherwise, set it from this input reload. */
5507 if (!reg_has_output_reload[nregno]
5508 /* But don't do so if another input reload
5509 will clobber this one's value. */
5510 && reload_reg_reaches_end_p (spill_regs[i],
5511 reload_when_needed[r]))
5513 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
5515 /* Unless we inherited this reload, show we haven't
5516 recently done a store. */
5517 if (! reload_inherited[r])
5518 spill_reg_store[i] = 0;
5520 for (k = 0; k < nr; k++)
5522 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
5524 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]]
5531 /* The following if-statement was #if 0'd in 1.34 (or before...).
5532 It's reenabled in 1.35 because supposedly nothing else
5533 deals with this problem. */
5535 /* If a register gets output-reloaded from a non-spill register,
5536 that invalidates any previous reloaded copy of it.
5537 But forget_old_reloads_1 won't get to see it, because
5538 it thinks only about the original insn. So invalidate it here. */
5539 if (i < 0 && reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
5541 register int nregno = REGNO (reload_out[r]);
5542 reg_last_reload_reg[nregno] = 0;
5547 /* Emit code before BEFORE_INSN to perform an input reload of IN to RELOADREG.
5548 Returns first insn emitted. */
5551 gen_input_reload (reloadreg, in, before_insn)
5556 register rtx prev_insn = PREV_INSN (before_insn);
5558 /* How to do this reload can get quite tricky. Normally, we are being
5559 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
5560 register that didn't get a hard register. In that case we can just
5561 call emit_move_insn.
5563 We can also be asked to reload a PLUS that adds either two registers or
5564 a register and a constant or MEM. This can occur during frame pointer
5565 elimination. That case if handled by trying to emit a single insn
5566 to perform the add. If it is not valid, we use a two insn sequence.
5568 Finally, we could be called to handle an 'o' constraint by putting
5569 an address into a register. In that case, we first try to do this
5570 with a named pattern of "reload_load_address". If no such pattern
5571 exists, we just emit a SET insn and hope for the best (it will normally
5572 be valid on machines that use 'o').
5574 This entire process is made complex because reload will never
5575 process the insns we generate here and so we must ensure that
5576 they will fit their constraints and also by the fact that parts of
5577 IN might be being reloaded separately and replaced with spill registers.
5578 Because of this, we are, in some sense, just guessing the right approach
5579 here. The one listed above seems to work.
5581 ??? At some point, this whole thing needs to be rethought. */
5583 if (GET_CODE (in) == PLUS
5584 && GET_CODE (XEXP (in, 0)) == REG
5585 && (GET_CODE (XEXP (in, 1)) == REG
5586 || CONSTANT_P (XEXP (in, 1))
5587 || GET_CODE (XEXP (in, 1)) == MEM))
5589 /* We need to compute the sum of what is either a register and a
5590 constant, a register and memory, or a hard register and a pseudo
5591 register and put it into the reload register. The best possible way
5592 of doing this is if the machine has a three-operand ADD insn that
5593 accepts the required operands.
5595 The simplest approach is to try to generate such an insn and see if it
5596 is recognized and matches its constraints. If so, it can be used.
5598 It might be better not to actually emit the insn unless it is valid,
5599 but we need to pass the insn as an operand to `recog' and
5600 `insn_extract' and it is simpler to emit and then delete the insn if
5601 not valid than to dummy things up. */
5603 rtx op0, op1, tem, insn;
5606 op0 = find_replacement (&XEXP (in, 0));
5607 op1 = find_replacement (&XEXP (in, 1));
5609 /* Since constraint checking is strict, commutativity won't be
5610 checked, so we need to do that here to avoid spurious failure
5611 if the add instruction is two-address and the second operand
5612 of the add is the same as the reload reg, which is frequently
5613 the case. If the insn would be A = B + A, rearrange it so
5614 it will be A = A + B as constrain_operands expects. */
5616 if (GET_CODE (XEXP (in, 1)) == REG
5617 && REGNO (reloadreg) == REGNO (XEXP (in, 1)))
5618 tem = op0, op0 = op1, op1 = tem;
5620 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
5621 in = gen_rtx (PLUS, GET_MODE (in), op0, op1);
5623 insn = emit_insn_before (gen_rtx (SET, VOIDmode, reloadreg, in),
5625 code = recog_memoized (insn);
5629 insn_extract (insn);
5630 /* We want constrain operands to treat this insn strictly in
5631 its validity determination, i.e., the way it would after reload
5633 if (constrain_operands (code, 1))
5637 if (PREV_INSN (insn))
5638 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
5639 if (NEXT_INSN (insn))
5640 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
5642 /* If that failed, we must use a conservative two-insn sequence.
5643 use move to copy constant, MEM, or pseudo register to the reload
5644 register since "move" will be able to handle an arbitrary operand,
5645 unlike add which can't, in general. Then add the registers.
5647 If there is another way to do this for a specific machine, a
5648 DEFINE_PEEPHOLE should be specified that recognizes the sequence
5651 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM
5652 || (GET_CODE (op1) == REG
5653 && REGNO (op1) >= FIRST_PSEUDO_REGISTER))
5654 tem = op0, op0 = op1, op1 = tem;
5656 emit_insn_before (gen_move_insn (reloadreg, op0), before_insn);
5657 emit_insn_before (gen_add2_insn (reloadreg, op1), before_insn);
5660 #ifdef SECONDARY_MEMORY_NEEDED
5661 /* If we need a memory location to do the move, do it that way. */
5662 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
5663 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
5664 REGNO_REG_CLASS (REGNO (reloadreg)),
5665 GET_MODE (reloadreg)))
5667 /* Get the memory to use and rewrite both registers to its mode. */
5668 rtx loc = get_secondary_mem (in, GET_MODE (reloadreg));
5670 if (GET_MODE (loc) != GET_MODE (reloadreg))
5671 reloadreg = gen_rtx (REG, GET_MODE (loc), REGNO (reloadreg));
5673 if (GET_MODE (loc) != GET_MODE (in))
5674 in = gen_rtx (REG, GET_MODE (loc), REGNO (in));
5676 emit_insn_before (gen_move_insn (loc, in), before_insn);
5677 emit_insn_before (gen_move_insn (reloadreg, loc), before_insn);
5681 /* If IN is a simple operand, use gen_move_insn. */
5682 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
5683 emit_insn_before (gen_move_insn (reloadreg, in), before_insn);
5685 #ifdef HAVE_reload_load_address
5686 else if (HAVE_reload_load_address)
5687 emit_insn_before (gen_reload_load_address (reloadreg, in), before_insn);
5690 /* Otherwise, just write (set REGLOADREG IN) and hope for the best. */
5692 emit_insn_before (gen_rtx (SET, VOIDmode, reloadreg, in), before_insn);
5694 /* Return the first insn emitted.
5695 We can not just return PREV_INSN (before_insn), because there may have
5696 been multiple instructions emitted. Also note that gen_move_insn may
5697 emit more than one insn itself, so we can not assume that there is one
5698 insn emitted per emit_insn_before call. */
5700 return NEXT_INSN (prev_insn);
5703 /* Delete a previously made output-reload
5704 whose result we now believe is not needed.
5705 First we double-check.
5707 INSN is the insn now being processed.
5708 OUTPUT_RELOAD_INSN is the insn of the output reload.
5709 J is the reload-number for this insn. */
5712 delete_output_reload (insn, j, output_reload_insn)
5715 rtx output_reload_insn;
5719 /* Get the raw pseudo-register referred to. */
5721 rtx reg = reload_in[j];
5722 while (GET_CODE (reg) == SUBREG)
5723 reg = SUBREG_REG (reg);
5725 /* If the pseudo-reg we are reloading is no longer referenced
5726 anywhere between the store into it and here,
5727 and no jumps or labels intervene, then the value can get
5728 here through the reload reg alone.
5729 Otherwise, give up--return. */
5730 for (i1 = NEXT_INSN (output_reload_insn);
5731 i1 != insn; i1 = NEXT_INSN (i1))
5733 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
5735 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
5736 && reg_mentioned_p (reg, PATTERN (i1)))
5740 /* If this insn will store in the pseudo again,
5741 the previous store can be removed. */
5742 if (reload_out[j] == reload_in[j])
5743 delete_insn (output_reload_insn);
5745 /* See if the pseudo reg has been completely replaced
5746 with reload regs. If so, delete the store insn
5747 and forget we had a stack slot for the pseudo. */
5748 else if (reg_n_deaths[REGNO (reg)] == 1
5749 && reg_basic_block[REGNO (reg)] >= 0
5750 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
5754 /* We know that it was used only between here
5755 and the beginning of the current basic block.
5756 (We also know that the last use before INSN was
5757 the output reload we are thinking of deleting, but never mind that.)
5758 Search that range; see if any ref remains. */
5759 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
5761 rtx set = single_set (i2);
5763 /* Uses which just store in the pseudo don't count,
5764 since if they are the only uses, they are dead. */
5765 if (set != 0 && SET_DEST (set) == reg)
5767 if (GET_CODE (i2) == CODE_LABEL
5768 || GET_CODE (i2) == JUMP_INSN)
5770 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
5771 && reg_mentioned_p (reg, PATTERN (i2)))
5772 /* Some other ref remains;
5773 we can't do anything. */
5777 /* Delete the now-dead stores into this pseudo. */
5778 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
5780 rtx set = single_set (i2);
5782 if (set != 0 && SET_DEST (set) == reg)
5784 if (GET_CODE (i2) == CODE_LABEL
5785 || GET_CODE (i2) == JUMP_INSN)
5789 /* For the debugging info,
5790 say the pseudo lives in this reload reg. */
5791 reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
5792 alter_reg (REGNO (reg), -1);
5797 /* Output reload-insns to reload VALUE into RELOADREG.
5798 VALUE is a autoincrement or autodecrement RTX whose operand
5799 is a register or memory location;
5800 so reloading involves incrementing that location.
5802 INC_AMOUNT is the number to increment or decrement by (always positive).
5803 This cannot be deduced from VALUE.
5805 INSN is the insn before which the new insns should be emitted.
5807 The return value is the first of the insns emitted. */
5810 inc_for_reload (reloadreg, value, inc_amount, insn)
5816 /* REG or MEM to be copied and incremented. */
5817 rtx incloc = XEXP (value, 0);
5818 /* Nonzero if increment after copying. */
5819 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
5820 rtx prev = PREV_INSN (insn);
5825 /* No hard register is equivalent to this register after
5826 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
5827 we could inc/dec that register as well (maybe even using it for
5828 the source), but I'm not sure it's worth worrying about. */
5829 if (GET_CODE (incloc) == REG)
5830 reg_last_reload_reg[REGNO (incloc)] = 0;
5832 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
5833 inc_amount = - inc_amount;
5835 inc = GEN_INT (inc_amount);
5837 /* If this is post-increment, first copy the location to the reload reg. */
5839 emit_insn_before (gen_move_insn (reloadreg, incloc), insn);
5841 /* See if we can directly increment INCLOC. Use a method similar to that
5842 in gen_input_reload. */
5844 add_insn = emit_insn_before (gen_rtx (SET, VOIDmode, incloc,
5845 gen_rtx (PLUS, GET_MODE (incloc),
5846 incloc, inc)), insn);
5848 code = recog_memoized (add_insn);
5851 insn_extract (add_insn);
5852 if (constrain_operands (code, 1))
5854 /* If this is a pre-increment and we have incremented the value
5855 where it lives, copy the incremented value to RELOADREG to
5856 be used as an address. */
5859 emit_insn_before (gen_move_insn (reloadreg, incloc), insn);
5860 return NEXT_INSN (prev);
5864 if (PREV_INSN (add_insn))
5865 NEXT_INSN (PREV_INSN (add_insn)) = NEXT_INSN (add_insn);
5866 if (NEXT_INSN (add_insn))
5867 PREV_INSN (NEXT_INSN (add_insn)) = PREV_INSN (add_insn);
5869 /* If couldn't do the increment directly, must increment in RELOADREG.
5870 The way we do this depends on whether this is pre- or post-increment.
5871 For pre-increment, copy INCLOC to the reload register, increment it
5872 there, then save back. */
5876 emit_insn_before (gen_move_insn (reloadreg, incloc), insn);
5877 emit_insn_before (gen_add2_insn (reloadreg, inc), insn);
5878 emit_insn_before (gen_move_insn (incloc, reloadreg), insn);
5883 Because this might be a jump insn or a compare, and because RELOADREG
5884 may not be available after the insn in an input reload, we must do
5885 the incrementation before the insn being reloaded for.
5887 We have already copied INCLOC to RELOADREG. Increment the copy in
5888 RELOADREG, save that back, then decrement RELOADREG so it has
5889 the original value. */
5891 emit_insn_before (gen_add2_insn (reloadreg, inc), insn);
5892 emit_insn_before (gen_move_insn (incloc, reloadreg), insn);
5893 emit_insn_before (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)),
5897 return NEXT_INSN (prev);
5900 /* Return 1 if we are certain that the constraint-string STRING allows
5901 the hard register REG. Return 0 if we can't be sure of this. */
5904 constraint_accepts_reg_p (string, reg)
5909 int regno = true_regnum (reg);
5912 /* Initialize for first alternative. */
5914 /* Check that each alternative contains `g' or `r'. */
5916 switch (c = *string++)
5919 /* If an alternative lacks `g' or `r', we lose. */
5922 /* If an alternative lacks `g' or `r', we lose. */
5925 /* Initialize for next alternative. */
5930 /* Any general reg wins for this alternative. */
5931 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
5935 /* Any reg in specified class wins for this alternative. */
5937 enum reg_class class = REG_CLASS_FROM_LETTER (c);
5939 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
5945 /* Return the number of places FIND appears within X, but don't count
5946 an occurrence if some SET_DEST is FIND. */
5949 count_occurrences (x, find)
5950 register rtx x, find;
5953 register enum rtx_code code;
5954 register char *format_ptr;
5962 code = GET_CODE (x);
5977 if (SET_DEST (x) == find)
5978 return count_occurrences (SET_SRC (x), find);
5982 format_ptr = GET_RTX_FORMAT (code);
5985 for (i = 0; i < GET_RTX_LENGTH (code); i++)
5987 switch (*format_ptr++)
5990 count += count_occurrences (XEXP (x, i), find);
5994 if (XVEC (x, i) != NULL)
5996 for (j = 0; j < XVECLEN (x, i); j++)
5997 count += count_occurrences (XVECEXP (x, i, j), find);
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