1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
36 #include "basic-block.h"
46 /* This file contains the reload pass of the compiler, which is
47 run after register allocation has been done. It checks that
48 each insn is valid (operands required to be in registers really
49 are in registers of the proper class) and fixes up invalid ones
50 by copying values temporarily into registers for the insns
53 The results of register allocation are described by the vector
54 reg_renumber; the insns still contain pseudo regs, but reg_renumber
55 can be used to find which hard reg, if any, a pseudo reg is in.
57 The technique we always use is to free up a few hard regs that are
58 called ``reload regs'', and for each place where a pseudo reg
59 must be in a hard reg, copy it temporarily into one of the reload regs.
61 Reload regs are allocated locally for every instruction that needs
62 reloads. When there are pseudos which are allocated to a register that
63 has been chosen as a reload reg, such pseudos must be ``spilled''.
64 This means that they go to other hard regs, or to stack slots if no other
65 available hard regs can be found. Spilling can invalidate more
66 insns, requiring additional need for reloads, so we must keep checking
67 until the process stabilizes.
69 For machines with different classes of registers, we must keep track
70 of the register class needed for each reload, and make sure that
71 we allocate enough reload registers of each class.
73 The file reload.c contains the code that checks one insn for
74 validity and reports the reloads that it needs. This file
75 is in charge of scanning the entire rtl code, accumulating the
76 reload needs, spilling, assigning reload registers to use for
77 fixing up each insn, and generating the new insns to copy values
78 into the reload registers. */
80 #ifndef REGISTER_MOVE_COST
81 #define REGISTER_MOVE_COST(m, x, y) 2
85 #define LOCAL_REGNO(REGNO) 0
88 /* During reload_as_needed, element N contains a REG rtx for the hard reg
89 into which reg N has been reloaded (perhaps for a previous insn). */
90 static rtx *reg_last_reload_reg;
92 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
93 for an output reload that stores into reg N. */
94 static char *reg_has_output_reload;
96 /* Indicates which hard regs are reload-registers for an output reload
97 in the current insn. */
98 static HARD_REG_SET reg_is_output_reload;
100 /* Element N is the constant value to which pseudo reg N is equivalent,
101 or zero if pseudo reg N is not equivalent to a constant.
102 find_reloads looks at this in order to replace pseudo reg N
103 with the constant it stands for. */
104 rtx *reg_equiv_constant;
106 /* Element N is a memory location to which pseudo reg N is equivalent,
107 prior to any register elimination (such as frame pointer to stack
108 pointer). Depending on whether or not it is a valid address, this value
109 is transferred to either reg_equiv_address or reg_equiv_mem. */
110 rtx *reg_equiv_memory_loc;
112 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
113 This is used when the address is not valid as a memory address
114 (because its displacement is too big for the machine.) */
115 rtx *reg_equiv_address;
117 /* Element N is the memory slot to which pseudo reg N is equivalent,
118 or zero if pseudo reg N is not equivalent to a memory slot. */
121 /* Widest width in which each pseudo reg is referred to (via subreg). */
122 static unsigned int *reg_max_ref_width;
124 /* Element N is the list of insns that initialized reg N from its equivalent
125 constant or memory slot. */
126 static rtx *reg_equiv_init;
128 /* Vector to remember old contents of reg_renumber before spilling. */
129 static short *reg_old_renumber;
131 /* During reload_as_needed, element N contains the last pseudo regno reloaded
132 into hard register N. If that pseudo reg occupied more than one register,
133 reg_reloaded_contents points to that pseudo for each spill register in
134 use; all of these must remain set for an inheritance to occur. */
135 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
137 /* During reload_as_needed, element N contains the insn for which
138 hard register N was last used. Its contents are significant only
139 when reg_reloaded_valid is set for this register. */
140 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
142 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
143 static HARD_REG_SET reg_reloaded_valid;
144 /* Indicate if the register was dead at the end of the reload.
145 This is only valid if reg_reloaded_contents is set and valid. */
146 static HARD_REG_SET reg_reloaded_dead;
148 /* Number of spill-regs so far; number of valid elements of spill_regs. */
151 /* In parallel with spill_regs, contains REG rtx's for those regs.
152 Holds the last rtx used for any given reg, or 0 if it has never
153 been used for spilling yet. This rtx is reused, provided it has
155 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
157 /* In parallel with spill_regs, contains nonzero for a spill reg
158 that was stored after the last time it was used.
159 The precise value is the insn generated to do the store. */
160 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
162 /* This is the register that was stored with spill_reg_store. This is a
163 copy of reload_out / reload_out_reg when the value was stored; if
164 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
165 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
167 /* This table is the inverse mapping of spill_regs:
168 indexed by hard reg number,
169 it contains the position of that reg in spill_regs,
170 or -1 for something that is not in spill_regs.
172 ?!? This is no longer accurate. */
173 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
175 /* This reg set indicates registers that can't be used as spill registers for
176 the currently processed insn. These are the hard registers which are live
177 during the insn, but not allocated to pseudos, as well as fixed
179 static HARD_REG_SET bad_spill_regs;
181 /* These are the hard registers that can't be used as spill register for any
182 insn. This includes registers used for user variables and registers that
183 we can't eliminate. A register that appears in this set also can't be used
184 to retry register allocation. */
185 static HARD_REG_SET bad_spill_regs_global;
187 /* Describes order of use of registers for reloading
188 of spilled pseudo-registers. `n_spills' is the number of
189 elements that are actually valid; new ones are added at the end.
191 Both spill_regs and spill_reg_order are used on two occasions:
192 once during find_reload_regs, where they keep track of the spill registers
193 for a single insn, but also during reload_as_needed where they show all
194 the registers ever used by reload. For the latter case, the information
195 is calculated during finish_spills. */
196 static short spill_regs[FIRST_PSEUDO_REGISTER];
198 /* This vector of reg sets indicates, for each pseudo, which hard registers
199 may not be used for retrying global allocation because the register was
200 formerly spilled from one of them. If we allowed reallocating a pseudo to
201 a register that it was already allocated to, reload might not
203 static HARD_REG_SET *pseudo_previous_regs;
205 /* This vector of reg sets indicates, for each pseudo, which hard
206 registers may not be used for retrying global allocation because they
207 are used as spill registers during one of the insns in which the
209 static HARD_REG_SET *pseudo_forbidden_regs;
211 /* All hard regs that have been used as spill registers for any insn are
212 marked in this set. */
213 static HARD_REG_SET used_spill_regs;
215 /* Index of last register assigned as a spill register. We allocate in
216 a round-robin fashion. */
217 static int last_spill_reg;
219 /* Nonzero if indirect addressing is supported on the machine; this means
220 that spilling (REG n) does not require reloading it into a register in
221 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
222 value indicates the level of indirect addressing supported, e.g., two
223 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
225 static char spill_indirect_levels;
227 /* Nonzero if indirect addressing is supported when the innermost MEM is
228 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
229 which these are valid is the same as spill_indirect_levels, above. */
230 char indirect_symref_ok;
232 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
233 char double_reg_address_ok;
235 /* Record the stack slot for each spilled hard register. */
236 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
238 /* Width allocated so far for that stack slot. */
239 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
241 /* Record which pseudos needed to be spilled. */
242 static regset_head spilled_pseudos;
244 /* Used for communication between order_regs_for_reload and count_pseudo.
245 Used to avoid counting one pseudo twice. */
246 static regset_head pseudos_counted;
248 /* First uid used by insns created by reload in this function.
249 Used in find_equiv_reg. */
250 int reload_first_uid;
252 /* Flag set by local-alloc or global-alloc if anything is live in
253 a call-clobbered reg across calls. */
254 int caller_save_needed;
256 /* Set to 1 while reload_as_needed is operating.
257 Required by some machines to handle any generated moves differently. */
258 int reload_in_progress = 0;
260 /* These arrays record the insn_code of insns that may be needed to
261 perform input and output reloads of special objects. They provide a
262 place to pass a scratch register. */
263 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
264 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
266 /* This obstack is used for allocation of rtl during register elimination.
267 The allocated storage can be freed once find_reloads has processed the
269 struct obstack reload_obstack;
271 /* Points to the beginning of the reload_obstack. All insn_chain structures
272 are allocated first. */
273 char *reload_startobj;
275 /* The point after all insn_chain structures. Used to quickly deallocate
276 memory allocated in copy_reloads during calculate_needs_all_insns. */
277 char *reload_firstobj;
279 /* This points before all local rtl generated by register elimination.
280 Used to quickly free all memory after processing one insn. */
281 static char *reload_insn_firstobj;
283 /* List of insn_chain instructions, one for every insn that reload needs to
285 struct insn_chain *reload_insn_chain;
288 extern tree current_function_decl;
290 extern union tree_node *current_function_decl;
293 /* List of all insns needing reloads. */
294 static struct insn_chain *insns_need_reload;
296 /* This structure is used to record information about register eliminations.
297 Each array entry describes one possible way of eliminating a register
298 in favor of another. If there is more than one way of eliminating a
299 particular register, the most preferred should be specified first. */
303 int from; /* Register number to be eliminated. */
304 int to; /* Register number used as replacement. */
305 int initial_offset; /* Initial difference between values. */
306 int can_eliminate; /* Non-zero if this elimination can be done. */
307 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
308 insns made by reload. */
309 int offset; /* Current offset between the two regs. */
310 int previous_offset; /* Offset at end of previous insn. */
311 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
312 rtx from_rtx; /* REG rtx for the register to be eliminated.
313 We cannot simply compare the number since
314 we might then spuriously replace a hard
315 register corresponding to a pseudo
316 assigned to the reg to be eliminated. */
317 rtx to_rtx; /* REG rtx for the replacement. */
320 static struct elim_table *reg_eliminate = 0;
322 /* This is an intermediate structure to initialize the table. It has
323 exactly the members provided by ELIMINABLE_REGS. */
324 static const struct elim_table_1
328 } reg_eliminate_1[] =
330 /* If a set of eliminable registers was specified, define the table from it.
331 Otherwise, default to the normal case of the frame pointer being
332 replaced by the stack pointer. */
334 #ifdef ELIMINABLE_REGS
337 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
340 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
342 /* Record the number of pending eliminations that have an offset not equal
343 to their initial offset. If non-zero, we use a new copy of each
344 replacement result in any insns encountered. */
345 int num_not_at_initial_offset;
347 /* Count the number of registers that we may be able to eliminate. */
348 static int num_eliminable;
349 /* And the number of registers that are equivalent to a constant that
350 can be eliminated to frame_pointer / arg_pointer + constant. */
351 static int num_eliminable_invariants;
353 /* For each label, we record the offset of each elimination. If we reach
354 a label by more than one path and an offset differs, we cannot do the
355 elimination. This information is indexed by the number of the label.
356 The first table is an array of flags that records whether we have yet
357 encountered a label and the second table is an array of arrays, one
358 entry in the latter array for each elimination. */
360 static char *offsets_known_at;
361 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
363 /* Number of labels in the current function. */
365 static int num_labels;
367 static void replace_pseudos_in_call_usage PARAMS ((rtx *,
370 static void maybe_fix_stack_asms PARAMS ((void));
371 static void copy_reloads PARAMS ((struct insn_chain *));
372 static void calculate_needs_all_insns PARAMS ((int));
373 static int find_reg PARAMS ((struct insn_chain *, int));
374 static void find_reload_regs PARAMS ((struct insn_chain *));
375 static void select_reload_regs PARAMS ((void));
376 static void delete_caller_save_insns PARAMS ((void));
378 static void spill_failure PARAMS ((rtx, enum reg_class));
379 static void count_spilled_pseudo PARAMS ((int, int, int));
380 static void delete_dead_insn PARAMS ((rtx));
381 static void alter_reg PARAMS ((int, int));
382 static void set_label_offsets PARAMS ((rtx, rtx, int));
383 static void check_eliminable_occurrences PARAMS ((rtx));
384 static void elimination_effects PARAMS ((rtx, enum machine_mode));
385 static int eliminate_regs_in_insn PARAMS ((rtx, int));
386 static void update_eliminable_offsets PARAMS ((void));
387 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
388 static void set_initial_elim_offsets PARAMS ((void));
389 static void verify_initial_elim_offsets PARAMS ((void));
390 static void set_initial_label_offsets PARAMS ((void));
391 static void set_offsets_for_label PARAMS ((rtx));
392 static void init_elim_table PARAMS ((void));
393 static void update_eliminables PARAMS ((HARD_REG_SET *));
394 static void spill_hard_reg PARAMS ((unsigned int, int));
395 static int finish_spills PARAMS ((int));
396 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
397 static void scan_paradoxical_subregs PARAMS ((rtx));
398 static void count_pseudo PARAMS ((int));
399 static void order_regs_for_reload PARAMS ((struct insn_chain *));
400 static void reload_as_needed PARAMS ((int));
401 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
402 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
403 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
406 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
409 static int reload_reg_free_p PARAMS ((unsigned int, int,
411 static int reload_reg_free_for_value_p PARAMS ((int, int, int,
413 rtx, rtx, int, int));
414 static int free_for_value_p PARAMS ((int, enum machine_mode, int,
415 enum reload_type, rtx, rtx,
417 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
419 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
421 static int conflicts_with_override PARAMS ((rtx));
422 static void failed_reload PARAMS ((rtx, int));
423 static int set_reload_reg PARAMS ((int, int));
424 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
425 static void choose_reload_regs PARAMS ((struct insn_chain *));
426 static void merge_assigned_reloads PARAMS ((rtx));
427 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
428 struct reload *, rtx, int));
429 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
430 struct reload *, int));
431 static void do_input_reload PARAMS ((struct insn_chain *,
432 struct reload *, int));
433 static void do_output_reload PARAMS ((struct insn_chain *,
434 struct reload *, int));
435 static void emit_reload_insns PARAMS ((struct insn_chain *));
436 static void delete_output_reload PARAMS ((rtx, int, int));
437 static void delete_address_reloads PARAMS ((rtx, rtx));
438 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
439 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
440 static void reload_cse_regs_1 PARAMS ((rtx));
441 static int reload_cse_noop_set_p PARAMS ((rtx));
442 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
443 static int reload_cse_simplify_operands PARAMS ((rtx, rtx));
444 static void reload_combine PARAMS ((void));
445 static void reload_combine_note_use PARAMS ((rtx *, rtx));
446 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
447 static void reload_cse_move2add PARAMS ((rtx));
448 static void move2add_note_store PARAMS ((rtx, rtx, void *));
450 static void add_auto_inc_notes PARAMS ((rtx, rtx));
452 static void copy_eh_notes PARAMS ((rtx, rtx));
453 static HOST_WIDE_INT sext_for_mode PARAMS ((enum machine_mode,
455 static void failed_reload PARAMS ((rtx, int));
456 static int set_reload_reg PARAMS ((int, int));
457 static void reload_cse_simplify PARAMS ((rtx, rtx));
458 void fixup_abnormal_edges PARAMS ((void));
459 extern void dump_needs PARAMS ((struct insn_chain *));
461 /* Initialize the reload pass once per compilation. */
468 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
469 Set spill_indirect_levels to the number of levels such addressing is
470 permitted, zero if it is not permitted at all. */
473 = gen_rtx_MEM (Pmode,
476 LAST_VIRTUAL_REGISTER + 1),
478 spill_indirect_levels = 0;
480 while (memory_address_p (QImode, tem))
482 spill_indirect_levels++;
483 tem = gen_rtx_MEM (Pmode, tem);
486 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
488 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
489 indirect_symref_ok = memory_address_p (QImode, tem);
491 /* See if reg+reg is a valid (and offsettable) address. */
493 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
495 tem = gen_rtx_PLUS (Pmode,
496 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
497 gen_rtx_REG (Pmode, i));
499 /* This way, we make sure that reg+reg is an offsettable address. */
500 tem = plus_constant (tem, 4);
502 if (memory_address_p (QImode, tem))
504 double_reg_address_ok = 1;
509 /* Initialize obstack for our rtl allocation. */
510 gcc_obstack_init (&reload_obstack);
511 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
513 INIT_REG_SET (&spilled_pseudos);
514 INIT_REG_SET (&pseudos_counted);
517 /* List of insn chains that are currently unused. */
518 static struct insn_chain *unused_insn_chains = 0;
520 /* Allocate an empty insn_chain structure. */
524 struct insn_chain *c;
526 if (unused_insn_chains == 0)
528 c = (struct insn_chain *)
529 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
530 INIT_REG_SET (&c->live_throughout);
531 INIT_REG_SET (&c->dead_or_set);
535 c = unused_insn_chains;
536 unused_insn_chains = c->next;
538 c->is_caller_save_insn = 0;
539 c->need_operand_change = 0;
545 /* Small utility function to set all regs in hard reg set TO which are
546 allocated to pseudos in regset FROM. */
549 compute_use_by_pseudos (to, from)
555 EXECUTE_IF_SET_IN_REG_SET
556 (from, FIRST_PSEUDO_REGISTER, regno,
558 int r = reg_renumber[regno];
563 /* reload_combine uses the information from
564 BASIC_BLOCK->global_live_at_start, which might still
565 contain registers that have not actually been allocated
566 since they have an equivalence. */
567 if (! reload_completed)
572 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
574 SET_HARD_REG_BIT (*to, r + nregs);
579 /* Replace all pseudos found in LOC with their corresponding
583 replace_pseudos_in_call_usage (loc, mem_mode, usage)
585 enum machine_mode mem_mode;
599 unsigned int regno = REGNO (x);
601 if (regno < FIRST_PSEUDO_REGISTER)
604 x = eliminate_regs (x, mem_mode, usage);
608 replace_pseudos_in_call_usage (loc, mem_mode, usage);
612 if (reg_equiv_constant[regno])
613 *loc = reg_equiv_constant[regno];
614 else if (reg_equiv_mem[regno])
615 *loc = reg_equiv_mem[regno];
616 else if (reg_equiv_address[regno])
617 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
618 else if (GET_CODE (regno_reg_rtx[regno]) != REG
619 || REGNO (regno_reg_rtx[regno]) != regno)
620 *loc = regno_reg_rtx[regno];
626 else if (code == MEM)
628 replace_pseudos_in_call_usage (& XEXP (x, 0), GET_MODE (x), usage);
632 /* Process each of our operands recursively. */
633 fmt = GET_RTX_FORMAT (code);
634 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
636 replace_pseudos_in_call_usage (&XEXP (x, i), mem_mode, usage);
637 else if (*fmt == 'E')
638 for (j = 0; j < XVECLEN (x, i); j++)
639 replace_pseudos_in_call_usage (& XVECEXP (x, i, j), mem_mode, usage);
643 /* Global variables used by reload and its subroutines. */
645 /* Set during calculate_needs if an insn needs register elimination. */
646 static int something_needs_elimination;
647 /* Set during calculate_needs if an insn needs an operand changed. */
648 int something_needs_operands_changed;
650 /* Nonzero means we couldn't get enough spill regs. */
653 /* Main entry point for the reload pass.
655 FIRST is the first insn of the function being compiled.
657 GLOBAL nonzero means we were called from global_alloc
658 and should attempt to reallocate any pseudoregs that we
659 displace from hard regs we will use for reloads.
660 If GLOBAL is zero, we do not have enough information to do that,
661 so any pseudo reg that is spilled must go to the stack.
663 Return value is nonzero if reload failed
664 and we must not do any more for this function. */
667 reload (first, global)
673 struct elim_table *ep;
676 /* The two pointers used to track the true location of the memory used
677 for label offsets. */
678 char *real_known_ptr = NULL;
679 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
681 /* Make sure even insns with volatile mem refs are recognizable. */
686 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
688 /* Make sure that the last insn in the chain
689 is not something that needs reloading. */
690 emit_note (NULL, NOTE_INSN_DELETED);
692 /* Enable find_equiv_reg to distinguish insns made by reload. */
693 reload_first_uid = get_max_uid ();
695 #ifdef SECONDARY_MEMORY_NEEDED
696 /* Initialize the secondary memory table. */
697 clear_secondary_mem ();
700 /* We don't have a stack slot for any spill reg yet. */
701 memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot);
702 memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
704 /* Initialize the save area information for caller-save, in case some
708 /* Compute which hard registers are now in use
709 as homes for pseudo registers.
710 This is done here rather than (eg) in global_alloc
711 because this point is reached even if not optimizing. */
712 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
715 /* A function that receives a nonlocal goto must save all call-saved
717 if (current_function_has_nonlocal_label)
718 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
719 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
720 regs_ever_live[i] = 1;
722 /* Find all the pseudo registers that didn't get hard regs
723 but do have known equivalent constants or memory slots.
724 These include parameters (known equivalent to parameter slots)
725 and cse'd or loop-moved constant memory addresses.
727 Record constant equivalents in reg_equiv_constant
728 so they will be substituted by find_reloads.
729 Record memory equivalents in reg_mem_equiv so they can
730 be substituted eventually by altering the REG-rtx's. */
732 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
733 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
734 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
735 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
736 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
737 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
738 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
739 pseudo_forbidden_regs
740 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
742 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
744 CLEAR_HARD_REG_SET (bad_spill_regs_global);
746 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
747 Also find all paradoxical subregs and find largest such for each pseudo.
748 On machines with small register classes, record hard registers that
749 are used for user variables. These can never be used for spills.
750 Also look for a "constant" REG_SETJMP. This means that all
751 caller-saved registers must be marked live. */
753 num_eliminable_invariants = 0;
754 for (insn = first; insn; insn = NEXT_INSN (insn))
756 rtx set = single_set (insn);
758 /* We may introduce USEs that we want to remove at the end, so
759 we'll mark them with QImode. Make sure there are no
760 previously-marked insns left by say regmove. */
761 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
762 && GET_MODE (insn) != VOIDmode)
763 PUT_MODE (insn, VOIDmode);
765 if (GET_CODE (insn) == CALL_INSN
766 && find_reg_note (insn, REG_SETJMP, NULL))
767 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
768 if (! call_used_regs[i])
769 regs_ever_live[i] = 1;
771 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
773 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
775 #ifdef LEGITIMATE_PIC_OPERAND_P
776 && (! function_invariant_p (XEXP (note, 0))
778 /* A function invariant is often CONSTANT_P but may
779 include a register. We promise to only pass
780 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
781 || (CONSTANT_P (XEXP (note, 0))
782 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))))
786 rtx x = XEXP (note, 0);
787 i = REGNO (SET_DEST (set));
788 if (i > LAST_VIRTUAL_REGISTER)
790 /* It can happen that a REG_EQUIV note contains a MEM
791 that is not a legitimate memory operand. As later
792 stages of reload assume that all addresses found
793 in the reg_equiv_* arrays were originally legitimate,
794 we ignore such REG_EQUIV notes. */
795 if (memory_operand (x, VOIDmode))
797 /* Always unshare the equivalence, so we can
798 substitute into this insn without touching the
800 reg_equiv_memory_loc[i] = copy_rtx (x);
802 else if (function_invariant_p (x))
804 if (GET_CODE (x) == PLUS)
806 /* This is PLUS of frame pointer and a constant,
807 and might be shared. Unshare it. */
808 reg_equiv_constant[i] = copy_rtx (x);
809 num_eliminable_invariants++;
811 else if (x == frame_pointer_rtx
812 || x == arg_pointer_rtx)
814 reg_equiv_constant[i] = x;
815 num_eliminable_invariants++;
817 else if (LEGITIMATE_CONSTANT_P (x))
818 reg_equiv_constant[i] = x;
820 reg_equiv_memory_loc[i]
821 = force_const_mem (GET_MODE (SET_DEST (set)), x);
826 /* If this register is being made equivalent to a MEM
827 and the MEM is not SET_SRC, the equivalencing insn
828 is one with the MEM as a SET_DEST and it occurs later.
829 So don't mark this insn now. */
830 if (GET_CODE (x) != MEM
831 || rtx_equal_p (SET_SRC (set), x))
833 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
838 /* If this insn is setting a MEM from a register equivalent to it,
839 this is the equivalencing insn. */
840 else if (set && GET_CODE (SET_DEST (set)) == MEM
841 && GET_CODE (SET_SRC (set)) == REG
842 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
843 && rtx_equal_p (SET_DEST (set),
844 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
845 reg_equiv_init[REGNO (SET_SRC (set))]
846 = gen_rtx_INSN_LIST (VOIDmode, insn,
847 reg_equiv_init[REGNO (SET_SRC (set))]);
850 scan_paradoxical_subregs (PATTERN (insn));
855 num_labels = max_label_num () - get_first_label_num ();
857 /* Allocate the tables used to store offset information at labels. */
858 /* We used to use alloca here, but the size of what it would try to
859 allocate would occasionally cause it to exceed the stack limit and
860 cause a core dump. */
861 real_known_ptr = xmalloc (num_labels);
863 = (int (*)[NUM_ELIMINABLE_REGS])
864 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
866 offsets_known_at = real_known_ptr - get_first_label_num ();
868 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
870 /* Alter each pseudo-reg rtx to contain its hard reg number.
871 Assign stack slots to the pseudos that lack hard regs or equivalents.
872 Do not touch virtual registers. */
874 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
877 /* If we have some registers we think can be eliminated, scan all insns to
878 see if there is an insn that sets one of these registers to something
879 other than itself plus a constant. If so, the register cannot be
880 eliminated. Doing this scan here eliminates an extra pass through the
881 main reload loop in the most common case where register elimination
883 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
884 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
885 || GET_CODE (insn) == CALL_INSN)
886 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
888 maybe_fix_stack_asms ();
890 insns_need_reload = 0;
891 something_needs_elimination = 0;
893 /* Initialize to -1, which means take the first spill register. */
896 /* Spill any hard regs that we know we can't eliminate. */
897 CLEAR_HARD_REG_SET (used_spill_regs);
898 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
899 if (! ep->can_eliminate)
900 spill_hard_reg (ep->from, 1);
902 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
903 if (frame_pointer_needed)
904 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
906 finish_spills (global);
908 /* From now on, we may need to generate moves differently. We may also
909 allow modifications of insns which cause them to not be recognized.
910 Any such modifications will be cleaned up during reload itself. */
911 reload_in_progress = 1;
913 /* This loop scans the entire function each go-round
914 and repeats until one repetition spills no additional hard regs. */
917 int something_changed;
920 HOST_WIDE_INT starting_frame_size;
922 /* Round size of stack frame to stack_alignment_needed. This must be done
923 here because the stack size may be a part of the offset computation
924 for register elimination, and there might have been new stack slots
925 created in the last iteration of this loop. */
926 if (cfun->stack_alignment_needed)
927 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
929 starting_frame_size = get_frame_size ();
931 set_initial_elim_offsets ();
932 set_initial_label_offsets ();
934 /* For each pseudo register that has an equivalent location defined,
935 try to eliminate any eliminable registers (such as the frame pointer)
936 assuming initial offsets for the replacement register, which
939 If the resulting location is directly addressable, substitute
940 the MEM we just got directly for the old REG.
942 If it is not addressable but is a constant or the sum of a hard reg
943 and constant, it is probably not addressable because the constant is
944 out of range, in that case record the address; we will generate
945 hairy code to compute the address in a register each time it is
946 needed. Similarly if it is a hard register, but one that is not
947 valid as an address register.
949 If the location is not addressable, but does not have one of the
950 above forms, assign a stack slot. We have to do this to avoid the
951 potential of producing lots of reloads if, e.g., a location involves
952 a pseudo that didn't get a hard register and has an equivalent memory
953 location that also involves a pseudo that didn't get a hard register.
955 Perhaps at some point we will improve reload_when_needed handling
956 so this problem goes away. But that's very hairy. */
958 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
959 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
961 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
963 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
965 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
966 else if (CONSTANT_P (XEXP (x, 0))
967 || (GET_CODE (XEXP (x, 0)) == REG
968 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
969 || (GET_CODE (XEXP (x, 0)) == PLUS
970 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
971 && (REGNO (XEXP (XEXP (x, 0), 0))
972 < FIRST_PSEUDO_REGISTER)
973 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
974 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
977 /* Make a new stack slot. Then indicate that something
978 changed so we go back and recompute offsets for
979 eliminable registers because the allocation of memory
980 below might change some offset. reg_equiv_{mem,address}
981 will be set up for this pseudo on the next pass around
983 reg_equiv_memory_loc[i] = 0;
984 reg_equiv_init[i] = 0;
989 if (caller_save_needed)
992 /* If we allocated another stack slot, redo elimination bookkeeping. */
993 if (starting_frame_size != get_frame_size ())
996 if (caller_save_needed)
998 save_call_clobbered_regs ();
999 /* That might have allocated new insn_chain structures. */
1000 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1003 calculate_needs_all_insns (global);
1005 CLEAR_REG_SET (&spilled_pseudos);
1008 something_changed = 0;
1010 /* If we allocated any new memory locations, make another pass
1011 since it might have changed elimination offsets. */
1012 if (starting_frame_size != get_frame_size ())
1013 something_changed = 1;
1016 HARD_REG_SET to_spill;
1017 CLEAR_HARD_REG_SET (to_spill);
1018 update_eliminables (&to_spill);
1019 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1020 if (TEST_HARD_REG_BIT (to_spill, i))
1022 spill_hard_reg (i, 1);
1025 /* Regardless of the state of spills, if we previously had
1026 a register that we thought we could eliminate, but no can
1027 not eliminate, we must run another pass.
1029 Consider pseudos which have an entry in reg_equiv_* which
1030 reference an eliminable register. We must make another pass
1031 to update reg_equiv_* so that we do not substitute in the
1032 old value from when we thought the elimination could be
1034 something_changed = 1;
1038 select_reload_regs ();
1042 if (insns_need_reload != 0 || did_spill)
1043 something_changed |= finish_spills (global);
1045 if (! something_changed)
1048 if (caller_save_needed)
1049 delete_caller_save_insns ();
1051 obstack_free (&reload_obstack, reload_firstobj);
1054 /* If global-alloc was run, notify it of any register eliminations we have
1057 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1058 if (ep->can_eliminate)
1059 mark_elimination (ep->from, ep->to);
1061 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1062 If that insn didn't set the register (i.e., it copied the register to
1063 memory), just delete that insn instead of the equivalencing insn plus
1064 anything now dead. If we call delete_dead_insn on that insn, we may
1065 delete the insn that actually sets the register if the register dies
1066 there and that is incorrect. */
1068 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1070 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1073 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1075 rtx equiv_insn = XEXP (list, 0);
1077 /* If we already deleted the insn or if it may trap, we can't
1078 delete it. The latter case shouldn't happen, but can
1079 if an insn has a variable address, gets a REG_EH_REGION
1080 note added to it, and then gets converted into an load
1081 from a constant address. */
1082 if (GET_CODE (equiv_insn) == NOTE
1083 || can_throw_internal (equiv_insn))
1085 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1086 delete_dead_insn (equiv_insn);
1089 PUT_CODE (equiv_insn, NOTE);
1090 NOTE_SOURCE_FILE (equiv_insn) = 0;
1091 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1097 /* Use the reload registers where necessary
1098 by generating move instructions to move the must-be-register
1099 values into or out of the reload registers. */
1101 if (insns_need_reload != 0 || something_needs_elimination
1102 || something_needs_operands_changed)
1104 HOST_WIDE_INT old_frame_size = get_frame_size ();
1106 reload_as_needed (global);
1108 if (old_frame_size != get_frame_size ())
1112 verify_initial_elim_offsets ();
1115 /* If we were able to eliminate the frame pointer, show that it is no
1116 longer live at the start of any basic block. If it ls live by
1117 virtue of being in a pseudo, that pseudo will be marked live
1118 and hence the frame pointer will be known to be live via that
1121 if (! frame_pointer_needed)
1123 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1124 HARD_FRAME_POINTER_REGNUM);
1126 /* Come here (with failure set nonzero) if we can't get enough spill regs
1127 and we decide not to abort about it. */
1130 CLEAR_REG_SET (&spilled_pseudos);
1131 reload_in_progress = 0;
1133 /* Now eliminate all pseudo regs by modifying them into
1134 their equivalent memory references.
1135 The REG-rtx's for the pseudos are modified in place,
1136 so all insns that used to refer to them now refer to memory.
1138 For a reg that has a reg_equiv_address, all those insns
1139 were changed by reloading so that no insns refer to it any longer;
1140 but the DECL_RTL of a variable decl may refer to it,
1141 and if so this causes the debugging info to mention the variable. */
1143 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1147 if (reg_equiv_mem[i])
1148 addr = XEXP (reg_equiv_mem[i], 0);
1150 if (reg_equiv_address[i])
1151 addr = reg_equiv_address[i];
1155 if (reg_renumber[i] < 0)
1157 rtx reg = regno_reg_rtx[i];
1159 REG_USERVAR_P (reg) = 0;
1160 PUT_CODE (reg, MEM);
1161 XEXP (reg, 0) = addr;
1162 if (reg_equiv_memory_loc[i])
1163 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1166 RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg)
1167 = MEM_SCALAR_P (reg) = 0;
1168 MEM_ATTRS (reg) = 0;
1171 else if (reg_equiv_mem[i])
1172 XEXP (reg_equiv_mem[i], 0) = addr;
1176 /* We must set reload_completed now since the cleanup_subreg_operands call
1177 below will re-recognize each insn and reload may have generated insns
1178 which are only valid during and after reload. */
1179 reload_completed = 1;
1181 /* Make a pass over all the insns and delete all USEs which we inserted
1182 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1183 notes. Delete all CLOBBER insns that don't refer to the return value
1184 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1185 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1186 and regenerate REG_INC notes that may have been moved around. */
1188 for (insn = first; insn; insn = NEXT_INSN (insn))
1193 if (GET_CODE (insn) == CALL_INSN)
1194 replace_pseudos_in_call_usage (& CALL_INSN_FUNCTION_USAGE (insn),
1196 CALL_INSN_FUNCTION_USAGE (insn));
1198 if ((GET_CODE (PATTERN (insn)) == USE
1199 /* We mark with QImode USEs introduced by reload itself. */
1200 && (GET_MODE (insn) == QImode
1201 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1202 || (GET_CODE (PATTERN (insn)) == CLOBBER
1203 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1204 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1210 pnote = ®_NOTES (insn);
1213 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1214 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1215 || REG_NOTE_KIND (*pnote) == REG_INC
1216 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1217 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1218 *pnote = XEXP (*pnote, 1);
1220 pnote = &XEXP (*pnote, 1);
1224 add_auto_inc_notes (insn, PATTERN (insn));
1227 /* And simplify (subreg (reg)) if it appears as an operand. */
1228 cleanup_subreg_operands (insn);
1231 /* If we are doing stack checking, give a warning if this function's
1232 frame size is larger than we expect. */
1233 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1235 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1236 static int verbose_warned = 0;
1238 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1239 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1240 size += UNITS_PER_WORD;
1242 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1244 warning ("frame size too large for reliable stack checking");
1245 if (! verbose_warned)
1247 warning ("try reducing the number of local variables");
1253 /* Indicate that we no longer have known memory locations or constants. */
1254 if (reg_equiv_constant)
1255 free (reg_equiv_constant);
1256 reg_equiv_constant = 0;
1257 if (reg_equiv_memory_loc)
1258 free (reg_equiv_memory_loc);
1259 reg_equiv_memory_loc = 0;
1262 free (real_known_ptr);
1266 free (reg_equiv_mem);
1267 free (reg_equiv_init);
1268 free (reg_equiv_address);
1269 free (reg_max_ref_width);
1270 free (reg_old_renumber);
1271 free (pseudo_previous_regs);
1272 free (pseudo_forbidden_regs);
1274 CLEAR_HARD_REG_SET (used_spill_regs);
1275 for (i = 0; i < n_spills; i++)
1276 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1278 /* Free all the insn_chain structures at once. */
1279 obstack_free (&reload_obstack, reload_startobj);
1280 unused_insn_chains = 0;
1281 fixup_abnormal_edges ();
1283 /* Replacing pseudos with their memory equivalents might have
1284 created shared rtx. Subsequent passes would get confused
1285 by this, so unshare everything here. */
1286 unshare_all_rtl_again (first);
1291 /* Yet another special case. Unfortunately, reg-stack forces people to
1292 write incorrect clobbers in asm statements. These clobbers must not
1293 cause the register to appear in bad_spill_regs, otherwise we'll call
1294 fatal_insn later. We clear the corresponding regnos in the live
1295 register sets to avoid this.
1296 The whole thing is rather sick, I'm afraid. */
1299 maybe_fix_stack_asms ()
1302 const char *constraints[MAX_RECOG_OPERANDS];
1303 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1304 struct insn_chain *chain;
1306 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1309 HARD_REG_SET clobbered, allowed;
1312 if (! INSN_P (chain->insn)
1313 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1315 pat = PATTERN (chain->insn);
1316 if (GET_CODE (pat) != PARALLEL)
1319 CLEAR_HARD_REG_SET (clobbered);
1320 CLEAR_HARD_REG_SET (allowed);
1322 /* First, make a mask of all stack regs that are clobbered. */
1323 for (i = 0; i < XVECLEN (pat, 0); i++)
1325 rtx t = XVECEXP (pat, 0, i);
1326 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1327 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1330 /* Get the operand values and constraints out of the insn. */
1331 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1332 constraints, operand_mode);
1334 /* For every operand, see what registers are allowed. */
1335 for (i = 0; i < noperands; i++)
1337 const char *p = constraints[i];
1338 /* For every alternative, we compute the class of registers allowed
1339 for reloading in CLS, and merge its contents into the reg set
1341 int cls = (int) NO_REGS;
1347 if (c == '\0' || c == ',' || c == '#')
1349 /* End of one alternative - mark the regs in the current
1350 class, and reset the class. */
1351 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1356 } while (c != '\0' && c != ',');
1364 case '=': case '+': case '*': case '%': case '?': case '!':
1365 case '0': case '1': case '2': case '3': case '4': case 'm':
1366 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1367 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1368 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1373 cls = (int) reg_class_subunion[cls]
1374 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1379 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1383 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1388 /* Those of the registers which are clobbered, but allowed by the
1389 constraints, must be usable as reload registers. So clear them
1390 out of the life information. */
1391 AND_HARD_REG_SET (allowed, clobbered);
1392 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1393 if (TEST_HARD_REG_BIT (allowed, i))
1395 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1396 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1403 /* Copy the global variables n_reloads and rld into the corresponding elts
1406 copy_reloads (chain)
1407 struct insn_chain *chain;
1409 chain->n_reloads = n_reloads;
1411 = (struct reload *) obstack_alloc (&reload_obstack,
1412 n_reloads * sizeof (struct reload));
1413 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1414 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1417 /* Walk the chain of insns, and determine for each whether it needs reloads
1418 and/or eliminations. Build the corresponding insns_need_reload list, and
1419 set something_needs_elimination as appropriate. */
1421 calculate_needs_all_insns (global)
1424 struct insn_chain **pprev_reload = &insns_need_reload;
1425 struct insn_chain *chain, *next = 0;
1427 something_needs_elimination = 0;
1429 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1430 for (chain = reload_insn_chain; chain != 0; chain = next)
1432 rtx insn = chain->insn;
1436 /* Clear out the shortcuts. */
1437 chain->n_reloads = 0;
1438 chain->need_elim = 0;
1439 chain->need_reload = 0;
1440 chain->need_operand_change = 0;
1442 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1443 include REG_LABEL), we need to see what effects this has on the
1444 known offsets at labels. */
1446 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1447 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1448 set_label_offsets (insn, insn, 0);
1452 rtx old_body = PATTERN (insn);
1453 int old_code = INSN_CODE (insn);
1454 rtx old_notes = REG_NOTES (insn);
1455 int did_elimination = 0;
1456 int operands_changed = 0;
1457 rtx set = single_set (insn);
1459 /* Skip insns that only set an equivalence. */
1460 if (set && GET_CODE (SET_DEST (set)) == REG
1461 && reg_renumber[REGNO (SET_DEST (set))] < 0
1462 && reg_equiv_constant[REGNO (SET_DEST (set))])
1465 /* If needed, eliminate any eliminable registers. */
1466 if (num_eliminable || num_eliminable_invariants)
1467 did_elimination = eliminate_regs_in_insn (insn, 0);
1469 /* Analyze the instruction. */
1470 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1471 global, spill_reg_order);
1473 /* If a no-op set needs more than one reload, this is likely
1474 to be something that needs input address reloads. We
1475 can't get rid of this cleanly later, and it is of no use
1476 anyway, so discard it now.
1477 We only do this when expensive_optimizations is enabled,
1478 since this complements reload inheritance / output
1479 reload deletion, and it can make debugging harder. */
1480 if (flag_expensive_optimizations && n_reloads > 1)
1482 rtx set = single_set (insn);
1484 && SET_SRC (set) == SET_DEST (set)
1485 && GET_CODE (SET_SRC (set)) == REG
1486 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1489 /* Delete it from the reload chain */
1491 chain->prev->next = next;
1493 reload_insn_chain = next;
1495 next->prev = chain->prev;
1496 chain->next = unused_insn_chains;
1497 unused_insn_chains = chain;
1502 update_eliminable_offsets ();
1504 /* Remember for later shortcuts which insns had any reloads or
1505 register eliminations. */
1506 chain->need_elim = did_elimination;
1507 chain->need_reload = n_reloads > 0;
1508 chain->need_operand_change = operands_changed;
1510 /* Discard any register replacements done. */
1511 if (did_elimination)
1513 obstack_free (&reload_obstack, reload_insn_firstobj);
1514 PATTERN (insn) = old_body;
1515 INSN_CODE (insn) = old_code;
1516 REG_NOTES (insn) = old_notes;
1517 something_needs_elimination = 1;
1520 something_needs_operands_changed |= operands_changed;
1524 copy_reloads (chain);
1525 *pprev_reload = chain;
1526 pprev_reload = &chain->next_need_reload;
1533 /* Comparison function for qsort to decide which of two reloads
1534 should be handled first. *P1 and *P2 are the reload numbers. */
1537 reload_reg_class_lower (r1p, r2p)
1541 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1544 /* Consider required reloads before optional ones. */
1545 t = rld[r1].optional - rld[r2].optional;
1549 /* Count all solitary classes before non-solitary ones. */
1550 t = ((reg_class_size[(int) rld[r2].class] == 1)
1551 - (reg_class_size[(int) rld[r1].class] == 1));
1555 /* Aside from solitaires, consider all multi-reg groups first. */
1556 t = rld[r2].nregs - rld[r1].nregs;
1560 /* Consider reloads in order of increasing reg-class number. */
1561 t = (int) rld[r1].class - (int) rld[r2].class;
1565 /* If reloads are equally urgent, sort by reload number,
1566 so that the results of qsort leave nothing to chance. */
1570 /* The cost of spilling each hard reg. */
1571 static int spill_cost[FIRST_PSEUDO_REGISTER];
1573 /* When spilling multiple hard registers, we use SPILL_COST for the first
1574 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1575 only the first hard reg for a multi-reg pseudo. */
1576 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1578 /* Update the spill cost arrays, considering that pseudo REG is live. */
1584 int freq = REG_FREQ (reg);
1585 int r = reg_renumber[reg];
1588 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1589 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1592 SET_REGNO_REG_SET (&pseudos_counted, reg);
1597 spill_add_cost[r] += freq;
1599 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1601 spill_cost[r + nregs] += freq;
1604 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1605 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1608 order_regs_for_reload (chain)
1609 struct insn_chain *chain;
1612 HARD_REG_SET used_by_pseudos;
1613 HARD_REG_SET used_by_pseudos2;
1615 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1617 memset (spill_cost, 0, sizeof spill_cost);
1618 memset (spill_add_cost, 0, sizeof spill_add_cost);
1620 /* Count number of uses of each hard reg by pseudo regs allocated to it
1621 and then order them by decreasing use. First exclude hard registers
1622 that are live in or across this insn. */
1624 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1625 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1626 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1627 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1629 /* Now find out which pseudos are allocated to it, and update
1631 CLEAR_REG_SET (&pseudos_counted);
1633 EXECUTE_IF_SET_IN_REG_SET
1634 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1638 EXECUTE_IF_SET_IN_REG_SET
1639 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1643 CLEAR_REG_SET (&pseudos_counted);
1646 /* Vector of reload-numbers showing the order in which the reloads should
1648 static short reload_order[MAX_RELOADS];
1650 /* This is used to keep track of the spill regs used in one insn. */
1651 static HARD_REG_SET used_spill_regs_local;
1653 /* We decided to spill hard register SPILLED, which has a size of
1654 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1655 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1656 update SPILL_COST/SPILL_ADD_COST. */
1659 count_spilled_pseudo (spilled, spilled_nregs, reg)
1660 int spilled, spilled_nregs, reg;
1662 int r = reg_renumber[reg];
1663 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1665 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1666 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1669 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1671 spill_add_cost[r] -= REG_FREQ (reg);
1673 spill_cost[r + nregs] -= REG_FREQ (reg);
1676 /* Find reload register to use for reload number ORDER. */
1679 find_reg (chain, order)
1680 struct insn_chain *chain;
1683 int rnum = reload_order[order];
1684 struct reload *rl = rld + rnum;
1685 int best_cost = INT_MAX;
1689 HARD_REG_SET not_usable;
1690 HARD_REG_SET used_by_other_reload;
1692 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1693 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1694 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1696 CLEAR_HARD_REG_SET (used_by_other_reload);
1697 for (k = 0; k < order; k++)
1699 int other = reload_order[k];
1701 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1702 for (j = 0; j < rld[other].nregs; j++)
1703 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1706 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1708 unsigned int regno = i;
1710 if (! TEST_HARD_REG_BIT (not_usable, regno)
1711 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1712 && HARD_REGNO_MODE_OK (regno, rl->mode))
1714 int this_cost = spill_cost[regno];
1716 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1718 for (j = 1; j < this_nregs; j++)
1720 this_cost += spill_add_cost[regno + j];
1721 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1722 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1727 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1729 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1731 if (this_cost < best_cost
1732 /* Among registers with equal cost, prefer caller-saved ones, or
1733 use REG_ALLOC_ORDER if it is defined. */
1734 || (this_cost == best_cost
1735 #ifdef REG_ALLOC_ORDER
1736 && (inv_reg_alloc_order[regno]
1737 < inv_reg_alloc_order[best_reg])
1739 && call_used_regs[regno]
1740 && ! call_used_regs[best_reg]
1745 best_cost = this_cost;
1753 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1755 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1756 rl->regno = best_reg;
1758 EXECUTE_IF_SET_IN_REG_SET
1759 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1761 count_spilled_pseudo (best_reg, rl->nregs, j);
1764 EXECUTE_IF_SET_IN_REG_SET
1765 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1767 count_spilled_pseudo (best_reg, rl->nregs, j);
1770 for (i = 0; i < rl->nregs; i++)
1772 if (spill_cost[best_reg + i] != 0
1773 || spill_add_cost[best_reg + i] != 0)
1775 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1780 /* Find more reload regs to satisfy the remaining need of an insn, which
1782 Do it by ascending class number, since otherwise a reg
1783 might be spilled for a big class and might fail to count
1784 for a smaller class even though it belongs to that class. */
1787 find_reload_regs (chain)
1788 struct insn_chain *chain;
1792 /* In order to be certain of getting the registers we need,
1793 we must sort the reloads into order of increasing register class.
1794 Then our grabbing of reload registers will parallel the process
1795 that provided the reload registers. */
1796 for (i = 0; i < chain->n_reloads; i++)
1798 /* Show whether this reload already has a hard reg. */
1799 if (chain->rld[i].reg_rtx)
1801 int regno = REGNO (chain->rld[i].reg_rtx);
1802 chain->rld[i].regno = regno;
1804 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1807 chain->rld[i].regno = -1;
1808 reload_order[i] = i;
1811 n_reloads = chain->n_reloads;
1812 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1814 CLEAR_HARD_REG_SET (used_spill_regs_local);
1817 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1819 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1821 /* Compute the order of preference for hard registers to spill. */
1823 order_regs_for_reload (chain);
1825 for (i = 0; i < n_reloads; i++)
1827 int r = reload_order[i];
1829 /* Ignore reloads that got marked inoperative. */
1830 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1831 && ! rld[r].optional
1832 && rld[r].regno == -1)
1833 if (! find_reg (chain, i))
1835 spill_failure (chain->insn, rld[r].class);
1841 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1842 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1844 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1848 select_reload_regs ()
1850 struct insn_chain *chain;
1852 /* Try to satisfy the needs for each insn. */
1853 for (chain = insns_need_reload; chain != 0;
1854 chain = chain->next_need_reload)
1855 find_reload_regs (chain);
1858 /* Delete all insns that were inserted by emit_caller_save_insns during
1861 delete_caller_save_insns ()
1863 struct insn_chain *c = reload_insn_chain;
1867 while (c != 0 && c->is_caller_save_insn)
1869 struct insn_chain *next = c->next;
1872 if (c == reload_insn_chain)
1873 reload_insn_chain = next;
1877 next->prev = c->prev;
1879 c->prev->next = next;
1880 c->next = unused_insn_chains;
1881 unused_insn_chains = c;
1889 /* Handle the failure to find a register to spill.
1890 INSN should be one of the insns which needed this particular spill reg. */
1893 spill_failure (insn, class)
1895 enum reg_class class;
1897 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1898 if (asm_noperands (PATTERN (insn)) >= 0)
1899 error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'",
1900 reg_class_names[class]);
1903 error ("unable to find a register to spill in class `%s'",
1904 reg_class_names[class]);
1905 fatal_insn ("this is the insn:", insn);
1909 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1910 data that is dead in INSN. */
1913 delete_dead_insn (insn)
1916 rtx prev = prev_real_insn (insn);
1919 /* If the previous insn sets a register that dies in our insn, delete it
1921 if (prev && GET_CODE (PATTERN (prev)) == SET
1922 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1923 && reg_mentioned_p (prev_dest, PATTERN (insn))
1924 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1925 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1926 delete_dead_insn (prev);
1928 PUT_CODE (insn, NOTE);
1929 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1930 NOTE_SOURCE_FILE (insn) = 0;
1933 /* Modify the home of pseudo-reg I.
1934 The new home is present in reg_renumber[I].
1936 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1937 or it may be -1, meaning there is none or it is not relevant.
1938 This is used so that all pseudos spilled from a given hard reg
1939 can share one stack slot. */
1942 alter_reg (i, from_reg)
1946 /* When outputting an inline function, this can happen
1947 for a reg that isn't actually used. */
1948 if (regno_reg_rtx[i] == 0)
1951 /* If the reg got changed to a MEM at rtl-generation time,
1953 if (GET_CODE (regno_reg_rtx[i]) != REG)
1956 /* Modify the reg-rtx to contain the new hard reg
1957 number or else to contain its pseudo reg number. */
1958 REGNO (regno_reg_rtx[i])
1959 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1961 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1962 allocate a stack slot for it. */
1964 if (reg_renumber[i] < 0
1965 && REG_N_REFS (i) > 0
1966 && reg_equiv_constant[i] == 0
1967 && reg_equiv_memory_loc[i] == 0)
1970 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1971 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1974 /* Each pseudo reg has an inherent size which comes from its own mode,
1975 and a total size which provides room for paradoxical subregs
1976 which refer to the pseudo reg in wider modes.
1978 We can use a slot already allocated if it provides both
1979 enough inherent space and enough total space.
1980 Otherwise, we allocate a new slot, making sure that it has no less
1981 inherent space, and no less total space, then the previous slot. */
1984 /* No known place to spill from => no slot to reuse. */
1985 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1986 inherent_size == total_size ? 0 : -1);
1987 if (BYTES_BIG_ENDIAN)
1988 /* Cancel the big-endian correction done in assign_stack_local.
1989 Get the address of the beginning of the slot.
1990 This is so we can do a big-endian correction unconditionally
1992 adjust = inherent_size - total_size;
1994 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1996 /* Nothing can alias this slot except this pseudo. */
1997 set_mem_alias_set (x, new_alias_set ());
2000 /* Reuse a stack slot if possible. */
2001 else if (spill_stack_slot[from_reg] != 0
2002 && spill_stack_slot_width[from_reg] >= total_size
2003 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2005 x = spill_stack_slot[from_reg];
2007 /* Allocate a bigger slot. */
2010 /* Compute maximum size needed, both for inherent size
2011 and for total size. */
2012 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2015 if (spill_stack_slot[from_reg])
2017 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2019 mode = GET_MODE (spill_stack_slot[from_reg]);
2020 if (spill_stack_slot_width[from_reg] > total_size)
2021 total_size = spill_stack_slot_width[from_reg];
2024 /* Make a slot with that size. */
2025 x = assign_stack_local (mode, total_size,
2026 inherent_size == total_size ? 0 : -1);
2029 /* All pseudos mapped to this slot can alias each other. */
2030 if (spill_stack_slot[from_reg])
2031 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2033 set_mem_alias_set (x, new_alias_set ());
2035 if (BYTES_BIG_ENDIAN)
2037 /* Cancel the big-endian correction done in assign_stack_local.
2038 Get the address of the beginning of the slot.
2039 This is so we can do a big-endian correction unconditionally
2041 adjust = GET_MODE_SIZE (mode) - total_size;
2044 = adjust_address_nv (x, mode_for_size (total_size
2050 spill_stack_slot[from_reg] = stack_slot;
2051 spill_stack_slot_width[from_reg] = total_size;
2054 /* On a big endian machine, the "address" of the slot
2055 is the address of the low part that fits its inherent mode. */
2056 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2057 adjust += (total_size - inherent_size);
2059 /* If we have any adjustment to make, or if the stack slot is the
2060 wrong mode, make a new stack slot. */
2061 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2063 /* If we have a decl for the original register, set it for the
2064 memory. If this is a shared MEM, make a copy. */
2067 rtx decl = DECL_RTL_IF_SET (REGNO_DECL (i));
2069 /* We can do this only for the DECLs home pseudo, not for
2070 any copies of it, since otherwise when the stack slot
2071 is reused, nonoverlapping_memrefs_p might think they
2073 if (decl && GET_CODE (decl) == REG && REGNO (decl) == (unsigned) i)
2075 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2078 set_mem_expr (x, REGNO_DECL (i));
2082 /* Save the stack slot for later. */
2083 reg_equiv_memory_loc[i] = x;
2087 /* Mark the slots in regs_ever_live for the hard regs
2088 used by pseudo-reg number REGNO. */
2091 mark_home_live (regno)
2096 i = reg_renumber[regno];
2099 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2101 regs_ever_live[i++] = 1;
2104 /* This function handles the tracking of elimination offsets around branches.
2106 X is a piece of RTL being scanned.
2108 INSN is the insn that it came from, if any.
2110 INITIAL_P is non-zero if we are to set the offset to be the initial
2111 offset and zero if we are setting the offset of the label to be the
2115 set_label_offsets (x, insn, initial_p)
2120 enum rtx_code code = GET_CODE (x);
2123 struct elim_table *p;
2128 if (LABEL_REF_NONLOCAL_P (x))
2133 /* ... fall through ... */
2136 /* If we know nothing about this label, set the desired offsets. Note
2137 that this sets the offset at a label to be the offset before a label
2138 if we don't know anything about the label. This is not correct for
2139 the label after a BARRIER, but is the best guess we can make. If
2140 we guessed wrong, we will suppress an elimination that might have
2141 been possible had we been able to guess correctly. */
2143 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2145 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2146 offsets_at[CODE_LABEL_NUMBER (x)][i]
2147 = (initial_p ? reg_eliminate[i].initial_offset
2148 : reg_eliminate[i].offset);
2149 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2152 /* Otherwise, if this is the definition of a label and it is
2153 preceded by a BARRIER, set our offsets to the known offset of
2157 && (tem = prev_nonnote_insn (insn)) != 0
2158 && GET_CODE (tem) == BARRIER)
2159 set_offsets_for_label (insn);
2161 /* If neither of the above cases is true, compare each offset
2162 with those previously recorded and suppress any eliminations
2163 where the offsets disagree. */
2165 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2166 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2167 != (initial_p ? reg_eliminate[i].initial_offset
2168 : reg_eliminate[i].offset))
2169 reg_eliminate[i].can_eliminate = 0;
2174 set_label_offsets (PATTERN (insn), insn, initial_p);
2176 /* ... fall through ... */
2180 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2181 and hence must have all eliminations at their initial offsets. */
2182 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2183 if (REG_NOTE_KIND (tem) == REG_LABEL)
2184 set_label_offsets (XEXP (tem, 0), insn, 1);
2190 /* Each of the labels in the parallel or address vector must be
2191 at their initial offsets. We want the first field for PARALLEL
2192 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2194 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2195 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2200 /* We only care about setting PC. If the source is not RETURN,
2201 IF_THEN_ELSE, or a label, disable any eliminations not at
2202 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2203 isn't one of those possibilities. For branches to a label,
2204 call ourselves recursively.
2206 Note that this can disable elimination unnecessarily when we have
2207 a non-local goto since it will look like a non-constant jump to
2208 someplace in the current function. This isn't a significant
2209 problem since such jumps will normally be when all elimination
2210 pairs are back to their initial offsets. */
2212 if (SET_DEST (x) != pc_rtx)
2215 switch (GET_CODE (SET_SRC (x)))
2222 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2226 tem = XEXP (SET_SRC (x), 1);
2227 if (GET_CODE (tem) == LABEL_REF)
2228 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2229 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2232 tem = XEXP (SET_SRC (x), 2);
2233 if (GET_CODE (tem) == LABEL_REF)
2234 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2235 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2243 /* If we reach here, all eliminations must be at their initial
2244 offset because we are doing a jump to a variable address. */
2245 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2246 if (p->offset != p->initial_offset)
2247 p->can_eliminate = 0;
2255 /* Scan X and replace any eliminable registers (such as fp) with a
2256 replacement (such as sp), plus an offset.
2258 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2259 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2260 MEM, we are allowed to replace a sum of a register and the constant zero
2261 with the register, which we cannot do outside a MEM. In addition, we need
2262 to record the fact that a register is referenced outside a MEM.
2264 If INSN is an insn, it is the insn containing X. If we replace a REG
2265 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2266 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2267 the REG is being modified.
2269 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2270 That's used when we eliminate in expressions stored in notes.
2271 This means, do not set ref_outside_mem even if the reference
2274 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2275 replacements done assuming all offsets are at their initial values. If
2276 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2277 encounter, return the actual location so that find_reloads will do
2278 the proper thing. */
2281 eliminate_regs (x, mem_mode, insn)
2283 enum machine_mode mem_mode;
2286 enum rtx_code code = GET_CODE (x);
2287 struct elim_table *ep;
2294 if (! current_function_decl)
2314 /* This is only for the benefit of the debugging backends, which call
2315 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2316 removed after CSE. */
2317 new = eliminate_regs (XEXP (x, 0), 0, insn);
2318 if (GET_CODE (new) == MEM)
2319 return XEXP (new, 0);
2325 /* First handle the case where we encounter a bare register that
2326 is eliminable. Replace it with a PLUS. */
2327 if (regno < FIRST_PSEUDO_REGISTER)
2329 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2331 if (ep->from_rtx == x && ep->can_eliminate)
2332 return plus_constant (ep->to_rtx, ep->previous_offset);
2335 else if (reg_renumber && reg_renumber[regno] < 0
2336 && reg_equiv_constant && reg_equiv_constant[regno]
2337 && ! CONSTANT_P (reg_equiv_constant[regno]))
2338 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2342 /* You might think handling MINUS in a manner similar to PLUS is a
2343 good idea. It is not. It has been tried multiple times and every
2344 time the change has had to have been reverted.
2346 Other parts of reload know a PLUS is special (gen_reload for example)
2347 and require special code to handle code a reloaded PLUS operand.
2349 Also consider backends where the flags register is clobbered by a
2350 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2351 lea instruction comes to mind). If we try to reload a MINUS, we
2352 may kill the flags register that was holding a useful value.
2354 So, please before trying to handle MINUS, consider reload as a
2355 whole instead of this little section as well as the backend issues. */
2357 /* If this is the sum of an eliminable register and a constant, rework
2359 if (GET_CODE (XEXP (x, 0)) == REG
2360 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2361 && CONSTANT_P (XEXP (x, 1)))
2363 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2365 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2367 /* The only time we want to replace a PLUS with a REG (this
2368 occurs when the constant operand of the PLUS is the negative
2369 of the offset) is when we are inside a MEM. We won't want
2370 to do so at other times because that would change the
2371 structure of the insn in a way that reload can't handle.
2372 We special-case the commonest situation in
2373 eliminate_regs_in_insn, so just replace a PLUS with a
2374 PLUS here, unless inside a MEM. */
2375 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2376 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2379 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2380 plus_constant (XEXP (x, 1),
2381 ep->previous_offset));
2384 /* If the register is not eliminable, we are done since the other
2385 operand is a constant. */
2389 /* If this is part of an address, we want to bring any constant to the
2390 outermost PLUS. We will do this by doing register replacement in
2391 our operands and seeing if a constant shows up in one of them.
2393 Note that there is no risk of modifying the structure of the insn,
2394 since we only get called for its operands, thus we are either
2395 modifying the address inside a MEM, or something like an address
2396 operand of a load-address insn. */
2399 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2400 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2402 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2404 /* If one side is a PLUS and the other side is a pseudo that
2405 didn't get a hard register but has a reg_equiv_constant,
2406 we must replace the constant here since it may no longer
2407 be in the position of any operand. */
2408 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2409 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2410 && reg_renumber[REGNO (new1)] < 0
2411 && reg_equiv_constant != 0
2412 && reg_equiv_constant[REGNO (new1)] != 0)
2413 new1 = reg_equiv_constant[REGNO (new1)];
2414 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2415 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2416 && reg_renumber[REGNO (new0)] < 0
2417 && reg_equiv_constant[REGNO (new0)] != 0)
2418 new0 = reg_equiv_constant[REGNO (new0)];
2420 new = form_sum (new0, new1);
2422 /* As above, if we are not inside a MEM we do not want to
2423 turn a PLUS into something else. We might try to do so here
2424 for an addition of 0 if we aren't optimizing. */
2425 if (! mem_mode && GET_CODE (new) != PLUS)
2426 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2434 /* If this is the product of an eliminable register and a
2435 constant, apply the distribute law and move the constant out
2436 so that we have (plus (mult ..) ..). This is needed in order
2437 to keep load-address insns valid. This case is pathological.
2438 We ignore the possibility of overflow here. */
2439 if (GET_CODE (XEXP (x, 0)) == REG
2440 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2441 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2442 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2444 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2447 /* Refs inside notes don't count for this purpose. */
2448 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2449 || GET_CODE (insn) == INSN_LIST)))
2450 ep->ref_outside_mem = 1;
2453 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2454 ep->previous_offset * INTVAL (XEXP (x, 1)));
2457 /* ... fall through ... */
2461 /* See comments before PLUS about handling MINUS. */
2463 case DIV: case UDIV:
2464 case MOD: case UMOD:
2465 case AND: case IOR: case XOR:
2466 case ROTATERT: case ROTATE:
2467 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2469 case GE: case GT: case GEU: case GTU:
2470 case LE: case LT: case LEU: case LTU:
2472 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2474 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2476 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2477 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2482 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2485 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2486 if (new != XEXP (x, 0))
2488 /* If this is a REG_DEAD note, it is not valid anymore.
2489 Using the eliminated version could result in creating a
2490 REG_DEAD note for the stack or frame pointer. */
2491 if (GET_MODE (x) == REG_DEAD)
2493 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2496 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2500 /* ... fall through ... */
2503 /* Now do eliminations in the rest of the chain. If this was
2504 an EXPR_LIST, this might result in allocating more memory than is
2505 strictly needed, but it simplifies the code. */
2508 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2509 if (new != XEXP (x, 1))
2511 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2519 case STRICT_LOW_PART:
2521 case SIGN_EXTEND: case ZERO_EXTEND:
2522 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2523 case FLOAT: case FIX:
2524 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2528 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2529 if (new != XEXP (x, 0))
2530 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2534 /* Similar to above processing, but preserve SUBREG_BYTE.
2535 Convert (subreg (mem)) to (mem) if not paradoxical.
2536 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2537 pseudo didn't get a hard reg, we must replace this with the
2538 eliminated version of the memory location because push_reloads
2539 may do the replacement in certain circumstances. */
2540 if (GET_CODE (SUBREG_REG (x)) == REG
2541 && (GET_MODE_SIZE (GET_MODE (x))
2542 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2543 && reg_equiv_memory_loc != 0
2544 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2546 new = SUBREG_REG (x);
2549 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2551 if (new != SUBREG_REG (x))
2553 int x_size = GET_MODE_SIZE (GET_MODE (x));
2554 int new_size = GET_MODE_SIZE (GET_MODE (new));
2556 if (GET_CODE (new) == MEM
2557 && ((x_size < new_size
2558 #ifdef WORD_REGISTER_OPERATIONS
2559 /* On these machines, combine can create rtl of the form
2560 (set (subreg:m1 (reg:m2 R) 0) ...)
2561 where m1 < m2, and expects something interesting to
2562 happen to the entire word. Moreover, it will use the
2563 (reg:m2 R) later, expecting all bits to be preserved.
2564 So if the number of words is the same, preserve the
2565 subreg so that push_reloads can see it. */
2566 && ! ((x_size - 1) / UNITS_PER_WORD
2567 == (new_size -1 ) / UNITS_PER_WORD)
2570 || x_size == new_size)
2572 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2574 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2580 /* This is only for the benefit of the debugging backends, which call
2581 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2582 removed after CSE. */
2583 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2584 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2586 /* Our only special processing is to pass the mode of the MEM to our
2587 recursive call and copy the flags. While we are here, handle this
2588 case more efficiently. */
2590 replace_equiv_address_nv (x,
2591 eliminate_regs (XEXP (x, 0),
2592 GET_MODE (x), insn));
2595 /* Handle insn_list USE that a call to a pure function may generate. */
2596 new = eliminate_regs (XEXP (x, 0), 0, insn);
2597 if (new != XEXP (x, 0))
2598 return gen_rtx_USE (GET_MODE (x), new);
2610 /* Process each of our operands recursively. If any have changed, make a
2612 fmt = GET_RTX_FORMAT (code);
2613 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2617 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2618 if (new != XEXP (x, i) && ! copied)
2620 rtx new_x = rtx_alloc (code);
2622 (sizeof (*new_x) - sizeof (new_x->fld)
2623 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2629 else if (*fmt == 'E')
2632 for (j = 0; j < XVECLEN (x, i); j++)
2634 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2635 if (new != XVECEXP (x, i, j) && ! copied_vec)
2637 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2641 rtx new_x = rtx_alloc (code);
2643 (sizeof (*new_x) - sizeof (new_x->fld)
2644 + (sizeof (new_x->fld[0])
2645 * GET_RTX_LENGTH (code))));
2649 XVEC (x, i) = new_v;
2652 XVECEXP (x, i, j) = new;
2660 /* Scan rtx X for modifications of elimination target registers. Update
2661 the table of eliminables to reflect the changed state. MEM_MODE is
2662 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2665 elimination_effects (x, mem_mode)
2667 enum machine_mode mem_mode;
2670 enum rtx_code code = GET_CODE (x);
2671 struct elim_table *ep;
2698 /* First handle the case where we encounter a bare register that
2699 is eliminable. Replace it with a PLUS. */
2700 if (regno < FIRST_PSEUDO_REGISTER)
2702 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2704 if (ep->from_rtx == x && ep->can_eliminate)
2707 ep->ref_outside_mem = 1;
2712 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2713 && reg_equiv_constant[regno]
2714 && ! function_invariant_p (reg_equiv_constant[regno]))
2715 elimination_effects (reg_equiv_constant[regno], mem_mode);
2724 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2725 if (ep->to_rtx == XEXP (x, 0))
2727 int size = GET_MODE_SIZE (mem_mode);
2729 /* If more bytes than MEM_MODE are pushed, account for them. */
2730 #ifdef PUSH_ROUNDING
2731 if (ep->to_rtx == stack_pointer_rtx)
2732 size = PUSH_ROUNDING (size);
2734 if (code == PRE_DEC || code == POST_DEC)
2736 else if (code == PRE_INC || code == POST_INC)
2738 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2739 && GET_CODE (XEXP (x, 1)) == PLUS
2740 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2741 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2742 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2745 /* These two aren't unary operators. */
2746 if (code == POST_MODIFY || code == PRE_MODIFY)
2749 /* Fall through to generic unary operation case. */
2750 case STRICT_LOW_PART:
2752 case SIGN_EXTEND: case ZERO_EXTEND:
2753 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2754 case FLOAT: case FIX:
2755 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2759 elimination_effects (XEXP (x, 0), mem_mode);
2763 if (GET_CODE (SUBREG_REG (x)) == REG
2764 && (GET_MODE_SIZE (GET_MODE (x))
2765 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2766 && reg_equiv_memory_loc != 0
2767 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2770 elimination_effects (SUBREG_REG (x), mem_mode);
2774 /* If using a register that is the source of an eliminate we still
2775 think can be performed, note it cannot be performed since we don't
2776 know how this register is used. */
2777 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2778 if (ep->from_rtx == XEXP (x, 0))
2779 ep->can_eliminate = 0;
2781 elimination_effects (XEXP (x, 0), mem_mode);
2785 /* If clobbering a register that is the replacement register for an
2786 elimination we still think can be performed, note that it cannot
2787 be performed. Otherwise, we need not be concerned about it. */
2788 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2789 if (ep->to_rtx == XEXP (x, 0))
2790 ep->can_eliminate = 0;
2792 elimination_effects (XEXP (x, 0), mem_mode);
2796 /* Check for setting a register that we know about. */
2797 if (GET_CODE (SET_DEST (x)) == REG)
2799 /* See if this is setting the replacement register for an
2802 If DEST is the hard frame pointer, we do nothing because we
2803 assume that all assignments to the frame pointer are for
2804 non-local gotos and are being done at a time when they are valid
2805 and do not disturb anything else. Some machines want to
2806 eliminate a fake argument pointer (or even a fake frame pointer)
2807 with either the real frame or the stack pointer. Assignments to
2808 the hard frame pointer must not prevent this elimination. */
2810 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2812 if (ep->to_rtx == SET_DEST (x)
2813 && SET_DEST (x) != hard_frame_pointer_rtx)
2815 /* If it is being incremented, adjust the offset. Otherwise,
2816 this elimination can't be done. */
2817 rtx src = SET_SRC (x);
2819 if (GET_CODE (src) == PLUS
2820 && XEXP (src, 0) == SET_DEST (x)
2821 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2822 ep->offset -= INTVAL (XEXP (src, 1));
2824 ep->can_eliminate = 0;
2828 elimination_effects (SET_DEST (x), 0);
2829 elimination_effects (SET_SRC (x), 0);
2833 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2836 /* Our only special processing is to pass the mode of the MEM to our
2838 elimination_effects (XEXP (x, 0), GET_MODE (x));
2845 fmt = GET_RTX_FORMAT (code);
2846 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2849 elimination_effects (XEXP (x, i), mem_mode);
2850 else if (*fmt == 'E')
2851 for (j = 0; j < XVECLEN (x, i); j++)
2852 elimination_effects (XVECEXP (x, i, j), mem_mode);
2856 /* Descend through rtx X and verify that no references to eliminable registers
2857 remain. If any do remain, mark the involved register as not
2861 check_eliminable_occurrences (x)
2871 code = GET_CODE (x);
2873 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2875 struct elim_table *ep;
2877 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2878 if (ep->from_rtx == x && ep->can_eliminate)
2879 ep->can_eliminate = 0;
2883 fmt = GET_RTX_FORMAT (code);
2884 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2887 check_eliminable_occurrences (XEXP (x, i));
2888 else if (*fmt == 'E')
2891 for (j = 0; j < XVECLEN (x, i); j++)
2892 check_eliminable_occurrences (XVECEXP (x, i, j));
2897 /* Scan INSN and eliminate all eliminable registers in it.
2899 If REPLACE is nonzero, do the replacement destructively. Also
2900 delete the insn as dead it if it is setting an eliminable register.
2902 If REPLACE is zero, do all our allocations in reload_obstack.
2904 If no eliminations were done and this insn doesn't require any elimination
2905 processing (these are not identical conditions: it might be updating sp,
2906 but not referencing fp; this needs to be seen during reload_as_needed so
2907 that the offset between fp and sp can be taken into consideration), zero
2908 is returned. Otherwise, 1 is returned. */
2911 eliminate_regs_in_insn (insn, replace)
2915 int icode = recog_memoized (insn);
2916 rtx old_body = PATTERN (insn);
2917 int insn_is_asm = asm_noperands (old_body) >= 0;
2918 rtx old_set = single_set (insn);
2922 rtx substed_operand[MAX_RECOG_OPERANDS];
2923 rtx orig_operand[MAX_RECOG_OPERANDS];
2924 struct elim_table *ep;
2926 if (! insn_is_asm && icode < 0)
2928 if (GET_CODE (PATTERN (insn)) == USE
2929 || GET_CODE (PATTERN (insn)) == CLOBBER
2930 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2931 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2932 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2937 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2938 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2940 /* Check for setting an eliminable register. */
2941 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2942 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2944 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2945 /* If this is setting the frame pointer register to the
2946 hardware frame pointer register and this is an elimination
2947 that will be done (tested above), this insn is really
2948 adjusting the frame pointer downward to compensate for
2949 the adjustment done before a nonlocal goto. */
2950 if (ep->from == FRAME_POINTER_REGNUM
2951 && ep->to == HARD_FRAME_POINTER_REGNUM)
2953 rtx base = SET_SRC (old_set);
2954 rtx base_insn = insn;
2957 while (base != ep->to_rtx)
2959 rtx prev_insn, prev_set;
2961 if (GET_CODE (base) == PLUS
2962 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2964 offset += INTVAL (XEXP (base, 1));
2965 base = XEXP (base, 0);
2967 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2968 && (prev_set = single_set (prev_insn)) != 0
2969 && rtx_equal_p (SET_DEST (prev_set), base))
2971 base = SET_SRC (prev_set);
2972 base_insn = prev_insn;
2978 if (base == ep->to_rtx)
2981 = plus_constant (ep->to_rtx, offset - ep->offset);
2983 new_body = old_body;
2986 new_body = copy_insn (old_body);
2987 if (REG_NOTES (insn))
2988 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2990 PATTERN (insn) = new_body;
2991 old_set = single_set (insn);
2993 /* First see if this insn remains valid when we
2994 make the change. If not, keep the INSN_CODE
2995 the same and let reload fit it up. */
2996 validate_change (insn, &SET_SRC (old_set), src, 1);
2997 validate_change (insn, &SET_DEST (old_set),
2999 if (! apply_change_group ())
3001 SET_SRC (old_set) = src;
3002 SET_DEST (old_set) = ep->to_rtx;
3011 /* In this case this insn isn't serving a useful purpose. We
3012 will delete it in reload_as_needed once we know that this
3013 elimination is, in fact, being done.
3015 If REPLACE isn't set, we can't delete this insn, but needn't
3016 process it since it won't be used unless something changes. */
3019 delete_dead_insn (insn);
3027 /* We allow one special case which happens to work on all machines we
3028 currently support: a single set with the source being a PLUS of an
3029 eliminable register and a constant. */
3031 && GET_CODE (SET_DEST (old_set)) == REG
3032 && GET_CODE (SET_SRC (old_set)) == PLUS
3033 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3034 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
3035 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
3037 rtx reg = XEXP (SET_SRC (old_set), 0);
3038 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
3040 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3041 if (ep->from_rtx == reg && ep->can_eliminate)
3043 offset += ep->offset;
3048 /* We assume here that if we need a PARALLEL with
3049 CLOBBERs for this assignment, we can do with the
3050 MATCH_SCRATCHes that add_clobbers allocates.
3051 There's not much we can do if that doesn't work. */
3052 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3056 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3059 rtvec vec = rtvec_alloc (num_clobbers + 1);
3061 vec->elem[0] = PATTERN (insn);
3062 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3063 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3065 if (INSN_CODE (insn) < 0)
3070 new_body = old_body;
3073 new_body = copy_insn (old_body);
3074 if (REG_NOTES (insn))
3075 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3077 PATTERN (insn) = new_body;
3078 old_set = single_set (insn);
3080 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3081 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3084 /* This can't have an effect on elimination offsets, so skip right
3090 /* Determine the effects of this insn on elimination offsets. */
3091 elimination_effects (old_body, 0);
3093 /* Eliminate all eliminable registers occurring in operands that
3094 can be handled by reload. */
3095 extract_insn (insn);
3097 for (i = 0; i < recog_data.n_operands; i++)
3099 orig_operand[i] = recog_data.operand[i];
3100 substed_operand[i] = recog_data.operand[i];
3102 /* For an asm statement, every operand is eliminable. */
3103 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3105 /* Check for setting a register that we know about. */
3106 if (recog_data.operand_type[i] != OP_IN
3107 && GET_CODE (orig_operand[i]) == REG)
3109 /* If we are assigning to a register that can be eliminated, it
3110 must be as part of a PARALLEL, since the code above handles
3111 single SETs. We must indicate that we can no longer
3112 eliminate this reg. */
3113 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3115 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3116 ep->can_eliminate = 0;
3119 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3120 replace ? insn : NULL_RTX);
3121 if (substed_operand[i] != orig_operand[i])
3122 val = any_changes = 1;
3123 /* Terminate the search in check_eliminable_occurrences at
3125 *recog_data.operand_loc[i] = 0;
3127 /* If an output operand changed from a REG to a MEM and INSN is an
3128 insn, write a CLOBBER insn. */
3129 if (recog_data.operand_type[i] != OP_IN
3130 && GET_CODE (orig_operand[i]) == REG
3131 && GET_CODE (substed_operand[i]) == MEM
3133 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3138 for (i = 0; i < recog_data.n_dups; i++)
3139 *recog_data.dup_loc[i]
3140 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3142 /* If any eliminable remain, they aren't eliminable anymore. */
3143 check_eliminable_occurrences (old_body);
3145 /* Substitute the operands; the new values are in the substed_operand
3147 for (i = 0; i < recog_data.n_operands; i++)
3148 *recog_data.operand_loc[i] = substed_operand[i];
3149 for (i = 0; i < recog_data.n_dups; i++)
3150 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3152 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3153 re-recognize the insn. We do this in case we had a simple addition
3154 but now can do this as a load-address. This saves an insn in this
3156 If re-recognition fails, the old insn code number will still be used,
3157 and some register operands may have changed into PLUS expressions.
3158 These will be handled by find_reloads by loading them into a register
3163 /* If we aren't replacing things permanently and we changed something,
3164 make another copy to ensure that all the RTL is new. Otherwise
3165 things can go wrong if find_reload swaps commutative operands
3166 and one is inside RTL that has been copied while the other is not. */
3167 new_body = old_body;
3170 new_body = copy_insn (old_body);
3171 if (REG_NOTES (insn))
3172 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3174 PATTERN (insn) = new_body;
3176 /* If we had a move insn but now we don't, rerecognize it. This will
3177 cause spurious re-recognition if the old move had a PARALLEL since
3178 the new one still will, but we can't call single_set without
3179 having put NEW_BODY into the insn and the re-recognition won't
3180 hurt in this rare case. */
3181 /* ??? Why this huge if statement - why don't we just rerecognize the
3185 && ((GET_CODE (SET_SRC (old_set)) == REG
3186 && (GET_CODE (new_body) != SET
3187 || GET_CODE (SET_SRC (new_body)) != REG))
3188 /* If this was a load from or store to memory, compare
3189 the MEM in recog_data.operand to the one in the insn.
3190 If they are not equal, then rerecognize the insn. */
3192 && ((GET_CODE (SET_SRC (old_set)) == MEM
3193 && SET_SRC (old_set) != recog_data.operand[1])
3194 || (GET_CODE (SET_DEST (old_set)) == MEM
3195 && SET_DEST (old_set) != recog_data.operand[0])))
3196 /* If this was an add insn before, rerecognize. */
3197 || GET_CODE (SET_SRC (old_set)) == PLUS))
3199 int new_icode = recog (PATTERN (insn), insn, 0);
3201 INSN_CODE (insn) = icode;
3205 /* Restore the old body. If there were any changes to it, we made a copy
3206 of it while the changes were still in place, so we'll correctly return
3207 a modified insn below. */
3210 /* Restore the old body. */
3211 for (i = 0; i < recog_data.n_operands; i++)
3212 *recog_data.operand_loc[i] = orig_operand[i];
3213 for (i = 0; i < recog_data.n_dups; i++)
3214 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3217 /* Update all elimination pairs to reflect the status after the current
3218 insn. The changes we make were determined by the earlier call to
3219 elimination_effects.
3221 We also detect a cases where register elimination cannot be done,
3222 namely, if a register would be both changed and referenced outside a MEM
3223 in the resulting insn since such an insn is often undefined and, even if
3224 not, we cannot know what meaning will be given to it. Note that it is
3225 valid to have a register used in an address in an insn that changes it
3226 (presumably with a pre- or post-increment or decrement).
3228 If anything changes, return nonzero. */
3230 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3232 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3233 ep->can_eliminate = 0;
3235 ep->ref_outside_mem = 0;
3237 if (ep->previous_offset != ep->offset)
3242 /* If we changed something, perform elimination in REG_NOTES. This is
3243 needed even when REPLACE is zero because a REG_DEAD note might refer
3244 to a register that we eliminate and could cause a different number
3245 of spill registers to be needed in the final reload pass than in
3247 if (val && REG_NOTES (insn) != 0)
3248 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3253 /* Loop through all elimination pairs.
3254 Recalculate the number not at initial offset.
3256 Compute the maximum offset (minimum offset if the stack does not
3257 grow downward) for each elimination pair. */
3260 update_eliminable_offsets ()
3262 struct elim_table *ep;
3264 num_not_at_initial_offset = 0;
3265 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3267 ep->previous_offset = ep->offset;
3268 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3269 num_not_at_initial_offset++;
3273 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3274 replacement we currently believe is valid, mark it as not eliminable if X
3275 modifies DEST in any way other than by adding a constant integer to it.
3277 If DEST is the frame pointer, we do nothing because we assume that
3278 all assignments to the hard frame pointer are nonlocal gotos and are being
3279 done at a time when they are valid and do not disturb anything else.
3280 Some machines want to eliminate a fake argument pointer with either the
3281 frame or stack pointer. Assignments to the hard frame pointer must not
3282 prevent this elimination.
3284 Called via note_stores from reload before starting its passes to scan
3285 the insns of the function. */
3288 mark_not_eliminable (dest, x, data)
3291 void *data ATTRIBUTE_UNUSED;
3295 /* A SUBREG of a hard register here is just changing its mode. We should
3296 not see a SUBREG of an eliminable hard register, but check just in
3298 if (GET_CODE (dest) == SUBREG)
3299 dest = SUBREG_REG (dest);
3301 if (dest == hard_frame_pointer_rtx)
3304 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3305 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3306 && (GET_CODE (x) != SET
3307 || GET_CODE (SET_SRC (x)) != PLUS
3308 || XEXP (SET_SRC (x), 0) != dest
3309 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3311 reg_eliminate[i].can_eliminate_previous
3312 = reg_eliminate[i].can_eliminate = 0;
3317 /* Verify that the initial elimination offsets did not change since the
3318 last call to set_initial_elim_offsets. This is used to catch cases
3319 where something illegal happened during reload_as_needed that could
3320 cause incorrect code to be generated if we did not check for it. */
3323 verify_initial_elim_offsets ()
3327 #ifdef ELIMINABLE_REGS
3328 struct elim_table *ep;
3330 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3332 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3333 if (t != ep->initial_offset)
3337 INITIAL_FRAME_POINTER_OFFSET (t);
3338 if (t != reg_eliminate[0].initial_offset)
3343 /* Reset all offsets on eliminable registers to their initial values. */
3346 set_initial_elim_offsets ()
3348 struct elim_table *ep = reg_eliminate;
3350 #ifdef ELIMINABLE_REGS
3351 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3353 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3354 ep->previous_offset = ep->offset = ep->initial_offset;
3357 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3358 ep->previous_offset = ep->offset = ep->initial_offset;
3361 num_not_at_initial_offset = 0;
3364 /* Initialize the known label offsets.
3365 Set a known offset for each forced label to be at the initial offset
3366 of each elimination. We do this because we assume that all
3367 computed jumps occur from a location where each elimination is
3368 at its initial offset.
3369 For all other labels, show that we don't know the offsets. */
3372 set_initial_label_offsets ()
3375 memset ((char *) &offsets_known_at[get_first_label_num ()], 0, num_labels);
3377 for (x = forced_labels; x; x = XEXP (x, 1))
3379 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3382 /* Set all elimination offsets to the known values for the code label given
3386 set_offsets_for_label (insn)
3390 int label_nr = CODE_LABEL_NUMBER (insn);
3391 struct elim_table *ep;
3393 num_not_at_initial_offset = 0;
3394 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3396 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3397 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3398 num_not_at_initial_offset++;
3402 /* See if anything that happened changes which eliminations are valid.
3403 For example, on the Sparc, whether or not the frame pointer can
3404 be eliminated can depend on what registers have been used. We need
3405 not check some conditions again (such as flag_omit_frame_pointer)
3406 since they can't have changed. */
3409 update_eliminables (pset)
3412 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3413 int previous_frame_pointer_needed = frame_pointer_needed;
3415 struct elim_table *ep;
3417 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3418 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3419 #ifdef ELIMINABLE_REGS
3420 || ! CAN_ELIMINATE (ep->from, ep->to)
3423 ep->can_eliminate = 0;
3425 /* Look for the case where we have discovered that we can't replace
3426 register A with register B and that means that we will now be
3427 trying to replace register A with register C. This means we can
3428 no longer replace register C with register B and we need to disable
3429 such an elimination, if it exists. This occurs often with A == ap,
3430 B == sp, and C == fp. */
3432 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3434 struct elim_table *op;
3437 if (! ep->can_eliminate && ep->can_eliminate_previous)
3439 /* Find the current elimination for ep->from, if there is a
3441 for (op = reg_eliminate;
3442 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3443 if (op->from == ep->from && op->can_eliminate)
3449 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3451 for (op = reg_eliminate;
3452 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3453 if (op->from == new_to && op->to == ep->to)
3454 op->can_eliminate = 0;
3458 /* See if any registers that we thought we could eliminate the previous
3459 time are no longer eliminable. If so, something has changed and we
3460 must spill the register. Also, recompute the number of eliminable
3461 registers and see if the frame pointer is needed; it is if there is
3462 no elimination of the frame pointer that we can perform. */
3464 frame_pointer_needed = 1;
3465 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3467 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3468 && ep->to != HARD_FRAME_POINTER_REGNUM)
3469 frame_pointer_needed = 0;
3471 if (! ep->can_eliminate && ep->can_eliminate_previous)
3473 ep->can_eliminate_previous = 0;
3474 SET_HARD_REG_BIT (*pset, ep->from);
3479 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3480 /* If we didn't need a frame pointer last time, but we do now, spill
3481 the hard frame pointer. */
3482 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3483 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3487 /* Initialize the table of registers to eliminate. */
3492 struct elim_table *ep;
3493 #ifdef ELIMINABLE_REGS
3494 const struct elim_table_1 *ep1;
3498 reg_eliminate = (struct elim_table *)
3499 xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3501 /* Does this function require a frame pointer? */
3503 frame_pointer_needed = (! flag_omit_frame_pointer
3504 #ifdef EXIT_IGNORE_STACK
3505 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3506 and restore sp for alloca. So we can't eliminate
3507 the frame pointer in that case. At some point,
3508 we should improve this by emitting the
3509 sp-adjusting insns for this case. */
3510 || (current_function_calls_alloca
3511 && EXIT_IGNORE_STACK)
3513 || FRAME_POINTER_REQUIRED);
3517 #ifdef ELIMINABLE_REGS
3518 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3519 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3521 ep->from = ep1->from;
3523 ep->can_eliminate = ep->can_eliminate_previous
3524 = (CAN_ELIMINATE (ep->from, ep->to)
3525 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3528 reg_eliminate[0].from = reg_eliminate_1[0].from;
3529 reg_eliminate[0].to = reg_eliminate_1[0].to;
3530 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3531 = ! frame_pointer_needed;
3534 /* Count the number of eliminable registers and build the FROM and TO
3535 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3536 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3537 We depend on this. */
3538 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3540 num_eliminable += ep->can_eliminate;
3541 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3542 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3546 /* Kick all pseudos out of hard register REGNO.
3548 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3549 because we found we can't eliminate some register. In the case, no pseudos
3550 are allowed to be in the register, even if they are only in a block that
3551 doesn't require spill registers, unlike the case when we are spilling this
3552 hard reg to produce another spill register.
3554 Return nonzero if any pseudos needed to be kicked out. */
3557 spill_hard_reg (regno, cant_eliminate)
3565 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3566 regs_ever_live[regno] = 1;
3569 /* Spill every pseudo reg that was allocated to this reg
3570 or to something that overlaps this reg. */
3572 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3573 if (reg_renumber[i] >= 0
3574 && (unsigned int) reg_renumber[i] <= regno
3575 && ((unsigned int) reg_renumber[i]
3576 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3577 PSEUDO_REGNO_MODE (i))
3579 SET_REGNO_REG_SET (&spilled_pseudos, i);
3582 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3583 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3586 ior_hard_reg_set (set1, set2)
3587 HARD_REG_SET *set1, *set2;
3589 IOR_HARD_REG_SET (*set1, *set2);
3592 /* After find_reload_regs has been run for all insn that need reloads,
3593 and/or spill_hard_regs was called, this function is used to actually
3594 spill pseudo registers and try to reallocate them. It also sets up the
3595 spill_regs array for use by choose_reload_regs. */
3598 finish_spills (global)
3601 struct insn_chain *chain;
3602 int something_changed = 0;
3605 /* Build the spill_regs array for the function. */
3606 /* If there are some registers still to eliminate and one of the spill regs
3607 wasn't ever used before, additional stack space may have to be
3608 allocated to store this register. Thus, we may have changed the offset
3609 between the stack and frame pointers, so mark that something has changed.
3611 One might think that we need only set VAL to 1 if this is a call-used
3612 register. However, the set of registers that must be saved by the
3613 prologue is not identical to the call-used set. For example, the
3614 register used by the call insn for the return PC is a call-used register,
3615 but must be saved by the prologue. */
3618 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3619 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3621 spill_reg_order[i] = n_spills;
3622 spill_regs[n_spills++] = i;
3623 if (num_eliminable && ! regs_ever_live[i])
3624 something_changed = 1;
3625 regs_ever_live[i] = 1;
3628 spill_reg_order[i] = -1;
3630 EXECUTE_IF_SET_IN_REG_SET
3631 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3633 /* Record the current hard register the pseudo is allocated to in
3634 pseudo_previous_regs so we avoid reallocating it to the same
3635 hard reg in a later pass. */
3636 if (reg_renumber[i] < 0)
3639 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3640 /* Mark it as no longer having a hard register home. */
3641 reg_renumber[i] = -1;
3642 /* We will need to scan everything again. */
3643 something_changed = 1;
3646 /* Retry global register allocation if possible. */
3649 memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3650 /* For every insn that needs reloads, set the registers used as spill
3651 regs in pseudo_forbidden_regs for every pseudo live across the
3653 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3655 EXECUTE_IF_SET_IN_REG_SET
3656 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3658 ior_hard_reg_set (pseudo_forbidden_regs + i,
3659 &chain->used_spill_regs);
3661 EXECUTE_IF_SET_IN_REG_SET
3662 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3664 ior_hard_reg_set (pseudo_forbidden_regs + i,
3665 &chain->used_spill_regs);
3669 /* Retry allocating the spilled pseudos. For each reg, merge the
3670 various reg sets that indicate which hard regs can't be used,
3671 and call retry_global_alloc.
3672 We change spill_pseudos here to only contain pseudos that did not
3673 get a new hard register. */
3674 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3675 if (reg_old_renumber[i] != reg_renumber[i])
3677 HARD_REG_SET forbidden;
3678 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3679 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3680 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3681 retry_global_alloc (i, forbidden);
3682 if (reg_renumber[i] >= 0)
3683 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3687 /* Fix up the register information in the insn chain.
3688 This involves deleting those of the spilled pseudos which did not get
3689 a new hard register home from the live_{before,after} sets. */
3690 for (chain = reload_insn_chain; chain; chain = chain->next)
3692 HARD_REG_SET used_by_pseudos;
3693 HARD_REG_SET used_by_pseudos2;
3695 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3696 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3698 /* Mark any unallocated hard regs as available for spills. That
3699 makes inheritance work somewhat better. */
3700 if (chain->need_reload)
3702 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3703 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3704 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3706 /* Save the old value for the sanity test below. */
3707 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3709 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3710 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3711 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3712 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3714 /* Make sure we only enlarge the set. */
3715 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3721 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3722 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3724 int regno = reg_renumber[i];
3725 if (reg_old_renumber[i] == regno)
3728 alter_reg (i, reg_old_renumber[i]);
3729 reg_old_renumber[i] = regno;
3733 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3735 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3736 i, reg_renumber[i]);
3740 return something_changed;
3743 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3744 Also mark any hard registers used to store user variables as
3745 forbidden from being used for spill registers. */
3748 scan_paradoxical_subregs (x)
3753 enum rtx_code code = GET_CODE (x);
3759 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3760 && REG_USERVAR_P (x))
3761 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3770 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3778 if (GET_CODE (SUBREG_REG (x)) == REG
3779 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3780 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3781 = GET_MODE_SIZE (GET_MODE (x));
3788 fmt = GET_RTX_FORMAT (code);
3789 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3792 scan_paradoxical_subregs (XEXP (x, i));
3793 else if (fmt[i] == 'E')
3796 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3797 scan_paradoxical_subregs (XVECEXP (x, i, j));
3802 /* Reload pseudo-registers into hard regs around each insn as needed.
3803 Additional register load insns are output before the insn that needs it
3804 and perhaps store insns after insns that modify the reloaded pseudo reg.
3806 reg_last_reload_reg and reg_reloaded_contents keep track of
3807 which registers are already available in reload registers.
3808 We update these for the reloads that we perform,
3809 as the insns are scanned. */
3812 reload_as_needed (live_known)
3815 struct insn_chain *chain;
3816 #if defined (AUTO_INC_DEC)
3821 memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx);
3822 memset ((char *) spill_reg_store, 0, sizeof spill_reg_store);
3823 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3824 reg_has_output_reload = (char *) xmalloc (max_regno);
3825 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3827 set_initial_elim_offsets ();
3829 for (chain = reload_insn_chain; chain; chain = chain->next)
3832 rtx insn = chain->insn;
3833 rtx old_next = NEXT_INSN (insn);
3835 /* If we pass a label, copy the offsets from the label information
3836 into the current offsets of each elimination. */
3837 if (GET_CODE (insn) == CODE_LABEL)
3838 set_offsets_for_label (insn);
3840 else if (INSN_P (insn))
3842 rtx oldpat = copy_rtx (PATTERN (insn));
3844 /* If this is a USE and CLOBBER of a MEM, ensure that any
3845 references to eliminable registers have been removed. */
3847 if ((GET_CODE (PATTERN (insn)) == USE
3848 || GET_CODE (PATTERN (insn)) == CLOBBER)
3849 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3850 XEXP (XEXP (PATTERN (insn), 0), 0)
3851 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3852 GET_MODE (XEXP (PATTERN (insn), 0)),
3855 /* If we need to do register elimination processing, do so.
3856 This might delete the insn, in which case we are done. */
3857 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3859 eliminate_regs_in_insn (insn, 1);
3860 if (GET_CODE (insn) == NOTE)
3862 update_eliminable_offsets ();
3867 /* If need_elim is nonzero but need_reload is zero, one might think
3868 that we could simply set n_reloads to 0. However, find_reloads
3869 could have done some manipulation of the insn (such as swapping
3870 commutative operands), and these manipulations are lost during
3871 the first pass for every insn that needs register elimination.
3872 So the actions of find_reloads must be redone here. */
3874 if (! chain->need_elim && ! chain->need_reload
3875 && ! chain->need_operand_change)
3877 /* First find the pseudo regs that must be reloaded for this insn.
3878 This info is returned in the tables reload_... (see reload.h).
3879 Also modify the body of INSN by substituting RELOAD
3880 rtx's for those pseudo regs. */
3883 memset (reg_has_output_reload, 0, max_regno);
3884 CLEAR_HARD_REG_SET (reg_is_output_reload);
3886 find_reloads (insn, 1, spill_indirect_levels, live_known,
3892 rtx next = NEXT_INSN (insn);
3895 prev = PREV_INSN (insn);
3897 /* Now compute which reload regs to reload them into. Perhaps
3898 reusing reload regs from previous insns, or else output
3899 load insns to reload them. Maybe output store insns too.
3900 Record the choices of reload reg in reload_reg_rtx. */
3901 choose_reload_regs (chain);
3903 /* Merge any reloads that we didn't combine for fear of
3904 increasing the number of spill registers needed but now
3905 discover can be safely merged. */
3906 if (SMALL_REGISTER_CLASSES)
3907 merge_assigned_reloads (insn);
3909 /* Generate the insns to reload operands into or out of
3910 their reload regs. */
3911 emit_reload_insns (chain);
3913 /* Substitute the chosen reload regs from reload_reg_rtx
3914 into the insn's body (or perhaps into the bodies of other
3915 load and store insn that we just made for reloading
3916 and that we moved the structure into). */
3917 subst_reloads (insn);
3919 /* If this was an ASM, make sure that all the reload insns
3920 we have generated are valid. If not, give an error
3923 if (asm_noperands (PATTERN (insn)) >= 0)
3924 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3925 if (p != insn && INSN_P (p)
3926 && (recog_memoized (p) < 0
3927 || (extract_insn (p), ! constrain_operands (1))))
3929 error_for_asm (insn,
3930 "`asm' operand requires impossible reload");
3935 if (num_eliminable && chain->need_elim)
3936 update_eliminable_offsets ();
3938 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3939 is no longer validly lying around to save a future reload.
3940 Note that this does not detect pseudos that were reloaded
3941 for this insn in order to be stored in
3942 (obeying register constraints). That is correct; such reload
3943 registers ARE still valid. */
3944 note_stores (oldpat, forget_old_reloads_1, NULL);
3946 /* There may have been CLOBBER insns placed after INSN. So scan
3947 between INSN and NEXT and use them to forget old reloads. */
3948 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3949 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3950 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3953 /* Likewise for regs altered by auto-increment in this insn.
3954 REG_INC notes have been changed by reloading:
3955 find_reloads_address_1 records substitutions for them,
3956 which have been performed by subst_reloads above. */
3957 for (i = n_reloads - 1; i >= 0; i--)
3959 rtx in_reg = rld[i].in_reg;
3962 enum rtx_code code = GET_CODE (in_reg);
3963 /* PRE_INC / PRE_DEC will have the reload register ending up
3964 with the same value as the stack slot, but that doesn't
3965 hold true for POST_INC / POST_DEC. Either we have to
3966 convert the memory access to a true POST_INC / POST_DEC,
3967 or we can't use the reload register for inheritance. */
3968 if ((code == POST_INC || code == POST_DEC)
3969 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3970 REGNO (rld[i].reg_rtx))
3971 /* Make sure it is the inc/dec pseudo, and not
3972 some other (e.g. output operand) pseudo. */
3973 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3974 == REGNO (XEXP (in_reg, 0))))
3977 rtx reload_reg = rld[i].reg_rtx;
3978 enum machine_mode mode = GET_MODE (reload_reg);
3982 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3984 /* We really want to ignore REG_INC notes here, so
3985 use PATTERN (p) as argument to reg_set_p . */
3986 if (reg_set_p (reload_reg, PATTERN (p)))
3988 n = count_occurrences (PATTERN (p), reload_reg, 0);
3993 n = validate_replace_rtx (reload_reg,
3994 gen_rtx (code, mode,
3998 /* We must also verify that the constraints
3999 are met after the replacement. */
4002 n = constrain_operands (1);
4006 /* If the constraints were not met, then
4007 undo the replacement. */
4010 validate_replace_rtx (gen_rtx (code, mode,
4022 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4024 /* Mark this as having an output reload so that the
4025 REG_INC processing code below won't invalidate
4026 the reload for inheritance. */
4027 SET_HARD_REG_BIT (reg_is_output_reload,
4028 REGNO (reload_reg));
4029 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4032 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4035 else if ((code == PRE_INC || code == PRE_DEC)
4036 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4037 REGNO (rld[i].reg_rtx))
4038 /* Make sure it is the inc/dec pseudo, and not
4039 some other (e.g. output operand) pseudo. */
4040 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4041 == REGNO (XEXP (in_reg, 0))))
4043 SET_HARD_REG_BIT (reg_is_output_reload,
4044 REGNO (rld[i].reg_rtx));
4045 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4049 /* If a pseudo that got a hard register is auto-incremented,
4050 we must purge records of copying it into pseudos without
4052 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4053 if (REG_NOTE_KIND (x) == REG_INC)
4055 /* See if this pseudo reg was reloaded in this insn.
4056 If so, its last-reload info is still valid
4057 because it is based on this insn's reload. */
4058 for (i = 0; i < n_reloads; i++)
4059 if (rld[i].out == XEXP (x, 0))
4063 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4067 /* A reload reg's contents are unknown after a label. */
4068 if (GET_CODE (insn) == CODE_LABEL)
4069 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4071 /* Don't assume a reload reg is still good after a call insn
4072 if it is a call-used reg. */
4073 else if (GET_CODE (insn) == CALL_INSN)
4074 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4078 free (reg_last_reload_reg);
4079 free (reg_has_output_reload);
4082 /* Discard all record of any value reloaded from X,
4083 or reloaded in X from someplace else;
4084 unless X is an output reload reg of the current insn.
4086 X may be a hard reg (the reload reg)
4087 or it may be a pseudo reg that was reloaded from. */
4090 forget_old_reloads_1 (x, ignored, data)
4092 rtx ignored ATTRIBUTE_UNUSED;
4093 void *data ATTRIBUTE_UNUSED;
4098 /* note_stores does give us subregs of hard regs,
4099 subreg_regno_offset will abort if it is not a hard reg. */
4100 while (GET_CODE (x) == SUBREG)
4102 /* We ignore the subreg offset when calculating the regno,
4103 because we are using the entire underlying hard register
4108 if (GET_CODE (x) != REG)
4113 if (regno >= FIRST_PSEUDO_REGISTER)
4119 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4120 /* Storing into a spilled-reg invalidates its contents.
4121 This can happen if a block-local pseudo is allocated to that reg
4122 and it wasn't spilled because this block's total need is 0.
4123 Then some insn might have an optional reload and use this reg. */
4124 for (i = 0; i < nr; i++)
4125 /* But don't do this if the reg actually serves as an output
4126 reload reg in the current instruction. */
4128 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4130 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4131 spill_reg_store[regno + i] = 0;
4135 /* Since value of X has changed,
4136 forget any value previously copied from it. */
4139 /* But don't forget a copy if this is the output reload
4140 that establishes the copy's validity. */
4141 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4142 reg_last_reload_reg[regno + nr] = 0;
4145 /* The following HARD_REG_SETs indicate when each hard register is
4146 used for a reload of various parts of the current insn. */
4148 /* If reg is unavailable for all reloads. */
4149 static HARD_REG_SET reload_reg_unavailable;
4150 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4151 static HARD_REG_SET reload_reg_used;
4152 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4153 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4154 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4155 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4156 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4157 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4158 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4159 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4160 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4161 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4162 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4163 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4164 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4165 static HARD_REG_SET reload_reg_used_in_op_addr;
4166 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4167 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4168 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4169 static HARD_REG_SET reload_reg_used_in_insn;
4170 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4171 static HARD_REG_SET reload_reg_used_in_other_addr;
4173 /* If reg is in use as a reload reg for any sort of reload. */
4174 static HARD_REG_SET reload_reg_used_at_all;
4176 /* If reg is use as an inherited reload. We just mark the first register
4178 static HARD_REG_SET reload_reg_used_for_inherit;
4180 /* Records which hard regs are used in any way, either as explicit use or
4181 by being allocated to a pseudo during any point of the current insn. */
4182 static HARD_REG_SET reg_used_in_insn;
4184 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4185 TYPE. MODE is used to indicate how many consecutive regs are
4189 mark_reload_reg_in_use (regno, opnum, type, mode)
4192 enum reload_type type;
4193 enum machine_mode mode;
4195 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4198 for (i = regno; i < nregs + regno; i++)
4203 SET_HARD_REG_BIT (reload_reg_used, i);
4206 case RELOAD_FOR_INPUT_ADDRESS:
4207 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4210 case RELOAD_FOR_INPADDR_ADDRESS:
4211 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4214 case RELOAD_FOR_OUTPUT_ADDRESS:
4215 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4218 case RELOAD_FOR_OUTADDR_ADDRESS:
4219 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4222 case RELOAD_FOR_OPERAND_ADDRESS:
4223 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4226 case RELOAD_FOR_OPADDR_ADDR:
4227 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4230 case RELOAD_FOR_OTHER_ADDRESS:
4231 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4234 case RELOAD_FOR_INPUT:
4235 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4238 case RELOAD_FOR_OUTPUT:
4239 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4242 case RELOAD_FOR_INSN:
4243 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4247 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4251 /* Similarly, but show REGNO is no longer in use for a reload. */
4254 clear_reload_reg_in_use (regno, opnum, type, mode)
4257 enum reload_type type;
4258 enum machine_mode mode;
4260 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4261 unsigned int start_regno, end_regno, r;
4263 /* A complication is that for some reload types, inheritance might
4264 allow multiple reloads of the same types to share a reload register.
4265 We set check_opnum if we have to check only reloads with the same
4266 operand number, and check_any if we have to check all reloads. */
4267 int check_opnum = 0;
4269 HARD_REG_SET *used_in_set;
4274 used_in_set = &reload_reg_used;
4277 case RELOAD_FOR_INPUT_ADDRESS:
4278 used_in_set = &reload_reg_used_in_input_addr[opnum];
4281 case RELOAD_FOR_INPADDR_ADDRESS:
4283 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4286 case RELOAD_FOR_OUTPUT_ADDRESS:
4287 used_in_set = &reload_reg_used_in_output_addr[opnum];
4290 case RELOAD_FOR_OUTADDR_ADDRESS:
4292 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4295 case RELOAD_FOR_OPERAND_ADDRESS:
4296 used_in_set = &reload_reg_used_in_op_addr;
4299 case RELOAD_FOR_OPADDR_ADDR:
4301 used_in_set = &reload_reg_used_in_op_addr_reload;
4304 case RELOAD_FOR_OTHER_ADDRESS:
4305 used_in_set = &reload_reg_used_in_other_addr;
4309 case RELOAD_FOR_INPUT:
4310 used_in_set = &reload_reg_used_in_input[opnum];
4313 case RELOAD_FOR_OUTPUT:
4314 used_in_set = &reload_reg_used_in_output[opnum];
4317 case RELOAD_FOR_INSN:
4318 used_in_set = &reload_reg_used_in_insn;
4323 /* We resolve conflicts with remaining reloads of the same type by
4324 excluding the intervals of reload registers by them from the
4325 interval of freed reload registers. Since we only keep track of
4326 one set of interval bounds, we might have to exclude somewhat
4327 more than what would be necessary if we used a HARD_REG_SET here.
4328 But this should only happen very infrequently, so there should
4329 be no reason to worry about it. */
4331 start_regno = regno;
4332 end_regno = regno + nregs;
4333 if (check_opnum || check_any)
4335 for (i = n_reloads - 1; i >= 0; i--)
4337 if (rld[i].when_needed == type
4338 && (check_any || rld[i].opnum == opnum)
4341 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4342 unsigned int conflict_end
4344 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4346 /* If there is an overlap with the first to-be-freed register,
4347 adjust the interval start. */
4348 if (conflict_start <= start_regno && conflict_end > start_regno)
4349 start_regno = conflict_end;
4350 /* Otherwise, if there is a conflict with one of the other
4351 to-be-freed registers, adjust the interval end. */
4352 if (conflict_start > start_regno && conflict_start < end_regno)
4353 end_regno = conflict_start;
4358 for (r = start_regno; r < end_regno; r++)
4359 CLEAR_HARD_REG_BIT (*used_in_set, r);
4362 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4363 specified by OPNUM and TYPE. */
4366 reload_reg_free_p (regno, opnum, type)
4369 enum reload_type type;
4373 /* In use for a RELOAD_OTHER means it's not available for anything. */
4374 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4375 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4381 /* In use for anything means we can't use it for RELOAD_OTHER. */
4382 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4383 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4384 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4387 for (i = 0; i < reload_n_operands; i++)
4388 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4389 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4390 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4391 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4392 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4393 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4398 case RELOAD_FOR_INPUT:
4399 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4400 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4403 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4406 /* If it is used for some other input, can't use it. */
4407 for (i = 0; i < reload_n_operands; i++)
4408 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4411 /* If it is used in a later operand's address, can't use it. */
4412 for (i = opnum + 1; i < reload_n_operands; i++)
4413 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4414 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4419 case RELOAD_FOR_INPUT_ADDRESS:
4420 /* Can't use a register if it is used for an input address for this
4421 operand or used as an input in an earlier one. */
4422 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4423 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4426 for (i = 0; i < opnum; i++)
4427 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4432 case RELOAD_FOR_INPADDR_ADDRESS:
4433 /* Can't use a register if it is used for an input address
4434 for this operand or used as an input in an earlier
4436 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4439 for (i = 0; i < opnum; i++)
4440 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4445 case RELOAD_FOR_OUTPUT_ADDRESS:
4446 /* Can't use a register if it is used for an output address for this
4447 operand or used as an output in this or a later operand. Note
4448 that multiple output operands are emitted in reverse order, so
4449 the conflicting ones are those with lower indices. */
4450 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4453 for (i = 0; i <= opnum; i++)
4454 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4459 case RELOAD_FOR_OUTADDR_ADDRESS:
4460 /* Can't use a register if it is used for an output address
4461 for this operand or used as an output in this or a
4462 later operand. Note that multiple output operands are
4463 emitted in reverse order, so the conflicting ones are
4464 those with lower indices. */
4465 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4468 for (i = 0; i <= opnum; i++)
4469 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4474 case RELOAD_FOR_OPERAND_ADDRESS:
4475 for (i = 0; i < reload_n_operands; i++)
4476 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4479 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4480 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4482 case RELOAD_FOR_OPADDR_ADDR:
4483 for (i = 0; i < reload_n_operands; i++)
4484 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4487 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4489 case RELOAD_FOR_OUTPUT:
4490 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4491 outputs, or an operand address for this or an earlier output.
4492 Note that multiple output operands are emitted in reverse order,
4493 so the conflicting ones are those with higher indices. */
4494 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4497 for (i = 0; i < reload_n_operands; i++)
4498 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4501 for (i = opnum; i < reload_n_operands; i++)
4502 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4503 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4508 case RELOAD_FOR_INSN:
4509 for (i = 0; i < reload_n_operands; i++)
4510 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4511 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4514 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4515 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4517 case RELOAD_FOR_OTHER_ADDRESS:
4518 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4523 /* Return 1 if the value in reload reg REGNO, as used by a reload
4524 needed for the part of the insn specified by OPNUM and TYPE,
4525 is still available in REGNO at the end of the insn.
4527 We can assume that the reload reg was already tested for availability
4528 at the time it is needed, and we should not check this again,
4529 in case the reg has already been marked in use. */
4532 reload_reg_reaches_end_p (regno, opnum, type)
4535 enum reload_type type;
4542 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4543 its value must reach the end. */
4546 /* If this use is for part of the insn,
4547 its value reaches if no subsequent part uses the same register.
4548 Just like the above function, don't try to do this with lots
4551 case RELOAD_FOR_OTHER_ADDRESS:
4552 /* Here we check for everything else, since these don't conflict
4553 with anything else and everything comes later. */
4555 for (i = 0; i < reload_n_operands; i++)
4556 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4557 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4558 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4559 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4560 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4561 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4564 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4565 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4566 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4568 case RELOAD_FOR_INPUT_ADDRESS:
4569 case RELOAD_FOR_INPADDR_ADDRESS:
4570 /* Similar, except that we check only for this and subsequent inputs
4571 and the address of only subsequent inputs and we do not need
4572 to check for RELOAD_OTHER objects since they are known not to
4575 for (i = opnum; i < reload_n_operands; i++)
4576 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4579 for (i = opnum + 1; i < reload_n_operands; i++)
4580 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4581 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4584 for (i = 0; i < reload_n_operands; i++)
4585 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4586 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4587 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4590 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4593 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4594 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4595 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4597 case RELOAD_FOR_INPUT:
4598 /* Similar to input address, except we start at the next operand for
4599 both input and input address and we do not check for
4600 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4603 for (i = opnum + 1; i < reload_n_operands; i++)
4604 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4605 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4606 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4609 /* ... fall through ... */
4611 case RELOAD_FOR_OPERAND_ADDRESS:
4612 /* Check outputs and their addresses. */
4614 for (i = 0; i < reload_n_operands; i++)
4615 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4616 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4617 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4620 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4622 case RELOAD_FOR_OPADDR_ADDR:
4623 for (i = 0; i < reload_n_operands; i++)
4624 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4625 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4626 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4629 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4630 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4631 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4633 case RELOAD_FOR_INSN:
4634 /* These conflict with other outputs with RELOAD_OTHER. So
4635 we need only check for output addresses. */
4637 opnum = reload_n_operands;
4639 /* ... fall through ... */
4641 case RELOAD_FOR_OUTPUT:
4642 case RELOAD_FOR_OUTPUT_ADDRESS:
4643 case RELOAD_FOR_OUTADDR_ADDRESS:
4644 /* We already know these can't conflict with a later output. So the
4645 only thing to check are later output addresses.
4646 Note that multiple output operands are emitted in reverse order,
4647 so the conflicting ones are those with lower indices. */
4648 for (i = 0; i < opnum; i++)
4649 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4650 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4659 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4662 This function uses the same algorithm as reload_reg_free_p above. */
4665 reloads_conflict (r1, r2)
4668 enum reload_type r1_type = rld[r1].when_needed;
4669 enum reload_type r2_type = rld[r2].when_needed;
4670 int r1_opnum = rld[r1].opnum;
4671 int r2_opnum = rld[r2].opnum;
4673 /* RELOAD_OTHER conflicts with everything. */
4674 if (r2_type == RELOAD_OTHER)
4677 /* Otherwise, check conflicts differently for each type. */
4681 case RELOAD_FOR_INPUT:
4682 return (r2_type == RELOAD_FOR_INSN
4683 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4684 || r2_type == RELOAD_FOR_OPADDR_ADDR
4685 || r2_type == RELOAD_FOR_INPUT
4686 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4687 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4688 && r2_opnum > r1_opnum));
4690 case RELOAD_FOR_INPUT_ADDRESS:
4691 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4692 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4694 case RELOAD_FOR_INPADDR_ADDRESS:
4695 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4696 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4698 case RELOAD_FOR_OUTPUT_ADDRESS:
4699 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4700 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4702 case RELOAD_FOR_OUTADDR_ADDRESS:
4703 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4704 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4706 case RELOAD_FOR_OPERAND_ADDRESS:
4707 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4708 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4710 case RELOAD_FOR_OPADDR_ADDR:
4711 return (r2_type == RELOAD_FOR_INPUT
4712 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4714 case RELOAD_FOR_OUTPUT:
4715 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4716 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4717 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4718 && r2_opnum >= r1_opnum));
4720 case RELOAD_FOR_INSN:
4721 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4722 || r2_type == RELOAD_FOR_INSN
4723 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4725 case RELOAD_FOR_OTHER_ADDRESS:
4726 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4736 /* Indexed by reload number, 1 if incoming value
4737 inherited from previous insns. */
4738 char reload_inherited[MAX_RELOADS];
4740 /* For an inherited reload, this is the insn the reload was inherited from,
4741 if we know it. Otherwise, this is 0. */
4742 rtx reload_inheritance_insn[MAX_RELOADS];
4744 /* If non-zero, this is a place to get the value of the reload,
4745 rather than using reload_in. */
4746 rtx reload_override_in[MAX_RELOADS];
4748 /* For each reload, the hard register number of the register used,
4749 or -1 if we did not need a register for this reload. */
4750 int reload_spill_index[MAX_RELOADS];
4752 /* Subroutine of free_for_value_p, used to check a single register.
4753 START_REGNO is the starting regno of the full reload register
4754 (possibly comprising multiple hard registers) that we are considering. */
4757 reload_reg_free_for_value_p (start_regno, regno, opnum, type, value, out,
4758 reloadnum, ignore_address_reloads)
4759 int start_regno, regno;
4761 enum reload_type type;
4764 int ignore_address_reloads;
4767 /* Set if we see an input reload that must not share its reload register
4768 with any new earlyclobber, but might otherwise share the reload
4769 register with an output or input-output reload. */
4770 int check_earlyclobber = 0;
4774 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4777 if (out == const0_rtx)
4783 /* We use some pseudo 'time' value to check if the lifetimes of the
4784 new register use would overlap with the one of a previous reload
4785 that is not read-only or uses a different value.
4786 The 'time' used doesn't have to be linear in any shape or form, just
4788 Some reload types use different 'buckets' for each operand.
4789 So there are MAX_RECOG_OPERANDS different time values for each
4791 We compute TIME1 as the time when the register for the prospective
4792 new reload ceases to be live, and TIME2 for each existing
4793 reload as the time when that the reload register of that reload
4795 Where there is little to be gained by exact lifetime calculations,
4796 we just make conservative assumptions, i.e. a longer lifetime;
4797 this is done in the 'default:' cases. */
4800 case RELOAD_FOR_OTHER_ADDRESS:
4801 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4802 time1 = copy ? 0 : 1;
4805 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4807 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4808 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4809 respectively, to the time values for these, we get distinct time
4810 values. To get distinct time values for each operand, we have to
4811 multiply opnum by at least three. We round that up to four because
4812 multiply by four is often cheaper. */
4813 case RELOAD_FOR_INPADDR_ADDRESS:
4814 time1 = opnum * 4 + 2;
4816 case RELOAD_FOR_INPUT_ADDRESS:
4817 time1 = opnum * 4 + 3;
4819 case RELOAD_FOR_INPUT:
4820 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4821 executes (inclusive). */
4822 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4824 case RELOAD_FOR_OPADDR_ADDR:
4826 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4827 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4829 case RELOAD_FOR_OPERAND_ADDRESS:
4830 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4832 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4834 case RELOAD_FOR_OUTADDR_ADDRESS:
4835 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4837 case RELOAD_FOR_OUTPUT_ADDRESS:
4838 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4841 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4844 for (i = 0; i < n_reloads; i++)
4846 rtx reg = rld[i].reg_rtx;
4847 if (reg && GET_CODE (reg) == REG
4848 && ((unsigned) regno - true_regnum (reg)
4849 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned) 1)
4852 rtx other_input = rld[i].in;
4854 /* If the other reload loads the same input value, that
4855 will not cause a conflict only if it's loading it into
4856 the same register. */
4857 if (true_regnum (reg) != start_regno)
4858 other_input = NULL_RTX;
4859 if (! other_input || ! rtx_equal_p (other_input, value)
4860 || rld[i].out || out)
4863 switch (rld[i].when_needed)
4865 case RELOAD_FOR_OTHER_ADDRESS:
4868 case RELOAD_FOR_INPADDR_ADDRESS:
4869 /* find_reloads makes sure that a
4870 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4871 by at most one - the first -
4872 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4873 address reload is inherited, the address address reload
4874 goes away, so we can ignore this conflict. */
4875 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4876 && ignore_address_reloads
4877 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4878 Then the address address is still needed to store
4879 back the new address. */
4880 && ! rld[reloadnum].out)
4882 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4883 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4885 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4886 && ignore_address_reloads
4887 /* Unless we are reloading an auto_inc expression. */
4888 && ! rld[reloadnum].out)
4890 time2 = rld[i].opnum * 4 + 2;
4892 case RELOAD_FOR_INPUT_ADDRESS:
4893 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4894 && ignore_address_reloads
4895 && ! rld[reloadnum].out)
4897 time2 = rld[i].opnum * 4 + 3;
4899 case RELOAD_FOR_INPUT:
4900 time2 = rld[i].opnum * 4 + 4;
4901 check_earlyclobber = 1;
4903 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4904 == MAX_RECOG_OPERAND * 4 */
4905 case RELOAD_FOR_OPADDR_ADDR:
4906 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4907 && ignore_address_reloads
4908 && ! rld[reloadnum].out)
4910 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4912 case RELOAD_FOR_OPERAND_ADDRESS:
4913 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4914 check_earlyclobber = 1;
4916 case RELOAD_FOR_INSN:
4917 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4919 case RELOAD_FOR_OUTPUT:
4920 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4921 instruction is executed. */
4922 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4924 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4925 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4927 case RELOAD_FOR_OUTADDR_ADDRESS:
4928 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4929 && ignore_address_reloads
4930 && ! rld[reloadnum].out)
4932 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4934 case RELOAD_FOR_OUTPUT_ADDRESS:
4935 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4938 /* If there is no conflict in the input part, handle this
4939 like an output reload. */
4940 if (! rld[i].in || rtx_equal_p (other_input, value))
4942 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4943 /* Earlyclobbered outputs must conflict with inputs. */
4944 if (earlyclobber_operand_p (rld[i].out))
4945 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4950 /* RELOAD_OTHER might be live beyond instruction execution,
4951 but this is not obvious when we set time2 = 1. So check
4952 here if there might be a problem with the new reload
4953 clobbering the register used by the RELOAD_OTHER. */
4961 && (! rld[i].in || rld[i].out
4962 || ! rtx_equal_p (other_input, value)))
4963 || (out && rld[reloadnum].out_reg
4964 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4970 /* Earlyclobbered outputs must conflict with inputs. */
4971 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4977 /* Return 1 if the value in reload reg REGNO, as used by a reload
4978 needed for the part of the insn specified by OPNUM and TYPE,
4979 may be used to load VALUE into it.
4981 MODE is the mode in which the register is used, this is needed to
4982 determine how many hard regs to test.
4984 Other read-only reloads with the same value do not conflict
4985 unless OUT is non-zero and these other reloads have to live while
4986 output reloads live.
4987 If OUT is CONST0_RTX, this is a special case: it means that the
4988 test should not be for using register REGNO as reload register, but
4989 for copying from register REGNO into the reload register.
4991 RELOADNUM is the number of the reload we want to load this value for;
4992 a reload does not conflict with itself.
4994 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4995 reloads that load an address for the very reload we are considering.
4997 The caller has to make sure that there is no conflict with the return
5001 free_for_value_p (regno, mode, opnum, type, value, out, reloadnum,
5002 ignore_address_reloads)
5004 enum machine_mode mode;
5006 enum reload_type type;
5009 int ignore_address_reloads;
5011 int nregs = HARD_REGNO_NREGS (regno, mode);
5013 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5014 value, out, reloadnum,
5015 ignore_address_reloads))
5020 /* Determine whether the reload reg X overlaps any rtx'es used for
5021 overriding inheritance. Return nonzero if so. */
5024 conflicts_with_override (x)
5028 for (i = 0; i < n_reloads; i++)
5029 if (reload_override_in[i]
5030 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5035 /* Give an error message saying we failed to find a reload for INSN,
5036 and clear out reload R. */
5038 failed_reload (insn, r)
5042 if (asm_noperands (PATTERN (insn)) < 0)
5043 /* It's the compiler's fault. */
5044 fatal_insn ("could not find a spill register", insn);
5046 /* It's the user's fault; the operand's mode and constraint
5047 don't match. Disable this reload so we don't crash in final. */
5048 error_for_asm (insn,
5049 "`asm' operand constraint incompatible with operand size");
5053 rld[r].optional = 1;
5054 rld[r].secondary_p = 1;
5057 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5058 for reload R. If it's valid, get an rtx for it. Return nonzero if
5061 set_reload_reg (i, r)
5065 rtx reg = spill_reg_rtx[i];
5067 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5068 spill_reg_rtx[i] = reg
5069 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5071 regno = true_regnum (reg);
5073 /* Detect when the reload reg can't hold the reload mode.
5074 This used to be one `if', but Sequent compiler can't handle that. */
5075 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5077 enum machine_mode test_mode = VOIDmode;
5079 test_mode = GET_MODE (rld[r].in);
5080 /* If rld[r].in has VOIDmode, it means we will load it
5081 in whatever mode the reload reg has: to wit, rld[r].mode.
5082 We have already tested that for validity. */
5083 /* Aside from that, we need to test that the expressions
5084 to reload from or into have modes which are valid for this
5085 reload register. Otherwise the reload insns would be invalid. */
5086 if (! (rld[r].in != 0 && test_mode != VOIDmode
5087 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5088 if (! (rld[r].out != 0
5089 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5091 /* The reg is OK. */
5094 /* Mark as in use for this insn the reload regs we use
5096 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5097 rld[r].when_needed, rld[r].mode);
5099 rld[r].reg_rtx = reg;
5100 reload_spill_index[r] = spill_regs[i];
5107 /* Find a spill register to use as a reload register for reload R.
5108 LAST_RELOAD is non-zero if this is the last reload for the insn being
5111 Set rld[R].reg_rtx to the register allocated.
5113 We return 1 if successful, or 0 if we couldn't find a spill reg and
5114 we didn't change anything. */
5117 allocate_reload_reg (chain, r, last_reload)
5118 struct insn_chain *chain ATTRIBUTE_UNUSED;
5124 /* If we put this reload ahead, thinking it is a group,
5125 then insist on finding a group. Otherwise we can grab a
5126 reg that some other reload needs.
5127 (That can happen when we have a 68000 DATA_OR_FP_REG
5128 which is a group of data regs or one fp reg.)
5129 We need not be so restrictive if there are no more reloads
5132 ??? Really it would be nicer to have smarter handling
5133 for that kind of reg class, where a problem like this is normal.
5134 Perhaps those classes should be avoided for reloading
5135 by use of more alternatives. */
5137 int force_group = rld[r].nregs > 1 && ! last_reload;
5139 /* If we want a single register and haven't yet found one,
5140 take any reg in the right class and not in use.
5141 If we want a consecutive group, here is where we look for it.
5143 We use two passes so we can first look for reload regs to
5144 reuse, which are already in use for other reloads in this insn,
5145 and only then use additional registers.
5146 I think that maximizing reuse is needed to make sure we don't
5147 run out of reload regs. Suppose we have three reloads, and
5148 reloads A and B can share regs. These need two regs.
5149 Suppose A and B are given different regs.
5150 That leaves none for C. */
5151 for (pass = 0; pass < 2; pass++)
5153 /* I is the index in spill_regs.
5154 We advance it round-robin between insns to use all spill regs
5155 equally, so that inherited reloads have a chance
5156 of leapfrogging each other. */
5160 for (count = 0; count < n_spills; count++)
5162 int class = (int) rld[r].class;
5168 regnum = spill_regs[i];
5170 if ((reload_reg_free_p (regnum, rld[r].opnum,
5173 /* We check reload_reg_used to make sure we
5174 don't clobber the return register. */
5175 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5176 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5177 rld[r].when_needed, rld[r].in,
5179 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5180 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5181 /* Look first for regs to share, then for unshared. But
5182 don't share regs used for inherited reloads; they are
5183 the ones we want to preserve. */
5185 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5187 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5190 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5191 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5192 (on 68000) got us two FP regs. If NR is 1,
5193 we would reject both of them. */
5196 /* If we need only one reg, we have already won. */
5199 /* But reject a single reg if we demand a group. */
5204 /* Otherwise check that as many consecutive regs as we need
5205 are available here. */
5208 int regno = regnum + nr - 1;
5209 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5210 && spill_reg_order[regno] >= 0
5211 && reload_reg_free_p (regno, rld[r].opnum,
5212 rld[r].when_needed)))
5221 /* If we found something on pass 1, omit pass 2. */
5222 if (count < n_spills)
5226 /* We should have found a spill register by now. */
5227 if (count >= n_spills)
5230 /* I is the index in SPILL_REG_RTX of the reload register we are to
5231 allocate. Get an rtx for it and find its register number. */
5233 return set_reload_reg (i, r);
5236 /* Initialize all the tables needed to allocate reload registers.
5237 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5238 is the array we use to restore the reg_rtx field for every reload. */
5241 choose_reload_regs_init (chain, save_reload_reg_rtx)
5242 struct insn_chain *chain;
5243 rtx *save_reload_reg_rtx;
5247 for (i = 0; i < n_reloads; i++)
5248 rld[i].reg_rtx = save_reload_reg_rtx[i];
5250 memset (reload_inherited, 0, MAX_RELOADS);
5251 memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5252 memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5254 CLEAR_HARD_REG_SET (reload_reg_used);
5255 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5256 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5257 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5258 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5259 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5261 CLEAR_HARD_REG_SET (reg_used_in_insn);
5264 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5265 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5266 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5267 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5268 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5269 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5272 for (i = 0; i < reload_n_operands; i++)
5274 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5275 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5276 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5277 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5278 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5279 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5282 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5284 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5286 for (i = 0; i < n_reloads; i++)
5287 /* If we have already decided to use a certain register,
5288 don't use it in another way. */
5290 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5291 rld[i].when_needed, rld[i].mode);
5294 /* Assign hard reg targets for the pseudo-registers we must reload
5295 into hard regs for this insn.
5296 Also output the instructions to copy them in and out of the hard regs.
5298 For machines with register classes, we are responsible for
5299 finding a reload reg in the proper class. */
5302 choose_reload_regs (chain)
5303 struct insn_chain *chain;
5305 rtx insn = chain->insn;
5307 unsigned int max_group_size = 1;
5308 enum reg_class group_class = NO_REGS;
5309 int pass, win, inheritance;
5311 rtx save_reload_reg_rtx[MAX_RELOADS];
5313 /* In order to be certain of getting the registers we need,
5314 we must sort the reloads into order of increasing register class.
5315 Then our grabbing of reload registers will parallel the process
5316 that provided the reload registers.
5318 Also note whether any of the reloads wants a consecutive group of regs.
5319 If so, record the maximum size of the group desired and what
5320 register class contains all the groups needed by this insn. */
5322 for (j = 0; j < n_reloads; j++)
5324 reload_order[j] = j;
5325 reload_spill_index[j] = -1;
5327 if (rld[j].nregs > 1)
5329 max_group_size = MAX (rld[j].nregs, max_group_size);
5331 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5334 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5338 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5340 /* If -O, try first with inheritance, then turning it off.
5341 If not -O, don't do inheritance.
5342 Using inheritance when not optimizing leads to paradoxes
5343 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5344 because one side of the comparison might be inherited. */
5346 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5348 choose_reload_regs_init (chain, save_reload_reg_rtx);
5350 /* Process the reloads in order of preference just found.
5351 Beyond this point, subregs can be found in reload_reg_rtx.
5353 This used to look for an existing reloaded home for all of the
5354 reloads, and only then perform any new reloads. But that could lose
5355 if the reloads were done out of reg-class order because a later
5356 reload with a looser constraint might have an old home in a register
5357 needed by an earlier reload with a tighter constraint.
5359 To solve this, we make two passes over the reloads, in the order
5360 described above. In the first pass we try to inherit a reload
5361 from a previous insn. If there is a later reload that needs a
5362 class that is a proper subset of the class being processed, we must
5363 also allocate a spill register during the first pass.
5365 Then make a second pass over the reloads to allocate any reloads
5366 that haven't been given registers yet. */
5368 for (j = 0; j < n_reloads; j++)
5370 int r = reload_order[j];
5371 rtx search_equiv = NULL_RTX;
5373 /* Ignore reloads that got marked inoperative. */
5374 if (rld[r].out == 0 && rld[r].in == 0
5375 && ! rld[r].secondary_p)
5378 /* If find_reloads chose to use reload_in or reload_out as a reload
5379 register, we don't need to chose one. Otherwise, try even if it
5380 found one since we might save an insn if we find the value lying
5382 Try also when reload_in is a pseudo without a hard reg. */
5383 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5384 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5385 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5386 && GET_CODE (rld[r].in) != MEM
5387 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5390 #if 0 /* No longer needed for correct operation.
5391 It might give better code, or might not; worth an experiment? */
5392 /* If this is an optional reload, we can't inherit from earlier insns
5393 until we are sure that any non-optional reloads have been allocated.
5394 The following code takes advantage of the fact that optional reloads
5395 are at the end of reload_order. */
5396 if (rld[r].optional != 0)
5397 for (i = 0; i < j; i++)
5398 if ((rld[reload_order[i]].out != 0
5399 || rld[reload_order[i]].in != 0
5400 || rld[reload_order[i]].secondary_p)
5401 && ! rld[reload_order[i]].optional
5402 && rld[reload_order[i]].reg_rtx == 0)
5403 allocate_reload_reg (chain, reload_order[i], 0);
5406 /* First see if this pseudo is already available as reloaded
5407 for a previous insn. We cannot try to inherit for reloads
5408 that are smaller than the maximum number of registers needed
5409 for groups unless the register we would allocate cannot be used
5412 We could check here to see if this is a secondary reload for
5413 an object that is already in a register of the desired class.
5414 This would avoid the need for the secondary reload register.
5415 But this is complex because we can't easily determine what
5416 objects might want to be loaded via this reload. So let a
5417 register be allocated here. In `emit_reload_insns' we suppress
5418 one of the loads in the case described above. */
5424 enum machine_mode mode = VOIDmode;
5428 else if (GET_CODE (rld[r].in) == REG)
5430 regno = REGNO (rld[r].in);
5431 mode = GET_MODE (rld[r].in);
5433 else if (GET_CODE (rld[r].in_reg) == REG)
5435 regno = REGNO (rld[r].in_reg);
5436 mode = GET_MODE (rld[r].in_reg);
5438 else if (GET_CODE (rld[r].in_reg) == SUBREG
5439 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5441 byte = SUBREG_BYTE (rld[r].in_reg);
5442 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5443 if (regno < FIRST_PSEUDO_REGISTER)
5444 regno = subreg_regno (rld[r].in_reg);
5445 mode = GET_MODE (rld[r].in_reg);
5448 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5449 || GET_CODE (rld[r].in_reg) == PRE_DEC
5450 || GET_CODE (rld[r].in_reg) == POST_INC
5451 || GET_CODE (rld[r].in_reg) == POST_DEC)
5452 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5454 regno = REGNO (XEXP (rld[r].in_reg, 0));
5455 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5456 rld[r].out = rld[r].in;
5460 /* This won't work, since REGNO can be a pseudo reg number.
5461 Also, it takes much more hair to keep track of all the things
5462 that can invalidate an inherited reload of part of a pseudoreg. */
5463 else if (GET_CODE (rld[r].in) == SUBREG
5464 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5465 regno = subreg_regno (rld[r].in);
5468 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5470 enum reg_class class = rld[r].class, last_class;
5471 rtx last_reg = reg_last_reload_reg[regno];
5472 enum machine_mode need_mode;
5474 i = REGNO (last_reg);
5475 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5476 last_class = REGNO_REG_CLASS (i);
5482 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5483 GET_MODE_CLASS (mode));
5486 #ifdef CLASS_CANNOT_CHANGE_MODE
5488 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], i)
5489 ? ! CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (last_reg),
5491 : (GET_MODE_SIZE (GET_MODE (last_reg))
5492 >= GET_MODE_SIZE (need_mode)))
5494 (GET_MODE_SIZE (GET_MODE (last_reg))
5495 >= GET_MODE_SIZE (need_mode))
5497 && reg_reloaded_contents[i] == regno
5498 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5499 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5500 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5501 /* Even if we can't use this register as a reload
5502 register, we might use it for reload_override_in,
5503 if copying it to the desired class is cheap
5505 || ((REGISTER_MOVE_COST (mode, last_class, class)
5506 < MEMORY_MOVE_COST (mode, class, 1))
5507 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5508 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5512 #ifdef SECONDARY_MEMORY_NEEDED
5513 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5518 && (rld[r].nregs == max_group_size
5519 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5521 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5522 rld[r].when_needed, rld[r].in,
5525 /* If a group is needed, verify that all the subsequent
5526 registers still have their values intact. */
5527 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5530 for (k = 1; k < nr; k++)
5531 if (reg_reloaded_contents[i + k] != regno
5532 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5540 last_reg = (GET_MODE (last_reg) == mode
5541 ? last_reg : gen_rtx_REG (mode, i));
5544 for (k = 0; k < nr; k++)
5545 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5548 /* We found a register that contains the
5549 value we need. If this register is the
5550 same as an `earlyclobber' operand of the
5551 current insn, just mark it as a place to
5552 reload from since we can't use it as the
5553 reload register itself. */
5555 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5556 if (reg_overlap_mentioned_for_reload_p
5557 (reg_last_reload_reg[regno],
5558 reload_earlyclobbers[i1]))
5561 if (i1 != n_earlyclobbers
5562 || ! (free_for_value_p (i, rld[r].mode,
5564 rld[r].when_needed, rld[r].in,
5566 /* Don't use it if we'd clobber a pseudo reg. */
5567 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5569 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5570 /* Don't clobber the frame pointer. */
5571 || (i == HARD_FRAME_POINTER_REGNUM
5572 && frame_pointer_needed
5574 /* Don't really use the inherited spill reg
5575 if we need it wider than we've got it. */
5576 || (GET_MODE_SIZE (rld[r].mode)
5577 > GET_MODE_SIZE (mode))
5580 /* If find_reloads chose reload_out as reload
5581 register, stay with it - that leaves the
5582 inherited register for subsequent reloads. */
5583 || (rld[r].out && rld[r].reg_rtx
5584 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5586 if (! rld[r].optional)
5588 reload_override_in[r] = last_reg;
5589 reload_inheritance_insn[r]
5590 = reg_reloaded_insn[i];
5596 /* We can use this as a reload reg. */
5597 /* Mark the register as in use for this part of
5599 mark_reload_reg_in_use (i,
5603 rld[r].reg_rtx = last_reg;
5604 reload_inherited[r] = 1;
5605 reload_inheritance_insn[r]
5606 = reg_reloaded_insn[i];
5607 reload_spill_index[r] = i;
5608 for (k = 0; k < nr; k++)
5609 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5617 /* Here's another way to see if the value is already lying around. */
5620 && ! reload_inherited[r]
5622 && (CONSTANT_P (rld[r].in)
5623 || GET_CODE (rld[r].in) == PLUS
5624 || GET_CODE (rld[r].in) == REG
5625 || GET_CODE (rld[r].in) == MEM)
5626 && (rld[r].nregs == max_group_size
5627 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5628 search_equiv = rld[r].in;
5629 /* If this is an output reload from a simple move insn, look
5630 if an equivalence for the input is available. */
5631 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5633 rtx set = single_set (insn);
5636 && rtx_equal_p (rld[r].out, SET_DEST (set))
5637 && CONSTANT_P (SET_SRC (set)))
5638 search_equiv = SET_SRC (set);
5644 = find_equiv_reg (search_equiv, insn, rld[r].class,
5645 -1, NULL, 0, rld[r].mode);
5650 if (GET_CODE (equiv) == REG)
5651 regno = REGNO (equiv);
5652 else if (GET_CODE (equiv) == SUBREG)
5654 /* This must be a SUBREG of a hard register.
5655 Make a new REG since this might be used in an
5656 address and not all machines support SUBREGs
5658 regno = subreg_regno (equiv);
5659 equiv = gen_rtx_REG (rld[r].mode, regno);
5665 /* If we found a spill reg, reject it unless it is free
5666 and of the desired class. */
5668 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5669 && ! free_for_value_p (regno, rld[r].mode,
5670 rld[r].opnum, rld[r].when_needed,
5671 rld[r].in, rld[r].out, r, 1))
5672 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5676 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5679 /* We found a register that contains the value we need.
5680 If this register is the same as an `earlyclobber' operand
5681 of the current insn, just mark it as a place to reload from
5682 since we can't use it as the reload register itself. */
5685 for (i = 0; i < n_earlyclobbers; i++)
5686 if (reg_overlap_mentioned_for_reload_p (equiv,
5687 reload_earlyclobbers[i]))
5689 if (! rld[r].optional)
5690 reload_override_in[r] = equiv;
5695 /* If the equiv register we have found is explicitly clobbered
5696 in the current insn, it depends on the reload type if we
5697 can use it, use it for reload_override_in, or not at all.
5698 In particular, we then can't use EQUIV for a
5699 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5703 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5704 switch (rld[r].when_needed)
5706 case RELOAD_FOR_OTHER_ADDRESS:
5707 case RELOAD_FOR_INPADDR_ADDRESS:
5708 case RELOAD_FOR_INPUT_ADDRESS:
5709 case RELOAD_FOR_OPADDR_ADDR:
5712 case RELOAD_FOR_INPUT:
5713 case RELOAD_FOR_OPERAND_ADDRESS:
5714 if (! rld[r].optional)
5715 reload_override_in[r] = equiv;
5721 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5722 switch (rld[r].when_needed)
5724 case RELOAD_FOR_OTHER_ADDRESS:
5725 case RELOAD_FOR_INPADDR_ADDRESS:
5726 case RELOAD_FOR_INPUT_ADDRESS:
5727 case RELOAD_FOR_OPADDR_ADDR:
5728 case RELOAD_FOR_OPERAND_ADDRESS:
5729 case RELOAD_FOR_INPUT:
5732 if (! rld[r].optional)
5733 reload_override_in[r] = equiv;
5741 /* If we found an equivalent reg, say no code need be generated
5742 to load it, and use it as our reload reg. */
5744 && (regno != HARD_FRAME_POINTER_REGNUM
5745 || !frame_pointer_needed))
5747 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5749 rld[r].reg_rtx = equiv;
5750 reload_inherited[r] = 1;
5752 /* If reg_reloaded_valid is not set for this register,
5753 there might be a stale spill_reg_store lying around.
5754 We must clear it, since otherwise emit_reload_insns
5755 might delete the store. */
5756 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5757 spill_reg_store[regno] = NULL_RTX;
5758 /* If any of the hard registers in EQUIV are spill
5759 registers, mark them as in use for this insn. */
5760 for (k = 0; k < nr; k++)
5762 i = spill_reg_order[regno + k];
5765 mark_reload_reg_in_use (regno, rld[r].opnum,
5768 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5775 /* If we found a register to use already, or if this is an optional
5776 reload, we are done. */
5777 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5781 /* No longer needed for correct operation. Might or might
5782 not give better code on the average. Want to experiment? */
5784 /* See if there is a later reload that has a class different from our
5785 class that intersects our class or that requires less register
5786 than our reload. If so, we must allocate a register to this
5787 reload now, since that reload might inherit a previous reload
5788 and take the only available register in our class. Don't do this
5789 for optional reloads since they will force all previous reloads
5790 to be allocated. Also don't do this for reloads that have been
5793 for (i = j + 1; i < n_reloads; i++)
5795 int s = reload_order[i];
5797 if ((rld[s].in == 0 && rld[s].out == 0
5798 && ! rld[s].secondary_p)
5802 if ((rld[s].class != rld[r].class
5803 && reg_classes_intersect_p (rld[r].class,
5805 || rld[s].nregs < rld[r].nregs)
5812 allocate_reload_reg (chain, r, j == n_reloads - 1);
5816 /* Now allocate reload registers for anything non-optional that
5817 didn't get one yet. */
5818 for (j = 0; j < n_reloads; j++)
5820 int r = reload_order[j];
5822 /* Ignore reloads that got marked inoperative. */
5823 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5826 /* Skip reloads that already have a register allocated or are
5828 if (rld[r].reg_rtx != 0 || rld[r].optional)
5831 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5835 /* If that loop got all the way, we have won. */
5842 /* Loop around and try without any inheritance. */
5847 /* First undo everything done by the failed attempt
5848 to allocate with inheritance. */
5849 choose_reload_regs_init (chain, save_reload_reg_rtx);
5851 /* Some sanity tests to verify that the reloads found in the first
5852 pass are identical to the ones we have now. */
5853 if (chain->n_reloads != n_reloads)
5856 for (i = 0; i < n_reloads; i++)
5858 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5860 if (chain->rld[i].when_needed != rld[i].when_needed)
5862 for (j = 0; j < n_spills; j++)
5863 if (spill_regs[j] == chain->rld[i].regno)
5864 if (! set_reload_reg (j, i))
5865 failed_reload (chain->insn, i);
5869 /* If we thought we could inherit a reload, because it seemed that
5870 nothing else wanted the same reload register earlier in the insn,
5871 verify that assumption, now that all reloads have been assigned.
5872 Likewise for reloads where reload_override_in has been set. */
5874 /* If doing expensive optimizations, do one preliminary pass that doesn't
5875 cancel any inheritance, but removes reloads that have been needed only
5876 for reloads that we know can be inherited. */
5877 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5879 for (j = 0; j < n_reloads; j++)
5881 int r = reload_order[j];
5883 if (reload_inherited[r] && rld[r].reg_rtx)
5884 check_reg = rld[r].reg_rtx;
5885 else if (reload_override_in[r]
5886 && (GET_CODE (reload_override_in[r]) == REG
5887 || GET_CODE (reload_override_in[r]) == SUBREG))
5888 check_reg = reload_override_in[r];
5891 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5892 rld[r].opnum, rld[r].when_needed, rld[r].in,
5893 (reload_inherited[r]
5894 ? rld[r].out : const0_rtx),
5899 reload_inherited[r] = 0;
5900 reload_override_in[r] = 0;
5902 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5903 reload_override_in, then we do not need its related
5904 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5905 likewise for other reload types.
5906 We handle this by removing a reload when its only replacement
5907 is mentioned in reload_in of the reload we are going to inherit.
5908 A special case are auto_inc expressions; even if the input is
5909 inherited, we still need the address for the output. We can
5910 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5911 If we succeeded removing some reload and we are doing a preliminary
5912 pass just to remove such reloads, make another pass, since the
5913 removal of one reload might allow us to inherit another one. */
5915 && rld[r].out != rld[r].in
5916 && remove_address_replacements (rld[r].in) && pass)
5921 /* Now that reload_override_in is known valid,
5922 actually override reload_in. */
5923 for (j = 0; j < n_reloads; j++)
5924 if (reload_override_in[j])
5925 rld[j].in = reload_override_in[j];
5927 /* If this reload won't be done because it has been cancelled or is
5928 optional and not inherited, clear reload_reg_rtx so other
5929 routines (such as subst_reloads) don't get confused. */
5930 for (j = 0; j < n_reloads; j++)
5931 if (rld[j].reg_rtx != 0
5932 && ((rld[j].optional && ! reload_inherited[j])
5933 || (rld[j].in == 0 && rld[j].out == 0
5934 && ! rld[j].secondary_p)))
5936 int regno = true_regnum (rld[j].reg_rtx);
5938 if (spill_reg_order[regno] >= 0)
5939 clear_reload_reg_in_use (regno, rld[j].opnum,
5940 rld[j].when_needed, rld[j].mode);
5942 reload_spill_index[j] = -1;
5945 /* Record which pseudos and which spill regs have output reloads. */
5946 for (j = 0; j < n_reloads; j++)
5948 int r = reload_order[j];
5950 i = reload_spill_index[r];
5952 /* I is nonneg if this reload uses a register.
5953 If rld[r].reg_rtx is 0, this is an optional reload
5954 that we opted to ignore. */
5955 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5956 && rld[r].reg_rtx != 0)
5958 int nregno = REGNO (rld[r].out_reg);
5961 if (nregno < FIRST_PSEUDO_REGISTER)
5962 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5965 reg_has_output_reload[nregno + nr] = 1;
5969 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5971 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5974 if (rld[r].when_needed != RELOAD_OTHER
5975 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5976 && rld[r].when_needed != RELOAD_FOR_INSN)
5982 /* Deallocate the reload register for reload R. This is called from
5983 remove_address_replacements. */
5986 deallocate_reload_reg (r)
5991 if (! rld[r].reg_rtx)
5993 regno = true_regnum (rld[r].reg_rtx);
5995 if (spill_reg_order[regno] >= 0)
5996 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5998 reload_spill_index[r] = -1;
6001 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
6002 reloads of the same item for fear that we might not have enough reload
6003 registers. However, normally they will get the same reload register
6004 and hence actually need not be loaded twice.
6006 Here we check for the most common case of this phenomenon: when we have
6007 a number of reloads for the same object, each of which were allocated
6008 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6009 reload, and is not modified in the insn itself. If we find such,
6010 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6011 This will not increase the number of spill registers needed and will
6012 prevent redundant code. */
6015 merge_assigned_reloads (insn)
6020 /* Scan all the reloads looking for ones that only load values and
6021 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6022 assigned and not modified by INSN. */
6024 for (i = 0; i < n_reloads; i++)
6026 int conflicting_input = 0;
6027 int max_input_address_opnum = -1;
6028 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6030 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6031 || rld[i].out != 0 || rld[i].reg_rtx == 0
6032 || reg_set_p (rld[i].reg_rtx, insn))
6035 /* Look at all other reloads. Ensure that the only use of this
6036 reload_reg_rtx is in a reload that just loads the same value
6037 as we do. Note that any secondary reloads must be of the identical
6038 class since the values, modes, and result registers are the
6039 same, so we need not do anything with any secondary reloads. */
6041 for (j = 0; j < n_reloads; j++)
6043 if (i == j || rld[j].reg_rtx == 0
6044 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6048 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6049 && rld[j].opnum > max_input_address_opnum)
6050 max_input_address_opnum = rld[j].opnum;
6052 /* If the reload regs aren't exactly the same (e.g, different modes)
6053 or if the values are different, we can't merge this reload.
6054 But if it is an input reload, we might still merge
6055 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6057 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6058 || rld[j].out != 0 || rld[j].in == 0
6059 || ! rtx_equal_p (rld[i].in, rld[j].in))
6061 if (rld[j].when_needed != RELOAD_FOR_INPUT
6062 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6063 || rld[i].opnum > rld[j].opnum)
6064 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6066 conflicting_input = 1;
6067 if (min_conflicting_input_opnum > rld[j].opnum)
6068 min_conflicting_input_opnum = rld[j].opnum;
6072 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6073 we, in fact, found any matching reloads. */
6076 && max_input_address_opnum <= min_conflicting_input_opnum)
6078 for (j = 0; j < n_reloads; j++)
6079 if (i != j && rld[j].reg_rtx != 0
6080 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6081 && (! conflicting_input
6082 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6083 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6085 rld[i].when_needed = RELOAD_OTHER;
6087 reload_spill_index[j] = -1;
6088 transfer_replacements (i, j);
6091 /* If this is now RELOAD_OTHER, look for any reloads that load
6092 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6093 if they were for inputs, RELOAD_OTHER for outputs. Note that
6094 this test is equivalent to looking for reloads for this operand
6096 /* We must take special care when there are two or more reloads to
6097 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6098 same value or a part of it; we must not change its type if there
6099 is a conflicting input. */
6101 if (rld[i].when_needed == RELOAD_OTHER)
6102 for (j = 0; j < n_reloads; j++)
6104 && rld[j].when_needed != RELOAD_OTHER
6105 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6106 && (! conflicting_input
6107 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6108 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6109 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6112 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6113 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6114 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6119 /* These arrays are filled by emit_reload_insns and its subroutines. */
6120 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6121 static rtx other_input_address_reload_insns = 0;
6122 static rtx other_input_reload_insns = 0;
6123 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6124 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6125 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6126 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6127 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6128 static rtx operand_reload_insns = 0;
6129 static rtx other_operand_reload_insns = 0;
6130 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6132 /* Values to be put in spill_reg_store are put here first. */
6133 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6134 static HARD_REG_SET reg_reloaded_died;
6136 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6137 has the number J. OLD contains the value to be used as input. */
6140 emit_input_reload_insns (chain, rl, old, j)
6141 struct insn_chain *chain;
6146 rtx insn = chain->insn;
6147 rtx reloadreg = rl->reg_rtx;
6148 rtx oldequiv_reg = 0;
6151 enum machine_mode mode;
6154 /* Determine the mode to reload in.
6155 This is very tricky because we have three to choose from.
6156 There is the mode the insn operand wants (rl->inmode).
6157 There is the mode of the reload register RELOADREG.
6158 There is the intrinsic mode of the operand, which we could find
6159 by stripping some SUBREGs.
6160 It turns out that RELOADREG's mode is irrelevant:
6161 we can change that arbitrarily.
6163 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6164 then the reload reg may not support QImode moves, so use SImode.
6165 If foo is in memory due to spilling a pseudo reg, this is safe,
6166 because the QImode value is in the least significant part of a
6167 slot big enough for a SImode. If foo is some other sort of
6168 memory reference, then it is impossible to reload this case,
6169 so previous passes had better make sure this never happens.
6171 Then consider a one-word union which has SImode and one of its
6172 members is a float, being fetched as (SUBREG:SF union:SI).
6173 We must fetch that as SFmode because we could be loading into
6174 a float-only register. In this case OLD's mode is correct.
6176 Consider an immediate integer: it has VOIDmode. Here we need
6177 to get a mode from something else.
6179 In some cases, there is a fourth mode, the operand's
6180 containing mode. If the insn specifies a containing mode for
6181 this operand, it overrides all others.
6183 I am not sure whether the algorithm here is always right,
6184 but it does the right things in those cases. */
6186 mode = GET_MODE (old);
6187 if (mode == VOIDmode)
6190 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6191 /* If we need a secondary register for this operation, see if
6192 the value is already in a register in that class. Don't
6193 do this if the secondary register will be used as a scratch
6196 if (rl->secondary_in_reload >= 0
6197 && rl->secondary_in_icode == CODE_FOR_nothing
6200 = find_equiv_reg (old, insn,
6201 rld[rl->secondary_in_reload].class,
6205 /* If reloading from memory, see if there is a register
6206 that already holds the same value. If so, reload from there.
6207 We can pass 0 as the reload_reg_p argument because
6208 any other reload has either already been emitted,
6209 in which case find_equiv_reg will see the reload-insn,
6210 or has yet to be emitted, in which case it doesn't matter
6211 because we will use this equiv reg right away. */
6213 if (oldequiv == 0 && optimize
6214 && (GET_CODE (old) == MEM
6215 || (GET_CODE (old) == REG
6216 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6217 && reg_renumber[REGNO (old)] < 0)))
6218 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6222 unsigned int regno = true_regnum (oldequiv);
6224 /* Don't use OLDEQUIV if any other reload changes it at an
6225 earlier stage of this insn or at this stage. */
6226 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6227 rl->in, const0_rtx, j, 0))
6230 /* If it is no cheaper to copy from OLDEQUIV into the
6231 reload register than it would be to move from memory,
6232 don't use it. Likewise, if we need a secondary register
6236 && ((REGNO_REG_CLASS (regno) != rl->class
6237 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6239 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6240 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6241 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6245 #ifdef SECONDARY_MEMORY_NEEDED
6246 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6254 /* delete_output_reload is only invoked properly if old contains
6255 the original pseudo register. Since this is replaced with a
6256 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6257 find the pseudo in RELOAD_IN_REG. */
6259 && reload_override_in[j]
6260 && GET_CODE (rl->in_reg) == REG)
6267 else if (GET_CODE (oldequiv) == REG)
6268 oldequiv_reg = oldequiv;
6269 else if (GET_CODE (oldequiv) == SUBREG)
6270 oldequiv_reg = SUBREG_REG (oldequiv);
6272 /* If we are reloading from a register that was recently stored in
6273 with an output-reload, see if we can prove there was
6274 actually no need to store the old value in it. */
6276 if (optimize && GET_CODE (oldequiv) == REG
6277 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6278 && spill_reg_store[REGNO (oldequiv)]
6279 && GET_CODE (old) == REG
6280 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6281 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6283 delete_output_reload (insn, j, REGNO (oldequiv));
6285 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6286 then load RELOADREG from OLDEQUIV. Note that we cannot use
6287 gen_lowpart_common since it can do the wrong thing when
6288 RELOADREG has a multi-word mode. Note that RELOADREG
6289 must always be a REG here. */
6291 if (GET_MODE (reloadreg) != mode)
6292 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6293 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6294 oldequiv = SUBREG_REG (oldequiv);
6295 if (GET_MODE (oldequiv) != VOIDmode
6296 && mode != GET_MODE (oldequiv))
6297 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6299 /* Switch to the right place to emit the reload insns. */
6300 switch (rl->when_needed)
6303 where = &other_input_reload_insns;
6305 case RELOAD_FOR_INPUT:
6306 where = &input_reload_insns[rl->opnum];
6308 case RELOAD_FOR_INPUT_ADDRESS:
6309 where = &input_address_reload_insns[rl->opnum];
6311 case RELOAD_FOR_INPADDR_ADDRESS:
6312 where = &inpaddr_address_reload_insns[rl->opnum];
6314 case RELOAD_FOR_OUTPUT_ADDRESS:
6315 where = &output_address_reload_insns[rl->opnum];
6317 case RELOAD_FOR_OUTADDR_ADDRESS:
6318 where = &outaddr_address_reload_insns[rl->opnum];
6320 case RELOAD_FOR_OPERAND_ADDRESS:
6321 where = &operand_reload_insns;
6323 case RELOAD_FOR_OPADDR_ADDR:
6324 where = &other_operand_reload_insns;
6326 case RELOAD_FOR_OTHER_ADDRESS:
6327 where = &other_input_address_reload_insns;
6333 push_to_sequence (*where);
6335 /* Auto-increment addresses must be reloaded in a special way. */
6336 if (rl->out && ! rl->out_reg)
6338 /* We are not going to bother supporting the case where a
6339 incremented register can't be copied directly from
6340 OLDEQUIV since this seems highly unlikely. */
6341 if (rl->secondary_in_reload >= 0)
6344 if (reload_inherited[j])
6345 oldequiv = reloadreg;
6347 old = XEXP (rl->in_reg, 0);
6349 if (optimize && GET_CODE (oldequiv) == REG
6350 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6351 && spill_reg_store[REGNO (oldequiv)]
6352 && GET_CODE (old) == REG
6353 && (dead_or_set_p (insn,
6354 spill_reg_stored_to[REGNO (oldequiv)])
6355 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6357 delete_output_reload (insn, j, REGNO (oldequiv));
6359 /* Prevent normal processing of this reload. */
6361 /* Output a special code sequence for this case. */
6362 new_spill_reg_store[REGNO (reloadreg)]
6363 = inc_for_reload (reloadreg, oldequiv, rl->out,
6367 /* If we are reloading a pseudo-register that was set by the previous
6368 insn, see if we can get rid of that pseudo-register entirely
6369 by redirecting the previous insn into our reload register. */
6371 else if (optimize && GET_CODE (old) == REG
6372 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6373 && dead_or_set_p (insn, old)
6374 /* This is unsafe if some other reload
6375 uses the same reg first. */
6376 && ! conflicts_with_override (reloadreg)
6377 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6378 rl->when_needed, old, rl->out, j, 0))
6380 rtx temp = PREV_INSN (insn);
6381 while (temp && GET_CODE (temp) == NOTE)
6382 temp = PREV_INSN (temp);
6384 && GET_CODE (temp) == INSN
6385 && GET_CODE (PATTERN (temp)) == SET
6386 && SET_DEST (PATTERN (temp)) == old
6387 /* Make sure we can access insn_operand_constraint. */
6388 && asm_noperands (PATTERN (temp)) < 0
6389 /* This is unsafe if operand occurs more than once in current
6390 insn. Perhaps some occurrences aren't reloaded. */
6391 && count_occurrences (PATTERN (insn), old, 0) == 1)
6393 rtx old = SET_DEST (PATTERN (temp));
6394 /* Store into the reload register instead of the pseudo. */
6395 SET_DEST (PATTERN (temp)) = reloadreg;
6397 /* Verify that resulting insn is valid. */
6398 extract_insn (temp);
6399 if (constrain_operands (1))
6401 /* If the previous insn is an output reload, the source is
6402 a reload register, and its spill_reg_store entry will
6403 contain the previous destination. This is now
6405 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6406 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6408 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6409 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6412 /* If these are the only uses of the pseudo reg,
6413 pretend for GDB it lives in the reload reg we used. */
6414 if (REG_N_DEATHS (REGNO (old)) == 1
6415 && REG_N_SETS (REGNO (old)) == 1)
6417 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6418 alter_reg (REGNO (old), -1);
6424 SET_DEST (PATTERN (temp)) = old;
6429 /* We can't do that, so output an insn to load RELOADREG. */
6431 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6432 /* If we have a secondary reload, pick up the secondary register
6433 and icode, if any. If OLDEQUIV and OLD are different or
6434 if this is an in-out reload, recompute whether or not we
6435 still need a secondary register and what the icode should
6436 be. If we still need a secondary register and the class or
6437 icode is different, go back to reloading from OLD if using
6438 OLDEQUIV means that we got the wrong type of register. We
6439 cannot have different class or icode due to an in-out reload
6440 because we don't make such reloads when both the input and
6441 output need secondary reload registers. */
6443 if (! special && rl->secondary_in_reload >= 0)
6445 rtx second_reload_reg = 0;
6446 int secondary_reload = rl->secondary_in_reload;
6447 rtx real_oldequiv = oldequiv;
6450 enum insn_code icode;
6452 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6453 and similarly for OLD.
6454 See comments in get_secondary_reload in reload.c. */
6455 /* If it is a pseudo that cannot be replaced with its
6456 equivalent MEM, we must fall back to reload_in, which
6457 will have all the necessary substitutions registered.
6458 Likewise for a pseudo that can't be replaced with its
6459 equivalent constant.
6461 Take extra care for subregs of such pseudos. Note that
6462 we cannot use reg_equiv_mem in this case because it is
6463 not in the right mode. */
6466 if (GET_CODE (tmp) == SUBREG)
6467 tmp = SUBREG_REG (tmp);
6468 if (GET_CODE (tmp) == REG
6469 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6470 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6471 || reg_equiv_constant[REGNO (tmp)] != 0))
6473 if (! reg_equiv_mem[REGNO (tmp)]
6474 || num_not_at_initial_offset
6475 || GET_CODE (oldequiv) == SUBREG)
6476 real_oldequiv = rl->in;
6478 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6482 if (GET_CODE (tmp) == SUBREG)
6483 tmp = SUBREG_REG (tmp);
6484 if (GET_CODE (tmp) == REG
6485 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6486 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6487 || reg_equiv_constant[REGNO (tmp)] != 0))
6489 if (! reg_equiv_mem[REGNO (tmp)]
6490 || num_not_at_initial_offset
6491 || GET_CODE (old) == SUBREG)
6494 real_old = reg_equiv_mem[REGNO (tmp)];
6497 second_reload_reg = rld[secondary_reload].reg_rtx;
6498 icode = rl->secondary_in_icode;
6500 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6501 || (rl->in != 0 && rl->out != 0))
6503 enum reg_class new_class
6504 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6505 mode, real_oldequiv);
6507 if (new_class == NO_REGS)
6508 second_reload_reg = 0;
6511 enum insn_code new_icode;
6512 enum machine_mode new_mode;
6514 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6515 REGNO (second_reload_reg)))
6516 oldequiv = old, real_oldequiv = real_old;
6519 new_icode = reload_in_optab[(int) mode];
6520 if (new_icode != CODE_FOR_nothing
6521 && ((insn_data[(int) new_icode].operand[0].predicate
6522 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6524 || (insn_data[(int) new_icode].operand[1].predicate
6525 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6526 (real_oldequiv, mode)))))
6527 new_icode = CODE_FOR_nothing;
6529 if (new_icode == CODE_FOR_nothing)
6532 new_mode = insn_data[(int) new_icode].operand[2].mode;
6534 if (GET_MODE (second_reload_reg) != new_mode)
6536 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6538 oldequiv = old, real_oldequiv = real_old;
6541 = gen_rtx_REG (new_mode,
6542 REGNO (second_reload_reg));
6548 /* If we still need a secondary reload register, check
6549 to see if it is being used as a scratch or intermediate
6550 register and generate code appropriately. If we need
6551 a scratch register, use REAL_OLDEQUIV since the form of
6552 the insn may depend on the actual address if it is
6555 if (second_reload_reg)
6557 if (icode != CODE_FOR_nothing)
6559 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6560 second_reload_reg));
6565 /* See if we need a scratch register to load the
6566 intermediate register (a tertiary reload). */
6567 enum insn_code tertiary_icode
6568 = rld[secondary_reload].secondary_in_icode;
6570 if (tertiary_icode != CODE_FOR_nothing)
6572 rtx third_reload_reg
6573 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6575 emit_insn ((GEN_FCN (tertiary_icode)
6576 (second_reload_reg, real_oldequiv,
6577 third_reload_reg)));
6580 gen_reload (second_reload_reg, real_oldequiv,
6584 oldequiv = second_reload_reg;
6590 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6592 rtx real_oldequiv = oldequiv;
6594 if ((GET_CODE (oldequiv) == REG
6595 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6596 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6597 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6598 || (GET_CODE (oldequiv) == SUBREG
6599 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6600 && (REGNO (SUBREG_REG (oldequiv))
6601 >= FIRST_PSEUDO_REGISTER)
6602 && ((reg_equiv_memory_loc
6603 [REGNO (SUBREG_REG (oldequiv))] != 0)
6604 || (reg_equiv_constant
6605 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6606 || (CONSTANT_P (oldequiv)
6607 && (PREFERRED_RELOAD_CLASS (oldequiv,
6608 REGNO_REG_CLASS (REGNO (reloadreg)))
6610 real_oldequiv = rl->in;
6611 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6615 if (flag_non_call_exceptions)
6616 copy_eh_notes (insn, get_insns ());
6618 /* End this sequence. */
6619 *where = get_insns ();
6622 /* Update reload_override_in so that delete_address_reloads_1
6623 can see the actual register usage. */
6625 reload_override_in[j] = oldequiv;
6628 /* Generate insns to for the output reload RL, which is for the insn described
6629 by CHAIN and has the number J. */
6631 emit_output_reload_insns (chain, rl, j)
6632 struct insn_chain *chain;
6636 rtx reloadreg = rl->reg_rtx;
6637 rtx insn = chain->insn;
6640 enum machine_mode mode = GET_MODE (old);
6643 if (rl->when_needed == RELOAD_OTHER)
6646 push_to_sequence (output_reload_insns[rl->opnum]);
6648 /* Determine the mode to reload in.
6649 See comments above (for input reloading). */
6651 if (mode == VOIDmode)
6653 /* VOIDmode should never happen for an output. */
6654 if (asm_noperands (PATTERN (insn)) < 0)
6655 /* It's the compiler's fault. */
6656 fatal_insn ("VOIDmode on an output", insn);
6657 error_for_asm (insn, "output operand is constant in `asm'");
6658 /* Prevent crash--use something we know is valid. */
6660 old = gen_rtx_REG (mode, REGNO (reloadreg));
6663 if (GET_MODE (reloadreg) != mode)
6664 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6666 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6668 /* If we need two reload regs, set RELOADREG to the intermediate
6669 one, since it will be stored into OLD. We might need a secondary
6670 register only for an input reload, so check again here. */
6672 if (rl->secondary_out_reload >= 0)
6676 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6677 && reg_equiv_mem[REGNO (old)] != 0)
6678 real_old = reg_equiv_mem[REGNO (old)];
6680 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6684 rtx second_reloadreg = reloadreg;
6685 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6687 /* See if RELOADREG is to be used as a scratch register
6688 or as an intermediate register. */
6689 if (rl->secondary_out_icode != CODE_FOR_nothing)
6691 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6692 (real_old, second_reloadreg, reloadreg)));
6697 /* See if we need both a scratch and intermediate reload
6700 int secondary_reload = rl->secondary_out_reload;
6701 enum insn_code tertiary_icode
6702 = rld[secondary_reload].secondary_out_icode;
6704 if (GET_MODE (reloadreg) != mode)
6705 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6707 if (tertiary_icode != CODE_FOR_nothing)
6710 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6713 /* Copy primary reload reg to secondary reload reg.
6714 (Note that these have been swapped above, then
6715 secondary reload reg to OLD using our insn.) */
6717 /* If REAL_OLD is a paradoxical SUBREG, remove it
6718 and try to put the opposite SUBREG on
6720 if (GET_CODE (real_old) == SUBREG
6721 && (GET_MODE_SIZE (GET_MODE (real_old))
6722 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6723 && 0 != (tem = gen_lowpart_common
6724 (GET_MODE (SUBREG_REG (real_old)),
6726 real_old = SUBREG_REG (real_old), reloadreg = tem;
6728 gen_reload (reloadreg, second_reloadreg,
6729 rl->opnum, rl->when_needed);
6730 emit_insn ((GEN_FCN (tertiary_icode)
6731 (real_old, reloadreg, third_reloadreg)));
6736 /* Copy between the reload regs here and then to
6739 gen_reload (reloadreg, second_reloadreg,
6740 rl->opnum, rl->when_needed);
6746 /* Output the last reload insn. */
6751 /* Don't output the last reload if OLD is not the dest of
6752 INSN and is in the src and is clobbered by INSN. */
6753 if (! flag_expensive_optimizations
6754 || GET_CODE (old) != REG
6755 || !(set = single_set (insn))
6756 || rtx_equal_p (old, SET_DEST (set))
6757 || !reg_mentioned_p (old, SET_SRC (set))
6758 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6759 gen_reload (old, reloadreg, rl->opnum,
6763 /* Look at all insns we emitted, just to be safe. */
6764 for (p = get_insns (); p; p = NEXT_INSN (p))
6767 rtx pat = PATTERN (p);
6769 /* If this output reload doesn't come from a spill reg,
6770 clear any memory of reloaded copies of the pseudo reg.
6771 If this output reload comes from a spill reg,
6772 reg_has_output_reload will make this do nothing. */
6773 note_stores (pat, forget_old_reloads_1, NULL);
6775 if (reg_mentioned_p (rl->reg_rtx, pat))
6777 rtx set = single_set (insn);
6778 if (reload_spill_index[j] < 0
6780 && SET_SRC (set) == rl->reg_rtx)
6782 int src = REGNO (SET_SRC (set));
6784 reload_spill_index[j] = src;
6785 SET_HARD_REG_BIT (reg_is_output_reload, src);
6786 if (find_regno_note (insn, REG_DEAD, src))
6787 SET_HARD_REG_BIT (reg_reloaded_died, src);
6789 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6791 int s = rl->secondary_out_reload;
6792 set = single_set (p);
6793 /* If this reload copies only to the secondary reload
6794 register, the secondary reload does the actual
6796 if (s >= 0 && set == NULL_RTX)
6797 /* We can't tell what function the secondary reload
6798 has and where the actual store to the pseudo is
6799 made; leave new_spill_reg_store alone. */
6802 && SET_SRC (set) == rl->reg_rtx
6803 && SET_DEST (set) == rld[s].reg_rtx)
6805 /* Usually the next instruction will be the
6806 secondary reload insn; if we can confirm
6807 that it is, setting new_spill_reg_store to
6808 that insn will allow an extra optimization. */
6809 rtx s_reg = rld[s].reg_rtx;
6810 rtx next = NEXT_INSN (p);
6811 rld[s].out = rl->out;
6812 rld[s].out_reg = rl->out_reg;
6813 set = single_set (next);
6814 if (set && SET_SRC (set) == s_reg
6815 && ! new_spill_reg_store[REGNO (s_reg)])
6817 SET_HARD_REG_BIT (reg_is_output_reload,
6819 new_spill_reg_store[REGNO (s_reg)] = next;
6823 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6828 if (rl->when_needed == RELOAD_OTHER)
6830 emit_insn (other_output_reload_insns[rl->opnum]);
6831 other_output_reload_insns[rl->opnum] = get_insns ();
6834 output_reload_insns[rl->opnum] = get_insns ();
6836 if (flag_non_call_exceptions)
6837 copy_eh_notes (insn, get_insns ());
6842 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6843 and has the number J. */
6845 do_input_reload (chain, rl, j)
6846 struct insn_chain *chain;
6850 int expect_occurrences = 1;
6851 rtx insn = chain->insn;
6852 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6853 ? rl->in_reg : rl->in);
6856 /* AUTO_INC reloads need to be handled even if inherited. We got an
6857 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6858 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6859 && ! rtx_equal_p (rl->reg_rtx, old)
6860 && rl->reg_rtx != 0)
6861 emit_input_reload_insns (chain, rld + j, old, j);
6863 /* When inheriting a wider reload, we have a MEM in rl->in,
6864 e.g. inheriting a SImode output reload for
6865 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6866 if (optimize && reload_inherited[j] && rl->in
6867 && GET_CODE (rl->in) == MEM
6868 && GET_CODE (rl->in_reg) == MEM
6869 && reload_spill_index[j] >= 0
6870 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6873 = count_occurrences (PATTERN (insn), rl->in, 0) == 1 ? 0 : -1;
6874 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6877 /* If we are reloading a register that was recently stored in with an
6878 output-reload, see if we can prove there was
6879 actually no need to store the old value in it. */
6882 && (reload_inherited[j] || reload_override_in[j])
6884 && GET_CODE (rl->reg_rtx) == REG
6885 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6887 /* There doesn't seem to be any reason to restrict this to pseudos
6888 and doing so loses in the case where we are copying from a
6889 register of the wrong class. */
6890 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6891 >= FIRST_PSEUDO_REGISTER)
6893 /* The insn might have already some references to stackslots
6894 replaced by MEMs, while reload_out_reg still names the
6896 && (dead_or_set_p (insn,
6897 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6898 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6900 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6903 /* Do output reloading for reload RL, which is for the insn described by
6904 CHAIN and has the number J.
6905 ??? At some point we need to support handling output reloads of
6906 JUMP_INSNs or insns that set cc0. */
6908 do_output_reload (chain, rl, j)
6909 struct insn_chain *chain;
6914 rtx insn = chain->insn;
6915 /* If this is an output reload that stores something that is
6916 not loaded in this same reload, see if we can eliminate a previous
6918 rtx pseudo = rl->out_reg;
6922 && GET_CODE (pseudo) == REG
6923 && ! rtx_equal_p (rl->in_reg, pseudo)
6924 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6925 && reg_last_reload_reg[REGNO (pseudo)])
6927 int pseudo_no = REGNO (pseudo);
6928 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6930 /* We don't need to test full validity of last_regno for
6931 inherit here; we only want to know if the store actually
6932 matches the pseudo. */
6933 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6934 && reg_reloaded_contents[last_regno] == pseudo_no
6935 && spill_reg_store[last_regno]
6936 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6937 delete_output_reload (insn, j, last_regno);
6942 || rl->reg_rtx == old
6943 || rl->reg_rtx == 0)
6946 /* An output operand that dies right away does need a reload,
6947 but need not be copied from it. Show the new location in the
6949 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6950 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6952 XEXP (note, 0) = rl->reg_rtx;
6955 /* Likewise for a SUBREG of an operand that dies. */
6956 else if (GET_CODE (old) == SUBREG
6957 && GET_CODE (SUBREG_REG (old)) == REG
6958 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6961 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6965 else if (GET_CODE (old) == SCRATCH)
6966 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6967 but we don't want to make an output reload. */
6970 /* If is a JUMP_INSN, we can't support output reloads yet. */
6971 if (GET_CODE (insn) == JUMP_INSN)
6974 emit_output_reload_insns (chain, rld + j, j);
6977 /* Output insns to reload values in and out of the chosen reload regs. */
6980 emit_reload_insns (chain)
6981 struct insn_chain *chain;
6983 rtx insn = chain->insn;
6987 CLEAR_HARD_REG_SET (reg_reloaded_died);
6989 for (j = 0; j < reload_n_operands; j++)
6990 input_reload_insns[j] = input_address_reload_insns[j]
6991 = inpaddr_address_reload_insns[j]
6992 = output_reload_insns[j] = output_address_reload_insns[j]
6993 = outaddr_address_reload_insns[j]
6994 = other_output_reload_insns[j] = 0;
6995 other_input_address_reload_insns = 0;
6996 other_input_reload_insns = 0;
6997 operand_reload_insns = 0;
6998 other_operand_reload_insns = 0;
7000 /* Dump reloads into the dump file. */
7003 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7004 debug_reload_to_stream (rtl_dump_file);
7007 /* Now output the instructions to copy the data into and out of the
7008 reload registers. Do these in the order that the reloads were reported,
7009 since reloads of base and index registers precede reloads of operands
7010 and the operands may need the base and index registers reloaded. */
7012 for (j = 0; j < n_reloads; j++)
7015 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7016 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7018 do_input_reload (chain, rld + j, j);
7019 do_output_reload (chain, rld + j, j);
7022 /* Now write all the insns we made for reloads in the order expected by
7023 the allocation functions. Prior to the insn being reloaded, we write
7024 the following reloads:
7026 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7028 RELOAD_OTHER reloads.
7030 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7031 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7032 RELOAD_FOR_INPUT reload for the operand.
7034 RELOAD_FOR_OPADDR_ADDRS reloads.
7036 RELOAD_FOR_OPERAND_ADDRESS reloads.
7038 After the insn being reloaded, we write the following:
7040 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7041 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7042 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7043 reloads for the operand. The RELOAD_OTHER output reloads are
7044 output in descending order by reload number. */
7046 emit_insn_before (other_input_address_reload_insns, insn);
7047 emit_insn_before (other_input_reload_insns, insn);
7049 for (j = 0; j < reload_n_operands; j++)
7051 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7052 emit_insn_before (input_address_reload_insns[j], insn);
7053 emit_insn_before (input_reload_insns[j], insn);
7056 emit_insn_before (other_operand_reload_insns, insn);
7057 emit_insn_before (operand_reload_insns, insn);
7059 for (j = 0; j < reload_n_operands; j++)
7061 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7062 x = emit_insn_after (output_address_reload_insns[j], x);
7063 x = emit_insn_after (output_reload_insns[j], x);
7064 emit_insn_after (other_output_reload_insns[j], x);
7067 /* For all the spill regs newly reloaded in this instruction,
7068 record what they were reloaded from, so subsequent instructions
7069 can inherit the reloads.
7071 Update spill_reg_store for the reloads of this insn.
7072 Copy the elements that were updated in the loop above. */
7074 for (j = 0; j < n_reloads; j++)
7076 int r = reload_order[j];
7077 int i = reload_spill_index[r];
7079 /* If this is a non-inherited input reload from a pseudo, we must
7080 clear any memory of a previous store to the same pseudo. Only do
7081 something if there will not be an output reload for the pseudo
7083 if (rld[r].in_reg != 0
7084 && ! (reload_inherited[r] || reload_override_in[r]))
7086 rtx reg = rld[r].in_reg;
7088 if (GET_CODE (reg) == SUBREG)
7089 reg = SUBREG_REG (reg);
7091 if (GET_CODE (reg) == REG
7092 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7093 && ! reg_has_output_reload[REGNO (reg)])
7095 int nregno = REGNO (reg);
7097 if (reg_last_reload_reg[nregno])
7099 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7101 if (reg_reloaded_contents[last_regno] == nregno)
7102 spill_reg_store[last_regno] = 0;
7107 /* I is nonneg if this reload used a register.
7108 If rld[r].reg_rtx is 0, this is an optional reload
7109 that we opted to ignore. */
7111 if (i >= 0 && rld[r].reg_rtx != 0)
7113 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7115 int part_reaches_end = 0;
7116 int all_reaches_end = 1;
7118 /* For a multi register reload, we need to check if all or part
7119 of the value lives to the end. */
7120 for (k = 0; k < nr; k++)
7122 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7123 rld[r].when_needed))
7124 part_reaches_end = 1;
7126 all_reaches_end = 0;
7129 /* Ignore reloads that don't reach the end of the insn in
7131 if (all_reaches_end)
7133 /* First, clear out memory of what used to be in this spill reg.
7134 If consecutive registers are used, clear them all. */
7136 for (k = 0; k < nr; k++)
7137 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7139 /* Maybe the spill reg contains a copy of reload_out. */
7141 && (GET_CODE (rld[r].out) == REG
7145 || GET_CODE (rld[r].out_reg) == REG))
7147 rtx out = (GET_CODE (rld[r].out) == REG
7151 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7152 int nregno = REGNO (out);
7153 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7154 : HARD_REGNO_NREGS (nregno,
7155 GET_MODE (rld[r].reg_rtx)));
7157 spill_reg_store[i] = new_spill_reg_store[i];
7158 spill_reg_stored_to[i] = out;
7159 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7161 /* If NREGNO is a hard register, it may occupy more than
7162 one register. If it does, say what is in the
7163 rest of the registers assuming that both registers
7164 agree on how many words the object takes. If not,
7165 invalidate the subsequent registers. */
7167 if (nregno < FIRST_PSEUDO_REGISTER)
7168 for (k = 1; k < nnr; k++)
7169 reg_last_reload_reg[nregno + k]
7171 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7174 /* Now do the inverse operation. */
7175 for (k = 0; k < nr; k++)
7177 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7178 reg_reloaded_contents[i + k]
7179 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7182 reg_reloaded_insn[i + k] = insn;
7183 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7187 /* Maybe the spill reg contains a copy of reload_in. Only do
7188 something if there will not be an output reload for
7189 the register being reloaded. */
7190 else if (rld[r].out_reg == 0
7192 && ((GET_CODE (rld[r].in) == REG
7193 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7194 && ! reg_has_output_reload[REGNO (rld[r].in)])
7195 || (GET_CODE (rld[r].in_reg) == REG
7196 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7197 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7202 if (GET_CODE (rld[r].in) == REG
7203 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7204 nregno = REGNO (rld[r].in);
7205 else if (GET_CODE (rld[r].in_reg) == REG)
7206 nregno = REGNO (rld[r].in_reg);
7208 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7210 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7211 : HARD_REGNO_NREGS (nregno,
7212 GET_MODE (rld[r].reg_rtx)));
7214 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7216 if (nregno < FIRST_PSEUDO_REGISTER)
7217 for (k = 1; k < nnr; k++)
7218 reg_last_reload_reg[nregno + k]
7220 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7223 /* Unless we inherited this reload, show we haven't
7224 recently done a store.
7225 Previous stores of inherited auto_inc expressions
7226 also have to be discarded. */
7227 if (! reload_inherited[r]
7228 || (rld[r].out && ! rld[r].out_reg))
7229 spill_reg_store[i] = 0;
7231 for (k = 0; k < nr; k++)
7233 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7234 reg_reloaded_contents[i + k]
7235 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7238 reg_reloaded_insn[i + k] = insn;
7239 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7244 /* However, if part of the reload reaches the end, then we must
7245 invalidate the old info for the part that survives to the end. */
7246 else if (part_reaches_end)
7248 for (k = 0; k < nr; k++)
7249 if (reload_reg_reaches_end_p (i + k,
7251 rld[r].when_needed))
7252 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7256 /* The following if-statement was #if 0'd in 1.34 (or before...).
7257 It's reenabled in 1.35 because supposedly nothing else
7258 deals with this problem. */
7260 /* If a register gets output-reloaded from a non-spill register,
7261 that invalidates any previous reloaded copy of it.
7262 But forget_old_reloads_1 won't get to see it, because
7263 it thinks only about the original insn. So invalidate it here. */
7264 if (i < 0 && rld[r].out != 0
7265 && (GET_CODE (rld[r].out) == REG
7266 || (GET_CODE (rld[r].out) == MEM
7267 && GET_CODE (rld[r].out_reg) == REG)))
7269 rtx out = (GET_CODE (rld[r].out) == REG
7270 ? rld[r].out : rld[r].out_reg);
7271 int nregno = REGNO (out);
7272 if (nregno >= FIRST_PSEUDO_REGISTER)
7274 rtx src_reg, store_insn = NULL_RTX;
7276 reg_last_reload_reg[nregno] = 0;
7278 /* If we can find a hard register that is stored, record
7279 the storing insn so that we may delete this insn with
7280 delete_output_reload. */
7281 src_reg = rld[r].reg_rtx;
7283 /* If this is an optional reload, try to find the source reg
7284 from an input reload. */
7287 rtx set = single_set (insn);
7288 if (set && SET_DEST (set) == rld[r].out)
7292 src_reg = SET_SRC (set);
7294 for (k = 0; k < n_reloads; k++)
7296 if (rld[k].in == src_reg)
7298 src_reg = rld[k].reg_rtx;
7305 store_insn = new_spill_reg_store[REGNO (src_reg)];
7306 if (src_reg && GET_CODE (src_reg) == REG
7307 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7309 int src_regno = REGNO (src_reg);
7310 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7311 /* The place where to find a death note varies with
7312 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7313 necessarily checked exactly in the code that moves
7314 notes, so just check both locations. */
7315 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7316 if (! note && store_insn)
7317 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7320 spill_reg_store[src_regno + nr] = store_insn;
7321 spill_reg_stored_to[src_regno + nr] = out;
7322 reg_reloaded_contents[src_regno + nr] = nregno;
7323 reg_reloaded_insn[src_regno + nr] = store_insn;
7324 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7325 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7326 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7328 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7330 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7332 reg_last_reload_reg[nregno] = src_reg;
7337 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7339 while (num_regs-- > 0)
7340 reg_last_reload_reg[nregno + num_regs] = 0;
7344 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7347 /* Emit code to perform a reload from IN (which may be a reload register) to
7348 OUT (which may also be a reload register). IN or OUT is from operand
7349 OPNUM with reload type TYPE.
7351 Returns first insn emitted. */
7354 gen_reload (out, in, opnum, type)
7358 enum reload_type type;
7360 rtx last = get_last_insn ();
7363 /* If IN is a paradoxical SUBREG, remove it and try to put the
7364 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7365 if (GET_CODE (in) == SUBREG
7366 && (GET_MODE_SIZE (GET_MODE (in))
7367 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7368 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7369 in = SUBREG_REG (in), out = tem;
7370 else if (GET_CODE (out) == SUBREG
7371 && (GET_MODE_SIZE (GET_MODE (out))
7372 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7373 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7374 out = SUBREG_REG (out), in = tem;
7376 /* How to do this reload can get quite tricky. Normally, we are being
7377 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7378 register that didn't get a hard register. In that case we can just
7379 call emit_move_insn.
7381 We can also be asked to reload a PLUS that adds a register or a MEM to
7382 another register, constant or MEM. This can occur during frame pointer
7383 elimination and while reloading addresses. This case is handled by
7384 trying to emit a single insn to perform the add. If it is not valid,
7385 we use a two insn sequence.
7387 Finally, we could be called to handle an 'o' constraint by putting
7388 an address into a register. In that case, we first try to do this
7389 with a named pattern of "reload_load_address". If no such pattern
7390 exists, we just emit a SET insn and hope for the best (it will normally
7391 be valid on machines that use 'o').
7393 This entire process is made complex because reload will never
7394 process the insns we generate here and so we must ensure that
7395 they will fit their constraints and also by the fact that parts of
7396 IN might be being reloaded separately and replaced with spill registers.
7397 Because of this, we are, in some sense, just guessing the right approach
7398 here. The one listed above seems to work.
7400 ??? At some point, this whole thing needs to be rethought. */
7402 if (GET_CODE (in) == PLUS
7403 && (GET_CODE (XEXP (in, 0)) == REG
7404 || GET_CODE (XEXP (in, 0)) == SUBREG
7405 || GET_CODE (XEXP (in, 0)) == MEM)
7406 && (GET_CODE (XEXP (in, 1)) == REG
7407 || GET_CODE (XEXP (in, 1)) == SUBREG
7408 || CONSTANT_P (XEXP (in, 1))
7409 || GET_CODE (XEXP (in, 1)) == MEM))
7411 /* We need to compute the sum of a register or a MEM and another
7412 register, constant, or MEM, and put it into the reload
7413 register. The best possible way of doing this is if the machine
7414 has a three-operand ADD insn that accepts the required operands.
7416 The simplest approach is to try to generate such an insn and see if it
7417 is recognized and matches its constraints. If so, it can be used.
7419 It might be better not to actually emit the insn unless it is valid,
7420 but we need to pass the insn as an operand to `recog' and
7421 `extract_insn' and it is simpler to emit and then delete the insn if
7422 not valid than to dummy things up. */
7424 rtx op0, op1, tem, insn;
7427 op0 = find_replacement (&XEXP (in, 0));
7428 op1 = find_replacement (&XEXP (in, 1));
7430 /* Since constraint checking is strict, commutativity won't be
7431 checked, so we need to do that here to avoid spurious failure
7432 if the add instruction is two-address and the second operand
7433 of the add is the same as the reload reg, which is frequently
7434 the case. If the insn would be A = B + A, rearrange it so
7435 it will be A = A + B as constrain_operands expects. */
7437 if (GET_CODE (XEXP (in, 1)) == REG
7438 && REGNO (out) == REGNO (XEXP (in, 1)))
7439 tem = op0, op0 = op1, op1 = tem;
7441 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7442 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7444 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7445 code = recog_memoized (insn);
7449 extract_insn (insn);
7450 /* We want constrain operands to treat this insn strictly in
7451 its validity determination, i.e., the way it would after reload
7453 if (constrain_operands (1))
7457 delete_insns_since (last);
7459 /* If that failed, we must use a conservative two-insn sequence.
7461 Use a move to copy one operand into the reload register. Prefer
7462 to reload a constant, MEM or pseudo since the move patterns can
7463 handle an arbitrary operand. If OP1 is not a constant, MEM or
7464 pseudo and OP1 is not a valid operand for an add instruction, then
7467 After reloading one of the operands into the reload register, add
7468 the reload register to the output register.
7470 If there is another way to do this for a specific machine, a
7471 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7474 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7476 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7477 || (GET_CODE (op1) == REG
7478 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7479 || (code != CODE_FOR_nothing
7480 && ! ((*insn_data[code].operand[2].predicate)
7481 (op1, insn_data[code].operand[2].mode))))
7482 tem = op0, op0 = op1, op1 = tem;
7484 gen_reload (out, op0, opnum, type);
7486 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7487 This fixes a problem on the 32K where the stack pointer cannot
7488 be used as an operand of an add insn. */
7490 if (rtx_equal_p (op0, op1))
7493 insn = emit_insn (gen_add2_insn (out, op1));
7495 /* If that failed, copy the address register to the reload register.
7496 Then add the constant to the reload register. */
7498 code = recog_memoized (insn);
7502 extract_insn (insn);
7503 /* We want constrain operands to treat this insn strictly in
7504 its validity determination, i.e., the way it would after reload
7506 if (constrain_operands (1))
7508 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7510 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7515 delete_insns_since (last);
7517 gen_reload (out, op1, opnum, type);
7518 insn = emit_insn (gen_add2_insn (out, op0));
7519 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7522 #ifdef SECONDARY_MEMORY_NEEDED
7523 /* If we need a memory location to do the move, do it that way. */
7524 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7525 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7526 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7527 REGNO_REG_CLASS (REGNO (out)),
7530 /* Get the memory to use and rewrite both registers to its mode. */
7531 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7533 if (GET_MODE (loc) != GET_MODE (out))
7534 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7536 if (GET_MODE (loc) != GET_MODE (in))
7537 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7539 gen_reload (loc, in, opnum, type);
7540 gen_reload (out, loc, opnum, type);
7544 /* If IN is a simple operand, use gen_move_insn. */
7545 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7546 emit_insn (gen_move_insn (out, in));
7548 #ifdef HAVE_reload_load_address
7549 else if (HAVE_reload_load_address)
7550 emit_insn (gen_reload_load_address (out, in));
7553 /* Otherwise, just write (set OUT IN) and hope for the best. */
7555 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7557 /* Return the first insn emitted.
7558 We can not just return get_last_insn, because there may have
7559 been multiple instructions emitted. Also note that gen_move_insn may
7560 emit more than one insn itself, so we can not assume that there is one
7561 insn emitted per emit_insn_before call. */
7563 return last ? NEXT_INSN (last) : get_insns ();
7566 /* Delete a previously made output-reload whose result we now believe
7567 is not needed. First we double-check.
7569 INSN is the insn now being processed.
7570 LAST_RELOAD_REG is the hard register number for which we want to delete
7571 the last output reload.
7572 J is the reload-number that originally used REG. The caller has made
7573 certain that reload J doesn't use REG any longer for input. */
7576 delete_output_reload (insn, j, last_reload_reg)
7579 int last_reload_reg;
7581 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7582 rtx reg = spill_reg_stored_to[last_reload_reg];
7585 int n_inherited = 0;
7589 /* Get the raw pseudo-register referred to. */
7591 while (GET_CODE (reg) == SUBREG)
7592 reg = SUBREG_REG (reg);
7593 substed = reg_equiv_memory_loc[REGNO (reg)];
7595 /* This is unsafe if the operand occurs more often in the current
7596 insn than it is inherited. */
7597 for (k = n_reloads - 1; k >= 0; k--)
7599 rtx reg2 = rld[k].in;
7602 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7603 reg2 = rld[k].in_reg;
7605 if (rld[k].out && ! rld[k].out_reg)
7606 reg2 = XEXP (rld[k].in_reg, 0);
7608 while (GET_CODE (reg2) == SUBREG)
7609 reg2 = SUBREG_REG (reg2);
7610 if (rtx_equal_p (reg2, reg))
7612 if (reload_inherited[k] || reload_override_in[k] || k == j)
7615 reg2 = rld[k].out_reg;
7618 while (GET_CODE (reg2) == SUBREG)
7619 reg2 = XEXP (reg2, 0);
7620 if (rtx_equal_p (reg2, reg))
7627 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7629 n_occurrences += count_occurrences (PATTERN (insn),
7630 eliminate_regs (substed, 0,
7632 if (n_occurrences > n_inherited)
7635 /* If the pseudo-reg we are reloading is no longer referenced
7636 anywhere between the store into it and here,
7637 and no jumps or labels intervene, then the value can get
7638 here through the reload reg alone.
7639 Otherwise, give up--return. */
7640 for (i1 = NEXT_INSN (output_reload_insn);
7641 i1 != insn; i1 = NEXT_INSN (i1))
7643 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7645 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7646 && reg_mentioned_p (reg, PATTERN (i1)))
7648 /* If this is USE in front of INSN, we only have to check that
7649 there are no more references than accounted for by inheritance. */
7650 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7652 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7653 i1 = NEXT_INSN (i1);
7655 if (n_occurrences <= n_inherited && i1 == insn)
7661 /* We will be deleting the insn. Remove the spill reg information. */
7662 for (k = HARD_REGNO_NREGS (last_reload_reg, GET_MODE (reg)); k-- > 0; )
7664 spill_reg_store[last_reload_reg + k] = 0;
7665 spill_reg_stored_to[last_reload_reg + k] = 0;
7668 /* The caller has already checked that REG dies or is set in INSN.
7669 It has also checked that we are optimizing, and thus some
7670 inaccurancies in the debugging information are acceptable.
7671 So we could just delete output_reload_insn. But in some cases
7672 we can improve the debugging information without sacrificing
7673 optimization - maybe even improving the code: See if the pseudo
7674 reg has been completely replaced with reload regs. If so, delete
7675 the store insn and forget we had a stack slot for the pseudo. */
7676 if (rld[j].out != rld[j].in
7677 && REG_N_DEATHS (REGNO (reg)) == 1
7678 && REG_N_SETS (REGNO (reg)) == 1
7679 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7680 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7684 /* We know that it was used only between here and the beginning of
7685 the current basic block. (We also know that the last use before
7686 INSN was the output reload we are thinking of deleting, but never
7687 mind that.) Search that range; see if any ref remains. */
7688 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7690 rtx set = single_set (i2);
7692 /* Uses which just store in the pseudo don't count,
7693 since if they are the only uses, they are dead. */
7694 if (set != 0 && SET_DEST (set) == reg)
7696 if (GET_CODE (i2) == CODE_LABEL
7697 || GET_CODE (i2) == JUMP_INSN)
7699 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7700 && reg_mentioned_p (reg, PATTERN (i2)))
7702 /* Some other ref remains; just delete the output reload we
7704 delete_address_reloads (output_reload_insn, insn);
7705 delete_insn (output_reload_insn);
7710 /* Delete the now-dead stores into this pseudo. Note that this
7711 loop also takes care of deleting output_reload_insn. */
7712 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7714 rtx set = single_set (i2);
7716 if (set != 0 && SET_DEST (set) == reg)
7718 delete_address_reloads (i2, insn);
7721 if (GET_CODE (i2) == CODE_LABEL
7722 || GET_CODE (i2) == JUMP_INSN)
7726 /* For the debugging info, say the pseudo lives in this reload reg. */
7727 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7728 alter_reg (REGNO (reg), -1);
7732 delete_address_reloads (output_reload_insn, insn);
7733 delete_insn (output_reload_insn);
7737 /* We are going to delete DEAD_INSN. Recursively delete loads of
7738 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7739 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7741 delete_address_reloads (dead_insn, current_insn)
7742 rtx dead_insn, current_insn;
7744 rtx set = single_set (dead_insn);
7745 rtx set2, dst, prev, next;
7748 rtx dst = SET_DEST (set);
7749 if (GET_CODE (dst) == MEM)
7750 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7752 /* If we deleted the store from a reloaded post_{in,de}c expression,
7753 we can delete the matching adds. */
7754 prev = PREV_INSN (dead_insn);
7755 next = NEXT_INSN (dead_insn);
7756 if (! prev || ! next)
7758 set = single_set (next);
7759 set2 = single_set (prev);
7761 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7762 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7763 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7765 dst = SET_DEST (set);
7766 if (! rtx_equal_p (dst, SET_DEST (set2))
7767 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7768 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7769 || (INTVAL (XEXP (SET_SRC (set), 1))
7770 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7772 delete_related_insns (prev);
7773 delete_related_insns (next);
7776 /* Subfunction of delete_address_reloads: process registers found in X. */
7778 delete_address_reloads_1 (dead_insn, x, current_insn)
7779 rtx dead_insn, x, current_insn;
7781 rtx prev, set, dst, i2;
7783 enum rtx_code code = GET_CODE (x);
7787 const char *fmt = GET_RTX_FORMAT (code);
7788 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7791 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7792 else if (fmt[i] == 'E')
7794 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7795 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7802 if (spill_reg_order[REGNO (x)] < 0)
7805 /* Scan backwards for the insn that sets x. This might be a way back due
7807 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7809 code = GET_CODE (prev);
7810 if (code == CODE_LABEL || code == JUMP_INSN)
7812 if (GET_RTX_CLASS (code) != 'i')
7814 if (reg_set_p (x, PATTERN (prev)))
7816 if (reg_referenced_p (x, PATTERN (prev)))
7819 if (! prev || INSN_UID (prev) < reload_first_uid)
7821 /* Check that PREV only sets the reload register. */
7822 set = single_set (prev);
7825 dst = SET_DEST (set);
7826 if (GET_CODE (dst) != REG
7827 || ! rtx_equal_p (dst, x))
7829 if (! reg_set_p (dst, PATTERN (dead_insn)))
7831 /* Check if DST was used in a later insn -
7832 it might have been inherited. */
7833 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7835 if (GET_CODE (i2) == CODE_LABEL)
7839 if (reg_referenced_p (dst, PATTERN (i2)))
7841 /* If there is a reference to the register in the current insn,
7842 it might be loaded in a non-inherited reload. If no other
7843 reload uses it, that means the register is set before
7845 if (i2 == current_insn)
7847 for (j = n_reloads - 1; j >= 0; j--)
7848 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7849 || reload_override_in[j] == dst)
7851 for (j = n_reloads - 1; j >= 0; j--)
7852 if (rld[j].in && rld[j].reg_rtx == dst)
7859 if (GET_CODE (i2) == JUMP_INSN)
7861 /* If DST is still live at CURRENT_INSN, check if it is used for
7862 any reload. Note that even if CURRENT_INSN sets DST, we still
7863 have to check the reloads. */
7864 if (i2 == current_insn)
7866 for (j = n_reloads - 1; j >= 0; j--)
7867 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7868 || reload_override_in[j] == dst)
7870 /* ??? We can't finish the loop here, because dst might be
7871 allocated to a pseudo in this block if no reload in this
7872 block needs any of the clsses containing DST - see
7873 spill_hard_reg. There is no easy way to tell this, so we
7874 have to scan till the end of the basic block. */
7876 if (reg_set_p (dst, PATTERN (i2)))
7880 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7881 reg_reloaded_contents[REGNO (dst)] = -1;
7885 /* Output reload-insns to reload VALUE into RELOADREG.
7886 VALUE is an autoincrement or autodecrement RTX whose operand
7887 is a register or memory location;
7888 so reloading involves incrementing that location.
7889 IN is either identical to VALUE, or some cheaper place to reload from.
7891 INC_AMOUNT is the number to increment or decrement by (always positive).
7892 This cannot be deduced from VALUE.
7894 Return the instruction that stores into RELOADREG. */
7897 inc_for_reload (reloadreg, in, value, inc_amount)
7902 /* REG or MEM to be copied and incremented. */
7903 rtx incloc = XEXP (value, 0);
7904 /* Nonzero if increment after copying. */
7905 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7911 rtx real_in = in == value ? XEXP (in, 0) : in;
7913 /* No hard register is equivalent to this register after
7914 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7915 we could inc/dec that register as well (maybe even using it for
7916 the source), but I'm not sure it's worth worrying about. */
7917 if (GET_CODE (incloc) == REG)
7918 reg_last_reload_reg[REGNO (incloc)] = 0;
7920 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7921 inc_amount = -inc_amount;
7923 inc = GEN_INT (inc_amount);
7925 /* If this is post-increment, first copy the location to the reload reg. */
7926 if (post && real_in != reloadreg)
7927 emit_insn (gen_move_insn (reloadreg, real_in));
7931 /* See if we can directly increment INCLOC. Use a method similar to
7932 that in gen_reload. */
7934 last = get_last_insn ();
7935 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7936 gen_rtx_PLUS (GET_MODE (incloc),
7939 code = recog_memoized (add_insn);
7942 extract_insn (add_insn);
7943 if (constrain_operands (1))
7945 /* If this is a pre-increment and we have incremented the value
7946 where it lives, copy the incremented value to RELOADREG to
7947 be used as an address. */
7950 emit_insn (gen_move_insn (reloadreg, incloc));
7955 delete_insns_since (last);
7958 /* If couldn't do the increment directly, must increment in RELOADREG.
7959 The way we do this depends on whether this is pre- or post-increment.
7960 For pre-increment, copy INCLOC to the reload register, increment it
7961 there, then save back. */
7965 if (in != reloadreg)
7966 emit_insn (gen_move_insn (reloadreg, real_in));
7967 emit_insn (gen_add2_insn (reloadreg, inc));
7968 store = emit_insn (gen_move_insn (incloc, reloadreg));
7973 Because this might be a jump insn or a compare, and because RELOADREG
7974 may not be available after the insn in an input reload, we must do
7975 the incrementation before the insn being reloaded for.
7977 We have already copied IN to RELOADREG. Increment the copy in
7978 RELOADREG, save that back, then decrement RELOADREG so it has
7979 the original value. */
7981 emit_insn (gen_add2_insn (reloadreg, inc));
7982 store = emit_insn (gen_move_insn (incloc, reloadreg));
7983 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7990 /* See whether a single set SET is a noop. */
7992 reload_cse_noop_set_p (set)
7995 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
7998 /* Try to simplify INSN. */
8000 reload_cse_simplify (insn, testreg)
8004 rtx body = PATTERN (insn);
8006 if (GET_CODE (body) == SET)
8010 /* Simplify even if we may think it is a no-op.
8011 We may think a memory load of a value smaller than WORD_SIZE
8012 is redundant because we haven't taken into account possible
8013 implicit extension. reload_cse_simplify_set() will bring
8014 this out, so it's safer to simplify before we delete. */
8015 count += reload_cse_simplify_set (body, insn);
8017 if (!count && reload_cse_noop_set_p (body))
8019 rtx value = SET_DEST (body);
8021 && ! REG_FUNCTION_VALUE_P (value))
8023 delete_insn_and_edges (insn);
8028 apply_change_group ();
8030 reload_cse_simplify_operands (insn, testreg);
8032 else if (GET_CODE (body) == PARALLEL)
8036 rtx value = NULL_RTX;
8038 /* If every action in a PARALLEL is a noop, we can delete
8039 the entire PARALLEL. */
8040 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8042 rtx part = XVECEXP (body, 0, i);
8043 if (GET_CODE (part) == SET)
8045 if (! reload_cse_noop_set_p (part))
8047 if (REG_P (SET_DEST (part))
8048 && REG_FUNCTION_VALUE_P (SET_DEST (part)))
8052 value = SET_DEST (part);
8055 else if (GET_CODE (part) != CLOBBER)
8061 delete_insn_and_edges (insn);
8062 /* We're done with this insn. */
8066 /* It's not a no-op, but we can try to simplify it. */
8067 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8068 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8069 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8072 apply_change_group ();
8074 reload_cse_simplify_operands (insn, testreg);
8078 /* Do a very simple CSE pass over the hard registers.
8080 This function detects no-op moves where we happened to assign two
8081 different pseudo-registers to the same hard register, and then
8082 copied one to the other. Reload will generate a useless
8083 instruction copying a register to itself.
8085 This function also detects cases where we load a value from memory
8086 into two different registers, and (if memory is more expensive than
8087 registers) changes it to simply copy the first register into the
8090 Another optimization is performed that scans the operands of each
8091 instruction to see whether the value is already available in a
8092 hard register. It then replaces the operand with the hard register
8093 if possible, much like an optional reload would. */
8096 reload_cse_regs_1 (first)
8100 rtx testreg = gen_rtx_REG (VOIDmode, -1);
8103 init_alias_analysis ();
8105 for (insn = first; insn; insn = NEXT_INSN (insn))
8108 reload_cse_simplify (insn, testreg);
8110 cselib_process_insn (insn);
8114 end_alias_analysis ();
8118 /* Call cse / combine like post-reload optimization phases.
8119 FIRST is the first instruction. */
8121 reload_cse_regs (first)
8124 reload_cse_regs_1 (first);
8126 reload_cse_move2add (first);
8127 if (flag_expensive_optimizations)
8128 reload_cse_regs_1 (first);
8131 /* Try to simplify a single SET instruction. SET is the set pattern.
8132 INSN is the instruction it came from.
8133 This function only handles one case: if we set a register to a value
8134 which is not a register, we try to find that value in some other register
8135 and change the set into a register copy. */
8138 reload_cse_simplify_set (set, insn)
8145 enum reg_class dclass;
8148 struct elt_loc_list *l;
8149 #ifdef LOAD_EXTEND_OP
8150 enum rtx_code extend_op = NIL;
8153 dreg = true_regnum (SET_DEST (set));
8157 src = SET_SRC (set);
8158 if (side_effects_p (src) || true_regnum (src) >= 0)
8161 dclass = REGNO_REG_CLASS (dreg);
8163 #ifdef LOAD_EXTEND_OP
8164 /* When replacing a memory with a register, we need to honor assumptions
8165 that combine made wrt the contents of sign bits. We'll do this by
8166 generating an extend instruction instead of a reg->reg copy. Thus
8167 the destination must be a register that we can widen. */
8168 if (GET_CODE (src) == MEM
8169 && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD
8170 && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != NIL
8171 && GET_CODE (SET_DEST (set)) != REG)
8175 /* If memory loads are cheaper than register copies, don't change them. */
8176 if (GET_CODE (src) == MEM)
8177 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8178 else if (CONSTANT_P (src))
8179 old_cost = rtx_cost (src, SET);
8180 else if (GET_CODE (src) == REG)
8181 old_cost = REGISTER_MOVE_COST (GET_MODE (src),
8182 REGNO_REG_CLASS (REGNO (src)), dclass);
8185 old_cost = rtx_cost (src, SET);
8187 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0);
8190 for (l = val->locs; l; l = l->next)
8192 rtx this_rtx = l->loc;
8195 if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
8197 #ifdef LOAD_EXTEND_OP
8198 if (extend_op != NIL)
8200 HOST_WIDE_INT this_val;
8202 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
8203 constants, such as SYMBOL_REF, cannot be extended. */
8204 if (GET_CODE (this_rtx) != CONST_INT)
8207 this_val = INTVAL (this_rtx);
8211 this_val &= GET_MODE_MASK (GET_MODE (src));
8214 /* ??? In theory we're already extended. */
8215 if (this_val == trunc_int_for_mode (this_val, GET_MODE (src)))
8220 this_rtx = GEN_INT (this_val);
8223 this_cost = rtx_cost (this_rtx, SET);
8225 else if (GET_CODE (this_rtx) == REG)
8227 #ifdef LOAD_EXTEND_OP
8228 if (extend_op != NIL)
8230 this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
8231 this_cost = rtx_cost (this_rtx, SET);
8235 this_cost = REGISTER_MOVE_COST (GET_MODE (this_rtx),
8236 REGNO_REG_CLASS (REGNO (this_rtx)),
8242 /* If equal costs, prefer registers over anything else. That
8243 tends to lead to smaller instructions on some machines. */
8244 if (this_cost < old_cost
8245 || (this_cost == old_cost
8246 && GET_CODE (this_rtx) == REG
8247 && GET_CODE (SET_SRC (set)) != REG))
8249 #ifdef LOAD_EXTEND_OP
8250 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD
8251 && extend_op != NIL)
8253 rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set)));
8254 ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
8255 validate_change (insn, &SET_DEST (set), wide_dest, 1);
8259 validate_change (insn, &SET_SRC (set), copy_rtx (this_rtx), 1);
8260 old_cost = this_cost, did_change = 1;
8267 /* Try to replace operands in INSN with equivalent values that are already
8268 in registers. This can be viewed as optional reloading.
8270 For each non-register operand in the insn, see if any hard regs are
8271 known to be equivalent to that operand. Record the alternatives which
8272 can accept these hard registers. Among all alternatives, select the
8273 ones which are better or equal to the one currently matching, where
8274 "better" is in terms of '?' and '!' constraints. Among the remaining
8275 alternatives, select the one which replaces most operands with
8279 reload_cse_simplify_operands (insn, testreg)
8285 /* For each operand, all registers that are equivalent to it. */
8286 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8288 const char *constraints[MAX_RECOG_OPERANDS];
8290 /* Vector recording how bad an alternative is. */
8291 int *alternative_reject;
8292 /* Vector recording how many registers can be introduced by choosing
8293 this alternative. */
8294 int *alternative_nregs;
8295 /* Array of vectors recording, for each operand and each alternative,
8296 which hard register to substitute, or -1 if the operand should be
8298 int *op_alt_regno[MAX_RECOG_OPERANDS];
8299 /* Array of alternatives, sorted in order of decreasing desirability. */
8300 int *alternative_order;
8302 extract_insn (insn);
8304 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8307 /* Figure out which alternative currently matches. */
8308 if (! constrain_operands (1))
8309 fatal_insn_not_found (insn);
8311 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8312 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8313 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8314 memset ((char *) alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
8315 memset ((char *) alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
8317 /* For each operand, find out which regs are equivalent. */
8318 for (i = 0; i < recog_data.n_operands; i++)
8321 struct elt_loc_list *l;
8323 CLEAR_HARD_REG_SET (equiv_regs[i]);
8325 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8326 right, so avoid the problem here. Likewise if we have a constant
8327 and the insn pattern doesn't tell us the mode we need. */
8328 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL
8329 || (CONSTANT_P (recog_data.operand[i])
8330 && recog_data.operand_mode[i] == VOIDmode))
8333 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8337 for (l = v->locs; l; l = l->next)
8338 if (GET_CODE (l->loc) == REG)
8339 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8342 for (i = 0; i < recog_data.n_operands; i++)
8344 enum machine_mode mode;
8348 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8349 for (j = 0; j < recog_data.n_alternatives; j++)
8350 op_alt_regno[i][j] = -1;
8352 p = constraints[i] = recog_data.constraints[i];
8353 mode = recog_data.operand_mode[i];
8355 /* Add the reject values for each alternative given by the constraints
8356 for this operand. */
8364 alternative_reject[j] += 3;
8366 alternative_reject[j] += 300;
8369 /* We won't change operands which are already registers. We
8370 also don't want to modify output operands. */
8371 regno = true_regnum (recog_data.operand[i]);
8373 || constraints[i][0] == '='
8374 || constraints[i][0] == '+')
8377 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8379 int class = (int) NO_REGS;
8381 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8384 REGNO (testreg) = regno;
8385 PUT_MODE (testreg, mode);
8387 /* We found a register equal to this operand. Now look for all
8388 alternatives that can accept this register and have not been
8389 assigned a register they can use yet. */
8398 case '=': case '+': case '?':
8399 case '#': case '&': case '!':
8401 case '0': case '1': case '2': case '3': case '4':
8402 case '5': case '6': case '7': case '8': case '9':
8403 case 'm': case '<': case '>': case 'V': case 'o':
8404 case 'E': case 'F': case 'G': case 'H':
8405 case 's': case 'i': case 'n':
8406 case 'I': case 'J': case 'K': case 'L':
8407 case 'M': case 'N': case 'O': case 'P':
8409 /* These don't say anything we care about. */
8413 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8418 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char) c)];
8421 case ',': case '\0':
8422 /* See if REGNO fits this alternative, and set it up as the
8423 replacement register if we don't have one for this
8424 alternative yet and the operand being replaced is not
8425 a cheap CONST_INT. */
8426 if (op_alt_regno[i][j] == -1
8427 && reg_fits_class_p (testreg, class, 0, mode)
8428 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8429 || (rtx_cost (recog_data.operand[i], SET)
8430 > rtx_cost (testreg, SET))))
8432 alternative_nregs[j]++;
8433 op_alt_regno[i][j] = regno;
8445 /* Record all alternatives which are better or equal to the currently
8446 matching one in the alternative_order array. */
8447 for (i = j = 0; i < recog_data.n_alternatives; i++)
8448 if (alternative_reject[i] <= alternative_reject[which_alternative])
8449 alternative_order[j++] = i;
8450 recog_data.n_alternatives = j;
8452 /* Sort it. Given a small number of alternatives, a dumb algorithm
8453 won't hurt too much. */
8454 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8457 int best_reject = alternative_reject[alternative_order[i]];
8458 int best_nregs = alternative_nregs[alternative_order[i]];
8461 for (j = i + 1; j < recog_data.n_alternatives; j++)
8463 int this_reject = alternative_reject[alternative_order[j]];
8464 int this_nregs = alternative_nregs[alternative_order[j]];
8466 if (this_reject < best_reject
8467 || (this_reject == best_reject && this_nregs < best_nregs))
8470 best_reject = this_reject;
8471 best_nregs = this_nregs;
8475 tmp = alternative_order[best];
8476 alternative_order[best] = alternative_order[i];
8477 alternative_order[i] = tmp;
8480 /* Substitute the operands as determined by op_alt_regno for the best
8482 j = alternative_order[0];
8484 for (i = 0; i < recog_data.n_operands; i++)
8486 enum machine_mode mode = recog_data.operand_mode[i];
8487 if (op_alt_regno[i][j] == -1)
8490 validate_change (insn, recog_data.operand_loc[i],
8491 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8494 for (i = recog_data.n_dups - 1; i >= 0; i--)
8496 int op = recog_data.dup_num[i];
8497 enum machine_mode mode = recog_data.operand_mode[op];
8499 if (op_alt_regno[op][j] == -1)
8502 validate_change (insn, recog_data.dup_loc[i],
8503 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8506 return apply_change_group ();
8509 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8511 This code might also be useful when reload gave up on reg+reg addresssing
8512 because of clashes between the return register and INDEX_REG_CLASS. */
8514 /* The maximum number of uses of a register we can keep track of to
8515 replace them with reg+reg addressing. */
8516 #define RELOAD_COMBINE_MAX_USES 6
8518 /* INSN is the insn where a register has ben used, and USEP points to the
8519 location of the register within the rtl. */
8520 struct reg_use { rtx insn, *usep; };
8522 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8523 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8524 indicates where it becomes live again.
8525 Otherwise, USE_INDEX is the index of the last encountered use of the
8526 register (which is first among these we have seen since we scan backwards),
8527 OFFSET contains the constant offset that is added to the register in
8528 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8529 last, of these uses.
8530 STORE_RUID is always meaningful if we only want to use a value in a
8531 register in a different place: it denotes the next insn in the insn
8532 stream (i.e. the last ecountered) that sets or clobbers the register. */
8535 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8540 } reg_state[FIRST_PSEUDO_REGISTER];
8542 /* Reverse linear uid. This is increased in reload_combine while scanning
8543 the instructions from last to first. It is used to set last_label_ruid
8544 and the store_ruid / use_ruid fields in reg_state. */
8545 static int reload_combine_ruid;
8547 #define LABEL_LIVE(LABEL) \
8548 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8554 int first_index_reg = -1;
8555 int last_index_reg = 0;
8559 int last_label_ruid;
8560 int min_labelno, n_labels;
8561 HARD_REG_SET ever_live_at_start, *label_live;
8563 /* If reg+reg can be used in offsetable memory addresses, the main chunk of
8564 reload has already used it where appropriate, so there is no use in
8565 trying to generate it now. */
8566 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8569 /* To avoid wasting too much time later searching for an index register,
8570 determine the minimum and maximum index register numbers. */
8571 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8572 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
8574 if (first_index_reg == -1)
8575 first_index_reg = r;
8580 /* If no index register is available, we can quit now. */
8581 if (first_index_reg == -1)
8584 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8585 information is a bit fuzzy immediately after reload, but it's
8586 still good enough to determine which registers are live at a jump
8588 min_labelno = get_first_label_num ();
8589 n_labels = max_label_num () - min_labelno;
8590 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8591 CLEAR_HARD_REG_SET (ever_live_at_start);
8593 FOR_EACH_BB_REVERSE (bb)
8596 if (GET_CODE (insn) == CODE_LABEL)
8600 REG_SET_TO_HARD_REG_SET (live,
8601 bb->global_live_at_start);
8602 compute_use_by_pseudos (&live,
8603 bb->global_live_at_start);
8604 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8605 IOR_HARD_REG_SET (ever_live_at_start, live);
8609 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8610 last_label_ruid = reload_combine_ruid = 0;
8611 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8613 reg_state[r].store_ruid = reload_combine_ruid;
8615 reg_state[r].use_index = -1;
8617 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8620 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8624 /* We cannot do our optimization across labels. Invalidating all the use
8625 information we have would be costly, so we just note where the label
8626 is and then later disable any optimization that would cross it. */
8627 if (GET_CODE (insn) == CODE_LABEL)
8628 last_label_ruid = reload_combine_ruid;
8629 else if (GET_CODE (insn) == BARRIER)
8630 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8631 if (! fixed_regs[r])
8632 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8634 if (! INSN_P (insn))
8637 reload_combine_ruid++;
8639 /* Look for (set (REGX) (CONST_INT))
8640 (set (REGX) (PLUS (REGX) (REGY)))
8642 ... (MEM (REGX)) ...
8644 (set (REGZ) (CONST_INT))
8646 ... (MEM (PLUS (REGZ) (REGY)))... .
8648 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8649 and that we know all uses of REGX before it dies. */
8650 set = single_set (insn);
8652 && GET_CODE (SET_DEST (set)) == REG
8653 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8654 GET_MODE (SET_DEST (set)))
8656 && GET_CODE (SET_SRC (set)) == PLUS
8657 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8658 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8659 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8661 rtx reg = SET_DEST (set);
8662 rtx plus = SET_SRC (set);
8663 rtx base = XEXP (plus, 1);
8664 rtx prev = prev_nonnote_insn (insn);
8665 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8666 unsigned int regno = REGNO (reg);
8667 rtx const_reg = NULL_RTX;
8668 rtx reg_sum = NULL_RTX;
8670 /* Now, we need an index register.
8671 We'll set index_reg to this index register, const_reg to the
8672 register that is to be loaded with the constant
8673 (denoted as REGZ in the substitution illustration above),
8674 and reg_sum to the register-register that we want to use to
8675 substitute uses of REG (typically in MEMs) with.
8676 First check REG and BASE for being index registers;
8677 we can use them even if they are not dead. */
8678 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8679 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8687 /* Otherwise, look for a free index register. Since we have
8688 checked above that neiter REG nor BASE are index registers,
8689 if we find anything at all, it will be different from these
8691 for (i = first_index_reg; i <= last_index_reg; i++)
8693 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8695 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8696 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8697 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8699 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8701 const_reg = index_reg;
8702 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8708 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8709 (REGY), i.e. BASE, is not clobbered before the last use we'll
8712 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8713 && rtx_equal_p (SET_DEST (prev_set), reg)
8714 && reg_state[regno].use_index >= 0
8715 && (reg_state[REGNO (base)].store_ruid
8716 <= reg_state[regno].use_ruid)
8721 /* Change destination register and, if necessary, the
8722 constant value in PREV, the constant loading instruction. */
8723 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8724 if (reg_state[regno].offset != const0_rtx)
8725 validate_change (prev,
8726 &SET_SRC (prev_set),
8727 GEN_INT (INTVAL (SET_SRC (prev_set))
8728 + INTVAL (reg_state[regno].offset)),
8731 /* Now for every use of REG that we have recorded, replace REG
8733 for (i = reg_state[regno].use_index;
8734 i < RELOAD_COMBINE_MAX_USES; i++)
8735 validate_change (reg_state[regno].reg_use[i].insn,
8736 reg_state[regno].reg_use[i].usep,
8737 /* Each change must have its own
8739 copy_rtx (reg_sum), 1);
8741 if (apply_change_group ())
8745 /* Delete the reg-reg addition. */
8748 if (reg_state[regno].offset != const0_rtx)
8749 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8751 for (np = ®_NOTES (prev); *np;)
8753 if (REG_NOTE_KIND (*np) == REG_EQUAL
8754 || REG_NOTE_KIND (*np) == REG_EQUIV)
8755 *np = XEXP (*np, 1);
8757 np = &XEXP (*np, 1);
8760 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8761 reg_state[REGNO (const_reg)].store_ruid
8762 = reload_combine_ruid;
8768 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8770 if (GET_CODE (insn) == CALL_INSN)
8774 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8775 if (call_used_regs[r])
8777 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8778 reg_state[r].store_ruid = reload_combine_ruid;
8781 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8782 link = XEXP (link, 1))
8784 rtx usage_rtx = XEXP (XEXP (link, 0), 0);
8785 if (GET_CODE (usage_rtx) == REG)
8788 unsigned int start_reg = REGNO (usage_rtx);
8789 unsigned int num_regs =
8790 HARD_REGNO_NREGS (start_reg, GET_MODE (usage_rtx));
8791 unsigned int end_reg = start_reg + num_regs - 1;
8792 for (i = start_reg; i <= end_reg; i++)
8793 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
8795 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8796 reg_state[i].store_ruid = reload_combine_ruid;
8799 reg_state[i].use_index = -1;
8804 else if (GET_CODE (insn) == JUMP_INSN
8805 && GET_CODE (PATTERN (insn)) != RETURN)
8807 /* Non-spill registers might be used at the call destination in
8808 some unknown fashion, so we have to mark the unknown use. */
8811 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8812 && JUMP_LABEL (insn))
8813 live = &LABEL_LIVE (JUMP_LABEL (insn));
8815 live = &ever_live_at_start;
8817 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8818 if (TEST_HARD_REG_BIT (*live, i))
8819 reg_state[i].use_index = -1;
8822 reload_combine_note_use (&PATTERN (insn), insn);
8823 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8825 if (REG_NOTE_KIND (note) == REG_INC
8826 && GET_CODE (XEXP (note, 0)) == REG)
8828 int regno = REGNO (XEXP (note, 0));
8830 reg_state[regno].store_ruid = reload_combine_ruid;
8831 reg_state[regno].use_index = -1;
8839 /* Check if DST is a register or a subreg of a register; if it is,
8840 update reg_state[regno].store_ruid and reg_state[regno].use_index
8841 accordingly. Called via note_stores from reload_combine. */
8844 reload_combine_note_store (dst, set, data)
8846 void *data ATTRIBUTE_UNUSED;
8850 enum machine_mode mode = GET_MODE (dst);
8852 if (GET_CODE (dst) == SUBREG)
8854 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
8855 GET_MODE (SUBREG_REG (dst)),
8858 dst = SUBREG_REG (dst);
8860 if (GET_CODE (dst) != REG)
8862 regno += REGNO (dst);
8864 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8865 careful with registers / register parts that are not full words.
8867 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8868 if (GET_CODE (set) != SET
8869 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8870 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8871 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8873 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8875 reg_state[i].use_index = -1;
8876 reg_state[i].store_ruid = reload_combine_ruid;
8881 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8883 reg_state[i].store_ruid = reload_combine_ruid;
8884 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8889 /* XP points to a piece of rtl that has to be checked for any uses of
8891 *XP is the pattern of INSN, or a part of it.
8892 Called from reload_combine, and recursively by itself. */
8894 reload_combine_note_use (xp, insn)
8898 enum rtx_code code = x->code;
8901 rtx offset = const0_rtx; /* For the REG case below. */
8906 if (GET_CODE (SET_DEST (x)) == REG)
8908 reload_combine_note_use (&SET_SRC (x), insn);
8914 /* If this is the USE of a return value, we can't change it. */
8915 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8917 /* Mark the return register as used in an unknown fashion. */
8918 rtx reg = XEXP (x, 0);
8919 int regno = REGNO (reg);
8920 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8922 while (--nregs >= 0)
8923 reg_state[regno + nregs].use_index = -1;
8929 if (GET_CODE (SET_DEST (x)) == REG)
8931 /* No spurious CLOBBERs of pseudo registers may remain. */
8932 if (REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER)
8939 /* We are interested in (plus (reg) (const_int)) . */
8940 if (GET_CODE (XEXP (x, 0)) != REG
8941 || GET_CODE (XEXP (x, 1)) != CONST_INT)
8943 offset = XEXP (x, 1);
8948 int regno = REGNO (x);
8952 /* No spurious USEs of pseudo registers may remain. */
8953 if (regno >= FIRST_PSEUDO_REGISTER)
8956 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
8958 /* We can't substitute into multi-hard-reg uses. */
8961 while (--nregs >= 0)
8962 reg_state[regno + nregs].use_index = -1;
8966 /* If this register is already used in some unknown fashion, we
8968 If we decrement the index from zero to -1, we can't store more
8969 uses, so this register becomes used in an unknown fashion. */
8970 use_index = --reg_state[regno].use_index;
8974 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
8976 /* We have found another use for a register that is already
8977 used later. Check if the offsets match; if not, mark the
8978 register as used in an unknown fashion. */
8979 if (! rtx_equal_p (offset, reg_state[regno].offset))
8981 reg_state[regno].use_index = -1;
8987 /* This is the first use of this register we have seen since we
8988 marked it as dead. */
8989 reg_state[regno].offset = offset;
8990 reg_state[regno].use_ruid = reload_combine_ruid;
8992 reg_state[regno].reg_use[use_index].insn = insn;
8993 reg_state[regno].reg_use[use_index].usep = xp;
9001 /* Recursively process the components of X. */
9002 fmt = GET_RTX_FORMAT (code);
9003 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9006 reload_combine_note_use (&XEXP (x, i), insn);
9007 else if (fmt[i] == 'E')
9009 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9010 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9015 /* See if we can reduce the cost of a constant by replacing a move
9016 with an add. We track situations in which a register is set to a
9017 constant or to a register plus a constant. */
9018 /* We cannot do our optimization across labels. Invalidating all the
9019 information about register contents we have would be costly, so we
9020 use move2add_last_label_luid to note where the label is and then
9021 later disable any optimization that would cross it.
9022 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9023 reg_set_luid[n] is greater than last_label_luid[n] . */
9024 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9026 /* If reg_base_reg[n] is negative, register n has been set to
9027 reg_offset[n] in mode reg_mode[n] .
9028 If reg_base_reg[n] is non-negative, register n has been set to the
9029 sum of reg_offset[n] and the value of register reg_base_reg[n]
9030 before reg_set_luid[n], calculated in mode reg_mode[n] . */
9031 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
9032 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9033 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9035 /* move2add_luid is linearily increased while scanning the instructions
9036 from first to last. It is used to set reg_set_luid in
9037 reload_cse_move2add and move2add_note_store. */
9038 static int move2add_luid;
9040 /* move2add_last_label_luid is set whenever a label is found. Labels
9041 invalidate all previously collected reg_offset data. */
9042 static int move2add_last_label_luid;
9044 /* Generate a CONST_INT and force it in the range of MODE. */
9046 static HOST_WIDE_INT
9047 sext_for_mode (mode, value)
9048 enum machine_mode mode;
9049 HOST_WIDE_INT value;
9051 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
9052 int width = GET_MODE_BITSIZE (mode);
9054 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
9056 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
9057 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
9058 cval |= (HOST_WIDE_INT) -1 << width;
9063 /* ??? We don't know how zero / sign extension is handled, hence we
9064 can't go from a narrower to a wider mode. */
9065 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
9066 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
9067 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
9068 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
9069 GET_MODE_BITSIZE (INMODE))))
9072 reload_cse_move2add (first)
9078 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9079 reg_set_luid[i] = 0;
9081 move2add_last_label_luid = 0;
9083 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9087 if (GET_CODE (insn) == CODE_LABEL)
9089 move2add_last_label_luid = move2add_luid;
9090 /* We're going to increment move2add_luid twice after a
9091 label, so that we can use move2add_last_label_luid + 1 as
9092 the luid for constants. */
9096 if (! INSN_P (insn))
9098 pat = PATTERN (insn);
9099 /* For simplicity, we only perform this optimization on
9100 straightforward SETs. */
9101 if (GET_CODE (pat) == SET
9102 && GET_CODE (SET_DEST (pat)) == REG)
9104 rtx reg = SET_DEST (pat);
9105 int regno = REGNO (reg);
9106 rtx src = SET_SRC (pat);
9108 /* Check if we have valid information on the contents of this
9109 register in the mode of REG. */
9110 if (reg_set_luid[regno] > move2add_last_label_luid
9111 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno]))
9113 /* Try to transform (set (REGX) (CONST_INT A))
9115 (set (REGX) (CONST_INT B))
9117 (set (REGX) (CONST_INT A))
9119 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9121 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9124 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9126 - reg_offset[regno]));
9127 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9128 use (set (reg) (reg)) instead.
9129 We don't delete this insn, nor do we convert it into a
9130 note, to avoid losing register notes or the return
9131 value flag. jump2 already knowns how to get rid of
9133 if (new_src == const0_rtx)
9134 success = validate_change (insn, &SET_SRC (pat), reg, 0);
9135 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9136 && have_add2_insn (reg, new_src))
9137 success = validate_change (insn, &PATTERN (insn),
9138 gen_add2_insn (reg, new_src), 0);
9139 reg_set_luid[regno] = move2add_luid;
9140 reg_mode[regno] = GET_MODE (reg);
9141 reg_offset[regno] = INTVAL (src);
9145 /* Try to transform (set (REGX) (REGY))
9146 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9149 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9152 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9154 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9155 else if (GET_CODE (src) == REG
9156 && reg_set_luid[regno] == reg_set_luid[REGNO (src)]
9157 && reg_base_reg[regno] == reg_base_reg[REGNO (src)]
9158 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg),
9159 reg_mode[REGNO (src)]))
9161 rtx next = next_nonnote_insn (insn);
9164 set = single_set (next);
9166 && SET_DEST (set) == reg
9167 && GET_CODE (SET_SRC (set)) == PLUS
9168 && XEXP (SET_SRC (set), 0) == reg
9169 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9171 rtx src3 = XEXP (SET_SRC (set), 1);
9172 HOST_WIDE_INT added_offset = INTVAL (src3);
9173 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)];
9174 HOST_WIDE_INT regno_offset = reg_offset[regno];
9175 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9181 if (new_src == const0_rtx)
9182 /* See above why we create (set (reg) (reg)) here. */
9184 = validate_change (next, &SET_SRC (set), reg, 0);
9185 else if ((rtx_cost (new_src, PLUS)
9186 < COSTS_N_INSNS (1) + rtx_cost (src3, SET))
9187 && have_add2_insn (reg, new_src))
9189 = validate_change (next, &PATTERN (next),
9190 gen_add2_insn (reg, new_src), 0);
9194 reg_mode[regno] = GET_MODE (reg);
9195 reg_offset[regno] = sext_for_mode (GET_MODE (reg),
9204 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9206 if (REG_NOTE_KIND (note) == REG_INC
9207 && GET_CODE (XEXP (note, 0)) == REG)
9209 /* Reset the information about this register. */
9210 int regno = REGNO (XEXP (note, 0));
9211 if (regno < FIRST_PSEUDO_REGISTER)
9212 reg_set_luid[regno] = 0;
9215 note_stores (PATTERN (insn), move2add_note_store, NULL);
9216 /* If this is a CALL_INSN, all call used registers are stored with
9218 if (GET_CODE (insn) == CALL_INSN)
9220 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9222 if (call_used_regs[i])
9223 /* Reset the information about this register. */
9224 reg_set_luid[i] = 0;
9230 /* SET is a SET or CLOBBER that sets DST.
9231 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9232 Called from reload_cse_move2add via note_stores. */
9235 move2add_note_store (dst, set, data)
9237 void *data ATTRIBUTE_UNUSED;
9239 unsigned int regno = 0;
9241 enum machine_mode mode = GET_MODE (dst);
9243 if (GET_CODE (dst) == SUBREG)
9245 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
9246 GET_MODE (SUBREG_REG (dst)),
9249 dst = SUBREG_REG (dst);
9252 /* Some targets do argument pushes without adding REG_INC notes. */
9254 if (GET_CODE (dst) == MEM)
9256 dst = XEXP (dst, 0);
9257 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC
9258 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
9259 reg_set_luid[REGNO (XEXP (dst, 0))] = 0;
9262 if (GET_CODE (dst) != REG)
9265 regno += REGNO (dst);
9267 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9268 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9269 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9270 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9272 rtx src = SET_SRC (set);
9274 HOST_WIDE_INT offset;
9276 /* This may be different from mode, if SET_DEST (set) is a
9278 enum machine_mode dst_mode = GET_MODE (dst);
9280 switch (GET_CODE (src))
9283 if (GET_CODE (XEXP (src, 0)) == REG)
9285 base_reg = XEXP (src, 0);
9287 if (GET_CODE (XEXP (src, 1)) == CONST_INT)
9288 offset = INTVAL (XEXP (src, 1));
9289 else if (GET_CODE (XEXP (src, 1)) == REG
9290 && (reg_set_luid[REGNO (XEXP (src, 1))]
9291 > move2add_last_label_luid)
9292 && (MODES_OK_FOR_MOVE2ADD
9293 (dst_mode, reg_mode[REGNO (XEXP (src, 1))])))
9295 if (reg_base_reg[REGNO (XEXP (src, 1))] < 0)
9296 offset = reg_offset[REGNO (XEXP (src, 1))];
9297 /* Maybe the first register is known to be a
9299 else if (reg_set_luid[REGNO (base_reg)]
9300 > move2add_last_label_luid
9301 && (MODES_OK_FOR_MOVE2ADD
9302 (dst_mode, reg_mode[REGNO (XEXP (src, 1))]))
9303 && reg_base_reg[REGNO (base_reg)] < 0)
9305 offset = reg_offset[REGNO (base_reg)];
9306 base_reg = XEXP (src, 1);
9325 /* Start tracking the register as a constant. */
9326 reg_base_reg[regno] = -1;
9327 reg_offset[regno] = INTVAL (SET_SRC (set));
9328 /* We assign the same luid to all registers set to constants. */
9329 reg_set_luid[regno] = move2add_last_label_luid + 1;
9330 reg_mode[regno] = mode;
9335 /* Invalidate the contents of the register. */
9336 reg_set_luid[regno] = 0;
9340 base_regno = REGNO (base_reg);
9341 /* If information about the base register is not valid, set it
9342 up as a new base register, pretending its value is known
9343 starting from the current insn. */
9344 if (reg_set_luid[base_regno] <= move2add_last_label_luid)
9346 reg_base_reg[base_regno] = base_regno;
9347 reg_offset[base_regno] = 0;
9348 reg_set_luid[base_regno] = move2add_luid;
9349 reg_mode[base_regno] = mode;
9351 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode,
9352 reg_mode[base_regno]))
9355 reg_mode[regno] = mode;
9357 /* Copy base information from our base register. */
9358 reg_set_luid[regno] = reg_set_luid[base_regno];
9359 reg_base_reg[regno] = reg_base_reg[base_regno];
9361 /* Compute the sum of the offsets or constants. */
9362 reg_offset[regno] = sext_for_mode (dst_mode,
9364 + reg_offset[base_regno]);
9368 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9370 for (i = regno; i < endregno; i++)
9371 /* Reset the information about this register. */
9372 reg_set_luid[i] = 0;
9378 add_auto_inc_notes (insn, x)
9382 enum rtx_code code = GET_CODE (x);
9386 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9389 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9393 /* Scan all the operand sub-expressions. */
9394 fmt = GET_RTX_FORMAT (code);
9395 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9398 add_auto_inc_notes (insn, XEXP (x, i));
9399 else if (fmt[i] == 'E')
9400 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9401 add_auto_inc_notes (insn, XVECEXP (x, i, j));
9406 /* Copy EH notes from an insn to its reloads. */
9408 copy_eh_notes (insn, x)
9412 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
9415 for (; x != 0; x = NEXT_INSN (x))
9417 if (may_trap_p (PATTERN (x)))
9419 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
9425 /* This is used by reload pass, that does emit some instructions after
9426 abnormal calls moving basic block end, but in fact it wants to emit
9427 them on the edge. Looks for abnormal call edges, find backward the
9428 proper call and fix the damage.
9430 Similar handle instructions throwing exceptions internally. */
9432 fixup_abnormal_edges ()
9434 bool inserted = false;
9441 /* Look for cases we are interested in - an calls or instructions causing
9443 for (e = bb->succ; e; e = e->succ_next)
9445 if (e->flags & EDGE_ABNORMAL_CALL)
9447 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
9448 == (EDGE_ABNORMAL | EDGE_EH))
9451 if (e && GET_CODE (bb->end) != CALL_INSN && !can_throw_internal (bb->end))
9453 rtx insn = bb->end, stop = NEXT_INSN (bb->end);
9455 for (e = bb->succ; e; e = e->succ_next)
9456 if (e->flags & EDGE_FALLTHRU)
9458 /* Get past the new insns generated. Allow notes, as the insns may
9459 be already deleted. */
9460 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE)
9461 && !can_throw_internal (insn)
9462 && insn != bb->head)
9463 insn = PREV_INSN (insn);
9464 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn))
9468 insn = NEXT_INSN (insn);
9469 while (insn && insn != stop)
9471 next = NEXT_INSN (insn);
9476 /* Sometimes there's still the return value USE.
9477 If it's placed after a trapping call (i.e. that
9478 call is the last insn anyway), we have no fallthru
9479 edge. Simply delete this use and don't try to insert
9480 on the non-existant edge. */
9481 if (GET_CODE (PATTERN (insn)) != USE)
9483 /* We're not deleting it, we're moving it. */
9484 INSN_DELETED_P (insn) = 0;
9485 PREV_INSN (insn) = NULL_RTX;
9486 NEXT_INSN (insn) = NULL_RTX;
9488 insert_insn_on_edge (insn, e);
9496 commit_edge_insertions ();
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