1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
106 This is used when the address is not valid as a memory address
107 (because its displacement is too big for the machine.) */
108 rtx *reg_equiv_address;
110 /* Element N is the memory slot to which pseudo reg N is equivalent,
111 or zero if pseudo reg N is not equivalent to a memory slot. */
114 /* Widest width in which each pseudo reg is referred to (via subreg). */
115 static unsigned int *reg_max_ref_width;
117 /* Element N is the list of insns that initialized reg N from its equivalent
118 constant or memory slot. */
119 static rtx *reg_equiv_init;
121 /* Vector to remember old contents of reg_renumber before spilling. */
122 static short *reg_old_renumber;
124 /* During reload_as_needed, element N contains the last pseudo regno reloaded
125 into hard register N. If that pseudo reg occupied more than one register,
126 reg_reloaded_contents points to that pseudo for each spill register in
127 use; all of these must remain set for an inheritance to occur. */
128 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
130 /* During reload_as_needed, element N contains the insn for which
131 hard register N was last used. Its contents are significant only
132 when reg_reloaded_valid is set for this register. */
133 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
135 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
136 static HARD_REG_SET reg_reloaded_valid;
137 /* Indicate if the register was dead at the end of the reload.
138 This is only valid if reg_reloaded_contents is set and valid. */
139 static HARD_REG_SET reg_reloaded_dead;
141 /* Number of spill-regs so far; number of valid elements of spill_regs. */
144 /* In parallel with spill_regs, contains REG rtx's for those regs.
145 Holds the last rtx used for any given reg, or 0 if it has never
146 been used for spilling yet. This rtx is reused, provided it has
148 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
150 /* In parallel with spill_regs, contains nonzero for a spill reg
151 that was stored after the last time it was used.
152 The precise value is the insn generated to do the store. */
153 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
155 /* This is the register that was stored with spill_reg_store. This is a
156 copy of reload_out / reload_out_reg when the value was stored; if
157 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
158 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
160 /* This table is the inverse mapping of spill_regs:
161 indexed by hard reg number,
162 it contains the position of that reg in spill_regs,
163 or -1 for something that is not in spill_regs.
165 ?!? This is no longer accurate. */
166 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
168 /* This reg set indicates registers that can't be used as spill registers for
169 the currently processed insn. These are the hard registers which are live
170 during the insn, but not allocated to pseudos, as well as fixed
172 static HARD_REG_SET bad_spill_regs;
174 /* These are the hard registers that can't be used as spill register for any
175 insn. This includes registers used for user variables and registers that
176 we can't eliminate. A register that appears in this set also can't be used
177 to retry register allocation. */
178 static HARD_REG_SET bad_spill_regs_global;
180 /* Describes order of use of registers for reloading
181 of spilled pseudo-registers. `n_spills' is the number of
182 elements that are actually valid; new ones are added at the end.
184 Both spill_regs and spill_reg_order are used on two occasions:
185 once during find_reload_regs, where they keep track of the spill registers
186 for a single insn, but also during reload_as_needed where they show all
187 the registers ever used by reload. For the latter case, the information
188 is calculated during finish_spills. */
189 static short spill_regs[FIRST_PSEUDO_REGISTER];
191 /* This vector of reg sets indicates, for each pseudo, which hard registers
192 may not be used for retrying global allocation because the register was
193 formerly spilled from one of them. If we allowed reallocating a pseudo to
194 a register that it was already allocated to, reload might not
196 static HARD_REG_SET *pseudo_previous_regs;
198 /* This vector of reg sets indicates, for each pseudo, which hard
199 registers may not be used for retrying global allocation because they
200 are used as spill registers during one of the insns in which the
202 static HARD_REG_SET *pseudo_forbidden_regs;
204 /* All hard regs that have been used as spill registers for any insn are
205 marked in this set. */
206 static HARD_REG_SET used_spill_regs;
208 /* Index of last register assigned as a spill register. We allocate in
209 a round-robin fashion. */
210 static int last_spill_reg;
212 /* Nonzero if indirect addressing is supported on the machine; this means
213 that spilling (REG n) does not require reloading it into a register in
214 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
215 value indicates the level of indirect addressing supported, e.g., two
216 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
218 static char spill_indirect_levels;
220 /* Nonzero if indirect addressing is supported when the innermost MEM is
221 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
222 which these are valid is the same as spill_indirect_levels, above. */
223 char indirect_symref_ok;
225 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
226 char double_reg_address_ok;
228 /* Record the stack slot for each spilled hard register. */
229 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
231 /* Width allocated so far for that stack slot. */
232 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
234 /* Record which pseudos needed to be spilled. */
235 static regset_head spilled_pseudos;
237 /* Used for communication between order_regs_for_reload and count_pseudo.
238 Used to avoid counting one pseudo twice. */
239 static regset_head pseudos_counted;
241 /* First uid used by insns created by reload in this function.
242 Used in find_equiv_reg. */
243 int reload_first_uid;
245 /* Flag set by local-alloc or global-alloc if anything is live in
246 a call-clobbered reg across calls. */
247 int caller_save_needed;
249 /* Set to 1 while reload_as_needed is operating.
250 Required by some machines to handle any generated moves differently. */
251 int reload_in_progress = 0;
253 /* These arrays record the insn_code of insns that may be needed to
254 perform input and output reloads of special objects. They provide a
255 place to pass a scratch register. */
256 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
257 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
259 /* This obstack is used for allocation of rtl during register elimination.
260 The allocated storage can be freed once find_reloads has processed the
262 struct obstack reload_obstack;
264 /* Points to the beginning of the reload_obstack. All insn_chain structures
265 are allocated first. */
266 char *reload_startobj;
268 /* The point after all insn_chain structures. Used to quickly deallocate
269 memory allocated in copy_reloads during calculate_needs_all_insns. */
270 char *reload_firstobj;
272 /* This points before all local rtl generated by register elimination.
273 Used to quickly free all memory after processing one insn. */
274 static char *reload_insn_firstobj;
276 /* List of insn_chain instructions, one for every insn that reload needs to
278 struct insn_chain *reload_insn_chain;
280 /* List of all insns needing reloads. */
281 static struct insn_chain *insns_need_reload;
283 /* This structure is used to record information about register eliminations.
284 Each array entry describes one possible way of eliminating a register
285 in favor of another. If there is more than one way of eliminating a
286 particular register, the most preferred should be specified first. */
290 int from; /* Register number to be eliminated. */
291 int to; /* Register number used as replacement. */
292 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
293 int can_eliminate; /* Nonzero if this elimination can be done. */
294 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
295 insns made by reload. */
296 HOST_WIDE_INT offset; /* Current offset between the two regs. */
297 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
298 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
299 rtx from_rtx; /* REG rtx for the register to be eliminated.
300 We cannot simply compare the number since
301 we might then spuriously replace a hard
302 register corresponding to a pseudo
303 assigned to the reg to be eliminated. */
304 rtx to_rtx; /* REG rtx for the replacement. */
307 static struct elim_table *reg_eliminate = 0;
309 /* This is an intermediate structure to initialize the table. It has
310 exactly the members provided by ELIMINABLE_REGS. */
311 static const struct elim_table_1
315 } reg_eliminate_1[] =
317 /* If a set of eliminable registers was specified, define the table from it.
318 Otherwise, default to the normal case of the frame pointer being
319 replaced by the stack pointer. */
321 #ifdef ELIMINABLE_REGS
324 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
327 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
329 /* Record the number of pending eliminations that have an offset not equal
330 to their initial offset. If nonzero, we use a new copy of each
331 replacement result in any insns encountered. */
332 int num_not_at_initial_offset;
334 /* Count the number of registers that we may be able to eliminate. */
335 static int num_eliminable;
336 /* And the number of registers that are equivalent to a constant that
337 can be eliminated to frame_pointer / arg_pointer + constant. */
338 static int num_eliminable_invariants;
340 /* For each label, we record the offset of each elimination. If we reach
341 a label by more than one path and an offset differs, we cannot do the
342 elimination. This information is indexed by the difference of the
343 number of the label and the first label number. We can't offset the
344 pointer itself as this can cause problems on machines with segmented
345 memory. The first table is an array of flags that records whether we
346 have yet encountered a label and the second table is an array of arrays,
347 one entry in the latter array for each elimination. */
349 static int first_label_num;
350 static char *offsets_known_at;
351 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
353 /* Number of labels in the current function. */
355 static int num_labels;
357 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
358 static void maybe_fix_stack_asms (void);
359 static void copy_reloads (struct insn_chain *);
360 static void calculate_needs_all_insns (int);
361 static int find_reg (struct insn_chain *, int);
362 static void find_reload_regs (struct insn_chain *);
363 static void select_reload_regs (void);
364 static void delete_caller_save_insns (void);
366 static void spill_failure (rtx, enum reg_class);
367 static void count_spilled_pseudo (int, int, int);
368 static void delete_dead_insn (rtx);
369 static void alter_reg (int, int);
370 static void set_label_offsets (rtx, rtx, int);
371 static void check_eliminable_occurrences (rtx);
372 static void elimination_effects (rtx, enum machine_mode);
373 static int eliminate_regs_in_insn (rtx, int);
374 static void update_eliminable_offsets (void);
375 static void mark_not_eliminable (rtx, rtx, void *);
376 static void set_initial_elim_offsets (void);
377 static void verify_initial_elim_offsets (void);
378 static void set_initial_label_offsets (void);
379 static void set_offsets_for_label (rtx);
380 static void init_elim_table (void);
381 static void update_eliminables (HARD_REG_SET *);
382 static void spill_hard_reg (unsigned int, int);
383 static int finish_spills (int);
384 static void ior_hard_reg_set (HARD_REG_SET *, HARD_REG_SET *);
385 static void scan_paradoxical_subregs (rtx);
386 static void count_pseudo (int);
387 static void order_regs_for_reload (struct insn_chain *);
388 static void reload_as_needed (int);
389 static void forget_old_reloads_1 (rtx, rtx, void *);
390 static int reload_reg_class_lower (const void *, const void *);
391 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
393 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
395 static int reload_reg_free_p (unsigned int, int, enum reload_type);
396 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
398 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
400 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
401 static int allocate_reload_reg (struct insn_chain *, int, int);
402 static int conflicts_with_override (rtx);
403 static void failed_reload (rtx, int);
404 static int set_reload_reg (int, int);
405 static void choose_reload_regs_init (struct insn_chain *, rtx *);
406 static void choose_reload_regs (struct insn_chain *);
407 static void merge_assigned_reloads (rtx);
408 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
410 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
412 static void do_input_reload (struct insn_chain *, struct reload *, int);
413 static void do_output_reload (struct insn_chain *, struct reload *, int);
414 static void emit_reload_insns (struct insn_chain *);
415 static void delete_output_reload (rtx, int, int);
416 static void delete_address_reloads (rtx, rtx);
417 static void delete_address_reloads_1 (rtx, rtx, rtx);
418 static rtx inc_for_reload (rtx, rtx, rtx, int);
420 static void add_auto_inc_notes (rtx, rtx);
422 static void copy_eh_notes (rtx, rtx);
424 /* Initialize the reload pass once per compilation. */
431 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
432 Set spill_indirect_levels to the number of levels such addressing is
433 permitted, zero if it is not permitted at all. */
436 = gen_rtx_MEM (Pmode,
439 LAST_VIRTUAL_REGISTER + 1),
441 spill_indirect_levels = 0;
443 while (memory_address_p (QImode, tem))
445 spill_indirect_levels++;
446 tem = gen_rtx_MEM (Pmode, tem);
449 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
451 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
452 indirect_symref_ok = memory_address_p (QImode, tem);
454 /* See if reg+reg is a valid (and offsettable) address. */
456 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
458 tem = gen_rtx_PLUS (Pmode,
459 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
460 gen_rtx_REG (Pmode, i));
462 /* This way, we make sure that reg+reg is an offsettable address. */
463 tem = plus_constant (tem, 4);
465 if (memory_address_p (QImode, tem))
467 double_reg_address_ok = 1;
472 /* Initialize obstack for our rtl allocation. */
473 gcc_obstack_init (&reload_obstack);
474 reload_startobj = obstack_alloc (&reload_obstack, 0);
476 INIT_REG_SET (&spilled_pseudos);
477 INIT_REG_SET (&pseudos_counted);
480 /* List of insn chains that are currently unused. */
481 static struct insn_chain *unused_insn_chains = 0;
483 /* Allocate an empty insn_chain structure. */
485 new_insn_chain (void)
487 struct insn_chain *c;
489 if (unused_insn_chains == 0)
491 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
492 INIT_REG_SET (&c->live_throughout);
493 INIT_REG_SET (&c->dead_or_set);
497 c = unused_insn_chains;
498 unused_insn_chains = c->next;
500 c->is_caller_save_insn = 0;
501 c->need_operand_change = 0;
507 /* Small utility function to set all regs in hard reg set TO which are
508 allocated to pseudos in regset FROM. */
511 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
515 EXECUTE_IF_SET_IN_REG_SET
516 (from, FIRST_PSEUDO_REGISTER, regno,
518 int r = reg_renumber[regno];
523 /* reload_combine uses the information from
524 BASIC_BLOCK->global_live_at_start, which might still
525 contain registers that have not actually been allocated
526 since they have an equivalence. */
527 if (! reload_completed)
532 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
534 SET_HARD_REG_BIT (*to, r + nregs);
539 /* Replace all pseudos found in LOC with their corresponding
543 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
556 unsigned int regno = REGNO (x);
558 if (regno < FIRST_PSEUDO_REGISTER)
561 x = eliminate_regs (x, mem_mode, usage);
565 replace_pseudos_in (loc, mem_mode, usage);
569 if (reg_equiv_constant[regno])
570 *loc = reg_equiv_constant[regno];
571 else if (reg_equiv_mem[regno])
572 *loc = reg_equiv_mem[regno];
573 else if (reg_equiv_address[regno])
574 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
575 else if (GET_CODE (regno_reg_rtx[regno]) != REG
576 || REGNO (regno_reg_rtx[regno]) != regno)
577 *loc = regno_reg_rtx[regno];
583 else if (code == MEM)
585 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
589 /* Process each of our operands recursively. */
590 fmt = GET_RTX_FORMAT (code);
591 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
593 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
594 else if (*fmt == 'E')
595 for (j = 0; j < XVECLEN (x, i); j++)
596 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
600 /* Global variables used by reload and its subroutines. */
602 /* Set during calculate_needs if an insn needs register elimination. */
603 static int something_needs_elimination;
604 /* Set during calculate_needs if an insn needs an operand changed. */
605 int something_needs_operands_changed;
607 /* Nonzero means we couldn't get enough spill regs. */
610 /* Main entry point for the reload pass.
612 FIRST is the first insn of the function being compiled.
614 GLOBAL nonzero means we were called from global_alloc
615 and should attempt to reallocate any pseudoregs that we
616 displace from hard regs we will use for reloads.
617 If GLOBAL is zero, we do not have enough information to do that,
618 so any pseudo reg that is spilled must go to the stack.
620 Return value is nonzero if reload failed
621 and we must not do any more for this function. */
624 reload (rtx first, int global)
628 struct elim_table *ep;
631 /* Make sure even insns with volatile mem refs are recognizable. */
636 reload_firstobj = obstack_alloc (&reload_obstack, 0);
638 /* Make sure that the last insn in the chain
639 is not something that needs reloading. */
640 emit_note (NOTE_INSN_DELETED);
642 /* Enable find_equiv_reg to distinguish insns made by reload. */
643 reload_first_uid = get_max_uid ();
645 #ifdef SECONDARY_MEMORY_NEEDED
646 /* Initialize the secondary memory table. */
647 clear_secondary_mem ();
650 /* We don't have a stack slot for any spill reg yet. */
651 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
652 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
654 /* Initialize the save area information for caller-save, in case some
658 /* Compute which hard registers are now in use
659 as homes for pseudo registers.
660 This is done here rather than (eg) in global_alloc
661 because this point is reached even if not optimizing. */
662 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
665 /* A function that receives a nonlocal goto must save all call-saved
667 if (current_function_has_nonlocal_label)
668 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
669 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
670 regs_ever_live[i] = 1;
672 #ifdef NON_SAVING_SETJMP
673 /* A function that calls setjmp should save and restore all the
674 call-saved registers on a system where longjmp clobbers them. */
675 if (NON_SAVING_SETJMP && current_function_calls_setjmp)
677 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
678 if (! call_used_regs[i])
679 regs_ever_live[i] = 1;
683 /* Find all the pseudo registers that didn't get hard regs
684 but do have known equivalent constants or memory slots.
685 These include parameters (known equivalent to parameter slots)
686 and cse'd or loop-moved constant memory addresses.
688 Record constant equivalents in reg_equiv_constant
689 so they will be substituted by find_reloads.
690 Record memory equivalents in reg_mem_equiv so they can
691 be substituted eventually by altering the REG-rtx's. */
693 reg_equiv_constant = xcalloc (max_regno, sizeof (rtx));
694 reg_equiv_mem = xcalloc (max_regno, sizeof (rtx));
695 reg_equiv_init = xcalloc (max_regno, sizeof (rtx));
696 reg_equiv_address = xcalloc (max_regno, sizeof (rtx));
697 reg_max_ref_width = xcalloc (max_regno, sizeof (int));
698 reg_old_renumber = xcalloc (max_regno, sizeof (short));
699 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
700 pseudo_forbidden_regs = xmalloc (max_regno * sizeof (HARD_REG_SET));
701 pseudo_previous_regs = xcalloc (max_regno, sizeof (HARD_REG_SET));
703 CLEAR_HARD_REG_SET (bad_spill_regs_global);
705 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
706 Also find all paradoxical subregs and find largest such for each pseudo.
707 On machines with small register classes, record hard registers that
708 are used for user variables. These can never be used for spills. */
710 num_eliminable_invariants = 0;
711 for (insn = first; insn; insn = NEXT_INSN (insn))
713 rtx set = single_set (insn);
715 /* We may introduce USEs that we want to remove at the end, so
716 we'll mark them with QImode. Make sure there are no
717 previously-marked insns left by say regmove. */
718 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
719 && GET_MODE (insn) != VOIDmode)
720 PUT_MODE (insn, VOIDmode);
722 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
724 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
726 #ifdef LEGITIMATE_PIC_OPERAND_P
727 && (! function_invariant_p (XEXP (note, 0))
729 /* A function invariant is often CONSTANT_P but may
730 include a register. We promise to only pass
731 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
732 || (CONSTANT_P (XEXP (note, 0))
733 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))))
737 rtx x = XEXP (note, 0);
738 i = REGNO (SET_DEST (set));
739 if (i > LAST_VIRTUAL_REGISTER)
741 /* It can happen that a REG_EQUIV note contains a MEM
742 that is not a legitimate memory operand. As later
743 stages of reload assume that all addresses found
744 in the reg_equiv_* arrays were originally legitimate,
745 we ignore such REG_EQUIV notes. */
746 if (memory_operand (x, VOIDmode))
748 /* Always unshare the equivalence, so we can
749 substitute into this insn without touching the
751 reg_equiv_memory_loc[i] = copy_rtx (x);
753 else if (function_invariant_p (x))
755 if (GET_CODE (x) == PLUS)
757 /* This is PLUS of frame pointer and a constant,
758 and might be shared. Unshare it. */
759 reg_equiv_constant[i] = copy_rtx (x);
760 num_eliminable_invariants++;
762 else if (x == frame_pointer_rtx
763 || x == arg_pointer_rtx)
765 reg_equiv_constant[i] = x;
766 num_eliminable_invariants++;
768 else if (LEGITIMATE_CONSTANT_P (x))
769 reg_equiv_constant[i] = x;
772 reg_equiv_memory_loc[i]
773 = force_const_mem (GET_MODE (SET_DEST (set)), x);
774 if (!reg_equiv_memory_loc[i])
781 /* If this register is being made equivalent to a MEM
782 and the MEM is not SET_SRC, the equivalencing insn
783 is one with the MEM as a SET_DEST and it occurs later.
784 So don't mark this insn now. */
785 if (GET_CODE (x) != MEM
786 || rtx_equal_p (SET_SRC (set), x))
788 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
793 /* If this insn is setting a MEM from a register equivalent to it,
794 this is the equivalencing insn. */
795 else if (set && GET_CODE (SET_DEST (set)) == MEM
796 && GET_CODE (SET_SRC (set)) == REG
797 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
798 && rtx_equal_p (SET_DEST (set),
799 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
800 reg_equiv_init[REGNO (SET_SRC (set))]
801 = gen_rtx_INSN_LIST (VOIDmode, insn,
802 reg_equiv_init[REGNO (SET_SRC (set))]);
805 scan_paradoxical_subregs (PATTERN (insn));
810 first_label_num = get_first_label_num ();
811 num_labels = max_label_num () - first_label_num;
813 /* Allocate the tables used to store offset information at labels. */
814 /* We used to use alloca here, but the size of what it would try to
815 allocate would occasionally cause it to exceed the stack limit and
816 cause a core dump. */
817 offsets_known_at = xmalloc (num_labels);
818 offsets_at = xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
820 /* Alter each pseudo-reg rtx to contain its hard reg number.
821 Assign stack slots to the pseudos that lack hard regs or equivalents.
822 Do not touch virtual registers. */
824 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
827 /* If we have some registers we think can be eliminated, scan all insns to
828 see if there is an insn that sets one of these registers to something
829 other than itself plus a constant. If so, the register cannot be
830 eliminated. Doing this scan here eliminates an extra pass through the
831 main reload loop in the most common case where register elimination
833 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
834 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
835 || GET_CODE (insn) == CALL_INSN)
836 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
838 maybe_fix_stack_asms ();
840 insns_need_reload = 0;
841 something_needs_elimination = 0;
843 /* Initialize to -1, which means take the first spill register. */
846 /* Spill any hard regs that we know we can't eliminate. */
847 CLEAR_HARD_REG_SET (used_spill_regs);
848 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
849 if (! ep->can_eliminate)
850 spill_hard_reg (ep->from, 1);
852 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
853 if (frame_pointer_needed)
854 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
856 finish_spills (global);
858 /* From now on, we may need to generate moves differently. We may also
859 allow modifications of insns which cause them to not be recognized.
860 Any such modifications will be cleaned up during reload itself. */
861 reload_in_progress = 1;
863 /* This loop scans the entire function each go-round
864 and repeats until one repetition spills no additional hard regs. */
867 int something_changed;
870 HOST_WIDE_INT starting_frame_size;
872 /* Round size of stack frame to stack_alignment_needed. This must be done
873 here because the stack size may be a part of the offset computation
874 for register elimination, and there might have been new stack slots
875 created in the last iteration of this loop. */
876 if (cfun->stack_alignment_needed)
877 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
879 starting_frame_size = get_frame_size ();
881 set_initial_elim_offsets ();
882 set_initial_label_offsets ();
884 /* For each pseudo register that has an equivalent location defined,
885 try to eliminate any eliminable registers (such as the frame pointer)
886 assuming initial offsets for the replacement register, which
889 If the resulting location is directly addressable, substitute
890 the MEM we just got directly for the old REG.
892 If it is not addressable but is a constant or the sum of a hard reg
893 and constant, it is probably not addressable because the constant is
894 out of range, in that case record the address; we will generate
895 hairy code to compute the address in a register each time it is
896 needed. Similarly if it is a hard register, but one that is not
897 valid as an address register.
899 If the location is not addressable, but does not have one of the
900 above forms, assign a stack slot. We have to do this to avoid the
901 potential of producing lots of reloads if, e.g., a location involves
902 a pseudo that didn't get a hard register and has an equivalent memory
903 location that also involves a pseudo that didn't get a hard register.
905 Perhaps at some point we will improve reload_when_needed handling
906 so this problem goes away. But that's very hairy. */
908 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
909 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
911 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
913 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
915 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
916 else if (CONSTANT_P (XEXP (x, 0))
917 || (GET_CODE (XEXP (x, 0)) == REG
918 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
919 || (GET_CODE (XEXP (x, 0)) == PLUS
920 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
921 && (REGNO (XEXP (XEXP (x, 0), 0))
922 < FIRST_PSEUDO_REGISTER)
923 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
924 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
927 /* Make a new stack slot. Then indicate that something
928 changed so we go back and recompute offsets for
929 eliminable registers because the allocation of memory
930 below might change some offset. reg_equiv_{mem,address}
931 will be set up for this pseudo on the next pass around
933 reg_equiv_memory_loc[i] = 0;
934 reg_equiv_init[i] = 0;
939 if (caller_save_needed)
942 /* If we allocated another stack slot, redo elimination bookkeeping. */
943 if (starting_frame_size != get_frame_size ())
946 if (caller_save_needed)
948 save_call_clobbered_regs ();
949 /* That might have allocated new insn_chain structures. */
950 reload_firstobj = obstack_alloc (&reload_obstack, 0);
953 calculate_needs_all_insns (global);
955 CLEAR_REG_SET (&spilled_pseudos);
958 something_changed = 0;
960 /* If we allocated any new memory locations, make another pass
961 since it might have changed elimination offsets. */
962 if (starting_frame_size != get_frame_size ())
963 something_changed = 1;
966 HARD_REG_SET to_spill;
967 CLEAR_HARD_REG_SET (to_spill);
968 update_eliminables (&to_spill);
969 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
970 if (TEST_HARD_REG_BIT (to_spill, i))
972 spill_hard_reg (i, 1);
975 /* Regardless of the state of spills, if we previously had
976 a register that we thought we could eliminate, but now can
977 not eliminate, we must run another pass.
979 Consider pseudos which have an entry in reg_equiv_* which
980 reference an eliminable register. We must make another pass
981 to update reg_equiv_* so that we do not substitute in the
982 old value from when we thought the elimination could be
984 something_changed = 1;
988 select_reload_regs ();
992 if (insns_need_reload != 0 || did_spill)
993 something_changed |= finish_spills (global);
995 if (! something_changed)
998 if (caller_save_needed)
999 delete_caller_save_insns ();
1001 obstack_free (&reload_obstack, reload_firstobj);
1004 /* If global-alloc was run, notify it of any register eliminations we have
1007 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1008 if (ep->can_eliminate)
1009 mark_elimination (ep->from, ep->to);
1011 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1012 If that insn didn't set the register (i.e., it copied the register to
1013 memory), just delete that insn instead of the equivalencing insn plus
1014 anything now dead. If we call delete_dead_insn on that insn, we may
1015 delete the insn that actually sets the register if the register dies
1016 there and that is incorrect. */
1018 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1020 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1023 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1025 rtx equiv_insn = XEXP (list, 0);
1027 /* If we already deleted the insn or if it may trap, we can't
1028 delete it. The latter case shouldn't happen, but can
1029 if an insn has a variable address, gets a REG_EH_REGION
1030 note added to it, and then gets converted into an load
1031 from a constant address. */
1032 if (GET_CODE (equiv_insn) == NOTE
1033 || can_throw_internal (equiv_insn))
1035 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1036 delete_dead_insn (equiv_insn);
1039 PUT_CODE (equiv_insn, NOTE);
1040 NOTE_SOURCE_FILE (equiv_insn) = 0;
1041 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1047 /* Use the reload registers where necessary
1048 by generating move instructions to move the must-be-register
1049 values into or out of the reload registers. */
1051 if (insns_need_reload != 0 || something_needs_elimination
1052 || something_needs_operands_changed)
1054 HOST_WIDE_INT old_frame_size = get_frame_size ();
1056 reload_as_needed (global);
1058 if (old_frame_size != get_frame_size ())
1062 verify_initial_elim_offsets ();
1065 /* If we were able to eliminate the frame pointer, show that it is no
1066 longer live at the start of any basic block. If it ls live by
1067 virtue of being in a pseudo, that pseudo will be marked live
1068 and hence the frame pointer will be known to be live via that
1071 if (! frame_pointer_needed)
1073 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1074 HARD_FRAME_POINTER_REGNUM);
1076 /* Come here (with failure set nonzero) if we can't get enough spill regs
1077 and we decide not to abort about it. */
1080 CLEAR_REG_SET (&spilled_pseudos);
1081 reload_in_progress = 0;
1083 /* Now eliminate all pseudo regs by modifying them into
1084 their equivalent memory references.
1085 The REG-rtx's for the pseudos are modified in place,
1086 so all insns that used to refer to them now refer to memory.
1088 For a reg that has a reg_equiv_address, all those insns
1089 were changed by reloading so that no insns refer to it any longer;
1090 but the DECL_RTL of a variable decl may refer to it,
1091 and if so this causes the debugging info to mention the variable. */
1093 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1097 if (reg_equiv_mem[i])
1098 addr = XEXP (reg_equiv_mem[i], 0);
1100 if (reg_equiv_address[i])
1101 addr = reg_equiv_address[i];
1105 if (reg_renumber[i] < 0)
1107 rtx reg = regno_reg_rtx[i];
1109 REG_USERVAR_P (reg) = 0;
1110 PUT_CODE (reg, MEM);
1111 XEXP (reg, 0) = addr;
1112 if (reg_equiv_memory_loc[i])
1113 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1116 RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg)
1117 = MEM_SCALAR_P (reg) = 0;
1118 MEM_ATTRS (reg) = 0;
1121 else if (reg_equiv_mem[i])
1122 XEXP (reg_equiv_mem[i], 0) = addr;
1126 /* We must set reload_completed now since the cleanup_subreg_operands call
1127 below will re-recognize each insn and reload may have generated insns
1128 which are only valid during and after reload. */
1129 reload_completed = 1;
1131 /* Make a pass over all the insns and delete all USEs which we inserted
1132 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1133 notes. Delete all CLOBBER insns, except those that refer to the return
1134 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1135 from misarranging variable-array code, and simplify (subreg (reg))
1136 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1137 are no longer useful or accurate. Strip and regenerate REG_INC notes
1138 that may have been moved around. */
1140 for (insn = first; insn; insn = NEXT_INSN (insn))
1145 if (GET_CODE (insn) == CALL_INSN)
1146 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1147 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1149 if ((GET_CODE (PATTERN (insn)) == USE
1150 /* We mark with QImode USEs introduced by reload itself. */
1151 && (GET_MODE (insn) == QImode
1152 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1153 || (GET_CODE (PATTERN (insn)) == CLOBBER
1154 && (GET_CODE (XEXP (PATTERN (insn), 0)) != MEM
1155 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1156 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1157 && XEXP (XEXP (PATTERN (insn), 0), 0)
1158 != stack_pointer_rtx))
1159 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1160 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1166 /* Some CLOBBERs may survive until here and still reference unassigned
1167 pseudos with const equivalent, which may in turn cause ICE in later
1168 passes if the reference remains in place. */
1169 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1170 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1171 VOIDmode, PATTERN (insn));
1173 pnote = ®_NOTES (insn);
1176 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1177 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1178 || REG_NOTE_KIND (*pnote) == REG_INC
1179 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1180 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1181 *pnote = XEXP (*pnote, 1);
1183 pnote = &XEXP (*pnote, 1);
1187 add_auto_inc_notes (insn, PATTERN (insn));
1190 /* And simplify (subreg (reg)) if it appears as an operand. */
1191 cleanup_subreg_operands (insn);
1194 /* If we are doing stack checking, give a warning if this function's
1195 frame size is larger than we expect. */
1196 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1198 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1199 static int verbose_warned = 0;
1201 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1202 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1203 size += UNITS_PER_WORD;
1205 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1207 warning ("frame size too large for reliable stack checking");
1208 if (! verbose_warned)
1210 warning ("try reducing the number of local variables");
1216 /* Indicate that we no longer have known memory locations or constants. */
1217 if (reg_equiv_constant)
1218 free (reg_equiv_constant);
1219 reg_equiv_constant = 0;
1220 if (reg_equiv_memory_loc)
1221 free (reg_equiv_memory_loc);
1222 reg_equiv_memory_loc = 0;
1224 if (offsets_known_at)
1225 free (offsets_known_at);
1229 free (reg_equiv_mem);
1230 free (reg_equiv_init);
1231 free (reg_equiv_address);
1232 free (reg_max_ref_width);
1233 free (reg_old_renumber);
1234 free (pseudo_previous_regs);
1235 free (pseudo_forbidden_regs);
1237 CLEAR_HARD_REG_SET (used_spill_regs);
1238 for (i = 0; i < n_spills; i++)
1239 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1241 /* Free all the insn_chain structures at once. */
1242 obstack_free (&reload_obstack, reload_startobj);
1243 unused_insn_chains = 0;
1244 fixup_abnormal_edges ();
1246 /* Replacing pseudos with their memory equivalents might have
1247 created shared rtx. Subsequent passes would get confused
1248 by this, so unshare everything here. */
1249 unshare_all_rtl_again (first);
1251 #ifdef STACK_BOUNDARY
1252 /* init_emit has set the alignment of the hard frame pointer
1253 to STACK_BOUNDARY. It is very likely no longer valid if
1254 the hard frame pointer was used for register allocation. */
1255 if (!frame_pointer_needed)
1256 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1262 /* Yet another special case. Unfortunately, reg-stack forces people to
1263 write incorrect clobbers in asm statements. These clobbers must not
1264 cause the register to appear in bad_spill_regs, otherwise we'll call
1265 fatal_insn later. We clear the corresponding regnos in the live
1266 register sets to avoid this.
1267 The whole thing is rather sick, I'm afraid. */
1270 maybe_fix_stack_asms (void)
1273 const char *constraints[MAX_RECOG_OPERANDS];
1274 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1275 struct insn_chain *chain;
1277 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1280 HARD_REG_SET clobbered, allowed;
1283 if (! INSN_P (chain->insn)
1284 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1286 pat = PATTERN (chain->insn);
1287 if (GET_CODE (pat) != PARALLEL)
1290 CLEAR_HARD_REG_SET (clobbered);
1291 CLEAR_HARD_REG_SET (allowed);
1293 /* First, make a mask of all stack regs that are clobbered. */
1294 for (i = 0; i < XVECLEN (pat, 0); i++)
1296 rtx t = XVECEXP (pat, 0, i);
1297 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1298 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1301 /* Get the operand values and constraints out of the insn. */
1302 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1303 constraints, operand_mode);
1305 /* For every operand, see what registers are allowed. */
1306 for (i = 0; i < noperands; i++)
1308 const char *p = constraints[i];
1309 /* For every alternative, we compute the class of registers allowed
1310 for reloading in CLS, and merge its contents into the reg set
1312 int cls = (int) NO_REGS;
1318 if (c == '\0' || c == ',' || c == '#')
1320 /* End of one alternative - mark the regs in the current
1321 class, and reset the class. */
1322 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1328 } while (c != '\0' && c != ',');
1336 case '=': case '+': case '*': case '%': case '?': case '!':
1337 case '0': case '1': case '2': case '3': case '4': case 'm':
1338 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1339 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1340 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1345 cls = (int) reg_class_subunion[cls]
1346 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1351 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1355 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1356 cls = (int) reg_class_subunion[cls]
1357 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1359 cls = (int) reg_class_subunion[cls]
1360 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1362 p += CONSTRAINT_LEN (c, p);
1365 /* Those of the registers which are clobbered, but allowed by the
1366 constraints, must be usable as reload registers. So clear them
1367 out of the life information. */
1368 AND_HARD_REG_SET (allowed, clobbered);
1369 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1370 if (TEST_HARD_REG_BIT (allowed, i))
1372 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1373 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1380 /* Copy the global variables n_reloads and rld into the corresponding elts
1383 copy_reloads (struct insn_chain *chain)
1385 chain->n_reloads = n_reloads;
1386 chain->rld = obstack_alloc (&reload_obstack,
1387 n_reloads * sizeof (struct reload));
1388 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1389 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1392 /* Walk the chain of insns, and determine for each whether it needs reloads
1393 and/or eliminations. Build the corresponding insns_need_reload list, and
1394 set something_needs_elimination as appropriate. */
1396 calculate_needs_all_insns (int global)
1398 struct insn_chain **pprev_reload = &insns_need_reload;
1399 struct insn_chain *chain, *next = 0;
1401 something_needs_elimination = 0;
1403 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1404 for (chain = reload_insn_chain; chain != 0; chain = next)
1406 rtx insn = chain->insn;
1410 /* Clear out the shortcuts. */
1411 chain->n_reloads = 0;
1412 chain->need_elim = 0;
1413 chain->need_reload = 0;
1414 chain->need_operand_change = 0;
1416 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1417 include REG_LABEL), we need to see what effects this has on the
1418 known offsets at labels. */
1420 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1421 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1422 set_label_offsets (insn, insn, 0);
1426 rtx old_body = PATTERN (insn);
1427 int old_code = INSN_CODE (insn);
1428 rtx old_notes = REG_NOTES (insn);
1429 int did_elimination = 0;
1430 int operands_changed = 0;
1431 rtx set = single_set (insn);
1433 /* Skip insns that only set an equivalence. */
1434 if (set && GET_CODE (SET_DEST (set)) == REG
1435 && reg_renumber[REGNO (SET_DEST (set))] < 0
1436 && reg_equiv_constant[REGNO (SET_DEST (set))])
1439 /* If needed, eliminate any eliminable registers. */
1440 if (num_eliminable || num_eliminable_invariants)
1441 did_elimination = eliminate_regs_in_insn (insn, 0);
1443 /* Analyze the instruction. */
1444 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1445 global, spill_reg_order);
1447 /* If a no-op set needs more than one reload, this is likely
1448 to be something that needs input address reloads. We
1449 can't get rid of this cleanly later, and it is of no use
1450 anyway, so discard it now.
1451 We only do this when expensive_optimizations is enabled,
1452 since this complements reload inheritance / output
1453 reload deletion, and it can make debugging harder. */
1454 if (flag_expensive_optimizations && n_reloads > 1)
1456 rtx set = single_set (insn);
1458 && SET_SRC (set) == SET_DEST (set)
1459 && GET_CODE (SET_SRC (set)) == REG
1460 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1463 /* Delete it from the reload chain. */
1465 chain->prev->next = next;
1467 reload_insn_chain = next;
1469 next->prev = chain->prev;
1470 chain->next = unused_insn_chains;
1471 unused_insn_chains = chain;
1476 update_eliminable_offsets ();
1478 /* Remember for later shortcuts which insns had any reloads or
1479 register eliminations. */
1480 chain->need_elim = did_elimination;
1481 chain->need_reload = n_reloads > 0;
1482 chain->need_operand_change = operands_changed;
1484 /* Discard any register replacements done. */
1485 if (did_elimination)
1487 obstack_free (&reload_obstack, reload_insn_firstobj);
1488 PATTERN (insn) = old_body;
1489 INSN_CODE (insn) = old_code;
1490 REG_NOTES (insn) = old_notes;
1491 something_needs_elimination = 1;
1494 something_needs_operands_changed |= operands_changed;
1498 copy_reloads (chain);
1499 *pprev_reload = chain;
1500 pprev_reload = &chain->next_need_reload;
1507 /* Comparison function for qsort to decide which of two reloads
1508 should be handled first. *P1 and *P2 are the reload numbers. */
1511 reload_reg_class_lower (const void *r1p, const void *r2p)
1513 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1516 /* Consider required reloads before optional ones. */
1517 t = rld[r1].optional - rld[r2].optional;
1521 /* Count all solitary classes before non-solitary ones. */
1522 t = ((reg_class_size[(int) rld[r2].class] == 1)
1523 - (reg_class_size[(int) rld[r1].class] == 1));
1527 /* Aside from solitaires, consider all multi-reg groups first. */
1528 t = rld[r2].nregs - rld[r1].nregs;
1532 /* Consider reloads in order of increasing reg-class number. */
1533 t = (int) rld[r1].class - (int) rld[r2].class;
1537 /* If reloads are equally urgent, sort by reload number,
1538 so that the results of qsort leave nothing to chance. */
1542 /* The cost of spilling each hard reg. */
1543 static int spill_cost[FIRST_PSEUDO_REGISTER];
1545 /* When spilling multiple hard registers, we use SPILL_COST for the first
1546 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1547 only the first hard reg for a multi-reg pseudo. */
1548 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1550 /* Update the spill cost arrays, considering that pseudo REG is live. */
1553 count_pseudo (int reg)
1555 int freq = REG_FREQ (reg);
1556 int r = reg_renumber[reg];
1559 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1560 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1563 SET_REGNO_REG_SET (&pseudos_counted, reg);
1568 spill_add_cost[r] += freq;
1570 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1572 spill_cost[r + nregs] += freq;
1575 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1576 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1579 order_regs_for_reload (struct insn_chain *chain)
1582 HARD_REG_SET used_by_pseudos;
1583 HARD_REG_SET used_by_pseudos2;
1585 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1587 memset (spill_cost, 0, sizeof spill_cost);
1588 memset (spill_add_cost, 0, sizeof spill_add_cost);
1590 /* Count number of uses of each hard reg by pseudo regs allocated to it
1591 and then order them by decreasing use. First exclude hard registers
1592 that are live in or across this insn. */
1594 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1595 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1596 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1597 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1599 /* Now find out which pseudos are allocated to it, and update
1601 CLEAR_REG_SET (&pseudos_counted);
1603 EXECUTE_IF_SET_IN_REG_SET
1604 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1608 EXECUTE_IF_SET_IN_REG_SET
1609 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1613 CLEAR_REG_SET (&pseudos_counted);
1616 /* Vector of reload-numbers showing the order in which the reloads should
1618 static short reload_order[MAX_RELOADS];
1620 /* This is used to keep track of the spill regs used in one insn. */
1621 static HARD_REG_SET used_spill_regs_local;
1623 /* We decided to spill hard register SPILLED, which has a size of
1624 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1625 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1626 update SPILL_COST/SPILL_ADD_COST. */
1629 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1631 int r = reg_renumber[reg];
1632 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1634 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1635 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1638 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1640 spill_add_cost[r] -= REG_FREQ (reg);
1642 spill_cost[r + nregs] -= REG_FREQ (reg);
1645 /* Find reload register to use for reload number ORDER. */
1648 find_reg (struct insn_chain *chain, int order)
1650 int rnum = reload_order[order];
1651 struct reload *rl = rld + rnum;
1652 int best_cost = INT_MAX;
1656 HARD_REG_SET not_usable;
1657 HARD_REG_SET used_by_other_reload;
1659 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1660 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1661 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1663 CLEAR_HARD_REG_SET (used_by_other_reload);
1664 for (k = 0; k < order; k++)
1666 int other = reload_order[k];
1668 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1669 for (j = 0; j < rld[other].nregs; j++)
1670 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1673 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1675 unsigned int regno = i;
1677 if (! TEST_HARD_REG_BIT (not_usable, regno)
1678 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1679 && HARD_REGNO_MODE_OK (regno, rl->mode))
1681 int this_cost = spill_cost[regno];
1683 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1685 for (j = 1; j < this_nregs; j++)
1687 this_cost += spill_add_cost[regno + j];
1688 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1689 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1694 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1696 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1698 if (this_cost < best_cost
1699 /* Among registers with equal cost, prefer caller-saved ones, or
1700 use REG_ALLOC_ORDER if it is defined. */
1701 || (this_cost == best_cost
1702 #ifdef REG_ALLOC_ORDER
1703 && (inv_reg_alloc_order[regno]
1704 < inv_reg_alloc_order[best_reg])
1706 && call_used_regs[regno]
1707 && ! call_used_regs[best_reg]
1712 best_cost = this_cost;
1720 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1722 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1723 rl->regno = best_reg;
1725 EXECUTE_IF_SET_IN_REG_SET
1726 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1728 count_spilled_pseudo (best_reg, rl->nregs, j);
1731 EXECUTE_IF_SET_IN_REG_SET
1732 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1734 count_spilled_pseudo (best_reg, rl->nregs, j);
1737 for (i = 0; i < rl->nregs; i++)
1739 if (spill_cost[best_reg + i] != 0
1740 || spill_add_cost[best_reg + i] != 0)
1742 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1747 /* Find more reload regs to satisfy the remaining need of an insn, which
1749 Do it by ascending class number, since otherwise a reg
1750 might be spilled for a big class and might fail to count
1751 for a smaller class even though it belongs to that class. */
1754 find_reload_regs (struct insn_chain *chain)
1758 /* In order to be certain of getting the registers we need,
1759 we must sort the reloads into order of increasing register class.
1760 Then our grabbing of reload registers will parallel the process
1761 that provided the reload registers. */
1762 for (i = 0; i < chain->n_reloads; i++)
1764 /* Show whether this reload already has a hard reg. */
1765 if (chain->rld[i].reg_rtx)
1767 int regno = REGNO (chain->rld[i].reg_rtx);
1768 chain->rld[i].regno = regno;
1770 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1773 chain->rld[i].regno = -1;
1774 reload_order[i] = i;
1777 n_reloads = chain->n_reloads;
1778 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1780 CLEAR_HARD_REG_SET (used_spill_regs_local);
1783 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1785 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1787 /* Compute the order of preference for hard registers to spill. */
1789 order_regs_for_reload (chain);
1791 for (i = 0; i < n_reloads; i++)
1793 int r = reload_order[i];
1795 /* Ignore reloads that got marked inoperative. */
1796 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1797 && ! rld[r].optional
1798 && rld[r].regno == -1)
1799 if (! find_reg (chain, i))
1801 spill_failure (chain->insn, rld[r].class);
1807 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1808 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1810 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1814 select_reload_regs (void)
1816 struct insn_chain *chain;
1818 /* Try to satisfy the needs for each insn. */
1819 for (chain = insns_need_reload; chain != 0;
1820 chain = chain->next_need_reload)
1821 find_reload_regs (chain);
1824 /* Delete all insns that were inserted by emit_caller_save_insns during
1827 delete_caller_save_insns (void)
1829 struct insn_chain *c = reload_insn_chain;
1833 while (c != 0 && c->is_caller_save_insn)
1835 struct insn_chain *next = c->next;
1838 if (c == reload_insn_chain)
1839 reload_insn_chain = next;
1843 next->prev = c->prev;
1845 c->prev->next = next;
1846 c->next = unused_insn_chains;
1847 unused_insn_chains = c;
1855 /* Handle the failure to find a register to spill.
1856 INSN should be one of the insns which needed this particular spill reg. */
1859 spill_failure (rtx insn, enum reg_class class)
1861 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1862 if (asm_noperands (PATTERN (insn)) >= 0)
1863 error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'",
1864 reg_class_names[class]);
1867 error ("unable to find a register to spill in class `%s'",
1868 reg_class_names[class]);
1869 fatal_insn ("this is the insn:", insn);
1873 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1874 data that is dead in INSN. */
1877 delete_dead_insn (rtx insn)
1879 rtx prev = prev_real_insn (insn);
1882 /* If the previous insn sets a register that dies in our insn, delete it
1884 if (prev && GET_CODE (PATTERN (prev)) == SET
1885 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1886 && reg_mentioned_p (prev_dest, PATTERN (insn))
1887 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1888 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1889 delete_dead_insn (prev);
1891 PUT_CODE (insn, NOTE);
1892 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1893 NOTE_SOURCE_FILE (insn) = 0;
1896 /* Modify the home of pseudo-reg I.
1897 The new home is present in reg_renumber[I].
1899 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1900 or it may be -1, meaning there is none or it is not relevant.
1901 This is used so that all pseudos spilled from a given hard reg
1902 can share one stack slot. */
1905 alter_reg (int i, int from_reg)
1907 /* When outputting an inline function, this can happen
1908 for a reg that isn't actually used. */
1909 if (regno_reg_rtx[i] == 0)
1912 /* If the reg got changed to a MEM at rtl-generation time,
1914 if (GET_CODE (regno_reg_rtx[i]) != REG)
1917 /* Modify the reg-rtx to contain the new hard reg
1918 number or else to contain its pseudo reg number. */
1919 REGNO (regno_reg_rtx[i])
1920 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1922 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1923 allocate a stack slot for it. */
1925 if (reg_renumber[i] < 0
1926 && REG_N_REFS (i) > 0
1927 && reg_equiv_constant[i] == 0
1928 && reg_equiv_memory_loc[i] == 0)
1931 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1932 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1935 /* Each pseudo reg has an inherent size which comes from its own mode,
1936 and a total size which provides room for paradoxical subregs
1937 which refer to the pseudo reg in wider modes.
1939 We can use a slot already allocated if it provides both
1940 enough inherent space and enough total space.
1941 Otherwise, we allocate a new slot, making sure that it has no less
1942 inherent space, and no less total space, then the previous slot. */
1945 /* No known place to spill from => no slot to reuse. */
1946 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1947 inherent_size == total_size ? 0 : -1);
1948 if (BYTES_BIG_ENDIAN)
1949 /* Cancel the big-endian correction done in assign_stack_local.
1950 Get the address of the beginning of the slot.
1951 This is so we can do a big-endian correction unconditionally
1953 adjust = inherent_size - total_size;
1955 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1957 /* Nothing can alias this slot except this pseudo. */
1958 set_mem_alias_set (x, new_alias_set ());
1961 /* Reuse a stack slot if possible. */
1962 else if (spill_stack_slot[from_reg] != 0
1963 && spill_stack_slot_width[from_reg] >= total_size
1964 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1966 x = spill_stack_slot[from_reg];
1968 /* Allocate a bigger slot. */
1971 /* Compute maximum size needed, both for inherent size
1972 and for total size. */
1973 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1976 if (spill_stack_slot[from_reg])
1978 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1980 mode = GET_MODE (spill_stack_slot[from_reg]);
1981 if (spill_stack_slot_width[from_reg] > total_size)
1982 total_size = spill_stack_slot_width[from_reg];
1985 /* Make a slot with that size. */
1986 x = assign_stack_local (mode, total_size,
1987 inherent_size == total_size ? 0 : -1);
1990 /* All pseudos mapped to this slot can alias each other. */
1991 if (spill_stack_slot[from_reg])
1992 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
1994 set_mem_alias_set (x, new_alias_set ());
1996 if (BYTES_BIG_ENDIAN)
1998 /* Cancel the big-endian correction done in assign_stack_local.
1999 Get the address of the beginning of the slot.
2000 This is so we can do a big-endian correction unconditionally
2002 adjust = GET_MODE_SIZE (mode) - total_size;
2005 = adjust_address_nv (x, mode_for_size (total_size
2011 spill_stack_slot[from_reg] = stack_slot;
2012 spill_stack_slot_width[from_reg] = total_size;
2015 /* On a big endian machine, the "address" of the slot
2016 is the address of the low part that fits its inherent mode. */
2017 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2018 adjust += (total_size - inherent_size);
2020 /* If we have any adjustment to make, or if the stack slot is the
2021 wrong mode, make a new stack slot. */
2022 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2024 /* If we have a decl for the original register, set it for the
2025 memory. If this is a shared MEM, make a copy. */
2026 if (REG_EXPR (regno_reg_rtx[i])
2027 && TREE_CODE_CLASS (TREE_CODE (REG_EXPR (regno_reg_rtx[i]))) == 'd')
2029 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2031 /* We can do this only for the DECLs home pseudo, not for
2032 any copies of it, since otherwise when the stack slot
2033 is reused, nonoverlapping_memrefs_p might think they
2035 if (decl && GET_CODE (decl) == REG && REGNO (decl) == (unsigned) i)
2037 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2040 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2044 /* Save the stack slot for later. */
2045 reg_equiv_memory_loc[i] = x;
2049 /* Mark the slots in regs_ever_live for the hard regs
2050 used by pseudo-reg number REGNO. */
2053 mark_home_live (int regno)
2057 i = reg_renumber[regno];
2060 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2062 regs_ever_live[i++] = 1;
2065 /* This function handles the tracking of elimination offsets around branches.
2067 X is a piece of RTL being scanned.
2069 INSN is the insn that it came from, if any.
2071 INITIAL_P is nonzero if we are to set the offset to be the initial
2072 offset and zero if we are setting the offset of the label to be the
2076 set_label_offsets (rtx x, rtx insn, int initial_p)
2078 enum rtx_code code = GET_CODE (x);
2081 struct elim_table *p;
2086 if (LABEL_REF_NONLOCAL_P (x))
2091 /* ... fall through ... */
2094 /* If we know nothing about this label, set the desired offsets. Note
2095 that this sets the offset at a label to be the offset before a label
2096 if we don't know anything about the label. This is not correct for
2097 the label after a BARRIER, but is the best guess we can make. If
2098 we guessed wrong, we will suppress an elimination that might have
2099 been possible had we been able to guess correctly. */
2101 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2103 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2104 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2105 = (initial_p ? reg_eliminate[i].initial_offset
2106 : reg_eliminate[i].offset);
2107 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2110 /* Otherwise, if this is the definition of a label and it is
2111 preceded by a BARRIER, set our offsets to the known offset of
2115 && (tem = prev_nonnote_insn (insn)) != 0
2116 && GET_CODE (tem) == BARRIER)
2117 set_offsets_for_label (insn);
2119 /* If neither of the above cases is true, compare each offset
2120 with those previously recorded and suppress any eliminations
2121 where the offsets disagree. */
2123 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2124 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2125 != (initial_p ? reg_eliminate[i].initial_offset
2126 : reg_eliminate[i].offset))
2127 reg_eliminate[i].can_eliminate = 0;
2132 set_label_offsets (PATTERN (insn), insn, initial_p);
2134 /* ... fall through ... */
2138 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2139 and hence must have all eliminations at their initial offsets. */
2140 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2141 if (REG_NOTE_KIND (tem) == REG_LABEL)
2142 set_label_offsets (XEXP (tem, 0), insn, 1);
2148 /* Each of the labels in the parallel or address vector must be
2149 at their initial offsets. We want the first field for PARALLEL
2150 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2152 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2153 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2158 /* We only care about setting PC. If the source is not RETURN,
2159 IF_THEN_ELSE, or a label, disable any eliminations not at
2160 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2161 isn't one of those possibilities. For branches to a label,
2162 call ourselves recursively.
2164 Note that this can disable elimination unnecessarily when we have
2165 a non-local goto since it will look like a non-constant jump to
2166 someplace in the current function. This isn't a significant
2167 problem since such jumps will normally be when all elimination
2168 pairs are back to their initial offsets. */
2170 if (SET_DEST (x) != pc_rtx)
2173 switch (GET_CODE (SET_SRC (x)))
2180 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2184 tem = XEXP (SET_SRC (x), 1);
2185 if (GET_CODE (tem) == LABEL_REF)
2186 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2187 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2190 tem = XEXP (SET_SRC (x), 2);
2191 if (GET_CODE (tem) == LABEL_REF)
2192 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2193 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2201 /* If we reach here, all eliminations must be at their initial
2202 offset because we are doing a jump to a variable address. */
2203 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2204 if (p->offset != p->initial_offset)
2205 p->can_eliminate = 0;
2213 /* Scan X and replace any eliminable registers (such as fp) with a
2214 replacement (such as sp), plus an offset.
2216 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2217 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2218 MEM, we are allowed to replace a sum of a register and the constant zero
2219 with the register, which we cannot do outside a MEM. In addition, we need
2220 to record the fact that a register is referenced outside a MEM.
2222 If INSN is an insn, it is the insn containing X. If we replace a REG
2223 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2224 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2225 the REG is being modified.
2227 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2228 That's used when we eliminate in expressions stored in notes.
2229 This means, do not set ref_outside_mem even if the reference
2232 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2233 replacements done assuming all offsets are at their initial values. If
2234 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2235 encounter, return the actual location so that find_reloads will do
2236 the proper thing. */
2239 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2241 enum rtx_code code = GET_CODE (x);
2242 struct elim_table *ep;
2249 if (! current_function_decl)
2269 /* This is only for the benefit of the debugging backends, which call
2270 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2271 removed after CSE. */
2272 new = eliminate_regs (XEXP (x, 0), 0, insn);
2273 if (GET_CODE (new) == MEM)
2274 return XEXP (new, 0);
2280 /* First handle the case where we encounter a bare register that
2281 is eliminable. Replace it with a PLUS. */
2282 if (regno < FIRST_PSEUDO_REGISTER)
2284 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2286 if (ep->from_rtx == x && ep->can_eliminate)
2287 return plus_constant (ep->to_rtx, ep->previous_offset);
2290 else if (reg_renumber && reg_renumber[regno] < 0
2291 && reg_equiv_constant && reg_equiv_constant[regno]
2292 && ! CONSTANT_P (reg_equiv_constant[regno]))
2293 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2297 /* You might think handling MINUS in a manner similar to PLUS is a
2298 good idea. It is not. It has been tried multiple times and every
2299 time the change has had to have been reverted.
2301 Other parts of reload know a PLUS is special (gen_reload for example)
2302 and require special code to handle code a reloaded PLUS operand.
2304 Also consider backends where the flags register is clobbered by a
2305 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2306 lea instruction comes to mind). If we try to reload a MINUS, we
2307 may kill the flags register that was holding a useful value.
2309 So, please before trying to handle MINUS, consider reload as a
2310 whole instead of this little section as well as the backend issues. */
2312 /* If this is the sum of an eliminable register and a constant, rework
2314 if (GET_CODE (XEXP (x, 0)) == REG
2315 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2316 && CONSTANT_P (XEXP (x, 1)))
2318 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2320 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2322 /* The only time we want to replace a PLUS with a REG (this
2323 occurs when the constant operand of the PLUS is the negative
2324 of the offset) is when we are inside a MEM. We won't want
2325 to do so at other times because that would change the
2326 structure of the insn in a way that reload can't handle.
2327 We special-case the commonest situation in
2328 eliminate_regs_in_insn, so just replace a PLUS with a
2329 PLUS here, unless inside a MEM. */
2330 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2331 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2334 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2335 plus_constant (XEXP (x, 1),
2336 ep->previous_offset));
2339 /* If the register is not eliminable, we are done since the other
2340 operand is a constant. */
2344 /* If this is part of an address, we want to bring any constant to the
2345 outermost PLUS. We will do this by doing register replacement in
2346 our operands and seeing if a constant shows up in one of them.
2348 Note that there is no risk of modifying the structure of the insn,
2349 since we only get called for its operands, thus we are either
2350 modifying the address inside a MEM, or something like an address
2351 operand of a load-address insn. */
2354 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2355 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2357 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2359 /* If one side is a PLUS and the other side is a pseudo that
2360 didn't get a hard register but has a reg_equiv_constant,
2361 we must replace the constant here since it may no longer
2362 be in the position of any operand. */
2363 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2364 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2365 && reg_renumber[REGNO (new1)] < 0
2366 && reg_equiv_constant != 0
2367 && reg_equiv_constant[REGNO (new1)] != 0)
2368 new1 = reg_equiv_constant[REGNO (new1)];
2369 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2370 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2371 && reg_renumber[REGNO (new0)] < 0
2372 && reg_equiv_constant[REGNO (new0)] != 0)
2373 new0 = reg_equiv_constant[REGNO (new0)];
2375 new = form_sum (new0, new1);
2377 /* As above, if we are not inside a MEM we do not want to
2378 turn a PLUS into something else. We might try to do so here
2379 for an addition of 0 if we aren't optimizing. */
2380 if (! mem_mode && GET_CODE (new) != PLUS)
2381 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2389 /* If this is the product of an eliminable register and a
2390 constant, apply the distribute law and move the constant out
2391 so that we have (plus (mult ..) ..). This is needed in order
2392 to keep load-address insns valid. This case is pathological.
2393 We ignore the possibility of overflow here. */
2394 if (GET_CODE (XEXP (x, 0)) == REG
2395 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2396 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2397 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2399 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2402 /* Refs inside notes don't count for this purpose. */
2403 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2404 || GET_CODE (insn) == INSN_LIST)))
2405 ep->ref_outside_mem = 1;
2408 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2409 ep->previous_offset * INTVAL (XEXP (x, 1)));
2412 /* ... fall through ... */
2416 /* See comments before PLUS about handling MINUS. */
2418 case DIV: case UDIV:
2419 case MOD: case UMOD:
2420 case AND: case IOR: case XOR:
2421 case ROTATERT: case ROTATE:
2422 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2424 case GE: case GT: case GEU: case GTU:
2425 case LE: case LT: case LEU: case LTU:
2427 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2429 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2431 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2432 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2437 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2440 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2441 if (new != XEXP (x, 0))
2443 /* If this is a REG_DEAD note, it is not valid anymore.
2444 Using the eliminated version could result in creating a
2445 REG_DEAD note for the stack or frame pointer. */
2446 if (GET_MODE (x) == REG_DEAD)
2448 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2451 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2455 /* ... fall through ... */
2458 /* Now do eliminations in the rest of the chain. If this was
2459 an EXPR_LIST, this might result in allocating more memory than is
2460 strictly needed, but it simplifies the code. */
2463 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2464 if (new != XEXP (x, 1))
2466 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2474 case STRICT_LOW_PART:
2476 case SIGN_EXTEND: case ZERO_EXTEND:
2477 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2478 case FLOAT: case FIX:
2479 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2487 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2488 if (new != XEXP (x, 0))
2489 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2493 /* Similar to above processing, but preserve SUBREG_BYTE.
2494 Convert (subreg (mem)) to (mem) if not paradoxical.
2495 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2496 pseudo didn't get a hard reg, we must replace this with the
2497 eliminated version of the memory location because push_reload
2498 may do the replacement in certain circumstances. */
2499 if (GET_CODE (SUBREG_REG (x)) == REG
2500 && (GET_MODE_SIZE (GET_MODE (x))
2501 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2502 && reg_equiv_memory_loc != 0
2503 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2505 new = SUBREG_REG (x);
2508 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2510 if (new != SUBREG_REG (x))
2512 int x_size = GET_MODE_SIZE (GET_MODE (x));
2513 int new_size = GET_MODE_SIZE (GET_MODE (new));
2515 if (GET_CODE (new) == MEM
2516 && ((x_size < new_size
2517 #ifdef WORD_REGISTER_OPERATIONS
2518 /* On these machines, combine can create rtl of the form
2519 (set (subreg:m1 (reg:m2 R) 0) ...)
2520 where m1 < m2, and expects something interesting to
2521 happen to the entire word. Moreover, it will use the
2522 (reg:m2 R) later, expecting all bits to be preserved.
2523 So if the number of words is the same, preserve the
2524 subreg so that push_reload can see it. */
2525 && ! ((x_size - 1) / UNITS_PER_WORD
2526 == (new_size -1 ) / UNITS_PER_WORD)
2529 || x_size == new_size)
2531 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2533 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2539 /* This is only for the benefit of the debugging backends, which call
2540 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2541 removed after CSE. */
2542 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2543 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2545 /* Our only special processing is to pass the mode of the MEM to our
2546 recursive call and copy the flags. While we are here, handle this
2547 case more efficiently. */
2549 replace_equiv_address_nv (x,
2550 eliminate_regs (XEXP (x, 0),
2551 GET_MODE (x), insn));
2554 /* Handle insn_list USE that a call to a pure function may generate. */
2555 new = eliminate_regs (XEXP (x, 0), 0, insn);
2556 if (new != XEXP (x, 0))
2557 return gen_rtx_USE (GET_MODE (x), new);
2569 /* Process each of our operands recursively. If any have changed, make a
2571 fmt = GET_RTX_FORMAT (code);
2572 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2576 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2577 if (new != XEXP (x, i) && ! copied)
2579 rtx new_x = rtx_alloc (code);
2580 memcpy (new_x, x, RTX_SIZE (code));
2586 else if (*fmt == 'E')
2589 for (j = 0; j < XVECLEN (x, i); j++)
2591 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2592 if (new != XVECEXP (x, i, j) && ! copied_vec)
2594 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2598 rtx new_x = rtx_alloc (code);
2599 memcpy (new_x, x, RTX_SIZE (code));
2603 XVEC (x, i) = new_v;
2606 XVECEXP (x, i, j) = new;
2614 /* Scan rtx X for modifications of elimination target registers. Update
2615 the table of eliminables to reflect the changed state. MEM_MODE is
2616 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2619 elimination_effects (rtx x, enum machine_mode mem_mode)
2621 enum rtx_code code = GET_CODE (x);
2622 struct elim_table *ep;
2649 /* First handle the case where we encounter a bare register that
2650 is eliminable. Replace it with a PLUS. */
2651 if (regno < FIRST_PSEUDO_REGISTER)
2653 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2655 if (ep->from_rtx == x && ep->can_eliminate)
2658 ep->ref_outside_mem = 1;
2663 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2664 && reg_equiv_constant[regno]
2665 && ! function_invariant_p (reg_equiv_constant[regno]))
2666 elimination_effects (reg_equiv_constant[regno], mem_mode);
2675 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2676 if (ep->to_rtx == XEXP (x, 0))
2678 int size = GET_MODE_SIZE (mem_mode);
2680 /* If more bytes than MEM_MODE are pushed, account for them. */
2681 #ifdef PUSH_ROUNDING
2682 if (ep->to_rtx == stack_pointer_rtx)
2683 size = PUSH_ROUNDING (size);
2685 if (code == PRE_DEC || code == POST_DEC)
2687 else if (code == PRE_INC || code == POST_INC)
2689 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2690 && GET_CODE (XEXP (x, 1)) == PLUS
2691 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2692 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2693 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2696 /* These two aren't unary operators. */
2697 if (code == POST_MODIFY || code == PRE_MODIFY)
2700 /* Fall through to generic unary operation case. */
2701 case STRICT_LOW_PART:
2703 case SIGN_EXTEND: case ZERO_EXTEND:
2704 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2705 case FLOAT: case FIX:
2706 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2714 elimination_effects (XEXP (x, 0), mem_mode);
2718 if (GET_CODE (SUBREG_REG (x)) == REG
2719 && (GET_MODE_SIZE (GET_MODE (x))
2720 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2721 && reg_equiv_memory_loc != 0
2722 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2725 elimination_effects (SUBREG_REG (x), mem_mode);
2729 /* If using a register that is the source of an eliminate we still
2730 think can be performed, note it cannot be performed since we don't
2731 know how this register is used. */
2732 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2733 if (ep->from_rtx == XEXP (x, 0))
2734 ep->can_eliminate = 0;
2736 elimination_effects (XEXP (x, 0), mem_mode);
2740 /* If clobbering a register that is the replacement register for an
2741 elimination we still think can be performed, note that it cannot
2742 be performed. Otherwise, we need not be concerned about it. */
2743 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2744 if (ep->to_rtx == XEXP (x, 0))
2745 ep->can_eliminate = 0;
2747 elimination_effects (XEXP (x, 0), mem_mode);
2751 /* Check for setting a register that we know about. */
2752 if (GET_CODE (SET_DEST (x)) == REG)
2754 /* See if this is setting the replacement register for an
2757 If DEST is the hard frame pointer, we do nothing because we
2758 assume that all assignments to the frame pointer are for
2759 non-local gotos and are being done at a time when they are valid
2760 and do not disturb anything else. Some machines want to
2761 eliminate a fake argument pointer (or even a fake frame pointer)
2762 with either the real frame or the stack pointer. Assignments to
2763 the hard frame pointer must not prevent this elimination. */
2765 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2767 if (ep->to_rtx == SET_DEST (x)
2768 && SET_DEST (x) != hard_frame_pointer_rtx)
2770 /* If it is being incremented, adjust the offset. Otherwise,
2771 this elimination can't be done. */
2772 rtx src = SET_SRC (x);
2774 if (GET_CODE (src) == PLUS
2775 && XEXP (src, 0) == SET_DEST (x)
2776 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2777 ep->offset -= INTVAL (XEXP (src, 1));
2779 ep->can_eliminate = 0;
2783 elimination_effects (SET_DEST (x), 0);
2784 elimination_effects (SET_SRC (x), 0);
2788 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2791 /* Our only special processing is to pass the mode of the MEM to our
2793 elimination_effects (XEXP (x, 0), GET_MODE (x));
2800 fmt = GET_RTX_FORMAT (code);
2801 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2804 elimination_effects (XEXP (x, i), mem_mode);
2805 else if (*fmt == 'E')
2806 for (j = 0; j < XVECLEN (x, i); j++)
2807 elimination_effects (XVECEXP (x, i, j), mem_mode);
2811 /* Descend through rtx X and verify that no references to eliminable registers
2812 remain. If any do remain, mark the involved register as not
2816 check_eliminable_occurrences (rtx x)
2825 code = GET_CODE (x);
2827 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2829 struct elim_table *ep;
2831 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2832 if (ep->from_rtx == x && ep->can_eliminate)
2833 ep->can_eliminate = 0;
2837 fmt = GET_RTX_FORMAT (code);
2838 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2841 check_eliminable_occurrences (XEXP (x, i));
2842 else if (*fmt == 'E')
2845 for (j = 0; j < XVECLEN (x, i); j++)
2846 check_eliminable_occurrences (XVECEXP (x, i, j));
2851 /* Scan INSN and eliminate all eliminable registers in it.
2853 If REPLACE is nonzero, do the replacement destructively. Also
2854 delete the insn as dead it if it is setting an eliminable register.
2856 If REPLACE is zero, do all our allocations in reload_obstack.
2858 If no eliminations were done and this insn doesn't require any elimination
2859 processing (these are not identical conditions: it might be updating sp,
2860 but not referencing fp; this needs to be seen during reload_as_needed so
2861 that the offset between fp and sp can be taken into consideration), zero
2862 is returned. Otherwise, 1 is returned. */
2865 eliminate_regs_in_insn (rtx insn, int replace)
2867 int icode = recog_memoized (insn);
2868 rtx old_body = PATTERN (insn);
2869 int insn_is_asm = asm_noperands (old_body) >= 0;
2870 rtx old_set = single_set (insn);
2874 rtx substed_operand[MAX_RECOG_OPERANDS];
2875 rtx orig_operand[MAX_RECOG_OPERANDS];
2876 struct elim_table *ep;
2878 if (! insn_is_asm && icode < 0)
2880 if (GET_CODE (PATTERN (insn)) == USE
2881 || GET_CODE (PATTERN (insn)) == CLOBBER
2882 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2883 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2884 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2889 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2890 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2892 /* Check for setting an eliminable register. */
2893 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2894 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2896 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2897 /* If this is setting the frame pointer register to the
2898 hardware frame pointer register and this is an elimination
2899 that will be done (tested above), this insn is really
2900 adjusting the frame pointer downward to compensate for
2901 the adjustment done before a nonlocal goto. */
2902 if (ep->from == FRAME_POINTER_REGNUM
2903 && ep->to == HARD_FRAME_POINTER_REGNUM)
2905 rtx base = SET_SRC (old_set);
2906 rtx base_insn = insn;
2907 HOST_WIDE_INT offset = 0;
2909 while (base != ep->to_rtx)
2911 rtx prev_insn, prev_set;
2913 if (GET_CODE (base) == PLUS
2914 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2916 offset += INTVAL (XEXP (base, 1));
2917 base = XEXP (base, 0);
2919 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2920 && (prev_set = single_set (prev_insn)) != 0
2921 && rtx_equal_p (SET_DEST (prev_set), base))
2923 base = SET_SRC (prev_set);
2924 base_insn = prev_insn;
2930 if (base == ep->to_rtx)
2933 = plus_constant (ep->to_rtx, offset - ep->offset);
2935 new_body = old_body;
2938 new_body = copy_insn (old_body);
2939 if (REG_NOTES (insn))
2940 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2942 PATTERN (insn) = new_body;
2943 old_set = single_set (insn);
2945 /* First see if this insn remains valid when we
2946 make the change. If not, keep the INSN_CODE
2947 the same and let reload fit it up. */
2948 validate_change (insn, &SET_SRC (old_set), src, 1);
2949 validate_change (insn, &SET_DEST (old_set),
2951 if (! apply_change_group ())
2953 SET_SRC (old_set) = src;
2954 SET_DEST (old_set) = ep->to_rtx;
2963 /* In this case this insn isn't serving a useful purpose. We
2964 will delete it in reload_as_needed once we know that this
2965 elimination is, in fact, being done.
2967 If REPLACE isn't set, we can't delete this insn, but needn't
2968 process it since it won't be used unless something changes. */
2971 delete_dead_insn (insn);
2979 /* We allow one special case which happens to work on all machines we
2980 currently support: a single set with the source being a PLUS of an
2981 eliminable register and a constant. */
2983 && GET_CODE (SET_DEST (old_set)) == REG
2984 && GET_CODE (SET_SRC (old_set)) == PLUS
2985 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
2986 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
2987 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
2989 rtx reg = XEXP (SET_SRC (old_set), 0);
2990 HOST_WIDE_INT offset = INTVAL (XEXP (SET_SRC (old_set), 1));
2992 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2993 if (ep->from_rtx == reg && ep->can_eliminate)
2995 offset += ep->offset;
3000 /* We assume here that if we need a PARALLEL with
3001 CLOBBERs for this assignment, we can do with the
3002 MATCH_SCRATCHes that add_clobbers allocates.
3003 There's not much we can do if that doesn't work. */
3004 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3008 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3011 rtvec vec = rtvec_alloc (num_clobbers + 1);
3013 vec->elem[0] = PATTERN (insn);
3014 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3015 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3017 if (INSN_CODE (insn) < 0)
3022 new_body = old_body;
3025 new_body = copy_insn (old_body);
3026 if (REG_NOTES (insn))
3027 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3029 PATTERN (insn) = new_body;
3030 old_set = single_set (insn);
3032 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3033 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3036 /* This can't have an effect on elimination offsets, so skip right
3042 /* Determine the effects of this insn on elimination offsets. */
3043 elimination_effects (old_body, 0);
3045 /* Eliminate all eliminable registers occurring in operands that
3046 can be handled by reload. */
3047 extract_insn (insn);
3048 for (i = 0; i < recog_data.n_operands; i++)
3050 orig_operand[i] = recog_data.operand[i];
3051 substed_operand[i] = recog_data.operand[i];
3053 /* For an asm statement, every operand is eliminable. */
3054 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3056 /* Check for setting a register that we know about. */
3057 if (recog_data.operand_type[i] != OP_IN
3058 && GET_CODE (orig_operand[i]) == REG)
3060 /* If we are assigning to a register that can be eliminated, it
3061 must be as part of a PARALLEL, since the code above handles
3062 single SETs. We must indicate that we can no longer
3063 eliminate this reg. */
3064 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3066 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3067 ep->can_eliminate = 0;
3070 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3071 replace ? insn : NULL_RTX);
3072 if (substed_operand[i] != orig_operand[i])
3074 /* Terminate the search in check_eliminable_occurrences at
3076 *recog_data.operand_loc[i] = 0;
3078 /* If an output operand changed from a REG to a MEM and INSN is an
3079 insn, write a CLOBBER insn. */
3080 if (recog_data.operand_type[i] != OP_IN
3081 && GET_CODE (orig_operand[i]) == REG
3082 && GET_CODE (substed_operand[i]) == MEM
3084 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3089 for (i = 0; i < recog_data.n_dups; i++)
3090 *recog_data.dup_loc[i]
3091 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3093 /* If any eliminable remain, they aren't eliminable anymore. */
3094 check_eliminable_occurrences (old_body);
3096 /* Substitute the operands; the new values are in the substed_operand
3098 for (i = 0; i < recog_data.n_operands; i++)
3099 *recog_data.operand_loc[i] = substed_operand[i];
3100 for (i = 0; i < recog_data.n_dups; i++)
3101 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3103 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3104 re-recognize the insn. We do this in case we had a simple addition
3105 but now can do this as a load-address. This saves an insn in this
3107 If re-recognition fails, the old insn code number will still be used,
3108 and some register operands may have changed into PLUS expressions.
3109 These will be handled by find_reloads by loading them into a register
3114 /* If we aren't replacing things permanently and we changed something,
3115 make another copy to ensure that all the RTL is new. Otherwise
3116 things can go wrong if find_reload swaps commutative operands
3117 and one is inside RTL that has been copied while the other is not. */
3118 new_body = old_body;
3121 new_body = copy_insn (old_body);
3122 if (REG_NOTES (insn))
3123 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3125 PATTERN (insn) = new_body;
3127 /* If we had a move insn but now we don't, rerecognize it. This will
3128 cause spurious re-recognition if the old move had a PARALLEL since
3129 the new one still will, but we can't call single_set without
3130 having put NEW_BODY into the insn and the re-recognition won't
3131 hurt in this rare case. */
3132 /* ??? Why this huge if statement - why don't we just rerecognize the
3136 && ((GET_CODE (SET_SRC (old_set)) == REG
3137 && (GET_CODE (new_body) != SET
3138 || GET_CODE (SET_SRC (new_body)) != REG))
3139 /* If this was a load from or store to memory, compare
3140 the MEM in recog_data.operand to the one in the insn.
3141 If they are not equal, then rerecognize the insn. */
3143 && ((GET_CODE (SET_SRC (old_set)) == MEM
3144 && SET_SRC (old_set) != recog_data.operand[1])
3145 || (GET_CODE (SET_DEST (old_set)) == MEM
3146 && SET_DEST (old_set) != recog_data.operand[0])))
3147 /* If this was an add insn before, rerecognize. */
3148 || GET_CODE (SET_SRC (old_set)) == PLUS))
3150 int new_icode = recog (PATTERN (insn), insn, 0);
3152 INSN_CODE (insn) = icode;
3156 /* Restore the old body. If there were any changes to it, we made a copy
3157 of it while the changes were still in place, so we'll correctly return
3158 a modified insn below. */
3161 /* Restore the old body. */
3162 for (i = 0; i < recog_data.n_operands; i++)
3163 *recog_data.operand_loc[i] = orig_operand[i];
3164 for (i = 0; i < recog_data.n_dups; i++)
3165 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3168 /* Update all elimination pairs to reflect the status after the current
3169 insn. The changes we make were determined by the earlier call to
3170 elimination_effects.
3172 We also detect cases where register elimination cannot be done,
3173 namely, if a register would be both changed and referenced outside a MEM
3174 in the resulting insn since such an insn is often undefined and, even if
3175 not, we cannot know what meaning will be given to it. Note that it is
3176 valid to have a register used in an address in an insn that changes it
3177 (presumably with a pre- or post-increment or decrement).
3179 If anything changes, return nonzero. */
3181 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3183 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3184 ep->can_eliminate = 0;
3186 ep->ref_outside_mem = 0;
3188 if (ep->previous_offset != ep->offset)
3193 /* If we changed something, perform elimination in REG_NOTES. This is
3194 needed even when REPLACE is zero because a REG_DEAD note might refer
3195 to a register that we eliminate and could cause a different number
3196 of spill registers to be needed in the final reload pass than in
3198 if (val && REG_NOTES (insn) != 0)
3199 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3204 /* Loop through all elimination pairs.
3205 Recalculate the number not at initial offset.
3207 Compute the maximum offset (minimum offset if the stack does not
3208 grow downward) for each elimination pair. */
3211 update_eliminable_offsets (void)
3213 struct elim_table *ep;
3215 num_not_at_initial_offset = 0;
3216 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3218 ep->previous_offset = ep->offset;
3219 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3220 num_not_at_initial_offset++;
3224 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3225 replacement we currently believe is valid, mark it as not eliminable if X
3226 modifies DEST in any way other than by adding a constant integer to it.
3228 If DEST is the frame pointer, we do nothing because we assume that
3229 all assignments to the hard frame pointer are nonlocal gotos and are being
3230 done at a time when they are valid and do not disturb anything else.
3231 Some machines want to eliminate a fake argument pointer with either the
3232 frame or stack pointer. Assignments to the hard frame pointer must not
3233 prevent this elimination.
3235 Called via note_stores from reload before starting its passes to scan
3236 the insns of the function. */
3239 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3243 /* A SUBREG of a hard register here is just changing its mode. We should
3244 not see a SUBREG of an eliminable hard register, but check just in
3246 if (GET_CODE (dest) == SUBREG)
3247 dest = SUBREG_REG (dest);
3249 if (dest == hard_frame_pointer_rtx)
3252 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3253 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3254 && (GET_CODE (x) != SET
3255 || GET_CODE (SET_SRC (x)) != PLUS
3256 || XEXP (SET_SRC (x), 0) != dest
3257 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3259 reg_eliminate[i].can_eliminate_previous
3260 = reg_eliminate[i].can_eliminate = 0;
3265 /* Verify that the initial elimination offsets did not change since the
3266 last call to set_initial_elim_offsets. This is used to catch cases
3267 where something illegal happened during reload_as_needed that could
3268 cause incorrect code to be generated if we did not check for it. */
3271 verify_initial_elim_offsets (void)
3275 #ifdef ELIMINABLE_REGS
3276 struct elim_table *ep;
3278 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3280 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3281 if (t != ep->initial_offset)
3285 INITIAL_FRAME_POINTER_OFFSET (t);
3286 if (t != reg_eliminate[0].initial_offset)
3291 /* Reset all offsets on eliminable registers to their initial values. */
3294 set_initial_elim_offsets (void)
3296 struct elim_table *ep = reg_eliminate;
3298 #ifdef ELIMINABLE_REGS
3299 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3301 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3302 ep->previous_offset = ep->offset = ep->initial_offset;
3305 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3306 ep->previous_offset = ep->offset = ep->initial_offset;
3309 num_not_at_initial_offset = 0;
3312 /* Initialize the known label offsets.
3313 Set a known offset for each forced label to be at the initial offset
3314 of each elimination. We do this because we assume that all
3315 computed jumps occur from a location where each elimination is
3316 at its initial offset.
3317 For all other labels, show that we don't know the offsets. */
3320 set_initial_label_offsets (void)
3323 memset (offsets_known_at, 0, num_labels);
3325 for (x = forced_labels; x; x = XEXP (x, 1))
3327 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3330 /* Set all elimination offsets to the known values for the code label given
3334 set_offsets_for_label (rtx insn)
3337 int label_nr = CODE_LABEL_NUMBER (insn);
3338 struct elim_table *ep;
3340 num_not_at_initial_offset = 0;
3341 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3343 ep->offset = ep->previous_offset
3344 = offsets_at[label_nr - first_label_num][i];
3345 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3346 num_not_at_initial_offset++;
3350 /* See if anything that happened changes which eliminations are valid.
3351 For example, on the SPARC, whether or not the frame pointer can
3352 be eliminated can depend on what registers have been used. We need
3353 not check some conditions again (such as flag_omit_frame_pointer)
3354 since they can't have changed. */
3357 update_eliminables (HARD_REG_SET *pset)
3359 int previous_frame_pointer_needed = frame_pointer_needed;
3360 struct elim_table *ep;
3362 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3363 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3364 #ifdef ELIMINABLE_REGS
3365 || ! CAN_ELIMINATE (ep->from, ep->to)
3368 ep->can_eliminate = 0;
3370 /* Look for the case where we have discovered that we can't replace
3371 register A with register B and that means that we will now be
3372 trying to replace register A with register C. This means we can
3373 no longer replace register C with register B and we need to disable
3374 such an elimination, if it exists. This occurs often with A == ap,
3375 B == sp, and C == fp. */
3377 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3379 struct elim_table *op;
3382 if (! ep->can_eliminate && ep->can_eliminate_previous)
3384 /* Find the current elimination for ep->from, if there is a
3386 for (op = reg_eliminate;
3387 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3388 if (op->from == ep->from && op->can_eliminate)
3394 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3396 for (op = reg_eliminate;
3397 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3398 if (op->from == new_to && op->to == ep->to)
3399 op->can_eliminate = 0;
3403 /* See if any registers that we thought we could eliminate the previous
3404 time are no longer eliminable. If so, something has changed and we
3405 must spill the register. Also, recompute the number of eliminable
3406 registers and see if the frame pointer is needed; it is if there is
3407 no elimination of the frame pointer that we can perform. */
3409 frame_pointer_needed = 1;
3410 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3412 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3413 && ep->to != HARD_FRAME_POINTER_REGNUM)
3414 frame_pointer_needed = 0;
3416 if (! ep->can_eliminate && ep->can_eliminate_previous)
3418 ep->can_eliminate_previous = 0;
3419 SET_HARD_REG_BIT (*pset, ep->from);
3424 /* If we didn't need a frame pointer last time, but we do now, spill
3425 the hard frame pointer. */
3426 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3427 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3430 /* Initialize the table of registers to eliminate. */
3433 init_elim_table (void)
3435 struct elim_table *ep;
3436 #ifdef ELIMINABLE_REGS
3437 const struct elim_table_1 *ep1;
3441 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3443 /* Does this function require a frame pointer? */
3445 frame_pointer_needed = (! flag_omit_frame_pointer
3446 #ifdef EXIT_IGNORE_STACK
3447 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3448 and restore sp for alloca. So we can't eliminate
3449 the frame pointer in that case. At some point,
3450 we should improve this by emitting the
3451 sp-adjusting insns for this case. */
3452 || (current_function_calls_alloca
3453 && EXIT_IGNORE_STACK)
3455 || FRAME_POINTER_REQUIRED);
3459 #ifdef ELIMINABLE_REGS
3460 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3461 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3463 ep->from = ep1->from;
3465 ep->can_eliminate = ep->can_eliminate_previous
3466 = (CAN_ELIMINATE (ep->from, ep->to)
3467 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3470 reg_eliminate[0].from = reg_eliminate_1[0].from;
3471 reg_eliminate[0].to = reg_eliminate_1[0].to;
3472 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3473 = ! frame_pointer_needed;
3476 /* Count the number of eliminable registers and build the FROM and TO
3477 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3478 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3479 We depend on this. */
3480 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3482 num_eliminable += ep->can_eliminate;
3483 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3484 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3488 /* Kick all pseudos out of hard register REGNO.
3490 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3491 because we found we can't eliminate some register. In the case, no pseudos
3492 are allowed to be in the register, even if they are only in a block that
3493 doesn't require spill registers, unlike the case when we are spilling this
3494 hard reg to produce another spill register.
3496 Return nonzero if any pseudos needed to be kicked out. */
3499 spill_hard_reg (unsigned int regno, int cant_eliminate)
3505 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3506 regs_ever_live[regno] = 1;
3509 /* Spill every pseudo reg that was allocated to this reg
3510 or to something that overlaps this reg. */
3512 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3513 if (reg_renumber[i] >= 0
3514 && (unsigned int) reg_renumber[i] <= regno
3515 && ((unsigned int) reg_renumber[i]
3516 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3517 PSEUDO_REGNO_MODE (i))
3519 SET_REGNO_REG_SET (&spilled_pseudos, i);
3522 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3523 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3526 ior_hard_reg_set (HARD_REG_SET *set1, HARD_REG_SET *set2)
3528 IOR_HARD_REG_SET (*set1, *set2);
3531 /* After find_reload_regs has been run for all insn that need reloads,
3532 and/or spill_hard_regs was called, this function is used to actually
3533 spill pseudo registers and try to reallocate them. It also sets up the
3534 spill_regs array for use by choose_reload_regs. */
3537 finish_spills (int global)
3539 struct insn_chain *chain;
3540 int something_changed = 0;
3543 /* Build the spill_regs array for the function. */
3544 /* If there are some registers still to eliminate and one of the spill regs
3545 wasn't ever used before, additional stack space may have to be
3546 allocated to store this register. Thus, we may have changed the offset
3547 between the stack and frame pointers, so mark that something has changed.
3549 One might think that we need only set VAL to 1 if this is a call-used
3550 register. However, the set of registers that must be saved by the
3551 prologue is not identical to the call-used set. For example, the
3552 register used by the call insn for the return PC is a call-used register,
3553 but must be saved by the prologue. */
3556 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3557 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3559 spill_reg_order[i] = n_spills;
3560 spill_regs[n_spills++] = i;
3561 if (num_eliminable && ! regs_ever_live[i])
3562 something_changed = 1;
3563 regs_ever_live[i] = 1;
3566 spill_reg_order[i] = -1;
3568 EXECUTE_IF_SET_IN_REG_SET
3569 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3571 /* Record the current hard register the pseudo is allocated to in
3572 pseudo_previous_regs so we avoid reallocating it to the same
3573 hard reg in a later pass. */
3574 if (reg_renumber[i] < 0)
3577 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3578 /* Mark it as no longer having a hard register home. */
3579 reg_renumber[i] = -1;
3580 /* We will need to scan everything again. */
3581 something_changed = 1;
3584 /* Retry global register allocation if possible. */
3587 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3588 /* For every insn that needs reloads, set the registers used as spill
3589 regs in pseudo_forbidden_regs for every pseudo live across the
3591 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3593 EXECUTE_IF_SET_IN_REG_SET
3594 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3596 ior_hard_reg_set (pseudo_forbidden_regs + i,
3597 &chain->used_spill_regs);
3599 EXECUTE_IF_SET_IN_REG_SET
3600 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3602 ior_hard_reg_set (pseudo_forbidden_regs + i,
3603 &chain->used_spill_regs);
3607 /* Retry allocating the spilled pseudos. For each reg, merge the
3608 various reg sets that indicate which hard regs can't be used,
3609 and call retry_global_alloc.
3610 We change spill_pseudos here to only contain pseudos that did not
3611 get a new hard register. */
3612 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3613 if (reg_old_renumber[i] != reg_renumber[i])
3615 HARD_REG_SET forbidden;
3616 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3617 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3618 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3619 retry_global_alloc (i, forbidden);
3620 if (reg_renumber[i] >= 0)
3621 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3625 /* Fix up the register information in the insn chain.
3626 This involves deleting those of the spilled pseudos which did not get
3627 a new hard register home from the live_{before,after} sets. */
3628 for (chain = reload_insn_chain; chain; chain = chain->next)
3630 HARD_REG_SET used_by_pseudos;
3631 HARD_REG_SET used_by_pseudos2;
3633 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3634 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3636 /* Mark any unallocated hard regs as available for spills. That
3637 makes inheritance work somewhat better. */
3638 if (chain->need_reload)
3640 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3641 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3642 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3644 /* Save the old value for the sanity test below. */
3645 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3647 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3648 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3649 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3650 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3652 /* Make sure we only enlarge the set. */
3653 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3659 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3660 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3662 int regno = reg_renumber[i];
3663 if (reg_old_renumber[i] == regno)
3666 alter_reg (i, reg_old_renumber[i]);
3667 reg_old_renumber[i] = regno;
3671 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3673 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3674 i, reg_renumber[i]);
3678 return something_changed;
3681 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3682 Also mark any hard registers used to store user variables as
3683 forbidden from being used for spill registers. */
3686 scan_paradoxical_subregs (rtx x)
3690 enum rtx_code code = GET_CODE (x);
3696 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3697 && REG_USERVAR_P (x))
3698 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3707 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3715 if (GET_CODE (SUBREG_REG (x)) == REG
3716 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3717 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3718 = GET_MODE_SIZE (GET_MODE (x));
3725 fmt = GET_RTX_FORMAT (code);
3726 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3729 scan_paradoxical_subregs (XEXP (x, i));
3730 else if (fmt[i] == 'E')
3733 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3734 scan_paradoxical_subregs (XVECEXP (x, i, j));
3739 /* Reload pseudo-registers into hard regs around each insn as needed.
3740 Additional register load insns are output before the insn that needs it
3741 and perhaps store insns after insns that modify the reloaded pseudo reg.
3743 reg_last_reload_reg and reg_reloaded_contents keep track of
3744 which registers are already available in reload registers.
3745 We update these for the reloads that we perform,
3746 as the insns are scanned. */
3749 reload_as_needed (int live_known)
3751 struct insn_chain *chain;
3752 #if defined (AUTO_INC_DEC)
3757 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3758 memset (spill_reg_store, 0, sizeof spill_reg_store);
3759 reg_last_reload_reg = xcalloc (max_regno, sizeof (rtx));
3760 reg_has_output_reload = xmalloc (max_regno);
3761 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3763 set_initial_elim_offsets ();
3765 for (chain = reload_insn_chain; chain; chain = chain->next)
3768 rtx insn = chain->insn;
3769 rtx old_next = NEXT_INSN (insn);
3771 /* If we pass a label, copy the offsets from the label information
3772 into the current offsets of each elimination. */
3773 if (GET_CODE (insn) == CODE_LABEL)
3774 set_offsets_for_label (insn);
3776 else if (INSN_P (insn))
3778 rtx oldpat = copy_rtx (PATTERN (insn));
3780 /* If this is a USE and CLOBBER of a MEM, ensure that any
3781 references to eliminable registers have been removed. */
3783 if ((GET_CODE (PATTERN (insn)) == USE
3784 || GET_CODE (PATTERN (insn)) == CLOBBER)
3785 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3786 XEXP (XEXP (PATTERN (insn), 0), 0)
3787 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3788 GET_MODE (XEXP (PATTERN (insn), 0)),
3791 /* If we need to do register elimination processing, do so.
3792 This might delete the insn, in which case we are done. */
3793 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3795 eliminate_regs_in_insn (insn, 1);
3796 if (GET_CODE (insn) == NOTE)
3798 update_eliminable_offsets ();
3803 /* If need_elim is nonzero but need_reload is zero, one might think
3804 that we could simply set n_reloads to 0. However, find_reloads
3805 could have done some manipulation of the insn (such as swapping
3806 commutative operands), and these manipulations are lost during
3807 the first pass for every insn that needs register elimination.
3808 So the actions of find_reloads must be redone here. */
3810 if (! chain->need_elim && ! chain->need_reload
3811 && ! chain->need_operand_change)
3813 /* First find the pseudo regs that must be reloaded for this insn.
3814 This info is returned in the tables reload_... (see reload.h).
3815 Also modify the body of INSN by substituting RELOAD
3816 rtx's for those pseudo regs. */
3819 memset (reg_has_output_reload, 0, max_regno);
3820 CLEAR_HARD_REG_SET (reg_is_output_reload);
3822 find_reloads (insn, 1, spill_indirect_levels, live_known,
3828 rtx next = NEXT_INSN (insn);
3831 prev = PREV_INSN (insn);
3833 /* Now compute which reload regs to reload them into. Perhaps
3834 reusing reload regs from previous insns, or else output
3835 load insns to reload them. Maybe output store insns too.
3836 Record the choices of reload reg in reload_reg_rtx. */
3837 choose_reload_regs (chain);
3839 /* Merge any reloads that we didn't combine for fear of
3840 increasing the number of spill registers needed but now
3841 discover can be safely merged. */
3842 if (SMALL_REGISTER_CLASSES)
3843 merge_assigned_reloads (insn);
3845 /* Generate the insns to reload operands into or out of
3846 their reload regs. */
3847 emit_reload_insns (chain);
3849 /* Substitute the chosen reload regs from reload_reg_rtx
3850 into the insn's body (or perhaps into the bodies of other
3851 load and store insn that we just made for reloading
3852 and that we moved the structure into). */
3853 subst_reloads (insn);
3855 /* If this was an ASM, make sure that all the reload insns
3856 we have generated are valid. If not, give an error
3859 if (asm_noperands (PATTERN (insn)) >= 0)
3860 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3861 if (p != insn && INSN_P (p)
3862 && GET_CODE (PATTERN (p)) != USE
3863 && (recog_memoized (p) < 0
3864 || (extract_insn (p), ! constrain_operands (1))))
3866 error_for_asm (insn,
3867 "`asm' operand requires impossible reload");
3872 if (num_eliminable && chain->need_elim)
3873 update_eliminable_offsets ();
3875 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3876 is no longer validly lying around to save a future reload.
3877 Note that this does not detect pseudos that were reloaded
3878 for this insn in order to be stored in
3879 (obeying register constraints). That is correct; such reload
3880 registers ARE still valid. */
3881 note_stores (oldpat, forget_old_reloads_1, NULL);
3883 /* There may have been CLOBBER insns placed after INSN. So scan
3884 between INSN and NEXT and use them to forget old reloads. */
3885 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3886 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3887 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3890 /* Likewise for regs altered by auto-increment in this insn.
3891 REG_INC notes have been changed by reloading:
3892 find_reloads_address_1 records substitutions for them,
3893 which have been performed by subst_reloads above. */
3894 for (i = n_reloads - 1; i >= 0; i--)
3896 rtx in_reg = rld[i].in_reg;
3899 enum rtx_code code = GET_CODE (in_reg);
3900 /* PRE_INC / PRE_DEC will have the reload register ending up
3901 with the same value as the stack slot, but that doesn't
3902 hold true for POST_INC / POST_DEC. Either we have to
3903 convert the memory access to a true POST_INC / POST_DEC,
3904 or we can't use the reload register for inheritance. */
3905 if ((code == POST_INC || code == POST_DEC)
3906 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3907 REGNO (rld[i].reg_rtx))
3908 /* Make sure it is the inc/dec pseudo, and not
3909 some other (e.g. output operand) pseudo. */
3910 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3911 == REGNO (XEXP (in_reg, 0))))
3914 rtx reload_reg = rld[i].reg_rtx;
3915 enum machine_mode mode = GET_MODE (reload_reg);
3919 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3921 /* We really want to ignore REG_INC notes here, so
3922 use PATTERN (p) as argument to reg_set_p . */
3923 if (reg_set_p (reload_reg, PATTERN (p)))
3925 n = count_occurrences (PATTERN (p), reload_reg, 0);
3930 n = validate_replace_rtx (reload_reg,
3931 gen_rtx (code, mode,
3935 /* We must also verify that the constraints
3936 are met after the replacement. */
3939 n = constrain_operands (1);
3943 /* If the constraints were not met, then
3944 undo the replacement. */
3947 validate_replace_rtx (gen_rtx (code, mode,
3959 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3961 /* Mark this as having an output reload so that the
3962 REG_INC processing code below won't invalidate
3963 the reload for inheritance. */
3964 SET_HARD_REG_BIT (reg_is_output_reload,
3965 REGNO (reload_reg));
3966 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3969 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3972 else if ((code == PRE_INC || code == PRE_DEC)
3973 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3974 REGNO (rld[i].reg_rtx))
3975 /* Make sure it is the inc/dec pseudo, and not
3976 some other (e.g. output operand) pseudo. */
3977 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3978 == REGNO (XEXP (in_reg, 0))))
3980 SET_HARD_REG_BIT (reg_is_output_reload,
3981 REGNO (rld[i].reg_rtx));
3982 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3986 /* If a pseudo that got a hard register is auto-incremented,
3987 we must purge records of copying it into pseudos without
3989 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3990 if (REG_NOTE_KIND (x) == REG_INC)
3992 /* See if this pseudo reg was reloaded in this insn.
3993 If so, its last-reload info is still valid
3994 because it is based on this insn's reload. */
3995 for (i = 0; i < n_reloads; i++)
3996 if (rld[i].out == XEXP (x, 0))
4000 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4004 /* A reload reg's contents are unknown after a label. */
4005 if (GET_CODE (insn) == CODE_LABEL)
4006 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4008 /* Don't assume a reload reg is still good after a call insn
4009 if it is a call-used reg. */
4010 else if (GET_CODE (insn) == CALL_INSN)
4011 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4015 free (reg_last_reload_reg);
4016 free (reg_has_output_reload);
4019 /* Discard all record of any value reloaded from X,
4020 or reloaded in X from someplace else;
4021 unless X is an output reload reg of the current insn.
4023 X may be a hard reg (the reload reg)
4024 or it may be a pseudo reg that was reloaded from. */
4027 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4028 void *data ATTRIBUTE_UNUSED)
4033 /* note_stores does give us subregs of hard regs,
4034 subreg_regno_offset will abort if it is not a hard reg. */
4035 while (GET_CODE (x) == SUBREG)
4037 /* We ignore the subreg offset when calculating the regno,
4038 because we are using the entire underlying hard register
4043 if (GET_CODE (x) != REG)
4048 if (regno >= FIRST_PSEUDO_REGISTER)
4054 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4055 /* Storing into a spilled-reg invalidates its contents.
4056 This can happen if a block-local pseudo is allocated to that reg
4057 and it wasn't spilled because this block's total need is 0.
4058 Then some insn might have an optional reload and use this reg. */
4059 for (i = 0; i < nr; i++)
4060 /* But don't do this if the reg actually serves as an output
4061 reload reg in the current instruction. */
4063 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4065 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4066 spill_reg_store[regno + i] = 0;
4070 /* Since value of X has changed,
4071 forget any value previously copied from it. */
4074 /* But don't forget a copy if this is the output reload
4075 that establishes the copy's validity. */
4076 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4077 reg_last_reload_reg[regno + nr] = 0;
4080 /* The following HARD_REG_SETs indicate when each hard register is
4081 used for a reload of various parts of the current insn. */
4083 /* If reg is unavailable for all reloads. */
4084 static HARD_REG_SET reload_reg_unavailable;
4085 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4086 static HARD_REG_SET reload_reg_used;
4087 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4088 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4089 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4090 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4091 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4092 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4093 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4094 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4095 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4096 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4097 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4098 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4099 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4100 static HARD_REG_SET reload_reg_used_in_op_addr;
4101 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4102 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4103 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4104 static HARD_REG_SET reload_reg_used_in_insn;
4105 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4106 static HARD_REG_SET reload_reg_used_in_other_addr;
4108 /* If reg is in use as a reload reg for any sort of reload. */
4109 static HARD_REG_SET reload_reg_used_at_all;
4111 /* If reg is use as an inherited reload. We just mark the first register
4113 static HARD_REG_SET reload_reg_used_for_inherit;
4115 /* Records which hard regs are used in any way, either as explicit use or
4116 by being allocated to a pseudo during any point of the current insn. */
4117 static HARD_REG_SET reg_used_in_insn;
4119 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4120 TYPE. MODE is used to indicate how many consecutive regs are
4124 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4125 enum machine_mode mode)
4127 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4130 for (i = regno; i < nregs + regno; i++)
4135 SET_HARD_REG_BIT (reload_reg_used, i);
4138 case RELOAD_FOR_INPUT_ADDRESS:
4139 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4142 case RELOAD_FOR_INPADDR_ADDRESS:
4143 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4146 case RELOAD_FOR_OUTPUT_ADDRESS:
4147 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4150 case RELOAD_FOR_OUTADDR_ADDRESS:
4151 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4154 case RELOAD_FOR_OPERAND_ADDRESS:
4155 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4158 case RELOAD_FOR_OPADDR_ADDR:
4159 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4162 case RELOAD_FOR_OTHER_ADDRESS:
4163 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4166 case RELOAD_FOR_INPUT:
4167 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4170 case RELOAD_FOR_OUTPUT:
4171 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4174 case RELOAD_FOR_INSN:
4175 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4179 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4183 /* Similarly, but show REGNO is no longer in use for a reload. */
4186 clear_reload_reg_in_use (unsigned int regno, int opnum,
4187 enum reload_type type, enum machine_mode mode)
4189 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4190 unsigned int start_regno, end_regno, r;
4192 /* A complication is that for some reload types, inheritance might
4193 allow multiple reloads of the same types to share a reload register.
4194 We set check_opnum if we have to check only reloads with the same
4195 operand number, and check_any if we have to check all reloads. */
4196 int check_opnum = 0;
4198 HARD_REG_SET *used_in_set;
4203 used_in_set = &reload_reg_used;
4206 case RELOAD_FOR_INPUT_ADDRESS:
4207 used_in_set = &reload_reg_used_in_input_addr[opnum];
4210 case RELOAD_FOR_INPADDR_ADDRESS:
4212 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4215 case RELOAD_FOR_OUTPUT_ADDRESS:
4216 used_in_set = &reload_reg_used_in_output_addr[opnum];
4219 case RELOAD_FOR_OUTADDR_ADDRESS:
4221 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4224 case RELOAD_FOR_OPERAND_ADDRESS:
4225 used_in_set = &reload_reg_used_in_op_addr;
4228 case RELOAD_FOR_OPADDR_ADDR:
4230 used_in_set = &reload_reg_used_in_op_addr_reload;
4233 case RELOAD_FOR_OTHER_ADDRESS:
4234 used_in_set = &reload_reg_used_in_other_addr;
4238 case RELOAD_FOR_INPUT:
4239 used_in_set = &reload_reg_used_in_input[opnum];
4242 case RELOAD_FOR_OUTPUT:
4243 used_in_set = &reload_reg_used_in_output[opnum];
4246 case RELOAD_FOR_INSN:
4247 used_in_set = &reload_reg_used_in_insn;
4252 /* We resolve conflicts with remaining reloads of the same type by
4253 excluding the intervals of reload registers by them from the
4254 interval of freed reload registers. Since we only keep track of
4255 one set of interval bounds, we might have to exclude somewhat
4256 more than what would be necessary if we used a HARD_REG_SET here.
4257 But this should only happen very infrequently, so there should
4258 be no reason to worry about it. */
4260 start_regno = regno;
4261 end_regno = regno + nregs;
4262 if (check_opnum || check_any)
4264 for (i = n_reloads - 1; i >= 0; i--)
4266 if (rld[i].when_needed == type
4267 && (check_any || rld[i].opnum == opnum)
4270 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4271 unsigned int conflict_end
4273 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4275 /* If there is an overlap with the first to-be-freed register,
4276 adjust the interval start. */
4277 if (conflict_start <= start_regno && conflict_end > start_regno)
4278 start_regno = conflict_end;
4279 /* Otherwise, if there is a conflict with one of the other
4280 to-be-freed registers, adjust the interval end. */
4281 if (conflict_start > start_regno && conflict_start < end_regno)
4282 end_regno = conflict_start;
4287 for (r = start_regno; r < end_regno; r++)
4288 CLEAR_HARD_REG_BIT (*used_in_set, r);
4291 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4292 specified by OPNUM and TYPE. */
4295 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4299 /* In use for a RELOAD_OTHER means it's not available for anything. */
4300 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4301 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4307 /* In use for anything means we can't use it for RELOAD_OTHER. */
4308 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4309 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4310 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4313 for (i = 0; i < reload_n_operands; i++)
4314 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4315 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4316 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4317 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4318 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4319 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4324 case RELOAD_FOR_INPUT:
4325 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4326 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4329 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4332 /* If it is used for some other input, can't use it. */
4333 for (i = 0; i < reload_n_operands; i++)
4334 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4337 /* If it is used in a later operand's address, can't use it. */
4338 for (i = opnum + 1; i < reload_n_operands; i++)
4339 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4340 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4345 case RELOAD_FOR_INPUT_ADDRESS:
4346 /* Can't use a register if it is used for an input address for this
4347 operand or used as an input in an earlier one. */
4348 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4349 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4352 for (i = 0; i < opnum; i++)
4353 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4358 case RELOAD_FOR_INPADDR_ADDRESS:
4359 /* Can't use a register if it is used for an input address
4360 for this operand or used as an input in an earlier
4362 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4365 for (i = 0; i < opnum; i++)
4366 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4371 case RELOAD_FOR_OUTPUT_ADDRESS:
4372 /* Can't use a register if it is used for an output address for this
4373 operand or used as an output in this or a later operand. Note
4374 that multiple output operands are emitted in reverse order, so
4375 the conflicting ones are those with lower indices. */
4376 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4379 for (i = 0; i <= opnum; i++)
4380 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4385 case RELOAD_FOR_OUTADDR_ADDRESS:
4386 /* Can't use a register if it is used for an output address
4387 for this operand or used as an output in this or a
4388 later operand. Note that multiple output operands are
4389 emitted in reverse order, so the conflicting ones are
4390 those with lower indices. */
4391 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4394 for (i = 0; i <= opnum; i++)
4395 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4400 case RELOAD_FOR_OPERAND_ADDRESS:
4401 for (i = 0; i < reload_n_operands; i++)
4402 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4405 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4406 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4408 case RELOAD_FOR_OPADDR_ADDR:
4409 for (i = 0; i < reload_n_operands; i++)
4410 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4413 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4415 case RELOAD_FOR_OUTPUT:
4416 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4417 outputs, or an operand address for this or an earlier output.
4418 Note that multiple output operands are emitted in reverse order,
4419 so the conflicting ones are those with higher indices. */
4420 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4423 for (i = 0; i < reload_n_operands; i++)
4424 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4427 for (i = opnum; i < reload_n_operands; i++)
4428 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4429 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4434 case RELOAD_FOR_INSN:
4435 for (i = 0; i < reload_n_operands; i++)
4436 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4437 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4440 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4441 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4443 case RELOAD_FOR_OTHER_ADDRESS:
4444 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4449 /* Return 1 if the value in reload reg REGNO, as used by a reload
4450 needed for the part of the insn specified by OPNUM and TYPE,
4451 is still available in REGNO at the end of the insn.
4453 We can assume that the reload reg was already tested for availability
4454 at the time it is needed, and we should not check this again,
4455 in case the reg has already been marked in use. */
4458 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4465 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4466 its value must reach the end. */
4469 /* If this use is for part of the insn,
4470 its value reaches if no subsequent part uses the same register.
4471 Just like the above function, don't try to do this with lots
4474 case RELOAD_FOR_OTHER_ADDRESS:
4475 /* Here we check for everything else, since these don't conflict
4476 with anything else and everything comes later. */
4478 for (i = 0; i < reload_n_operands; i++)
4479 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4480 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4481 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4482 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4483 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4484 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4487 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4488 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4489 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4491 case RELOAD_FOR_INPUT_ADDRESS:
4492 case RELOAD_FOR_INPADDR_ADDRESS:
4493 /* Similar, except that we check only for this and subsequent inputs
4494 and the address of only subsequent inputs and we do not need
4495 to check for RELOAD_OTHER objects since they are known not to
4498 for (i = opnum; i < reload_n_operands; i++)
4499 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4502 for (i = opnum + 1; i < reload_n_operands; i++)
4503 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4504 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4507 for (i = 0; i < reload_n_operands; i++)
4508 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4509 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4510 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4513 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4516 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4517 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4518 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4520 case RELOAD_FOR_INPUT:
4521 /* Similar to input address, except we start at the next operand for
4522 both input and input address and we do not check for
4523 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4526 for (i = opnum + 1; i < reload_n_operands; i++)
4527 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4528 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4529 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4532 /* ... fall through ... */
4534 case RELOAD_FOR_OPERAND_ADDRESS:
4535 /* Check outputs and their addresses. */
4537 for (i = 0; i < reload_n_operands; i++)
4538 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4539 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4540 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4543 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4545 case RELOAD_FOR_OPADDR_ADDR:
4546 for (i = 0; i < reload_n_operands; i++)
4547 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4548 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4549 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4552 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4553 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4554 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4556 case RELOAD_FOR_INSN:
4557 /* These conflict with other outputs with RELOAD_OTHER. So
4558 we need only check for output addresses. */
4560 opnum = reload_n_operands;
4562 /* ... fall through ... */
4564 case RELOAD_FOR_OUTPUT:
4565 case RELOAD_FOR_OUTPUT_ADDRESS:
4566 case RELOAD_FOR_OUTADDR_ADDRESS:
4567 /* We already know these can't conflict with a later output. So the
4568 only thing to check are later output addresses.
4569 Note that multiple output operands are emitted in reverse order,
4570 so the conflicting ones are those with lower indices. */
4571 for (i = 0; i < opnum; i++)
4572 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4573 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4582 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4585 This function uses the same algorithm as reload_reg_free_p above. */
4588 reloads_conflict (int r1, int r2)
4590 enum reload_type r1_type = rld[r1].when_needed;
4591 enum reload_type r2_type = rld[r2].when_needed;
4592 int r1_opnum = rld[r1].opnum;
4593 int r2_opnum = rld[r2].opnum;
4595 /* RELOAD_OTHER conflicts with everything. */
4596 if (r2_type == RELOAD_OTHER)
4599 /* Otherwise, check conflicts differently for each type. */
4603 case RELOAD_FOR_INPUT:
4604 return (r2_type == RELOAD_FOR_INSN
4605 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4606 || r2_type == RELOAD_FOR_OPADDR_ADDR
4607 || r2_type == RELOAD_FOR_INPUT
4608 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4609 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4610 && r2_opnum > r1_opnum));
4612 case RELOAD_FOR_INPUT_ADDRESS:
4613 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4614 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4616 case RELOAD_FOR_INPADDR_ADDRESS:
4617 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4618 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4620 case RELOAD_FOR_OUTPUT_ADDRESS:
4621 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4622 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4624 case RELOAD_FOR_OUTADDR_ADDRESS:
4625 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4626 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4628 case RELOAD_FOR_OPERAND_ADDRESS:
4629 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4630 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4632 case RELOAD_FOR_OPADDR_ADDR:
4633 return (r2_type == RELOAD_FOR_INPUT
4634 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4636 case RELOAD_FOR_OUTPUT:
4637 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4638 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4639 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4640 && r2_opnum >= r1_opnum));
4642 case RELOAD_FOR_INSN:
4643 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4644 || r2_type == RELOAD_FOR_INSN
4645 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4647 case RELOAD_FOR_OTHER_ADDRESS:
4648 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4658 /* Indexed by reload number, 1 if incoming value
4659 inherited from previous insns. */
4660 char reload_inherited[MAX_RELOADS];
4662 /* For an inherited reload, this is the insn the reload was inherited from,
4663 if we know it. Otherwise, this is 0. */
4664 rtx reload_inheritance_insn[MAX_RELOADS];
4666 /* If nonzero, this is a place to get the value of the reload,
4667 rather than using reload_in. */
4668 rtx reload_override_in[MAX_RELOADS];
4670 /* For each reload, the hard register number of the register used,
4671 or -1 if we did not need a register for this reload. */
4672 int reload_spill_index[MAX_RELOADS];
4674 /* Subroutine of free_for_value_p, used to check a single register.
4675 START_REGNO is the starting regno of the full reload register
4676 (possibly comprising multiple hard registers) that we are considering. */
4679 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4680 enum reload_type type, rtx value, rtx out,
4681 int reloadnum, int ignore_address_reloads)
4684 /* Set if we see an input reload that must not share its reload register
4685 with any new earlyclobber, but might otherwise share the reload
4686 register with an output or input-output reload. */
4687 int check_earlyclobber = 0;
4691 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4694 if (out == const0_rtx)
4700 /* We use some pseudo 'time' value to check if the lifetimes of the
4701 new register use would overlap with the one of a previous reload
4702 that is not read-only or uses a different value.
4703 The 'time' used doesn't have to be linear in any shape or form, just
4705 Some reload types use different 'buckets' for each operand.
4706 So there are MAX_RECOG_OPERANDS different time values for each
4708 We compute TIME1 as the time when the register for the prospective
4709 new reload ceases to be live, and TIME2 for each existing
4710 reload as the time when that the reload register of that reload
4712 Where there is little to be gained by exact lifetime calculations,
4713 we just make conservative assumptions, i.e. a longer lifetime;
4714 this is done in the 'default:' cases. */
4717 case RELOAD_FOR_OTHER_ADDRESS:
4718 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4719 time1 = copy ? 0 : 1;
4722 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4724 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4725 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4726 respectively, to the time values for these, we get distinct time
4727 values. To get distinct time values for each operand, we have to
4728 multiply opnum by at least three. We round that up to four because
4729 multiply by four is often cheaper. */
4730 case RELOAD_FOR_INPADDR_ADDRESS:
4731 time1 = opnum * 4 + 2;
4733 case RELOAD_FOR_INPUT_ADDRESS:
4734 time1 = opnum * 4 + 3;
4736 case RELOAD_FOR_INPUT:
4737 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4738 executes (inclusive). */
4739 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4741 case RELOAD_FOR_OPADDR_ADDR:
4743 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4744 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4746 case RELOAD_FOR_OPERAND_ADDRESS:
4747 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4749 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4751 case RELOAD_FOR_OUTADDR_ADDRESS:
4752 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4754 case RELOAD_FOR_OUTPUT_ADDRESS:
4755 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4758 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4761 for (i = 0; i < n_reloads; i++)
4763 rtx reg = rld[i].reg_rtx;
4764 if (reg && GET_CODE (reg) == REG
4765 && ((unsigned) regno - true_regnum (reg)
4766 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned) 1)
4769 rtx other_input = rld[i].in;
4771 /* If the other reload loads the same input value, that
4772 will not cause a conflict only if it's loading it into
4773 the same register. */
4774 if (true_regnum (reg) != start_regno)
4775 other_input = NULL_RTX;
4776 if (! other_input || ! rtx_equal_p (other_input, value)
4777 || rld[i].out || out)
4780 switch (rld[i].when_needed)
4782 case RELOAD_FOR_OTHER_ADDRESS:
4785 case RELOAD_FOR_INPADDR_ADDRESS:
4786 /* find_reloads makes sure that a
4787 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4788 by at most one - the first -
4789 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4790 address reload is inherited, the address address reload
4791 goes away, so we can ignore this conflict. */
4792 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4793 && ignore_address_reloads
4794 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4795 Then the address address is still needed to store
4796 back the new address. */
4797 && ! rld[reloadnum].out)
4799 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4800 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4802 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4803 && ignore_address_reloads
4804 /* Unless we are reloading an auto_inc expression. */
4805 && ! rld[reloadnum].out)
4807 time2 = rld[i].opnum * 4 + 2;
4809 case RELOAD_FOR_INPUT_ADDRESS:
4810 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4811 && ignore_address_reloads
4812 && ! rld[reloadnum].out)
4814 time2 = rld[i].opnum * 4 + 3;
4816 case RELOAD_FOR_INPUT:
4817 time2 = rld[i].opnum * 4 + 4;
4818 check_earlyclobber = 1;
4820 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4821 == MAX_RECOG_OPERAND * 4 */
4822 case RELOAD_FOR_OPADDR_ADDR:
4823 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4824 && ignore_address_reloads
4825 && ! rld[reloadnum].out)
4827 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4829 case RELOAD_FOR_OPERAND_ADDRESS:
4830 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4831 check_earlyclobber = 1;
4833 case RELOAD_FOR_INSN:
4834 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4836 case RELOAD_FOR_OUTPUT:
4837 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4838 instruction is executed. */
4839 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4841 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4842 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4844 case RELOAD_FOR_OUTADDR_ADDRESS:
4845 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4846 && ignore_address_reloads
4847 && ! rld[reloadnum].out)
4849 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4851 case RELOAD_FOR_OUTPUT_ADDRESS:
4852 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4855 /* If there is no conflict in the input part, handle this
4856 like an output reload. */
4857 if (! rld[i].in || rtx_equal_p (other_input, value))
4859 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4860 /* Earlyclobbered outputs must conflict with inputs. */
4861 if (earlyclobber_operand_p (rld[i].out))
4862 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4867 /* RELOAD_OTHER might be live beyond instruction execution,
4868 but this is not obvious when we set time2 = 1. So check
4869 here if there might be a problem with the new reload
4870 clobbering the register used by the RELOAD_OTHER. */
4878 && (! rld[i].in || rld[i].out
4879 || ! rtx_equal_p (other_input, value)))
4880 || (out && rld[reloadnum].out_reg
4881 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4887 /* Earlyclobbered outputs must conflict with inputs. */
4888 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4894 /* Return 1 if the value in reload reg REGNO, as used by a reload
4895 needed for the part of the insn specified by OPNUM and TYPE,
4896 may be used to load VALUE into it.
4898 MODE is the mode in which the register is used, this is needed to
4899 determine how many hard regs to test.
4901 Other read-only reloads with the same value do not conflict
4902 unless OUT is nonzero and these other reloads have to live while
4903 output reloads live.
4904 If OUT is CONST0_RTX, this is a special case: it means that the
4905 test should not be for using register REGNO as reload register, but
4906 for copying from register REGNO into the reload register.
4908 RELOADNUM is the number of the reload we want to load this value for;
4909 a reload does not conflict with itself.
4911 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4912 reloads that load an address for the very reload we are considering.
4914 The caller has to make sure that there is no conflict with the return
4918 free_for_value_p (int regno, enum machine_mode mode, int opnum,
4919 enum reload_type type, rtx value, rtx out, int reloadnum,
4920 int ignore_address_reloads)
4922 int nregs = HARD_REGNO_NREGS (regno, mode);
4924 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4925 value, out, reloadnum,
4926 ignore_address_reloads))
4931 /* Determine whether the reload reg X overlaps any rtx'es used for
4932 overriding inheritance. Return nonzero if so. */
4935 conflicts_with_override (rtx x)
4938 for (i = 0; i < n_reloads; i++)
4939 if (reload_override_in[i]
4940 && reg_overlap_mentioned_p (x, reload_override_in[i]))
4945 /* Give an error message saying we failed to find a reload for INSN,
4946 and clear out reload R. */
4948 failed_reload (rtx insn, int r)
4950 if (asm_noperands (PATTERN (insn)) < 0)
4951 /* It's the compiler's fault. */
4952 fatal_insn ("could not find a spill register", insn);
4954 /* It's the user's fault; the operand's mode and constraint
4955 don't match. Disable this reload so we don't crash in final. */
4956 error_for_asm (insn,
4957 "`asm' operand constraint incompatible with operand size");
4961 rld[r].optional = 1;
4962 rld[r].secondary_p = 1;
4965 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
4966 for reload R. If it's valid, get an rtx for it. Return nonzero if
4969 set_reload_reg (int i, int r)
4972 rtx reg = spill_reg_rtx[i];
4974 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
4975 spill_reg_rtx[i] = reg
4976 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
4978 regno = true_regnum (reg);
4980 /* Detect when the reload reg can't hold the reload mode.
4981 This used to be one `if', but Sequent compiler can't handle that. */
4982 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
4984 enum machine_mode test_mode = VOIDmode;
4986 test_mode = GET_MODE (rld[r].in);
4987 /* If rld[r].in has VOIDmode, it means we will load it
4988 in whatever mode the reload reg has: to wit, rld[r].mode.
4989 We have already tested that for validity. */
4990 /* Aside from that, we need to test that the expressions
4991 to reload from or into have modes which are valid for this
4992 reload register. Otherwise the reload insns would be invalid. */
4993 if (! (rld[r].in != 0 && test_mode != VOIDmode
4994 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
4995 if (! (rld[r].out != 0
4996 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
4998 /* The reg is OK. */
5001 /* Mark as in use for this insn the reload regs we use
5003 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5004 rld[r].when_needed, rld[r].mode);
5006 rld[r].reg_rtx = reg;
5007 reload_spill_index[r] = spill_regs[i];
5014 /* Find a spill register to use as a reload register for reload R.
5015 LAST_RELOAD is nonzero if this is the last reload for the insn being
5018 Set rld[R].reg_rtx to the register allocated.
5020 We return 1 if successful, or 0 if we couldn't find a spill reg and
5021 we didn't change anything. */
5024 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5029 /* If we put this reload ahead, thinking it is a group,
5030 then insist on finding a group. Otherwise we can grab a
5031 reg that some other reload needs.
5032 (That can happen when we have a 68000 DATA_OR_FP_REG
5033 which is a group of data regs or one fp reg.)
5034 We need not be so restrictive if there are no more reloads
5037 ??? Really it would be nicer to have smarter handling
5038 for that kind of reg class, where a problem like this is normal.
5039 Perhaps those classes should be avoided for reloading
5040 by use of more alternatives. */
5042 int force_group = rld[r].nregs > 1 && ! last_reload;
5044 /* If we want a single register and haven't yet found one,
5045 take any reg in the right class and not in use.
5046 If we want a consecutive group, here is where we look for it.
5048 We use two passes so we can first look for reload regs to
5049 reuse, which are already in use for other reloads in this insn,
5050 and only then use additional registers.
5051 I think that maximizing reuse is needed to make sure we don't
5052 run out of reload regs. Suppose we have three reloads, and
5053 reloads A and B can share regs. These need two regs.
5054 Suppose A and B are given different regs.
5055 That leaves none for C. */
5056 for (pass = 0; pass < 2; pass++)
5058 /* I is the index in spill_regs.
5059 We advance it round-robin between insns to use all spill regs
5060 equally, so that inherited reloads have a chance
5061 of leapfrogging each other. */
5065 for (count = 0; count < n_spills; count++)
5067 int class = (int) rld[r].class;
5073 regnum = spill_regs[i];
5075 if ((reload_reg_free_p (regnum, rld[r].opnum,
5078 /* We check reload_reg_used to make sure we
5079 don't clobber the return register. */
5080 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5081 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5082 rld[r].when_needed, rld[r].in,
5084 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5085 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5086 /* Look first for regs to share, then for unshared. But
5087 don't share regs used for inherited reloads; they are
5088 the ones we want to preserve. */
5090 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5092 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5095 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5096 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5097 (on 68000) got us two FP regs. If NR is 1,
5098 we would reject both of them. */
5101 /* If we need only one reg, we have already won. */
5104 /* But reject a single reg if we demand a group. */
5109 /* Otherwise check that as many consecutive regs as we need
5110 are available here. */
5113 int regno = regnum + nr - 1;
5114 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5115 && spill_reg_order[regno] >= 0
5116 && reload_reg_free_p (regno, rld[r].opnum,
5117 rld[r].when_needed)))
5126 /* If we found something on pass 1, omit pass 2. */
5127 if (count < n_spills)
5131 /* We should have found a spill register by now. */
5132 if (count >= n_spills)
5135 /* I is the index in SPILL_REG_RTX of the reload register we are to
5136 allocate. Get an rtx for it and find its register number. */
5138 return set_reload_reg (i, r);
5141 /* Initialize all the tables needed to allocate reload registers.
5142 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5143 is the array we use to restore the reg_rtx field for every reload. */
5146 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5150 for (i = 0; i < n_reloads; i++)
5151 rld[i].reg_rtx = save_reload_reg_rtx[i];
5153 memset (reload_inherited, 0, MAX_RELOADS);
5154 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5155 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5157 CLEAR_HARD_REG_SET (reload_reg_used);
5158 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5159 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5160 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5161 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5162 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5164 CLEAR_HARD_REG_SET (reg_used_in_insn);
5167 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5168 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5169 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5170 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5171 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5172 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5175 for (i = 0; i < reload_n_operands; i++)
5177 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5178 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5179 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5180 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5181 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5182 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5185 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5187 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5189 for (i = 0; i < n_reloads; i++)
5190 /* If we have already decided to use a certain register,
5191 don't use it in another way. */
5193 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5194 rld[i].when_needed, rld[i].mode);
5197 /* Assign hard reg targets for the pseudo-registers we must reload
5198 into hard regs for this insn.
5199 Also output the instructions to copy them in and out of the hard regs.
5201 For machines with register classes, we are responsible for
5202 finding a reload reg in the proper class. */
5205 choose_reload_regs (struct insn_chain *chain)
5207 rtx insn = chain->insn;
5209 unsigned int max_group_size = 1;
5210 enum reg_class group_class = NO_REGS;
5211 int pass, win, inheritance;
5213 rtx save_reload_reg_rtx[MAX_RELOADS];
5215 /* In order to be certain of getting the registers we need,
5216 we must sort the reloads into order of increasing register class.
5217 Then our grabbing of reload registers will parallel the process
5218 that provided the reload registers.
5220 Also note whether any of the reloads wants a consecutive group of regs.
5221 If so, record the maximum size of the group desired and what
5222 register class contains all the groups needed by this insn. */
5224 for (j = 0; j < n_reloads; j++)
5226 reload_order[j] = j;
5227 reload_spill_index[j] = -1;
5229 if (rld[j].nregs > 1)
5231 max_group_size = MAX (rld[j].nregs, max_group_size);
5233 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5236 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5240 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5242 /* If -O, try first with inheritance, then turning it off.
5243 If not -O, don't do inheritance.
5244 Using inheritance when not optimizing leads to paradoxes
5245 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5246 because one side of the comparison might be inherited. */
5248 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5250 choose_reload_regs_init (chain, save_reload_reg_rtx);
5252 /* Process the reloads in order of preference just found.
5253 Beyond this point, subregs can be found in reload_reg_rtx.
5255 This used to look for an existing reloaded home for all of the
5256 reloads, and only then perform any new reloads. But that could lose
5257 if the reloads were done out of reg-class order because a later
5258 reload with a looser constraint might have an old home in a register
5259 needed by an earlier reload with a tighter constraint.
5261 To solve this, we make two passes over the reloads, in the order
5262 described above. In the first pass we try to inherit a reload
5263 from a previous insn. If there is a later reload that needs a
5264 class that is a proper subset of the class being processed, we must
5265 also allocate a spill register during the first pass.
5267 Then make a second pass over the reloads to allocate any reloads
5268 that haven't been given registers yet. */
5270 for (j = 0; j < n_reloads; j++)
5272 int r = reload_order[j];
5273 rtx search_equiv = NULL_RTX;
5275 /* Ignore reloads that got marked inoperative. */
5276 if (rld[r].out == 0 && rld[r].in == 0
5277 && ! rld[r].secondary_p)
5280 /* If find_reloads chose to use reload_in or reload_out as a reload
5281 register, we don't need to chose one. Otherwise, try even if it
5282 found one since we might save an insn if we find the value lying
5284 Try also when reload_in is a pseudo without a hard reg. */
5285 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5286 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5287 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5288 && GET_CODE (rld[r].in) != MEM
5289 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5292 #if 0 /* No longer needed for correct operation.
5293 It might give better code, or might not; worth an experiment? */
5294 /* If this is an optional reload, we can't inherit from earlier insns
5295 until we are sure that any non-optional reloads have been allocated.
5296 The following code takes advantage of the fact that optional reloads
5297 are at the end of reload_order. */
5298 if (rld[r].optional != 0)
5299 for (i = 0; i < j; i++)
5300 if ((rld[reload_order[i]].out != 0
5301 || rld[reload_order[i]].in != 0
5302 || rld[reload_order[i]].secondary_p)
5303 && ! rld[reload_order[i]].optional
5304 && rld[reload_order[i]].reg_rtx == 0)
5305 allocate_reload_reg (chain, reload_order[i], 0);
5308 /* First see if this pseudo is already available as reloaded
5309 for a previous insn. We cannot try to inherit for reloads
5310 that are smaller than the maximum number of registers needed
5311 for groups unless the register we would allocate cannot be used
5314 We could check here to see if this is a secondary reload for
5315 an object that is already in a register of the desired class.
5316 This would avoid the need for the secondary reload register.
5317 But this is complex because we can't easily determine what
5318 objects might want to be loaded via this reload. So let a
5319 register be allocated here. In `emit_reload_insns' we suppress
5320 one of the loads in the case described above. */
5326 enum machine_mode mode = VOIDmode;
5330 else if (GET_CODE (rld[r].in) == REG)
5332 regno = REGNO (rld[r].in);
5333 mode = GET_MODE (rld[r].in);
5335 else if (GET_CODE (rld[r].in_reg) == REG)
5337 regno = REGNO (rld[r].in_reg);
5338 mode = GET_MODE (rld[r].in_reg);
5340 else if (GET_CODE (rld[r].in_reg) == SUBREG
5341 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5343 byte = SUBREG_BYTE (rld[r].in_reg);
5344 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5345 if (regno < FIRST_PSEUDO_REGISTER)
5346 regno = subreg_regno (rld[r].in_reg);
5347 mode = GET_MODE (rld[r].in_reg);
5350 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5351 || GET_CODE (rld[r].in_reg) == PRE_DEC
5352 || GET_CODE (rld[r].in_reg) == POST_INC
5353 || GET_CODE (rld[r].in_reg) == POST_DEC)
5354 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5356 regno = REGNO (XEXP (rld[r].in_reg, 0));
5357 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5358 rld[r].out = rld[r].in;
5362 /* This won't work, since REGNO can be a pseudo reg number.
5363 Also, it takes much more hair to keep track of all the things
5364 that can invalidate an inherited reload of part of a pseudoreg. */
5365 else if (GET_CODE (rld[r].in) == SUBREG
5366 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5367 regno = subreg_regno (rld[r].in);
5370 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5372 enum reg_class class = rld[r].class, last_class;
5373 rtx last_reg = reg_last_reload_reg[regno];
5374 enum machine_mode need_mode;
5376 i = REGNO (last_reg);
5377 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5378 last_class = REGNO_REG_CLASS (i);
5384 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5385 GET_MODE_CLASS (mode));
5388 #ifdef CANNOT_CHANGE_MODE_CLASS
5389 (!REG_CANNOT_CHANGE_MODE_P (i, GET_MODE (last_reg),
5393 (GET_MODE_SIZE (GET_MODE (last_reg))
5394 >= GET_MODE_SIZE (need_mode))
5395 #ifdef CANNOT_CHANGE_MODE_CLASS
5398 && reg_reloaded_contents[i] == regno
5399 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5400 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5401 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5402 /* Even if we can't use this register as a reload
5403 register, we might use it for reload_override_in,
5404 if copying it to the desired class is cheap
5406 || ((REGISTER_MOVE_COST (mode, last_class, class)
5407 < MEMORY_MOVE_COST (mode, class, 1))
5408 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5409 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5413 #ifdef SECONDARY_MEMORY_NEEDED
5414 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5419 && (rld[r].nregs == max_group_size
5420 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5422 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5423 rld[r].when_needed, rld[r].in,
5426 /* If a group is needed, verify that all the subsequent
5427 registers still have their values intact. */
5428 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5431 for (k = 1; k < nr; k++)
5432 if (reg_reloaded_contents[i + k] != regno
5433 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5441 last_reg = (GET_MODE (last_reg) == mode
5442 ? last_reg : gen_rtx_REG (mode, i));
5445 for (k = 0; k < nr; k++)
5446 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5449 /* We found a register that contains the
5450 value we need. If this register is the
5451 same as an `earlyclobber' operand of the
5452 current insn, just mark it as a place to
5453 reload from since we can't use it as the
5454 reload register itself. */
5456 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5457 if (reg_overlap_mentioned_for_reload_p
5458 (reg_last_reload_reg[regno],
5459 reload_earlyclobbers[i1]))
5462 if (i1 != n_earlyclobbers
5463 || ! (free_for_value_p (i, rld[r].mode,
5465 rld[r].when_needed, rld[r].in,
5467 /* Don't use it if we'd clobber a pseudo reg. */
5468 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5470 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5471 /* Don't clobber the frame pointer. */
5472 || (i == HARD_FRAME_POINTER_REGNUM
5473 && frame_pointer_needed
5475 /* Don't really use the inherited spill reg
5476 if we need it wider than we've got it. */
5477 || (GET_MODE_SIZE (rld[r].mode)
5478 > GET_MODE_SIZE (mode))
5481 /* If find_reloads chose reload_out as reload
5482 register, stay with it - that leaves the
5483 inherited register for subsequent reloads. */
5484 || (rld[r].out && rld[r].reg_rtx
5485 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5487 if (! rld[r].optional)
5489 reload_override_in[r] = last_reg;
5490 reload_inheritance_insn[r]
5491 = reg_reloaded_insn[i];
5497 /* We can use this as a reload reg. */
5498 /* Mark the register as in use for this part of
5500 mark_reload_reg_in_use (i,
5504 rld[r].reg_rtx = last_reg;
5505 reload_inherited[r] = 1;
5506 reload_inheritance_insn[r]
5507 = reg_reloaded_insn[i];
5508 reload_spill_index[r] = i;
5509 for (k = 0; k < nr; k++)
5510 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5518 /* Here's another way to see if the value is already lying around. */
5521 && ! reload_inherited[r]
5523 && (CONSTANT_P (rld[r].in)
5524 || GET_CODE (rld[r].in) == PLUS
5525 || GET_CODE (rld[r].in) == REG
5526 || GET_CODE (rld[r].in) == MEM)
5527 && (rld[r].nregs == max_group_size
5528 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5529 search_equiv = rld[r].in;
5530 /* If this is an output reload from a simple move insn, look
5531 if an equivalence for the input is available. */
5532 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5534 rtx set = single_set (insn);
5537 && rtx_equal_p (rld[r].out, SET_DEST (set))
5538 && CONSTANT_P (SET_SRC (set)))
5539 search_equiv = SET_SRC (set);
5545 = find_equiv_reg (search_equiv, insn, rld[r].class,
5546 -1, NULL, 0, rld[r].mode);
5551 if (GET_CODE (equiv) == REG)
5552 regno = REGNO (equiv);
5553 else if (GET_CODE (equiv) == SUBREG)
5555 /* This must be a SUBREG of a hard register.
5556 Make a new REG since this might be used in an
5557 address and not all machines support SUBREGs
5559 regno = subreg_regno (equiv);
5560 equiv = gen_rtx_REG (rld[r].mode, regno);
5566 /* If we found a spill reg, reject it unless it is free
5567 and of the desired class. */
5571 int bad_for_class = 0;
5572 int max_regno = regno + rld[r].nregs;
5574 for (i = regno; i < max_regno; i++)
5576 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5578 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5583 && ! free_for_value_p (regno, rld[r].mode,
5584 rld[r].opnum, rld[r].when_needed,
5585 rld[r].in, rld[r].out, r, 1))
5590 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5593 /* We found a register that contains the value we need.
5594 If this register is the same as an `earlyclobber' operand
5595 of the current insn, just mark it as a place to reload from
5596 since we can't use it as the reload register itself. */
5599 for (i = 0; i < n_earlyclobbers; i++)
5600 if (reg_overlap_mentioned_for_reload_p (equiv,
5601 reload_earlyclobbers[i]))
5603 if (! rld[r].optional)
5604 reload_override_in[r] = equiv;
5609 /* If the equiv register we have found is explicitly clobbered
5610 in the current insn, it depends on the reload type if we
5611 can use it, use it for reload_override_in, or not at all.
5612 In particular, we then can't use EQUIV for a
5613 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5617 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5618 switch (rld[r].when_needed)
5620 case RELOAD_FOR_OTHER_ADDRESS:
5621 case RELOAD_FOR_INPADDR_ADDRESS:
5622 case RELOAD_FOR_INPUT_ADDRESS:
5623 case RELOAD_FOR_OPADDR_ADDR:
5626 case RELOAD_FOR_INPUT:
5627 case RELOAD_FOR_OPERAND_ADDRESS:
5628 if (! rld[r].optional)
5629 reload_override_in[r] = equiv;
5635 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5636 switch (rld[r].when_needed)
5638 case RELOAD_FOR_OTHER_ADDRESS:
5639 case RELOAD_FOR_INPADDR_ADDRESS:
5640 case RELOAD_FOR_INPUT_ADDRESS:
5641 case RELOAD_FOR_OPADDR_ADDR:
5642 case RELOAD_FOR_OPERAND_ADDRESS:
5643 case RELOAD_FOR_INPUT:
5646 if (! rld[r].optional)
5647 reload_override_in[r] = equiv;
5655 /* If we found an equivalent reg, say no code need be generated
5656 to load it, and use it as our reload reg. */
5658 && (regno != HARD_FRAME_POINTER_REGNUM
5659 || !frame_pointer_needed))
5661 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5663 rld[r].reg_rtx = equiv;
5664 reload_inherited[r] = 1;
5666 /* If reg_reloaded_valid is not set for this register,
5667 there might be a stale spill_reg_store lying around.
5668 We must clear it, since otherwise emit_reload_insns
5669 might delete the store. */
5670 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5671 spill_reg_store[regno] = NULL_RTX;
5672 /* If any of the hard registers in EQUIV are spill
5673 registers, mark them as in use for this insn. */
5674 for (k = 0; k < nr; k++)
5676 i = spill_reg_order[regno + k];
5679 mark_reload_reg_in_use (regno, rld[r].opnum,
5682 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5689 /* If we found a register to use already, or if this is an optional
5690 reload, we are done. */
5691 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5695 /* No longer needed for correct operation. Might or might
5696 not give better code on the average. Want to experiment? */
5698 /* See if there is a later reload that has a class different from our
5699 class that intersects our class or that requires less register
5700 than our reload. If so, we must allocate a register to this
5701 reload now, since that reload might inherit a previous reload
5702 and take the only available register in our class. Don't do this
5703 for optional reloads since they will force all previous reloads
5704 to be allocated. Also don't do this for reloads that have been
5707 for (i = j + 1; i < n_reloads; i++)
5709 int s = reload_order[i];
5711 if ((rld[s].in == 0 && rld[s].out == 0
5712 && ! rld[s].secondary_p)
5716 if ((rld[s].class != rld[r].class
5717 && reg_classes_intersect_p (rld[r].class,
5719 || rld[s].nregs < rld[r].nregs)
5726 allocate_reload_reg (chain, r, j == n_reloads - 1);
5730 /* Now allocate reload registers for anything non-optional that
5731 didn't get one yet. */
5732 for (j = 0; j < n_reloads; j++)
5734 int r = reload_order[j];
5736 /* Ignore reloads that got marked inoperative. */
5737 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5740 /* Skip reloads that already have a register allocated or are
5742 if (rld[r].reg_rtx != 0 || rld[r].optional)
5745 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5749 /* If that loop got all the way, we have won. */
5756 /* Loop around and try without any inheritance. */
5761 /* First undo everything done by the failed attempt
5762 to allocate with inheritance. */
5763 choose_reload_regs_init (chain, save_reload_reg_rtx);
5765 /* Some sanity tests to verify that the reloads found in the first
5766 pass are identical to the ones we have now. */
5767 if (chain->n_reloads != n_reloads)
5770 for (i = 0; i < n_reloads; i++)
5772 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5774 if (chain->rld[i].when_needed != rld[i].when_needed)
5776 for (j = 0; j < n_spills; j++)
5777 if (spill_regs[j] == chain->rld[i].regno)
5778 if (! set_reload_reg (j, i))
5779 failed_reload (chain->insn, i);
5783 /* If we thought we could inherit a reload, because it seemed that
5784 nothing else wanted the same reload register earlier in the insn,
5785 verify that assumption, now that all reloads have been assigned.
5786 Likewise for reloads where reload_override_in has been set. */
5788 /* If doing expensive optimizations, do one preliminary pass that doesn't
5789 cancel any inheritance, but removes reloads that have been needed only
5790 for reloads that we know can be inherited. */
5791 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5793 for (j = 0; j < n_reloads; j++)
5795 int r = reload_order[j];
5797 if (reload_inherited[r] && rld[r].reg_rtx)
5798 check_reg = rld[r].reg_rtx;
5799 else if (reload_override_in[r]
5800 && (GET_CODE (reload_override_in[r]) == REG
5801 || GET_CODE (reload_override_in[r]) == SUBREG))
5802 check_reg = reload_override_in[r];
5805 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5806 rld[r].opnum, rld[r].when_needed, rld[r].in,
5807 (reload_inherited[r]
5808 ? rld[r].out : const0_rtx),
5813 reload_inherited[r] = 0;
5814 reload_override_in[r] = 0;
5816 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5817 reload_override_in, then we do not need its related
5818 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5819 likewise for other reload types.
5820 We handle this by removing a reload when its only replacement
5821 is mentioned in reload_in of the reload we are going to inherit.
5822 A special case are auto_inc expressions; even if the input is
5823 inherited, we still need the address for the output. We can
5824 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5825 If we succeeded removing some reload and we are doing a preliminary
5826 pass just to remove such reloads, make another pass, since the
5827 removal of one reload might allow us to inherit another one. */
5829 && rld[r].out != rld[r].in
5830 && remove_address_replacements (rld[r].in) && pass)
5835 /* Now that reload_override_in is known valid,
5836 actually override reload_in. */
5837 for (j = 0; j < n_reloads; j++)
5838 if (reload_override_in[j])
5839 rld[j].in = reload_override_in[j];
5841 /* If this reload won't be done because it has been canceled or is
5842 optional and not inherited, clear reload_reg_rtx so other
5843 routines (such as subst_reloads) don't get confused. */
5844 for (j = 0; j < n_reloads; j++)
5845 if (rld[j].reg_rtx != 0
5846 && ((rld[j].optional && ! reload_inherited[j])
5847 || (rld[j].in == 0 && rld[j].out == 0
5848 && ! rld[j].secondary_p)))
5850 int regno = true_regnum (rld[j].reg_rtx);
5852 if (spill_reg_order[regno] >= 0)
5853 clear_reload_reg_in_use (regno, rld[j].opnum,
5854 rld[j].when_needed, rld[j].mode);
5856 reload_spill_index[j] = -1;
5859 /* Record which pseudos and which spill regs have output reloads. */
5860 for (j = 0; j < n_reloads; j++)
5862 int r = reload_order[j];
5864 i = reload_spill_index[r];
5866 /* I is nonneg if this reload uses a register.
5867 If rld[r].reg_rtx is 0, this is an optional reload
5868 that we opted to ignore. */
5869 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5870 && rld[r].reg_rtx != 0)
5872 int nregno = REGNO (rld[r].out_reg);
5875 if (nregno < FIRST_PSEUDO_REGISTER)
5876 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5879 reg_has_output_reload[nregno + nr] = 1;
5883 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5885 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5888 if (rld[r].when_needed != RELOAD_OTHER
5889 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5890 && rld[r].when_needed != RELOAD_FOR_INSN)
5896 /* Deallocate the reload register for reload R. This is called from
5897 remove_address_replacements. */
5900 deallocate_reload_reg (int r)
5904 if (! rld[r].reg_rtx)
5906 regno = true_regnum (rld[r].reg_rtx);
5908 if (spill_reg_order[regno] >= 0)
5909 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5911 reload_spill_index[r] = -1;
5914 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
5915 reloads of the same item for fear that we might not have enough reload
5916 registers. However, normally they will get the same reload register
5917 and hence actually need not be loaded twice.
5919 Here we check for the most common case of this phenomenon: when we have
5920 a number of reloads for the same object, each of which were allocated
5921 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5922 reload, and is not modified in the insn itself. If we find such,
5923 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5924 This will not increase the number of spill registers needed and will
5925 prevent redundant code. */
5928 merge_assigned_reloads (rtx insn)
5932 /* Scan all the reloads looking for ones that only load values and
5933 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5934 assigned and not modified by INSN. */
5936 for (i = 0; i < n_reloads; i++)
5938 int conflicting_input = 0;
5939 int max_input_address_opnum = -1;
5940 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5942 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5943 || rld[i].out != 0 || rld[i].reg_rtx == 0
5944 || reg_set_p (rld[i].reg_rtx, insn))
5947 /* Look at all other reloads. Ensure that the only use of this
5948 reload_reg_rtx is in a reload that just loads the same value
5949 as we do. Note that any secondary reloads must be of the identical
5950 class since the values, modes, and result registers are the
5951 same, so we need not do anything with any secondary reloads. */
5953 for (j = 0; j < n_reloads; j++)
5955 if (i == j || rld[j].reg_rtx == 0
5956 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
5960 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5961 && rld[j].opnum > max_input_address_opnum)
5962 max_input_address_opnum = rld[j].opnum;
5964 /* If the reload regs aren't exactly the same (e.g, different modes)
5965 or if the values are different, we can't merge this reload.
5966 But if it is an input reload, we might still merge
5967 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
5969 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5970 || rld[j].out != 0 || rld[j].in == 0
5971 || ! rtx_equal_p (rld[i].in, rld[j].in))
5973 if (rld[j].when_needed != RELOAD_FOR_INPUT
5974 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
5975 || rld[i].opnum > rld[j].opnum)
5976 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
5978 conflicting_input = 1;
5979 if (min_conflicting_input_opnum > rld[j].opnum)
5980 min_conflicting_input_opnum = rld[j].opnum;
5984 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5985 we, in fact, found any matching reloads. */
5988 && max_input_address_opnum <= min_conflicting_input_opnum)
5990 for (j = 0; j < n_reloads; j++)
5991 if (i != j && rld[j].reg_rtx != 0
5992 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5993 && (! conflicting_input
5994 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5995 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
5997 rld[i].when_needed = RELOAD_OTHER;
5999 reload_spill_index[j] = -1;
6000 transfer_replacements (i, j);
6003 /* If this is now RELOAD_OTHER, look for any reloads that load
6004 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6005 if they were for inputs, RELOAD_OTHER for outputs. Note that
6006 this test is equivalent to looking for reloads for this operand
6008 /* We must take special care when there are two or more reloads to
6009 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6010 same value or a part of it; we must not change its type if there
6011 is a conflicting input. */
6013 if (rld[i].when_needed == RELOAD_OTHER)
6014 for (j = 0; j < n_reloads; j++)
6016 && rld[j].when_needed != RELOAD_OTHER
6017 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6018 && (! conflicting_input
6019 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6020 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6021 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6027 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6028 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6029 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6031 /* Check to see if we accidentally converted two reloads
6032 that use the same reload register with different inputs
6033 to the same type. If so, the resulting code won't work,
6036 for (k = 0; k < j; k++)
6037 if (rld[k].in != 0 && rld[k].reg_rtx != 0
6038 && rld[k].when_needed == rld[j].when_needed
6039 && rtx_equal_p (rld[k].reg_rtx, rld[j].reg_rtx)
6040 && ! rtx_equal_p (rld[k].in, rld[j].in))
6047 /* These arrays are filled by emit_reload_insns and its subroutines. */
6048 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6049 static rtx other_input_address_reload_insns = 0;
6050 static rtx other_input_reload_insns = 0;
6051 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6052 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6053 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6054 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6055 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6056 static rtx operand_reload_insns = 0;
6057 static rtx other_operand_reload_insns = 0;
6058 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6060 /* Values to be put in spill_reg_store are put here first. */
6061 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6062 static HARD_REG_SET reg_reloaded_died;
6064 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6065 has the number J. OLD contains the value to be used as input. */
6068 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6071 rtx insn = chain->insn;
6072 rtx reloadreg = rl->reg_rtx;
6073 rtx oldequiv_reg = 0;
6076 enum machine_mode mode;
6079 /* Determine the mode to reload in.
6080 This is very tricky because we have three to choose from.
6081 There is the mode the insn operand wants (rl->inmode).
6082 There is the mode of the reload register RELOADREG.
6083 There is the intrinsic mode of the operand, which we could find
6084 by stripping some SUBREGs.
6085 It turns out that RELOADREG's mode is irrelevant:
6086 we can change that arbitrarily.
6088 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6089 then the reload reg may not support QImode moves, so use SImode.
6090 If foo is in memory due to spilling a pseudo reg, this is safe,
6091 because the QImode value is in the least significant part of a
6092 slot big enough for a SImode. If foo is some other sort of
6093 memory reference, then it is impossible to reload this case,
6094 so previous passes had better make sure this never happens.
6096 Then consider a one-word union which has SImode and one of its
6097 members is a float, being fetched as (SUBREG:SF union:SI).
6098 We must fetch that as SFmode because we could be loading into
6099 a float-only register. In this case OLD's mode is correct.
6101 Consider an immediate integer: it has VOIDmode. Here we need
6102 to get a mode from something else.
6104 In some cases, there is a fourth mode, the operand's
6105 containing mode. If the insn specifies a containing mode for
6106 this operand, it overrides all others.
6108 I am not sure whether the algorithm here is always right,
6109 but it does the right things in those cases. */
6111 mode = GET_MODE (old);
6112 if (mode == VOIDmode)
6115 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6116 /* If we need a secondary register for this operation, see if
6117 the value is already in a register in that class. Don't
6118 do this if the secondary register will be used as a scratch
6121 if (rl->secondary_in_reload >= 0
6122 && rl->secondary_in_icode == CODE_FOR_nothing
6125 = find_equiv_reg (old, insn,
6126 rld[rl->secondary_in_reload].class,
6130 /* If reloading from memory, see if there is a register
6131 that already holds the same value. If so, reload from there.
6132 We can pass 0 as the reload_reg_p argument because
6133 any other reload has either already been emitted,
6134 in which case find_equiv_reg will see the reload-insn,
6135 or has yet to be emitted, in which case it doesn't matter
6136 because we will use this equiv reg right away. */
6138 if (oldequiv == 0 && optimize
6139 && (GET_CODE (old) == MEM
6140 || (GET_CODE (old) == REG
6141 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6142 && reg_renumber[REGNO (old)] < 0)))
6143 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6147 unsigned int regno = true_regnum (oldequiv);
6149 /* Don't use OLDEQUIV if any other reload changes it at an
6150 earlier stage of this insn or at this stage. */
6151 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6152 rl->in, const0_rtx, j, 0))
6155 /* If it is no cheaper to copy from OLDEQUIV into the
6156 reload register than it would be to move from memory,
6157 don't use it. Likewise, if we need a secondary register
6161 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6162 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6164 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6165 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6166 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6170 #ifdef SECONDARY_MEMORY_NEEDED
6171 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6179 /* delete_output_reload is only invoked properly if old contains
6180 the original pseudo register. Since this is replaced with a
6181 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6182 find the pseudo in RELOAD_IN_REG. */
6184 && reload_override_in[j]
6185 && GET_CODE (rl->in_reg) == REG)
6192 else if (GET_CODE (oldequiv) == REG)
6193 oldequiv_reg = oldequiv;
6194 else if (GET_CODE (oldequiv) == SUBREG)
6195 oldequiv_reg = SUBREG_REG (oldequiv);
6197 /* If we are reloading from a register that was recently stored in
6198 with an output-reload, see if we can prove there was
6199 actually no need to store the old value in it. */
6201 if (optimize && GET_CODE (oldequiv) == REG
6202 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6203 && spill_reg_store[REGNO (oldequiv)]
6204 && GET_CODE (old) == REG
6205 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6206 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6208 delete_output_reload (insn, j, REGNO (oldequiv));
6210 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6211 then load RELOADREG from OLDEQUIV. Note that we cannot use
6212 gen_lowpart_common since it can do the wrong thing when
6213 RELOADREG has a multi-word mode. Note that RELOADREG
6214 must always be a REG here. */
6216 if (GET_MODE (reloadreg) != mode)
6217 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6218 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6219 oldequiv = SUBREG_REG (oldequiv);
6220 if (GET_MODE (oldequiv) != VOIDmode
6221 && mode != GET_MODE (oldequiv))
6222 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6224 /* Switch to the right place to emit the reload insns. */
6225 switch (rl->when_needed)
6228 where = &other_input_reload_insns;
6230 case RELOAD_FOR_INPUT:
6231 where = &input_reload_insns[rl->opnum];
6233 case RELOAD_FOR_INPUT_ADDRESS:
6234 where = &input_address_reload_insns[rl->opnum];
6236 case RELOAD_FOR_INPADDR_ADDRESS:
6237 where = &inpaddr_address_reload_insns[rl->opnum];
6239 case RELOAD_FOR_OUTPUT_ADDRESS:
6240 where = &output_address_reload_insns[rl->opnum];
6242 case RELOAD_FOR_OUTADDR_ADDRESS:
6243 where = &outaddr_address_reload_insns[rl->opnum];
6245 case RELOAD_FOR_OPERAND_ADDRESS:
6246 where = &operand_reload_insns;
6248 case RELOAD_FOR_OPADDR_ADDR:
6249 where = &other_operand_reload_insns;
6251 case RELOAD_FOR_OTHER_ADDRESS:
6252 where = &other_input_address_reload_insns;
6258 push_to_sequence (*where);
6260 /* Auto-increment addresses must be reloaded in a special way. */
6261 if (rl->out && ! rl->out_reg)
6263 /* We are not going to bother supporting the case where a
6264 incremented register can't be copied directly from
6265 OLDEQUIV since this seems highly unlikely. */
6266 if (rl->secondary_in_reload >= 0)
6269 if (reload_inherited[j])
6270 oldequiv = reloadreg;
6272 old = XEXP (rl->in_reg, 0);
6274 if (optimize && GET_CODE (oldequiv) == REG
6275 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6276 && spill_reg_store[REGNO (oldequiv)]
6277 && GET_CODE (old) == REG
6278 && (dead_or_set_p (insn,
6279 spill_reg_stored_to[REGNO (oldequiv)])
6280 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6282 delete_output_reload (insn, j, REGNO (oldequiv));
6284 /* Prevent normal processing of this reload. */
6286 /* Output a special code sequence for this case. */
6287 new_spill_reg_store[REGNO (reloadreg)]
6288 = inc_for_reload (reloadreg, oldequiv, rl->out,
6292 /* If we are reloading a pseudo-register that was set by the previous
6293 insn, see if we can get rid of that pseudo-register entirely
6294 by redirecting the previous insn into our reload register. */
6296 else if (optimize && GET_CODE (old) == REG
6297 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6298 && dead_or_set_p (insn, old)
6299 /* This is unsafe if some other reload
6300 uses the same reg first. */
6301 && ! conflicts_with_override (reloadreg)
6302 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6303 rl->when_needed, old, rl->out, j, 0))
6305 rtx temp = PREV_INSN (insn);
6306 while (temp && GET_CODE (temp) == NOTE)
6307 temp = PREV_INSN (temp);
6309 && GET_CODE (temp) == INSN
6310 && GET_CODE (PATTERN (temp)) == SET
6311 && SET_DEST (PATTERN (temp)) == old
6312 /* Make sure we can access insn_operand_constraint. */
6313 && asm_noperands (PATTERN (temp)) < 0
6314 /* This is unsafe if operand occurs more than once in current
6315 insn. Perhaps some occurrences aren't reloaded. */
6316 && count_occurrences (PATTERN (insn), old, 0) == 1)
6318 rtx old = SET_DEST (PATTERN (temp));
6319 /* Store into the reload register instead of the pseudo. */
6320 SET_DEST (PATTERN (temp)) = reloadreg;
6322 /* Verify that resulting insn is valid. */
6323 extract_insn (temp);
6324 if (constrain_operands (1))
6326 /* If the previous insn is an output reload, the source is
6327 a reload register, and its spill_reg_store entry will
6328 contain the previous destination. This is now
6330 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6331 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6333 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6334 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6337 /* If these are the only uses of the pseudo reg,
6338 pretend for GDB it lives in the reload reg we used. */
6339 if (REG_N_DEATHS (REGNO (old)) == 1
6340 && REG_N_SETS (REGNO (old)) == 1)
6342 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6343 alter_reg (REGNO (old), -1);
6349 SET_DEST (PATTERN (temp)) = old;
6354 /* We can't do that, so output an insn to load RELOADREG. */
6356 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6357 /* If we have a secondary reload, pick up the secondary register
6358 and icode, if any. If OLDEQUIV and OLD are different or
6359 if this is an in-out reload, recompute whether or not we
6360 still need a secondary register and what the icode should
6361 be. If we still need a secondary register and the class or
6362 icode is different, go back to reloading from OLD if using
6363 OLDEQUIV means that we got the wrong type of register. We
6364 cannot have different class or icode due to an in-out reload
6365 because we don't make such reloads when both the input and
6366 output need secondary reload registers. */
6368 if (! special && rl->secondary_in_reload >= 0)
6370 rtx second_reload_reg = 0;
6371 int secondary_reload = rl->secondary_in_reload;
6372 rtx real_oldequiv = oldequiv;
6375 enum insn_code icode;
6377 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6378 and similarly for OLD.
6379 See comments in get_secondary_reload in reload.c. */
6380 /* If it is a pseudo that cannot be replaced with its
6381 equivalent MEM, we must fall back to reload_in, which
6382 will have all the necessary substitutions registered.
6383 Likewise for a pseudo that can't be replaced with its
6384 equivalent constant.
6386 Take extra care for subregs of such pseudos. Note that
6387 we cannot use reg_equiv_mem in this case because it is
6388 not in the right mode. */
6391 if (GET_CODE (tmp) == SUBREG)
6392 tmp = SUBREG_REG (tmp);
6393 if (GET_CODE (tmp) == REG
6394 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6395 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6396 || reg_equiv_constant[REGNO (tmp)] != 0))
6398 if (! reg_equiv_mem[REGNO (tmp)]
6399 || num_not_at_initial_offset
6400 || GET_CODE (oldequiv) == SUBREG)
6401 real_oldequiv = rl->in;
6403 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6407 if (GET_CODE (tmp) == SUBREG)
6408 tmp = SUBREG_REG (tmp);
6409 if (GET_CODE (tmp) == REG
6410 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6411 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6412 || reg_equiv_constant[REGNO (tmp)] != 0))
6414 if (! reg_equiv_mem[REGNO (tmp)]
6415 || num_not_at_initial_offset
6416 || GET_CODE (old) == SUBREG)
6419 real_old = reg_equiv_mem[REGNO (tmp)];
6422 second_reload_reg = rld[secondary_reload].reg_rtx;
6423 icode = rl->secondary_in_icode;
6425 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6426 || (rl->in != 0 && rl->out != 0))
6428 enum reg_class new_class
6429 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6430 mode, real_oldequiv);
6432 if (new_class == NO_REGS)
6433 second_reload_reg = 0;
6436 enum insn_code new_icode;
6437 enum machine_mode new_mode;
6439 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6440 REGNO (second_reload_reg)))
6441 oldequiv = old, real_oldequiv = real_old;
6444 new_icode = reload_in_optab[(int) mode];
6445 if (new_icode != CODE_FOR_nothing
6446 && ((insn_data[(int) new_icode].operand[0].predicate
6447 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6449 || (insn_data[(int) new_icode].operand[1].predicate
6450 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6451 (real_oldequiv, mode)))))
6452 new_icode = CODE_FOR_nothing;
6454 if (new_icode == CODE_FOR_nothing)
6457 new_mode = insn_data[(int) new_icode].operand[2].mode;
6459 if (GET_MODE (second_reload_reg) != new_mode)
6461 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6463 oldequiv = old, real_oldequiv = real_old;
6466 = reload_adjust_reg_for_mode (second_reload_reg,
6473 /* If we still need a secondary reload register, check
6474 to see if it is being used as a scratch or intermediate
6475 register and generate code appropriately. If we need
6476 a scratch register, use REAL_OLDEQUIV since the form of
6477 the insn may depend on the actual address if it is
6480 if (second_reload_reg)
6482 if (icode != CODE_FOR_nothing)
6484 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6485 second_reload_reg));
6490 /* See if we need a scratch register to load the
6491 intermediate register (a tertiary reload). */
6492 enum insn_code tertiary_icode
6493 = rld[secondary_reload].secondary_in_icode;
6495 if (tertiary_icode != CODE_FOR_nothing)
6497 rtx third_reload_reg
6498 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6500 emit_insn ((GEN_FCN (tertiary_icode)
6501 (second_reload_reg, real_oldequiv,
6502 third_reload_reg)));
6505 gen_reload (second_reload_reg, real_oldequiv,
6509 oldequiv = second_reload_reg;
6515 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6517 rtx real_oldequiv = oldequiv;
6519 if ((GET_CODE (oldequiv) == REG
6520 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6521 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6522 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6523 || (GET_CODE (oldequiv) == SUBREG
6524 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6525 && (REGNO (SUBREG_REG (oldequiv))
6526 >= FIRST_PSEUDO_REGISTER)
6527 && ((reg_equiv_memory_loc
6528 [REGNO (SUBREG_REG (oldequiv))] != 0)
6529 || (reg_equiv_constant
6530 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6531 || (CONSTANT_P (oldequiv)
6532 && (PREFERRED_RELOAD_CLASS (oldequiv,
6533 REGNO_REG_CLASS (REGNO (reloadreg)))
6535 real_oldequiv = rl->in;
6536 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6540 if (flag_non_call_exceptions)
6541 copy_eh_notes (insn, get_insns ());
6543 /* End this sequence. */
6544 *where = get_insns ();
6547 /* Update reload_override_in so that delete_address_reloads_1
6548 can see the actual register usage. */
6550 reload_override_in[j] = oldequiv;
6553 /* Generate insns to for the output reload RL, which is for the insn described
6554 by CHAIN and has the number J. */
6556 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6559 rtx reloadreg = rl->reg_rtx;
6560 rtx insn = chain->insn;
6563 enum machine_mode mode = GET_MODE (old);
6566 if (rl->when_needed == RELOAD_OTHER)
6569 push_to_sequence (output_reload_insns[rl->opnum]);
6571 /* Determine the mode to reload in.
6572 See comments above (for input reloading). */
6574 if (mode == VOIDmode)
6576 /* VOIDmode should never happen for an output. */
6577 if (asm_noperands (PATTERN (insn)) < 0)
6578 /* It's the compiler's fault. */
6579 fatal_insn ("VOIDmode on an output", insn);
6580 error_for_asm (insn, "output operand is constant in `asm'");
6581 /* Prevent crash--use something we know is valid. */
6583 old = gen_rtx_REG (mode, REGNO (reloadreg));
6586 if (GET_MODE (reloadreg) != mode)
6587 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6589 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6591 /* If we need two reload regs, set RELOADREG to the intermediate
6592 one, since it will be stored into OLD. We might need a secondary
6593 register only for an input reload, so check again here. */
6595 if (rl->secondary_out_reload >= 0)
6599 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6600 && reg_equiv_mem[REGNO (old)] != 0)
6601 real_old = reg_equiv_mem[REGNO (old)];
6603 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6607 rtx second_reloadreg = reloadreg;
6608 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6610 /* See if RELOADREG is to be used as a scratch register
6611 or as an intermediate register. */
6612 if (rl->secondary_out_icode != CODE_FOR_nothing)
6614 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6615 (real_old, second_reloadreg, reloadreg)));
6620 /* See if we need both a scratch and intermediate reload
6623 int secondary_reload = rl->secondary_out_reload;
6624 enum insn_code tertiary_icode
6625 = rld[secondary_reload].secondary_out_icode;
6627 if (GET_MODE (reloadreg) != mode)
6628 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6630 if (tertiary_icode != CODE_FOR_nothing)
6633 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6636 /* Copy primary reload reg to secondary reload reg.
6637 (Note that these have been swapped above, then
6638 secondary reload reg to OLD using our insn.) */
6640 /* If REAL_OLD is a paradoxical SUBREG, remove it
6641 and try to put the opposite SUBREG on
6643 if (GET_CODE (real_old) == SUBREG
6644 && (GET_MODE_SIZE (GET_MODE (real_old))
6645 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6646 && 0 != (tem = gen_lowpart_common
6647 (GET_MODE (SUBREG_REG (real_old)),
6649 real_old = SUBREG_REG (real_old), reloadreg = tem;
6651 gen_reload (reloadreg, second_reloadreg,
6652 rl->opnum, rl->when_needed);
6653 emit_insn ((GEN_FCN (tertiary_icode)
6654 (real_old, reloadreg, third_reloadreg)));
6659 /* Copy between the reload regs here and then to
6662 gen_reload (reloadreg, second_reloadreg,
6663 rl->opnum, rl->when_needed);
6669 /* Output the last reload insn. */
6674 /* Don't output the last reload if OLD is not the dest of
6675 INSN and is in the src and is clobbered by INSN. */
6676 if (! flag_expensive_optimizations
6677 || GET_CODE (old) != REG
6678 || !(set = single_set (insn))
6679 || rtx_equal_p (old, SET_DEST (set))
6680 || !reg_mentioned_p (old, SET_SRC (set))
6681 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6682 gen_reload (old, reloadreg, rl->opnum,
6686 /* Look at all insns we emitted, just to be safe. */
6687 for (p = get_insns (); p; p = NEXT_INSN (p))
6690 rtx pat = PATTERN (p);
6692 /* If this output reload doesn't come from a spill reg,
6693 clear any memory of reloaded copies of the pseudo reg.
6694 If this output reload comes from a spill reg,
6695 reg_has_output_reload will make this do nothing. */
6696 note_stores (pat, forget_old_reloads_1, NULL);
6698 if (reg_mentioned_p (rl->reg_rtx, pat))
6700 rtx set = single_set (insn);
6701 if (reload_spill_index[j] < 0
6703 && SET_SRC (set) == rl->reg_rtx)
6705 int src = REGNO (SET_SRC (set));
6707 reload_spill_index[j] = src;
6708 SET_HARD_REG_BIT (reg_is_output_reload, src);
6709 if (find_regno_note (insn, REG_DEAD, src))
6710 SET_HARD_REG_BIT (reg_reloaded_died, src);
6712 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6714 int s = rl->secondary_out_reload;
6715 set = single_set (p);
6716 /* If this reload copies only to the secondary reload
6717 register, the secondary reload does the actual
6719 if (s >= 0 && set == NULL_RTX)
6720 /* We can't tell what function the secondary reload
6721 has and where the actual store to the pseudo is
6722 made; leave new_spill_reg_store alone. */
6725 && SET_SRC (set) == rl->reg_rtx
6726 && SET_DEST (set) == rld[s].reg_rtx)
6728 /* Usually the next instruction will be the
6729 secondary reload insn; if we can confirm
6730 that it is, setting new_spill_reg_store to
6731 that insn will allow an extra optimization. */
6732 rtx s_reg = rld[s].reg_rtx;
6733 rtx next = NEXT_INSN (p);
6734 rld[s].out = rl->out;
6735 rld[s].out_reg = rl->out_reg;
6736 set = single_set (next);
6737 if (set && SET_SRC (set) == s_reg
6738 && ! new_spill_reg_store[REGNO (s_reg)])
6740 SET_HARD_REG_BIT (reg_is_output_reload,
6742 new_spill_reg_store[REGNO (s_reg)] = next;
6746 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6751 if (rl->when_needed == RELOAD_OTHER)
6753 emit_insn (other_output_reload_insns[rl->opnum]);
6754 other_output_reload_insns[rl->opnum] = get_insns ();
6757 output_reload_insns[rl->opnum] = get_insns ();
6759 if (flag_non_call_exceptions)
6760 copy_eh_notes (insn, get_insns ());
6765 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6766 and has the number J. */
6768 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
6770 rtx insn = chain->insn;
6771 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6772 ? rl->in_reg : rl->in);
6775 /* AUTO_INC reloads need to be handled even if inherited. We got an
6776 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6777 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6778 && ! rtx_equal_p (rl->reg_rtx, old)
6779 && rl->reg_rtx != 0)
6780 emit_input_reload_insns (chain, rld + j, old, j);
6782 /* When inheriting a wider reload, we have a MEM in rl->in,
6783 e.g. inheriting a SImode output reload for
6784 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6785 if (optimize && reload_inherited[j] && rl->in
6786 && GET_CODE (rl->in) == MEM
6787 && GET_CODE (rl->in_reg) == MEM
6788 && reload_spill_index[j] >= 0
6789 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6790 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6792 /* If we are reloading a register that was recently stored in with an
6793 output-reload, see if we can prove there was
6794 actually no need to store the old value in it. */
6797 && (reload_inherited[j] || reload_override_in[j])
6799 && GET_CODE (rl->reg_rtx) == REG
6800 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6802 /* There doesn't seem to be any reason to restrict this to pseudos
6803 and doing so loses in the case where we are copying from a
6804 register of the wrong class. */
6805 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6806 >= FIRST_PSEUDO_REGISTER)
6808 /* The insn might have already some references to stackslots
6809 replaced by MEMs, while reload_out_reg still names the
6811 && (dead_or_set_p (insn,
6812 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6813 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6815 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6818 /* Do output reloading for reload RL, which is for the insn described by
6819 CHAIN and has the number J.
6820 ??? At some point we need to support handling output reloads of
6821 JUMP_INSNs or insns that set cc0. */
6823 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
6826 rtx insn = chain->insn;
6827 /* If this is an output reload that stores something that is
6828 not loaded in this same reload, see if we can eliminate a previous
6830 rtx pseudo = rl->out_reg;
6834 && GET_CODE (pseudo) == REG
6835 && ! rtx_equal_p (rl->in_reg, pseudo)
6836 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6837 && reg_last_reload_reg[REGNO (pseudo)])
6839 int pseudo_no = REGNO (pseudo);
6840 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6842 /* We don't need to test full validity of last_regno for
6843 inherit here; we only want to know if the store actually
6844 matches the pseudo. */
6845 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6846 && reg_reloaded_contents[last_regno] == pseudo_no
6847 && spill_reg_store[last_regno]
6848 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6849 delete_output_reload (insn, j, last_regno);
6854 || rl->reg_rtx == old
6855 || rl->reg_rtx == 0)
6858 /* An output operand that dies right away does need a reload,
6859 but need not be copied from it. Show the new location in the
6861 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6862 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6864 XEXP (note, 0) = rl->reg_rtx;
6867 /* Likewise for a SUBREG of an operand that dies. */
6868 else if (GET_CODE (old) == SUBREG
6869 && GET_CODE (SUBREG_REG (old)) == REG
6870 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6873 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6877 else if (GET_CODE (old) == SCRATCH)
6878 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6879 but we don't want to make an output reload. */
6882 /* If is a JUMP_INSN, we can't support output reloads yet. */
6883 if (GET_CODE (insn) == JUMP_INSN)
6886 emit_output_reload_insns (chain, rld + j, j);
6889 /* Output insns to reload values in and out of the chosen reload regs. */
6892 emit_reload_insns (struct insn_chain *chain)
6894 rtx insn = chain->insn;
6898 CLEAR_HARD_REG_SET (reg_reloaded_died);
6900 for (j = 0; j < reload_n_operands; j++)
6901 input_reload_insns[j] = input_address_reload_insns[j]
6902 = inpaddr_address_reload_insns[j]
6903 = output_reload_insns[j] = output_address_reload_insns[j]
6904 = outaddr_address_reload_insns[j]
6905 = other_output_reload_insns[j] = 0;
6906 other_input_address_reload_insns = 0;
6907 other_input_reload_insns = 0;
6908 operand_reload_insns = 0;
6909 other_operand_reload_insns = 0;
6911 /* Dump reloads into the dump file. */
6914 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6915 debug_reload_to_stream (rtl_dump_file);
6918 /* Now output the instructions to copy the data into and out of the
6919 reload registers. Do these in the order that the reloads were reported,
6920 since reloads of base and index registers precede reloads of operands
6921 and the operands may need the base and index registers reloaded. */
6923 for (j = 0; j < n_reloads; j++)
6926 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6927 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6929 do_input_reload (chain, rld + j, j);
6930 do_output_reload (chain, rld + j, j);
6933 /* Now write all the insns we made for reloads in the order expected by
6934 the allocation functions. Prior to the insn being reloaded, we write
6935 the following reloads:
6937 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6939 RELOAD_OTHER reloads.
6941 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6942 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6943 RELOAD_FOR_INPUT reload for the operand.
6945 RELOAD_FOR_OPADDR_ADDRS reloads.
6947 RELOAD_FOR_OPERAND_ADDRESS reloads.
6949 After the insn being reloaded, we write the following:
6951 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6952 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6953 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6954 reloads for the operand. The RELOAD_OTHER output reloads are
6955 output in descending order by reload number. */
6957 emit_insn_before (other_input_address_reload_insns, insn);
6958 emit_insn_before (other_input_reload_insns, insn);
6960 for (j = 0; j < reload_n_operands; j++)
6962 emit_insn_before (inpaddr_address_reload_insns[j], insn);
6963 emit_insn_before (input_address_reload_insns[j], insn);
6964 emit_insn_before (input_reload_insns[j], insn);
6967 emit_insn_before (other_operand_reload_insns, insn);
6968 emit_insn_before (operand_reload_insns, insn);
6970 for (j = 0; j < reload_n_operands; j++)
6972 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
6973 x = emit_insn_after (output_address_reload_insns[j], x);
6974 x = emit_insn_after (output_reload_insns[j], x);
6975 emit_insn_after (other_output_reload_insns[j], x);
6978 /* For all the spill regs newly reloaded in this instruction,
6979 record what they were reloaded from, so subsequent instructions
6980 can inherit the reloads.
6982 Update spill_reg_store for the reloads of this insn.
6983 Copy the elements that were updated in the loop above. */
6985 for (j = 0; j < n_reloads; j++)
6987 int r = reload_order[j];
6988 int i = reload_spill_index[r];
6990 /* If this is a non-inherited input reload from a pseudo, we must
6991 clear any memory of a previous store to the same pseudo. Only do
6992 something if there will not be an output reload for the pseudo
6994 if (rld[r].in_reg != 0
6995 && ! (reload_inherited[r] || reload_override_in[r]))
6997 rtx reg = rld[r].in_reg;
6999 if (GET_CODE (reg) == SUBREG)
7000 reg = SUBREG_REG (reg);
7002 if (GET_CODE (reg) == REG
7003 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7004 && ! reg_has_output_reload[REGNO (reg)])
7006 int nregno = REGNO (reg);
7008 if (reg_last_reload_reg[nregno])
7010 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7012 if (reg_reloaded_contents[last_regno] == nregno)
7013 spill_reg_store[last_regno] = 0;
7018 /* I is nonneg if this reload used a register.
7019 If rld[r].reg_rtx is 0, this is an optional reload
7020 that we opted to ignore. */
7022 if (i >= 0 && rld[r].reg_rtx != 0)
7024 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7026 int part_reaches_end = 0;
7027 int all_reaches_end = 1;
7029 /* For a multi register reload, we need to check if all or part
7030 of the value lives to the end. */
7031 for (k = 0; k < nr; k++)
7033 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7034 rld[r].when_needed))
7035 part_reaches_end = 1;
7037 all_reaches_end = 0;
7040 /* Ignore reloads that don't reach the end of the insn in
7042 if (all_reaches_end)
7044 /* First, clear out memory of what used to be in this spill reg.
7045 If consecutive registers are used, clear them all. */
7047 for (k = 0; k < nr; k++)
7048 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7050 /* Maybe the spill reg contains a copy of reload_out. */
7052 && (GET_CODE (rld[r].out) == REG
7056 || GET_CODE (rld[r].out_reg) == REG))
7058 rtx out = (GET_CODE (rld[r].out) == REG
7062 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7063 int nregno = REGNO (out);
7064 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7065 : HARD_REGNO_NREGS (nregno,
7066 GET_MODE (rld[r].reg_rtx)));
7068 spill_reg_store[i] = new_spill_reg_store[i];
7069 spill_reg_stored_to[i] = out;
7070 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7072 /* If NREGNO is a hard register, it may occupy more than
7073 one register. If it does, say what is in the
7074 rest of the registers assuming that both registers
7075 agree on how many words the object takes. If not,
7076 invalidate the subsequent registers. */
7078 if (nregno < FIRST_PSEUDO_REGISTER)
7079 for (k = 1; k < nnr; k++)
7080 reg_last_reload_reg[nregno + k]
7082 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7085 /* Now do the inverse operation. */
7086 for (k = 0; k < nr; k++)
7088 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7089 reg_reloaded_contents[i + k]
7090 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7093 reg_reloaded_insn[i + k] = insn;
7094 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7098 /* Maybe the spill reg contains a copy of reload_in. Only do
7099 something if there will not be an output reload for
7100 the register being reloaded. */
7101 else if (rld[r].out_reg == 0
7103 && ((GET_CODE (rld[r].in) == REG
7104 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7105 && ! reg_has_output_reload[REGNO (rld[r].in)])
7106 || (GET_CODE (rld[r].in_reg) == REG
7107 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7108 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7113 if (GET_CODE (rld[r].in) == REG
7114 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7115 nregno = REGNO (rld[r].in);
7116 else if (GET_CODE (rld[r].in_reg) == REG)
7117 nregno = REGNO (rld[r].in_reg);
7119 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7121 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7122 : HARD_REGNO_NREGS (nregno,
7123 GET_MODE (rld[r].reg_rtx)));
7125 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7127 if (nregno < FIRST_PSEUDO_REGISTER)
7128 for (k = 1; k < nnr; k++)
7129 reg_last_reload_reg[nregno + k]
7131 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7134 /* Unless we inherited this reload, show we haven't
7135 recently done a store.
7136 Previous stores of inherited auto_inc expressions
7137 also have to be discarded. */
7138 if (! reload_inherited[r]
7139 || (rld[r].out && ! rld[r].out_reg))
7140 spill_reg_store[i] = 0;
7142 for (k = 0; k < nr; k++)
7144 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7145 reg_reloaded_contents[i + k]
7146 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7149 reg_reloaded_insn[i + k] = insn;
7150 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7155 /* However, if part of the reload reaches the end, then we must
7156 invalidate the old info for the part that survives to the end. */
7157 else if (part_reaches_end)
7159 for (k = 0; k < nr; k++)
7160 if (reload_reg_reaches_end_p (i + k,
7162 rld[r].when_needed))
7163 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7167 /* The following if-statement was #if 0'd in 1.34 (or before...).
7168 It's reenabled in 1.35 because supposedly nothing else
7169 deals with this problem. */
7171 /* If a register gets output-reloaded from a non-spill register,
7172 that invalidates any previous reloaded copy of it.
7173 But forget_old_reloads_1 won't get to see it, because
7174 it thinks only about the original insn. So invalidate it here. */
7175 if (i < 0 && rld[r].out != 0
7176 && (GET_CODE (rld[r].out) == REG
7177 || (GET_CODE (rld[r].out) == MEM
7178 && GET_CODE (rld[r].out_reg) == REG)))
7180 rtx out = (GET_CODE (rld[r].out) == REG
7181 ? rld[r].out : rld[r].out_reg);
7182 int nregno = REGNO (out);
7183 if (nregno >= FIRST_PSEUDO_REGISTER)
7185 rtx src_reg, store_insn = NULL_RTX;
7187 reg_last_reload_reg[nregno] = 0;
7189 /* If we can find a hard register that is stored, record
7190 the storing insn so that we may delete this insn with
7191 delete_output_reload. */
7192 src_reg = rld[r].reg_rtx;
7194 /* If this is an optional reload, try to find the source reg
7195 from an input reload. */
7198 rtx set = single_set (insn);
7199 if (set && SET_DEST (set) == rld[r].out)
7203 src_reg = SET_SRC (set);
7205 for (k = 0; k < n_reloads; k++)
7207 if (rld[k].in == src_reg)
7209 src_reg = rld[k].reg_rtx;
7216 store_insn = new_spill_reg_store[REGNO (src_reg)];
7217 if (src_reg && GET_CODE (src_reg) == REG
7218 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7220 int src_regno = REGNO (src_reg);
7221 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7222 /* The place where to find a death note varies with
7223 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7224 necessarily checked exactly in the code that moves
7225 notes, so just check both locations. */
7226 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7227 if (! note && store_insn)
7228 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7231 spill_reg_store[src_regno + nr] = store_insn;
7232 spill_reg_stored_to[src_regno + nr] = out;
7233 reg_reloaded_contents[src_regno + nr] = nregno;
7234 reg_reloaded_insn[src_regno + nr] = store_insn;
7235 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7236 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7237 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7239 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7241 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7243 reg_last_reload_reg[nregno] = src_reg;
7248 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7250 while (num_regs-- > 0)
7251 reg_last_reload_reg[nregno + num_regs] = 0;
7255 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7258 /* Emit code to perform a reload from IN (which may be a reload register) to
7259 OUT (which may also be a reload register). IN or OUT is from operand
7260 OPNUM with reload type TYPE.
7262 Returns first insn emitted. */
7265 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7267 rtx last = get_last_insn ();
7270 /* If IN is a paradoxical SUBREG, remove it and try to put the
7271 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7272 if (GET_CODE (in) == SUBREG
7273 && (GET_MODE_SIZE (GET_MODE (in))
7274 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7275 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7276 in = SUBREG_REG (in), out = tem;
7277 else if (GET_CODE (out) == SUBREG
7278 && (GET_MODE_SIZE (GET_MODE (out))
7279 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7280 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7281 out = SUBREG_REG (out), in = tem;
7283 /* How to do this reload can get quite tricky. Normally, we are being
7284 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7285 register that didn't get a hard register. In that case we can just
7286 call emit_move_insn.
7288 We can also be asked to reload a PLUS that adds a register or a MEM to
7289 another register, constant or MEM. This can occur during frame pointer
7290 elimination and while reloading addresses. This case is handled by
7291 trying to emit a single insn to perform the add. If it is not valid,
7292 we use a two insn sequence.
7294 Finally, we could be called to handle an 'o' constraint by putting
7295 an address into a register. In that case, we first try to do this
7296 with a named pattern of "reload_load_address". If no such pattern
7297 exists, we just emit a SET insn and hope for the best (it will normally
7298 be valid on machines that use 'o').
7300 This entire process is made complex because reload will never
7301 process the insns we generate here and so we must ensure that
7302 they will fit their constraints and also by the fact that parts of
7303 IN might be being reloaded separately and replaced with spill registers.
7304 Because of this, we are, in some sense, just guessing the right approach
7305 here. The one listed above seems to work.
7307 ??? At some point, this whole thing needs to be rethought. */
7309 if (GET_CODE (in) == PLUS
7310 && (GET_CODE (XEXP (in, 0)) == REG
7311 || GET_CODE (XEXP (in, 0)) == SUBREG
7312 || GET_CODE (XEXP (in, 0)) == MEM)
7313 && (GET_CODE (XEXP (in, 1)) == REG
7314 || GET_CODE (XEXP (in, 1)) == SUBREG
7315 || CONSTANT_P (XEXP (in, 1))
7316 || GET_CODE (XEXP (in, 1)) == MEM))
7318 /* We need to compute the sum of a register or a MEM and another
7319 register, constant, or MEM, and put it into the reload
7320 register. The best possible way of doing this is if the machine
7321 has a three-operand ADD insn that accepts the required operands.
7323 The simplest approach is to try to generate such an insn and see if it
7324 is recognized and matches its constraints. If so, it can be used.
7326 It might be better not to actually emit the insn unless it is valid,
7327 but we need to pass the insn as an operand to `recog' and
7328 `extract_insn' and it is simpler to emit and then delete the insn if
7329 not valid than to dummy things up. */
7331 rtx op0, op1, tem, insn;
7334 op0 = find_replacement (&XEXP (in, 0));
7335 op1 = find_replacement (&XEXP (in, 1));
7337 /* Since constraint checking is strict, commutativity won't be
7338 checked, so we need to do that here to avoid spurious failure
7339 if the add instruction is two-address and the second operand
7340 of the add is the same as the reload reg, which is frequently
7341 the case. If the insn would be A = B + A, rearrange it so
7342 it will be A = A + B as constrain_operands expects. */
7344 if (GET_CODE (XEXP (in, 1)) == REG
7345 && REGNO (out) == REGNO (XEXP (in, 1)))
7346 tem = op0, op0 = op1, op1 = tem;
7348 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7349 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7351 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7352 code = recog_memoized (insn);
7356 extract_insn (insn);
7357 /* We want constrain operands to treat this insn strictly in
7358 its validity determination, i.e., the way it would after reload
7360 if (constrain_operands (1))
7364 delete_insns_since (last);
7366 /* If that failed, we must use a conservative two-insn sequence.
7368 Use a move to copy one operand into the reload register. Prefer
7369 to reload a constant, MEM or pseudo since the move patterns can
7370 handle an arbitrary operand. If OP1 is not a constant, MEM or
7371 pseudo and OP1 is not a valid operand for an add instruction, then
7374 After reloading one of the operands into the reload register, add
7375 the reload register to the output register.
7377 If there is another way to do this for a specific machine, a
7378 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7381 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7383 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7384 || (GET_CODE (op1) == REG
7385 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7386 || (code != CODE_FOR_nothing
7387 && ! ((*insn_data[code].operand[2].predicate)
7388 (op1, insn_data[code].operand[2].mode))))
7389 tem = op0, op0 = op1, op1 = tem;
7391 gen_reload (out, op0, opnum, type);
7393 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7394 This fixes a problem on the 32K where the stack pointer cannot
7395 be used as an operand of an add insn. */
7397 if (rtx_equal_p (op0, op1))
7400 insn = emit_insn (gen_add2_insn (out, op1));
7402 /* If that failed, copy the address register to the reload register.
7403 Then add the constant to the reload register. */
7405 code = recog_memoized (insn);
7409 extract_insn (insn);
7410 /* We want constrain operands to treat this insn strictly in
7411 its validity determination, i.e., the way it would after reload
7413 if (constrain_operands (1))
7415 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7417 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7422 delete_insns_since (last);
7424 gen_reload (out, op1, opnum, type);
7425 insn = emit_insn (gen_add2_insn (out, op0));
7426 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7429 #ifdef SECONDARY_MEMORY_NEEDED
7430 /* If we need a memory location to do the move, do it that way. */
7431 else if ((GET_CODE (in) == REG || GET_CODE (in) == SUBREG)
7432 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7433 && (GET_CODE (out) == REG || GET_CODE (out) == SUBREG)
7434 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7435 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7436 REGNO_REG_CLASS (reg_or_subregno (out)),
7439 /* Get the memory to use and rewrite both registers to its mode. */
7440 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7442 if (GET_MODE (loc) != GET_MODE (out))
7443 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7445 if (GET_MODE (loc) != GET_MODE (in))
7446 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7448 gen_reload (loc, in, opnum, type);
7449 gen_reload (out, loc, opnum, type);
7453 /* If IN is a simple operand, use gen_move_insn. */
7454 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7455 emit_insn (gen_move_insn (out, in));
7457 #ifdef HAVE_reload_load_address
7458 else if (HAVE_reload_load_address)
7459 emit_insn (gen_reload_load_address (out, in));
7462 /* Otherwise, just write (set OUT IN) and hope for the best. */
7464 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7466 /* Return the first insn emitted.
7467 We can not just return get_last_insn, because there may have
7468 been multiple instructions emitted. Also note that gen_move_insn may
7469 emit more than one insn itself, so we can not assume that there is one
7470 insn emitted per emit_insn_before call. */
7472 return last ? NEXT_INSN (last) : get_insns ();
7475 /* Delete a previously made output-reload whose result we now believe
7476 is not needed. First we double-check.
7478 INSN is the insn now being processed.
7479 LAST_RELOAD_REG is the hard register number for which we want to delete
7480 the last output reload.
7481 J is the reload-number that originally used REG. The caller has made
7482 certain that reload J doesn't use REG any longer for input. */
7485 delete_output_reload (rtx insn, int j, int last_reload_reg)
7487 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7488 rtx reg = spill_reg_stored_to[last_reload_reg];
7491 int n_inherited = 0;
7495 /* It is possible that this reload has been only used to set another reload
7496 we eliminated earlier and thus deleted this instruction too. */
7497 if (INSN_DELETED_P (output_reload_insn))
7500 /* Get the raw pseudo-register referred to. */
7502 while (GET_CODE (reg) == SUBREG)
7503 reg = SUBREG_REG (reg);
7504 substed = reg_equiv_memory_loc[REGNO (reg)];
7506 /* This is unsafe if the operand occurs more often in the current
7507 insn than it is inherited. */
7508 for (k = n_reloads - 1; k >= 0; k--)
7510 rtx reg2 = rld[k].in;
7513 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7514 reg2 = rld[k].in_reg;
7516 if (rld[k].out && ! rld[k].out_reg)
7517 reg2 = XEXP (rld[k].in_reg, 0);
7519 while (GET_CODE (reg2) == SUBREG)
7520 reg2 = SUBREG_REG (reg2);
7521 if (rtx_equal_p (reg2, reg))
7523 if (reload_inherited[k] || reload_override_in[k] || k == j)
7526 reg2 = rld[k].out_reg;
7529 while (GET_CODE (reg2) == SUBREG)
7530 reg2 = XEXP (reg2, 0);
7531 if (rtx_equal_p (reg2, reg))
7538 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7540 n_occurrences += count_occurrences (PATTERN (insn),
7541 eliminate_regs (substed, 0,
7543 if (n_occurrences > n_inherited)
7546 /* If the pseudo-reg we are reloading is no longer referenced
7547 anywhere between the store into it and here,
7548 and no jumps or labels intervene, then the value can get
7549 here through the reload reg alone.
7550 Otherwise, give up--return. */
7551 for (i1 = NEXT_INSN (output_reload_insn);
7552 i1 != insn; i1 = NEXT_INSN (i1))
7554 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7556 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7557 && reg_mentioned_p (reg, PATTERN (i1)))
7559 /* If this is USE in front of INSN, we only have to check that
7560 there are no more references than accounted for by inheritance. */
7561 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7563 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7564 i1 = NEXT_INSN (i1);
7566 if (n_occurrences <= n_inherited && i1 == insn)
7572 /* We will be deleting the insn. Remove the spill reg information. */
7573 for (k = HARD_REGNO_NREGS (last_reload_reg, GET_MODE (reg)); k-- > 0; )
7575 spill_reg_store[last_reload_reg + k] = 0;
7576 spill_reg_stored_to[last_reload_reg + k] = 0;
7579 /* The caller has already checked that REG dies or is set in INSN.
7580 It has also checked that we are optimizing, and thus some
7581 inaccuracies in the debugging information are acceptable.
7582 So we could just delete output_reload_insn. But in some cases
7583 we can improve the debugging information without sacrificing
7584 optimization - maybe even improving the code: See if the pseudo
7585 reg has been completely replaced with reload regs. If so, delete
7586 the store insn and forget we had a stack slot for the pseudo. */
7587 if (rld[j].out != rld[j].in
7588 && REG_N_DEATHS (REGNO (reg)) == 1
7589 && REG_N_SETS (REGNO (reg)) == 1
7590 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7591 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7595 /* We know that it was used only between here and the beginning of
7596 the current basic block. (We also know that the last use before
7597 INSN was the output reload we are thinking of deleting, but never
7598 mind that.) Search that range; see if any ref remains. */
7599 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7601 rtx set = single_set (i2);
7603 /* Uses which just store in the pseudo don't count,
7604 since if they are the only uses, they are dead. */
7605 if (set != 0 && SET_DEST (set) == reg)
7607 if (GET_CODE (i2) == CODE_LABEL
7608 || GET_CODE (i2) == JUMP_INSN)
7610 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7611 && reg_mentioned_p (reg, PATTERN (i2)))
7613 /* Some other ref remains; just delete the output reload we
7615 delete_address_reloads (output_reload_insn, insn);
7616 delete_insn (output_reload_insn);
7621 /* Delete the now-dead stores into this pseudo. Note that this
7622 loop also takes care of deleting output_reload_insn. */
7623 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7625 rtx set = single_set (i2);
7627 if (set != 0 && SET_DEST (set) == reg)
7629 delete_address_reloads (i2, insn);
7632 if (GET_CODE (i2) == CODE_LABEL
7633 || GET_CODE (i2) == JUMP_INSN)
7637 /* For the debugging info, say the pseudo lives in this reload reg. */
7638 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7639 alter_reg (REGNO (reg), -1);
7643 delete_address_reloads (output_reload_insn, insn);
7644 delete_insn (output_reload_insn);
7648 /* We are going to delete DEAD_INSN. Recursively delete loads of
7649 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7650 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7652 delete_address_reloads (rtx dead_insn, rtx current_insn)
7654 rtx set = single_set (dead_insn);
7655 rtx set2, dst, prev, next;
7658 rtx dst = SET_DEST (set);
7659 if (GET_CODE (dst) == MEM)
7660 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7662 /* If we deleted the store from a reloaded post_{in,de}c expression,
7663 we can delete the matching adds. */
7664 prev = PREV_INSN (dead_insn);
7665 next = NEXT_INSN (dead_insn);
7666 if (! prev || ! next)
7668 set = single_set (next);
7669 set2 = single_set (prev);
7671 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7672 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7673 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7675 dst = SET_DEST (set);
7676 if (! rtx_equal_p (dst, SET_DEST (set2))
7677 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7678 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7679 || (INTVAL (XEXP (SET_SRC (set), 1))
7680 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7682 delete_related_insns (prev);
7683 delete_related_insns (next);
7686 /* Subfunction of delete_address_reloads: process registers found in X. */
7688 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
7690 rtx prev, set, dst, i2;
7692 enum rtx_code code = GET_CODE (x);
7696 const char *fmt = GET_RTX_FORMAT (code);
7697 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7700 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7701 else if (fmt[i] == 'E')
7703 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7704 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7711 if (spill_reg_order[REGNO (x)] < 0)
7714 /* Scan backwards for the insn that sets x. This might be a way back due
7716 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7718 code = GET_CODE (prev);
7719 if (code == CODE_LABEL || code == JUMP_INSN)
7721 if (GET_RTX_CLASS (code) != 'i')
7723 if (reg_set_p (x, PATTERN (prev)))
7725 if (reg_referenced_p (x, PATTERN (prev)))
7728 if (! prev || INSN_UID (prev) < reload_first_uid)
7730 /* Check that PREV only sets the reload register. */
7731 set = single_set (prev);
7734 dst = SET_DEST (set);
7735 if (GET_CODE (dst) != REG
7736 || ! rtx_equal_p (dst, x))
7738 if (! reg_set_p (dst, PATTERN (dead_insn)))
7740 /* Check if DST was used in a later insn -
7741 it might have been inherited. */
7742 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7744 if (GET_CODE (i2) == CODE_LABEL)
7748 if (reg_referenced_p (dst, PATTERN (i2)))
7750 /* If there is a reference to the register in the current insn,
7751 it might be loaded in a non-inherited reload. If no other
7752 reload uses it, that means the register is set before
7754 if (i2 == current_insn)
7756 for (j = n_reloads - 1; j >= 0; j--)
7757 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7758 || reload_override_in[j] == dst)
7760 for (j = n_reloads - 1; j >= 0; j--)
7761 if (rld[j].in && rld[j].reg_rtx == dst)
7768 if (GET_CODE (i2) == JUMP_INSN)
7770 /* If DST is still live at CURRENT_INSN, check if it is used for
7771 any reload. Note that even if CURRENT_INSN sets DST, we still
7772 have to check the reloads. */
7773 if (i2 == current_insn)
7775 for (j = n_reloads - 1; j >= 0; j--)
7776 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7777 || reload_override_in[j] == dst)
7779 /* ??? We can't finish the loop here, because dst might be
7780 allocated to a pseudo in this block if no reload in this
7781 block needs any of the classes containing DST - see
7782 spill_hard_reg. There is no easy way to tell this, so we
7783 have to scan till the end of the basic block. */
7785 if (reg_set_p (dst, PATTERN (i2)))
7789 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7790 reg_reloaded_contents[REGNO (dst)] = -1;
7794 /* Output reload-insns to reload VALUE into RELOADREG.
7795 VALUE is an autoincrement or autodecrement RTX whose operand
7796 is a register or memory location;
7797 so reloading involves incrementing that location.
7798 IN is either identical to VALUE, or some cheaper place to reload from.
7800 INC_AMOUNT is the number to increment or decrement by (always positive).
7801 This cannot be deduced from VALUE.
7803 Return the instruction that stores into RELOADREG. */
7806 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
7808 /* REG or MEM to be copied and incremented. */
7809 rtx incloc = XEXP (value, 0);
7810 /* Nonzero if increment after copying. */
7811 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7817 rtx real_in = in == value ? XEXP (in, 0) : in;
7819 /* No hard register is equivalent to this register after
7820 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7821 we could inc/dec that register as well (maybe even using it for
7822 the source), but I'm not sure it's worth worrying about. */
7823 if (GET_CODE (incloc) == REG)
7824 reg_last_reload_reg[REGNO (incloc)] = 0;
7826 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7827 inc_amount = -inc_amount;
7829 inc = GEN_INT (inc_amount);
7831 /* If this is post-increment, first copy the location to the reload reg. */
7832 if (post && real_in != reloadreg)
7833 emit_insn (gen_move_insn (reloadreg, real_in));
7837 /* See if we can directly increment INCLOC. Use a method similar to
7838 that in gen_reload. */
7840 last = get_last_insn ();
7841 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7842 gen_rtx_PLUS (GET_MODE (incloc),
7845 code = recog_memoized (add_insn);
7848 extract_insn (add_insn);
7849 if (constrain_operands (1))
7851 /* If this is a pre-increment and we have incremented the value
7852 where it lives, copy the incremented value to RELOADREG to
7853 be used as an address. */
7856 emit_insn (gen_move_insn (reloadreg, incloc));
7861 delete_insns_since (last);
7864 /* If couldn't do the increment directly, must increment in RELOADREG.
7865 The way we do this depends on whether this is pre- or post-increment.
7866 For pre-increment, copy INCLOC to the reload register, increment it
7867 there, then save back. */
7871 if (in != reloadreg)
7872 emit_insn (gen_move_insn (reloadreg, real_in));
7873 emit_insn (gen_add2_insn (reloadreg, inc));
7874 store = emit_insn (gen_move_insn (incloc, reloadreg));
7879 Because this might be a jump insn or a compare, and because RELOADREG
7880 may not be available after the insn in an input reload, we must do
7881 the incrementation before the insn being reloaded for.
7883 We have already copied IN to RELOADREG. Increment the copy in
7884 RELOADREG, save that back, then decrement RELOADREG so it has
7885 the original value. */
7887 emit_insn (gen_add2_insn (reloadreg, inc));
7888 store = emit_insn (gen_move_insn (incloc, reloadreg));
7889 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7897 add_auto_inc_notes (rtx insn, rtx x)
7899 enum rtx_code code = GET_CODE (x);
7903 if (code == MEM && auto_inc_p (XEXP (x, 0)))
7906 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
7910 /* Scan all the operand sub-expressions. */
7911 fmt = GET_RTX_FORMAT (code);
7912 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7915 add_auto_inc_notes (insn, XEXP (x, i));
7916 else if (fmt[i] == 'E')
7917 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7918 add_auto_inc_notes (insn, XVECEXP (x, i, j));
7923 /* Copy EH notes from an insn to its reloads. */
7925 copy_eh_notes (rtx insn, rtx x)
7927 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
7930 for (; x != 0; x = NEXT_INSN (x))
7932 if (may_trap_p (PATTERN (x)))
7934 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
7940 /* This is used by reload pass, that does emit some instructions after
7941 abnormal calls moving basic block end, but in fact it wants to emit
7942 them on the edge. Looks for abnormal call edges, find backward the
7943 proper call and fix the damage.
7945 Similar handle instructions throwing exceptions internally. */
7947 fixup_abnormal_edges (void)
7949 bool inserted = false;
7956 /* Look for cases we are interested in - calls or instructions causing
7958 for (e = bb->succ; e; e = e->succ_next)
7960 if (e->flags & EDGE_ABNORMAL_CALL)
7962 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
7963 == (EDGE_ABNORMAL | EDGE_EH))
7966 if (e && GET_CODE (BB_END (bb)) != CALL_INSN
7967 && !can_throw_internal (BB_END (bb)))
7969 rtx insn = BB_END (bb), stop = NEXT_INSN (BB_END (bb));
7971 for (e = bb->succ; e; e = e->succ_next)
7972 if (e->flags & EDGE_FALLTHRU)
7974 /* Get past the new insns generated. Allow notes, as the insns may
7975 be already deleted. */
7976 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE)
7977 && !can_throw_internal (insn)
7978 && insn != BB_HEAD (bb))
7979 insn = PREV_INSN (insn);
7980 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn))
7984 insn = NEXT_INSN (insn);
7985 while (insn && insn != stop)
7987 next = NEXT_INSN (insn);
7992 /* Sometimes there's still the return value USE.
7993 If it's placed after a trapping call (i.e. that
7994 call is the last insn anyway), we have no fallthru
7995 edge. Simply delete this use and don't try to insert
7996 on the non-existent edge. */
7997 if (GET_CODE (PATTERN (insn)) != USE)
7999 /* We're not deleting it, we're moving it. */
8000 INSN_DELETED_P (insn) = 0;
8001 PREV_INSN (insn) = NULL_RTX;
8002 NEXT_INSN (insn) = NULL_RTX;
8004 insert_insn_on_edge (insn, e);
8011 /* We've possibly turned single trapping insn into multiple ones. */
8012 if (flag_non_call_exceptions)
8015 blocks = sbitmap_alloc (last_basic_block);
8016 sbitmap_ones (blocks);
8017 find_many_sub_basic_blocks (blocks);
8020 commit_edge_insertions ();
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