1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 88, 89, 92-97, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "insn-flags.h"
31 #include "insn-codes.h"
35 #include "basic-block.h"
42 /* This file contains the reload pass of the compiler, which is
43 run after register allocation has been done. It checks that
44 each insn is valid (operands required to be in registers really
45 are in registers of the proper class) and fixes up invalid ones
46 by copying values temporarily into registers for the insns
49 The results of register allocation are described by the vector
50 reg_renumber; the insns still contain pseudo regs, but reg_renumber
51 can be used to find which hard reg, if any, a pseudo reg is in.
53 The technique we always use is to free up a few hard regs that are
54 called ``reload regs'', and for each place where a pseudo reg
55 must be in a hard reg, copy it temporarily into one of the reload regs.
57 Reload regs are allocated locally for every instruction that needs
58 reloads. When there are pseudos which are allocated to a register that
59 has been chosen as a reload reg, such pseudos must be ``spilled''.
60 This means that they go to other hard regs, or to stack slots if no other
61 available hard regs can be found. Spilling can invalidate more
62 insns, requiring additional need for reloads, so we must keep checking
63 until the process stabilizes.
65 For machines with different classes of registers, we must keep track
66 of the register class needed for each reload, and make sure that
67 we allocate enough reload registers of each class.
69 The file reload.c contains the code that checks one insn for
70 validity and reports the reloads that it needs. This file
71 is in charge of scanning the entire rtl code, accumulating the
72 reload needs, spilling, assigning reload registers to use for
73 fixing up each insn, and generating the new insns to copy values
74 into the reload registers. */
77 #ifndef REGISTER_MOVE_COST
78 #define REGISTER_MOVE_COST(x, y) 2
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
106 This is used when the address is not valid as a memory address
107 (because its displacement is too big for the machine.) */
108 rtx *reg_equiv_address;
110 /* Element N is the memory slot to which pseudo reg N is equivalent,
111 or zero if pseudo reg N is not equivalent to a memory slot. */
114 /* Widest width in which each pseudo reg is referred to (via subreg). */
115 static int *reg_max_ref_width;
117 /* Element N is the list of insns that initialized reg N from its equivalent
118 constant or memory slot. */
119 static rtx *reg_equiv_init;
121 /* Vector to remember old contents of reg_renumber before spilling. */
122 static short *reg_old_renumber;
124 /* During reload_as_needed, element N contains the last pseudo regno reloaded
125 into hard register N. If that pseudo reg occupied more than one register,
126 reg_reloaded_contents points to that pseudo for each spill register in
127 use; all of these must remain set for an inheritance to occur. */
128 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
130 /* During reload_as_needed, element N contains the insn for which
131 hard register N was last used. Its contents are significant only
132 when reg_reloaded_valid is set for this register. */
133 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
135 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
136 static HARD_REG_SET reg_reloaded_valid;
137 /* Indicate if the register was dead at the end of the reload.
138 This is only valid if reg_reloaded_contents is set and valid. */
139 static HARD_REG_SET reg_reloaded_dead;
141 /* Number of spill-regs so far; number of valid elements of spill_regs. */
144 /* In parallel with spill_regs, contains REG rtx's for those regs.
145 Holds the last rtx used for any given reg, or 0 if it has never
146 been used for spilling yet. This rtx is reused, provided it has
148 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
150 /* In parallel with spill_regs, contains nonzero for a spill reg
151 that was stored after the last time it was used.
152 The precise value is the insn generated to do the store. */
153 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
155 /* This is the register that was stored with spill_reg_store. This is a
156 copy of reload_out / reload_out_reg when the value was stored; if
157 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
158 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
160 /* This table is the inverse mapping of spill_regs:
161 indexed by hard reg number,
162 it contains the position of that reg in spill_regs,
163 or -1 for something that is not in spill_regs.
165 ?!? This is no longer accurate. */
166 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
168 /* This reg set indicates registers that can't be used as spill registers for
169 the currently processed insn. These are the hard registers which are live
170 during the insn, but not allocated to pseudos, as well as fixed
172 static HARD_REG_SET bad_spill_regs;
174 /* These are the hard registers that can't be used as spill register for any
175 insn. This includes registers used for user variables and registers that
176 we can't eliminate. A register that appears in this set also can't be used
177 to retry register allocation. */
178 static HARD_REG_SET bad_spill_regs_global;
180 /* Describes order of use of registers for reloading
181 of spilled pseudo-registers. `n_spills' is the number of
182 elements that are actually valid; new ones are added at the end.
184 Both spill_regs and spill_reg_order are used on two occasions:
185 once during find_reload_regs, where they keep track of the spill registers
186 for a single insn, but also during reload_as_needed where they show all
187 the registers ever used by reload. For the latter case, the information
188 is calculated during finish_spills. */
189 static short spill_regs[FIRST_PSEUDO_REGISTER];
191 /* This vector of reg sets indicates, for each pseudo, which hard registers
192 may not be used for retrying global allocation because the register was
193 formerly spilled from one of them. If we allowed reallocating a pseudo to
194 a register that it was already allocated to, reload might not
196 static HARD_REG_SET *pseudo_previous_regs;
198 /* This vector of reg sets indicates, for each pseudo, which hard
199 registers may not be used for retrying global allocation because they
200 are used as spill registers during one of the insns in which the
202 static HARD_REG_SET *pseudo_forbidden_regs;
204 /* All hard regs that have been used as spill registers for any insn are
205 marked in this set. */
206 static HARD_REG_SET used_spill_regs;
208 /* Index of last register assigned as a spill register. We allocate in
209 a round-robin fashion. */
210 static int last_spill_reg;
212 /* Describes order of preference for putting regs into spill_regs.
213 Contains the numbers of all the hard regs, in order most preferred first.
214 This order is different for each function.
215 It is set up by order_regs_for_reload.
216 Empty elements at the end contain -1. */
217 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
219 /* Nonzero if indirect addressing is supported on the machine; this means
220 that spilling (REG n) does not require reloading it into a register in
221 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
222 value indicates the level of indirect addressing supported, e.g., two
223 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
225 static char spill_indirect_levels;
227 /* Nonzero if indirect addressing is supported when the innermost MEM is
228 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
229 which these are valid is the same as spill_indirect_levels, above. */
230 char indirect_symref_ok;
232 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
233 char double_reg_address_ok;
235 /* Record the stack slot for each spilled hard register. */
236 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
238 /* Width allocated so far for that stack slot. */
239 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
241 /* Record which pseudos needed to be spilled. */
242 static regset spilled_pseudos;
244 /* First uid used by insns created by reload in this function.
245 Used in find_equiv_reg. */
246 int reload_first_uid;
248 /* Flag set by local-alloc or global-alloc if anything is live in
249 a call-clobbered reg across calls. */
250 int caller_save_needed;
252 /* Set to 1 while reload_as_needed is operating.
253 Required by some machines to handle any generated moves differently. */
254 int reload_in_progress = 0;
256 /* These arrays record the insn_code of insns that may be needed to
257 perform input and output reloads of special objects. They provide a
258 place to pass a scratch register. */
259 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
260 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
262 /* This obstack is used for allocation of rtl during register elimination.
263 The allocated storage can be freed once find_reloads has processed the
265 struct obstack reload_obstack;
267 /* Points to the beginning of the reload_obstack. All insn_chain structures
268 are allocated first. */
269 char *reload_startobj;
271 /* The point after all insn_chain structures. Used to quickly deallocate
272 memory used while processing one insn. */
273 char *reload_firstobj;
275 #define obstack_chunk_alloc xmalloc
276 #define obstack_chunk_free free
278 /* List of labels that must never be deleted. */
279 extern rtx forced_labels;
281 /* List of insn_chain instructions, one for every insn that reload needs to
283 struct insn_chain *reload_insn_chain;
285 /* List of all insns needing reloads. */
286 static struct insn_chain *insns_need_reload;
288 /* This structure is used to record information about register eliminations.
289 Each array entry describes one possible way of eliminating a register
290 in favor of another. If there is more than one way of eliminating a
291 particular register, the most preferred should be specified first. */
295 int from; /* Register number to be eliminated. */
296 int to; /* Register number used as replacement. */
297 int initial_offset; /* Initial difference between values. */
298 int can_eliminate; /* Non-zero if this elimination can be done. */
299 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
300 insns made by reload. */
301 int offset; /* Current offset between the two regs. */
302 int previous_offset; /* Offset at end of previous insn. */
303 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
304 rtx from_rtx; /* REG rtx for the register to be eliminated.
305 We cannot simply compare the number since
306 we might then spuriously replace a hard
307 register corresponding to a pseudo
308 assigned to the reg to be eliminated. */
309 rtx to_rtx; /* REG rtx for the replacement. */
312 static struct elim_table * reg_eliminate = 0;
314 /* This is an intermediate structure to initialize the table. It has
315 exactly the members provided by ELIMINABLE_REGS. */
316 static struct elim_table_1
320 } reg_eliminate_1[] =
322 /* If a set of eliminable registers was specified, define the table from it.
323 Otherwise, default to the normal case of the frame pointer being
324 replaced by the stack pointer. */
326 #ifdef ELIMINABLE_REGS
329 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
332 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate_1/sizeof reg_eliminate_1[0])
334 /* Record the number of pending eliminations that have an offset not equal
335 to their initial offset. If non-zero, we use a new copy of each
336 replacement result in any insns encountered. */
337 int num_not_at_initial_offset;
339 /* Count the number of registers that we may be able to eliminate. */
340 static int num_eliminable;
342 /* For each label, we record the offset of each elimination. If we reach
343 a label by more than one path and an offset differs, we cannot do the
344 elimination. This information is indexed by the number of the label.
345 The first table is an array of flags that records whether we have yet
346 encountered a label and the second table is an array of arrays, one
347 entry in the latter array for each elimination. */
349 static char *offsets_known_at;
350 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
352 /* Number of labels in the current function. */
354 static int num_labels;
356 struct hard_reg_n_uses
362 static void maybe_fix_stack_asms PROTO((void));
363 static void calculate_needs_all_insns PROTO((int));
364 static void calculate_needs PROTO((struct insn_chain *));
365 static void find_reload_regs PROTO((struct insn_chain *chain,
367 static void find_tworeg_group PROTO((struct insn_chain *, int,
369 static void find_group PROTO((struct insn_chain *, int,
371 static int possible_group_p PROTO((struct insn_chain *, int));
372 static void count_possible_groups PROTO((struct insn_chain *, int));
373 static int modes_equiv_for_class_p PROTO((enum machine_mode,
376 static void delete_caller_save_insns PROTO((void));
378 static void spill_failure PROTO((rtx));
379 static void new_spill_reg PROTO((struct insn_chain *, int, int,
381 static void maybe_mark_pseudo_spilled PROTO((int));
382 static void delete_dead_insn PROTO((rtx));
383 static void alter_reg PROTO((int, int));
384 static void set_label_offsets PROTO((rtx, rtx, int));
385 static int eliminate_regs_in_insn PROTO((rtx, int));
386 static void update_eliminable_offsets PROTO((void));
387 static void mark_not_eliminable PROTO((rtx, rtx));
388 static void set_initial_elim_offsets PROTO((void));
389 static void verify_initial_elim_offsets PROTO((void));
390 static void set_initial_label_offsets PROTO((void));
391 static void set_offsets_for_label PROTO((rtx));
392 static void init_elim_table PROTO((void));
393 static void update_eliminables PROTO((HARD_REG_SET *));
394 static void spill_hard_reg PROTO((int, FILE *, int));
395 static int finish_spills PROTO((int, FILE *));
396 static void ior_hard_reg_set PROTO((HARD_REG_SET *, HARD_REG_SET *));
397 static void scan_paradoxical_subregs PROTO((rtx));
398 static int hard_reg_use_compare PROTO((const GENERIC_PTR, const GENERIC_PTR));
399 static void count_pseudo PROTO((struct hard_reg_n_uses *, int));
400 static void order_regs_for_reload PROTO((struct insn_chain *));
401 static void reload_as_needed PROTO((int));
402 static void forget_old_reloads_1 PROTO((rtx, rtx));
403 static int reload_reg_class_lower PROTO((const GENERIC_PTR, const GENERIC_PTR));
404 static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
406 static void clear_reload_reg_in_use PROTO((int, int, enum reload_type,
408 static int reload_reg_free_p PROTO((int, int, enum reload_type));
409 static int reload_reg_free_before_p PROTO((int, int, enum reload_type, int));
410 static int reload_reg_free_for_value_p PROTO((int, int, enum reload_type, rtx, rtx, int));
411 static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
412 static int allocate_reload_reg PROTO((struct insn_chain *, int, int,
414 static void choose_reload_regs PROTO((struct insn_chain *));
415 static void merge_assigned_reloads PROTO((rtx));
416 static void emit_reload_insns PROTO((struct insn_chain *));
417 static void delete_output_reload PROTO((rtx, int, int));
418 static void delete_address_reloads PROTO((rtx, rtx));
419 static void delete_address_reloads_1 PROTO((rtx, rtx, rtx));
420 static rtx inc_for_reload PROTO((rtx, rtx, rtx, int));
421 static int constraint_accepts_reg_p PROTO((char *, rtx));
422 static void reload_cse_regs_1 PROTO((rtx));
423 static void reload_cse_invalidate_regno PROTO((int, enum machine_mode, int));
424 static int reload_cse_mem_conflict_p PROTO((rtx, rtx));
425 static void reload_cse_invalidate_mem PROTO((rtx));
426 static void reload_cse_invalidate_rtx PROTO((rtx, rtx));
427 static int reload_cse_regno_equal_p PROTO((int, rtx, enum machine_mode));
428 static int reload_cse_noop_set_p PROTO((rtx, rtx));
429 static int reload_cse_simplify_set PROTO((rtx, rtx));
430 static int reload_cse_simplify_operands PROTO((rtx));
431 static void reload_cse_check_clobber PROTO((rtx, rtx));
432 static void reload_cse_record_set PROTO((rtx, rtx));
433 static void reload_combine PROTO((void));
434 static void reload_combine_note_use PROTO((rtx *, rtx));
435 static void reload_combine_note_store PROTO((rtx, rtx));
436 static void reload_cse_move2add PROTO((rtx));
437 static void move2add_note_store PROTO((rtx, rtx));
439 /* Initialize the reload pass once per compilation. */
446 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
447 Set spill_indirect_levels to the number of levels such addressing is
448 permitted, zero if it is not permitted at all. */
451 = gen_rtx_MEM (Pmode,
453 gen_rtx_REG (Pmode, LAST_VIRTUAL_REGISTER + 1),
455 spill_indirect_levels = 0;
457 while (memory_address_p (QImode, tem))
459 spill_indirect_levels++;
460 tem = gen_rtx_MEM (Pmode, tem);
463 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
465 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
466 indirect_symref_ok = memory_address_p (QImode, tem);
468 /* See if reg+reg is a valid (and offsettable) address. */
470 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
472 tem = gen_rtx_PLUS (Pmode,
473 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
474 gen_rtx_REG (Pmode, i));
475 /* This way, we make sure that reg+reg is an offsettable address. */
476 tem = plus_constant (tem, 4);
478 if (memory_address_p (QImode, tem))
480 double_reg_address_ok = 1;
485 /* Initialize obstack for our rtl allocation. */
486 gcc_obstack_init (&reload_obstack);
487 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
490 /* List of insn chains that are currently unused. */
491 static struct insn_chain *unused_insn_chains = 0;
493 /* Allocate an empty insn_chain structure. */
497 struct insn_chain *c;
499 if (unused_insn_chains == 0)
501 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
502 c->live_before = OBSTACK_ALLOC_REG_SET (&reload_obstack);
503 c->live_after = OBSTACK_ALLOC_REG_SET (&reload_obstack);
507 c = unused_insn_chains;
508 unused_insn_chains = c->next;
510 c->is_caller_save_insn = 0;
511 c->need_operand_change = 0;
517 /* Small utility function to set all regs in hard reg set TO which are
518 allocated to pseudos in regset FROM. */
520 compute_use_by_pseudos (to, from)
525 EXECUTE_IF_SET_IN_REG_SET
526 (from, FIRST_PSEUDO_REGISTER, regno,
528 int r = reg_renumber[regno];
532 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
534 SET_HARD_REG_BIT (*to, r + nregs);
538 /* Global variables used by reload and its subroutines. */
540 /* Set during calculate_needs if an insn needs register elimination. */
541 static int something_needs_elimination;
542 /* Set during calculate_needs if an insn needs an operand changed. */
543 int something_needs_operands_changed;
545 /* Nonzero means we couldn't get enough spill regs. */
548 /* Main entry point for the reload pass.
550 FIRST is the first insn of the function being compiled.
552 GLOBAL nonzero means we were called from global_alloc
553 and should attempt to reallocate any pseudoregs that we
554 displace from hard regs we will use for reloads.
555 If GLOBAL is zero, we do not have enough information to do that,
556 so any pseudo reg that is spilled must go to the stack.
558 DUMPFILE is the global-reg debugging dump file stream, or 0.
559 If it is nonzero, messages are written to it to describe
560 which registers are seized as reload regs, which pseudo regs
561 are spilled from them, and where the pseudo regs are reallocated to.
563 Return value is nonzero if reload failed
564 and we must not do any more for this function. */
567 reload (first, global, dumpfile)
574 register struct elim_table *ep;
576 /* The two pointers used to track the true location of the memory used
577 for label offsets. */
578 char *real_known_ptr = NULL_PTR;
579 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
581 /* Make sure even insns with volatile mem refs are recognizable. */
586 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
588 /* Make sure that the last insn in the chain
589 is not something that needs reloading. */
590 emit_note (NULL_PTR, NOTE_INSN_DELETED);
592 /* Enable find_equiv_reg to distinguish insns made by reload. */
593 reload_first_uid = get_max_uid ();
595 #ifdef SECONDARY_MEMORY_NEEDED
596 /* Initialize the secondary memory table. */
597 clear_secondary_mem ();
600 /* We don't have a stack slot for any spill reg yet. */
601 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
602 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
604 /* Initialize the save area information for caller-save, in case some
608 /* Compute which hard registers are now in use
609 as homes for pseudo registers.
610 This is done here rather than (eg) in global_alloc
611 because this point is reached even if not optimizing. */
612 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
615 /* A function that receives a nonlocal goto must save all call-saved
617 if (current_function_has_nonlocal_label)
618 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
620 if (! call_used_regs[i] && ! fixed_regs[i])
621 regs_ever_live[i] = 1;
624 /* Find all the pseudo registers that didn't get hard regs
625 but do have known equivalent constants or memory slots.
626 These include parameters (known equivalent to parameter slots)
627 and cse'd or loop-moved constant memory addresses.
629 Record constant equivalents in reg_equiv_constant
630 so they will be substituted by find_reloads.
631 Record memory equivalents in reg_mem_equiv so they can
632 be substituted eventually by altering the REG-rtx's. */
634 reg_equiv_constant = (rtx *) xmalloc (max_regno * sizeof (rtx));
635 bzero ((char *) reg_equiv_constant, max_regno * sizeof (rtx));
636 reg_equiv_memory_loc = (rtx *) xmalloc (max_regno * sizeof (rtx));
637 bzero ((char *) reg_equiv_memory_loc, max_regno * sizeof (rtx));
638 reg_equiv_mem = (rtx *) xmalloc (max_regno * sizeof (rtx));
639 bzero ((char *) reg_equiv_mem, max_regno * sizeof (rtx));
640 reg_equiv_init = (rtx *) xmalloc (max_regno * sizeof (rtx));
641 bzero ((char *) reg_equiv_init, max_regno * sizeof (rtx));
642 reg_equiv_address = (rtx *) xmalloc (max_regno * sizeof (rtx));
643 bzero ((char *) reg_equiv_address, max_regno * sizeof (rtx));
644 reg_max_ref_width = (int *) xmalloc (max_regno * sizeof (int));
645 bzero ((char *) reg_max_ref_width, max_regno * sizeof (int));
646 reg_old_renumber = (short *) xmalloc (max_regno * sizeof (short));
647 bcopy (reg_renumber, reg_old_renumber, max_regno * sizeof (short));
648 pseudo_forbidden_regs
649 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
651 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
653 CLEAR_HARD_REG_SET (bad_spill_regs_global);
654 bzero ((char *) pseudo_previous_regs, max_regno * sizeof (HARD_REG_SET));
656 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
657 Also find all paradoxical subregs and find largest such for each pseudo.
658 On machines with small register classes, record hard registers that
659 are used for user variables. These can never be used for spills.
660 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
661 caller-saved registers must be marked live. */
663 for (insn = first; insn; insn = NEXT_INSN (insn))
665 rtx set = single_set (insn);
667 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
668 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
669 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
670 if (! call_used_regs[i])
671 regs_ever_live[i] = 1;
673 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
675 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
677 #ifdef LEGITIMATE_PIC_OPERAND_P
678 && (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic
679 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
683 rtx x = XEXP (note, 0);
684 i = REGNO (SET_DEST (set));
685 if (i > LAST_VIRTUAL_REGISTER)
687 if (GET_CODE (x) == MEM)
689 /* If the operand is a PLUS, the MEM may be shared,
690 so make sure we have an unshared copy here. */
691 if (GET_CODE (XEXP (x, 0)) == PLUS)
694 reg_equiv_memory_loc[i] = x;
696 else if (CONSTANT_P (x))
698 if (LEGITIMATE_CONSTANT_P (x))
699 reg_equiv_constant[i] = x;
701 reg_equiv_memory_loc[i]
702 = force_const_mem (GET_MODE (SET_DEST (set)), x);
707 /* If this register is being made equivalent to a MEM
708 and the MEM is not SET_SRC, the equivalencing insn
709 is one with the MEM as a SET_DEST and it occurs later.
710 So don't mark this insn now. */
711 if (GET_CODE (x) != MEM
712 || rtx_equal_p (SET_SRC (set), x))
714 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
719 /* If this insn is setting a MEM from a register equivalent to it,
720 this is the equivalencing insn. */
721 else if (set && GET_CODE (SET_DEST (set)) == MEM
722 && GET_CODE (SET_SRC (set)) == REG
723 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
724 && rtx_equal_p (SET_DEST (set),
725 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
726 reg_equiv_init[REGNO (SET_SRC (set))]
727 = gen_rtx_INSN_LIST (VOIDmode, insn,
728 reg_equiv_init[REGNO (SET_SRC (set))]);
730 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
731 scan_paradoxical_subregs (PATTERN (insn));
736 num_labels = max_label_num () - get_first_label_num ();
738 /* Allocate the tables used to store offset information at labels. */
739 /* We used to use alloca here, but the size of what it would try to
740 allocate would occasionally cause it to exceed the stack limit and
741 cause a core dump. */
742 real_known_ptr = xmalloc (num_labels);
744 = (int (*)[NUM_ELIMINABLE_REGS])
745 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
747 offsets_known_at = real_known_ptr - get_first_label_num ();
749 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
751 /* Alter each pseudo-reg rtx to contain its hard reg number.
752 Assign stack slots to the pseudos that lack hard regs or equivalents.
753 Do not touch virtual registers. */
755 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
758 /* If we have some registers we think can be eliminated, scan all insns to
759 see if there is an insn that sets one of these registers to something
760 other than itself plus a constant. If so, the register cannot be
761 eliminated. Doing this scan here eliminates an extra pass through the
762 main reload loop in the most common case where register elimination
764 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
765 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
766 || GET_CODE (insn) == CALL_INSN)
767 note_stores (PATTERN (insn), mark_not_eliminable);
769 #ifndef REGISTER_CONSTRAINTS
770 /* If all the pseudo regs have hard regs,
771 except for those that are never referenced,
772 we know that no reloads are needed. */
773 /* But that is not true if there are register constraints, since
774 in that case some pseudos might be in the wrong kind of hard reg. */
776 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
777 if (reg_renumber[i] == -1 && REG_N_REFS (i) != 0)
780 if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
782 free (real_known_ptr);
784 free (reg_equiv_constant);
785 free (reg_equiv_memory_loc);
786 free (reg_equiv_mem);
787 free (reg_equiv_init);
788 free (reg_equiv_address);
789 free (reg_max_ref_width);
790 free (reg_old_renumber);
791 free (pseudo_previous_regs);
792 free (pseudo_forbidden_regs);
797 maybe_fix_stack_asms ();
799 insns_need_reload = 0;
800 something_needs_elimination = 0;
802 /* Initialize to -1, which means take the first spill register. */
805 spilled_pseudos = ALLOCA_REG_SET ();
807 /* Spill any hard regs that we know we can't eliminate. */
808 CLEAR_HARD_REG_SET (used_spill_regs);
809 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
810 if (! ep->can_eliminate)
811 spill_hard_reg (ep->from, dumpfile, 1);
813 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
814 if (frame_pointer_needed)
815 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, dumpfile, 1);
817 finish_spills (global, dumpfile);
819 /* From now on, we need to emit any moves without making new pseudos. */
820 reload_in_progress = 1;
822 /* This loop scans the entire function each go-round
823 and repeats until one repetition spills no additional hard regs. */
826 int something_changed;
828 struct insn_chain *chain;
830 HOST_WIDE_INT starting_frame_size;
832 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done
833 here because the stack size may be a part of the offset computation
834 for register elimination, and there might have been new stack slots
835 created in the last iteration of this loop. */
836 assign_stack_local (BLKmode, 0, 0);
838 starting_frame_size = get_frame_size ();
840 set_initial_elim_offsets ();
841 set_initial_label_offsets ();
843 /* For each pseudo register that has an equivalent location defined,
844 try to eliminate any eliminable registers (such as the frame pointer)
845 assuming initial offsets for the replacement register, which
848 If the resulting location is directly addressable, substitute
849 the MEM we just got directly for the old REG.
851 If it is not addressable but is a constant or the sum of a hard reg
852 and constant, it is probably not addressable because the constant is
853 out of range, in that case record the address; we will generate
854 hairy code to compute the address in a register each time it is
855 needed. Similarly if it is a hard register, but one that is not
856 valid as an address register.
858 If the location is not addressable, but does not have one of the
859 above forms, assign a stack slot. We have to do this to avoid the
860 potential of producing lots of reloads if, e.g., a location involves
861 a pseudo that didn't get a hard register and has an equivalent memory
862 location that also involves a pseudo that didn't get a hard register.
864 Perhaps at some point we will improve reload_when_needed handling
865 so this problem goes away. But that's very hairy. */
867 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
868 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
870 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
872 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
874 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
875 else if (CONSTANT_P (XEXP (x, 0))
876 || (GET_CODE (XEXP (x, 0)) == REG
877 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
878 || (GET_CODE (XEXP (x, 0)) == PLUS
879 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
880 && (REGNO (XEXP (XEXP (x, 0), 0))
881 < FIRST_PSEUDO_REGISTER)
882 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
883 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
886 /* Make a new stack slot. Then indicate that something
887 changed so we go back and recompute offsets for
888 eliminable registers because the allocation of memory
889 below might change some offset. reg_equiv_{mem,address}
890 will be set up for this pseudo on the next pass around
892 reg_equiv_memory_loc[i] = 0;
893 reg_equiv_init[i] = 0;
898 if (caller_save_needed)
901 /* If we allocated another stack slot, redo elimination bookkeeping. */
902 if (starting_frame_size != get_frame_size ())
905 if (caller_save_needed)
907 save_call_clobbered_regs ();
908 /* That might have allocated new insn_chain structures. */
909 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
912 calculate_needs_all_insns (global);
914 CLEAR_REG_SET (spilled_pseudos);
917 something_changed = 0;
919 /* If we allocated any new memory locations, make another pass
920 since it might have changed elimination offsets. */
921 if (starting_frame_size != get_frame_size ())
922 something_changed = 1;
925 HARD_REG_SET to_spill;
926 CLEAR_HARD_REG_SET (to_spill);
927 update_eliminables (&to_spill);
928 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
929 if (TEST_HARD_REG_BIT (to_spill, i))
931 spill_hard_reg (i, dumpfile, 1);
934 /* Regardless of the state of spills, if we previously had
935 a register that we thought we could eliminate, but no can
936 not eliminate, we must run another pass.
938 Consider pseudos which have an entry in reg_equiv_* which
939 reference an eliminable register. We must make another pass
940 to update reg_equiv_* so that we do not substitute in the
941 old value from when we thought the elimination could be
943 something_changed = 1;
947 CLEAR_HARD_REG_SET (used_spill_regs);
948 /* Try to satisfy the needs for each insn. */
949 for (chain = insns_need_reload; chain != 0;
950 chain = chain->next_need_reload)
951 find_reload_regs (chain, dumpfile);
956 if (insns_need_reload != 0 || did_spill)
957 something_changed |= finish_spills (global, dumpfile);
959 if (! something_changed)
962 if (caller_save_needed)
963 delete_caller_save_insns ();
966 /* If global-alloc was run, notify it of any register eliminations we have
969 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
970 if (ep->can_eliminate)
971 mark_elimination (ep->from, ep->to);
973 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
974 If that insn didn't set the register (i.e., it copied the register to
975 memory), just delete that insn instead of the equivalencing insn plus
976 anything now dead. If we call delete_dead_insn on that insn, we may
977 delete the insn that actually sets the register if the register dies
978 there and that is incorrect. */
980 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
982 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
985 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
987 rtx equiv_insn = XEXP (list, 0);
988 if (GET_CODE (equiv_insn) == NOTE)
990 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
991 delete_dead_insn (equiv_insn);
994 PUT_CODE (equiv_insn, NOTE);
995 NOTE_SOURCE_FILE (equiv_insn) = 0;
996 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1002 /* Use the reload registers where necessary
1003 by generating move instructions to move the must-be-register
1004 values into or out of the reload registers. */
1006 if (insns_need_reload != 0 || something_needs_elimination
1007 || something_needs_operands_changed)
1009 int old_frame_size = get_frame_size ();
1011 reload_as_needed (global);
1013 if (old_frame_size != get_frame_size ())
1017 verify_initial_elim_offsets ();
1020 /* If we were able to eliminate the frame pointer, show that it is no
1021 longer live at the start of any basic block. If it ls live by
1022 virtue of being in a pseudo, that pseudo will be marked live
1023 and hence the frame pointer will be known to be live via that
1026 if (! frame_pointer_needed)
1027 for (i = 0; i < n_basic_blocks; i++)
1028 CLEAR_REGNO_REG_SET (basic_block_live_at_start[i],
1029 HARD_FRAME_POINTER_REGNUM);
1031 /* Come here (with failure set nonzero) if we can't get enough spill regs
1032 and we decide not to abort about it. */
1035 reload_in_progress = 0;
1037 /* Now eliminate all pseudo regs by modifying them into
1038 their equivalent memory references.
1039 The REG-rtx's for the pseudos are modified in place,
1040 so all insns that used to refer to them now refer to memory.
1042 For a reg that has a reg_equiv_address, all those insns
1043 were changed by reloading so that no insns refer to it any longer;
1044 but the DECL_RTL of a variable decl may refer to it,
1045 and if so this causes the debugging info to mention the variable. */
1047 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1051 int is_readonly = 0;
1053 if (reg_equiv_memory_loc[i])
1055 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1056 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1059 if (reg_equiv_mem[i])
1060 addr = XEXP (reg_equiv_mem[i], 0);
1062 if (reg_equiv_address[i])
1063 addr = reg_equiv_address[i];
1067 if (reg_renumber[i] < 0)
1069 rtx reg = regno_reg_rtx[i];
1070 XEXP (reg, 0) = addr;
1071 REG_USERVAR_P (reg) = 0;
1072 RTX_UNCHANGING_P (reg) = is_readonly;
1073 MEM_IN_STRUCT_P (reg) = in_struct;
1074 /* We have no alias information about this newly created
1076 MEM_ALIAS_SET (reg) = 0;
1077 PUT_CODE (reg, MEM);
1079 else if (reg_equiv_mem[i])
1080 XEXP (reg_equiv_mem[i], 0) = addr;
1084 /* We've finished reloading. This reload_completed must be set before we
1085 perform instruction splitting below. */
1086 reload_completed = 1;
1088 /* Make a pass over all the insns and delete all USEs which we inserted
1089 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1090 notes. Delete all CLOBBER insns and simplify (subreg (reg)) operands. */
1092 for (insn = first; insn; insn = NEXT_INSN (insn))
1093 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1097 if ((GET_CODE (PATTERN (insn)) == USE
1098 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1099 || GET_CODE (PATTERN (insn)) == CLOBBER)
1101 PUT_CODE (insn, NOTE);
1102 NOTE_SOURCE_FILE (insn) = 0;
1103 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1107 pnote = ®_NOTES (insn);
1110 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1111 || REG_NOTE_KIND (*pnote) == REG_UNUSED)
1112 *pnote = XEXP (*pnote, 1);
1114 pnote = &XEXP (*pnote, 1);
1117 /* And simplify (subreg (reg)) if it appears as an operand. */
1118 cleanup_subreg_operands (insn);
1120 /* If optimizing and we are performing instruction scheduling after
1121 reload, then go ahead and split insns now since we are about to
1122 recompute flow information anyway. */
1123 if (optimize && flag_schedule_insns_after_reload)
1127 last = try_split (PATTERN (insn), insn, 1);
1131 PUT_CODE (insn, NOTE);
1132 NOTE_SOURCE_FILE (insn) = 0;
1133 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1139 /* If we are doing stack checking, give a warning if this function's
1140 frame size is larger than we expect. */
1141 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1143 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1145 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1146 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1147 size += UNITS_PER_WORD;
1149 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1150 warning ("frame size too large for reliable stack checking");
1153 /* Indicate that we no longer have known memory locations or constants. */
1154 if (reg_equiv_constant)
1155 free (reg_equiv_constant);
1156 reg_equiv_constant = 0;
1157 if (reg_equiv_memory_loc)
1158 free (reg_equiv_memory_loc);
1159 reg_equiv_memory_loc = 0;
1162 free (real_known_ptr);
1166 free (reg_equiv_mem);
1167 free (reg_equiv_init);
1168 free (reg_equiv_address);
1169 free (reg_max_ref_width);
1170 free (reg_old_renumber);
1171 free (pseudo_previous_regs);
1172 free (pseudo_forbidden_regs);
1174 FREE_REG_SET (spilled_pseudos);
1176 CLEAR_HARD_REG_SET (used_spill_regs);
1177 for (i = 0; i < n_spills; i++)
1178 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1180 /* Free all the insn_chain structures at once. */
1181 obstack_free (&reload_obstack, reload_startobj);
1182 unused_insn_chains = 0;
1187 /* Yet another special case. Unfortunately, reg-stack forces people to
1188 write incorrect clobbers in asm statements. These clobbers must not
1189 cause the register to appear in bad_spill_regs, otherwise we'll call
1190 fatal_insn later. We clear the corresponding regnos in the live
1191 register sets to avoid this.
1192 The whole thing is rather sick, I'm afraid. */
1194 maybe_fix_stack_asms ()
1197 char *constraints[MAX_RECOG_OPERANDS];
1198 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1199 struct insn_chain *chain;
1201 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1204 HARD_REG_SET clobbered, allowed;
1207 if (GET_RTX_CLASS (GET_CODE (chain->insn)) != 'i'
1208 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1210 pat = PATTERN (chain->insn);
1211 if (GET_CODE (pat) != PARALLEL)
1214 CLEAR_HARD_REG_SET (clobbered);
1215 CLEAR_HARD_REG_SET (allowed);
1217 /* First, make a mask of all stack regs that are clobbered. */
1218 for (i = 0; i < XVECLEN (pat, 0); i++)
1220 rtx t = XVECEXP (pat, 0, i);
1221 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1222 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1225 /* Get the operand values and constraints out of the insn. */
1226 decode_asm_operands (pat, recog_operand, recog_operand_loc,
1227 constraints, operand_mode);
1229 /* For every operand, see what registers are allowed. */
1230 for (i = 0; i < noperands; i++)
1232 char *p = constraints[i];
1233 /* For every alternative, we compute the class of registers allowed
1234 for reloading in CLS, and merge its contents into the reg set
1236 int cls = (int) NO_REGS;
1242 if (c == '\0' || c == ',' || c == '#')
1244 /* End of one alternative - mark the regs in the current
1245 class, and reset the class. */
1246 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1251 } while (c != '\0' && c != ',');
1259 case '=': case '+': case '*': case '%': case '?': case '!':
1260 case '0': case '1': case '2': case '3': case '4': case 'm':
1261 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1262 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1263 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1265 #ifdef EXTRA_CONSTRAINT
1266 case 'Q': case 'R': case 'S': case 'T': case 'U':
1271 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1276 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1280 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1285 /* Those of the registers which are clobbered, but allowed by the
1286 constraints, must be usable as reload registers. So clear them
1287 out of the life information. */
1288 AND_HARD_REG_SET (allowed, clobbered);
1289 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1290 if (TEST_HARD_REG_BIT (allowed, i))
1292 CLEAR_REGNO_REG_SET (chain->live_before, i);
1293 CLEAR_REGNO_REG_SET (chain->live_after, i);
1301 /* Walk the chain of insns, and determine for each whether it needs reloads
1302 and/or eliminations. Build the corresponding insns_need_reload list, and
1303 set something_needs_elimination as appropriate. */
1305 calculate_needs_all_insns (global)
1308 struct insn_chain **pprev_reload = &insns_need_reload;
1309 struct insn_chain **pchain;
1311 something_needs_elimination = 0;
1313 for (pchain = &reload_insn_chain; *pchain != 0; pchain = &(*pchain)->next)
1316 struct insn_chain *chain;
1321 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1322 include REG_LABEL), we need to see what effects this has on the
1323 known offsets at labels. */
1325 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1326 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1327 && REG_NOTES (insn) != 0))
1328 set_label_offsets (insn, insn, 0);
1330 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1332 rtx old_body = PATTERN (insn);
1333 int old_code = INSN_CODE (insn);
1334 rtx old_notes = REG_NOTES (insn);
1335 int did_elimination = 0;
1336 int operands_changed = 0;
1338 /* If needed, eliminate any eliminable registers. */
1340 did_elimination = eliminate_regs_in_insn (insn, 0);
1342 /* Analyze the instruction. */
1343 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1344 global, spill_reg_order);
1346 /* If a no-op set needs more than one reload, this is likely
1347 to be something that needs input address reloads. We
1348 can't get rid of this cleanly later, and it is of no use
1349 anyway, so discard it now.
1350 We only do this when expensive_optimizations is enabled,
1351 since this complements reload inheritance / output
1352 reload deletion, and it can make debugging harder. */
1353 if (flag_expensive_optimizations && n_reloads > 1)
1355 rtx set = single_set (insn);
1357 && SET_SRC (set) == SET_DEST (set)
1358 && GET_CODE (SET_SRC (set)) == REG
1359 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1361 PUT_CODE (insn, NOTE);
1362 NOTE_SOURCE_FILE (insn) = 0;
1363 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1368 update_eliminable_offsets ();
1370 /* Remember for later shortcuts which insns had any reloads or
1371 register eliminations. */
1372 chain->need_elim = did_elimination;
1373 chain->need_reload = n_reloads > 0;
1374 chain->need_operand_change = operands_changed;
1376 /* Discard any register replacements done. */
1377 if (did_elimination)
1379 obstack_free (&reload_obstack, reload_firstobj);
1380 PATTERN (insn) = old_body;
1381 INSN_CODE (insn) = old_code;
1382 REG_NOTES (insn) = old_notes;
1383 something_needs_elimination = 1;
1386 something_needs_operands_changed |= operands_changed;
1390 *pprev_reload = chain;
1391 pprev_reload = &chain->next_need_reload;
1393 calculate_needs (chain);
1400 /* Compute the most additional registers needed by one instruction,
1401 given by CHAIN. Collect information separately for each class of regs.
1403 To compute the number of reload registers of each class needed for an
1404 insn, we must simulate what choose_reload_regs can do. We do this by
1405 splitting an insn into an "input" and an "output" part. RELOAD_OTHER
1406 reloads are used in both. The input part uses those reloads,
1407 RELOAD_FOR_INPUT reloads, which must be live over the entire input section
1408 of reloads, and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
1409 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the inputs.
1411 The registers needed for output are RELOAD_OTHER and RELOAD_FOR_OUTPUT,
1412 which are live for the entire output portion, and the maximum of all the
1413 RELOAD_FOR_OUTPUT_ADDRESS reloads for each operand.
1415 The total number of registers needed is the maximum of the
1416 inputs and outputs. */
1419 calculate_needs (chain)
1420 struct insn_chain *chain;
1424 /* Each `struct needs' corresponds to one RELOAD_... type. */
1428 struct needs output;
1430 struct needs other_addr;
1431 struct needs op_addr;
1432 struct needs op_addr_reload;
1433 struct needs in_addr[MAX_RECOG_OPERANDS];
1434 struct needs in_addr_addr[MAX_RECOG_OPERANDS];
1435 struct needs out_addr[MAX_RECOG_OPERANDS];
1436 struct needs out_addr_addr[MAX_RECOG_OPERANDS];
1439 bzero ((char *) chain->group_size, sizeof chain->group_size);
1440 for (i = 0; i < N_REG_CLASSES; i++)
1441 chain->group_mode[i] = VOIDmode;
1442 bzero ((char *) &insn_needs, sizeof insn_needs);
1444 /* Count each reload once in every class
1445 containing the reload's own class. */
1447 for (i = 0; i < n_reloads; i++)
1449 register enum reg_class *p;
1450 enum reg_class class = reload_reg_class[i];
1452 enum machine_mode mode;
1453 struct needs *this_needs;
1455 /* Don't count the dummy reloads, for which one of the
1456 regs mentioned in the insn can be used for reloading.
1457 Don't count optional reloads.
1458 Don't count reloads that got combined with others. */
1459 if (reload_reg_rtx[i] != 0
1460 || reload_optional[i] != 0
1461 || (reload_out[i] == 0 && reload_in[i] == 0
1462 && ! reload_secondary_p[i]))
1465 mode = reload_inmode[i];
1466 if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1467 mode = reload_outmode[i];
1468 size = CLASS_MAX_NREGS (class, mode);
1470 /* Decide which time-of-use to count this reload for. */
1471 switch (reload_when_needed[i])
1474 this_needs = &insn_needs.other;
1476 case RELOAD_FOR_INPUT:
1477 this_needs = &insn_needs.input;
1479 case RELOAD_FOR_OUTPUT:
1480 this_needs = &insn_needs.output;
1482 case RELOAD_FOR_INSN:
1483 this_needs = &insn_needs.insn;
1485 case RELOAD_FOR_OTHER_ADDRESS:
1486 this_needs = &insn_needs.other_addr;
1488 case RELOAD_FOR_INPUT_ADDRESS:
1489 this_needs = &insn_needs.in_addr[reload_opnum[i]];
1491 case RELOAD_FOR_INPADDR_ADDRESS:
1492 this_needs = &insn_needs.in_addr_addr[reload_opnum[i]];
1494 case RELOAD_FOR_OUTPUT_ADDRESS:
1495 this_needs = &insn_needs.out_addr[reload_opnum[i]];
1497 case RELOAD_FOR_OUTADDR_ADDRESS:
1498 this_needs = &insn_needs.out_addr_addr[reload_opnum[i]];
1500 case RELOAD_FOR_OPERAND_ADDRESS:
1501 this_needs = &insn_needs.op_addr;
1503 case RELOAD_FOR_OPADDR_ADDR:
1504 this_needs = &insn_needs.op_addr_reload;
1510 enum machine_mode other_mode, allocate_mode;
1512 /* Count number of groups needed separately from
1513 number of individual regs needed. */
1514 this_needs->groups[(int) class]++;
1515 p = reg_class_superclasses[(int) class];
1516 while (*p != LIM_REG_CLASSES)
1517 this_needs->groups[(int) *p++]++;
1519 /* Record size and mode of a group of this class. */
1520 /* If more than one size group is needed,
1521 make all groups the largest needed size. */
1522 if (chain->group_size[(int) class] < size)
1524 other_mode = chain->group_mode[(int) class];
1525 allocate_mode = mode;
1527 chain->group_size[(int) class] = size;
1528 chain->group_mode[(int) class] = mode;
1533 allocate_mode = chain->group_mode[(int) class];
1536 /* Crash if two dissimilar machine modes both need
1537 groups of consecutive regs of the same class. */
1539 if (other_mode != VOIDmode && other_mode != allocate_mode
1540 && ! modes_equiv_for_class_p (allocate_mode,
1542 fatal_insn ("Two dissimilar machine modes both need groups of consecutive regs of the same class",
1547 this_needs->regs[(unsigned char)reload_nongroup[i]][(int) class] += 1;
1548 p = reg_class_superclasses[(int) class];
1549 while (*p != LIM_REG_CLASSES)
1550 this_needs->regs[(unsigned char)reload_nongroup[i]][(int) *p++] += 1;
1556 /* All reloads have been counted for this insn;
1557 now merge the various times of use.
1558 This sets insn_needs, etc., to the maximum total number
1559 of registers needed at any point in this insn. */
1561 for (i = 0; i < N_REG_CLASSES; i++)
1563 int j, in_max, out_max;
1565 /* Compute normal and nongroup needs. */
1566 for (j = 0; j <= 1; j++)
1569 for (in_max = 0, out_max = 0, k = 0; k < reload_n_operands; k++)
1571 in_max = MAX (in_max,
1572 (insn_needs.in_addr[k].regs[j][i]
1573 + insn_needs.in_addr_addr[k].regs[j][i]));
1574 out_max = MAX (out_max, insn_needs.out_addr[k].regs[j][i]);
1575 out_max = MAX (out_max,
1576 insn_needs.out_addr_addr[k].regs[j][i]);
1579 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1580 and operand addresses but not things used to reload
1581 them. Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads
1582 don't conflict with things needed to reload inputs or
1585 in_max = MAX (MAX (insn_needs.op_addr.regs[j][i],
1586 insn_needs.op_addr_reload.regs[j][i]),
1589 out_max = MAX (out_max, insn_needs.insn.regs[j][i]);
1591 insn_needs.input.regs[j][i]
1592 = MAX (insn_needs.input.regs[j][i]
1593 + insn_needs.op_addr.regs[j][i]
1594 + insn_needs.insn.regs[j][i],
1595 in_max + insn_needs.input.regs[j][i]);
1597 insn_needs.output.regs[j][i] += out_max;
1598 insn_needs.other.regs[j][i]
1599 += MAX (MAX (insn_needs.input.regs[j][i],
1600 insn_needs.output.regs[j][i]),
1601 insn_needs.other_addr.regs[j][i]);
1605 /* Now compute group needs. */
1606 for (in_max = 0, out_max = 0, j = 0; j < reload_n_operands; j++)
1608 in_max = MAX (in_max, insn_needs.in_addr[j].groups[i]);
1609 in_max = MAX (in_max, insn_needs.in_addr_addr[j].groups[i]);
1610 out_max = MAX (out_max, insn_needs.out_addr[j].groups[i]);
1611 out_max = MAX (out_max, insn_needs.out_addr_addr[j].groups[i]);
1614 in_max = MAX (MAX (insn_needs.op_addr.groups[i],
1615 insn_needs.op_addr_reload.groups[i]),
1617 out_max = MAX (out_max, insn_needs.insn.groups[i]);
1619 insn_needs.input.groups[i]
1620 = MAX (insn_needs.input.groups[i]
1621 + insn_needs.op_addr.groups[i]
1622 + insn_needs.insn.groups[i],
1623 in_max + insn_needs.input.groups[i]);
1625 insn_needs.output.groups[i] += out_max;
1626 insn_needs.other.groups[i]
1627 += MAX (MAX (insn_needs.input.groups[i],
1628 insn_needs.output.groups[i]),
1629 insn_needs.other_addr.groups[i]);
1632 /* Record the needs for later. */
1633 chain->need = insn_needs.other;
1636 /* Find a group of exactly 2 registers.
1638 First try to fill out the group by spilling a single register which
1639 would allow completion of the group.
1641 Then try to create a new group from a pair of registers, neither of
1642 which are explicitly used.
1644 Then try to create a group from any pair of registers. */
1647 find_tworeg_group (chain, class, dumpfile)
1648 struct insn_chain *chain;
1653 /* First, look for a register that will complete a group. */
1654 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1658 j = potential_reload_regs[i];
1659 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1660 && ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1661 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1662 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1663 && HARD_REGNO_MODE_OK (other, chain->group_mode[class])
1664 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, other)
1665 /* We don't want one part of another group.
1666 We could get "two groups" that overlap! */
1667 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, other))
1668 || (j < FIRST_PSEUDO_REGISTER - 1
1669 && (other = j + 1, spill_reg_order[other] >= 0)
1670 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1671 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1672 && HARD_REGNO_MODE_OK (j, chain->group_mode[class])
1673 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, other)
1674 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, other))))
1676 register enum reg_class *p;
1678 /* We have found one that will complete a group,
1679 so count off one group as provided. */
1680 chain->need.groups[class]--;
1681 p = reg_class_superclasses[class];
1682 while (*p != LIM_REG_CLASSES)
1684 if (chain->group_size [(int) *p] <= chain->group_size [class])
1685 chain->need.groups[(int) *p]--;
1689 /* Indicate both these regs are part of a group. */
1690 SET_HARD_REG_BIT (chain->counted_for_groups, j);
1691 SET_HARD_REG_BIT (chain->counted_for_groups, other);
1695 /* We can't complete a group, so start one. */
1696 if (i == FIRST_PSEUDO_REGISTER)
1697 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1700 j = potential_reload_regs[i];
1701 /* Verify that J+1 is a potential reload reg. */
1702 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1703 if (potential_reload_regs[k] == j + 1)
1705 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1706 && k < FIRST_PSEUDO_REGISTER
1707 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1708 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1709 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1710 && HARD_REGNO_MODE_OK (j, chain->group_mode[class])
1711 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, j + 1)
1712 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1))
1716 /* I should be the index in potential_reload_regs
1717 of the new reload reg we have found. */
1719 new_spill_reg (chain, i, class, 0, dumpfile);
1722 /* Find a group of more than 2 registers.
1723 Look for a sufficient sequence of unspilled registers, and spill them all
1727 find_group (chain, class, dumpfile)
1728 struct insn_chain *chain;
1734 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1736 int j = potential_reload_regs[i];
1739 && j + chain->group_size[class] <= FIRST_PSEUDO_REGISTER
1740 && HARD_REGNO_MODE_OK (j, chain->group_mode[class]))
1743 /* Check each reg in the sequence. */
1744 for (k = 0; k < chain->group_size[class]; k++)
1745 if (! (spill_reg_order[j + k] < 0
1746 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1747 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1749 /* We got a full sequence, so spill them all. */
1750 if (k == chain->group_size[class])
1752 register enum reg_class *p;
1753 for (k = 0; k < chain->group_size[class]; k++)
1756 SET_HARD_REG_BIT (chain->counted_for_groups, j + k);
1757 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1758 if (potential_reload_regs[idx] == j + k)
1760 new_spill_reg (chain, idx, class, 0, dumpfile);
1763 /* We have found one that will complete a group,
1764 so count off one group as provided. */
1765 chain->need.groups[class]--;
1766 p = reg_class_superclasses[class];
1767 while (*p != LIM_REG_CLASSES)
1769 if (chain->group_size [(int) *p]
1770 <= chain->group_size [class])
1771 chain->need.groups[(int) *p]--;
1778 /* There are no groups left. */
1779 spill_failure (chain->insn);
1783 /* If pseudo REG conflicts with one of our reload registers, mark it as
1786 maybe_mark_pseudo_spilled (reg)
1790 int r = reg_renumber[reg];
1795 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1796 for (i = 0; i < n_spills; i++)
1797 if (r <= spill_regs[i] && r + nregs > spill_regs[i])
1799 SET_REGNO_REG_SET (spilled_pseudos, reg);
1804 /* Find more reload regs to satisfy the remaining need of an insn, which
1806 Do it by ascending class number, since otherwise a reg
1807 might be spilled for a big class and might fail to count
1808 for a smaller class even though it belongs to that class.
1810 Count spilled regs in `spills', and add entries to
1811 `spill_regs' and `spill_reg_order'.
1813 ??? Note there is a problem here.
1814 When there is a need for a group in a high-numbered class,
1815 and also need for non-group regs that come from a lower class,
1816 the non-group regs are chosen first. If there aren't many regs,
1817 they might leave no room for a group.
1819 This was happening on the 386. To fix it, we added the code
1820 that calls possible_group_p, so that the lower class won't
1821 break up the last possible group.
1823 Really fixing the problem would require changes above
1824 in counting the regs already spilled, and in choose_reload_regs.
1825 It might be hard to avoid introducing bugs there. */
1828 find_reload_regs (chain, dumpfile)
1829 struct insn_chain *chain;
1833 short *group_needs = chain->need.groups;
1834 short *simple_needs = chain->need.regs[0];
1835 short *nongroup_needs = chain->need.regs[1];
1838 fprintf (dumpfile, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1840 /* Compute the order of preference for hard registers to spill.
1841 Store them by decreasing preference in potential_reload_regs. */
1843 order_regs_for_reload (chain);
1845 /* So far, no hard regs have been spilled. */
1847 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1848 spill_reg_order[i] = -1;
1850 CLEAR_HARD_REG_SET (chain->used_spill_regs);
1851 CLEAR_HARD_REG_SET (chain->counted_for_groups);
1852 CLEAR_HARD_REG_SET (chain->counted_for_nongroups);
1854 for (class = 0; class < N_REG_CLASSES; class++)
1856 /* First get the groups of registers.
1857 If we got single registers first, we might fragment
1859 while (group_needs[class] > 0)
1861 /* If any single spilled regs happen to form groups,
1862 count them now. Maybe we don't really need
1863 to spill another group. */
1864 count_possible_groups (chain, class);
1866 if (group_needs[class] <= 0)
1869 /* Groups of size 2, the only groups used on most machines,
1870 are treated specially. */
1871 if (chain->group_size[class] == 2)
1872 find_tworeg_group (chain, class, dumpfile);
1874 find_group (chain, class, dumpfile);
1879 /* Now similarly satisfy all need for single registers. */
1881 while (simple_needs[class] > 0 || nongroup_needs[class] > 0)
1883 /* If we spilled enough regs, but they weren't counted
1884 against the non-group need, see if we can count them now.
1885 If so, we can avoid some actual spilling. */
1886 if (simple_needs[class] <= 0 && nongroup_needs[class] > 0)
1887 for (i = 0; i < n_spills; i++)
1889 int regno = spill_regs[i];
1890 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1891 && !TEST_HARD_REG_BIT (chain->counted_for_groups, regno)
1892 && !TEST_HARD_REG_BIT (chain->counted_for_nongroups, regno)
1893 && nongroup_needs[class] > 0)
1895 register enum reg_class *p;
1897 SET_HARD_REG_BIT (chain->counted_for_nongroups, regno);
1898 nongroup_needs[class]--;
1899 p = reg_class_superclasses[class];
1900 while (*p != LIM_REG_CLASSES)
1901 nongroup_needs[(int) *p++]--;
1905 if (simple_needs[class] <= 0 && nongroup_needs[class] <= 0)
1908 /* Consider the potential reload regs that aren't
1909 yet in use as reload regs, in order of preference.
1910 Find the most preferred one that's in this class. */
1912 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1914 int regno = potential_reload_regs[i];
1916 && TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1917 /* If this reg will not be available for groups,
1918 pick one that does not foreclose possible groups.
1919 This is a kludge, and not very general,
1920 but it should be sufficient to make the 386 work,
1921 and the problem should not occur on machines with
1923 && (nongroup_needs[class] == 0
1924 || possible_group_p (chain, regno)))
1928 /* If we couldn't get a register, try to get one even if we
1929 might foreclose possible groups. This may cause problems
1930 later, but that's better than aborting now, since it is
1931 possible that we will, in fact, be able to form the needed
1932 group even with this allocation. */
1934 if (i >= FIRST_PSEUDO_REGISTER
1935 && asm_noperands (chain->insn) < 0)
1936 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1937 if (potential_reload_regs[i] >= 0
1938 && TEST_HARD_REG_BIT (reg_class_contents[class],
1939 potential_reload_regs[i]))
1942 /* I should be the index in potential_reload_regs
1943 of the new reload reg we have found. */
1945 new_spill_reg (chain, i, class, 1, dumpfile);
1951 /* We know which hard regs to use, now mark the pseudos that live in them
1952 as needing to be kicked out. */
1953 EXECUTE_IF_SET_IN_REG_SET
1954 (chain->live_before, FIRST_PSEUDO_REGISTER, i,
1956 maybe_mark_pseudo_spilled (i);
1958 EXECUTE_IF_SET_IN_REG_SET
1959 (chain->live_after, FIRST_PSEUDO_REGISTER, i,
1961 maybe_mark_pseudo_spilled (i);
1964 IOR_HARD_REG_SET (used_spill_regs, chain->used_spill_regs);
1968 dump_needs (chain, dumpfile)
1969 struct insn_chain *chain;
1972 static char *reg_class_names[] = REG_CLASS_NAMES;
1974 struct needs *n = &chain->need;
1976 for (i = 0; i < N_REG_CLASSES; i++)
1978 if (n->regs[i][0] > 0)
1980 ";; Need %d reg%s of class %s.\n",
1981 n->regs[i][0], n->regs[i][0] == 1 ? "" : "s",
1982 reg_class_names[i]);
1983 if (n->regs[i][1] > 0)
1985 ";; Need %d nongroup reg%s of class %s.\n",
1986 n->regs[i][1], n->regs[i][1] == 1 ? "" : "s",
1987 reg_class_names[i]);
1988 if (n->groups[i] > 0)
1990 ";; Need %d group%s (%smode) of class %s.\n",
1991 n->groups[i], n->groups[i] == 1 ? "" : "s",
1992 mode_name[(int) chain->group_mode[i]],
1993 reg_class_names[i]);
1997 /* Delete all insns that were inserted by emit_caller_save_insns during
2000 delete_caller_save_insns ()
2002 struct insn_chain *c = reload_insn_chain;
2006 while (c != 0 && c->is_caller_save_insn)
2008 struct insn_chain *next = c->next;
2011 if (insn == basic_block_head[c->block])
2012 basic_block_head[c->block] = NEXT_INSN (insn);
2013 if (insn == basic_block_end[c->block])
2014 basic_block_end[c->block] = PREV_INSN (insn);
2015 if (c == reload_insn_chain)
2016 reload_insn_chain = next;
2018 if (NEXT_INSN (insn) != 0)
2019 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2020 if (PREV_INSN (insn) != 0)
2021 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2024 next->prev = c->prev;
2026 c->prev->next = next;
2027 c->next = unused_insn_chains;
2028 unused_insn_chains = c;
2036 /* Nonzero if, after spilling reg REGNO for non-groups,
2037 it will still be possible to find a group if we still need one. */
2040 possible_group_p (chain, regno)
2041 struct insn_chain *chain;
2045 int class = (int) NO_REGS;
2047 for (i = 0; i < (int) N_REG_CLASSES; i++)
2048 if (chain->need.groups[i] > 0)
2054 if (class == (int) NO_REGS)
2057 /* Consider each pair of consecutive registers. */
2058 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
2060 /* Ignore pairs that include reg REGNO. */
2061 if (i == regno || i + 1 == regno)
2064 /* Ignore pairs that are outside the class that needs the group.
2065 ??? Here we fail to handle the case where two different classes
2066 independently need groups. But this never happens with our
2067 current machine descriptions. */
2068 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
2069 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
2072 /* A pair of consecutive regs we can still spill does the trick. */
2073 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
2074 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2075 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
2078 /* A pair of one already spilled and one we can spill does it
2079 provided the one already spilled is not otherwise reserved. */
2080 if (spill_reg_order[i] < 0
2081 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2082 && spill_reg_order[i + 1] >= 0
2083 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, i + 1)
2084 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, i + 1))
2086 if (spill_reg_order[i + 1] < 0
2087 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
2088 && spill_reg_order[i] >= 0
2089 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, i)
2090 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, i))
2097 /* Count any groups of CLASS that can be formed from the registers recently
2101 count_possible_groups (chain, class)
2102 struct insn_chain *chain;
2108 /* Now find all consecutive groups of spilled registers
2109 and mark each group off against the need for such groups.
2110 But don't count them against ordinary need, yet. */
2112 if (chain->group_size[class] == 0)
2115 CLEAR_HARD_REG_SET (new);
2117 /* Make a mask of all the regs that are spill regs in class I. */
2118 for (i = 0; i < n_spills; i++)
2120 int regno = spill_regs[i];
2122 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
2123 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, regno)
2124 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, regno))
2125 SET_HARD_REG_BIT (new, regno);
2128 /* Find each consecutive group of them. */
2129 for (i = 0; i < FIRST_PSEUDO_REGISTER && chain->need.groups[class] > 0; i++)
2130 if (TEST_HARD_REG_BIT (new, i)
2131 && i + chain->group_size[class] <= FIRST_PSEUDO_REGISTER
2132 && HARD_REGNO_MODE_OK (i, chain->group_mode[class]))
2134 for (j = 1; j < chain->group_size[class]; j++)
2135 if (! TEST_HARD_REG_BIT (new, i + j))
2138 if (j == chain->group_size[class])
2140 /* We found a group. Mark it off against this class's need for
2141 groups, and against each superclass too. */
2142 register enum reg_class *p;
2144 chain->need.groups[class]--;
2145 p = reg_class_superclasses[class];
2146 while (*p != LIM_REG_CLASSES)
2148 if (chain->group_size [(int) *p] <= chain->group_size [class])
2149 chain->need.groups[(int) *p]--;
2153 /* Don't count these registers again. */
2154 for (j = 0; j < chain->group_size[class]; j++)
2155 SET_HARD_REG_BIT (chain->counted_for_groups, i + j);
2158 /* Skip to the last reg in this group. When i is incremented above,
2159 it will then point to the first reg of the next possible group. */
2164 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2165 another mode that needs to be reloaded for the same register class CLASS.
2166 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2167 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2169 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2170 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2171 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2172 causes unnecessary failures on machines requiring alignment of register
2173 groups when the two modes are different sizes, because the larger mode has
2174 more strict alignment rules than the smaller mode. */
2177 modes_equiv_for_class_p (allocate_mode, other_mode, class)
2178 enum machine_mode allocate_mode, other_mode;
2179 enum reg_class class;
2182 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2184 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
2185 && HARD_REGNO_MODE_OK (regno, allocate_mode)
2186 && ! HARD_REGNO_MODE_OK (regno, other_mode))
2192 /* Handle the failure to find a register to spill.
2193 INSN should be one of the insns which needed this particular spill reg. */
2196 spill_failure (insn)
2199 if (asm_noperands (PATTERN (insn)) >= 0)
2200 error_for_asm (insn, "`asm' needs too many reloads");
2202 fatal_insn ("Unable to find a register to spill.", insn);
2205 /* Add a new register to the tables of available spill-registers.
2206 CHAIN is the insn for which the register will be used; we decrease the
2208 I is the index of this register in potential_reload_regs.
2209 CLASS is the regclass whose need is being satisfied.
2210 NONGROUP is 0 if this register is part of a group.
2211 DUMPFILE is the same as the one that `reload' got. */
2214 new_spill_reg (chain, i, class, nongroup, dumpfile)
2215 struct insn_chain *chain;
2221 register enum reg_class *p;
2222 int regno = potential_reload_regs[i];
2224 if (i >= FIRST_PSEUDO_REGISTER)
2226 spill_failure (chain->insn);
2231 if (TEST_HARD_REG_BIT (bad_spill_regs, regno))
2233 static char *reg_class_names[] = REG_CLASS_NAMES;
2235 if (asm_noperands (PATTERN (chain->insn)) < 0)
2237 /* The error message is still correct - we know only that it wasn't
2238 an asm statement that caused the problem, but one of the global
2239 registers declared by the users might have screwed us. */
2240 error ("fixed or forbidden register %d (%s) was spilled for class %s.",
2241 regno, reg_names[regno], reg_class_names[class]);
2242 error ("This may be due to a compiler bug or to impossible asm");
2243 error ("statements or clauses.");
2244 fatal_insn ("This is the instruction:", chain->insn);
2246 error_for_asm (chain->insn, "Invalid `asm' statement:");
2247 error_for_asm (chain->insn,
2248 "fixed or forbidden register %d (%s) was spilled for class %s.",
2249 regno, reg_names[regno], reg_class_names[class]);
2254 /* Make reg REGNO an additional reload reg. */
2256 potential_reload_regs[i] = -1;
2257 spill_regs[n_spills] = regno;
2258 spill_reg_order[regno] = n_spills;
2260 fprintf (dumpfile, "Spilling reg %d.\n", regno);
2261 SET_HARD_REG_BIT (chain->used_spill_regs, regno);
2263 /* Clear off the needs we just satisfied. */
2265 chain->need.regs[0][class]--;
2266 p = reg_class_superclasses[class];
2267 while (*p != LIM_REG_CLASSES)
2268 chain->need.regs[0][(int) *p++]--;
2270 if (nongroup && chain->need.regs[1][class] > 0)
2272 SET_HARD_REG_BIT (chain->counted_for_nongroups, regno);
2273 chain->need.regs[1][class]--;
2274 p = reg_class_superclasses[class];
2275 while (*p != LIM_REG_CLASSES)
2276 chain->need.regs[1][(int) *p++]--;
2282 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2283 data that is dead in INSN. */
2286 delete_dead_insn (insn)
2289 rtx prev = prev_real_insn (insn);
2292 /* If the previous insn sets a register that dies in our insn, delete it
2294 if (prev && GET_CODE (PATTERN (prev)) == SET
2295 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2296 && reg_mentioned_p (prev_dest, PATTERN (insn))
2297 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2298 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2299 delete_dead_insn (prev);
2301 PUT_CODE (insn, NOTE);
2302 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2303 NOTE_SOURCE_FILE (insn) = 0;
2306 /* Modify the home of pseudo-reg I.
2307 The new home is present in reg_renumber[I].
2309 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2310 or it may be -1, meaning there is none or it is not relevant.
2311 This is used so that all pseudos spilled from a given hard reg
2312 can share one stack slot. */
2315 alter_reg (i, from_reg)
2319 /* When outputting an inline function, this can happen
2320 for a reg that isn't actually used. */
2321 if (regno_reg_rtx[i] == 0)
2324 /* If the reg got changed to a MEM at rtl-generation time,
2326 if (GET_CODE (regno_reg_rtx[i]) != REG)
2329 /* Modify the reg-rtx to contain the new hard reg
2330 number or else to contain its pseudo reg number. */
2331 REGNO (regno_reg_rtx[i])
2332 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2334 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2335 allocate a stack slot for it. */
2337 if (reg_renumber[i] < 0
2338 && REG_N_REFS (i) > 0
2339 && reg_equiv_constant[i] == 0
2340 && reg_equiv_memory_loc[i] == 0)
2343 int inherent_size = PSEUDO_REGNO_BYTES (i);
2344 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2347 /* Each pseudo reg has an inherent size which comes from its own mode,
2348 and a total size which provides room for paradoxical subregs
2349 which refer to the pseudo reg in wider modes.
2351 We can use a slot already allocated if it provides both
2352 enough inherent space and enough total space.
2353 Otherwise, we allocate a new slot, making sure that it has no less
2354 inherent space, and no less total space, then the previous slot. */
2357 /* No known place to spill from => no slot to reuse. */
2358 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
2359 inherent_size == total_size ? 0 : -1);
2360 if (BYTES_BIG_ENDIAN)
2361 /* Cancel the big-endian correction done in assign_stack_local.
2362 Get the address of the beginning of the slot.
2363 This is so we can do a big-endian correction unconditionally
2365 adjust = inherent_size - total_size;
2367 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2369 /* Reuse a stack slot if possible. */
2370 else if (spill_stack_slot[from_reg] != 0
2371 && spill_stack_slot_width[from_reg] >= total_size
2372 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2374 x = spill_stack_slot[from_reg];
2375 /* Allocate a bigger slot. */
2378 /* Compute maximum size needed, both for inherent size
2379 and for total size. */
2380 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2382 if (spill_stack_slot[from_reg])
2384 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2386 mode = GET_MODE (spill_stack_slot[from_reg]);
2387 if (spill_stack_slot_width[from_reg] > total_size)
2388 total_size = spill_stack_slot_width[from_reg];
2390 /* Make a slot with that size. */
2391 x = assign_stack_local (mode, total_size,
2392 inherent_size == total_size ? 0 : -1);
2394 if (BYTES_BIG_ENDIAN)
2396 /* Cancel the big-endian correction done in assign_stack_local.
2397 Get the address of the beginning of the slot.
2398 This is so we can do a big-endian correction unconditionally
2400 adjust = GET_MODE_SIZE (mode) - total_size;
2402 stack_slot = gen_rtx_MEM (mode_for_size (total_size
2405 plus_constant (XEXP (x, 0), adjust));
2407 spill_stack_slot[from_reg] = stack_slot;
2408 spill_stack_slot_width[from_reg] = total_size;
2411 /* On a big endian machine, the "address" of the slot
2412 is the address of the low part that fits its inherent mode. */
2413 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2414 adjust += (total_size - inherent_size);
2416 /* If we have any adjustment to make, or if the stack slot is the
2417 wrong mode, make a new stack slot. */
2418 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2420 x = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
2421 plus_constant (XEXP (x, 0), adjust));
2423 /* If this was shared among registers, must ensure we never
2424 set it readonly since that can cause scheduling
2425 problems. Note we would only have in this adjustment
2426 case in any event, since the code above doesn't set it. */
2429 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2432 /* Save the stack slot for later. */
2433 reg_equiv_memory_loc[i] = x;
2437 /* Mark the slots in regs_ever_live for the hard regs
2438 used by pseudo-reg number REGNO. */
2441 mark_home_live (regno)
2444 register int i, lim;
2445 i = reg_renumber[regno];
2448 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2450 regs_ever_live[i++] = 1;
2453 /* This function handles the tracking of elimination offsets around branches.
2455 X is a piece of RTL being scanned.
2457 INSN is the insn that it came from, if any.
2459 INITIAL_P is non-zero if we are to set the offset to be the initial
2460 offset and zero if we are setting the offset of the label to be the
2464 set_label_offsets (x, insn, initial_p)
2469 enum rtx_code code = GET_CODE (x);
2472 struct elim_table *p;
2477 if (LABEL_REF_NONLOCAL_P (x))
2482 /* ... fall through ... */
2485 /* If we know nothing about this label, set the desired offsets. Note
2486 that this sets the offset at a label to be the offset before a label
2487 if we don't know anything about the label. This is not correct for
2488 the label after a BARRIER, but is the best guess we can make. If
2489 we guessed wrong, we will suppress an elimination that might have
2490 been possible had we been able to guess correctly. */
2492 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2494 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2495 offsets_at[CODE_LABEL_NUMBER (x)][i]
2496 = (initial_p ? reg_eliminate[i].initial_offset
2497 : reg_eliminate[i].offset);
2498 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2501 /* Otherwise, if this is the definition of a label and it is
2502 preceded by a BARRIER, set our offsets to the known offset of
2506 && (tem = prev_nonnote_insn (insn)) != 0
2507 && GET_CODE (tem) == BARRIER)
2508 set_offsets_for_label (insn);
2510 /* If neither of the above cases is true, compare each offset
2511 with those previously recorded and suppress any eliminations
2512 where the offsets disagree. */
2514 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2515 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2516 != (initial_p ? reg_eliminate[i].initial_offset
2517 : reg_eliminate[i].offset))
2518 reg_eliminate[i].can_eliminate = 0;
2523 set_label_offsets (PATTERN (insn), insn, initial_p);
2525 /* ... fall through ... */
2529 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2530 and hence must have all eliminations at their initial offsets. */
2531 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2532 if (REG_NOTE_KIND (tem) == REG_LABEL)
2533 set_label_offsets (XEXP (tem, 0), insn, 1);
2538 /* Each of the labels in the address vector must be at their initial
2539 offsets. We want the first field for ADDR_VEC and the second
2540 field for ADDR_DIFF_VEC. */
2542 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2543 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2548 /* We only care about setting PC. If the source is not RETURN,
2549 IF_THEN_ELSE, or a label, disable any eliminations not at
2550 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2551 isn't one of those possibilities. For branches to a label,
2552 call ourselves recursively.
2554 Note that this can disable elimination unnecessarily when we have
2555 a non-local goto since it will look like a non-constant jump to
2556 someplace in the current function. This isn't a significant
2557 problem since such jumps will normally be when all elimination
2558 pairs are back to their initial offsets. */
2560 if (SET_DEST (x) != pc_rtx)
2563 switch (GET_CODE (SET_SRC (x)))
2570 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2574 tem = XEXP (SET_SRC (x), 1);
2575 if (GET_CODE (tem) == LABEL_REF)
2576 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2577 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2580 tem = XEXP (SET_SRC (x), 2);
2581 if (GET_CODE (tem) == LABEL_REF)
2582 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2583 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2591 /* If we reach here, all eliminations must be at their initial
2592 offset because we are doing a jump to a variable address. */
2593 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2594 if (p->offset != p->initial_offset)
2595 p->can_eliminate = 0;
2603 /* Used for communication between the next two function to properly share
2604 the vector for an ASM_OPERANDS. */
2606 static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2608 /* Scan X and replace any eliminable registers (such as fp) with a
2609 replacement (such as sp), plus an offset.
2611 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2612 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2613 MEM, we are allowed to replace a sum of a register and the constant zero
2614 with the register, which we cannot do outside a MEM. In addition, we need
2615 to record the fact that a register is referenced outside a MEM.
2617 If INSN is an insn, it is the insn containing X. If we replace a REG
2618 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2619 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2620 the REG is being modified.
2622 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2623 That's used when we eliminate in expressions stored in notes.
2624 This means, do not set ref_outside_mem even if the reference
2627 If we see a modification to a register we know about, take the
2628 appropriate action (see case SET, below).
2630 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2631 replacements done assuming all offsets are at their initial values. If
2632 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2633 encounter, return the actual location so that find_reloads will do
2634 the proper thing. */
2637 eliminate_regs (x, mem_mode, insn)
2639 enum machine_mode mem_mode;
2642 enum rtx_code code = GET_CODE (x);
2643 struct elim_table *ep;
2666 /* This is only for the benefit of the debugging backends, which call
2667 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2668 removed after CSE. */
2669 new = eliminate_regs (XEXP (x, 0), 0, insn);
2670 if (GET_CODE (new) == MEM)
2671 return XEXP (new, 0);
2677 /* First handle the case where we encounter a bare register that
2678 is eliminable. Replace it with a PLUS. */
2679 if (regno < FIRST_PSEUDO_REGISTER)
2681 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2683 if (ep->from_rtx == x && ep->can_eliminate)
2686 /* Refs inside notes don't count for this purpose. */
2687 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2688 || GET_CODE (insn) == INSN_LIST)))
2689 ep->ref_outside_mem = 1;
2690 return plus_constant (ep->to_rtx, ep->previous_offset);
2697 /* If this is the sum of an eliminable register and a constant, rework
2699 if (GET_CODE (XEXP (x, 0)) == REG
2700 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2701 && CONSTANT_P (XEXP (x, 1)))
2703 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2705 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2708 /* Refs inside notes don't count for this purpose. */
2709 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2710 || GET_CODE (insn) == INSN_LIST)))
2711 ep->ref_outside_mem = 1;
2713 /* The only time we want to replace a PLUS with a REG (this
2714 occurs when the constant operand of the PLUS is the negative
2715 of the offset) is when we are inside a MEM. We won't want
2716 to do so at other times because that would change the
2717 structure of the insn in a way that reload can't handle.
2718 We special-case the commonest situation in
2719 eliminate_regs_in_insn, so just replace a PLUS with a
2720 PLUS here, unless inside a MEM. */
2721 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2722 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2725 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2726 plus_constant (XEXP (x, 1),
2727 ep->previous_offset));
2730 /* If the register is not eliminable, we are done since the other
2731 operand is a constant. */
2735 /* If this is part of an address, we want to bring any constant to the
2736 outermost PLUS. We will do this by doing register replacement in
2737 our operands and seeing if a constant shows up in one of them.
2739 We assume here this is part of an address (or a "load address" insn)
2740 since an eliminable register is not likely to appear in any other
2743 If we have (plus (eliminable) (reg)), we want to produce
2744 (plus (plus (replacement) (reg) (const))). If this was part of a
2745 normal add insn, (plus (replacement) (reg)) will be pushed as a
2746 reload. This is the desired action. */
2749 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2750 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2752 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2754 /* If one side is a PLUS and the other side is a pseudo that
2755 didn't get a hard register but has a reg_equiv_constant,
2756 we must replace the constant here since it may no longer
2757 be in the position of any operand. */
2758 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2759 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2760 && reg_renumber[REGNO (new1)] < 0
2761 && reg_equiv_constant != 0
2762 && reg_equiv_constant[REGNO (new1)] != 0)
2763 new1 = reg_equiv_constant[REGNO (new1)];
2764 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2765 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2766 && reg_renumber[REGNO (new0)] < 0
2767 && reg_equiv_constant[REGNO (new0)] != 0)
2768 new0 = reg_equiv_constant[REGNO (new0)];
2770 new = form_sum (new0, new1);
2772 /* As above, if we are not inside a MEM we do not want to
2773 turn a PLUS into something else. We might try to do so here
2774 for an addition of 0 if we aren't optimizing. */
2775 if (! mem_mode && GET_CODE (new) != PLUS)
2776 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2784 /* If this is the product of an eliminable register and a
2785 constant, apply the distribute law and move the constant out
2786 so that we have (plus (mult ..) ..). This is needed in order
2787 to keep load-address insns valid. This case is pathological.
2788 We ignore the possibility of overflow here. */
2789 if (GET_CODE (XEXP (x, 0)) == REG
2790 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2791 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2792 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2794 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2797 /* Refs inside notes don't count for this purpose. */
2798 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2799 || GET_CODE (insn) == INSN_LIST)))
2800 ep->ref_outside_mem = 1;
2803 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2804 ep->previous_offset * INTVAL (XEXP (x, 1)));
2807 /* ... fall through ... */
2812 case DIV: case UDIV:
2813 case MOD: case UMOD:
2814 case AND: case IOR: case XOR:
2815 case ROTATERT: case ROTATE:
2816 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2818 case GE: case GT: case GEU: case GTU:
2819 case LE: case LT: case LEU: case LTU:
2821 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2823 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2825 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2826 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2831 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2834 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2835 if (new != XEXP (x, 0))
2836 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2839 /* ... fall through ... */
2842 /* Now do eliminations in the rest of the chain. If this was
2843 an EXPR_LIST, this might result in allocating more memory than is
2844 strictly needed, but it simplifies the code. */
2847 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2848 if (new != XEXP (x, 1))
2849 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2857 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2858 if (ep->to_rtx == XEXP (x, 0))
2860 int size = GET_MODE_SIZE (mem_mode);
2862 /* If more bytes than MEM_MODE are pushed, account for them. */
2863 #ifdef PUSH_ROUNDING
2864 if (ep->to_rtx == stack_pointer_rtx)
2865 size = PUSH_ROUNDING (size);
2867 if (code == PRE_DEC || code == POST_DEC)
2873 /* Fall through to generic unary operation case. */
2874 case STRICT_LOW_PART:
2876 case SIGN_EXTEND: case ZERO_EXTEND:
2877 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2878 case FLOAT: case FIX:
2879 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2883 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2884 if (new != XEXP (x, 0))
2885 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2889 /* Similar to above processing, but preserve SUBREG_WORD.
2890 Convert (subreg (mem)) to (mem) if not paradoxical.
2891 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2892 pseudo didn't get a hard reg, we must replace this with the
2893 eliminated version of the memory location because push_reloads
2894 may do the replacement in certain circumstances. */
2895 if (GET_CODE (SUBREG_REG (x)) == REG
2896 && (GET_MODE_SIZE (GET_MODE (x))
2897 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2898 && reg_equiv_memory_loc != 0
2899 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2902 new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
2905 /* If we didn't change anything, we must retain the pseudo. */
2906 if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
2907 new = SUBREG_REG (x);
2910 /* In this case, we must show that the pseudo is used in this
2911 insn so that delete_output_reload will do the right thing. */
2912 if (insn != 0 && GET_CODE (insn) != EXPR_LIST
2913 && GET_CODE (insn) != INSN_LIST)
2914 REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode,
2917 = gen_rtx_EXPR_LIST (REG_EQUAL, new, NULL_RTX);
2919 /* Ensure NEW isn't shared in case we have to reload it. */
2920 new = copy_rtx (new);
2923 new = SUBREG_REG (x);
2927 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2929 if (new != XEXP (x, 0))
2931 int x_size = GET_MODE_SIZE (GET_MODE (x));
2932 int new_size = GET_MODE_SIZE (GET_MODE (new));
2934 if (GET_CODE (new) == MEM
2935 && ((x_size < new_size
2936 #ifdef WORD_REGISTER_OPERATIONS
2937 /* On these machines, combine can create rtl of the form
2938 (set (subreg:m1 (reg:m2 R) 0) ...)
2939 where m1 < m2, and expects something interesting to
2940 happen to the entire word. Moreover, it will use the
2941 (reg:m2 R) later, expecting all bits to be preserved.
2942 So if the number of words is the same, preserve the
2943 subreg so that push_reloads can see it. */
2944 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
2947 || (x_size == new_size))
2950 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2951 enum machine_mode mode = GET_MODE (x);
2953 if (BYTES_BIG_ENDIAN)
2954 offset += (MIN (UNITS_PER_WORD,
2955 GET_MODE_SIZE (GET_MODE (new)))
2956 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2958 PUT_MODE (new, mode);
2959 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2963 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
2969 /* If using a register that is the source of an eliminate we still
2970 think can be performed, note it cannot be performed since we don't
2971 know how this register is used. */
2972 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2973 if (ep->from_rtx == XEXP (x, 0))
2974 ep->can_eliminate = 0;
2976 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2977 if (new != XEXP (x, 0))
2978 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2982 /* If clobbering a register that is the replacement register for an
2983 elimination we still think can be performed, note that it cannot
2984 be performed. Otherwise, we need not be concerned about it. */
2985 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2986 if (ep->to_rtx == XEXP (x, 0))
2987 ep->can_eliminate = 0;
2989 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2990 if (new != XEXP (x, 0))
2991 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2997 /* Properly handle sharing input and constraint vectors. */
2998 if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
3000 /* When we come to a new vector not seen before,
3001 scan all its elements; keep the old vector if none
3002 of them changes; otherwise, make a copy. */
3003 old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
3004 temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
3005 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3006 temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
3009 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3010 if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
3013 if (i == ASM_OPERANDS_INPUT_LENGTH (x))
3014 new_asm_operands_vec = old_asm_operands_vec;
3016 new_asm_operands_vec
3017 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
3020 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
3021 if (new_asm_operands_vec == old_asm_operands_vec)
3024 new = gen_rtx_ASM_OPERANDS (VOIDmode, ASM_OPERANDS_TEMPLATE (x),
3025 ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
3026 ASM_OPERANDS_OUTPUT_IDX (x),
3027 new_asm_operands_vec,
3028 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
3029 ASM_OPERANDS_SOURCE_FILE (x),
3030 ASM_OPERANDS_SOURCE_LINE (x));
3031 new->volatil = x->volatil;
3036 /* Check for setting a register that we know about. */
3037 if (GET_CODE (SET_DEST (x)) == REG)
3039 /* See if this is setting the replacement register for an
3042 If DEST is the hard frame pointer, we do nothing because we
3043 assume that all assignments to the frame pointer are for
3044 non-local gotos and are being done at a time when they are valid
3045 and do not disturb anything else. Some machines want to
3046 eliminate a fake argument pointer (or even a fake frame pointer)
3047 with either the real frame or the stack pointer. Assignments to
3048 the hard frame pointer must not prevent this elimination. */
3050 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3052 if (ep->to_rtx == SET_DEST (x)
3053 && SET_DEST (x) != hard_frame_pointer_rtx)
3055 /* If it is being incremented, adjust the offset. Otherwise,
3056 this elimination can't be done. */
3057 rtx src = SET_SRC (x);
3059 if (GET_CODE (src) == PLUS
3060 && XEXP (src, 0) == SET_DEST (x)
3061 && GET_CODE (XEXP (src, 1)) == CONST_INT)
3062 ep->offset -= INTVAL (XEXP (src, 1));
3064 ep->can_eliminate = 0;
3067 /* Now check to see we are assigning to a register that can be
3068 eliminated. If so, it must be as part of a PARALLEL, since we
3069 will not have been called if this is a single SET. So indicate
3070 that we can no longer eliminate this reg. */
3071 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3073 if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
3074 ep->can_eliminate = 0;
3077 /* Now avoid the loop below in this common case. */
3079 rtx new0 = eliminate_regs (SET_DEST (x), 0, insn);
3080 rtx new1 = eliminate_regs (SET_SRC (x), 0, insn);
3082 /* If SET_DEST changed from a REG to a MEM and INSN is an insn,
3083 write a CLOBBER insn. */
3084 if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
3085 && insn != 0 && GET_CODE (insn) != EXPR_LIST
3086 && GET_CODE (insn) != INSN_LIST)
3087 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, SET_DEST (x)), insn);
3089 if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
3090 return gen_rtx_SET (VOIDmode, new0, new1);
3096 /* This is only for the benefit of the debugging backends, which call
3097 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
3098 removed after CSE. */
3099 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
3100 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
3102 /* Our only special processing is to pass the mode of the MEM to our
3103 recursive call and copy the flags. While we are here, handle this
3104 case more efficiently. */
3105 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
3106 if (new != XEXP (x, 0))
3108 new = gen_rtx_MEM (GET_MODE (x), new);
3109 new->volatil = x->volatil;
3110 new->unchanging = x->unchanging;
3111 new->in_struct = x->in_struct;
3121 /* Process each of our operands recursively. If any have changed, make a
3123 fmt = GET_RTX_FORMAT (code);
3124 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3128 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
3129 if (new != XEXP (x, i) && ! copied)
3131 rtx new_x = rtx_alloc (code);
3132 bcopy ((char *) x, (char *) new_x,
3133 (sizeof (*new_x) - sizeof (new_x->fld)
3134 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
3140 else if (*fmt == 'E')
3143 for (j = 0; j < XVECLEN (x, i); j++)
3145 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
3146 if (new != XVECEXP (x, i, j) && ! copied_vec)
3148 rtvec new_v = gen_rtvec_vv (XVECLEN (x, i),
3152 rtx new_x = rtx_alloc (code);
3153 bcopy ((char *) x, (char *) new_x,
3154 (sizeof (*new_x) - sizeof (new_x->fld)
3155 + (sizeof (new_x->fld[0])
3156 * GET_RTX_LENGTH (code))));
3160 XVEC (x, i) = new_v;
3163 XVECEXP (x, i, j) = new;
3171 /* Scan INSN and eliminate all eliminable registers in it.
3173 If REPLACE is nonzero, do the replacement destructively. Also
3174 delete the insn as dead it if it is setting an eliminable register.
3176 If REPLACE is zero, do all our allocations in reload_obstack.
3178 If no eliminations were done and this insn doesn't require any elimination
3179 processing (these are not identical conditions: it might be updating sp,
3180 but not referencing fp; this needs to be seen during reload_as_needed so
3181 that the offset between fp and sp can be taken into consideration), zero
3182 is returned. Otherwise, 1 is returned. */
3185 eliminate_regs_in_insn (insn, replace)
3189 rtx old_body = PATTERN (insn);
3190 rtx old_set = single_set (insn);
3193 struct elim_table *ep;
3196 push_obstacks (&reload_obstack, &reload_obstack);
3198 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
3199 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3201 /* Check for setting an eliminable register. */
3202 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3203 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3205 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3206 /* If this is setting the frame pointer register to the
3207 hardware frame pointer register and this is an elimination
3208 that will be done (tested above), this insn is really
3209 adjusting the frame pointer downward to compensate for
3210 the adjustment done before a nonlocal goto. */
3211 if (ep->from == FRAME_POINTER_REGNUM
3212 && ep->to == HARD_FRAME_POINTER_REGNUM)
3214 rtx src = SET_SRC (old_set);
3216 rtx prev_insn, prev_set;
3218 if (src == ep->to_rtx)
3220 else if (GET_CODE (src) == PLUS
3221 && GET_CODE (XEXP (src, 0)) == CONST_INT
3222 && XEXP (src, 1) == ep->to_rtx)
3223 offset = INTVAL (XEXP (src, 0)), ok = 1;
3224 else if (GET_CODE (src) == PLUS
3225 && GET_CODE (XEXP (src, 1)) == CONST_INT
3226 && XEXP (src, 0) == ep->to_rtx)
3227 offset = INTVAL (XEXP (src, 1)), ok = 1;
3228 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
3229 && (prev_set = single_set (prev_insn)) != 0
3230 && rtx_equal_p (SET_DEST (prev_set), src))
3232 src = SET_SRC (prev_set);
3233 if (src == ep->to_rtx)
3235 else if (GET_CODE (src) == PLUS
3236 && GET_CODE (XEXP (src, 0)) == CONST_INT
3237 && XEXP (src, 1) == ep->to_rtx)
3238 offset = INTVAL (XEXP (src, 0)), ok = 1;
3239 else if (GET_CODE (src) == PLUS
3240 && GET_CODE (XEXP (src, 1)) == CONST_INT
3241 && XEXP (src, 0) == ep->to_rtx)
3242 offset = INTVAL (XEXP (src, 1)), ok = 1;
3250 = plus_constant (ep->to_rtx, offset - ep->offset);
3252 /* First see if this insn remains valid when we
3253 make the change. If not, keep the INSN_CODE
3254 the same and let reload fit it up. */
3255 validate_change (insn, &SET_SRC (old_set), src, 1);
3256 validate_change (insn, &SET_DEST (old_set),
3258 if (! apply_change_group ())
3260 SET_SRC (old_set) = src;
3261 SET_DEST (old_set) = ep->to_rtx;
3271 /* In this case this insn isn't serving a useful purpose. We
3272 will delete it in reload_as_needed once we know that this
3273 elimination is, in fact, being done.
3275 If REPLACE isn't set, we can't delete this insn, but needn't
3276 process it since it won't be used unless something changes. */
3278 delete_dead_insn (insn);
3283 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3284 in the insn is the negative of the offset in FROM. Substitute
3285 (set (reg) (reg to)) for the insn and change its code.
3287 We have to do this here, rather than in eliminate_regs, so that we can
3288 change the insn code. */
3290 if (GET_CODE (SET_SRC (old_set)) == PLUS
3291 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3292 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT)
3293 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3295 if (ep->from_rtx == XEXP (SET_SRC (old_set), 0)
3296 && ep->can_eliminate)
3298 /* We must stop at the first elimination that will be used.
3299 If this one would replace the PLUS with a REG, do it
3300 now. Otherwise, quit the loop and let eliminate_regs
3301 do its normal replacement. */
3302 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_set), 1)))
3304 /* We assume here that we don't need a PARALLEL of
3305 any CLOBBERs for this assignment. There's not
3306 much we can do if we do need it. */
3307 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3310 INSN_CODE (insn) = -1;
3319 old_asm_operands_vec = 0;
3321 /* Replace the body of this insn with a substituted form. If we changed
3322 something, return non-zero.
3324 If we are replacing a body that was a (set X (plus Y Z)), try to
3325 re-recognize the insn. We do this in case we had a simple addition
3326 but now can do this as a load-address. This saves an insn in this
3329 new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX);
3330 if (new_body != old_body)
3332 /* If we aren't replacing things permanently and we changed something,
3333 make another copy to ensure that all the RTL is new. Otherwise
3334 things can go wrong if find_reload swaps commutative operands
3335 and one is inside RTL that has been copied while the other is not. */
3337 /* Don't copy an asm_operands because (1) there's no need and (2)
3338 copy_rtx can't do it properly when there are multiple outputs. */
3339 if (! replace && asm_noperands (old_body) < 0)
3340 new_body = copy_rtx (new_body);
3342 /* If we had a move insn but now we don't, rerecognize it. This will
3343 cause spurious re-recognition if the old move had a PARALLEL since
3344 the new one still will, but we can't call single_set without
3345 having put NEW_BODY into the insn and the re-recognition won't
3346 hurt in this rare case. */
3348 && ((GET_CODE (SET_SRC (old_set)) == REG
3349 && (GET_CODE (new_body) != SET
3350 || GET_CODE (SET_SRC (new_body)) != REG))
3351 /* If this was a load from or store to memory, compare
3352 the MEM in recog_operand to the one in the insn. If they
3353 are not equal, then rerecognize the insn. */
3355 && ((GET_CODE (SET_SRC (old_set)) == MEM
3356 && SET_SRC (old_set) != recog_operand[1])
3357 || (GET_CODE (SET_DEST (old_set)) == MEM
3358 && SET_DEST (old_set) != recog_operand[0])))
3359 /* If this was an add insn before, rerecognize. */
3360 || GET_CODE (SET_SRC (old_set)) == PLUS))
3362 if (! validate_change (insn, &PATTERN (insn), new_body, 0))
3363 /* If recognition fails, store the new body anyway.
3364 It's normal to have recognition failures here
3365 due to bizarre memory addresses; reloading will fix them. */
3366 PATTERN (insn) = new_body;
3369 PATTERN (insn) = new_body;
3374 /* Loop through all elimination pairs. See if any have changed.
3376 We also detect a cases where register elimination cannot be done,
3377 namely, if a register would be both changed and referenced outside a MEM
3378 in the resulting insn since such an insn is often undefined and, even if
3379 not, we cannot know what meaning will be given to it. Note that it is
3380 valid to have a register used in an address in an insn that changes it
3381 (presumably with a pre- or post-increment or decrement).
3383 If anything changes, return nonzero. */
3385 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3387 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3388 ep->can_eliminate = 0;
3390 ep->ref_outside_mem = 0;
3392 if (ep->previous_offset != ep->offset)
3397 /* If we changed something, perform elimination in REG_NOTES. This is
3398 needed even when REPLACE is zero because a REG_DEAD note might refer
3399 to a register that we eliminate and could cause a different number
3400 of spill registers to be needed in the final reload pass than in
3402 if (val && REG_NOTES (insn) != 0)
3403 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3411 /* Loop through all elimination pairs.
3412 Recalculate the number not at initial offset.
3414 Compute the maximum offset (minimum offset if the stack does not
3415 grow downward) for each elimination pair. */
3418 update_eliminable_offsets ()
3420 struct elim_table *ep;
3422 num_not_at_initial_offset = 0;
3423 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3425 ep->previous_offset = ep->offset;
3426 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3427 num_not_at_initial_offset++;
3431 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3432 replacement we currently believe is valid, mark it as not eliminable if X
3433 modifies DEST in any way other than by adding a constant integer to it.
3435 If DEST is the frame pointer, we do nothing because we assume that
3436 all assignments to the hard frame pointer are nonlocal gotos and are being
3437 done at a time when they are valid and do not disturb anything else.
3438 Some machines want to eliminate a fake argument pointer with either the
3439 frame or stack pointer. Assignments to the hard frame pointer must not
3440 prevent this elimination.
3442 Called via note_stores from reload before starting its passes to scan
3443 the insns of the function. */
3446 mark_not_eliminable (dest, x)
3450 register unsigned int i;
3452 /* A SUBREG of a hard register here is just changing its mode. We should
3453 not see a SUBREG of an eliminable hard register, but check just in
3455 if (GET_CODE (dest) == SUBREG)
3456 dest = SUBREG_REG (dest);
3458 if (dest == hard_frame_pointer_rtx)
3461 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3462 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3463 && (GET_CODE (x) != SET
3464 || GET_CODE (SET_SRC (x)) != PLUS
3465 || XEXP (SET_SRC (x), 0) != dest
3466 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3468 reg_eliminate[i].can_eliminate_previous
3469 = reg_eliminate[i].can_eliminate = 0;
3474 /* Verify that the initial elimination offsets did not change since the
3475 last call to set_initial_elim_offsets. This is used to catch cases
3476 where something illegal happened during reload_as_needed that could
3477 cause incorrect code to be generated if we did not check for it. */
3479 verify_initial_elim_offsets ()
3483 #ifdef ELIMINABLE_REGS
3484 struct elim_table *ep;
3486 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3488 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3489 if (t != ep->initial_offset)
3493 INITIAL_FRAME_POINTER_OFFSET (t);
3494 if (t != reg_eliminate[0].initial_offset)
3499 /* Reset all offsets on eliminable registers to their initial values. */
3501 set_initial_elim_offsets ()
3503 struct elim_table *ep = reg_eliminate;
3505 #ifdef ELIMINABLE_REGS
3506 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3508 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3509 ep->previous_offset = ep->offset = ep->initial_offset;
3512 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3513 ep->previous_offset = ep->offset = ep->initial_offset;
3516 num_not_at_initial_offset = 0;
3519 /* Initialize the known label offsets.
3520 Set a known offset for each forced label to be at the initial offset
3521 of each elimination. We do this because we assume that all
3522 computed jumps occur from a location where each elimination is
3523 at its initial offset.
3524 For all other labels, show that we don't know the offsets. */
3527 set_initial_label_offsets ()
3530 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
3532 for (x = forced_labels; x; x = XEXP (x, 1))
3534 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3537 /* Set all elimination offsets to the known values for the code label given
3540 set_offsets_for_label (insn)
3544 int label_nr = CODE_LABEL_NUMBER (insn);
3545 struct elim_table *ep;
3547 num_not_at_initial_offset = 0;
3548 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3550 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3551 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3552 num_not_at_initial_offset++;
3556 /* See if anything that happened changes which eliminations are valid.
3557 For example, on the Sparc, whether or not the frame pointer can
3558 be eliminated can depend on what registers have been used. We need
3559 not check some conditions again (such as flag_omit_frame_pointer)
3560 since they can't have changed. */
3563 update_eliminables (pset)
3566 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3567 int previous_frame_pointer_needed = frame_pointer_needed;
3569 struct elim_table *ep;
3571 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3572 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3573 #ifdef ELIMINABLE_REGS
3574 || ! CAN_ELIMINATE (ep->from, ep->to)
3577 ep->can_eliminate = 0;
3579 /* Look for the case where we have discovered that we can't replace
3580 register A with register B and that means that we will now be
3581 trying to replace register A with register C. This means we can
3582 no longer replace register C with register B and we need to disable
3583 such an elimination, if it exists. This occurs often with A == ap,
3584 B == sp, and C == fp. */
3586 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3588 struct elim_table *op;
3589 register int new_to = -1;
3591 if (! ep->can_eliminate && ep->can_eliminate_previous)
3593 /* Find the current elimination for ep->from, if there is a
3595 for (op = reg_eliminate;
3596 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3597 if (op->from == ep->from && op->can_eliminate)
3603 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3605 for (op = reg_eliminate;
3606 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3607 if (op->from == new_to && op->to == ep->to)
3608 op->can_eliminate = 0;
3612 /* See if any registers that we thought we could eliminate the previous
3613 time are no longer eliminable. If so, something has changed and we
3614 must spill the register. Also, recompute the number of eliminable
3615 registers and see if the frame pointer is needed; it is if there is
3616 no elimination of the frame pointer that we can perform. */
3618 frame_pointer_needed = 1;
3619 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3621 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3622 && ep->to != HARD_FRAME_POINTER_REGNUM)
3623 frame_pointer_needed = 0;
3625 if (! ep->can_eliminate && ep->can_eliminate_previous)
3627 ep->can_eliminate_previous = 0;
3628 SET_HARD_REG_BIT (*pset, ep->from);
3633 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3634 /* If we didn't need a frame pointer last time, but we do now, spill
3635 the hard frame pointer. */
3636 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3637 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3641 /* Initialize the table of registers to eliminate. */
3645 struct elim_table *ep;
3646 #ifdef ELIMINABLE_REGS
3647 struct elim_table_1 *ep1;
3652 reg_eliminate = (struct elim_table *)
3653 xmalloc(sizeof(struct elim_table) * NUM_ELIMINABLE_REGS);
3654 bzero ((PTR) reg_eliminate,
3655 sizeof(struct elim_table) * NUM_ELIMINABLE_REGS);
3658 /* Does this function require a frame pointer? */
3660 frame_pointer_needed = (! flag_omit_frame_pointer
3661 #ifdef EXIT_IGNORE_STACK
3662 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3663 and restore sp for alloca. So we can't eliminate
3664 the frame pointer in that case. At some point,
3665 we should improve this by emitting the
3666 sp-adjusting insns for this case. */
3667 || (current_function_calls_alloca
3668 && EXIT_IGNORE_STACK)
3670 || FRAME_POINTER_REQUIRED);
3674 #ifdef ELIMINABLE_REGS
3675 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3676 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3678 ep->from = ep1->from;
3680 ep->can_eliminate = ep->can_eliminate_previous
3681 = (CAN_ELIMINATE (ep->from, ep->to)
3682 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3685 reg_eliminate[0].from = reg_eliminate_1[0].from;
3686 reg_eliminate[0].to = reg_eliminate_1[0].to;
3687 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3688 = ! frame_pointer_needed;
3691 /* Count the number of eliminable registers and build the FROM and TO
3692 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3693 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3694 We depend on this. */
3695 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3697 num_eliminable += ep->can_eliminate;
3698 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3699 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3703 /* Kick all pseudos out of hard register REGNO.
3704 If DUMPFILE is nonzero, log actions taken on that file.
3706 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3707 because we found we can't eliminate some register. In the case, no pseudos
3708 are allowed to be in the register, even if they are only in a block that
3709 doesn't require spill registers, unlike the case when we are spilling this
3710 hard reg to produce another spill register.
3712 Return nonzero if any pseudos needed to be kicked out. */
3715 spill_hard_reg (regno, dumpfile, cant_eliminate)
3724 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3725 regs_ever_live[regno] = 1;
3728 /* Spill every pseudo reg that was allocated to this reg
3729 or to something that overlaps this reg. */
3731 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3732 if (reg_renumber[i] >= 0
3733 && reg_renumber[i] <= regno
3735 + HARD_REGNO_NREGS (reg_renumber[i],
3736 PSEUDO_REGNO_MODE (i))
3738 SET_REGNO_REG_SET (spilled_pseudos, i);
3741 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3742 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3744 ior_hard_reg_set (set1, set2)
3745 HARD_REG_SET *set1, *set2;
3747 IOR_HARD_REG_SET (*set1, *set2);
3750 /* After find_reload_regs has been run for all insn that need reloads,
3751 and/or spill_hard_regs was called, this function is used to actually
3752 spill pseudo registers and try to reallocate them. It also sets up the
3753 spill_regs array for use by choose_reload_regs. */
3756 finish_spills (global, dumpfile)
3760 struct insn_chain *chain;
3761 int something_changed = 0;
3764 /* Build the spill_regs array for the function. */
3765 /* If there are some registers still to eliminate and one of the spill regs
3766 wasn't ever used before, additional stack space may have to be
3767 allocated to store this register. Thus, we may have changed the offset
3768 between the stack and frame pointers, so mark that something has changed.
3770 One might think that we need only set VAL to 1 if this is a call-used
3771 register. However, the set of registers that must be saved by the
3772 prologue is not identical to the call-used set. For example, the
3773 register used by the call insn for the return PC is a call-used register,
3774 but must be saved by the prologue. */
3777 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3778 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3780 spill_reg_order[i] = n_spills;
3781 spill_regs[n_spills++] = i;
3782 if (num_eliminable && ! regs_ever_live[i])
3783 something_changed = 1;
3784 regs_ever_live[i] = 1;
3787 spill_reg_order[i] = -1;
3789 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3790 if (REGNO_REG_SET_P (spilled_pseudos, i))
3792 /* Record the current hard register the pseudo is allocated to in
3793 pseudo_previous_regs so we avoid reallocating it to the same
3794 hard reg in a later pass. */
3795 if (reg_renumber[i] < 0)
3797 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3798 /* Mark it as no longer having a hard register home. */
3799 reg_renumber[i] = -1;
3800 /* We will need to scan everything again. */
3801 something_changed = 1;
3804 /* Retry global register allocation if possible. */
3807 bzero ((char *) pseudo_forbidden_regs, max_regno * sizeof (HARD_REG_SET));
3808 /* For every insn that needs reloads, set the registers used as spill
3809 regs in pseudo_forbidden_regs for every pseudo live across the
3811 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3813 EXECUTE_IF_SET_IN_REG_SET
3814 (chain->live_before, FIRST_PSEUDO_REGISTER, i,
3816 ior_hard_reg_set (pseudo_forbidden_regs + i,
3817 &chain->used_spill_regs);
3819 EXECUTE_IF_SET_IN_REG_SET
3820 (chain->live_after, FIRST_PSEUDO_REGISTER, i,
3822 ior_hard_reg_set (pseudo_forbidden_regs + i,
3823 &chain->used_spill_regs);
3827 /* Retry allocating the spilled pseudos. For each reg, merge the
3828 various reg sets that indicate which hard regs can't be used,
3829 and call retry_global_alloc.
3830 We change spill_pseudos here to only contain pseudos that did not
3831 get a new hard register. */
3832 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3833 if (reg_old_renumber[i] != reg_renumber[i])
3835 HARD_REG_SET forbidden;
3836 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3837 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3838 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3839 retry_global_alloc (i, forbidden);
3840 if (reg_renumber[i] >= 0)
3841 CLEAR_REGNO_REG_SET (spilled_pseudos, i);
3845 /* Fix up the register information in the insn chain.
3846 This involves deleting those of the spilled pseudos which did not get
3847 a new hard register home from the live_{before,after} sets. */
3848 for (chain = reload_insn_chain; chain; chain = chain->next)
3850 HARD_REG_SET used_by_pseudos;
3851 HARD_REG_SET used_by_pseudos2;
3853 AND_COMPL_REG_SET (chain->live_before, spilled_pseudos);
3854 AND_COMPL_REG_SET (chain->live_after, spilled_pseudos);
3856 /* Mark any unallocated hard regs as available for spills. That
3857 makes inheritance work somewhat better. */
3858 if (chain->need_reload)
3860 REG_SET_TO_HARD_REG_SET (used_by_pseudos, chain->live_before);
3861 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, chain->live_after);
3862 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3864 /* Save the old value for the sanity test below. */
3865 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3867 compute_use_by_pseudos (&used_by_pseudos, chain->live_before);
3868 compute_use_by_pseudos (&used_by_pseudos, chain->live_after);
3869 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3870 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3872 /* Make sure we only enlarge the set. */
3873 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3879 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3880 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3882 int regno = reg_renumber[i];
3883 if (reg_old_renumber[i] == regno)
3886 alter_reg (i, reg_old_renumber[i]);
3887 reg_old_renumber[i] = regno;
3891 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3893 fprintf (dumpfile, " Register %d now in %d.\n\n",
3894 i, reg_renumber[i]);
3898 return something_changed;
3901 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3902 Also mark any hard registers used to store user variables as
3903 forbidden from being used for spill registers. */
3906 scan_paradoxical_subregs (x)
3911 register enum rtx_code code = GET_CODE (x);
3917 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3918 && REG_USERVAR_P (x))
3919 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3935 if (GET_CODE (SUBREG_REG (x)) == REG
3936 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3937 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3938 = GET_MODE_SIZE (GET_MODE (x));
3945 fmt = GET_RTX_FORMAT (code);
3946 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3949 scan_paradoxical_subregs (XEXP (x, i));
3950 else if (fmt[i] == 'E')
3953 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3954 scan_paradoxical_subregs (XVECEXP (x, i, j));
3960 hard_reg_use_compare (p1p, p2p)
3961 const GENERIC_PTR p1p;
3962 const GENERIC_PTR p2p;
3964 struct hard_reg_n_uses *p1 = (struct hard_reg_n_uses *)p1p;
3965 struct hard_reg_n_uses *p2 = (struct hard_reg_n_uses *)p2p;
3966 int bad1 = TEST_HARD_REG_BIT (bad_spill_regs, p1->regno);
3967 int bad2 = TEST_HARD_REG_BIT (bad_spill_regs, p2->regno);
3969 return p1->regno - p2->regno;
3974 if (p1->uses > p2->uses)
3976 if (p1->uses < p2->uses)
3978 /* If regs are equally good, sort by regno,
3979 so that the results of qsort leave nothing to chance. */
3980 return p1->regno - p2->regno;
3983 /* Used for communication between order_regs_for_reload and count_pseudo.
3984 Used to avoid counting one pseudo twice. */
3985 static regset pseudos_counted;
3987 /* Update the costs in N_USES, considering that pseudo REG is live. */
3989 count_pseudo (n_uses, reg)
3990 struct hard_reg_n_uses *n_uses;
3993 int r = reg_renumber[reg];
3996 if (REGNO_REG_SET_P (pseudos_counted, reg))
3998 SET_REGNO_REG_SET (pseudos_counted, reg);
4003 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
4005 n_uses[r++].uses += REG_N_REFS (reg);
4007 /* Choose the order to consider regs for use as reload registers
4008 based on how much trouble would be caused by spilling one.
4009 Store them in order of decreasing preference in potential_reload_regs. */
4012 order_regs_for_reload (chain)
4013 struct insn_chain *chain;
4017 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
4019 pseudos_counted = ALLOCA_REG_SET ();
4021 COPY_HARD_REG_SET (bad_spill_regs, bad_spill_regs_global);
4023 /* Count number of uses of each hard reg by pseudo regs allocated to it
4024 and then order them by decreasing use. */
4026 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4030 hard_reg_n_uses[i].regno = i;
4031 hard_reg_n_uses[i].uses = 0;
4033 /* Test the various reasons why we can't use a register for
4034 spilling in this insn. */
4036 || REGNO_REG_SET_P (chain->live_before, i)
4037 || REGNO_REG_SET_P (chain->live_after, i))
4039 SET_HARD_REG_BIT (bad_spill_regs, i);
4043 /* Now find out which pseudos are allocated to it, and update
4045 CLEAR_REG_SET (pseudos_counted);
4047 EXECUTE_IF_SET_IN_REG_SET
4048 (chain->live_before, FIRST_PSEUDO_REGISTER, j,
4050 count_pseudo (hard_reg_n_uses, j);
4052 EXECUTE_IF_SET_IN_REG_SET
4053 (chain->live_after, FIRST_PSEUDO_REGISTER, j,
4055 count_pseudo (hard_reg_n_uses, j);
4059 FREE_REG_SET (pseudos_counted);
4061 /* Prefer registers not so far used, for use in temporary loading.
4062 Among them, if REG_ALLOC_ORDER is defined, use that order.
4063 Otherwise, prefer registers not preserved by calls. */
4065 #ifdef REG_ALLOC_ORDER
4066 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4068 int regno = reg_alloc_order[i];
4070 if (hard_reg_n_uses[regno].uses == 0
4071 && ! TEST_HARD_REG_BIT (bad_spill_regs, regno))
4072 potential_reload_regs[o++] = regno;
4075 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4077 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i]
4078 && ! TEST_HARD_REG_BIT (bad_spill_regs, i))
4079 potential_reload_regs[o++] = i;
4081 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4083 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i]
4084 && ! TEST_HARD_REG_BIT (bad_spill_regs, i))
4085 potential_reload_regs[o++] = i;
4089 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
4090 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
4092 /* Now add the regs that are already used,
4093 preferring those used less often. The fixed and otherwise forbidden
4094 registers will be at the end of this list. */
4096 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4097 if (hard_reg_n_uses[i].uses != 0
4098 && ! TEST_HARD_REG_BIT (bad_spill_regs, hard_reg_n_uses[i].regno))
4099 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
4100 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4101 if (TEST_HARD_REG_BIT (bad_spill_regs, hard_reg_n_uses[i].regno))
4102 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
4105 /* Reload pseudo-registers into hard regs around each insn as needed.
4106 Additional register load insns are output before the insn that needs it
4107 and perhaps store insns after insns that modify the reloaded pseudo reg.
4109 reg_last_reload_reg and reg_reloaded_contents keep track of
4110 which registers are already available in reload registers.
4111 We update these for the reloads that we perform,
4112 as the insns are scanned. */
4115 reload_as_needed (live_known)
4118 struct insn_chain *chain;
4122 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
4123 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
4124 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
4125 bzero ((char *) reg_last_reload_reg, max_regno * sizeof (rtx));
4126 reg_has_output_reload = (char *) alloca (max_regno);
4127 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4129 set_initial_elim_offsets ();
4131 for (chain = reload_insn_chain; chain; chain = chain->next)
4134 rtx insn = chain->insn;
4135 rtx old_next = NEXT_INSN (insn);
4137 /* If we pass a label, copy the offsets from the label information
4138 into the current offsets of each elimination. */
4139 if (GET_CODE (insn) == CODE_LABEL)
4140 set_offsets_for_label (insn);
4142 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
4144 rtx oldpat = PATTERN (insn);
4146 /* If this is a USE and CLOBBER of a MEM, ensure that any
4147 references to eliminable registers have been removed. */
4149 if ((GET_CODE (PATTERN (insn)) == USE
4150 || GET_CODE (PATTERN (insn)) == CLOBBER)
4151 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
4152 XEXP (XEXP (PATTERN (insn), 0), 0)
4153 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4154 GET_MODE (XEXP (PATTERN (insn), 0)),
4157 /* If we need to do register elimination processing, do so.
4158 This might delete the insn, in which case we are done. */
4159 if (num_eliminable && chain->need_elim)
4161 eliminate_regs_in_insn (insn, 1);
4162 if (GET_CODE (insn) == NOTE)
4164 update_eliminable_offsets ();
4169 /* If need_elim is nonzero but need_reload is zero, one might think
4170 that we could simply set n_reloads to 0. However, find_reloads
4171 could have done some manipulation of the insn (such as swapping
4172 commutative operands), and these manipulations are lost during
4173 the first pass for every insn that needs register elimination.
4174 So the actions of find_reloads must be redone here. */
4176 if (! chain->need_elim && ! chain->need_reload
4177 && ! chain->need_operand_change)
4179 /* First find the pseudo regs that must be reloaded for this insn.
4180 This info is returned in the tables reload_... (see reload.h).
4181 Also modify the body of INSN by substituting RELOAD
4182 rtx's for those pseudo regs. */
4185 bzero (reg_has_output_reload, max_regno);
4186 CLEAR_HARD_REG_SET (reg_is_output_reload);
4188 find_reloads (insn, 1, spill_indirect_levels, live_known,
4192 if (num_eliminable && chain->need_elim)
4193 update_eliminable_offsets ();
4197 rtx next = NEXT_INSN (insn);
4200 prev = PREV_INSN (insn);
4202 /* Now compute which reload regs to reload them into. Perhaps
4203 reusing reload regs from previous insns, or else output
4204 load insns to reload them. Maybe output store insns too.
4205 Record the choices of reload reg in reload_reg_rtx. */
4206 choose_reload_regs (chain);
4208 /* Merge any reloads that we didn't combine for fear of
4209 increasing the number of spill registers needed but now
4210 discover can be safely merged. */
4211 if (SMALL_REGISTER_CLASSES)
4212 merge_assigned_reloads (insn);
4214 /* Generate the insns to reload operands into or out of
4215 their reload regs. */
4216 emit_reload_insns (chain);
4218 /* Substitute the chosen reload regs from reload_reg_rtx
4219 into the insn's body (or perhaps into the bodies of other
4220 load and store insn that we just made for reloading
4221 and that we moved the structure into). */
4224 /* If this was an ASM, make sure that all the reload insns
4225 we have generated are valid. If not, give an error
4228 if (asm_noperands (PATTERN (insn)) >= 0)
4229 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4230 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
4231 && (recog_memoized (p) < 0
4232 || (extract_insn (p), ! constrain_operands (1))))
4234 error_for_asm (insn,
4235 "`asm' operand requires impossible reload");
4237 NOTE_SOURCE_FILE (p) = 0;
4238 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
4241 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4242 is no longer validly lying around to save a future reload.
4243 Note that this does not detect pseudos that were reloaded
4244 for this insn in order to be stored in
4245 (obeying register constraints). That is correct; such reload
4246 registers ARE still valid. */
4247 note_stores (oldpat, forget_old_reloads_1);
4249 /* There may have been CLOBBER insns placed after INSN. So scan
4250 between INSN and NEXT and use them to forget old reloads. */
4251 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4252 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
4253 note_stores (PATTERN (x), forget_old_reloads_1);
4256 /* Likewise for regs altered by auto-increment in this insn.
4257 REG_INC notes have been changed by reloading:
4258 find_reloads_address_1 records substitutions for them,
4259 which have been performed by subst_reloads above. */
4260 for (i = n_reloads - 1; i >= 0; i--)
4262 rtx in_reg = reload_in_reg[i];
4265 enum rtx_code code = GET_CODE (in_reg);
4266 /* PRE_INC / PRE_DEC will have the reload register ending up
4267 with the same value as the stack slot, but that doesn't
4268 hold true for POST_INC / POST_DEC. Either we have to
4269 convert the memory access to a true POST_INC / POST_DEC,
4270 or we can't use the reload register for inheritance. */
4271 if ((code == POST_INC || code == POST_DEC)
4272 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4273 REGNO (reload_reg_rtx[i]))
4274 /* Make sure it is the inc/dec pseudo, and not
4275 some other (e.g. output operand) pseudo. */
4276 && (reg_reloaded_contents[REGNO (reload_reg_rtx[i])]
4277 == REGNO (XEXP (in_reg, 0))))
4280 rtx reload_reg = reload_reg_rtx[i];
4281 enum machine_mode mode = GET_MODE (reload_reg);
4285 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4287 /* We really want to ignore REG_INC notes here, so
4288 use PATTERN (p) as argument to reg_set_p . */
4289 if (reg_set_p (reload_reg, PATTERN (p)))
4291 n = count_occurrences (PATTERN (p), reload_reg);
4295 n = validate_replace_rtx (reload_reg,
4296 gen_rtx (code, mode,
4301 REG_NOTES (p) = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4304 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX);
4308 #if 0 /* ??? Is this code obsolete now? Need to check carefully. */
4309 /* Likewise for regs altered by auto-increment in this insn.
4310 But note that the reg-notes are not changed by reloading:
4311 they still contain the pseudo-regs, not the spill regs. */
4312 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4313 if (REG_NOTE_KIND (x) == REG_INC)
4315 /* See if this pseudo reg was reloaded in this insn.
4316 If so, its last-reload info is still valid
4317 because it is based on this insn's reload. */
4318 for (i = 0; i < n_reloads; i++)
4319 if (reload_out[i] == XEXP (x, 0))
4323 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX);
4328 /* A reload reg's contents are unknown after a label. */
4329 if (GET_CODE (insn) == CODE_LABEL)
4330 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4332 /* Don't assume a reload reg is still good after a call insn
4333 if it is a call-used reg. */
4334 else if (GET_CODE (insn) == CALL_INSN)
4335 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
4337 /* In case registers overlap, allow certain insns to invalidate
4338 particular hard registers. */
4340 #ifdef INSN_CLOBBERS_REGNO_P
4341 for (i = 0 ; i < FIRST_PSEUDO_REGISTER; i++)
4342 if (TEST_HARD_REG_BIT (reg_reloaded_valid, i)
4343 && INSN_CLOBBERS_REGNO_P (insn, i))
4344 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i);
4353 /* Discard all record of any value reloaded from X,
4354 or reloaded in X from someplace else;
4355 unless X is an output reload reg of the current insn.
4357 X may be a hard reg (the reload reg)
4358 or it may be a pseudo reg that was reloaded from. */
4361 forget_old_reloads_1 (x, ignored)
4363 rtx ignored ATTRIBUTE_UNUSED;
4369 /* note_stores does give us subregs of hard regs. */
4370 while (GET_CODE (x) == SUBREG)
4372 offset += SUBREG_WORD (x);
4376 if (GET_CODE (x) != REG)
4379 regno = REGNO (x) + offset;
4381 if (regno >= FIRST_PSEUDO_REGISTER)
4386 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4387 /* Storing into a spilled-reg invalidates its contents.
4388 This can happen if a block-local pseudo is allocated to that reg
4389 and it wasn't spilled because this block's total need is 0.
4390 Then some insn might have an optional reload and use this reg. */
4391 for (i = 0; i < nr; i++)
4392 /* But don't do this if the reg actually serves as an output
4393 reload reg in the current instruction. */
4395 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4396 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4399 /* Since value of X has changed,
4400 forget any value previously copied from it. */
4403 /* But don't forget a copy if this is the output reload
4404 that establishes the copy's validity. */
4405 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4406 reg_last_reload_reg[regno + nr] = 0;
4409 /* For each reload, the mode of the reload register. */
4410 static enum machine_mode reload_mode[MAX_RELOADS];
4412 /* For each reload, the largest number of registers it will require. */
4413 static int reload_nregs[MAX_RELOADS];
4415 /* Comparison function for qsort to decide which of two reloads
4416 should be handled first. *P1 and *P2 are the reload numbers. */
4419 reload_reg_class_lower (r1p, r2p)
4420 const GENERIC_PTR r1p;
4421 const GENERIC_PTR r2p;
4423 register int r1 = *(short *)r1p, r2 = *(short *)r2p;
4426 /* Consider required reloads before optional ones. */
4427 t = reload_optional[r1] - reload_optional[r2];
4431 /* Count all solitary classes before non-solitary ones. */
4432 t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
4433 - (reg_class_size[(int) reload_reg_class[r1]] == 1));
4437 /* Aside from solitaires, consider all multi-reg groups first. */
4438 t = reload_nregs[r2] - reload_nregs[r1];
4442 /* Consider reloads in order of increasing reg-class number. */
4443 t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
4447 /* If reloads are equally urgent, sort by reload number,
4448 so that the results of qsort leave nothing to chance. */
4452 /* The following HARD_REG_SETs indicate when each hard register is
4453 used for a reload of various parts of the current insn. */
4455 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4456 static HARD_REG_SET reload_reg_used;
4457 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4458 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4459 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4460 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4461 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4462 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4463 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4464 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4465 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4466 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4467 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4468 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4469 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4470 static HARD_REG_SET reload_reg_used_in_op_addr;
4471 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4472 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4473 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4474 static HARD_REG_SET reload_reg_used_in_insn;
4475 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4476 static HARD_REG_SET reload_reg_used_in_other_addr;
4478 /* If reg is in use as a reload reg for any sort of reload. */
4479 static HARD_REG_SET reload_reg_used_at_all;
4481 /* If reg is use as an inherited reload. We just mark the first register
4483 static HARD_REG_SET reload_reg_used_for_inherit;
4485 /* Records which hard regs are allocated to a pseudo during any point of the
4487 static HARD_REG_SET reg_used_by_pseudo;
4489 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4490 TYPE. MODE is used to indicate how many consecutive regs are
4494 mark_reload_reg_in_use (regno, opnum, type, mode)
4497 enum reload_type type;
4498 enum machine_mode mode;
4500 int nregs = HARD_REGNO_NREGS (regno, mode);
4503 for (i = regno; i < nregs + regno; i++)
4508 SET_HARD_REG_BIT (reload_reg_used, i);
4511 case RELOAD_FOR_INPUT_ADDRESS:
4512 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4515 case RELOAD_FOR_INPADDR_ADDRESS:
4516 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4519 case RELOAD_FOR_OUTPUT_ADDRESS:
4520 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4523 case RELOAD_FOR_OUTADDR_ADDRESS:
4524 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4527 case RELOAD_FOR_OPERAND_ADDRESS:
4528 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4531 case RELOAD_FOR_OPADDR_ADDR:
4532 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4535 case RELOAD_FOR_OTHER_ADDRESS:
4536 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4539 case RELOAD_FOR_INPUT:
4540 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4543 case RELOAD_FOR_OUTPUT:
4544 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4547 case RELOAD_FOR_INSN:
4548 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4552 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4556 /* Similarly, but show REGNO is no longer in use for a reload. */
4559 clear_reload_reg_in_use (regno, opnum, type, mode)
4562 enum reload_type type;
4563 enum machine_mode mode;
4565 int nregs = HARD_REGNO_NREGS (regno, mode);
4566 int start_regno, end_regno;
4568 /* A complication is that for some reload types, inheritance might
4569 allow multiple reloads of the same types to share a reload register.
4570 We set check_opnum if we have to check only reloads with the same
4571 operand number, and check_any if we have to check all reloads. */
4572 int check_opnum = 0;
4574 HARD_REG_SET *used_in_set;
4579 used_in_set = &reload_reg_used;
4582 case RELOAD_FOR_INPUT_ADDRESS:
4583 used_in_set = &reload_reg_used_in_input_addr[opnum];
4586 case RELOAD_FOR_INPADDR_ADDRESS:
4588 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4591 case RELOAD_FOR_OUTPUT_ADDRESS:
4592 used_in_set = &reload_reg_used_in_output_addr[opnum];
4595 case RELOAD_FOR_OUTADDR_ADDRESS:
4597 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4600 case RELOAD_FOR_OPERAND_ADDRESS:
4601 used_in_set = &reload_reg_used_in_op_addr;
4604 case RELOAD_FOR_OPADDR_ADDR:
4606 used_in_set = &reload_reg_used_in_op_addr_reload;
4609 case RELOAD_FOR_OTHER_ADDRESS:
4610 used_in_set = &reload_reg_used_in_other_addr;
4614 case RELOAD_FOR_INPUT:
4615 used_in_set = &reload_reg_used_in_input[opnum];
4618 case RELOAD_FOR_OUTPUT:
4619 used_in_set = &reload_reg_used_in_output[opnum];
4622 case RELOAD_FOR_INSN:
4623 used_in_set = &reload_reg_used_in_insn;
4628 /* We resolve conflicts with remaining reloads of the same type by
4629 excluding the intervals of of reload registers by them from the
4630 interval of freed reload registers. Since we only keep track of
4631 one set of interval bounds, we might have to exclude somewhat
4632 more then what would be necessary if we used a HARD_REG_SET here.
4633 But this should only happen very infrequently, so there should
4634 be no reason to worry about it. */
4636 start_regno = regno;
4637 end_regno = regno + nregs;
4638 if (check_opnum || check_any)
4640 for (i = n_reloads - 1; i >= 0; i--)
4642 if (reload_when_needed[i] == type
4643 && (check_any || reload_opnum[i] == opnum)
4644 && reload_reg_rtx[i])
4646 int conflict_start = true_regnum (reload_reg_rtx[i]);
4649 + HARD_REGNO_NREGS (conflict_start, reload_mode[i]));
4651 /* If there is an overlap with the first to-be-freed register,
4652 adjust the interval start. */
4653 if (conflict_start <= start_regno && conflict_end > start_regno)
4654 start_regno = conflict_end;
4655 /* Otherwise, if there is a conflict with one of the other
4656 to-be-freed registers, adjust the interval end. */
4657 if (conflict_start > start_regno && conflict_start < end_regno)
4658 end_regno = conflict_start;
4662 for (i = start_regno; i < end_regno; i++)
4663 CLEAR_HARD_REG_BIT (*used_in_set, i);
4666 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4667 specified by OPNUM and TYPE. */
4670 reload_reg_free_p (regno, opnum, type)
4673 enum reload_type type;
4677 /* In use for a RELOAD_OTHER means it's not available for anything. */
4678 if (TEST_HARD_REG_BIT (reload_reg_used, regno))
4684 /* In use for anything means we can't use it for RELOAD_OTHER. */
4685 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4686 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4687 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4690 for (i = 0; i < reload_n_operands; i++)
4691 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4692 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4693 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4694 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4695 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4696 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4701 case RELOAD_FOR_INPUT:
4702 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4703 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4706 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4709 /* If it is used for some other input, can't use it. */
4710 for (i = 0; i < reload_n_operands; i++)
4711 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4714 /* If it is used in a later operand's address, can't use it. */
4715 for (i = opnum + 1; i < reload_n_operands; i++)
4716 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4717 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4722 case RELOAD_FOR_INPUT_ADDRESS:
4723 /* Can't use a register if it is used for an input address for this
4724 operand or used as an input in an earlier one. */
4725 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4726 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4729 for (i = 0; i < opnum; i++)
4730 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4735 case RELOAD_FOR_INPADDR_ADDRESS:
4736 /* Can't use a register if it is used for an input address
4737 for this operand or used as an input in an earlier
4739 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4742 for (i = 0; i < opnum; i++)
4743 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4748 case RELOAD_FOR_OUTPUT_ADDRESS:
4749 /* Can't use a register if it is used for an output address for this
4750 operand or used as an output in this or a later operand. */
4751 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4754 for (i = opnum; i < reload_n_operands; i++)
4755 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4760 case RELOAD_FOR_OUTADDR_ADDRESS:
4761 /* Can't use a register if it is used for an output address
4762 for this operand or used as an output in this or a
4764 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4767 for (i = opnum; i < reload_n_operands; i++)
4768 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4773 case RELOAD_FOR_OPERAND_ADDRESS:
4774 for (i = 0; i < reload_n_operands; i++)
4775 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4778 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4779 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4781 case RELOAD_FOR_OPADDR_ADDR:
4782 for (i = 0; i < reload_n_operands; i++)
4783 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4786 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4788 case RELOAD_FOR_OUTPUT:
4789 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4790 outputs, or an operand address for this or an earlier output. */
4791 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4794 for (i = 0; i < reload_n_operands; i++)
4795 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4798 for (i = 0; i <= opnum; i++)
4799 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4800 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4805 case RELOAD_FOR_INSN:
4806 for (i = 0; i < reload_n_operands; i++)
4807 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4808 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4811 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4812 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4814 case RELOAD_FOR_OTHER_ADDRESS:
4815 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4820 /* Return 1 if the value in reload reg REGNO, as used by a reload
4821 needed for the part of the insn specified by OPNUM and TYPE,
4822 is not in use for a reload in any prior part of the insn.
4824 We can assume that the reload reg was already tested for availability
4825 at the time it is needed, and we should not check this again,
4826 in case the reg has already been marked in use.
4828 However, if EQUIV is set, we are checking the availability of a register
4829 holding an equivalence to the value to be loaded into the reload register,
4830 not the availability of the reload register itself.
4832 This is still less stringent than what reload_reg_free_p checks; for
4833 example, compare the checks for RELOAD_OTHER. */
4836 reload_reg_free_before_p (regno, opnum, type, equiv)
4839 enum reload_type type;
4844 /* The code to handle EQUIV below is wrong.
4846 If we wnat to know if a value in a particular reload register is available
4847 at a particular point in time during reloading, we must check *all*
4848 prior reloads to see if they clobber the value.
4850 Note this is significantly different from determining when a register is
4851 free for usage in a reload!
4853 This change is temporary. It will go away. */
4859 case RELOAD_FOR_OTHER_ADDRESS:
4860 /* These always come first. */
4861 if (equiv && TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno))
4866 if (equiv && TEST_HARD_REG_BIT (reload_reg_used, regno))
4868 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4870 /* If this use is for part of the insn,
4871 check the reg is not in use for any prior part. It is tempting
4872 to try to do this by falling through from objecs that occur
4873 later in the insn to ones that occur earlier, but that will not
4874 correctly take into account the fact that here we MUST ignore
4875 things that would prevent the register from being allocated in
4876 the first place, since we know that it was allocated. */
4878 case RELOAD_FOR_OUTPUT_ADDRESS:
4880 && TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4882 /* Earlier reloads include RELOAD_FOR_OUTADDR_ADDRESS reloads. */
4883 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4885 /* ... fall through ... */
4886 case RELOAD_FOR_OUTADDR_ADDRESS:
4888 && (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno)
4889 || TEST_HARD_REG_BIT (reload_reg_used, regno)))
4891 /* Earlier reloads are for earlier outputs or their addresses,
4892 any RELOAD_FOR_INSN reloads, any inputs or their addresses, or any
4893 RELOAD_FOR_OTHER_ADDRESS reloads (we know it can't conflict with
4895 for (i = 0; i < opnum; i++)
4896 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4897 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4900 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4903 for (i = 0; i < reload_n_operands; i++)
4904 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4905 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4906 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4907 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4910 return (! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4911 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4912 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4913 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4915 case RELOAD_FOR_OUTPUT:
4916 case RELOAD_FOR_INSN:
4917 /* There is no reason to call this function for output reloads, thus
4918 anything we'd put here wouldn't be tested. So just abort. */
4921 case RELOAD_FOR_OPERAND_ADDRESS:
4922 if (equiv && TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4925 /* Earlier reloads include RELOAD_FOR_OPADDR_ADDR reloads. */
4926 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4929 /* ... fall through ... */
4931 case RELOAD_FOR_OPADDR_ADDR:
4934 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4935 || TEST_HARD_REG_BIT (reload_reg_used, regno))
4937 for (i = 0; i < reload_n_operands; i++)
4938 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4941 /* These can't conflict with inputs, or each other, so all we have to
4942 test is input addresses and the addresses of OTHER items. */
4944 for (i = 0; i < reload_n_operands; i++)
4945 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4946 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4949 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4951 case RELOAD_FOR_INPUT:
4952 if (equiv && TEST_HARD_REG_BIT (reload_reg_used, regno))
4955 /* The only things earlier are the address for this and
4956 earlier inputs, other inputs (which we know we don't conflict
4957 with), and addresses of RELOAD_OTHER objects.
4958 We can ignore the conflict with addresses of this operand, since
4959 when we inherit this operand, its address reloads are discarded. */
4961 for (i = 0; i < opnum; i++)
4962 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4963 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4966 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4968 case RELOAD_FOR_INPUT_ADDRESS:
4969 /* Earlier reloads include RELOAD_FOR_INPADDR_ADDRESS reloads. */
4970 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4972 /* ... fall through ... */
4973 case RELOAD_FOR_INPADDR_ADDRESS:
4974 if (equiv && TEST_HARD_REG_BIT (reload_reg_used, regno))
4977 /* Similarly, all we have to check is for use in earlier inputs'
4979 for (i = 0; i < opnum; i++)
4980 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4981 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4984 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4989 /* Return 1 if the value in reload reg REGNO, as used by a reload
4990 needed for the part of the insn specified by OPNUM and TYPE,
4991 is still available in REGNO at the end of the insn.
4993 We can assume that the reload reg was already tested for availability
4994 at the time it is needed, and we should not check this again,
4995 in case the reg has already been marked in use. */
4998 reload_reg_reaches_end_p (regno, opnum, type)
5001 enum reload_type type;
5008 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5009 its value must reach the end. */
5012 /* If this use is for part of the insn,
5013 its value reaches if no subsequent part uses the same register.
5014 Just like the above function, don't try to do this with lots
5017 case RELOAD_FOR_OTHER_ADDRESS:
5018 /* Here we check for everything else, since these don't conflict
5019 with anything else and everything comes later. */
5021 for (i = 0; i < reload_n_operands; i++)
5022 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5023 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5024 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
5025 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5026 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5027 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5030 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5031 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5032 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5034 case RELOAD_FOR_INPUT_ADDRESS:
5035 case RELOAD_FOR_INPADDR_ADDRESS:
5036 /* Similar, except that we check only for this and subsequent inputs
5037 and the address of only subsequent inputs and we do not need
5038 to check for RELOAD_OTHER objects since they are known not to
5041 for (i = opnum; i < reload_n_operands; i++)
5042 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5045 for (i = opnum + 1; i < reload_n_operands; i++)
5046 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5047 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5050 for (i = 0; i < reload_n_operands; i++)
5051 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5052 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5053 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5056 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5059 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5060 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
5062 case RELOAD_FOR_INPUT:
5063 /* Similar to input address, except we start at the next operand for
5064 both input and input address and we do not check for
5065 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5068 for (i = opnum + 1; i < reload_n_operands; i++)
5069 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5070 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5071 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5074 /* ... fall through ... */
5076 case RELOAD_FOR_OPERAND_ADDRESS:
5077 /* Check outputs and their addresses. */
5079 for (i = 0; i < reload_n_operands; i++)
5080 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5081 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5082 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5087 case RELOAD_FOR_OPADDR_ADDR:
5088 for (i = 0; i < reload_n_operands; i++)
5089 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5090 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5091 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5094 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5095 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
5097 case RELOAD_FOR_INSN:
5098 /* These conflict with other outputs with RELOAD_OTHER. So
5099 we need only check for output addresses. */
5103 /* ... fall through ... */
5105 case RELOAD_FOR_OUTPUT:
5106 case RELOAD_FOR_OUTPUT_ADDRESS:
5107 case RELOAD_FOR_OUTADDR_ADDRESS:
5108 /* We already know these can't conflict with a later output. So the
5109 only thing to check are later output addresses. */
5110 for (i = opnum + 1; i < reload_n_operands; i++)
5111 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5112 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5121 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5124 This function uses the same algorithm as reload_reg_free_p above. */
5127 reloads_conflict (r1, r2)
5130 enum reload_type r1_type = reload_when_needed[r1];
5131 enum reload_type r2_type = reload_when_needed[r2];
5132 int r1_opnum = reload_opnum[r1];
5133 int r2_opnum = reload_opnum[r2];
5135 /* RELOAD_OTHER conflicts with everything. */
5136 if (r2_type == RELOAD_OTHER)
5139 /* Otherwise, check conflicts differently for each type. */
5143 case RELOAD_FOR_INPUT:
5144 return (r2_type == RELOAD_FOR_INSN
5145 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5146 || r2_type == RELOAD_FOR_OPADDR_ADDR
5147 || r2_type == RELOAD_FOR_INPUT
5148 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5149 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5150 && r2_opnum > r1_opnum));
5152 case RELOAD_FOR_INPUT_ADDRESS:
5153 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5154 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5156 case RELOAD_FOR_INPADDR_ADDRESS:
5157 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5158 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5160 case RELOAD_FOR_OUTPUT_ADDRESS:
5161 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5162 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
5164 case RELOAD_FOR_OUTADDR_ADDRESS:
5165 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5166 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
5168 case RELOAD_FOR_OPERAND_ADDRESS:
5169 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5170 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5172 case RELOAD_FOR_OPADDR_ADDR:
5173 return (r2_type == RELOAD_FOR_INPUT
5174 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5176 case RELOAD_FOR_OUTPUT:
5177 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5178 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5179 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5180 && r2_opnum >= r1_opnum));
5182 case RELOAD_FOR_INSN:
5183 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5184 || r2_type == RELOAD_FOR_INSN
5185 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5187 case RELOAD_FOR_OTHER_ADDRESS:
5188 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5198 /* Vector of reload-numbers showing the order in which the reloads should
5200 short reload_order[MAX_RELOADS];
5202 /* Indexed by reload number, 1 if incoming value
5203 inherited from previous insns. */
5204 char reload_inherited[MAX_RELOADS];
5206 /* For an inherited reload, this is the insn the reload was inherited from,
5207 if we know it. Otherwise, this is 0. */
5208 rtx reload_inheritance_insn[MAX_RELOADS];
5210 /* If non-zero, this is a place to get the value of the reload,
5211 rather than using reload_in. */
5212 rtx reload_override_in[MAX_RELOADS];
5214 /* For each reload, the hard register number of the register used,
5215 or -1 if we did not need a register for this reload. */
5216 int reload_spill_index[MAX_RELOADS];
5218 /* Return 1 if the value in reload reg REGNO, as used by a reload
5219 needed for the part of the insn specified by OPNUM and TYPE,
5220 may be used to load VALUE into it.
5222 Other read-only reloads with the same value do not conflict
5223 unless OUT is non-zero and these other reloads have to live while
5224 output reloads live.
5226 RELOADNUM is the number of the reload we want to load this value for;
5227 a reload does not conflict with itself.
5229 The caller has to make sure that there is no conflict with the return
5232 reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum)
5235 enum reload_type type;
5242 /* We use some pseudo 'time' value to check if the lifetimes of the
5243 new register use would overlap with the one of a previous reload
5244 that is not read-only or uses a different value.
5245 The 'time' used doesn't have to be linear in any shape or form, just
5247 Some reload types use different 'buckets' for each operand.
5248 So there are MAX_RECOG_OPERANDS different time values for each
5250 We compute TIME1 as the time when the register for the prospective
5251 new reload ceases to be live, and TIME2 for each existing
5252 reload as the time when that the reload register of that reload
5254 Where there is little to be gained by exact lifetime calculations,
5255 we just make conservative assumptions, i.e. a longer lifetime;
5256 this is done in the 'default:' cases. */
5259 case RELOAD_FOR_OTHER_ADDRESS:
5262 /* For each input, we might have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5263 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5264 respectively, to the time values for these, we get distinct time
5265 values. To get distinct time values for each operand, we have to
5266 multiply opnum by at least three. We round that up to four because
5267 multiply by four is often cheaper. */
5268 case RELOAD_FOR_INPADDR_ADDRESS:
5269 time1 = opnum * 4 + 1;
5271 case RELOAD_FOR_INPUT_ADDRESS:
5272 time1 = opnum * 4 + 2;
5274 case RELOAD_FOR_OPADDR_ADDR:
5275 /* opnum * 4 + 3 < opnum * 4 + 4
5276 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5277 time1 = MAX_RECOG_OPERANDS * 4;
5279 case RELOAD_FOR_INPUT:
5280 /* All RELOAD_FOR_INPUT reloads remain live till just before the
5281 instruction is executed. */
5282 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5284 case RELOAD_FOR_OPERAND_ADDRESS:
5285 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5287 time1 = MAX_RECOG_OPERANDS * 4 + 2;
5289 case RELOAD_FOR_OUTPUT_ADDRESS:
5290 time1 = MAX_RECOG_OPERANDS * 4 + 3 + opnum;
5293 time1 = MAX_RECOG_OPERANDS * 5 + 3;
5296 for (i = 0; i < n_reloads; i++)
5298 rtx reg = reload_reg_rtx[i];
5299 if (reg && GET_CODE (reg) == REG
5300 && ((unsigned) regno - true_regnum (reg)
5301 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
5305 && reload_when_needed[i] != RELOAD_FOR_INPUT
5306 && reload_when_needed[i] != RELOAD_FOR_INPUT_ADDRESS
5307 && reload_when_needed[i] != RELOAD_FOR_INPADDR_ADDRESS)
5309 if (! reload_in[i] || ! rtx_equal_p (reload_in[i], value)
5313 switch (reload_when_needed[i])
5315 case RELOAD_FOR_OTHER_ADDRESS:
5318 case RELOAD_FOR_INPADDR_ADDRESS:
5319 /* find_reloads makes sure that a
5320 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5321 by at most one - the first -
5322 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5323 address reload is inherited, the address address reload
5324 goes away, so we can ignore this conflict. */
5325 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1)
5327 time2 = reload_opnum[i] * 4 + 1;
5329 case RELOAD_FOR_INPUT_ADDRESS:
5330 time2 = reload_opnum[i] * 4 + 2;
5332 case RELOAD_FOR_INPUT:
5333 time2 = reload_opnum[i] * 4 + 3;
5335 case RELOAD_FOR_OPADDR_ADDR:
5336 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1)
5338 time2 = MAX_RECOG_OPERANDS * 4;
5340 case RELOAD_FOR_OPERAND_ADDRESS:
5341 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5343 case RELOAD_FOR_OUTPUT:
5344 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5345 instruction is executed. */
5346 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5348 case RELOAD_FOR_OUTADDR_ADDRESS:
5349 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1)
5352 /* The first RELOAD_FOR_OUTPUT_ADDRESS reload conflicts with the
5353 RELOAD_FOR_OUTPUT reloads, so assign it the same time value. */
5354 case RELOAD_FOR_OUTPUT_ADDRESS:
5355 time2 = MAX_RECOG_OPERANDS * 4 + 3 + reload_opnum[i];
5358 if (! reload_in[i] || rtx_equal_p (reload_in[i], value))
5360 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5374 /* Find a spill register to use as a reload register for reload R.
5375 LAST_RELOAD is non-zero if this is the last reload for the insn being
5378 Set reload_reg_rtx[R] to the register allocated.
5380 If NOERROR is nonzero, we return 1 if successful,
5381 or 0 if we couldn't find a spill reg and we didn't change anything. */
5384 allocate_reload_reg (chain, r, last_reload, noerror)
5385 struct insn_chain *chain;
5390 rtx insn = chain->insn;
5391 int i, pass, count, regno;
5394 /* If we put this reload ahead, thinking it is a group,
5395 then insist on finding a group. Otherwise we can grab a
5396 reg that some other reload needs.
5397 (That can happen when we have a 68000 DATA_OR_FP_REG
5398 which is a group of data regs or one fp reg.)
5399 We need not be so restrictive if there are no more reloads
5402 ??? Really it would be nicer to have smarter handling
5403 for that kind of reg class, where a problem like this is normal.
5404 Perhaps those classes should be avoided for reloading
5405 by use of more alternatives. */
5407 int force_group = reload_nregs[r] > 1 && ! last_reload;
5409 /* If we want a single register and haven't yet found one,
5410 take any reg in the right class and not in use.
5411 If we want a consecutive group, here is where we look for it.
5413 We use two passes so we can first look for reload regs to
5414 reuse, which are already in use for other reloads in this insn,
5415 and only then use additional registers.
5416 I think that maximizing reuse is needed to make sure we don't
5417 run out of reload regs. Suppose we have three reloads, and
5418 reloads A and B can share regs. These need two regs.
5419 Suppose A and B are given different regs.
5420 That leaves none for C. */
5421 for (pass = 0; pass < 2; pass++)
5423 /* I is the index in spill_regs.
5424 We advance it round-robin between insns to use all spill regs
5425 equally, so that inherited reloads have a chance
5426 of leapfrogging each other. Don't do this, however, when we have
5427 group needs and failure would be fatal; if we only have a relatively
5428 small number of spill registers, and more than one of them has
5429 group needs, then by starting in the middle, we may end up
5430 allocating the first one in such a way that we are not left with
5431 sufficient groups to handle the rest. */
5433 if (noerror || ! force_group)
5438 for (count = 0; count < n_spills; count++)
5440 int class = (int) reload_reg_class[r];
5446 regnum = spill_regs[i];
5448 if ((reload_reg_free_p (regnum, reload_opnum[r],
5449 reload_when_needed[r])
5451 /* We check reload_reg_used to make sure we
5452 don't clobber the return register. */
5453 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5454 && reload_reg_free_for_value_p (regnum,
5456 reload_when_needed[r],
5459 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5460 && HARD_REGNO_MODE_OK (regnum, reload_mode[r])
5461 /* Look first for regs to share, then for unshared. But
5462 don't share regs used for inherited reloads; they are
5463 the ones we want to preserve. */
5465 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5467 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5470 int nr = HARD_REGNO_NREGS (regnum, reload_mode[r]);
5471 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5472 (on 68000) got us two FP regs. If NR is 1,
5473 we would reject both of them. */
5475 nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
5476 /* If we need only one reg, we have already won. */
5479 /* But reject a single reg if we demand a group. */
5484 /* Otherwise check that as many consecutive regs as we need
5486 Also, don't use for a group registers that are
5487 needed for nongroups. */
5488 if (! TEST_HARD_REG_BIT (chain->counted_for_nongroups, regnum))
5491 regno = regnum + nr - 1;
5492 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5493 && spill_reg_order[regno] >= 0
5494 && reload_reg_free_p (regno, reload_opnum[r],
5495 reload_when_needed[r])
5496 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups,
5506 /* If we found something on pass 1, omit pass 2. */
5507 if (count < n_spills)
5511 /* We should have found a spill register by now. */
5512 if (count == n_spills)
5519 /* I is the index in SPILL_REG_RTX of the reload register we are to
5520 allocate. Get an rtx for it and find its register number. */
5522 new = spill_reg_rtx[i];
5524 if (new == 0 || GET_MODE (new) != reload_mode[r])
5525 spill_reg_rtx[i] = new
5526 = gen_rtx_REG (reload_mode[r], spill_regs[i]);
5528 regno = true_regnum (new);
5530 /* Detect when the reload reg can't hold the reload mode.
5531 This used to be one `if', but Sequent compiler can't handle that. */
5532 if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5534 enum machine_mode test_mode = VOIDmode;
5536 test_mode = GET_MODE (reload_in[r]);
5537 /* If reload_in[r] has VOIDmode, it means we will load it
5538 in whatever mode the reload reg has: to wit, reload_mode[r].
5539 We have already tested that for validity. */
5540 /* Aside from that, we need to test that the expressions
5541 to reload from or into have modes which are valid for this
5542 reload register. Otherwise the reload insns would be invalid. */
5543 if (! (reload_in[r] != 0 && test_mode != VOIDmode
5544 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5545 if (! (reload_out[r] != 0
5546 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
5548 /* The reg is OK. */
5551 /* Mark as in use for this insn the reload regs we use
5553 mark_reload_reg_in_use (spill_regs[i], reload_opnum[r],
5554 reload_when_needed[r], reload_mode[r]);
5556 reload_reg_rtx[r] = new;
5557 reload_spill_index[r] = spill_regs[i];
5562 /* The reg is not OK. */
5567 if (asm_noperands (PATTERN (insn)) < 0)
5568 /* It's the compiler's fault. */
5569 fatal_insn ("Could not find a spill register", insn);
5571 /* It's the user's fault; the operand's mode and constraint
5572 don't match. Disable this reload so we don't crash in final. */
5573 error_for_asm (insn,
5574 "`asm' operand constraint incompatible with operand size");
5577 reload_reg_rtx[r] = 0;
5578 reload_optional[r] = 1;
5579 reload_secondary_p[r] = 1;
5584 /* Assign hard reg targets for the pseudo-registers we must reload
5585 into hard regs for this insn.
5586 Also output the instructions to copy them in and out of the hard regs.
5588 For machines with register classes, we are responsible for
5589 finding a reload reg in the proper class. */
5592 choose_reload_regs (chain)
5593 struct insn_chain *chain;
5595 rtx insn = chain->insn;
5597 int max_group_size = 1;
5598 enum reg_class group_class = NO_REGS;
5602 rtx save_reload_reg_rtx[MAX_RELOADS];
5603 char save_reload_inherited[MAX_RELOADS];
5604 rtx save_reload_inheritance_insn[MAX_RELOADS];
5605 rtx save_reload_override_in[MAX_RELOADS];
5606 int save_reload_spill_index[MAX_RELOADS];
5607 HARD_REG_SET save_reload_reg_used;
5608 HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
5609 HARD_REG_SET save_reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
5610 HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
5611 HARD_REG_SET save_reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
5612 HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS];
5613 HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS];
5614 HARD_REG_SET save_reload_reg_used_in_op_addr;
5615 HARD_REG_SET save_reload_reg_used_in_op_addr_reload;
5616 HARD_REG_SET save_reload_reg_used_in_insn;
5617 HARD_REG_SET save_reload_reg_used_in_other_addr;
5618 HARD_REG_SET save_reload_reg_used_at_all;
5620 bzero (reload_inherited, MAX_RELOADS);
5621 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5622 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5624 CLEAR_HARD_REG_SET (reload_reg_used);
5625 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5626 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5627 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5628 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5629 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5631 CLEAR_HARD_REG_SET (reg_used_by_pseudo);
5632 compute_use_by_pseudos (®_used_by_pseudo, chain->live_before);
5633 compute_use_by_pseudos (®_used_by_pseudo, chain->live_after);
5635 for (i = 0; i < reload_n_operands; i++)
5637 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5638 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5639 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5640 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5641 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5642 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5645 IOR_COMPL_HARD_REG_SET (reload_reg_used, chain->used_spill_regs);
5647 #if 0 /* Not needed, now that we can always retry without inheritance. */
5648 /* See if we have more mandatory reloads than spill regs.
5649 If so, then we cannot risk optimizations that could prevent
5650 reloads from sharing one spill register.
5652 Since we will try finding a better register than reload_reg_rtx
5653 unless it is equal to reload_in or reload_out, count such reloads. */
5657 for (j = 0; j < n_reloads; j++)
5658 if (! reload_optional[j]
5659 && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
5660 && (reload_reg_rtx[j] == 0
5661 || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
5662 && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
5669 /* In order to be certain of getting the registers we need,
5670 we must sort the reloads into order of increasing register class.
5671 Then our grabbing of reload registers will parallel the process
5672 that provided the reload registers.
5674 Also note whether any of the reloads wants a consecutive group of regs.
5675 If so, record the maximum size of the group desired and what
5676 register class contains all the groups needed by this insn. */
5678 for (j = 0; j < n_reloads; j++)
5680 reload_order[j] = j;
5681 reload_spill_index[j] = -1;
5684 = (reload_inmode[j] == VOIDmode
5685 || (GET_MODE_SIZE (reload_outmode[j])
5686 > GET_MODE_SIZE (reload_inmode[j])))
5687 ? reload_outmode[j] : reload_inmode[j];
5689 reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
5691 if (reload_nregs[j] > 1)
5693 max_group_size = MAX (reload_nregs[j], max_group_size);
5694 group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
5697 /* If we have already decided to use a certain register,
5698 don't use it in another way. */
5699 if (reload_reg_rtx[j])
5700 mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j],
5701 reload_when_needed[j], reload_mode[j]);
5705 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5707 bcopy ((char *) reload_reg_rtx, (char *) save_reload_reg_rtx,
5708 sizeof reload_reg_rtx);
5709 bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
5710 bcopy ((char *) reload_inheritance_insn,
5711 (char *) save_reload_inheritance_insn,
5712 sizeof reload_inheritance_insn);
5713 bcopy ((char *) reload_override_in, (char *) save_reload_override_in,
5714 sizeof reload_override_in);
5715 bcopy ((char *) reload_spill_index, (char *) save_reload_spill_index,
5716 sizeof reload_spill_index);
5717 COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
5718 COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
5719 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
5720 reload_reg_used_in_op_addr);
5722 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr_reload,
5723 reload_reg_used_in_op_addr_reload);
5725 COPY_HARD_REG_SET (save_reload_reg_used_in_insn,
5726 reload_reg_used_in_insn);
5727 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr,
5728 reload_reg_used_in_other_addr);
5730 for (i = 0; i < reload_n_operands; i++)
5732 COPY_HARD_REG_SET (save_reload_reg_used_in_output[i],
5733 reload_reg_used_in_output[i]);
5734 COPY_HARD_REG_SET (save_reload_reg_used_in_input[i],
5735 reload_reg_used_in_input[i]);
5736 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i],
5737 reload_reg_used_in_input_addr[i]);
5738 COPY_HARD_REG_SET (save_reload_reg_used_in_inpaddr_addr[i],
5739 reload_reg_used_in_inpaddr_addr[i]);
5740 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i],
5741 reload_reg_used_in_output_addr[i]);
5742 COPY_HARD_REG_SET (save_reload_reg_used_in_outaddr_addr[i],
5743 reload_reg_used_in_outaddr_addr[i]);
5746 /* If -O, try first with inheritance, then turning it off.
5747 If not -O, don't do inheritance.
5748 Using inheritance when not optimizing leads to paradoxes
5749 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5750 because one side of the comparison might be inherited. */
5752 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5754 /* Process the reloads in order of preference just found.
5755 Beyond this point, subregs can be found in reload_reg_rtx.
5757 This used to look for an existing reloaded home for all
5758 of the reloads, and only then perform any new reloads.
5759 But that could lose if the reloads were done out of reg-class order
5760 because a later reload with a looser constraint might have an old
5761 home in a register needed by an earlier reload with a tighter constraint.
5763 To solve this, we make two passes over the reloads, in the order
5764 described above. In the first pass we try to inherit a reload
5765 from a previous insn. If there is a later reload that needs a
5766 class that is a proper subset of the class being processed, we must
5767 also allocate a spill register during the first pass.
5769 Then make a second pass over the reloads to allocate any reloads
5770 that haven't been given registers yet. */
5772 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5774 for (j = 0; j < n_reloads; j++)
5776 register int r = reload_order[j];
5778 /* Ignore reloads that got marked inoperative. */
5779 if (reload_out[r] == 0 && reload_in[r] == 0
5780 && ! reload_secondary_p[r])
5783 /* If find_reloads chose to use reload_in or reload_out as a reload
5784 register, we don't need to chose one. Otherwise, try even if it
5785 found one since we might save an insn if we find the value lying
5787 Try also when reload_in is a pseudo without a hard reg. */
5788 if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
5789 && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
5790 || (rtx_equal_p (reload_out[r], reload_reg_rtx[r])
5791 && GET_CODE (reload_in[r]) != MEM
5792 && true_regnum (reload_in[r]) < FIRST_PSEUDO_REGISTER)))
5795 #if 0 /* No longer needed for correct operation.
5796 It might give better code, or might not; worth an experiment? */
5797 /* If this is an optional reload, we can't inherit from earlier insns
5798 until we are sure that any non-optional reloads have been allocated.
5799 The following code takes advantage of the fact that optional reloads
5800 are at the end of reload_order. */
5801 if (reload_optional[r] != 0)
5802 for (i = 0; i < j; i++)
5803 if ((reload_out[reload_order[i]] != 0
5804 || reload_in[reload_order[i]] != 0
5805 || reload_secondary_p[reload_order[i]])
5806 && ! reload_optional[reload_order[i]]
5807 && reload_reg_rtx[reload_order[i]] == 0)
5808 allocate_reload_reg (chain, reload_order[i], 0, inheritance);
5811 /* First see if this pseudo is already available as reloaded
5812 for a previous insn. We cannot try to inherit for reloads
5813 that are smaller than the maximum number of registers needed
5814 for groups unless the register we would allocate cannot be used
5817 We could check here to see if this is a secondary reload for
5818 an object that is already in a register of the desired class.
5819 This would avoid the need for the secondary reload register.
5820 But this is complex because we can't easily determine what
5821 objects might want to be loaded via this reload. So let a
5822 register be allocated here. In `emit_reload_insns' we suppress
5823 one of the loads in the case described above. */
5828 register int regno = -1;
5829 enum machine_mode mode;
5831 if (reload_in[r] == 0)
5833 else if (GET_CODE (reload_in[r]) == REG)
5835 regno = REGNO (reload_in[r]);
5836 mode = GET_MODE (reload_in[r]);
5838 else if (GET_CODE (reload_in_reg[r]) == REG)
5840 regno = REGNO (reload_in_reg[r]);
5841 mode = GET_MODE (reload_in_reg[r]);
5843 else if (GET_CODE (reload_in_reg[r]) == SUBREG
5844 && GET_CODE (SUBREG_REG (reload_in_reg[r])) == REG)
5846 word = SUBREG_WORD (reload_in_reg[r]);
5847 regno = REGNO (SUBREG_REG (reload_in_reg[r]));
5848 if (regno < FIRST_PSEUDO_REGISTER)
5850 mode = GET_MODE (reload_in_reg[r]);
5853 else if ((GET_CODE (reload_in_reg[r]) == PRE_INC
5854 || GET_CODE (reload_in_reg[r]) == PRE_DEC
5855 || GET_CODE (reload_in_reg[r]) == POST_INC
5856 || GET_CODE (reload_in_reg[r]) == POST_DEC)
5857 && GET_CODE (XEXP (reload_in_reg[r], 0)) == REG)
5859 regno = REGNO (XEXP (reload_in_reg[r], 0));
5860 mode = GET_MODE (XEXP (reload_in_reg[r], 0));
5861 reload_out[r] = reload_in[r];
5865 /* This won't work, since REGNO can be a pseudo reg number.
5866 Also, it takes much more hair to keep track of all the things
5867 that can invalidate an inherited reload of part of a pseudoreg. */
5868 else if (GET_CODE (reload_in[r]) == SUBREG
5869 && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
5870 regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
5873 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5875 enum reg_class class = reload_reg_class[r], last_class;
5876 rtx last_reg = reg_last_reload_reg[regno];
5878 i = REGNO (last_reg) + word;
5879 last_class = REGNO_REG_CLASS (i);
5880 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5881 >= GET_MODE_SIZE (mode) + word * UNITS_PER_WORD)
5882 && reg_reloaded_contents[i] == regno
5883 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5884 && HARD_REGNO_MODE_OK (i, reload_mode[r])
5885 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5886 /* Even if we can't use this register as a reload
5887 register, we might use it for reload_override_in,
5888 if copying it to the desired class is cheap
5890 || ((REGISTER_MOVE_COST (last_class, class)
5891 < MEMORY_MOVE_COST (mode, class, 1))
5892 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5893 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5897 #ifdef SECONDARY_MEMORY_NEEDED
5898 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5903 && (reload_nregs[r] == max_group_size
5904 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5906 && ((reload_reg_free_p (i, reload_opnum[r],
5907 reload_when_needed[r])
5908 && reload_reg_free_before_p (i, reload_opnum[r],
5909 reload_when_needed[r],
5911 || reload_reg_free_for_value_p (i, reload_opnum[r],
5912 reload_when_needed[r],
5916 /* If a group is needed, verify that all the subsequent
5917 registers still have their values intact. */
5919 = HARD_REGNO_NREGS (i, reload_mode[r]);
5922 for (k = 1; k < nr; k++)
5923 if (reg_reloaded_contents[i + k] != regno
5924 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5931 last_reg = (GET_MODE (last_reg) == mode
5932 ? last_reg : gen_rtx_REG (mode, i));
5934 /* We found a register that contains the
5935 value we need. If this register is the
5936 same as an `earlyclobber' operand of the
5937 current insn, just mark it as a place to
5938 reload from since we can't use it as the
5939 reload register itself. */
5941 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5942 if (reg_overlap_mentioned_for_reload_p
5943 (reg_last_reload_reg[regno],
5944 reload_earlyclobbers[i1]))
5947 if (i1 != n_earlyclobbers
5948 /* Don't use it if we'd clobber a pseudo reg. */
5949 || (TEST_HARD_REG_BIT (reg_used_by_pseudo, i)
5951 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5952 /* Don't really use the inherited spill reg
5953 if we need it wider than we've got it. */
5954 || (GET_MODE_SIZE (reload_mode[r])
5955 > GET_MODE_SIZE (mode))
5956 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5959 /* If find_reloads chose reload_out as reload
5960 register, stay with it - that leaves the
5961 inherited register for subsequent reloads. */
5962 || (reload_out[r] && reload_reg_rtx[r]
5963 && rtx_equal_p (reload_out[r],
5964 reload_reg_rtx[r])))
5966 reload_override_in[r] = last_reg;
5967 reload_inheritance_insn[r]
5968 = reg_reloaded_insn[i];
5973 /* We can use this as a reload reg. */
5974 /* Mark the register as in use for this part of
5976 mark_reload_reg_in_use (i,
5978 reload_when_needed[r],
5980 reload_reg_rtx[r] = last_reg;
5981 reload_inherited[r] = 1;
5982 reload_inheritance_insn[r]
5983 = reg_reloaded_insn[i];
5984 reload_spill_index[r] = i;
5985 for (k = 0; k < nr; k++)
5986 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5994 /* Here's another way to see if the value is already lying around. */
5996 && reload_in[r] != 0
5997 && ! reload_inherited[r]
5998 && reload_out[r] == 0
5999 && (CONSTANT_P (reload_in[r])
6000 || GET_CODE (reload_in[r]) == PLUS
6001 || GET_CODE (reload_in[r]) == REG
6002 || GET_CODE (reload_in[r]) == MEM)
6003 && (reload_nregs[r] == max_group_size
6004 || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
6007 = find_equiv_reg (reload_in[r], insn, reload_reg_class[r],
6008 -1, NULL_PTR, 0, reload_mode[r]);
6013 if (GET_CODE (equiv) == REG)
6014 regno = REGNO (equiv);
6015 else if (GET_CODE (equiv) == SUBREG)
6017 /* This must be a SUBREG of a hard register.
6018 Make a new REG since this might be used in an
6019 address and not all machines support SUBREGs
6021 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
6022 equiv = gen_rtx_REG (reload_mode[r], regno);
6028 /* If we found a spill reg, reject it unless it is free
6029 and of the desired class. */
6031 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
6032 && ! reload_reg_free_for_value_p (regno, reload_opnum[r],
6033 reload_when_needed[r],
6036 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
6040 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
6043 /* We found a register that contains the value we need.
6044 If this register is the same as an `earlyclobber' operand
6045 of the current insn, just mark it as a place to reload from
6046 since we can't use it as the reload register itself. */
6049 for (i = 0; i < n_earlyclobbers; i++)
6050 if (reg_overlap_mentioned_for_reload_p (equiv,
6051 reload_earlyclobbers[i]))
6053 reload_override_in[r] = equiv;
6058 /* If the equiv register we have found is explicitly clobbered
6059 in the current insn, it depends on the reload type if we
6060 can use it, use it for reload_override_in, or not at all.
6061 In particular, we then can't use EQUIV for a
6062 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6064 if (equiv != 0 && regno_clobbered_p (regno, insn))
6066 switch (reload_when_needed[r])
6068 case RELOAD_FOR_OTHER_ADDRESS:
6069 case RELOAD_FOR_INPADDR_ADDRESS:
6070 case RELOAD_FOR_INPUT_ADDRESS:
6071 case RELOAD_FOR_OPADDR_ADDR:
6074 case RELOAD_FOR_INPUT:
6075 case RELOAD_FOR_OPERAND_ADDRESS:
6076 reload_override_in[r] = equiv;
6084 /* If we found an equivalent reg, say no code need be generated
6085 to load it, and use it as our reload reg. */
6086 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
6088 int nr = HARD_REGNO_NREGS (regno, reload_mode[r]);
6090 reload_reg_rtx[r] = equiv;
6091 reload_inherited[r] = 1;
6093 /* If reg_reloaded_valid is not set for this register,
6094 there might be a stale spill_reg_store lying around.
6095 We must clear it, since otherwise emit_reload_insns
6096 might delete the store. */
6097 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6098 spill_reg_store[regno] = NULL_RTX;
6099 /* If any of the hard registers in EQUIV are spill
6100 registers, mark them as in use for this insn. */
6101 for (k = 0; k < nr; k++)
6103 i = spill_reg_order[regno + k];
6106 mark_reload_reg_in_use (regno, reload_opnum[r],
6107 reload_when_needed[r],
6109 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6116 /* If we found a register to use already, or if this is an optional
6117 reload, we are done. */
6118 if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
6121 #if 0 /* No longer needed for correct operation. Might or might not
6122 give better code on the average. Want to experiment? */
6124 /* See if there is a later reload that has a class different from our
6125 class that intersects our class or that requires less register
6126 than our reload. If so, we must allocate a register to this
6127 reload now, since that reload might inherit a previous reload
6128 and take the only available register in our class. Don't do this
6129 for optional reloads since they will force all previous reloads
6130 to be allocated. Also don't do this for reloads that have been
6133 for (i = j + 1; i < n_reloads; i++)
6135 int s = reload_order[i];
6137 if ((reload_in[s] == 0 && reload_out[s] == 0
6138 && ! reload_secondary_p[s])
6139 || reload_optional[s])
6142 if ((reload_reg_class[s] != reload_reg_class[r]
6143 && reg_classes_intersect_p (reload_reg_class[r],
6144 reload_reg_class[s]))
6145 || reload_nregs[s] < reload_nregs[r])
6152 allocate_reload_reg (chain, r, j == n_reloads - 1, inheritance);
6156 /* Now allocate reload registers for anything non-optional that
6157 didn't get one yet. */
6158 for (j = 0; j < n_reloads; j++)
6160 register int r = reload_order[j];
6162 /* Ignore reloads that got marked inoperative. */
6163 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
6166 /* Skip reloads that already have a register allocated or are
6168 if (reload_reg_rtx[r] != 0 || reload_optional[r])
6171 if (! allocate_reload_reg (chain, r, j == n_reloads - 1, inheritance))
6175 /* If that loop got all the way, we have won. */
6179 /* Loop around and try without any inheritance. */
6180 /* First undo everything done by the failed attempt
6181 to allocate with inheritance. */
6182 bcopy ((char *) save_reload_reg_rtx, (char *) reload_reg_rtx,
6183 sizeof reload_reg_rtx);
6184 bcopy ((char *) save_reload_inherited, (char *) reload_inherited,
6185 sizeof reload_inherited);
6186 bcopy ((char *) save_reload_inheritance_insn,
6187 (char *) reload_inheritance_insn,
6188 sizeof reload_inheritance_insn);
6189 bcopy ((char *) save_reload_override_in, (char *) reload_override_in,
6190 sizeof reload_override_in);
6191 bcopy ((char *) save_reload_spill_index, (char *) reload_spill_index,
6192 sizeof reload_spill_index);
6193 COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
6194 COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
6195 COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
6196 save_reload_reg_used_in_op_addr);
6197 COPY_HARD_REG_SET (reload_reg_used_in_op_addr_reload,
6198 save_reload_reg_used_in_op_addr_reload);
6199 COPY_HARD_REG_SET (reload_reg_used_in_insn,
6200 save_reload_reg_used_in_insn);
6201 COPY_HARD_REG_SET (reload_reg_used_in_other_addr,
6202 save_reload_reg_used_in_other_addr);
6204 for (i = 0; i < reload_n_operands; i++)
6206 COPY_HARD_REG_SET (reload_reg_used_in_input[i],
6207 save_reload_reg_used_in_input[i]);
6208 COPY_HARD_REG_SET (reload_reg_used_in_output[i],
6209 save_reload_reg_used_in_output[i]);
6210 COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i],
6211 save_reload_reg_used_in_input_addr[i]);
6212 COPY_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i],
6213 save_reload_reg_used_in_inpaddr_addr[i]);
6214 COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i],
6215 save_reload_reg_used_in_output_addr[i]);
6216 COPY_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i],
6217 save_reload_reg_used_in_outaddr_addr[i]);
6221 /* If we thought we could inherit a reload, because it seemed that
6222 nothing else wanted the same reload register earlier in the insn,
6223 verify that assumption, now that all reloads have been assigned.
6224 Likewise for reloads where reload_override_in has been set. */
6226 /* If doing expensive optimizations, do one preliminary pass that doesn't
6227 cancel any inheritance, but removes reloads that have been needed only
6228 for reloads that we know can be inherited. */
6229 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6231 for (j = 0; j < n_reloads; j++)
6233 register int r = reload_order[j];
6235 if (reload_inherited[r] && reload_reg_rtx[r])
6236 check_reg = reload_reg_rtx[r];
6237 else if (reload_override_in[r]
6238 && (GET_CODE (reload_override_in[r]) == REG
6239 || GET_CODE (reload_override_in[r]) == SUBREG))
6240 check_reg = reload_override_in[r];
6243 if (! (reload_reg_free_before_p (true_regnum (check_reg),
6244 reload_opnum[r], reload_when_needed[r],
6245 ! reload_inherited[r])
6246 || reload_reg_free_for_value_p (true_regnum (check_reg),
6248 reload_when_needed[r],
6254 reload_inherited[r] = 0;
6255 reload_override_in[r] = 0;
6257 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6258 reload_override_in, then we do not need its related
6259 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6260 likewise for other reload types.
6261 We handle this by removing a reload when its only replacement
6262 is mentioned in reload_in of the reload we are going to inherit.
6263 A special case are auto_inc expressions; even if the input is
6264 inherited, we still need the address for the output. We can
6265 recognize them because they have RELOAD_OUT set but not
6267 If we suceeded removing some reload and we are doing a preliminary
6268 pass just to remove such reloads, make another pass, since the
6269 removal of one reload might allow us to inherit another one. */
6270 else if ((! reload_out[r] || reload_out_reg[r])
6271 && remove_address_replacements (reload_in[r]) && pass)
6276 /* Now that reload_override_in is known valid,
6277 actually override reload_in. */
6278 for (j = 0; j < n_reloads; j++)
6279 if (reload_override_in[j])
6280 reload_in[j] = reload_override_in[j];
6282 /* If this reload won't be done because it has been cancelled or is
6283 optional and not inherited, clear reload_reg_rtx so other
6284 routines (such as subst_reloads) don't get confused. */
6285 for (j = 0; j < n_reloads; j++)
6286 if (reload_reg_rtx[j] != 0
6287 && ((reload_optional[j] && ! reload_inherited[j])
6288 || (reload_in[j] == 0 && reload_out[j] == 0
6289 && ! reload_secondary_p[j])))
6291 int regno = true_regnum (reload_reg_rtx[j]);
6293 if (spill_reg_order[regno] >= 0)
6294 clear_reload_reg_in_use (regno, reload_opnum[j],
6295 reload_when_needed[j], reload_mode[j]);
6296 reload_reg_rtx[j] = 0;
6299 /* Record which pseudos and which spill regs have output reloads. */
6300 for (j = 0; j < n_reloads; j++)
6302 register int r = reload_order[j];
6304 i = reload_spill_index[r];
6306 /* I is nonneg if this reload uses a register.
6307 If reload_reg_rtx[r] is 0, this is an optional reload
6308 that we opted to ignore. */
6309 if (reload_out_reg[r] != 0 && GET_CODE (reload_out_reg[r]) == REG
6310 && reload_reg_rtx[r] != 0)
6312 register int nregno = REGNO (reload_out_reg[r]);
6315 if (nregno < FIRST_PSEUDO_REGISTER)
6316 nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
6319 reg_has_output_reload[nregno + nr] = 1;
6323 nr = HARD_REGNO_NREGS (i, reload_mode[r]);
6325 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6328 if (reload_when_needed[r] != RELOAD_OTHER
6329 && reload_when_needed[r] != RELOAD_FOR_OUTPUT
6330 && reload_when_needed[r] != RELOAD_FOR_INSN)
6336 /* Deallocate the reload register for reload R. This is called from
6337 remove_address_replacements. */
6339 deallocate_reload_reg (r)
6344 if (! reload_reg_rtx[r])
6346 regno = true_regnum (reload_reg_rtx[r]);
6347 reload_reg_rtx[r] = 0;
6348 if (spill_reg_order[regno] >= 0)
6349 clear_reload_reg_in_use (regno, reload_opnum[r], reload_when_needed[r],
6351 reload_spill_index[r] = -1;
6354 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
6355 reloads of the same item for fear that we might not have enough reload
6356 registers. However, normally they will get the same reload register
6357 and hence actually need not be loaded twice.
6359 Here we check for the most common case of this phenomenon: when we have
6360 a number of reloads for the same object, each of which were allocated
6361 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6362 reload, and is not modified in the insn itself. If we find such,
6363 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6364 This will not increase the number of spill registers needed and will
6365 prevent redundant code. */
6368 merge_assigned_reloads (insn)
6373 /* Scan all the reloads looking for ones that only load values and
6374 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6375 assigned and not modified by INSN. */
6377 for (i = 0; i < n_reloads; i++)
6379 int conflicting_input = 0;
6380 int max_input_address_opnum = -1;
6381 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6383 if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER
6384 || reload_out[i] != 0 || reload_reg_rtx[i] == 0
6385 || reg_set_p (reload_reg_rtx[i], insn))
6388 /* Look at all other reloads. Ensure that the only use of this
6389 reload_reg_rtx is in a reload that just loads the same value
6390 as we do. Note that any secondary reloads must be of the identical
6391 class since the values, modes, and result registers are the
6392 same, so we need not do anything with any secondary reloads. */
6394 for (j = 0; j < n_reloads; j++)
6396 if (i == j || reload_reg_rtx[j] == 0
6397 || ! reg_overlap_mentioned_p (reload_reg_rtx[j],
6401 if (reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS
6402 && reload_opnum[j] > max_input_address_opnum)
6403 max_input_address_opnum = reload_opnum[j];
6405 /* If the reload regs aren't exactly the same (e.g, different modes)
6406 or if the values are different, we can't merge this reload.
6407 But if it is an input reload, we might still merge
6408 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6410 if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
6411 || reload_out[j] != 0 || reload_in[j] == 0
6412 || ! rtx_equal_p (reload_in[i], reload_in[j]))
6414 if (reload_when_needed[j] != RELOAD_FOR_INPUT
6415 || ((reload_when_needed[i] != RELOAD_FOR_INPUT_ADDRESS
6416 || reload_opnum[i] > reload_opnum[j])
6417 && reload_when_needed[i] != RELOAD_FOR_OTHER_ADDRESS))
6419 conflicting_input = 1;
6420 if (min_conflicting_input_opnum > reload_opnum[j])
6421 min_conflicting_input_opnum = reload_opnum[j];
6425 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6426 we, in fact, found any matching reloads. */
6429 && max_input_address_opnum <= min_conflicting_input_opnum)
6431 for (j = 0; j < n_reloads; j++)
6432 if (i != j && reload_reg_rtx[j] != 0
6433 && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
6434 && (! conflicting_input
6435 || reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS
6436 || reload_when_needed[j] == RELOAD_FOR_OTHER_ADDRESS))
6438 reload_when_needed[i] = RELOAD_OTHER;
6440 reload_spill_index[j] = -1;
6441 transfer_replacements (i, j);
6444 /* If this is now RELOAD_OTHER, look for any reloads that load
6445 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6446 if they were for inputs, RELOAD_OTHER for outputs. Note that
6447 this test is equivalent to looking for reloads for this operand
6450 if (reload_when_needed[i] == RELOAD_OTHER)
6451 for (j = 0; j < n_reloads; j++)
6452 if (reload_in[j] != 0
6453 && reload_when_needed[i] != RELOAD_OTHER
6454 && reg_overlap_mentioned_for_reload_p (reload_in[j],
6456 reload_when_needed[j]
6457 = ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
6458 || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS)
6459 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6465 /* Output insns to reload values in and out of the chosen reload regs. */
6468 emit_reload_insns (chain)
6469 struct insn_chain *chain;
6471 rtx insn = chain->insn;
6474 rtx input_reload_insns[MAX_RECOG_OPERANDS];
6475 rtx other_input_address_reload_insns = 0;
6476 rtx other_input_reload_insns = 0;
6477 rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6478 rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6479 rtx output_reload_insns[MAX_RECOG_OPERANDS];
6480 rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6481 rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6482 rtx operand_reload_insns = 0;
6483 rtx other_operand_reload_insns = 0;
6484 rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6485 rtx following_insn = NEXT_INSN (insn);
6486 rtx before_insn = PREV_INSN (insn);
6488 /* Values to be put in spill_reg_store are put here first. */
6489 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6490 HARD_REG_SET reg_reloaded_died;
6492 CLEAR_HARD_REG_SET (reg_reloaded_died);
6494 for (j = 0; j < reload_n_operands; j++)
6495 input_reload_insns[j] = input_address_reload_insns[j]
6496 = inpaddr_address_reload_insns[j]
6497 = output_reload_insns[j] = output_address_reload_insns[j]
6498 = outaddr_address_reload_insns[j]
6499 = other_output_reload_insns[j] = 0;
6501 /* Now output the instructions to copy the data into and out of the
6502 reload registers. Do these in the order that the reloads were reported,
6503 since reloads of base and index registers precede reloads of operands
6504 and the operands may need the base and index registers reloaded. */
6506 for (j = 0; j < n_reloads; j++)
6509 rtx oldequiv_reg = 0;
6510 rtx this_reload_insn = 0;
6511 int expect_occurrences = 1;
6513 if (reload_reg_rtx[j]
6514 && REGNO (reload_reg_rtx[j]) < FIRST_PSEUDO_REGISTER)
6515 new_spill_reg_store[REGNO (reload_reg_rtx[j])] = 0;
6517 old = (reload_in[j] && GET_CODE (reload_in[j]) == MEM
6518 ? reload_in_reg[j] : reload_in[j]);
6521 /* AUTO_INC reloads need to be handled even if inherited. We got an
6522 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6523 && (! reload_inherited[j] || (reload_out[j] && ! reload_out_reg[j]))
6524 && ! rtx_equal_p (reload_reg_rtx[j], old)
6525 && reload_reg_rtx[j] != 0)
6527 register rtx reloadreg = reload_reg_rtx[j];
6529 enum machine_mode mode;
6532 /* Determine the mode to reload in.
6533 This is very tricky because we have three to choose from.
6534 There is the mode the insn operand wants (reload_inmode[J]).
6535 There is the mode of the reload register RELOADREG.
6536 There is the intrinsic mode of the operand, which we could find
6537 by stripping some SUBREGs.
6538 It turns out that RELOADREG's mode is irrelevant:
6539 we can change that arbitrarily.
6541 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6542 then the reload reg may not support QImode moves, so use SImode.
6543 If foo is in memory due to spilling a pseudo reg, this is safe,
6544 because the QImode value is in the least significant part of a
6545 slot big enough for a SImode. If foo is some other sort of
6546 memory reference, then it is impossible to reload this case,
6547 so previous passes had better make sure this never happens.
6549 Then consider a one-word union which has SImode and one of its
6550 members is a float, being fetched as (SUBREG:SF union:SI).
6551 We must fetch that as SFmode because we could be loading into
6552 a float-only register. In this case OLD's mode is correct.
6554 Consider an immediate integer: it has VOIDmode. Here we need
6555 to get a mode from something else.
6557 In some cases, there is a fourth mode, the operand's
6558 containing mode. If the insn specifies a containing mode for
6559 this operand, it overrides all others.
6561 I am not sure whether the algorithm here is always right,
6562 but it does the right things in those cases. */
6564 mode = GET_MODE (old);
6565 if (mode == VOIDmode)
6566 mode = reload_inmode[j];
6568 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6569 /* If we need a secondary register for this operation, see if
6570 the value is already in a register in that class. Don't
6571 do this if the secondary register will be used as a scratch
6574 if (reload_secondary_in_reload[j] >= 0
6575 && reload_secondary_in_icode[j] == CODE_FOR_nothing
6578 = find_equiv_reg (old, insn,
6579 reload_reg_class[reload_secondary_in_reload[j]],
6580 -1, NULL_PTR, 0, mode);
6583 /* If reloading from memory, see if there is a register
6584 that already holds the same value. If so, reload from there.
6585 We can pass 0 as the reload_reg_p argument because
6586 any other reload has either already been emitted,
6587 in which case find_equiv_reg will see the reload-insn,
6588 or has yet to be emitted, in which case it doesn't matter
6589 because we will use this equiv reg right away. */
6591 if (oldequiv == 0 && optimize
6592 && (GET_CODE (old) == MEM
6593 || (GET_CODE (old) == REG
6594 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6595 && reg_renumber[REGNO (old)] < 0)))
6596 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6597 -1, NULL_PTR, 0, mode);
6601 int regno = true_regnum (oldequiv);
6603 /* If OLDEQUIV is a spill register, don't use it for this
6604 if any other reload needs it at an earlier stage of this insn
6605 or at this stage. */
6606 if (spill_reg_order[regno] >= 0
6607 && (! reload_reg_free_p (regno, reload_opnum[j],
6608 reload_when_needed[j])
6609 || ! reload_reg_free_before_p (regno, reload_opnum[j],
6610 reload_when_needed[j], 1)))
6613 /* If OLDEQUIV is not a spill register,
6614 don't use it if any other reload wants it. */
6615 if (spill_reg_order[regno] < 0)
6618 for (k = 0; k < n_reloads; k++)
6619 if (reload_reg_rtx[k] != 0 && k != j
6620 && reg_overlap_mentioned_for_reload_p (reload_reg_rtx[k],
6628 /* If it is no cheaper to copy from OLDEQUIV into the
6629 reload register than it would be to move from memory,
6630 don't use it. Likewise, if we need a secondary register
6634 && ((REGNO_REG_CLASS (regno) != reload_reg_class[j]
6635 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
6636 reload_reg_class[j])
6637 >= MEMORY_MOVE_COST (mode, reload_reg_class[j], 1)))
6638 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6639 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6643 #ifdef SECONDARY_MEMORY_NEEDED
6644 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6645 reload_reg_class[j],
6652 /* delete_output_reload is only invoked properly if old contains
6653 the original pseudo register. Since this is replaced with a
6654 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6655 find the pseudo in RELOAD_IN_REG. */
6657 && reload_override_in[j]
6658 && GET_CODE (reload_in_reg[j]) == REG)
6661 old = reload_in_reg[j];
6665 else if (GET_CODE (oldequiv) == REG)
6666 oldequiv_reg = oldequiv;
6667 else if (GET_CODE (oldequiv) == SUBREG)
6668 oldequiv_reg = SUBREG_REG (oldequiv);
6670 /* If we are reloading from a register that was recently stored in
6671 with an output-reload, see if we can prove there was
6672 actually no need to store the old value in it. */
6674 if (optimize && GET_CODE (oldequiv) == REG
6675 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6676 && spill_reg_store[REGNO (oldequiv)]
6677 && GET_CODE (old) == REG
6678 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6679 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6680 reload_out_reg[j])))
6681 delete_output_reload (insn, j, REGNO (oldequiv));
6683 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6684 then load RELOADREG from OLDEQUIV. Note that we cannot use
6685 gen_lowpart_common since it can do the wrong thing when
6686 RELOADREG has a multi-word mode. Note that RELOADREG
6687 must always be a REG here. */
6689 if (GET_MODE (reloadreg) != mode)
6690 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6691 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6692 oldequiv = SUBREG_REG (oldequiv);
6693 if (GET_MODE (oldequiv) != VOIDmode
6694 && mode != GET_MODE (oldequiv))
6695 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6697 /* Switch to the right place to emit the reload insns. */
6698 switch (reload_when_needed[j])
6701 where = &other_input_reload_insns;
6703 case RELOAD_FOR_INPUT:
6704 where = &input_reload_insns[reload_opnum[j]];
6706 case RELOAD_FOR_INPUT_ADDRESS:
6707 where = &input_address_reload_insns[reload_opnum[j]];
6709 case RELOAD_FOR_INPADDR_ADDRESS:
6710 where = &inpaddr_address_reload_insns[reload_opnum[j]];
6712 case RELOAD_FOR_OUTPUT_ADDRESS:
6713 where = &output_address_reload_insns[reload_opnum[j]];
6715 case RELOAD_FOR_OUTADDR_ADDRESS:
6716 where = &outaddr_address_reload_insns[reload_opnum[j]];
6718 case RELOAD_FOR_OPERAND_ADDRESS:
6719 where = &operand_reload_insns;
6721 case RELOAD_FOR_OPADDR_ADDR:
6722 where = &other_operand_reload_insns;
6724 case RELOAD_FOR_OTHER_ADDRESS:
6725 where = &other_input_address_reload_insns;
6731 push_to_sequence (*where);
6734 /* Auto-increment addresses must be reloaded in a special way. */
6735 if (reload_out[j] && ! reload_out_reg[j])
6737 /* We are not going to bother supporting the case where a
6738 incremented register can't be copied directly from
6739 OLDEQUIV since this seems highly unlikely. */
6740 if (reload_secondary_in_reload[j] >= 0)
6743 if (reload_inherited[j])
6744 oldequiv = reloadreg;
6746 old = XEXP (reload_in_reg[j], 0);
6748 if (optimize && GET_CODE (oldequiv) == REG
6749 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6750 && spill_reg_store[REGNO (oldequiv)]
6751 && GET_CODE (old) == REG
6752 && (dead_or_set_p (insn,
6753 spill_reg_stored_to[REGNO (oldequiv)])
6754 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6756 delete_output_reload (insn, j, REGNO (oldequiv));
6758 /* Prevent normal processing of this reload. */
6760 /* Output a special code sequence for this case. */
6761 new_spill_reg_store[REGNO (reloadreg)]
6762 = inc_for_reload (reloadreg, oldequiv, reload_out[j],
6766 /* If we are reloading a pseudo-register that was set by the previous
6767 insn, see if we can get rid of that pseudo-register entirely
6768 by redirecting the previous insn into our reload register. */
6770 else if (optimize && GET_CODE (old) == REG
6771 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6772 && dead_or_set_p (insn, old)
6773 /* This is unsafe if some other reload
6774 uses the same reg first. */
6775 && reload_reg_free_before_p (REGNO (reloadreg),
6777 reload_when_needed[j], 0))
6779 rtx temp = PREV_INSN (insn);
6780 while (temp && GET_CODE (temp) == NOTE)
6781 temp = PREV_INSN (temp);
6783 && GET_CODE (temp) == INSN
6784 && GET_CODE (PATTERN (temp)) == SET
6785 && SET_DEST (PATTERN (temp)) == old
6786 /* Make sure we can access insn_operand_constraint. */
6787 && asm_noperands (PATTERN (temp)) < 0
6788 /* This is unsafe if prev insn rejects our reload reg. */
6789 && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
6791 /* This is unsafe if operand occurs more than once in current
6792 insn. Perhaps some occurrences aren't reloaded. */
6793 && count_occurrences (PATTERN (insn), old) == 1
6794 /* Don't risk splitting a matching pair of operands. */
6795 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6797 /* Store into the reload register instead of the pseudo. */
6798 SET_DEST (PATTERN (temp)) = reloadreg;
6800 /* If the previous insn is an output reload, the source is
6801 a reload register, and its spill_reg_store entry will
6802 contain the previous destination. This is now
6804 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6805 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6807 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6808 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6811 /* If these are the only uses of the pseudo reg,
6812 pretend for GDB it lives in the reload reg we used. */
6813 if (REG_N_DEATHS (REGNO (old)) == 1
6814 && REG_N_SETS (REGNO (old)) == 1)
6816 reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
6817 alter_reg (REGNO (old), -1);
6823 /* We can't do that, so output an insn to load RELOADREG. */
6827 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6828 rtx second_reload_reg = 0;
6829 enum insn_code icode;
6831 /* If we have a secondary reload, pick up the secondary register
6832 and icode, if any. If OLDEQUIV and OLD are different or
6833 if this is an in-out reload, recompute whether or not we
6834 still need a secondary register and what the icode should
6835 be. If we still need a secondary register and the class or
6836 icode is different, go back to reloading from OLD if using
6837 OLDEQUIV means that we got the wrong type of register. We
6838 cannot have different class or icode due to an in-out reload
6839 because we don't make such reloads when both the input and
6840 output need secondary reload registers. */
6842 if (reload_secondary_in_reload[j] >= 0)
6844 int secondary_reload = reload_secondary_in_reload[j];
6845 rtx real_oldequiv = oldequiv;
6848 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6849 and similarly for OLD.
6850 See comments in get_secondary_reload in reload.c. */
6851 /* If it is a pseudo that cannot be replaced with its
6852 equivalent MEM, we must fall back to reload_in, which
6853 will have all the necessary substitutions registered. */
6855 if (GET_CODE (oldequiv) == REG
6856 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6857 && reg_equiv_memory_loc[REGNO (oldequiv)] != 0)
6859 if (reg_equiv_address[REGNO (oldequiv)]
6860 || num_not_at_initial_offset)
6861 real_oldequiv = reload_in[j];
6863 real_oldequiv = reg_equiv_mem[REGNO (oldequiv)];
6866 if (GET_CODE (old) == REG
6867 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6868 && reg_equiv_memory_loc[REGNO (old)] != 0)
6870 if (reg_equiv_address[REGNO (old)]
6871 || num_not_at_initial_offset)
6872 real_old = reload_in[j];
6874 real_old = reg_equiv_mem[REGNO (old)];
6877 second_reload_reg = reload_reg_rtx[secondary_reload];
6878 icode = reload_secondary_in_icode[j];
6880 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6881 || (reload_in[j] != 0 && reload_out[j] != 0))
6883 enum reg_class new_class
6884 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6885 mode, real_oldequiv);
6887 if (new_class == NO_REGS)
6888 second_reload_reg = 0;
6891 enum insn_code new_icode;
6892 enum machine_mode new_mode;
6894 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6895 REGNO (second_reload_reg)))
6896 oldequiv = old, real_oldequiv = real_old;
6899 new_icode = reload_in_optab[(int) mode];
6900 if (new_icode != CODE_FOR_nothing
6901 && ((insn_operand_predicate[(int) new_icode][0]
6902 && ! ((*insn_operand_predicate[(int) new_icode][0])
6904 || (insn_operand_predicate[(int) new_icode][1]
6905 && ! ((*insn_operand_predicate[(int) new_icode][1])
6906 (real_oldequiv, mode)))))
6907 new_icode = CODE_FOR_nothing;
6909 if (new_icode == CODE_FOR_nothing)
6912 new_mode = insn_operand_mode[(int) new_icode][2];
6914 if (GET_MODE (second_reload_reg) != new_mode)
6916 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6918 oldequiv = old, real_oldequiv = real_old;
6921 = gen_rtx_REG (new_mode,
6922 REGNO (second_reload_reg));
6928 /* If we still need a secondary reload register, check
6929 to see if it is being used as a scratch or intermediate
6930 register and generate code appropriately. If we need
6931 a scratch register, use REAL_OLDEQUIV since the form of
6932 the insn may depend on the actual address if it is
6935 if (second_reload_reg)
6937 if (icode != CODE_FOR_nothing)
6939 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6940 second_reload_reg));
6945 /* See if we need a scratch register to load the
6946 intermediate register (a tertiary reload). */
6947 enum insn_code tertiary_icode
6948 = reload_secondary_in_icode[secondary_reload];
6950 if (tertiary_icode != CODE_FOR_nothing)
6952 rtx third_reload_reg
6953 = reload_reg_rtx[reload_secondary_in_reload[secondary_reload]];
6955 emit_insn ((GEN_FCN (tertiary_icode)
6956 (second_reload_reg, real_oldequiv,
6957 third_reload_reg)));
6960 gen_reload (second_reload_reg, real_oldequiv,
6962 reload_when_needed[j]);
6964 oldequiv = second_reload_reg;
6970 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6972 rtx real_oldequiv = oldequiv;
6974 if ((GET_CODE (oldequiv) == REG
6975 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6976 && reg_equiv_memory_loc[REGNO (oldequiv)] != 0)
6977 || (GET_CODE (oldequiv) == SUBREG
6978 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6979 && (REGNO (SUBREG_REG (oldequiv))
6980 >= FIRST_PSEUDO_REGISTER)
6981 && (reg_equiv_memory_loc
6982 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6983 real_oldequiv = reload_in[j];
6984 gen_reload (reloadreg, real_oldequiv, reload_opnum[j],
6985 reload_when_needed[j]);
6990 this_reload_insn = get_last_insn ();
6991 /* End this sequence. */
6992 *where = get_insns ();
6995 /* Update reload_override_in so that delete_address_reloads_1
6996 can see the actual register usage. */
6998 reload_override_in[j] = oldequiv;
7001 /* When inheriting a wider reload, we have a MEM in reload_in[j],
7002 e.g. inheriting a SImode output reload for
7003 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7004 if (optimize && reload_inherited[j] && reload_in[j]
7005 && GET_CODE (reload_in[j]) == MEM
7006 && GET_CODE (reload_in_reg[j]) == MEM
7007 && reload_spill_index[j] >= 0
7008 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7011 = count_occurrences (PATTERN (insn), reload_in[j]) == 1 ? 0 : -1;
7013 = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7016 /* If we are reloading a register that was recently stored in with an
7017 output-reload, see if we can prove there was
7018 actually no need to store the old value in it. */
7021 && (reload_inherited[j] || reload_override_in[j])
7022 && reload_reg_rtx[j]
7023 && GET_CODE (reload_reg_rtx[j]) == REG
7024 && spill_reg_store[REGNO (reload_reg_rtx[j])] != 0
7026 /* There doesn't seem to be any reason to restrict this to pseudos
7027 and doing so loses in the case where we are copying from a
7028 register of the wrong class. */
7029 && REGNO (spill_reg_stored_to[REGNO (reload_reg_rtx[j])])
7030 >= FIRST_PSEUDO_REGISTER
7032 /* The insn might have already some references to stackslots
7033 replaced by MEMs, while reload_out_reg still names the
7035 && (dead_or_set_p (insn,
7036 spill_reg_stored_to[REGNO (reload_reg_rtx[j])])
7037 || rtx_equal_p (spill_reg_stored_to[REGNO (reload_reg_rtx[j])],
7038 reload_out_reg[j])))
7039 delete_output_reload (insn, j, REGNO (reload_reg_rtx[j]));
7041 /* Input-reloading is done. Now do output-reloading,
7042 storing the value from the reload-register after the main insn
7043 if reload_out[j] is nonzero.
7045 ??? At some point we need to support handling output reloads of
7046 JUMP_INSNs or insns that set cc0. */
7048 /* If this is an output reload that stores something that is
7049 not loaded in this same reload, see if we can eliminate a previous
7052 rtx pseudo = reload_out_reg[j];
7055 && GET_CODE (pseudo) == REG
7056 && ! rtx_equal_p (reload_in_reg[j], pseudo)
7057 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7058 && reg_last_reload_reg[REGNO (pseudo)])
7060 int pseudo_no = REGNO (pseudo);
7061 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7063 /* We don't need to test full validity of last_regno for
7064 inherit here; we only want to know if the store actually
7065 matches the pseudo. */
7066 if (reg_reloaded_contents[last_regno] == pseudo_no
7067 && spill_reg_store[last_regno]
7068 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7069 delete_output_reload (insn, j, last_regno);
7073 old = reload_out_reg[j];
7075 && reload_reg_rtx[j] != old
7076 && reload_reg_rtx[j] != 0)
7078 register rtx reloadreg = reload_reg_rtx[j];
7079 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7080 register rtx second_reloadreg = 0;
7083 enum machine_mode mode;
7086 /* An output operand that dies right away does need a reload,
7087 but need not be copied from it. Show the new location in the
7089 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
7090 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7092 XEXP (note, 0) = reload_reg_rtx[j];
7095 /* Likewise for a SUBREG of an operand that dies. */
7096 else if (GET_CODE (old) == SUBREG
7097 && GET_CODE (SUBREG_REG (old)) == REG
7098 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7101 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7105 else if (GET_CODE (old) == SCRATCH)
7106 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7107 but we don't want to make an output reload. */
7111 /* Strip off of OLD any size-increasing SUBREGs such as
7112 (SUBREG:SI foo:QI 0). */
7114 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
7115 && (GET_MODE_SIZE (GET_MODE (old))
7116 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
7117 old = SUBREG_REG (old);
7120 /* If is a JUMP_INSN, we can't support output reloads yet. */
7121 if (GET_CODE (insn) == JUMP_INSN)
7124 if (reload_when_needed[j] == RELOAD_OTHER)
7127 push_to_sequence (output_reload_insns[reload_opnum[j]]);
7129 old = reload_out[j];
7131 /* Determine the mode to reload in.
7132 See comments above (for input reloading). */
7134 mode = GET_MODE (old);
7135 if (mode == VOIDmode)
7137 /* VOIDmode should never happen for an output. */
7138 if (asm_noperands (PATTERN (insn)) < 0)
7139 /* It's the compiler's fault. */
7140 fatal_insn ("VOIDmode on an output", insn);
7141 error_for_asm (insn, "output operand is constant in `asm'");
7142 /* Prevent crash--use something we know is valid. */
7144 old = gen_rtx_REG (mode, REGNO (reloadreg));
7147 if (GET_MODE (reloadreg) != mode)
7148 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
7150 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7152 /* If we need two reload regs, set RELOADREG to the intermediate
7153 one, since it will be stored into OLD. We might need a secondary
7154 register only for an input reload, so check again here. */
7156 if (reload_secondary_out_reload[j] >= 0)
7160 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
7161 && reg_equiv_mem[REGNO (old)] != 0)
7162 real_old = reg_equiv_mem[REGNO (old)];
7164 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
7168 second_reloadreg = reloadreg;
7169 reloadreg = reload_reg_rtx[reload_secondary_out_reload[j]];
7171 /* See if RELOADREG is to be used as a scratch register
7172 or as an intermediate register. */
7173 if (reload_secondary_out_icode[j] != CODE_FOR_nothing)
7175 emit_insn ((GEN_FCN (reload_secondary_out_icode[j])
7176 (real_old, second_reloadreg, reloadreg)));
7181 /* See if we need both a scratch and intermediate reload
7184 int secondary_reload = reload_secondary_out_reload[j];
7185 enum insn_code tertiary_icode
7186 = reload_secondary_out_icode[secondary_reload];
7188 if (GET_MODE (reloadreg) != mode)
7189 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
7191 if (tertiary_icode != CODE_FOR_nothing)
7194 = reload_reg_rtx[reload_secondary_out_reload[secondary_reload]];
7197 /* Copy primary reload reg to secondary reload reg.
7198 (Note that these have been swapped above, then
7199 secondary reload reg to OLD using our insn. */
7201 /* If REAL_OLD is a paradoxical SUBREG, remove it
7202 and try to put the opposite SUBREG on
7204 if (GET_CODE (real_old) == SUBREG
7205 && (GET_MODE_SIZE (GET_MODE (real_old))
7206 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7207 && 0 != (tem = gen_lowpart_common
7208 (GET_MODE (SUBREG_REG (real_old)),
7210 real_old = SUBREG_REG (real_old), reloadreg = tem;
7212 gen_reload (reloadreg, second_reloadreg,
7213 reload_opnum[j], reload_when_needed[j]);
7214 emit_insn ((GEN_FCN (tertiary_icode)
7215 (real_old, reloadreg, third_reloadreg)));
7220 /* Copy between the reload regs here and then to
7223 gen_reload (reloadreg, second_reloadreg,
7224 reload_opnum[j], reload_when_needed[j]);
7230 /* Output the last reload insn. */
7235 /* Don't output the last reload if OLD is not the dest of
7236 INSN and is in the src and is clobbered by INSN. */
7237 if (! flag_expensive_optimizations
7238 || GET_CODE (old) != REG
7239 || !(set = single_set (insn))
7240 || rtx_equal_p (old, SET_DEST (set))
7241 || !reg_mentioned_p (old, SET_SRC (set))
7242 || !regno_clobbered_p (REGNO (old), insn))
7243 gen_reload (old, reloadreg, reload_opnum[j],
7244 reload_when_needed[j]);
7247 /* Look at all insns we emitted, just to be safe. */
7248 for (p = get_insns (); p; p = NEXT_INSN (p))
7249 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
7251 rtx pat = PATTERN (p);
7253 /* If this output reload doesn't come from a spill reg,
7254 clear any memory of reloaded copies of the pseudo reg.
7255 If this output reload comes from a spill reg,
7256 reg_has_output_reload will make this do nothing. */
7257 note_stores (pat, forget_old_reloads_1);
7259 if (reg_mentioned_p (reload_reg_rtx[j], pat))
7261 rtx set = single_set (insn);
7262 if (reload_spill_index[j] < 0
7264 && SET_SRC (set) == reload_reg_rtx[j])
7266 int src = REGNO (SET_SRC (set));
7268 reload_spill_index[j] = src;
7269 SET_HARD_REG_BIT (reg_is_output_reload, src);
7270 if (find_regno_note (insn, REG_DEAD, src))
7271 SET_HARD_REG_BIT (reg_reloaded_died, src);
7273 if (REGNO (reload_reg_rtx[j]) < FIRST_PSEUDO_REGISTER)
7275 int s = reload_secondary_out_reload[j];
7276 set = single_set (p);
7277 /* If this reload copies only to the secondary reload
7278 register, the secondary reload does the actual
7280 if (s >= 0 && set == NULL_RTX)
7281 ; /* We can't tell what function the secondary reload
7282 has and where the actual store to the pseudo is
7283 made; leave new_spill_reg_store alone. */
7285 && SET_SRC (set) == reload_reg_rtx[j]
7286 && SET_DEST (set) == reload_reg_rtx[s])
7288 /* Usually the next instruction will be the
7289 secondary reload insn; if we can confirm
7290 that it is, setting new_spill_reg_store to
7291 that insn will allow an extra optimization. */
7292 rtx s_reg = reload_reg_rtx[s];
7293 rtx next = NEXT_INSN (p);
7294 reload_out[s] = reload_out[j];
7295 reload_out_reg[s] = reload_out_reg[j];
7296 set = single_set (next);
7297 if (set && SET_SRC (set) == s_reg
7298 && ! new_spill_reg_store[REGNO (s_reg)])
7300 SET_HARD_REG_BIT (reg_is_output_reload,
7302 new_spill_reg_store[REGNO (s_reg)] = next;
7306 new_spill_reg_store[REGNO (reload_reg_rtx[j])] = p;
7311 if (reload_when_needed[j] == RELOAD_OTHER)
7313 emit_insns (other_output_reload_insns[reload_opnum[j]]);
7314 other_output_reload_insns[reload_opnum[j]] = get_insns ();
7317 output_reload_insns[reload_opnum[j]] = get_insns ();
7323 /* Now write all the insns we made for reloads in the order expected by
7324 the allocation functions. Prior to the insn being reloaded, we write
7325 the following reloads:
7327 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7329 RELOAD_OTHER reloads.
7331 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7332 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7333 RELOAD_FOR_INPUT reload for the operand.
7335 RELOAD_FOR_OPADDR_ADDRS reloads.
7337 RELOAD_FOR_OPERAND_ADDRESS reloads.
7339 After the insn being reloaded, we write the following:
7341 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7342 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7343 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7344 reloads for the operand. The RELOAD_OTHER output reloads are
7345 output in descending order by reload number. */
7347 emit_insns_before (other_input_address_reload_insns, insn);
7348 emit_insns_before (other_input_reload_insns, insn);
7350 for (j = 0; j < reload_n_operands; j++)
7352 emit_insns_before (inpaddr_address_reload_insns[j], insn);
7353 emit_insns_before (input_address_reload_insns[j], insn);
7354 emit_insns_before (input_reload_insns[j], insn);
7357 emit_insns_before (other_operand_reload_insns, insn);
7358 emit_insns_before (operand_reload_insns, insn);
7360 for (j = 0; j < reload_n_operands; j++)
7362 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
7363 emit_insns_before (output_address_reload_insns[j], following_insn);
7364 emit_insns_before (output_reload_insns[j], following_insn);
7365 emit_insns_before (other_output_reload_insns[j], following_insn);
7368 /* Keep basic block info up to date. */
7371 if (basic_block_head[chain->block] == insn)
7372 basic_block_head[chain->block] = NEXT_INSN (before_insn);
7373 if (basic_block_end[chain->block] == insn)
7374 basic_block_end[chain->block] = PREV_INSN (following_insn);
7377 /* For all the spill regs newly reloaded in this instruction,
7378 record what they were reloaded from, so subsequent instructions
7379 can inherit the reloads.
7381 Update spill_reg_store for the reloads of this insn.
7382 Copy the elements that were updated in the loop above. */
7384 for (j = 0; j < n_reloads; j++)
7386 register int r = reload_order[j];
7387 register int i = reload_spill_index[r];
7389 /* I is nonneg if this reload used a register.
7390 If reload_reg_rtx[r] is 0, this is an optional reload
7391 that we opted to ignore. */
7393 if (i >= 0 && reload_reg_rtx[r] != 0)
7396 = HARD_REGNO_NREGS (i, GET_MODE (reload_reg_rtx[r]));
7398 int part_reaches_end = 0;
7399 int all_reaches_end = 1;
7401 /* For a multi register reload, we need to check if all or part
7402 of the value lives to the end. */
7403 for (k = 0; k < nr; k++)
7405 if (reload_reg_reaches_end_p (i + k, reload_opnum[r],
7406 reload_when_needed[r]))
7407 part_reaches_end = 1;
7409 all_reaches_end = 0;
7412 /* Ignore reloads that don't reach the end of the insn in
7414 if (all_reaches_end)
7416 /* First, clear out memory of what used to be in this spill reg.
7417 If consecutive registers are used, clear them all. */
7419 for (k = 0; k < nr; k++)
7420 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7422 /* Maybe the spill reg contains a copy of reload_out. */
7423 if (reload_out[r] != 0
7424 && (GET_CODE (reload_out[r]) == REG
7426 || ! reload_out_reg[r]
7428 || GET_CODE (reload_out_reg[r]) == REG))
7430 rtx out = (GET_CODE (reload_out[r]) == REG
7434 /* AUTO_INC */ : XEXP (reload_in_reg[r], 0));
7435 register int nregno = REGNO (out);
7436 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7437 : HARD_REGNO_NREGS (nregno,
7438 GET_MODE (reload_reg_rtx[r])));
7440 spill_reg_store[i] = new_spill_reg_store[i];
7441 spill_reg_stored_to[i] = out;
7442 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
7444 /* If NREGNO is a hard register, it may occupy more than
7445 one register. If it does, say what is in the
7446 rest of the registers assuming that both registers
7447 agree on how many words the object takes. If not,
7448 invalidate the subsequent registers. */
7450 if (nregno < FIRST_PSEUDO_REGISTER)
7451 for (k = 1; k < nnr; k++)
7452 reg_last_reload_reg[nregno + k]
7454 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
7455 REGNO (reload_reg_rtx[r]) + k)
7458 /* Now do the inverse operation. */
7459 for (k = 0; k < nr; k++)
7461 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7462 reg_reloaded_contents[i + k]
7463 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7466 reg_reloaded_insn[i + k] = insn;
7467 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7471 /* Maybe the spill reg contains a copy of reload_in. Only do
7472 something if there will not be an output reload for
7473 the register being reloaded. */
7474 else if (reload_out_reg[r] == 0
7475 && reload_in[r] != 0
7476 && ((GET_CODE (reload_in[r]) == REG
7477 && REGNO (reload_in[r]) >= FIRST_PSEUDO_REGISTER
7478 && ! reg_has_output_reload[REGNO (reload_in[r])])
7479 || (GET_CODE (reload_in_reg[r]) == REG
7480 && ! reg_has_output_reload[REGNO (reload_in_reg[r])]))
7481 && ! reg_set_p (reload_reg_rtx[r], PATTERN (insn)))
7483 register int nregno;
7486 if (GET_CODE (reload_in[r]) == REG
7487 && REGNO (reload_in[r]) >= FIRST_PSEUDO_REGISTER)
7488 nregno = REGNO (reload_in[r]);
7489 else if (GET_CODE (reload_in_reg[r]) == REG)
7490 nregno = REGNO (reload_in_reg[r]);
7492 nregno = REGNO (XEXP (reload_in_reg[r], 0));
7494 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7495 : HARD_REGNO_NREGS (nregno,
7496 GET_MODE (reload_reg_rtx[r])));
7498 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
7500 if (nregno < FIRST_PSEUDO_REGISTER)
7501 for (k = 1; k < nnr; k++)
7502 reg_last_reload_reg[nregno + k]
7504 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
7505 REGNO (reload_reg_rtx[r]) + k)
7508 /* Unless we inherited this reload, show we haven't
7509 recently done a store.
7510 Previous stores of inherited auto_inc expressions
7511 also have to be discarded. */
7512 if (! reload_inherited[r]
7513 || (reload_out[r] && ! reload_out_reg[r]))
7514 spill_reg_store[i] = 0;
7516 for (k = 0; k < nr; k++)
7518 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7519 reg_reloaded_contents[i + k]
7520 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7523 reg_reloaded_insn[i + k] = insn;
7524 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7529 /* However, if part of the reload reaches the end, then we must
7530 invalidate the old info for the part that survives to the end. */
7531 else if (part_reaches_end)
7533 for (k = 0; k < nr; k++)
7534 if (reload_reg_reaches_end_p (i + k,
7536 reload_when_needed[r]))
7537 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7541 /* The following if-statement was #if 0'd in 1.34 (or before...).
7542 It's reenabled in 1.35 because supposedly nothing else
7543 deals with this problem. */
7545 /* If a register gets output-reloaded from a non-spill register,
7546 that invalidates any previous reloaded copy of it.
7547 But forget_old_reloads_1 won't get to see it, because
7548 it thinks only about the original insn. So invalidate it here. */
7549 if (i < 0 && reload_out[r] != 0
7550 && (GET_CODE (reload_out[r]) == REG
7551 || (GET_CODE (reload_out[r]) == MEM
7552 && GET_CODE (reload_out_reg[r]) == REG)))
7554 rtx out = (GET_CODE (reload_out[r]) == REG
7555 ? reload_out[r] : reload_out_reg[r]);
7556 register int nregno = REGNO (out);
7557 if (nregno >= FIRST_PSEUDO_REGISTER)
7559 rtx src_reg, store_insn;
7561 reg_last_reload_reg[nregno] = 0;
7563 /* If we can find a hard register that is stored, record
7564 the storing insn so that we may delete this insn with
7565 delete_output_reload. */
7566 src_reg = reload_reg_rtx[r];
7568 /* If this is an optional reload, try to find the source reg
7569 from an input reload. */
7572 rtx set = single_set (insn);
7573 if (SET_DEST (set) == reload_out[r])
7577 src_reg = SET_SRC (set);
7579 for (k = 0; k < n_reloads; k++)
7581 if (reload_in[k] == src_reg)
7583 src_reg = reload_reg_rtx[k];
7590 store_insn = new_spill_reg_store[REGNO (src_reg)];
7591 if (src_reg && GET_CODE (src_reg) == REG
7592 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7594 int src_regno = REGNO (src_reg);
7595 int nr = HARD_REGNO_NREGS (src_regno, reload_mode[r]);
7596 /* The place where to find a death note varies with
7597 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7598 necessarily checked exactly in the code that moves
7599 notes, so just check both locations. */
7600 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7602 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7605 spill_reg_store[src_regno + nr] = store_insn;
7606 spill_reg_stored_to[src_regno + nr] = out;
7607 reg_reloaded_contents[src_regno + nr] = nregno;
7608 reg_reloaded_insn[src_regno + nr] = store_insn;
7609 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7610 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7611 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7613 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7615 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7617 reg_last_reload_reg[nregno] = src_reg;
7622 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (reload_out[r]));
7624 while (num_regs-- > 0)
7625 reg_last_reload_reg[nregno + num_regs] = 0;
7629 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7632 /* Emit code to perform a reload from IN (which may be a reload register) to
7633 OUT (which may also be a reload register). IN or OUT is from operand
7634 OPNUM with reload type TYPE.
7636 Returns first insn emitted. */
7639 gen_reload (out, in, opnum, type)
7643 enum reload_type type;
7645 rtx last = get_last_insn ();
7648 /* If IN is a paradoxical SUBREG, remove it and try to put the
7649 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7650 if (GET_CODE (in) == SUBREG
7651 && (GET_MODE_SIZE (GET_MODE (in))
7652 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7653 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7654 in = SUBREG_REG (in), out = tem;
7655 else if (GET_CODE (out) == SUBREG
7656 && (GET_MODE_SIZE (GET_MODE (out))
7657 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7658 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7659 out = SUBREG_REG (out), in = tem;
7661 /* How to do this reload can get quite tricky. Normally, we are being
7662 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7663 register that didn't get a hard register. In that case we can just
7664 call emit_move_insn.
7666 We can also be asked to reload a PLUS that adds a register or a MEM to
7667 another register, constant or MEM. This can occur during frame pointer
7668 elimination and while reloading addresses. This case is handled by
7669 trying to emit a single insn to perform the add. If it is not valid,
7670 we use a two insn sequence.
7672 Finally, we could be called to handle an 'o' constraint by putting
7673 an address into a register. In that case, we first try to do this
7674 with a named pattern of "reload_load_address". If no such pattern
7675 exists, we just emit a SET insn and hope for the best (it will normally
7676 be valid on machines that use 'o').
7678 This entire process is made complex because reload will never
7679 process the insns we generate here and so we must ensure that
7680 they will fit their constraints and also by the fact that parts of
7681 IN might be being reloaded separately and replaced with spill registers.
7682 Because of this, we are, in some sense, just guessing the right approach
7683 here. The one listed above seems to work.
7685 ??? At some point, this whole thing needs to be rethought. */
7687 if (GET_CODE (in) == PLUS
7688 && (GET_CODE (XEXP (in, 0)) == REG
7689 || GET_CODE (XEXP (in, 0)) == SUBREG
7690 || GET_CODE (XEXP (in, 0)) == MEM)
7691 && (GET_CODE (XEXP (in, 1)) == REG
7692 || GET_CODE (XEXP (in, 1)) == SUBREG
7693 || CONSTANT_P (XEXP (in, 1))
7694 || GET_CODE (XEXP (in, 1)) == MEM))
7696 /* We need to compute the sum of a register or a MEM and another
7697 register, constant, or MEM, and put it into the reload
7698 register. The best possible way of doing this is if the machine
7699 has a three-operand ADD insn that accepts the required operands.
7701 The simplest approach is to try to generate such an insn and see if it
7702 is recognized and matches its constraints. If so, it can be used.
7704 It might be better not to actually emit the insn unless it is valid,
7705 but we need to pass the insn as an operand to `recog' and
7706 `extract_insn' and it is simpler to emit and then delete the insn if
7707 not valid than to dummy things up. */
7709 rtx op0, op1, tem, insn;
7712 op0 = find_replacement (&XEXP (in, 0));
7713 op1 = find_replacement (&XEXP (in, 1));
7715 /* Since constraint checking is strict, commutativity won't be
7716 checked, so we need to do that here to avoid spurious failure
7717 if the add instruction is two-address and the second operand
7718 of the add is the same as the reload reg, which is frequently
7719 the case. If the insn would be A = B + A, rearrange it so
7720 it will be A = A + B as constrain_operands expects. */
7722 if (GET_CODE (XEXP (in, 1)) == REG
7723 && REGNO (out) == REGNO (XEXP (in, 1)))
7724 tem = op0, op0 = op1, op1 = tem;
7726 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7727 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7729 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7730 code = recog_memoized (insn);
7734 extract_insn (insn);
7735 /* We want constrain operands to treat this insn strictly in
7736 its validity determination, i.e., the way it would after reload
7738 if (constrain_operands (1))
7742 delete_insns_since (last);
7744 /* If that failed, we must use a conservative two-insn sequence.
7745 use move to copy constant, MEM, or pseudo register to the reload
7746 register since "move" will be able to handle an arbitrary operand,
7747 unlike add which can't, in general. Then add the registers.
7749 If there is another way to do this for a specific machine, a
7750 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7753 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7754 || (GET_CODE (op1) == REG
7755 && REGNO (op1) >= FIRST_PSEUDO_REGISTER))
7756 tem = op0, op0 = op1, op1 = tem;
7758 gen_reload (out, op0, opnum, type);
7760 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7761 This fixes a problem on the 32K where the stack pointer cannot
7762 be used as an operand of an add insn. */
7764 if (rtx_equal_p (op0, op1))
7767 insn = emit_insn (gen_add2_insn (out, op1));
7769 /* If that failed, copy the address register to the reload register.
7770 Then add the constant to the reload register. */
7772 code = recog_memoized (insn);
7776 extract_insn (insn);
7777 /* We want constrain operands to treat this insn strictly in
7778 its validity determination, i.e., the way it would after reload
7780 if (constrain_operands (1))
7782 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7784 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7789 delete_insns_since (last);
7791 gen_reload (out, op1, opnum, type);
7792 insn = emit_insn (gen_add2_insn (out, op0));
7793 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7796 #ifdef SECONDARY_MEMORY_NEEDED
7797 /* If we need a memory location to do the move, do it that way. */
7798 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7799 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7800 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7801 REGNO_REG_CLASS (REGNO (out)),
7804 /* Get the memory to use and rewrite both registers to its mode. */
7805 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7807 if (GET_MODE (loc) != GET_MODE (out))
7808 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7810 if (GET_MODE (loc) != GET_MODE (in))
7811 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7813 gen_reload (loc, in, opnum, type);
7814 gen_reload (out, loc, opnum, type);
7818 /* If IN is a simple operand, use gen_move_insn. */
7819 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7820 emit_insn (gen_move_insn (out, in));
7822 #ifdef HAVE_reload_load_address
7823 else if (HAVE_reload_load_address)
7824 emit_insn (gen_reload_load_address (out, in));
7827 /* Otherwise, just write (set OUT IN) and hope for the best. */
7829 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7831 /* Return the first insn emitted.
7832 We can not just return get_last_insn, because there may have
7833 been multiple instructions emitted. Also note that gen_move_insn may
7834 emit more than one insn itself, so we can not assume that there is one
7835 insn emitted per emit_insn_before call. */
7837 return last ? NEXT_INSN (last) : get_insns ();
7840 /* Delete a previously made output-reload
7841 whose result we now believe is not needed.
7842 First we double-check.
7844 INSN is the insn now being processed.
7845 LAST_RELOAD_REG is the hard register number for which we want to delete
7846 the last output reload.
7847 J is the reload-number that originally used REG. The caller has made
7848 certain that reload J doesn't use REG any longer for input. */
7851 delete_output_reload (insn, j, last_reload_reg)
7854 int last_reload_reg;
7856 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7857 rtx reg = spill_reg_stored_to[last_reload_reg];
7860 int n_inherited = 0;
7864 /* Get the raw pseudo-register referred to. */
7866 while (GET_CODE (reg) == SUBREG)
7867 reg = SUBREG_REG (reg);
7868 substed = reg_equiv_memory_loc[REGNO (reg)];
7870 /* This is unsafe if the operand occurs more often in the current
7871 insn than it is inherited. */
7872 for (k = n_reloads - 1; k >= 0; k--)
7874 rtx reg2 = reload_in[k];
7877 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7878 reg2 = reload_in_reg[k];
7880 if (reload_out[k] && ! reload_out_reg[k])
7881 reg2 = XEXP (reload_in_reg[k], 0);
7883 while (GET_CODE (reg2) == SUBREG)
7884 reg2 = SUBREG_REG (reg2);
7885 if (rtx_equal_p (reg2, reg))
7887 if (reload_inherited[k] || reload_override_in[k] || k == j)
7890 reg2 = reload_out_reg[k];
7893 while (GET_CODE (reg2) == SUBREG)
7894 reg2 = XEXP (reg2, 0);
7895 if (rtx_equal_p (reg2, reg))
7902 n_occurrences = count_occurrences (PATTERN (insn), reg);
7904 n_occurrences += count_occurrences (PATTERN (insn), substed);
7905 if (n_occurrences > n_inherited)
7908 /* If the pseudo-reg we are reloading is no longer referenced
7909 anywhere between the store into it and here,
7910 and no jumps or labels intervene, then the value can get
7911 here through the reload reg alone.
7912 Otherwise, give up--return. */
7913 for (i1 = NEXT_INSN (output_reload_insn);
7914 i1 != insn; i1 = NEXT_INSN (i1))
7916 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7918 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7919 && reg_mentioned_p (reg, PATTERN (i1)))
7921 /* If this is USE in front of INSN, we only have to check that
7922 there are no more references than accounted for by inheritance. */
7923 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7925 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7926 i1 = NEXT_INSN (i1);
7928 if (n_occurrences <= n_inherited && i1 == insn)
7934 /* The caller has already checked that REG dies or is set in INSN.
7935 It has also checked that we are optimizing, and thus some inaccurancies
7936 in the debugging information are acceptable.
7937 So we could just delete output_reload_insn.
7938 But in some cases we can improve the debugging information without
7939 sacrificing optimization - maybe even improving the code:
7940 See if the pseudo reg has been completely replaced
7941 with reload regs. If so, delete the store insn
7942 and forget we had a stack slot for the pseudo. */
7943 if (reload_out[j] != reload_in[j]
7944 && REG_N_DEATHS (REGNO (reg)) == 1
7945 && REG_N_SETS (REGNO (reg)) == 1
7946 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7947 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7951 /* We know that it was used only between here
7952 and the beginning of the current basic block.
7953 (We also know that the last use before INSN was
7954 the output reload we are thinking of deleting, but never mind that.)
7955 Search that range; see if any ref remains. */
7956 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7958 rtx set = single_set (i2);
7960 /* Uses which just store in the pseudo don't count,
7961 since if they are the only uses, they are dead. */
7962 if (set != 0 && SET_DEST (set) == reg)
7964 if (GET_CODE (i2) == CODE_LABEL
7965 || GET_CODE (i2) == JUMP_INSN)
7967 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7968 && reg_mentioned_p (reg, PATTERN (i2)))
7970 /* Some other ref remains; just delete the output reload we
7972 delete_address_reloads (output_reload_insn, insn);
7973 PUT_CODE (output_reload_insn, NOTE);
7974 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7975 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7980 /* Delete the now-dead stores into this pseudo. */
7981 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7983 rtx set = single_set (i2);
7985 if (set != 0 && SET_DEST (set) == reg)
7987 delete_address_reloads (i2, insn);
7988 /* This might be a basic block head,
7989 thus don't use delete_insn. */
7990 PUT_CODE (i2, NOTE);
7991 NOTE_SOURCE_FILE (i2) = 0;
7992 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7994 if (GET_CODE (i2) == CODE_LABEL
7995 || GET_CODE (i2) == JUMP_INSN)
7999 /* For the debugging info,
8000 say the pseudo lives in this reload reg. */
8001 reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
8002 alter_reg (REGNO (reg), -1);
8004 delete_address_reloads (output_reload_insn, insn);
8005 PUT_CODE (output_reload_insn, NOTE);
8006 NOTE_SOURCE_FILE (output_reload_insn) = 0;
8007 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
8011 /* We are going to delete DEAD_INSN. Recursively delete loads of
8012 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8013 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8015 delete_address_reloads (dead_insn, current_insn)
8016 rtx dead_insn, current_insn;
8018 rtx set = single_set (dead_insn);
8019 rtx set2, dst, prev, next;
8022 rtx dst = SET_DEST (set);
8023 if (GET_CODE (dst) == MEM)
8024 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8026 /* If we deleted the store from a reloaded post_{in,de}c expression,
8027 we can delete the matching adds. */
8028 prev = PREV_INSN (dead_insn);
8029 next = NEXT_INSN (dead_insn);
8030 if (! prev || ! next)
8032 set = single_set (next);
8033 set2 = single_set (prev);
8035 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8036 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8037 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8039 dst = SET_DEST (set);
8040 if (! rtx_equal_p (dst, SET_DEST (set2))
8041 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8042 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8043 || (INTVAL (XEXP (SET_SRC (set), 1))
8044 != - INTVAL (XEXP (SET_SRC (set2), 1))))
8050 /* Subfunction of delete_address_reloads: process registers found in X. */
8052 delete_address_reloads_1 (dead_insn, x, current_insn)
8053 rtx dead_insn, x, current_insn;
8055 rtx prev, set, dst, i2;
8057 enum rtx_code code = GET_CODE (x);
8061 char *fmt= GET_RTX_FORMAT (code);
8062 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8065 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8066 else if (fmt[i] == 'E')
8068 for (j = XVECLEN (x, i) - 1; j >=0; j--)
8069 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8076 if (spill_reg_order[REGNO (x)] < 0)
8079 /* Scan backwards for the insn that sets x. This might be a way back due
8081 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8083 code = GET_CODE (prev);
8084 if (code == CODE_LABEL || code == JUMP_INSN)
8086 if (GET_RTX_CLASS (code) != 'i')
8088 if (reg_set_p (x, PATTERN (prev)))
8090 if (reg_referenced_p (x, PATTERN (prev)))
8093 if (! prev || INSN_UID (prev) < reload_first_uid)
8095 /* Check that PREV only sets the reload register. */
8096 set = single_set (prev);
8099 dst = SET_DEST (set);
8100 if (GET_CODE (dst) != REG
8101 || ! rtx_equal_p (dst, x))
8103 if (! reg_set_p (dst, PATTERN (dead_insn)))
8105 /* Check if DST was used in a later insn -
8106 it might have been inherited. */
8107 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8109 if (GET_CODE (i2) == CODE_LABEL)
8111 if (GET_RTX_CLASS (GET_CODE (i2)) != 'i')
8113 if (reg_referenced_p (dst, PATTERN (i2)))
8115 /* If there is a reference to the register in the current insn,
8116 it might be loaded in a non-inherited reload. If no other
8117 reload uses it, that means the register is set before
8119 if (i2 == current_insn)
8121 for (j = n_reloads - 1; j >= 0; j--)
8122 if ((reload_reg_rtx[j] == dst && reload_inherited[j])
8123 || reload_override_in[j] == dst)
8125 for (j = n_reloads - 1; j >= 0; j--)
8126 if (reload_in[j] && reload_reg_rtx[j] == dst)
8133 if (GET_CODE (i2) == JUMP_INSN)
8135 if (reg_set_p (dst, PATTERN (i2)))
8137 /* If DST is still live at CURRENT_INSN, check if it is used for
8139 if (i2 == current_insn)
8141 for (j = n_reloads - 1; j >= 0; j--)
8142 if ((reload_reg_rtx[j] == dst && reload_inherited[j])
8143 || reload_override_in[j] == dst)
8145 /* ??? We can't finish the loop here, because dst might be
8146 allocated to a pseudo in this block if no reload in this
8147 block needs any of the clsses containing DST - see
8148 spill_hard_reg. There is no easy way to tell this, so we
8149 have to scan till the end of the basic block. */
8153 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8154 reg_reloaded_contents[REGNO (dst)] = -1;
8155 /* Can't use delete_insn here because PREV might be a basic block head. */
8156 PUT_CODE (prev, NOTE);
8157 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
8158 NOTE_SOURCE_FILE (prev) = 0;
8161 /* Output reload-insns to reload VALUE into RELOADREG.
8162 VALUE is an autoincrement or autodecrement RTX whose operand
8163 is a register or memory location;
8164 so reloading involves incrementing that location.
8165 IN is either identical to VALUE, or some cheaper place to reload from.
8167 INC_AMOUNT is the number to increment or decrement by (always positive).
8168 This cannot be deduced from VALUE.
8170 Return the instruction that stores into RELOADREG. */
8173 inc_for_reload (reloadreg, in, value, inc_amount)
8178 /* REG or MEM to be copied and incremented. */
8179 rtx incloc = XEXP (value, 0);
8180 /* Nonzero if increment after copying. */
8181 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
8187 rtx real_in = in == value ? XEXP (in, 0) : in;
8189 /* No hard register is equivalent to this register after
8190 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
8191 we could inc/dec that register as well (maybe even using it for
8192 the source), but I'm not sure it's worth worrying about. */
8193 if (GET_CODE (incloc) == REG)
8194 reg_last_reload_reg[REGNO (incloc)] = 0;
8196 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8197 inc_amount = - inc_amount;
8199 inc = GEN_INT (inc_amount);
8201 /* If this is post-increment, first copy the location to the reload reg. */
8202 if (post && real_in != reloadreg)
8203 emit_insn (gen_move_insn (reloadreg, real_in));
8207 /* See if we can directly increment INCLOC. Use a method similar to
8208 that in gen_reload. */
8210 last = get_last_insn ();
8211 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8212 gen_rtx_PLUS (GET_MODE (incloc),
8215 code = recog_memoized (add_insn);
8218 extract_insn (add_insn);
8219 if (constrain_operands (1))
8221 /* If this is a pre-increment and we have incremented the value
8222 where it lives, copy the incremented value to RELOADREG to
8223 be used as an address. */
8226 emit_insn (gen_move_insn (reloadreg, incloc));
8231 delete_insns_since (last);
8234 /* If couldn't do the increment directly, must increment in RELOADREG.
8235 The way we do this depends on whether this is pre- or post-increment.
8236 For pre-increment, copy INCLOC to the reload register, increment it
8237 there, then save back. */
8241 if (in != reloadreg)
8242 emit_insn (gen_move_insn (reloadreg, real_in));
8243 emit_insn (gen_add2_insn (reloadreg, inc));
8244 store = emit_insn (gen_move_insn (incloc, reloadreg));
8249 Because this might be a jump insn or a compare, and because RELOADREG
8250 may not be available after the insn in an input reload, we must do
8251 the incrementation before the insn being reloaded for.
8253 We have already copied IN to RELOADREG. Increment the copy in
8254 RELOADREG, save that back, then decrement RELOADREG so it has
8255 the original value. */
8257 emit_insn (gen_add2_insn (reloadreg, inc));
8258 store = emit_insn (gen_move_insn (incloc, reloadreg));
8259 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8265 /* Return 1 if we are certain that the constraint-string STRING allows
8266 the hard register REG. Return 0 if we can't be sure of this. */
8269 constraint_accepts_reg_p (string, reg)
8274 int regno = true_regnum (reg);
8277 /* Initialize for first alternative. */
8279 /* Check that each alternative contains `g' or `r'. */
8281 switch (c = *string++)
8284 /* If an alternative lacks `g' or `r', we lose. */
8287 /* If an alternative lacks `g' or `r', we lose. */
8290 /* Initialize for next alternative. */
8295 /* Any general reg wins for this alternative. */
8296 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
8300 /* Any reg in specified class wins for this alternative. */
8302 enum reg_class class = REG_CLASS_FROM_LETTER (c);
8304 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
8310 /* Return the number of places FIND appears within X, but don't count
8311 an occurrence if some SET_DEST is FIND. */
8314 count_occurrences (x, find)
8315 register rtx x, find;
8318 register enum rtx_code code;
8319 register char *format_ptr;
8327 code = GET_CODE (x);
8342 if (GET_CODE (find) == MEM && rtx_equal_p (x, find))
8346 if (SET_DEST (x) == find)
8347 return count_occurrences (SET_SRC (x), find);
8354 format_ptr = GET_RTX_FORMAT (code);
8357 for (i = 0; i < GET_RTX_LENGTH (code); i++)
8359 switch (*format_ptr++)
8362 count += count_occurrences (XEXP (x, i), find);
8366 if (XVEC (x, i) != NULL)
8368 for (j = 0; j < XVECLEN (x, i); j++)
8369 count += count_occurrences (XVECEXP (x, i, j), find);
8377 /* This array holds values which are equivalent to a hard register
8378 during reload_cse_regs. Each array element is an EXPR_LIST of
8379 values. Each time a hard register is set, we set the corresponding
8380 array element to the value. Each time a hard register is copied
8381 into memory, we add the memory location to the corresponding array
8382 element. We don't store values or memory addresses with side
8383 effects in this array.
8385 If the value is a CONST_INT, then the mode of the containing
8386 EXPR_LIST is the mode in which that CONST_INT was referenced.
8388 We sometimes clobber a specific entry in a list. In that case, we
8389 just set XEXP (list-entry, 0) to 0. */
8391 static rtx *reg_values;
8393 /* This is a preallocated REG rtx which we use as a temporary in
8394 reload_cse_invalidate_regno, so that we don't need to allocate a
8395 new one each time through a loop in that function. */
8397 static rtx invalidate_regno_rtx;
8399 /* Invalidate any entries in reg_values which depend on REGNO,
8400 including those for REGNO itself. This is called if REGNO is
8401 changing. If CLOBBER is true, then always forget anything we
8402 currently know about REGNO. MODE is the mode of the assignment to
8403 REGNO, which is used to determine how many hard registers are being
8404 changed. If MODE is VOIDmode, then only REGNO is being changed;
8405 this is used when invalidating call clobbered registers across a
8409 reload_cse_invalidate_regno (regno, mode, clobber)
8411 enum machine_mode mode;
8417 /* Our callers don't always go through true_regnum; we may see a
8418 pseudo-register here from a CLOBBER or the like. We probably
8419 won't ever see a pseudo-register that has a real register number,
8420 for we check anyhow for safety. */
8421 if (regno >= FIRST_PSEUDO_REGISTER)
8422 regno = reg_renumber[regno];
8426 if (mode == VOIDmode)
8427 endregno = regno + 1;
8429 endregno = regno + HARD_REGNO_NREGS (regno, mode);
8432 for (i = regno; i < endregno; i++)
8435 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8439 for (x = reg_values[i]; x; x = XEXP (x, 1))
8441 if (XEXP (x, 0) != 0
8442 && refers_to_regno_p (regno, endregno, XEXP (x, 0), NULL_PTR))
8444 /* If this is the only entry on the list, clear
8445 reg_values[i]. Otherwise, just clear this entry on
8447 if (XEXP (x, 1) == 0 && x == reg_values[i])
8457 /* We must look at earlier registers, in case REGNO is part of a
8458 multi word value but is not the first register. If an earlier
8459 register has a value in a mode which overlaps REGNO, then we must
8460 invalidate that earlier register. Note that we do not need to
8461 check REGNO or later registers (we must not check REGNO itself,
8462 because we would incorrectly conclude that there was a conflict). */
8464 for (i = 0; i < regno; i++)
8468 for (x = reg_values[i]; x; x = XEXP (x, 1))
8470 if (XEXP (x, 0) != 0)
8472 PUT_MODE (invalidate_regno_rtx, GET_MODE (x));
8473 REGNO (invalidate_regno_rtx) = i;
8474 if (refers_to_regno_p (regno, endregno, invalidate_regno_rtx,
8477 reload_cse_invalidate_regno (i, VOIDmode, 1);
8485 /* The memory at address MEM_BASE is being changed.
8486 Return whether this change will invalidate VAL. */
8489 reload_cse_mem_conflict_p (mem_base, val)
8497 code = GET_CODE (val);
8500 /* Get rid of a few simple cases quickly. */
8513 if (GET_MODE (mem_base) == BLKmode
8514 || GET_MODE (val) == BLKmode)
8516 if (anti_dependence (val, mem_base))
8518 /* The address may contain nested MEMs. */
8525 fmt = GET_RTX_FORMAT (code);
8527 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8531 if (reload_cse_mem_conflict_p (mem_base, XEXP (val, i)))
8534 else if (fmt[i] == 'E')
8538 for (j = 0; j < XVECLEN (val, i); j++)
8539 if (reload_cse_mem_conflict_p (mem_base, XVECEXP (val, i, j)))
8547 /* Invalidate any entries in reg_values which are changed because of a
8548 store to MEM_RTX. If this is called because of a non-const call
8549 instruction, MEM_RTX is (mem:BLK const0_rtx). */
8552 reload_cse_invalidate_mem (mem_rtx)
8557 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8561 for (x = reg_values[i]; x; x = XEXP (x, 1))
8563 if (XEXP (x, 0) != 0
8564 && reload_cse_mem_conflict_p (mem_rtx, XEXP (x, 0)))
8566 /* If this is the only entry on the list, clear
8567 reg_values[i]. Otherwise, just clear this entry on
8569 if (XEXP (x, 1) == 0 && x == reg_values[i])
8580 /* Invalidate DEST, which is being assigned to or clobbered. The
8581 second parameter exists so that this function can be passed to
8582 note_stores; it is ignored. */
8585 reload_cse_invalidate_rtx (dest, ignore)
8587 rtx ignore ATTRIBUTE_UNUSED;
8589 while (GET_CODE (dest) == STRICT_LOW_PART
8590 || GET_CODE (dest) == SIGN_EXTRACT
8591 || GET_CODE (dest) == ZERO_EXTRACT
8592 || GET_CODE (dest) == SUBREG)
8593 dest = XEXP (dest, 0);
8595 if (GET_CODE (dest) == REG)
8596 reload_cse_invalidate_regno (REGNO (dest), GET_MODE (dest), 1);
8597 else if (GET_CODE (dest) == MEM)
8598 reload_cse_invalidate_mem (dest);
8601 /* Do a very simple CSE pass over the hard registers.
8603 This function detects no-op moves where we happened to assign two
8604 different pseudo-registers to the same hard register, and then
8605 copied one to the other. Reload will generate a useless
8606 instruction copying a register to itself.
8608 This function also detects cases where we load a value from memory
8609 into two different registers, and (if memory is more expensive than
8610 registers) changes it to simply copy the first register into the
8613 Another optimization is performed that scans the operands of each
8614 instruction to see whether the value is already available in a
8615 hard register. It then replaces the operand with the hard register
8616 if possible, much like an optional reload would. */
8619 reload_cse_regs_1 (first)
8627 init_alias_analysis ();
8629 reg_values = (rtx *) alloca (FIRST_PSEUDO_REGISTER * sizeof (rtx));
8630 bzero ((char *)reg_values, FIRST_PSEUDO_REGISTER * sizeof (rtx));
8632 /* Create our EXPR_LIST structures on reload_obstack, so that we can
8633 free them when we are done. */
8634 push_obstacks (&reload_obstack, &reload_obstack);
8635 firstobj = (char *) obstack_alloc (&reload_obstack, 0);
8637 /* We pass this to reload_cse_invalidate_mem to invalidate all of
8638 memory for a non-const call instruction. */
8639 callmem = gen_rtx_MEM (BLKmode, const0_rtx);
8641 /* This is used in reload_cse_invalidate_regno to avoid consing a
8642 new REG in a loop in that function. */
8643 invalidate_regno_rtx = gen_rtx_REG (VOIDmode, 0);
8645 for (insn = first; insn; insn = NEXT_INSN (insn))
8649 if (GET_CODE (insn) == CODE_LABEL)
8651 /* Forget all the register values at a code label. We don't
8652 try to do anything clever around jumps. */
8653 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8659 #ifdef NON_SAVING_SETJMP
8660 if (NON_SAVING_SETJMP && GET_CODE (insn) == NOTE
8661 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
8663 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8670 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8673 /* If this is a call instruction, forget anything stored in a
8674 call clobbered register, or, if this is not a const call, in
8676 if (GET_CODE (insn) == CALL_INSN)
8678 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8679 if (call_used_regs[i])
8680 reload_cse_invalidate_regno (i, VOIDmode, 1);
8682 if (! CONST_CALL_P (insn))
8683 reload_cse_invalidate_mem (callmem);
8686 body = PATTERN (insn);
8687 if (GET_CODE (body) == SET)
8690 if (reload_cse_noop_set_p (body, insn))
8692 /* If this sets the return value of the function, we must keep
8693 a USE around, in case this is in a different basic block
8694 than the final USE. Otherwise, we could loose important
8695 register lifeness information on SMALL_REGISTER_CLASSES
8696 machines, where return registers might be used as spills:
8697 subsequent passes assume that spill registers are dead at
8698 the end of a basic block. */
8699 if (REG_FUNCTION_VALUE_P (SET_DEST (body)))
8702 PATTERN (insn) = gen_rtx_USE (VOIDmode, SET_DEST (body));
8703 INSN_CODE (insn) = -1;
8704 REG_NOTES (insn) = NULL_RTX;
8705 push_obstacks (&reload_obstack, &reload_obstack);
8709 PUT_CODE (insn, NOTE);
8710 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8711 NOTE_SOURCE_FILE (insn) = 0;
8714 /* We're done with this insn. */
8718 /* It's not a no-op, but we can try to simplify it. */
8719 count += reload_cse_simplify_set (body, insn);
8722 apply_change_group ();
8724 reload_cse_simplify_operands (insn);
8726 reload_cse_record_set (body, body);
8728 else if (GET_CODE (body) == PARALLEL)
8731 rtx value = NULL_RTX;
8733 /* If every action in a PARALLEL is a noop, we can delete
8734 the entire PARALLEL. */
8735 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8737 rtx part = XVECEXP (body, 0, i);
8738 if (GET_CODE (part) == SET)
8740 if (! reload_cse_noop_set_p (part, insn))
8742 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8746 value = SET_DEST (part);
8749 else if (GET_CODE (part) != CLOBBER)
8757 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
8758 INSN_CODE (insn) = -1;
8759 REG_NOTES (insn) = NULL_RTX;
8760 push_obstacks (&reload_obstack, &reload_obstack);
8764 PUT_CODE (insn, NOTE);
8765 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8766 NOTE_SOURCE_FILE (insn) = 0;
8769 /* We're done with this insn. */
8773 /* It's not a no-op, but we can try to simplify it. */
8774 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8775 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8776 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8779 apply_change_group ();
8781 reload_cse_simplify_operands (insn);
8783 /* Look through the PARALLEL and record the values being
8784 set, if possible. Also handle any CLOBBERs. */
8785 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8787 rtx x = XVECEXP (body, 0, i);
8789 if (GET_CODE (x) == SET)
8790 reload_cse_record_set (x, body);
8792 note_stores (x, reload_cse_invalidate_rtx);
8796 note_stores (body, reload_cse_invalidate_rtx);
8799 /* Clobber any registers which appear in REG_INC notes. We
8800 could keep track of the changes to their values, but it is
8801 unlikely to help. */
8805 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
8806 if (REG_NOTE_KIND (x) == REG_INC)
8807 reload_cse_invalidate_rtx (XEXP (x, 0), NULL_RTX);
8811 /* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only
8812 after we have processed the insn. */
8813 if (GET_CODE (insn) == CALL_INSN)
8817 for (x = CALL_INSN_FUNCTION_USAGE (insn); x; x = XEXP (x, 1))
8818 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
8819 reload_cse_invalidate_rtx (XEXP (XEXP (x, 0), 0), NULL_RTX);
8823 /* Free all the temporary structures we created, and go back to the
8824 regular obstacks. */
8825 obstack_free (&reload_obstack, firstobj);
8829 /* Call cse / combine like post-reload optimization phases.
8830 FIRST is the first instruction. */
8832 reload_cse_regs (first)
8835 reload_cse_regs_1 (first);
8837 reload_cse_move2add (first);
8838 if (flag_expensive_optimizations)
8839 reload_cse_regs_1 (first);
8842 /* Return whether the values known for REGNO are equal to VAL. MODE
8843 is the mode of the object that VAL is being copied to; this matters
8844 if VAL is a CONST_INT. */
8847 reload_cse_regno_equal_p (regno, val, mode)
8850 enum machine_mode mode;
8857 for (x = reg_values[regno]; x; x = XEXP (x, 1))
8858 if (XEXP (x, 0) != 0
8859 && rtx_equal_p (XEXP (x, 0), val)
8860 && (! flag_float_store || GET_CODE (XEXP (x, 0)) != MEM
8861 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
8862 && (GET_CODE (val) != CONST_INT
8863 || mode == GET_MODE (x)
8864 || (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8865 /* On a big endian machine if the value spans more than
8866 one register then this register holds the high part of
8867 it and we can't use it.
8869 ??? We should also compare with the high part of the
8871 && !(WORDS_BIG_ENDIAN
8872 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
8873 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
8874 GET_MODE_BITSIZE (GET_MODE (x))))))
8880 /* See whether a single set is a noop. SET is the set instruction we
8881 are should check, and INSN is the instruction from which it came. */
8884 reload_cse_noop_set_p (set, insn)
8889 enum machine_mode dest_mode;
8893 src = SET_SRC (set);
8894 dest = SET_DEST (set);
8895 dest_mode = GET_MODE (dest);
8897 if (side_effects_p (src))
8900 dreg = true_regnum (dest);
8901 sreg = true_regnum (src);
8903 /* Check for setting a register to itself. In this case, we don't
8904 have to worry about REG_DEAD notes. */
8905 if (dreg >= 0 && dreg == sreg)
8911 /* Check for setting a register to itself. */
8915 /* Check for setting a register to a value which we already know
8916 is in the register. */
8917 else if (reload_cse_regno_equal_p (dreg, src, dest_mode))
8920 /* Check for setting a register DREG to another register SREG
8921 where SREG is equal to a value which is already in DREG. */
8926 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
8930 if (XEXP (x, 0) == 0)
8933 if (dest_mode == GET_MODE (x))
8935 else if (GET_MODE_BITSIZE (dest_mode)
8936 < GET_MODE_BITSIZE (GET_MODE (x)))
8937 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
8942 && reload_cse_regno_equal_p (dreg, tmp, dest_mode))
8950 else if (GET_CODE (dest) == MEM)
8952 /* Check for storing a register to memory when we know that the
8953 register is equivalent to the memory location. */
8955 && reload_cse_regno_equal_p (sreg, dest, dest_mode)
8956 && ! side_effects_p (dest))
8963 /* Try to simplify a single SET instruction. SET is the set pattern.
8964 INSN is the instruction it came from.
8965 This function only handles one case: if we set a register to a value
8966 which is not a register, we try to find that value in some other register
8967 and change the set into a register copy. */
8970 reload_cse_simplify_set (set, insn)
8976 enum machine_mode dest_mode;
8977 enum reg_class dclass;
8980 dreg = true_regnum (SET_DEST (set));
8984 src = SET_SRC (set);
8985 if (side_effects_p (src) || true_regnum (src) >= 0)
8988 dclass = REGNO_REG_CLASS (dreg);
8990 /* If memory loads are cheaper than register copies, don't change them. */
8991 if (GET_CODE (src) == MEM
8992 && MEMORY_MOVE_COST (GET_MODE (src), dclass, 1) < 2)
8995 /* If the constant is cheaper than a register, don't change it. */
8996 if (CONSTANT_P (src)
8997 && rtx_cost (src, SET) < 2)
9000 dest_mode = GET_MODE (SET_DEST (set));
9001 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
9004 && REGISTER_MOVE_COST (REGNO_REG_CLASS (i), dclass) == 2
9005 && reload_cse_regno_equal_p (i, src, dest_mode))
9009 /* Pop back to the real obstacks while changing the insn. */
9012 validated = validate_change (insn, &SET_SRC (set),
9013 gen_rtx_REG (dest_mode, i), 1);
9015 /* Go back to the obstack we are using for temporary
9017 push_obstacks (&reload_obstack, &reload_obstack);
9026 /* Try to replace operands in INSN with equivalent values that are already
9027 in registers. This can be viewed as optional reloading.
9029 For each non-register operand in the insn, see if any hard regs are
9030 known to be equivalent to that operand. Record the alternatives which
9031 can accept these hard registers. Among all alternatives, select the
9032 ones which are better or equal to the one currently matching, where
9033 "better" is in terms of '?' and '!' constraints. Among the remaining
9034 alternatives, select the one which replaces most operands with
9038 reload_cse_simplify_operands (insn)
9041 #ifdef REGISTER_CONSTRAINTS
9044 char *constraints[MAX_RECOG_OPERANDS];
9046 /* Vector recording how bad an alternative is. */
9047 int *alternative_reject;
9048 /* Vector recording how many registers can be introduced by choosing
9049 this alternative. */
9050 int *alternative_nregs;
9051 /* Array of vectors recording, for each operand and each alternative,
9052 which hard register to substitute, or -1 if the operand should be
9054 int *op_alt_regno[MAX_RECOG_OPERANDS];
9055 /* Array of alternatives, sorted in order of decreasing desirability. */
9056 int *alternative_order;
9057 rtx reg = gen_rtx_REG (VOIDmode, -1);
9059 extract_insn (insn);
9061 if (recog_n_alternatives == 0 || recog_n_operands == 0)
9064 /* Figure out which alternative currently matches. */
9065 if (! constrain_operands (1))
9066 fatal_insn_not_found (insn);
9068 alternative_reject = (int *) alloca (recog_n_alternatives * sizeof (int));
9069 alternative_nregs = (int *) alloca (recog_n_alternatives * sizeof (int));
9070 alternative_order = (int *) alloca (recog_n_alternatives * sizeof (int));
9071 bzero ((char *)alternative_reject, recog_n_alternatives * sizeof (int));
9072 bzero ((char *)alternative_nregs, recog_n_alternatives * sizeof (int));
9074 for (i = 0; i < recog_n_operands; i++)
9076 enum machine_mode mode;
9080 op_alt_regno[i] = (int *) alloca (recog_n_alternatives * sizeof (int));
9081 for (j = 0; j < recog_n_alternatives; j++)
9082 op_alt_regno[i][j] = -1;
9084 p = constraints[i] = recog_constraints[i];
9085 mode = recog_operand_mode[i];
9087 /* Add the reject values for each alternative given by the constraints
9088 for this operand. */
9096 alternative_reject[j] += 3;
9098 alternative_reject[j] += 300;
9101 /* We won't change operands which are already registers. We
9102 also don't want to modify output operands. */
9103 regno = true_regnum (recog_operand[i]);
9105 || constraints[i][0] == '='
9106 || constraints[i][0] == '+')
9109 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
9111 int class = (int) NO_REGS;
9113 if (! reload_cse_regno_equal_p (regno, recog_operand[i], mode))
9116 REGNO (reg) = regno;
9117 PUT_MODE (reg, mode);
9119 /* We found a register equal to this operand. Now look for all
9120 alternatives that can accept this register and have not been
9121 assigned a register they can use yet. */
9130 case '=': case '+': case '?':
9131 case '#': case '&': case '!':
9133 case '0': case '1': case '2': case '3': case '4':
9134 case 'm': case '<': case '>': case 'V': case 'o':
9135 case 'E': case 'F': case 'G': case 'H':
9136 case 's': case 'i': case 'n':
9137 case 'I': case 'J': case 'K': case 'L':
9138 case 'M': case 'N': case 'O': case 'P':
9139 #ifdef EXTRA_CONSTRAINT
9140 case 'Q': case 'R': case 'S': case 'T': case 'U':
9143 /* These don't say anything we care about. */
9147 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
9152 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
9155 case ',': case '\0':
9156 /* See if REGNO fits this alternative, and set it up as the
9157 replacement register if we don't have one for this
9158 alternative yet and the operand being replaced is not
9159 a cheap CONST_INT. */
9160 if (op_alt_regno[i][j] == -1
9161 && reg_fits_class_p (reg, class, 0, mode)
9162 && (GET_CODE (recog_operand[i]) != CONST_INT
9163 || rtx_cost (recog_operand[i], SET) > rtx_cost (reg, SET)))
9165 alternative_nregs[j]++;
9166 op_alt_regno[i][j] = regno;
9178 /* Record all alternatives which are better or equal to the currently
9179 matching one in the alternative_order array. */
9180 for (i = j = 0; i < recog_n_alternatives; i++)
9181 if (alternative_reject[i] <= alternative_reject[which_alternative])
9182 alternative_order[j++] = i;
9183 recog_n_alternatives = j;
9185 /* Sort it. Given a small number of alternatives, a dumb algorithm
9186 won't hurt too much. */
9187 for (i = 0; i < recog_n_alternatives - 1; i++)
9190 int best_reject = alternative_reject[alternative_order[i]];
9191 int best_nregs = alternative_nregs[alternative_order[i]];
9194 for (j = i + 1; j < recog_n_alternatives; j++)
9196 int this_reject = alternative_reject[alternative_order[j]];
9197 int this_nregs = alternative_nregs[alternative_order[j]];
9199 if (this_reject < best_reject
9200 || (this_reject == best_reject && this_nregs < best_nregs))
9203 best_reject = this_reject;
9204 best_nregs = this_nregs;
9208 tmp = alternative_order[best];
9209 alternative_order[best] = alternative_order[i];
9210 alternative_order[i] = tmp;
9213 /* Substitute the operands as determined by op_alt_regno for the best
9215 j = alternative_order[0];
9217 /* Pop back to the real obstacks while changing the insn. */
9220 for (i = 0; i < recog_n_operands; i++)
9222 enum machine_mode mode = recog_operand_mode[i];
9223 if (op_alt_regno[i][j] == -1)
9226 validate_change (insn, recog_operand_loc[i],
9227 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
9230 for (i = recog_n_dups - 1; i >= 0; i--)
9232 int op = recog_dup_num[i];
9233 enum machine_mode mode = recog_operand_mode[op];
9235 if (op_alt_regno[op][j] == -1)
9238 validate_change (insn, recog_dup_loc[i],
9239 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
9242 /* Go back to the obstack we are using for temporary
9244 push_obstacks (&reload_obstack, &reload_obstack);
9246 return apply_change_group ();
9252 /* These two variables are used to pass information from
9253 reload_cse_record_set to reload_cse_check_clobber. */
9255 static int reload_cse_check_clobbered;
9256 static rtx reload_cse_check_src;
9258 /* See if DEST overlaps with RELOAD_CSE_CHECK_SRC. If it does, set
9259 RELOAD_CSE_CHECK_CLOBBERED. This is called via note_stores. The
9260 second argument, which is passed by note_stores, is ignored. */
9263 reload_cse_check_clobber (dest, ignore)
9265 rtx ignore ATTRIBUTE_UNUSED;
9267 if (reg_overlap_mentioned_p (dest, reload_cse_check_src))
9268 reload_cse_check_clobbered = 1;
9271 /* Record the result of a SET instruction. SET is the set pattern.
9272 BODY is the pattern of the insn that it came from. */
9275 reload_cse_record_set (set, body)
9281 enum machine_mode dest_mode;
9283 dest = SET_DEST (set);
9284 src = SET_SRC (set);
9285 dreg = true_regnum (dest);
9286 sreg = true_regnum (src);
9287 dest_mode = GET_MODE (dest);
9289 /* Some machines don't define AUTO_INC_DEC, but they still use push
9290 instructions. We need to catch that case here in order to
9291 invalidate the stack pointer correctly. Note that invalidating
9292 the stack pointer is different from invalidating DEST. */
9294 while (GET_CODE (x) == SUBREG
9295 || GET_CODE (x) == ZERO_EXTRACT
9296 || GET_CODE (x) == SIGN_EXTRACT
9297 || GET_CODE (x) == STRICT_LOW_PART)
9299 if (push_operand (x, GET_MODE (x)))
9301 reload_cse_invalidate_rtx (stack_pointer_rtx, NULL_RTX);
9302 reload_cse_invalidate_rtx (dest, NULL_RTX);
9306 /* We can only handle an assignment to a register, or a store of a
9307 register to a memory location. For other cases, we just clobber
9308 the destination. We also have to just clobber if there are side
9309 effects in SRC or DEST. */
9310 if ((dreg < 0 && GET_CODE (dest) != MEM)
9311 || side_effects_p (src)
9312 || side_effects_p (dest))
9314 reload_cse_invalidate_rtx (dest, NULL_RTX);
9319 /* We don't try to handle values involving CC, because it's a pain
9320 to keep track of when they have to be invalidated. */
9321 if (reg_mentioned_p (cc0_rtx, src)
9322 || reg_mentioned_p (cc0_rtx, dest))
9324 reload_cse_invalidate_rtx (dest, NULL_RTX);
9329 /* If BODY is a PARALLEL, then we need to see whether the source of
9330 SET is clobbered by some other instruction in the PARALLEL. */
9331 if (GET_CODE (body) == PARALLEL)
9335 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
9339 x = XVECEXP (body, 0, i);
9343 reload_cse_check_clobbered = 0;
9344 reload_cse_check_src = src;
9345 note_stores (x, reload_cse_check_clobber);
9346 if (reload_cse_check_clobbered)
9348 reload_cse_invalidate_rtx (dest, NULL_RTX);
9358 /* This is an assignment to a register. Update the value we
9359 have stored for the register. */
9364 /* This is a copy from one register to another. Any values
9365 which were valid for SREG are now valid for DREG. If the
9366 mode changes, we use gen_lowpart_common to extract only
9367 the part of the value that is copied. */
9368 reg_values[dreg] = 0;
9369 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
9373 if (XEXP (x, 0) == 0)
9375 if (dest_mode == GET_MODE (XEXP (x, 0)))
9377 else if (GET_MODE_BITSIZE (dest_mode)
9378 > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
9381 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
9383 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, tmp,
9388 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, src, NULL_RTX);
9390 /* We've changed DREG, so invalidate any values held by other
9391 registers that depend upon it. */
9392 reload_cse_invalidate_regno (dreg, dest_mode, 0);
9394 /* If this assignment changes more than one hard register,
9395 forget anything we know about the others. */
9396 for (i = 1; i < HARD_REGNO_NREGS (dreg, dest_mode); i++)
9397 reg_values[dreg + i] = 0;
9399 else if (GET_CODE (dest) == MEM)
9401 /* Invalidate conflicting memory locations. */
9402 reload_cse_invalidate_mem (dest);
9404 /* If we're storing a register to memory, add DEST to the list
9406 if (sreg >= 0 && ! side_effects_p (dest))
9407 reg_values[sreg] = gen_rtx_EXPR_LIST (dest_mode, dest,
9412 /* We should have bailed out earlier. */
9417 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
9419 This code might also be useful when reload gave up on reg+reg addresssing
9420 because of clashes between the return register and INDEX_REG_CLASS. */
9422 /* The maximum number of uses of a register we can keep track of to
9423 replace them with reg+reg addressing. */
9424 #define RELOAD_COMBINE_MAX_USES 6
9426 /* INSN is the insn where a register has ben used, and USEP points to the
9427 location of the register within the rtl. */
9428 struct reg_use { rtx insn, *usep; };
9430 /* If the register is used in some unknown fashion, USE_INDEX is negative.
9431 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
9432 indicates where it becomes live again.
9433 Otherwise, USE_INDEX is the index of the last encountered use of the
9434 register (which is first among these we have seen since we scan backwards),
9435 OFFSET contains the constant offset that is added to the register in
9436 all encountered uses, and USE_RUID indicates the first encountered, i.e.
9437 last, of these uses. */
9440 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
9445 } reg_state[FIRST_PSEUDO_REGISTER];
9447 /* Reverse linear uid. This is increased in reload_combine while scanning
9448 the instructions from last to first. It is used to set last_label_ruid
9449 and the store_ruid / use_ruid fields in reg_state. */
9450 static int reload_combine_ruid;
9456 int first_index_reg = 1, last_index_reg = 0;
9458 int last_label_ruid;
9460 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
9461 reload has already used it where appropriate, so there is no use in
9462 trying to generate it now. */
9463 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
9466 /* To avoid wasting too much time later searching for an index register,
9467 determine the minimum and maximum index register numbers. */
9468 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9470 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i))
9472 if (! last_index_reg)
9474 first_index_reg = i;
9477 /* If no index register is available, we can quit now. */
9478 if (first_index_reg > last_index_reg)
9481 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
9482 last_label_ruid = reload_combine_ruid = 0;
9483 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9486 reg_state[i].use_index = -1;
9489 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9490 reg_state[i].store_ruid = reload_combine_ruid;
9494 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
9498 /* We cannot do our optimization across labels. Invalidating all the use
9499 information we have would be costly, so we just note where the label
9500 is and then later disable any optimization that would cross it. */
9501 if (GET_CODE (insn) == CODE_LABEL)
9502 last_label_ruid = reload_combine_ruid;
9503 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
9505 reload_combine_ruid++;
9507 /* Look for (set (REGX) (CONST_INT))
9508 (set (REGX) (PLUS (REGX) (REGY)))
9510 ... (MEM (REGX)) ...
9512 (set (REGZ) (CONST_INT))
9514 ... (MEM (PLUS (REGZ) (REGY)))... .
9516 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
9517 and that we know all uses of REGX before it dies. */
9518 set = single_set (insn);
9520 && GET_CODE (SET_DEST (set)) == REG
9521 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
9522 GET_MODE (SET_DEST (set)))
9524 && GET_CODE (SET_SRC (set)) == PLUS
9525 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
9526 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
9527 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
9529 rtx reg = SET_DEST (set);
9530 rtx plus = SET_SRC (set);
9531 rtx base = XEXP (plus, 1);
9532 rtx prev = prev_nonnote_insn (insn);
9533 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
9534 int regno = REGNO (reg);
9536 rtx reg_sum = NULL_RTX;
9538 /* Now, we need an index register.
9539 We'll set index_reg to this index register, const_reg to the
9540 register that is to be loaded with the constant
9541 (denoted as REGZ in the substitution illustration above),
9542 and reg_sum to the register-register that we want to use to
9543 substitute uses of REG (typically in MEMs) with.
9544 First check REG and BASE for being index registers;
9545 we can use them even if they are not dead. */
9546 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
9547 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
9555 /* Otherwise, look for a free index register. Since we have
9556 checked above that neiter REG nor BASE are index registers,
9557 if we find anything at all, it will be different from these
9559 for (i = first_index_reg; i <= last_index_reg; i++)
9561 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
9562 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
9563 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
9564 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
9566 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
9567 const_reg = index_reg;
9568 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
9574 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
9575 && rtx_equal_p (SET_DEST (prev_set), reg)
9576 && reg_state[regno].use_index >= 0
9581 /* Change destination register and - if necessary - the
9582 constant value in PREV, the constant loading instruction. */
9583 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
9584 if (reg_state[regno].offset != const0_rtx)
9585 validate_change (prev,
9586 &SET_SRC (prev_set),
9587 GEN_INT (INTVAL (SET_SRC (prev_set))
9588 + INTVAL (reg_state[regno].offset)),
9590 /* Now for every use of REG that we have recorded, replace REG
9592 for (i = reg_state[regno].use_index;
9593 i < RELOAD_COMBINE_MAX_USES; i++)
9594 validate_change (reg_state[regno].reg_use[i].insn,
9595 reg_state[regno].reg_use[i].usep,
9598 if (apply_change_group ())
9602 /* Delete the reg-reg addition. */
9603 PUT_CODE (insn, NOTE);
9604 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9605 NOTE_SOURCE_FILE (insn) = 0;
9607 if (reg_state[regno].offset != const0_rtx)
9609 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
9611 for (np = ®_NOTES (prev); *np; )
9613 if (REG_NOTE_KIND (*np) == REG_EQUAL
9614 || REG_NOTE_KIND (*np) == REG_EQUIV)
9615 *np = XEXP (*np, 1);
9617 np = &XEXP (*np, 1);
9620 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9621 reg_state[REGNO (const_reg)].store_ruid = reload_combine_ruid;
9626 note_stores (PATTERN (insn), reload_combine_note_store);
9627 if (GET_CODE (insn) == CALL_INSN)
9631 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9633 if (call_used_regs[i])
9635 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9636 reg_state[i].store_ruid = reload_combine_ruid;
9639 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
9640 link = XEXP (link, 1))
9642 rtx use = XEXP (link, 0);
9643 int regno = REGNO (XEXP (use, 0));
9644 if (GET_CODE (use) == CLOBBER)
9646 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9647 reg_state[regno].store_ruid = reload_combine_ruid;
9650 reg_state[regno].use_index = -1;
9653 if (GET_CODE (insn) == JUMP_INSN)
9655 /* Non-spill registers might be used at the call destination in
9656 some unknown fashion, so we have to mark the unknown use. */
9657 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9660 reg_state[i].use_index = -1;
9663 reload_combine_note_use (&PATTERN (insn), insn);
9664 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9666 if (REG_NOTE_KIND (note) == REG_INC
9667 && GET_CODE (XEXP (note, 0)) == REG)
9668 reg_state[REGNO (XEXP (note, 0))].use_index = -1;
9673 /* Check if DST is a register or a subreg of a register; if it is,
9674 update reg_state[regno].store_ruid and reg_state[regno].use_index
9675 accordingly. Called via note_stores from reload_combine.
9676 The second argument, SET, is ignored. */
9678 reload_combine_note_store (dst, set)
9679 rtx dst, set ATTRIBUTE_UNUSED;
9683 unsigned size = GET_MODE_SIZE (GET_MODE (dst));
9685 if (GET_CODE (dst) == SUBREG)
9687 regno = SUBREG_WORD (dst);
9688 dst = SUBREG_REG (dst);
9690 if (GET_CODE (dst) != REG)
9692 regno += REGNO (dst);
9693 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
9694 careful with registers / register parts that are not full words. */
9695 if (size < (unsigned) UNITS_PER_WORD)
9696 reg_state[regno].use_index = -1;
9699 for (i = size / UNITS_PER_WORD - 1 + regno; i >= regno; i--)
9701 reg_state[i].store_ruid = reload_combine_ruid;
9702 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9707 /* XP points to a piece of rtl that has to be checked for any uses of
9709 *XP is the pattern of INSN, or a part of it.
9710 Called from reload_combine, and recursively by itself. */
9712 reload_combine_note_use (xp, insn)
9716 enum rtx_code code = x->code;
9719 rtx offset = const0_rtx; /* For the REG case below. */
9724 if (GET_CODE (SET_DEST (x)) == REG)
9726 reload_combine_note_use (&SET_SRC (x), insn);
9732 if (GET_CODE (SET_DEST (x)) == REG)
9737 /* We are interested in (plus (reg) (const_int)) . */
9738 if (GET_CODE (XEXP (x, 0)) != REG || GET_CODE (XEXP (x, 1)) != CONST_INT)
9740 offset = XEXP (x, 1);
9745 int regno = REGNO (x);
9748 /* Some spurious USEs of pseudo registers might remain.
9749 Just ignore them. */
9750 if (regno >= FIRST_PSEUDO_REGISTER)
9753 /* If this register is already used in some unknown fashion, we
9755 If we decrement the index from zero to -1, we can't store more
9756 uses, so this register becomes used in an unknown fashion. */
9757 use_index = --reg_state[regno].use_index;
9761 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
9763 /* We have found another use for a register that is already
9764 used later. Check if the offsets match; if not, mark the
9765 register as used in an unknown fashion. */
9766 if (! rtx_equal_p (offset, reg_state[regno].offset))
9768 reg_state[regno].use_index = -1;
9774 /* This is the first use of this register we have seen since we
9775 marked it as dead. */
9776 reg_state[regno].offset = offset;
9777 reg_state[regno].use_ruid = reload_combine_ruid;
9779 reg_state[regno].reg_use[use_index].insn = insn;
9780 reg_state[regno].reg_use[use_index].usep = xp;
9788 /* Recursively process the components of X. */
9789 fmt = GET_RTX_FORMAT (code);
9790 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9793 reload_combine_note_use (&XEXP (x, i), insn);
9794 else if (fmt[i] == 'E')
9796 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9797 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9802 /* See if we can reduce the cost of a constant by replacing a move with
9804 /* We cannot do our optimization across labels. Invalidating all the
9805 information about register contents we have would be costly, so we
9806 use last_label_luid (local variable of reload_cse_move2add) to note
9807 where the label is and then later disable any optimization that would
9809 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9810 reg_set_luid[n] is larger than last_label_luid[n] . */
9811 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9812 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
9813 reg_mode[n] to be valid.
9814 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
9815 has been set to reg_offset[n] in mode reg_mode[n] .
9816 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
9817 register n has been set to the sum of reg_offset[n] and register
9818 reg_base_reg[n], calculated in mode reg_mode[n] . */
9819 static rtx reg_offset[FIRST_PSEUDO_REGISTER];
9820 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9821 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9822 /* move2add_luid is linearily increased while scanning the instructions
9823 from first to last. It is used to set reg_set_luid in
9824 reload_cse_move2add and move2add_note_store. */
9825 static int move2add_luid;
9828 reload_cse_move2add (first)
9833 int last_label_luid;
9835 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
9836 reg_set_luid[i] = 0;
9838 last_label_luid = 0;
9840 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9844 if (GET_CODE (insn) == CODE_LABEL)
9845 last_label_luid = move2add_luid;
9846 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
9848 pat = PATTERN (insn);
9849 /* For simplicity, we only perform this optimization on
9850 straightforward SETs. */
9851 if (GET_CODE (pat) == SET
9852 && GET_CODE (SET_DEST (pat)) == REG)
9854 rtx reg = SET_DEST (pat);
9855 int regno = REGNO (reg);
9856 rtx src = SET_SRC (pat);
9858 /* Check if we have valid information on the contents of this
9859 register in the mode of REG. */
9860 /* ??? We don't know how zero / sign extension is handled, hence
9861 we can't go from a narrower to a wider mode. */
9862 if (reg_set_luid[regno] > last_label_luid
9863 && (GET_MODE_SIZE (GET_MODE (reg))
9864 <= GET_MODE_SIZE (reg_mode[regno]))
9865 && GET_CODE (reg_offset[regno]) == CONST_INT)
9867 /* Try to transform (set (REGX) (CONST_INT A))
9869 (set (REGX) (CONST_INT B))
9871 (set (REGX) (CONST_INT A))
9873 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9875 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9878 rtx new_src = GEN_INT (INTVAL (src)
9879 - INTVAL (reg_offset[regno]));
9880 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9881 use (set (reg) (reg)) instead.
9882 We don't delete this insn, nor do we convert it into a
9883 note, to avoid losing register notes or the return
9884 value flag. jump2 already knowns how to get rid of
9886 if (new_src == const0_rtx)
9887 success = validate_change (insn, &SET_SRC (pat), reg, 0);
9888 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9889 && have_add2_insn (GET_MODE (reg)))
9890 success = validate_change (insn, &PATTERN (insn),
9891 gen_add2_insn (reg, new_src), 0);
9892 reg_set_luid[regno] = move2add_luid;
9893 reg_mode[regno] = GET_MODE (reg);
9894 reg_offset[regno] = src;
9898 /* Try to transform (set (REGX) (REGY))
9899 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9902 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9905 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9907 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9908 else if (GET_CODE (src) == REG
9909 && reg_base_reg[regno] == REGNO (src)
9910 && reg_set_luid[regno] > reg_set_luid[REGNO (src)])
9912 rtx next = next_nonnote_insn (insn);
9915 set = single_set (next);
9918 && SET_DEST (set) == reg
9919 && GET_CODE (SET_SRC (set)) == PLUS
9920 && XEXP (SET_SRC (set), 0) == reg
9921 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9923 rtx src3 = XEXP (SET_SRC (set), 1);
9924 rtx new_src = GEN_INT (INTVAL (src3)
9925 - INTVAL (reg_offset[regno]));
9928 if (new_src == const0_rtx)
9929 /* See above why we create (set (reg) (reg)) here. */
9931 = validate_change (next, &SET_SRC (set), reg, 0);
9932 else if ((rtx_cost (new_src, PLUS)
9933 < 2 + rtx_cost (src3, SET))
9934 && have_add2_insn (GET_MODE (reg)))
9936 = validate_change (next, &PATTERN (next),
9937 gen_add2_insn (reg, new_src), 0);
9940 /* INSN might be the first insn in a basic block
9941 if the preceding insn is a conditional jump
9942 or a possible-throwing call. */
9943 PUT_CODE (insn, NOTE);
9944 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9945 NOTE_SOURCE_FILE (insn) = 0;
9948 reg_set_luid[regno] = move2add_luid;
9949 reg_mode[regno] = GET_MODE (reg);
9950 reg_offset[regno] = src3;
9957 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9959 if (REG_NOTE_KIND (note) == REG_INC
9960 && GET_CODE (XEXP (note, 0)) == REG)
9962 /* Indicate that this register has been recently written to,
9963 but the exact contents are not available. */
9964 int regno = REGNO (XEXP (note, 0));
9965 if (regno < FIRST_PSEUDO_REGISTER)
9967 reg_set_luid[regno] = move2add_luid;
9968 reg_offset[regno] = note;
9972 note_stores (PATTERN (insn), move2add_note_store);
9973 /* If this is a CALL_INSN, all call used registers are stored with
9975 if (GET_CODE (insn) == CALL_INSN)
9977 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
9979 if (call_used_regs[i])
9981 reg_set_luid[i] = move2add_luid;
9982 reg_offset[i] = insn; /* Invalidate contents. */
9989 /* SET is a SET or CLOBBER that sets DST.
9990 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9991 Called from reload_cse_move2add via note_stores. */
9993 move2add_note_store (dst, set)
9999 enum machine_mode mode = GET_MODE (dst);
10000 if (GET_CODE (dst) == SUBREG)
10002 regno = SUBREG_WORD (dst);
10003 dst = SUBREG_REG (dst);
10005 if (GET_CODE (dst) != REG)
10008 regno += REGNO (dst);
10010 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET)
10012 rtx src = SET_SRC (set);
10014 reg_mode[regno] = mode;
10015 switch (GET_CODE (src))
10019 rtx src0 = XEXP (src, 0);
10020 if (GET_CODE (src0) == REG)
10022 if (REGNO (src0) != regno
10023 || reg_offset[regno] != const0_rtx)
10025 reg_base_reg[regno] = REGNO (src0);
10026 reg_set_luid[regno] = move2add_luid;
10028 reg_offset[regno] = XEXP (src, 1);
10031 reg_set_luid[regno] = move2add_luid;
10032 reg_offset[regno] = set; /* Invalidate contents. */
10037 reg_base_reg[regno] = REGNO (SET_SRC (set));
10038 reg_offset[regno] = const0_rtx;
10039 reg_set_luid[regno] = move2add_luid;
10043 reg_base_reg[regno] = -1;
10044 reg_offset[regno] = SET_SRC (set);
10045 reg_set_luid[regno] = move2add_luid;
10051 for (i = regno + HARD_REGNO_NREGS (regno, mode) - 1; i >= regno; i--)
10053 /* Indicate that this register has been recently written to,
10054 but the exact contents are not available. */
10055 reg_set_luid[i] = move2add_luid;
10056 reg_offset[i] = dst;
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