1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "insn-flags.h"
32 #include "insn-codes.h"
37 #include "basic-block.h"
45 #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY
46 #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
49 /* This file contains the reload pass of the compiler, which is
50 run after register allocation has been done. It checks that
51 each insn is valid (operands required to be in registers really
52 are in registers of the proper class) and fixes up invalid ones
53 by copying values temporarily into registers for the insns
56 The results of register allocation are described by the vector
57 reg_renumber; the insns still contain pseudo regs, but reg_renumber
58 can be used to find which hard reg, if any, a pseudo reg is in.
60 The technique we always use is to free up a few hard regs that are
61 called ``reload regs'', and for each place where a pseudo reg
62 must be in a hard reg, copy it temporarily into one of the reload regs.
64 Reload regs are allocated locally for every instruction that needs
65 reloads. When there are pseudos which are allocated to a register that
66 has been chosen as a reload reg, such pseudos must be ``spilled''.
67 This means that they go to other hard regs, or to stack slots if no other
68 available hard regs can be found. Spilling can invalidate more
69 insns, requiring additional need for reloads, so we must keep checking
70 until the process stabilizes.
72 For machines with different classes of registers, we must keep track
73 of the register class needed for each reload, and make sure that
74 we allocate enough reload registers of each class.
76 The file reload.c contains the code that checks one insn for
77 validity and reports the reloads that it needs. This file
78 is in charge of scanning the entire rtl code, accumulating the
79 reload needs, spilling, assigning reload registers to use for
80 fixing up each insn, and generating the new insns to copy values
81 into the reload registers. */
83 #ifndef REGISTER_MOVE_COST
84 #define REGISTER_MOVE_COST(m, x, y) 2
88 #define LOCAL_REGNO(REGNO) 0
91 /* During reload_as_needed, element N contains a REG rtx for the hard reg
92 into which reg N has been reloaded (perhaps for a previous insn). */
93 static rtx *reg_last_reload_reg;
95 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
96 for an output reload that stores into reg N. */
97 static char *reg_has_output_reload;
99 /* Indicates which hard regs are reload-registers for an output reload
100 in the current insn. */
101 static HARD_REG_SET reg_is_output_reload;
103 /* Element N is the constant value to which pseudo reg N is equivalent,
104 or zero if pseudo reg N is not equivalent to a constant.
105 find_reloads looks at this in order to replace pseudo reg N
106 with the constant it stands for. */
107 rtx *reg_equiv_constant;
109 /* Element N is a memory location to which pseudo reg N is equivalent,
110 prior to any register elimination (such as frame pointer to stack
111 pointer). Depending on whether or not it is a valid address, this value
112 is transferred to either reg_equiv_address or reg_equiv_mem. */
113 rtx *reg_equiv_memory_loc;
115 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
116 This is used when the address is not valid as a memory address
117 (because its displacement is too big for the machine.) */
118 rtx *reg_equiv_address;
120 /* Element N is the memory slot to which pseudo reg N is equivalent,
121 or zero if pseudo reg N is not equivalent to a memory slot. */
124 /* Widest width in which each pseudo reg is referred to (via subreg). */
125 static unsigned int *reg_max_ref_width;
127 /* Element N is the list of insns that initialized reg N from its equivalent
128 constant or memory slot. */
129 static rtx *reg_equiv_init;
131 /* Vector to remember old contents of reg_renumber before spilling. */
132 static short *reg_old_renumber;
134 /* During reload_as_needed, element N contains the last pseudo regno reloaded
135 into hard register N. If that pseudo reg occupied more than one register,
136 reg_reloaded_contents points to that pseudo for each spill register in
137 use; all of these must remain set for an inheritance to occur. */
138 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
140 /* During reload_as_needed, element N contains the insn for which
141 hard register N was last used. Its contents are significant only
142 when reg_reloaded_valid is set for this register. */
143 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
145 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
146 static HARD_REG_SET reg_reloaded_valid;
147 /* Indicate if the register was dead at the end of the reload.
148 This is only valid if reg_reloaded_contents is set and valid. */
149 static HARD_REG_SET reg_reloaded_dead;
151 /* Number of spill-regs so far; number of valid elements of spill_regs. */
154 /* In parallel with spill_regs, contains REG rtx's for those regs.
155 Holds the last rtx used for any given reg, or 0 if it has never
156 been used for spilling yet. This rtx is reused, provided it has
158 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
160 /* In parallel with spill_regs, contains nonzero for a spill reg
161 that was stored after the last time it was used.
162 The precise value is the insn generated to do the store. */
163 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
165 /* This is the register that was stored with spill_reg_store. This is a
166 copy of reload_out / reload_out_reg when the value was stored; if
167 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
168 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
170 /* This table is the inverse mapping of spill_regs:
171 indexed by hard reg number,
172 it contains the position of that reg in spill_regs,
173 or -1 for something that is not in spill_regs.
175 ?!? This is no longer accurate. */
176 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
178 /* This reg set indicates registers that can't be used as spill registers for
179 the currently processed insn. These are the hard registers which are live
180 during the insn, but not allocated to pseudos, as well as fixed
182 static HARD_REG_SET bad_spill_regs;
184 /* These are the hard registers that can't be used as spill register for any
185 insn. This includes registers used for user variables and registers that
186 we can't eliminate. A register that appears in this set also can't be used
187 to retry register allocation. */
188 static HARD_REG_SET bad_spill_regs_global;
190 /* Describes order of use of registers for reloading
191 of spilled pseudo-registers. `n_spills' is the number of
192 elements that are actually valid; new ones are added at the end.
194 Both spill_regs and spill_reg_order are used on two occasions:
195 once during find_reload_regs, where they keep track of the spill registers
196 for a single insn, but also during reload_as_needed where they show all
197 the registers ever used by reload. For the latter case, the information
198 is calculated during finish_spills. */
199 static short spill_regs[FIRST_PSEUDO_REGISTER];
201 /* This vector of reg sets indicates, for each pseudo, which hard registers
202 may not be used for retrying global allocation because the register was
203 formerly spilled from one of them. If we allowed reallocating a pseudo to
204 a register that it was already allocated to, reload might not
206 static HARD_REG_SET *pseudo_previous_regs;
208 /* This vector of reg sets indicates, for each pseudo, which hard
209 registers may not be used for retrying global allocation because they
210 are used as spill registers during one of the insns in which the
212 static HARD_REG_SET *pseudo_forbidden_regs;
214 /* All hard regs that have been used as spill registers for any insn are
215 marked in this set. */
216 static HARD_REG_SET used_spill_regs;
218 /* Index of last register assigned as a spill register. We allocate in
219 a round-robin fashion. */
220 static int last_spill_reg;
222 /* Nonzero if indirect addressing is supported on the machine; this means
223 that spilling (REG n) does not require reloading it into a register in
224 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
225 value indicates the level of indirect addressing supported, e.g., two
226 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
228 static char spill_indirect_levels;
230 /* Nonzero if indirect addressing is supported when the innermost MEM is
231 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
232 which these are valid is the same as spill_indirect_levels, above. */
233 char indirect_symref_ok;
235 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
236 char double_reg_address_ok;
238 /* Record the stack slot for each spilled hard register. */
239 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
241 /* Width allocated so far for that stack slot. */
242 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
244 /* Record which pseudos needed to be spilled. */
245 static regset_head spilled_pseudos;
247 /* Used for communication between order_regs_for_reload and count_pseudo.
248 Used to avoid counting one pseudo twice. */
249 static regset_head pseudos_counted;
251 /* First uid used by insns created by reload in this function.
252 Used in find_equiv_reg. */
253 int reload_first_uid;
255 /* Flag set by local-alloc or global-alloc if anything is live in
256 a call-clobbered reg across calls. */
257 int caller_save_needed;
259 /* Set to 1 while reload_as_needed is operating.
260 Required by some machines to handle any generated moves differently. */
261 int reload_in_progress = 0;
263 /* These arrays record the insn_code of insns that may be needed to
264 perform input and output reloads of special objects. They provide a
265 place to pass a scratch register. */
266 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
267 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
269 /* This obstack is used for allocation of rtl during register elimination.
270 The allocated storage can be freed once find_reloads has processed the
272 struct obstack reload_obstack;
274 /* Points to the beginning of the reload_obstack. All insn_chain structures
275 are allocated first. */
276 char *reload_startobj;
278 /* The point after all insn_chain structures. Used to quickly deallocate
279 memory allocated in copy_reloads during calculate_needs_all_insns. */
280 char *reload_firstobj;
282 /* This points before all local rtl generated by register elimination.
283 Used to quickly free all memory after processing one insn. */
284 static char *reload_insn_firstobj;
286 #define obstack_chunk_alloc xmalloc
287 #define obstack_chunk_free free
289 /* List of insn_chain instructions, one for every insn that reload needs to
291 struct insn_chain *reload_insn_chain;
294 extern tree current_function_decl;
296 extern union tree_node *current_function_decl;
299 /* List of all insns needing reloads. */
300 static struct insn_chain *insns_need_reload;
302 /* This structure is used to record information about register eliminations.
303 Each array entry describes one possible way of eliminating a register
304 in favor of another. If there is more than one way of eliminating a
305 particular register, the most preferred should be specified first. */
309 int from; /* Register number to be eliminated. */
310 int to; /* Register number used as replacement. */
311 int initial_offset; /* Initial difference between values. */
312 int can_eliminate; /* Non-zero if this elimination can be done. */
313 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
314 insns made by reload. */
315 int offset; /* Current offset between the two regs. */
316 int previous_offset; /* Offset at end of previous insn. */
317 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
318 rtx from_rtx; /* REG rtx for the register to be eliminated.
319 We cannot simply compare the number since
320 we might then spuriously replace a hard
321 register corresponding to a pseudo
322 assigned to the reg to be eliminated. */
323 rtx to_rtx; /* REG rtx for the replacement. */
326 static struct elim_table *reg_eliminate = 0;
328 /* This is an intermediate structure to initialize the table. It has
329 exactly the members provided by ELIMINABLE_REGS. */
330 static struct elim_table_1
334 } reg_eliminate_1[] =
336 /* If a set of eliminable registers was specified, define the table from it.
337 Otherwise, default to the normal case of the frame pointer being
338 replaced by the stack pointer. */
340 #ifdef ELIMINABLE_REGS
343 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
346 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
348 /* Record the number of pending eliminations that have an offset not equal
349 to their initial offset. If non-zero, we use a new copy of each
350 replacement result in any insns encountered. */
351 int num_not_at_initial_offset;
353 /* Count the number of registers that we may be able to eliminate. */
354 static int num_eliminable;
355 /* And the number of registers that are equivalent to a constant that
356 can be eliminated to frame_pointer / arg_pointer + constant. */
357 static int num_eliminable_invariants;
359 /* For each label, we record the offset of each elimination. If we reach
360 a label by more than one path and an offset differs, we cannot do the
361 elimination. This information is indexed by the number of the label.
362 The first table is an array of flags that records whether we have yet
363 encountered a label and the second table is an array of arrays, one
364 entry in the latter array for each elimination. */
366 static char *offsets_known_at;
367 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
369 /* Number of labels in the current function. */
371 static int num_labels;
373 static void replace_pseudos_in_call_usage PARAMS((rtx *,
376 static void maybe_fix_stack_asms PARAMS ((void));
377 static void copy_reloads PARAMS ((struct insn_chain *));
378 static void calculate_needs_all_insns PARAMS ((int));
379 static int find_reg PARAMS ((struct insn_chain *, int));
380 static void find_reload_regs PARAMS ((struct insn_chain *));
381 static void select_reload_regs PARAMS ((void));
382 static void delete_caller_save_insns PARAMS ((void));
384 static void spill_failure PARAMS ((rtx, enum reg_class));
385 static void count_spilled_pseudo PARAMS ((int, int, int));
386 static void delete_dead_insn PARAMS ((rtx));
387 static void alter_reg PARAMS ((int, int));
388 static void set_label_offsets PARAMS ((rtx, rtx, int));
389 static void check_eliminable_occurrences PARAMS ((rtx));
390 static void elimination_effects PARAMS ((rtx, enum machine_mode));
391 static int eliminate_regs_in_insn PARAMS ((rtx, int));
392 static void update_eliminable_offsets PARAMS ((void));
393 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
394 static void set_initial_elim_offsets PARAMS ((void));
395 static void verify_initial_elim_offsets PARAMS ((void));
396 static void set_initial_label_offsets PARAMS ((void));
397 static void set_offsets_for_label PARAMS ((rtx));
398 static void init_elim_table PARAMS ((void));
399 static void update_eliminables PARAMS ((HARD_REG_SET *));
400 static void spill_hard_reg PARAMS ((unsigned int, int));
401 static int finish_spills PARAMS ((int));
402 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
403 static void scan_paradoxical_subregs PARAMS ((rtx));
404 static void count_pseudo PARAMS ((int));
405 static void order_regs_for_reload PARAMS ((struct insn_chain *));
406 static void reload_as_needed PARAMS ((int));
407 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
408 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
409 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
412 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
415 static int reload_reg_free_p PARAMS ((unsigned int, int,
417 static int reload_reg_free_for_value_p PARAMS ((int, int, enum reload_type,
418 rtx, rtx, int, int));
419 static int free_for_value_p PARAMS ((int, enum machine_mode, int,
420 enum reload_type, rtx, rtx,
422 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
424 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
426 static int conflicts_with_override PARAMS ((rtx));
427 static void failed_reload PARAMS ((rtx, int));
428 static int set_reload_reg PARAMS ((int, int));
429 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
430 static void choose_reload_regs PARAMS ((struct insn_chain *));
431 static void merge_assigned_reloads PARAMS ((rtx));
432 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
433 struct reload *, rtx, int));
434 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
435 struct reload *, int));
436 static void do_input_reload PARAMS ((struct insn_chain *,
437 struct reload *, int));
438 static void do_output_reload PARAMS ((struct insn_chain *,
439 struct reload *, int));
440 static void emit_reload_insns PARAMS ((struct insn_chain *));
441 static void delete_output_reload PARAMS ((rtx, int, int));
442 static void delete_address_reloads PARAMS ((rtx, rtx));
443 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
444 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
445 static int constraint_accepts_reg_p PARAMS ((const char *, rtx));
446 static void reload_cse_regs_1 PARAMS ((rtx));
447 static int reload_cse_noop_set_p PARAMS ((rtx));
448 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
449 static int reload_cse_simplify_operands PARAMS ((rtx));
450 static void reload_combine PARAMS ((void));
451 static void reload_combine_note_use PARAMS ((rtx *, rtx));
452 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
453 static void reload_cse_move2add PARAMS ((rtx));
454 static void move2add_note_store PARAMS ((rtx, rtx, void *));
456 static void add_auto_inc_notes PARAMS ((rtx, rtx));
458 static rtx gen_mode_int PARAMS ((enum machine_mode,
460 static void failed_reload PARAMS ((rtx, int));
461 static int set_reload_reg PARAMS ((int, int));
462 static void reload_cse_delete_noop_set PARAMS ((rtx, rtx));
463 static void reload_cse_simplify PARAMS ((rtx));
464 extern void dump_needs PARAMS ((struct insn_chain *));
466 /* Initialize the reload pass once per compilation. */
473 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
474 Set spill_indirect_levels to the number of levels such addressing is
475 permitted, zero if it is not permitted at all. */
478 = gen_rtx_MEM (Pmode,
481 LAST_VIRTUAL_REGISTER + 1),
483 spill_indirect_levels = 0;
485 while (memory_address_p (QImode, tem))
487 spill_indirect_levels++;
488 tem = gen_rtx_MEM (Pmode, tem);
491 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
493 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
494 indirect_symref_ok = memory_address_p (QImode, tem);
496 /* See if reg+reg is a valid (and offsettable) address. */
498 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
500 tem = gen_rtx_PLUS (Pmode,
501 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
502 gen_rtx_REG (Pmode, i));
504 /* This way, we make sure that reg+reg is an offsettable address. */
505 tem = plus_constant (tem, 4);
507 if (memory_address_p (QImode, tem))
509 double_reg_address_ok = 1;
514 /* Initialize obstack for our rtl allocation. */
515 gcc_obstack_init (&reload_obstack);
516 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
518 INIT_REG_SET (&spilled_pseudos);
519 INIT_REG_SET (&pseudos_counted);
522 /* List of insn chains that are currently unused. */
523 static struct insn_chain *unused_insn_chains = 0;
525 /* Allocate an empty insn_chain structure. */
529 struct insn_chain *c;
531 if (unused_insn_chains == 0)
533 c = (struct insn_chain *)
534 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
535 INIT_REG_SET (&c->live_throughout);
536 INIT_REG_SET (&c->dead_or_set);
540 c = unused_insn_chains;
541 unused_insn_chains = c->next;
543 c->is_caller_save_insn = 0;
544 c->need_operand_change = 0;
550 /* Small utility function to set all regs in hard reg set TO which are
551 allocated to pseudos in regset FROM. */
554 compute_use_by_pseudos (to, from)
560 EXECUTE_IF_SET_IN_REG_SET
561 (from, FIRST_PSEUDO_REGISTER, regno,
563 int r = reg_renumber[regno];
568 /* reload_combine uses the information from
569 BASIC_BLOCK->global_live_at_start, which might still
570 contain registers that have not actually been allocated
571 since they have an equivalence. */
572 if (! reload_completed)
577 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
579 SET_HARD_REG_BIT (*to, r + nregs);
584 /* Replace all pseudos found in LOC with their corresponding
588 replace_pseudos_in_call_usage (loc, mem_mode, usage)
590 enum machine_mode mem_mode;
604 if (REGNO (x) < FIRST_PSEUDO_REGISTER)
607 x = eliminate_regs (x, mem_mode, usage);
611 replace_pseudos_in_call_usage (loc, mem_mode, usage);
615 if (reg_renumber [REGNO (x)] < 0)
616 *loc = regno_reg_rtx[REGNO (x)];
617 else if (reg_equiv_mem[REGNO (x)])
618 *loc = reg_equiv_mem[REGNO (x)];
624 else if (code == MEM)
626 replace_pseudos_in_call_usage (& XEXP (x, 0), GET_MODE (x), usage);
630 /* Process each of our operands recursively. */
631 fmt = GET_RTX_FORMAT (code);
632 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
634 replace_pseudos_in_call_usage (&XEXP (x, i), mem_mode, usage);
635 else if (*fmt == 'E')
636 for (j = 0; j < XVECLEN (x, i); j++)
637 replace_pseudos_in_call_usage (& XVECEXP (x, i, j), mem_mode, usage);
641 /* Global variables used by reload and its subroutines. */
643 /* Set during calculate_needs if an insn needs register elimination. */
644 static int something_needs_elimination;
645 /* Set during calculate_needs if an insn needs an operand changed. */
646 int something_needs_operands_changed;
648 /* Nonzero means we couldn't get enough spill regs. */
651 /* Main entry point for the reload pass.
653 FIRST is the first insn of the function being compiled.
655 GLOBAL nonzero means we were called from global_alloc
656 and should attempt to reallocate any pseudoregs that we
657 displace from hard regs we will use for reloads.
658 If GLOBAL is zero, we do not have enough information to do that,
659 so any pseudo reg that is spilled must go to the stack.
661 Return value is nonzero if reload failed
662 and we must not do any more for this function. */
665 reload (first, global)
671 register struct elim_table *ep;
673 /* The two pointers used to track the true location of the memory used
674 for label offsets. */
675 char *real_known_ptr = NULL_PTR;
676 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
678 /* Make sure even insns with volatile mem refs are recognizable. */
683 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
685 /* Make sure that the last insn in the chain
686 is not something that needs reloading. */
687 emit_note (NULL_PTR, NOTE_INSN_DELETED);
689 /* Enable find_equiv_reg to distinguish insns made by reload. */
690 reload_first_uid = get_max_uid ();
692 #ifdef SECONDARY_MEMORY_NEEDED
693 /* Initialize the secondary memory table. */
694 clear_secondary_mem ();
697 /* We don't have a stack slot for any spill reg yet. */
698 memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot);
699 memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
701 /* Initialize the save area information for caller-save, in case some
705 /* Compute which hard registers are now in use
706 as homes for pseudo registers.
707 This is done here rather than (eg) in global_alloc
708 because this point is reached even if not optimizing. */
709 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
712 /* A function that receives a nonlocal goto must save all call-saved
714 if (current_function_has_nonlocal_label)
715 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
716 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
717 regs_ever_live[i] = 1;
719 /* Find all the pseudo registers that didn't get hard regs
720 but do have known equivalent constants or memory slots.
721 These include parameters (known equivalent to parameter slots)
722 and cse'd or loop-moved constant memory addresses.
724 Record constant equivalents in reg_equiv_constant
725 so they will be substituted by find_reloads.
726 Record memory equivalents in reg_mem_equiv so they can
727 be substituted eventually by altering the REG-rtx's. */
729 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
730 reg_equiv_memory_loc = (rtx *) xcalloc (max_regno, sizeof (rtx));
731 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
732 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
733 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
734 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
735 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
736 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
737 pseudo_forbidden_regs
738 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
740 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
742 CLEAR_HARD_REG_SET (bad_spill_regs_global);
744 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
745 Also find all paradoxical subregs and find largest such for each pseudo.
746 On machines with small register classes, record hard registers that
747 are used for user variables. These can never be used for spills.
748 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
749 caller-saved registers must be marked live. */
751 num_eliminable_invariants = 0;
752 for (insn = first; insn; insn = NEXT_INSN (insn))
754 rtx set = single_set (insn);
756 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
757 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
758 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
759 if (! call_used_regs[i])
760 regs_ever_live[i] = 1;
762 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
764 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
766 #ifdef LEGITIMATE_PIC_OPERAND_P
767 && (! function_invariant_p (XEXP (note, 0))
769 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
773 rtx x = XEXP (note, 0);
774 i = REGNO (SET_DEST (set));
775 if (i > LAST_VIRTUAL_REGISTER)
777 if (GET_CODE (x) == MEM)
779 /* If the operand is a PLUS, the MEM may be shared,
780 so make sure we have an unshared copy here. */
781 if (GET_CODE (XEXP (x, 0)) == PLUS)
784 reg_equiv_memory_loc[i] = x;
786 else if (function_invariant_p (x))
788 if (GET_CODE (x) == PLUS)
790 /* This is PLUS of frame pointer and a constant,
791 and might be shared. Unshare it. */
792 reg_equiv_constant[i] = copy_rtx (x);
793 num_eliminable_invariants++;
795 else if (x == frame_pointer_rtx
796 || x == arg_pointer_rtx)
798 reg_equiv_constant[i] = x;
799 num_eliminable_invariants++;
801 else if (LEGITIMATE_CONSTANT_P (x))
802 reg_equiv_constant[i] = x;
804 reg_equiv_memory_loc[i]
805 = force_const_mem (GET_MODE (SET_DEST (set)), x);
810 /* If this register is being made equivalent to a MEM
811 and the MEM is not SET_SRC, the equivalencing insn
812 is one with the MEM as a SET_DEST and it occurs later.
813 So don't mark this insn now. */
814 if (GET_CODE (x) != MEM
815 || rtx_equal_p (SET_SRC (set), x))
817 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
822 /* If this insn is setting a MEM from a register equivalent to it,
823 this is the equivalencing insn. */
824 else if (set && GET_CODE (SET_DEST (set)) == MEM
825 && GET_CODE (SET_SRC (set)) == REG
826 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
827 && rtx_equal_p (SET_DEST (set),
828 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
829 reg_equiv_init[REGNO (SET_SRC (set))]
830 = gen_rtx_INSN_LIST (VOIDmode, insn,
831 reg_equiv_init[REGNO (SET_SRC (set))]);
834 scan_paradoxical_subregs (PATTERN (insn));
839 num_labels = max_label_num () - get_first_label_num ();
841 /* Allocate the tables used to store offset information at labels. */
842 /* We used to use alloca here, but the size of what it would try to
843 allocate would occasionally cause it to exceed the stack limit and
844 cause a core dump. */
845 real_known_ptr = xmalloc (num_labels);
847 = (int (*)[NUM_ELIMINABLE_REGS])
848 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
850 offsets_known_at = real_known_ptr - get_first_label_num ();
852 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
854 /* Alter each pseudo-reg rtx to contain its hard reg number.
855 Assign stack slots to the pseudos that lack hard regs or equivalents.
856 Do not touch virtual registers. */
858 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
861 /* If we have some registers we think can be eliminated, scan all insns to
862 see if there is an insn that sets one of these registers to something
863 other than itself plus a constant. If so, the register cannot be
864 eliminated. Doing this scan here eliminates an extra pass through the
865 main reload loop in the most common case where register elimination
867 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
868 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
869 || GET_CODE (insn) == CALL_INSN)
870 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
872 maybe_fix_stack_asms ();
874 insns_need_reload = 0;
875 something_needs_elimination = 0;
877 /* Initialize to -1, which means take the first spill register. */
880 /* Spill any hard regs that we know we can't eliminate. */
881 CLEAR_HARD_REG_SET (used_spill_regs);
882 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
883 if (! ep->can_eliminate)
884 spill_hard_reg (ep->from, 1);
886 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
887 if (frame_pointer_needed)
888 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
890 finish_spills (global);
892 /* From now on, we may need to generate moves differently. We may also
893 allow modifications of insns which cause them to not be recognized.
894 Any such modifications will be cleaned up during reload itself. */
895 reload_in_progress = 1;
897 /* This loop scans the entire function each go-round
898 and repeats until one repetition spills no additional hard regs. */
901 int something_changed;
904 HOST_WIDE_INT starting_frame_size;
906 /* Round size of stack frame to stack_alignment_needed. This must be done
907 here because the stack size may be a part of the offset computation
908 for register elimination, and there might have been new stack slots
909 created in the last iteration of this loop. */
910 if (cfun->stack_alignment_needed)
911 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
913 starting_frame_size = get_frame_size ();
915 set_initial_elim_offsets ();
916 set_initial_label_offsets ();
918 /* For each pseudo register that has an equivalent location defined,
919 try to eliminate any eliminable registers (such as the frame pointer)
920 assuming initial offsets for the replacement register, which
923 If the resulting location is directly addressable, substitute
924 the MEM we just got directly for the old REG.
926 If it is not addressable but is a constant or the sum of a hard reg
927 and constant, it is probably not addressable because the constant is
928 out of range, in that case record the address; we will generate
929 hairy code to compute the address in a register each time it is
930 needed. Similarly if it is a hard register, but one that is not
931 valid as an address register.
933 If the location is not addressable, but does not have one of the
934 above forms, assign a stack slot. We have to do this to avoid the
935 potential of producing lots of reloads if, e.g., a location involves
936 a pseudo that didn't get a hard register and has an equivalent memory
937 location that also involves a pseudo that didn't get a hard register.
939 Perhaps at some point we will improve reload_when_needed handling
940 so this problem goes away. But that's very hairy. */
942 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
943 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
945 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
947 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
949 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
950 else if (CONSTANT_P (XEXP (x, 0))
951 || (GET_CODE (XEXP (x, 0)) == REG
952 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
953 || (GET_CODE (XEXP (x, 0)) == PLUS
954 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
955 && (REGNO (XEXP (XEXP (x, 0), 0))
956 < FIRST_PSEUDO_REGISTER)
957 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
958 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
961 /* Make a new stack slot. Then indicate that something
962 changed so we go back and recompute offsets for
963 eliminable registers because the allocation of memory
964 below might change some offset. reg_equiv_{mem,address}
965 will be set up for this pseudo on the next pass around
967 reg_equiv_memory_loc[i] = 0;
968 reg_equiv_init[i] = 0;
973 if (caller_save_needed)
976 /* If we allocated another stack slot, redo elimination bookkeeping. */
977 if (starting_frame_size != get_frame_size ())
980 if (caller_save_needed)
982 save_call_clobbered_regs ();
983 /* That might have allocated new insn_chain structures. */
984 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
987 calculate_needs_all_insns (global);
989 CLEAR_REG_SET (&spilled_pseudos);
992 something_changed = 0;
994 /* If we allocated any new memory locations, make another pass
995 since it might have changed elimination offsets. */
996 if (starting_frame_size != get_frame_size ())
997 something_changed = 1;
1000 HARD_REG_SET to_spill;
1001 CLEAR_HARD_REG_SET (to_spill);
1002 update_eliminables (&to_spill);
1003 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1004 if (TEST_HARD_REG_BIT (to_spill, i))
1006 spill_hard_reg (i, 1);
1009 /* Regardless of the state of spills, if we previously had
1010 a register that we thought we could eliminate, but no can
1011 not eliminate, we must run another pass.
1013 Consider pseudos which have an entry in reg_equiv_* which
1014 reference an eliminable register. We must make another pass
1015 to update reg_equiv_* so that we do not substitute in the
1016 old value from when we thought the elimination could be
1018 something_changed = 1;
1022 select_reload_regs ();
1026 if (insns_need_reload != 0 || did_spill)
1027 something_changed |= finish_spills (global);
1029 if (! something_changed)
1032 if (caller_save_needed)
1033 delete_caller_save_insns ();
1035 obstack_free (&reload_obstack, reload_firstobj);
1038 /* If global-alloc was run, notify it of any register eliminations we have
1041 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1042 if (ep->can_eliminate)
1043 mark_elimination (ep->from, ep->to);
1045 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1046 If that insn didn't set the register (i.e., it copied the register to
1047 memory), just delete that insn instead of the equivalencing insn plus
1048 anything now dead. If we call delete_dead_insn on that insn, we may
1049 delete the insn that actually sets the register if the register dies
1050 there and that is incorrect. */
1052 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1054 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1057 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1059 rtx equiv_insn = XEXP (list, 0);
1060 if (GET_CODE (equiv_insn) == NOTE)
1062 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1063 delete_dead_insn (equiv_insn);
1066 PUT_CODE (equiv_insn, NOTE);
1067 NOTE_SOURCE_FILE (equiv_insn) = 0;
1068 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1074 /* Use the reload registers where necessary
1075 by generating move instructions to move the must-be-register
1076 values into or out of the reload registers. */
1078 if (insns_need_reload != 0 || something_needs_elimination
1079 || something_needs_operands_changed)
1081 HOST_WIDE_INT old_frame_size = get_frame_size ();
1083 reload_as_needed (global);
1085 if (old_frame_size != get_frame_size ())
1089 verify_initial_elim_offsets ();
1092 /* If we were able to eliminate the frame pointer, show that it is no
1093 longer live at the start of any basic block. If it ls live by
1094 virtue of being in a pseudo, that pseudo will be marked live
1095 and hence the frame pointer will be known to be live via that
1098 if (! frame_pointer_needed)
1099 for (i = 0; i < n_basic_blocks; i++)
1100 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1101 HARD_FRAME_POINTER_REGNUM);
1103 /* Come here (with failure set nonzero) if we can't get enough spill regs
1104 and we decide not to abort about it. */
1107 CLEAR_REG_SET (&spilled_pseudos);
1108 reload_in_progress = 0;
1110 /* Now eliminate all pseudo regs by modifying them into
1111 their equivalent memory references.
1112 The REG-rtx's for the pseudos are modified in place,
1113 so all insns that used to refer to them now refer to memory.
1115 For a reg that has a reg_equiv_address, all those insns
1116 were changed by reloading so that no insns refer to it any longer;
1117 but the DECL_RTL of a variable decl may refer to it,
1118 and if so this causes the debugging info to mention the variable. */
1120 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1125 int is_readonly = 0;
1127 if (reg_equiv_memory_loc[i])
1129 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1130 is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]);
1131 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1134 if (reg_equiv_mem[i])
1135 addr = XEXP (reg_equiv_mem[i], 0);
1137 if (reg_equiv_address[i])
1138 addr = reg_equiv_address[i];
1142 if (reg_renumber[i] < 0)
1144 rtx reg = regno_reg_rtx[i];
1145 PUT_CODE (reg, MEM);
1146 XEXP (reg, 0) = addr;
1147 REG_USERVAR_P (reg) = 0;
1148 RTX_UNCHANGING_P (reg) = is_readonly;
1149 MEM_IN_STRUCT_P (reg) = in_struct;
1150 MEM_SCALAR_P (reg) = is_scalar;
1151 /* We have no alias information about this newly created
1153 MEM_ALIAS_SET (reg) = 0;
1155 else if (reg_equiv_mem[i])
1156 XEXP (reg_equiv_mem[i], 0) = addr;
1160 /* We must set reload_completed now since the cleanup_subreg_operands call
1161 below will re-recognize each insn and reload may have generated insns
1162 which are only valid during and after reload. */
1163 reload_completed = 1;
1165 /* Make a pass over all the insns and delete all USEs which we inserted
1166 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1167 notes. Delete all CLOBBER insns that don't refer to the return value
1168 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1169 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1170 and regenerate REG_INC notes that may have been moved around. */
1172 for (insn = first; insn; insn = NEXT_INSN (insn))
1177 if (GET_CODE (insn) == CALL_INSN)
1178 replace_pseudos_in_call_usage (& CALL_INSN_FUNCTION_USAGE (insn),
1180 CALL_INSN_FUNCTION_USAGE (insn));
1182 if ((GET_CODE (PATTERN (insn)) == USE
1183 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1184 || (GET_CODE (PATTERN (insn)) == CLOBBER
1185 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1186 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1188 PUT_CODE (insn, NOTE);
1189 NOTE_SOURCE_FILE (insn) = 0;
1190 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1194 pnote = ®_NOTES (insn);
1197 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1198 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1199 || REG_NOTE_KIND (*pnote) == REG_INC
1200 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1201 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1202 *pnote = XEXP (*pnote, 1);
1204 pnote = &XEXP (*pnote, 1);
1208 add_auto_inc_notes (insn, PATTERN (insn));
1211 /* And simplify (subreg (reg)) if it appears as an operand. */
1212 cleanup_subreg_operands (insn);
1215 /* If we are doing stack checking, give a warning if this function's
1216 frame size is larger than we expect. */
1217 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1219 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1220 static int verbose_warned = 0;
1222 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1223 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1224 size += UNITS_PER_WORD;
1226 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1228 warning ("frame size too large for reliable stack checking");
1229 if (! verbose_warned)
1231 warning ("try reducing the number of local variables");
1237 /* Indicate that we no longer have known memory locations or constants. */
1238 if (reg_equiv_constant)
1239 free (reg_equiv_constant);
1240 reg_equiv_constant = 0;
1241 if (reg_equiv_memory_loc)
1242 free (reg_equiv_memory_loc);
1243 reg_equiv_memory_loc = 0;
1246 free (real_known_ptr);
1250 free (reg_equiv_mem);
1251 free (reg_equiv_init);
1252 free (reg_equiv_address);
1253 free (reg_max_ref_width);
1254 free (reg_old_renumber);
1255 free (pseudo_previous_regs);
1256 free (pseudo_forbidden_regs);
1258 CLEAR_HARD_REG_SET (used_spill_regs);
1259 for (i = 0; i < n_spills; i++)
1260 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1262 /* Free all the insn_chain structures at once. */
1263 obstack_free (&reload_obstack, reload_startobj);
1264 unused_insn_chains = 0;
1269 /* Yet another special case. Unfortunately, reg-stack forces people to
1270 write incorrect clobbers in asm statements. These clobbers must not
1271 cause the register to appear in bad_spill_regs, otherwise we'll call
1272 fatal_insn later. We clear the corresponding regnos in the live
1273 register sets to avoid this.
1274 The whole thing is rather sick, I'm afraid. */
1277 maybe_fix_stack_asms ()
1280 const char *constraints[MAX_RECOG_OPERANDS];
1281 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1282 struct insn_chain *chain;
1284 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1287 HARD_REG_SET clobbered, allowed;
1290 if (! INSN_P (chain->insn)
1291 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1293 pat = PATTERN (chain->insn);
1294 if (GET_CODE (pat) != PARALLEL)
1297 CLEAR_HARD_REG_SET (clobbered);
1298 CLEAR_HARD_REG_SET (allowed);
1300 /* First, make a mask of all stack regs that are clobbered. */
1301 for (i = 0; i < XVECLEN (pat, 0); i++)
1303 rtx t = XVECEXP (pat, 0, i);
1304 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1305 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1308 /* Get the operand values and constraints out of the insn. */
1309 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1310 constraints, operand_mode);
1312 /* For every operand, see what registers are allowed. */
1313 for (i = 0; i < noperands; i++)
1315 const char *p = constraints[i];
1316 /* For every alternative, we compute the class of registers allowed
1317 for reloading in CLS, and merge its contents into the reg set
1319 int cls = (int) NO_REGS;
1325 if (c == '\0' || c == ',' || c == '#')
1327 /* End of one alternative - mark the regs in the current
1328 class, and reset the class. */
1329 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1334 } while (c != '\0' && c != ',');
1342 case '=': case '+': case '*': case '%': case '?': case '!':
1343 case '0': case '1': case '2': case '3': case '4': case 'm':
1344 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1345 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1346 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1351 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1356 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1360 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1365 /* Those of the registers which are clobbered, but allowed by the
1366 constraints, must be usable as reload registers. So clear them
1367 out of the life information. */
1368 AND_HARD_REG_SET (allowed, clobbered);
1369 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1370 if (TEST_HARD_REG_BIT (allowed, i))
1372 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1373 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1380 /* Copy the global variables n_reloads and rld into the corresponding elts
1383 copy_reloads (chain)
1384 struct insn_chain *chain;
1386 chain->n_reloads = n_reloads;
1388 = (struct reload *) obstack_alloc (&reload_obstack,
1389 n_reloads * sizeof (struct reload));
1390 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1391 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1394 /* Walk the chain of insns, and determine for each whether it needs reloads
1395 and/or eliminations. Build the corresponding insns_need_reload list, and
1396 set something_needs_elimination as appropriate. */
1398 calculate_needs_all_insns (global)
1401 struct insn_chain **pprev_reload = &insns_need_reload;
1402 struct insn_chain *chain, *next = 0;
1404 something_needs_elimination = 0;
1406 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1407 for (chain = reload_insn_chain; chain != 0; chain = next)
1409 rtx insn = chain->insn;
1413 /* Clear out the shortcuts. */
1414 chain->n_reloads = 0;
1415 chain->need_elim = 0;
1416 chain->need_reload = 0;
1417 chain->need_operand_change = 0;
1419 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1420 include REG_LABEL), we need to see what effects this has on the
1421 known offsets at labels. */
1423 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1424 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1425 set_label_offsets (insn, insn, 0);
1429 rtx old_body = PATTERN (insn);
1430 int old_code = INSN_CODE (insn);
1431 rtx old_notes = REG_NOTES (insn);
1432 int did_elimination = 0;
1433 int operands_changed = 0;
1434 rtx set = single_set (insn);
1436 /* Skip insns that only set an equivalence. */
1437 if (set && GET_CODE (SET_DEST (set)) == REG
1438 && reg_renumber[REGNO (SET_DEST (set))] < 0
1439 && reg_equiv_constant[REGNO (SET_DEST (set))])
1442 /* If needed, eliminate any eliminable registers. */
1443 if (num_eliminable || num_eliminable_invariants)
1444 did_elimination = eliminate_regs_in_insn (insn, 0);
1446 /* Analyze the instruction. */
1447 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1448 global, spill_reg_order);
1450 /* If a no-op set needs more than one reload, this is likely
1451 to be something that needs input address reloads. We
1452 can't get rid of this cleanly later, and it is of no use
1453 anyway, so discard it now.
1454 We only do this when expensive_optimizations is enabled,
1455 since this complements reload inheritance / output
1456 reload deletion, and it can make debugging harder. */
1457 if (flag_expensive_optimizations && n_reloads > 1)
1459 rtx set = single_set (insn);
1461 && SET_SRC (set) == SET_DEST (set)
1462 && GET_CODE (SET_SRC (set)) == REG
1463 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1465 PUT_CODE (insn, NOTE);
1466 NOTE_SOURCE_FILE (insn) = 0;
1467 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1468 /* Delete it from the reload chain */
1470 chain->prev->next = next;
1472 reload_insn_chain = next;
1474 next->prev = chain->prev;
1475 chain->next = unused_insn_chains;
1476 unused_insn_chains = chain;
1481 update_eliminable_offsets ();
1483 /* Remember for later shortcuts which insns had any reloads or
1484 register eliminations. */
1485 chain->need_elim = did_elimination;
1486 chain->need_reload = n_reloads > 0;
1487 chain->need_operand_change = operands_changed;
1489 /* Discard any register replacements done. */
1490 if (did_elimination)
1492 obstack_free (&reload_obstack, reload_insn_firstobj);
1493 PATTERN (insn) = old_body;
1494 INSN_CODE (insn) = old_code;
1495 REG_NOTES (insn) = old_notes;
1496 something_needs_elimination = 1;
1499 something_needs_operands_changed |= operands_changed;
1503 copy_reloads (chain);
1504 *pprev_reload = chain;
1505 pprev_reload = &chain->next_need_reload;
1512 /* Comparison function for qsort to decide which of two reloads
1513 should be handled first. *P1 and *P2 are the reload numbers. */
1516 reload_reg_class_lower (r1p, r2p)
1520 register int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1523 /* Consider required reloads before optional ones. */
1524 t = rld[r1].optional - rld[r2].optional;
1528 /* Count all solitary classes before non-solitary ones. */
1529 t = ((reg_class_size[(int) rld[r2].class] == 1)
1530 - (reg_class_size[(int) rld[r1].class] == 1));
1534 /* Aside from solitaires, consider all multi-reg groups first. */
1535 t = rld[r2].nregs - rld[r1].nregs;
1539 /* Consider reloads in order of increasing reg-class number. */
1540 t = (int) rld[r1].class - (int) rld[r2].class;
1544 /* If reloads are equally urgent, sort by reload number,
1545 so that the results of qsort leave nothing to chance. */
1549 /* The cost of spilling each hard reg. */
1550 static int spill_cost[FIRST_PSEUDO_REGISTER];
1552 /* When spilling multiple hard registers, we use SPILL_COST for the first
1553 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1554 only the first hard reg for a multi-reg pseudo. */
1555 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1557 /* Update the spill cost arrays, considering that pseudo REG is live. */
1563 int n_refs = REG_N_REFS (reg);
1564 int r = reg_renumber[reg];
1567 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1568 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1571 SET_REGNO_REG_SET (&pseudos_counted, reg);
1576 spill_add_cost[r] += n_refs;
1578 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1580 spill_cost[r + nregs] += n_refs;
1583 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1584 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1587 order_regs_for_reload (chain)
1588 struct insn_chain *chain;
1591 HARD_REG_SET used_by_pseudos;
1592 HARD_REG_SET used_by_pseudos2;
1594 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1596 memset (spill_cost, 0, sizeof spill_cost);
1597 memset (spill_add_cost, 0, sizeof spill_add_cost);
1599 /* Count number of uses of each hard reg by pseudo regs allocated to it
1600 and then order them by decreasing use. First exclude hard registers
1601 that are live in or across this insn. */
1603 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1604 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1605 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1606 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1608 /* Now find out which pseudos are allocated to it, and update
1610 CLEAR_REG_SET (&pseudos_counted);
1612 EXECUTE_IF_SET_IN_REG_SET
1613 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1617 EXECUTE_IF_SET_IN_REG_SET
1618 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1622 CLEAR_REG_SET (&pseudos_counted);
1625 /* Vector of reload-numbers showing the order in which the reloads should
1627 static short reload_order[MAX_RELOADS];
1629 /* This is used to keep track of the spill regs used in one insn. */
1630 static HARD_REG_SET used_spill_regs_local;
1632 /* We decided to spill hard register SPILLED, which has a size of
1633 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1634 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1635 update SPILL_COST/SPILL_ADD_COST. */
1638 count_spilled_pseudo (spilled, spilled_nregs, reg)
1639 int spilled, spilled_nregs, reg;
1641 int r = reg_renumber[reg];
1642 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1644 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1645 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1648 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1650 spill_add_cost[r] -= REG_N_REFS (reg);
1652 spill_cost[r + nregs] -= REG_N_REFS (reg);
1655 /* Find reload register to use for reload number ORDER. */
1658 find_reg (chain, order)
1659 struct insn_chain *chain;
1662 int rnum = reload_order[order];
1663 struct reload *rl = rld + rnum;
1664 int best_cost = INT_MAX;
1668 HARD_REG_SET not_usable;
1669 HARD_REG_SET used_by_other_reload;
1671 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1672 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1673 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1675 CLEAR_HARD_REG_SET (used_by_other_reload);
1676 for (k = 0; k < order; k++)
1678 int other = reload_order[k];
1680 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1681 for (j = 0; j < rld[other].nregs; j++)
1682 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1685 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1687 unsigned int regno = i;
1689 if (! TEST_HARD_REG_BIT (not_usable, regno)
1690 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1691 && HARD_REGNO_MODE_OK (regno, rl->mode))
1693 int this_cost = spill_cost[regno];
1695 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1697 for (j = 1; j < this_nregs; j++)
1699 this_cost += spill_add_cost[regno + j];
1700 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1701 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1706 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1708 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1710 if (this_cost < best_cost
1711 /* Among registers with equal cost, prefer caller-saved ones, or
1712 use REG_ALLOC_ORDER if it is defined. */
1713 || (this_cost == best_cost
1714 #ifdef REG_ALLOC_ORDER
1715 && (inv_reg_alloc_order[regno]
1716 < inv_reg_alloc_order[best_reg])
1718 && call_used_regs[regno]
1719 && ! call_used_regs[best_reg]
1724 best_cost = this_cost;
1732 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1734 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1735 rl->regno = best_reg;
1737 EXECUTE_IF_SET_IN_REG_SET
1738 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1740 count_spilled_pseudo (best_reg, rl->nregs, j);
1743 EXECUTE_IF_SET_IN_REG_SET
1744 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1746 count_spilled_pseudo (best_reg, rl->nregs, j);
1749 for (i = 0; i < rl->nregs; i++)
1751 if (spill_cost[best_reg + i] != 0
1752 || spill_add_cost[best_reg + i] != 0)
1754 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1759 /* Find more reload regs to satisfy the remaining need of an insn, which
1761 Do it by ascending class number, since otherwise a reg
1762 might be spilled for a big class and might fail to count
1763 for a smaller class even though it belongs to that class. */
1766 find_reload_regs (chain)
1767 struct insn_chain *chain;
1771 /* In order to be certain of getting the registers we need,
1772 we must sort the reloads into order of increasing register class.
1773 Then our grabbing of reload registers will parallel the process
1774 that provided the reload registers. */
1775 for (i = 0; i < chain->n_reloads; i++)
1777 /* Show whether this reload already has a hard reg. */
1778 if (chain->rld[i].reg_rtx)
1780 int regno = REGNO (chain->rld[i].reg_rtx);
1781 chain->rld[i].regno = regno;
1783 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1786 chain->rld[i].regno = -1;
1787 reload_order[i] = i;
1790 n_reloads = chain->n_reloads;
1791 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1793 CLEAR_HARD_REG_SET (used_spill_regs_local);
1796 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1798 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1800 /* Compute the order of preference for hard registers to spill. */
1802 order_regs_for_reload (chain);
1804 for (i = 0; i < n_reloads; i++)
1806 int r = reload_order[i];
1808 /* Ignore reloads that got marked inoperative. */
1809 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1810 && ! rld[r].optional
1811 && rld[r].regno == -1)
1812 if (! find_reg (chain, i))
1814 spill_failure (chain->insn, rld[r].class);
1820 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1821 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1823 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1827 select_reload_regs ()
1829 struct insn_chain *chain;
1831 /* Try to satisfy the needs for each insn. */
1832 for (chain = insns_need_reload; chain != 0;
1833 chain = chain->next_need_reload)
1834 find_reload_regs (chain);
1837 /* Delete all insns that were inserted by emit_caller_save_insns during
1840 delete_caller_save_insns ()
1842 struct insn_chain *c = reload_insn_chain;
1846 while (c != 0 && c->is_caller_save_insn)
1848 struct insn_chain *next = c->next;
1851 if (insn == BLOCK_HEAD (c->block))
1852 BLOCK_HEAD (c->block) = NEXT_INSN (insn);
1853 if (insn == BLOCK_END (c->block))
1854 BLOCK_END (c->block) = PREV_INSN (insn);
1855 if (c == reload_insn_chain)
1856 reload_insn_chain = next;
1858 if (NEXT_INSN (insn) != 0)
1859 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
1860 if (PREV_INSN (insn) != 0)
1861 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
1864 next->prev = c->prev;
1866 c->prev->next = next;
1867 c->next = unused_insn_chains;
1868 unused_insn_chains = c;
1876 /* Handle the failure to find a register to spill.
1877 INSN should be one of the insns which needed this particular spill reg. */
1880 spill_failure (insn, class)
1882 enum reg_class class;
1884 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1885 if (asm_noperands (PATTERN (insn)) >= 0)
1886 error_for_asm (insn, "Can't find a register in class `%s' while reloading `asm'.",
1887 reg_class_names[class]);
1890 error ("Unable to find a register to spill in class `%s'.",
1891 reg_class_names[class]);
1892 fatal_insn ("This is the insn:", insn);
1896 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1897 data that is dead in INSN. */
1900 delete_dead_insn (insn)
1903 rtx prev = prev_real_insn (insn);
1906 /* If the previous insn sets a register that dies in our insn, delete it
1908 if (prev && GET_CODE (PATTERN (prev)) == SET
1909 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1910 && reg_mentioned_p (prev_dest, PATTERN (insn))
1911 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1912 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1913 delete_dead_insn (prev);
1915 PUT_CODE (insn, NOTE);
1916 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1917 NOTE_SOURCE_FILE (insn) = 0;
1920 /* Modify the home of pseudo-reg I.
1921 The new home is present in reg_renumber[I].
1923 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1924 or it may be -1, meaning there is none or it is not relevant.
1925 This is used so that all pseudos spilled from a given hard reg
1926 can share one stack slot. */
1929 alter_reg (i, from_reg)
1933 /* When outputting an inline function, this can happen
1934 for a reg that isn't actually used. */
1935 if (regno_reg_rtx[i] == 0)
1938 /* If the reg got changed to a MEM at rtl-generation time,
1940 if (GET_CODE (regno_reg_rtx[i]) != REG)
1943 /* Modify the reg-rtx to contain the new hard reg
1944 number or else to contain its pseudo reg number. */
1945 REGNO (regno_reg_rtx[i])
1946 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1948 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1949 allocate a stack slot for it. */
1951 if (reg_renumber[i] < 0
1952 && REG_N_REFS (i) > 0
1953 && reg_equiv_constant[i] == 0
1954 && reg_equiv_memory_loc[i] == 0)
1957 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1958 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1961 /* Each pseudo reg has an inherent size which comes from its own mode,
1962 and a total size which provides room for paradoxical subregs
1963 which refer to the pseudo reg in wider modes.
1965 We can use a slot already allocated if it provides both
1966 enough inherent space and enough total space.
1967 Otherwise, we allocate a new slot, making sure that it has no less
1968 inherent space, and no less total space, then the previous slot. */
1971 /* No known place to spill from => no slot to reuse. */
1972 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1973 inherent_size == total_size ? 0 : -1);
1974 if (BYTES_BIG_ENDIAN)
1975 /* Cancel the big-endian correction done in assign_stack_local.
1976 Get the address of the beginning of the slot.
1977 This is so we can do a big-endian correction unconditionally
1979 adjust = inherent_size - total_size;
1981 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1983 /* Nothing can alias this slot except this pseudo. */
1984 MEM_ALIAS_SET (x) = new_alias_set ();
1987 /* Reuse a stack slot if possible. */
1988 else if (spill_stack_slot[from_reg] != 0
1989 && spill_stack_slot_width[from_reg] >= total_size
1990 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1992 x = spill_stack_slot[from_reg];
1994 /* Allocate a bigger slot. */
1997 /* Compute maximum size needed, both for inherent size
1998 and for total size. */
1999 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2002 if (spill_stack_slot[from_reg])
2004 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2006 mode = GET_MODE (spill_stack_slot[from_reg]);
2007 if (spill_stack_slot_width[from_reg] > total_size)
2008 total_size = spill_stack_slot_width[from_reg];
2011 /* Make a slot with that size. */
2012 x = assign_stack_local (mode, total_size,
2013 inherent_size == total_size ? 0 : -1);
2016 /* All pseudos mapped to this slot can alias each other. */
2017 if (spill_stack_slot[from_reg])
2018 MEM_ALIAS_SET (x) = MEM_ALIAS_SET (spill_stack_slot[from_reg]);
2020 MEM_ALIAS_SET (x) = new_alias_set ();
2022 if (BYTES_BIG_ENDIAN)
2024 /* Cancel the big-endian correction done in assign_stack_local.
2025 Get the address of the beginning of the slot.
2026 This is so we can do a big-endian correction unconditionally
2028 adjust = GET_MODE_SIZE (mode) - total_size;
2030 stack_slot = gen_rtx_MEM (mode_for_size (total_size
2033 plus_constant (XEXP (x, 0), adjust));
2036 spill_stack_slot[from_reg] = stack_slot;
2037 spill_stack_slot_width[from_reg] = total_size;
2040 /* On a big endian machine, the "address" of the slot
2041 is the address of the low part that fits its inherent mode. */
2042 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2043 adjust += (total_size - inherent_size);
2045 /* If we have any adjustment to make, or if the stack slot is the
2046 wrong mode, make a new stack slot. */
2047 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2049 rtx new = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
2050 plus_constant (XEXP (x, 0), adjust));
2052 MEM_COPY_ATTRIBUTES (new, x);
2056 /* Save the stack slot for later. */
2057 reg_equiv_memory_loc[i] = x;
2061 /* Mark the slots in regs_ever_live for the hard regs
2062 used by pseudo-reg number REGNO. */
2065 mark_home_live (regno)
2068 register int i, lim;
2070 i = reg_renumber[regno];
2073 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2075 regs_ever_live[i++] = 1;
2078 /* This function handles the tracking of elimination offsets around branches.
2080 X is a piece of RTL being scanned.
2082 INSN is the insn that it came from, if any.
2084 INITIAL_P is non-zero if we are to set the offset to be the initial
2085 offset and zero if we are setting the offset of the label to be the
2089 set_label_offsets (x, insn, initial_p)
2094 enum rtx_code code = GET_CODE (x);
2097 struct elim_table *p;
2102 if (LABEL_REF_NONLOCAL_P (x))
2107 /* ... fall through ... */
2110 /* If we know nothing about this label, set the desired offsets. Note
2111 that this sets the offset at a label to be the offset before a label
2112 if we don't know anything about the label. This is not correct for
2113 the label after a BARRIER, but is the best guess we can make. If
2114 we guessed wrong, we will suppress an elimination that might have
2115 been possible had we been able to guess correctly. */
2117 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2119 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2120 offsets_at[CODE_LABEL_NUMBER (x)][i]
2121 = (initial_p ? reg_eliminate[i].initial_offset
2122 : reg_eliminate[i].offset);
2123 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2126 /* Otherwise, if this is the definition of a label and it is
2127 preceded by a BARRIER, set our offsets to the known offset of
2131 && (tem = prev_nonnote_insn (insn)) != 0
2132 && GET_CODE (tem) == BARRIER)
2133 set_offsets_for_label (insn);
2135 /* If neither of the above cases is true, compare each offset
2136 with those previously recorded and suppress any eliminations
2137 where the offsets disagree. */
2139 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2140 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2141 != (initial_p ? reg_eliminate[i].initial_offset
2142 : reg_eliminate[i].offset))
2143 reg_eliminate[i].can_eliminate = 0;
2148 set_label_offsets (PATTERN (insn), insn, initial_p);
2150 /* ... fall through ... */
2154 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2155 and hence must have all eliminations at their initial offsets. */
2156 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2157 if (REG_NOTE_KIND (tem) == REG_LABEL)
2158 set_label_offsets (XEXP (tem, 0), insn, 1);
2164 /* Each of the labels in the parallel or address vector must be
2165 at their initial offsets. We want the first field for PARALLEL
2166 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2168 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2169 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2174 /* We only care about setting PC. If the source is not RETURN,
2175 IF_THEN_ELSE, or a label, disable any eliminations not at
2176 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2177 isn't one of those possibilities. For branches to a label,
2178 call ourselves recursively.
2180 Note that this can disable elimination unnecessarily when we have
2181 a non-local goto since it will look like a non-constant jump to
2182 someplace in the current function. This isn't a significant
2183 problem since such jumps will normally be when all elimination
2184 pairs are back to their initial offsets. */
2186 if (SET_DEST (x) != pc_rtx)
2189 switch (GET_CODE (SET_SRC (x)))
2196 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2200 tem = XEXP (SET_SRC (x), 1);
2201 if (GET_CODE (tem) == LABEL_REF)
2202 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2203 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2206 tem = XEXP (SET_SRC (x), 2);
2207 if (GET_CODE (tem) == LABEL_REF)
2208 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2209 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2217 /* If we reach here, all eliminations must be at their initial
2218 offset because we are doing a jump to a variable address. */
2219 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2220 if (p->offset != p->initial_offset)
2221 p->can_eliminate = 0;
2229 /* Scan X and replace any eliminable registers (such as fp) with a
2230 replacement (such as sp), plus an offset.
2232 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2233 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2234 MEM, we are allowed to replace a sum of a register and the constant zero
2235 with the register, which we cannot do outside a MEM. In addition, we need
2236 to record the fact that a register is referenced outside a MEM.
2238 If INSN is an insn, it is the insn containing X. If we replace a REG
2239 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2240 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2241 the REG is being modified.
2243 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2244 That's used when we eliminate in expressions stored in notes.
2245 This means, do not set ref_outside_mem even if the reference
2248 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2249 replacements done assuming all offsets are at their initial values. If
2250 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2251 encounter, return the actual location so that find_reloads will do
2252 the proper thing. */
2255 eliminate_regs (x, mem_mode, insn)
2257 enum machine_mode mem_mode;
2260 enum rtx_code code = GET_CODE (x);
2261 struct elim_table *ep;
2268 if (! current_function_decl)
2287 /* This is only for the benefit of the debugging backends, which call
2288 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2289 removed after CSE. */
2290 new = eliminate_regs (XEXP (x, 0), 0, insn);
2291 if (GET_CODE (new) == MEM)
2292 return XEXP (new, 0);
2298 /* First handle the case where we encounter a bare register that
2299 is eliminable. Replace it with a PLUS. */
2300 if (regno < FIRST_PSEUDO_REGISTER)
2302 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2304 if (ep->from_rtx == x && ep->can_eliminate)
2305 return plus_constant (ep->to_rtx, ep->previous_offset);
2308 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2309 && reg_equiv_constant[regno]
2310 && ! CONSTANT_P (reg_equiv_constant[regno]))
2311 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2315 /* You might think handling MINUS in a manner similar to PLUS is a
2316 good idea. It is not. It has been tried multiple times and every
2317 time the change has had to have been reverted.
2319 Other parts of reload know a PLUS is special (gen_reload for example)
2320 and require special code to handle code a reloaded PLUS operand.
2322 Also consider backends where the flags register is clobbered by a
2323 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2324 lea instruction comes to mind). If we try to reload a MINUS, we
2325 may kill the flags register that was holding a useful value.
2327 So, please before trying to handle MINUS, consider reload as a
2328 whole instead of this little section as well as the backend issues. */
2330 /* If this is the sum of an eliminable register and a constant, rework
2332 if (GET_CODE (XEXP (x, 0)) == REG
2333 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2334 && CONSTANT_P (XEXP (x, 1)))
2336 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2338 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2340 /* The only time we want to replace a PLUS with a REG (this
2341 occurs when the constant operand of the PLUS is the negative
2342 of the offset) is when we are inside a MEM. We won't want
2343 to do so at other times because that would change the
2344 structure of the insn in a way that reload can't handle.
2345 We special-case the commonest situation in
2346 eliminate_regs_in_insn, so just replace a PLUS with a
2347 PLUS here, unless inside a MEM. */
2348 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2349 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2352 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2353 plus_constant (XEXP (x, 1),
2354 ep->previous_offset));
2357 /* If the register is not eliminable, we are done since the other
2358 operand is a constant. */
2362 /* If this is part of an address, we want to bring any constant to the
2363 outermost PLUS. We will do this by doing register replacement in
2364 our operands and seeing if a constant shows up in one of them.
2366 Note that there is no risk of modifying the structure of the insn,
2367 since we only get called for its operands, thus we are either
2368 modifying the address inside a MEM, or something like an address
2369 operand of a load-address insn. */
2372 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2373 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2375 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2377 /* If one side is a PLUS and the other side is a pseudo that
2378 didn't get a hard register but has a reg_equiv_constant,
2379 we must replace the constant here since it may no longer
2380 be in the position of any operand. */
2381 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2382 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2383 && reg_renumber[REGNO (new1)] < 0
2384 && reg_equiv_constant != 0
2385 && reg_equiv_constant[REGNO (new1)] != 0)
2386 new1 = reg_equiv_constant[REGNO (new1)];
2387 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2388 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2389 && reg_renumber[REGNO (new0)] < 0
2390 && reg_equiv_constant[REGNO (new0)] != 0)
2391 new0 = reg_equiv_constant[REGNO (new0)];
2393 new = form_sum (new0, new1);
2395 /* As above, if we are not inside a MEM we do not want to
2396 turn a PLUS into something else. We might try to do so here
2397 for an addition of 0 if we aren't optimizing. */
2398 if (! mem_mode && GET_CODE (new) != PLUS)
2399 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2407 /* If this is the product of an eliminable register and a
2408 constant, apply the distribute law and move the constant out
2409 so that we have (plus (mult ..) ..). This is needed in order
2410 to keep load-address insns valid. This case is pathological.
2411 We ignore the possibility of overflow here. */
2412 if (GET_CODE (XEXP (x, 0)) == REG
2413 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2414 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2415 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2417 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2420 /* Refs inside notes don't count for this purpose. */
2421 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2422 || GET_CODE (insn) == INSN_LIST)))
2423 ep->ref_outside_mem = 1;
2426 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2427 ep->previous_offset * INTVAL (XEXP (x, 1)));
2430 /* ... fall through ... */
2434 /* See comments before PLUS about handling MINUS. */
2436 case DIV: case UDIV:
2437 case MOD: case UMOD:
2438 case AND: case IOR: case XOR:
2439 case ROTATERT: case ROTATE:
2440 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2442 case GE: case GT: case GEU: case GTU:
2443 case LE: case LT: case LEU: case LTU:
2445 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2447 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2449 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2450 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2455 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2458 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2459 if (new != XEXP (x, 0))
2461 /* If this is a REG_DEAD note, it is not valid anymore.
2462 Using the eliminated version could result in creating a
2463 REG_DEAD note for the stack or frame pointer. */
2464 if (GET_MODE (x) == REG_DEAD)
2466 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2469 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2473 /* ... fall through ... */
2476 /* Now do eliminations in the rest of the chain. If this was
2477 an EXPR_LIST, this might result in allocating more memory than is
2478 strictly needed, but it simplifies the code. */
2481 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2482 if (new != XEXP (x, 1))
2483 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2491 case STRICT_LOW_PART:
2493 case SIGN_EXTEND: case ZERO_EXTEND:
2494 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2495 case FLOAT: case FIX:
2496 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2500 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2501 if (new != XEXP (x, 0))
2502 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2506 /* Similar to above processing, but preserve SUBREG_WORD.
2507 Convert (subreg (mem)) to (mem) if not paradoxical.
2508 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2509 pseudo didn't get a hard reg, we must replace this with the
2510 eliminated version of the memory location because push_reloads
2511 may do the replacement in certain circumstances. */
2512 if (GET_CODE (SUBREG_REG (x)) == REG
2513 && (GET_MODE_SIZE (GET_MODE (x))
2514 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2515 && reg_equiv_memory_loc != 0
2516 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2518 new = SUBREG_REG (x);
2521 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2523 if (new != XEXP (x, 0))
2525 int x_size = GET_MODE_SIZE (GET_MODE (x));
2526 int new_size = GET_MODE_SIZE (GET_MODE (new));
2528 if (GET_CODE (new) == MEM
2529 && ((x_size < new_size
2530 #ifdef WORD_REGISTER_OPERATIONS
2531 /* On these machines, combine can create rtl of the form
2532 (set (subreg:m1 (reg:m2 R) 0) ...)
2533 where m1 < m2, and expects something interesting to
2534 happen to the entire word. Moreover, it will use the
2535 (reg:m2 R) later, expecting all bits to be preserved.
2536 So if the number of words is the same, preserve the
2537 subreg so that push_reloads can see it. */
2538 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
2541 || (x_size == new_size))
2544 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2545 enum machine_mode mode = GET_MODE (x);
2547 if (BYTES_BIG_ENDIAN)
2548 offset += (MIN (UNITS_PER_WORD,
2549 GET_MODE_SIZE (GET_MODE (new)))
2550 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2552 PUT_MODE (new, mode);
2553 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2557 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
2563 /* This is only for the benefit of the debugging backends, which call
2564 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2565 removed after CSE. */
2566 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2567 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2569 /* Our only special processing is to pass the mode of the MEM to our
2570 recursive call and copy the flags. While we are here, handle this
2571 case more efficiently. */
2572 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
2573 if (new != XEXP (x, 0))
2575 new = gen_rtx_MEM (GET_MODE (x), new);
2576 MEM_COPY_ATTRIBUTES (new, x);
2592 /* Process each of our operands recursively. If any have changed, make a
2594 fmt = GET_RTX_FORMAT (code);
2595 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2599 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2600 if (new != XEXP (x, i) && ! copied)
2602 rtx new_x = rtx_alloc (code);
2604 (sizeof (*new_x) - sizeof (new_x->fld)
2605 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2611 else if (*fmt == 'E')
2614 for (j = 0; j < XVECLEN (x, i); j++)
2616 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2617 if (new != XVECEXP (x, i, j) && ! copied_vec)
2619 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2623 rtx new_x = rtx_alloc (code);
2625 (sizeof (*new_x) - sizeof (new_x->fld)
2626 + (sizeof (new_x->fld[0])
2627 * GET_RTX_LENGTH (code))));
2631 XVEC (x, i) = new_v;
2634 XVECEXP (x, i, j) = new;
2642 /* Scan rtx X for modifications of elimination target registers. Update
2643 the table of eliminables to reflect the changed state. MEM_MODE is
2644 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2647 elimination_effects (x, mem_mode)
2649 enum machine_mode mem_mode;
2652 enum rtx_code code = GET_CODE (x);
2653 struct elim_table *ep;
2679 /* First handle the case where we encounter a bare register that
2680 is eliminable. Replace it with a PLUS. */
2681 if (regno < FIRST_PSEUDO_REGISTER)
2683 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2685 if (ep->from_rtx == x && ep->can_eliminate)
2688 ep->ref_outside_mem = 1;
2693 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2694 && reg_equiv_constant[regno]
2695 && ! CONSTANT_P (reg_equiv_constant[regno]))
2696 elimination_effects (reg_equiv_constant[regno], mem_mode);
2705 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2706 if (ep->to_rtx == XEXP (x, 0))
2708 int size = GET_MODE_SIZE (mem_mode);
2710 /* If more bytes than MEM_MODE are pushed, account for them. */
2711 #ifdef PUSH_ROUNDING
2712 if (ep->to_rtx == stack_pointer_rtx)
2713 size = PUSH_ROUNDING (size);
2715 if (code == PRE_DEC || code == POST_DEC)
2717 else if (code == PRE_INC || code == POST_INC)
2719 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2720 && GET_CODE (XEXP (x, 1)) == PLUS
2721 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2722 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2723 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2726 /* These two aren't unary operators. */
2727 if (code == POST_MODIFY || code == PRE_MODIFY)
2730 /* Fall through to generic unary operation case. */
2731 case STRICT_LOW_PART:
2733 case SIGN_EXTEND: case ZERO_EXTEND:
2734 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2735 case FLOAT: case FIX:
2736 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2740 elimination_effects (XEXP (x, 0), mem_mode);
2744 if (GET_CODE (SUBREG_REG (x)) == REG
2745 && (GET_MODE_SIZE (GET_MODE (x))
2746 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2747 && reg_equiv_memory_loc != 0
2748 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2751 elimination_effects (SUBREG_REG (x), mem_mode);
2755 /* If using a register that is the source of an eliminate we still
2756 think can be performed, note it cannot be performed since we don't
2757 know how this register is used. */
2758 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2759 if (ep->from_rtx == XEXP (x, 0))
2760 ep->can_eliminate = 0;
2762 elimination_effects (XEXP (x, 0), mem_mode);
2766 /* If clobbering a register that is the replacement register for an
2767 elimination we still think can be performed, note that it cannot
2768 be performed. Otherwise, we need not be concerned about it. */
2769 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2770 if (ep->to_rtx == XEXP (x, 0))
2771 ep->can_eliminate = 0;
2773 elimination_effects (XEXP (x, 0), mem_mode);
2777 /* Check for setting a register that we know about. */
2778 if (GET_CODE (SET_DEST (x)) == REG)
2780 /* See if this is setting the replacement register for an
2783 If DEST is the hard frame pointer, we do nothing because we
2784 assume that all assignments to the frame pointer are for
2785 non-local gotos and are being done at a time when they are valid
2786 and do not disturb anything else. Some machines want to
2787 eliminate a fake argument pointer (or even a fake frame pointer)
2788 with either the real frame or the stack pointer. Assignments to
2789 the hard frame pointer must not prevent this elimination. */
2791 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2793 if (ep->to_rtx == SET_DEST (x)
2794 && SET_DEST (x) != hard_frame_pointer_rtx)
2796 /* If it is being incremented, adjust the offset. Otherwise,
2797 this elimination can't be done. */
2798 rtx src = SET_SRC (x);
2800 if (GET_CODE (src) == PLUS
2801 && XEXP (src, 0) == SET_DEST (x)
2802 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2803 ep->offset -= INTVAL (XEXP (src, 1));
2805 ep->can_eliminate = 0;
2809 elimination_effects (SET_DEST (x), 0);
2810 elimination_effects (SET_SRC (x), 0);
2814 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2817 /* Our only special processing is to pass the mode of the MEM to our
2819 elimination_effects (XEXP (x, 0), GET_MODE (x));
2826 fmt = GET_RTX_FORMAT (code);
2827 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2830 elimination_effects (XEXP (x, i), mem_mode);
2831 else if (*fmt == 'E')
2832 for (j = 0; j < XVECLEN (x, i); j++)
2833 elimination_effects (XVECEXP (x, i, j), mem_mode);
2837 /* Descend through rtx X and verify that no references to eliminable registers
2838 remain. If any do remain, mark the involved register as not
2842 check_eliminable_occurrences (x)
2852 code = GET_CODE (x);
2854 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2856 struct elim_table *ep;
2858 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2859 if (ep->from_rtx == x && ep->can_eliminate)
2860 ep->can_eliminate = 0;
2864 fmt = GET_RTX_FORMAT (code);
2865 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2868 check_eliminable_occurrences (XEXP (x, i));
2869 else if (*fmt == 'E')
2872 for (j = 0; j < XVECLEN (x, i); j++)
2873 check_eliminable_occurrences (XVECEXP (x, i, j));
2878 /* Scan INSN and eliminate all eliminable registers in it.
2880 If REPLACE is nonzero, do the replacement destructively. Also
2881 delete the insn as dead it if it is setting an eliminable register.
2883 If REPLACE is zero, do all our allocations in reload_obstack.
2885 If no eliminations were done and this insn doesn't require any elimination
2886 processing (these are not identical conditions: it might be updating sp,
2887 but not referencing fp; this needs to be seen during reload_as_needed so
2888 that the offset between fp and sp can be taken into consideration), zero
2889 is returned. Otherwise, 1 is returned. */
2892 eliminate_regs_in_insn (insn, replace)
2896 int icode = recog_memoized (insn);
2897 rtx old_body = PATTERN (insn);
2898 int insn_is_asm = asm_noperands (old_body) >= 0;
2899 rtx old_set = single_set (insn);
2903 rtx substed_operand[MAX_RECOG_OPERANDS];
2904 rtx orig_operand[MAX_RECOG_OPERANDS];
2905 struct elim_table *ep;
2907 if (! insn_is_asm && icode < 0)
2909 if (GET_CODE (PATTERN (insn)) == USE
2910 || GET_CODE (PATTERN (insn)) == CLOBBER
2911 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2912 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2913 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2918 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2919 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2921 /* Check for setting an eliminable register. */
2922 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2923 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2925 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2926 /* If this is setting the frame pointer register to the
2927 hardware frame pointer register and this is an elimination
2928 that will be done (tested above), this insn is really
2929 adjusting the frame pointer downward to compensate for
2930 the adjustment done before a nonlocal goto. */
2931 if (ep->from == FRAME_POINTER_REGNUM
2932 && ep->to == HARD_FRAME_POINTER_REGNUM)
2934 rtx src = SET_SRC (old_set);
2935 int offset = 0, ok = 0;
2936 rtx prev_insn, prev_set;
2938 if (src == ep->to_rtx)
2940 else if (GET_CODE (src) == PLUS
2941 && GET_CODE (XEXP (src, 0)) == CONST_INT
2942 && XEXP (src, 1) == ep->to_rtx)
2943 offset = INTVAL (XEXP (src, 0)), ok = 1;
2944 else if (GET_CODE (src) == PLUS
2945 && GET_CODE (XEXP (src, 1)) == CONST_INT
2946 && XEXP (src, 0) == ep->to_rtx)
2947 offset = INTVAL (XEXP (src, 1)), ok = 1;
2948 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
2949 && (prev_set = single_set (prev_insn)) != 0
2950 && rtx_equal_p (SET_DEST (prev_set), src))
2952 src = SET_SRC (prev_set);
2953 if (src == ep->to_rtx)
2955 else if (GET_CODE (src) == PLUS
2956 && GET_CODE (XEXP (src, 0)) == CONST_INT
2957 && XEXP (src, 1) == ep->to_rtx)
2958 offset = INTVAL (XEXP (src, 0)), ok = 1;
2959 else if (GET_CODE (src) == PLUS
2960 && GET_CODE (XEXP (src, 1)) == CONST_INT
2961 && XEXP (src, 0) == ep->to_rtx)
2962 offset = INTVAL (XEXP (src, 1)), ok = 1;
2970 = plus_constant (ep->to_rtx, offset - ep->offset);
2972 /* First see if this insn remains valid when we
2973 make the change. If not, keep the INSN_CODE
2974 the same and let reload fit it up. */
2975 validate_change (insn, &SET_SRC (old_set), src, 1);
2976 validate_change (insn, &SET_DEST (old_set),
2978 if (! apply_change_group ())
2980 SET_SRC (old_set) = src;
2981 SET_DEST (old_set) = ep->to_rtx;
2991 /* In this case this insn isn't serving a useful purpose. We
2992 will delete it in reload_as_needed once we know that this
2993 elimination is, in fact, being done.
2995 If REPLACE isn't set, we can't delete this insn, but needn't
2996 process it since it won't be used unless something changes. */
2999 delete_dead_insn (insn);
3007 /* We allow one special case which happens to work on all machines we
3008 currently support: a single set with the source being a PLUS of an
3009 eliminable register and a constant. */
3011 && GET_CODE (SET_SRC (old_set)) == PLUS
3012 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3013 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
3014 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
3016 rtx reg = XEXP (SET_SRC (old_set), 0);
3017 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
3019 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3020 if (ep->from_rtx == reg && ep->can_eliminate)
3022 offset += ep->offset;
3027 /* We assume here that if we need a PARALLEL with
3028 CLOBBERs for this assignment, we can do with the
3029 MATCH_SCRATCHes that add_clobbers allocates.
3030 There's not much we can do if that doesn't work. */
3031 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3035 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3038 rtvec vec = rtvec_alloc (num_clobbers + 1);
3040 vec->elem[0] = PATTERN (insn);
3041 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3042 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3044 if (INSN_CODE (insn) < 0)
3049 new_body = old_body;
3052 new_body = copy_insn (old_body);
3053 if (REG_NOTES (insn))
3054 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3056 PATTERN (insn) = new_body;
3057 old_set = single_set (insn);
3059 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3060 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3063 /* This can't have an effect on elimination offsets, so skip right
3069 /* Determine the effects of this insn on elimination offsets. */
3070 elimination_effects (old_body, 0);
3072 /* Eliminate all eliminable registers occurring in operands that
3073 can be handled by reload. */
3074 extract_insn (insn);
3076 for (i = 0; i < recog_data.n_operands; i++)
3078 orig_operand[i] = recog_data.operand[i];
3079 substed_operand[i] = recog_data.operand[i];
3081 /* For an asm statement, every operand is eliminable. */
3082 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3084 /* Check for setting a register that we know about. */
3085 if (recog_data.operand_type[i] != OP_IN
3086 && GET_CODE (orig_operand[i]) == REG)
3088 /* If we are assigning to a register that can be eliminated, it
3089 must be as part of a PARALLEL, since the code above handles
3090 single SETs. We must indicate that we can no longer
3091 eliminate this reg. */
3092 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3094 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3095 ep->can_eliminate = 0;
3098 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3099 replace ? insn : NULL_RTX);
3100 if (substed_operand[i] != orig_operand[i])
3101 val = any_changes = 1;
3102 /* Terminate the search in check_eliminable_occurrences at
3104 *recog_data.operand_loc[i] = 0;
3106 /* If an output operand changed from a REG to a MEM and INSN is an
3107 insn, write a CLOBBER insn. */
3108 if (recog_data.operand_type[i] != OP_IN
3109 && GET_CODE (orig_operand[i]) == REG
3110 && GET_CODE (substed_operand[i]) == MEM
3112 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3117 for (i = 0; i < recog_data.n_dups; i++)
3118 *recog_data.dup_loc[i]
3119 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3121 /* If any eliminable remain, they aren't eliminable anymore. */
3122 check_eliminable_occurrences (old_body);
3124 /* Substitute the operands; the new values are in the substed_operand
3126 for (i = 0; i < recog_data.n_operands; i++)
3127 *recog_data.operand_loc[i] = substed_operand[i];
3128 for (i = 0; i < recog_data.n_dups; i++)
3129 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3131 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3132 re-recognize the insn. We do this in case we had a simple addition
3133 but now can do this as a load-address. This saves an insn in this
3135 If re-recognition fails, the old insn code number will still be used,
3136 and some register operands may have changed into PLUS expressions.
3137 These will be handled by find_reloads by loading them into a register
3142 /* If we aren't replacing things permanently and we changed something,
3143 make another copy to ensure that all the RTL is new. Otherwise
3144 things can go wrong if find_reload swaps commutative operands
3145 and one is inside RTL that has been copied while the other is not. */
3146 new_body = old_body;
3149 new_body = copy_insn (old_body);
3150 if (REG_NOTES (insn))
3151 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3153 PATTERN (insn) = new_body;
3155 /* If we had a move insn but now we don't, rerecognize it. This will
3156 cause spurious re-recognition if the old move had a PARALLEL since
3157 the new one still will, but we can't call single_set without
3158 having put NEW_BODY into the insn and the re-recognition won't
3159 hurt in this rare case. */
3160 /* ??? Why this huge if statement - why don't we just rerecognize the
3164 && ((GET_CODE (SET_SRC (old_set)) == REG
3165 && (GET_CODE (new_body) != SET
3166 || GET_CODE (SET_SRC (new_body)) != REG))
3167 /* If this was a load from or store to memory, compare
3168 the MEM in recog_data.operand to the one in the insn.
3169 If they are not equal, then rerecognize the insn. */
3171 && ((GET_CODE (SET_SRC (old_set)) == MEM
3172 && SET_SRC (old_set) != recog_data.operand[1])
3173 || (GET_CODE (SET_DEST (old_set)) == MEM
3174 && SET_DEST (old_set) != recog_data.operand[0])))
3175 /* If this was an add insn before, rerecognize. */
3176 || GET_CODE (SET_SRC (old_set)) == PLUS))
3178 int new_icode = recog (PATTERN (insn), insn, 0);
3180 INSN_CODE (insn) = icode;
3184 /* Restore the old body. If there were any changes to it, we made a copy
3185 of it while the changes were still in place, so we'll correctly return
3186 a modified insn below. */
3189 /* Restore the old body. */
3190 for (i = 0; i < recog_data.n_operands; i++)
3191 *recog_data.operand_loc[i] = orig_operand[i];
3192 for (i = 0; i < recog_data.n_dups; i++)
3193 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3196 /* Update all elimination pairs to reflect the status after the current
3197 insn. The changes we make were determined by the earlier call to
3198 elimination_effects.
3200 We also detect a cases where register elimination cannot be done,
3201 namely, if a register would be both changed and referenced outside a MEM
3202 in the resulting insn since such an insn is often undefined and, even if
3203 not, we cannot know what meaning will be given to it. Note that it is
3204 valid to have a register used in an address in an insn that changes it
3205 (presumably with a pre- or post-increment or decrement).
3207 If anything changes, return nonzero. */
3209 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3211 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3212 ep->can_eliminate = 0;
3214 ep->ref_outside_mem = 0;
3216 if (ep->previous_offset != ep->offset)
3221 /* If we changed something, perform elimination in REG_NOTES. This is
3222 needed even when REPLACE is zero because a REG_DEAD note might refer
3223 to a register that we eliminate and could cause a different number
3224 of spill registers to be needed in the final reload pass than in
3226 if (val && REG_NOTES (insn) != 0)
3227 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3232 /* Loop through all elimination pairs.
3233 Recalculate the number not at initial offset.
3235 Compute the maximum offset (minimum offset if the stack does not
3236 grow downward) for each elimination pair. */
3239 update_eliminable_offsets ()
3241 struct elim_table *ep;
3243 num_not_at_initial_offset = 0;
3244 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3246 ep->previous_offset = ep->offset;
3247 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3248 num_not_at_initial_offset++;
3252 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3253 replacement we currently believe is valid, mark it as not eliminable if X
3254 modifies DEST in any way other than by adding a constant integer to it.
3256 If DEST is the frame pointer, we do nothing because we assume that
3257 all assignments to the hard frame pointer are nonlocal gotos and are being
3258 done at a time when they are valid and do not disturb anything else.
3259 Some machines want to eliminate a fake argument pointer with either the
3260 frame or stack pointer. Assignments to the hard frame pointer must not
3261 prevent this elimination.
3263 Called via note_stores from reload before starting its passes to scan
3264 the insns of the function. */
3267 mark_not_eliminable (dest, x, data)
3270 void *data ATTRIBUTE_UNUSED;
3272 register unsigned int i;
3274 /* A SUBREG of a hard register here is just changing its mode. We should
3275 not see a SUBREG of an eliminable hard register, but check just in
3277 if (GET_CODE (dest) == SUBREG)
3278 dest = SUBREG_REG (dest);
3280 if (dest == hard_frame_pointer_rtx)
3283 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3284 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3285 && (GET_CODE (x) != SET
3286 || GET_CODE (SET_SRC (x)) != PLUS
3287 || XEXP (SET_SRC (x), 0) != dest
3288 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3290 reg_eliminate[i].can_eliminate_previous
3291 = reg_eliminate[i].can_eliminate = 0;
3296 /* Verify that the initial elimination offsets did not change since the
3297 last call to set_initial_elim_offsets. This is used to catch cases
3298 where something illegal happened during reload_as_needed that could
3299 cause incorrect code to be generated if we did not check for it. */
3302 verify_initial_elim_offsets ()
3306 #ifdef ELIMINABLE_REGS
3307 struct elim_table *ep;
3309 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3311 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3312 if (t != ep->initial_offset)
3316 INITIAL_FRAME_POINTER_OFFSET (t);
3317 if (t != reg_eliminate[0].initial_offset)
3322 /* Reset all offsets on eliminable registers to their initial values. */
3325 set_initial_elim_offsets ()
3327 struct elim_table *ep = reg_eliminate;
3329 #ifdef ELIMINABLE_REGS
3330 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3332 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3333 ep->previous_offset = ep->offset = ep->initial_offset;
3336 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3337 ep->previous_offset = ep->offset = ep->initial_offset;
3340 num_not_at_initial_offset = 0;
3343 /* Initialize the known label offsets.
3344 Set a known offset for each forced label to be at the initial offset
3345 of each elimination. We do this because we assume that all
3346 computed jumps occur from a location where each elimination is
3347 at its initial offset.
3348 For all other labels, show that we don't know the offsets. */
3351 set_initial_label_offsets ()
3354 memset ((char *) &offsets_known_at[get_first_label_num ()], 0, num_labels);
3356 for (x = forced_labels; x; x = XEXP (x, 1))
3358 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3361 /* Set all elimination offsets to the known values for the code label given
3365 set_offsets_for_label (insn)
3369 int label_nr = CODE_LABEL_NUMBER (insn);
3370 struct elim_table *ep;
3372 num_not_at_initial_offset = 0;
3373 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3375 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3376 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3377 num_not_at_initial_offset++;
3381 /* See if anything that happened changes which eliminations are valid.
3382 For example, on the Sparc, whether or not the frame pointer can
3383 be eliminated can depend on what registers have been used. We need
3384 not check some conditions again (such as flag_omit_frame_pointer)
3385 since they can't have changed. */
3388 update_eliminables (pset)
3391 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3392 int previous_frame_pointer_needed = frame_pointer_needed;
3394 struct elim_table *ep;
3396 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3397 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3398 #ifdef ELIMINABLE_REGS
3399 || ! CAN_ELIMINATE (ep->from, ep->to)
3402 ep->can_eliminate = 0;
3404 /* Look for the case where we have discovered that we can't replace
3405 register A with register B and that means that we will now be
3406 trying to replace register A with register C. This means we can
3407 no longer replace register C with register B and we need to disable
3408 such an elimination, if it exists. This occurs often with A == ap,
3409 B == sp, and C == fp. */
3411 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3413 struct elim_table *op;
3414 register int new_to = -1;
3416 if (! ep->can_eliminate && ep->can_eliminate_previous)
3418 /* Find the current elimination for ep->from, if there is a
3420 for (op = reg_eliminate;
3421 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3422 if (op->from == ep->from && op->can_eliminate)
3428 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3430 for (op = reg_eliminate;
3431 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3432 if (op->from == new_to && op->to == ep->to)
3433 op->can_eliminate = 0;
3437 /* See if any registers that we thought we could eliminate the previous
3438 time are no longer eliminable. If so, something has changed and we
3439 must spill the register. Also, recompute the number of eliminable
3440 registers and see if the frame pointer is needed; it is if there is
3441 no elimination of the frame pointer that we can perform. */
3443 frame_pointer_needed = 1;
3444 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3446 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3447 && ep->to != HARD_FRAME_POINTER_REGNUM)
3448 frame_pointer_needed = 0;
3450 if (! ep->can_eliminate && ep->can_eliminate_previous)
3452 ep->can_eliminate_previous = 0;
3453 SET_HARD_REG_BIT (*pset, ep->from);
3458 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3459 /* If we didn't need a frame pointer last time, but we do now, spill
3460 the hard frame pointer. */
3461 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3462 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3466 /* Initialize the table of registers to eliminate. */
3471 struct elim_table *ep;
3472 #ifdef ELIMINABLE_REGS
3473 struct elim_table_1 *ep1;
3477 reg_eliminate = (struct elim_table *)
3478 xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3480 /* Does this function require a frame pointer? */
3482 frame_pointer_needed = (! flag_omit_frame_pointer
3483 #ifdef EXIT_IGNORE_STACK
3484 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3485 and restore sp for alloca. So we can't eliminate
3486 the frame pointer in that case. At some point,
3487 we should improve this by emitting the
3488 sp-adjusting insns for this case. */
3489 || (current_function_calls_alloca
3490 && EXIT_IGNORE_STACK)
3492 || FRAME_POINTER_REQUIRED);
3496 #ifdef ELIMINABLE_REGS
3497 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3498 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3500 ep->from = ep1->from;
3502 ep->can_eliminate = ep->can_eliminate_previous
3503 = (CAN_ELIMINATE (ep->from, ep->to)
3504 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3507 reg_eliminate[0].from = reg_eliminate_1[0].from;
3508 reg_eliminate[0].to = reg_eliminate_1[0].to;
3509 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3510 = ! frame_pointer_needed;
3513 /* Count the number of eliminable registers and build the FROM and TO
3514 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3515 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3516 We depend on this. */
3517 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3519 num_eliminable += ep->can_eliminate;
3520 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3521 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3525 /* Kick all pseudos out of hard register REGNO.
3527 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3528 because we found we can't eliminate some register. In the case, no pseudos
3529 are allowed to be in the register, even if they are only in a block that
3530 doesn't require spill registers, unlike the case when we are spilling this
3531 hard reg to produce another spill register.
3533 Return nonzero if any pseudos needed to be kicked out. */
3536 spill_hard_reg (regno, cant_eliminate)
3544 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3545 regs_ever_live[regno] = 1;
3548 /* Spill every pseudo reg that was allocated to this reg
3549 or to something that overlaps this reg. */
3551 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3552 if (reg_renumber[i] >= 0
3553 && (unsigned int) reg_renumber[i] <= regno
3554 && ((unsigned int) reg_renumber[i]
3555 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3556 PSEUDO_REGNO_MODE (i))
3558 SET_REGNO_REG_SET (&spilled_pseudos, i);
3561 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3562 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3565 ior_hard_reg_set (set1, set2)
3566 HARD_REG_SET *set1, *set2;
3568 IOR_HARD_REG_SET (*set1, *set2);
3571 /* After find_reload_regs has been run for all insn that need reloads,
3572 and/or spill_hard_regs was called, this function is used to actually
3573 spill pseudo registers and try to reallocate them. It also sets up the
3574 spill_regs array for use by choose_reload_regs. */
3577 finish_spills (global)
3580 struct insn_chain *chain;
3581 int something_changed = 0;
3584 /* Build the spill_regs array for the function. */
3585 /* If there are some registers still to eliminate and one of the spill regs
3586 wasn't ever used before, additional stack space may have to be
3587 allocated to store this register. Thus, we may have changed the offset
3588 between the stack and frame pointers, so mark that something has changed.
3590 One might think that we need only set VAL to 1 if this is a call-used
3591 register. However, the set of registers that must be saved by the
3592 prologue is not identical to the call-used set. For example, the
3593 register used by the call insn for the return PC is a call-used register,
3594 but must be saved by the prologue. */
3597 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3598 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3600 spill_reg_order[i] = n_spills;
3601 spill_regs[n_spills++] = i;
3602 if (num_eliminable && ! regs_ever_live[i])
3603 something_changed = 1;
3604 regs_ever_live[i] = 1;
3607 spill_reg_order[i] = -1;
3609 EXECUTE_IF_SET_IN_REG_SET
3610 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3612 /* Record the current hard register the pseudo is allocated to in
3613 pseudo_previous_regs so we avoid reallocating it to the same
3614 hard reg in a later pass. */
3615 if (reg_renumber[i] < 0)
3618 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3619 /* Mark it as no longer having a hard register home. */
3620 reg_renumber[i] = -1;
3621 /* We will need to scan everything again. */
3622 something_changed = 1;
3625 /* Retry global register allocation if possible. */
3628 memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3629 /* For every insn that needs reloads, set the registers used as spill
3630 regs in pseudo_forbidden_regs for every pseudo live across the
3632 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3634 EXECUTE_IF_SET_IN_REG_SET
3635 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3637 ior_hard_reg_set (pseudo_forbidden_regs + i,
3638 &chain->used_spill_regs);
3640 EXECUTE_IF_SET_IN_REG_SET
3641 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3643 ior_hard_reg_set (pseudo_forbidden_regs + i,
3644 &chain->used_spill_regs);
3648 /* Retry allocating the spilled pseudos. For each reg, merge the
3649 various reg sets that indicate which hard regs can't be used,
3650 and call retry_global_alloc.
3651 We change spill_pseudos here to only contain pseudos that did not
3652 get a new hard register. */
3653 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3654 if (reg_old_renumber[i] != reg_renumber[i])
3656 HARD_REG_SET forbidden;
3657 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3658 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3659 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3660 retry_global_alloc (i, forbidden);
3661 if (reg_renumber[i] >= 0)
3662 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3666 /* Fix up the register information in the insn chain.
3667 This involves deleting those of the spilled pseudos which did not get
3668 a new hard register home from the live_{before,after} sets. */
3669 for (chain = reload_insn_chain; chain; chain = chain->next)
3671 HARD_REG_SET used_by_pseudos;
3672 HARD_REG_SET used_by_pseudos2;
3674 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3675 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3677 /* Mark any unallocated hard regs as available for spills. That
3678 makes inheritance work somewhat better. */
3679 if (chain->need_reload)
3681 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3682 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3683 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3685 /* Save the old value for the sanity test below. */
3686 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3688 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3689 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3690 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3691 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3693 /* Make sure we only enlarge the set. */
3694 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3700 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3701 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3703 int regno = reg_renumber[i];
3704 if (reg_old_renumber[i] == regno)
3707 alter_reg (i, reg_old_renumber[i]);
3708 reg_old_renumber[i] = regno;
3712 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3714 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3715 i, reg_renumber[i]);
3719 return something_changed;
3722 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3723 Also mark any hard registers used to store user variables as
3724 forbidden from being used for spill registers. */
3727 scan_paradoxical_subregs (x)
3731 register const char *fmt;
3732 register enum rtx_code code = GET_CODE (x);
3738 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3739 && REG_USERVAR_P (x))
3740 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3756 if (GET_CODE (SUBREG_REG (x)) == REG
3757 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3758 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3759 = GET_MODE_SIZE (GET_MODE (x));
3766 fmt = GET_RTX_FORMAT (code);
3767 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3770 scan_paradoxical_subregs (XEXP (x, i));
3771 else if (fmt[i] == 'E')
3774 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3775 scan_paradoxical_subregs (XVECEXP (x, i, j));
3780 /* Reload pseudo-registers into hard regs around each insn as needed.
3781 Additional register load insns are output before the insn that needs it
3782 and perhaps store insns after insns that modify the reloaded pseudo reg.
3784 reg_last_reload_reg and reg_reloaded_contents keep track of
3785 which registers are already available in reload registers.
3786 We update these for the reloads that we perform,
3787 as the insns are scanned. */
3790 reload_as_needed (live_known)
3793 struct insn_chain *chain;
3794 #if defined (AUTO_INC_DEC)
3799 memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx);
3800 memset ((char *) spill_reg_store, 0, sizeof spill_reg_store);
3801 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3802 reg_has_output_reload = (char *) xmalloc (max_regno);
3803 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3805 set_initial_elim_offsets ();
3807 for (chain = reload_insn_chain; chain; chain = chain->next)
3810 rtx insn = chain->insn;
3811 rtx old_next = NEXT_INSN (insn);
3813 /* If we pass a label, copy the offsets from the label information
3814 into the current offsets of each elimination. */
3815 if (GET_CODE (insn) == CODE_LABEL)
3816 set_offsets_for_label (insn);
3818 else if (INSN_P (insn))
3820 rtx oldpat = PATTERN (insn);
3822 /* If this is a USE and CLOBBER of a MEM, ensure that any
3823 references to eliminable registers have been removed. */
3825 if ((GET_CODE (PATTERN (insn)) == USE
3826 || GET_CODE (PATTERN (insn)) == CLOBBER)
3827 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3828 XEXP (XEXP (PATTERN (insn), 0), 0)
3829 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3830 GET_MODE (XEXP (PATTERN (insn), 0)),
3833 /* If we need to do register elimination processing, do so.
3834 This might delete the insn, in which case we are done. */
3835 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3837 eliminate_regs_in_insn (insn, 1);
3838 if (GET_CODE (insn) == NOTE)
3840 update_eliminable_offsets ();
3845 /* If need_elim is nonzero but need_reload is zero, one might think
3846 that we could simply set n_reloads to 0. However, find_reloads
3847 could have done some manipulation of the insn (such as swapping
3848 commutative operands), and these manipulations are lost during
3849 the first pass for every insn that needs register elimination.
3850 So the actions of find_reloads must be redone here. */
3852 if (! chain->need_elim && ! chain->need_reload
3853 && ! chain->need_operand_change)
3855 /* First find the pseudo regs that must be reloaded for this insn.
3856 This info is returned in the tables reload_... (see reload.h).
3857 Also modify the body of INSN by substituting RELOAD
3858 rtx's for those pseudo regs. */
3861 memset (reg_has_output_reload, 0, max_regno);
3862 CLEAR_HARD_REG_SET (reg_is_output_reload);
3864 find_reloads (insn, 1, spill_indirect_levels, live_known,
3868 if (num_eliminable && chain->need_elim)
3869 update_eliminable_offsets ();
3873 rtx next = NEXT_INSN (insn);
3876 prev = PREV_INSN (insn);
3878 /* Now compute which reload regs to reload them into. Perhaps
3879 reusing reload regs from previous insns, or else output
3880 load insns to reload them. Maybe output store insns too.
3881 Record the choices of reload reg in reload_reg_rtx. */
3882 choose_reload_regs (chain);
3884 /* Merge any reloads that we didn't combine for fear of
3885 increasing the number of spill registers needed but now
3886 discover can be safely merged. */
3887 if (SMALL_REGISTER_CLASSES)
3888 merge_assigned_reloads (insn);
3890 /* Generate the insns to reload operands into or out of
3891 their reload regs. */
3892 emit_reload_insns (chain);
3894 /* Substitute the chosen reload regs from reload_reg_rtx
3895 into the insn's body (or perhaps into the bodies of other
3896 load and store insn that we just made for reloading
3897 and that we moved the structure into). */
3898 subst_reloads (insn);
3900 /* If this was an ASM, make sure that all the reload insns
3901 we have generated are valid. If not, give an error
3904 if (asm_noperands (PATTERN (insn)) >= 0)
3905 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3906 if (p != insn && INSN_P (p)
3907 && (recog_memoized (p) < 0
3908 || (extract_insn (p), ! constrain_operands (1))))
3910 error_for_asm (insn,
3911 "`asm' operand requires impossible reload");
3913 NOTE_SOURCE_FILE (p) = 0;
3914 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3917 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3918 is no longer validly lying around to save a future reload.
3919 Note that this does not detect pseudos that were reloaded
3920 for this insn in order to be stored in
3921 (obeying register constraints). That is correct; such reload
3922 registers ARE still valid. */
3923 note_stores (oldpat, forget_old_reloads_1, NULL);
3925 /* There may have been CLOBBER insns placed after INSN. So scan
3926 between INSN and NEXT and use them to forget old reloads. */
3927 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3928 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3929 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3932 /* Likewise for regs altered by auto-increment in this insn.
3933 REG_INC notes have been changed by reloading:
3934 find_reloads_address_1 records substitutions for them,
3935 which have been performed by subst_reloads above. */
3936 for (i = n_reloads - 1; i >= 0; i--)
3938 rtx in_reg = rld[i].in_reg;
3941 enum rtx_code code = GET_CODE (in_reg);
3942 /* PRE_INC / PRE_DEC will have the reload register ending up
3943 with the same value as the stack slot, but that doesn't
3944 hold true for POST_INC / POST_DEC. Either we have to
3945 convert the memory access to a true POST_INC / POST_DEC,
3946 or we can't use the reload register for inheritance. */
3947 if ((code == POST_INC || code == POST_DEC)
3948 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3949 REGNO (rld[i].reg_rtx))
3950 /* Make sure it is the inc/dec pseudo, and not
3951 some other (e.g. output operand) pseudo. */
3952 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3953 == REGNO (XEXP (in_reg, 0))))
3956 rtx reload_reg = rld[i].reg_rtx;
3957 enum machine_mode mode = GET_MODE (reload_reg);
3961 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3963 /* We really want to ignore REG_INC notes here, so
3964 use PATTERN (p) as argument to reg_set_p . */
3965 if (reg_set_p (reload_reg, PATTERN (p)))
3967 n = count_occurrences (PATTERN (p), reload_reg, 0);
3972 n = validate_replace_rtx (reload_reg,
3973 gen_rtx (code, mode,
3977 /* We must also verify that the constraints
3978 are met after the replacement. */
3981 n = constrain_operands (1);
3985 /* If the constraints were not met, then
3986 undo the replacement. */
3989 validate_replace_rtx (gen_rtx (code, mode,
4001 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4003 /* Mark this as having an output reload so that the
4004 REG_INC processing code below won't invalidate
4005 the reload for inheritance. */
4006 SET_HARD_REG_BIT (reg_is_output_reload,
4007 REGNO (reload_reg));
4008 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4011 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4014 else if ((code == PRE_INC || code == PRE_DEC)
4015 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4016 REGNO (rld[i].reg_rtx))
4017 /* Make sure it is the inc/dec pseudo, and not
4018 some other (e.g. output operand) pseudo. */
4019 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4020 == REGNO (XEXP (in_reg, 0))))
4022 SET_HARD_REG_BIT (reg_is_output_reload,
4023 REGNO (rld[i].reg_rtx));
4024 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4028 /* If a pseudo that got a hard register is auto-incremented,
4029 we must purge records of copying it into pseudos without
4031 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4032 if (REG_NOTE_KIND (x) == REG_INC)
4034 /* See if this pseudo reg was reloaded in this insn.
4035 If so, its last-reload info is still valid
4036 because it is based on this insn's reload. */
4037 for (i = 0; i < n_reloads; i++)
4038 if (rld[i].out == XEXP (x, 0))
4042 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4046 /* A reload reg's contents are unknown after a label. */
4047 if (GET_CODE (insn) == CODE_LABEL)
4048 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4050 /* Don't assume a reload reg is still good after a call insn
4051 if it is a call-used reg. */
4052 else if (GET_CODE (insn) == CALL_INSN)
4053 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
4057 free (reg_last_reload_reg);
4058 free (reg_has_output_reload);
4061 /* Discard all record of any value reloaded from X,
4062 or reloaded in X from someplace else;
4063 unless X is an output reload reg of the current insn.
4065 X may be a hard reg (the reload reg)
4066 or it may be a pseudo reg that was reloaded from. */
4069 forget_old_reloads_1 (x, ignored, data)
4071 rtx ignored ATTRIBUTE_UNUSED;
4072 void *data ATTRIBUTE_UNUSED;
4078 /* note_stores does give us subregs of hard regs. */
4079 while (GET_CODE (x) == SUBREG)
4081 offset += SUBREG_WORD (x);
4085 if (GET_CODE (x) != REG)
4088 regno = REGNO (x) + offset;
4090 if (regno >= FIRST_PSEUDO_REGISTER)
4096 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4097 /* Storing into a spilled-reg invalidates its contents.
4098 This can happen if a block-local pseudo is allocated to that reg
4099 and it wasn't spilled because this block's total need is 0.
4100 Then some insn might have an optional reload and use this reg. */
4101 for (i = 0; i < nr; i++)
4102 /* But don't do this if the reg actually serves as an output
4103 reload reg in the current instruction. */
4105 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4107 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4108 spill_reg_store[regno + i] = 0;
4112 /* Since value of X has changed,
4113 forget any value previously copied from it. */
4116 /* But don't forget a copy if this is the output reload
4117 that establishes the copy's validity. */
4118 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4119 reg_last_reload_reg[regno + nr] = 0;
4122 /* The following HARD_REG_SETs indicate when each hard register is
4123 used for a reload of various parts of the current insn. */
4125 /* If reg is unavailable for all reloads. */
4126 static HARD_REG_SET reload_reg_unavailable;
4127 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4128 static HARD_REG_SET reload_reg_used;
4129 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4130 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4131 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4132 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4133 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4134 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4135 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4136 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4137 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4138 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4139 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4140 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4141 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4142 static HARD_REG_SET reload_reg_used_in_op_addr;
4143 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4144 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4145 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4146 static HARD_REG_SET reload_reg_used_in_insn;
4147 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4148 static HARD_REG_SET reload_reg_used_in_other_addr;
4150 /* If reg is in use as a reload reg for any sort of reload. */
4151 static HARD_REG_SET reload_reg_used_at_all;
4153 /* If reg is use as an inherited reload. We just mark the first register
4155 static HARD_REG_SET reload_reg_used_for_inherit;
4157 /* Records which hard regs are used in any way, either as explicit use or
4158 by being allocated to a pseudo during any point of the current insn. */
4159 static HARD_REG_SET reg_used_in_insn;
4161 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4162 TYPE. MODE is used to indicate how many consecutive regs are
4166 mark_reload_reg_in_use (regno, opnum, type, mode)
4169 enum reload_type type;
4170 enum machine_mode mode;
4172 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4175 for (i = regno; i < nregs + regno; i++)
4180 SET_HARD_REG_BIT (reload_reg_used, i);
4183 case RELOAD_FOR_INPUT_ADDRESS:
4184 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4187 case RELOAD_FOR_INPADDR_ADDRESS:
4188 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4191 case RELOAD_FOR_OUTPUT_ADDRESS:
4192 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4195 case RELOAD_FOR_OUTADDR_ADDRESS:
4196 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4199 case RELOAD_FOR_OPERAND_ADDRESS:
4200 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4203 case RELOAD_FOR_OPADDR_ADDR:
4204 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4207 case RELOAD_FOR_OTHER_ADDRESS:
4208 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4211 case RELOAD_FOR_INPUT:
4212 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4215 case RELOAD_FOR_OUTPUT:
4216 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4219 case RELOAD_FOR_INSN:
4220 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4224 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4228 /* Similarly, but show REGNO is no longer in use for a reload. */
4231 clear_reload_reg_in_use (regno, opnum, type, mode)
4234 enum reload_type type;
4235 enum machine_mode mode;
4237 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4238 unsigned int start_regno, end_regno, r;
4240 /* A complication is that for some reload types, inheritance might
4241 allow multiple reloads of the same types to share a reload register.
4242 We set check_opnum if we have to check only reloads with the same
4243 operand number, and check_any if we have to check all reloads. */
4244 int check_opnum = 0;
4246 HARD_REG_SET *used_in_set;
4251 used_in_set = &reload_reg_used;
4254 case RELOAD_FOR_INPUT_ADDRESS:
4255 used_in_set = &reload_reg_used_in_input_addr[opnum];
4258 case RELOAD_FOR_INPADDR_ADDRESS:
4260 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4263 case RELOAD_FOR_OUTPUT_ADDRESS:
4264 used_in_set = &reload_reg_used_in_output_addr[opnum];
4267 case RELOAD_FOR_OUTADDR_ADDRESS:
4269 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4272 case RELOAD_FOR_OPERAND_ADDRESS:
4273 used_in_set = &reload_reg_used_in_op_addr;
4276 case RELOAD_FOR_OPADDR_ADDR:
4278 used_in_set = &reload_reg_used_in_op_addr_reload;
4281 case RELOAD_FOR_OTHER_ADDRESS:
4282 used_in_set = &reload_reg_used_in_other_addr;
4286 case RELOAD_FOR_INPUT:
4287 used_in_set = &reload_reg_used_in_input[opnum];
4290 case RELOAD_FOR_OUTPUT:
4291 used_in_set = &reload_reg_used_in_output[opnum];
4294 case RELOAD_FOR_INSN:
4295 used_in_set = &reload_reg_used_in_insn;
4300 /* We resolve conflicts with remaining reloads of the same type by
4301 excluding the intervals of of reload registers by them from the
4302 interval of freed reload registers. Since we only keep track of
4303 one set of interval bounds, we might have to exclude somewhat
4304 more then what would be necessary if we used a HARD_REG_SET here.
4305 But this should only happen very infrequently, so there should
4306 be no reason to worry about it. */
4308 start_regno = regno;
4309 end_regno = regno + nregs;
4310 if (check_opnum || check_any)
4312 for (i = n_reloads - 1; i >= 0; i--)
4314 if (rld[i].when_needed == type
4315 && (check_any || rld[i].opnum == opnum)
4318 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4319 unsigned int conflict_end
4321 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4323 /* If there is an overlap with the first to-be-freed register,
4324 adjust the interval start. */
4325 if (conflict_start <= start_regno && conflict_end > start_regno)
4326 start_regno = conflict_end;
4327 /* Otherwise, if there is a conflict with one of the other
4328 to-be-freed registers, adjust the interval end. */
4329 if (conflict_start > start_regno && conflict_start < end_regno)
4330 end_regno = conflict_start;
4335 for (r = start_regno; r < end_regno; r++)
4336 CLEAR_HARD_REG_BIT (*used_in_set, r);
4339 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4340 specified by OPNUM and TYPE. */
4343 reload_reg_free_p (regno, opnum, type)
4346 enum reload_type type;
4350 /* In use for a RELOAD_OTHER means it's not available for anything. */
4351 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4352 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4358 /* In use for anything means we can't use it for RELOAD_OTHER. */
4359 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4360 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4361 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4364 for (i = 0; i < reload_n_operands; i++)
4365 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4366 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4367 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4368 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4369 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4370 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4375 case RELOAD_FOR_INPUT:
4376 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4377 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4380 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4383 /* If it is used for some other input, can't use it. */
4384 for (i = 0; i < reload_n_operands; i++)
4385 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4388 /* If it is used in a later operand's address, can't use it. */
4389 for (i = opnum + 1; i < reload_n_operands; i++)
4390 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4391 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4396 case RELOAD_FOR_INPUT_ADDRESS:
4397 /* Can't use a register if it is used for an input address for this
4398 operand or used as an input in an earlier one. */
4399 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4400 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4403 for (i = 0; i < opnum; i++)
4404 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4409 case RELOAD_FOR_INPADDR_ADDRESS:
4410 /* Can't use a register if it is used for an input address
4411 for this operand or used as an input in an earlier
4413 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4416 for (i = 0; i < opnum; i++)
4417 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4422 case RELOAD_FOR_OUTPUT_ADDRESS:
4423 /* Can't use a register if it is used for an output address for this
4424 operand or used as an output in this or a later operand. */
4425 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4428 for (i = opnum; i < reload_n_operands; i++)
4429 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4434 case RELOAD_FOR_OUTADDR_ADDRESS:
4435 /* Can't use a register if it is used for an output address
4436 for this operand or used as an output in this or a
4438 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4441 for (i = opnum; i < reload_n_operands; i++)
4442 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4447 case RELOAD_FOR_OPERAND_ADDRESS:
4448 for (i = 0; i < reload_n_operands; i++)
4449 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4452 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4453 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4455 case RELOAD_FOR_OPADDR_ADDR:
4456 for (i = 0; i < reload_n_operands; i++)
4457 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4460 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4462 case RELOAD_FOR_OUTPUT:
4463 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4464 outputs, or an operand address for this or an earlier output. */
4465 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4468 for (i = 0; i < reload_n_operands; i++)
4469 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4472 for (i = 0; i <= opnum; i++)
4473 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4474 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4479 case RELOAD_FOR_INSN:
4480 for (i = 0; i < reload_n_operands; i++)
4481 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4482 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4485 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4486 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4488 case RELOAD_FOR_OTHER_ADDRESS:
4489 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4494 /* Return 1 if the value in reload reg REGNO, as used by a reload
4495 needed for the part of the insn specified by OPNUM and TYPE,
4496 is still available in REGNO at the end of the insn.
4498 We can assume that the reload reg was already tested for availability
4499 at the time it is needed, and we should not check this again,
4500 in case the reg has already been marked in use. */
4503 reload_reg_reaches_end_p (regno, opnum, type)
4506 enum reload_type type;
4513 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4514 its value must reach the end. */
4517 /* If this use is for part of the insn,
4518 its value reaches if no subsequent part uses the same register.
4519 Just like the above function, don't try to do this with lots
4522 case RELOAD_FOR_OTHER_ADDRESS:
4523 /* Here we check for everything else, since these don't conflict
4524 with anything else and everything comes later. */
4526 for (i = 0; i < reload_n_operands; i++)
4527 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4528 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4529 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4530 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4531 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4532 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4535 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4536 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4537 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4539 case RELOAD_FOR_INPUT_ADDRESS:
4540 case RELOAD_FOR_INPADDR_ADDRESS:
4541 /* Similar, except that we check only for this and subsequent inputs
4542 and the address of only subsequent inputs and we do not need
4543 to check for RELOAD_OTHER objects since they are known not to
4546 for (i = opnum; i < reload_n_operands; i++)
4547 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4550 for (i = opnum + 1; i < reload_n_operands; i++)
4551 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4552 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4555 for (i = 0; i < reload_n_operands; i++)
4556 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4557 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4558 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4561 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4564 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4565 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4566 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4568 case RELOAD_FOR_INPUT:
4569 /* Similar to input address, except we start at the next operand for
4570 both input and input address and we do not check for
4571 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4574 for (i = opnum + 1; i < reload_n_operands; i++)
4575 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4576 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4577 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4580 /* ... fall through ... */
4582 case RELOAD_FOR_OPERAND_ADDRESS:
4583 /* Check outputs and their addresses. */
4585 for (i = 0; i < reload_n_operands; i++)
4586 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4587 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4588 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4591 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4593 case RELOAD_FOR_OPADDR_ADDR:
4594 for (i = 0; i < reload_n_operands; i++)
4595 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4596 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4597 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4600 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4601 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4602 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4604 case RELOAD_FOR_INSN:
4605 /* These conflict with other outputs with RELOAD_OTHER. So
4606 we need only check for output addresses. */
4610 /* ... fall through ... */
4612 case RELOAD_FOR_OUTPUT:
4613 case RELOAD_FOR_OUTPUT_ADDRESS:
4614 case RELOAD_FOR_OUTADDR_ADDRESS:
4615 /* We already know these can't conflict with a later output. So the
4616 only thing to check are later output addresses. */
4617 for (i = opnum + 1; i < reload_n_operands; i++)
4618 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4619 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4628 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4631 This function uses the same algorithm as reload_reg_free_p above. */
4634 reloads_conflict (r1, r2)
4637 enum reload_type r1_type = rld[r1].when_needed;
4638 enum reload_type r2_type = rld[r2].when_needed;
4639 int r1_opnum = rld[r1].opnum;
4640 int r2_opnum = rld[r2].opnum;
4642 /* RELOAD_OTHER conflicts with everything. */
4643 if (r2_type == RELOAD_OTHER)
4646 /* Otherwise, check conflicts differently for each type. */
4650 case RELOAD_FOR_INPUT:
4651 return (r2_type == RELOAD_FOR_INSN
4652 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4653 || r2_type == RELOAD_FOR_OPADDR_ADDR
4654 || r2_type == RELOAD_FOR_INPUT
4655 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4656 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4657 && r2_opnum > r1_opnum));
4659 case RELOAD_FOR_INPUT_ADDRESS:
4660 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4661 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4663 case RELOAD_FOR_INPADDR_ADDRESS:
4664 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4665 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4667 case RELOAD_FOR_OUTPUT_ADDRESS:
4668 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4669 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4671 case RELOAD_FOR_OUTADDR_ADDRESS:
4672 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4673 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4675 case RELOAD_FOR_OPERAND_ADDRESS:
4676 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4677 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4679 case RELOAD_FOR_OPADDR_ADDR:
4680 return (r2_type == RELOAD_FOR_INPUT
4681 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4683 case RELOAD_FOR_OUTPUT:
4684 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4685 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4686 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4687 && r2_opnum <= r1_opnum));
4689 case RELOAD_FOR_INSN:
4690 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4691 || r2_type == RELOAD_FOR_INSN
4692 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4694 case RELOAD_FOR_OTHER_ADDRESS:
4695 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4705 /* Indexed by reload number, 1 if incoming value
4706 inherited from previous insns. */
4707 char reload_inherited[MAX_RELOADS];
4709 /* For an inherited reload, this is the insn the reload was inherited from,
4710 if we know it. Otherwise, this is 0. */
4711 rtx reload_inheritance_insn[MAX_RELOADS];
4713 /* If non-zero, this is a place to get the value of the reload,
4714 rather than using reload_in. */
4715 rtx reload_override_in[MAX_RELOADS];
4717 /* For each reload, the hard register number of the register used,
4718 or -1 if we did not need a register for this reload. */
4719 int reload_spill_index[MAX_RELOADS];
4721 /* Subroutine of free_for_value_p, used to check a single register. */
4724 reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum,
4725 ignore_address_reloads)
4728 enum reload_type type;
4731 int ignore_address_reloads;
4734 /* Set if we see an input reload that must not share its reload register
4735 with any new earlyclobber, but might otherwise share the reload
4736 register with an output or input-output reload. */
4737 int check_earlyclobber = 0;
4741 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4744 if (out == const0_rtx)
4750 /* We use some pseudo 'time' value to check if the lifetimes of the
4751 new register use would overlap with the one of a previous reload
4752 that is not read-only or uses a different value.
4753 The 'time' used doesn't have to be linear in any shape or form, just
4755 Some reload types use different 'buckets' for each operand.
4756 So there are MAX_RECOG_OPERANDS different time values for each
4758 We compute TIME1 as the time when the register for the prospective
4759 new reload ceases to be live, and TIME2 for each existing
4760 reload as the time when that the reload register of that reload
4762 Where there is little to be gained by exact lifetime calculations,
4763 we just make conservative assumptions, i.e. a longer lifetime;
4764 this is done in the 'default:' cases. */
4767 case RELOAD_FOR_OTHER_ADDRESS:
4768 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4769 time1 = copy ? 0 : 1;
4772 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4774 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4775 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4776 respectively, to the time values for these, we get distinct time
4777 values. To get distinct time values for each operand, we have to
4778 multiply opnum by at least three. We round that up to four because
4779 multiply by four is often cheaper. */
4780 case RELOAD_FOR_INPADDR_ADDRESS:
4781 time1 = opnum * 4 + 2;
4783 case RELOAD_FOR_INPUT_ADDRESS:
4784 time1 = opnum * 4 + 3;
4786 case RELOAD_FOR_INPUT:
4787 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4788 executes (inclusive). */
4789 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4791 case RELOAD_FOR_OPADDR_ADDR:
4793 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4794 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4796 case RELOAD_FOR_OPERAND_ADDRESS:
4797 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4799 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4801 case RELOAD_FOR_OUTADDR_ADDRESS:
4802 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4804 case RELOAD_FOR_OUTPUT_ADDRESS:
4805 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4808 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4811 for (i = 0; i < n_reloads; i++)
4813 rtx reg = rld[i].reg_rtx;
4814 if (reg && GET_CODE (reg) == REG
4815 && ((unsigned) regno - true_regnum (reg)
4816 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
4819 if (! rld[i].in || ! rtx_equal_p (rld[i].in, value)
4820 || rld[i].out || out)
4823 switch (rld[i].when_needed)
4825 case RELOAD_FOR_OTHER_ADDRESS:
4828 case RELOAD_FOR_INPADDR_ADDRESS:
4829 /* find_reloads makes sure that a
4830 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4831 by at most one - the first -
4832 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4833 address reload is inherited, the address address reload
4834 goes away, so we can ignore this conflict. */
4835 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4836 && ignore_address_reloads
4837 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4838 Then the address address is still needed to store
4839 back the new address. */
4840 && ! rld[reloadnum].out)
4842 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4843 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4845 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4846 && ignore_address_reloads
4847 /* Unless we are reloading an auto_inc expression. */
4848 && ! rld[reloadnum].out)
4850 time2 = rld[i].opnum * 4 + 2;
4852 case RELOAD_FOR_INPUT_ADDRESS:
4853 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4854 && ignore_address_reloads
4855 && ! rld[reloadnum].out)
4857 time2 = rld[i].opnum * 4 + 3;
4859 case RELOAD_FOR_INPUT:
4860 time2 = rld[i].opnum * 4 + 4;
4861 check_earlyclobber = 1;
4863 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4864 == MAX_RECOG_OPERAND * 4 */
4865 case RELOAD_FOR_OPADDR_ADDR:
4866 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4867 && ignore_address_reloads
4868 && ! rld[reloadnum].out)
4870 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4872 case RELOAD_FOR_OPERAND_ADDRESS:
4873 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4874 check_earlyclobber = 1;
4876 case RELOAD_FOR_INSN:
4877 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4879 case RELOAD_FOR_OUTPUT:
4880 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4881 instruction is executed. */
4882 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4884 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4885 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4887 case RELOAD_FOR_OUTADDR_ADDRESS:
4888 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4889 && ignore_address_reloads
4890 && ! rld[reloadnum].out)
4892 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4894 case RELOAD_FOR_OUTPUT_ADDRESS:
4895 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4898 /* If there is no conflict in the input part, handle this
4899 like an output reload. */
4900 if (! rld[i].in || rtx_equal_p (rld[i].in, value))
4902 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4903 /* Earlyclobbered outputs must conflict with inputs. */
4904 if (earlyclobber_operand_p (rld[i].out))
4905 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4910 /* RELOAD_OTHER might be live beyond instruction execution,
4911 but this is not obvious when we set time2 = 1. So check
4912 here if there might be a problem with the new reload
4913 clobbering the register used by the RELOAD_OTHER. */
4921 && (! rld[i].in || rld[i].out
4922 || ! rtx_equal_p (rld[i].in, value)))
4923 || (out && rld[reloadnum].out_reg
4924 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4930 /* Earlyclobbered outputs must conflict with inputs. */
4931 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4937 /* Return 1 if the value in reload reg REGNO, as used by a reload
4938 needed for the part of the insn specified by OPNUM and TYPE,
4939 may be used to load VALUE into it.
4941 MODE is the mode in which the register is used, this is needed to
4942 determine how many hard regs to test.
4944 Other read-only reloads with the same value do not conflict
4945 unless OUT is non-zero and these other reloads have to live while
4946 output reloads live.
4947 If OUT is CONST0_RTX, this is a special case: it means that the
4948 test should not be for using register REGNO as reload register, but
4949 for copying from register REGNO into the reload register.
4951 RELOADNUM is the number of the reload we want to load this value for;
4952 a reload does not conflict with itself.
4954 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4955 reloads that load an address for the very reload we are considering.
4957 The caller has to make sure that there is no conflict with the return
4961 free_for_value_p (regno, mode, opnum, type, value, out, reloadnum,
4962 ignore_address_reloads)
4964 enum machine_mode mode;
4966 enum reload_type type;
4969 int ignore_address_reloads;
4971 int nregs = HARD_REGNO_NREGS (regno, mode);
4973 if (! reload_reg_free_for_value_p (regno + nregs, opnum, type, value, out,
4974 reloadnum, ignore_address_reloads))
4979 /* Determine whether the reload reg X overlaps any rtx'es used for
4980 overriding inheritance. Return nonzero if so. */
4983 conflicts_with_override (x)
4987 for (i = 0; i < n_reloads; i++)
4988 if (reload_override_in[i]
4989 && reg_overlap_mentioned_p (x, reload_override_in[i]))
4994 /* Give an error message saying we failed to find a reload for INSN,
4995 and clear out reload R. */
4997 failed_reload (insn, r)
5001 if (asm_noperands (PATTERN (insn)) < 0)
5002 /* It's the compiler's fault. */
5003 fatal_insn ("Could not find a spill register", insn);
5005 /* It's the user's fault; the operand's mode and constraint
5006 don't match. Disable this reload so we don't crash in final. */
5007 error_for_asm (insn,
5008 "`asm' operand constraint incompatible with operand size");
5012 rld[r].optional = 1;
5013 rld[r].secondary_p = 1;
5016 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5017 for reload R. If it's valid, get an rtx for it. Return nonzero if
5020 set_reload_reg (i, r)
5024 rtx reg = spill_reg_rtx[i];
5026 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5027 spill_reg_rtx[i] = reg
5028 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5030 regno = true_regnum (reg);
5032 /* Detect when the reload reg can't hold the reload mode.
5033 This used to be one `if', but Sequent compiler can't handle that. */
5034 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5036 enum machine_mode test_mode = VOIDmode;
5038 test_mode = GET_MODE (rld[r].in);
5039 /* If rld[r].in has VOIDmode, it means we will load it
5040 in whatever mode the reload reg has: to wit, rld[r].mode.
5041 We have already tested that for validity. */
5042 /* Aside from that, we need to test that the expressions
5043 to reload from or into have modes which are valid for this
5044 reload register. Otherwise the reload insns would be invalid. */
5045 if (! (rld[r].in != 0 && test_mode != VOIDmode
5046 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5047 if (! (rld[r].out != 0
5048 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5050 /* The reg is OK. */
5053 /* Mark as in use for this insn the reload regs we use
5055 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5056 rld[r].when_needed, rld[r].mode);
5058 rld[r].reg_rtx = reg;
5059 reload_spill_index[r] = spill_regs[i];
5066 /* Find a spill register to use as a reload register for reload R.
5067 LAST_RELOAD is non-zero if this is the last reload for the insn being
5070 Set rld[R].reg_rtx to the register allocated.
5072 We return 1 if successful, or 0 if we couldn't find a spill reg and
5073 we didn't change anything. */
5076 allocate_reload_reg (chain, r, last_reload)
5077 struct insn_chain *chain ATTRIBUTE_UNUSED;
5083 /* If we put this reload ahead, thinking it is a group,
5084 then insist on finding a group. Otherwise we can grab a
5085 reg that some other reload needs.
5086 (That can happen when we have a 68000 DATA_OR_FP_REG
5087 which is a group of data regs or one fp reg.)
5088 We need not be so restrictive if there are no more reloads
5091 ??? Really it would be nicer to have smarter handling
5092 for that kind of reg class, where a problem like this is normal.
5093 Perhaps those classes should be avoided for reloading
5094 by use of more alternatives. */
5096 int force_group = rld[r].nregs > 1 && ! last_reload;
5098 /* If we want a single register and haven't yet found one,
5099 take any reg in the right class and not in use.
5100 If we want a consecutive group, here is where we look for it.
5102 We use two passes so we can first look for reload regs to
5103 reuse, which are already in use for other reloads in this insn,
5104 and only then use additional registers.
5105 I think that maximizing reuse is needed to make sure we don't
5106 run out of reload regs. Suppose we have three reloads, and
5107 reloads A and B can share regs. These need two regs.
5108 Suppose A and B are given different regs.
5109 That leaves none for C. */
5110 for (pass = 0; pass < 2; pass++)
5112 /* I is the index in spill_regs.
5113 We advance it round-robin between insns to use all spill regs
5114 equally, so that inherited reloads have a chance
5115 of leapfrogging each other. */
5119 for (count = 0; count < n_spills; count++)
5121 int class = (int) rld[r].class;
5127 regnum = spill_regs[i];
5129 if ((reload_reg_free_p (regnum, rld[r].opnum,
5132 /* We check reload_reg_used to make sure we
5133 don't clobber the return register. */
5134 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5135 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5136 rld[r].when_needed, rld[r].in,
5138 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5139 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5140 /* Look first for regs to share, then for unshared. But
5141 don't share regs used for inherited reloads; they are
5142 the ones we want to preserve. */
5144 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5146 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5149 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5150 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5151 (on 68000) got us two FP regs. If NR is 1,
5152 we would reject both of them. */
5155 /* If we need only one reg, we have already won. */
5158 /* But reject a single reg if we demand a group. */
5163 /* Otherwise check that as many consecutive regs as we need
5164 are available here. */
5167 int regno = regnum + nr - 1;
5168 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5169 && spill_reg_order[regno] >= 0
5170 && reload_reg_free_p (regno, rld[r].opnum,
5171 rld[r].when_needed)))
5180 /* If we found something on pass 1, omit pass 2. */
5181 if (count < n_spills)
5185 /* We should have found a spill register by now. */
5186 if (count >= n_spills)
5189 /* I is the index in SPILL_REG_RTX of the reload register we are to
5190 allocate. Get an rtx for it and find its register number. */
5192 return set_reload_reg (i, r);
5195 /* Initialize all the tables needed to allocate reload registers.
5196 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5197 is the array we use to restore the reg_rtx field for every reload. */
5200 choose_reload_regs_init (chain, save_reload_reg_rtx)
5201 struct insn_chain *chain;
5202 rtx *save_reload_reg_rtx;
5206 for (i = 0; i < n_reloads; i++)
5207 rld[i].reg_rtx = save_reload_reg_rtx[i];
5209 memset (reload_inherited, 0, MAX_RELOADS);
5210 memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5211 memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5213 CLEAR_HARD_REG_SET (reload_reg_used);
5214 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5215 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5216 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5217 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5218 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5220 CLEAR_HARD_REG_SET (reg_used_in_insn);
5223 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5224 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5225 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5226 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5227 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5228 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5231 for (i = 0; i < reload_n_operands; i++)
5233 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5234 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5235 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5236 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5237 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5238 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5241 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5243 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5245 for (i = 0; i < n_reloads; i++)
5246 /* If we have already decided to use a certain register,
5247 don't use it in another way. */
5249 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5250 rld[i].when_needed, rld[i].mode);
5253 /* Assign hard reg targets for the pseudo-registers we must reload
5254 into hard regs for this insn.
5255 Also output the instructions to copy them in and out of the hard regs.
5257 For machines with register classes, we are responsible for
5258 finding a reload reg in the proper class. */
5261 choose_reload_regs (chain)
5262 struct insn_chain *chain;
5264 rtx insn = chain->insn;
5266 unsigned int max_group_size = 1;
5267 enum reg_class group_class = NO_REGS;
5268 int pass, win, inheritance;
5270 rtx save_reload_reg_rtx[MAX_RELOADS];
5272 /* In order to be certain of getting the registers we need,
5273 we must sort the reloads into order of increasing register class.
5274 Then our grabbing of reload registers will parallel the process
5275 that provided the reload registers.
5277 Also note whether any of the reloads wants a consecutive group of regs.
5278 If so, record the maximum size of the group desired and what
5279 register class contains all the groups needed by this insn. */
5281 for (j = 0; j < n_reloads; j++)
5283 reload_order[j] = j;
5284 reload_spill_index[j] = -1;
5286 if (rld[j].nregs > 1)
5288 max_group_size = MAX (rld[j].nregs, max_group_size);
5290 = reg_class_superunion[(int) rld[j].class][(int)group_class];
5293 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5297 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5299 /* If -O, try first with inheritance, then turning it off.
5300 If not -O, don't do inheritance.
5301 Using inheritance when not optimizing leads to paradoxes
5302 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5303 because one side of the comparison might be inherited. */
5305 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5307 choose_reload_regs_init (chain, save_reload_reg_rtx);
5309 /* Process the reloads in order of preference just found.
5310 Beyond this point, subregs can be found in reload_reg_rtx.
5312 This used to look for an existing reloaded home for all of the
5313 reloads, and only then perform any new reloads. But that could lose
5314 if the reloads were done out of reg-class order because a later
5315 reload with a looser constraint might have an old home in a register
5316 needed by an earlier reload with a tighter constraint.
5318 To solve this, we make two passes over the reloads, in the order
5319 described above. In the first pass we try to inherit a reload
5320 from a previous insn. If there is a later reload that needs a
5321 class that is a proper subset of the class being processed, we must
5322 also allocate a spill register during the first pass.
5324 Then make a second pass over the reloads to allocate any reloads
5325 that haven't been given registers yet. */
5327 for (j = 0; j < n_reloads; j++)
5329 register int r = reload_order[j];
5330 rtx search_equiv = NULL_RTX;
5332 /* Ignore reloads that got marked inoperative. */
5333 if (rld[r].out == 0 && rld[r].in == 0
5334 && ! rld[r].secondary_p)
5337 /* If find_reloads chose to use reload_in or reload_out as a reload
5338 register, we don't need to chose one. Otherwise, try even if it
5339 found one since we might save an insn if we find the value lying
5341 Try also when reload_in is a pseudo without a hard reg. */
5342 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5343 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5344 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5345 && GET_CODE (rld[r].in) != MEM
5346 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5349 #if 0 /* No longer needed for correct operation.
5350 It might give better code, or might not; worth an experiment? */
5351 /* If this is an optional reload, we can't inherit from earlier insns
5352 until we are sure that any non-optional reloads have been allocated.
5353 The following code takes advantage of the fact that optional reloads
5354 are at the end of reload_order. */
5355 if (rld[r].optional != 0)
5356 for (i = 0; i < j; i++)
5357 if ((rld[reload_order[i]].out != 0
5358 || rld[reload_order[i]].in != 0
5359 || rld[reload_order[i]].secondary_p)
5360 && ! rld[reload_order[i]].optional
5361 && rld[reload_order[i]].reg_rtx == 0)
5362 allocate_reload_reg (chain, reload_order[i], 0);
5365 /* First see if this pseudo is already available as reloaded
5366 for a previous insn. We cannot try to inherit for reloads
5367 that are smaller than the maximum number of registers needed
5368 for groups unless the register we would allocate cannot be used
5371 We could check here to see if this is a secondary reload for
5372 an object that is already in a register of the desired class.
5373 This would avoid the need for the secondary reload register.
5374 But this is complex because we can't easily determine what
5375 objects might want to be loaded via this reload. So let a
5376 register be allocated here. In `emit_reload_insns' we suppress
5377 one of the loads in the case described above. */
5382 register int regno = -1;
5383 enum machine_mode mode = VOIDmode;
5387 else if (GET_CODE (rld[r].in) == REG)
5389 regno = REGNO (rld[r].in);
5390 mode = GET_MODE (rld[r].in);
5392 else if (GET_CODE (rld[r].in_reg) == REG)
5394 regno = REGNO (rld[r].in_reg);
5395 mode = GET_MODE (rld[r].in_reg);
5397 else if (GET_CODE (rld[r].in_reg) == SUBREG
5398 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5400 word = SUBREG_WORD (rld[r].in_reg);
5401 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5402 if (regno < FIRST_PSEUDO_REGISTER)
5404 mode = GET_MODE (rld[r].in_reg);
5407 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5408 || GET_CODE (rld[r].in_reg) == PRE_DEC
5409 || GET_CODE (rld[r].in_reg) == POST_INC
5410 || GET_CODE (rld[r].in_reg) == POST_DEC)
5411 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5413 regno = REGNO (XEXP (rld[r].in_reg, 0));
5414 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5415 rld[r].out = rld[r].in;
5419 /* This won't work, since REGNO can be a pseudo reg number.
5420 Also, it takes much more hair to keep track of all the things
5421 that can invalidate an inherited reload of part of a pseudoreg. */
5422 else if (GET_CODE (rld[r].in) == SUBREG
5423 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5424 regno = REGNO (SUBREG_REG (rld[r].in)) + SUBREG_WORD (rld[r].in);
5427 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5429 enum reg_class class = rld[r].class, last_class;
5430 rtx last_reg = reg_last_reload_reg[regno];
5431 enum machine_mode need_mode;
5433 i = REGNO (last_reg) + word;
5434 last_class = REGNO_REG_CLASS (i);
5440 = smallest_mode_for_size (GET_MODE_SIZE (mode)
5441 + word * UNITS_PER_WORD,
5442 GET_MODE_CLASS (mode));
5445 #ifdef CLASS_CANNOT_CHANGE_MODE
5447 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], i)
5448 ? ! CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (last_reg),
5450 : (GET_MODE_SIZE (GET_MODE (last_reg))
5451 >= GET_MODE_SIZE (need_mode)))
5453 (GET_MODE_SIZE (GET_MODE (last_reg))
5454 >= GET_MODE_SIZE (need_mode))
5456 && reg_reloaded_contents[i] == regno
5457 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5458 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5459 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5460 /* Even if we can't use this register as a reload
5461 register, we might use it for reload_override_in,
5462 if copying it to the desired class is cheap
5464 || ((REGISTER_MOVE_COST (mode, last_class, class)
5465 < MEMORY_MOVE_COST (mode, class, 1))
5466 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5467 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5471 #ifdef SECONDARY_MEMORY_NEEDED
5472 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5477 && (rld[r].nregs == max_group_size
5478 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5480 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5481 rld[r].when_needed, rld[r].in,
5484 /* If a group is needed, verify that all the subsequent
5485 registers still have their values intact. */
5486 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5489 for (k = 1; k < nr; k++)
5490 if (reg_reloaded_contents[i + k] != regno
5491 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5498 last_reg = (GET_MODE (last_reg) == mode
5499 ? last_reg : gen_rtx_REG (mode, i));
5501 /* We found a register that contains the
5502 value we need. If this register is the
5503 same as an `earlyclobber' operand of the
5504 current insn, just mark it as a place to
5505 reload from since we can't use it as the
5506 reload register itself. */
5508 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5509 if (reg_overlap_mentioned_for_reload_p
5510 (reg_last_reload_reg[regno],
5511 reload_earlyclobbers[i1]))
5514 if (i1 != n_earlyclobbers
5515 || ! (free_for_value_p (i, rld[r].mode,
5517 rld[r].when_needed, rld[r].in,
5519 /* Don't use it if we'd clobber a pseudo reg. */
5520 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5522 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5523 /* Don't clobber the frame pointer. */
5524 || (i == HARD_FRAME_POINTER_REGNUM
5526 /* Don't really use the inherited spill reg
5527 if we need it wider than we've got it. */
5528 || (GET_MODE_SIZE (rld[r].mode)
5529 > GET_MODE_SIZE (mode))
5530 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5533 /* If find_reloads chose reload_out as reload
5534 register, stay with it - that leaves the
5535 inherited register for subsequent reloads. */
5536 || (rld[r].out && rld[r].reg_rtx
5537 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5539 if (! rld[r].optional)
5541 reload_override_in[r] = last_reg;
5542 reload_inheritance_insn[r]
5543 = reg_reloaded_insn[i];
5549 /* We can use this as a reload reg. */
5550 /* Mark the register as in use for this part of
5552 mark_reload_reg_in_use (i,
5556 rld[r].reg_rtx = last_reg;
5557 reload_inherited[r] = 1;
5558 reload_inheritance_insn[r]
5559 = reg_reloaded_insn[i];
5560 reload_spill_index[r] = i;
5561 for (k = 0; k < nr; k++)
5562 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5570 /* Here's another way to see if the value is already lying around. */
5573 && ! reload_inherited[r]
5575 && (CONSTANT_P (rld[r].in)
5576 || GET_CODE (rld[r].in) == PLUS
5577 || GET_CODE (rld[r].in) == REG
5578 || GET_CODE (rld[r].in) == MEM)
5579 && (rld[r].nregs == max_group_size
5580 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5581 search_equiv = rld[r].in;
5582 /* If this is an output reload from a simple move insn, look
5583 if an equivalence for the input is available. */
5584 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5586 rtx set = single_set (insn);
5589 && rtx_equal_p (rld[r].out, SET_DEST (set))
5590 && CONSTANT_P (SET_SRC (set)))
5591 search_equiv = SET_SRC (set);
5597 = find_equiv_reg (search_equiv, insn, rld[r].class,
5598 -1, NULL_PTR, 0, rld[r].mode);
5603 if (GET_CODE (equiv) == REG)
5604 regno = REGNO (equiv);
5605 else if (GET_CODE (equiv) == SUBREG)
5607 /* This must be a SUBREG of a hard register.
5608 Make a new REG since this might be used in an
5609 address and not all machines support SUBREGs
5611 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5612 equiv = gen_rtx_REG (rld[r].mode, regno);
5618 /* If we found a spill reg, reject it unless it is free
5619 and of the desired class. */
5621 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5622 && ! free_for_value_p (regno, rld[r].mode,
5623 rld[r].opnum, rld[r].when_needed,
5624 rld[r].in, rld[r].out, r, 1))
5625 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5629 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5632 /* We found a register that contains the value we need.
5633 If this register is the same as an `earlyclobber' operand
5634 of the current insn, just mark it as a place to reload from
5635 since we can't use it as the reload register itself. */
5638 for (i = 0; i < n_earlyclobbers; i++)
5639 if (reg_overlap_mentioned_for_reload_p (equiv,
5640 reload_earlyclobbers[i]))
5642 if (! rld[r].optional)
5643 reload_override_in[r] = equiv;
5648 /* If the equiv register we have found is explicitly clobbered
5649 in the current insn, it depends on the reload type if we
5650 can use it, use it for reload_override_in, or not at all.
5651 In particular, we then can't use EQUIV for a
5652 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5656 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5657 switch (rld[r].when_needed)
5659 case RELOAD_FOR_OTHER_ADDRESS:
5660 case RELOAD_FOR_INPADDR_ADDRESS:
5661 case RELOAD_FOR_INPUT_ADDRESS:
5662 case RELOAD_FOR_OPADDR_ADDR:
5665 case RELOAD_FOR_INPUT:
5666 case RELOAD_FOR_OPERAND_ADDRESS:
5667 if (! rld[r].optional)
5668 reload_override_in[r] = equiv;
5674 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5675 switch (rld[r].when_needed)
5677 case RELOAD_FOR_OTHER_ADDRESS:
5678 case RELOAD_FOR_INPADDR_ADDRESS:
5679 case RELOAD_FOR_INPUT_ADDRESS:
5680 case RELOAD_FOR_OPADDR_ADDR:
5681 case RELOAD_FOR_OPERAND_ADDRESS:
5682 case RELOAD_FOR_INPUT:
5685 if (! rld[r].optional)
5686 reload_override_in[r] = equiv;
5694 /* If we found an equivalent reg, say no code need be generated
5695 to load it, and use it as our reload reg. */
5696 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5698 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5700 rld[r].reg_rtx = equiv;
5701 reload_inherited[r] = 1;
5703 /* If reg_reloaded_valid is not set for this register,
5704 there might be a stale spill_reg_store lying around.
5705 We must clear it, since otherwise emit_reload_insns
5706 might delete the store. */
5707 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5708 spill_reg_store[regno] = NULL_RTX;
5709 /* If any of the hard registers in EQUIV are spill
5710 registers, mark them as in use for this insn. */
5711 for (k = 0; k < nr; k++)
5713 i = spill_reg_order[regno + k];
5716 mark_reload_reg_in_use (regno, rld[r].opnum,
5719 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5726 /* If we found a register to use already, or if this is an optional
5727 reload, we are done. */
5728 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5732 /* No longer needed for correct operation. Might or might
5733 not give better code on the average. Want to experiment? */
5735 /* See if there is a later reload that has a class different from our
5736 class that intersects our class or that requires less register
5737 than our reload. If so, we must allocate a register to this
5738 reload now, since that reload might inherit a previous reload
5739 and take the only available register in our class. Don't do this
5740 for optional reloads since they will force all previous reloads
5741 to be allocated. Also don't do this for reloads that have been
5744 for (i = j + 1; i < n_reloads; i++)
5746 int s = reload_order[i];
5748 if ((rld[s].in == 0 && rld[s].out == 0
5749 && ! rld[s].secondary_p)
5753 if ((rld[s].class != rld[r].class
5754 && reg_classes_intersect_p (rld[r].class,
5756 || rld[s].nregs < rld[r].nregs)
5763 allocate_reload_reg (chain, r, j == n_reloads - 1);
5767 /* Now allocate reload registers for anything non-optional that
5768 didn't get one yet. */
5769 for (j = 0; j < n_reloads; j++)
5771 register int r = reload_order[j];
5773 /* Ignore reloads that got marked inoperative. */
5774 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5777 /* Skip reloads that already have a register allocated or are
5779 if (rld[r].reg_rtx != 0 || rld[r].optional)
5782 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5786 /* If that loop got all the way, we have won. */
5793 /* Loop around and try without any inheritance. */
5798 /* First undo everything done by the failed attempt
5799 to allocate with inheritance. */
5800 choose_reload_regs_init (chain, save_reload_reg_rtx);
5802 /* Some sanity tests to verify that the reloads found in the first
5803 pass are identical to the ones we have now. */
5804 if (chain->n_reloads != n_reloads)
5807 for (i = 0; i < n_reloads; i++)
5809 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5811 if (chain->rld[i].when_needed != rld[i].when_needed)
5813 for (j = 0; j < n_spills; j++)
5814 if (spill_regs[j] == chain->rld[i].regno)
5815 if (! set_reload_reg (j, i))
5816 failed_reload (chain->insn, i);
5820 /* If we thought we could inherit a reload, because it seemed that
5821 nothing else wanted the same reload register earlier in the insn,
5822 verify that assumption, now that all reloads have been assigned.
5823 Likewise for reloads where reload_override_in has been set. */
5825 /* If doing expensive optimizations, do one preliminary pass that doesn't
5826 cancel any inheritance, but removes reloads that have been needed only
5827 for reloads that we know can be inherited. */
5828 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5830 for (j = 0; j < n_reloads; j++)
5832 register int r = reload_order[j];
5834 if (reload_inherited[r] && rld[r].reg_rtx)
5835 check_reg = rld[r].reg_rtx;
5836 else if (reload_override_in[r]
5837 && (GET_CODE (reload_override_in[r]) == REG
5838 || GET_CODE (reload_override_in[r]) == SUBREG))
5839 check_reg = reload_override_in[r];
5842 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5843 rld[r].opnum, rld[r].when_needed, rld[r].in,
5844 (reload_inherited[r]
5845 ? rld[r].out : const0_rtx),
5850 reload_inherited[r] = 0;
5851 reload_override_in[r] = 0;
5853 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5854 reload_override_in, then we do not need its related
5855 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5856 likewise for other reload types.
5857 We handle this by removing a reload when its only replacement
5858 is mentioned in reload_in of the reload we are going to inherit.
5859 A special case are auto_inc expressions; even if the input is
5860 inherited, we still need the address for the output. We can
5861 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5862 If we suceeded removing some reload and we are doing a preliminary
5863 pass just to remove such reloads, make another pass, since the
5864 removal of one reload might allow us to inherit another one. */
5866 && rld[r].out != rld[r].in
5867 && remove_address_replacements (rld[r].in) && pass)
5872 /* Now that reload_override_in is known valid,
5873 actually override reload_in. */
5874 for (j = 0; j < n_reloads; j++)
5875 if (reload_override_in[j])
5876 rld[j].in = reload_override_in[j];
5878 /* If this reload won't be done because it has been cancelled or is
5879 optional and not inherited, clear reload_reg_rtx so other
5880 routines (such as subst_reloads) don't get confused. */
5881 for (j = 0; j < n_reloads; j++)
5882 if (rld[j].reg_rtx != 0
5883 && ((rld[j].optional && ! reload_inherited[j])
5884 || (rld[j].in == 0 && rld[j].out == 0
5885 && ! rld[j].secondary_p)))
5887 int regno = true_regnum (rld[j].reg_rtx);
5889 if (spill_reg_order[regno] >= 0)
5890 clear_reload_reg_in_use (regno, rld[j].opnum,
5891 rld[j].when_needed, rld[j].mode);
5893 reload_spill_index[j] = -1;
5896 /* Record which pseudos and which spill regs have output reloads. */
5897 for (j = 0; j < n_reloads; j++)
5899 register int r = reload_order[j];
5901 i = reload_spill_index[r];
5903 /* I is nonneg if this reload uses a register.
5904 If rld[r].reg_rtx is 0, this is an optional reload
5905 that we opted to ignore. */
5906 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5907 && rld[r].reg_rtx != 0)
5909 register int nregno = REGNO (rld[r].out_reg);
5912 if (nregno < FIRST_PSEUDO_REGISTER)
5913 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5916 reg_has_output_reload[nregno + nr] = 1;
5920 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5922 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5925 if (rld[r].when_needed != RELOAD_OTHER
5926 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5927 && rld[r].when_needed != RELOAD_FOR_INSN)
5933 /* Deallocate the reload register for reload R. This is called from
5934 remove_address_replacements. */
5937 deallocate_reload_reg (r)
5942 if (! rld[r].reg_rtx)
5944 regno = true_regnum (rld[r].reg_rtx);
5946 if (spill_reg_order[regno] >= 0)
5947 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5949 reload_spill_index[r] = -1;
5952 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5953 reloads of the same item for fear that we might not have enough reload
5954 registers. However, normally they will get the same reload register
5955 and hence actually need not be loaded twice.
5957 Here we check for the most common case of this phenomenon: when we have
5958 a number of reloads for the same object, each of which were allocated
5959 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5960 reload, and is not modified in the insn itself. If we find such,
5961 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5962 This will not increase the number of spill registers needed and will
5963 prevent redundant code. */
5966 merge_assigned_reloads (insn)
5971 /* Scan all the reloads looking for ones that only load values and
5972 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5973 assigned and not modified by INSN. */
5975 for (i = 0; i < n_reloads; i++)
5977 int conflicting_input = 0;
5978 int max_input_address_opnum = -1;
5979 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5981 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5982 || rld[i].out != 0 || rld[i].reg_rtx == 0
5983 || reg_set_p (rld[i].reg_rtx, insn))
5986 /* Look at all other reloads. Ensure that the only use of this
5987 reload_reg_rtx is in a reload that just loads the same value
5988 as we do. Note that any secondary reloads must be of the identical
5989 class since the values, modes, and result registers are the
5990 same, so we need not do anything with any secondary reloads. */
5992 for (j = 0; j < n_reloads; j++)
5994 if (i == j || rld[j].reg_rtx == 0
5995 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
5999 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6000 && rld[j].opnum > max_input_address_opnum)
6001 max_input_address_opnum = rld[j].opnum;
6003 /* If the reload regs aren't exactly the same (e.g, different modes)
6004 or if the values are different, we can't merge this reload.
6005 But if it is an input reload, we might still merge
6006 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6008 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6009 || rld[j].out != 0 || rld[j].in == 0
6010 || ! rtx_equal_p (rld[i].in, rld[j].in))
6012 if (rld[j].when_needed != RELOAD_FOR_INPUT
6013 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6014 || rld[i].opnum > rld[j].opnum)
6015 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6017 conflicting_input = 1;
6018 if (min_conflicting_input_opnum > rld[j].opnum)
6019 min_conflicting_input_opnum = rld[j].opnum;
6023 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6024 we, in fact, found any matching reloads. */
6027 && max_input_address_opnum <= min_conflicting_input_opnum)
6029 for (j = 0; j < n_reloads; j++)
6030 if (i != j && rld[j].reg_rtx != 0
6031 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6032 && (! conflicting_input
6033 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6034 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6036 rld[i].when_needed = RELOAD_OTHER;
6038 reload_spill_index[j] = -1;
6039 transfer_replacements (i, j);
6042 /* If this is now RELOAD_OTHER, look for any reloads that load
6043 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6044 if they were for inputs, RELOAD_OTHER for outputs. Note that
6045 this test is equivalent to looking for reloads for this operand
6048 if (rld[i].when_needed == RELOAD_OTHER)
6049 for (j = 0; j < n_reloads; j++)
6051 && rld[i].when_needed != RELOAD_OTHER
6052 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6055 = ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
6056 || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6057 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6062 /* These arrays are filled by emit_reload_insns and its subroutines. */
6063 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6064 static rtx other_input_address_reload_insns = 0;
6065 static rtx other_input_reload_insns = 0;
6066 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6067 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6068 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6069 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6070 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6071 static rtx operand_reload_insns = 0;
6072 static rtx other_operand_reload_insns = 0;
6073 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6075 /* Values to be put in spill_reg_store are put here first. */
6076 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6077 static HARD_REG_SET reg_reloaded_died;
6079 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6080 has the number J. OLD contains the value to be used as input. */
6083 emit_input_reload_insns (chain, rl, old, j)
6084 struct insn_chain *chain;
6089 rtx insn = chain->insn;
6090 register rtx reloadreg = rl->reg_rtx;
6091 rtx oldequiv_reg = 0;
6094 enum machine_mode mode;
6097 /* Determine the mode to reload in.
6098 This is very tricky because we have three to choose from.
6099 There is the mode the insn operand wants (rl->inmode).
6100 There is the mode of the reload register RELOADREG.
6101 There is the intrinsic mode of the operand, which we could find
6102 by stripping some SUBREGs.
6103 It turns out that RELOADREG's mode is irrelevant:
6104 we can change that arbitrarily.
6106 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6107 then the reload reg may not support QImode moves, so use SImode.
6108 If foo is in memory due to spilling a pseudo reg, this is safe,
6109 because the QImode value is in the least significant part of a
6110 slot big enough for a SImode. If foo is some other sort of
6111 memory reference, then it is impossible to reload this case,
6112 so previous passes had better make sure this never happens.
6114 Then consider a one-word union which has SImode and one of its
6115 members is a float, being fetched as (SUBREG:SF union:SI).
6116 We must fetch that as SFmode because we could be loading into
6117 a float-only register. In this case OLD's mode is correct.
6119 Consider an immediate integer: it has VOIDmode. Here we need
6120 to get a mode from something else.
6122 In some cases, there is a fourth mode, the operand's
6123 containing mode. If the insn specifies a containing mode for
6124 this operand, it overrides all others.
6126 I am not sure whether the algorithm here is always right,
6127 but it does the right things in those cases. */
6129 mode = GET_MODE (old);
6130 if (mode == VOIDmode)
6133 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6134 /* If we need a secondary register for this operation, see if
6135 the value is already in a register in that class. Don't
6136 do this if the secondary register will be used as a scratch
6139 if (rl->secondary_in_reload >= 0
6140 && rl->secondary_in_icode == CODE_FOR_nothing
6143 = find_equiv_reg (old, insn,
6144 rld[rl->secondary_in_reload].class,
6145 -1, NULL_PTR, 0, mode);
6148 /* If reloading from memory, see if there is a register
6149 that already holds the same value. If so, reload from there.
6150 We can pass 0 as the reload_reg_p argument because
6151 any other reload has either already been emitted,
6152 in which case find_equiv_reg will see the reload-insn,
6153 or has yet to be emitted, in which case it doesn't matter
6154 because we will use this equiv reg right away. */
6156 if (oldequiv == 0 && optimize
6157 && (GET_CODE (old) == MEM
6158 || (GET_CODE (old) == REG
6159 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6160 && reg_renumber[REGNO (old)] < 0)))
6161 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6162 -1, NULL_PTR, 0, mode);
6166 unsigned int regno = true_regnum (oldequiv);
6168 /* Don't use OLDEQUIV if any other reload changes it at an
6169 earlier stage of this insn or at this stage. */
6170 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6171 rl->in, const0_rtx, j, 0))
6174 /* If it is no cheaper to copy from OLDEQUIV into the
6175 reload register than it would be to move from memory,
6176 don't use it. Likewise, if we need a secondary register
6180 && ((REGNO_REG_CLASS (regno) != rl->class
6181 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6183 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6184 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6185 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6189 #ifdef SECONDARY_MEMORY_NEEDED
6190 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6198 /* delete_output_reload is only invoked properly if old contains
6199 the original pseudo register. Since this is replaced with a
6200 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6201 find the pseudo in RELOAD_IN_REG. */
6203 && reload_override_in[j]
6204 && GET_CODE (rl->in_reg) == REG)
6211 else if (GET_CODE (oldequiv) == REG)
6212 oldequiv_reg = oldequiv;
6213 else if (GET_CODE (oldequiv) == SUBREG)
6214 oldequiv_reg = SUBREG_REG (oldequiv);
6216 /* If we are reloading from a register that was recently stored in
6217 with an output-reload, see if we can prove there was
6218 actually no need to store the old value in it. */
6220 if (optimize && GET_CODE (oldequiv) == REG
6221 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6222 && spill_reg_store[REGNO (oldequiv)]
6223 && GET_CODE (old) == REG
6224 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6225 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6227 delete_output_reload (insn, j, REGNO (oldequiv));
6229 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6230 then load RELOADREG from OLDEQUIV. Note that we cannot use
6231 gen_lowpart_common since it can do the wrong thing when
6232 RELOADREG has a multi-word mode. Note that RELOADREG
6233 must always be a REG here. */
6235 if (GET_MODE (reloadreg) != mode)
6236 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6237 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6238 oldequiv = SUBREG_REG (oldequiv);
6239 if (GET_MODE (oldequiv) != VOIDmode
6240 && mode != GET_MODE (oldequiv))
6241 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6243 /* Switch to the right place to emit the reload insns. */
6244 switch (rl->when_needed)
6247 where = &other_input_reload_insns;
6249 case RELOAD_FOR_INPUT:
6250 where = &input_reload_insns[rl->opnum];
6252 case RELOAD_FOR_INPUT_ADDRESS:
6253 where = &input_address_reload_insns[rl->opnum];
6255 case RELOAD_FOR_INPADDR_ADDRESS:
6256 where = &inpaddr_address_reload_insns[rl->opnum];
6258 case RELOAD_FOR_OUTPUT_ADDRESS:
6259 where = &output_address_reload_insns[rl->opnum];
6261 case RELOAD_FOR_OUTADDR_ADDRESS:
6262 where = &outaddr_address_reload_insns[rl->opnum];
6264 case RELOAD_FOR_OPERAND_ADDRESS:
6265 where = &operand_reload_insns;
6267 case RELOAD_FOR_OPADDR_ADDR:
6268 where = &other_operand_reload_insns;
6270 case RELOAD_FOR_OTHER_ADDRESS:
6271 where = &other_input_address_reload_insns;
6277 push_to_sequence (*where);
6279 /* Auto-increment addresses must be reloaded in a special way. */
6280 if (rl->out && ! rl->out_reg)
6282 /* We are not going to bother supporting the case where a
6283 incremented register can't be copied directly from
6284 OLDEQUIV since this seems highly unlikely. */
6285 if (rl->secondary_in_reload >= 0)
6288 if (reload_inherited[j])
6289 oldequiv = reloadreg;
6291 old = XEXP (rl->in_reg, 0);
6293 if (optimize && GET_CODE (oldequiv) == REG
6294 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6295 && spill_reg_store[REGNO (oldequiv)]
6296 && GET_CODE (old) == REG
6297 && (dead_or_set_p (insn,
6298 spill_reg_stored_to[REGNO (oldequiv)])
6299 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6301 delete_output_reload (insn, j, REGNO (oldequiv));
6303 /* Prevent normal processing of this reload. */
6305 /* Output a special code sequence for this case. */
6306 new_spill_reg_store[REGNO (reloadreg)]
6307 = inc_for_reload (reloadreg, oldequiv, rl->out,
6311 /* If we are reloading a pseudo-register that was set by the previous
6312 insn, see if we can get rid of that pseudo-register entirely
6313 by redirecting the previous insn into our reload register. */
6315 else if (optimize && GET_CODE (old) == REG
6316 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6317 && dead_or_set_p (insn, old)
6318 /* This is unsafe if some other reload
6319 uses the same reg first. */
6320 && ! conflicts_with_override (reloadreg)
6321 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6322 rl->when_needed, old, rl->out, j, 0))
6324 rtx temp = PREV_INSN (insn);
6325 while (temp && GET_CODE (temp) == NOTE)
6326 temp = PREV_INSN (temp);
6328 && GET_CODE (temp) == INSN
6329 && GET_CODE (PATTERN (temp)) == SET
6330 && SET_DEST (PATTERN (temp)) == old
6331 /* Make sure we can access insn_operand_constraint. */
6332 && asm_noperands (PATTERN (temp)) < 0
6333 /* This is unsafe if prev insn rejects our reload reg. */
6334 && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint,
6336 /* This is unsafe if operand occurs more than once in current
6337 insn. Perhaps some occurrences aren't reloaded. */
6338 && count_occurrences (PATTERN (insn), old, 0) == 1
6339 /* Don't risk splitting a matching pair of operands. */
6340 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6342 /* Store into the reload register instead of the pseudo. */
6343 SET_DEST (PATTERN (temp)) = reloadreg;
6345 /* If the previous insn is an output reload, the source is
6346 a reload register, and its spill_reg_store entry will
6347 contain the previous destination. This is now
6349 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6350 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6352 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6353 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6356 /* If these are the only uses of the pseudo reg,
6357 pretend for GDB it lives in the reload reg we used. */
6358 if (REG_N_DEATHS (REGNO (old)) == 1
6359 && REG_N_SETS (REGNO (old)) == 1)
6361 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6362 alter_reg (REGNO (old), -1);
6368 /* We can't do that, so output an insn to load RELOADREG. */
6370 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6371 /* If we have a secondary reload, pick up the secondary register
6372 and icode, if any. If OLDEQUIV and OLD are different or
6373 if this is an in-out reload, recompute whether or not we
6374 still need a secondary register and what the icode should
6375 be. If we still need a secondary register and the class or
6376 icode is different, go back to reloading from OLD if using
6377 OLDEQUIV means that we got the wrong type of register. We
6378 cannot have different class or icode due to an in-out reload
6379 because we don't make such reloads when both the input and
6380 output need secondary reload registers. */
6382 if (! special && rl->secondary_in_reload >= 0)
6384 rtx second_reload_reg = 0;
6385 int secondary_reload = rl->secondary_in_reload;
6386 rtx real_oldequiv = oldequiv;
6389 enum insn_code icode;
6391 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6392 and similarly for OLD.
6393 See comments in get_secondary_reload in reload.c. */
6394 /* If it is a pseudo that cannot be replaced with its
6395 equivalent MEM, we must fall back to reload_in, which
6396 will have all the necessary substitutions registered.
6397 Likewise for a pseudo that can't be replaced with its
6398 equivalent constant.
6400 Take extra care for subregs of such pseudos. Note that
6401 we cannot use reg_equiv_mem in this case because it is
6402 not in the right mode. */
6405 if (GET_CODE (tmp) == SUBREG)
6406 tmp = SUBREG_REG (tmp);
6407 if (GET_CODE (tmp) == REG
6408 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6409 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6410 || reg_equiv_constant[REGNO (tmp)] != 0))
6412 if (! reg_equiv_mem[REGNO (tmp)]
6413 || num_not_at_initial_offset
6414 || GET_CODE (oldequiv) == SUBREG)
6415 real_oldequiv = rl->in;
6417 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6421 if (GET_CODE (tmp) == SUBREG)
6422 tmp = SUBREG_REG (tmp);
6423 if (GET_CODE (tmp) == REG
6424 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6425 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6426 || reg_equiv_constant[REGNO (tmp)] != 0))
6428 if (! reg_equiv_mem[REGNO (tmp)]
6429 || num_not_at_initial_offset
6430 || GET_CODE (old) == SUBREG)
6433 real_old = reg_equiv_mem[REGNO (tmp)];
6436 second_reload_reg = rld[secondary_reload].reg_rtx;
6437 icode = rl->secondary_in_icode;
6439 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6440 || (rl->in != 0 && rl->out != 0))
6442 enum reg_class new_class
6443 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6444 mode, real_oldequiv);
6446 if (new_class == NO_REGS)
6447 second_reload_reg = 0;
6450 enum insn_code new_icode;
6451 enum machine_mode new_mode;
6453 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6454 REGNO (second_reload_reg)))
6455 oldequiv = old, real_oldequiv = real_old;
6458 new_icode = reload_in_optab[(int) mode];
6459 if (new_icode != CODE_FOR_nothing
6460 && ((insn_data[(int) new_icode].operand[0].predicate
6461 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6463 || (insn_data[(int) new_icode].operand[1].predicate
6464 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6465 (real_oldequiv, mode)))))
6466 new_icode = CODE_FOR_nothing;
6468 if (new_icode == CODE_FOR_nothing)
6471 new_mode = insn_data[(int) new_icode].operand[2].mode;
6473 if (GET_MODE (second_reload_reg) != new_mode)
6475 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6477 oldequiv = old, real_oldequiv = real_old;
6480 = gen_rtx_REG (new_mode,
6481 REGNO (second_reload_reg));
6487 /* If we still need a secondary reload register, check
6488 to see if it is being used as a scratch or intermediate
6489 register and generate code appropriately. If we need
6490 a scratch register, use REAL_OLDEQUIV since the form of
6491 the insn may depend on the actual address if it is
6494 if (second_reload_reg)
6496 if (icode != CODE_FOR_nothing)
6498 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6499 second_reload_reg));
6504 /* See if we need a scratch register to load the
6505 intermediate register (a tertiary reload). */
6506 enum insn_code tertiary_icode
6507 = rld[secondary_reload].secondary_in_icode;
6509 if (tertiary_icode != CODE_FOR_nothing)
6511 rtx third_reload_reg
6512 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6514 emit_insn ((GEN_FCN (tertiary_icode)
6515 (second_reload_reg, real_oldequiv,
6516 third_reload_reg)));
6519 gen_reload (second_reload_reg, real_oldequiv,
6523 oldequiv = second_reload_reg;
6529 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6531 rtx real_oldequiv = oldequiv;
6533 if ((GET_CODE (oldequiv) == REG
6534 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6535 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6536 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6537 || (GET_CODE (oldequiv) == SUBREG
6538 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6539 && (REGNO (SUBREG_REG (oldequiv))
6540 >= FIRST_PSEUDO_REGISTER)
6541 && ((reg_equiv_memory_loc
6542 [REGNO (SUBREG_REG (oldequiv))] != 0)
6543 || (reg_equiv_constant
6544 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6545 || (CONSTANT_P (oldequiv)
6546 && PREFERRED_RELOAD_CLASS (oldequiv,
6547 REGNO_REG_CLASS (REGNO (reloadreg))) == NO_REGS))
6548 real_oldequiv = rl->in;
6549 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6553 /* End this sequence. */
6554 *where = get_insns ();
6557 /* Update reload_override_in so that delete_address_reloads_1
6558 can see the actual register usage. */
6560 reload_override_in[j] = oldequiv;
6563 /* Generate insns to for the output reload RL, which is for the insn described
6564 by CHAIN and has the number J. */
6566 emit_output_reload_insns (chain, rl, j)
6567 struct insn_chain *chain;
6571 rtx reloadreg = rl->reg_rtx;
6572 rtx insn = chain->insn;
6575 enum machine_mode mode = GET_MODE (old);
6578 if (rl->when_needed == RELOAD_OTHER)
6581 push_to_sequence (output_reload_insns[rl->opnum]);
6583 /* Determine the mode to reload in.
6584 See comments above (for input reloading). */
6586 if (mode == VOIDmode)
6588 /* VOIDmode should never happen for an output. */
6589 if (asm_noperands (PATTERN (insn)) < 0)
6590 /* It's the compiler's fault. */
6591 fatal_insn ("VOIDmode on an output", insn);
6592 error_for_asm (insn, "output operand is constant in `asm'");
6593 /* Prevent crash--use something we know is valid. */
6595 old = gen_rtx_REG (mode, REGNO (reloadreg));
6598 if (GET_MODE (reloadreg) != mode)
6599 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6601 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6603 /* If we need two reload regs, set RELOADREG to the intermediate
6604 one, since it will be stored into OLD. We might need a secondary
6605 register only for an input reload, so check again here. */
6607 if (rl->secondary_out_reload >= 0)
6611 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6612 && reg_equiv_mem[REGNO (old)] != 0)
6613 real_old = reg_equiv_mem[REGNO (old)];
6615 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6619 rtx second_reloadreg = reloadreg;
6620 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6622 /* See if RELOADREG is to be used as a scratch register
6623 or as an intermediate register. */
6624 if (rl->secondary_out_icode != CODE_FOR_nothing)
6626 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6627 (real_old, second_reloadreg, reloadreg)));
6632 /* See if we need both a scratch and intermediate reload
6635 int secondary_reload = rl->secondary_out_reload;
6636 enum insn_code tertiary_icode
6637 = rld[secondary_reload].secondary_out_icode;
6639 if (GET_MODE (reloadreg) != mode)
6640 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6642 if (tertiary_icode != CODE_FOR_nothing)
6645 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6648 /* Copy primary reload reg to secondary reload reg.
6649 (Note that these have been swapped above, then
6650 secondary reload reg to OLD using our insn. */
6652 /* If REAL_OLD is a paradoxical SUBREG, remove it
6653 and try to put the opposite SUBREG on
6655 if (GET_CODE (real_old) == SUBREG
6656 && (GET_MODE_SIZE (GET_MODE (real_old))
6657 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6658 && 0 != (tem = gen_lowpart_common
6659 (GET_MODE (SUBREG_REG (real_old)),
6661 real_old = SUBREG_REG (real_old), reloadreg = tem;
6663 gen_reload (reloadreg, second_reloadreg,
6664 rl->opnum, rl->when_needed);
6665 emit_insn ((GEN_FCN (tertiary_icode)
6666 (real_old, reloadreg, third_reloadreg)));
6671 /* Copy between the reload regs here and then to
6674 gen_reload (reloadreg, second_reloadreg,
6675 rl->opnum, rl->when_needed);
6681 /* Output the last reload insn. */
6686 /* Don't output the last reload if OLD is not the dest of
6687 INSN and is in the src and is clobbered by INSN. */
6688 if (! flag_expensive_optimizations
6689 || GET_CODE (old) != REG
6690 || !(set = single_set (insn))
6691 || rtx_equal_p (old, SET_DEST (set))
6692 || !reg_mentioned_p (old, SET_SRC (set))
6693 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6694 gen_reload (old, reloadreg, rl->opnum,
6698 /* Look at all insns we emitted, just to be safe. */
6699 for (p = get_insns (); p; p = NEXT_INSN (p))
6702 rtx pat = PATTERN (p);
6704 /* If this output reload doesn't come from a spill reg,
6705 clear any memory of reloaded copies of the pseudo reg.
6706 If this output reload comes from a spill reg,
6707 reg_has_output_reload will make this do nothing. */
6708 note_stores (pat, forget_old_reloads_1, NULL);
6710 if (reg_mentioned_p (rl->reg_rtx, pat))
6712 rtx set = single_set (insn);
6713 if (reload_spill_index[j] < 0
6715 && SET_SRC (set) == rl->reg_rtx)
6717 int src = REGNO (SET_SRC (set));
6719 reload_spill_index[j] = src;
6720 SET_HARD_REG_BIT (reg_is_output_reload, src);
6721 if (find_regno_note (insn, REG_DEAD, src))
6722 SET_HARD_REG_BIT (reg_reloaded_died, src);
6724 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6726 int s = rl->secondary_out_reload;
6727 set = single_set (p);
6728 /* If this reload copies only to the secondary reload
6729 register, the secondary reload does the actual
6731 if (s >= 0 && set == NULL_RTX)
6732 /* We can't tell what function the secondary reload
6733 has and where the actual store to the pseudo is
6734 made; leave new_spill_reg_store alone. */
6737 && SET_SRC (set) == rl->reg_rtx
6738 && SET_DEST (set) == rld[s].reg_rtx)
6740 /* Usually the next instruction will be the
6741 secondary reload insn; if we can confirm
6742 that it is, setting new_spill_reg_store to
6743 that insn will allow an extra optimization. */
6744 rtx s_reg = rld[s].reg_rtx;
6745 rtx next = NEXT_INSN (p);
6746 rld[s].out = rl->out;
6747 rld[s].out_reg = rl->out_reg;
6748 set = single_set (next);
6749 if (set && SET_SRC (set) == s_reg
6750 && ! new_spill_reg_store[REGNO (s_reg)])
6752 SET_HARD_REG_BIT (reg_is_output_reload,
6754 new_spill_reg_store[REGNO (s_reg)] = next;
6758 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6763 if (rl->when_needed == RELOAD_OTHER)
6765 emit_insns (other_output_reload_insns[rl->opnum]);
6766 other_output_reload_insns[rl->opnum] = get_insns ();
6769 output_reload_insns[rl->opnum] = get_insns ();
6774 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6775 and has the number J. */
6777 do_input_reload (chain, rl, j)
6778 struct insn_chain *chain;
6782 int expect_occurrences = 1;
6783 rtx insn = chain->insn;
6784 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6785 ? rl->in_reg : rl->in);
6788 /* AUTO_INC reloads need to be handled even if inherited. We got an
6789 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6790 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6791 && ! rtx_equal_p (rl->reg_rtx, old)
6792 && rl->reg_rtx != 0)
6793 emit_input_reload_insns (chain, rld + j, old, j);
6795 /* When inheriting a wider reload, we have a MEM in rl->in,
6796 e.g. inheriting a SImode output reload for
6797 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6798 if (optimize && reload_inherited[j] && rl->in
6799 && GET_CODE (rl->in) == MEM
6800 && GET_CODE (rl->in_reg) == MEM
6801 && reload_spill_index[j] >= 0
6802 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6805 = count_occurrences (PATTERN (insn), rl->in, 0) == 1 ? 0 : -1;
6806 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6809 /* If we are reloading a register that was recently stored in with an
6810 output-reload, see if we can prove there was
6811 actually no need to store the old value in it. */
6814 && (reload_inherited[j] || reload_override_in[j])
6816 && GET_CODE (rl->reg_rtx) == REG
6817 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6819 /* There doesn't seem to be any reason to restrict this to pseudos
6820 and doing so loses in the case where we are copying from a
6821 register of the wrong class. */
6822 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6823 >= FIRST_PSEUDO_REGISTER)
6825 /* The insn might have already some references to stackslots
6826 replaced by MEMs, while reload_out_reg still names the
6828 && (dead_or_set_p (insn,
6829 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6830 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6832 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6835 /* Do output reloading for reload RL, which is for the insn described by
6836 CHAIN and has the number J.
6837 ??? At some point we need to support handling output reloads of
6838 JUMP_INSNs or insns that set cc0. */
6840 do_output_reload (chain, rl, j)
6841 struct insn_chain *chain;
6846 rtx insn = chain->insn;
6847 /* If this is an output reload that stores something that is
6848 not loaded in this same reload, see if we can eliminate a previous
6850 rtx pseudo = rl->out_reg;
6853 && GET_CODE (pseudo) == REG
6854 && ! rtx_equal_p (rl->in_reg, pseudo)
6855 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6856 && reg_last_reload_reg[REGNO (pseudo)])
6858 int pseudo_no = REGNO (pseudo);
6859 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6861 /* We don't need to test full validity of last_regno for
6862 inherit here; we only want to know if the store actually
6863 matches the pseudo. */
6864 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6865 && reg_reloaded_contents[last_regno] == pseudo_no
6866 && spill_reg_store[last_regno]
6867 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6868 delete_output_reload (insn, j, last_regno);
6873 || rl->reg_rtx == old
6874 || rl->reg_rtx == 0)
6877 /* An output operand that dies right away does need a reload,
6878 but need not be copied from it. Show the new location in the
6880 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6881 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6883 XEXP (note, 0) = rl->reg_rtx;
6886 /* Likewise for a SUBREG of an operand that dies. */
6887 else if (GET_CODE (old) == SUBREG
6888 && GET_CODE (SUBREG_REG (old)) == REG
6889 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6892 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6896 else if (GET_CODE (old) == SCRATCH)
6897 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6898 but we don't want to make an output reload. */
6901 /* If is a JUMP_INSN, we can't support output reloads yet. */
6902 if (GET_CODE (insn) == JUMP_INSN)
6905 emit_output_reload_insns (chain, rld + j, j);
6908 /* Output insns to reload values in and out of the chosen reload regs. */
6911 emit_reload_insns (chain)
6912 struct insn_chain *chain;
6914 rtx insn = chain->insn;
6917 rtx following_insn = NEXT_INSN (insn);
6918 rtx before_insn = PREV_INSN (insn);
6920 CLEAR_HARD_REG_SET (reg_reloaded_died);
6922 for (j = 0; j < reload_n_operands; j++)
6923 input_reload_insns[j] = input_address_reload_insns[j]
6924 = inpaddr_address_reload_insns[j]
6925 = output_reload_insns[j] = output_address_reload_insns[j]
6926 = outaddr_address_reload_insns[j]
6927 = other_output_reload_insns[j] = 0;
6928 other_input_address_reload_insns = 0;
6929 other_input_reload_insns = 0;
6930 operand_reload_insns = 0;
6931 other_operand_reload_insns = 0;
6933 /* Dump reloads into the dump file. */
6936 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6937 debug_reload_to_stream (rtl_dump_file);
6940 /* Now output the instructions to copy the data into and out of the
6941 reload registers. Do these in the order that the reloads were reported,
6942 since reloads of base and index registers precede reloads of operands
6943 and the operands may need the base and index registers reloaded. */
6945 for (j = 0; j < n_reloads; j++)
6948 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6949 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6951 do_input_reload (chain, rld + j, j);
6952 do_output_reload (chain, rld + j, j);
6955 /* Now write all the insns we made for reloads in the order expected by
6956 the allocation functions. Prior to the insn being reloaded, we write
6957 the following reloads:
6959 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6961 RELOAD_OTHER reloads.
6963 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6964 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6965 RELOAD_FOR_INPUT reload for the operand.
6967 RELOAD_FOR_OPADDR_ADDRS reloads.
6969 RELOAD_FOR_OPERAND_ADDRESS reloads.
6971 After the insn being reloaded, we write the following:
6973 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6974 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6975 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6976 reloads for the operand. The RELOAD_OTHER output reloads are
6977 output in descending order by reload number. */
6979 emit_insns_before (other_input_address_reload_insns, insn);
6980 emit_insns_before (other_input_reload_insns, insn);
6982 for (j = 0; j < reload_n_operands; j++)
6984 emit_insns_before (inpaddr_address_reload_insns[j], insn);
6985 emit_insns_before (input_address_reload_insns[j], insn);
6986 emit_insns_before (input_reload_insns[j], insn);
6989 emit_insns_before (other_operand_reload_insns, insn);
6990 emit_insns_before (operand_reload_insns, insn);
6992 for (j = 0; j < reload_n_operands; j++)
6994 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
6995 emit_insns_before (output_address_reload_insns[j], following_insn);
6996 emit_insns_before (output_reload_insns[j], following_insn);
6997 emit_insns_before (other_output_reload_insns[j], following_insn);
7000 /* Keep basic block info up to date. */
7003 if (BLOCK_HEAD (chain->block) == insn)
7004 BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
7005 if (BLOCK_END (chain->block) == insn)
7006 BLOCK_END (chain->block) = PREV_INSN (following_insn);
7009 /* For all the spill regs newly reloaded in this instruction,
7010 record what they were reloaded from, so subsequent instructions
7011 can inherit the reloads.
7013 Update spill_reg_store for the reloads of this insn.
7014 Copy the elements that were updated in the loop above. */
7016 for (j = 0; j < n_reloads; j++)
7018 register int r = reload_order[j];
7019 register int i = reload_spill_index[r];
7021 /* If this is a non-inherited input reload from a pseudo, we must
7022 clear any memory of a previous store to the same pseudo. Only do
7023 something if there will not be an output reload for the pseudo
7025 if (rld[r].in_reg != 0
7026 && ! (reload_inherited[r] || reload_override_in[r]))
7028 rtx reg = rld[r].in_reg;
7030 if (GET_CODE (reg) == SUBREG)
7031 reg = SUBREG_REG (reg);
7033 if (GET_CODE (reg) == REG
7034 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7035 && ! reg_has_output_reload[REGNO (reg)])
7037 int nregno = REGNO (reg);
7039 if (reg_last_reload_reg[nregno])
7041 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7043 if (reg_reloaded_contents[last_regno] == nregno)
7044 spill_reg_store[last_regno] = 0;
7049 /* I is nonneg if this reload used a register.
7050 If rld[r].reg_rtx is 0, this is an optional reload
7051 that we opted to ignore. */
7053 if (i >= 0 && rld[r].reg_rtx != 0)
7055 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7057 int part_reaches_end = 0;
7058 int all_reaches_end = 1;
7060 /* For a multi register reload, we need to check if all or part
7061 of the value lives to the end. */
7062 for (k = 0; k < nr; k++)
7064 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7065 rld[r].when_needed))
7066 part_reaches_end = 1;
7068 all_reaches_end = 0;
7071 /* Ignore reloads that don't reach the end of the insn in
7073 if (all_reaches_end)
7075 /* First, clear out memory of what used to be in this spill reg.
7076 If consecutive registers are used, clear them all. */
7078 for (k = 0; k < nr; k++)
7079 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7081 /* Maybe the spill reg contains a copy of reload_out. */
7083 && (GET_CODE (rld[r].out) == REG
7087 || GET_CODE (rld[r].out_reg) == REG))
7089 rtx out = (GET_CODE (rld[r].out) == REG
7093 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7094 register int nregno = REGNO (out);
7095 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7096 : HARD_REGNO_NREGS (nregno,
7097 GET_MODE (rld[r].reg_rtx)));
7099 spill_reg_store[i] = new_spill_reg_store[i];
7100 spill_reg_stored_to[i] = out;
7101 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7103 /* If NREGNO is a hard register, it may occupy more than
7104 one register. If it does, say what is in the
7105 rest of the registers assuming that both registers
7106 agree on how many words the object takes. If not,
7107 invalidate the subsequent registers. */
7109 if (nregno < FIRST_PSEUDO_REGISTER)
7110 for (k = 1; k < nnr; k++)
7111 reg_last_reload_reg[nregno + k]
7113 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7114 REGNO (rld[r].reg_rtx) + k)
7117 /* Now do the inverse operation. */
7118 for (k = 0; k < nr; k++)
7120 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7121 reg_reloaded_contents[i + k]
7122 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7125 reg_reloaded_insn[i + k] = insn;
7126 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7130 /* Maybe the spill reg contains a copy of reload_in. Only do
7131 something if there will not be an output reload for
7132 the register being reloaded. */
7133 else if (rld[r].out_reg == 0
7135 && ((GET_CODE (rld[r].in) == REG
7136 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7137 && ! reg_has_output_reload[REGNO (rld[r].in)])
7138 || (GET_CODE (rld[r].in_reg) == REG
7139 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7140 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7142 register int nregno;
7145 if (GET_CODE (rld[r].in) == REG
7146 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7147 nregno = REGNO (rld[r].in);
7148 else if (GET_CODE (rld[r].in_reg) == REG)
7149 nregno = REGNO (rld[r].in_reg);
7151 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7153 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7154 : HARD_REGNO_NREGS (nregno,
7155 GET_MODE (rld[r].reg_rtx)));
7157 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7159 if (nregno < FIRST_PSEUDO_REGISTER)
7160 for (k = 1; k < nnr; k++)
7161 reg_last_reload_reg[nregno + k]
7163 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7164 REGNO (rld[r].reg_rtx) + k)
7167 /* Unless we inherited this reload, show we haven't
7168 recently done a store.
7169 Previous stores of inherited auto_inc expressions
7170 also have to be discarded. */
7171 if (! reload_inherited[r]
7172 || (rld[r].out && ! rld[r].out_reg))
7173 spill_reg_store[i] = 0;
7175 for (k = 0; k < nr; k++)
7177 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7178 reg_reloaded_contents[i + k]
7179 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7182 reg_reloaded_insn[i + k] = insn;
7183 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7188 /* However, if part of the reload reaches the end, then we must
7189 invalidate the old info for the part that survives to the end. */
7190 else if (part_reaches_end)
7192 for (k = 0; k < nr; k++)
7193 if (reload_reg_reaches_end_p (i + k,
7195 rld[r].when_needed))
7196 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7200 /* The following if-statement was #if 0'd in 1.34 (or before...).
7201 It's reenabled in 1.35 because supposedly nothing else
7202 deals with this problem. */
7204 /* If a register gets output-reloaded from a non-spill register,
7205 that invalidates any previous reloaded copy of it.
7206 But forget_old_reloads_1 won't get to see it, because
7207 it thinks only about the original insn. So invalidate it here. */
7208 if (i < 0 && rld[r].out != 0
7209 && (GET_CODE (rld[r].out) == REG
7210 || (GET_CODE (rld[r].out) == MEM
7211 && GET_CODE (rld[r].out_reg) == REG)))
7213 rtx out = (GET_CODE (rld[r].out) == REG
7214 ? rld[r].out : rld[r].out_reg);
7215 register int nregno = REGNO (out);
7216 if (nregno >= FIRST_PSEUDO_REGISTER)
7218 rtx src_reg, store_insn = NULL_RTX;
7220 reg_last_reload_reg[nregno] = 0;
7222 /* If we can find a hard register that is stored, record
7223 the storing insn so that we may delete this insn with
7224 delete_output_reload. */
7225 src_reg = rld[r].reg_rtx;
7227 /* If this is an optional reload, try to find the source reg
7228 from an input reload. */
7231 rtx set = single_set (insn);
7232 if (set && SET_DEST (set) == rld[r].out)
7236 src_reg = SET_SRC (set);
7238 for (k = 0; k < n_reloads; k++)
7240 if (rld[k].in == src_reg)
7242 src_reg = rld[k].reg_rtx;
7249 store_insn = new_spill_reg_store[REGNO (src_reg)];
7250 if (src_reg && GET_CODE (src_reg) == REG
7251 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7253 int src_regno = REGNO (src_reg);
7254 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7255 /* The place where to find a death note varies with
7256 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7257 necessarily checked exactly in the code that moves
7258 notes, so just check both locations. */
7259 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7261 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7264 spill_reg_store[src_regno + nr] = store_insn;
7265 spill_reg_stored_to[src_regno + nr] = out;
7266 reg_reloaded_contents[src_regno + nr] = nregno;
7267 reg_reloaded_insn[src_regno + nr] = store_insn;
7268 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7269 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7270 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7272 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7274 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7276 reg_last_reload_reg[nregno] = src_reg;
7281 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7283 while (num_regs-- > 0)
7284 reg_last_reload_reg[nregno + num_regs] = 0;
7288 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7291 /* Emit code to perform a reload from IN (which may be a reload register) to
7292 OUT (which may also be a reload register). IN or OUT is from operand
7293 OPNUM with reload type TYPE.
7295 Returns first insn emitted. */
7298 gen_reload (out, in, opnum, type)
7302 enum reload_type type;
7304 rtx last = get_last_insn ();
7307 /* If IN is a paradoxical SUBREG, remove it and try to put the
7308 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7309 if (GET_CODE (in) == SUBREG
7310 && (GET_MODE_SIZE (GET_MODE (in))
7311 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7312 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7313 in = SUBREG_REG (in), out = tem;
7314 else if (GET_CODE (out) == SUBREG
7315 && (GET_MODE_SIZE (GET_MODE (out))
7316 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7317 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7318 out = SUBREG_REG (out), in = tem;
7320 /* How to do this reload can get quite tricky. Normally, we are being
7321 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7322 register that didn't get a hard register. In that case we can just
7323 call emit_move_insn.
7325 We can also be asked to reload a PLUS that adds a register or a MEM to
7326 another register, constant or MEM. This can occur during frame pointer
7327 elimination and while reloading addresses. This case is handled by
7328 trying to emit a single insn to perform the add. If it is not valid,
7329 we use a two insn sequence.
7331 Finally, we could be called to handle an 'o' constraint by putting
7332 an address into a register. In that case, we first try to do this
7333 with a named pattern of "reload_load_address". If no such pattern
7334 exists, we just emit a SET insn and hope for the best (it will normally
7335 be valid on machines that use 'o').
7337 This entire process is made complex because reload will never
7338 process the insns we generate here and so we must ensure that
7339 they will fit their constraints and also by the fact that parts of
7340 IN might be being reloaded separately and replaced with spill registers.
7341 Because of this, we are, in some sense, just guessing the right approach
7342 here. The one listed above seems to work.
7344 ??? At some point, this whole thing needs to be rethought. */
7346 if (GET_CODE (in) == PLUS
7347 && (GET_CODE (XEXP (in, 0)) == REG
7348 || GET_CODE (XEXP (in, 0)) == SUBREG
7349 || GET_CODE (XEXP (in, 0)) == MEM)
7350 && (GET_CODE (XEXP (in, 1)) == REG
7351 || GET_CODE (XEXP (in, 1)) == SUBREG
7352 || CONSTANT_P (XEXP (in, 1))
7353 || GET_CODE (XEXP (in, 1)) == MEM))
7355 /* We need to compute the sum of a register or a MEM and another
7356 register, constant, or MEM, and put it into the reload
7357 register. The best possible way of doing this is if the machine
7358 has a three-operand ADD insn that accepts the required operands.
7360 The simplest approach is to try to generate such an insn and see if it
7361 is recognized and matches its constraints. If so, it can be used.
7363 It might be better not to actually emit the insn unless it is valid,
7364 but we need to pass the insn as an operand to `recog' and
7365 `extract_insn' and it is simpler to emit and then delete the insn if
7366 not valid than to dummy things up. */
7368 rtx op0, op1, tem, insn;
7371 op0 = find_replacement (&XEXP (in, 0));
7372 op1 = find_replacement (&XEXP (in, 1));
7374 /* Since constraint checking is strict, commutativity won't be
7375 checked, so we need to do that here to avoid spurious failure
7376 if the add instruction is two-address and the second operand
7377 of the add is the same as the reload reg, which is frequently
7378 the case. If the insn would be A = B + A, rearrange it so
7379 it will be A = A + B as constrain_operands expects. */
7381 if (GET_CODE (XEXP (in, 1)) == REG
7382 && REGNO (out) == REGNO (XEXP (in, 1)))
7383 tem = op0, op0 = op1, op1 = tem;
7385 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7386 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7388 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7389 code = recog_memoized (insn);
7393 extract_insn (insn);
7394 /* We want constrain operands to treat this insn strictly in
7395 its validity determination, i.e., the way it would after reload
7397 if (constrain_operands (1))
7401 delete_insns_since (last);
7403 /* If that failed, we must use a conservative two-insn sequence.
7405 Use a move to copy one operand into the reload register. Prefer
7406 to reload a constant, MEM or pseudo since the move patterns can
7407 handle an arbitrary operand. If OP1 is not a constant, MEM or
7408 pseudo and OP1 is not a valid operand for an add instruction, then
7411 After reloading one of the operands into the reload register, add
7412 the reload register to the output register.
7414 If there is another way to do this for a specific machine, a
7415 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7418 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7420 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7421 || (GET_CODE (op1) == REG
7422 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7423 || (code != CODE_FOR_nothing
7424 && ! ((*insn_data[code].operand[2].predicate)
7425 (op1, insn_data[code].operand[2].mode))))
7426 tem = op0, op0 = op1, op1 = tem;
7428 gen_reload (out, op0, opnum, type);
7430 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7431 This fixes a problem on the 32K where the stack pointer cannot
7432 be used as an operand of an add insn. */
7434 if (rtx_equal_p (op0, op1))
7437 insn = emit_insn (gen_add2_insn (out, op1));
7439 /* If that failed, copy the address register to the reload register.
7440 Then add the constant to the reload register. */
7442 code = recog_memoized (insn);
7446 extract_insn (insn);
7447 /* We want constrain operands to treat this insn strictly in
7448 its validity determination, i.e., the way it would after reload
7450 if (constrain_operands (1))
7452 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7454 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7459 delete_insns_since (last);
7461 gen_reload (out, op1, opnum, type);
7462 insn = emit_insn (gen_add2_insn (out, op0));
7463 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7466 #ifdef SECONDARY_MEMORY_NEEDED
7467 /* If we need a memory location to do the move, do it that way. */
7468 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7469 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7470 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7471 REGNO_REG_CLASS (REGNO (out)),
7474 /* Get the memory to use and rewrite both registers to its mode. */
7475 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7477 if (GET_MODE (loc) != GET_MODE (out))
7478 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7480 if (GET_MODE (loc) != GET_MODE (in))
7481 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7483 gen_reload (loc, in, opnum, type);
7484 gen_reload (out, loc, opnum, type);
7488 /* If IN is a simple operand, use gen_move_insn. */
7489 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7490 emit_insn (gen_move_insn (out, in));
7492 #ifdef HAVE_reload_load_address
7493 else if (HAVE_reload_load_address)
7494 emit_insn (gen_reload_load_address (out, in));
7497 /* Otherwise, just write (set OUT IN) and hope for the best. */
7499 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7501 /* Return the first insn emitted.
7502 We can not just return get_last_insn, because there may have
7503 been multiple instructions emitted. Also note that gen_move_insn may
7504 emit more than one insn itself, so we can not assume that there is one
7505 insn emitted per emit_insn_before call. */
7507 return last ? NEXT_INSN (last) : get_insns ();
7510 /* Delete a previously made output-reload
7511 whose result we now believe is not needed.
7512 First we double-check.
7514 INSN is the insn now being processed.
7515 LAST_RELOAD_REG is the hard register number for which we want to delete
7516 the last output reload.
7517 J is the reload-number that originally used REG. The caller has made
7518 certain that reload J doesn't use REG any longer for input. */
7521 delete_output_reload (insn, j, last_reload_reg)
7524 int last_reload_reg;
7526 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7527 rtx reg = spill_reg_stored_to[last_reload_reg];
7530 int n_inherited = 0;
7534 /* Get the raw pseudo-register referred to. */
7536 while (GET_CODE (reg) == SUBREG)
7537 reg = SUBREG_REG (reg);
7538 substed = reg_equiv_memory_loc[REGNO (reg)];
7540 /* This is unsafe if the operand occurs more often in the current
7541 insn than it is inherited. */
7542 for (k = n_reloads - 1; k >= 0; k--)
7544 rtx reg2 = rld[k].in;
7547 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7548 reg2 = rld[k].in_reg;
7550 if (rld[k].out && ! rld[k].out_reg)
7551 reg2 = XEXP (rld[k].in_reg, 0);
7553 while (GET_CODE (reg2) == SUBREG)
7554 reg2 = SUBREG_REG (reg2);
7555 if (rtx_equal_p (reg2, reg))
7557 if (reload_inherited[k] || reload_override_in[k] || k == j)
7560 reg2 = rld[k].out_reg;
7563 while (GET_CODE (reg2) == SUBREG)
7564 reg2 = XEXP (reg2, 0);
7565 if (rtx_equal_p (reg2, reg))
7572 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7574 n_occurrences += count_occurrences (PATTERN (insn), substed, 0);
7575 if (n_occurrences > n_inherited)
7578 /* If the pseudo-reg we are reloading is no longer referenced
7579 anywhere between the store into it and here,
7580 and no jumps or labels intervene, then the value can get
7581 here through the reload reg alone.
7582 Otherwise, give up--return. */
7583 for (i1 = NEXT_INSN (output_reload_insn);
7584 i1 != insn; i1 = NEXT_INSN (i1))
7586 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7588 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7589 && reg_mentioned_p (reg, PATTERN (i1)))
7591 /* If this is USE in front of INSN, we only have to check that
7592 there are no more references than accounted for by inheritance. */
7593 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7595 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7596 i1 = NEXT_INSN (i1);
7598 if (n_occurrences <= n_inherited && i1 == insn)
7604 /* The caller has already checked that REG dies or is set in INSN.
7605 It has also checked that we are optimizing, and thus some inaccurancies
7606 in the debugging information are acceptable.
7607 So we could just delete output_reload_insn.
7608 But in some cases we can improve the debugging information without
7609 sacrificing optimization - maybe even improving the code:
7610 See if the pseudo reg has been completely replaced
7611 with reload regs. If so, delete the store insn
7612 and forget we had a stack slot for the pseudo. */
7613 if (rld[j].out != rld[j].in
7614 && REG_N_DEATHS (REGNO (reg)) == 1
7615 && REG_N_SETS (REGNO (reg)) == 1
7616 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7617 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7621 /* We know that it was used only between here
7622 and the beginning of the current basic block.
7623 (We also know that the last use before INSN was
7624 the output reload we are thinking of deleting, but never mind that.)
7625 Search that range; see if any ref remains. */
7626 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7628 rtx set = single_set (i2);
7630 /* Uses which just store in the pseudo don't count,
7631 since if they are the only uses, they are dead. */
7632 if (set != 0 && SET_DEST (set) == reg)
7634 if (GET_CODE (i2) == CODE_LABEL
7635 || GET_CODE (i2) == JUMP_INSN)
7637 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7638 && reg_mentioned_p (reg, PATTERN (i2)))
7640 /* Some other ref remains; just delete the output reload we
7642 delete_address_reloads (output_reload_insn, insn);
7643 PUT_CODE (output_reload_insn, NOTE);
7644 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7645 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7650 /* Delete the now-dead stores into this pseudo. */
7651 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7653 rtx set = single_set (i2);
7655 if (set != 0 && SET_DEST (set) == reg)
7657 delete_address_reloads (i2, insn);
7658 /* This might be a basic block head,
7659 thus don't use delete_insn. */
7660 PUT_CODE (i2, NOTE);
7661 NOTE_SOURCE_FILE (i2) = 0;
7662 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7664 if (GET_CODE (i2) == CODE_LABEL
7665 || GET_CODE (i2) == JUMP_INSN)
7669 /* For the debugging info,
7670 say the pseudo lives in this reload reg. */
7671 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7672 alter_reg (REGNO (reg), -1);
7674 delete_address_reloads (output_reload_insn, insn);
7675 PUT_CODE (output_reload_insn, NOTE);
7676 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7677 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7681 /* We are going to delete DEAD_INSN. Recursively delete loads of
7682 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7683 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7685 delete_address_reloads (dead_insn, current_insn)
7686 rtx dead_insn, current_insn;
7688 rtx set = single_set (dead_insn);
7689 rtx set2, dst, prev, next;
7692 rtx dst = SET_DEST (set);
7693 if (GET_CODE (dst) == MEM)
7694 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7696 /* If we deleted the store from a reloaded post_{in,de}c expression,
7697 we can delete the matching adds. */
7698 prev = PREV_INSN (dead_insn);
7699 next = NEXT_INSN (dead_insn);
7700 if (! prev || ! next)
7702 set = single_set (next);
7703 set2 = single_set (prev);
7705 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7706 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7707 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7709 dst = SET_DEST (set);
7710 if (! rtx_equal_p (dst, SET_DEST (set2))
7711 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7712 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7713 || (INTVAL (XEXP (SET_SRC (set), 1))
7714 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7720 /* Subfunction of delete_address_reloads: process registers found in X. */
7722 delete_address_reloads_1 (dead_insn, x, current_insn)
7723 rtx dead_insn, x, current_insn;
7725 rtx prev, set, dst, i2;
7727 enum rtx_code code = GET_CODE (x);
7731 const char *fmt = GET_RTX_FORMAT (code);
7732 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7735 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7736 else if (fmt[i] == 'E')
7738 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7739 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7746 if (spill_reg_order[REGNO (x)] < 0)
7749 /* Scan backwards for the insn that sets x. This might be a way back due
7751 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7753 code = GET_CODE (prev);
7754 if (code == CODE_LABEL || code == JUMP_INSN)
7756 if (GET_RTX_CLASS (code) != 'i')
7758 if (reg_set_p (x, PATTERN (prev)))
7760 if (reg_referenced_p (x, PATTERN (prev)))
7763 if (! prev || INSN_UID (prev) < reload_first_uid)
7765 /* Check that PREV only sets the reload register. */
7766 set = single_set (prev);
7769 dst = SET_DEST (set);
7770 if (GET_CODE (dst) != REG
7771 || ! rtx_equal_p (dst, x))
7773 if (! reg_set_p (dst, PATTERN (dead_insn)))
7775 /* Check if DST was used in a later insn -
7776 it might have been inherited. */
7777 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7779 if (GET_CODE (i2) == CODE_LABEL)
7783 if (reg_referenced_p (dst, PATTERN (i2)))
7785 /* If there is a reference to the register in the current insn,
7786 it might be loaded in a non-inherited reload. If no other
7787 reload uses it, that means the register is set before
7789 if (i2 == current_insn)
7791 for (j = n_reloads - 1; j >= 0; j--)
7792 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7793 || reload_override_in[j] == dst)
7795 for (j = n_reloads - 1; j >= 0; j--)
7796 if (rld[j].in && rld[j].reg_rtx == dst)
7803 if (GET_CODE (i2) == JUMP_INSN)
7805 /* If DST is still live at CURRENT_INSN, check if it is used for
7806 any reload. Note that even if CURRENT_INSN sets DST, we still
7807 have to check the reloads. */
7808 if (i2 == current_insn)
7810 for (j = n_reloads - 1; j >= 0; j--)
7811 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7812 || reload_override_in[j] == dst)
7814 /* ??? We can't finish the loop here, because dst might be
7815 allocated to a pseudo in this block if no reload in this
7816 block needs any of the clsses containing DST - see
7817 spill_hard_reg. There is no easy way to tell this, so we
7818 have to scan till the end of the basic block. */
7820 if (reg_set_p (dst, PATTERN (i2)))
7824 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7825 reg_reloaded_contents[REGNO (dst)] = -1;
7826 /* Can't use delete_insn here because PREV might be a basic block head. */
7827 PUT_CODE (prev, NOTE);
7828 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
7829 NOTE_SOURCE_FILE (prev) = 0;
7832 /* Output reload-insns to reload VALUE into RELOADREG.
7833 VALUE is an autoincrement or autodecrement RTX whose operand
7834 is a register or memory location;
7835 so reloading involves incrementing that location.
7836 IN is either identical to VALUE, or some cheaper place to reload from.
7838 INC_AMOUNT is the number to increment or decrement by (always positive).
7839 This cannot be deduced from VALUE.
7841 Return the instruction that stores into RELOADREG. */
7844 inc_for_reload (reloadreg, in, value, inc_amount)
7849 /* REG or MEM to be copied and incremented. */
7850 rtx incloc = XEXP (value, 0);
7851 /* Nonzero if increment after copying. */
7852 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7858 rtx real_in = in == value ? XEXP (in, 0) : in;
7860 /* No hard register is equivalent to this register after
7861 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7862 we could inc/dec that register as well (maybe even using it for
7863 the source), but I'm not sure it's worth worrying about. */
7864 if (GET_CODE (incloc) == REG)
7865 reg_last_reload_reg[REGNO (incloc)] = 0;
7867 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7868 inc_amount = -inc_amount;
7870 inc = GEN_INT (inc_amount);
7872 /* If this is post-increment, first copy the location to the reload reg. */
7873 if (post && real_in != reloadreg)
7874 emit_insn (gen_move_insn (reloadreg, real_in));
7878 /* See if we can directly increment INCLOC. Use a method similar to
7879 that in gen_reload. */
7881 last = get_last_insn ();
7882 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7883 gen_rtx_PLUS (GET_MODE (incloc),
7886 code = recog_memoized (add_insn);
7889 extract_insn (add_insn);
7890 if (constrain_operands (1))
7892 /* If this is a pre-increment and we have incremented the value
7893 where it lives, copy the incremented value to RELOADREG to
7894 be used as an address. */
7897 emit_insn (gen_move_insn (reloadreg, incloc));
7902 delete_insns_since (last);
7905 /* If couldn't do the increment directly, must increment in RELOADREG.
7906 The way we do this depends on whether this is pre- or post-increment.
7907 For pre-increment, copy INCLOC to the reload register, increment it
7908 there, then save back. */
7912 if (in != reloadreg)
7913 emit_insn (gen_move_insn (reloadreg, real_in));
7914 emit_insn (gen_add2_insn (reloadreg, inc));
7915 store = emit_insn (gen_move_insn (incloc, reloadreg));
7920 Because this might be a jump insn or a compare, and because RELOADREG
7921 may not be available after the insn in an input reload, we must do
7922 the incrementation before the insn being reloaded for.
7924 We have already copied IN to RELOADREG. Increment the copy in
7925 RELOADREG, save that back, then decrement RELOADREG so it has
7926 the original value. */
7928 emit_insn (gen_add2_insn (reloadreg, inc));
7929 store = emit_insn (gen_move_insn (incloc, reloadreg));
7930 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7936 /* Return 1 if we are certain that the constraint-string STRING allows
7937 the hard register REG. Return 0 if we can't be sure of this. */
7940 constraint_accepts_reg_p (string, reg)
7945 int regno = true_regnum (reg);
7948 /* Initialize for first alternative. */
7950 /* Check that each alternative contains `g' or `r'. */
7952 switch (c = *string++)
7955 /* If an alternative lacks `g' or `r', we lose. */
7958 /* If an alternative lacks `g' or `r', we lose. */
7961 /* Initialize for next alternative. */
7966 /* Any general reg wins for this alternative. */
7967 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7971 /* Any reg in specified class wins for this alternative. */
7973 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7975 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
7981 /* INSN is a no-op; delete it.
7982 If this sets the return value of the function, we must keep a USE around,
7983 in case this is in a different basic block than the final USE. Otherwise,
7984 we could loose important register lifeness information on
7985 SMALL_REGISTER_CLASSES machines, where return registers might be used as
7986 spills: subsequent passes assume that spill registers are dead at the end
7988 VALUE must be the return value in such a case, NULL otherwise. */
7990 reload_cse_delete_noop_set (insn, value)
7995 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
7996 INSN_CODE (insn) = -1;
7997 REG_NOTES (insn) = NULL_RTX;
8001 PUT_CODE (insn, NOTE);
8002 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8003 NOTE_SOURCE_FILE (insn) = 0;
8007 /* See whether a single set SET is a noop. */
8009 reload_cse_noop_set_p (set)
8012 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
8015 /* Try to simplify INSN. */
8017 reload_cse_simplify (insn)
8020 rtx body = PATTERN (insn);
8022 if (GET_CODE (body) == SET)
8025 if (reload_cse_noop_set_p (body))
8027 rtx value = SET_DEST (body);
8028 if (! REG_FUNCTION_VALUE_P (SET_DEST (body)))
8030 reload_cse_delete_noop_set (insn, value);
8034 /* It's not a no-op, but we can try to simplify it. */
8035 count += reload_cse_simplify_set (body, insn);
8038 apply_change_group ();
8040 reload_cse_simplify_operands (insn);
8042 else if (GET_CODE (body) == PARALLEL)
8046 rtx value = NULL_RTX;
8048 /* If every action in a PARALLEL is a noop, we can delete
8049 the entire PARALLEL. */
8050 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8052 rtx part = XVECEXP (body, 0, i);
8053 if (GET_CODE (part) == SET)
8055 if (! reload_cse_noop_set_p (part))
8057 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8061 value = SET_DEST (part);
8064 else if (GET_CODE (part) != CLOBBER)
8070 reload_cse_delete_noop_set (insn, value);
8071 /* We're done with this insn. */
8075 /* It's not a no-op, but we can try to simplify it. */
8076 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8077 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8078 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8081 apply_change_group ();
8083 reload_cse_simplify_operands (insn);
8087 /* Do a very simple CSE pass over the hard registers.
8089 This function detects no-op moves where we happened to assign two
8090 different pseudo-registers to the same hard register, and then
8091 copied one to the other. Reload will generate a useless
8092 instruction copying a register to itself.
8094 This function also detects cases where we load a value from memory
8095 into two different registers, and (if memory is more expensive than
8096 registers) changes it to simply copy the first register into the
8099 Another optimization is performed that scans the operands of each
8100 instruction to see whether the value is already available in a
8101 hard register. It then replaces the operand with the hard register
8102 if possible, much like an optional reload would. */
8105 reload_cse_regs_1 (first)
8111 init_alias_analysis ();
8113 for (insn = first; insn; insn = NEXT_INSN (insn))
8116 reload_cse_simplify (insn);
8118 cselib_process_insn (insn);
8122 end_alias_analysis ();
8126 /* Call cse / combine like post-reload optimization phases.
8127 FIRST is the first instruction. */
8129 reload_cse_regs (first)
8132 reload_cse_regs_1 (first);
8134 reload_cse_move2add (first);
8135 if (flag_expensive_optimizations)
8136 reload_cse_regs_1 (first);
8139 /* Try to simplify a single SET instruction. SET is the set pattern.
8140 INSN is the instruction it came from.
8141 This function only handles one case: if we set a register to a value
8142 which is not a register, we try to find that value in some other register
8143 and change the set into a register copy. */
8146 reload_cse_simplify_set (set, insn)
8153 enum reg_class dclass;
8156 struct elt_loc_list *l;
8158 dreg = true_regnum (SET_DEST (set));
8162 src = SET_SRC (set);
8163 if (side_effects_p (src) || true_regnum (src) >= 0)
8166 dclass = REGNO_REG_CLASS (dreg);
8168 /* If memory loads are cheaper than register copies, don't change them. */
8169 if (GET_CODE (src) == MEM)
8170 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8171 else if (CONSTANT_P (src))
8172 old_cost = rtx_cost (src, SET);
8173 else if (GET_CODE (src) == REG)
8174 old_cost = REGISTER_MOVE_COST (GET_MODE (src),
8175 REGNO_REG_CLASS (REGNO (src)), dclass);
8178 old_cost = rtx_cost (src, SET);
8180 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0);
8183 for (l = val->locs; l; l = l->next)
8186 if (CONSTANT_P (l->loc) && ! references_value_p (l->loc, 0))
8187 this_cost = rtx_cost (l->loc, SET);
8188 else if (GET_CODE (l->loc) == REG)
8189 this_cost = REGISTER_MOVE_COST (GET_MODE (l->loc),
8190 REGNO_REG_CLASS (REGNO (l->loc)),
8194 /* If equal costs, prefer registers over anything else. That tends to
8195 lead to smaller instructions on some machines. */
8196 if ((this_cost < old_cost
8197 || (this_cost == old_cost
8198 && GET_CODE (l->loc) == REG
8199 && GET_CODE (SET_SRC (set)) != REG))
8200 && validate_change (insn, &SET_SRC (set), copy_rtx (l->loc), 1))
8201 old_cost = this_cost, did_change = 1;
8207 /* Try to replace operands in INSN with equivalent values that are already
8208 in registers. This can be viewed as optional reloading.
8210 For each non-register operand in the insn, see if any hard regs are
8211 known to be equivalent to that operand. Record the alternatives which
8212 can accept these hard registers. Among all alternatives, select the
8213 ones which are better or equal to the one currently matching, where
8214 "better" is in terms of '?' and '!' constraints. Among the remaining
8215 alternatives, select the one which replaces most operands with
8219 reload_cse_simplify_operands (insn)
8224 /* For each operand, all registers that are equivalent to it. */
8225 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8227 const char *constraints[MAX_RECOG_OPERANDS];
8229 /* Vector recording how bad an alternative is. */
8230 int *alternative_reject;
8231 /* Vector recording how many registers can be introduced by choosing
8232 this alternative. */
8233 int *alternative_nregs;
8234 /* Array of vectors recording, for each operand and each alternative,
8235 which hard register to substitute, or -1 if the operand should be
8237 int *op_alt_regno[MAX_RECOG_OPERANDS];
8238 /* Array of alternatives, sorted in order of decreasing desirability. */
8239 int *alternative_order;
8240 rtx reg = gen_rtx_REG (VOIDmode, -1);
8242 extract_insn (insn);
8244 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8247 /* Figure out which alternative currently matches. */
8248 if (! constrain_operands (1))
8249 fatal_insn_not_found (insn);
8251 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8252 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8253 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8254 memset ((char *)alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
8255 memset ((char *)alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
8257 /* For each operand, find out which regs are equivalent. */
8258 for (i = 0; i < recog_data.n_operands; i++)
8261 struct elt_loc_list *l;
8263 CLEAR_HARD_REG_SET (equiv_regs[i]);
8265 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8266 right, so avoid the problem here. Likewise if we have a constant
8267 and the insn pattern doesn't tell us the mode we need. */
8268 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL
8269 || (CONSTANT_P (recog_data.operand[i])
8270 && recog_data.operand_mode[i] == VOIDmode))
8273 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8277 for (l = v->locs; l; l = l->next)
8278 if (GET_CODE (l->loc) == REG)
8279 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8282 for (i = 0; i < recog_data.n_operands; i++)
8284 enum machine_mode mode;
8288 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8289 for (j = 0; j < recog_data.n_alternatives; j++)
8290 op_alt_regno[i][j] = -1;
8292 p = constraints[i] = recog_data.constraints[i];
8293 mode = recog_data.operand_mode[i];
8295 /* Add the reject values for each alternative given by the constraints
8296 for this operand. */
8304 alternative_reject[j] += 3;
8306 alternative_reject[j] += 300;
8309 /* We won't change operands which are already registers. We
8310 also don't want to modify output operands. */
8311 regno = true_regnum (recog_data.operand[i]);
8313 || constraints[i][0] == '='
8314 || constraints[i][0] == '+')
8317 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8319 int class = (int) NO_REGS;
8321 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8324 REGNO (reg) = regno;
8325 PUT_MODE (reg, mode);
8327 /* We found a register equal to this operand. Now look for all
8328 alternatives that can accept this register and have not been
8329 assigned a register they can use yet. */
8338 case '=': case '+': case '?':
8339 case '#': case '&': case '!':
8341 case '0': case '1': case '2': case '3': case '4':
8342 case '5': case '6': case '7': case '8': case '9':
8343 case 'm': case '<': case '>': case 'V': case 'o':
8344 case 'E': case 'F': case 'G': case 'H':
8345 case 's': case 'i': case 'n':
8346 case 'I': case 'J': case 'K': case 'L':
8347 case 'M': case 'N': case 'O': case 'P':
8349 /* These don't say anything we care about. */
8353 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8358 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
8361 case ',': case '\0':
8362 /* See if REGNO fits this alternative, and set it up as the
8363 replacement register if we don't have one for this
8364 alternative yet and the operand being replaced is not
8365 a cheap CONST_INT. */
8366 if (op_alt_regno[i][j] == -1
8367 && reg_fits_class_p (reg, class, 0, mode)
8368 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8369 || (rtx_cost (recog_data.operand[i], SET)
8370 > rtx_cost (reg, SET))))
8372 alternative_nregs[j]++;
8373 op_alt_regno[i][j] = regno;
8385 /* Record all alternatives which are better or equal to the currently
8386 matching one in the alternative_order array. */
8387 for (i = j = 0; i < recog_data.n_alternatives; i++)
8388 if (alternative_reject[i] <= alternative_reject[which_alternative])
8389 alternative_order[j++] = i;
8390 recog_data.n_alternatives = j;
8392 /* Sort it. Given a small number of alternatives, a dumb algorithm
8393 won't hurt too much. */
8394 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8397 int best_reject = alternative_reject[alternative_order[i]];
8398 int best_nregs = alternative_nregs[alternative_order[i]];
8401 for (j = i + 1; j < recog_data.n_alternatives; j++)
8403 int this_reject = alternative_reject[alternative_order[j]];
8404 int this_nregs = alternative_nregs[alternative_order[j]];
8406 if (this_reject < best_reject
8407 || (this_reject == best_reject && this_nregs < best_nregs))
8410 best_reject = this_reject;
8411 best_nregs = this_nregs;
8415 tmp = alternative_order[best];
8416 alternative_order[best] = alternative_order[i];
8417 alternative_order[i] = tmp;
8420 /* Substitute the operands as determined by op_alt_regno for the best
8422 j = alternative_order[0];
8424 for (i = 0; i < recog_data.n_operands; i++)
8426 enum machine_mode mode = recog_data.operand_mode[i];
8427 if (op_alt_regno[i][j] == -1)
8430 validate_change (insn, recog_data.operand_loc[i],
8431 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8434 for (i = recog_data.n_dups - 1; i >= 0; i--)
8436 int op = recog_data.dup_num[i];
8437 enum machine_mode mode = recog_data.operand_mode[op];
8439 if (op_alt_regno[op][j] == -1)
8442 validate_change (insn, recog_data.dup_loc[i],
8443 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8446 return apply_change_group ();
8449 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8451 This code might also be useful when reload gave up on reg+reg addresssing
8452 because of clashes between the return register and INDEX_REG_CLASS. */
8454 /* The maximum number of uses of a register we can keep track of to
8455 replace them with reg+reg addressing. */
8456 #define RELOAD_COMBINE_MAX_USES 6
8458 /* INSN is the insn where a register has ben used, and USEP points to the
8459 location of the register within the rtl. */
8460 struct reg_use { rtx insn, *usep; };
8462 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8463 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8464 indicates where it becomes live again.
8465 Otherwise, USE_INDEX is the index of the last encountered use of the
8466 register (which is first among these we have seen since we scan backwards),
8467 OFFSET contains the constant offset that is added to the register in
8468 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8469 last, of these uses.
8470 STORE_RUID is always meaningful if we only want to use a value in a
8471 register in a different place: it denotes the next insn in the insn
8472 stream (i.e. the last ecountered) that sets or clobbers the register. */
8475 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8480 } reg_state[FIRST_PSEUDO_REGISTER];
8482 /* Reverse linear uid. This is increased in reload_combine while scanning
8483 the instructions from last to first. It is used to set last_label_ruid
8484 and the store_ruid / use_ruid fields in reg_state. */
8485 static int reload_combine_ruid;
8487 #define LABEL_LIVE(LABEL) \
8488 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8494 int first_index_reg = -1, last_index_reg;
8497 int last_label_ruid;
8498 int min_labelno, n_labels;
8499 HARD_REG_SET ever_live_at_start, *label_live;
8501 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
8502 reload has already used it where appropriate, so there is no use in
8503 trying to generate it now. */
8504 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8507 /* To avoid wasting too much time later searching for an index register,
8508 determine the minimum and maximum index register numbers. */
8509 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8510 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
8512 if (first_index_reg == -1)
8513 first_index_reg = r;
8518 /* If no index register is available, we can quit now. */
8519 if (first_index_reg == -1)
8522 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8523 information is a bit fuzzy immediately after reload, but it's
8524 still good enough to determine which registers are live at a jump
8526 min_labelno = get_first_label_num ();
8527 n_labels = max_label_num () - min_labelno;
8528 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8529 CLEAR_HARD_REG_SET (ever_live_at_start);
8531 for (i = n_basic_blocks - 1; i >= 0; i--)
8533 insn = BLOCK_HEAD (i);
8534 if (GET_CODE (insn) == CODE_LABEL)
8538 REG_SET_TO_HARD_REG_SET (live,
8539 BASIC_BLOCK (i)->global_live_at_start);
8540 compute_use_by_pseudos (&live,
8541 BASIC_BLOCK (i)->global_live_at_start);
8542 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8543 IOR_HARD_REG_SET (ever_live_at_start, live);
8547 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8548 last_label_ruid = reload_combine_ruid = 0;
8549 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8551 reg_state[r].store_ruid = reload_combine_ruid;
8553 reg_state[r].use_index = -1;
8555 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8558 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8562 /* We cannot do our optimization across labels. Invalidating all the use
8563 information we have would be costly, so we just note where the label
8564 is and then later disable any optimization that would cross it. */
8565 if (GET_CODE (insn) == CODE_LABEL)
8566 last_label_ruid = reload_combine_ruid;
8567 else if (GET_CODE (insn) == BARRIER)
8568 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8569 if (! fixed_regs[r])
8570 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8572 if (! INSN_P (insn))
8575 reload_combine_ruid++;
8577 /* Look for (set (REGX) (CONST_INT))
8578 (set (REGX) (PLUS (REGX) (REGY)))
8580 ... (MEM (REGX)) ...
8582 (set (REGZ) (CONST_INT))
8584 ... (MEM (PLUS (REGZ) (REGY)))... .
8586 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8587 and that we know all uses of REGX before it dies. */
8588 set = single_set (insn);
8590 && GET_CODE (SET_DEST (set)) == REG
8591 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8592 GET_MODE (SET_DEST (set)))
8594 && GET_CODE (SET_SRC (set)) == PLUS
8595 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8596 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8597 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8599 rtx reg = SET_DEST (set);
8600 rtx plus = SET_SRC (set);
8601 rtx base = XEXP (plus, 1);
8602 rtx prev = prev_nonnote_insn (insn);
8603 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8604 unsigned int regno = REGNO (reg);
8605 rtx const_reg = NULL_RTX;
8606 rtx reg_sum = NULL_RTX;
8608 /* Now, we need an index register.
8609 We'll set index_reg to this index register, const_reg to the
8610 register that is to be loaded with the constant
8611 (denoted as REGZ in the substitution illustration above),
8612 and reg_sum to the register-register that we want to use to
8613 substitute uses of REG (typically in MEMs) with.
8614 First check REG and BASE for being index registers;
8615 we can use them even if they are not dead. */
8616 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8617 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8625 /* Otherwise, look for a free index register. Since we have
8626 checked above that neiter REG nor BASE are index registers,
8627 if we find anything at all, it will be different from these
8629 for (i = first_index_reg; i <= last_index_reg; i++)
8631 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8633 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8634 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8635 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8637 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8639 const_reg = index_reg;
8640 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8646 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8647 (REGY), i.e. BASE, is not clobbered before the last use we'll
8650 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8651 && rtx_equal_p (SET_DEST (prev_set), reg)
8652 && reg_state[regno].use_index >= 0
8653 && (reg_state[REGNO (base)].store_ruid
8654 <= reg_state[regno].use_ruid)
8659 /* Change destination register and, if necessary, the
8660 constant value in PREV, the constant loading instruction. */
8661 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8662 if (reg_state[regno].offset != const0_rtx)
8663 validate_change (prev,
8664 &SET_SRC (prev_set),
8665 GEN_INT (INTVAL (SET_SRC (prev_set))
8666 + INTVAL (reg_state[regno].offset)),
8669 /* Now for every use of REG that we have recorded, replace REG
8671 for (i = reg_state[regno].use_index;
8672 i < RELOAD_COMBINE_MAX_USES; i++)
8673 validate_change (reg_state[regno].reg_use[i].insn,
8674 reg_state[regno].reg_use[i].usep,
8677 if (apply_change_group ())
8681 /* Delete the reg-reg addition. */
8682 PUT_CODE (insn, NOTE);
8683 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8684 NOTE_SOURCE_FILE (insn) = 0;
8686 if (reg_state[regno].offset != const0_rtx)
8687 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8689 for (np = ®_NOTES (prev); *np;)
8691 if (REG_NOTE_KIND (*np) == REG_EQUAL
8692 || REG_NOTE_KIND (*np) == REG_EQUIV)
8693 *np = XEXP (*np, 1);
8695 np = &XEXP (*np, 1);
8698 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8699 reg_state[REGNO (const_reg)].store_ruid
8700 = reload_combine_ruid;
8706 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8708 if (GET_CODE (insn) == CALL_INSN)
8712 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8713 if (call_used_regs[r])
8715 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8716 reg_state[r].store_ruid = reload_combine_ruid;
8719 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8720 link = XEXP (link, 1))
8722 rtx usage_rtx = XEXP (XEXP (link, 0), 0);
8723 if (GET_CODE (usage_rtx) == REG)
8726 unsigned int start_reg = REGNO (usage_rtx);
8727 unsigned int num_regs =
8728 HARD_REGNO_NREGS (start_reg, GET_MODE (usage_rtx));
8729 unsigned int end_reg = start_reg + num_regs - 1;
8730 for (i = start_reg; i <= end_reg; i++)
8731 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
8733 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8734 reg_state[i].store_ruid = reload_combine_ruid;
8737 reg_state[i].use_index = -1;
8742 else if (GET_CODE (insn) == JUMP_INSN
8743 && GET_CODE (PATTERN (insn)) != RETURN)
8745 /* Non-spill registers might be used at the call destination in
8746 some unknown fashion, so we have to mark the unknown use. */
8749 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8750 && JUMP_LABEL (insn))
8751 live = &LABEL_LIVE (JUMP_LABEL (insn));
8753 live = &ever_live_at_start;
8755 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8756 if (TEST_HARD_REG_BIT (*live, i))
8757 reg_state[i].use_index = -1;
8760 reload_combine_note_use (&PATTERN (insn), insn);
8761 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8763 if (REG_NOTE_KIND (note) == REG_INC
8764 && GET_CODE (XEXP (note, 0)) == REG)
8766 int regno = REGNO (XEXP (note, 0));
8768 reg_state[regno].store_ruid = reload_combine_ruid;
8769 reg_state[regno].use_index = -1;
8777 /* Check if DST is a register or a subreg of a register; if it is,
8778 update reg_state[regno].store_ruid and reg_state[regno].use_index
8779 accordingly. Called via note_stores from reload_combine. */
8782 reload_combine_note_store (dst, set, data)
8784 void *data ATTRIBUTE_UNUSED;
8788 enum machine_mode mode = GET_MODE (dst);
8790 if (GET_CODE (dst) == SUBREG)
8792 regno = SUBREG_WORD (dst);
8793 dst = SUBREG_REG (dst);
8795 if (GET_CODE (dst) != REG)
8797 regno += REGNO (dst);
8799 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8800 careful with registers / register parts that are not full words.
8802 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8803 if (GET_CODE (set) != SET
8804 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8805 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8806 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8808 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8810 reg_state[i].use_index = -1;
8811 reg_state[i].store_ruid = reload_combine_ruid;
8816 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8818 reg_state[i].store_ruid = reload_combine_ruid;
8819 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8824 /* XP points to a piece of rtl that has to be checked for any uses of
8826 *XP is the pattern of INSN, or a part of it.
8827 Called from reload_combine, and recursively by itself. */
8829 reload_combine_note_use (xp, insn)
8833 enum rtx_code code = x->code;
8836 rtx offset = const0_rtx; /* For the REG case below. */
8841 if (GET_CODE (SET_DEST (x)) == REG)
8843 reload_combine_note_use (&SET_SRC (x), insn);
8849 /* If this is the USE of a return value, we can't change it. */
8850 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8852 /* Mark the return register as used in an unknown fashion. */
8853 rtx reg = XEXP (x, 0);
8854 int regno = REGNO (reg);
8855 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8857 while (--nregs >= 0)
8858 reg_state[regno + nregs].use_index = -1;
8864 if (GET_CODE (SET_DEST (x)) == REG)
8869 /* We are interested in (plus (reg) (const_int)) . */
8870 if (GET_CODE (XEXP (x, 0)) != REG
8871 || GET_CODE (XEXP (x, 1)) != CONST_INT)
8873 offset = XEXP (x, 1);
8878 int regno = REGNO (x);
8882 /* Some spurious USEs of pseudo registers might remain.
8883 Just ignore them. */
8884 if (regno >= FIRST_PSEUDO_REGISTER)
8887 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
8889 /* We can't substitute into multi-hard-reg uses. */
8892 while (--nregs >= 0)
8893 reg_state[regno + nregs].use_index = -1;
8897 /* If this register is already used in some unknown fashion, we
8899 If we decrement the index from zero to -1, we can't store more
8900 uses, so this register becomes used in an unknown fashion. */
8901 use_index = --reg_state[regno].use_index;
8905 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
8907 /* We have found another use for a register that is already
8908 used later. Check if the offsets match; if not, mark the
8909 register as used in an unknown fashion. */
8910 if (! rtx_equal_p (offset, reg_state[regno].offset))
8912 reg_state[regno].use_index = -1;
8918 /* This is the first use of this register we have seen since we
8919 marked it as dead. */
8920 reg_state[regno].offset = offset;
8921 reg_state[regno].use_ruid = reload_combine_ruid;
8923 reg_state[regno].reg_use[use_index].insn = insn;
8924 reg_state[regno].reg_use[use_index].usep = xp;
8932 /* Recursively process the components of X. */
8933 fmt = GET_RTX_FORMAT (code);
8934 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8937 reload_combine_note_use (&XEXP (x, i), insn);
8938 else if (fmt[i] == 'E')
8940 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8941 reload_combine_note_use (&XVECEXP (x, i, j), insn);
8946 /* See if we can reduce the cost of a constant by replacing a move with
8948 /* We cannot do our optimization across labels. Invalidating all the
8949 information about register contents we have would be costly, so we
8950 use last_label_luid (local variable of reload_cse_move2add) to note
8951 where the label is and then later disable any optimization that would
8953 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
8954 reg_set_luid[n] is larger than last_label_luid[n] . */
8955 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
8957 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
8958 reg_mode[n] to be valid.
8959 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
8960 has been set to reg_offset[n] in mode reg_mode[n] .
8961 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
8962 register n has been set to the sum of reg_offset[n] and register
8963 reg_base_reg[n], calculated in mode reg_mode[n] . */
8964 static rtx reg_offset[FIRST_PSEUDO_REGISTER];
8965 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
8966 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
8968 /* move2add_luid is linearily increased while scanning the instructions
8969 from first to last. It is used to set reg_set_luid in
8970 reload_cse_move2add and move2add_note_store. */
8971 static int move2add_luid;
8973 /* Generate a CONST_INT and force it in the range of MODE. */
8976 gen_mode_int (mode, value)
8977 enum machine_mode mode;
8978 HOST_WIDE_INT value;
8980 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
8981 int width = GET_MODE_BITSIZE (mode);
8983 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
8985 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
8986 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
8987 cval |= (HOST_WIDE_INT) -1 << width;
8989 return GEN_INT (cval);
8993 reload_cse_move2add (first)
8998 int last_label_luid;
9000 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9001 reg_set_luid[i] = 0;
9003 last_label_luid = 0;
9005 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9009 if (GET_CODE (insn) == CODE_LABEL)
9010 last_label_luid = move2add_luid;
9011 if (! INSN_P (insn))
9013 pat = PATTERN (insn);
9014 /* For simplicity, we only perform this optimization on
9015 straightforward SETs. */
9016 if (GET_CODE (pat) == SET
9017 && GET_CODE (SET_DEST (pat)) == REG)
9019 rtx reg = SET_DEST (pat);
9020 int regno = REGNO (reg);
9021 rtx src = SET_SRC (pat);
9023 /* Check if we have valid information on the contents of this
9024 register in the mode of REG. */
9025 /* ??? We don't know how zero / sign extension is handled, hence
9026 we can't go from a narrower to a wider mode. */
9027 if (reg_set_luid[regno] > last_label_luid
9028 && ((GET_MODE_SIZE (GET_MODE (reg))
9029 == GET_MODE_SIZE (reg_mode[regno]))
9030 || ((GET_MODE_SIZE (GET_MODE (reg))
9031 <= GET_MODE_SIZE (reg_mode[regno]))
9032 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (reg)),
9033 GET_MODE_BITSIZE (reg_mode[regno]))))
9034 && GET_CODE (reg_offset[regno]) == CONST_INT)
9036 /* Try to transform (set (REGX) (CONST_INT A))
9038 (set (REGX) (CONST_INT B))
9040 (set (REGX) (CONST_INT A))
9042 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9044 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9048 = gen_mode_int (GET_MODE (reg),
9049 INTVAL (src) - INTVAL (reg_offset[regno]));
9050 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9051 use (set (reg) (reg)) instead.
9052 We don't delete this insn, nor do we convert it into a
9053 note, to avoid losing register notes or the return
9054 value flag. jump2 already knowns how to get rid of
9056 if (new_src == const0_rtx)
9057 success = validate_change (insn, &SET_SRC (pat), reg, 0);
9058 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9059 && have_add2_insn (GET_MODE (reg)))
9060 success = validate_change (insn, &PATTERN (insn),
9061 gen_add2_insn (reg, new_src), 0);
9062 reg_set_luid[regno] = move2add_luid;
9063 reg_mode[regno] = GET_MODE (reg);
9064 reg_offset[regno] = src;
9068 /* Try to transform (set (REGX) (REGY))
9069 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9072 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9075 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9077 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9078 else if (GET_CODE (src) == REG
9079 && reg_base_reg[regno] == (int) REGNO (src)
9080 && reg_set_luid[regno] > reg_set_luid[REGNO (src)])
9082 rtx next = next_nonnote_insn (insn);
9085 set = single_set (next);
9088 && SET_DEST (set) == reg
9089 && GET_CODE (SET_SRC (set)) == PLUS
9090 && XEXP (SET_SRC (set), 0) == reg
9091 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9093 rtx src3 = XEXP (SET_SRC (set), 1);
9095 = gen_mode_int (GET_MODE (reg),
9097 - INTVAL (reg_offset[regno]));
9100 if (new_src == const0_rtx)
9101 /* See above why we create (set (reg) (reg)) here. */
9103 = validate_change (next, &SET_SRC (set), reg, 0);
9104 else if ((rtx_cost (new_src, PLUS)
9105 < COSTS_N_INSNS (1) + rtx_cost (src3, SET))
9106 && have_add2_insn (GET_MODE (reg)))
9108 = validate_change (next, &PATTERN (next),
9109 gen_add2_insn (reg, new_src), 0);
9112 /* INSN might be the first insn in a basic block
9113 if the preceding insn is a conditional jump
9114 or a possible-throwing call. */
9115 PUT_CODE (insn, NOTE);
9116 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9117 NOTE_SOURCE_FILE (insn) = 0;
9120 reg_set_luid[regno] = move2add_luid;
9121 reg_mode[regno] = GET_MODE (reg);
9122 reg_offset[regno] = src3;
9129 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9131 if (REG_NOTE_KIND (note) == REG_INC
9132 && GET_CODE (XEXP (note, 0)) == REG)
9134 /* Indicate that this register has been recently written to,
9135 but the exact contents are not available. */
9136 int regno = REGNO (XEXP (note, 0));
9137 if (regno < FIRST_PSEUDO_REGISTER)
9139 reg_set_luid[regno] = move2add_luid;
9140 reg_offset[regno] = note;
9144 note_stores (PATTERN (insn), move2add_note_store, NULL);
9145 /* If this is a CALL_INSN, all call used registers are stored with
9147 if (GET_CODE (insn) == CALL_INSN)
9149 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9151 if (call_used_regs[i])
9153 reg_set_luid[i] = move2add_luid;
9154 reg_offset[i] = insn; /* Invalidate contents. */
9161 /* SET is a SET or CLOBBER that sets DST.
9162 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9163 Called from reload_cse_move2add via note_stores. */
9166 move2add_note_store (dst, set, data)
9168 void *data ATTRIBUTE_UNUSED;
9170 unsigned int regno = 0;
9172 enum machine_mode mode = GET_MODE (dst);
9174 if (GET_CODE (dst) == SUBREG)
9176 regno = SUBREG_WORD (dst);
9177 dst = SUBREG_REG (dst);
9180 /* Some targets do argument pushes without adding REG_INC notes. */
9182 if (GET_CODE (dst) == MEM)
9184 dst = XEXP (dst, 0);
9185 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_DEC
9186 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
9188 regno = REGNO (XEXP (dst, 0));
9189 reg_set_luid[regno] = move2add_luid;
9190 reg_offset[regno] = dst;
9194 if (GET_CODE (dst) != REG)
9197 regno += REGNO (dst);
9199 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9200 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9201 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9202 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9204 rtx src = SET_SRC (set);
9206 reg_mode[regno] = mode;
9207 switch (GET_CODE (src))
9211 rtx src0 = XEXP (src, 0);
9213 if (GET_CODE (src0) == REG)
9215 if (REGNO (src0) != regno
9216 || reg_offset[regno] != const0_rtx)
9217 reg_base_reg[regno] = REGNO (src0);
9219 reg_set_luid[regno] = move2add_luid;
9220 reg_offset[regno] = XEXP (src, 1);
9224 reg_set_luid[regno] = move2add_luid;
9225 reg_offset[regno] = set; /* Invalidate contents. */
9230 reg_base_reg[regno] = REGNO (SET_SRC (set));
9231 reg_offset[regno] = const0_rtx;
9232 reg_set_luid[regno] = move2add_luid;
9236 reg_base_reg[regno] = -1;
9237 reg_offset[regno] = SET_SRC (set);
9238 reg_set_luid[regno] = move2add_luid;
9244 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9246 for (i = regno; i < endregno; i++)
9248 /* Indicate that this register has been recently written to,
9249 but the exact contents are not available. */
9250 reg_set_luid[i] = move2add_luid;
9251 reg_offset[i] = dst;
9258 add_auto_inc_notes (insn, x)
9262 enum rtx_code code = GET_CODE (x);
9266 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9269 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9273 /* Scan all the operand sub-expressions. */
9274 fmt = GET_RTX_FORMAT (code);
9275 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9278 add_auto_inc_notes (insn, XEXP (x, i));
9279 else if (fmt[i] == 'E')
9280 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9281 add_auto_inc_notes (insn, XVECEXP (x, i, j));
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