1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 88, 89, 92-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "insn-flags.h"
32 #include "insn-codes.h"
37 #include "basic-block.h"
44 #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY
45 #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
48 /* This file contains the reload pass of the compiler, which is
49 run after register allocation has been done. It checks that
50 each insn is valid (operands required to be in registers really
51 are in registers of the proper class) and fixes up invalid ones
52 by copying values temporarily into registers for the insns
55 The results of register allocation are described by the vector
56 reg_renumber; the insns still contain pseudo regs, but reg_renumber
57 can be used to find which hard reg, if any, a pseudo reg is in.
59 The technique we always use is to free up a few hard regs that are
60 called ``reload regs'', and for each place where a pseudo reg
61 must be in a hard reg, copy it temporarily into one of the reload regs.
63 Reload regs are allocated locally for every instruction that needs
64 reloads. When there are pseudos which are allocated to a register that
65 has been chosen as a reload reg, such pseudos must be ``spilled''.
66 This means that they go to other hard regs, or to stack slots if no other
67 available hard regs can be found. Spilling can invalidate more
68 insns, requiring additional need for reloads, so we must keep checking
69 until the process stabilizes.
71 For machines with different classes of registers, we must keep track
72 of the register class needed for each reload, and make sure that
73 we allocate enough reload registers of each class.
75 The file reload.c contains the code that checks one insn for
76 validity and reports the reloads that it needs. This file
77 is in charge of scanning the entire rtl code, accumulating the
78 reload needs, spilling, assigning reload registers to use for
79 fixing up each insn, and generating the new insns to copy values
80 into the reload registers. */
83 #ifndef REGISTER_MOVE_COST
84 #define REGISTER_MOVE_COST(x, y) 2
87 /* During reload_as_needed, element N contains a REG rtx for the hard reg
88 into which reg N has been reloaded (perhaps for a previous insn). */
89 static rtx *reg_last_reload_reg;
91 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
92 for an output reload that stores into reg N. */
93 static char *reg_has_output_reload;
95 /* Indicates which hard regs are reload-registers for an output reload
96 in the current insn. */
97 static HARD_REG_SET reg_is_output_reload;
99 /* Element N is the constant value to which pseudo reg N is equivalent,
100 or zero if pseudo reg N is not equivalent to a constant.
101 find_reloads looks at this in order to replace pseudo reg N
102 with the constant it stands for. */
103 rtx *reg_equiv_constant;
105 /* Element N is a memory location to which pseudo reg N is equivalent,
106 prior to any register elimination (such as frame pointer to stack
107 pointer). Depending on whether or not it is a valid address, this value
108 is transferred to either reg_equiv_address or reg_equiv_mem. */
109 rtx *reg_equiv_memory_loc;
111 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
112 This is used when the address is not valid as a memory address
113 (because its displacement is too big for the machine.) */
114 rtx *reg_equiv_address;
116 /* Element N is the memory slot to which pseudo reg N is equivalent,
117 or zero if pseudo reg N is not equivalent to a memory slot. */
120 /* Widest width in which each pseudo reg is referred to (via subreg). */
121 static int *reg_max_ref_width;
123 /* Element N is the list of insns that initialized reg N from its equivalent
124 constant or memory slot. */
125 static rtx *reg_equiv_init;
127 /* Vector to remember old contents of reg_renumber before spilling. */
128 static short *reg_old_renumber;
130 /* During reload_as_needed, element N contains the last pseudo regno reloaded
131 into hard register N. If that pseudo reg occupied more than one register,
132 reg_reloaded_contents points to that pseudo for each spill register in
133 use; all of these must remain set for an inheritance to occur. */
134 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
136 /* During reload_as_needed, element N contains the insn for which
137 hard register N was last used. Its contents are significant only
138 when reg_reloaded_valid is set for this register. */
139 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
141 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
142 static HARD_REG_SET reg_reloaded_valid;
143 /* Indicate if the register was dead at the end of the reload.
144 This is only valid if reg_reloaded_contents is set and valid. */
145 static HARD_REG_SET reg_reloaded_dead;
147 /* Number of spill-regs so far; number of valid elements of spill_regs. */
150 /* In parallel with spill_regs, contains REG rtx's for those regs.
151 Holds the last rtx used for any given reg, or 0 if it has never
152 been used for spilling yet. This rtx is reused, provided it has
154 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
156 /* In parallel with spill_regs, contains nonzero for a spill reg
157 that was stored after the last time it was used.
158 The precise value is the insn generated to do the store. */
159 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
161 /* This is the register that was stored with spill_reg_store. This is a
162 copy of reload_out / reload_out_reg when the value was stored; if
163 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
164 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
166 /* This table is the inverse mapping of spill_regs:
167 indexed by hard reg number,
168 it contains the position of that reg in spill_regs,
169 or -1 for something that is not in spill_regs.
171 ?!? This is no longer accurate. */
172 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
174 /* This reg set indicates registers that can't be used as spill registers for
175 the currently processed insn. These are the hard registers which are live
176 during the insn, but not allocated to pseudos, as well as fixed
178 static HARD_REG_SET bad_spill_regs;
180 /* These are the hard registers that can't be used as spill register for any
181 insn. This includes registers used for user variables and registers that
182 we can't eliminate. A register that appears in this set also can't be used
183 to retry register allocation. */
184 static HARD_REG_SET bad_spill_regs_global;
186 /* Describes order of use of registers for reloading
187 of spilled pseudo-registers. `n_spills' is the number of
188 elements that are actually valid; new ones are added at the end.
190 Both spill_regs and spill_reg_order are used on two occasions:
191 once during find_reload_regs, where they keep track of the spill registers
192 for a single insn, but also during reload_as_needed where they show all
193 the registers ever used by reload. For the latter case, the information
194 is calculated during finish_spills. */
195 static short spill_regs[FIRST_PSEUDO_REGISTER];
197 /* This vector of reg sets indicates, for each pseudo, which hard registers
198 may not be used for retrying global allocation because the register was
199 formerly spilled from one of them. If we allowed reallocating a pseudo to
200 a register that it was already allocated to, reload might not
202 static HARD_REG_SET *pseudo_previous_regs;
204 /* This vector of reg sets indicates, for each pseudo, which hard
205 registers may not be used for retrying global allocation because they
206 are used as spill registers during one of the insns in which the
208 static HARD_REG_SET *pseudo_forbidden_regs;
210 /* All hard regs that have been used as spill registers for any insn are
211 marked in this set. */
212 static HARD_REG_SET used_spill_regs;
214 /* Index of last register assigned as a spill register. We allocate in
215 a round-robin fashion. */
216 static int last_spill_reg;
218 /* Nonzero if indirect addressing is supported on the machine; this means
219 that spilling (REG n) does not require reloading it into a register in
220 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
221 value indicates the level of indirect addressing supported, e.g., two
222 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
224 static char spill_indirect_levels;
226 /* Nonzero if indirect addressing is supported when the innermost MEM is
227 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
228 which these are valid is the same as spill_indirect_levels, above. */
229 char indirect_symref_ok;
231 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
232 char double_reg_address_ok;
234 /* Record the stack slot for each spilled hard register. */
235 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
237 /* Width allocated so far for that stack slot. */
238 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
240 /* Record which pseudos needed to be spilled. */
241 static regset_head spilled_pseudos;
243 /* Used for communication between order_regs_for_reload and count_pseudo.
244 Used to avoid counting one pseudo twice. */
245 static regset_head pseudos_counted;
247 /* First uid used by insns created by reload in this function.
248 Used in find_equiv_reg. */
249 int reload_first_uid;
251 /* Flag set by local-alloc or global-alloc if anything is live in
252 a call-clobbered reg across calls. */
253 int caller_save_needed;
255 /* Set to 1 while reload_as_needed is operating.
256 Required by some machines to handle any generated moves differently. */
257 int reload_in_progress = 0;
259 /* These arrays record the insn_code of insns that may be needed to
260 perform input and output reloads of special objects. They provide a
261 place to pass a scratch register. */
262 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
263 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
265 /* This obstack is used for allocation of rtl during register elimination.
266 The allocated storage can be freed once find_reloads has processed the
268 struct obstack reload_obstack;
270 /* Points to the beginning of the reload_obstack. All insn_chain structures
271 are allocated first. */
272 char *reload_startobj;
274 /* The point after all insn_chain structures. Used to quickly deallocate
275 memory allocated in copy_reloads during calculate_needs_all_insns. */
276 char *reload_firstobj;
278 /* This points before all local rtl generated by register elimination.
279 Used to quickly free all memory after processing one insn. */
280 static char *reload_insn_firstobj;
282 #define obstack_chunk_alloc xmalloc
283 #define obstack_chunk_free free
285 /* List of insn_chain instructions, one for every insn that reload needs to
287 struct insn_chain *reload_insn_chain;
290 extern tree current_function_decl;
292 extern union tree_node *current_function_decl;
295 /* List of all insns needing reloads. */
296 static struct insn_chain *insns_need_reload;
298 /* This structure is used to record information about register eliminations.
299 Each array entry describes one possible way of eliminating a register
300 in favor of another. If there is more than one way of eliminating a
301 particular register, the most preferred should be specified first. */
305 int from; /* Register number to be eliminated. */
306 int to; /* Register number used as replacement. */
307 int initial_offset; /* Initial difference between values. */
308 int can_eliminate; /* Non-zero if this elimination can be done. */
309 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
310 insns made by reload. */
311 int offset; /* Current offset between the two regs. */
312 int previous_offset; /* Offset at end of previous insn. */
313 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
314 rtx from_rtx; /* REG rtx for the register to be eliminated.
315 We cannot simply compare the number since
316 we might then spuriously replace a hard
317 register corresponding to a pseudo
318 assigned to the reg to be eliminated. */
319 rtx to_rtx; /* REG rtx for the replacement. */
322 static struct elim_table * reg_eliminate = 0;
324 /* This is an intermediate structure to initialize the table. It has
325 exactly the members provided by ELIMINABLE_REGS. */
326 static struct elim_table_1
330 } reg_eliminate_1[] =
332 /* If a set of eliminable registers was specified, define the table from it.
333 Otherwise, default to the normal case of the frame pointer being
334 replaced by the stack pointer. */
336 #ifdef ELIMINABLE_REGS
339 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
342 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate_1/sizeof reg_eliminate_1[0])
344 /* Record the number of pending eliminations that have an offset not equal
345 to their initial offset. If non-zero, we use a new copy of each
346 replacement result in any insns encountered. */
347 int num_not_at_initial_offset;
349 /* Count the number of registers that we may be able to eliminate. */
350 static int num_eliminable;
351 /* And the number of registers that are equivalent to a constant that
352 can be eliminated to frame_pointer / arg_pointer + constant. */
353 static int num_eliminable_invariants;
355 /* For each label, we record the offset of each elimination. If we reach
356 a label by more than one path and an offset differs, we cannot do the
357 elimination. This information is indexed by the number of the label.
358 The first table is an array of flags that records whether we have yet
359 encountered a label and the second table is an array of arrays, one
360 entry in the latter array for each elimination. */
362 static char *offsets_known_at;
363 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
365 /* Number of labels in the current function. */
367 static int num_labels;
369 static void maybe_fix_stack_asms PROTO((void));
370 static void copy_reloads PROTO((struct insn_chain *));
371 static void calculate_needs_all_insns PROTO((int));
372 static int find_reg PROTO((struct insn_chain *, int,
374 static void find_reload_regs PROTO((struct insn_chain *, FILE *));
375 static void select_reload_regs PROTO((FILE *));
376 static void delete_caller_save_insns PROTO((void));
378 static void spill_failure PROTO((rtx));
379 static void count_spilled_pseudo PROTO((int, int, int));
380 static void delete_dead_insn PROTO((rtx));
381 static void alter_reg PROTO((int, int));
382 static void set_label_offsets PROTO((rtx, rtx, int));
383 static void check_eliminable_occurrences PROTO((rtx));
384 static void elimination_effects PROTO((rtx, enum machine_mode));
385 static int eliminate_regs_in_insn PROTO((rtx, int));
386 static void update_eliminable_offsets PROTO((void));
387 static void mark_not_eliminable PROTO((rtx, rtx, void *));
388 static void set_initial_elim_offsets PROTO((void));
389 static void verify_initial_elim_offsets PROTO((void));
390 static void set_initial_label_offsets PROTO((void));
391 static void set_offsets_for_label PROTO((rtx));
392 static void init_elim_table PROTO((void));
393 static void update_eliminables PROTO((HARD_REG_SET *));
394 static void spill_hard_reg PROTO((int, FILE *, int));
395 static int finish_spills PROTO((int, FILE *));
396 static void ior_hard_reg_set PROTO((HARD_REG_SET *, HARD_REG_SET *));
397 static void scan_paradoxical_subregs PROTO((rtx));
398 static void count_pseudo PROTO((int));
399 static void order_regs_for_reload PROTO((struct insn_chain *));
400 static void reload_as_needed PROTO((int));
401 static void forget_old_reloads_1 PROTO((rtx, rtx, void *));
402 static int reload_reg_class_lower PROTO((const PTR, const PTR));
403 static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
405 static void clear_reload_reg_in_use PROTO((int, int, enum reload_type,
407 static int reload_reg_free_p PROTO((int, int, enum reload_type));
408 static int reload_reg_free_for_value_p PROTO((int, int, enum reload_type,
409 rtx, rtx, int, int));
410 static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
411 static int allocate_reload_reg PROTO((struct insn_chain *, int, int));
412 static void failed_reload PROTO((rtx, int));
413 static int set_reload_reg PROTO((int, int));
414 static void choose_reload_regs_init PROTO((struct insn_chain *, rtx *));
415 static void choose_reload_regs PROTO((struct insn_chain *));
416 static void merge_assigned_reloads PROTO((rtx));
417 static void emit_reload_insns PROTO((struct insn_chain *));
418 static void delete_output_reload PROTO((rtx, int, int));
419 static void delete_address_reloads PROTO((rtx, rtx));
420 static void delete_address_reloads_1 PROTO((rtx, rtx, rtx));
421 static rtx inc_for_reload PROTO((rtx, rtx, rtx, int));
422 static int constraint_accepts_reg_p PROTO((const char *, rtx));
423 static void reload_cse_regs_1 PROTO((rtx));
424 static void reload_cse_invalidate_regno PROTO((int, enum machine_mode, int));
425 static int reload_cse_mem_conflict_p PROTO((rtx, rtx));
426 static void reload_cse_invalidate_mem PROTO((rtx));
427 static void reload_cse_invalidate_rtx PROTO((rtx, rtx, void *));
428 static int reload_cse_regno_equal_p PROTO((int, rtx, enum machine_mode));
429 static int reload_cse_noop_set_p PROTO((rtx, rtx));
430 static int reload_cse_simplify_set PROTO((rtx, rtx));
431 static int reload_cse_simplify_operands PROTO((rtx));
432 static void reload_cse_check_clobber PROTO((rtx, rtx, void *));
433 static void reload_cse_record_set PROTO((rtx, rtx));
434 static void reload_combine PROTO((void));
435 static void reload_combine_note_use PROTO((rtx *, rtx));
436 static void reload_combine_note_store PROTO((rtx, rtx, void *));
437 static void reload_cse_move2add PROTO((rtx));
438 static void move2add_note_store PROTO((rtx, rtx, void *));
440 static void add_auto_inc_notes PROTO((rtx, rtx));
442 static rtx gen_mode_int PROTO((enum machine_mode,
444 static void failed_reload PROTO((rtx, int));
445 static int set_reload_reg PROTO((int, int));
446 extern void dump_needs PROTO((struct insn_chain *, FILE *));
448 /* Initialize the reload pass once per compilation. */
455 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
456 Set spill_indirect_levels to the number of levels such addressing is
457 permitted, zero if it is not permitted at all. */
460 = gen_rtx_MEM (Pmode,
463 LAST_VIRTUAL_REGISTER + 1),
465 spill_indirect_levels = 0;
467 while (memory_address_p (QImode, tem))
469 spill_indirect_levels++;
470 tem = gen_rtx_MEM (Pmode, tem);
473 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
475 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
476 indirect_symref_ok = memory_address_p (QImode, tem);
478 /* See if reg+reg is a valid (and offsettable) address. */
480 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
482 tem = gen_rtx_PLUS (Pmode,
483 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
484 gen_rtx_REG (Pmode, i));
486 /* This way, we make sure that reg+reg is an offsettable address. */
487 tem = plus_constant (tem, 4);
489 if (memory_address_p (QImode, tem))
491 double_reg_address_ok = 1;
496 /* Initialize obstack for our rtl allocation. */
497 gcc_obstack_init (&reload_obstack);
498 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
500 INIT_REG_SET (&spilled_pseudos);
501 INIT_REG_SET (&pseudos_counted);
504 /* List of insn chains that are currently unused. */
505 static struct insn_chain *unused_insn_chains = 0;
507 /* Allocate an empty insn_chain structure. */
511 struct insn_chain *c;
513 if (unused_insn_chains == 0)
515 c = (struct insn_chain *)
516 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
517 c->live_before = OBSTACK_ALLOC_REG_SET (&reload_obstack);
518 c->live_after = OBSTACK_ALLOC_REG_SET (&reload_obstack);
522 c = unused_insn_chains;
523 unused_insn_chains = c->next;
525 c->is_caller_save_insn = 0;
526 c->need_operand_change = 0;
532 /* Small utility function to set all regs in hard reg set TO which are
533 allocated to pseudos in regset FROM. */
535 compute_use_by_pseudos (to, from)
540 EXECUTE_IF_SET_IN_REG_SET
541 (from, FIRST_PSEUDO_REGISTER, regno,
543 int r = reg_renumber[regno];
547 /* reload_combine uses the information from
548 BASIC_BLOCK->global_live_at_start, which might still
549 contain registers that have not actually been allocated
550 since they have an equivalence. */
551 if (! reload_completed)
556 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
558 SET_HARD_REG_BIT (*to, r + nregs);
563 /* Global variables used by reload and its subroutines. */
565 /* Set during calculate_needs if an insn needs register elimination. */
566 static int something_needs_elimination;
567 /* Set during calculate_needs if an insn needs an operand changed. */
568 int something_needs_operands_changed;
570 /* Nonzero means we couldn't get enough spill regs. */
573 /* Main entry point for the reload pass.
575 FIRST is the first insn of the function being compiled.
577 GLOBAL nonzero means we were called from global_alloc
578 and should attempt to reallocate any pseudoregs that we
579 displace from hard regs we will use for reloads.
580 If GLOBAL is zero, we do not have enough information to do that,
581 so any pseudo reg that is spilled must go to the stack.
583 DUMPFILE is the global-reg debugging dump file stream, or 0.
584 If it is nonzero, messages are written to it to describe
585 which registers are seized as reload regs, which pseudo regs
586 are spilled from them, and where the pseudo regs are reallocated to.
588 Return value is nonzero if reload failed
589 and we must not do any more for this function. */
592 reload (first, global, dumpfile)
599 register struct elim_table *ep;
601 /* The two pointers used to track the true location of the memory used
602 for label offsets. */
603 char *real_known_ptr = NULL_PTR;
604 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
606 /* Make sure even insns with volatile mem refs are recognizable. */
611 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
613 /* Make sure that the last insn in the chain
614 is not something that needs reloading. */
615 emit_note (NULL_PTR, NOTE_INSN_DELETED);
617 /* Enable find_equiv_reg to distinguish insns made by reload. */
618 reload_first_uid = get_max_uid ();
620 #ifdef SECONDARY_MEMORY_NEEDED
621 /* Initialize the secondary memory table. */
622 clear_secondary_mem ();
625 /* We don't have a stack slot for any spill reg yet. */
626 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
627 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
629 /* Initialize the save area information for caller-save, in case some
633 /* Compute which hard registers are now in use
634 as homes for pseudo registers.
635 This is done here rather than (eg) in global_alloc
636 because this point is reached even if not optimizing. */
637 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
640 /* A function that receives a nonlocal goto must save all call-saved
642 if (current_function_has_nonlocal_label)
643 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
645 if (! call_used_regs[i] && ! fixed_regs[i])
646 regs_ever_live[i] = 1;
649 /* Find all the pseudo registers that didn't get hard regs
650 but do have known equivalent constants or memory slots.
651 These include parameters (known equivalent to parameter slots)
652 and cse'd or loop-moved constant memory addresses.
654 Record constant equivalents in reg_equiv_constant
655 so they will be substituted by find_reloads.
656 Record memory equivalents in reg_mem_equiv so they can
657 be substituted eventually by altering the REG-rtx's. */
659 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
660 reg_equiv_memory_loc = (rtx *) xcalloc (max_regno, sizeof (rtx));
661 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
662 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
663 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
664 reg_max_ref_width = (int *) xcalloc (max_regno, sizeof (int));
665 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
666 bcopy ((PTR) reg_renumber, (PTR) reg_old_renumber, max_regno * sizeof (short));
667 pseudo_forbidden_regs
668 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
670 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
672 CLEAR_HARD_REG_SET (bad_spill_regs_global);
674 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
675 Also find all paradoxical subregs and find largest such for each pseudo.
676 On machines with small register classes, record hard registers that
677 are used for user variables. These can never be used for spills.
678 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
679 caller-saved registers must be marked live. */
681 num_eliminable_invariants = 0;
682 for (insn = first; insn; insn = NEXT_INSN (insn))
684 rtx set = single_set (insn);
686 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
687 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
688 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
689 if (! call_used_regs[i])
690 regs_ever_live[i] = 1;
692 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
694 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
696 #ifdef LEGITIMATE_PIC_OPERAND_P
697 && (! function_invariant_p (XEXP (note, 0))
699 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
703 rtx x = XEXP (note, 0);
704 i = REGNO (SET_DEST (set));
705 if (i > LAST_VIRTUAL_REGISTER)
707 if (GET_CODE (x) == MEM)
709 /* If the operand is a PLUS, the MEM may be shared,
710 so make sure we have an unshared copy here. */
711 if (GET_CODE (XEXP (x, 0)) == PLUS)
714 reg_equiv_memory_loc[i] = x;
716 else if (function_invariant_p (x))
718 if (GET_CODE (x) == PLUS)
720 /* This is PLUS of frame pointer and a constant,
721 and might be shared. Unshare it. */
722 reg_equiv_constant[i] = copy_rtx (x);
723 num_eliminable_invariants++;
725 else if (x == frame_pointer_rtx
726 || x == arg_pointer_rtx)
728 reg_equiv_constant[i] = x;
729 num_eliminable_invariants++;
731 else if (LEGITIMATE_CONSTANT_P (x))
732 reg_equiv_constant[i] = x;
734 reg_equiv_memory_loc[i]
735 = force_const_mem (GET_MODE (SET_DEST (set)), x);
740 /* If this register is being made equivalent to a MEM
741 and the MEM is not SET_SRC, the equivalencing insn
742 is one with the MEM as a SET_DEST and it occurs later.
743 So don't mark this insn now. */
744 if (GET_CODE (x) != MEM
745 || rtx_equal_p (SET_SRC (set), x))
747 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
752 /* If this insn is setting a MEM from a register equivalent to it,
753 this is the equivalencing insn. */
754 else if (set && GET_CODE (SET_DEST (set)) == MEM
755 && GET_CODE (SET_SRC (set)) == REG
756 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
757 && rtx_equal_p (SET_DEST (set),
758 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
759 reg_equiv_init[REGNO (SET_SRC (set))]
760 = gen_rtx_INSN_LIST (VOIDmode, insn,
761 reg_equiv_init[REGNO (SET_SRC (set))]);
763 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
764 scan_paradoxical_subregs (PATTERN (insn));
769 num_labels = max_label_num () - get_first_label_num ();
771 /* Allocate the tables used to store offset information at labels. */
772 /* We used to use alloca here, but the size of what it would try to
773 allocate would occasionally cause it to exceed the stack limit and
774 cause a core dump. */
775 real_known_ptr = xmalloc (num_labels);
777 = (int (*)[NUM_ELIMINABLE_REGS])
778 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
780 offsets_known_at = real_known_ptr - get_first_label_num ();
782 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
784 /* Alter each pseudo-reg rtx to contain its hard reg number.
785 Assign stack slots to the pseudos that lack hard regs or equivalents.
786 Do not touch virtual registers. */
788 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
791 /* If we have some registers we think can be eliminated, scan all insns to
792 see if there is an insn that sets one of these registers to something
793 other than itself plus a constant. If so, the register cannot be
794 eliminated. Doing this scan here eliminates an extra pass through the
795 main reload loop in the most common case where register elimination
797 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
798 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
799 || GET_CODE (insn) == CALL_INSN)
800 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
802 maybe_fix_stack_asms ();
804 insns_need_reload = 0;
805 something_needs_elimination = 0;
807 /* Initialize to -1, which means take the first spill register. */
810 /* Spill any hard regs that we know we can't eliminate. */
811 CLEAR_HARD_REG_SET (used_spill_regs);
812 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
813 if (! ep->can_eliminate)
814 spill_hard_reg (ep->from, dumpfile, 1);
816 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
817 if (frame_pointer_needed)
818 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, dumpfile, 1);
820 finish_spills (global, dumpfile);
822 /* From now on, we may need to generate moves differently. We may also
823 allow modifications of insns which cause them to not be recognized.
824 Any such modifications will be cleaned up during reload itself. */
825 reload_in_progress = 1;
827 /* This loop scans the entire function each go-round
828 and repeats until one repetition spills no additional hard regs. */
831 int something_changed;
834 HOST_WIDE_INT starting_frame_size;
836 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done
837 here because the stack size may be a part of the offset computation
838 for register elimination, and there might have been new stack slots
839 created in the last iteration of this loop. */
840 assign_stack_local (BLKmode, 0, 0);
842 starting_frame_size = get_frame_size ();
844 set_initial_elim_offsets ();
845 set_initial_label_offsets ();
847 /* For each pseudo register that has an equivalent location defined,
848 try to eliminate any eliminable registers (such as the frame pointer)
849 assuming initial offsets for the replacement register, which
852 If the resulting location is directly addressable, substitute
853 the MEM we just got directly for the old REG.
855 If it is not addressable but is a constant or the sum of a hard reg
856 and constant, it is probably not addressable because the constant is
857 out of range, in that case record the address; we will generate
858 hairy code to compute the address in a register each time it is
859 needed. Similarly if it is a hard register, but one that is not
860 valid as an address register.
862 If the location is not addressable, but does not have one of the
863 above forms, assign a stack slot. We have to do this to avoid the
864 potential of producing lots of reloads if, e.g., a location involves
865 a pseudo that didn't get a hard register and has an equivalent memory
866 location that also involves a pseudo that didn't get a hard register.
868 Perhaps at some point we will improve reload_when_needed handling
869 so this problem goes away. But that's very hairy. */
871 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
872 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
874 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
876 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
878 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
879 else if (CONSTANT_P (XEXP (x, 0))
880 || (GET_CODE (XEXP (x, 0)) == REG
881 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
882 || (GET_CODE (XEXP (x, 0)) == PLUS
883 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
884 && (REGNO (XEXP (XEXP (x, 0), 0))
885 < FIRST_PSEUDO_REGISTER)
886 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
887 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
890 /* Make a new stack slot. Then indicate that something
891 changed so we go back and recompute offsets for
892 eliminable registers because the allocation of memory
893 below might change some offset. reg_equiv_{mem,address}
894 will be set up for this pseudo on the next pass around
896 reg_equiv_memory_loc[i] = 0;
897 reg_equiv_init[i] = 0;
902 if (caller_save_needed)
905 /* If we allocated another stack slot, redo elimination bookkeeping. */
906 if (starting_frame_size != get_frame_size ())
909 if (caller_save_needed)
911 save_call_clobbered_regs ();
912 /* That might have allocated new insn_chain structures. */
913 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
916 calculate_needs_all_insns (global);
918 CLEAR_REG_SET (&spilled_pseudos);
921 something_changed = 0;
923 /* If we allocated any new memory locations, make another pass
924 since it might have changed elimination offsets. */
925 if (starting_frame_size != get_frame_size ())
926 something_changed = 1;
929 HARD_REG_SET to_spill;
930 CLEAR_HARD_REG_SET (to_spill);
931 update_eliminables (&to_spill);
932 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
933 if (TEST_HARD_REG_BIT (to_spill, i))
935 spill_hard_reg (i, dumpfile, 1);
938 /* Regardless of the state of spills, if we previously had
939 a register that we thought we could eliminate, but no can
940 not eliminate, we must run another pass.
942 Consider pseudos which have an entry in reg_equiv_* which
943 reference an eliminable register. We must make another pass
944 to update reg_equiv_* so that we do not substitute in the
945 old value from when we thought the elimination could be
947 something_changed = 1;
951 select_reload_regs (dumpfile);
955 if (insns_need_reload != 0 || did_spill)
956 something_changed |= finish_spills (global, dumpfile);
958 if (! something_changed)
961 if (caller_save_needed)
962 delete_caller_save_insns ();
964 obstack_free (&reload_obstack, reload_firstobj);
967 /* If global-alloc was run, notify it of any register eliminations we have
970 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
971 if (ep->can_eliminate)
972 mark_elimination (ep->from, ep->to);
974 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
975 If that insn didn't set the register (i.e., it copied the register to
976 memory), just delete that insn instead of the equivalencing insn plus
977 anything now dead. If we call delete_dead_insn on that insn, we may
978 delete the insn that actually sets the register if the register dies
979 there and that is incorrect. */
981 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
983 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
986 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
988 rtx equiv_insn = XEXP (list, 0);
989 if (GET_CODE (equiv_insn) == NOTE)
991 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
992 delete_dead_insn (equiv_insn);
995 PUT_CODE (equiv_insn, NOTE);
996 NOTE_SOURCE_FILE (equiv_insn) = 0;
997 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1003 /* Use the reload registers where necessary
1004 by generating move instructions to move the must-be-register
1005 values into or out of the reload registers. */
1007 if (insns_need_reload != 0 || something_needs_elimination
1008 || something_needs_operands_changed)
1010 int old_frame_size = get_frame_size ();
1012 reload_as_needed (global);
1014 if (old_frame_size != get_frame_size ())
1018 verify_initial_elim_offsets ();
1021 /* If we were able to eliminate the frame pointer, show that it is no
1022 longer live at the start of any basic block. If it ls live by
1023 virtue of being in a pseudo, that pseudo will be marked live
1024 and hence the frame pointer will be known to be live via that
1027 if (! frame_pointer_needed)
1028 for (i = 0; i < n_basic_blocks; i++)
1029 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1030 HARD_FRAME_POINTER_REGNUM);
1032 /* Come here (with failure set nonzero) if we can't get enough spill regs
1033 and we decide not to abort about it. */
1036 CLEAR_REG_SET (&spilled_pseudos);
1037 reload_in_progress = 0;
1039 /* Now eliminate all pseudo regs by modifying them into
1040 their equivalent memory references.
1041 The REG-rtx's for the pseudos are modified in place,
1042 so all insns that used to refer to them now refer to memory.
1044 For a reg that has a reg_equiv_address, all those insns
1045 were changed by reloading so that no insns refer to it any longer;
1046 but the DECL_RTL of a variable decl may refer to it,
1047 and if so this causes the debugging info to mention the variable. */
1049 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1054 int is_readonly = 0;
1056 if (reg_equiv_memory_loc[i])
1058 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1059 is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]);
1060 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1063 if (reg_equiv_mem[i])
1064 addr = XEXP (reg_equiv_mem[i], 0);
1066 if (reg_equiv_address[i])
1067 addr = reg_equiv_address[i];
1071 if (reg_renumber[i] < 0)
1073 rtx reg = regno_reg_rtx[i];
1074 PUT_CODE (reg, MEM);
1075 XEXP (reg, 0) = addr;
1076 REG_USERVAR_P (reg) = 0;
1077 RTX_UNCHANGING_P (reg) = is_readonly;
1078 MEM_IN_STRUCT_P (reg) = in_struct;
1079 MEM_SCALAR_P (reg) = is_scalar;
1080 /* We have no alias information about this newly created
1082 MEM_ALIAS_SET (reg) = 0;
1084 else if (reg_equiv_mem[i])
1085 XEXP (reg_equiv_mem[i], 0) = addr;
1089 /* We must set reload_completed now since the cleanup_subreg_operands call
1090 below will re-recognize each insn and reload may have generated insns
1091 which are only valid during and after reload. */
1092 reload_completed = 1;
1094 /* Make a pass over all the insns and delete all USEs which we inserted
1095 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1096 notes. Delete all CLOBBER insns that don't refer to the return value
1097 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1098 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1099 and regenerate REG_INC notes that may have been moved around. */
1101 for (insn = first; insn; insn = NEXT_INSN (insn))
1102 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1106 if ((GET_CODE (PATTERN (insn)) == USE
1107 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1108 || (GET_CODE (PATTERN (insn)) == CLOBBER
1109 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1110 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1112 PUT_CODE (insn, NOTE);
1113 NOTE_SOURCE_FILE (insn) = 0;
1114 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1118 pnote = ®_NOTES (insn);
1121 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1122 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1123 || REG_NOTE_KIND (*pnote) == REG_INC
1124 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1125 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1126 *pnote = XEXP (*pnote, 1);
1128 pnote = &XEXP (*pnote, 1);
1132 add_auto_inc_notes (insn, PATTERN (insn));
1135 /* And simplify (subreg (reg)) if it appears as an operand. */
1136 cleanup_subreg_operands (insn);
1139 /* If we are doing stack checking, give a warning if this function's
1140 frame size is larger than we expect. */
1141 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1143 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1144 static int verbose_warned = 0;
1146 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1147 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1148 size += UNITS_PER_WORD;
1150 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1152 warning ("frame size too large for reliable stack checking");
1153 if (! verbose_warned)
1155 warning ("try reducing the number of local variables");
1161 /* Indicate that we no longer have known memory locations or constants. */
1162 if (reg_equiv_constant)
1163 free (reg_equiv_constant);
1164 reg_equiv_constant = 0;
1165 if (reg_equiv_memory_loc)
1166 free (reg_equiv_memory_loc);
1167 reg_equiv_memory_loc = 0;
1170 free (real_known_ptr);
1174 free (reg_equiv_mem);
1175 free (reg_equiv_init);
1176 free (reg_equiv_address);
1177 free (reg_max_ref_width);
1178 free (reg_old_renumber);
1179 free (pseudo_previous_regs);
1180 free (pseudo_forbidden_regs);
1182 CLEAR_HARD_REG_SET (used_spill_regs);
1183 for (i = 0; i < n_spills; i++)
1184 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1186 /* Free all the insn_chain structures at once. */
1187 obstack_free (&reload_obstack, reload_startobj);
1188 unused_insn_chains = 0;
1193 /* Yet another special case. Unfortunately, reg-stack forces people to
1194 write incorrect clobbers in asm statements. These clobbers must not
1195 cause the register to appear in bad_spill_regs, otherwise we'll call
1196 fatal_insn later. We clear the corresponding regnos in the live
1197 register sets to avoid this.
1198 The whole thing is rather sick, I'm afraid. */
1200 maybe_fix_stack_asms ()
1203 const char *constraints[MAX_RECOG_OPERANDS];
1204 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1205 struct insn_chain *chain;
1207 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1210 HARD_REG_SET clobbered, allowed;
1213 if (GET_RTX_CLASS (GET_CODE (chain->insn)) != 'i'
1214 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1216 pat = PATTERN (chain->insn);
1217 if (GET_CODE (pat) != PARALLEL)
1220 CLEAR_HARD_REG_SET (clobbered);
1221 CLEAR_HARD_REG_SET (allowed);
1223 /* First, make a mask of all stack regs that are clobbered. */
1224 for (i = 0; i < XVECLEN (pat, 0); i++)
1226 rtx t = XVECEXP (pat, 0, i);
1227 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1228 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1231 /* Get the operand values and constraints out of the insn. */
1232 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1233 constraints, operand_mode);
1235 /* For every operand, see what registers are allowed. */
1236 for (i = 0; i < noperands; i++)
1238 const char *p = constraints[i];
1239 /* For every alternative, we compute the class of registers allowed
1240 for reloading in CLS, and merge its contents into the reg set
1242 int cls = (int) NO_REGS;
1248 if (c == '\0' || c == ',' || c == '#')
1250 /* End of one alternative - mark the regs in the current
1251 class, and reset the class. */
1252 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1257 } while (c != '\0' && c != ',');
1265 case '=': case '+': case '*': case '%': case '?': case '!':
1266 case '0': case '1': case '2': case '3': case '4': case 'm':
1267 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1268 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1269 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1271 #ifdef EXTRA_CONSTRAINT
1272 case 'Q': case 'R': case 'S': case 'T': case 'U':
1277 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1282 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1286 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1291 /* Those of the registers which are clobbered, but allowed by the
1292 constraints, must be usable as reload registers. So clear them
1293 out of the life information. */
1294 AND_HARD_REG_SET (allowed, clobbered);
1295 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1296 if (TEST_HARD_REG_BIT (allowed, i))
1298 CLEAR_REGNO_REG_SET (chain->live_before, i);
1299 CLEAR_REGNO_REG_SET (chain->live_after, i);
1306 /* Copy the global variables n_reloads and rld into the corresponding elts
1309 copy_reloads (chain)
1310 struct insn_chain *chain;
1312 chain->n_reloads = n_reloads;
1314 = (struct reload *) obstack_alloc (&reload_obstack,
1315 n_reloads * sizeof (struct reload));
1316 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1317 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1320 /* Walk the chain of insns, and determine for each whether it needs reloads
1321 and/or eliminations. Build the corresponding insns_need_reload list, and
1322 set something_needs_elimination as appropriate. */
1324 calculate_needs_all_insns (global)
1327 struct insn_chain **pprev_reload = &insns_need_reload;
1328 struct insn_chain *chain;
1330 something_needs_elimination = 0;
1332 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1333 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1335 rtx insn = chain->insn;
1337 /* Clear out the shortcuts. */
1338 chain->n_reloads = 0;
1339 chain->need_elim = 0;
1340 chain->need_reload = 0;
1341 chain->need_operand_change = 0;
1343 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1344 include REG_LABEL), we need to see what effects this has on the
1345 known offsets at labels. */
1347 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1348 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1349 && REG_NOTES (insn) != 0))
1350 set_label_offsets (insn, insn, 0);
1352 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1354 rtx old_body = PATTERN (insn);
1355 int old_code = INSN_CODE (insn);
1356 rtx old_notes = REG_NOTES (insn);
1357 int did_elimination = 0;
1358 int operands_changed = 0;
1359 rtx set = single_set (insn);
1361 /* Skip insns that only set an equivalence. */
1362 if (set && GET_CODE (SET_DEST (set)) == REG
1363 && reg_renumber[REGNO (SET_DEST (set))] < 0
1364 && reg_equiv_constant[REGNO (SET_DEST (set))])
1367 /* If needed, eliminate any eliminable registers. */
1368 if (num_eliminable || num_eliminable_invariants)
1369 did_elimination = eliminate_regs_in_insn (insn, 0);
1371 /* Analyze the instruction. */
1372 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1373 global, spill_reg_order);
1375 /* If a no-op set needs more than one reload, this is likely
1376 to be something that needs input address reloads. We
1377 can't get rid of this cleanly later, and it is of no use
1378 anyway, so discard it now.
1379 We only do this when expensive_optimizations is enabled,
1380 since this complements reload inheritance / output
1381 reload deletion, and it can make debugging harder. */
1382 if (flag_expensive_optimizations && n_reloads > 1)
1384 rtx set = single_set (insn);
1386 && SET_SRC (set) == SET_DEST (set)
1387 && GET_CODE (SET_SRC (set)) == REG
1388 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1390 PUT_CODE (insn, NOTE);
1391 NOTE_SOURCE_FILE (insn) = 0;
1392 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1397 update_eliminable_offsets ();
1399 /* Remember for later shortcuts which insns had any reloads or
1400 register eliminations. */
1401 chain->need_elim = did_elimination;
1402 chain->need_reload = n_reloads > 0;
1403 chain->need_operand_change = operands_changed;
1405 /* Discard any register replacements done. */
1406 if (did_elimination)
1408 obstack_free (&reload_obstack, reload_insn_firstobj);
1409 PATTERN (insn) = old_body;
1410 INSN_CODE (insn) = old_code;
1411 REG_NOTES (insn) = old_notes;
1412 something_needs_elimination = 1;
1415 something_needs_operands_changed |= operands_changed;
1419 copy_reloads (chain);
1420 *pprev_reload = chain;
1421 pprev_reload = &chain->next_need_reload;
1428 /* Comparison function for qsort to decide which of two reloads
1429 should be handled first. *P1 and *P2 are the reload numbers. */
1432 reload_reg_class_lower (r1p, r2p)
1436 register int r1 = *(short *)r1p, r2 = *(short *)r2p;
1439 /* Consider required reloads before optional ones. */
1440 t = rld[r1].optional - rld[r2].optional;
1444 /* Count all solitary classes before non-solitary ones. */
1445 t = ((reg_class_size[(int) rld[r2].class] == 1)
1446 - (reg_class_size[(int) rld[r1].class] == 1));
1450 /* Aside from solitaires, consider all multi-reg groups first. */
1451 t = rld[r2].nregs - rld[r1].nregs;
1455 /* Consider reloads in order of increasing reg-class number. */
1456 t = (int) rld[r1].class - (int) rld[r2].class;
1460 /* If reloads are equally urgent, sort by reload number,
1461 so that the results of qsort leave nothing to chance. */
1465 /* The cost of spilling each hard reg. */
1466 static int spill_cost[FIRST_PSEUDO_REGISTER];
1468 /* When spilling multiple hard registers, we use SPILL_COST for the first
1469 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1470 only the first hard reg for a multi-reg pseudo. */
1471 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1473 /* Update the spill cost arrays, considering that pseudo REG is live. */
1478 int n_refs = REG_N_REFS (reg);
1479 int r = reg_renumber[reg];
1482 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1483 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1486 SET_REGNO_REG_SET (&pseudos_counted, reg);
1491 spill_add_cost[r] += n_refs;
1493 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1495 spill_cost[r + nregs] += n_refs;
1498 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1499 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1501 order_regs_for_reload (chain)
1502 struct insn_chain *chain;
1506 COPY_HARD_REG_SET (bad_spill_regs, bad_spill_regs_global);
1508 memset (spill_cost, 0, sizeof spill_cost);
1509 memset (spill_add_cost, 0, sizeof spill_add_cost);
1511 /* Count number of uses of each hard reg by pseudo regs allocated to it
1512 and then order them by decreasing use. */
1514 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1516 /* Test the various reasons why we can't use a register for
1517 spilling in this insn. */
1519 || REGNO_REG_SET_P (chain->live_before, i)
1520 || REGNO_REG_SET_P (chain->live_after, i))
1521 SET_HARD_REG_BIT (bad_spill_regs, i);
1523 /* Now find out which pseudos are allocated to it, and update
1525 CLEAR_REG_SET (&pseudos_counted);
1527 EXECUTE_IF_SET_IN_REG_SET
1528 (chain->live_before, FIRST_PSEUDO_REGISTER, j,
1532 EXECUTE_IF_SET_IN_REG_SET
1533 (chain->live_after, FIRST_PSEUDO_REGISTER, j,
1537 CLEAR_REG_SET (&pseudos_counted);
1540 /* Vector of reload-numbers showing the order in which the reloads should
1542 static short reload_order[MAX_RELOADS];
1544 /* This is used to keep track of the spill regs used in one insn. */
1545 static HARD_REG_SET used_spill_regs_local;
1547 /* We decided to spill hard register SPILLED, which has a size of
1548 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1549 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1550 update SPILL_COST/SPILL_ADD_COST. */
1552 count_spilled_pseudo (spilled, spilled_nregs, reg)
1553 int spilled, spilled_nregs, reg;
1555 int r = reg_renumber[reg];
1556 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1558 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1559 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1562 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1564 spill_add_cost[r] -= REG_N_REFS (reg);
1566 spill_cost[r + nregs] -= REG_N_REFS (reg);
1569 /* Find reload register to use for reload number ORDER. */
1572 find_reg (chain, order, dumpfile)
1573 struct insn_chain *chain;
1577 int rnum = reload_order[order];
1578 struct reload *rl = rld + rnum;
1579 int best_cost = INT_MAX;
1582 HARD_REG_SET not_usable;
1583 HARD_REG_SET used_by_other_reload;
1585 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1586 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1587 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1589 CLEAR_HARD_REG_SET (used_by_other_reload);
1590 for (i = 0; i < order; i++)
1592 int other = reload_order[i];
1593 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1594 for (j = 0; j < rld[other].nregs; j++)
1595 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1598 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1601 if (! TEST_HARD_REG_BIT (not_usable, regno)
1602 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1603 && HARD_REGNO_MODE_OK (regno, rl->mode))
1605 int this_cost = spill_cost[regno];
1607 int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1609 for (j = 1; j < this_nregs; j++)
1611 this_cost += spill_add_cost[regno + j];
1612 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1613 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1618 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1620 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1622 if (this_cost < best_cost
1623 /* Among registers with equal cost, prefer caller-saved ones, or
1624 use REG_ALLOC_ORDER if it is defined. */
1625 || (this_cost == best_cost
1626 #ifdef REG_ALLOC_ORDER
1627 && (inv_reg_alloc_order[regno]
1628 < inv_reg_alloc_order[best_reg])
1630 && call_used_regs[regno]
1631 && ! call_used_regs[best_reg]
1636 best_cost = this_cost;
1643 fprintf (dumpfile, "Using reg %d for reload %d\n", best_reg, rnum);
1644 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1645 rl->regno = best_reg;
1647 EXECUTE_IF_SET_IN_REG_SET
1648 (chain->live_before, FIRST_PSEUDO_REGISTER, j,
1650 count_spilled_pseudo (best_reg, rl->nregs, j);
1652 EXECUTE_IF_SET_IN_REG_SET
1653 (chain->live_after, FIRST_PSEUDO_REGISTER, j,
1655 count_spilled_pseudo (best_reg, rl->nregs, j);
1658 for (i = 0; i < rl->nregs; i++)
1660 if (spill_cost[best_reg + i] != 0
1661 || spill_add_cost[best_reg + i] != 0)
1663 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1668 /* Find more reload regs to satisfy the remaining need of an insn, which
1670 Do it by ascending class number, since otherwise a reg
1671 might be spilled for a big class and might fail to count
1672 for a smaller class even though it belongs to that class. */
1675 find_reload_regs (chain, dumpfile)
1676 struct insn_chain *chain;
1681 /* In order to be certain of getting the registers we need,
1682 we must sort the reloads into order of increasing register class.
1683 Then our grabbing of reload registers will parallel the process
1684 that provided the reload registers. */
1685 for (i = 0; i < chain->n_reloads; i++)
1687 /* Show whether this reload already has a hard reg. */
1688 if (chain->rld[i].reg_rtx)
1690 int regno = REGNO (chain->rld[i].reg_rtx);
1691 chain->rld[i].regno = regno;
1692 chain->rld[i].nregs = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1695 chain->rld[i].regno = -1;
1696 reload_order[i] = i;
1699 n_reloads = chain->n_reloads;
1700 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1702 CLEAR_HARD_REG_SET (used_spill_regs_local);
1705 fprintf (dumpfile, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1707 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1709 /* Compute the order of preference for hard registers to spill. */
1711 order_regs_for_reload (chain);
1713 for (i = 0; i < n_reloads; i++)
1715 int r = reload_order[i];
1717 /* Ignore reloads that got marked inoperative. */
1718 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1719 && ! rld[r].optional
1720 && rld[r].regno == -1)
1721 if (! find_reg (chain, i, dumpfile))
1723 spill_failure (chain->insn);
1729 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1730 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1732 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1736 select_reload_regs (dumpfile)
1739 struct insn_chain *chain;
1741 /* Try to satisfy the needs for each insn. */
1742 for (chain = insns_need_reload; chain != 0;
1743 chain = chain->next_need_reload)
1744 find_reload_regs (chain, dumpfile);
1747 /* Delete all insns that were inserted by emit_caller_save_insns during
1750 delete_caller_save_insns ()
1752 struct insn_chain *c = reload_insn_chain;
1756 while (c != 0 && c->is_caller_save_insn)
1758 struct insn_chain *next = c->next;
1761 if (insn == BLOCK_HEAD (c->block))
1762 BLOCK_HEAD (c->block) = NEXT_INSN (insn);
1763 if (insn == BLOCK_END (c->block))
1764 BLOCK_END (c->block) = PREV_INSN (insn);
1765 if (c == reload_insn_chain)
1766 reload_insn_chain = next;
1768 if (NEXT_INSN (insn) != 0)
1769 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
1770 if (PREV_INSN (insn) != 0)
1771 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
1774 next->prev = c->prev;
1776 c->prev->next = next;
1777 c->next = unused_insn_chains;
1778 unused_insn_chains = c;
1786 /* Handle the failure to find a register to spill.
1787 INSN should be one of the insns which needed this particular spill reg. */
1790 spill_failure (insn)
1793 if (asm_noperands (PATTERN (insn)) >= 0)
1794 error_for_asm (insn, "`asm' needs too many reloads");
1796 fatal_insn ("Unable to find a register to spill.", insn);
1799 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1800 data that is dead in INSN. */
1803 delete_dead_insn (insn)
1806 rtx prev = prev_real_insn (insn);
1809 /* If the previous insn sets a register that dies in our insn, delete it
1811 if (prev && GET_CODE (PATTERN (prev)) == SET
1812 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1813 && reg_mentioned_p (prev_dest, PATTERN (insn))
1814 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1815 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1816 delete_dead_insn (prev);
1818 PUT_CODE (insn, NOTE);
1819 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1820 NOTE_SOURCE_FILE (insn) = 0;
1823 /* Modify the home of pseudo-reg I.
1824 The new home is present in reg_renumber[I].
1826 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1827 or it may be -1, meaning there is none or it is not relevant.
1828 This is used so that all pseudos spilled from a given hard reg
1829 can share one stack slot. */
1832 alter_reg (i, from_reg)
1836 /* When outputting an inline function, this can happen
1837 for a reg that isn't actually used. */
1838 if (regno_reg_rtx[i] == 0)
1841 /* If the reg got changed to a MEM at rtl-generation time,
1843 if (GET_CODE (regno_reg_rtx[i]) != REG)
1846 /* Modify the reg-rtx to contain the new hard reg
1847 number or else to contain its pseudo reg number. */
1848 REGNO (regno_reg_rtx[i])
1849 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1851 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1852 allocate a stack slot for it. */
1854 if (reg_renumber[i] < 0
1855 && REG_N_REFS (i) > 0
1856 && reg_equiv_constant[i] == 0
1857 && reg_equiv_memory_loc[i] == 0)
1860 int inherent_size = PSEUDO_REGNO_BYTES (i);
1861 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1864 /* Each pseudo reg has an inherent size which comes from its own mode,
1865 and a total size which provides room for paradoxical subregs
1866 which refer to the pseudo reg in wider modes.
1868 We can use a slot already allocated if it provides both
1869 enough inherent space and enough total space.
1870 Otherwise, we allocate a new slot, making sure that it has no less
1871 inherent space, and no less total space, then the previous slot. */
1874 /* No known place to spill from => no slot to reuse. */
1875 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1876 inherent_size == total_size ? 0 : -1);
1877 if (BYTES_BIG_ENDIAN)
1878 /* Cancel the big-endian correction done in assign_stack_local.
1879 Get the address of the beginning of the slot.
1880 This is so we can do a big-endian correction unconditionally
1882 adjust = inherent_size - total_size;
1884 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1886 /* Reuse a stack slot if possible. */
1887 else if (spill_stack_slot[from_reg] != 0
1888 && spill_stack_slot_width[from_reg] >= total_size
1889 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1891 x = spill_stack_slot[from_reg];
1892 /* Allocate a bigger slot. */
1895 /* Compute maximum size needed, both for inherent size
1896 and for total size. */
1897 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1899 if (spill_stack_slot[from_reg])
1901 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1903 mode = GET_MODE (spill_stack_slot[from_reg]);
1904 if (spill_stack_slot_width[from_reg] > total_size)
1905 total_size = spill_stack_slot_width[from_reg];
1907 /* Make a slot with that size. */
1908 x = assign_stack_local (mode, total_size,
1909 inherent_size == total_size ? 0 : -1);
1911 if (BYTES_BIG_ENDIAN)
1913 /* Cancel the big-endian correction done in assign_stack_local.
1914 Get the address of the beginning of the slot.
1915 This is so we can do a big-endian correction unconditionally
1917 adjust = GET_MODE_SIZE (mode) - total_size;
1919 stack_slot = gen_rtx_MEM (mode_for_size (total_size
1922 plus_constant (XEXP (x, 0), adjust));
1924 spill_stack_slot[from_reg] = stack_slot;
1925 spill_stack_slot_width[from_reg] = total_size;
1928 /* On a big endian machine, the "address" of the slot
1929 is the address of the low part that fits its inherent mode. */
1930 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
1931 adjust += (total_size - inherent_size);
1933 /* If we have any adjustment to make, or if the stack slot is the
1934 wrong mode, make a new stack slot. */
1935 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
1937 x = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
1938 plus_constant (XEXP (x, 0), adjust));
1940 /* If this was shared among registers, must ensure we never
1941 set it readonly since that can cause scheduling
1942 problems. Note we would only have in this adjustment
1943 case in any event, since the code above doesn't set it. */
1946 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1949 /* Save the stack slot for later. */
1950 reg_equiv_memory_loc[i] = x;
1954 /* Mark the slots in regs_ever_live for the hard regs
1955 used by pseudo-reg number REGNO. */
1958 mark_home_live (regno)
1961 register int i, lim;
1962 i = reg_renumber[regno];
1965 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
1967 regs_ever_live[i++] = 1;
1970 /* This function handles the tracking of elimination offsets around branches.
1972 X is a piece of RTL being scanned.
1974 INSN is the insn that it came from, if any.
1976 INITIAL_P is non-zero if we are to set the offset to be the initial
1977 offset and zero if we are setting the offset of the label to be the
1981 set_label_offsets (x, insn, initial_p)
1986 enum rtx_code code = GET_CODE (x);
1989 struct elim_table *p;
1994 if (LABEL_REF_NONLOCAL_P (x))
1999 /* ... fall through ... */
2002 /* If we know nothing about this label, set the desired offsets. Note
2003 that this sets the offset at a label to be the offset before a label
2004 if we don't know anything about the label. This is not correct for
2005 the label after a BARRIER, but is the best guess we can make. If
2006 we guessed wrong, we will suppress an elimination that might have
2007 been possible had we been able to guess correctly. */
2009 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2011 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2012 offsets_at[CODE_LABEL_NUMBER (x)][i]
2013 = (initial_p ? reg_eliminate[i].initial_offset
2014 : reg_eliminate[i].offset);
2015 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2018 /* Otherwise, if this is the definition of a label and it is
2019 preceded by a BARRIER, set our offsets to the known offset of
2023 && (tem = prev_nonnote_insn (insn)) != 0
2024 && GET_CODE (tem) == BARRIER)
2025 set_offsets_for_label (insn);
2027 /* If neither of the above cases is true, compare each offset
2028 with those previously recorded and suppress any eliminations
2029 where the offsets disagree. */
2031 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2032 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2033 != (initial_p ? reg_eliminate[i].initial_offset
2034 : reg_eliminate[i].offset))
2035 reg_eliminate[i].can_eliminate = 0;
2040 set_label_offsets (PATTERN (insn), insn, initial_p);
2042 /* ... fall through ... */
2046 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2047 and hence must have all eliminations at their initial offsets. */
2048 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2049 if (REG_NOTE_KIND (tem) == REG_LABEL)
2050 set_label_offsets (XEXP (tem, 0), insn, 1);
2055 /* Each of the labels in the address vector must be at their initial
2056 offsets. We want the first field for ADDR_VEC and the second
2057 field for ADDR_DIFF_VEC. */
2059 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2060 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2065 /* We only care about setting PC. If the source is not RETURN,
2066 IF_THEN_ELSE, or a label, disable any eliminations not at
2067 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2068 isn't one of those possibilities. For branches to a label,
2069 call ourselves recursively.
2071 Note that this can disable elimination unnecessarily when we have
2072 a non-local goto since it will look like a non-constant jump to
2073 someplace in the current function. This isn't a significant
2074 problem since such jumps will normally be when all elimination
2075 pairs are back to their initial offsets. */
2077 if (SET_DEST (x) != pc_rtx)
2080 switch (GET_CODE (SET_SRC (x)))
2087 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2091 tem = XEXP (SET_SRC (x), 1);
2092 if (GET_CODE (tem) == LABEL_REF)
2093 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2094 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2097 tem = XEXP (SET_SRC (x), 2);
2098 if (GET_CODE (tem) == LABEL_REF)
2099 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2100 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2108 /* If we reach here, all eliminations must be at their initial
2109 offset because we are doing a jump to a variable address. */
2110 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2111 if (p->offset != p->initial_offset)
2112 p->can_eliminate = 0;
2120 /* Scan X and replace any eliminable registers (such as fp) with a
2121 replacement (such as sp), plus an offset.
2123 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2124 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2125 MEM, we are allowed to replace a sum of a register and the constant zero
2126 with the register, which we cannot do outside a MEM. In addition, we need
2127 to record the fact that a register is referenced outside a MEM.
2129 If INSN is an insn, it is the insn containing X. If we replace a REG
2130 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2131 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2132 the REG is being modified.
2134 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2135 That's used when we eliminate in expressions stored in notes.
2136 This means, do not set ref_outside_mem even if the reference
2139 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2140 replacements done assuming all offsets are at their initial values. If
2141 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2142 encounter, return the actual location so that find_reloads will do
2143 the proper thing. */
2146 eliminate_regs (x, mem_mode, insn)
2148 enum machine_mode mem_mode;
2151 enum rtx_code code = GET_CODE (x);
2152 struct elim_table *ep;
2159 if (! current_function_decl)
2178 /* This is only for the benefit of the debugging backends, which call
2179 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2180 removed after CSE. */
2181 new = eliminate_regs (XEXP (x, 0), 0, insn);
2182 if (GET_CODE (new) == MEM)
2183 return XEXP (new, 0);
2189 /* First handle the case where we encounter a bare register that
2190 is eliminable. Replace it with a PLUS. */
2191 if (regno < FIRST_PSEUDO_REGISTER)
2193 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2195 if (ep->from_rtx == x && ep->can_eliminate)
2196 return plus_constant (ep->to_rtx, ep->previous_offset);
2199 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2200 && reg_equiv_constant[regno]
2201 && ! CONSTANT_P (reg_equiv_constant[regno]))
2202 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2206 /* You might think handling MINUS in a manner similar to PLUS is a
2207 good idea. It is not. It has been tried multiple times and every
2208 time the change has had to have been reverted.
2210 Other parts of reload know a PLUS is special (gen_reload for example)
2211 and require special code to handle code a reloaded PLUS operand.
2213 Also consider backends where the flags register is clobbered by a
2214 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2215 lea instruction comes to mind). If we try to reload a MINUS, we
2216 may kill the flags register that was holding a useful value.
2218 So, please before trying to handle MINUS, consider reload as a
2219 whole instead of this little section as well as the backend issues. */
2221 /* If this is the sum of an eliminable register and a constant, rework
2223 if (GET_CODE (XEXP (x, 0)) == REG
2224 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2225 && CONSTANT_P (XEXP (x, 1)))
2227 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2229 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2231 /* The only time we want to replace a PLUS with a REG (this
2232 occurs when the constant operand of the PLUS is the negative
2233 of the offset) is when we are inside a MEM. We won't want
2234 to do so at other times because that would change the
2235 structure of the insn in a way that reload can't handle.
2236 We special-case the commonest situation in
2237 eliminate_regs_in_insn, so just replace a PLUS with a
2238 PLUS here, unless inside a MEM. */
2239 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2240 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2243 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2244 plus_constant (XEXP (x, 1),
2245 ep->previous_offset));
2248 /* If the register is not eliminable, we are done since the other
2249 operand is a constant. */
2253 /* If this is part of an address, we want to bring any constant to the
2254 outermost PLUS. We will do this by doing register replacement in
2255 our operands and seeing if a constant shows up in one of them.
2257 Note that there is no risk of modifying the structure of the insn,
2258 since we only get called for its operands, thus we are either
2259 modifying the address inside a MEM, or something like an address
2260 operand of a load-address insn. */
2263 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2264 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2266 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2268 /* If one side is a PLUS and the other side is a pseudo that
2269 didn't get a hard register but has a reg_equiv_constant,
2270 we must replace the constant here since it may no longer
2271 be in the position of any operand. */
2272 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2273 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2274 && reg_renumber[REGNO (new1)] < 0
2275 && reg_equiv_constant != 0
2276 && reg_equiv_constant[REGNO (new1)] != 0)
2277 new1 = reg_equiv_constant[REGNO (new1)];
2278 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2279 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2280 && reg_renumber[REGNO (new0)] < 0
2281 && reg_equiv_constant[REGNO (new0)] != 0)
2282 new0 = reg_equiv_constant[REGNO (new0)];
2284 new = form_sum (new0, new1);
2286 /* As above, if we are not inside a MEM we do not want to
2287 turn a PLUS into something else. We might try to do so here
2288 for an addition of 0 if we aren't optimizing. */
2289 if (! mem_mode && GET_CODE (new) != PLUS)
2290 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2298 /* If this is the product of an eliminable register and a
2299 constant, apply the distribute law and move the constant out
2300 so that we have (plus (mult ..) ..). This is needed in order
2301 to keep load-address insns valid. This case is pathological.
2302 We ignore the possibility of overflow here. */
2303 if (GET_CODE (XEXP (x, 0)) == REG
2304 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2305 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2306 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2308 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2311 /* Refs inside notes don't count for this purpose. */
2312 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2313 || GET_CODE (insn) == INSN_LIST)))
2314 ep->ref_outside_mem = 1;
2317 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2318 ep->previous_offset * INTVAL (XEXP (x, 1)));
2321 /* ... fall through ... */
2325 /* See comments before PLUS about handling MINUS. */
2327 case DIV: case UDIV:
2328 case MOD: case UMOD:
2329 case AND: case IOR: case XOR:
2330 case ROTATERT: case ROTATE:
2331 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2333 case GE: case GT: case GEU: case GTU:
2334 case LE: case LT: case LEU: case LTU:
2336 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2338 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2340 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2341 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2346 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2349 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2350 if (new != XEXP (x, 0))
2352 /* If this is a REG_DEAD note, it is not valid anymore.
2353 Using the eliminated version could result in creating a
2354 REG_DEAD note for the stack or frame pointer. */
2355 if (GET_MODE (x) == REG_DEAD)
2357 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2360 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2364 /* ... fall through ... */
2367 /* Now do eliminations in the rest of the chain. If this was
2368 an EXPR_LIST, this might result in allocating more memory than is
2369 strictly needed, but it simplifies the code. */
2372 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2373 if (new != XEXP (x, 1))
2374 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2382 case STRICT_LOW_PART:
2384 case SIGN_EXTEND: case ZERO_EXTEND:
2385 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2386 case FLOAT: case FIX:
2387 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2391 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2392 if (new != XEXP (x, 0))
2393 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2397 /* Similar to above processing, but preserve SUBREG_WORD.
2398 Convert (subreg (mem)) to (mem) if not paradoxical.
2399 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2400 pseudo didn't get a hard reg, we must replace this with the
2401 eliminated version of the memory location because push_reloads
2402 may do the replacement in certain circumstances. */
2403 if (GET_CODE (SUBREG_REG (x)) == REG
2404 && (GET_MODE_SIZE (GET_MODE (x))
2405 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2406 && reg_equiv_memory_loc != 0
2407 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2409 new = SUBREG_REG (x);
2412 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2414 if (new != XEXP (x, 0))
2416 int x_size = GET_MODE_SIZE (GET_MODE (x));
2417 int new_size = GET_MODE_SIZE (GET_MODE (new));
2419 if (GET_CODE (new) == MEM
2420 && ((x_size < new_size
2421 #ifdef WORD_REGISTER_OPERATIONS
2422 /* On these machines, combine can create rtl of the form
2423 (set (subreg:m1 (reg:m2 R) 0) ...)
2424 where m1 < m2, and expects something interesting to
2425 happen to the entire word. Moreover, it will use the
2426 (reg:m2 R) later, expecting all bits to be preserved.
2427 So if the number of words is the same, preserve the
2428 subreg so that push_reloads can see it. */
2429 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
2432 || (x_size == new_size))
2435 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2436 enum machine_mode mode = GET_MODE (x);
2438 if (BYTES_BIG_ENDIAN)
2439 offset += (MIN (UNITS_PER_WORD,
2440 GET_MODE_SIZE (GET_MODE (new)))
2441 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2443 PUT_MODE (new, mode);
2444 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2448 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
2454 /* This is only for the benefit of the debugging backends, which call
2455 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2456 removed after CSE. */
2457 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2458 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2460 /* Our only special processing is to pass the mode of the MEM to our
2461 recursive call and copy the flags. While we are here, handle this
2462 case more efficiently. */
2463 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
2464 if (new != XEXP (x, 0))
2466 new = gen_rtx_MEM (GET_MODE (x), new);
2467 new->volatil = x->volatil;
2468 new->unchanging = x->unchanging;
2469 new->in_struct = x->in_struct;
2485 /* Process each of our operands recursively. If any have changed, make a
2487 fmt = GET_RTX_FORMAT (code);
2488 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2492 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2493 if (new != XEXP (x, i) && ! copied)
2495 rtx new_x = rtx_alloc (code);
2496 bcopy ((char *) x, (char *) new_x,
2497 (sizeof (*new_x) - sizeof (new_x->fld)
2498 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2504 else if (*fmt == 'E')
2507 for (j = 0; j < XVECLEN (x, i); j++)
2509 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2510 if (new != XVECEXP (x, i, j) && ! copied_vec)
2512 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2516 rtx new_x = rtx_alloc (code);
2517 bcopy ((char *) x, (char *) new_x,
2518 (sizeof (*new_x) - sizeof (new_x->fld)
2519 + (sizeof (new_x->fld[0])
2520 * GET_RTX_LENGTH (code))));
2524 XVEC (x, i) = new_v;
2527 XVECEXP (x, i, j) = new;
2535 /* Scan rtx X for modifications of elimination target registers. Update
2536 the table of eliminables to reflect the changed state. MEM_MODE is
2537 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2540 elimination_effects (x, mem_mode)
2542 enum machine_mode mem_mode;
2545 enum rtx_code code = GET_CODE (x);
2546 struct elim_table *ep;
2572 /* First handle the case where we encounter a bare register that
2573 is eliminable. Replace it with a PLUS. */
2574 if (regno < FIRST_PSEUDO_REGISTER)
2576 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2578 if (ep->from_rtx == x && ep->can_eliminate)
2581 ep->ref_outside_mem = 1;
2586 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2587 && reg_equiv_constant[regno]
2588 && ! CONSTANT_P (reg_equiv_constant[regno]))
2589 elimination_effects (reg_equiv_constant[regno], mem_mode);
2596 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2597 if (ep->to_rtx == XEXP (x, 0))
2599 int size = GET_MODE_SIZE (mem_mode);
2601 /* If more bytes than MEM_MODE are pushed, account for them. */
2602 #ifdef PUSH_ROUNDING
2603 if (ep->to_rtx == stack_pointer_rtx)
2604 size = PUSH_ROUNDING (size);
2606 if (code == PRE_DEC || code == POST_DEC)
2612 /* Fall through to generic unary operation case. */
2613 case STRICT_LOW_PART:
2615 case SIGN_EXTEND: case ZERO_EXTEND:
2616 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2617 case FLOAT: case FIX:
2618 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2622 elimination_effects (XEXP (x, 0), mem_mode);
2626 if (GET_CODE (SUBREG_REG (x)) == REG
2627 && (GET_MODE_SIZE (GET_MODE (x))
2628 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2629 && reg_equiv_memory_loc != 0
2630 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2633 elimination_effects (SUBREG_REG (x), mem_mode);
2637 /* If using a register that is the source of an eliminate we still
2638 think can be performed, note it cannot be performed since we don't
2639 know how this register is used. */
2640 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2641 if (ep->from_rtx == XEXP (x, 0))
2642 ep->can_eliminate = 0;
2644 elimination_effects (XEXP (x, 0), mem_mode);
2648 /* If clobbering a register that is the replacement register for an
2649 elimination we still think can be performed, note that it cannot
2650 be performed. Otherwise, we need not be concerned about it. */
2651 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2652 if (ep->to_rtx == XEXP (x, 0))
2653 ep->can_eliminate = 0;
2655 elimination_effects (XEXP (x, 0), mem_mode);
2659 /* Check for setting a register that we know about. */
2660 if (GET_CODE (SET_DEST (x)) == REG)
2662 /* See if this is setting the replacement register for an
2665 If DEST is the hard frame pointer, we do nothing because we
2666 assume that all assignments to the frame pointer are for
2667 non-local gotos and are being done at a time when they are valid
2668 and do not disturb anything else. Some machines want to
2669 eliminate a fake argument pointer (or even a fake frame pointer)
2670 with either the real frame or the stack pointer. Assignments to
2671 the hard frame pointer must not prevent this elimination. */
2673 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2675 if (ep->to_rtx == SET_DEST (x)
2676 && SET_DEST (x) != hard_frame_pointer_rtx)
2678 /* If it is being incremented, adjust the offset. Otherwise,
2679 this elimination can't be done. */
2680 rtx src = SET_SRC (x);
2682 if (GET_CODE (src) == PLUS
2683 && XEXP (src, 0) == SET_DEST (x)
2684 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2685 ep->offset -= INTVAL (XEXP (src, 1));
2687 ep->can_eliminate = 0;
2691 elimination_effects (SET_DEST (x), 0);
2692 elimination_effects (SET_SRC (x), 0);
2696 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2699 /* Our only special processing is to pass the mode of the MEM to our
2701 elimination_effects (XEXP (x, 0), GET_MODE (x));
2708 fmt = GET_RTX_FORMAT (code);
2709 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2712 elimination_effects (XEXP (x, i), mem_mode);
2713 else if (*fmt == 'E')
2714 for (j = 0; j < XVECLEN (x, i); j++)
2715 elimination_effects (XVECEXP (x, i, j), mem_mode);
2719 /* Descend through rtx X and verify that no references to eliminable registers
2720 remain. If any do remain, mark the involved register as not
2723 check_eliminable_occurrences (x)
2733 code = GET_CODE (x);
2735 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2737 struct elim_table *ep;
2739 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2740 if (ep->from_rtx == x && ep->can_eliminate)
2741 ep->can_eliminate = 0;
2745 fmt = GET_RTX_FORMAT (code);
2746 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2749 check_eliminable_occurrences (XEXP (x, i));
2750 else if (*fmt == 'E')
2753 for (j = 0; j < XVECLEN (x, i); j++)
2754 check_eliminable_occurrences (XVECEXP (x, i, j));
2759 /* Scan INSN and eliminate all eliminable registers in it.
2761 If REPLACE is nonzero, do the replacement destructively. Also
2762 delete the insn as dead it if it is setting an eliminable register.
2764 If REPLACE is zero, do all our allocations in reload_obstack.
2766 If no eliminations were done and this insn doesn't require any elimination
2767 processing (these are not identical conditions: it might be updating sp,
2768 but not referencing fp; this needs to be seen during reload_as_needed so
2769 that the offset between fp and sp can be taken into consideration), zero
2770 is returned. Otherwise, 1 is returned. */
2773 eliminate_regs_in_insn (insn, replace)
2777 int icode = recog_memoized (insn);
2778 rtx old_body = PATTERN (insn);
2779 int insn_is_asm = asm_noperands (old_body) >= 0;
2780 rtx old_set = single_set (insn);
2784 rtx substed_operand[MAX_RECOG_OPERANDS];
2785 rtx orig_operand[MAX_RECOG_OPERANDS];
2786 struct elim_table *ep;
2788 if (! insn_is_asm && icode < 0)
2790 if (GET_CODE (PATTERN (insn)) == USE
2791 || GET_CODE (PATTERN (insn)) == CLOBBER
2792 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2793 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2794 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2800 push_obstacks (&reload_obstack, &reload_obstack);
2802 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2803 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2805 /* Check for setting an eliminable register. */
2806 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2807 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2809 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2810 /* If this is setting the frame pointer register to the
2811 hardware frame pointer register and this is an elimination
2812 that will be done (tested above), this insn is really
2813 adjusting the frame pointer downward to compensate for
2814 the adjustment done before a nonlocal goto. */
2815 if (ep->from == FRAME_POINTER_REGNUM
2816 && ep->to == HARD_FRAME_POINTER_REGNUM)
2818 rtx src = SET_SRC (old_set);
2819 int offset = 0, ok = 0;
2820 rtx prev_insn, prev_set;
2822 if (src == ep->to_rtx)
2824 else if (GET_CODE (src) == PLUS
2825 && GET_CODE (XEXP (src, 0)) == CONST_INT
2826 && XEXP (src, 1) == ep->to_rtx)
2827 offset = INTVAL (XEXP (src, 0)), ok = 1;
2828 else if (GET_CODE (src) == PLUS
2829 && GET_CODE (XEXP (src, 1)) == CONST_INT
2830 && XEXP (src, 0) == ep->to_rtx)
2831 offset = INTVAL (XEXP (src, 1)), ok = 1;
2832 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
2833 && (prev_set = single_set (prev_insn)) != 0
2834 && rtx_equal_p (SET_DEST (prev_set), src))
2836 src = SET_SRC (prev_set);
2837 if (src == ep->to_rtx)
2839 else if (GET_CODE (src) == PLUS
2840 && GET_CODE (XEXP (src, 0)) == CONST_INT
2841 && XEXP (src, 1) == ep->to_rtx)
2842 offset = INTVAL (XEXP (src, 0)), ok = 1;
2843 else if (GET_CODE (src) == PLUS
2844 && GET_CODE (XEXP (src, 1)) == CONST_INT
2845 && XEXP (src, 0) == ep->to_rtx)
2846 offset = INTVAL (XEXP (src, 1)), ok = 1;
2854 = plus_constant (ep->to_rtx, offset - ep->offset);
2856 /* First see if this insn remains valid when we
2857 make the change. If not, keep the INSN_CODE
2858 the same and let reload fit it up. */
2859 validate_change (insn, &SET_SRC (old_set), src, 1);
2860 validate_change (insn, &SET_DEST (old_set),
2862 if (! apply_change_group ())
2864 SET_SRC (old_set) = src;
2865 SET_DEST (old_set) = ep->to_rtx;
2875 /* In this case this insn isn't serving a useful purpose. We
2876 will delete it in reload_as_needed once we know that this
2877 elimination is, in fact, being done.
2879 If REPLACE isn't set, we can't delete this insn, but needn't
2880 process it since it won't be used unless something changes. */
2883 delete_dead_insn (insn);
2890 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
2891 in the insn is the negative of the offset in FROM. Substitute
2892 (set (reg) (reg to)) for the insn and change its code.
2894 We have to do this here, rather than in eliminate_regs, so that we can
2895 change the insn code. */
2897 if (GET_CODE (SET_SRC (old_set)) == PLUS
2898 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
2899 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT)
2900 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2902 if (ep->from_rtx == XEXP (SET_SRC (old_set), 0)
2903 && ep->can_eliminate)
2905 /* We must stop at the first elimination that will be used.
2906 If this one would replace the PLUS with a REG, do it
2907 now. Otherwise, quit the loop and let eliminate_regs
2908 do its normal replacement. */
2909 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_set), 1)))
2911 /* We assume here that we don't need a PARALLEL of
2912 any CLOBBERs for this assignment. There's not
2913 much we can do if we do need it. */
2914 PATTERN (insn) = gen_rtx_SET (VOIDmode,
2917 INSN_CODE (insn) = -1;
2926 /* Determine the effects of this insn on elimination offsets. */
2927 elimination_effects (old_body, 0);
2929 /* Eliminate all eliminable registers occurring in operands that
2930 can be handled by reload. */
2931 extract_insn (insn);
2933 for (i = 0; i < recog_data.n_operands; i++)
2935 orig_operand[i] = recog_data.operand[i];
2936 substed_operand[i] = recog_data.operand[i];
2938 /* For an asm statement, every operand is eliminable. */
2939 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
2941 /* Check for setting a register that we know about. */
2942 if (recog_data.operand_type[i] != OP_IN
2943 && GET_CODE (orig_operand[i]) == REG)
2945 /* If we are assigning to a register that can be eliminated, it
2946 must be as part of a PARALLEL, since the code above handles
2947 single SETs. We must indicate that we can no longer
2948 eliminate this reg. */
2949 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2951 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
2952 ep->can_eliminate = 0;
2955 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
2956 replace ? insn : NULL_RTX);
2957 if (substed_operand[i] != orig_operand[i])
2958 val = any_changes = 1;
2959 /* Terminate the search in check_eliminable_occurrences at
2961 *recog_data.operand_loc[i] = 0;
2963 /* If an output operand changed from a REG to a MEM and INSN is an
2964 insn, write a CLOBBER insn. */
2965 if (recog_data.operand_type[i] != OP_IN
2966 && GET_CODE (orig_operand[i]) == REG
2967 && GET_CODE (substed_operand[i]) == MEM
2969 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
2974 for (i = 0; i < recog_data.n_dups; i++)
2975 *recog_data.dup_loc[i]
2976 = *recog_data.operand_loc[(int)recog_data.dup_num[i]];
2978 /* If any eliminable remain, they aren't eliminable anymore. */
2979 check_eliminable_occurrences (old_body);
2981 /* Substitute the operands; the new values are in the substed_operand
2983 for (i = 0; i < recog_data.n_operands; i++)
2984 *recog_data.operand_loc[i] = substed_operand[i];
2985 for (i = 0; i < recog_data.n_dups; i++)
2986 *recog_data.dup_loc[i] = substed_operand[(int)recog_data.dup_num[i]];
2988 /* If we are replacing a body that was a (set X (plus Y Z)), try to
2989 re-recognize the insn. We do this in case we had a simple addition
2990 but now can do this as a load-address. This saves an insn in this
2992 If re-recognition fails, the old insn code number will still be used,
2993 and some register operands may have changed into PLUS expressions.
2994 These will be handled by find_reloads by loading them into a register
2999 /* If we aren't replacing things permanently and we changed something,
3000 make another copy to ensure that all the RTL is new. Otherwise
3001 things can go wrong if find_reload swaps commutative operands
3002 and one is inside RTL that has been copied while the other is not. */
3003 new_body = old_body;
3006 new_body = copy_insn (old_body);
3007 if (REG_NOTES (insn))
3008 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3010 PATTERN (insn) = new_body;
3012 /* If we had a move insn but now we don't, rerecognize it. This will
3013 cause spurious re-recognition if the old move had a PARALLEL since
3014 the new one still will, but we can't call single_set without
3015 having put NEW_BODY into the insn and the re-recognition won't
3016 hurt in this rare case. */
3017 /* ??? Why this huge if statement - why don't we just rerecognize the
3021 && ((GET_CODE (SET_SRC (old_set)) == REG
3022 && (GET_CODE (new_body) != SET
3023 || GET_CODE (SET_SRC (new_body)) != REG))
3024 /* If this was a load from or store to memory, compare
3025 the MEM in recog_data.operand to the one in the insn.
3026 If they are not equal, then rerecognize the insn. */
3028 && ((GET_CODE (SET_SRC (old_set)) == MEM
3029 && SET_SRC (old_set) != recog_data.operand[1])
3030 || (GET_CODE (SET_DEST (old_set)) == MEM
3031 && SET_DEST (old_set) != recog_data.operand[0])))
3032 /* If this was an add insn before, rerecognize. */
3033 || GET_CODE (SET_SRC (old_set)) == PLUS))
3035 int new_icode = recog (PATTERN (insn), insn, 0);
3037 INSN_CODE (insn) = icode;
3041 /* Restore the old body. If there were any changes to it, we made a copy
3042 of it while the changes were still in place, so we'll correctly return
3043 a modified insn below. */
3046 /* Restore the old body. */
3047 for (i = 0; i < recog_data.n_operands; i++)
3048 *recog_data.operand_loc[i] = orig_operand[i];
3049 for (i = 0; i < recog_data.n_dups; i++)
3050 *recog_data.dup_loc[i] = orig_operand[(int)recog_data.dup_num[i]];
3053 /* Update all elimination pairs to reflect the status after the current
3054 insn. The changes we make were determined by the earlier call to
3055 elimination_effects.
3057 We also detect a cases where register elimination cannot be done,
3058 namely, if a register would be both changed and referenced outside a MEM
3059 in the resulting insn since such an insn is often undefined and, even if
3060 not, we cannot know what meaning will be given to it. Note that it is
3061 valid to have a register used in an address in an insn that changes it
3062 (presumably with a pre- or post-increment or decrement).
3064 If anything changes, return nonzero. */
3066 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3068 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3069 ep->can_eliminate = 0;
3071 ep->ref_outside_mem = 0;
3073 if (ep->previous_offset != ep->offset)
3078 /* If we changed something, perform elimination in REG_NOTES. This is
3079 needed even when REPLACE is zero because a REG_DEAD note might refer
3080 to a register that we eliminate and could cause a different number
3081 of spill registers to be needed in the final reload pass than in
3083 if (val && REG_NOTES (insn) != 0)
3084 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3092 /* Loop through all elimination pairs.
3093 Recalculate the number not at initial offset.
3095 Compute the maximum offset (minimum offset if the stack does not
3096 grow downward) for each elimination pair. */
3099 update_eliminable_offsets ()
3101 struct elim_table *ep;
3103 num_not_at_initial_offset = 0;
3104 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3106 ep->previous_offset = ep->offset;
3107 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3108 num_not_at_initial_offset++;
3112 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3113 replacement we currently believe is valid, mark it as not eliminable if X
3114 modifies DEST in any way other than by adding a constant integer to it.
3116 If DEST is the frame pointer, we do nothing because we assume that
3117 all assignments to the hard frame pointer are nonlocal gotos and are being
3118 done at a time when they are valid and do not disturb anything else.
3119 Some machines want to eliminate a fake argument pointer with either the
3120 frame or stack pointer. Assignments to the hard frame pointer must not
3121 prevent this elimination.
3123 Called via note_stores from reload before starting its passes to scan
3124 the insns of the function. */
3127 mark_not_eliminable (dest, x, data)
3130 void *data ATTRIBUTE_UNUSED;
3132 register unsigned int i;
3134 /* A SUBREG of a hard register here is just changing its mode. We should
3135 not see a SUBREG of an eliminable hard register, but check just in
3137 if (GET_CODE (dest) == SUBREG)
3138 dest = SUBREG_REG (dest);
3140 if (dest == hard_frame_pointer_rtx)
3143 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3144 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3145 && (GET_CODE (x) != SET
3146 || GET_CODE (SET_SRC (x)) != PLUS
3147 || XEXP (SET_SRC (x), 0) != dest
3148 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3150 reg_eliminate[i].can_eliminate_previous
3151 = reg_eliminate[i].can_eliminate = 0;
3156 /* Verify that the initial elimination offsets did not change since the
3157 last call to set_initial_elim_offsets. This is used to catch cases
3158 where something illegal happened during reload_as_needed that could
3159 cause incorrect code to be generated if we did not check for it. */
3161 verify_initial_elim_offsets ()
3165 #ifdef ELIMINABLE_REGS
3166 struct elim_table *ep;
3168 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3170 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3171 if (t != ep->initial_offset)
3175 INITIAL_FRAME_POINTER_OFFSET (t);
3176 if (t != reg_eliminate[0].initial_offset)
3181 /* Reset all offsets on eliminable registers to their initial values. */
3183 set_initial_elim_offsets ()
3185 struct elim_table *ep = reg_eliminate;
3187 #ifdef ELIMINABLE_REGS
3188 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3190 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3191 ep->previous_offset = ep->offset = ep->initial_offset;
3194 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3195 ep->previous_offset = ep->offset = ep->initial_offset;
3198 num_not_at_initial_offset = 0;
3201 /* Initialize the known label offsets.
3202 Set a known offset for each forced label to be at the initial offset
3203 of each elimination. We do this because we assume that all
3204 computed jumps occur from a location where each elimination is
3205 at its initial offset.
3206 For all other labels, show that we don't know the offsets. */
3209 set_initial_label_offsets ()
3212 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
3214 for (x = forced_labels; x; x = XEXP (x, 1))
3216 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3219 /* Set all elimination offsets to the known values for the code label given
3222 set_offsets_for_label (insn)
3226 int label_nr = CODE_LABEL_NUMBER (insn);
3227 struct elim_table *ep;
3229 num_not_at_initial_offset = 0;
3230 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3232 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3233 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3234 num_not_at_initial_offset++;
3238 /* See if anything that happened changes which eliminations are valid.
3239 For example, on the Sparc, whether or not the frame pointer can
3240 be eliminated can depend on what registers have been used. We need
3241 not check some conditions again (such as flag_omit_frame_pointer)
3242 since they can't have changed. */
3245 update_eliminables (pset)
3248 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3249 int previous_frame_pointer_needed = frame_pointer_needed;
3251 struct elim_table *ep;
3253 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3254 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3255 #ifdef ELIMINABLE_REGS
3256 || ! CAN_ELIMINATE (ep->from, ep->to)
3259 ep->can_eliminate = 0;
3261 /* Look for the case where we have discovered that we can't replace
3262 register A with register B and that means that we will now be
3263 trying to replace register A with register C. This means we can
3264 no longer replace register C with register B and we need to disable
3265 such an elimination, if it exists. This occurs often with A == ap,
3266 B == sp, and C == fp. */
3268 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3270 struct elim_table *op;
3271 register int new_to = -1;
3273 if (! ep->can_eliminate && ep->can_eliminate_previous)
3275 /* Find the current elimination for ep->from, if there is a
3277 for (op = reg_eliminate;
3278 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3279 if (op->from == ep->from && op->can_eliminate)
3285 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3287 for (op = reg_eliminate;
3288 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3289 if (op->from == new_to && op->to == ep->to)
3290 op->can_eliminate = 0;
3294 /* See if any registers that we thought we could eliminate the previous
3295 time are no longer eliminable. If so, something has changed and we
3296 must spill the register. Also, recompute the number of eliminable
3297 registers and see if the frame pointer is needed; it is if there is
3298 no elimination of the frame pointer that we can perform. */
3300 frame_pointer_needed = 1;
3301 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3303 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3304 && ep->to != HARD_FRAME_POINTER_REGNUM)
3305 frame_pointer_needed = 0;
3307 if (! ep->can_eliminate && ep->can_eliminate_previous)
3309 ep->can_eliminate_previous = 0;
3310 SET_HARD_REG_BIT (*pset, ep->from);
3315 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3316 /* If we didn't need a frame pointer last time, but we do now, spill
3317 the hard frame pointer. */
3318 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3319 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3323 /* Initialize the table of registers to eliminate. */
3327 struct elim_table *ep;
3328 #ifdef ELIMINABLE_REGS
3329 struct elim_table_1 *ep1;
3333 reg_eliminate = (struct elim_table *)
3334 xcalloc(sizeof(struct elim_table), NUM_ELIMINABLE_REGS);
3336 /* Does this function require a frame pointer? */
3338 frame_pointer_needed = (! flag_omit_frame_pointer
3339 #ifdef EXIT_IGNORE_STACK
3340 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3341 and restore sp for alloca. So we can't eliminate
3342 the frame pointer in that case. At some point,
3343 we should improve this by emitting the
3344 sp-adjusting insns for this case. */
3345 || (current_function_calls_alloca
3346 && EXIT_IGNORE_STACK)
3348 || FRAME_POINTER_REQUIRED);
3352 #ifdef ELIMINABLE_REGS
3353 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3354 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3356 ep->from = ep1->from;
3358 ep->can_eliminate = ep->can_eliminate_previous
3359 = (CAN_ELIMINATE (ep->from, ep->to)
3360 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3363 reg_eliminate[0].from = reg_eliminate_1[0].from;
3364 reg_eliminate[0].to = reg_eliminate_1[0].to;
3365 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3366 = ! frame_pointer_needed;
3369 /* Count the number of eliminable registers and build the FROM and TO
3370 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3371 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3372 We depend on this. */
3373 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3375 num_eliminable += ep->can_eliminate;
3376 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3377 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3381 /* Kick all pseudos out of hard register REGNO.
3382 If DUMPFILE is nonzero, log actions taken on that file.
3384 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3385 because we found we can't eliminate some register. In the case, no pseudos
3386 are allowed to be in the register, even if they are only in a block that
3387 doesn't require spill registers, unlike the case when we are spilling this
3388 hard reg to produce another spill register.
3390 Return nonzero if any pseudos needed to be kicked out. */
3393 spill_hard_reg (regno, dumpfile, cant_eliminate)
3395 FILE *dumpfile ATTRIBUTE_UNUSED;
3402 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3403 regs_ever_live[regno] = 1;
3406 /* Spill every pseudo reg that was allocated to this reg
3407 or to something that overlaps this reg. */
3409 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3410 if (reg_renumber[i] >= 0
3411 && reg_renumber[i] <= regno
3413 + HARD_REGNO_NREGS (reg_renumber[i],
3414 PSEUDO_REGNO_MODE (i))
3416 SET_REGNO_REG_SET (&spilled_pseudos, i);
3419 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3420 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3422 ior_hard_reg_set (set1, set2)
3423 HARD_REG_SET *set1, *set2;
3425 IOR_HARD_REG_SET (*set1, *set2);
3428 /* After find_reload_regs has been run for all insn that need reloads,
3429 and/or spill_hard_regs was called, this function is used to actually
3430 spill pseudo registers and try to reallocate them. It also sets up the
3431 spill_regs array for use by choose_reload_regs. */
3434 finish_spills (global, dumpfile)
3438 struct insn_chain *chain;
3439 int something_changed = 0;
3442 /* Build the spill_regs array for the function. */
3443 /* If there are some registers still to eliminate and one of the spill regs
3444 wasn't ever used before, additional stack space may have to be
3445 allocated to store this register. Thus, we may have changed the offset
3446 between the stack and frame pointers, so mark that something has changed.
3448 One might think that we need only set VAL to 1 if this is a call-used
3449 register. However, the set of registers that must be saved by the
3450 prologue is not identical to the call-used set. For example, the
3451 register used by the call insn for the return PC is a call-used register,
3452 but must be saved by the prologue. */
3455 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3456 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3458 spill_reg_order[i] = n_spills;
3459 spill_regs[n_spills++] = i;
3460 if (num_eliminable && ! regs_ever_live[i])
3461 something_changed = 1;
3462 regs_ever_live[i] = 1;
3465 spill_reg_order[i] = -1;
3467 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3468 if (REGNO_REG_SET_P (&spilled_pseudos, i))
3470 /* Record the current hard register the pseudo is allocated to in
3471 pseudo_previous_regs so we avoid reallocating it to the same
3472 hard reg in a later pass. */
3473 if (reg_renumber[i] < 0)
3475 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3476 /* Mark it as no longer having a hard register home. */
3477 reg_renumber[i] = -1;
3478 /* We will need to scan everything again. */
3479 something_changed = 1;
3482 /* Retry global register allocation if possible. */
3485 bzero ((char *) pseudo_forbidden_regs, max_regno * sizeof (HARD_REG_SET));
3486 /* For every insn that needs reloads, set the registers used as spill
3487 regs in pseudo_forbidden_regs for every pseudo live across the
3489 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3491 EXECUTE_IF_SET_IN_REG_SET
3492 (chain->live_before, FIRST_PSEUDO_REGISTER, i,
3494 ior_hard_reg_set (pseudo_forbidden_regs + i,
3495 &chain->used_spill_regs);
3497 EXECUTE_IF_SET_IN_REG_SET
3498 (chain->live_after, FIRST_PSEUDO_REGISTER, i,
3500 ior_hard_reg_set (pseudo_forbidden_regs + i,
3501 &chain->used_spill_regs);
3505 /* Retry allocating the spilled pseudos. For each reg, merge the
3506 various reg sets that indicate which hard regs can't be used,
3507 and call retry_global_alloc.
3508 We change spill_pseudos here to only contain pseudos that did not
3509 get a new hard register. */
3510 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3511 if (reg_old_renumber[i] != reg_renumber[i])
3513 HARD_REG_SET forbidden;
3514 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3515 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3516 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3517 retry_global_alloc (i, forbidden);
3518 if (reg_renumber[i] >= 0)
3519 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3523 /* Fix up the register information in the insn chain.
3524 This involves deleting those of the spilled pseudos which did not get
3525 a new hard register home from the live_{before,after} sets. */
3526 for (chain = reload_insn_chain; chain; chain = chain->next)
3528 HARD_REG_SET used_by_pseudos;
3529 HARD_REG_SET used_by_pseudos2;
3531 AND_COMPL_REG_SET (chain->live_before, &spilled_pseudos);
3532 AND_COMPL_REG_SET (chain->live_after, &spilled_pseudos);
3534 /* Mark any unallocated hard regs as available for spills. That
3535 makes inheritance work somewhat better. */
3536 if (chain->need_reload)
3538 REG_SET_TO_HARD_REG_SET (used_by_pseudos, chain->live_before);
3539 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, chain->live_after);
3540 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3542 /* Save the old value for the sanity test below. */
3543 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3545 compute_use_by_pseudos (&used_by_pseudos, chain->live_before);
3546 compute_use_by_pseudos (&used_by_pseudos, chain->live_after);
3547 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3548 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3550 /* Make sure we only enlarge the set. */
3551 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3557 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3558 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3560 int regno = reg_renumber[i];
3561 if (reg_old_renumber[i] == regno)
3564 alter_reg (i, reg_old_renumber[i]);
3565 reg_old_renumber[i] = regno;
3569 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3571 fprintf (dumpfile, " Register %d now in %d.\n\n",
3572 i, reg_renumber[i]);
3576 return something_changed;
3579 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3580 Also mark any hard registers used to store user variables as
3581 forbidden from being used for spill registers. */
3584 scan_paradoxical_subregs (x)
3588 register const char *fmt;
3589 register enum rtx_code code = GET_CODE (x);
3595 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3596 && REG_USERVAR_P (x))
3597 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3613 if (GET_CODE (SUBREG_REG (x)) == REG
3614 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3615 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3616 = GET_MODE_SIZE (GET_MODE (x));
3623 fmt = GET_RTX_FORMAT (code);
3624 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3627 scan_paradoxical_subregs (XEXP (x, i));
3628 else if (fmt[i] == 'E')
3631 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3632 scan_paradoxical_subregs (XVECEXP (x, i, j));
3637 /* Reload pseudo-registers into hard regs around each insn as needed.
3638 Additional register load insns are output before the insn that needs it
3639 and perhaps store insns after insns that modify the reloaded pseudo reg.
3641 reg_last_reload_reg and reg_reloaded_contents keep track of
3642 which registers are already available in reload registers.
3643 We update these for the reloads that we perform,
3644 as the insns are scanned. */
3647 reload_as_needed (live_known)
3650 struct insn_chain *chain;
3651 #if defined (AUTO_INC_DEC)
3656 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
3657 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
3658 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3659 reg_has_output_reload = (char *) xmalloc (max_regno);
3660 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3662 set_initial_elim_offsets ();
3664 for (chain = reload_insn_chain; chain; chain = chain->next)
3667 rtx insn = chain->insn;
3668 rtx old_next = NEXT_INSN (insn);
3670 /* If we pass a label, copy the offsets from the label information
3671 into the current offsets of each elimination. */
3672 if (GET_CODE (insn) == CODE_LABEL)
3673 set_offsets_for_label (insn);
3675 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3677 rtx oldpat = PATTERN (insn);
3679 /* If this is a USE and CLOBBER of a MEM, ensure that any
3680 references to eliminable registers have been removed. */
3682 if ((GET_CODE (PATTERN (insn)) == USE
3683 || GET_CODE (PATTERN (insn)) == CLOBBER)
3684 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3685 XEXP (XEXP (PATTERN (insn), 0), 0)
3686 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3687 GET_MODE (XEXP (PATTERN (insn), 0)),
3690 /* If we need to do register elimination processing, do so.
3691 This might delete the insn, in which case we are done. */
3692 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3694 eliminate_regs_in_insn (insn, 1);
3695 if (GET_CODE (insn) == NOTE)
3697 update_eliminable_offsets ();
3702 /* If need_elim is nonzero but need_reload is zero, one might think
3703 that we could simply set n_reloads to 0. However, find_reloads
3704 could have done some manipulation of the insn (such as swapping
3705 commutative operands), and these manipulations are lost during
3706 the first pass for every insn that needs register elimination.
3707 So the actions of find_reloads must be redone here. */
3709 if (! chain->need_elim && ! chain->need_reload
3710 && ! chain->need_operand_change)
3712 /* First find the pseudo regs that must be reloaded for this insn.
3713 This info is returned in the tables reload_... (see reload.h).
3714 Also modify the body of INSN by substituting RELOAD
3715 rtx's for those pseudo regs. */
3718 bzero (reg_has_output_reload, max_regno);
3719 CLEAR_HARD_REG_SET (reg_is_output_reload);
3721 find_reloads (insn, 1, spill_indirect_levels, live_known,
3725 if (num_eliminable && chain->need_elim)
3726 update_eliminable_offsets ();
3730 rtx next = NEXT_INSN (insn);
3733 prev = PREV_INSN (insn);
3735 /* Now compute which reload regs to reload them into. Perhaps
3736 reusing reload regs from previous insns, or else output
3737 load insns to reload them. Maybe output store insns too.
3738 Record the choices of reload reg in reload_reg_rtx. */
3739 choose_reload_regs (chain);
3741 /* Merge any reloads that we didn't combine for fear of
3742 increasing the number of spill registers needed but now
3743 discover can be safely merged. */
3744 if (SMALL_REGISTER_CLASSES)
3745 merge_assigned_reloads (insn);
3747 /* Generate the insns to reload operands into or out of
3748 their reload regs. */
3749 emit_reload_insns (chain);
3751 /* Substitute the chosen reload regs from reload_reg_rtx
3752 into the insn's body (or perhaps into the bodies of other
3753 load and store insn that we just made for reloading
3754 and that we moved the structure into). */
3757 /* If this was an ASM, make sure that all the reload insns
3758 we have generated are valid. If not, give an error
3761 if (asm_noperands (PATTERN (insn)) >= 0)
3762 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3763 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
3764 && (recog_memoized (p) < 0
3765 || (extract_insn (p), ! constrain_operands (1))))
3767 error_for_asm (insn,
3768 "`asm' operand requires impossible reload");
3770 NOTE_SOURCE_FILE (p) = 0;
3771 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3774 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3775 is no longer validly lying around to save a future reload.
3776 Note that this does not detect pseudos that were reloaded
3777 for this insn in order to be stored in
3778 (obeying register constraints). That is correct; such reload
3779 registers ARE still valid. */
3780 note_stores (oldpat, forget_old_reloads_1, NULL);
3782 /* There may have been CLOBBER insns placed after INSN. So scan
3783 between INSN and NEXT and use them to forget old reloads. */
3784 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3785 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3786 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3789 /* Likewise for regs altered by auto-increment in this insn.
3790 REG_INC notes have been changed by reloading:
3791 find_reloads_address_1 records substitutions for them,
3792 which have been performed by subst_reloads above. */
3793 for (i = n_reloads - 1; i >= 0; i--)
3795 rtx in_reg = rld[i].in_reg;
3798 enum rtx_code code = GET_CODE (in_reg);
3799 /* PRE_INC / PRE_DEC will have the reload register ending up
3800 with the same value as the stack slot, but that doesn't
3801 hold true for POST_INC / POST_DEC. Either we have to
3802 convert the memory access to a true POST_INC / POST_DEC,
3803 or we can't use the reload register for inheritance. */
3804 if ((code == POST_INC || code == POST_DEC)
3805 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3806 REGNO (rld[i].reg_rtx))
3807 /* Make sure it is the inc/dec pseudo, and not
3808 some other (e.g. output operand) pseudo. */
3809 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3810 == REGNO (XEXP (in_reg, 0))))
3813 rtx reload_reg = rld[i].reg_rtx;
3814 enum machine_mode mode = GET_MODE (reload_reg);
3818 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3820 /* We really want to ignore REG_INC notes here, so
3821 use PATTERN (p) as argument to reg_set_p . */
3822 if (reg_set_p (reload_reg, PATTERN (p)))
3824 n = count_occurrences (PATTERN (p), reload_reg);
3829 n = validate_replace_rtx (reload_reg,
3830 gen_rtx (code, mode,
3834 /* We must also verify that the constraints
3835 are met after the replacement. */
3838 n = constrain_operands (1);
3842 /* If the constraints were not met, then
3843 undo the replacement. */
3846 validate_replace_rtx (gen_rtx (code, mode,
3858 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3860 /* Mark this as having an output reload so that the
3861 REG_INC processing code below won't invalidate
3862 the reload for inheritance. */
3863 SET_HARD_REG_BIT (reg_is_output_reload,
3864 REGNO (reload_reg));
3865 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3868 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3871 else if ((code == PRE_INC || code == PRE_DEC)
3872 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3873 REGNO (rld[i].reg_rtx))
3874 /* Make sure it is the inc/dec pseudo, and not
3875 some other (e.g. output operand) pseudo. */
3876 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3877 == REGNO (XEXP (in_reg, 0))))
3879 SET_HARD_REG_BIT (reg_is_output_reload,
3880 REGNO (rld[i].reg_rtx));
3881 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3885 /* If a pseudo that got a hard register is auto-incremented,
3886 we must purge records of copying it into pseudos without
3888 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3889 if (REG_NOTE_KIND (x) == REG_INC)
3891 /* See if this pseudo reg was reloaded in this insn.
3892 If so, its last-reload info is still valid
3893 because it is based on this insn's reload. */
3894 for (i = 0; i < n_reloads; i++)
3895 if (rld[i].out == XEXP (x, 0))
3899 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
3903 /* A reload reg's contents are unknown after a label. */
3904 if (GET_CODE (insn) == CODE_LABEL)
3905 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3907 /* Don't assume a reload reg is still good after a call insn
3908 if it is a call-used reg. */
3909 else if (GET_CODE (insn) == CALL_INSN)
3910 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
3914 free (reg_last_reload_reg);
3915 free (reg_has_output_reload);
3918 /* Discard all record of any value reloaded from X,
3919 or reloaded in X from someplace else;
3920 unless X is an output reload reg of the current insn.
3922 X may be a hard reg (the reload reg)
3923 or it may be a pseudo reg that was reloaded from. */
3926 forget_old_reloads_1 (x, ignored, data)
3928 rtx ignored ATTRIBUTE_UNUSED;
3929 void *data ATTRIBUTE_UNUSED;
3935 /* note_stores does give us subregs of hard regs. */
3936 while (GET_CODE (x) == SUBREG)
3938 offset += SUBREG_WORD (x);
3942 if (GET_CODE (x) != REG)
3945 regno = REGNO (x) + offset;
3947 if (regno >= FIRST_PSEUDO_REGISTER)
3952 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
3953 /* Storing into a spilled-reg invalidates its contents.
3954 This can happen if a block-local pseudo is allocated to that reg
3955 and it wasn't spilled because this block's total need is 0.
3956 Then some insn might have an optional reload and use this reg. */
3957 for (i = 0; i < nr; i++)
3958 /* But don't do this if the reg actually serves as an output
3959 reload reg in the current instruction. */
3961 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
3962 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
3965 /* Since value of X has changed,
3966 forget any value previously copied from it. */
3969 /* But don't forget a copy if this is the output reload
3970 that establishes the copy's validity. */
3971 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
3972 reg_last_reload_reg[regno + nr] = 0;
3975 /* The following HARD_REG_SETs indicate when each hard register is
3976 used for a reload of various parts of the current insn. */
3978 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
3979 static HARD_REG_SET reload_reg_used;
3980 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
3981 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
3982 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
3983 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
3984 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
3985 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
3986 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
3987 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
3988 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
3989 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
3990 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
3991 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
3992 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
3993 static HARD_REG_SET reload_reg_used_in_op_addr;
3994 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
3995 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
3996 /* If reg is in use for a RELOAD_FOR_INSN reload. */
3997 static HARD_REG_SET reload_reg_used_in_insn;
3998 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
3999 static HARD_REG_SET reload_reg_used_in_other_addr;
4001 /* If reg is in use as a reload reg for any sort of reload. */
4002 static HARD_REG_SET reload_reg_used_at_all;
4004 /* If reg is use as an inherited reload. We just mark the first register
4006 static HARD_REG_SET reload_reg_used_for_inherit;
4008 /* Records which hard regs are used in any way, either as explicit use or
4009 by being allocated to a pseudo during any point of the current insn. */
4010 static HARD_REG_SET reg_used_in_insn;
4012 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4013 TYPE. MODE is used to indicate how many consecutive regs are
4017 mark_reload_reg_in_use (regno, opnum, type, mode)
4020 enum reload_type type;
4021 enum machine_mode mode;
4023 int nregs = HARD_REGNO_NREGS (regno, mode);
4026 for (i = regno; i < nregs + regno; i++)
4031 SET_HARD_REG_BIT (reload_reg_used, i);
4034 case RELOAD_FOR_INPUT_ADDRESS:
4035 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4038 case RELOAD_FOR_INPADDR_ADDRESS:
4039 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4042 case RELOAD_FOR_OUTPUT_ADDRESS:
4043 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4046 case RELOAD_FOR_OUTADDR_ADDRESS:
4047 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4050 case RELOAD_FOR_OPERAND_ADDRESS:
4051 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4054 case RELOAD_FOR_OPADDR_ADDR:
4055 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4058 case RELOAD_FOR_OTHER_ADDRESS:
4059 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4062 case RELOAD_FOR_INPUT:
4063 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4066 case RELOAD_FOR_OUTPUT:
4067 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4070 case RELOAD_FOR_INSN:
4071 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4075 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4079 /* Similarly, but show REGNO is no longer in use for a reload. */
4082 clear_reload_reg_in_use (regno, opnum, type, mode)
4085 enum reload_type type;
4086 enum machine_mode mode;
4088 int nregs = HARD_REGNO_NREGS (regno, mode);
4089 int start_regno, end_regno;
4091 /* A complication is that for some reload types, inheritance might
4092 allow multiple reloads of the same types to share a reload register.
4093 We set check_opnum if we have to check only reloads with the same
4094 operand number, and check_any if we have to check all reloads. */
4095 int check_opnum = 0;
4097 HARD_REG_SET *used_in_set;
4102 used_in_set = &reload_reg_used;
4105 case RELOAD_FOR_INPUT_ADDRESS:
4106 used_in_set = &reload_reg_used_in_input_addr[opnum];
4109 case RELOAD_FOR_INPADDR_ADDRESS:
4111 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4114 case RELOAD_FOR_OUTPUT_ADDRESS:
4115 used_in_set = &reload_reg_used_in_output_addr[opnum];
4118 case RELOAD_FOR_OUTADDR_ADDRESS:
4120 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4123 case RELOAD_FOR_OPERAND_ADDRESS:
4124 used_in_set = &reload_reg_used_in_op_addr;
4127 case RELOAD_FOR_OPADDR_ADDR:
4129 used_in_set = &reload_reg_used_in_op_addr_reload;
4132 case RELOAD_FOR_OTHER_ADDRESS:
4133 used_in_set = &reload_reg_used_in_other_addr;
4137 case RELOAD_FOR_INPUT:
4138 used_in_set = &reload_reg_used_in_input[opnum];
4141 case RELOAD_FOR_OUTPUT:
4142 used_in_set = &reload_reg_used_in_output[opnum];
4145 case RELOAD_FOR_INSN:
4146 used_in_set = &reload_reg_used_in_insn;
4151 /* We resolve conflicts with remaining reloads of the same type by
4152 excluding the intervals of of reload registers by them from the
4153 interval of freed reload registers. Since we only keep track of
4154 one set of interval bounds, we might have to exclude somewhat
4155 more then what would be necessary if we used a HARD_REG_SET here.
4156 But this should only happen very infrequently, so there should
4157 be no reason to worry about it. */
4159 start_regno = regno;
4160 end_regno = regno + nregs;
4161 if (check_opnum || check_any)
4163 for (i = n_reloads - 1; i >= 0; i--)
4165 if (rld[i].when_needed == type
4166 && (check_any || rld[i].opnum == opnum)
4169 int conflict_start = true_regnum (rld[i].reg_rtx);
4172 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4174 /* If there is an overlap with the first to-be-freed register,
4175 adjust the interval start. */
4176 if (conflict_start <= start_regno && conflict_end > start_regno)
4177 start_regno = conflict_end;
4178 /* Otherwise, if there is a conflict with one of the other
4179 to-be-freed registers, adjust the interval end. */
4180 if (conflict_start > start_regno && conflict_start < end_regno)
4181 end_regno = conflict_start;
4185 for (i = start_regno; i < end_regno; i++)
4186 CLEAR_HARD_REG_BIT (*used_in_set, i);
4189 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4190 specified by OPNUM and TYPE. */
4193 reload_reg_free_p (regno, opnum, type)
4196 enum reload_type type;
4200 /* In use for a RELOAD_OTHER means it's not available for anything. */
4201 if (TEST_HARD_REG_BIT (reload_reg_used, regno))
4207 /* In use for anything means we can't use it for RELOAD_OTHER. */
4208 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4209 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4210 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4213 for (i = 0; i < reload_n_operands; i++)
4214 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4215 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4216 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4217 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4218 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4219 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4224 case RELOAD_FOR_INPUT:
4225 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4226 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4229 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4232 /* If it is used for some other input, can't use it. */
4233 for (i = 0; i < reload_n_operands; i++)
4234 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4237 /* If it is used in a later operand's address, can't use it. */
4238 for (i = opnum + 1; i < reload_n_operands; i++)
4239 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4240 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4245 case RELOAD_FOR_INPUT_ADDRESS:
4246 /* Can't use a register if it is used for an input address for this
4247 operand or used as an input in an earlier one. */
4248 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4249 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4252 for (i = 0; i < opnum; i++)
4253 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4258 case RELOAD_FOR_INPADDR_ADDRESS:
4259 /* Can't use a register if it is used for an input address
4260 for this operand or used as an input in an earlier
4262 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4265 for (i = 0; i < opnum; i++)
4266 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4271 case RELOAD_FOR_OUTPUT_ADDRESS:
4272 /* Can't use a register if it is used for an output address for this
4273 operand or used as an output in this or a later operand. */
4274 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4277 for (i = opnum; i < reload_n_operands; i++)
4278 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4283 case RELOAD_FOR_OUTADDR_ADDRESS:
4284 /* Can't use a register if it is used for an output address
4285 for this operand or used as an output in this or a
4287 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4290 for (i = opnum; i < reload_n_operands; i++)
4291 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4296 case RELOAD_FOR_OPERAND_ADDRESS:
4297 for (i = 0; i < reload_n_operands; i++)
4298 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4301 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4302 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4304 case RELOAD_FOR_OPADDR_ADDR:
4305 for (i = 0; i < reload_n_operands; i++)
4306 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4309 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4311 case RELOAD_FOR_OUTPUT:
4312 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4313 outputs, or an operand address for this or an earlier output. */
4314 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4317 for (i = 0; i < reload_n_operands; i++)
4318 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4321 for (i = 0; i <= opnum; i++)
4322 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4323 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4328 case RELOAD_FOR_INSN:
4329 for (i = 0; i < reload_n_operands; i++)
4330 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4331 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4334 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4335 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4337 case RELOAD_FOR_OTHER_ADDRESS:
4338 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4343 /* Return 1 if the value in reload reg REGNO, as used by a reload
4344 needed for the part of the insn specified by OPNUM and TYPE,
4345 is still available in REGNO at the end of the insn.
4347 We can assume that the reload reg was already tested for availability
4348 at the time it is needed, and we should not check this again,
4349 in case the reg has already been marked in use. */
4352 reload_reg_reaches_end_p (regno, opnum, type)
4355 enum reload_type type;
4362 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4363 its value must reach the end. */
4366 /* If this use is for part of the insn,
4367 its value reaches if no subsequent part uses the same register.
4368 Just like the above function, don't try to do this with lots
4371 case RELOAD_FOR_OTHER_ADDRESS:
4372 /* Here we check for everything else, since these don't conflict
4373 with anything else and everything comes later. */
4375 for (i = 0; i < reload_n_operands; i++)
4376 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4377 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4378 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4379 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4380 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4381 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4384 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4385 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4386 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4388 case RELOAD_FOR_INPUT_ADDRESS:
4389 case RELOAD_FOR_INPADDR_ADDRESS:
4390 /* Similar, except that we check only for this and subsequent inputs
4391 and the address of only subsequent inputs and we do not need
4392 to check for RELOAD_OTHER objects since they are known not to
4395 for (i = opnum; i < reload_n_operands; i++)
4396 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4399 for (i = opnum + 1; i < reload_n_operands; i++)
4400 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4401 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4404 for (i = 0; i < reload_n_operands; i++)
4405 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4406 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4407 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4410 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4413 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4414 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4416 case RELOAD_FOR_INPUT:
4417 /* Similar to input address, except we start at the next operand for
4418 both input and input address and we do not check for
4419 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4422 for (i = opnum + 1; i < reload_n_operands; i++)
4423 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4424 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4425 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4428 /* ... fall through ... */
4430 case RELOAD_FOR_OPERAND_ADDRESS:
4431 /* Check outputs and their addresses. */
4433 for (i = 0; i < reload_n_operands; i++)
4434 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4435 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4436 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4441 case RELOAD_FOR_OPADDR_ADDR:
4442 for (i = 0; i < reload_n_operands; i++)
4443 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4444 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4445 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4448 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4449 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4451 case RELOAD_FOR_INSN:
4452 /* These conflict with other outputs with RELOAD_OTHER. So
4453 we need only check for output addresses. */
4457 /* ... fall through ... */
4459 case RELOAD_FOR_OUTPUT:
4460 case RELOAD_FOR_OUTPUT_ADDRESS:
4461 case RELOAD_FOR_OUTADDR_ADDRESS:
4462 /* We already know these can't conflict with a later output. So the
4463 only thing to check are later output addresses. */
4464 for (i = opnum + 1; i < reload_n_operands; i++)
4465 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4466 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4475 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4478 This function uses the same algorithm as reload_reg_free_p above. */
4481 reloads_conflict (r1, r2)
4484 enum reload_type r1_type = rld[r1].when_needed;
4485 enum reload_type r2_type = rld[r2].when_needed;
4486 int r1_opnum = rld[r1].opnum;
4487 int r2_opnum = rld[r2].opnum;
4489 /* RELOAD_OTHER conflicts with everything. */
4490 if (r2_type == RELOAD_OTHER)
4493 /* Otherwise, check conflicts differently for each type. */
4497 case RELOAD_FOR_INPUT:
4498 return (r2_type == RELOAD_FOR_INSN
4499 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4500 || r2_type == RELOAD_FOR_OPADDR_ADDR
4501 || r2_type == RELOAD_FOR_INPUT
4502 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4503 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4504 && r2_opnum > r1_opnum));
4506 case RELOAD_FOR_INPUT_ADDRESS:
4507 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4508 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4510 case RELOAD_FOR_INPADDR_ADDRESS:
4511 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4512 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4514 case RELOAD_FOR_OUTPUT_ADDRESS:
4515 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4516 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4518 case RELOAD_FOR_OUTADDR_ADDRESS:
4519 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4520 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4522 case RELOAD_FOR_OPERAND_ADDRESS:
4523 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4524 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4526 case RELOAD_FOR_OPADDR_ADDR:
4527 return (r2_type == RELOAD_FOR_INPUT
4528 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4530 case RELOAD_FOR_OUTPUT:
4531 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4532 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4533 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4534 && r2_opnum <= r1_opnum));
4536 case RELOAD_FOR_INSN:
4537 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4538 || r2_type == RELOAD_FOR_INSN
4539 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4541 case RELOAD_FOR_OTHER_ADDRESS:
4542 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4552 /* Indexed by reload number, 1 if incoming value
4553 inherited from previous insns. */
4554 char reload_inherited[MAX_RELOADS];
4556 /* For an inherited reload, this is the insn the reload was inherited from,
4557 if we know it. Otherwise, this is 0. */
4558 rtx reload_inheritance_insn[MAX_RELOADS];
4560 /* If non-zero, this is a place to get the value of the reload,
4561 rather than using reload_in. */
4562 rtx reload_override_in[MAX_RELOADS];
4564 /* For each reload, the hard register number of the register used,
4565 or -1 if we did not need a register for this reload. */
4566 int reload_spill_index[MAX_RELOADS];
4568 /* Return 1 if the value in reload reg REGNO, as used by a reload
4569 needed for the part of the insn specified by OPNUM and TYPE,
4570 may be used to load VALUE into it.
4572 Other read-only reloads with the same value do not conflict
4573 unless OUT is non-zero and these other reloads have to live while
4574 output reloads live.
4575 If OUT is CONST0_RTX, this is a special case: it means that the
4576 test should not be for using register REGNO as reload register, but
4577 for copying from register REGNO into the reload register.
4579 RELOADNUM is the number of the reload we want to load this value for;
4580 a reload does not conflict with itself.
4582 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4583 reloads that load an address for the very reload we are considering.
4585 The caller has to make sure that there is no conflict with the return
4588 reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum,
4589 ignore_address_reloads)
4592 enum reload_type type;
4595 int ignore_address_reloads;
4598 /* Set if we see an input reload that must not share its reload register
4599 with any new earlyclobber, but might otherwise share the reload
4600 register with an output or input-output reload. */
4601 int check_earlyclobber = 0;
4605 /* ??? reload_reg_used is abused to hold the registers that are not
4606 available as spill registers, including hard registers that are
4607 earlyclobbered in asms. As a temporary measure, reject anything
4608 in reload_reg_used. */
4609 if (TEST_HARD_REG_BIT (reload_reg_used, regno))
4612 if (out == const0_rtx)
4618 /* We use some pseudo 'time' value to check if the lifetimes of the
4619 new register use would overlap with the one of a previous reload
4620 that is not read-only or uses a different value.
4621 The 'time' used doesn't have to be linear in any shape or form, just
4623 Some reload types use different 'buckets' for each operand.
4624 So there are MAX_RECOG_OPERANDS different time values for each
4626 We compute TIME1 as the time when the register for the prospective
4627 new reload ceases to be live, and TIME2 for each existing
4628 reload as the time when that the reload register of that reload
4630 Where there is little to be gained by exact lifetime calculations,
4631 we just make conservative assumptions, i.e. a longer lifetime;
4632 this is done in the 'default:' cases. */
4635 case RELOAD_FOR_OTHER_ADDRESS:
4636 /* RELOAD_FOR_OTHER_ADDRESS conflits with RELOAD_OTHER reloads. */
4637 time1 = copy ? 0 : 1;
4640 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4642 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4643 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4644 respectively, to the time values for these, we get distinct time
4645 values. To get distinct time values for each operand, we have to
4646 multiply opnum by at least three. We round that up to four because
4647 multiply by four is often cheaper. */
4648 case RELOAD_FOR_INPADDR_ADDRESS:
4649 time1 = opnum * 4 + 2;
4651 case RELOAD_FOR_INPUT_ADDRESS:
4652 time1 = opnum * 4 + 3;
4654 case RELOAD_FOR_INPUT:
4655 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4656 executes (inclusive). */
4657 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4659 case RELOAD_FOR_OPADDR_ADDR:
4661 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4662 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4664 case RELOAD_FOR_OPERAND_ADDRESS:
4665 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4667 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4669 case RELOAD_FOR_OUTADDR_ADDRESS:
4670 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4672 case RELOAD_FOR_OUTPUT_ADDRESS:
4673 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4676 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4679 for (i = 0; i < n_reloads; i++)
4681 rtx reg = rld[i].reg_rtx;
4682 if (reg && GET_CODE (reg) == REG
4683 && ((unsigned) regno - true_regnum (reg)
4684 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
4687 if (! rld[i].in || ! rtx_equal_p (rld[i].in, value)
4688 || rld[i].out || out)
4691 switch (rld[i].when_needed)
4693 case RELOAD_FOR_OTHER_ADDRESS:
4696 case RELOAD_FOR_INPADDR_ADDRESS:
4697 /* find_reloads makes sure that a
4698 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4699 by at most one - the first -
4700 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4701 address reload is inherited, the address address reload
4702 goes away, so we can ignore this conflict. */
4703 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4704 && ignore_address_reloads
4705 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4706 Then the address address is still needed to store
4707 back the new address. */
4708 && ! rld[reloadnum].out)
4710 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4711 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4713 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4714 && ignore_address_reloads
4715 /* Unless we are reloading an auto_inc expression. */
4716 && ! rld[reloadnum].out)
4718 time2 = rld[i].opnum * 4 + 2;
4720 case RELOAD_FOR_INPUT_ADDRESS:
4721 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4722 && ignore_address_reloads
4723 && ! rld[reloadnum].out)
4725 time2 = rld[i].opnum * 4 + 3;
4727 case RELOAD_FOR_INPUT:
4728 time2 = rld[i].opnum * 4 + 4;
4729 check_earlyclobber = 1;
4731 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4732 == MAX_RECOG_OPERAND * 4 */
4733 case RELOAD_FOR_OPADDR_ADDR:
4734 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4735 && ignore_address_reloads
4736 && ! rld[reloadnum].out)
4738 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4740 case RELOAD_FOR_OPERAND_ADDRESS:
4741 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4742 check_earlyclobber = 1;
4744 case RELOAD_FOR_INSN:
4745 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4747 case RELOAD_FOR_OUTPUT:
4748 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4749 instruction is executed. */
4750 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4752 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4753 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4755 case RELOAD_FOR_OUTADDR_ADDRESS:
4756 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4757 && ignore_address_reloads
4758 && ! rld[reloadnum].out)
4760 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4762 case RELOAD_FOR_OUTPUT_ADDRESS:
4763 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4766 /* If there is no conflict in the input part, handle this
4767 like an output reload. */
4768 if (! rld[i].in || rtx_equal_p (rld[i].in, value))
4770 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4771 /* Earlyclobbered outputs must conflict with inputs. */
4772 if (earlyclobber_operand_p (rld[i].out))
4773 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4778 /* RELOAD_OTHER might be live beyond instruction execution,
4779 but this is not obvious when we set time2 = 1. So check
4780 here if there might be a problem with the new reload
4781 clobbering the register used by the RELOAD_OTHER. */
4789 && (! rld[i].in || rld[i].out
4790 || ! rtx_equal_p (rld[i].in, value)))
4791 || (out && rld[reloadnum].out_reg
4792 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4798 /* Earlyclobbered outputs must conflict with inputs. */
4799 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4805 /* Give an error message saying we failed to find a reload for INSN,
4806 and clear out reload R. */
4808 failed_reload (insn, r)
4812 if (asm_noperands (PATTERN (insn)) < 0)
4813 /* It's the compiler's fault. */
4814 fatal_insn ("Could not find a spill register", insn);
4816 /* It's the user's fault; the operand's mode and constraint
4817 don't match. Disable this reload so we don't crash in final. */
4818 error_for_asm (insn,
4819 "`asm' operand constraint incompatible with operand size");
4823 rld[r].optional = 1;
4824 rld[r].secondary_p = 1;
4827 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
4828 for reload R. If it's valid, get an rtx for it. Return nonzero if
4831 set_reload_reg (i, r)
4835 rtx reg = spill_reg_rtx[i];
4837 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
4838 spill_reg_rtx[i] = reg
4839 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
4841 regno = true_regnum (reg);
4843 /* Detect when the reload reg can't hold the reload mode.
4844 This used to be one `if', but Sequent compiler can't handle that. */
4845 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
4847 enum machine_mode test_mode = VOIDmode;
4849 test_mode = GET_MODE (rld[r].in);
4850 /* If rld[r].in has VOIDmode, it means we will load it
4851 in whatever mode the reload reg has: to wit, rld[r].mode.
4852 We have already tested that for validity. */
4853 /* Aside from that, we need to test that the expressions
4854 to reload from or into have modes which are valid for this
4855 reload register. Otherwise the reload insns would be invalid. */
4856 if (! (rld[r].in != 0 && test_mode != VOIDmode
4857 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
4858 if (! (rld[r].out != 0
4859 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
4861 /* The reg is OK. */
4864 /* Mark as in use for this insn the reload regs we use
4866 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
4867 rld[r].when_needed, rld[r].mode);
4869 rld[r].reg_rtx = reg;
4870 reload_spill_index[r] = spill_regs[i];
4877 /* Find a spill register to use as a reload register for reload R.
4878 LAST_RELOAD is non-zero if this is the last reload for the insn being
4881 Set rld[R].reg_rtx to the register allocated.
4883 We return 1 if successful, or 0 if we couldn't find a spill reg and
4884 we didn't change anything. */
4887 allocate_reload_reg (chain, r, last_reload)
4888 struct insn_chain *chain;
4892 rtx insn = chain->insn;
4895 /* If we put this reload ahead, thinking it is a group,
4896 then insist on finding a group. Otherwise we can grab a
4897 reg that some other reload needs.
4898 (That can happen when we have a 68000 DATA_OR_FP_REG
4899 which is a group of data regs or one fp reg.)
4900 We need not be so restrictive if there are no more reloads
4903 ??? Really it would be nicer to have smarter handling
4904 for that kind of reg class, where a problem like this is normal.
4905 Perhaps those classes should be avoided for reloading
4906 by use of more alternatives. */
4908 int force_group = rld[r].nregs > 1 && ! last_reload;
4910 /* If we want a single register and haven't yet found one,
4911 take any reg in the right class and not in use.
4912 If we want a consecutive group, here is where we look for it.
4914 We use two passes so we can first look for reload regs to
4915 reuse, which are already in use for other reloads in this insn,
4916 and only then use additional registers.
4917 I think that maximizing reuse is needed to make sure we don't
4918 run out of reload regs. Suppose we have three reloads, and
4919 reloads A and B can share regs. These need two regs.
4920 Suppose A and B are given different regs.
4921 That leaves none for C. */
4922 for (pass = 0; pass < 2; pass++)
4924 /* I is the index in spill_regs.
4925 We advance it round-robin between insns to use all spill regs
4926 equally, so that inherited reloads have a chance
4927 of leapfrogging each other. */
4931 for (count = 0; count < n_spills; count++)
4933 int class = (int) rld[r].class;
4939 regnum = spill_regs[i];
4941 if ((reload_reg_free_p (regnum, rld[r].opnum,
4944 /* We check reload_reg_used to make sure we
4945 don't clobber the return register. */
4946 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
4947 && reload_reg_free_for_value_p (regnum,
4952 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
4953 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
4954 /* Look first for regs to share, then for unshared. But
4955 don't share regs used for inherited reloads; they are
4956 the ones we want to preserve. */
4958 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
4960 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
4963 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
4964 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
4965 (on 68000) got us two FP regs. If NR is 1,
4966 we would reject both of them. */
4969 /* If we need only one reg, we have already won. */
4972 /* But reject a single reg if we demand a group. */
4977 /* Otherwise check that as many consecutive regs as we need
4978 are available here. */
4981 int regno = regnum + nr - 1;
4982 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
4983 && spill_reg_order[regno] >= 0
4984 && reload_reg_free_p (regno, rld[r].opnum,
4985 rld[r].when_needed)))
4994 /* If we found something on pass 1, omit pass 2. */
4995 if (count < n_spills)
4999 /* We should have found a spill register by now. */
5000 if (count >= n_spills)
5003 /* I is the index in SPILL_REG_RTX of the reload register we are to
5004 allocate. Get an rtx for it and find its register number. */
5006 return set_reload_reg (i, r);
5009 /* Initialize all the tables needed to allocate reload registers.
5010 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5011 is the array we use to restore the reg_rtx field for every reload. */
5013 choose_reload_regs_init (chain, save_reload_reg_rtx)
5014 struct insn_chain *chain;
5015 rtx *save_reload_reg_rtx;
5019 for (i = 0; i < n_reloads; i++)
5020 rld[i].reg_rtx = save_reload_reg_rtx[i];
5022 bzero (reload_inherited, MAX_RELOADS);
5023 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5024 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5026 CLEAR_HARD_REG_SET (reload_reg_used);
5027 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5028 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5029 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5030 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5031 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5033 CLEAR_HARD_REG_SET (reg_used_in_insn);
5036 REG_SET_TO_HARD_REG_SET (tmp, chain->live_before);
5037 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5038 REG_SET_TO_HARD_REG_SET (tmp, chain->live_after);
5039 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5040 compute_use_by_pseudos (®_used_in_insn, chain->live_before);
5041 compute_use_by_pseudos (®_used_in_insn, chain->live_after);
5043 for (i = 0; i < reload_n_operands; i++)
5045 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5046 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5047 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5048 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5049 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5050 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5053 IOR_COMPL_HARD_REG_SET (reload_reg_used, chain->used_spill_regs);
5055 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5057 for (i = 0; i < n_reloads; i++)
5058 /* If we have already decided to use a certain register,
5059 don't use it in another way. */
5061 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5062 rld[i].when_needed, rld[i].mode);
5065 /* Assign hard reg targets for the pseudo-registers we must reload
5066 into hard regs for this insn.
5067 Also output the instructions to copy them in and out of the hard regs.
5069 For machines with register classes, we are responsible for
5070 finding a reload reg in the proper class. */
5073 choose_reload_regs (chain)
5074 struct insn_chain *chain;
5076 rtx insn = chain->insn;
5078 int max_group_size = 1;
5079 enum reg_class group_class = NO_REGS;
5080 int pass, win, inheritance;
5082 rtx save_reload_reg_rtx[MAX_RELOADS];
5084 /* In order to be certain of getting the registers we need,
5085 we must sort the reloads into order of increasing register class.
5086 Then our grabbing of reload registers will parallel the process
5087 that provided the reload registers.
5089 Also note whether any of the reloads wants a consecutive group of regs.
5090 If so, record the maximum size of the group desired and what
5091 register class contains all the groups needed by this insn. */
5093 for (j = 0; j < n_reloads; j++)
5095 reload_order[j] = j;
5096 reload_spill_index[j] = -1;
5098 if (rld[j].nregs > 1)
5100 max_group_size = MAX (rld[j].nregs, max_group_size);
5101 group_class = reg_class_superunion[(int)rld[j].class][(int)group_class];
5104 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5108 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5110 /* If -O, try first with inheritance, then turning it off.
5111 If not -O, don't do inheritance.
5112 Using inheritance when not optimizing leads to paradoxes
5113 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5114 because one side of the comparison might be inherited. */
5116 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5118 choose_reload_regs_init (chain, save_reload_reg_rtx);
5120 /* Process the reloads in order of preference just found.
5121 Beyond this point, subregs can be found in reload_reg_rtx.
5123 This used to look for an existing reloaded home for all
5124 of the reloads, and only then perform any new reloads.
5125 But that could lose if the reloads were done out of reg-class order
5126 because a later reload with a looser constraint might have an old
5127 home in a register needed by an earlier reload with a tighter constraint.
5129 To solve this, we make two passes over the reloads, in the order
5130 described above. In the first pass we try to inherit a reload
5131 from a previous insn. If there is a later reload that needs a
5132 class that is a proper subset of the class being processed, we must
5133 also allocate a spill register during the first pass.
5135 Then make a second pass over the reloads to allocate any reloads
5136 that haven't been given registers yet. */
5138 for (j = 0; j < n_reloads; j++)
5140 register int r = reload_order[j];
5141 rtx search_equiv = NULL_RTX;
5143 /* Ignore reloads that got marked inoperative. */
5144 if (rld[r].out == 0 && rld[r].in == 0
5145 && ! rld[r].secondary_p)
5148 /* If find_reloads chose to use reload_in or reload_out as a reload
5149 register, we don't need to chose one. Otherwise, try even if it
5150 found one since we might save an insn if we find the value lying
5152 Try also when reload_in is a pseudo without a hard reg. */
5153 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5154 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5155 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5156 && GET_CODE (rld[r].in) != MEM
5157 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5160 #if 0 /* No longer needed for correct operation.
5161 It might give better code, or might not; worth an experiment? */
5162 /* If this is an optional reload, we can't inherit from earlier insns
5163 until we are sure that any non-optional reloads have been allocated.
5164 The following code takes advantage of the fact that optional reloads
5165 are at the end of reload_order. */
5166 if (rld[r].optional != 0)
5167 for (i = 0; i < j; i++)
5168 if ((rld[reload_order[i]].out != 0
5169 || rld[reload_order[i]].in != 0
5170 || rld[reload_order[i]].secondary_p)
5171 && ! rld[reload_order[i]].optional
5172 && rld[reload_order[i]].reg_rtx == 0)
5173 allocate_reload_reg (chain, reload_order[i], 0);
5176 /* First see if this pseudo is already available as reloaded
5177 for a previous insn. We cannot try to inherit for reloads
5178 that are smaller than the maximum number of registers needed
5179 for groups unless the register we would allocate cannot be used
5182 We could check here to see if this is a secondary reload for
5183 an object that is already in a register of the desired class.
5184 This would avoid the need for the secondary reload register.
5185 But this is complex because we can't easily determine what
5186 objects might want to be loaded via this reload. So let a
5187 register be allocated here. In `emit_reload_insns' we suppress
5188 one of the loads in the case described above. */
5193 register int regno = -1;
5194 enum machine_mode mode = VOIDmode;
5198 else if (GET_CODE (rld[r].in) == REG)
5200 regno = REGNO (rld[r].in);
5201 mode = GET_MODE (rld[r].in);
5203 else if (GET_CODE (rld[r].in_reg) == REG)
5205 regno = REGNO (rld[r].in_reg);
5206 mode = GET_MODE (rld[r].in_reg);
5208 else if (GET_CODE (rld[r].in_reg) == SUBREG
5209 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5211 word = SUBREG_WORD (rld[r].in_reg);
5212 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5213 if (regno < FIRST_PSEUDO_REGISTER)
5215 mode = GET_MODE (rld[r].in_reg);
5218 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5219 || GET_CODE (rld[r].in_reg) == PRE_DEC
5220 || GET_CODE (rld[r].in_reg) == POST_INC
5221 || GET_CODE (rld[r].in_reg) == POST_DEC)
5222 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5224 regno = REGNO (XEXP (rld[r].in_reg, 0));
5225 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5226 rld[r].out = rld[r].in;
5230 /* This won't work, since REGNO can be a pseudo reg number.
5231 Also, it takes much more hair to keep track of all the things
5232 that can invalidate an inherited reload of part of a pseudoreg. */
5233 else if (GET_CODE (rld[r].in) == SUBREG
5234 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5235 regno = REGNO (SUBREG_REG (rld[r].in)) + SUBREG_WORD (rld[r].in);
5238 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5240 enum reg_class class = rld[r].class, last_class;
5241 rtx last_reg = reg_last_reload_reg[regno];
5243 i = REGNO (last_reg) + word;
5244 last_class = REGNO_REG_CLASS (i);
5245 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5246 >= GET_MODE_SIZE (mode) + word * UNITS_PER_WORD)
5247 && reg_reloaded_contents[i] == regno
5248 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5249 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5250 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5251 /* Even if we can't use this register as a reload
5252 register, we might use it for reload_override_in,
5253 if copying it to the desired class is cheap
5255 || ((REGISTER_MOVE_COST (last_class, class)
5256 < MEMORY_MOVE_COST (mode, class, 1))
5257 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5258 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5262 #ifdef SECONDARY_MEMORY_NEEDED
5263 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5268 && (rld[r].nregs == max_group_size
5269 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5271 && reload_reg_free_for_value_p (i, rld[r].opnum,
5276 /* If a group is needed, verify that all the subsequent
5277 registers still have their values intact. */
5279 = HARD_REGNO_NREGS (i, rld[r].mode);
5282 for (k = 1; k < nr; k++)
5283 if (reg_reloaded_contents[i + k] != regno
5284 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5291 last_reg = (GET_MODE (last_reg) == mode
5292 ? last_reg : gen_rtx_REG (mode, i));
5294 /* We found a register that contains the
5295 value we need. If this register is the
5296 same as an `earlyclobber' operand of the
5297 current insn, just mark it as a place to
5298 reload from since we can't use it as the
5299 reload register itself. */
5301 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5302 if (reg_overlap_mentioned_for_reload_p
5303 (reg_last_reload_reg[regno],
5304 reload_earlyclobbers[i1]))
5307 if (i1 != n_earlyclobbers
5308 || ! (reload_reg_free_for_value_p
5309 (i, rld[r].opnum, rld[r].when_needed,
5310 rld[r].in, rld[r].out, r, 1))
5311 /* Don't use it if we'd clobber a pseudo reg. */
5312 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5314 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5315 /* Don't clobber the frame pointer. */
5316 || (i == HARD_FRAME_POINTER_REGNUM && rld[r].out)
5317 /* Don't really use the inherited spill reg
5318 if we need it wider than we've got it. */
5319 || (GET_MODE_SIZE (rld[r].mode)
5320 > GET_MODE_SIZE (mode))
5321 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5324 /* If find_reloads chose reload_out as reload
5325 register, stay with it - that leaves the
5326 inherited register for subsequent reloads. */
5327 || (rld[r].out && rld[r].reg_rtx
5328 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5330 reload_override_in[r] = last_reg;
5331 reload_inheritance_insn[r]
5332 = reg_reloaded_insn[i];
5337 /* We can use this as a reload reg. */
5338 /* Mark the register as in use for this part of
5340 mark_reload_reg_in_use (i,
5344 rld[r].reg_rtx = last_reg;
5345 reload_inherited[r] = 1;
5346 reload_inheritance_insn[r]
5347 = reg_reloaded_insn[i];
5348 reload_spill_index[r] = i;
5349 for (k = 0; k < nr; k++)
5350 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5358 /* Here's another way to see if the value is already lying around. */
5361 && ! reload_inherited[r]
5363 && (CONSTANT_P (rld[r].in)
5364 || GET_CODE (rld[r].in) == PLUS
5365 || GET_CODE (rld[r].in) == REG
5366 || GET_CODE (rld[r].in) == MEM)
5367 && (rld[r].nregs == max_group_size
5368 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5369 search_equiv = rld[r].in;
5370 /* If this is an output reload from a simple move insn, look
5371 if an equivalence for the input is available. */
5372 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5374 rtx set = single_set (insn);
5377 && rtx_equal_p (rld[r].out, SET_DEST (set))
5378 && CONSTANT_P (SET_SRC (set)))
5379 search_equiv = SET_SRC (set);
5385 = find_equiv_reg (search_equiv, insn, rld[r].class,
5386 -1, NULL_PTR, 0, rld[r].mode);
5391 if (GET_CODE (equiv) == REG)
5392 regno = REGNO (equiv);
5393 else if (GET_CODE (equiv) == SUBREG)
5395 /* This must be a SUBREG of a hard register.
5396 Make a new REG since this might be used in an
5397 address and not all machines support SUBREGs
5399 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5400 equiv = gen_rtx_REG (rld[r].mode, regno);
5406 /* If we found a spill reg, reject it unless it is free
5407 and of the desired class. */
5409 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5410 && ! reload_reg_free_for_value_p (regno, rld[r].opnum,
5414 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5418 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5421 /* We found a register that contains the value we need.
5422 If this register is the same as an `earlyclobber' operand
5423 of the current insn, just mark it as a place to reload from
5424 since we can't use it as the reload register itself. */
5427 for (i = 0; i < n_earlyclobbers; i++)
5428 if (reg_overlap_mentioned_for_reload_p (equiv,
5429 reload_earlyclobbers[i]))
5431 reload_override_in[r] = equiv;
5436 /* If the equiv register we have found is explicitly clobbered
5437 in the current insn, it depends on the reload type if we
5438 can use it, use it for reload_override_in, or not at all.
5439 In particular, we then can't use EQUIV for a
5440 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5442 if (equiv != 0 && regno_clobbered_p (regno, insn))
5444 switch (rld[r].when_needed)
5446 case RELOAD_FOR_OTHER_ADDRESS:
5447 case RELOAD_FOR_INPADDR_ADDRESS:
5448 case RELOAD_FOR_INPUT_ADDRESS:
5449 case RELOAD_FOR_OPADDR_ADDR:
5452 case RELOAD_FOR_INPUT:
5453 case RELOAD_FOR_OPERAND_ADDRESS:
5454 reload_override_in[r] = equiv;
5462 /* If we found an equivalent reg, say no code need be generated
5463 to load it, and use it as our reload reg. */
5464 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5466 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5468 rld[r].reg_rtx = equiv;
5469 reload_inherited[r] = 1;
5471 /* If reg_reloaded_valid is not set for this register,
5472 there might be a stale spill_reg_store lying around.
5473 We must clear it, since otherwise emit_reload_insns
5474 might delete the store. */
5475 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5476 spill_reg_store[regno] = NULL_RTX;
5477 /* If any of the hard registers in EQUIV are spill
5478 registers, mark them as in use for this insn. */
5479 for (k = 0; k < nr; k++)
5481 i = spill_reg_order[regno + k];
5484 mark_reload_reg_in_use (regno, rld[r].opnum,
5487 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5494 /* If we found a register to use already, or if this is an optional
5495 reload, we are done. */
5496 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5499 #if 0 /* No longer needed for correct operation. Might or might not
5500 give better code on the average. Want to experiment? */
5502 /* See if there is a later reload that has a class different from our
5503 class that intersects our class or that requires less register
5504 than our reload. If so, we must allocate a register to this
5505 reload now, since that reload might inherit a previous reload
5506 and take the only available register in our class. Don't do this
5507 for optional reloads since they will force all previous reloads
5508 to be allocated. Also don't do this for reloads that have been
5511 for (i = j + 1; i < n_reloads; i++)
5513 int s = reload_order[i];
5515 if ((rld[s].in == 0 && rld[s].out == 0
5516 && ! rld[s].secondary_p)
5520 if ((rld[s].class != rld[r].class
5521 && reg_classes_intersect_p (rld[r].class,
5523 || rld[s].nregs < rld[r].nregs)
5530 allocate_reload_reg (chain, r, j == n_reloads - 1);
5534 /* Now allocate reload registers for anything non-optional that
5535 didn't get one yet. */
5536 for (j = 0; j < n_reloads; j++)
5538 register int r = reload_order[j];
5540 /* Ignore reloads that got marked inoperative. */
5541 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5544 /* Skip reloads that already have a register allocated or are
5546 if (rld[r].reg_rtx != 0 || rld[r].optional)
5549 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5553 /* If that loop got all the way, we have won. */
5560 /* Loop around and try without any inheritance. */
5565 /* First undo everything done by the failed attempt
5566 to allocate with inheritance. */
5567 choose_reload_regs_init (chain, save_reload_reg_rtx);
5569 /* Some sanity tests to verify that the reloads found in the first
5570 pass are identical to the ones we have now. */
5571 if (chain->n_reloads != n_reloads)
5574 for (i = 0; i < n_reloads; i++)
5576 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5578 if (chain->rld[i].when_needed != rld[i].when_needed)
5580 for (j = 0; j < n_spills; j++)
5581 if (spill_regs[j] == chain->rld[i].regno)
5582 if (! set_reload_reg (j, i))
5583 failed_reload (chain->insn, i);
5587 /* If we thought we could inherit a reload, because it seemed that
5588 nothing else wanted the same reload register earlier in the insn,
5589 verify that assumption, now that all reloads have been assigned.
5590 Likewise for reloads where reload_override_in has been set. */
5592 /* If doing expensive optimizations, do one preliminary pass that doesn't
5593 cancel any inheritance, but removes reloads that have been needed only
5594 for reloads that we know can be inherited. */
5595 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5597 for (j = 0; j < n_reloads; j++)
5599 register int r = reload_order[j];
5601 if (reload_inherited[r] && rld[r].reg_rtx)
5602 check_reg = rld[r].reg_rtx;
5603 else if (reload_override_in[r]
5604 && (GET_CODE (reload_override_in[r]) == REG
5605 || GET_CODE (reload_override_in[r]) == SUBREG))
5606 check_reg = reload_override_in[r];
5609 if (! reload_reg_free_for_value_p (true_regnum (check_reg),
5613 (reload_inherited[r]
5614 ? rld[r].out : const0_rtx),
5619 reload_inherited[r] = 0;
5620 reload_override_in[r] = 0;
5622 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5623 reload_override_in, then we do not need its related
5624 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5625 likewise for other reload types.
5626 We handle this by removing a reload when its only replacement
5627 is mentioned in reload_in of the reload we are going to inherit.
5628 A special case are auto_inc expressions; even if the input is
5629 inherited, we still need the address for the output. We can
5630 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5631 If we suceeded removing some reload and we are doing a preliminary
5632 pass just to remove such reloads, make another pass, since the
5633 removal of one reload might allow us to inherit another one. */
5635 && rld[r].out != rld[r].in
5636 && remove_address_replacements (rld[r].in) && pass)
5641 /* Now that reload_override_in is known valid,
5642 actually override reload_in. */
5643 for (j = 0; j < n_reloads; j++)
5644 if (reload_override_in[j])
5645 rld[j].in = reload_override_in[j];
5647 /* If this reload won't be done because it has been cancelled or is
5648 optional and not inherited, clear reload_reg_rtx so other
5649 routines (such as subst_reloads) don't get confused. */
5650 for (j = 0; j < n_reloads; j++)
5651 if (rld[j].reg_rtx != 0
5652 && ((rld[j].optional && ! reload_inherited[j])
5653 || (rld[j].in == 0 && rld[j].out == 0
5654 && ! rld[j].secondary_p)))
5656 int regno = true_regnum (rld[j].reg_rtx);
5658 if (spill_reg_order[regno] >= 0)
5659 clear_reload_reg_in_use (regno, rld[j].opnum,
5660 rld[j].when_needed, rld[j].mode);
5664 /* Record which pseudos and which spill regs have output reloads. */
5665 for (j = 0; j < n_reloads; j++)
5667 register int r = reload_order[j];
5669 i = reload_spill_index[r];
5671 /* I is nonneg if this reload uses a register.
5672 If rld[r].reg_rtx is 0, this is an optional reload
5673 that we opted to ignore. */
5674 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5675 && rld[r].reg_rtx != 0)
5677 register int nregno = REGNO (rld[r].out_reg);
5680 if (nregno < FIRST_PSEUDO_REGISTER)
5681 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5684 reg_has_output_reload[nregno + nr] = 1;
5688 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5690 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5693 if (rld[r].when_needed != RELOAD_OTHER
5694 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5695 && rld[r].when_needed != RELOAD_FOR_INSN)
5701 /* Deallocate the reload register for reload R. This is called from
5702 remove_address_replacements. */
5704 deallocate_reload_reg (r)
5709 if (! rld[r].reg_rtx)
5711 regno = true_regnum (rld[r].reg_rtx);
5713 if (spill_reg_order[regno] >= 0)
5714 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5716 reload_spill_index[r] = -1;
5719 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5720 reloads of the same item for fear that we might not have enough reload
5721 registers. However, normally they will get the same reload register
5722 and hence actually need not be loaded twice.
5724 Here we check for the most common case of this phenomenon: when we have
5725 a number of reloads for the same object, each of which were allocated
5726 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5727 reload, and is not modified in the insn itself. If we find such,
5728 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5729 This will not increase the number of spill registers needed and will
5730 prevent redundant code. */
5733 merge_assigned_reloads (insn)
5738 /* Scan all the reloads looking for ones that only load values and
5739 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5740 assigned and not modified by INSN. */
5742 for (i = 0; i < n_reloads; i++)
5744 int conflicting_input = 0;
5745 int max_input_address_opnum = -1;
5746 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5748 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5749 || rld[i].out != 0 || rld[i].reg_rtx == 0
5750 || reg_set_p (rld[i].reg_rtx, insn))
5753 /* Look at all other reloads. Ensure that the only use of this
5754 reload_reg_rtx is in a reload that just loads the same value
5755 as we do. Note that any secondary reloads must be of the identical
5756 class since the values, modes, and result registers are the
5757 same, so we need not do anything with any secondary reloads. */
5759 for (j = 0; j < n_reloads; j++)
5761 if (i == j || rld[j].reg_rtx == 0
5762 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
5766 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5767 && rld[j].opnum > max_input_address_opnum)
5768 max_input_address_opnum = rld[j].opnum;
5770 /* If the reload regs aren't exactly the same (e.g, different modes)
5771 or if the values are different, we can't merge this reload.
5772 But if it is an input reload, we might still merge
5773 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
5775 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5776 || rld[j].out != 0 || rld[j].in == 0
5777 || ! rtx_equal_p (rld[i].in, rld[j].in))
5779 if (rld[j].when_needed != RELOAD_FOR_INPUT
5780 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
5781 || rld[i].opnum > rld[j].opnum)
5782 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
5784 conflicting_input = 1;
5785 if (min_conflicting_input_opnum > rld[j].opnum)
5786 min_conflicting_input_opnum = rld[j].opnum;
5790 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5791 we, in fact, found any matching reloads. */
5794 && max_input_address_opnum <= min_conflicting_input_opnum)
5796 for (j = 0; j < n_reloads; j++)
5797 if (i != j && rld[j].reg_rtx != 0
5798 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5799 && (! conflicting_input
5800 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5801 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
5803 rld[i].when_needed = RELOAD_OTHER;
5805 reload_spill_index[j] = -1;
5806 transfer_replacements (i, j);
5809 /* If this is now RELOAD_OTHER, look for any reloads that load
5810 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5811 if they were for inputs, RELOAD_OTHER for outputs. Note that
5812 this test is equivalent to looking for reloads for this operand
5815 if (rld[i].when_needed == RELOAD_OTHER)
5816 for (j = 0; j < n_reloads; j++)
5818 && rld[i].when_needed != RELOAD_OTHER
5819 && reg_overlap_mentioned_for_reload_p (rld[j].in,
5822 = ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
5823 || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
5824 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
5830 /* Output insns to reload values in and out of the chosen reload regs. */
5833 emit_reload_insns (chain)
5834 struct insn_chain *chain;
5836 rtx insn = chain->insn;
5839 rtx input_reload_insns[MAX_RECOG_OPERANDS];
5840 rtx other_input_address_reload_insns = 0;
5841 rtx other_input_reload_insns = 0;
5842 rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
5843 rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5844 rtx output_reload_insns[MAX_RECOG_OPERANDS];
5845 rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
5846 rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5847 rtx operand_reload_insns = 0;
5848 rtx other_operand_reload_insns = 0;
5849 rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
5850 rtx following_insn = NEXT_INSN (insn);
5851 rtx before_insn = PREV_INSN (insn);
5853 /* Values to be put in spill_reg_store are put here first. */
5854 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
5855 HARD_REG_SET reg_reloaded_died;
5857 CLEAR_HARD_REG_SET (reg_reloaded_died);
5859 for (j = 0; j < reload_n_operands; j++)
5860 input_reload_insns[j] = input_address_reload_insns[j]
5861 = inpaddr_address_reload_insns[j]
5862 = output_reload_insns[j] = output_address_reload_insns[j]
5863 = outaddr_address_reload_insns[j]
5864 = other_output_reload_insns[j] = 0;
5866 /* Now output the instructions to copy the data into and out of the
5867 reload registers. Do these in the order that the reloads were reported,
5868 since reloads of base and index registers precede reloads of operands
5869 and the operands may need the base and index registers reloaded. */
5871 for (j = 0; j < n_reloads; j++)
5874 rtx oldequiv_reg = 0;
5875 rtx this_reload_insn = 0;
5876 int expect_occurrences = 1;
5879 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
5880 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
5882 old = (rld[j].in && GET_CODE (rld[j].in) == MEM
5883 ? rld[j].in_reg : rld[j].in);
5886 /* AUTO_INC reloads need to be handled even if inherited. We got an
5887 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
5888 && (! reload_inherited[j] || (rld[j].out && ! rld[j].out_reg))
5889 && ! rtx_equal_p (rld[j].reg_rtx, old)
5890 && rld[j].reg_rtx != 0)
5892 register rtx reloadreg = rld[j].reg_rtx;
5894 enum machine_mode mode;
5897 /* Determine the mode to reload in.
5898 This is very tricky because we have three to choose from.
5899 There is the mode the insn operand wants (rld[J].inmode).
5900 There is the mode of the reload register RELOADREG.
5901 There is the intrinsic mode of the operand, which we could find
5902 by stripping some SUBREGs.
5903 It turns out that RELOADREG's mode is irrelevant:
5904 we can change that arbitrarily.
5906 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
5907 then the reload reg may not support QImode moves, so use SImode.
5908 If foo is in memory due to spilling a pseudo reg, this is safe,
5909 because the QImode value is in the least significant part of a
5910 slot big enough for a SImode. If foo is some other sort of
5911 memory reference, then it is impossible to reload this case,
5912 so previous passes had better make sure this never happens.
5914 Then consider a one-word union which has SImode and one of its
5915 members is a float, being fetched as (SUBREG:SF union:SI).
5916 We must fetch that as SFmode because we could be loading into
5917 a float-only register. In this case OLD's mode is correct.
5919 Consider an immediate integer: it has VOIDmode. Here we need
5920 to get a mode from something else.
5922 In some cases, there is a fourth mode, the operand's
5923 containing mode. If the insn specifies a containing mode for
5924 this operand, it overrides all others.
5926 I am not sure whether the algorithm here is always right,
5927 but it does the right things in those cases. */
5929 mode = GET_MODE (old);
5930 if (mode == VOIDmode)
5931 mode = rld[j].inmode;
5933 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5934 /* If we need a secondary register for this operation, see if
5935 the value is already in a register in that class. Don't
5936 do this if the secondary register will be used as a scratch
5939 if (rld[j].secondary_in_reload >= 0
5940 && rld[j].secondary_in_icode == CODE_FOR_nothing
5943 = find_equiv_reg (old, insn,
5944 rld[rld[j].secondary_in_reload].class,
5945 -1, NULL_PTR, 0, mode);
5948 /* If reloading from memory, see if there is a register
5949 that already holds the same value. If so, reload from there.
5950 We can pass 0 as the reload_reg_p argument because
5951 any other reload has either already been emitted,
5952 in which case find_equiv_reg will see the reload-insn,
5953 or has yet to be emitted, in which case it doesn't matter
5954 because we will use this equiv reg right away. */
5956 if (oldequiv == 0 && optimize
5957 && (GET_CODE (old) == MEM
5958 || (GET_CODE (old) == REG
5959 && REGNO (old) >= FIRST_PSEUDO_REGISTER
5960 && reg_renumber[REGNO (old)] < 0)))
5961 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
5962 -1, NULL_PTR, 0, mode);
5966 int regno = true_regnum (oldequiv);
5968 /* Don't use OLDEQUIV if any other reload changes it at an
5969 earlier stage of this insn or at this stage. */
5970 if (! reload_reg_free_for_value_p (regno, rld[j].opnum,
5972 rld[j].in, const0_rtx, j,
5976 /* If it is no cheaper to copy from OLDEQUIV into the
5977 reload register than it would be to move from memory,
5978 don't use it. Likewise, if we need a secondary register
5982 && ((REGNO_REG_CLASS (regno) != rld[j].class
5983 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
5985 >= MEMORY_MOVE_COST (mode, rld[j].class, 1)))
5986 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5987 || (SECONDARY_INPUT_RELOAD_CLASS (rld[j].class,
5991 #ifdef SECONDARY_MEMORY_NEEDED
5992 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6000 /* delete_output_reload is only invoked properly if old contains
6001 the original pseudo register. Since this is replaced with a
6002 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6003 find the pseudo in RELOAD_IN_REG. */
6005 && reload_override_in[j]
6006 && GET_CODE (rld[j].in_reg) == REG)
6009 old = rld[j].in_reg;
6013 else if (GET_CODE (oldequiv) == REG)
6014 oldequiv_reg = oldequiv;
6015 else if (GET_CODE (oldequiv) == SUBREG)
6016 oldequiv_reg = SUBREG_REG (oldequiv);
6018 /* If we are reloading from a register that was recently stored in
6019 with an output-reload, see if we can prove there was
6020 actually no need to store the old value in it. */
6022 if (optimize && GET_CODE (oldequiv) == REG
6023 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6024 && spill_reg_store[REGNO (oldequiv)]
6025 && GET_CODE (old) == REG
6026 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6027 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6029 delete_output_reload (insn, j, REGNO (oldequiv));
6031 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6032 then load RELOADREG from OLDEQUIV. Note that we cannot use
6033 gen_lowpart_common since it can do the wrong thing when
6034 RELOADREG has a multi-word mode. Note that RELOADREG
6035 must always be a REG here. */
6037 if (GET_MODE (reloadreg) != mode)
6038 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6039 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6040 oldequiv = SUBREG_REG (oldequiv);
6041 if (GET_MODE (oldequiv) != VOIDmode
6042 && mode != GET_MODE (oldequiv))
6043 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6045 /* Switch to the right place to emit the reload insns. */
6046 switch (rld[j].when_needed)
6049 where = &other_input_reload_insns;
6051 case RELOAD_FOR_INPUT:
6052 where = &input_reload_insns[rld[j].opnum];
6054 case RELOAD_FOR_INPUT_ADDRESS:
6055 where = &input_address_reload_insns[rld[j].opnum];
6057 case RELOAD_FOR_INPADDR_ADDRESS:
6058 where = &inpaddr_address_reload_insns[rld[j].opnum];
6060 case RELOAD_FOR_OUTPUT_ADDRESS:
6061 where = &output_address_reload_insns[rld[j].opnum];
6063 case RELOAD_FOR_OUTADDR_ADDRESS:
6064 where = &outaddr_address_reload_insns[rld[j].opnum];
6066 case RELOAD_FOR_OPERAND_ADDRESS:
6067 where = &operand_reload_insns;
6069 case RELOAD_FOR_OPADDR_ADDR:
6070 where = &other_operand_reload_insns;
6072 case RELOAD_FOR_OTHER_ADDRESS:
6073 where = &other_input_address_reload_insns;
6079 push_to_sequence (*where);
6082 /* Auto-increment addresses must be reloaded in a special way. */
6083 if (rld[j].out && ! rld[j].out_reg)
6085 /* We are not going to bother supporting the case where a
6086 incremented register can't be copied directly from
6087 OLDEQUIV since this seems highly unlikely. */
6088 if (rld[j].secondary_in_reload >= 0)
6091 if (reload_inherited[j])
6092 oldequiv = reloadreg;
6094 old = XEXP (rld[j].in_reg, 0);
6096 if (optimize && GET_CODE (oldequiv) == REG
6097 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6098 && spill_reg_store[REGNO (oldequiv)]
6099 && GET_CODE (old) == REG
6100 && (dead_or_set_p (insn,
6101 spill_reg_stored_to[REGNO (oldequiv)])
6102 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6104 delete_output_reload (insn, j, REGNO (oldequiv));
6106 /* Prevent normal processing of this reload. */
6108 /* Output a special code sequence for this case. */
6109 new_spill_reg_store[REGNO (reloadreg)]
6110 = inc_for_reload (reloadreg, oldequiv, rld[j].out,
6114 /* If we are reloading a pseudo-register that was set by the previous
6115 insn, see if we can get rid of that pseudo-register entirely
6116 by redirecting the previous insn into our reload register. */
6118 else if (optimize && GET_CODE (old) == REG
6119 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6120 && dead_or_set_p (insn, old)
6121 /* This is unsafe if some other reload
6122 uses the same reg first. */
6123 && reload_reg_free_for_value_p (REGNO (reloadreg),
6129 rtx temp = PREV_INSN (insn);
6130 while (temp && GET_CODE (temp) == NOTE)
6131 temp = PREV_INSN (temp);
6133 && GET_CODE (temp) == INSN
6134 && GET_CODE (PATTERN (temp)) == SET
6135 && SET_DEST (PATTERN (temp)) == old
6136 /* Make sure we can access insn_operand_constraint. */
6137 && asm_noperands (PATTERN (temp)) < 0
6138 /* This is unsafe if prev insn rejects our reload reg. */
6139 && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint,
6141 /* This is unsafe if operand occurs more than once in current
6142 insn. Perhaps some occurrences aren't reloaded. */
6143 && count_occurrences (PATTERN (insn), old) == 1
6144 /* Don't risk splitting a matching pair of operands. */
6145 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6147 /* Store into the reload register instead of the pseudo. */
6148 SET_DEST (PATTERN (temp)) = reloadreg;
6150 /* If the previous insn is an output reload, the source is
6151 a reload register, and its spill_reg_store entry will
6152 contain the previous destination. This is now
6154 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6155 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6157 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6158 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6161 /* If these are the only uses of the pseudo reg,
6162 pretend for GDB it lives in the reload reg we used. */
6163 if (REG_N_DEATHS (REGNO (old)) == 1
6164 && REG_N_SETS (REGNO (old)) == 1)
6166 reg_renumber[REGNO (old)] = REGNO (rld[j].reg_rtx);
6167 alter_reg (REGNO (old), -1);
6173 /* We can't do that, so output an insn to load RELOADREG. */
6177 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6178 rtx second_reload_reg = 0;
6179 enum insn_code icode;
6181 /* If we have a secondary reload, pick up the secondary register
6182 and icode, if any. If OLDEQUIV and OLD are different or
6183 if this is an in-out reload, recompute whether or not we
6184 still need a secondary register and what the icode should
6185 be. If we still need a secondary register and the class or
6186 icode is different, go back to reloading from OLD if using
6187 OLDEQUIV means that we got the wrong type of register. We
6188 cannot have different class or icode due to an in-out reload
6189 because we don't make such reloads when both the input and
6190 output need secondary reload registers. */
6192 if (rld[j].secondary_in_reload >= 0)
6194 int secondary_reload = rld[j].secondary_in_reload;
6195 rtx real_oldequiv = oldequiv;
6199 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6200 and similarly for OLD.
6201 See comments in get_secondary_reload in reload.c. */
6202 /* If it is a pseudo that cannot be replaced with its
6203 equivalent MEM, we must fall back to reload_in, which
6204 will have all the necessary substitutions registered.
6205 Likewise for a pseudo that can't be replaced with its
6206 equivalent constant.
6208 Take extra care for subregs of such pseudos. Note that
6209 we cannot use reg_equiv_mem in this case because it is
6210 not in the right mode. */
6213 if (GET_CODE (tmp) == SUBREG)
6214 tmp = SUBREG_REG (tmp);
6215 if (GET_CODE (tmp) == REG
6216 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6217 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6218 || reg_equiv_constant[REGNO (tmp)] != 0))
6220 if (! reg_equiv_mem[REGNO (tmp)]
6221 || num_not_at_initial_offset
6222 || GET_CODE (oldequiv) == SUBREG)
6223 real_oldequiv = rld[j].in;
6225 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6229 if (GET_CODE (tmp) == SUBREG)
6230 tmp = SUBREG_REG (tmp);
6231 if (GET_CODE (tmp) == REG
6232 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6233 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6234 || reg_equiv_constant[REGNO (tmp)] != 0))
6236 if (! reg_equiv_mem[REGNO (tmp)]
6237 || num_not_at_initial_offset
6238 || GET_CODE (old) == SUBREG)
6239 real_old = rld[j].in;
6241 real_old = reg_equiv_mem[REGNO (tmp)];
6244 second_reload_reg = rld[secondary_reload].reg_rtx;
6245 icode = rld[j].secondary_in_icode;
6247 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6248 || (rld[j].in != 0 && rld[j].out != 0))
6250 enum reg_class new_class
6251 = SECONDARY_INPUT_RELOAD_CLASS (rld[j].class,
6252 mode, real_oldequiv);
6254 if (new_class == NO_REGS)
6255 second_reload_reg = 0;
6258 enum insn_code new_icode;
6259 enum machine_mode new_mode;
6261 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6262 REGNO (second_reload_reg)))
6263 oldequiv = old, real_oldequiv = real_old;
6266 new_icode = reload_in_optab[(int) mode];
6267 if (new_icode != CODE_FOR_nothing
6268 && ((insn_data[(int) new_icode].operand[0].predicate
6269 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6271 || (insn_data[(int) new_icode].operand[1].predicate
6272 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6273 (real_oldequiv, mode)))))
6274 new_icode = CODE_FOR_nothing;
6276 if (new_icode == CODE_FOR_nothing)
6279 new_mode = insn_data[(int) new_icode].operand[2].mode;
6281 if (GET_MODE (second_reload_reg) != new_mode)
6283 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6285 oldequiv = old, real_oldequiv = real_old;
6288 = gen_rtx_REG (new_mode,
6289 REGNO (second_reload_reg));
6295 /* If we still need a secondary reload register, check
6296 to see if it is being used as a scratch or intermediate
6297 register and generate code appropriately. If we need
6298 a scratch register, use REAL_OLDEQUIV since the form of
6299 the insn may depend on the actual address if it is
6302 if (second_reload_reg)
6304 if (icode != CODE_FOR_nothing)
6306 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6307 second_reload_reg));
6312 /* See if we need a scratch register to load the
6313 intermediate register (a tertiary reload). */
6314 enum insn_code tertiary_icode
6315 = rld[secondary_reload].secondary_in_icode;
6317 if (tertiary_icode != CODE_FOR_nothing)
6319 rtx third_reload_reg
6320 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6322 emit_insn ((GEN_FCN (tertiary_icode)
6323 (second_reload_reg, real_oldequiv,
6324 third_reload_reg)));
6327 gen_reload (second_reload_reg, real_oldequiv,
6329 rld[j].when_needed);
6331 oldequiv = second_reload_reg;
6337 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6339 rtx real_oldequiv = oldequiv;
6341 if ((GET_CODE (oldequiv) == REG
6342 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6343 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6344 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6345 || (GET_CODE (oldequiv) == SUBREG
6346 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6347 && (REGNO (SUBREG_REG (oldequiv))
6348 >= FIRST_PSEUDO_REGISTER)
6349 && ((reg_equiv_memory_loc
6350 [REGNO (SUBREG_REG (oldequiv))] != 0)
6351 || (reg_equiv_constant
6352 [REGNO (SUBREG_REG (oldequiv))] != 0))))
6353 real_oldequiv = rld[j].in;
6354 gen_reload (reloadreg, real_oldequiv, rld[j].opnum,
6355 rld[j].when_needed);
6360 this_reload_insn = get_last_insn ();
6361 /* End this sequence. */
6362 *where = get_insns ();
6365 /* Update reload_override_in so that delete_address_reloads_1
6366 can see the actual register usage. */
6368 reload_override_in[j] = oldequiv;
6371 /* When inheriting a wider reload, we have a MEM in rld[j].in,
6372 e.g. inheriting a SImode output reload for
6373 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6374 if (optimize && reload_inherited[j] && rld[j].in
6375 && GET_CODE (rld[j].in) == MEM
6376 && GET_CODE (rld[j].in_reg) == MEM
6377 && reload_spill_index[j] >= 0
6378 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6381 = count_occurrences (PATTERN (insn), rld[j].in) == 1 ? 0 : -1;
6383 = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6386 /* If we are reloading a register that was recently stored in with an
6387 output-reload, see if we can prove there was
6388 actually no need to store the old value in it. */
6391 && (reload_inherited[j] || reload_override_in[j])
6393 && GET_CODE (rld[j].reg_rtx) == REG
6394 && spill_reg_store[REGNO (rld[j].reg_rtx)] != 0
6396 /* There doesn't seem to be any reason to restrict this to pseudos
6397 and doing so loses in the case where we are copying from a
6398 register of the wrong class. */
6399 && (REGNO (spill_reg_stored_to[REGNO (rld[j].reg_rtx)])
6400 >= FIRST_PSEUDO_REGISTER)
6402 /* The insn might have already some references to stackslots
6403 replaced by MEMs, while reload_out_reg still names the
6405 && (dead_or_set_p (insn,
6406 spill_reg_stored_to[REGNO (rld[j].reg_rtx)])
6407 || rtx_equal_p (spill_reg_stored_to[REGNO (rld[j].reg_rtx)],
6409 delete_output_reload (insn, j, REGNO (rld[j].reg_rtx));
6411 /* Input-reloading is done. Now do output-reloading,
6412 storing the value from the reload-register after the main insn
6413 if rld[j].out is nonzero.
6415 ??? At some point we need to support handling output reloads of
6416 JUMP_INSNs or insns that set cc0. */
6418 /* If this is an output reload that stores something that is
6419 not loaded in this same reload, see if we can eliminate a previous
6422 rtx pseudo = rld[j].out_reg;
6425 && GET_CODE (pseudo) == REG
6426 && ! rtx_equal_p (rld[j].in_reg, pseudo)
6427 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6428 && reg_last_reload_reg[REGNO (pseudo)])
6430 int pseudo_no = REGNO (pseudo);
6431 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6433 /* We don't need to test full validity of last_regno for
6434 inherit here; we only want to know if the store actually
6435 matches the pseudo. */
6436 if (reg_reloaded_contents[last_regno] == pseudo_no
6437 && spill_reg_store[last_regno]
6438 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6439 delete_output_reload (insn, j, last_regno);
6443 old = rld[j].out_reg;
6445 && rld[j].reg_rtx != old
6446 && rld[j].reg_rtx != 0)
6448 register rtx reloadreg = rld[j].reg_rtx;
6449 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6450 register rtx second_reloadreg = 0;
6453 enum machine_mode mode;
6456 /* An output operand that dies right away does need a reload,
6457 but need not be copied from it. Show the new location in the
6459 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6460 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6462 XEXP (note, 0) = rld[j].reg_rtx;
6465 /* Likewise for a SUBREG of an operand that dies. */
6466 else if (GET_CODE (old) == SUBREG
6467 && GET_CODE (SUBREG_REG (old)) == REG
6468 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6471 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6475 else if (GET_CODE (old) == SCRATCH)
6476 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6477 but we don't want to make an output reload. */
6481 /* Strip off of OLD any size-increasing SUBREGs such as
6482 (SUBREG:SI foo:QI 0). */
6484 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
6485 && (GET_MODE_SIZE (GET_MODE (old))
6486 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
6487 old = SUBREG_REG (old);
6490 /* If is a JUMP_INSN, we can't support output reloads yet. */
6491 if (GET_CODE (insn) == JUMP_INSN)
6494 if (rld[j].when_needed == RELOAD_OTHER)
6497 push_to_sequence (output_reload_insns[rld[j].opnum]);
6501 /* Determine the mode to reload in.
6502 See comments above (for input reloading). */
6504 mode = GET_MODE (old);
6505 if (mode == VOIDmode)
6507 /* VOIDmode should never happen for an output. */
6508 if (asm_noperands (PATTERN (insn)) < 0)
6509 /* It's the compiler's fault. */
6510 fatal_insn ("VOIDmode on an output", insn);
6511 error_for_asm (insn, "output operand is constant in `asm'");
6512 /* Prevent crash--use something we know is valid. */
6514 old = gen_rtx_REG (mode, REGNO (reloadreg));
6517 if (GET_MODE (reloadreg) != mode)
6518 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6520 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6522 /* If we need two reload regs, set RELOADREG to the intermediate
6523 one, since it will be stored into OLD. We might need a secondary
6524 register only for an input reload, so check again here. */
6526 if (rld[j].secondary_out_reload >= 0)
6530 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6531 && reg_equiv_mem[REGNO (old)] != 0)
6532 real_old = reg_equiv_mem[REGNO (old)];
6534 if((SECONDARY_OUTPUT_RELOAD_CLASS (rld[j].class,
6538 second_reloadreg = reloadreg;
6539 reloadreg = rld[rld[j].secondary_out_reload].reg_rtx;
6541 /* See if RELOADREG is to be used as a scratch register
6542 or as an intermediate register. */
6543 if (rld[j].secondary_out_icode != CODE_FOR_nothing)
6545 emit_insn ((GEN_FCN (rld[j].secondary_out_icode)
6546 (real_old, second_reloadreg, reloadreg)));
6551 /* See if we need both a scratch and intermediate reload
6554 int secondary_reload = rld[j].secondary_out_reload;
6555 enum insn_code tertiary_icode
6556 = rld[secondary_reload].secondary_out_icode;
6558 if (GET_MODE (reloadreg) != mode)
6559 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6561 if (tertiary_icode != CODE_FOR_nothing)
6564 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6567 /* Copy primary reload reg to secondary reload reg.
6568 (Note that these have been swapped above, then
6569 secondary reload reg to OLD using our insn. */
6571 /* If REAL_OLD is a paradoxical SUBREG, remove it
6572 and try to put the opposite SUBREG on
6574 if (GET_CODE (real_old) == SUBREG
6575 && (GET_MODE_SIZE (GET_MODE (real_old))
6576 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6577 && 0 != (tem = gen_lowpart_common
6578 (GET_MODE (SUBREG_REG (real_old)),
6580 real_old = SUBREG_REG (real_old), reloadreg = tem;
6582 gen_reload (reloadreg, second_reloadreg,
6583 rld[j].opnum, rld[j].when_needed);
6584 emit_insn ((GEN_FCN (tertiary_icode)
6585 (real_old, reloadreg, third_reloadreg)));
6590 /* Copy between the reload regs here and then to
6593 gen_reload (reloadreg, second_reloadreg,
6594 rld[j].opnum, rld[j].when_needed);
6600 /* Output the last reload insn. */
6605 /* Don't output the last reload if OLD is not the dest of
6606 INSN and is in the src and is clobbered by INSN. */
6607 if (! flag_expensive_optimizations
6608 || GET_CODE (old) != REG
6609 || !(set = single_set (insn))
6610 || rtx_equal_p (old, SET_DEST (set))
6611 || !reg_mentioned_p (old, SET_SRC (set))
6612 || !regno_clobbered_p (REGNO (old), insn))
6613 gen_reload (old, reloadreg, rld[j].opnum,
6614 rld[j].when_needed);
6617 /* Look at all insns we emitted, just to be safe. */
6618 for (p = get_insns (); p; p = NEXT_INSN (p))
6619 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
6621 rtx pat = PATTERN (p);
6623 /* If this output reload doesn't come from a spill reg,
6624 clear any memory of reloaded copies of the pseudo reg.
6625 If this output reload comes from a spill reg,
6626 reg_has_output_reload will make this do nothing. */
6627 note_stores (pat, forget_old_reloads_1, NULL);
6629 if (reg_mentioned_p (rld[j].reg_rtx, pat))
6631 rtx set = single_set (insn);
6632 if (reload_spill_index[j] < 0
6634 && SET_SRC (set) == rld[j].reg_rtx)
6636 int src = REGNO (SET_SRC (set));
6638 reload_spill_index[j] = src;
6639 SET_HARD_REG_BIT (reg_is_output_reload, src);
6640 if (find_regno_note (insn, REG_DEAD, src))
6641 SET_HARD_REG_BIT (reg_reloaded_died, src);
6643 if (REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6645 int s = rld[j].secondary_out_reload;
6646 set = single_set (p);
6647 /* If this reload copies only to the secondary reload
6648 register, the secondary reload does the actual
6650 if (s >= 0 && set == NULL_RTX)
6651 ; /* We can't tell what function the secondary reload
6652 has and where the actual store to the pseudo is
6653 made; leave new_spill_reg_store alone. */
6655 && SET_SRC (set) == rld[j].reg_rtx
6656 && SET_DEST (set) == rld[s].reg_rtx)
6658 /* Usually the next instruction will be the
6659 secondary reload insn; if we can confirm
6660 that it is, setting new_spill_reg_store to
6661 that insn will allow an extra optimization. */
6662 rtx s_reg = rld[s].reg_rtx;
6663 rtx next = NEXT_INSN (p);
6664 rld[s].out = rld[j].out;
6665 rld[s].out_reg = rld[j].out_reg;
6666 set = single_set (next);
6667 if (set && SET_SRC (set) == s_reg
6668 && ! new_spill_reg_store[REGNO (s_reg)])
6670 SET_HARD_REG_BIT (reg_is_output_reload,
6672 new_spill_reg_store[REGNO (s_reg)] = next;
6676 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = p;
6681 if (rld[j].when_needed == RELOAD_OTHER)
6683 emit_insns (other_output_reload_insns[rld[j].opnum]);
6684 other_output_reload_insns[rld[j].opnum] = get_insns ();
6687 output_reload_insns[rld[j].opnum] = get_insns ();
6693 /* Now write all the insns we made for reloads in the order expected by
6694 the allocation functions. Prior to the insn being reloaded, we write
6695 the following reloads:
6697 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6699 RELOAD_OTHER reloads.
6701 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6702 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6703 RELOAD_FOR_INPUT reload for the operand.
6705 RELOAD_FOR_OPADDR_ADDRS reloads.
6707 RELOAD_FOR_OPERAND_ADDRESS reloads.
6709 After the insn being reloaded, we write the following:
6711 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6712 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6713 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6714 reloads for the operand. The RELOAD_OTHER output reloads are
6715 output in descending order by reload number. */
6717 emit_insns_before (other_input_address_reload_insns, insn);
6718 emit_insns_before (other_input_reload_insns, insn);
6720 for (j = 0; j < reload_n_operands; j++)
6722 emit_insns_before (inpaddr_address_reload_insns[j], insn);
6723 emit_insns_before (input_address_reload_insns[j], insn);
6724 emit_insns_before (input_reload_insns[j], insn);
6727 emit_insns_before (other_operand_reload_insns, insn);
6728 emit_insns_before (operand_reload_insns, insn);
6730 for (j = 0; j < reload_n_operands; j++)
6732 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
6733 emit_insns_before (output_address_reload_insns[j], following_insn);
6734 emit_insns_before (output_reload_insns[j], following_insn);
6735 emit_insns_before (other_output_reload_insns[j], following_insn);
6738 /* Keep basic block info up to date. */
6741 if (BLOCK_HEAD (chain->block) == insn)
6742 BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
6743 if (BLOCK_END (chain->block) == insn)
6744 BLOCK_END (chain->block) = PREV_INSN (following_insn);
6747 /* For all the spill regs newly reloaded in this instruction,
6748 record what they were reloaded from, so subsequent instructions
6749 can inherit the reloads.
6751 Update spill_reg_store for the reloads of this insn.
6752 Copy the elements that were updated in the loop above. */
6754 for (j = 0; j < n_reloads; j++)
6756 register int r = reload_order[j];
6757 register int i = reload_spill_index[r];
6759 /* If this is a non-inherited input reload from a pseudo, we must
6760 clear any memory of a previous store to the same pseudo. Only do
6761 something if there will not be an output reload for the pseudo
6763 if (rld[r].in_reg != 0
6764 && ! (reload_inherited[r] || reload_override_in[r]))
6766 rtx reg = rld[r].in_reg;
6768 if (GET_CODE (reg) == SUBREG)
6769 reg = SUBREG_REG (reg);
6771 if (GET_CODE (reg) == REG
6772 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
6773 && ! reg_has_output_reload[REGNO (reg)])
6775 int nregno = REGNO (reg);
6777 if (reg_last_reload_reg[nregno])
6779 int last_regno = REGNO (reg_last_reload_reg[nregno]);
6781 if (reg_reloaded_contents[last_regno] == nregno)
6782 spill_reg_store[last_regno] = 0;
6787 /* I is nonneg if this reload used a register.
6788 If rld[r].reg_rtx is 0, this is an optional reload
6789 that we opted to ignore. */
6791 if (i >= 0 && rld[r].reg_rtx != 0)
6794 = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
6796 int part_reaches_end = 0;
6797 int all_reaches_end = 1;
6799 /* For a multi register reload, we need to check if all or part
6800 of the value lives to the end. */
6801 for (k = 0; k < nr; k++)
6803 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
6804 rld[r].when_needed))
6805 part_reaches_end = 1;
6807 all_reaches_end = 0;
6810 /* Ignore reloads that don't reach the end of the insn in
6812 if (all_reaches_end)
6814 /* First, clear out memory of what used to be in this spill reg.
6815 If consecutive registers are used, clear them all. */
6817 for (k = 0; k < nr; k++)
6818 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
6820 /* Maybe the spill reg contains a copy of reload_out. */
6822 && (GET_CODE (rld[r].out) == REG
6826 || GET_CODE (rld[r].out_reg) == REG))
6828 rtx out = (GET_CODE (rld[r].out) == REG
6832 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
6833 register int nregno = REGNO (out);
6834 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6835 : HARD_REGNO_NREGS (nregno,
6836 GET_MODE (rld[r].reg_rtx)));
6838 spill_reg_store[i] = new_spill_reg_store[i];
6839 spill_reg_stored_to[i] = out;
6840 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
6842 /* If NREGNO is a hard register, it may occupy more than
6843 one register. If it does, say what is in the
6844 rest of the registers assuming that both registers
6845 agree on how many words the object takes. If not,
6846 invalidate the subsequent registers. */
6848 if (nregno < FIRST_PSEUDO_REGISTER)
6849 for (k = 1; k < nnr; k++)
6850 reg_last_reload_reg[nregno + k]
6852 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
6853 REGNO (rld[r].reg_rtx) + k)
6856 /* Now do the inverse operation. */
6857 for (k = 0; k < nr; k++)
6859 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
6860 reg_reloaded_contents[i + k]
6861 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
6864 reg_reloaded_insn[i + k] = insn;
6865 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
6869 /* Maybe the spill reg contains a copy of reload_in. Only do
6870 something if there will not be an output reload for
6871 the register being reloaded. */
6872 else if (rld[r].out_reg == 0
6874 && ((GET_CODE (rld[r].in) == REG
6875 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
6876 && ! reg_has_output_reload[REGNO (rld[r].in)])
6877 || (GET_CODE (rld[r].in_reg) == REG
6878 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
6879 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
6881 register int nregno;
6884 if (GET_CODE (rld[r].in) == REG
6885 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
6886 nregno = REGNO (rld[r].in);
6887 else if (GET_CODE (rld[r].in_reg) == REG)
6888 nregno = REGNO (rld[r].in_reg);
6890 nregno = REGNO (XEXP (rld[r].in_reg, 0));
6892 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6893 : HARD_REGNO_NREGS (nregno,
6894 GET_MODE (rld[r].reg_rtx)));
6896 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
6898 if (nregno < FIRST_PSEUDO_REGISTER)
6899 for (k = 1; k < nnr; k++)
6900 reg_last_reload_reg[nregno + k]
6902 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
6903 REGNO (rld[r].reg_rtx) + k)
6906 /* Unless we inherited this reload, show we haven't
6907 recently done a store.
6908 Previous stores of inherited auto_inc expressions
6909 also have to be discarded. */
6910 if (! reload_inherited[r]
6911 || (rld[r].out && ! rld[r].out_reg))
6912 spill_reg_store[i] = 0;
6914 for (k = 0; k < nr; k++)
6916 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
6917 reg_reloaded_contents[i + k]
6918 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
6921 reg_reloaded_insn[i + k] = insn;
6922 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
6927 /* However, if part of the reload reaches the end, then we must
6928 invalidate the old info for the part that survives to the end. */
6929 else if (part_reaches_end)
6931 for (k = 0; k < nr; k++)
6932 if (reload_reg_reaches_end_p (i + k,
6934 rld[r].when_needed))
6935 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
6939 /* The following if-statement was #if 0'd in 1.34 (or before...).
6940 It's reenabled in 1.35 because supposedly nothing else
6941 deals with this problem. */
6943 /* If a register gets output-reloaded from a non-spill register,
6944 that invalidates any previous reloaded copy of it.
6945 But forget_old_reloads_1 won't get to see it, because
6946 it thinks only about the original insn. So invalidate it here. */
6947 if (i < 0 && rld[r].out != 0
6948 && (GET_CODE (rld[r].out) == REG
6949 || (GET_CODE (rld[r].out) == MEM
6950 && GET_CODE (rld[r].out_reg) == REG)))
6952 rtx out = (GET_CODE (rld[r].out) == REG
6953 ? rld[r].out : rld[r].out_reg);
6954 register int nregno = REGNO (out);
6955 if (nregno >= FIRST_PSEUDO_REGISTER)
6957 rtx src_reg, store_insn = NULL_RTX;
6959 reg_last_reload_reg[nregno] = 0;
6961 /* If we can find a hard register that is stored, record
6962 the storing insn so that we may delete this insn with
6963 delete_output_reload. */
6964 src_reg = rld[r].reg_rtx;
6966 /* If this is an optional reload, try to find the source reg
6967 from an input reload. */
6970 rtx set = single_set (insn);
6971 if (set && SET_DEST (set) == rld[r].out)
6975 src_reg = SET_SRC (set);
6977 for (k = 0; k < n_reloads; k++)
6979 if (rld[k].in == src_reg)
6981 src_reg = rld[k].reg_rtx;
6988 store_insn = new_spill_reg_store[REGNO (src_reg)];
6989 if (src_reg && GET_CODE (src_reg) == REG
6990 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
6992 int src_regno = REGNO (src_reg);
6993 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
6994 /* The place where to find a death note varies with
6995 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
6996 necessarily checked exactly in the code that moves
6997 notes, so just check both locations. */
6998 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7000 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7003 spill_reg_store[src_regno + nr] = store_insn;
7004 spill_reg_stored_to[src_regno + nr] = out;
7005 reg_reloaded_contents[src_regno + nr] = nregno;
7006 reg_reloaded_insn[src_regno + nr] = store_insn;
7007 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7008 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7009 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7011 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7013 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7015 reg_last_reload_reg[nregno] = src_reg;
7020 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (rld[r].out));
7022 while (num_regs-- > 0)
7023 reg_last_reload_reg[nregno + num_regs] = 0;
7027 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7030 /* Emit code to perform a reload from IN (which may be a reload register) to
7031 OUT (which may also be a reload register). IN or OUT is from operand
7032 OPNUM with reload type TYPE.
7034 Returns first insn emitted. */
7037 gen_reload (out, in, opnum, type)
7041 enum reload_type type;
7043 rtx last = get_last_insn ();
7046 /* If IN is a paradoxical SUBREG, remove it and try to put the
7047 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7048 if (GET_CODE (in) == SUBREG
7049 && (GET_MODE_SIZE (GET_MODE (in))
7050 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7051 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7052 in = SUBREG_REG (in), out = tem;
7053 else if (GET_CODE (out) == SUBREG
7054 && (GET_MODE_SIZE (GET_MODE (out))
7055 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7056 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7057 out = SUBREG_REG (out), in = tem;
7059 /* How to do this reload can get quite tricky. Normally, we are being
7060 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7061 register that didn't get a hard register. In that case we can just
7062 call emit_move_insn.
7064 We can also be asked to reload a PLUS that adds a register or a MEM to
7065 another register, constant or MEM. This can occur during frame pointer
7066 elimination and while reloading addresses. This case is handled by
7067 trying to emit a single insn to perform the add. If it is not valid,
7068 we use a two insn sequence.
7070 Finally, we could be called to handle an 'o' constraint by putting
7071 an address into a register. In that case, we first try to do this
7072 with a named pattern of "reload_load_address". If no such pattern
7073 exists, we just emit a SET insn and hope for the best (it will normally
7074 be valid on machines that use 'o').
7076 This entire process is made complex because reload will never
7077 process the insns we generate here and so we must ensure that
7078 they will fit their constraints and also by the fact that parts of
7079 IN might be being reloaded separately and replaced with spill registers.
7080 Because of this, we are, in some sense, just guessing the right approach
7081 here. The one listed above seems to work.
7083 ??? At some point, this whole thing needs to be rethought. */
7085 if (GET_CODE (in) == PLUS
7086 && (GET_CODE (XEXP (in, 0)) == REG
7087 || GET_CODE (XEXP (in, 0)) == SUBREG
7088 || GET_CODE (XEXP (in, 0)) == MEM)
7089 && (GET_CODE (XEXP (in, 1)) == REG
7090 || GET_CODE (XEXP (in, 1)) == SUBREG
7091 || CONSTANT_P (XEXP (in, 1))
7092 || GET_CODE (XEXP (in, 1)) == MEM))
7094 /* We need to compute the sum of a register or a MEM and another
7095 register, constant, or MEM, and put it into the reload
7096 register. The best possible way of doing this is if the machine
7097 has a three-operand ADD insn that accepts the required operands.
7099 The simplest approach is to try to generate such an insn and see if it
7100 is recognized and matches its constraints. If so, it can be used.
7102 It might be better not to actually emit the insn unless it is valid,
7103 but we need to pass the insn as an operand to `recog' and
7104 `extract_insn' and it is simpler to emit and then delete the insn if
7105 not valid than to dummy things up. */
7107 rtx op0, op1, tem, insn;
7110 op0 = find_replacement (&XEXP (in, 0));
7111 op1 = find_replacement (&XEXP (in, 1));
7113 /* Since constraint checking is strict, commutativity won't be
7114 checked, so we need to do that here to avoid spurious failure
7115 if the add instruction is two-address and the second operand
7116 of the add is the same as the reload reg, which is frequently
7117 the case. If the insn would be A = B + A, rearrange it so
7118 it will be A = A + B as constrain_operands expects. */
7120 if (GET_CODE (XEXP (in, 1)) == REG
7121 && REGNO (out) == REGNO (XEXP (in, 1)))
7122 tem = op0, op0 = op1, op1 = tem;
7124 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7125 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7127 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7128 code = recog_memoized (insn);
7132 extract_insn (insn);
7133 /* We want constrain operands to treat this insn strictly in
7134 its validity determination, i.e., the way it would after reload
7136 if (constrain_operands (1))
7140 delete_insns_since (last);
7142 /* If that failed, we must use a conservative two-insn sequence.
7144 Use a move to copy one operand into the reload register. Prefer
7145 to reload a constant, MEM or pseudo since the move patterns can
7146 handle an arbitrary operand. If OP1 is not a constant, MEM or
7147 pseudo and OP1 is not a valid operand for an add instruction, then
7150 After reloading one of the operands into the reload register, add
7151 the reload register to the output register.
7153 If there is another way to do this for a specific machine, a
7154 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7157 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7159 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7160 || (GET_CODE (op1) == REG
7161 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7162 || (code != CODE_FOR_nothing
7163 && ! ((*insn_data[code].operand[2].predicate)
7164 (op1, insn_data[code].operand[2].mode))))
7165 tem = op0, op0 = op1, op1 = tem;
7167 gen_reload (out, op0, opnum, type);
7169 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7170 This fixes a problem on the 32K where the stack pointer cannot
7171 be used as an operand of an add insn. */
7173 if (rtx_equal_p (op0, op1))
7176 insn = emit_insn (gen_add2_insn (out, op1));
7178 /* If that failed, copy the address register to the reload register.
7179 Then add the constant to the reload register. */
7181 code = recog_memoized (insn);
7185 extract_insn (insn);
7186 /* We want constrain operands to treat this insn strictly in
7187 its validity determination, i.e., the way it would after reload
7189 if (constrain_operands (1))
7191 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7193 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7198 delete_insns_since (last);
7200 gen_reload (out, op1, opnum, type);
7201 insn = emit_insn (gen_add2_insn (out, op0));
7202 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7205 #ifdef SECONDARY_MEMORY_NEEDED
7206 /* If we need a memory location to do the move, do it that way. */
7207 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7208 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7209 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7210 REGNO_REG_CLASS (REGNO (out)),
7213 /* Get the memory to use and rewrite both registers to its mode. */
7214 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7216 if (GET_MODE (loc) != GET_MODE (out))
7217 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7219 if (GET_MODE (loc) != GET_MODE (in))
7220 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7222 gen_reload (loc, in, opnum, type);
7223 gen_reload (out, loc, opnum, type);
7227 /* If IN is a simple operand, use gen_move_insn. */
7228 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7229 emit_insn (gen_move_insn (out, in));
7231 #ifdef HAVE_reload_load_address
7232 else if (HAVE_reload_load_address)
7233 emit_insn (gen_reload_load_address (out, in));
7236 /* Otherwise, just write (set OUT IN) and hope for the best. */
7238 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7240 /* Return the first insn emitted.
7241 We can not just return get_last_insn, because there may have
7242 been multiple instructions emitted. Also note that gen_move_insn may
7243 emit more than one insn itself, so we can not assume that there is one
7244 insn emitted per emit_insn_before call. */
7246 return last ? NEXT_INSN (last) : get_insns ();
7249 /* Delete a previously made output-reload
7250 whose result we now believe is not needed.
7251 First we double-check.
7253 INSN is the insn now being processed.
7254 LAST_RELOAD_REG is the hard register number for which we want to delete
7255 the last output reload.
7256 J is the reload-number that originally used REG. The caller has made
7257 certain that reload J doesn't use REG any longer for input. */
7260 delete_output_reload (insn, j, last_reload_reg)
7263 int last_reload_reg;
7265 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7266 rtx reg = spill_reg_stored_to[last_reload_reg];
7269 int n_inherited = 0;
7273 /* Get the raw pseudo-register referred to. */
7275 while (GET_CODE (reg) == SUBREG)
7276 reg = SUBREG_REG (reg);
7277 substed = reg_equiv_memory_loc[REGNO (reg)];
7279 /* This is unsafe if the operand occurs more often in the current
7280 insn than it is inherited. */
7281 for (k = n_reloads - 1; k >= 0; k--)
7283 rtx reg2 = rld[k].in;
7286 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7287 reg2 = rld[k].in_reg;
7289 if (rld[k].out && ! rld[k].out_reg)
7290 reg2 = XEXP (rld[k].in_reg, 0);
7292 while (GET_CODE (reg2) == SUBREG)
7293 reg2 = SUBREG_REG (reg2);
7294 if (rtx_equal_p (reg2, reg))
7296 if (reload_inherited[k] || reload_override_in[k] || k == j)
7299 reg2 = rld[k].out_reg;
7302 while (GET_CODE (reg2) == SUBREG)
7303 reg2 = XEXP (reg2, 0);
7304 if (rtx_equal_p (reg2, reg))
7311 n_occurrences = count_occurrences (PATTERN (insn), reg);
7313 n_occurrences += count_occurrences (PATTERN (insn), substed);
7314 if (n_occurrences > n_inherited)
7317 /* If the pseudo-reg we are reloading is no longer referenced
7318 anywhere between the store into it and here,
7319 and no jumps or labels intervene, then the value can get
7320 here through the reload reg alone.
7321 Otherwise, give up--return. */
7322 for (i1 = NEXT_INSN (output_reload_insn);
7323 i1 != insn; i1 = NEXT_INSN (i1))
7325 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7327 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7328 && reg_mentioned_p (reg, PATTERN (i1)))
7330 /* If this is USE in front of INSN, we only have to check that
7331 there are no more references than accounted for by inheritance. */
7332 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7334 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7335 i1 = NEXT_INSN (i1);
7337 if (n_occurrences <= n_inherited && i1 == insn)
7343 /* The caller has already checked that REG dies or is set in INSN.
7344 It has also checked that we are optimizing, and thus some inaccurancies
7345 in the debugging information are acceptable.
7346 So we could just delete output_reload_insn.
7347 But in some cases we can improve the debugging information without
7348 sacrificing optimization - maybe even improving the code:
7349 See if the pseudo reg has been completely replaced
7350 with reload regs. If so, delete the store insn
7351 and forget we had a stack slot for the pseudo. */
7352 if (rld[j].out != rld[j].in
7353 && REG_N_DEATHS (REGNO (reg)) == 1
7354 && REG_N_SETS (REGNO (reg)) == 1
7355 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7356 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7360 /* We know that it was used only between here
7361 and the beginning of the current basic block.
7362 (We also know that the last use before INSN was
7363 the output reload we are thinking of deleting, but never mind that.)
7364 Search that range; see if any ref remains. */
7365 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7367 rtx set = single_set (i2);
7369 /* Uses which just store in the pseudo don't count,
7370 since if they are the only uses, they are dead. */
7371 if (set != 0 && SET_DEST (set) == reg)
7373 if (GET_CODE (i2) == CODE_LABEL
7374 || GET_CODE (i2) == JUMP_INSN)
7376 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7377 && reg_mentioned_p (reg, PATTERN (i2)))
7379 /* Some other ref remains; just delete the output reload we
7381 delete_address_reloads (output_reload_insn, insn);
7382 PUT_CODE (output_reload_insn, NOTE);
7383 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7384 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7389 /* Delete the now-dead stores into this pseudo. */
7390 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7392 rtx set = single_set (i2);
7394 if (set != 0 && SET_DEST (set) == reg)
7396 delete_address_reloads (i2, insn);
7397 /* This might be a basic block head,
7398 thus don't use delete_insn. */
7399 PUT_CODE (i2, NOTE);
7400 NOTE_SOURCE_FILE (i2) = 0;
7401 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7403 if (GET_CODE (i2) == CODE_LABEL
7404 || GET_CODE (i2) == JUMP_INSN)
7408 /* For the debugging info,
7409 say the pseudo lives in this reload reg. */
7410 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7411 alter_reg (REGNO (reg), -1);
7413 delete_address_reloads (output_reload_insn, insn);
7414 PUT_CODE (output_reload_insn, NOTE);
7415 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7416 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7420 /* We are going to delete DEAD_INSN. Recursively delete loads of
7421 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7422 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7424 delete_address_reloads (dead_insn, current_insn)
7425 rtx dead_insn, current_insn;
7427 rtx set = single_set (dead_insn);
7428 rtx set2, dst, prev, next;
7431 rtx dst = SET_DEST (set);
7432 if (GET_CODE (dst) == MEM)
7433 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7435 /* If we deleted the store from a reloaded post_{in,de}c expression,
7436 we can delete the matching adds. */
7437 prev = PREV_INSN (dead_insn);
7438 next = NEXT_INSN (dead_insn);
7439 if (! prev || ! next)
7441 set = single_set (next);
7442 set2 = single_set (prev);
7444 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7445 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7446 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7448 dst = SET_DEST (set);
7449 if (! rtx_equal_p (dst, SET_DEST (set2))
7450 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7451 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7452 || (INTVAL (XEXP (SET_SRC (set), 1))
7453 != - INTVAL (XEXP (SET_SRC (set2), 1))))
7459 /* Subfunction of delete_address_reloads: process registers found in X. */
7461 delete_address_reloads_1 (dead_insn, x, current_insn)
7462 rtx dead_insn, x, current_insn;
7464 rtx prev, set, dst, i2;
7466 enum rtx_code code = GET_CODE (x);
7470 const char *fmt= GET_RTX_FORMAT (code);
7471 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7474 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7475 else if (fmt[i] == 'E')
7477 for (j = XVECLEN (x, i) - 1; j >=0; j--)
7478 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7485 if (spill_reg_order[REGNO (x)] < 0)
7488 /* Scan backwards for the insn that sets x. This might be a way back due
7490 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7492 code = GET_CODE (prev);
7493 if (code == CODE_LABEL || code == JUMP_INSN)
7495 if (GET_RTX_CLASS (code) != 'i')
7497 if (reg_set_p (x, PATTERN (prev)))
7499 if (reg_referenced_p (x, PATTERN (prev)))
7502 if (! prev || INSN_UID (prev) < reload_first_uid)
7504 /* Check that PREV only sets the reload register. */
7505 set = single_set (prev);
7508 dst = SET_DEST (set);
7509 if (GET_CODE (dst) != REG
7510 || ! rtx_equal_p (dst, x))
7512 if (! reg_set_p (dst, PATTERN (dead_insn)))
7514 /* Check if DST was used in a later insn -
7515 it might have been inherited. */
7516 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7518 if (GET_CODE (i2) == CODE_LABEL)
7520 if (GET_RTX_CLASS (GET_CODE (i2)) != 'i')
7522 if (reg_referenced_p (dst, PATTERN (i2)))
7524 /* If there is a reference to the register in the current insn,
7525 it might be loaded in a non-inherited reload. If no other
7526 reload uses it, that means the register is set before
7528 if (i2 == current_insn)
7530 for (j = n_reloads - 1; j >= 0; j--)
7531 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7532 || reload_override_in[j] == dst)
7534 for (j = n_reloads - 1; j >= 0; j--)
7535 if (rld[j].in && rld[j].reg_rtx == dst)
7542 if (GET_CODE (i2) == JUMP_INSN)
7544 /* If DST is still live at CURRENT_INSN, check if it is used for
7545 any reload. Note that even if CURRENT_INSN sets DST, we still
7546 have to check the reloads. */
7547 if (i2 == current_insn)
7549 for (j = n_reloads - 1; j >= 0; j--)
7550 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7551 || reload_override_in[j] == dst)
7553 /* ??? We can't finish the loop here, because dst might be
7554 allocated to a pseudo in this block if no reload in this
7555 block needs any of the clsses containing DST - see
7556 spill_hard_reg. There is no easy way to tell this, so we
7557 have to scan till the end of the basic block. */
7559 if (reg_set_p (dst, PATTERN (i2)))
7563 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7564 reg_reloaded_contents[REGNO (dst)] = -1;
7565 /* Can't use delete_insn here because PREV might be a basic block head. */
7566 PUT_CODE (prev, NOTE);
7567 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
7568 NOTE_SOURCE_FILE (prev) = 0;
7571 /* Output reload-insns to reload VALUE into RELOADREG.
7572 VALUE is an autoincrement or autodecrement RTX whose operand
7573 is a register or memory location;
7574 so reloading involves incrementing that location.
7575 IN is either identical to VALUE, or some cheaper place to reload from.
7577 INC_AMOUNT is the number to increment or decrement by (always positive).
7578 This cannot be deduced from VALUE.
7580 Return the instruction that stores into RELOADREG. */
7583 inc_for_reload (reloadreg, in, value, inc_amount)
7588 /* REG or MEM to be copied and incremented. */
7589 rtx incloc = XEXP (value, 0);
7590 /* Nonzero if increment after copying. */
7591 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7597 rtx real_in = in == value ? XEXP (in, 0) : in;
7599 /* No hard register is equivalent to this register after
7600 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7601 we could inc/dec that register as well (maybe even using it for
7602 the source), but I'm not sure it's worth worrying about. */
7603 if (GET_CODE (incloc) == REG)
7604 reg_last_reload_reg[REGNO (incloc)] = 0;
7606 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7607 inc_amount = - inc_amount;
7609 inc = GEN_INT (inc_amount);
7611 /* If this is post-increment, first copy the location to the reload reg. */
7612 if (post && real_in != reloadreg)
7613 emit_insn (gen_move_insn (reloadreg, real_in));
7617 /* See if we can directly increment INCLOC. Use a method similar to
7618 that in gen_reload. */
7620 last = get_last_insn ();
7621 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7622 gen_rtx_PLUS (GET_MODE (incloc),
7625 code = recog_memoized (add_insn);
7628 extract_insn (add_insn);
7629 if (constrain_operands (1))
7631 /* If this is a pre-increment and we have incremented the value
7632 where it lives, copy the incremented value to RELOADREG to
7633 be used as an address. */
7636 emit_insn (gen_move_insn (reloadreg, incloc));
7641 delete_insns_since (last);
7644 /* If couldn't do the increment directly, must increment in RELOADREG.
7645 The way we do this depends on whether this is pre- or post-increment.
7646 For pre-increment, copy INCLOC to the reload register, increment it
7647 there, then save back. */
7651 if (in != reloadreg)
7652 emit_insn (gen_move_insn (reloadreg, real_in));
7653 emit_insn (gen_add2_insn (reloadreg, inc));
7654 store = emit_insn (gen_move_insn (incloc, reloadreg));
7659 Because this might be a jump insn or a compare, and because RELOADREG
7660 may not be available after the insn in an input reload, we must do
7661 the incrementation before the insn being reloaded for.
7663 We have already copied IN to RELOADREG. Increment the copy in
7664 RELOADREG, save that back, then decrement RELOADREG so it has
7665 the original value. */
7667 emit_insn (gen_add2_insn (reloadreg, inc));
7668 store = emit_insn (gen_move_insn (incloc, reloadreg));
7669 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7675 /* Return 1 if we are certain that the constraint-string STRING allows
7676 the hard register REG. Return 0 if we can't be sure of this. */
7679 constraint_accepts_reg_p (string, reg)
7684 int regno = true_regnum (reg);
7687 /* Initialize for first alternative. */
7689 /* Check that each alternative contains `g' or `r'. */
7691 switch (c = *string++)
7694 /* If an alternative lacks `g' or `r', we lose. */
7697 /* If an alternative lacks `g' or `r', we lose. */
7700 /* Initialize for next alternative. */
7705 /* Any general reg wins for this alternative. */
7706 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7710 /* Any reg in specified class wins for this alternative. */
7712 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7714 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
7720 /* Return the number of places FIND appears within X, but don't count
7721 an occurrence if some SET_DEST is FIND. */
7724 count_occurrences (x, find)
7725 register rtx x, find;
7728 register enum rtx_code code;
7729 register const char *format_ptr;
7737 code = GET_CODE (x);
7752 if (GET_CODE (find) == MEM && rtx_equal_p (x, find))
7756 if (SET_DEST (x) == find)
7757 return count_occurrences (SET_SRC (x), find);
7764 format_ptr = GET_RTX_FORMAT (code);
7767 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7769 switch (*format_ptr++)
7772 count += count_occurrences (XEXP (x, i), find);
7776 if (XVEC (x, i) != NULL)
7778 for (j = 0; j < XVECLEN (x, i); j++)
7779 count += count_occurrences (XVECEXP (x, i, j), find);
7787 /* This array holds values which are equivalent to a hard register
7788 during reload_cse_regs. Each array element is an EXPR_LIST of
7789 values. Each time a hard register is set, we set the corresponding
7790 array element to the value. Each time a hard register is copied
7791 into memory, we add the memory location to the corresponding array
7792 element. We don't store values or memory addresses with side
7793 effects in this array.
7795 If the value is a CONST_INT, then the mode of the containing
7796 EXPR_LIST is the mode in which that CONST_INT was referenced.
7798 We sometimes clobber a specific entry in a list. In that case, we
7799 just set XEXP (list-entry, 0) to 0. */
7801 static rtx *reg_values;
7803 /* This is a preallocated REG rtx which we use as a temporary in
7804 reload_cse_invalidate_regno, so that we don't need to allocate a
7805 new one each time through a loop in that function. */
7807 static rtx invalidate_regno_rtx;
7809 /* Invalidate any entries in reg_values which depend on REGNO,
7810 including those for REGNO itself. This is called if REGNO is
7811 changing. If CLOBBER is true, then always forget anything we
7812 currently know about REGNO. MODE is the mode of the assignment to
7813 REGNO, which is used to determine how many hard registers are being
7814 changed. If MODE is VOIDmode, then only REGNO is being changed;
7815 this is used when invalidating call clobbered registers across a
7819 reload_cse_invalidate_regno (regno, mode, clobber)
7821 enum machine_mode mode;
7827 /* Our callers don't always go through true_regnum; we may see a
7828 pseudo-register here from a CLOBBER or the like. We probably
7829 won't ever see a pseudo-register that has a real register number,
7830 for we check anyhow for safety. */
7831 if (regno >= FIRST_PSEUDO_REGISTER)
7832 regno = reg_renumber[regno];
7836 if (mode == VOIDmode)
7837 endregno = regno + 1;
7839 endregno = regno + HARD_REGNO_NREGS (regno, mode);
7842 for (i = regno; i < endregno; i++)
7845 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
7849 for (x = reg_values[i]; x; x = XEXP (x, 1))
7851 if (XEXP (x, 0) != 0
7852 && refers_to_regno_p (regno, endregno, XEXP (x, 0), NULL_PTR))
7854 /* If this is the only entry on the list, clear
7855 reg_values[i]. Otherwise, just clear this entry on
7857 if (XEXP (x, 1) == 0 && x == reg_values[i])
7867 /* We must look at earlier registers, in case REGNO is part of a
7868 multi word value but is not the first register. If an earlier
7869 register has a value in a mode which overlaps REGNO, then we must
7870 invalidate that earlier register. Note that we do not need to
7871 check REGNO or later registers (we must not check REGNO itself,
7872 because we would incorrectly conclude that there was a conflict). */
7874 for (i = 0; i < regno; i++)
7878 for (x = reg_values[i]; x; x = XEXP (x, 1))
7880 if (XEXP (x, 0) != 0)
7882 PUT_MODE (invalidate_regno_rtx, GET_MODE (x));
7883 REGNO (invalidate_regno_rtx) = i;
7884 if (refers_to_regno_p (regno, endregno, invalidate_regno_rtx,
7887 reload_cse_invalidate_regno (i, VOIDmode, 1);
7895 /* The memory at address MEM_BASE is being changed.
7896 Return whether this change will invalidate VAL. */
7899 reload_cse_mem_conflict_p (mem_base, val)
7907 code = GET_CODE (val);
7910 /* Get rid of a few simple cases quickly. */
7923 if (GET_MODE (mem_base) == BLKmode
7924 || GET_MODE (val) == BLKmode)
7926 if (anti_dependence (val, mem_base))
7928 /* The address may contain nested MEMs. */
7935 fmt = GET_RTX_FORMAT (code);
7937 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7941 if (reload_cse_mem_conflict_p (mem_base, XEXP (val, i)))
7944 else if (fmt[i] == 'E')
7948 for (j = 0; j < XVECLEN (val, i); j++)
7949 if (reload_cse_mem_conflict_p (mem_base, XVECEXP (val, i, j)))
7957 /* Invalidate any entries in reg_values which are changed because of a
7958 store to MEM_RTX. If this is called because of a non-const call
7959 instruction, MEM_RTX is (mem:BLK const0_rtx). */
7962 reload_cse_invalidate_mem (mem_rtx)
7967 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
7971 for (x = reg_values[i]; x; x = XEXP (x, 1))
7973 if (XEXP (x, 0) != 0
7974 && reload_cse_mem_conflict_p (mem_rtx, XEXP (x, 0)))
7976 /* If this is the only entry on the list, clear
7977 reg_values[i]. Otherwise, just clear this entry on
7979 if (XEXP (x, 1) == 0 && x == reg_values[i])
7990 /* Invalidate DEST, which is being assigned to or clobbered. The
7991 second parameter exists so that this function can be passed to
7992 note_stores; it is ignored. */
7995 reload_cse_invalidate_rtx (dest, ignore, data)
7997 rtx ignore ATTRIBUTE_UNUSED;
7998 void *data ATTRIBUTE_UNUSED;
8000 while (GET_CODE (dest) == STRICT_LOW_PART
8001 || GET_CODE (dest) == SIGN_EXTRACT
8002 || GET_CODE (dest) == ZERO_EXTRACT
8003 || GET_CODE (dest) == SUBREG)
8004 dest = XEXP (dest, 0);
8006 if (GET_CODE (dest) == REG)
8007 reload_cse_invalidate_regno (REGNO (dest), GET_MODE (dest), 1);
8008 else if (GET_CODE (dest) == MEM)
8009 reload_cse_invalidate_mem (dest);
8012 /* Do a very simple CSE pass over the hard registers.
8014 This function detects no-op moves where we happened to assign two
8015 different pseudo-registers to the same hard register, and then
8016 copied one to the other. Reload will generate a useless
8017 instruction copying a register to itself.
8019 This function also detects cases where we load a value from memory
8020 into two different registers, and (if memory is more expensive than
8021 registers) changes it to simply copy the first register into the
8024 Another optimization is performed that scans the operands of each
8025 instruction to see whether the value is already available in a
8026 hard register. It then replaces the operand with the hard register
8027 if possible, much like an optional reload would. */
8030 reload_cse_regs_1 (first)
8038 init_alias_analysis ();
8040 reg_values = (rtx *) alloca (FIRST_PSEUDO_REGISTER * sizeof (rtx));
8041 bzero ((char *)reg_values, FIRST_PSEUDO_REGISTER * sizeof (rtx));
8043 /* Create our EXPR_LIST structures on reload_obstack, so that we can
8044 free them when we are done. */
8045 push_obstacks (&reload_obstack, &reload_obstack);
8046 firstobj = (char *) obstack_alloc (&reload_obstack, 0);
8048 /* We pass this to reload_cse_invalidate_mem to invalidate all of
8049 memory for a non-const call instruction. */
8050 callmem = gen_rtx_MEM (BLKmode, const0_rtx);
8052 /* This is used in reload_cse_invalidate_regno to avoid consing a
8053 new REG in a loop in that function. */
8054 invalidate_regno_rtx = gen_rtx_REG (VOIDmode, 0);
8056 for (insn = first; insn; insn = NEXT_INSN (insn))
8060 if (GET_CODE (insn) == CODE_LABEL)
8062 /* Forget all the register values at a code label. We don't
8063 try to do anything clever around jumps. */
8064 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8070 #ifdef NON_SAVING_SETJMP
8071 if (NON_SAVING_SETJMP && GET_CODE (insn) == NOTE
8072 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
8074 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8081 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8084 /* If this is a call instruction, forget anything stored in a
8085 call clobbered register, or, if this is not a const call, in
8087 if (GET_CODE (insn) == CALL_INSN)
8089 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8090 if (call_used_regs[i])
8091 reload_cse_invalidate_regno (i, VOIDmode, 1);
8093 if (! CONST_CALL_P (insn))
8094 reload_cse_invalidate_mem (callmem);
8098 /* Forget all the register values at a volatile asm. */
8099 if (GET_CODE (insn) == INSN
8100 && GET_CODE (PATTERN (insn)) == ASM_OPERANDS
8101 && MEM_VOLATILE_P (PATTERN (insn)))
8102 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8105 body = PATTERN (insn);
8106 if (GET_CODE (body) == SET)
8109 if (reload_cse_noop_set_p (body, insn))
8111 /* If this sets the return value of the function, we must keep
8112 a USE around, in case this is in a different basic block
8113 than the final USE. Otherwise, we could loose important
8114 register lifeness information on SMALL_REGISTER_CLASSES
8115 machines, where return registers might be used as spills:
8116 subsequent passes assume that spill registers are dead at
8117 the end of a basic block. */
8118 if (REG_FUNCTION_VALUE_P (SET_DEST (body)))
8121 PATTERN (insn) = gen_rtx_USE (VOIDmode, SET_DEST (body));
8122 INSN_CODE (insn) = -1;
8123 REG_NOTES (insn) = NULL_RTX;
8124 push_obstacks (&reload_obstack, &reload_obstack);
8128 PUT_CODE (insn, NOTE);
8129 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8130 NOTE_SOURCE_FILE (insn) = 0;
8133 /* We're done with this insn. */
8137 /* It's not a no-op, but we can try to simplify it. */
8138 count += reload_cse_simplify_set (body, insn);
8141 apply_change_group ();
8143 reload_cse_simplify_operands (insn);
8145 reload_cse_record_set (body, body);
8147 else if (GET_CODE (body) == PARALLEL)
8150 rtx value = NULL_RTX;
8152 /* If every action in a PARALLEL is a noop, we can delete
8153 the entire PARALLEL. */
8154 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8156 rtx part = XVECEXP (body, 0, i);
8157 if (GET_CODE (part) == SET)
8159 if (! reload_cse_noop_set_p (part, insn))
8161 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8165 value = SET_DEST (part);
8168 else if (GET_CODE (part) != CLOBBER)
8176 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
8177 INSN_CODE (insn) = -1;
8178 REG_NOTES (insn) = NULL_RTX;
8179 push_obstacks (&reload_obstack, &reload_obstack);
8183 PUT_CODE (insn, NOTE);
8184 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8185 NOTE_SOURCE_FILE (insn) = 0;
8188 /* We're done with this insn. */
8192 /* It's not a no-op, but we can try to simplify it. */
8193 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8194 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8195 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8198 apply_change_group ();
8200 reload_cse_simplify_operands (insn);
8202 /* Look through the PARALLEL and record the values being
8203 set, if possible. Also handle any CLOBBERs. */
8204 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8206 rtx x = XVECEXP (body, 0, i);
8208 if (GET_CODE (x) == SET)
8209 reload_cse_record_set (x, body);
8211 note_stores (x, reload_cse_invalidate_rtx, NULL);
8215 note_stores (body, reload_cse_invalidate_rtx, NULL);
8218 /* Clobber any registers which appear in REG_INC notes. We
8219 could keep track of the changes to their values, but it is
8220 unlikely to help. */
8224 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
8225 if (REG_NOTE_KIND (x) == REG_INC)
8226 reload_cse_invalidate_rtx (XEXP (x, 0), NULL_RTX, NULL);
8230 /* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only
8231 after we have processed the insn. */
8232 if (GET_CODE (insn) == CALL_INSN)
8236 for (x = CALL_INSN_FUNCTION_USAGE (insn); x; x = XEXP (x, 1))
8237 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
8238 reload_cse_invalidate_rtx (XEXP (XEXP (x, 0), 0), NULL_RTX,
8244 end_alias_analysis ();
8246 /* Free all the temporary structures we created, and go back to the
8247 regular obstacks. */
8248 obstack_free (&reload_obstack, firstobj);
8252 /* Call cse / combine like post-reload optimization phases.
8253 FIRST is the first instruction. */
8255 reload_cse_regs (first)
8258 reload_cse_regs_1 (first);
8260 reload_cse_move2add (first);
8261 if (flag_expensive_optimizations)
8262 reload_cse_regs_1 (first);
8265 /* Return whether the values known for REGNO are equal to VAL. MODE
8266 is the mode of the object that VAL is being copied to; this matters
8267 if VAL is a CONST_INT. */
8270 reload_cse_regno_equal_p (regno, val, mode)
8273 enum machine_mode mode;
8280 for (x = reg_values[regno]; x; x = XEXP (x, 1))
8281 if (XEXP (x, 0) != 0
8282 && rtx_equal_p (XEXP (x, 0), val)
8283 && (! flag_float_store || GET_CODE (XEXP (x, 0)) != MEM
8284 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
8285 && (GET_CODE (val) != CONST_INT
8286 || mode == GET_MODE (x)
8287 || (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8288 /* On a big endian machine if the value spans more than
8289 one register then this register holds the high part of
8290 it and we can't use it.
8292 ??? We should also compare with the high part of the
8294 && !(WORDS_BIG_ENDIAN
8295 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
8296 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
8297 GET_MODE_BITSIZE (GET_MODE (x))))))
8303 /* See whether a single set is a noop. SET is the set instruction we
8304 are should check, and INSN is the instruction from which it came. */
8307 reload_cse_noop_set_p (set, insn)
8309 rtx insn ATTRIBUTE_UNUSED;
8312 enum machine_mode dest_mode;
8316 src = SET_SRC (set);
8317 dest = SET_DEST (set);
8318 dest_mode = GET_MODE (dest);
8320 if (side_effects_p (src))
8323 dreg = true_regnum (dest);
8324 sreg = true_regnum (src);
8326 /* Check for setting a register to itself. In this case, we don't
8327 have to worry about REG_DEAD notes. */
8328 if (dreg >= 0 && dreg == sreg)
8334 /* Check for setting a register to itself. */
8338 /* Check for setting a register to a value which we already know
8339 is in the register. */
8340 else if (reload_cse_regno_equal_p (dreg, src, dest_mode))
8343 /* Check for setting a register DREG to another register SREG
8344 where SREG is equal to a value which is already in DREG. */
8349 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
8353 if (XEXP (x, 0) == 0)
8356 if (dest_mode == GET_MODE (x))
8358 else if (GET_MODE_BITSIZE (dest_mode)
8359 < GET_MODE_BITSIZE (GET_MODE (x)))
8360 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
8365 && reload_cse_regno_equal_p (dreg, tmp, dest_mode))
8373 else if (GET_CODE (dest) == MEM)
8375 /* Check for storing a register to memory when we know that the
8376 register is equivalent to the memory location. */
8378 && reload_cse_regno_equal_p (sreg, dest, dest_mode)
8379 && ! side_effects_p (dest))
8386 /* Try to simplify a single SET instruction. SET is the set pattern.
8387 INSN is the instruction it came from.
8388 This function only handles one case: if we set a register to a value
8389 which is not a register, we try to find that value in some other register
8390 and change the set into a register copy. */
8393 reload_cse_simplify_set (set, insn)
8399 enum machine_mode dest_mode;
8400 enum reg_class dclass;
8403 dreg = true_regnum (SET_DEST (set));
8407 src = SET_SRC (set);
8408 if (side_effects_p (src) || true_regnum (src) >= 0)
8411 dclass = REGNO_REG_CLASS (dreg);
8413 /* If memory loads are cheaper than register copies, don't change them. */
8414 if (GET_CODE (src) == MEM
8415 && MEMORY_MOVE_COST (GET_MODE (src), dclass, 1) < 2)
8418 /* If the constant is cheaper than a register, don't change it. */
8419 if (CONSTANT_P (src)
8420 && rtx_cost (src, SET) < 2)
8423 dest_mode = GET_MODE (SET_DEST (set));
8424 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8427 && REGISTER_MOVE_COST (REGNO_REG_CLASS (i), dclass) == 2
8428 && reload_cse_regno_equal_p (i, src, dest_mode))
8432 /* Pop back to the real obstacks while changing the insn. */
8435 validated = validate_change (insn, &SET_SRC (set),
8436 gen_rtx_REG (dest_mode, i), 1);
8438 /* Go back to the obstack we are using for temporary
8440 push_obstacks (&reload_obstack, &reload_obstack);
8449 /* Try to replace operands in INSN with equivalent values that are already
8450 in registers. This can be viewed as optional reloading.
8452 For each non-register operand in the insn, see if any hard regs are
8453 known to be equivalent to that operand. Record the alternatives which
8454 can accept these hard registers. Among all alternatives, select the
8455 ones which are better or equal to the one currently matching, where
8456 "better" is in terms of '?' and '!' constraints. Among the remaining
8457 alternatives, select the one which replaces most operands with
8461 reload_cse_simplify_operands (insn)
8466 const char *constraints[MAX_RECOG_OPERANDS];
8468 /* Vector recording how bad an alternative is. */
8469 int *alternative_reject;
8470 /* Vector recording how many registers can be introduced by choosing
8471 this alternative. */
8472 int *alternative_nregs;
8473 /* Array of vectors recording, for each operand and each alternative,
8474 which hard register to substitute, or -1 if the operand should be
8476 int *op_alt_regno[MAX_RECOG_OPERANDS];
8477 /* Array of alternatives, sorted in order of decreasing desirability. */
8478 int *alternative_order;
8479 rtx reg = gen_rtx_REG (VOIDmode, -1);
8481 extract_insn (insn);
8483 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8486 /* Figure out which alternative currently matches. */
8487 if (! constrain_operands (1))
8488 fatal_insn_not_found (insn);
8490 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8491 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8492 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8493 bzero ((char *)alternative_reject, recog_data.n_alternatives * sizeof (int));
8494 bzero ((char *)alternative_nregs, recog_data.n_alternatives * sizeof (int));
8496 for (i = 0; i < recog_data.n_operands; i++)
8498 enum machine_mode mode;
8502 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8503 for (j = 0; j < recog_data.n_alternatives; j++)
8504 op_alt_regno[i][j] = -1;
8506 p = constraints[i] = recog_data.constraints[i];
8507 mode = recog_data.operand_mode[i];
8509 /* Add the reject values for each alternative given by the constraints
8510 for this operand. */
8518 alternative_reject[j] += 3;
8520 alternative_reject[j] += 300;
8523 /* We won't change operands which are already registers. We
8524 also don't want to modify output operands. */
8525 regno = true_regnum (recog_data.operand[i]);
8527 || constraints[i][0] == '='
8528 || constraints[i][0] == '+')
8531 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8533 int class = (int) NO_REGS;
8535 if (! reload_cse_regno_equal_p (regno, recog_data.operand[i], mode))
8538 REGNO (reg) = regno;
8539 PUT_MODE (reg, mode);
8541 /* We found a register equal to this operand. Now look for all
8542 alternatives that can accept this register and have not been
8543 assigned a register they can use yet. */
8552 case '=': case '+': case '?':
8553 case '#': case '&': case '!':
8555 case '0': case '1': case '2': case '3': case '4':
8556 case '5': case '6': case '7': case '8': case '9':
8557 case 'm': case '<': case '>': case 'V': case 'o':
8558 case 'E': case 'F': case 'G': case 'H':
8559 case 's': case 'i': case 'n':
8560 case 'I': case 'J': case 'K': case 'L':
8561 case 'M': case 'N': case 'O': case 'P':
8562 #ifdef EXTRA_CONSTRAINT
8563 case 'Q': case 'R': case 'S': case 'T': case 'U':
8566 /* These don't say anything we care about. */
8570 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8575 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
8578 case ',': case '\0':
8579 /* See if REGNO fits this alternative, and set it up as the
8580 replacement register if we don't have one for this
8581 alternative yet and the operand being replaced is not
8582 a cheap CONST_INT. */
8583 if (op_alt_regno[i][j] == -1
8584 && reg_fits_class_p (reg, class, 0, mode)
8585 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8586 || (rtx_cost (recog_data.operand[i], SET)
8587 > rtx_cost (reg, SET))))
8589 alternative_nregs[j]++;
8590 op_alt_regno[i][j] = regno;
8602 /* Record all alternatives which are better or equal to the currently
8603 matching one in the alternative_order array. */
8604 for (i = j = 0; i < recog_data.n_alternatives; i++)
8605 if (alternative_reject[i] <= alternative_reject[which_alternative])
8606 alternative_order[j++] = i;
8607 recog_data.n_alternatives = j;
8609 /* Sort it. Given a small number of alternatives, a dumb algorithm
8610 won't hurt too much. */
8611 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8614 int best_reject = alternative_reject[alternative_order[i]];
8615 int best_nregs = alternative_nregs[alternative_order[i]];
8618 for (j = i + 1; j < recog_data.n_alternatives; j++)
8620 int this_reject = alternative_reject[alternative_order[j]];
8621 int this_nregs = alternative_nregs[alternative_order[j]];
8623 if (this_reject < best_reject
8624 || (this_reject == best_reject && this_nregs < best_nregs))
8627 best_reject = this_reject;
8628 best_nregs = this_nregs;
8632 tmp = alternative_order[best];
8633 alternative_order[best] = alternative_order[i];
8634 alternative_order[i] = tmp;
8637 /* Substitute the operands as determined by op_alt_regno for the best
8639 j = alternative_order[0];
8641 /* Pop back to the real obstacks while changing the insn. */
8644 for (i = 0; i < recog_data.n_operands; i++)
8646 enum machine_mode mode = recog_data.operand_mode[i];
8647 if (op_alt_regno[i][j] == -1)
8650 validate_change (insn, recog_data.operand_loc[i],
8651 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8654 for (i = recog_data.n_dups - 1; i >= 0; i--)
8656 int op = recog_data.dup_num[i];
8657 enum machine_mode mode = recog_data.operand_mode[op];
8659 if (op_alt_regno[op][j] == -1)
8662 validate_change (insn, recog_data.dup_loc[i],
8663 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8666 /* Go back to the obstack we are using for temporary
8668 push_obstacks (&reload_obstack, &reload_obstack);
8670 return apply_change_group ();
8673 /* These two variables are used to pass information from
8674 reload_cse_record_set to reload_cse_check_clobber. */
8676 static int reload_cse_check_clobbered;
8677 static rtx reload_cse_check_src;
8679 /* See if DEST overlaps with RELOAD_CSE_CHECK_SRC. If it does, set
8680 RELOAD_CSE_CHECK_CLOBBERED. This is called via note_stores. The
8681 second argument, which is passed by note_stores, is ignored. */
8684 reload_cse_check_clobber (dest, ignore, data)
8686 rtx ignore ATTRIBUTE_UNUSED;
8687 void *data ATTRIBUTE_UNUSED;
8689 if (reg_overlap_mentioned_p (dest, reload_cse_check_src))
8690 reload_cse_check_clobbered = 1;
8693 /* Record the result of a SET instruction. SET is the set pattern.
8694 BODY is the pattern of the insn that it came from. */
8697 reload_cse_record_set (set, body)
8703 enum machine_mode dest_mode;
8705 dest = SET_DEST (set);
8706 src = SET_SRC (set);
8707 dreg = true_regnum (dest);
8708 sreg = true_regnum (src);
8709 dest_mode = GET_MODE (dest);
8711 /* Some machines don't define AUTO_INC_DEC, but they still use push
8712 instructions. We need to catch that case here in order to
8713 invalidate the stack pointer correctly. Note that invalidating
8714 the stack pointer is different from invalidating DEST. */
8716 while (GET_CODE (x) == SUBREG
8717 || GET_CODE (x) == ZERO_EXTRACT
8718 || GET_CODE (x) == SIGN_EXTRACT
8719 || GET_CODE (x) == STRICT_LOW_PART)
8721 if (push_operand (x, GET_MODE (x)))
8723 reload_cse_invalidate_rtx (stack_pointer_rtx, NULL_RTX, NULL);
8724 reload_cse_invalidate_rtx (dest, NULL_RTX, NULL);
8728 /* We can only handle an assignment to a register, or a store of a
8729 register to a memory location. For other cases, we just clobber
8730 the destination. We also have to just clobber if there are side
8731 effects in SRC or DEST. */
8732 if ((dreg < 0 && GET_CODE (dest) != MEM)
8733 || side_effects_p (src)
8734 || side_effects_p (dest))
8736 reload_cse_invalidate_rtx (dest, NULL_RTX, NULL);
8741 /* We don't try to handle values involving CC, because it's a pain
8742 to keep track of when they have to be invalidated. */
8743 if (reg_mentioned_p (cc0_rtx, src)
8744 || reg_mentioned_p (cc0_rtx, dest))
8746 reload_cse_invalidate_rtx (dest, NULL_RTX, NULL);
8751 /* If BODY is a PARALLEL, then we need to see whether the source of
8752 SET is clobbered by some other instruction in the PARALLEL. */
8753 if (GET_CODE (body) == PARALLEL)
8757 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8761 x = XVECEXP (body, 0, i);
8765 reload_cse_check_clobbered = 0;
8766 reload_cse_check_src = src;
8767 note_stores (x, reload_cse_check_clobber, NULL);
8768 if (reload_cse_check_clobbered)
8770 reload_cse_invalidate_rtx (dest, NULL_RTX, NULL);
8780 /* This is an assignment to a register. Update the value we
8781 have stored for the register. */
8786 /* This is a copy from one register to another. Any values
8787 which were valid for SREG are now valid for DREG. If the
8788 mode changes, we use gen_lowpart_common to extract only
8789 the part of the value that is copied. */
8790 reg_values[dreg] = 0;
8791 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
8795 if (XEXP (x, 0) == 0)
8797 if (dest_mode == GET_MODE (XEXP (x, 0)))
8799 else if (GET_MODE_BITSIZE (dest_mode)
8800 > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
8803 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
8805 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, tmp,
8810 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, src, NULL_RTX);
8812 /* We've changed DREG, so invalidate any values held by other
8813 registers that depend upon it. */
8814 reload_cse_invalidate_regno (dreg, dest_mode, 0);
8816 /* If this assignment changes more than one hard register,
8817 forget anything we know about the others. */
8818 for (i = 1; i < HARD_REGNO_NREGS (dreg, dest_mode); i++)
8819 reg_values[dreg + i] = 0;
8821 else if (GET_CODE (dest) == MEM)
8823 /* Invalidate conflicting memory locations. */
8824 reload_cse_invalidate_mem (dest);
8826 /* If we're storing a register to memory, add DEST to the list
8828 if (sreg >= 0 && ! side_effects_p (dest))
8829 reg_values[sreg] = gen_rtx_EXPR_LIST (dest_mode, dest,
8834 /* We should have bailed out earlier. */
8839 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8841 This code might also be useful when reload gave up on reg+reg addresssing
8842 because of clashes between the return register and INDEX_REG_CLASS. */
8844 /* The maximum number of uses of a register we can keep track of to
8845 replace them with reg+reg addressing. */
8846 #define RELOAD_COMBINE_MAX_USES 6
8848 /* INSN is the insn where a register has ben used, and USEP points to the
8849 location of the register within the rtl. */
8850 struct reg_use { rtx insn, *usep; };
8852 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8853 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8854 indicates where it becomes live again.
8855 Otherwise, USE_INDEX is the index of the last encountered use of the
8856 register (which is first among these we have seen since we scan backwards),
8857 OFFSET contains the constant offset that is added to the register in
8858 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8859 last, of these uses.
8860 STORE_RUID is always meaningful if we only want to use a value in a
8861 register in a different place: it denotes the next insn in the insn
8862 stream (i.e. the last ecountered) that sets or clobbers the register. */
8865 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8870 } reg_state[FIRST_PSEUDO_REGISTER];
8872 /* Reverse linear uid. This is increased in reload_combine while scanning
8873 the instructions from last to first. It is used to set last_label_ruid
8874 and the store_ruid / use_ruid fields in reg_state. */
8875 static int reload_combine_ruid;
8877 #define LABEL_LIVE(LABEL) \
8878 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8884 int first_index_reg = 1, last_index_reg = 0;
8886 int last_label_ruid;
8887 int min_labelno, n_labels;
8888 HARD_REG_SET ever_live_at_start, *label_live;
8890 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
8891 reload has already used it where appropriate, so there is no use in
8892 trying to generate it now. */
8893 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8896 /* To avoid wasting too much time later searching for an index register,
8897 determine the minimum and maximum index register numbers. */
8898 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8900 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i))
8902 if (! last_index_reg)
8904 first_index_reg = i;
8907 /* If no index register is available, we can quit now. */
8908 if (first_index_reg > last_index_reg)
8911 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8912 information is a bit fuzzy immediately after reload, but it's
8913 still good enough to determine which registers are live at a jump
8915 min_labelno = get_first_label_num ();
8916 n_labels = max_label_num () - min_labelno;
8917 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8918 CLEAR_HARD_REG_SET (ever_live_at_start);
8919 for (i = n_basic_blocks - 1; i >= 0; i--)
8921 insn = BLOCK_HEAD (i);
8922 if (GET_CODE (insn) == CODE_LABEL)
8926 REG_SET_TO_HARD_REG_SET (live, BASIC_BLOCK (i)->global_live_at_start);
8927 compute_use_by_pseudos (&live, BASIC_BLOCK (i)->global_live_at_start);
8928 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8929 IOR_HARD_REG_SET (ever_live_at_start, live);
8933 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8934 last_label_ruid = reload_combine_ruid = 0;
8935 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8937 reg_state[i].store_ruid = reload_combine_ruid;
8939 reg_state[i].use_index = -1;
8941 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8944 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8948 /* We cannot do our optimization across labels. Invalidating all the use
8949 information we have would be costly, so we just note where the label
8950 is and then later disable any optimization that would cross it. */
8951 if (GET_CODE (insn) == CODE_LABEL)
8952 last_label_ruid = reload_combine_ruid;
8953 if (GET_CODE (insn) == BARRIER)
8955 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8956 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8958 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8960 reload_combine_ruid++;
8962 /* Look for (set (REGX) (CONST_INT))
8963 (set (REGX) (PLUS (REGX) (REGY)))
8965 ... (MEM (REGX)) ...
8967 (set (REGZ) (CONST_INT))
8969 ... (MEM (PLUS (REGZ) (REGY)))... .
8971 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8972 and that we know all uses of REGX before it dies. */
8973 set = single_set (insn);
8975 && GET_CODE (SET_DEST (set)) == REG
8976 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8977 GET_MODE (SET_DEST (set)))
8979 && GET_CODE (SET_SRC (set)) == PLUS
8980 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8981 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8982 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8984 rtx reg = SET_DEST (set);
8985 rtx plus = SET_SRC (set);
8986 rtx base = XEXP (plus, 1);
8987 rtx prev = prev_nonnote_insn (insn);
8988 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8989 int regno = REGNO (reg);
8990 rtx const_reg = NULL_RTX;
8991 rtx reg_sum = NULL_RTX;
8993 /* Now, we need an index register.
8994 We'll set index_reg to this index register, const_reg to the
8995 register that is to be loaded with the constant
8996 (denoted as REGZ in the substitution illustration above),
8997 and reg_sum to the register-register that we want to use to
8998 substitute uses of REG (typically in MEMs) with.
8999 First check REG and BASE for being index registers;
9000 we can use them even if they are not dead. */
9001 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
9002 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
9010 /* Otherwise, look for a free index register. Since we have
9011 checked above that neiter REG nor BASE are index registers,
9012 if we find anything at all, it will be different from these
9014 for (i = first_index_reg; i <= last_index_reg; i++)
9016 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
9017 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
9018 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
9019 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
9021 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
9022 const_reg = index_reg;
9023 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
9028 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
9029 (REGY), i.e. BASE, is not clobbered before the last use we'll
9032 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
9033 && rtx_equal_p (SET_DEST (prev_set), reg)
9034 && reg_state[regno].use_index >= 0
9035 && reg_state[REGNO (base)].store_ruid <= reg_state[regno].use_ruid
9040 /* Change destination register and - if necessary - the
9041 constant value in PREV, the constant loading instruction. */
9042 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
9043 if (reg_state[regno].offset != const0_rtx)
9044 validate_change (prev,
9045 &SET_SRC (prev_set),
9046 GEN_INT (INTVAL (SET_SRC (prev_set))
9047 + INTVAL (reg_state[regno].offset)),
9049 /* Now for every use of REG that we have recorded, replace REG
9051 for (i = reg_state[regno].use_index;
9052 i < RELOAD_COMBINE_MAX_USES; i++)
9053 validate_change (reg_state[regno].reg_use[i].insn,
9054 reg_state[regno].reg_use[i].usep,
9057 if (apply_change_group ())
9061 /* Delete the reg-reg addition. */
9062 PUT_CODE (insn, NOTE);
9063 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9064 NOTE_SOURCE_FILE (insn) = 0;
9066 if (reg_state[regno].offset != const0_rtx)
9068 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
9070 for (np = ®_NOTES (prev); *np; )
9072 if (REG_NOTE_KIND (*np) == REG_EQUAL
9073 || REG_NOTE_KIND (*np) == REG_EQUIV)
9074 *np = XEXP (*np, 1);
9076 np = &XEXP (*np, 1);
9079 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9080 reg_state[REGNO (const_reg)].store_ruid = reload_combine_ruid;
9085 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
9086 if (GET_CODE (insn) == CALL_INSN)
9090 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9092 if (call_used_regs[i])
9094 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9095 reg_state[i].store_ruid = reload_combine_ruid;
9098 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
9099 link = XEXP (link, 1))
9101 rtx use = XEXP (link, 0);
9102 int regno = REGNO (XEXP (use, 0));
9103 if (GET_CODE (use) == CLOBBER)
9105 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9106 reg_state[regno].store_ruid = reload_combine_ruid;
9109 reg_state[regno].use_index = -1;
9112 if (GET_CODE (insn) == JUMP_INSN && GET_CODE (PATTERN (insn)) != RETURN)
9114 /* Non-spill registers might be used at the call destination in
9115 some unknown fashion, so we have to mark the unknown use. */
9117 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
9118 && JUMP_LABEL (insn))
9119 live = &LABEL_LIVE (JUMP_LABEL (insn));
9121 live = &ever_live_at_start;
9122 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9124 if (TEST_HARD_REG_BIT (*live, i))
9125 reg_state[i].use_index = -1;
9128 reload_combine_note_use (&PATTERN (insn), insn);
9129 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9131 if (REG_NOTE_KIND (note) == REG_INC
9132 && GET_CODE (XEXP (note, 0)) == REG)
9134 int regno = REGNO (XEXP (note, 0));
9136 reg_state[regno].store_ruid = reload_combine_ruid;
9137 reg_state[regno].use_index = -1;
9144 /* Check if DST is a register or a subreg of a register; if it is,
9145 update reg_state[regno].store_ruid and reg_state[regno].use_index
9146 accordingly. Called via note_stores from reload_combine. */
9148 reload_combine_note_store (dst, set, data)
9150 void *data ATTRIBUTE_UNUSED;
9154 unsigned size = GET_MODE_SIZE (GET_MODE (dst));
9156 if (GET_CODE (dst) == SUBREG)
9158 regno = SUBREG_WORD (dst);
9159 dst = SUBREG_REG (dst);
9161 if (GET_CODE (dst) != REG)
9163 regno += REGNO (dst);
9165 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
9166 careful with registers / register parts that are not full words.
9168 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
9169 if (GET_CODE (set) != SET
9170 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
9171 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
9172 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
9174 for (i = (size - 1) / UNITS_PER_WORD + regno; i >= regno; i--)
9176 reg_state[i].use_index = -1;
9177 reg_state[i].store_ruid = reload_combine_ruid;
9182 for (i = (size - 1) / UNITS_PER_WORD + regno; i >= regno; i--)
9184 reg_state[i].store_ruid = reload_combine_ruid;
9185 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9190 /* XP points to a piece of rtl that has to be checked for any uses of
9192 *XP is the pattern of INSN, or a part of it.
9193 Called from reload_combine, and recursively by itself. */
9195 reload_combine_note_use (xp, insn)
9199 enum rtx_code code = x->code;
9202 rtx offset = const0_rtx; /* For the REG case below. */
9207 if (GET_CODE (SET_DEST (x)) == REG)
9209 reload_combine_note_use (&SET_SRC (x), insn);
9215 if (GET_CODE (SET_DEST (x)) == REG)
9220 /* We are interested in (plus (reg) (const_int)) . */
9221 if (GET_CODE (XEXP (x, 0)) != REG || GET_CODE (XEXP (x, 1)) != CONST_INT)
9223 offset = XEXP (x, 1);
9228 int regno = REGNO (x);
9231 /* Some spurious USEs of pseudo registers might remain.
9232 Just ignore them. */
9233 if (regno >= FIRST_PSEUDO_REGISTER)
9236 /* If this register is already used in some unknown fashion, we
9238 If we decrement the index from zero to -1, we can't store more
9239 uses, so this register becomes used in an unknown fashion. */
9240 use_index = --reg_state[regno].use_index;
9244 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
9246 /* We have found another use for a register that is already
9247 used later. Check if the offsets match; if not, mark the
9248 register as used in an unknown fashion. */
9249 if (! rtx_equal_p (offset, reg_state[regno].offset))
9251 reg_state[regno].use_index = -1;
9257 /* This is the first use of this register we have seen since we
9258 marked it as dead. */
9259 reg_state[regno].offset = offset;
9260 reg_state[regno].use_ruid = reload_combine_ruid;
9262 reg_state[regno].reg_use[use_index].insn = insn;
9263 reg_state[regno].reg_use[use_index].usep = xp;
9271 /* Recursively process the components of X. */
9272 fmt = GET_RTX_FORMAT (code);
9273 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9276 reload_combine_note_use (&XEXP (x, i), insn);
9277 else if (fmt[i] == 'E')
9279 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9280 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9285 /* See if we can reduce the cost of a constant by replacing a move with
9287 /* We cannot do our optimization across labels. Invalidating all the
9288 information about register contents we have would be costly, so we
9289 use last_label_luid (local variable of reload_cse_move2add) to note
9290 where the label is and then later disable any optimization that would
9292 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9293 reg_set_luid[n] is larger than last_label_luid[n] . */
9294 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9295 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
9296 reg_mode[n] to be valid.
9297 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
9298 has been set to reg_offset[n] in mode reg_mode[n] .
9299 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
9300 register n has been set to the sum of reg_offset[n] and register
9301 reg_base_reg[n], calculated in mode reg_mode[n] . */
9302 static rtx reg_offset[FIRST_PSEUDO_REGISTER];
9303 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9304 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9305 /* move2add_luid is linearily increased while scanning the instructions
9306 from first to last. It is used to set reg_set_luid in
9307 reload_cse_move2add and move2add_note_store. */
9308 static int move2add_luid;
9310 /* Generate a CONST_INT and force it in the range of MODE. */
9312 gen_mode_int (mode, value)
9313 enum machine_mode mode;
9314 HOST_WIDE_INT value;
9316 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
9317 int width = GET_MODE_BITSIZE (mode);
9319 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
9321 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
9322 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
9323 cval |= (HOST_WIDE_INT) -1 << width;
9325 return GEN_INT (cval);
9329 reload_cse_move2add (first)
9334 int last_label_luid;
9336 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
9337 reg_set_luid[i] = 0;
9339 last_label_luid = 0;
9341 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9345 if (GET_CODE (insn) == CODE_LABEL)
9346 last_label_luid = move2add_luid;
9347 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
9349 pat = PATTERN (insn);
9350 /* For simplicity, we only perform this optimization on
9351 straightforward SETs. */
9352 if (GET_CODE (pat) == SET
9353 && GET_CODE (SET_DEST (pat)) == REG)
9355 rtx reg = SET_DEST (pat);
9356 int regno = REGNO (reg);
9357 rtx src = SET_SRC (pat);
9359 /* Check if we have valid information on the contents of this
9360 register in the mode of REG. */
9361 /* ??? We don't know how zero / sign extension is handled, hence
9362 we can't go from a narrower to a wider mode. */
9363 if (reg_set_luid[regno] > last_label_luid
9364 && (GET_MODE_SIZE (GET_MODE (reg))
9365 <= GET_MODE_SIZE (reg_mode[regno]))
9366 && GET_CODE (reg_offset[regno]) == CONST_INT)
9368 /* Try to transform (set (REGX) (CONST_INT A))
9370 (set (REGX) (CONST_INT B))
9372 (set (REGX) (CONST_INT A))
9374 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9376 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9380 = gen_mode_int (GET_MODE (reg),
9381 INTVAL (src) - INTVAL (reg_offset[regno]));
9382 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9383 use (set (reg) (reg)) instead.
9384 We don't delete this insn, nor do we convert it into a
9385 note, to avoid losing register notes or the return
9386 value flag. jump2 already knowns how to get rid of
9388 if (new_src == const0_rtx)
9389 success = validate_change (insn, &SET_SRC (pat), reg, 0);
9390 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9391 && have_add2_insn (GET_MODE (reg)))
9392 success = validate_change (insn, &PATTERN (insn),
9393 gen_add2_insn (reg, new_src), 0);
9394 reg_set_luid[regno] = move2add_luid;
9395 reg_mode[regno] = GET_MODE (reg);
9396 reg_offset[regno] = src;
9400 /* Try to transform (set (REGX) (REGY))
9401 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9404 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9407 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9409 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9410 else if (GET_CODE (src) == REG
9411 && reg_base_reg[regno] == REGNO (src)
9412 && reg_set_luid[regno] > reg_set_luid[REGNO (src)])
9414 rtx next = next_nonnote_insn (insn);
9417 set = single_set (next);
9420 && SET_DEST (set) == reg
9421 && GET_CODE (SET_SRC (set)) == PLUS
9422 && XEXP (SET_SRC (set), 0) == reg
9423 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9425 rtx src3 = XEXP (SET_SRC (set), 1);
9427 = gen_mode_int (GET_MODE (reg),
9429 - INTVAL (reg_offset[regno]));
9432 if (new_src == const0_rtx)
9433 /* See above why we create (set (reg) (reg)) here. */
9435 = validate_change (next, &SET_SRC (set), reg, 0);
9436 else if ((rtx_cost (new_src, PLUS)
9437 < 2 + rtx_cost (src3, SET))
9438 && have_add2_insn (GET_MODE (reg)))
9440 = validate_change (next, &PATTERN (next),
9441 gen_add2_insn (reg, new_src), 0);
9444 /* INSN might be the first insn in a basic block
9445 if the preceding insn is a conditional jump
9446 or a possible-throwing call. */
9447 PUT_CODE (insn, NOTE);
9448 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9449 NOTE_SOURCE_FILE (insn) = 0;
9452 reg_set_luid[regno] = move2add_luid;
9453 reg_mode[regno] = GET_MODE (reg);
9454 reg_offset[regno] = src3;
9461 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9463 if (REG_NOTE_KIND (note) == REG_INC
9464 && GET_CODE (XEXP (note, 0)) == REG)
9466 /* Indicate that this register has been recently written to,
9467 but the exact contents are not available. */
9468 int regno = REGNO (XEXP (note, 0));
9469 if (regno < FIRST_PSEUDO_REGISTER)
9471 reg_set_luid[regno] = move2add_luid;
9472 reg_offset[regno] = note;
9476 note_stores (PATTERN (insn), move2add_note_store, NULL);
9477 /* If this is a CALL_INSN, all call used registers are stored with
9479 if (GET_CODE (insn) == CALL_INSN)
9481 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
9483 if (call_used_regs[i])
9485 reg_set_luid[i] = move2add_luid;
9486 reg_offset[i] = insn; /* Invalidate contents. */
9493 /* SET is a SET or CLOBBER that sets DST.
9494 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9495 Called from reload_cse_move2add via note_stores. */
9497 move2add_note_store (dst, set, data)
9499 void *data ATTRIBUTE_UNUSED;
9504 enum machine_mode mode = GET_MODE (dst);
9505 if (GET_CODE (dst) == SUBREG)
9507 regno = SUBREG_WORD (dst);
9508 dst = SUBREG_REG (dst);
9510 if (GET_CODE (dst) != REG)
9513 regno += REGNO (dst);
9515 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9516 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9517 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9518 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9520 rtx src = SET_SRC (set);
9522 reg_mode[regno] = mode;
9523 switch (GET_CODE (src))
9527 rtx src0 = XEXP (src, 0);
9528 if (GET_CODE (src0) == REG)
9530 if (REGNO (src0) != regno
9531 || reg_offset[regno] != const0_rtx)
9533 reg_base_reg[regno] = REGNO (src0);
9534 reg_set_luid[regno] = move2add_luid;
9536 reg_offset[regno] = XEXP (src, 1);
9539 reg_set_luid[regno] = move2add_luid;
9540 reg_offset[regno] = set; /* Invalidate contents. */
9545 reg_base_reg[regno] = REGNO (SET_SRC (set));
9546 reg_offset[regno] = const0_rtx;
9547 reg_set_luid[regno] = move2add_luid;
9551 reg_base_reg[regno] = -1;
9552 reg_offset[regno] = SET_SRC (set);
9553 reg_set_luid[regno] = move2add_luid;
9559 for (i = regno + HARD_REGNO_NREGS (regno, mode) - 1; i >= regno; i--)
9561 /* Indicate that this register has been recently written to,
9562 but the exact contents are not available. */
9563 reg_set_luid[i] = move2add_luid;
9564 reg_offset[i] = dst;
9571 add_auto_inc_notes (insn, x)
9575 enum rtx_code code = GET_CODE (x);
9579 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9582 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9586 /* Scan all the operand sub-expressions. */
9587 fmt = GET_RTX_FORMAT (code);
9588 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9591 add_auto_inc_notes (insn, XEXP (x, i));
9592 else if (fmt[i] == 'E')
9593 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9594 add_auto_inc_notes (insn, XVECEXP (x, i, j));
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