1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "addresses.h"
39 #include "basic-block.h"
51 /* This file contains the reload pass of the compiler, which is
52 run after register allocation has been done. It checks that
53 each insn is valid (operands required to be in registers really
54 are in registers of the proper class) and fixes up invalid ones
55 by copying values temporarily into registers for the insns
58 The results of register allocation are described by the vector
59 reg_renumber; the insns still contain pseudo regs, but reg_renumber
60 can be used to find which hard reg, if any, a pseudo reg is in.
62 The technique we always use is to free up a few hard regs that are
63 called ``reload regs'', and for each place where a pseudo reg
64 must be in a hard reg, copy it temporarily into one of the reload regs.
66 Reload regs are allocated locally for every instruction that needs
67 reloads. When there are pseudos which are allocated to a register that
68 has been chosen as a reload reg, such pseudos must be ``spilled''.
69 This means that they go to other hard regs, or to stack slots if no other
70 available hard regs can be found. Spilling can invalidate more
71 insns, requiring additional need for reloads, so we must keep checking
72 until the process stabilizes.
74 For machines with different classes of registers, we must keep track
75 of the register class needed for each reload, and make sure that
76 we allocate enough reload registers of each class.
78 The file reload.c contains the code that checks one insn for
79 validity and reports the reloads that it needs. This file
80 is in charge of scanning the entire rtl code, accumulating the
81 reload needs, spilling, assigning reload registers to use for
82 fixing up each insn, and generating the new insns to copy values
83 into the reload registers. */
85 /* During reload_as_needed, element N contains a REG rtx for the hard reg
86 into which reg N has been reloaded (perhaps for a previous insn). */
87 static rtx *reg_last_reload_reg;
89 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
90 for an output reload that stores into reg N. */
91 static regset_head reg_has_output_reload;
93 /* Indicates which hard regs are reload-registers for an output reload
94 in the current insn. */
95 static HARD_REG_SET reg_is_output_reload;
97 /* Element N is the constant value to which pseudo reg N is equivalent,
98 or zero if pseudo reg N is not equivalent to a constant.
99 find_reloads looks at this in order to replace pseudo reg N
100 with the constant it stands for. */
101 rtx *reg_equiv_constant;
103 /* Element N is an invariant value to which pseudo reg N is equivalent.
104 eliminate_regs_in_insn uses this to replace pseudos in particular
106 rtx *reg_equiv_invariant;
108 /* Element N is a memory location to which pseudo reg N is equivalent,
109 prior to any register elimination (such as frame pointer to stack
110 pointer). Depending on whether or not it is a valid address, this value
111 is transferred to either reg_equiv_address or reg_equiv_mem. */
112 rtx *reg_equiv_memory_loc;
114 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
115 collector can keep track of what is inside. */
116 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
118 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
119 This is used when the address is not valid as a memory address
120 (because its displacement is too big for the machine.) */
121 rtx *reg_equiv_address;
123 /* Element N is the memory slot to which pseudo reg N is equivalent,
124 or zero if pseudo reg N is not equivalent to a memory slot. */
127 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
128 alternate representations of the location of pseudo reg N. */
129 rtx *reg_equiv_alt_mem_list;
131 /* Widest width in which each pseudo reg is referred to (via subreg). */
132 static unsigned int *reg_max_ref_width;
134 /* Element N is the list of insns that initialized reg N from its equivalent
135 constant or memory slot. */
137 int reg_equiv_init_size;
139 /* Vector to remember old contents of reg_renumber before spilling. */
140 static short *reg_old_renumber;
142 /* During reload_as_needed, element N contains the last pseudo regno reloaded
143 into hard register N. If that pseudo reg occupied more than one register,
144 reg_reloaded_contents points to that pseudo for each spill register in
145 use; all of these must remain set for an inheritance to occur. */
146 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
148 /* During reload_as_needed, element N contains the insn for which
149 hard register N was last used. Its contents are significant only
150 when reg_reloaded_valid is set for this register. */
151 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
153 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
154 static HARD_REG_SET reg_reloaded_valid;
155 /* Indicate if the register was dead at the end of the reload.
156 This is only valid if reg_reloaded_contents is set and valid. */
157 static HARD_REG_SET reg_reloaded_dead;
159 /* Indicate whether the register's current value is one that is not
160 safe to retain across a call, even for registers that are normally
161 call-saved. This is only meaningful for members of reg_reloaded_valid. */
162 static HARD_REG_SET reg_reloaded_call_part_clobbered;
164 /* Number of spill-regs so far; number of valid elements of spill_regs. */
167 /* In parallel with spill_regs, contains REG rtx's for those regs.
168 Holds the last rtx used for any given reg, or 0 if it has never
169 been used for spilling yet. This rtx is reused, provided it has
171 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
173 /* In parallel with spill_regs, contains nonzero for a spill reg
174 that was stored after the last time it was used.
175 The precise value is the insn generated to do the store. */
176 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
178 /* This is the register that was stored with spill_reg_store. This is a
179 copy of reload_out / reload_out_reg when the value was stored; if
180 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
181 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
183 /* This table is the inverse mapping of spill_regs:
184 indexed by hard reg number,
185 it contains the position of that reg in spill_regs,
186 or -1 for something that is not in spill_regs.
188 ?!? This is no longer accurate. */
189 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
191 /* This reg set indicates registers that can't be used as spill registers for
192 the currently processed insn. These are the hard registers which are live
193 during the insn, but not allocated to pseudos, as well as fixed
195 static HARD_REG_SET bad_spill_regs;
197 /* These are the hard registers that can't be used as spill register for any
198 insn. This includes registers used for user variables and registers that
199 we can't eliminate. A register that appears in this set also can't be used
200 to retry register allocation. */
201 static HARD_REG_SET bad_spill_regs_global;
203 /* Describes order of use of registers for reloading
204 of spilled pseudo-registers. `n_spills' is the number of
205 elements that are actually valid; new ones are added at the end.
207 Both spill_regs and spill_reg_order are used on two occasions:
208 once during find_reload_regs, where they keep track of the spill registers
209 for a single insn, but also during reload_as_needed where they show all
210 the registers ever used by reload. For the latter case, the information
211 is calculated during finish_spills. */
212 static short spill_regs[FIRST_PSEUDO_REGISTER];
214 /* This vector of reg sets indicates, for each pseudo, which hard registers
215 may not be used for retrying global allocation because the register was
216 formerly spilled from one of them. If we allowed reallocating a pseudo to
217 a register that it was already allocated to, reload might not
219 static HARD_REG_SET *pseudo_previous_regs;
221 /* This vector of reg sets indicates, for each pseudo, which hard
222 registers may not be used for retrying global allocation because they
223 are used as spill registers during one of the insns in which the
225 static HARD_REG_SET *pseudo_forbidden_regs;
227 /* All hard regs that have been used as spill registers for any insn are
228 marked in this set. */
229 static HARD_REG_SET used_spill_regs;
231 /* Index of last register assigned as a spill register. We allocate in
232 a round-robin fashion. */
233 static int last_spill_reg;
235 /* Nonzero if indirect addressing is supported on the machine; this means
236 that spilling (REG n) does not require reloading it into a register in
237 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
238 value indicates the level of indirect addressing supported, e.g., two
239 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
241 static char spill_indirect_levels;
243 /* Nonzero if indirect addressing is supported when the innermost MEM is
244 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
245 which these are valid is the same as spill_indirect_levels, above. */
246 char indirect_symref_ok;
248 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
249 char double_reg_address_ok;
251 /* Record the stack slot for each spilled hard register. */
252 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
254 /* Width allocated so far for that stack slot. */
255 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
257 /* Record which pseudos needed to be spilled. */
258 static regset_head spilled_pseudos;
260 /* Used for communication between order_regs_for_reload and count_pseudo.
261 Used to avoid counting one pseudo twice. */
262 static regset_head pseudos_counted;
264 /* First uid used by insns created by reload in this function.
265 Used in find_equiv_reg. */
266 int reload_first_uid;
268 /* Flag set by local-alloc or global-alloc if anything is live in
269 a call-clobbered reg across calls. */
270 int caller_save_needed;
272 /* Set to 1 while reload_as_needed is operating.
273 Required by some machines to handle any generated moves differently. */
274 int reload_in_progress = 0;
276 /* These arrays record the insn_code of insns that may be needed to
277 perform input and output reloads of special objects. They provide a
278 place to pass a scratch register. */
279 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
280 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
282 /* This obstack is used for allocation of rtl during register elimination.
283 The allocated storage can be freed once find_reloads has processed the
285 static struct obstack reload_obstack;
287 /* Points to the beginning of the reload_obstack. All insn_chain structures
288 are allocated first. */
289 static char *reload_startobj;
291 /* The point after all insn_chain structures. Used to quickly deallocate
292 memory allocated in copy_reloads during calculate_needs_all_insns. */
293 static char *reload_firstobj;
295 /* This points before all local rtl generated by register elimination.
296 Used to quickly free all memory after processing one insn. */
297 static char *reload_insn_firstobj;
299 /* List of insn_chain instructions, one for every insn that reload needs to
301 struct insn_chain *reload_insn_chain;
303 /* List of all insns needing reloads. */
304 static struct insn_chain *insns_need_reload;
306 /* This structure is used to record information about register eliminations.
307 Each array entry describes one possible way of eliminating a register
308 in favor of another. If there is more than one way of eliminating a
309 particular register, the most preferred should be specified first. */
313 int from; /* Register number to be eliminated. */
314 int to; /* Register number used as replacement. */
315 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
316 int can_eliminate; /* Nonzero if this elimination can be done. */
317 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
318 insns made by reload. */
319 HOST_WIDE_INT offset; /* Current offset between the two regs. */
320 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
321 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
322 rtx from_rtx; /* REG rtx for the register to be eliminated.
323 We cannot simply compare the number since
324 we might then spuriously replace a hard
325 register corresponding to a pseudo
326 assigned to the reg to be eliminated. */
327 rtx to_rtx; /* REG rtx for the replacement. */
330 static struct elim_table *reg_eliminate = 0;
332 /* This is an intermediate structure to initialize the table. It has
333 exactly the members provided by ELIMINABLE_REGS. */
334 static const struct elim_table_1
338 } reg_eliminate_1[] =
340 /* If a set of eliminable registers was specified, define the table from it.
341 Otherwise, default to the normal case of the frame pointer being
342 replaced by the stack pointer. */
344 #ifdef ELIMINABLE_REGS
347 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
350 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
352 /* Record the number of pending eliminations that have an offset not equal
353 to their initial offset. If nonzero, we use a new copy of each
354 replacement result in any insns encountered. */
355 int num_not_at_initial_offset;
357 /* Count the number of registers that we may be able to eliminate. */
358 static int num_eliminable;
359 /* And the number of registers that are equivalent to a constant that
360 can be eliminated to frame_pointer / arg_pointer + constant. */
361 static int num_eliminable_invariants;
363 /* For each label, we record the offset of each elimination. If we reach
364 a label by more than one path and an offset differs, we cannot do the
365 elimination. This information is indexed by the difference of the
366 number of the label and the first label number. We can't offset the
367 pointer itself as this can cause problems on machines with segmented
368 memory. The first table is an array of flags that records whether we
369 have yet encountered a label and the second table is an array of arrays,
370 one entry in the latter array for each elimination. */
372 static int first_label_num;
373 static char *offsets_known_at;
374 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
376 /* Number of labels in the current function. */
378 static int num_labels;
380 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
381 static void maybe_fix_stack_asms (void);
382 static void copy_reloads (struct insn_chain *);
383 static void calculate_needs_all_insns (int);
384 static int find_reg (struct insn_chain *, int);
385 static void find_reload_regs (struct insn_chain *);
386 static void select_reload_regs (void);
387 static void delete_caller_save_insns (void);
389 static void spill_failure (rtx, enum reg_class);
390 static void count_spilled_pseudo (int, int, int);
391 static void delete_dead_insn (rtx);
392 static void alter_reg (int, int);
393 static void set_label_offsets (rtx, rtx, int);
394 static void check_eliminable_occurrences (rtx);
395 static void elimination_effects (rtx, enum machine_mode);
396 static int eliminate_regs_in_insn (rtx, int);
397 static void update_eliminable_offsets (void);
398 static void mark_not_eliminable (rtx, const_rtx, void *);
399 static void set_initial_elim_offsets (void);
400 static bool verify_initial_elim_offsets (void);
401 static void set_initial_label_offsets (void);
402 static void set_offsets_for_label (rtx);
403 static void init_elim_table (void);
404 static void update_eliminables (HARD_REG_SET *);
405 static void spill_hard_reg (unsigned int, int);
406 static int finish_spills (int);
407 static void scan_paradoxical_subregs (rtx);
408 static void count_pseudo (int);
409 static void order_regs_for_reload (struct insn_chain *);
410 static void reload_as_needed (int);
411 static void forget_old_reloads_1 (rtx, const_rtx, void *);
412 static void forget_marked_reloads (regset);
413 static int reload_reg_class_lower (const void *, const void *);
414 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
416 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
418 static int reload_reg_free_p (unsigned int, int, enum reload_type);
419 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
421 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
423 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
424 static int allocate_reload_reg (struct insn_chain *, int, int);
425 static int conflicts_with_override (rtx);
426 static void failed_reload (rtx, int);
427 static int set_reload_reg (int, int);
428 static void choose_reload_regs_init (struct insn_chain *, rtx *);
429 static void choose_reload_regs (struct insn_chain *);
430 static void merge_assigned_reloads (rtx);
431 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
433 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
435 static void do_input_reload (struct insn_chain *, struct reload *, int);
436 static void do_output_reload (struct insn_chain *, struct reload *, int);
437 static void emit_reload_insns (struct insn_chain *);
438 static void delete_output_reload (rtx, int, int, rtx);
439 static void delete_address_reloads (rtx, rtx);
440 static void delete_address_reloads_1 (rtx, rtx, rtx);
441 static rtx inc_for_reload (rtx, rtx, rtx, int);
443 static void add_auto_inc_notes (rtx, rtx);
445 static void copy_eh_notes (rtx, rtx);
446 static int reloads_conflict (int, int);
447 static rtx gen_reload (rtx, rtx, int, enum reload_type);
448 static rtx emit_insn_if_valid_for_reload (rtx);
450 /* Initialize the reload pass. This is called at the beginning of compilation
451 and may be called again if the target is reinitialized. */
458 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
459 Set spill_indirect_levels to the number of levels such addressing is
460 permitted, zero if it is not permitted at all. */
463 = gen_rtx_MEM (Pmode,
466 LAST_VIRTUAL_REGISTER + 1),
468 spill_indirect_levels = 0;
470 while (memory_address_p (QImode, tem))
472 spill_indirect_levels++;
473 tem = gen_rtx_MEM (Pmode, tem);
476 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
478 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
479 indirect_symref_ok = memory_address_p (QImode, tem);
481 /* See if reg+reg is a valid (and offsettable) address. */
483 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
485 tem = gen_rtx_PLUS (Pmode,
486 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
487 gen_rtx_REG (Pmode, i));
489 /* This way, we make sure that reg+reg is an offsettable address. */
490 tem = plus_constant (tem, 4);
492 if (memory_address_p (QImode, tem))
494 double_reg_address_ok = 1;
499 /* Initialize obstack for our rtl allocation. */
500 gcc_obstack_init (&reload_obstack);
501 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
503 INIT_REG_SET (&spilled_pseudos);
504 INIT_REG_SET (&pseudos_counted);
507 /* List of insn chains that are currently unused. */
508 static struct insn_chain *unused_insn_chains = 0;
510 /* Allocate an empty insn_chain structure. */
512 new_insn_chain (void)
514 struct insn_chain *c;
516 if (unused_insn_chains == 0)
518 c = XOBNEW (&reload_obstack, struct insn_chain);
519 INIT_REG_SET (&c->live_throughout);
520 INIT_REG_SET (&c->dead_or_set);
524 c = unused_insn_chains;
525 unused_insn_chains = c->next;
527 c->is_caller_save_insn = 0;
528 c->need_operand_change = 0;
534 /* Small utility function to set all regs in hard reg set TO which are
535 allocated to pseudos in regset FROM. */
538 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
541 reg_set_iterator rsi;
543 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
545 int r = reg_renumber[regno];
549 /* reload_combine uses the information from
550 DF_LIVE_IN (BASIC_BLOCK), which might still
551 contain registers that have not actually been allocated
552 since they have an equivalence. */
553 gcc_assert (reload_completed);
556 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
560 /* Replace all pseudos found in LOC with their corresponding
564 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
577 unsigned int regno = REGNO (x);
579 if (regno < FIRST_PSEUDO_REGISTER)
582 x = eliminate_regs (x, mem_mode, usage);
586 replace_pseudos_in (loc, mem_mode, usage);
590 if (reg_equiv_constant[regno])
591 *loc = reg_equiv_constant[regno];
592 else if (reg_equiv_mem[regno])
593 *loc = reg_equiv_mem[regno];
594 else if (reg_equiv_address[regno])
595 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
598 gcc_assert (!REG_P (regno_reg_rtx[regno])
599 || REGNO (regno_reg_rtx[regno]) != regno);
600 *loc = regno_reg_rtx[regno];
605 else if (code == MEM)
607 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
611 /* Process each of our operands recursively. */
612 fmt = GET_RTX_FORMAT (code);
613 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
615 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
616 else if (*fmt == 'E')
617 for (j = 0; j < XVECLEN (x, i); j++)
618 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
621 /* Determine if the current function has an exception receiver block
622 that reaches the exit block via non-exceptional edges */
625 has_nonexceptional_receiver (void)
629 basic_block *tos, *worklist, bb;
631 /* If we're not optimizing, then just err on the safe side. */
635 /* First determine which blocks can reach exit via normal paths. */
636 tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1);
639 bb->flags &= ~BB_REACHABLE;
641 /* Place the exit block on our worklist. */
642 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
643 *tos++ = EXIT_BLOCK_PTR;
645 /* Iterate: find everything reachable from what we've already seen. */
646 while (tos != worklist)
650 FOR_EACH_EDGE (e, ei, bb->preds)
651 if (!(e->flags & EDGE_ABNORMAL))
653 basic_block src = e->src;
655 if (!(src->flags & BB_REACHABLE))
657 src->flags |= BB_REACHABLE;
664 /* Now see if there's a reachable block with an exceptional incoming
667 if (bb->flags & BB_REACHABLE)
668 FOR_EACH_EDGE (e, ei, bb->preds)
669 if (e->flags & EDGE_ABNORMAL)
672 /* No exceptional block reached exit unexceptionally. */
677 /* Global variables used by reload and its subroutines. */
679 /* Set during calculate_needs if an insn needs register elimination. */
680 static int something_needs_elimination;
681 /* Set during calculate_needs if an insn needs an operand changed. */
682 static int something_needs_operands_changed;
684 /* Nonzero means we couldn't get enough spill regs. */
687 /* Main entry point for the reload pass.
689 FIRST is the first insn of the function being compiled.
691 GLOBAL nonzero means we were called from global_alloc
692 and should attempt to reallocate any pseudoregs that we
693 displace from hard regs we will use for reloads.
694 If GLOBAL is zero, we do not have enough information to do that,
695 so any pseudo reg that is spilled must go to the stack.
697 Return value is nonzero if reload failed
698 and we must not do any more for this function. */
701 reload (rtx first, int global)
705 struct elim_table *ep;
708 /* Make sure even insns with volatile mem refs are recognizable. */
713 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
715 /* Make sure that the last insn in the chain
716 is not something that needs reloading. */
717 emit_note (NOTE_INSN_DELETED);
719 /* Enable find_equiv_reg to distinguish insns made by reload. */
720 reload_first_uid = get_max_uid ();
722 #ifdef SECONDARY_MEMORY_NEEDED
723 /* Initialize the secondary memory table. */
724 clear_secondary_mem ();
727 /* We don't have a stack slot for any spill reg yet. */
728 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
729 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
731 /* Initialize the save area information for caller-save, in case some
735 /* Compute which hard registers are now in use
736 as homes for pseudo registers.
737 This is done here rather than (eg) in global_alloc
738 because this point is reached even if not optimizing. */
739 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
742 /* A function that has a nonlocal label that can reach the exit
743 block via non-exceptional paths must save all call-saved
745 if (cfun->has_nonlocal_label
746 && has_nonexceptional_receiver ())
747 crtl->saves_all_registers = 1;
749 if (crtl->saves_all_registers)
750 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
751 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
752 df_set_regs_ever_live (i, true);
754 /* Find all the pseudo registers that didn't get hard regs
755 but do have known equivalent constants or memory slots.
756 These include parameters (known equivalent to parameter slots)
757 and cse'd or loop-moved constant memory addresses.
759 Record constant equivalents in reg_equiv_constant
760 so they will be substituted by find_reloads.
761 Record memory equivalents in reg_mem_equiv so they can
762 be substituted eventually by altering the REG-rtx's. */
764 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
765 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
766 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
767 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
768 reg_equiv_address = XCNEWVEC (rtx, max_regno);
769 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
770 reg_old_renumber = XCNEWVEC (short, max_regno);
771 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
772 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
773 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
775 CLEAR_HARD_REG_SET (bad_spill_regs_global);
777 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
778 to. Also find all paradoxical subregs and find largest such for
781 num_eliminable_invariants = 0;
782 for (insn = first; insn; insn = NEXT_INSN (insn))
784 rtx set = single_set (insn);
786 /* We may introduce USEs that we want to remove at the end, so
787 we'll mark them with QImode. Make sure there are no
788 previously-marked insns left by say regmove. */
789 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
790 && GET_MODE (insn) != VOIDmode)
791 PUT_MODE (insn, VOIDmode);
794 scan_paradoxical_subregs (PATTERN (insn));
796 if (set != 0 && REG_P (SET_DEST (set)))
798 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
804 i = REGNO (SET_DEST (set));
807 if (i <= LAST_VIRTUAL_REGISTER)
810 if (! function_invariant_p (x)
812 /* A function invariant is often CONSTANT_P but may
813 include a register. We promise to only pass
814 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
816 && LEGITIMATE_PIC_OPERAND_P (x)))
818 /* It can happen that a REG_EQUIV note contains a MEM
819 that is not a legitimate memory operand. As later
820 stages of reload assume that all addresses found
821 in the reg_equiv_* arrays were originally legitimate,
822 we ignore such REG_EQUIV notes. */
823 if (memory_operand (x, VOIDmode))
825 /* Always unshare the equivalence, so we can
826 substitute into this insn without touching the
828 reg_equiv_memory_loc[i] = copy_rtx (x);
830 else if (function_invariant_p (x))
832 if (GET_CODE (x) == PLUS)
834 /* This is PLUS of frame pointer and a constant,
835 and might be shared. Unshare it. */
836 reg_equiv_invariant[i] = copy_rtx (x);
837 num_eliminable_invariants++;
839 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
841 reg_equiv_invariant[i] = x;
842 num_eliminable_invariants++;
844 else if (LEGITIMATE_CONSTANT_P (x))
845 reg_equiv_constant[i] = x;
848 reg_equiv_memory_loc[i]
849 = force_const_mem (GET_MODE (SET_DEST (set)), x);
850 if (! reg_equiv_memory_loc[i])
851 reg_equiv_init[i] = NULL_RTX;
856 reg_equiv_init[i] = NULL_RTX;
861 reg_equiv_init[i] = NULL_RTX;
866 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
867 if (reg_equiv_init[i])
869 fprintf (dump_file, "init_insns for %u: ", i);
870 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
871 fprintf (dump_file, "\n");
876 first_label_num = get_first_label_num ();
877 num_labels = max_label_num () - first_label_num;
879 /* Allocate the tables used to store offset information at labels. */
880 /* We used to use alloca here, but the size of what it would try to
881 allocate would occasionally cause it to exceed the stack limit and
882 cause a core dump. */
883 offsets_known_at = XNEWVEC (char, num_labels);
884 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
886 /* Alter each pseudo-reg rtx to contain its hard reg number.
887 Assign stack slots to the pseudos that lack hard regs or equivalents.
888 Do not touch virtual registers. */
890 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
893 /* If we have some registers we think can be eliminated, scan all insns to
894 see if there is an insn that sets one of these registers to something
895 other than itself plus a constant. If so, the register cannot be
896 eliminated. Doing this scan here eliminates an extra pass through the
897 main reload loop in the most common case where register elimination
899 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
901 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
903 maybe_fix_stack_asms ();
905 insns_need_reload = 0;
906 something_needs_elimination = 0;
908 /* Initialize to -1, which means take the first spill register. */
911 /* Spill any hard regs that we know we can't eliminate. */
912 CLEAR_HARD_REG_SET (used_spill_regs);
913 /* There can be multiple ways to eliminate a register;
914 they should be listed adjacently.
915 Elimination for any register fails only if all possible ways fail. */
916 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
919 int can_eliminate = 0;
922 can_eliminate |= ep->can_eliminate;
925 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
927 spill_hard_reg (from, 1);
930 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
931 if (frame_pointer_needed)
932 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
934 finish_spills (global);
936 /* From now on, we may need to generate moves differently. We may also
937 allow modifications of insns which cause them to not be recognized.
938 Any such modifications will be cleaned up during reload itself. */
939 reload_in_progress = 1;
941 /* This loop scans the entire function each go-round
942 and repeats until one repetition spills no additional hard regs. */
945 int something_changed;
947 HOST_WIDE_INT starting_frame_size;
949 starting_frame_size = get_frame_size ();
951 set_initial_elim_offsets ();
952 set_initial_label_offsets ();
954 /* For each pseudo register that has an equivalent location defined,
955 try to eliminate any eliminable registers (such as the frame pointer)
956 assuming initial offsets for the replacement register, which
959 If the resulting location is directly addressable, substitute
960 the MEM we just got directly for the old REG.
962 If it is not addressable but is a constant or the sum of a hard reg
963 and constant, it is probably not addressable because the constant is
964 out of range, in that case record the address; we will generate
965 hairy code to compute the address in a register each time it is
966 needed. Similarly if it is a hard register, but one that is not
967 valid as an address register.
969 If the location is not addressable, but does not have one of the
970 above forms, assign a stack slot. We have to do this to avoid the
971 potential of producing lots of reloads if, e.g., a location involves
972 a pseudo that didn't get a hard register and has an equivalent memory
973 location that also involves a pseudo that didn't get a hard register.
975 Perhaps at some point we will improve reload_when_needed handling
976 so this problem goes away. But that's very hairy. */
978 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
979 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
981 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
983 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
985 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
986 else if (CONSTANT_P (XEXP (x, 0))
987 || (REG_P (XEXP (x, 0))
988 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
989 || (GET_CODE (XEXP (x, 0)) == PLUS
990 && REG_P (XEXP (XEXP (x, 0), 0))
991 && (REGNO (XEXP (XEXP (x, 0), 0))
992 < FIRST_PSEUDO_REGISTER)
993 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
994 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
997 /* Make a new stack slot. Then indicate that something
998 changed so we go back and recompute offsets for
999 eliminable registers because the allocation of memory
1000 below might change some offset. reg_equiv_{mem,address}
1001 will be set up for this pseudo on the next pass around
1003 reg_equiv_memory_loc[i] = 0;
1004 reg_equiv_init[i] = 0;
1009 if (caller_save_needed)
1010 setup_save_areas ();
1012 /* If we allocated another stack slot, redo elimination bookkeeping. */
1013 if (starting_frame_size != get_frame_size ())
1015 if (starting_frame_size && crtl->stack_alignment_needed)
1017 /* If we have a stack frame, we must align it now. The
1018 stack size may be a part of the offset computation for
1019 register elimination. So if this changes the stack size,
1020 then repeat the elimination bookkeeping. We don't
1021 realign when there is no stack, as that will cause a
1022 stack frame when none is needed should
1023 STARTING_FRAME_OFFSET not be already aligned to
1025 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
1026 if (starting_frame_size != get_frame_size ())
1030 if (caller_save_needed)
1032 save_call_clobbered_regs ();
1033 /* That might have allocated new insn_chain structures. */
1034 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1037 calculate_needs_all_insns (global);
1039 CLEAR_REG_SET (&spilled_pseudos);
1042 something_changed = 0;
1044 /* If we allocated any new memory locations, make another pass
1045 since it might have changed elimination offsets. */
1046 if (starting_frame_size != get_frame_size ())
1047 something_changed = 1;
1049 /* Even if the frame size remained the same, we might still have
1050 changed elimination offsets, e.g. if find_reloads called
1051 force_const_mem requiring the back end to allocate a constant
1052 pool base register that needs to be saved on the stack. */
1053 else if (!verify_initial_elim_offsets ())
1054 something_changed = 1;
1057 HARD_REG_SET to_spill;
1058 CLEAR_HARD_REG_SET (to_spill);
1059 update_eliminables (&to_spill);
1060 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
1062 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1063 if (TEST_HARD_REG_BIT (to_spill, i))
1065 spill_hard_reg (i, 1);
1068 /* Regardless of the state of spills, if we previously had
1069 a register that we thought we could eliminate, but now can
1070 not eliminate, we must run another pass.
1072 Consider pseudos which have an entry in reg_equiv_* which
1073 reference an eliminable register. We must make another pass
1074 to update reg_equiv_* so that we do not substitute in the
1075 old value from when we thought the elimination could be
1077 something_changed = 1;
1081 select_reload_regs ();
1085 if (insns_need_reload != 0 || did_spill)
1086 something_changed |= finish_spills (global);
1088 if (! something_changed)
1091 if (caller_save_needed)
1092 delete_caller_save_insns ();
1094 obstack_free (&reload_obstack, reload_firstobj);
1097 /* If global-alloc was run, notify it of any register eliminations we have
1100 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1101 if (ep->can_eliminate)
1102 mark_elimination (ep->from, ep->to);
1104 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1105 If that insn didn't set the register (i.e., it copied the register to
1106 memory), just delete that insn instead of the equivalencing insn plus
1107 anything now dead. If we call delete_dead_insn on that insn, we may
1108 delete the insn that actually sets the register if the register dies
1109 there and that is incorrect. */
1111 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1113 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1116 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1118 rtx equiv_insn = XEXP (list, 0);
1120 /* If we already deleted the insn or if it may trap, we can't
1121 delete it. The latter case shouldn't happen, but can
1122 if an insn has a variable address, gets a REG_EH_REGION
1123 note added to it, and then gets converted into a load
1124 from a constant address. */
1125 if (NOTE_P (equiv_insn)
1126 || can_throw_internal (equiv_insn))
1128 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1129 delete_dead_insn (equiv_insn);
1131 SET_INSN_DELETED (equiv_insn);
1136 /* Use the reload registers where necessary
1137 by generating move instructions to move the must-be-register
1138 values into or out of the reload registers. */
1140 if (insns_need_reload != 0 || something_needs_elimination
1141 || something_needs_operands_changed)
1143 HOST_WIDE_INT old_frame_size = get_frame_size ();
1145 reload_as_needed (global);
1147 gcc_assert (old_frame_size == get_frame_size ());
1149 gcc_assert (verify_initial_elim_offsets ());
1152 /* If we were able to eliminate the frame pointer, show that it is no
1153 longer live at the start of any basic block. If it ls live by
1154 virtue of being in a pseudo, that pseudo will be marked live
1155 and hence the frame pointer will be known to be live via that
1158 if (! frame_pointer_needed)
1160 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1162 /* Come here (with failure set nonzero) if we can't get enough spill
1166 CLEAR_REG_SET (&spilled_pseudos);
1167 reload_in_progress = 0;
1169 /* Now eliminate all pseudo regs by modifying them into
1170 their equivalent memory references.
1171 The REG-rtx's for the pseudos are modified in place,
1172 so all insns that used to refer to them now refer to memory.
1174 For a reg that has a reg_equiv_address, all those insns
1175 were changed by reloading so that no insns refer to it any longer;
1176 but the DECL_RTL of a variable decl may refer to it,
1177 and if so this causes the debugging info to mention the variable. */
1179 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1183 if (reg_equiv_mem[i])
1184 addr = XEXP (reg_equiv_mem[i], 0);
1186 if (reg_equiv_address[i])
1187 addr = reg_equiv_address[i];
1191 if (reg_renumber[i] < 0)
1193 rtx reg = regno_reg_rtx[i];
1195 REG_USERVAR_P (reg) = 0;
1196 PUT_CODE (reg, MEM);
1197 XEXP (reg, 0) = addr;
1198 if (reg_equiv_memory_loc[i])
1199 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1202 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1203 MEM_ATTRS (reg) = 0;
1205 MEM_NOTRAP_P (reg) = 1;
1207 else if (reg_equiv_mem[i])
1208 XEXP (reg_equiv_mem[i], 0) = addr;
1212 /* We must set reload_completed now since the cleanup_subreg_operands call
1213 below will re-recognize each insn and reload may have generated insns
1214 which are only valid during and after reload. */
1215 reload_completed = 1;
1217 /* Make a pass over all the insns and delete all USEs which we inserted
1218 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1219 notes. Delete all CLOBBER insns, except those that refer to the return
1220 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1221 from misarranging variable-array code, and simplify (subreg (reg))
1222 operands. Strip and regenerate REG_INC notes that may have been moved
1225 for (insn = first; insn; insn = NEXT_INSN (insn))
1231 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1232 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1234 if ((GET_CODE (PATTERN (insn)) == USE
1235 /* We mark with QImode USEs introduced by reload itself. */
1236 && (GET_MODE (insn) == QImode
1237 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1238 || (GET_CODE (PATTERN (insn)) == CLOBBER
1239 && (!MEM_P (XEXP (PATTERN (insn), 0))
1240 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1241 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1242 && XEXP (XEXP (PATTERN (insn), 0), 0)
1243 != stack_pointer_rtx))
1244 && (!REG_P (XEXP (PATTERN (insn), 0))
1245 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1251 /* Some CLOBBERs may survive until here and still reference unassigned
1252 pseudos with const equivalent, which may in turn cause ICE in later
1253 passes if the reference remains in place. */
1254 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1255 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1256 VOIDmode, PATTERN (insn));
1258 /* Discard obvious no-ops, even without -O. This optimization
1259 is fast and doesn't interfere with debugging. */
1260 if (NONJUMP_INSN_P (insn)
1261 && GET_CODE (PATTERN (insn)) == SET
1262 && REG_P (SET_SRC (PATTERN (insn)))
1263 && REG_P (SET_DEST (PATTERN (insn)))
1264 && (REGNO (SET_SRC (PATTERN (insn)))
1265 == REGNO (SET_DEST (PATTERN (insn)))))
1271 pnote = ®_NOTES (insn);
1274 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1275 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1276 || REG_NOTE_KIND (*pnote) == REG_INC)
1277 *pnote = XEXP (*pnote, 1);
1279 pnote = &XEXP (*pnote, 1);
1283 add_auto_inc_notes (insn, PATTERN (insn));
1286 /* Simplify (subreg (reg)) if it appears as an operand. */
1287 cleanup_subreg_operands (insn);
1289 /* Clean up invalid ASMs so that they don't confuse later passes.
1291 if (asm_noperands (PATTERN (insn)) >= 0)
1293 extract_insn (insn);
1294 if (!constrain_operands (1))
1296 error_for_asm (insn,
1297 "%<asm%> operand has impossible constraints");
1304 /* If we are doing generic stack checking, give a warning if this
1305 function's frame size is larger than we expect. */
1306 if (flag_stack_check == GENERIC_STACK_CHECK)
1308 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1309 static int verbose_warned = 0;
1311 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1312 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1313 size += UNITS_PER_WORD;
1315 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1317 warning (0, "frame size too large for reliable stack checking");
1318 if (! verbose_warned)
1320 warning (0, "try reducing the number of local variables");
1326 /* Indicate that we no longer have known memory locations or constants. */
1327 if (reg_equiv_constant)
1328 free (reg_equiv_constant);
1329 if (reg_equiv_invariant)
1330 free (reg_equiv_invariant);
1331 reg_equiv_constant = 0;
1332 reg_equiv_invariant = 0;
1333 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1334 reg_equiv_memory_loc = 0;
1336 if (offsets_known_at)
1337 free (offsets_known_at);
1341 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1342 if (reg_equiv_alt_mem_list[i])
1343 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1344 free (reg_equiv_alt_mem_list);
1346 free (reg_equiv_mem);
1348 free (reg_equiv_address);
1349 free (reg_max_ref_width);
1350 free (reg_old_renumber);
1351 free (pseudo_previous_regs);
1352 free (pseudo_forbidden_regs);
1354 CLEAR_HARD_REG_SET (used_spill_regs);
1355 for (i = 0; i < n_spills; i++)
1356 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1358 /* Free all the insn_chain structures at once. */
1359 obstack_free (&reload_obstack, reload_startobj);
1360 unused_insn_chains = 0;
1361 fixup_abnormal_edges ();
1363 /* Replacing pseudos with their memory equivalents might have
1364 created shared rtx. Subsequent passes would get confused
1365 by this, so unshare everything here. */
1366 unshare_all_rtl_again (first);
1368 #ifdef STACK_BOUNDARY
1369 /* init_emit has set the alignment of the hard frame pointer
1370 to STACK_BOUNDARY. It is very likely no longer valid if
1371 the hard frame pointer was used for register allocation. */
1372 if (!frame_pointer_needed)
1373 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1379 /* Yet another special case. Unfortunately, reg-stack forces people to
1380 write incorrect clobbers in asm statements. These clobbers must not
1381 cause the register to appear in bad_spill_regs, otherwise we'll call
1382 fatal_insn later. We clear the corresponding regnos in the live
1383 register sets to avoid this.
1384 The whole thing is rather sick, I'm afraid. */
1387 maybe_fix_stack_asms (void)
1390 const char *constraints[MAX_RECOG_OPERANDS];
1391 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1392 struct insn_chain *chain;
1394 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1397 HARD_REG_SET clobbered, allowed;
1400 if (! INSN_P (chain->insn)
1401 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1403 pat = PATTERN (chain->insn);
1404 if (GET_CODE (pat) != PARALLEL)
1407 CLEAR_HARD_REG_SET (clobbered);
1408 CLEAR_HARD_REG_SET (allowed);
1410 /* First, make a mask of all stack regs that are clobbered. */
1411 for (i = 0; i < XVECLEN (pat, 0); i++)
1413 rtx t = XVECEXP (pat, 0, i);
1414 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1415 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1418 /* Get the operand values and constraints out of the insn. */
1419 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1420 constraints, operand_mode, NULL);
1422 /* For every operand, see what registers are allowed. */
1423 for (i = 0; i < noperands; i++)
1425 const char *p = constraints[i];
1426 /* For every alternative, we compute the class of registers allowed
1427 for reloading in CLS, and merge its contents into the reg set
1429 int cls = (int) NO_REGS;
1435 if (c == '\0' || c == ',' || c == '#')
1437 /* End of one alternative - mark the regs in the current
1438 class, and reset the class. */
1439 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1445 } while (c != '\0' && c != ',');
1453 case '=': case '+': case '*': case '%': case '?': case '!':
1454 case '0': case '1': case '2': case '3': case '4': case '<':
1455 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1456 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1457 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1458 case TARGET_MEM_CONSTRAINT:
1462 cls = (int) reg_class_subunion[cls]
1463 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1468 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1472 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1473 cls = (int) reg_class_subunion[cls]
1474 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1476 cls = (int) reg_class_subunion[cls]
1477 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1479 p += CONSTRAINT_LEN (c, p);
1482 /* Those of the registers which are clobbered, but allowed by the
1483 constraints, must be usable as reload registers. So clear them
1484 out of the life information. */
1485 AND_HARD_REG_SET (allowed, clobbered);
1486 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1487 if (TEST_HARD_REG_BIT (allowed, i))
1489 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1490 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1497 /* Copy the global variables n_reloads and rld into the corresponding elts
1500 copy_reloads (struct insn_chain *chain)
1502 chain->n_reloads = n_reloads;
1503 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1504 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1505 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1508 /* Walk the chain of insns, and determine for each whether it needs reloads
1509 and/or eliminations. Build the corresponding insns_need_reload list, and
1510 set something_needs_elimination as appropriate. */
1512 calculate_needs_all_insns (int global)
1514 struct insn_chain **pprev_reload = &insns_need_reload;
1515 struct insn_chain *chain, *next = 0;
1517 something_needs_elimination = 0;
1519 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1520 for (chain = reload_insn_chain; chain != 0; chain = next)
1522 rtx insn = chain->insn;
1526 /* Clear out the shortcuts. */
1527 chain->n_reloads = 0;
1528 chain->need_elim = 0;
1529 chain->need_reload = 0;
1530 chain->need_operand_change = 0;
1532 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1533 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1534 what effects this has on the known offsets at labels. */
1536 if (LABEL_P (insn) || JUMP_P (insn)
1537 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1538 set_label_offsets (insn, insn, 0);
1542 rtx old_body = PATTERN (insn);
1543 int old_code = INSN_CODE (insn);
1544 rtx old_notes = REG_NOTES (insn);
1545 int did_elimination = 0;
1546 int operands_changed = 0;
1547 rtx set = single_set (insn);
1549 /* Skip insns that only set an equivalence. */
1550 if (set && REG_P (SET_DEST (set))
1551 && reg_renumber[REGNO (SET_DEST (set))] < 0
1552 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1553 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1554 && reg_equiv_init[REGNO (SET_DEST (set))])
1557 /* If needed, eliminate any eliminable registers. */
1558 if (num_eliminable || num_eliminable_invariants)
1559 did_elimination = eliminate_regs_in_insn (insn, 0);
1561 /* Analyze the instruction. */
1562 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1563 global, spill_reg_order);
1565 /* If a no-op set needs more than one reload, this is likely
1566 to be something that needs input address reloads. We
1567 can't get rid of this cleanly later, and it is of no use
1568 anyway, so discard it now.
1569 We only do this when expensive_optimizations is enabled,
1570 since this complements reload inheritance / output
1571 reload deletion, and it can make debugging harder. */
1572 if (flag_expensive_optimizations && n_reloads > 1)
1574 rtx set = single_set (insn);
1576 && SET_SRC (set) == SET_DEST (set)
1577 && REG_P (SET_SRC (set))
1578 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1581 /* Delete it from the reload chain. */
1583 chain->prev->next = next;
1585 reload_insn_chain = next;
1587 next->prev = chain->prev;
1588 chain->next = unused_insn_chains;
1589 unused_insn_chains = chain;
1594 update_eliminable_offsets ();
1596 /* Remember for later shortcuts which insns had any reloads or
1597 register eliminations. */
1598 chain->need_elim = did_elimination;
1599 chain->need_reload = n_reloads > 0;
1600 chain->need_operand_change = operands_changed;
1602 /* Discard any register replacements done. */
1603 if (did_elimination)
1605 obstack_free (&reload_obstack, reload_insn_firstobj);
1606 PATTERN (insn) = old_body;
1607 INSN_CODE (insn) = old_code;
1608 REG_NOTES (insn) = old_notes;
1609 something_needs_elimination = 1;
1612 something_needs_operands_changed |= operands_changed;
1616 copy_reloads (chain);
1617 *pprev_reload = chain;
1618 pprev_reload = &chain->next_need_reload;
1625 /* Comparison function for qsort to decide which of two reloads
1626 should be handled first. *P1 and *P2 are the reload numbers. */
1629 reload_reg_class_lower (const void *r1p, const void *r2p)
1631 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1634 /* Consider required reloads before optional ones. */
1635 t = rld[r1].optional - rld[r2].optional;
1639 /* Count all solitary classes before non-solitary ones. */
1640 t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1641 - (reg_class_size[(int) rld[r1].rclass] == 1));
1645 /* Aside from solitaires, consider all multi-reg groups first. */
1646 t = rld[r2].nregs - rld[r1].nregs;
1650 /* Consider reloads in order of increasing reg-class number. */
1651 t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1655 /* If reloads are equally urgent, sort by reload number,
1656 so that the results of qsort leave nothing to chance. */
1660 /* The cost of spilling each hard reg. */
1661 static int spill_cost[FIRST_PSEUDO_REGISTER];
1663 /* When spilling multiple hard registers, we use SPILL_COST for the first
1664 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1665 only the first hard reg for a multi-reg pseudo. */
1666 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1668 /* Update the spill cost arrays, considering that pseudo REG is live. */
1671 count_pseudo (int reg)
1673 int freq = REG_FREQ (reg);
1674 int r = reg_renumber[reg];
1677 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1678 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1681 SET_REGNO_REG_SET (&pseudos_counted, reg);
1683 gcc_assert (r >= 0);
1685 spill_add_cost[r] += freq;
1687 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1689 spill_cost[r + nregs] += freq;
1692 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1693 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1696 order_regs_for_reload (struct insn_chain *chain)
1699 HARD_REG_SET used_by_pseudos;
1700 HARD_REG_SET used_by_pseudos2;
1701 reg_set_iterator rsi;
1703 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1705 memset (spill_cost, 0, sizeof spill_cost);
1706 memset (spill_add_cost, 0, sizeof spill_add_cost);
1708 /* Count number of uses of each hard reg by pseudo regs allocated to it
1709 and then order them by decreasing use. First exclude hard registers
1710 that are live in or across this insn. */
1712 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1713 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1714 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1715 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1717 /* Now find out which pseudos are allocated to it, and update
1719 CLEAR_REG_SET (&pseudos_counted);
1721 EXECUTE_IF_SET_IN_REG_SET
1722 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1726 EXECUTE_IF_SET_IN_REG_SET
1727 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1731 CLEAR_REG_SET (&pseudos_counted);
1734 /* Vector of reload-numbers showing the order in which the reloads should
1736 static short reload_order[MAX_RELOADS];
1738 /* This is used to keep track of the spill regs used in one insn. */
1739 static HARD_REG_SET used_spill_regs_local;
1741 /* We decided to spill hard register SPILLED, which has a size of
1742 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1743 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1744 update SPILL_COST/SPILL_ADD_COST. */
1747 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1749 int r = reg_renumber[reg];
1750 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1752 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1753 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1756 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1758 spill_add_cost[r] -= REG_FREQ (reg);
1760 spill_cost[r + nregs] -= REG_FREQ (reg);
1763 /* Find reload register to use for reload number ORDER. */
1766 find_reg (struct insn_chain *chain, int order)
1768 int rnum = reload_order[order];
1769 struct reload *rl = rld + rnum;
1770 int best_cost = INT_MAX;
1774 HARD_REG_SET not_usable;
1775 HARD_REG_SET used_by_other_reload;
1776 reg_set_iterator rsi;
1778 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1779 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1780 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1782 CLEAR_HARD_REG_SET (used_by_other_reload);
1783 for (k = 0; k < order; k++)
1785 int other = reload_order[k];
1787 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1788 for (j = 0; j < rld[other].nregs; j++)
1789 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1792 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1794 unsigned int regno = i;
1796 if (! TEST_HARD_REG_BIT (not_usable, regno)
1797 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1798 && HARD_REGNO_MODE_OK (regno, rl->mode))
1800 int this_cost = spill_cost[regno];
1802 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1804 for (j = 1; j < this_nregs; j++)
1806 this_cost += spill_add_cost[regno + j];
1807 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1808 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1813 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1815 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1817 if (this_cost < best_cost
1818 /* Among registers with equal cost, prefer caller-saved ones, or
1819 use REG_ALLOC_ORDER if it is defined. */
1820 || (this_cost == best_cost
1821 #ifdef REG_ALLOC_ORDER
1822 && (inv_reg_alloc_order[regno]
1823 < inv_reg_alloc_order[best_reg])
1825 && call_used_regs[regno]
1826 && ! call_used_regs[best_reg]
1831 best_cost = this_cost;
1839 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1841 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1842 rl->regno = best_reg;
1844 EXECUTE_IF_SET_IN_REG_SET
1845 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1847 count_spilled_pseudo (best_reg, rl->nregs, j);
1850 EXECUTE_IF_SET_IN_REG_SET
1851 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1853 count_spilled_pseudo (best_reg, rl->nregs, j);
1856 for (i = 0; i < rl->nregs; i++)
1858 gcc_assert (spill_cost[best_reg + i] == 0);
1859 gcc_assert (spill_add_cost[best_reg + i] == 0);
1860 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1865 /* Find more reload regs to satisfy the remaining need of an insn, which
1867 Do it by ascending class number, since otherwise a reg
1868 might be spilled for a big class and might fail to count
1869 for a smaller class even though it belongs to that class. */
1872 find_reload_regs (struct insn_chain *chain)
1876 /* In order to be certain of getting the registers we need,
1877 we must sort the reloads into order of increasing register class.
1878 Then our grabbing of reload registers will parallel the process
1879 that provided the reload registers. */
1880 for (i = 0; i < chain->n_reloads; i++)
1882 /* Show whether this reload already has a hard reg. */
1883 if (chain->rld[i].reg_rtx)
1885 int regno = REGNO (chain->rld[i].reg_rtx);
1886 chain->rld[i].regno = regno;
1888 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1891 chain->rld[i].regno = -1;
1892 reload_order[i] = i;
1895 n_reloads = chain->n_reloads;
1896 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1898 CLEAR_HARD_REG_SET (used_spill_regs_local);
1901 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1903 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1905 /* Compute the order of preference for hard registers to spill. */
1907 order_regs_for_reload (chain);
1909 for (i = 0; i < n_reloads; i++)
1911 int r = reload_order[i];
1913 /* Ignore reloads that got marked inoperative. */
1914 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1915 && ! rld[r].optional
1916 && rld[r].regno == -1)
1917 if (! find_reg (chain, i))
1920 fprintf (dump_file, "reload failure for reload %d\n", r);
1921 spill_failure (chain->insn, rld[r].rclass);
1927 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1928 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1930 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1934 select_reload_regs (void)
1936 struct insn_chain *chain;
1938 /* Try to satisfy the needs for each insn. */
1939 for (chain = insns_need_reload; chain != 0;
1940 chain = chain->next_need_reload)
1941 find_reload_regs (chain);
1944 /* Delete all insns that were inserted by emit_caller_save_insns during
1947 delete_caller_save_insns (void)
1949 struct insn_chain *c = reload_insn_chain;
1953 while (c != 0 && c->is_caller_save_insn)
1955 struct insn_chain *next = c->next;
1958 if (c == reload_insn_chain)
1959 reload_insn_chain = next;
1963 next->prev = c->prev;
1965 c->prev->next = next;
1966 c->next = unused_insn_chains;
1967 unused_insn_chains = c;
1975 /* Handle the failure to find a register to spill.
1976 INSN should be one of the insns which needed this particular spill reg. */
1979 spill_failure (rtx insn, enum reg_class rclass)
1981 if (asm_noperands (PATTERN (insn)) >= 0)
1982 error_for_asm (insn, "can't find a register in class %qs while "
1983 "reloading %<asm%>",
1984 reg_class_names[rclass]);
1987 error ("unable to find a register to spill in class %qs",
1988 reg_class_names[rclass]);
1992 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
1993 debug_reload_to_stream (dump_file);
1995 fatal_insn ("this is the insn:", insn);
1999 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2000 data that is dead in INSN. */
2003 delete_dead_insn (rtx insn)
2005 rtx prev = prev_real_insn (insn);
2008 /* If the previous insn sets a register that dies in our insn, delete it
2010 if (prev && GET_CODE (PATTERN (prev)) == SET
2011 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2012 && reg_mentioned_p (prev_dest, PATTERN (insn))
2013 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2014 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2015 delete_dead_insn (prev);
2017 SET_INSN_DELETED (insn);
2020 /* Modify the home of pseudo-reg I.
2021 The new home is present in reg_renumber[I].
2023 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2024 or it may be -1, meaning there is none or it is not relevant.
2025 This is used so that all pseudos spilled from a given hard reg
2026 can share one stack slot. */
2029 alter_reg (int i, int from_reg)
2031 /* When outputting an inline function, this can happen
2032 for a reg that isn't actually used. */
2033 if (regno_reg_rtx[i] == 0)
2036 /* If the reg got changed to a MEM at rtl-generation time,
2038 if (!REG_P (regno_reg_rtx[i]))
2041 /* Modify the reg-rtx to contain the new hard reg
2042 number or else to contain its pseudo reg number. */
2043 SET_REGNO (regno_reg_rtx[i],
2044 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2046 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2047 allocate a stack slot for it. */
2049 if (reg_renumber[i] < 0
2050 && REG_N_REFS (i) > 0
2051 && reg_equiv_constant[i] == 0
2052 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
2053 && reg_equiv_memory_loc[i] == 0)
2056 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2057 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2058 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2059 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2060 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2063 /* Each pseudo reg has an inherent size which comes from its own mode,
2064 and a total size which provides room for paradoxical subregs
2065 which refer to the pseudo reg in wider modes.
2067 We can use a slot already allocated if it provides both
2068 enough inherent space and enough total space.
2069 Otherwise, we allocate a new slot, making sure that it has no less
2070 inherent space, and no less total space, then the previous slot. */
2073 alias_set_type alias_set = new_alias_set ();
2075 /* No known place to spill from => no slot to reuse. */
2076 x = assign_stack_local (mode, total_size,
2077 min_align > inherent_align
2078 || total_size > inherent_size ? -1 : 0);
2079 if (BYTES_BIG_ENDIAN)
2080 /* Cancel the big-endian correction done in assign_stack_local.
2081 Get the address of the beginning of the slot.
2082 This is so we can do a big-endian correction unconditionally
2084 adjust = inherent_size - total_size;
2086 /* Nothing can alias this slot except this pseudo. */
2087 set_mem_alias_set (x, alias_set);
2088 dse_record_singleton_alias_set (alias_set, mode);
2091 /* Reuse a stack slot if possible. */
2092 else if (spill_stack_slot[from_reg] != 0
2093 && spill_stack_slot_width[from_reg] >= total_size
2094 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2096 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2097 x = spill_stack_slot[from_reg];
2098 /* Allocate a bigger slot. */
2101 /* Compute maximum size needed, both for inherent size
2102 and for total size. */
2105 if (spill_stack_slot[from_reg])
2107 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2109 mode = GET_MODE (spill_stack_slot[from_reg]);
2110 if (spill_stack_slot_width[from_reg] > total_size)
2111 total_size = spill_stack_slot_width[from_reg];
2112 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2113 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2116 /* Make a slot with that size. */
2117 x = assign_stack_local (mode, total_size,
2118 min_align > inherent_align
2119 || total_size > inherent_size ? -1 : 0);
2122 /* All pseudos mapped to this slot can alias each other. */
2123 if (spill_stack_slot[from_reg])
2125 alias_set_type alias_set
2126 = MEM_ALIAS_SET (spill_stack_slot[from_reg]);
2127 set_mem_alias_set (x, alias_set);
2128 dse_invalidate_singleton_alias_set (alias_set);
2132 alias_set_type alias_set = new_alias_set ();
2133 set_mem_alias_set (x, alias_set);
2134 dse_record_singleton_alias_set (alias_set, mode);
2137 if (BYTES_BIG_ENDIAN)
2139 /* Cancel the big-endian correction done in assign_stack_local.
2140 Get the address of the beginning of the slot.
2141 This is so we can do a big-endian correction unconditionally
2143 adjust = GET_MODE_SIZE (mode) - total_size;
2146 = adjust_address_nv (x, mode_for_size (total_size
2152 spill_stack_slot[from_reg] = stack_slot;
2153 spill_stack_slot_width[from_reg] = total_size;
2156 /* On a big endian machine, the "address" of the slot
2157 is the address of the low part that fits its inherent mode. */
2158 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2159 adjust += (total_size - inherent_size);
2161 /* If we have any adjustment to make, or if the stack slot is the
2162 wrong mode, make a new stack slot. */
2163 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2165 /* If we have a decl for the original register, set it for the
2166 memory. If this is a shared MEM, make a copy. */
2167 if (REG_EXPR (regno_reg_rtx[i])
2168 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2170 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2172 /* We can do this only for the DECLs home pseudo, not for
2173 any copies of it, since otherwise when the stack slot
2174 is reused, nonoverlapping_memrefs_p might think they
2176 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2178 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2181 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2185 /* Save the stack slot for later. */
2186 reg_equiv_memory_loc[i] = x;
2190 /* Mark the slots in regs_ever_live for the hard regs used by
2191 pseudo-reg number REGNO, accessed in MODE. */
2194 mark_home_live_1 (int regno, enum machine_mode mode)
2198 i = reg_renumber[regno];
2201 lim = end_hard_regno (mode, i);
2203 df_set_regs_ever_live(i++, true);
2206 /* Mark the slots in regs_ever_live for the hard regs
2207 used by pseudo-reg number REGNO. */
2210 mark_home_live (int regno)
2212 if (reg_renumber[regno] >= 0)
2213 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2216 /* This function handles the tracking of elimination offsets around branches.
2218 X is a piece of RTL being scanned.
2220 INSN is the insn that it came from, if any.
2222 INITIAL_P is nonzero if we are to set the offset to be the initial
2223 offset and zero if we are setting the offset of the label to be the
2227 set_label_offsets (rtx x, rtx insn, int initial_p)
2229 enum rtx_code code = GET_CODE (x);
2232 struct elim_table *p;
2237 if (LABEL_REF_NONLOCAL_P (x))
2242 /* ... fall through ... */
2245 /* If we know nothing about this label, set the desired offsets. Note
2246 that this sets the offset at a label to be the offset before a label
2247 if we don't know anything about the label. This is not correct for
2248 the label after a BARRIER, but is the best guess we can make. If
2249 we guessed wrong, we will suppress an elimination that might have
2250 been possible had we been able to guess correctly. */
2252 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2254 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2255 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2256 = (initial_p ? reg_eliminate[i].initial_offset
2257 : reg_eliminate[i].offset);
2258 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2261 /* Otherwise, if this is the definition of a label and it is
2262 preceded by a BARRIER, set our offsets to the known offset of
2266 && (tem = prev_nonnote_insn (insn)) != 0
2268 set_offsets_for_label (insn);
2270 /* If neither of the above cases is true, compare each offset
2271 with those previously recorded and suppress any eliminations
2272 where the offsets disagree. */
2274 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2275 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2276 != (initial_p ? reg_eliminate[i].initial_offset
2277 : reg_eliminate[i].offset))
2278 reg_eliminate[i].can_eliminate = 0;
2283 set_label_offsets (PATTERN (insn), insn, initial_p);
2285 /* ... fall through ... */
2289 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2290 to indirectly and hence must have all eliminations at their
2292 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2293 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2294 set_label_offsets (XEXP (tem, 0), insn, 1);
2300 /* Each of the labels in the parallel or address vector must be
2301 at their initial offsets. We want the first field for PARALLEL
2302 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2304 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2305 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2310 /* We only care about setting PC. If the source is not RETURN,
2311 IF_THEN_ELSE, or a label, disable any eliminations not at
2312 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2313 isn't one of those possibilities. For branches to a label,
2314 call ourselves recursively.
2316 Note that this can disable elimination unnecessarily when we have
2317 a non-local goto since it will look like a non-constant jump to
2318 someplace in the current function. This isn't a significant
2319 problem since such jumps will normally be when all elimination
2320 pairs are back to their initial offsets. */
2322 if (SET_DEST (x) != pc_rtx)
2325 switch (GET_CODE (SET_SRC (x)))
2332 set_label_offsets (SET_SRC (x), insn, initial_p);
2336 tem = XEXP (SET_SRC (x), 1);
2337 if (GET_CODE (tem) == LABEL_REF)
2338 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2339 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2342 tem = XEXP (SET_SRC (x), 2);
2343 if (GET_CODE (tem) == LABEL_REF)
2344 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2345 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2353 /* If we reach here, all eliminations must be at their initial
2354 offset because we are doing a jump to a variable address. */
2355 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2356 if (p->offset != p->initial_offset)
2357 p->can_eliminate = 0;
2365 /* Scan X and replace any eliminable registers (such as fp) with a
2366 replacement (such as sp), plus an offset.
2368 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2369 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2370 MEM, we are allowed to replace a sum of a register and the constant zero
2371 with the register, which we cannot do outside a MEM. In addition, we need
2372 to record the fact that a register is referenced outside a MEM.
2374 If INSN is an insn, it is the insn containing X. If we replace a REG
2375 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2376 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2377 the REG is being modified.
2379 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2380 That's used when we eliminate in expressions stored in notes.
2381 This means, do not set ref_outside_mem even if the reference
2384 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2385 replacements done assuming all offsets are at their initial values. If
2386 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2387 encounter, return the actual location so that find_reloads will do
2388 the proper thing. */
2391 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2392 bool may_use_invariant)
2394 enum rtx_code code = GET_CODE (x);
2395 struct elim_table *ep;
2402 if (! current_function_decl)
2425 /* First handle the case where we encounter a bare register that
2426 is eliminable. Replace it with a PLUS. */
2427 if (regno < FIRST_PSEUDO_REGISTER)
2429 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2431 if (ep->from_rtx == x && ep->can_eliminate)
2432 return plus_constant (ep->to_rtx, ep->previous_offset);
2435 else if (reg_renumber && reg_renumber[regno] < 0
2436 && reg_equiv_invariant && reg_equiv_invariant[regno])
2438 if (may_use_invariant)
2439 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2440 mem_mode, insn, true);
2441 /* There exists at least one use of REGNO that cannot be
2442 eliminated. Prevent the defining insn from being deleted. */
2443 reg_equiv_init[regno] = NULL_RTX;
2444 alter_reg (regno, -1);
2448 /* You might think handling MINUS in a manner similar to PLUS is a
2449 good idea. It is not. It has been tried multiple times and every
2450 time the change has had to have been reverted.
2452 Other parts of reload know a PLUS is special (gen_reload for example)
2453 and require special code to handle code a reloaded PLUS operand.
2455 Also consider backends where the flags register is clobbered by a
2456 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2457 lea instruction comes to mind). If we try to reload a MINUS, we
2458 may kill the flags register that was holding a useful value.
2460 So, please before trying to handle MINUS, consider reload as a
2461 whole instead of this little section as well as the backend issues. */
2463 /* If this is the sum of an eliminable register and a constant, rework
2465 if (REG_P (XEXP (x, 0))
2466 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2467 && CONSTANT_P (XEXP (x, 1)))
2469 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2471 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2473 /* The only time we want to replace a PLUS with a REG (this
2474 occurs when the constant operand of the PLUS is the negative
2475 of the offset) is when we are inside a MEM. We won't want
2476 to do so at other times because that would change the
2477 structure of the insn in a way that reload can't handle.
2478 We special-case the commonest situation in
2479 eliminate_regs_in_insn, so just replace a PLUS with a
2480 PLUS here, unless inside a MEM. */
2481 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2482 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2485 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2486 plus_constant (XEXP (x, 1),
2487 ep->previous_offset));
2490 /* If the register is not eliminable, we are done since the other
2491 operand is a constant. */
2495 /* If this is part of an address, we want to bring any constant to the
2496 outermost PLUS. We will do this by doing register replacement in
2497 our operands and seeing if a constant shows up in one of them.
2499 Note that there is no risk of modifying the structure of the insn,
2500 since we only get called for its operands, thus we are either
2501 modifying the address inside a MEM, or something like an address
2502 operand of a load-address insn. */
2505 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2506 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2508 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2510 /* If one side is a PLUS and the other side is a pseudo that
2511 didn't get a hard register but has a reg_equiv_constant,
2512 we must replace the constant here since it may no longer
2513 be in the position of any operand. */
2514 if (GET_CODE (new0) == PLUS && REG_P (new1)
2515 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2516 && reg_renumber[REGNO (new1)] < 0
2517 && reg_equiv_constant != 0
2518 && reg_equiv_constant[REGNO (new1)] != 0)
2519 new1 = reg_equiv_constant[REGNO (new1)];
2520 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2521 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2522 && reg_renumber[REGNO (new0)] < 0
2523 && reg_equiv_constant[REGNO (new0)] != 0)
2524 new0 = reg_equiv_constant[REGNO (new0)];
2526 new_rtx = form_sum (new0, new1);
2528 /* As above, if we are not inside a MEM we do not want to
2529 turn a PLUS into something else. We might try to do so here
2530 for an addition of 0 if we aren't optimizing. */
2531 if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2532 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2540 /* If this is the product of an eliminable register and a
2541 constant, apply the distribute law and move the constant out
2542 so that we have (plus (mult ..) ..). This is needed in order
2543 to keep load-address insns valid. This case is pathological.
2544 We ignore the possibility of overflow here. */
2545 if (REG_P (XEXP (x, 0))
2546 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2547 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2548 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2550 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2553 /* Refs inside notes don't count for this purpose. */
2554 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2555 || GET_CODE (insn) == INSN_LIST)))
2556 ep->ref_outside_mem = 1;
2559 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2560 ep->previous_offset * INTVAL (XEXP (x, 1)));
2563 /* ... fall through ... */
2567 /* See comments before PLUS about handling MINUS. */
2569 case DIV: case UDIV:
2570 case MOD: case UMOD:
2571 case AND: case IOR: case XOR:
2572 case ROTATERT: case ROTATE:
2573 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2575 case GE: case GT: case GEU: case GTU:
2576 case LE: case LT: case LEU: case LTU:
2578 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2579 rtx new1 = XEXP (x, 1)
2580 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2582 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2583 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2588 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2591 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2592 if (new_rtx != XEXP (x, 0))
2594 /* If this is a REG_DEAD note, it is not valid anymore.
2595 Using the eliminated version could result in creating a
2596 REG_DEAD note for the stack or frame pointer. */
2597 if (GET_MODE (x) == REG_DEAD)
2599 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2602 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2606 /* ... fall through ... */
2609 /* Now do eliminations in the rest of the chain. If this was
2610 an EXPR_LIST, this might result in allocating more memory than is
2611 strictly needed, but it simplifies the code. */
2614 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2615 if (new_rtx != XEXP (x, 1))
2617 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2625 /* We do not support elimination of a register that is modified.
2626 elimination_effects has already make sure that this does not
2632 /* We do not support elimination of a register that is modified.
2633 elimination_effects has already make sure that this does not
2634 happen. The only remaining case we need to consider here is
2635 that the increment value may be an eliminable register. */
2636 if (GET_CODE (XEXP (x, 1)) == PLUS
2637 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2639 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2642 if (new_rtx != XEXP (XEXP (x, 1), 1))
2643 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2644 gen_rtx_PLUS (GET_MODE (x),
2645 XEXP (x, 0), new_rtx));
2649 case STRICT_LOW_PART:
2651 case SIGN_EXTEND: case ZERO_EXTEND:
2652 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2653 case FLOAT: case FIX:
2654 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2663 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2664 if (new_rtx != XEXP (x, 0))
2665 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2669 /* Similar to above processing, but preserve SUBREG_BYTE.
2670 Convert (subreg (mem)) to (mem) if not paradoxical.
2671 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2672 pseudo didn't get a hard reg, we must replace this with the
2673 eliminated version of the memory location because push_reload
2674 may do the replacement in certain circumstances. */
2675 if (REG_P (SUBREG_REG (x))
2676 && (GET_MODE_SIZE (GET_MODE (x))
2677 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2678 && reg_equiv_memory_loc != 0
2679 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2681 new_rtx = SUBREG_REG (x);
2684 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2686 if (new_rtx != SUBREG_REG (x))
2688 int x_size = GET_MODE_SIZE (GET_MODE (x));
2689 int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2692 && ((x_size < new_size
2693 #ifdef WORD_REGISTER_OPERATIONS
2694 /* On these machines, combine can create rtl of the form
2695 (set (subreg:m1 (reg:m2 R) 0) ...)
2696 where m1 < m2, and expects something interesting to
2697 happen to the entire word. Moreover, it will use the
2698 (reg:m2 R) later, expecting all bits to be preserved.
2699 So if the number of words is the same, preserve the
2700 subreg so that push_reload can see it. */
2701 && ! ((x_size - 1) / UNITS_PER_WORD
2702 == (new_size -1 ) / UNITS_PER_WORD)
2705 || x_size == new_size)
2707 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2709 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2715 /* Our only special processing is to pass the mode of the MEM to our
2716 recursive call and copy the flags. While we are here, handle this
2717 case more efficiently. */
2719 replace_equiv_address_nv (x,
2720 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2724 /* Handle insn_list USE that a call to a pure function may generate. */
2725 new_rtx = eliminate_regs_1 (XEXP (x, 0), 0, insn, false);
2726 if (new_rtx != XEXP (x, 0))
2727 return gen_rtx_USE (GET_MODE (x), new_rtx);
2739 /* Process each of our operands recursively. If any have changed, make a
2741 fmt = GET_RTX_FORMAT (code);
2742 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2746 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2747 if (new_rtx != XEXP (x, i) && ! copied)
2749 x = shallow_copy_rtx (x);
2752 XEXP (x, i) = new_rtx;
2754 else if (*fmt == 'E')
2757 for (j = 0; j < XVECLEN (x, i); j++)
2759 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2760 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2762 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2766 x = shallow_copy_rtx (x);
2769 XVEC (x, i) = new_v;
2772 XVECEXP (x, i, j) = new_rtx;
2781 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2783 return eliminate_regs_1 (x, mem_mode, insn, false);
2786 /* Scan rtx X for modifications of elimination target registers. Update
2787 the table of eliminables to reflect the changed state. MEM_MODE is
2788 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2791 elimination_effects (rtx x, enum machine_mode mem_mode)
2793 enum rtx_code code = GET_CODE (x);
2794 struct elim_table *ep;
2819 /* First handle the case where we encounter a bare register that
2820 is eliminable. Replace it with a PLUS. */
2821 if (regno < FIRST_PSEUDO_REGISTER)
2823 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2825 if (ep->from_rtx == x && ep->can_eliminate)
2828 ep->ref_outside_mem = 1;
2833 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2834 && reg_equiv_constant[regno]
2835 && ! function_invariant_p (reg_equiv_constant[regno]))
2836 elimination_effects (reg_equiv_constant[regno], mem_mode);
2845 /* If we modify the source of an elimination rule, disable it. */
2846 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2847 if (ep->from_rtx == XEXP (x, 0))
2848 ep->can_eliminate = 0;
2850 /* If we modify the target of an elimination rule by adding a constant,
2851 update its offset. If we modify the target in any other way, we'll
2852 have to disable the rule as well. */
2853 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2854 if (ep->to_rtx == XEXP (x, 0))
2856 int size = GET_MODE_SIZE (mem_mode);
2858 /* If more bytes than MEM_MODE are pushed, account for them. */
2859 #ifdef PUSH_ROUNDING
2860 if (ep->to_rtx == stack_pointer_rtx)
2861 size = PUSH_ROUNDING (size);
2863 if (code == PRE_DEC || code == POST_DEC)
2865 else if (code == PRE_INC || code == POST_INC)
2867 else if (code == PRE_MODIFY || code == POST_MODIFY)
2869 if (GET_CODE (XEXP (x, 1)) == PLUS
2870 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2871 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
2872 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2874 ep->can_eliminate = 0;
2878 /* These two aren't unary operators. */
2879 if (code == POST_MODIFY || code == PRE_MODIFY)
2882 /* Fall through to generic unary operation case. */
2883 case STRICT_LOW_PART:
2885 case SIGN_EXTEND: case ZERO_EXTEND:
2886 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2887 case FLOAT: case FIX:
2888 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2897 elimination_effects (XEXP (x, 0), mem_mode);
2901 if (REG_P (SUBREG_REG (x))
2902 && (GET_MODE_SIZE (GET_MODE (x))
2903 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2904 && reg_equiv_memory_loc != 0
2905 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2908 elimination_effects (SUBREG_REG (x), mem_mode);
2912 /* If using a register that is the source of an eliminate we still
2913 think can be performed, note it cannot be performed since we don't
2914 know how this register is used. */
2915 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2916 if (ep->from_rtx == XEXP (x, 0))
2917 ep->can_eliminate = 0;
2919 elimination_effects (XEXP (x, 0), mem_mode);
2923 /* If clobbering a register that is the replacement register for an
2924 elimination we still think can be performed, note that it cannot
2925 be performed. Otherwise, we need not be concerned about it. */
2926 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2927 if (ep->to_rtx == XEXP (x, 0))
2928 ep->can_eliminate = 0;
2930 elimination_effects (XEXP (x, 0), mem_mode);
2934 /* Check for setting a register that we know about. */
2935 if (REG_P (SET_DEST (x)))
2937 /* See if this is setting the replacement register for an
2940 If DEST is the hard frame pointer, we do nothing because we
2941 assume that all assignments to the frame pointer are for
2942 non-local gotos and are being done at a time when they are valid
2943 and do not disturb anything else. Some machines want to
2944 eliminate a fake argument pointer (or even a fake frame pointer)
2945 with either the real frame or the stack pointer. Assignments to
2946 the hard frame pointer must not prevent this elimination. */
2948 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2950 if (ep->to_rtx == SET_DEST (x)
2951 && SET_DEST (x) != hard_frame_pointer_rtx)
2953 /* If it is being incremented, adjust the offset. Otherwise,
2954 this elimination can't be done. */
2955 rtx src = SET_SRC (x);
2957 if (GET_CODE (src) == PLUS
2958 && XEXP (src, 0) == SET_DEST (x)
2959 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2960 ep->offset -= INTVAL (XEXP (src, 1));
2962 ep->can_eliminate = 0;
2966 elimination_effects (SET_DEST (x), 0);
2967 elimination_effects (SET_SRC (x), 0);
2971 /* Our only special processing is to pass the mode of the MEM to our
2973 elimination_effects (XEXP (x, 0), GET_MODE (x));
2980 fmt = GET_RTX_FORMAT (code);
2981 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2984 elimination_effects (XEXP (x, i), mem_mode);
2985 else if (*fmt == 'E')
2986 for (j = 0; j < XVECLEN (x, i); j++)
2987 elimination_effects (XVECEXP (x, i, j), mem_mode);
2991 /* Descend through rtx X and verify that no references to eliminable registers
2992 remain. If any do remain, mark the involved register as not
2996 check_eliminable_occurrences (rtx x)
3005 code = GET_CODE (x);
3007 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3009 struct elim_table *ep;
3011 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3012 if (ep->from_rtx == x)
3013 ep->can_eliminate = 0;
3017 fmt = GET_RTX_FORMAT (code);
3018 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3021 check_eliminable_occurrences (XEXP (x, i));
3022 else if (*fmt == 'E')
3025 for (j = 0; j < XVECLEN (x, i); j++)
3026 check_eliminable_occurrences (XVECEXP (x, i, j));
3031 /* Scan INSN and eliminate all eliminable registers in it.
3033 If REPLACE is nonzero, do the replacement destructively. Also
3034 delete the insn as dead it if it is setting an eliminable register.
3036 If REPLACE is zero, do all our allocations in reload_obstack.
3038 If no eliminations were done and this insn doesn't require any elimination
3039 processing (these are not identical conditions: it might be updating sp,
3040 but not referencing fp; this needs to be seen during reload_as_needed so
3041 that the offset between fp and sp can be taken into consideration), zero
3042 is returned. Otherwise, 1 is returned. */
3045 eliminate_regs_in_insn (rtx insn, int replace)
3047 int icode = recog_memoized (insn);
3048 rtx old_body = PATTERN (insn);
3049 int insn_is_asm = asm_noperands (old_body) >= 0;
3050 rtx old_set = single_set (insn);
3054 rtx substed_operand[MAX_RECOG_OPERANDS];
3055 rtx orig_operand[MAX_RECOG_OPERANDS];
3056 struct elim_table *ep;
3057 rtx plus_src, plus_cst_src;
3059 if (! insn_is_asm && icode < 0)
3061 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3062 || GET_CODE (PATTERN (insn)) == CLOBBER
3063 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3064 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3065 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3069 if (old_set != 0 && REG_P (SET_DEST (old_set))
3070 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3072 /* Check for setting an eliminable register. */
3073 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3074 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3076 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3077 /* If this is setting the frame pointer register to the
3078 hardware frame pointer register and this is an elimination
3079 that will be done (tested above), this insn is really
3080 adjusting the frame pointer downward to compensate for
3081 the adjustment done before a nonlocal goto. */
3082 if (ep->from == FRAME_POINTER_REGNUM
3083 && ep->to == HARD_FRAME_POINTER_REGNUM)
3085 rtx base = SET_SRC (old_set);
3086 rtx base_insn = insn;
3087 HOST_WIDE_INT offset = 0;
3089 while (base != ep->to_rtx)
3091 rtx prev_insn, prev_set;
3093 if (GET_CODE (base) == PLUS
3094 && GET_CODE (XEXP (base, 1)) == CONST_INT)
3096 offset += INTVAL (XEXP (base, 1));
3097 base = XEXP (base, 0);
3099 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3100 && (prev_set = single_set (prev_insn)) != 0
3101 && rtx_equal_p (SET_DEST (prev_set), base))
3103 base = SET_SRC (prev_set);
3104 base_insn = prev_insn;
3110 if (base == ep->to_rtx)
3113 = plus_constant (ep->to_rtx, offset - ep->offset);
3115 new_body = old_body;
3118 new_body = copy_insn (old_body);
3119 if (REG_NOTES (insn))
3120 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3122 PATTERN (insn) = new_body;
3123 old_set = single_set (insn);
3125 /* First see if this insn remains valid when we
3126 make the change. If not, keep the INSN_CODE
3127 the same and let reload fit it up. */
3128 validate_change (insn, &SET_SRC (old_set), src, 1);
3129 validate_change (insn, &SET_DEST (old_set),
3131 if (! apply_change_group ())
3133 SET_SRC (old_set) = src;
3134 SET_DEST (old_set) = ep->to_rtx;
3143 /* In this case this insn isn't serving a useful purpose. We
3144 will delete it in reload_as_needed once we know that this
3145 elimination is, in fact, being done.
3147 If REPLACE isn't set, we can't delete this insn, but needn't
3148 process it since it won't be used unless something changes. */
3151 delete_dead_insn (insn);
3159 /* We allow one special case which happens to work on all machines we
3160 currently support: a single set with the source or a REG_EQUAL
3161 note being a PLUS of an eliminable register and a constant. */
3162 plus_src = plus_cst_src = 0;
3163 if (old_set && REG_P (SET_DEST (old_set)))
3165 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3166 plus_src = SET_SRC (old_set);
3167 /* First see if the source is of the form (plus (...) CST). */
3169 && GET_CODE (XEXP (plus_src, 1)) == CONST_INT)
3170 plus_cst_src = plus_src;
3171 else if (REG_P (SET_SRC (old_set))
3174 /* Otherwise, see if we have a REG_EQUAL note of the form
3175 (plus (...) CST). */
3177 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3179 if ((REG_NOTE_KIND (links) == REG_EQUAL
3180 || REG_NOTE_KIND (links) == REG_EQUIV)
3181 && GET_CODE (XEXP (links, 0)) == PLUS
3182 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT)
3184 plus_cst_src = XEXP (links, 0);
3190 /* Check that the first operand of the PLUS is a hard reg or
3191 the lowpart subreg of one. */
3194 rtx reg = XEXP (plus_cst_src, 0);
3195 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3196 reg = SUBREG_REG (reg);
3198 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3204 rtx reg = XEXP (plus_cst_src, 0);
3205 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3207 if (GET_CODE (reg) == SUBREG)
3208 reg = SUBREG_REG (reg);
3210 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3211 if (ep->from_rtx == reg && ep->can_eliminate)
3213 rtx to_rtx = ep->to_rtx;
3214 offset += ep->offset;
3215 offset = trunc_int_for_mode (offset, GET_MODE (reg));
3217 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3218 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3220 /* If we have a nonzero offset, and the source is already
3221 a simple REG, the following transformation would
3222 increase the cost of the insn by replacing a simple REG
3223 with (plus (reg sp) CST). So try only when we already
3224 had a PLUS before. */
3225 if (offset == 0 || plus_src)
3227 rtx new_src = plus_constant (to_rtx, offset);
3229 new_body = old_body;
3232 new_body = copy_insn (old_body);
3233 if (REG_NOTES (insn))
3234 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3236 PATTERN (insn) = new_body;
3237 old_set = single_set (insn);
3239 /* First see if this insn remains valid when we make the
3240 change. If not, try to replace the whole pattern with
3241 a simple set (this may help if the original insn was a
3242 PARALLEL that was only recognized as single_set due to
3243 REG_UNUSED notes). If this isn't valid either, keep
3244 the INSN_CODE the same and let reload fix it up. */
3245 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3247 rtx new_pat = gen_rtx_SET (VOIDmode,
3248 SET_DEST (old_set), new_src);
3250 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3251 SET_SRC (old_set) = new_src;
3258 /* This can't have an effect on elimination offsets, so skip right
3264 /* Determine the effects of this insn on elimination offsets. */
3265 elimination_effects (old_body, 0);
3267 /* Eliminate all eliminable registers occurring in operands that
3268 can be handled by reload. */
3269 extract_insn (insn);
3270 for (i = 0; i < recog_data.n_operands; i++)
3272 orig_operand[i] = recog_data.operand[i];
3273 substed_operand[i] = recog_data.operand[i];
3275 /* For an asm statement, every operand is eliminable. */
3276 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3278 bool is_set_src, in_plus;
3280 /* Check for setting a register that we know about. */
3281 if (recog_data.operand_type[i] != OP_IN
3282 && REG_P (orig_operand[i]))
3284 /* If we are assigning to a register that can be eliminated, it
3285 must be as part of a PARALLEL, since the code above handles
3286 single SETs. We must indicate that we can no longer
3287 eliminate this reg. */
3288 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3290 if (ep->from_rtx == orig_operand[i])
3291 ep->can_eliminate = 0;
3294 /* Companion to the above plus substitution, we can allow
3295 invariants as the source of a plain move. */
3297 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3301 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3302 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3306 = eliminate_regs_1 (recog_data.operand[i], 0,
3307 replace ? insn : NULL_RTX,
3308 is_set_src || in_plus);
3309 if (substed_operand[i] != orig_operand[i])
3311 /* Terminate the search in check_eliminable_occurrences at
3313 *recog_data.operand_loc[i] = 0;
3315 /* If an output operand changed from a REG to a MEM and INSN is an
3316 insn, write a CLOBBER insn. */
3317 if (recog_data.operand_type[i] != OP_IN
3318 && REG_P (orig_operand[i])
3319 && MEM_P (substed_operand[i])
3321 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3325 for (i = 0; i < recog_data.n_dups; i++)
3326 *recog_data.dup_loc[i]
3327 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3329 /* If any eliminable remain, they aren't eliminable anymore. */
3330 check_eliminable_occurrences (old_body);
3332 /* Substitute the operands; the new values are in the substed_operand
3334 for (i = 0; i < recog_data.n_operands; i++)
3335 *recog_data.operand_loc[i] = substed_operand[i];
3336 for (i = 0; i < recog_data.n_dups; i++)
3337 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3339 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3340 re-recognize the insn. We do this in case we had a simple addition
3341 but now can do this as a load-address. This saves an insn in this
3343 If re-recognition fails, the old insn code number will still be used,
3344 and some register operands may have changed into PLUS expressions.
3345 These will be handled by find_reloads by loading them into a register
3350 /* If we aren't replacing things permanently and we changed something,
3351 make another copy to ensure that all the RTL is new. Otherwise
3352 things can go wrong if find_reload swaps commutative operands
3353 and one is inside RTL that has been copied while the other is not. */
3354 new_body = old_body;
3357 new_body = copy_insn (old_body);
3358 if (REG_NOTES (insn))
3359 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3361 PATTERN (insn) = new_body;
3363 /* If we had a move insn but now we don't, rerecognize it. This will
3364 cause spurious re-recognition if the old move had a PARALLEL since
3365 the new one still will, but we can't call single_set without
3366 having put NEW_BODY into the insn and the re-recognition won't
3367 hurt in this rare case. */
3368 /* ??? Why this huge if statement - why don't we just rerecognize the
3372 && ((REG_P (SET_SRC (old_set))
3373 && (GET_CODE (new_body) != SET
3374 || !REG_P (SET_SRC (new_body))))
3375 /* If this was a load from or store to memory, compare
3376 the MEM in recog_data.operand to the one in the insn.
3377 If they are not equal, then rerecognize the insn. */
3379 && ((MEM_P (SET_SRC (old_set))
3380 && SET_SRC (old_set) != recog_data.operand[1])
3381 || (MEM_P (SET_DEST (old_set))
3382 && SET_DEST (old_set) != recog_data.operand[0])))
3383 /* If this was an add insn before, rerecognize. */
3384 || GET_CODE (SET_SRC (old_set)) == PLUS))
3386 int new_icode = recog (PATTERN (insn), insn, 0);
3388 INSN_CODE (insn) = new_icode;
3392 /* Restore the old body. If there were any changes to it, we made a copy
3393 of it while the changes were still in place, so we'll correctly return
3394 a modified insn below. */
3397 /* Restore the old body. */
3398 for (i = 0; i < recog_data.n_operands; i++)
3399 *recog_data.operand_loc[i] = orig_operand[i];
3400 for (i = 0; i < recog_data.n_dups; i++)
3401 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3404 /* Update all elimination pairs to reflect the status after the current
3405 insn. The changes we make were determined by the earlier call to
3406 elimination_effects.
3408 We also detect cases where register elimination cannot be done,
3409 namely, if a register would be both changed and referenced outside a MEM
3410 in the resulting insn since such an insn is often undefined and, even if
3411 not, we cannot know what meaning will be given to it. Note that it is
3412 valid to have a register used in an address in an insn that changes it
3413 (presumably with a pre- or post-increment or decrement).
3415 If anything changes, return nonzero. */
3417 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3419 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3420 ep->can_eliminate = 0;
3422 ep->ref_outside_mem = 0;
3424 if (ep->previous_offset != ep->offset)
3429 /* If we changed something, perform elimination in REG_NOTES. This is
3430 needed even when REPLACE is zero because a REG_DEAD note might refer
3431 to a register that we eliminate and could cause a different number
3432 of spill registers to be needed in the final reload pass than in
3434 if (val && REG_NOTES (insn) != 0)
3436 = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true);
3441 /* Loop through all elimination pairs.
3442 Recalculate the number not at initial offset.
3444 Compute the maximum offset (minimum offset if the stack does not
3445 grow downward) for each elimination pair. */
3448 update_eliminable_offsets (void)
3450 struct elim_table *ep;
3452 num_not_at_initial_offset = 0;
3453 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3455 ep->previous_offset = ep->offset;
3456 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3457 num_not_at_initial_offset++;
3461 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3462 replacement we currently believe is valid, mark it as not eliminable if X
3463 modifies DEST in any way other than by adding a constant integer to it.
3465 If DEST is the frame pointer, we do nothing because we assume that
3466 all assignments to the hard frame pointer are nonlocal gotos and are being
3467 done at a time when they are valid and do not disturb anything else.
3468 Some machines want to eliminate a fake argument pointer with either the
3469 frame or stack pointer. Assignments to the hard frame pointer must not
3470 prevent this elimination.
3472 Called via note_stores from reload before starting its passes to scan
3473 the insns of the function. */
3476 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3480 /* A SUBREG of a hard register here is just changing its mode. We should
3481 not see a SUBREG of an eliminable hard register, but check just in
3483 if (GET_CODE (dest) == SUBREG)
3484 dest = SUBREG_REG (dest);
3486 if (dest == hard_frame_pointer_rtx)
3489 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3490 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3491 && (GET_CODE (x) != SET
3492 || GET_CODE (SET_SRC (x)) != PLUS
3493 || XEXP (SET_SRC (x), 0) != dest
3494 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3496 reg_eliminate[i].can_eliminate_previous
3497 = reg_eliminate[i].can_eliminate = 0;
3502 /* Verify that the initial elimination offsets did not change since the
3503 last call to set_initial_elim_offsets. This is used to catch cases
3504 where something illegal happened during reload_as_needed that could
3505 cause incorrect code to be generated if we did not check for it. */
3508 verify_initial_elim_offsets (void)
3512 if (!num_eliminable)
3515 #ifdef ELIMINABLE_REGS
3517 struct elim_table *ep;
3519 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3521 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3522 if (t != ep->initial_offset)
3527 INITIAL_FRAME_POINTER_OFFSET (t);
3528 if (t != reg_eliminate[0].initial_offset)
3535 /* Reset all offsets on eliminable registers to their initial values. */
3538 set_initial_elim_offsets (void)
3540 struct elim_table *ep = reg_eliminate;
3542 #ifdef ELIMINABLE_REGS
3543 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3545 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3546 ep->previous_offset = ep->offset = ep->initial_offset;
3549 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3550 ep->previous_offset = ep->offset = ep->initial_offset;
3553 num_not_at_initial_offset = 0;
3556 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3559 set_initial_eh_label_offset (rtx label)
3561 set_label_offsets (label, NULL_RTX, 1);
3564 /* Initialize the known label offsets.
3565 Set a known offset for each forced label to be at the initial offset
3566 of each elimination. We do this because we assume that all
3567 computed jumps occur from a location where each elimination is
3568 at its initial offset.
3569 For all other labels, show that we don't know the offsets. */
3572 set_initial_label_offsets (void)
3575 memset (offsets_known_at, 0, num_labels);
3577 for (x = forced_labels; x; x = XEXP (x, 1))
3579 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3581 for_each_eh_label (set_initial_eh_label_offset);
3584 /* Set all elimination offsets to the known values for the code label given
3588 set_offsets_for_label (rtx insn)
3591 int label_nr = CODE_LABEL_NUMBER (insn);
3592 struct elim_table *ep;
3594 num_not_at_initial_offset = 0;
3595 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3597 ep->offset = ep->previous_offset
3598 = offsets_at[label_nr - first_label_num][i];
3599 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3600 num_not_at_initial_offset++;
3604 /* See if anything that happened changes which eliminations are valid.
3605 For example, on the SPARC, whether or not the frame pointer can
3606 be eliminated can depend on what registers have been used. We need
3607 not check some conditions again (such as flag_omit_frame_pointer)
3608 since they can't have changed. */
3611 update_eliminables (HARD_REG_SET *pset)
3613 int previous_frame_pointer_needed = frame_pointer_needed;
3614 struct elim_table *ep;
3616 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3617 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3618 #ifdef ELIMINABLE_REGS
3619 || ! CAN_ELIMINATE (ep->from, ep->to)
3622 ep->can_eliminate = 0;
3624 /* Look for the case where we have discovered that we can't replace
3625 register A with register B and that means that we will now be
3626 trying to replace register A with register C. This means we can
3627 no longer replace register C with register B and we need to disable
3628 such an elimination, if it exists. This occurs often with A == ap,
3629 B == sp, and C == fp. */
3631 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3633 struct elim_table *op;
3636 if (! ep->can_eliminate && ep->can_eliminate_previous)
3638 /* Find the current elimination for ep->from, if there is a
3640 for (op = reg_eliminate;
3641 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3642 if (op->from == ep->from && op->can_eliminate)
3648 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3650 for (op = reg_eliminate;
3651 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3652 if (op->from == new_to && op->to == ep->to)
3653 op->can_eliminate = 0;
3657 /* See if any registers that we thought we could eliminate the previous
3658 time are no longer eliminable. If so, something has changed and we
3659 must spill the register. Also, recompute the number of eliminable
3660 registers and see if the frame pointer is needed; it is if there is
3661 no elimination of the frame pointer that we can perform. */
3663 frame_pointer_needed = 1;
3664 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3666 if (ep->can_eliminate
3667 && ep->from == FRAME_POINTER_REGNUM
3668 && ep->to != HARD_FRAME_POINTER_REGNUM
3669 && (! SUPPORTS_STACK_ALIGNMENT
3670 || ! crtl->stack_realign_needed))
3671 frame_pointer_needed = 0;
3673 if (! ep->can_eliminate && ep->can_eliminate_previous)
3675 ep->can_eliminate_previous = 0;
3676 SET_HARD_REG_BIT (*pset, ep->from);
3681 /* If we didn't need a frame pointer last time, but we do now, spill
3682 the hard frame pointer. */
3683 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3684 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3687 /* Return true if X is used as the target register of an elimination. */
3690 elimination_target_reg_p (rtx x)
3692 struct elim_table *ep;
3694 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3695 if (ep->to_rtx == x && ep->can_eliminate)
3701 /* Initialize the table of registers to eliminate.
3702 Pre-condition: global flag frame_pointer_needed has been set before
3703 calling this function. */
3706 init_elim_table (void)
3708 struct elim_table *ep;
3709 #ifdef ELIMINABLE_REGS
3710 const struct elim_table_1 *ep1;
3714 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
3718 #ifdef ELIMINABLE_REGS
3719 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3720 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3722 ep->from = ep1->from;
3724 ep->can_eliminate = ep->can_eliminate_previous
3725 = (CAN_ELIMINATE (ep->from, ep->to)
3726 && ! (ep->to == STACK_POINTER_REGNUM
3727 && frame_pointer_needed
3728 && (! SUPPORTS_STACK_ALIGNMENT
3729 || ! stack_realign_fp)));
3732 reg_eliminate[0].from = reg_eliminate_1[0].from;
3733 reg_eliminate[0].to = reg_eliminate_1[0].to;
3734 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3735 = ! frame_pointer_needed;
3738 /* Count the number of eliminable registers and build the FROM and TO
3739 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3740 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3741 We depend on this. */
3742 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3744 num_eliminable += ep->can_eliminate;
3745 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3746 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3750 /* Kick all pseudos out of hard register REGNO.
3752 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3753 because we found we can't eliminate some register. In the case, no pseudos
3754 are allowed to be in the register, even if they are only in a block that
3755 doesn't require spill registers, unlike the case when we are spilling this
3756 hard reg to produce another spill register.
3758 Return nonzero if any pseudos needed to be kicked out. */
3761 spill_hard_reg (unsigned int regno, int cant_eliminate)
3767 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3768 df_set_regs_ever_live (regno, true);
3771 /* Spill every pseudo reg that was allocated to this reg
3772 or to something that overlaps this reg. */
3774 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3775 if (reg_renumber[i] >= 0
3776 && (unsigned int) reg_renumber[i] <= regno
3777 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
3778 SET_REGNO_REG_SET (&spilled_pseudos, i);
3781 /* After find_reload_regs has been run for all insn that need reloads,
3782 and/or spill_hard_regs was called, this function is used to actually
3783 spill pseudo registers and try to reallocate them. It also sets up the
3784 spill_regs array for use by choose_reload_regs. */
3787 finish_spills (int global)
3789 struct insn_chain *chain;
3790 int something_changed = 0;
3792 reg_set_iterator rsi;
3794 /* Build the spill_regs array for the function. */
3795 /* If there are some registers still to eliminate and one of the spill regs
3796 wasn't ever used before, additional stack space may have to be
3797 allocated to store this register. Thus, we may have changed the offset
3798 between the stack and frame pointers, so mark that something has changed.
3800 One might think that we need only set VAL to 1 if this is a call-used
3801 register. However, the set of registers that must be saved by the
3802 prologue is not identical to the call-used set. For example, the
3803 register used by the call insn for the return PC is a call-used register,
3804 but must be saved by the prologue. */
3807 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3808 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3810 spill_reg_order[i] = n_spills;
3811 spill_regs[n_spills++] = i;
3812 if (num_eliminable && ! df_regs_ever_live_p (i))
3813 something_changed = 1;
3814 df_set_regs_ever_live (i, true);
3817 spill_reg_order[i] = -1;
3819 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3821 /* Record the current hard register the pseudo is allocated to in
3822 pseudo_previous_regs so we avoid reallocating it to the same
3823 hard reg in a later pass. */
3824 gcc_assert (reg_renumber[i] >= 0);
3826 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3827 /* Mark it as no longer having a hard register home. */
3828 reg_renumber[i] = -1;
3829 /* We will need to scan everything again. */
3830 something_changed = 1;
3833 /* Retry global register allocation if possible. */
3836 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3837 /* For every insn that needs reloads, set the registers used as spill
3838 regs in pseudo_forbidden_regs for every pseudo live across the
3840 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3842 EXECUTE_IF_SET_IN_REG_SET
3843 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3845 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3846 chain->used_spill_regs);
3848 EXECUTE_IF_SET_IN_REG_SET
3849 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3851 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3852 chain->used_spill_regs);
3856 /* Retry allocating the spilled pseudos. For each reg, merge the
3857 various reg sets that indicate which hard regs can't be used,
3858 and call retry_global_alloc.
3859 We change spill_pseudos here to only contain pseudos that did not
3860 get a new hard register. */
3861 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3862 if (reg_old_renumber[i] != reg_renumber[i])
3864 HARD_REG_SET forbidden;
3865 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3866 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3867 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3868 retry_global_alloc (i, forbidden);
3869 if (reg_renumber[i] >= 0)
3870 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3874 /* Fix up the register information in the insn chain.
3875 This involves deleting those of the spilled pseudos which did not get
3876 a new hard register home from the live_{before,after} sets. */
3877 for (chain = reload_insn_chain; chain; chain = chain->next)
3879 HARD_REG_SET used_by_pseudos;
3880 HARD_REG_SET used_by_pseudos2;
3882 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3883 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3885 /* Mark any unallocated hard regs as available for spills. That
3886 makes inheritance work somewhat better. */
3887 if (chain->need_reload)
3889 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3890 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3891 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3893 /* Save the old value for the sanity test below. */
3894 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3896 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3897 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3898 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3899 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3901 /* Make sure we only enlarge the set. */
3902 gcc_assert (hard_reg_set_subset_p (used_by_pseudos2,
3903 chain->used_spill_regs));
3907 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3908 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3910 int regno = reg_renumber[i];
3911 if (reg_old_renumber[i] == regno)
3914 alter_reg (i, reg_old_renumber[i]);
3915 reg_old_renumber[i] = regno;
3919 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3921 fprintf (dump_file, " Register %d now in %d.\n\n",
3922 i, reg_renumber[i]);
3926 return something_changed;
3929 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3932 scan_paradoxical_subregs (rtx x)
3936 enum rtx_code code = GET_CODE (x);
3947 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3955 if (REG_P (SUBREG_REG (x))
3956 && (GET_MODE_SIZE (GET_MODE (x))
3957 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
3959 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3960 = GET_MODE_SIZE (GET_MODE (x));
3961 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
3969 fmt = GET_RTX_FORMAT (code);
3970 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3973 scan_paradoxical_subregs (XEXP (x, i));
3974 else if (fmt[i] == 'E')
3977 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3978 scan_paradoxical_subregs (XVECEXP (x, i, j));
3983 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
3984 examine all of the reload insns between PREV and NEXT exclusive, and
3985 annotate all that may trap. */
3988 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
3990 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
3991 unsigned int trap_count;
3997 if (may_trap_p (PATTERN (insn)))
4001 remove_note (insn, note);
4005 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
4006 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
4009 add_reg_note (i, REG_EH_REGION, XEXP (note, 0));
4013 /* Reload pseudo-registers into hard regs around each insn as needed.
4014 Additional register load insns are output before the insn that needs it
4015 and perhaps store insns after insns that modify the reloaded pseudo reg.
4017 reg_last_reload_reg and reg_reloaded_contents keep track of
4018 which registers are already available in reload registers.
4019 We update these for the reloads that we perform,
4020 as the insns are scanned. */
4023 reload_as_needed (int live_known)
4025 struct insn_chain *chain;
4026 #if defined (AUTO_INC_DEC)
4031 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4032 memset (spill_reg_store, 0, sizeof spill_reg_store);
4033 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4034 INIT_REG_SET (®_has_output_reload);
4035 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4036 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4038 set_initial_elim_offsets ();
4040 for (chain = reload_insn_chain; chain; chain = chain->next)
4043 rtx insn = chain->insn;
4044 rtx old_next = NEXT_INSN (insn);
4046 /* If we pass a label, copy the offsets from the label information
4047 into the current offsets of each elimination. */
4049 set_offsets_for_label (insn);
4051 else if (INSN_P (insn))
4053 regset_head regs_to_forget;
4054 INIT_REG_SET (®s_to_forget);
4055 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4057 /* If this is a USE and CLOBBER of a MEM, ensure that any
4058 references to eliminable registers have been removed. */
4060 if ((GET_CODE (PATTERN (insn)) == USE
4061 || GET_CODE (PATTERN (insn)) == CLOBBER)
4062 && MEM_P (XEXP (PATTERN (insn), 0)))
4063 XEXP (XEXP (PATTERN (insn), 0), 0)
4064 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4065 GET_MODE (XEXP (PATTERN (insn), 0)),
4068 /* If we need to do register elimination processing, do so.
4069 This might delete the insn, in which case we are done. */
4070 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4072 eliminate_regs_in_insn (insn, 1);
4075 update_eliminable_offsets ();
4076 CLEAR_REG_SET (®s_to_forget);
4081 /* If need_elim is nonzero but need_reload is zero, one might think
4082 that we could simply set n_reloads to 0. However, find_reloads
4083 could have done some manipulation of the insn (such as swapping
4084 commutative operands), and these manipulations are lost during
4085 the first pass for every insn that needs register elimination.
4086 So the actions of find_reloads must be redone here. */
4088 if (! chain->need_elim && ! chain->need_reload
4089 && ! chain->need_operand_change)
4091 /* First find the pseudo regs that must be reloaded for this insn.
4092 This info is returned in the tables reload_... (see reload.h).
4093 Also modify the body of INSN by substituting RELOAD
4094 rtx's for those pseudo regs. */
4097 CLEAR_REG_SET (®_has_output_reload);
4098 CLEAR_HARD_REG_SET (reg_is_output_reload);
4100 find_reloads (insn, 1, spill_indirect_levels, live_known,
4106 rtx next = NEXT_INSN (insn);
4109 prev = PREV_INSN (insn);
4111 /* Now compute which reload regs to reload them into. Perhaps
4112 reusing reload regs from previous insns, or else output
4113 load insns to reload them. Maybe output store insns too.
4114 Record the choices of reload reg in reload_reg_rtx. */
4115 choose_reload_regs (chain);
4117 /* Merge any reloads that we didn't combine for fear of
4118 increasing the number of spill registers needed but now
4119 discover can be safely merged. */
4120 if (SMALL_REGISTER_CLASSES)
4121 merge_assigned_reloads (insn);
4123 /* Generate the insns to reload operands into or out of
4124 their reload regs. */
4125 emit_reload_insns (chain);
4127 /* Substitute the chosen reload regs from reload_reg_rtx
4128 into the insn's body (or perhaps into the bodies of other
4129 load and store insn that we just made for reloading
4130 and that we moved the structure into). */
4131 subst_reloads (insn);
4133 /* Adjust the exception region notes for loads and stores. */
4134 if (flag_non_call_exceptions && !CALL_P (insn))
4135 fixup_eh_region_note (insn, prev, next);
4137 /* If this was an ASM, make sure that all the reload insns
4138 we have generated are valid. If not, give an error
4140 if (asm_noperands (PATTERN (insn)) >= 0)
4141 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4142 if (p != insn && INSN_P (p)
4143 && GET_CODE (PATTERN (p)) != USE
4144 && (recog_memoized (p) < 0
4145 || (extract_insn (p), ! constrain_operands (1))))
4147 error_for_asm (insn,
4148 "%<asm%> operand requires "
4149 "impossible reload");
4154 if (num_eliminable && chain->need_elim)
4155 update_eliminable_offsets ();
4157 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4158 is no longer validly lying around to save a future reload.
4159 Note that this does not detect pseudos that were reloaded
4160 for this insn in order to be stored in
4161 (obeying register constraints). That is correct; such reload
4162 registers ARE still valid. */
4163 forget_marked_reloads (®s_to_forget);
4164 CLEAR_REG_SET (®s_to_forget);
4166 /* There may have been CLOBBER insns placed after INSN. So scan
4167 between INSN and NEXT and use them to forget old reloads. */
4168 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4169 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4170 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4173 /* Likewise for regs altered by auto-increment in this insn.
4174 REG_INC notes have been changed by reloading:
4175 find_reloads_address_1 records substitutions for them,
4176 which have been performed by subst_reloads above. */
4177 for (i = n_reloads - 1; i >= 0; i--)
4179 rtx in_reg = rld[i].in_reg;
4182 enum rtx_code code = GET_CODE (in_reg);
4183 /* PRE_INC / PRE_DEC will have the reload register ending up
4184 with the same value as the stack slot, but that doesn't
4185 hold true for POST_INC / POST_DEC. Either we have to
4186 convert the memory access to a true POST_INC / POST_DEC,
4187 or we can't use the reload register for inheritance. */
4188 if ((code == POST_INC || code == POST_DEC)
4189 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4190 REGNO (rld[i].reg_rtx))
4191 /* Make sure it is the inc/dec pseudo, and not
4192 some other (e.g. output operand) pseudo. */
4193 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4194 == REGNO (XEXP (in_reg, 0))))
4197 rtx reload_reg = rld[i].reg_rtx;
4198 enum machine_mode mode = GET_MODE (reload_reg);
4202 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4204 /* We really want to ignore REG_INC notes here, so
4205 use PATTERN (p) as argument to reg_set_p . */
4206 if (reg_set_p (reload_reg, PATTERN (p)))
4208 n = count_occurrences (PATTERN (p), reload_reg, 0);
4213 n = validate_replace_rtx (reload_reg,
4214 gen_rtx_fmt_e (code,
4219 /* We must also verify that the constraints
4220 are met after the replacement. */
4223 n = constrain_operands (1);
4227 /* If the constraints were not met, then
4228 undo the replacement. */
4231 validate_replace_rtx (gen_rtx_fmt_e (code,
4243 add_reg_note (p, REG_INC, reload_reg);
4244 /* Mark this as having an output reload so that the
4245 REG_INC processing code below won't invalidate
4246 the reload for inheritance. */
4247 SET_HARD_REG_BIT (reg_is_output_reload,
4248 REGNO (reload_reg));
4249 SET_REGNO_REG_SET (®_has_output_reload,
4250 REGNO (XEXP (in_reg, 0)));
4253 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4256 else if ((code == PRE_INC || code == PRE_DEC)
4257 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4258 REGNO (rld[i].reg_rtx))
4259 /* Make sure it is the inc/dec pseudo, and not
4260 some other (e.g. output operand) pseudo. */
4261 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4262 == REGNO (XEXP (in_reg, 0))))
4264 SET_HARD_REG_BIT (reg_is_output_reload,
4265 REGNO (rld[i].reg_rtx));
4266 SET_REGNO_REG_SET (®_has_output_reload,
4267 REGNO (XEXP (in_reg, 0)));
4271 /* If a pseudo that got a hard register is auto-incremented,
4272 we must purge records of copying it into pseudos without
4274 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4275 if (REG_NOTE_KIND (x) == REG_INC)
4277 /* See if this pseudo reg was reloaded in this insn.
4278 If so, its last-reload info is still valid
4279 because it is based on this insn's reload. */
4280 for (i = 0; i < n_reloads; i++)
4281 if (rld[i].out == XEXP (x, 0))
4285 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4289 /* A reload reg's contents are unknown after a label. */
4291 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4293 /* Don't assume a reload reg is still good after a call insn
4294 if it is a call-used reg, or if it contains a value that will
4295 be partially clobbered by the call. */
4296 else if (CALL_P (insn))
4298 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4299 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4304 free (reg_last_reload_reg);
4305 CLEAR_REG_SET (®_has_output_reload);
4308 /* Discard all record of any value reloaded from X,
4309 or reloaded in X from someplace else;
4310 unless X is an output reload reg of the current insn.
4312 X may be a hard reg (the reload reg)
4313 or it may be a pseudo reg that was reloaded from.
4315 When DATA is non-NULL just mark the registers in regset
4316 to be forgotten later. */
4319 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4324 regset regs = (regset) data;
4326 /* note_stores does give us subregs of hard regs,
4327 subreg_regno_offset requires a hard reg. */
4328 while (GET_CODE (x) == SUBREG)
4330 /* We ignore the subreg offset when calculating the regno,
4331 because we are using the entire underlying hard register
4341 if (regno >= FIRST_PSEUDO_REGISTER)
4347 nr = hard_regno_nregs[regno][GET_MODE (x)];
4348 /* Storing into a spilled-reg invalidates its contents.
4349 This can happen if a block-local pseudo is allocated to that reg
4350 and it wasn't spilled because this block's total need is 0.
4351 Then some insn might have an optional reload and use this reg. */
4353 for (i = 0; i < nr; i++)
4354 /* But don't do this if the reg actually serves as an output
4355 reload reg in the current instruction. */
4357 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4359 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4360 spill_reg_store[regno + i] = 0;
4366 SET_REGNO_REG_SET (regs, regno + nr);
4369 /* Since value of X has changed,
4370 forget any value previously copied from it. */
4373 /* But don't forget a copy if this is the output reload
4374 that establishes the copy's validity. */
4376 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4377 reg_last_reload_reg[regno + nr] = 0;
4381 /* Forget the reloads marked in regset by previous function. */
4383 forget_marked_reloads (regset regs)
4386 reg_set_iterator rsi;
4387 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4389 if (reg < FIRST_PSEUDO_REGISTER
4390 /* But don't do this if the reg actually serves as an output
4391 reload reg in the current instruction. */
4393 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4395 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4396 spill_reg_store[reg] = 0;
4399 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4400 reg_last_reload_reg[reg] = 0;
4404 /* The following HARD_REG_SETs indicate when each hard register is
4405 used for a reload of various parts of the current insn. */
4407 /* If reg is unavailable for all reloads. */
4408 static HARD_REG_SET reload_reg_unavailable;
4409 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4410 static HARD_REG_SET reload_reg_used;
4411 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4412 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4413 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4414 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4415 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4416 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4417 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4418 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4419 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4420 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4421 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4422 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4423 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4424 static HARD_REG_SET reload_reg_used_in_op_addr;
4425 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4426 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4427 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4428 static HARD_REG_SET reload_reg_used_in_insn;
4429 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4430 static HARD_REG_SET reload_reg_used_in_other_addr;
4432 /* If reg is in use as a reload reg for any sort of reload. */
4433 static HARD_REG_SET reload_reg_used_at_all;
4435 /* If reg is use as an inherited reload. We just mark the first register
4437 static HARD_REG_SET reload_reg_used_for_inherit;
4439 /* Records which hard regs are used in any way, either as explicit use or
4440 by being allocated to a pseudo during any point of the current insn. */
4441 static HARD_REG_SET reg_used_in_insn;
4443 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4444 TYPE. MODE is used to indicate how many consecutive regs are
4448 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4449 enum machine_mode mode)
4451 unsigned int nregs = hard_regno_nregs[regno][mode];
4454 for (i = regno; i < nregs + regno; i++)
4459 SET_HARD_REG_BIT (reload_reg_used, i);
4462 case RELOAD_FOR_INPUT_ADDRESS:
4463 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4466 case RELOAD_FOR_INPADDR_ADDRESS:
4467 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4470 case RELOAD_FOR_OUTPUT_ADDRESS:
4471 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4474 case RELOAD_FOR_OUTADDR_ADDRESS:
4475 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4478 case RELOAD_FOR_OPERAND_ADDRESS:
4479 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4482 case RELOAD_FOR_OPADDR_ADDR:
4483 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4486 case RELOAD_FOR_OTHER_ADDRESS:
4487 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4490 case RELOAD_FOR_INPUT:
4491 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4494 case RELOAD_FOR_OUTPUT:
4495 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4498 case RELOAD_FOR_INSN:
4499 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4503 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4507 /* Similarly, but show REGNO is no longer in use for a reload. */
4510 clear_reload_reg_in_use (unsigned int regno, int opnum,
4511 enum reload_type type, enum machine_mode mode)
4513 unsigned int nregs = hard_regno_nregs[regno][mode];
4514 unsigned int start_regno, end_regno, r;
4516 /* A complication is that for some reload types, inheritance might
4517 allow multiple reloads of the same types to share a reload register.
4518 We set check_opnum if we have to check only reloads with the same
4519 operand number, and check_any if we have to check all reloads. */
4520 int check_opnum = 0;
4522 HARD_REG_SET *used_in_set;
4527 used_in_set = &reload_reg_used;
4530 case RELOAD_FOR_INPUT_ADDRESS:
4531 used_in_set = &reload_reg_used_in_input_addr[opnum];
4534 case RELOAD_FOR_INPADDR_ADDRESS:
4536 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4539 case RELOAD_FOR_OUTPUT_ADDRESS:
4540 used_in_set = &reload_reg_used_in_output_addr[opnum];
4543 case RELOAD_FOR_OUTADDR_ADDRESS:
4545 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4548 case RELOAD_FOR_OPERAND_ADDRESS:
4549 used_in_set = &reload_reg_used_in_op_addr;
4552 case RELOAD_FOR_OPADDR_ADDR:
4554 used_in_set = &reload_reg_used_in_op_addr_reload;
4557 case RELOAD_FOR_OTHER_ADDRESS:
4558 used_in_set = &reload_reg_used_in_other_addr;
4562 case RELOAD_FOR_INPUT:
4563 used_in_set = &reload_reg_used_in_input[opnum];
4566 case RELOAD_FOR_OUTPUT:
4567 used_in_set = &reload_reg_used_in_output[opnum];
4570 case RELOAD_FOR_INSN:
4571 used_in_set = &reload_reg_used_in_insn;
4576 /* We resolve conflicts with remaining reloads of the same type by
4577 excluding the intervals of reload registers by them from the
4578 interval of freed reload registers. Since we only keep track of
4579 one set of interval bounds, we might have to exclude somewhat
4580 more than what would be necessary if we used a HARD_REG_SET here.
4581 But this should only happen very infrequently, so there should
4582 be no reason to worry about it. */
4584 start_regno = regno;
4585 end_regno = regno + nregs;
4586 if (check_opnum || check_any)
4588 for (i = n_reloads - 1; i >= 0; i--)
4590 if (rld[i].when_needed == type
4591 && (check_any || rld[i].opnum == opnum)
4594 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4595 unsigned int conflict_end
4596 = end_hard_regno (rld[i].mode, conflict_start);
4598 /* If there is an overlap with the first to-be-freed register,
4599 adjust the interval start. */
4600 if (conflict_start <= start_regno && conflict_end > start_regno)
4601 start_regno = conflict_end;
4602 /* Otherwise, if there is a conflict with one of the other
4603 to-be-freed registers, adjust the interval end. */
4604 if (conflict_start > start_regno && conflict_start < end_regno)
4605 end_regno = conflict_start;
4610 for (r = start_regno; r < end_regno; r++)
4611 CLEAR_HARD_REG_BIT (*used_in_set, r);
4614 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4615 specified by OPNUM and TYPE. */
4618 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4622 /* In use for a RELOAD_OTHER means it's not available for anything. */
4623 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4624 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4630 /* In use for anything means we can't use it for RELOAD_OTHER. */
4631 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4632 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4633 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4634 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4637 for (i = 0; i < reload_n_operands; i++)
4638 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4639 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4640 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4641 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4642 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4643 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4648 case RELOAD_FOR_INPUT:
4649 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4650 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4653 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4656 /* If it is used for some other input, can't use it. */
4657 for (i = 0; i < reload_n_operands; i++)
4658 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4661 /* If it is used in a later operand's address, can't use it. */
4662 for (i = opnum + 1; i < reload_n_operands; i++)
4663 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4664 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4669 case RELOAD_FOR_INPUT_ADDRESS:
4670 /* Can't use a register if it is used for an input address for this
4671 operand or used as an input in an earlier one. */
4672 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4673 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4676 for (i = 0; i < opnum; i++)
4677 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4682 case RELOAD_FOR_INPADDR_ADDRESS:
4683 /* Can't use a register if it is used for an input address
4684 for this operand or used as an input in an earlier
4686 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4689 for (i = 0; i < opnum; i++)
4690 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4695 case RELOAD_FOR_OUTPUT_ADDRESS:
4696 /* Can't use a register if it is used for an output address for this
4697 operand or used as an output in this or a later operand. Note
4698 that multiple output operands are emitted in reverse order, so
4699 the conflicting ones are those with lower indices. */
4700 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4703 for (i = 0; i <= opnum; i++)
4704 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4709 case RELOAD_FOR_OUTADDR_ADDRESS:
4710 /* Can't use a register if it is used for an output address
4711 for this operand or used as an output in this or a
4712 later operand. Note that multiple output operands are
4713 emitted in reverse order, so the conflicting ones are
4714 those with lower indices. */
4715 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4718 for (i = 0; i <= opnum; i++)
4719 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4724 case RELOAD_FOR_OPERAND_ADDRESS:
4725 for (i = 0; i < reload_n_operands; i++)
4726 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4729 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4730 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4732 case RELOAD_FOR_OPADDR_ADDR:
4733 for (i = 0; i < reload_n_operands; i++)
4734 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4737 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4739 case RELOAD_FOR_OUTPUT:
4740 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4741 outputs, or an operand address for this or an earlier output.
4742 Note that multiple output operands are emitted in reverse order,
4743 so the conflicting ones are those with higher indices. */
4744 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4747 for (i = 0; i < reload_n_operands; i++)
4748 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4751 for (i = opnum; i < reload_n_operands; i++)
4752 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4753 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4758 case RELOAD_FOR_INSN:
4759 for (i = 0; i < reload_n_operands; i++)
4760 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4761 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4764 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4765 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4767 case RELOAD_FOR_OTHER_ADDRESS:
4768 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4775 /* Return 1 if the value in reload reg REGNO, as used by a reload
4776 needed for the part of the insn specified by OPNUM and TYPE,
4777 is still available in REGNO at the end of the insn.
4779 We can assume that the reload reg was already tested for availability
4780 at the time it is needed, and we should not check this again,
4781 in case the reg has already been marked in use. */
4784 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4791 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4792 its value must reach the end. */
4795 /* If this use is for part of the insn,
4796 its value reaches if no subsequent part uses the same register.
4797 Just like the above function, don't try to do this with lots
4800 case RELOAD_FOR_OTHER_ADDRESS:
4801 /* Here we check for everything else, since these don't conflict
4802 with anything else and everything comes later. */
4804 for (i = 0; i < reload_n_operands; i++)
4805 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4806 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4807 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4808 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4809 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4810 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4813 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4814 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4815 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4816 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4818 case RELOAD_FOR_INPUT_ADDRESS:
4819 case RELOAD_FOR_INPADDR_ADDRESS:
4820 /* Similar, except that we check only for this and subsequent inputs
4821 and the address of only subsequent inputs and we do not need
4822 to check for RELOAD_OTHER objects since they are known not to
4825 for (i = opnum; i < reload_n_operands; i++)
4826 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4829 for (i = opnum + 1; i < reload_n_operands; i++)
4830 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4831 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4834 for (i = 0; i < reload_n_operands; i++)
4835 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4836 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4837 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4840 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4843 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4844 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4845 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4847 case RELOAD_FOR_INPUT:
4848 /* Similar to input address, except we start at the next operand for
4849 both input and input address and we do not check for
4850 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4853 for (i = opnum + 1; i < reload_n_operands; i++)
4854 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4855 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4856 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4859 /* ... fall through ... */
4861 case RELOAD_FOR_OPERAND_ADDRESS:
4862 /* Check outputs and their addresses. */
4864 for (i = 0; i < reload_n_operands; i++)
4865 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4866 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4867 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4870 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4872 case RELOAD_FOR_OPADDR_ADDR:
4873 for (i = 0; i < reload_n_operands; i++)
4874 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4875 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4876 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4879 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4880 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4881 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4883 case RELOAD_FOR_INSN:
4884 /* These conflict with other outputs with RELOAD_OTHER. So
4885 we need only check for output addresses. */
4887 opnum = reload_n_operands;
4889 /* ... fall through ... */
4891 case RELOAD_FOR_OUTPUT:
4892 case RELOAD_FOR_OUTPUT_ADDRESS:
4893 case RELOAD_FOR_OUTADDR_ADDRESS:
4894 /* We already know these can't conflict with a later output. So the
4895 only thing to check are later output addresses.
4896 Note that multiple output operands are emitted in reverse order,
4897 so the conflicting ones are those with lower indices. */
4898 for (i = 0; i < opnum; i++)
4899 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4900 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4910 /* Like reload_reg_reaches_end_p, but check that the condition holds for
4911 every register in the range [REGNO, REGNO + NREGS). */
4914 reload_regs_reach_end_p (unsigned int regno, int nregs,
4915 int opnum, enum reload_type type)
4919 for (i = 0; i < nregs; i++)
4920 if (!reload_reg_reaches_end_p (regno + i, opnum, type))
4926 /* Returns whether R1 and R2 are uniquely chained: the value of one
4927 is used by the other, and that value is not used by any other
4928 reload for this insn. This is used to partially undo the decision
4929 made in find_reloads when in the case of multiple
4930 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
4931 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
4932 reloads. This code tries to avoid the conflict created by that
4933 change. It might be cleaner to explicitly keep track of which
4934 RELOAD_FOR_OPADDR_ADDR reload is associated with which
4935 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
4936 this after the fact. */
4938 reloads_unique_chain_p (int r1, int r2)
4942 /* We only check input reloads. */
4943 if (! rld[r1].in || ! rld[r2].in)
4946 /* Avoid anything with output reloads. */
4947 if (rld[r1].out || rld[r2].out)
4950 /* "chained" means one reload is a component of the other reload,
4951 not the same as the other reload. */
4952 if (rld[r1].opnum != rld[r2].opnum
4953 || rtx_equal_p (rld[r1].in, rld[r2].in)
4954 || rld[r1].optional || rld[r2].optional
4955 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
4956 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
4959 for (i = 0; i < n_reloads; i ++)
4960 /* Look for input reloads that aren't our two */
4961 if (i != r1 && i != r2 && rld[i].in)
4963 /* If our reload is mentioned at all, it isn't a simple chain. */
4964 if (reg_mentioned_p (rld[r1].in, rld[i].in))
4970 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4973 This function uses the same algorithm as reload_reg_free_p above. */
4976 reloads_conflict (int r1, int r2)
4978 enum reload_type r1_type = rld[r1].when_needed;
4979 enum reload_type r2_type = rld[r2].when_needed;
4980 int r1_opnum = rld[r1].opnum;
4981 int r2_opnum = rld[r2].opnum;
4983 /* RELOAD_OTHER conflicts with everything. */
4984 if (r2_type == RELOAD_OTHER)
4987 /* Otherwise, check conflicts differently for each type. */
4991 case RELOAD_FOR_INPUT:
4992 return (r2_type == RELOAD_FOR_INSN
4993 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4994 || r2_type == RELOAD_FOR_OPADDR_ADDR
4995 || r2_type == RELOAD_FOR_INPUT
4996 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4997 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4998 && r2_opnum > r1_opnum));
5000 case RELOAD_FOR_INPUT_ADDRESS:
5001 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5002 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5004 case RELOAD_FOR_INPADDR_ADDRESS:
5005 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5006 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5008 case RELOAD_FOR_OUTPUT_ADDRESS:
5009 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5010 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5012 case RELOAD_FOR_OUTADDR_ADDRESS:
5013 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5014 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5016 case RELOAD_FOR_OPERAND_ADDRESS:
5017 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5018 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5019 && !reloads_unique_chain_p (r1, r2)));
5021 case RELOAD_FOR_OPADDR_ADDR:
5022 return (r2_type == RELOAD_FOR_INPUT
5023 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5025 case RELOAD_FOR_OUTPUT:
5026 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5027 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5028 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5029 && r2_opnum >= r1_opnum));
5031 case RELOAD_FOR_INSN:
5032 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5033 || r2_type == RELOAD_FOR_INSN
5034 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5036 case RELOAD_FOR_OTHER_ADDRESS:
5037 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5047 /* Indexed by reload number, 1 if incoming value
5048 inherited from previous insns. */
5049 static char reload_inherited[MAX_RELOADS];
5051 /* For an inherited reload, this is the insn the reload was inherited from,
5052 if we know it. Otherwise, this is 0. */
5053 static rtx reload_inheritance_insn[MAX_RELOADS];
5055 /* If nonzero, this is a place to get the value of the reload,
5056 rather than using reload_in. */
5057 static rtx reload_override_in[MAX_RELOADS];
5059 /* For each reload, the hard register number of the register used,
5060 or -1 if we did not need a register for this reload. */
5061 static int reload_spill_index[MAX_RELOADS];
5063 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5064 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5066 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5067 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5069 /* Subroutine of free_for_value_p, used to check a single register.
5070 START_REGNO is the starting regno of the full reload register
5071 (possibly comprising multiple hard registers) that we are considering. */
5074 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5075 enum reload_type type, rtx value, rtx out,
5076 int reloadnum, int ignore_address_reloads)
5079 /* Set if we see an input reload that must not share its reload register
5080 with any new earlyclobber, but might otherwise share the reload
5081 register with an output or input-output reload. */
5082 int check_earlyclobber = 0;
5086 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5089 if (out == const0_rtx)
5095 /* We use some pseudo 'time' value to check if the lifetimes of the
5096 new register use would overlap with the one of a previous reload
5097 that is not read-only or uses a different value.
5098 The 'time' used doesn't have to be linear in any shape or form, just
5100 Some reload types use different 'buckets' for each operand.
5101 So there are MAX_RECOG_OPERANDS different time values for each
5103 We compute TIME1 as the time when the register for the prospective
5104 new reload ceases to be live, and TIME2 for each existing
5105 reload as the time when that the reload register of that reload
5107 Where there is little to be gained by exact lifetime calculations,
5108 we just make conservative assumptions, i.e. a longer lifetime;
5109 this is done in the 'default:' cases. */
5112 case RELOAD_FOR_OTHER_ADDRESS:
5113 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5114 time1 = copy ? 0 : 1;
5117 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5119 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5120 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5121 respectively, to the time values for these, we get distinct time
5122 values. To get distinct time values for each operand, we have to
5123 multiply opnum by at least three. We round that up to four because
5124 multiply by four is often cheaper. */
5125 case RELOAD_FOR_INPADDR_ADDRESS:
5126 time1 = opnum * 4 + 2;
5128 case RELOAD_FOR_INPUT_ADDRESS:
5129 time1 = opnum * 4 + 3;
5131 case RELOAD_FOR_INPUT:
5132 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5133 executes (inclusive). */
5134 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5136 case RELOAD_FOR_OPADDR_ADDR:
5138 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5139 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5141 case RELOAD_FOR_OPERAND_ADDRESS:
5142 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5144 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5146 case RELOAD_FOR_OUTADDR_ADDRESS:
5147 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5149 case RELOAD_FOR_OUTPUT_ADDRESS:
5150 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5153 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5156 for (i = 0; i < n_reloads; i++)
5158 rtx reg = rld[i].reg_rtx;
5159 if (reg && REG_P (reg)
5160 && ((unsigned) regno - true_regnum (reg)
5161 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5164 rtx other_input = rld[i].in;
5166 /* If the other reload loads the same input value, that
5167 will not cause a conflict only if it's loading it into
5168 the same register. */
5169 if (true_regnum (reg) != start_regno)
5170 other_input = NULL_RTX;
5171 if (! other_input || ! rtx_equal_p (other_input, value)
5172 || rld[i].out || out)
5175 switch (rld[i].when_needed)
5177 case RELOAD_FOR_OTHER_ADDRESS:
5180 case RELOAD_FOR_INPADDR_ADDRESS:
5181 /* find_reloads makes sure that a
5182 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5183 by at most one - the first -
5184 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5185 address reload is inherited, the address address reload
5186 goes away, so we can ignore this conflict. */
5187 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5188 && ignore_address_reloads
5189 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5190 Then the address address is still needed to store
5191 back the new address. */
5192 && ! rld[reloadnum].out)
5194 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5195 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5197 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5198 && ignore_address_reloads
5199 /* Unless we are reloading an auto_inc expression. */
5200 && ! rld[reloadnum].out)
5202 time2 = rld[i].opnum * 4 + 2;
5204 case RELOAD_FOR_INPUT_ADDRESS:
5205 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5206 && ignore_address_reloads
5207 && ! rld[reloadnum].out)
5209 time2 = rld[i].opnum * 4 + 3;
5211 case RELOAD_FOR_INPUT:
5212 time2 = rld[i].opnum * 4 + 4;
5213 check_earlyclobber = 1;
5215 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5216 == MAX_RECOG_OPERAND * 4 */
5217 case RELOAD_FOR_OPADDR_ADDR:
5218 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5219 && ignore_address_reloads
5220 && ! rld[reloadnum].out)
5222 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5224 case RELOAD_FOR_OPERAND_ADDRESS:
5225 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5226 check_earlyclobber = 1;
5228 case RELOAD_FOR_INSN:
5229 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5231 case RELOAD_FOR_OUTPUT:
5232 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5233 instruction is executed. */
5234 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5236 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5237 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5239 case RELOAD_FOR_OUTADDR_ADDRESS:
5240 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5241 && ignore_address_reloads
5242 && ! rld[reloadnum].out)
5244 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5246 case RELOAD_FOR_OUTPUT_ADDRESS:
5247 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5250 /* If there is no conflict in the input part, handle this
5251 like an output reload. */
5252 if (! rld[i].in || rtx_equal_p (other_input, value))
5254 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5255 /* Earlyclobbered outputs must conflict with inputs. */
5256 if (earlyclobber_operand_p (rld[i].out))
5257 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5262 /* RELOAD_OTHER might be live beyond instruction execution,
5263 but this is not obvious when we set time2 = 1. So check
5264 here if there might be a problem with the new reload
5265 clobbering the register used by the RELOAD_OTHER. */
5273 && (! rld[i].in || rld[i].out
5274 || ! rtx_equal_p (other_input, value)))
5275 || (out && rld[reloadnum].out_reg
5276 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5282 /* Earlyclobbered outputs must conflict with inputs. */
5283 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5289 /* Return 1 if the value in reload reg REGNO, as used by a reload
5290 needed for the part of the insn specified by OPNUM and TYPE,
5291 may be used to load VALUE into it.
5293 MODE is the mode in which the register is used, this is needed to
5294 determine how many hard regs to test.
5296 Other read-only reloads with the same value do not conflict
5297 unless OUT is nonzero and these other reloads have to live while
5298 output reloads live.
5299 If OUT is CONST0_RTX, this is a special case: it means that the
5300 test should not be for using register REGNO as reload register, but
5301 for copying from register REGNO into the reload register.
5303 RELOADNUM is the number of the reload we want to load this value for;
5304 a reload does not conflict with itself.
5306 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5307 reloads that load an address for the very reload we are considering.
5309 The caller has to make sure that there is no conflict with the return
5313 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5314 enum reload_type type, rtx value, rtx out, int reloadnum,
5315 int ignore_address_reloads)
5317 int nregs = hard_regno_nregs[regno][mode];
5319 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5320 value, out, reloadnum,
5321 ignore_address_reloads))
5326 /* Return nonzero if the rtx X is invariant over the current function. */
5327 /* ??? Actually, the places where we use this expect exactly what is
5328 tested here, and not everything that is function invariant. In
5329 particular, the frame pointer and arg pointer are special cased;
5330 pic_offset_table_rtx is not, and we must not spill these things to
5334 function_invariant_p (const_rtx x)
5338 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5340 if (GET_CODE (x) == PLUS
5341 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5342 && CONSTANT_P (XEXP (x, 1)))
5347 /* Determine whether the reload reg X overlaps any rtx'es used for
5348 overriding inheritance. Return nonzero if so. */
5351 conflicts_with_override (rtx x)
5354 for (i = 0; i < n_reloads; i++)
5355 if (reload_override_in[i]
5356 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5361 /* Give an error message saying we failed to find a reload for INSN,
5362 and clear out reload R. */
5364 failed_reload (rtx insn, int r)
5366 if (asm_noperands (PATTERN (insn)) < 0)
5367 /* It's the compiler's fault. */
5368 fatal_insn ("could not find a spill register", insn);
5370 /* It's the user's fault; the operand's mode and constraint
5371 don't match. Disable this reload so we don't crash in final. */
5372 error_for_asm (insn,
5373 "%<asm%> operand constraint incompatible with operand size");
5377 rld[r].optional = 1;
5378 rld[r].secondary_p = 1;
5381 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5382 for reload R. If it's valid, get an rtx for it. Return nonzero if
5385 set_reload_reg (int i, int r)
5388 rtx reg = spill_reg_rtx[i];
5390 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5391 spill_reg_rtx[i] = reg
5392 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5394 regno = true_regnum (reg);
5396 /* Detect when the reload reg can't hold the reload mode.
5397 This used to be one `if', but Sequent compiler can't handle that. */
5398 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5400 enum machine_mode test_mode = VOIDmode;
5402 test_mode = GET_MODE (rld[r].in);
5403 /* If rld[r].in has VOIDmode, it means we will load it
5404 in whatever mode the reload reg has: to wit, rld[r].mode.
5405 We have already tested that for validity. */
5406 /* Aside from that, we need to test that the expressions
5407 to reload from or into have modes which are valid for this
5408 reload register. Otherwise the reload insns would be invalid. */
5409 if (! (rld[r].in != 0 && test_mode != VOIDmode
5410 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5411 if (! (rld[r].out != 0
5412 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5414 /* The reg is OK. */
5417 /* Mark as in use for this insn the reload regs we use
5419 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5420 rld[r].when_needed, rld[r].mode);
5422 rld[r].reg_rtx = reg;
5423 reload_spill_index[r] = spill_regs[i];
5430 /* Find a spill register to use as a reload register for reload R.
5431 LAST_RELOAD is nonzero if this is the last reload for the insn being
5434 Set rld[R].reg_rtx to the register allocated.
5436 We return 1 if successful, or 0 if we couldn't find a spill reg and
5437 we didn't change anything. */
5440 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5445 /* If we put this reload ahead, thinking it is a group,
5446 then insist on finding a group. Otherwise we can grab a
5447 reg that some other reload needs.
5448 (That can happen when we have a 68000 DATA_OR_FP_REG
5449 which is a group of data regs or one fp reg.)
5450 We need not be so restrictive if there are no more reloads
5453 ??? Really it would be nicer to have smarter handling
5454 for that kind of reg class, where a problem like this is normal.
5455 Perhaps those classes should be avoided for reloading
5456 by use of more alternatives. */
5458 int force_group = rld[r].nregs > 1 && ! last_reload;
5460 /* If we want a single register and haven't yet found one,
5461 take any reg in the right class and not in use.
5462 If we want a consecutive group, here is where we look for it.
5464 We use two passes so we can first look for reload regs to
5465 reuse, which are already in use for other reloads in this insn,
5466 and only then use additional registers.
5467 I think that maximizing reuse is needed to make sure we don't
5468 run out of reload regs. Suppose we have three reloads, and
5469 reloads A and B can share regs. These need two regs.
5470 Suppose A and B are given different regs.
5471 That leaves none for C. */
5472 for (pass = 0; pass < 2; pass++)
5474 /* I is the index in spill_regs.
5475 We advance it round-robin between insns to use all spill regs
5476 equally, so that inherited reloads have a chance
5477 of leapfrogging each other. */
5481 for (count = 0; count < n_spills; count++)
5483 int rclass = (int) rld[r].rclass;
5489 regnum = spill_regs[i];
5491 if ((reload_reg_free_p (regnum, rld[r].opnum,
5494 /* We check reload_reg_used to make sure we
5495 don't clobber the return register. */
5496 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5497 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5498 rld[r].when_needed, rld[r].in,
5500 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
5501 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5502 /* Look first for regs to share, then for unshared. But
5503 don't share regs used for inherited reloads; they are
5504 the ones we want to preserve. */
5506 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5508 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5511 int nr = hard_regno_nregs[regnum][rld[r].mode];
5512 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5513 (on 68000) got us two FP regs. If NR is 1,
5514 we would reject both of them. */
5517 /* If we need only one reg, we have already won. */
5520 /* But reject a single reg if we demand a group. */
5525 /* Otherwise check that as many consecutive regs as we need
5526 are available here. */
5529 int regno = regnum + nr - 1;
5530 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
5531 && spill_reg_order[regno] >= 0
5532 && reload_reg_free_p (regno, rld[r].opnum,
5533 rld[r].when_needed)))
5542 /* If we found something on pass 1, omit pass 2. */
5543 if (count < n_spills)
5547 /* We should have found a spill register by now. */
5548 if (count >= n_spills)
5551 /* I is the index in SPILL_REG_RTX of the reload register we are to
5552 allocate. Get an rtx for it and find its register number. */
5554 return set_reload_reg (i, r);
5557 /* Initialize all the tables needed to allocate reload registers.
5558 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5559 is the array we use to restore the reg_rtx field for every reload. */
5562 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5566 for (i = 0; i < n_reloads; i++)
5567 rld[i].reg_rtx = save_reload_reg_rtx[i];
5569 memset (reload_inherited, 0, MAX_RELOADS);
5570 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5571 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5573 CLEAR_HARD_REG_SET (reload_reg_used);
5574 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5575 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5576 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5577 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5578 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5580 CLEAR_HARD_REG_SET (reg_used_in_insn);
5583 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5584 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5585 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5586 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5587 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5588 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5591 for (i = 0; i < reload_n_operands; i++)
5593 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5594 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5595 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5596 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5597 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5598 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5601 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5603 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5605 for (i = 0; i < n_reloads; i++)
5606 /* If we have already decided to use a certain register,
5607 don't use it in another way. */
5609 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5610 rld[i].when_needed, rld[i].mode);
5613 /* Assign hard reg targets for the pseudo-registers we must reload
5614 into hard regs for this insn.
5615 Also output the instructions to copy them in and out of the hard regs.
5617 For machines with register classes, we are responsible for
5618 finding a reload reg in the proper class. */
5621 choose_reload_regs (struct insn_chain *chain)
5623 rtx insn = chain->insn;
5625 unsigned int max_group_size = 1;
5626 enum reg_class group_class = NO_REGS;
5627 int pass, win, inheritance;
5629 rtx save_reload_reg_rtx[MAX_RELOADS];
5631 /* In order to be certain of getting the registers we need,
5632 we must sort the reloads into order of increasing register class.
5633 Then our grabbing of reload registers will parallel the process
5634 that provided the reload registers.
5636 Also note whether any of the reloads wants a consecutive group of regs.
5637 If so, record the maximum size of the group desired and what
5638 register class contains all the groups needed by this insn. */
5640 for (j = 0; j < n_reloads; j++)
5642 reload_order[j] = j;
5643 if (rld[j].reg_rtx != NULL_RTX)
5645 gcc_assert (REG_P (rld[j].reg_rtx)
5646 && HARD_REGISTER_P (rld[j].reg_rtx));
5647 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
5650 reload_spill_index[j] = -1;
5652 if (rld[j].nregs > 1)
5654 max_group_size = MAX (rld[j].nregs, max_group_size);
5656 = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
5659 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5663 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5665 /* If -O, try first with inheritance, then turning it off.
5666 If not -O, don't do inheritance.
5667 Using inheritance when not optimizing leads to paradoxes
5668 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5669 because one side of the comparison might be inherited. */
5671 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5673 choose_reload_regs_init (chain, save_reload_reg_rtx);
5675 /* Process the reloads in order of preference just found.
5676 Beyond this point, subregs can be found in reload_reg_rtx.
5678 This used to look for an existing reloaded home for all of the
5679 reloads, and only then perform any new reloads. But that could lose
5680 if the reloads were done out of reg-class order because a later
5681 reload with a looser constraint might have an old home in a register
5682 needed by an earlier reload with a tighter constraint.
5684 To solve this, we make two passes over the reloads, in the order
5685 described above. In the first pass we try to inherit a reload
5686 from a previous insn. If there is a later reload that needs a
5687 class that is a proper subset of the class being processed, we must
5688 also allocate a spill register during the first pass.
5690 Then make a second pass over the reloads to allocate any reloads
5691 that haven't been given registers yet. */
5693 for (j = 0; j < n_reloads; j++)
5695 int r = reload_order[j];
5696 rtx search_equiv = NULL_RTX;
5698 /* Ignore reloads that got marked inoperative. */
5699 if (rld[r].out == 0 && rld[r].in == 0
5700 && ! rld[r].secondary_p)
5703 /* If find_reloads chose to use reload_in or reload_out as a reload
5704 register, we don't need to chose one. Otherwise, try even if it
5705 found one since we might save an insn if we find the value lying
5707 Try also when reload_in is a pseudo without a hard reg. */
5708 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5709 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5710 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5711 && !MEM_P (rld[r].in)
5712 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5715 #if 0 /* No longer needed for correct operation.
5716 It might give better code, or might not; worth an experiment? */
5717 /* If this is an optional reload, we can't inherit from earlier insns
5718 until we are sure that any non-optional reloads have been allocated.
5719 The following code takes advantage of the fact that optional reloads
5720 are at the end of reload_order. */
5721 if (rld[r].optional != 0)
5722 for (i = 0; i < j; i++)
5723 if ((rld[reload_order[i]].out != 0
5724 || rld[reload_order[i]].in != 0
5725 || rld[reload_order[i]].secondary_p)
5726 && ! rld[reload_order[i]].optional
5727 && rld[reload_order[i]].reg_rtx == 0)
5728 allocate_reload_reg (chain, reload_order[i], 0);
5731 /* First see if this pseudo is already available as reloaded
5732 for a previous insn. We cannot try to inherit for reloads
5733 that are smaller than the maximum number of registers needed
5734 for groups unless the register we would allocate cannot be used
5737 We could check here to see if this is a secondary reload for
5738 an object that is already in a register of the desired class.
5739 This would avoid the need for the secondary reload register.
5740 But this is complex because we can't easily determine what
5741 objects might want to be loaded via this reload. So let a
5742 register be allocated here. In `emit_reload_insns' we suppress
5743 one of the loads in the case described above. */
5749 enum machine_mode mode = VOIDmode;
5753 else if (REG_P (rld[r].in))
5755 regno = REGNO (rld[r].in);
5756 mode = GET_MODE (rld[r].in);
5758 else if (REG_P (rld[r].in_reg))
5760 regno = REGNO (rld[r].in_reg);
5761 mode = GET_MODE (rld[r].in_reg);
5763 else if (GET_CODE (rld[r].in_reg) == SUBREG
5764 && REG_P (SUBREG_REG (rld[r].in_reg)))
5766 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5767 if (regno < FIRST_PSEUDO_REGISTER)
5768 regno = subreg_regno (rld[r].in_reg);
5770 byte = SUBREG_BYTE (rld[r].in_reg);
5771 mode = GET_MODE (rld[r].in_reg);
5774 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
5775 && REG_P (XEXP (rld[r].in_reg, 0)))
5777 regno = REGNO (XEXP (rld[r].in_reg, 0));
5778 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5779 rld[r].out = rld[r].in;
5783 /* This won't work, since REGNO can be a pseudo reg number.
5784 Also, it takes much more hair to keep track of all the things
5785 that can invalidate an inherited reload of part of a pseudoreg. */
5786 else if (GET_CODE (rld[r].in) == SUBREG
5787 && REG_P (SUBREG_REG (rld[r].in)))
5788 regno = subreg_regno (rld[r].in);
5792 && reg_last_reload_reg[regno] != 0
5793 #ifdef CANNOT_CHANGE_MODE_CLASS
5794 /* Verify that the register it's in can be used in
5796 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
5797 GET_MODE (reg_last_reload_reg[regno]),
5802 enum reg_class rclass = rld[r].rclass, last_class;
5803 rtx last_reg = reg_last_reload_reg[regno];
5804 enum machine_mode need_mode;
5806 i = REGNO (last_reg);
5807 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5808 last_class = REGNO_REG_CLASS (i);
5814 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5815 + byte * BITS_PER_UNIT,
5816 GET_MODE_CLASS (mode));
5818 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5819 >= GET_MODE_SIZE (need_mode))
5820 && reg_reloaded_contents[i] == regno
5821 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5822 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5823 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
5824 /* Even if we can't use this register as a reload
5825 register, we might use it for reload_override_in,
5826 if copying it to the desired class is cheap
5828 || ((REGISTER_MOVE_COST (mode, last_class, rclass)
5829 < MEMORY_MOVE_COST (mode, rclass, 1))
5830 && (secondary_reload_class (1, rclass, mode,
5833 #ifdef SECONDARY_MEMORY_NEEDED
5834 && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
5839 && (rld[r].nregs == max_group_size
5840 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5842 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5843 rld[r].when_needed, rld[r].in,
5846 /* If a group is needed, verify that all the subsequent
5847 registers still have their values intact. */
5848 int nr = hard_regno_nregs[i][rld[r].mode];
5851 for (k = 1; k < nr; k++)
5852 if (reg_reloaded_contents[i + k] != regno
5853 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5861 last_reg = (GET_MODE (last_reg) == mode
5862 ? last_reg : gen_rtx_REG (mode, i));
5865 for (k = 0; k < nr; k++)
5866 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
5869 /* We found a register that contains the
5870 value we need. If this register is the
5871 same as an `earlyclobber' operand of the
5872 current insn, just mark it as a place to
5873 reload from since we can't use it as the
5874 reload register itself. */
5876 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5877 if (reg_overlap_mentioned_for_reload_p
5878 (reg_last_reload_reg[regno],
5879 reload_earlyclobbers[i1]))
5882 if (i1 != n_earlyclobbers
5883 || ! (free_for_value_p (i, rld[r].mode,
5885 rld[r].when_needed, rld[r].in,
5887 /* Don't use it if we'd clobber a pseudo reg. */
5888 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5890 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5891 /* Don't clobber the frame pointer. */
5892 || (i == HARD_FRAME_POINTER_REGNUM
5893 && frame_pointer_needed
5895 /* Don't really use the inherited spill reg
5896 if we need it wider than we've got it. */
5897 || (GET_MODE_SIZE (rld[r].mode)
5898 > GET_MODE_SIZE (mode))
5901 /* If find_reloads chose reload_out as reload
5902 register, stay with it - that leaves the
5903 inherited register for subsequent reloads. */
5904 || (rld[r].out && rld[r].reg_rtx
5905 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5907 if (! rld[r].optional)
5909 reload_override_in[r] = last_reg;
5910 reload_inheritance_insn[r]
5911 = reg_reloaded_insn[i];
5917 /* We can use this as a reload reg. */
5918 /* Mark the register as in use for this part of
5920 mark_reload_reg_in_use (i,
5924 rld[r].reg_rtx = last_reg;
5925 reload_inherited[r] = 1;
5926 reload_inheritance_insn[r]
5927 = reg_reloaded_insn[i];
5928 reload_spill_index[r] = i;
5929 for (k = 0; k < nr; k++)
5930 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5938 /* Here's another way to see if the value is already lying around. */
5941 && ! reload_inherited[r]
5943 && (CONSTANT_P (rld[r].in)
5944 || GET_CODE (rld[r].in) == PLUS
5945 || REG_P (rld[r].in)
5946 || MEM_P (rld[r].in))
5947 && (rld[r].nregs == max_group_size
5948 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
5949 search_equiv = rld[r].in;
5950 /* If this is an output reload from a simple move insn, look
5951 if an equivalence for the input is available. */
5952 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5954 rtx set = single_set (insn);
5957 && rtx_equal_p (rld[r].out, SET_DEST (set))
5958 && CONSTANT_P (SET_SRC (set)))
5959 search_equiv = SET_SRC (set);
5965 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
5966 -1, NULL, 0, rld[r].mode);
5972 regno = REGNO (equiv);
5975 /* This must be a SUBREG of a hard register.
5976 Make a new REG since this might be used in an
5977 address and not all machines support SUBREGs
5979 gcc_assert (GET_CODE (equiv) == SUBREG);
5980 regno = subreg_regno (equiv);
5981 equiv = gen_rtx_REG (rld[r].mode, regno);
5982 /* If we choose EQUIV as the reload register, but the
5983 loop below decides to cancel the inheritance, we'll
5984 end up reloading EQUIV in rld[r].mode, not the mode
5985 it had originally. That isn't safe when EQUIV isn't
5986 available as a spill register since its value might
5987 still be live at this point. */
5988 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5989 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
5994 /* If we found a spill reg, reject it unless it is free
5995 and of the desired class. */
5999 int bad_for_class = 0;
6000 int max_regno = regno + rld[r].nregs;
6002 for (i = regno; i < max_regno; i++)
6004 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6006 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6011 && ! free_for_value_p (regno, rld[r].mode,
6012 rld[r].opnum, rld[r].when_needed,
6013 rld[r].in, rld[r].out, r, 1))
6018 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6021 /* We found a register that contains the value we need.
6022 If this register is the same as an `earlyclobber' operand
6023 of the current insn, just mark it as a place to reload from
6024 since we can't use it as the reload register itself. */
6027 for (i = 0; i < n_earlyclobbers; i++)
6028 if (reg_overlap_mentioned_for_reload_p (equiv,
6029 reload_earlyclobbers[i]))
6031 if (! rld[r].optional)
6032 reload_override_in[r] = equiv;
6037 /* If the equiv register we have found is explicitly clobbered
6038 in the current insn, it depends on the reload type if we
6039 can use it, use it for reload_override_in, or not at all.
6040 In particular, we then can't use EQUIV for a
6041 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6045 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6046 switch (rld[r].when_needed)
6048 case RELOAD_FOR_OTHER_ADDRESS:
6049 case RELOAD_FOR_INPADDR_ADDRESS:
6050 case RELOAD_FOR_INPUT_ADDRESS:
6051 case RELOAD_FOR_OPADDR_ADDR:
6054 case RELOAD_FOR_INPUT:
6055 case RELOAD_FOR_OPERAND_ADDRESS:
6056 if (! rld[r].optional)
6057 reload_override_in[r] = equiv;
6063 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6064 switch (rld[r].when_needed)
6066 case RELOAD_FOR_OTHER_ADDRESS:
6067 case RELOAD_FOR_INPADDR_ADDRESS:
6068 case RELOAD_FOR_INPUT_ADDRESS:
6069 case RELOAD_FOR_OPADDR_ADDR:
6070 case RELOAD_FOR_OPERAND_ADDRESS:
6071 case RELOAD_FOR_INPUT:
6074 if (! rld[r].optional)
6075 reload_override_in[r] = equiv;
6083 /* If we found an equivalent reg, say no code need be generated
6084 to load it, and use it as our reload reg. */
6086 && (regno != HARD_FRAME_POINTER_REGNUM
6087 || !frame_pointer_needed))
6089 int nr = hard_regno_nregs[regno][rld[r].mode];
6091 rld[r].reg_rtx = equiv;
6092 reload_inherited[r] = 1;
6094 /* If reg_reloaded_valid is not set for this register,
6095 there might be a stale spill_reg_store lying around.
6096 We must clear it, since otherwise emit_reload_insns
6097 might delete the store. */
6098 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6099 spill_reg_store[regno] = NULL_RTX;
6100 /* If any of the hard registers in EQUIV are spill
6101 registers, mark them as in use for this insn. */
6102 for (k = 0; k < nr; k++)
6104 i = spill_reg_order[regno + k];
6107 mark_reload_reg_in_use (regno, rld[r].opnum,
6110 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6117 /* If we found a register to use already, or if this is an optional
6118 reload, we are done. */
6119 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6123 /* No longer needed for correct operation. Might or might
6124 not give better code on the average. Want to experiment? */
6126 /* See if there is a later reload that has a class different from our
6127 class that intersects our class or that requires less register
6128 than our reload. If so, we must allocate a register to this
6129 reload now, since that reload might inherit a previous reload
6130 and take the only available register in our class. Don't do this
6131 for optional reloads since they will force all previous reloads
6132 to be allocated. Also don't do this for reloads that have been
6135 for (i = j + 1; i < n_reloads; i++)
6137 int s = reload_order[i];
6139 if ((rld[s].in == 0 && rld[s].out == 0
6140 && ! rld[s].secondary_p)
6144 if ((rld[s].rclass != rld[r].rclass
6145 && reg_classes_intersect_p (rld[r].rclass,
6147 || rld[s].nregs < rld[r].nregs)
6154 allocate_reload_reg (chain, r, j == n_reloads - 1);
6158 /* Now allocate reload registers for anything non-optional that
6159 didn't get one yet. */
6160 for (j = 0; j < n_reloads; j++)
6162 int r = reload_order[j];
6164 /* Ignore reloads that got marked inoperative. */
6165 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6168 /* Skip reloads that already have a register allocated or are
6170 if (rld[r].reg_rtx != 0 || rld[r].optional)
6173 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6177 /* If that loop got all the way, we have won. */
6184 /* Loop around and try without any inheritance. */
6189 /* First undo everything done by the failed attempt
6190 to allocate with inheritance. */
6191 choose_reload_regs_init (chain, save_reload_reg_rtx);
6193 /* Some sanity tests to verify that the reloads found in the first
6194 pass are identical to the ones we have now. */
6195 gcc_assert (chain->n_reloads == n_reloads);
6197 for (i = 0; i < n_reloads; i++)
6199 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6201 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6202 for (j = 0; j < n_spills; j++)
6203 if (spill_regs[j] == chain->rld[i].regno)
6204 if (! set_reload_reg (j, i))
6205 failed_reload (chain->insn, i);
6209 /* If we thought we could inherit a reload, because it seemed that
6210 nothing else wanted the same reload register earlier in the insn,
6211 verify that assumption, now that all reloads have been assigned.
6212 Likewise for reloads where reload_override_in has been set. */
6214 /* If doing expensive optimizations, do one preliminary pass that doesn't
6215 cancel any inheritance, but removes reloads that have been needed only
6216 for reloads that we know can be inherited. */
6217 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6219 for (j = 0; j < n_reloads; j++)
6221 int r = reload_order[j];
6223 if (reload_inherited[r] && rld[r].reg_rtx)
6224 check_reg = rld[r].reg_rtx;
6225 else if (reload_override_in[r]
6226 && (REG_P (reload_override_in[r])
6227 || GET_CODE (reload_override_in[r]) == SUBREG))
6228 check_reg = reload_override_in[r];
6231 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6232 rld[r].opnum, rld[r].when_needed, rld[r].in,
6233 (reload_inherited[r]
6234 ? rld[r].out : const0_rtx),
6239 reload_inherited[r] = 0;
6240 reload_override_in[r] = 0;
6242 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6243 reload_override_in, then we do not need its related
6244 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6245 likewise for other reload types.
6246 We handle this by removing a reload when its only replacement
6247 is mentioned in reload_in of the reload we are going to inherit.
6248 A special case are auto_inc expressions; even if the input is
6249 inherited, we still need the address for the output. We can
6250 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6251 If we succeeded removing some reload and we are doing a preliminary
6252 pass just to remove such reloads, make another pass, since the
6253 removal of one reload might allow us to inherit another one. */
6255 && rld[r].out != rld[r].in
6256 && remove_address_replacements (rld[r].in) && pass)
6261 /* Now that reload_override_in is known valid,
6262 actually override reload_in. */
6263 for (j = 0; j < n_reloads; j++)
6264 if (reload_override_in[j])
6265 rld[j].in = reload_override_in[j];
6267 /* If this reload won't be done because it has been canceled or is
6268 optional and not inherited, clear reload_reg_rtx so other
6269 routines (such as subst_reloads) don't get confused. */
6270 for (j = 0; j < n_reloads; j++)
6271 if (rld[j].reg_rtx != 0
6272 && ((rld[j].optional && ! reload_inherited[j])
6273 || (rld[j].in == 0 && rld[j].out == 0
6274 && ! rld[j].secondary_p)))
6276 int regno = true_regnum (rld[j].reg_rtx);
6278 if (spill_reg_order[regno] >= 0)
6279 clear_reload_reg_in_use (regno, rld[j].opnum,
6280 rld[j].when_needed, rld[j].mode);
6282 reload_spill_index[j] = -1;
6285 /* Record which pseudos and which spill regs have output reloads. */
6286 for (j = 0; j < n_reloads; j++)
6288 int r = reload_order[j];
6290 i = reload_spill_index[r];
6292 /* I is nonneg if this reload uses a register.
6293 If rld[r].reg_rtx is 0, this is an optional reload
6294 that we opted to ignore. */
6295 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6296 && rld[r].reg_rtx != 0)
6298 int nregno = REGNO (rld[r].out_reg);
6301 if (nregno < FIRST_PSEUDO_REGISTER)
6302 nr = hard_regno_nregs[nregno][rld[r].mode];
6305 SET_REGNO_REG_SET (®_has_output_reload,
6310 nr = hard_regno_nregs[i][rld[r].mode];
6312 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6315 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6316 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6317 || rld[r].when_needed == RELOAD_FOR_INSN);
6322 /* Deallocate the reload register for reload R. This is called from
6323 remove_address_replacements. */
6326 deallocate_reload_reg (int r)
6330 if (! rld[r].reg_rtx)
6332 regno = true_regnum (rld[r].reg_rtx);
6334 if (spill_reg_order[regno] >= 0)
6335 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6337 reload_spill_index[r] = -1;
6340 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6341 reloads of the same item for fear that we might not have enough reload
6342 registers. However, normally they will get the same reload register
6343 and hence actually need not be loaded twice.
6345 Here we check for the most common case of this phenomenon: when we have
6346 a number of reloads for the same object, each of which were allocated
6347 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6348 reload, and is not modified in the insn itself. If we find such,
6349 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6350 This will not increase the number of spill registers needed and will
6351 prevent redundant code. */
6354 merge_assigned_reloads (rtx insn)
6358 /* Scan all the reloads looking for ones that only load values and
6359 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6360 assigned and not modified by INSN. */
6362 for (i = 0; i < n_reloads; i++)
6364 int conflicting_input = 0;
6365 int max_input_address_opnum = -1;
6366 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6368 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6369 || rld[i].out != 0 || rld[i].reg_rtx == 0
6370 || reg_set_p (rld[i].reg_rtx, insn))
6373 /* Look at all other reloads. Ensure that the only use of this
6374 reload_reg_rtx is in a reload that just loads the same value
6375 as we do. Note that any secondary reloads must be of the identical
6376 class since the values, modes, and result registers are the
6377 same, so we need not do anything with any secondary reloads. */
6379 for (j = 0; j < n_reloads; j++)
6381 if (i == j || rld[j].reg_rtx == 0
6382 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6386 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6387 && rld[j].opnum > max_input_address_opnum)
6388 max_input_address_opnum = rld[j].opnum;
6390 /* If the reload regs aren't exactly the same (e.g, different modes)
6391 or if the values are different, we can't merge this reload.
6392 But if it is an input reload, we might still merge
6393 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6395 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6396 || rld[j].out != 0 || rld[j].in == 0
6397 || ! rtx_equal_p (rld[i].in, rld[j].in))
6399 if (rld[j].when_needed != RELOAD_FOR_INPUT
6400 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6401 || rld[i].opnum > rld[j].opnum)
6402 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6404 conflicting_input = 1;
6405 if (min_conflicting_input_opnum > rld[j].opnum)
6406 min_conflicting_input_opnum = rld[j].opnum;
6410 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6411 we, in fact, found any matching reloads. */
6414 && max_input_address_opnum <= min_conflicting_input_opnum)
6416 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6418 for (j = 0; j < n_reloads; j++)
6419 if (i != j && rld[j].reg_rtx != 0
6420 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6421 && (! conflicting_input
6422 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6423 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6425 rld[i].when_needed = RELOAD_OTHER;
6427 reload_spill_index[j] = -1;
6428 transfer_replacements (i, j);
6431 /* If this is now RELOAD_OTHER, look for any reloads that
6432 load parts of this operand and set them to
6433 RELOAD_FOR_OTHER_ADDRESS if they were for inputs,
6434 RELOAD_OTHER for outputs. Note that this test is
6435 equivalent to looking for reloads for this operand
6438 We must take special care with RELOAD_FOR_OUTPUT_ADDRESS;
6439 it may share registers with a RELOAD_FOR_INPUT, so we can
6440 not change it to RELOAD_FOR_OTHER_ADDRESS. We should
6441 never need to, since we do not modify RELOAD_FOR_OUTPUT.
6443 It is possible that the RELOAD_FOR_OPERAND_ADDRESS
6444 instruction is assigned the same register as the earlier
6445 RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two
6446 instructions will cause the RELOAD_FOR_OTHER_ADDRESS
6447 instruction to be deleted later on. */
6449 if (rld[i].when_needed == RELOAD_OTHER)
6450 for (j = 0; j < n_reloads; j++)
6452 && rld[j].when_needed != RELOAD_OTHER
6453 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6454 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6455 && rld[j].when_needed != RELOAD_FOR_OPERAND_ADDRESS
6456 && (! conflicting_input
6457 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6458 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6459 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6465 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6466 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6467 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6469 /* Check to see if we accidentally converted two
6470 reloads that use the same reload register with
6471 different inputs to the same type. If so, the
6472 resulting code won't work. */
6474 for (k = 0; k < j; k++)
6475 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6476 || rld[k].when_needed != rld[j].when_needed
6477 || !rtx_equal_p (rld[k].reg_rtx,
6479 || rtx_equal_p (rld[k].in,
6486 /* These arrays are filled by emit_reload_insns and its subroutines. */
6487 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6488 static rtx other_input_address_reload_insns = 0;
6489 static rtx other_input_reload_insns = 0;
6490 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6491 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6492 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6493 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6494 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6495 static rtx operand_reload_insns = 0;
6496 static rtx other_operand_reload_insns = 0;
6497 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6499 /* Values to be put in spill_reg_store are put here first. */
6500 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6501 static HARD_REG_SET reg_reloaded_died;
6503 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6504 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6505 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6506 adjusted register, and return true. Otherwise, return false. */
6508 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6509 enum reg_class new_class,
6510 enum machine_mode new_mode)
6515 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6517 unsigned regno = REGNO (reg);
6519 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6521 if (GET_MODE (reg) != new_mode)
6523 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6525 if (hard_regno_nregs[regno][new_mode]
6526 > hard_regno_nregs[regno][GET_MODE (reg)])
6528 reg = reload_adjust_reg_for_mode (reg, new_mode);
6536 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6537 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6538 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6539 adjusted register, and return true. Otherwise, return false. */
6541 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6542 enum insn_code icode)
6545 enum reg_class new_class = scratch_reload_class (icode);
6546 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6548 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6549 new_class, new_mode);
6552 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6553 has the number J. OLD contains the value to be used as input. */
6556 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6559 rtx insn = chain->insn;
6561 rtx oldequiv_reg = 0;
6564 enum machine_mode mode;
6567 /* delete_output_reload is only invoked properly if old contains
6568 the original pseudo register. Since this is replaced with a
6569 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6570 find the pseudo in RELOAD_IN_REG. */
6571 if (reload_override_in[j]
6572 && REG_P (rl->in_reg))
6579 else if (REG_P (oldequiv))
6580 oldequiv_reg = oldequiv;
6581 else if (GET_CODE (oldequiv) == SUBREG)
6582 oldequiv_reg = SUBREG_REG (oldequiv);
6584 reloadreg = reload_reg_rtx_for_input[j];
6585 mode = GET_MODE (reloadreg);
6587 /* If we are reloading from a register that was recently stored in
6588 with an output-reload, see if we can prove there was
6589 actually no need to store the old value in it. */
6591 if (optimize && REG_P (oldequiv)
6592 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6593 && spill_reg_store[REGNO (oldequiv)]
6595 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6596 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6598 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6600 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
6603 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6604 oldequiv = SUBREG_REG (oldequiv);
6605 if (GET_MODE (oldequiv) != VOIDmode
6606 && mode != GET_MODE (oldequiv))
6607 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6609 /* Switch to the right place to emit the reload insns. */
6610 switch (rl->when_needed)
6613 where = &other_input_reload_insns;
6615 case RELOAD_FOR_INPUT:
6616 where = &input_reload_insns[rl->opnum];
6618 case RELOAD_FOR_INPUT_ADDRESS:
6619 where = &input_address_reload_insns[rl->opnum];
6621 case RELOAD_FOR_INPADDR_ADDRESS:
6622 where = &inpaddr_address_reload_insns[rl->opnum];
6624 case RELOAD_FOR_OUTPUT_ADDRESS:
6625 where = &output_address_reload_insns[rl->opnum];
6627 case RELOAD_FOR_OUTADDR_ADDRESS:
6628 where = &outaddr_address_reload_insns[rl->opnum];
6630 case RELOAD_FOR_OPERAND_ADDRESS:
6631 where = &operand_reload_insns;
6633 case RELOAD_FOR_OPADDR_ADDR:
6634 where = &other_operand_reload_insns;
6636 case RELOAD_FOR_OTHER_ADDRESS:
6637 where = &other_input_address_reload_insns;
6643 push_to_sequence (*where);
6645 /* Auto-increment addresses must be reloaded in a special way. */
6646 if (rl->out && ! rl->out_reg)
6648 /* We are not going to bother supporting the case where a
6649 incremented register can't be copied directly from
6650 OLDEQUIV since this seems highly unlikely. */
6651 gcc_assert (rl->secondary_in_reload < 0);
6653 if (reload_inherited[j])
6654 oldequiv = reloadreg;
6656 old = XEXP (rl->in_reg, 0);
6658 if (optimize && REG_P (oldequiv)
6659 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6660 && spill_reg_store[REGNO (oldequiv)]
6662 && (dead_or_set_p (insn,
6663 spill_reg_stored_to[REGNO (oldequiv)])
6664 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6666 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6668 /* Prevent normal processing of this reload. */
6670 /* Output a special code sequence for this case. */
6671 new_spill_reg_store[REGNO (reloadreg)]
6672 = inc_for_reload (reloadreg, oldequiv, rl->out,
6676 /* If we are reloading a pseudo-register that was set by the previous
6677 insn, see if we can get rid of that pseudo-register entirely
6678 by redirecting the previous insn into our reload register. */
6680 else if (optimize && REG_P (old)
6681 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6682 && dead_or_set_p (insn, old)
6683 /* This is unsafe if some other reload
6684 uses the same reg first. */
6685 && ! conflicts_with_override (reloadreg)
6686 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6687 rl->when_needed, old, rl->out, j, 0))
6689 rtx temp = PREV_INSN (insn);
6690 while (temp && NOTE_P (temp))
6691 temp = PREV_INSN (temp);
6693 && NONJUMP_INSN_P (temp)
6694 && GET_CODE (PATTERN (temp)) == SET
6695 && SET_DEST (PATTERN (temp)) == old
6696 /* Make sure we can access insn_operand_constraint. */
6697 && asm_noperands (PATTERN (temp)) < 0
6698 /* This is unsafe if operand occurs more than once in current
6699 insn. Perhaps some occurrences aren't reloaded. */
6700 && count_occurrences (PATTERN (insn), old, 0) == 1)
6702 rtx old = SET_DEST (PATTERN (temp));
6703 /* Store into the reload register instead of the pseudo. */
6704 SET_DEST (PATTERN (temp)) = reloadreg;
6706 /* Verify that resulting insn is valid. */
6707 extract_insn (temp);
6708 if (constrain_operands (1))
6710 /* If the previous insn is an output reload, the source is
6711 a reload register, and its spill_reg_store entry will
6712 contain the previous destination. This is now
6714 if (REG_P (SET_SRC (PATTERN (temp)))
6715 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6717 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6718 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6721 /* If these are the only uses of the pseudo reg,
6722 pretend for GDB it lives in the reload reg we used. */
6723 if (REG_N_DEATHS (REGNO (old)) == 1
6724 && REG_N_SETS (REGNO (old)) == 1)
6726 reg_renumber[REGNO (old)] = REGNO (reloadreg);
6727 alter_reg (REGNO (old), -1);
6733 SET_DEST (PATTERN (temp)) = old;
6738 /* We can't do that, so output an insn to load RELOADREG. */
6740 /* If we have a secondary reload, pick up the secondary register
6741 and icode, if any. If OLDEQUIV and OLD are different or
6742 if this is an in-out reload, recompute whether or not we
6743 still need a secondary register and what the icode should
6744 be. If we still need a secondary register and the class or
6745 icode is different, go back to reloading from OLD if using
6746 OLDEQUIV means that we got the wrong type of register. We
6747 cannot have different class or icode due to an in-out reload
6748 because we don't make such reloads when both the input and
6749 output need secondary reload registers. */
6751 if (! special && rl->secondary_in_reload >= 0)
6753 rtx second_reload_reg = 0;
6754 rtx third_reload_reg = 0;
6755 int secondary_reload = rl->secondary_in_reload;
6756 rtx real_oldequiv = oldequiv;
6759 enum insn_code icode;
6760 enum insn_code tertiary_icode = CODE_FOR_nothing;
6762 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6763 and similarly for OLD.
6764 See comments in get_secondary_reload in reload.c. */
6765 /* If it is a pseudo that cannot be replaced with its
6766 equivalent MEM, we must fall back to reload_in, which
6767 will have all the necessary substitutions registered.
6768 Likewise for a pseudo that can't be replaced with its
6769 equivalent constant.
6771 Take extra care for subregs of such pseudos. Note that
6772 we cannot use reg_equiv_mem in this case because it is
6773 not in the right mode. */
6776 if (GET_CODE (tmp) == SUBREG)
6777 tmp = SUBREG_REG (tmp);
6779 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6780 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6781 || reg_equiv_constant[REGNO (tmp)] != 0))
6783 if (! reg_equiv_mem[REGNO (tmp)]
6784 || num_not_at_initial_offset
6785 || GET_CODE (oldequiv) == SUBREG)
6786 real_oldequiv = rl->in;
6788 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6792 if (GET_CODE (tmp) == SUBREG)
6793 tmp = SUBREG_REG (tmp);
6795 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6796 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6797 || reg_equiv_constant[REGNO (tmp)] != 0))
6799 if (! reg_equiv_mem[REGNO (tmp)]
6800 || num_not_at_initial_offset
6801 || GET_CODE (old) == SUBREG)
6804 real_old = reg_equiv_mem[REGNO (tmp)];
6807 second_reload_reg = rld[secondary_reload].reg_rtx;
6808 if (rld[secondary_reload].secondary_in_reload >= 0)
6810 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
6812 third_reload_reg = rld[tertiary_reload].reg_rtx;
6813 tertiary_icode = rld[secondary_reload].secondary_in_icode;
6814 /* We'd have to add more code for quartary reloads. */
6815 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
6817 icode = rl->secondary_in_icode;
6819 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6820 || (rl->in != 0 && rl->out != 0))
6822 secondary_reload_info sri, sri2;
6823 enum reg_class new_class, new_t_class;
6825 sri.icode = CODE_FOR_nothing;
6826 sri.prev_sri = NULL;
6827 new_class = targetm.secondary_reload (1, real_oldequiv, rl->rclass,
6830 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
6831 second_reload_reg = 0;
6832 else if (new_class == NO_REGS)
6834 if (reload_adjust_reg_for_icode (&second_reload_reg,
6835 third_reload_reg, sri.icode))
6836 icode = sri.icode, third_reload_reg = 0;
6838 oldequiv = old, real_oldequiv = real_old;
6840 else if (sri.icode != CODE_FOR_nothing)
6841 /* We currently lack a way to express this in reloads. */
6845 sri2.icode = CODE_FOR_nothing;
6846 sri2.prev_sri = &sri;
6847 new_t_class = targetm.secondary_reload (1, real_oldequiv,
6848 new_class, mode, &sri);
6849 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
6851 if (reload_adjust_reg_for_temp (&second_reload_reg,
6854 third_reload_reg = 0, tertiary_icode = sri2.icode;
6856 oldequiv = old, real_oldequiv = real_old;
6858 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
6860 rtx intermediate = second_reload_reg;
6862 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6864 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
6867 second_reload_reg = intermediate;
6868 tertiary_icode = sri2.icode;
6871 oldequiv = old, real_oldequiv = real_old;
6873 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
6875 rtx intermediate = second_reload_reg;
6877 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6879 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
6882 second_reload_reg = intermediate;
6883 tertiary_icode = sri2.icode;
6886 oldequiv = old, real_oldequiv = real_old;
6889 /* This could be handled more intelligently too. */
6890 oldequiv = old, real_oldequiv = real_old;
6894 /* If we still need a secondary reload register, check
6895 to see if it is being used as a scratch or intermediate
6896 register and generate code appropriately. If we need
6897 a scratch register, use REAL_OLDEQUIV since the form of
6898 the insn may depend on the actual address if it is
6901 if (second_reload_reg)
6903 if (icode != CODE_FOR_nothing)
6905 /* We'd have to add extra code to handle this case. */
6906 gcc_assert (!third_reload_reg);
6908 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6909 second_reload_reg));
6914 /* See if we need a scratch register to load the
6915 intermediate register (a tertiary reload). */
6916 if (tertiary_icode != CODE_FOR_nothing)
6918 emit_insn ((GEN_FCN (tertiary_icode)
6919 (second_reload_reg, real_oldequiv,
6920 third_reload_reg)));
6922 else if (third_reload_reg)
6924 gen_reload (third_reload_reg, real_oldequiv,
6927 gen_reload (second_reload_reg, third_reload_reg,
6932 gen_reload (second_reload_reg, real_oldequiv,
6936 oldequiv = second_reload_reg;
6941 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6943 rtx real_oldequiv = oldequiv;
6945 if ((REG_P (oldequiv)
6946 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6947 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6948 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6949 || (GET_CODE (oldequiv) == SUBREG
6950 && REG_P (SUBREG_REG (oldequiv))
6951 && (REGNO (SUBREG_REG (oldequiv))
6952 >= FIRST_PSEUDO_REGISTER)
6953 && ((reg_equiv_memory_loc
6954 [REGNO (SUBREG_REG (oldequiv))] != 0)
6955 || (reg_equiv_constant
6956 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6957 || (CONSTANT_P (oldequiv)
6958 && (PREFERRED_RELOAD_CLASS (oldequiv,
6959 REGNO_REG_CLASS (REGNO (reloadreg)))
6961 real_oldequiv = rl->in;
6962 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6966 if (flag_non_call_exceptions)
6967 copy_eh_notes (insn, get_insns ());
6969 /* End this sequence. */
6970 *where = get_insns ();
6973 /* Update reload_override_in so that delete_address_reloads_1
6974 can see the actual register usage. */
6976 reload_override_in[j] = oldequiv;
6979 /* Generate insns to for the output reload RL, which is for the insn described
6980 by CHAIN and has the number J. */
6982 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6986 rtx insn = chain->insn;
6989 enum machine_mode mode;
6993 if (rl->when_needed == RELOAD_OTHER)
6996 push_to_sequence (output_reload_insns[rl->opnum]);
6998 rl_reg_rtx = reload_reg_rtx_for_output[j];
6999 mode = GET_MODE (rl_reg_rtx);
7001 reloadreg = rl_reg_rtx;
7003 /* If we need two reload regs, set RELOADREG to the intermediate
7004 one, since it will be stored into OLD. We might need a secondary
7005 register only for an input reload, so check again here. */
7007 if (rl->secondary_out_reload >= 0)
7010 int secondary_reload = rl->secondary_out_reload;
7011 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7013 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7014 && reg_equiv_mem[REGNO (old)] != 0)
7015 real_old = reg_equiv_mem[REGNO (old)];
7017 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7019 rtx second_reloadreg = reloadreg;
7020 reloadreg = rld[secondary_reload].reg_rtx;
7022 /* See if RELOADREG is to be used as a scratch register
7023 or as an intermediate register. */
7024 if (rl->secondary_out_icode != CODE_FOR_nothing)
7026 /* We'd have to add extra code to handle this case. */
7027 gcc_assert (tertiary_reload < 0);
7029 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7030 (real_old, second_reloadreg, reloadreg)));
7035 /* See if we need both a scratch and intermediate reload
7038 enum insn_code tertiary_icode
7039 = rld[secondary_reload].secondary_out_icode;
7041 /* We'd have to add more code for quartary reloads. */
7042 gcc_assert (tertiary_reload < 0
7043 || rld[tertiary_reload].secondary_out_reload < 0);
7045 if (GET_MODE (reloadreg) != mode)
7046 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7048 if (tertiary_icode != CODE_FOR_nothing)
7050 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7053 /* Copy primary reload reg to secondary reload reg.
7054 (Note that these have been swapped above, then
7055 secondary reload reg to OLD using our insn.) */
7057 /* If REAL_OLD is a paradoxical SUBREG, remove it
7058 and try to put the opposite SUBREG on
7060 if (GET_CODE (real_old) == SUBREG
7061 && (GET_MODE_SIZE (GET_MODE (real_old))
7062 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7063 && 0 != (tem = gen_lowpart_common
7064 (GET_MODE (SUBREG_REG (real_old)),
7066 real_old = SUBREG_REG (real_old), reloadreg = tem;
7068 gen_reload (reloadreg, second_reloadreg,
7069 rl->opnum, rl->when_needed);
7070 emit_insn ((GEN_FCN (tertiary_icode)
7071 (real_old, reloadreg, third_reloadreg)));
7077 /* Copy between the reload regs here and then to
7080 gen_reload (reloadreg, second_reloadreg,
7081 rl->opnum, rl->when_needed);
7082 if (tertiary_reload >= 0)
7084 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7086 gen_reload (third_reloadreg, reloadreg,
7087 rl->opnum, rl->when_needed);
7088 reloadreg = third_reloadreg;
7095 /* Output the last reload insn. */
7100 /* Don't output the last reload if OLD is not the dest of
7101 INSN and is in the src and is clobbered by INSN. */
7102 if (! flag_expensive_optimizations
7104 || !(set = single_set (insn))
7105 || rtx_equal_p (old, SET_DEST (set))
7106 || !reg_mentioned_p (old, SET_SRC (set))
7107 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7108 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7109 gen_reload (old, reloadreg, rl->opnum,
7113 /* Look at all insns we emitted, just to be safe. */
7114 for (p = get_insns (); p; p = NEXT_INSN (p))
7117 rtx pat = PATTERN (p);
7119 /* If this output reload doesn't come from a spill reg,
7120 clear any memory of reloaded copies of the pseudo reg.
7121 If this output reload comes from a spill reg,
7122 reg_has_output_reload will make this do nothing. */
7123 note_stores (pat, forget_old_reloads_1, NULL);
7125 if (reg_mentioned_p (rl_reg_rtx, pat))
7127 rtx set = single_set (insn);
7128 if (reload_spill_index[j] < 0
7130 && SET_SRC (set) == rl_reg_rtx)
7132 int src = REGNO (SET_SRC (set));
7134 reload_spill_index[j] = src;
7135 SET_HARD_REG_BIT (reg_is_output_reload, src);
7136 if (find_regno_note (insn, REG_DEAD, src))
7137 SET_HARD_REG_BIT (reg_reloaded_died, src);
7139 if (HARD_REGISTER_P (rl_reg_rtx))
7141 int s = rl->secondary_out_reload;
7142 set = single_set (p);
7143 /* If this reload copies only to the secondary reload
7144 register, the secondary reload does the actual
7146 if (s >= 0 && set == NULL_RTX)
7147 /* We can't tell what function the secondary reload
7148 has and where the actual store to the pseudo is
7149 made; leave new_spill_reg_store alone. */
7152 && SET_SRC (set) == rl_reg_rtx
7153 && SET_DEST (set) == rld[s].reg_rtx)
7155 /* Usually the next instruction will be the
7156 secondary reload insn; if we can confirm
7157 that it is, setting new_spill_reg_store to
7158 that insn will allow an extra optimization. */
7159 rtx s_reg = rld[s].reg_rtx;
7160 rtx next = NEXT_INSN (p);
7161 rld[s].out = rl->out;
7162 rld[s].out_reg = rl->out_reg;
7163 set = single_set (next);
7164 if (set && SET_SRC (set) == s_reg
7165 && ! new_spill_reg_store[REGNO (s_reg)])
7167 SET_HARD_REG_BIT (reg_is_output_reload,
7169 new_spill_reg_store[REGNO (s_reg)] = next;
7173 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7178 if (rl->when_needed == RELOAD_OTHER)
7180 emit_insn (other_output_reload_insns[rl->opnum]);
7181 other_output_reload_insns[rl->opnum] = get_insns ();
7184 output_reload_insns[rl->opnum] = get_insns ();
7186 if (flag_non_call_exceptions)
7187 copy_eh_notes (insn, get_insns ());
7192 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7193 and has the number J. */
7195 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7197 rtx insn = chain->insn;
7198 rtx old = (rl->in && MEM_P (rl->in)
7199 ? rl->in_reg : rl->in);
7200 rtx reg_rtx = rl->reg_rtx;
7204 enum machine_mode mode;
7206 /* Determine the mode to reload in.
7207 This is very tricky because we have three to choose from.
7208 There is the mode the insn operand wants (rl->inmode).
7209 There is the mode of the reload register RELOADREG.
7210 There is the intrinsic mode of the operand, which we could find
7211 by stripping some SUBREGs.
7212 It turns out that RELOADREG's mode is irrelevant:
7213 we can change that arbitrarily.
7215 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7216 then the reload reg may not support QImode moves, so use SImode.
7217 If foo is in memory due to spilling a pseudo reg, this is safe,
7218 because the QImode value is in the least significant part of a
7219 slot big enough for a SImode. If foo is some other sort of
7220 memory reference, then it is impossible to reload this case,
7221 so previous passes had better make sure this never happens.
7223 Then consider a one-word union which has SImode and one of its
7224 members is a float, being fetched as (SUBREG:SF union:SI).
7225 We must fetch that as SFmode because we could be loading into
7226 a float-only register. In this case OLD's mode is correct.
7228 Consider an immediate integer: it has VOIDmode. Here we need
7229 to get a mode from something else.
7231 In some cases, there is a fourth mode, the operand's
7232 containing mode. If the insn specifies a containing mode for
7233 this operand, it overrides all others.
7235 I am not sure whether the algorithm here is always right,
7236 but it does the right things in those cases. */
7238 mode = GET_MODE (old);
7239 if (mode == VOIDmode)
7242 /* We cannot use gen_lowpart_common since it can do the wrong thing
7243 when REG_RTX has a multi-word mode. Note that REG_RTX must
7244 always be a REG here. */
7245 if (GET_MODE (reg_rtx) != mode)
7246 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7248 reload_reg_rtx_for_input[j] = reg_rtx;
7251 /* AUTO_INC reloads need to be handled even if inherited. We got an
7252 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7253 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7254 && ! rtx_equal_p (reg_rtx, old)
7256 emit_input_reload_insns (chain, rld + j, old, j);
7258 /* When inheriting a wider reload, we have a MEM in rl->in,
7259 e.g. inheriting a SImode output reload for
7260 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7261 if (optimize && reload_inherited[j] && rl->in
7263 && MEM_P (rl->in_reg)
7264 && reload_spill_index[j] >= 0
7265 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7266 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7268 /* If we are reloading a register that was recently stored in with an
7269 output-reload, see if we can prove there was
7270 actually no need to store the old value in it. */
7273 && (reload_inherited[j] || reload_override_in[j])
7276 && spill_reg_store[REGNO (reg_rtx)] != 0
7278 /* There doesn't seem to be any reason to restrict this to pseudos
7279 and doing so loses in the case where we are copying from a
7280 register of the wrong class. */
7281 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7283 /* The insn might have already some references to stackslots
7284 replaced by MEMs, while reload_out_reg still names the
7286 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7287 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7288 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7291 /* Do output reloading for reload RL, which is for the insn described by
7292 CHAIN and has the number J.
7293 ??? At some point we need to support handling output reloads of
7294 JUMP_INSNs or insns that set cc0. */
7296 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7299 rtx insn = chain->insn;
7300 /* If this is an output reload that stores something that is
7301 not loaded in this same reload, see if we can eliminate a previous
7303 rtx pseudo = rl->out_reg;
7304 rtx reg_rtx = rl->reg_rtx;
7306 if (rl->out && reg_rtx)
7308 enum machine_mode mode;
7310 /* Determine the mode to reload in.
7311 See comments above (for input reloading). */
7312 mode = GET_MODE (rl->out);
7313 if (mode == VOIDmode)
7315 /* VOIDmode should never happen for an output. */
7316 if (asm_noperands (PATTERN (insn)) < 0)
7317 /* It's the compiler's fault. */
7318 fatal_insn ("VOIDmode on an output", insn);
7319 error_for_asm (insn, "output operand is constant in %<asm%>");
7320 /* Prevent crash--use something we know is valid. */
7322 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7324 if (GET_MODE (reg_rtx) != mode)
7325 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7327 reload_reg_rtx_for_output[j] = reg_rtx;
7332 && ! rtx_equal_p (rl->in_reg, pseudo)
7333 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7334 && reg_last_reload_reg[REGNO (pseudo)])
7336 int pseudo_no = REGNO (pseudo);
7337 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7339 /* We don't need to test full validity of last_regno for
7340 inherit here; we only want to know if the store actually
7341 matches the pseudo. */
7342 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7343 && reg_reloaded_contents[last_regno] == pseudo_no
7344 && spill_reg_store[last_regno]
7345 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7346 delete_output_reload (insn, j, last_regno, reg_rtx);
7352 || rtx_equal_p (old, reg_rtx))
7355 /* An output operand that dies right away does need a reload,
7356 but need not be copied from it. Show the new location in the
7358 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7359 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7361 XEXP (note, 0) = reg_rtx;
7364 /* Likewise for a SUBREG of an operand that dies. */
7365 else if (GET_CODE (old) == SUBREG
7366 && REG_P (SUBREG_REG (old))
7367 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7370 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7373 else if (GET_CODE (old) == SCRATCH)
7374 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7375 but we don't want to make an output reload. */
7378 /* If is a JUMP_INSN, we can't support output reloads yet. */
7379 gcc_assert (NONJUMP_INSN_P (insn));
7381 emit_output_reload_insns (chain, rld + j, j);
7384 /* A reload copies values of MODE from register SRC to register DEST.
7385 Return true if it can be treated for inheritance purposes like a
7386 group of reloads, each one reloading a single hard register. The
7387 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7388 occupy the same number of hard registers. */
7391 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
7392 int src ATTRIBUTE_UNUSED,
7393 enum machine_mode mode ATTRIBUTE_UNUSED)
7395 #ifdef CANNOT_CHANGE_MODE_CLASS
7396 return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
7397 && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
7403 /* Output insns to reload values in and out of the chosen reload regs. */
7406 emit_reload_insns (struct insn_chain *chain)
7408 rtx insn = chain->insn;
7412 CLEAR_HARD_REG_SET (reg_reloaded_died);
7414 for (j = 0; j < reload_n_operands; j++)
7415 input_reload_insns[j] = input_address_reload_insns[j]
7416 = inpaddr_address_reload_insns[j]
7417 = output_reload_insns[j] = output_address_reload_insns[j]
7418 = outaddr_address_reload_insns[j]
7419 = other_output_reload_insns[j] = 0;
7420 other_input_address_reload_insns = 0;
7421 other_input_reload_insns = 0;
7422 operand_reload_insns = 0;
7423 other_operand_reload_insns = 0;
7425 /* Dump reloads into the dump file. */
7428 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7429 debug_reload_to_stream (dump_file);
7432 /* Now output the instructions to copy the data into and out of the
7433 reload registers. Do these in the order that the reloads were reported,
7434 since reloads of base and index registers precede reloads of operands
7435 and the operands may need the base and index registers reloaded. */
7437 for (j = 0; j < n_reloads; j++)
7439 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
7443 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
7444 new_spill_reg_store[i] = 0;
7447 do_input_reload (chain, rld + j, j);
7448 do_output_reload (chain, rld + j, j);
7451 /* Now write all the insns we made for reloads in the order expected by
7452 the allocation functions. Prior to the insn being reloaded, we write
7453 the following reloads:
7455 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7457 RELOAD_OTHER reloads.
7459 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7460 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7461 RELOAD_FOR_INPUT reload for the operand.
7463 RELOAD_FOR_OPADDR_ADDRS reloads.
7465 RELOAD_FOR_OPERAND_ADDRESS reloads.
7467 After the insn being reloaded, we write the following:
7469 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7470 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7471 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7472 reloads for the operand. The RELOAD_OTHER output reloads are
7473 output in descending order by reload number. */
7475 emit_insn_before (other_input_address_reload_insns, insn);
7476 emit_insn_before (other_input_reload_insns, insn);
7478 for (j = 0; j < reload_n_operands; j++)
7480 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7481 emit_insn_before (input_address_reload_insns[j], insn);
7482 emit_insn_before (input_reload_insns[j], insn);
7485 emit_insn_before (other_operand_reload_insns, insn);
7486 emit_insn_before (operand_reload_insns, insn);
7488 for (j = 0; j < reload_n_operands; j++)
7490 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7491 x = emit_insn_after (output_address_reload_insns[j], x);
7492 x = emit_insn_after (output_reload_insns[j], x);
7493 emit_insn_after (other_output_reload_insns[j], x);
7496 /* For all the spill regs newly reloaded in this instruction,
7497 record what they were reloaded from, so subsequent instructions
7498 can inherit the reloads.
7500 Update spill_reg_store for the reloads of this insn.
7501 Copy the elements that were updated in the loop above. */
7503 for (j = 0; j < n_reloads; j++)
7505 int r = reload_order[j];
7506 int i = reload_spill_index[r];
7508 /* If this is a non-inherited input reload from a pseudo, we must
7509 clear any memory of a previous store to the same pseudo. Only do
7510 something if there will not be an output reload for the pseudo
7512 if (rld[r].in_reg != 0
7513 && ! (reload_inherited[r] || reload_override_in[r]))
7515 rtx reg = rld[r].in_reg;
7517 if (GET_CODE (reg) == SUBREG)
7518 reg = SUBREG_REG (reg);
7521 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7522 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7524 int nregno = REGNO (reg);
7526 if (reg_last_reload_reg[nregno])
7528 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7530 if (reg_reloaded_contents[last_regno] == nregno)
7531 spill_reg_store[last_regno] = 0;
7536 /* I is nonneg if this reload used a register.
7537 If rld[r].reg_rtx is 0, this is an optional reload
7538 that we opted to ignore. */
7540 if (i >= 0 && rld[r].reg_rtx != 0)
7542 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7545 /* For a multi register reload, we need to check if all or part
7546 of the value lives to the end. */
7547 for (k = 0; k < nr; k++)
7548 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7549 rld[r].when_needed))
7550 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7552 /* Maybe the spill reg contains a copy of reload_out. */
7554 && (REG_P (rld[r].out)
7558 || REG_P (rld[r].out_reg)))
7561 enum machine_mode mode;
7564 reg = reload_reg_rtx_for_output[r];
7565 mode = GET_MODE (reg);
7566 regno = REGNO (reg);
7567 nregs = hard_regno_nregs[regno][mode];
7568 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7569 rld[r].when_needed))
7571 rtx out = (REG_P (rld[r].out)
7575 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7576 int out_regno = REGNO (out);
7577 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
7578 : hard_regno_nregs[out_regno][mode]);
7581 spill_reg_store[regno] = new_spill_reg_store[regno];
7582 spill_reg_stored_to[regno] = out;
7583 reg_last_reload_reg[out_regno] = reg;
7585 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
7586 && nregs == out_nregs
7587 && inherit_piecemeal_p (out_regno, regno, mode));
7589 /* If OUT_REGNO is a hard register, it may occupy more than
7590 one register. If it does, say what is in the
7591 rest of the registers assuming that both registers
7592 agree on how many words the object takes. If not,
7593 invalidate the subsequent registers. */
7595 if (HARD_REGISTER_NUM_P (out_regno))
7596 for (k = 1; k < out_nregs; k++)
7597 reg_last_reload_reg[out_regno + k]
7598 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7600 /* Now do the inverse operation. */
7601 for (k = 0; k < nregs; k++)
7603 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
7604 reg_reloaded_contents[regno + k]
7605 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
7608 reg_reloaded_insn[regno + k] = insn;
7609 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
7610 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
7611 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7614 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7619 /* Maybe the spill reg contains a copy of reload_in. Only do
7620 something if there will not be an output reload for
7621 the register being reloaded. */
7622 else if (rld[r].out_reg == 0
7624 && ((REG_P (rld[r].in)
7625 && !HARD_REGISTER_P (rld[r].in)
7626 && !REGNO_REG_SET_P (®_has_output_reload,
7628 || (REG_P (rld[r].in_reg)
7629 && !REGNO_REG_SET_P (®_has_output_reload,
7630 REGNO (rld[r].in_reg))))
7631 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
7634 enum machine_mode mode;
7637 reg = reload_reg_rtx_for_input[r];
7638 mode = GET_MODE (reg);
7639 regno = REGNO (reg);
7640 nregs = hard_regno_nregs[regno][mode];
7641 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7642 rld[r].when_needed))
7649 if (REG_P (rld[r].in)
7650 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7652 else if (REG_P (rld[r].in_reg))
7655 in = XEXP (rld[r].in_reg, 0);
7656 in_regno = REGNO (in);
7658 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
7659 : hard_regno_nregs[in_regno][mode]);
7661 reg_last_reload_reg[in_regno] = reg;
7663 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
7664 && nregs == in_nregs
7665 && inherit_piecemeal_p (regno, in_regno, mode));
7667 if (HARD_REGISTER_NUM_P (in_regno))
7668 for (k = 1; k < in_nregs; k++)
7669 reg_last_reload_reg[in_regno + k]
7670 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7672 /* Unless we inherited this reload, show we haven't
7673 recently done a store.
7674 Previous stores of inherited auto_inc expressions
7675 also have to be discarded. */
7676 if (! reload_inherited[r]
7677 || (rld[r].out && ! rld[r].out_reg))
7678 spill_reg_store[regno] = 0;
7680 for (k = 0; k < nregs; k++)
7682 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
7683 reg_reloaded_contents[regno + k]
7684 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
7687 reg_reloaded_insn[regno + k] = insn;
7688 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
7689 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
7690 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7693 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7700 /* The following if-statement was #if 0'd in 1.34 (or before...).
7701 It's reenabled in 1.35 because supposedly nothing else
7702 deals with this problem. */
7704 /* If a register gets output-reloaded from a non-spill register,
7705 that invalidates any previous reloaded copy of it.
7706 But forget_old_reloads_1 won't get to see it, because
7707 it thinks only about the original insn. So invalidate it here.
7708 Also do the same thing for RELOAD_OTHER constraints where the
7709 output is discarded. */
7711 && ((rld[r].out != 0
7712 && (REG_P (rld[r].out)
7713 || (MEM_P (rld[r].out)
7714 && REG_P (rld[r].out_reg))))
7715 || (rld[r].out == 0 && rld[r].out_reg
7716 && REG_P (rld[r].out_reg))))
7718 rtx out = ((rld[r].out && REG_P (rld[r].out))
7719 ? rld[r].out : rld[r].out_reg);
7720 int out_regno = REGNO (out);
7721 enum machine_mode mode = GET_MODE (out);
7723 /* REG_RTX is now set or clobbered by the main instruction.
7724 As the comment above explains, forget_old_reloads_1 only
7725 sees the original instruction, and there is no guarantee
7726 that the original instruction also clobbered REG_RTX.
7727 For example, if find_reloads sees that the input side of
7728 a matched operand pair dies in this instruction, it may
7729 use the input register as the reload register.
7731 Calling forget_old_reloads_1 is a waste of effort if
7732 REG_RTX is also the output register.
7734 If we know that REG_RTX holds the value of a pseudo
7735 register, the code after the call will record that fact. */
7736 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
7737 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
7739 if (!HARD_REGISTER_NUM_P (out_regno))
7741 rtx src_reg, store_insn = NULL_RTX;
7743 reg_last_reload_reg[out_regno] = 0;
7745 /* If we can find a hard register that is stored, record
7746 the storing insn so that we may delete this insn with
7747 delete_output_reload. */
7748 src_reg = reload_reg_rtx_for_output[r];
7750 /* If this is an optional reload, try to find the source reg
7751 from an input reload. */
7754 rtx set = single_set (insn);
7755 if (set && SET_DEST (set) == rld[r].out)
7759 src_reg = SET_SRC (set);
7761 for (k = 0; k < n_reloads; k++)
7763 if (rld[k].in == src_reg)
7765 src_reg = reload_reg_rtx_for_input[k];
7772 store_insn = new_spill_reg_store[REGNO (src_reg)];
7773 if (src_reg && REG_P (src_reg)
7774 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7776 int src_regno, src_nregs, k;
7779 gcc_assert (GET_MODE (src_reg) == mode);
7780 src_regno = REGNO (src_reg);
7781 src_nregs = hard_regno_nregs[src_regno][mode];
7782 /* The place where to find a death note varies with
7783 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7784 necessarily checked exactly in the code that moves
7785 notes, so just check both locations. */
7786 note = find_regno_note (insn, REG_DEAD, src_regno);
7787 if (! note && store_insn)
7788 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7789 for (k = 0; k < src_nregs; k++)
7791 spill_reg_store[src_regno + k] = store_insn;
7792 spill_reg_stored_to[src_regno + k] = out;
7793 reg_reloaded_contents[src_regno + k] = out_regno;
7794 reg_reloaded_insn[src_regno + k] = store_insn;
7795 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
7796 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
7797 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
7799 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7802 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7804 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
7806 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7808 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7810 reg_last_reload_reg[out_regno] = src_reg;
7811 /* We have to set reg_has_output_reload here, or else
7812 forget_old_reloads_1 will clear reg_last_reload_reg
7814 SET_REGNO_REG_SET (®_has_output_reload,
7820 int k, out_nregs = hard_regno_nregs[out_regno][mode];
7822 for (k = 0; k < out_nregs; k++)
7823 reg_last_reload_reg[out_regno + k] = 0;
7827 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7830 /* Go through the motions to emit INSN and test if it is strictly valid.
7831 Return the emitted insn if valid, else return NULL. */
7834 emit_insn_if_valid_for_reload (rtx insn)
7836 rtx last = get_last_insn ();
7839 insn = emit_insn (insn);
7840 code = recog_memoized (insn);
7844 extract_insn (insn);
7845 /* We want constrain operands to treat this insn strictly in its
7846 validity determination, i.e., the way it would after reload has
7848 if (constrain_operands (1))
7852 delete_insns_since (last);
7856 /* Emit code to perform a reload from IN (which may be a reload register) to
7857 OUT (which may also be a reload register). IN or OUT is from operand
7858 OPNUM with reload type TYPE.
7860 Returns first insn emitted. */
7863 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7865 rtx last = get_last_insn ();
7868 /* If IN is a paradoxical SUBREG, remove it and try to put the
7869 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7870 if (GET_CODE (in) == SUBREG
7871 && (GET_MODE_SIZE (GET_MODE (in))
7872 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7873 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7874 in = SUBREG_REG (in), out = tem;
7875 else if (GET_CODE (out) == SUBREG
7876 && (GET_MODE_SIZE (GET_MODE (out))
7877 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7878 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7879 out = SUBREG_REG (out), in = tem;
7881 /* How to do this reload can get quite tricky. Normally, we are being
7882 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7883 register that didn't get a hard register. In that case we can just
7884 call emit_move_insn.
7886 We can also be asked to reload a PLUS that adds a register or a MEM to
7887 another register, constant or MEM. This can occur during frame pointer
7888 elimination and while reloading addresses. This case is handled by
7889 trying to emit a single insn to perform the add. If it is not valid,
7890 we use a two insn sequence.
7892 Or we can be asked to reload an unary operand that was a fragment of
7893 an addressing mode, into a register. If it isn't recognized as-is,
7894 we try making the unop operand and the reload-register the same:
7895 (set reg:X (unop:X expr:Y))
7896 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
7898 Finally, we could be called to handle an 'o' constraint by putting
7899 an address into a register. In that case, we first try to do this
7900 with a named pattern of "reload_load_address". If no such pattern
7901 exists, we just emit a SET insn and hope for the best (it will normally
7902 be valid on machines that use 'o').
7904 This entire process is made complex because reload will never
7905 process the insns we generate here and so we must ensure that
7906 they will fit their constraints and also by the fact that parts of
7907 IN might be being reloaded separately and replaced with spill registers.
7908 Because of this, we are, in some sense, just guessing the right approach
7909 here. The one listed above seems to work.
7911 ??? At some point, this whole thing needs to be rethought. */
7913 if (GET_CODE (in) == PLUS
7914 && (REG_P (XEXP (in, 0))
7915 || GET_CODE (XEXP (in, 0)) == SUBREG
7916 || MEM_P (XEXP (in, 0)))
7917 && (REG_P (XEXP (in, 1))
7918 || GET_CODE (XEXP (in, 1)) == SUBREG
7919 || CONSTANT_P (XEXP (in, 1))
7920 || MEM_P (XEXP (in, 1))))
7922 /* We need to compute the sum of a register or a MEM and another
7923 register, constant, or MEM, and put it into the reload
7924 register. The best possible way of doing this is if the machine
7925 has a three-operand ADD insn that accepts the required operands.
7927 The simplest approach is to try to generate such an insn and see if it
7928 is recognized and matches its constraints. If so, it can be used.
7930 It might be better not to actually emit the insn unless it is valid,
7931 but we need to pass the insn as an operand to `recog' and
7932 `extract_insn' and it is simpler to emit and then delete the insn if
7933 not valid than to dummy things up. */
7935 rtx op0, op1, tem, insn;
7938 op0 = find_replacement (&XEXP (in, 0));
7939 op1 = find_replacement (&XEXP (in, 1));
7941 /* Since constraint checking is strict, commutativity won't be
7942 checked, so we need to do that here to avoid spurious failure
7943 if the add instruction is two-address and the second operand
7944 of the add is the same as the reload reg, which is frequently
7945 the case. If the insn would be A = B + A, rearrange it so
7946 it will be A = A + B as constrain_operands expects. */
7948 if (REG_P (XEXP (in, 1))
7949 && REGNO (out) == REGNO (XEXP (in, 1)))
7950 tem = op0, op0 = op1, op1 = tem;
7952 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7953 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7955 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7959 /* If that failed, we must use a conservative two-insn sequence.
7961 Use a move to copy one operand into the reload register. Prefer
7962 to reload a constant, MEM or pseudo since the move patterns can
7963 handle an arbitrary operand. If OP1 is not a constant, MEM or
7964 pseudo and OP1 is not a valid operand for an add instruction, then
7967 After reloading one of the operands into the reload register, add
7968 the reload register to the output register.
7970 If there is another way to do this for a specific machine, a
7971 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7974 code = (int) optab_handler (add_optab, GET_MODE (out))->insn_code;
7976 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7978 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7979 || (code != CODE_FOR_nothing
7980 && ! ((*insn_data[code].operand[2].predicate)
7981 (op1, insn_data[code].operand[2].mode))))
7982 tem = op0, op0 = op1, op1 = tem;
7984 gen_reload (out, op0, opnum, type);
7986 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7987 This fixes a problem on the 32K where the stack pointer cannot
7988 be used as an operand of an add insn. */
7990 if (rtx_equal_p (op0, op1))
7993 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
7996 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7997 set_unique_reg_note (insn, REG_EQUIV, in);
8001 /* If that failed, copy the address register to the reload register.
8002 Then add the constant to the reload register. */
8004 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8005 gen_reload (out, op1, opnum, type);
8006 insn = emit_insn (gen_add2_insn (out, op0));
8007 set_unique_reg_note (insn, REG_EQUIV, in);
8010 #ifdef SECONDARY_MEMORY_NEEDED
8011 /* If we need a memory location to do the move, do it that way. */
8012 else if ((REG_P (in)
8013 || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
8014 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
8016 || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
8017 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
8018 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
8019 REGNO_REG_CLASS (reg_or_subregno (out)),
8022 /* Get the memory to use and rewrite both registers to its mode. */
8023 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8025 if (GET_MODE (loc) != GET_MODE (out))
8026 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
8028 if (GET_MODE (loc) != GET_MODE (in))
8029 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
8031 gen_reload (loc, in, opnum, type);
8032 gen_reload (out, loc, opnum, type);
8035 else if (REG_P (out) && UNARY_P (in))
8042 op1 = find_replacement (&XEXP (in, 0));
8043 if (op1 != XEXP (in, 0))
8044 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8046 /* First, try a plain SET. */
8047 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8051 /* If that failed, move the inner operand to the reload
8052 register, and try the same unop with the inner expression
8053 replaced with the reload register. */
8055 if (GET_MODE (op1) != GET_MODE (out))
8056 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8060 gen_reload (out_moded, op1, opnum, type);
8063 = gen_rtx_SET (VOIDmode, out,
8064 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8066 insn = emit_insn_if_valid_for_reload (insn);
8069 set_unique_reg_note (insn, REG_EQUIV, in);
8073 fatal_insn ("Failure trying to reload:", set);
8075 /* If IN is a simple operand, use gen_move_insn. */
8076 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8078 tem = emit_insn (gen_move_insn (out, in));
8079 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8080 mark_jump_label (in, tem, 0);
8083 #ifdef HAVE_reload_load_address
8084 else if (HAVE_reload_load_address)
8085 emit_insn (gen_reload_load_address (out, in));
8088 /* Otherwise, just write (set OUT IN) and hope for the best. */
8090 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8092 /* Return the first insn emitted.
8093 We can not just return get_last_insn, because there may have
8094 been multiple instructions emitted. Also note that gen_move_insn may
8095 emit more than one insn itself, so we can not assume that there is one
8096 insn emitted per emit_insn_before call. */
8098 return last ? NEXT_INSN (last) : get_insns ();
8101 /* Delete a previously made output-reload whose result we now believe
8102 is not needed. First we double-check.
8104 INSN is the insn now being processed.
8105 LAST_RELOAD_REG is the hard register number for which we want to delete
8106 the last output reload.
8107 J is the reload-number that originally used REG. The caller has made
8108 certain that reload J doesn't use REG any longer for input.
8109 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8112 delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg)
8114 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8115 rtx reg = spill_reg_stored_to[last_reload_reg];
8118 int n_inherited = 0;
8122 /* It is possible that this reload has been only used to set another reload
8123 we eliminated earlier and thus deleted this instruction too. */
8124 if (INSN_DELETED_P (output_reload_insn))
8127 /* Get the raw pseudo-register referred to. */
8129 while (GET_CODE (reg) == SUBREG)
8130 reg = SUBREG_REG (reg);
8131 substed = reg_equiv_memory_loc[REGNO (reg)];
8133 /* This is unsafe if the operand occurs more often in the current
8134 insn than it is inherited. */
8135 for (k = n_reloads - 1; k >= 0; k--)
8137 rtx reg2 = rld[k].in;
8140 if (MEM_P (reg2) || reload_override_in[k])
8141 reg2 = rld[k].in_reg;
8143 if (rld[k].out && ! rld[k].out_reg)
8144 reg2 = XEXP (rld[k].in_reg, 0);
8146 while (GET_CODE (reg2) == SUBREG)
8147 reg2 = SUBREG_REG (reg2);
8148 if (rtx_equal_p (reg2, reg))
8150 if (reload_inherited[k] || reload_override_in[k] || k == j)
8156 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8157 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8158 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8161 n_occurrences += count_occurrences (PATTERN (insn),
8162 eliminate_regs (substed, 0,
8164 for (i1 = reg_equiv_alt_mem_list [REGNO (reg)]; i1; i1 = XEXP (i1, 1))
8166 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8167 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8169 if (n_occurrences > n_inherited)
8172 /* If the pseudo-reg we are reloading is no longer referenced
8173 anywhere between the store into it and here,
8174 and we're within the same basic block, then the value can only
8175 pass through the reload reg and end up here.
8176 Otherwise, give up--return. */
8177 for (i1 = NEXT_INSN (output_reload_insn);
8178 i1 != insn; i1 = NEXT_INSN (i1))
8180 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8182 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8183 && reg_mentioned_p (reg, PATTERN (i1)))
8185 /* If this is USE in front of INSN, we only have to check that
8186 there are no more references than accounted for by inheritance. */
8187 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8189 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8190 i1 = NEXT_INSN (i1);
8192 if (n_occurrences <= n_inherited && i1 == insn)
8198 /* We will be deleting the insn. Remove the spill reg information. */
8199 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8201 spill_reg_store[last_reload_reg + k] = 0;
8202 spill_reg_stored_to[last_reload_reg + k] = 0;
8205 /* The caller has already checked that REG dies or is set in INSN.
8206 It has also checked that we are optimizing, and thus some
8207 inaccuracies in the debugging information are acceptable.
8208 So we could just delete output_reload_insn. But in some cases
8209 we can improve the debugging information without sacrificing
8210 optimization - maybe even improving the code: See if the pseudo
8211 reg has been completely replaced with reload regs. If so, delete
8212 the store insn and forget we had a stack slot for the pseudo. */
8213 if (rld[j].out != rld[j].in
8214 && REG_N_DEATHS (REGNO (reg)) == 1
8215 && REG_N_SETS (REGNO (reg)) == 1
8216 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8217 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8221 /* We know that it was used only between here and the beginning of
8222 the current basic block. (We also know that the last use before
8223 INSN was the output reload we are thinking of deleting, but never
8224 mind that.) Search that range; see if any ref remains. */
8225 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8227 rtx set = single_set (i2);
8229 /* Uses which just store in the pseudo don't count,
8230 since if they are the only uses, they are dead. */
8231 if (set != 0 && SET_DEST (set) == reg)
8236 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8237 && reg_mentioned_p (reg, PATTERN (i2)))
8239 /* Some other ref remains; just delete the output reload we
8241 delete_address_reloads (output_reload_insn, insn);
8242 delete_insn (output_reload_insn);
8247 /* Delete the now-dead stores into this pseudo. Note that this
8248 loop also takes care of deleting output_reload_insn. */
8249 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8251 rtx set = single_set (i2);
8253 if (set != 0 && SET_DEST (set) == reg)
8255 delete_address_reloads (i2, insn);
8263 /* For the debugging info, say the pseudo lives in this reload reg. */
8264 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8265 alter_reg (REGNO (reg), -1);
8269 delete_address_reloads (output_reload_insn, insn);
8270 delete_insn (output_reload_insn);
8274 /* We are going to delete DEAD_INSN. Recursively delete loads of
8275 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8276 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8278 delete_address_reloads (rtx dead_insn, rtx current_insn)
8280 rtx set = single_set (dead_insn);
8281 rtx set2, dst, prev, next;
8284 rtx dst = SET_DEST (set);
8286 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8288 /* If we deleted the store from a reloaded post_{in,de}c expression,
8289 we can delete the matching adds. */
8290 prev = PREV_INSN (dead_insn);
8291 next = NEXT_INSN (dead_insn);
8292 if (! prev || ! next)
8294 set = single_set (next);
8295 set2 = single_set (prev);
8297 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8298 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8299 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8301 dst = SET_DEST (set);
8302 if (! rtx_equal_p (dst, SET_DEST (set2))
8303 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8304 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8305 || (INTVAL (XEXP (SET_SRC (set), 1))
8306 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8308 delete_related_insns (prev);
8309 delete_related_insns (next);
8312 /* Subfunction of delete_address_reloads: process registers found in X. */
8314 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8316 rtx prev, set, dst, i2;
8318 enum rtx_code code = GET_CODE (x);
8322 const char *fmt = GET_RTX_FORMAT (code);
8323 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8326 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8327 else if (fmt[i] == 'E')
8329 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8330 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8337 if (spill_reg_order[REGNO (x)] < 0)
8340 /* Scan backwards for the insn that sets x. This might be a way back due
8342 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8344 code = GET_CODE (prev);
8345 if (code == CODE_LABEL || code == JUMP_INSN)
8349 if (reg_set_p (x, PATTERN (prev)))
8351 if (reg_referenced_p (x, PATTERN (prev)))
8354 if (! prev || INSN_UID (prev) < reload_first_uid)
8356 /* Check that PREV only sets the reload register. */
8357 set = single_set (prev);
8360 dst = SET_DEST (set);
8362 || ! rtx_equal_p (dst, x))
8364 if (! reg_set_p (dst, PATTERN (dead_insn)))
8366 /* Check if DST was used in a later insn -
8367 it might have been inherited. */
8368 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8374 if (reg_referenced_p (dst, PATTERN (i2)))
8376 /* If there is a reference to the register in the current insn,
8377 it might be loaded in a non-inherited reload. If no other
8378 reload uses it, that means the register is set before
8380 if (i2 == current_insn)
8382 for (j = n_reloads - 1; j >= 0; j--)
8383 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8384 || reload_override_in[j] == dst)
8386 for (j = n_reloads - 1; j >= 0; j--)
8387 if (rld[j].in && rld[j].reg_rtx == dst)
8396 /* If DST is still live at CURRENT_INSN, check if it is used for
8397 any reload. Note that even if CURRENT_INSN sets DST, we still
8398 have to check the reloads. */
8399 if (i2 == current_insn)
8401 for (j = n_reloads - 1; j >= 0; j--)
8402 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8403 || reload_override_in[j] == dst)
8405 /* ??? We can't finish the loop here, because dst might be
8406 allocated to a pseudo in this block if no reload in this
8407 block needs any of the classes containing DST - see
8408 spill_hard_reg. There is no easy way to tell this, so we
8409 have to scan till the end of the basic block. */
8411 if (reg_set_p (dst, PATTERN (i2)))
8415 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8416 reg_reloaded_contents[REGNO (dst)] = -1;
8420 /* Output reload-insns to reload VALUE into RELOADREG.
8421 VALUE is an autoincrement or autodecrement RTX whose operand
8422 is a register or memory location;
8423 so reloading involves incrementing that location.
8424 IN is either identical to VALUE, or some cheaper place to reload from.
8426 INC_AMOUNT is the number to increment or decrement by (always positive).
8427 This cannot be deduced from VALUE.
8429 Return the instruction that stores into RELOADREG. */
8432 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8434 /* REG or MEM to be copied and incremented. */
8435 rtx incloc = find_replacement (&XEXP (value, 0));
8436 /* Nonzero if increment after copying. */
8437 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8438 || GET_CODE (value) == POST_MODIFY);
8444 rtx real_in = in == value ? incloc : in;
8446 /* No hard register is equivalent to this register after
8447 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8448 we could inc/dec that register as well (maybe even using it for
8449 the source), but I'm not sure it's worth worrying about. */
8451 reg_last_reload_reg[REGNO (incloc)] = 0;
8453 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8455 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8456 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8460 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8461 inc_amount = -inc_amount;
8463 inc = GEN_INT (inc_amount);
8466 /* If this is post-increment, first copy the location to the reload reg. */
8467 if (post && real_in != reloadreg)
8468 emit_insn (gen_move_insn (reloadreg, real_in));
8472 /* See if we can directly increment INCLOC. Use a method similar to
8473 that in gen_reload. */
8475 last = get_last_insn ();
8476 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8477 gen_rtx_PLUS (GET_MODE (incloc),
8480 code = recog_memoized (add_insn);
8483 extract_insn (add_insn);
8484 if (constrain_operands (1))
8486 /* If this is a pre-increment and we have incremented the value
8487 where it lives, copy the incremented value to RELOADREG to
8488 be used as an address. */
8491 emit_insn (gen_move_insn (reloadreg, incloc));
8496 delete_insns_since (last);
8499 /* If couldn't do the increment directly, must increment in RELOADREG.
8500 The way we do this depends on whether this is pre- or post-increment.
8501 For pre-increment, copy INCLOC to the reload register, increment it
8502 there, then save back. */
8506 if (in != reloadreg)
8507 emit_insn (gen_move_insn (reloadreg, real_in));
8508 emit_insn (gen_add2_insn (reloadreg, inc));
8509 store = emit_insn (gen_move_insn (incloc, reloadreg));
8514 Because this might be a jump insn or a compare, and because RELOADREG
8515 may not be available after the insn in an input reload, we must do
8516 the incrementation before the insn being reloaded for.
8518 We have already copied IN to RELOADREG. Increment the copy in
8519 RELOADREG, save that back, then decrement RELOADREG so it has
8520 the original value. */
8522 emit_insn (gen_add2_insn (reloadreg, inc));
8523 store = emit_insn (gen_move_insn (incloc, reloadreg));
8524 if (GET_CODE (inc) == CONST_INT)
8525 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
8527 emit_insn (gen_sub2_insn (reloadreg, inc));
8535 add_auto_inc_notes (rtx insn, rtx x)
8537 enum rtx_code code = GET_CODE (x);
8541 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8543 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
8547 /* Scan all the operand sub-expressions. */
8548 fmt = GET_RTX_FORMAT (code);
8549 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8552 add_auto_inc_notes (insn, XEXP (x, i));
8553 else if (fmt[i] == 'E')
8554 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8555 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8560 /* Copy EH notes from an insn to its reloads. */
8562 copy_eh_notes (rtx insn, rtx x)
8564 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8567 for (; x != 0; x = NEXT_INSN (x))
8569 if (may_trap_p (PATTERN (x)))
8570 add_reg_note (x, REG_EH_REGION, XEXP (eh_note, 0));
8575 /* This is used by reload pass, that does emit some instructions after
8576 abnormal calls moving basic block end, but in fact it wants to emit
8577 them on the edge. Looks for abnormal call edges, find backward the
8578 proper call and fix the damage.
8580 Similar handle instructions throwing exceptions internally. */
8582 fixup_abnormal_edges (void)
8584 bool inserted = false;
8592 /* Look for cases we are interested in - calls or instructions causing
8594 FOR_EACH_EDGE (e, ei, bb->succs)
8596 if (e->flags & EDGE_ABNORMAL_CALL)
8598 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8599 == (EDGE_ABNORMAL | EDGE_EH))
8602 if (e && !CALL_P (BB_END (bb))
8603 && !can_throw_internal (BB_END (bb)))
8607 /* Get past the new insns generated. Allow notes, as the insns
8608 may be already deleted. */
8610 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8611 && !can_throw_internal (insn)
8612 && insn != BB_HEAD (bb))
8613 insn = PREV_INSN (insn);
8615 if (CALL_P (insn) || can_throw_internal (insn))
8619 stop = NEXT_INSN (BB_END (bb));
8621 insn = NEXT_INSN (insn);
8623 FOR_EACH_EDGE (e, ei, bb->succs)
8624 if (e->flags & EDGE_FALLTHRU)
8627 while (insn && insn != stop)
8629 next = NEXT_INSN (insn);
8634 /* Sometimes there's still the return value USE.
8635 If it's placed after a trapping call (i.e. that
8636 call is the last insn anyway), we have no fallthru
8637 edge. Simply delete this use and don't try to insert
8638 on the non-existent edge. */
8639 if (GET_CODE (PATTERN (insn)) != USE)
8641 /* We're not deleting it, we're moving it. */
8642 INSN_DELETED_P (insn) = 0;
8643 PREV_INSN (insn) = NULL_RTX;
8644 NEXT_INSN (insn) = NULL_RTX;
8646 insert_insn_on_edge (insn, e);
8650 else if (!BARRIER_P (insn))
8651 set_block_for_insn (insn, NULL);
8656 /* It may be that we don't find any such trapping insn. In this
8657 case we discovered quite late that the insn that had been
8658 marked as can_throw_internal in fact couldn't trap at all.
8659 So we should in fact delete the EH edges out of the block. */
8661 purge_dead_edges (bb);
8665 /* We've possibly turned single trapping insn into multiple ones. */
8666 if (flag_non_call_exceptions)
8669 blocks = sbitmap_alloc (last_basic_block);
8670 sbitmap_ones (blocks);
8671 find_many_sub_basic_blocks (blocks);
8672 sbitmap_free (blocks);
8676 commit_edge_insertions ();
8678 #ifdef ENABLE_CHECKING
8679 /* Verify that we didn't turn one trapping insn into many, and that
8680 we found and corrected all of the problems wrt fixups on the
8682 verify_flow_info ();
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