1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 88, 89, 92-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "insn-flags.h"
32 #include "insn-codes.h"
37 #include "basic-block.h"
44 #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY
45 #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
48 /* This file contains the reload pass of the compiler, which is
49 run after register allocation has been done. It checks that
50 each insn is valid (operands required to be in registers really
51 are in registers of the proper class) and fixes up invalid ones
52 by copying values temporarily into registers for the insns
55 The results of register allocation are described by the vector
56 reg_renumber; the insns still contain pseudo regs, but reg_renumber
57 can be used to find which hard reg, if any, a pseudo reg is in.
59 The technique we always use is to free up a few hard regs that are
60 called ``reload regs'', and for each place where a pseudo reg
61 must be in a hard reg, copy it temporarily into one of the reload regs.
63 Reload regs are allocated locally for every instruction that needs
64 reloads. When there are pseudos which are allocated to a register that
65 has been chosen as a reload reg, such pseudos must be ``spilled''.
66 This means that they go to other hard regs, or to stack slots if no other
67 available hard regs can be found. Spilling can invalidate more
68 insns, requiring additional need for reloads, so we must keep checking
69 until the process stabilizes.
71 For machines with different classes of registers, we must keep track
72 of the register class needed for each reload, and make sure that
73 we allocate enough reload registers of each class.
75 The file reload.c contains the code that checks one insn for
76 validity and reports the reloads that it needs. This file
77 is in charge of scanning the entire rtl code, accumulating the
78 reload needs, spilling, assigning reload registers to use for
79 fixing up each insn, and generating the new insns to copy values
80 into the reload registers. */
83 #ifndef REGISTER_MOVE_COST
84 #define REGISTER_MOVE_COST(x, y) 2
87 /* During reload_as_needed, element N contains a REG rtx for the hard reg
88 into which reg N has been reloaded (perhaps for a previous insn). */
89 static rtx *reg_last_reload_reg;
91 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
92 for an output reload that stores into reg N. */
93 static char *reg_has_output_reload;
95 /* Indicates which hard regs are reload-registers for an output reload
96 in the current insn. */
97 static HARD_REG_SET reg_is_output_reload;
99 /* Element N is the constant value to which pseudo reg N is equivalent,
100 or zero if pseudo reg N is not equivalent to a constant.
101 find_reloads looks at this in order to replace pseudo reg N
102 with the constant it stands for. */
103 rtx *reg_equiv_constant;
105 /* Element N is a memory location to which pseudo reg N is equivalent,
106 prior to any register elimination (such as frame pointer to stack
107 pointer). Depending on whether or not it is a valid address, this value
108 is transferred to either reg_equiv_address or reg_equiv_mem. */
109 rtx *reg_equiv_memory_loc;
111 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
112 This is used when the address is not valid as a memory address
113 (because its displacement is too big for the machine.) */
114 rtx *reg_equiv_address;
116 /* Element N is the memory slot to which pseudo reg N is equivalent,
117 or zero if pseudo reg N is not equivalent to a memory slot. */
120 /* Widest width in which each pseudo reg is referred to (via subreg). */
121 static int *reg_max_ref_width;
123 /* Element N is the list of insns that initialized reg N from its equivalent
124 constant or memory slot. */
125 static rtx *reg_equiv_init;
127 /* Vector to remember old contents of reg_renumber before spilling. */
128 static short *reg_old_renumber;
130 /* During reload_as_needed, element N contains the last pseudo regno reloaded
131 into hard register N. If that pseudo reg occupied more than one register,
132 reg_reloaded_contents points to that pseudo for each spill register in
133 use; all of these must remain set for an inheritance to occur. */
134 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
136 /* During reload_as_needed, element N contains the insn for which
137 hard register N was last used. Its contents are significant only
138 when reg_reloaded_valid is set for this register. */
139 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
141 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
142 static HARD_REG_SET reg_reloaded_valid;
143 /* Indicate if the register was dead at the end of the reload.
144 This is only valid if reg_reloaded_contents is set and valid. */
145 static HARD_REG_SET reg_reloaded_dead;
147 /* Number of spill-regs so far; number of valid elements of spill_regs. */
150 /* In parallel with spill_regs, contains REG rtx's for those regs.
151 Holds the last rtx used for any given reg, or 0 if it has never
152 been used for spilling yet. This rtx is reused, provided it has
154 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
156 /* In parallel with spill_regs, contains nonzero for a spill reg
157 that was stored after the last time it was used.
158 The precise value is the insn generated to do the store. */
159 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
161 /* This is the register that was stored with spill_reg_store. This is a
162 copy of reload_out / reload_out_reg when the value was stored; if
163 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
164 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
166 /* This table is the inverse mapping of spill_regs:
167 indexed by hard reg number,
168 it contains the position of that reg in spill_regs,
169 or -1 for something that is not in spill_regs.
171 ?!? This is no longer accurate. */
172 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
174 /* This reg set indicates registers that can't be used as spill registers for
175 the currently processed insn. These are the hard registers which are live
176 during the insn, but not allocated to pseudos, as well as fixed
178 static HARD_REG_SET bad_spill_regs;
180 /* These are the hard registers that can't be used as spill register for any
181 insn. This includes registers used for user variables and registers that
182 we can't eliminate. A register that appears in this set also can't be used
183 to retry register allocation. */
184 static HARD_REG_SET bad_spill_regs_global;
186 /* Describes order of use of registers for reloading
187 of spilled pseudo-registers. `n_spills' is the number of
188 elements that are actually valid; new ones are added at the end.
190 Both spill_regs and spill_reg_order are used on two occasions:
191 once during find_reload_regs, where they keep track of the spill registers
192 for a single insn, but also during reload_as_needed where they show all
193 the registers ever used by reload. For the latter case, the information
194 is calculated during finish_spills. */
195 static short spill_regs[FIRST_PSEUDO_REGISTER];
197 /* This vector of reg sets indicates, for each pseudo, which hard registers
198 may not be used for retrying global allocation because the register was
199 formerly spilled from one of them. If we allowed reallocating a pseudo to
200 a register that it was already allocated to, reload might not
202 static HARD_REG_SET *pseudo_previous_regs;
204 /* This vector of reg sets indicates, for each pseudo, which hard
205 registers may not be used for retrying global allocation because they
206 are used as spill registers during one of the insns in which the
208 static HARD_REG_SET *pseudo_forbidden_regs;
210 /* All hard regs that have been used as spill registers for any insn are
211 marked in this set. */
212 static HARD_REG_SET used_spill_regs;
214 /* Index of last register assigned as a spill register. We allocate in
215 a round-robin fashion. */
216 static int last_spill_reg;
218 /* Describes order of preference for putting regs into spill_regs.
219 Contains the numbers of all the hard regs, in order most preferred first.
220 This order is different for each function.
221 It is set up by order_regs_for_reload.
222 Empty elements at the end contain -1. */
223 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
225 /* Nonzero if indirect addressing is supported on the machine; this means
226 that spilling (REG n) does not require reloading it into a register in
227 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
228 value indicates the level of indirect addressing supported, e.g., two
229 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
231 static char spill_indirect_levels;
233 /* Nonzero if indirect addressing is supported when the innermost MEM is
234 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
235 which these are valid is the same as spill_indirect_levels, above. */
236 char indirect_symref_ok;
238 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
239 char double_reg_address_ok;
241 /* Record the stack slot for each spilled hard register. */
242 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
244 /* Width allocated so far for that stack slot. */
245 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
247 /* Record which pseudos needed to be spilled. */
248 static regset spilled_pseudos;
250 /* First uid used by insns created by reload in this function.
251 Used in find_equiv_reg. */
252 int reload_first_uid;
254 /* Flag set by local-alloc or global-alloc if anything is live in
255 a call-clobbered reg across calls. */
256 int caller_save_needed;
258 /* Set to 1 while reload_as_needed is operating.
259 Required by some machines to handle any generated moves differently. */
260 int reload_in_progress = 0;
262 /* These arrays record the insn_code of insns that may be needed to
263 perform input and output reloads of special objects. They provide a
264 place to pass a scratch register. */
265 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
266 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
268 /* This obstack is used for allocation of rtl during register elimination.
269 The allocated storage can be freed once find_reloads has processed the
271 struct obstack reload_obstack;
273 /* Points to the beginning of the reload_obstack. All insn_chain structures
274 are allocated first. */
275 char *reload_startobj;
277 /* The point after all insn_chain structures. Used to quickly deallocate
278 memory used while processing one insn. */
279 char *reload_firstobj;
281 #define obstack_chunk_alloc xmalloc
282 #define obstack_chunk_free free
284 /* List of insn_chain instructions, one for every insn that reload needs to
286 struct insn_chain *reload_insn_chain;
289 extern tree current_function_decl;
291 extern union tree_node *current_function_decl;
294 /* List of all insns needing reloads. */
295 static struct insn_chain *insns_need_reload;
297 /* This structure is used to record information about register eliminations.
298 Each array entry describes one possible way of eliminating a register
299 in favor of another. If there is more than one way of eliminating a
300 particular register, the most preferred should be specified first. */
304 int from; /* Register number to be eliminated. */
305 int to; /* Register number used as replacement. */
306 int initial_offset; /* Initial difference between values. */
307 int can_eliminate; /* Non-zero if this elimination can be done. */
308 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
309 insns made by reload. */
310 int offset; /* Current offset between the two regs. */
311 int previous_offset; /* Offset at end of previous insn. */
312 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
313 rtx from_rtx; /* REG rtx for the register to be eliminated.
314 We cannot simply compare the number since
315 we might then spuriously replace a hard
316 register corresponding to a pseudo
317 assigned to the reg to be eliminated. */
318 rtx to_rtx; /* REG rtx for the replacement. */
321 static struct elim_table * reg_eliminate = 0;
323 /* This is an intermediate structure to initialize the table. It has
324 exactly the members provided by ELIMINABLE_REGS. */
325 static struct elim_table_1
329 } reg_eliminate_1[] =
331 /* If a set of eliminable registers was specified, define the table from it.
332 Otherwise, default to the normal case of the frame pointer being
333 replaced by the stack pointer. */
335 #ifdef ELIMINABLE_REGS
338 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
341 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate_1/sizeof reg_eliminate_1[0])
343 /* Record the number of pending eliminations that have an offset not equal
344 to their initial offset. If non-zero, we use a new copy of each
345 replacement result in any insns encountered. */
346 int num_not_at_initial_offset;
348 /* Count the number of registers that we may be able to eliminate. */
349 static int num_eliminable;
350 /* And the number of registers that are equivalent to a constant that
351 can be eliminated to frame_pointer / arg_pointer + constant. */
352 static int num_eliminable_invariants;
354 /* For each label, we record the offset of each elimination. If we reach
355 a label by more than one path and an offset differs, we cannot do the
356 elimination. This information is indexed by the number of the label.
357 The first table is an array of flags that records whether we have yet
358 encountered a label and the second table is an array of arrays, one
359 entry in the latter array for each elimination. */
361 static char *offsets_known_at;
362 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
364 /* Number of labels in the current function. */
366 static int num_labels;
368 struct hard_reg_n_uses
374 static void maybe_fix_stack_asms PROTO((void));
375 static void calculate_needs_all_insns PROTO((int));
376 static void calculate_needs PROTO((struct insn_chain *));
377 static void find_reload_regs PROTO((struct insn_chain *chain,
379 static void find_tworeg_group PROTO((struct insn_chain *, int,
381 static void find_group PROTO((struct insn_chain *, int,
383 static int possible_group_p PROTO((struct insn_chain *, int));
384 static void count_possible_groups PROTO((struct insn_chain *, int));
385 static int modes_equiv_for_class_p PROTO((enum machine_mode,
388 static void delete_caller_save_insns PROTO((void));
390 static void spill_failure PROTO((rtx));
391 static void new_spill_reg PROTO((struct insn_chain *, int, int,
393 static void maybe_mark_pseudo_spilled PROTO((int));
394 static void delete_dead_insn PROTO((rtx));
395 static void alter_reg PROTO((int, int));
396 static void set_label_offsets PROTO((rtx, rtx, int));
397 static void check_eliminable_occurrences PROTO((rtx));
398 static void elimination_effects PROTO((rtx, enum machine_mode));
399 static int eliminate_regs_in_insn PROTO((rtx, int));
400 static void update_eliminable_offsets PROTO((void));
401 static void mark_not_eliminable PROTO((rtx, rtx));
402 static void set_initial_elim_offsets PROTO((void));
403 static void verify_initial_elim_offsets PROTO((void));
404 static void set_initial_label_offsets PROTO((void));
405 static void set_offsets_for_label PROTO((rtx));
406 static void init_elim_table PROTO((void));
407 static void update_eliminables PROTO((HARD_REG_SET *));
408 static void spill_hard_reg PROTO((int, FILE *, int));
409 static int finish_spills PROTO((int, FILE *));
410 static void ior_hard_reg_set PROTO((HARD_REG_SET *, HARD_REG_SET *));
411 static void scan_paradoxical_subregs PROTO((rtx));
412 static int hard_reg_use_compare PROTO((const PTR, const PTR));
413 static void count_pseudo PROTO((struct hard_reg_n_uses *, int));
414 static void order_regs_for_reload PROTO((struct insn_chain *));
415 static void reload_as_needed PROTO((int));
416 static void forget_old_reloads_1 PROTO((rtx, rtx));
417 static int reload_reg_class_lower PROTO((const PTR, const PTR));
418 static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
420 static void clear_reload_reg_in_use PROTO((int, int, enum reload_type,
422 static int reload_reg_free_p PROTO((int, int, enum reload_type));
423 static int reload_reg_free_for_value_p PROTO((int, int, enum reload_type, rtx, rtx, int, int));
424 static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
425 static int allocate_reload_reg PROTO((struct insn_chain *, int, int,
427 static void choose_reload_regs_init PROTO((struct insn_chain *, rtx *));
428 static void choose_reload_regs PROTO((struct insn_chain *));
429 static void merge_assigned_reloads PROTO((rtx));
430 static void emit_reload_insns PROTO((struct insn_chain *));
431 static void delete_output_reload PROTO((rtx, int, int));
432 static void delete_address_reloads PROTO((rtx, rtx));
433 static void delete_address_reloads_1 PROTO((rtx, rtx, rtx));
434 static rtx inc_for_reload PROTO((rtx, rtx, rtx, int));
435 static int constraint_accepts_reg_p PROTO((const char *, rtx));
436 static void reload_cse_regs_1 PROTO((rtx));
437 static void reload_cse_invalidate_regno PROTO((int, enum machine_mode, int));
438 static int reload_cse_mem_conflict_p PROTO((rtx, rtx));
439 static void reload_cse_invalidate_mem PROTO((rtx));
440 static void reload_cse_invalidate_rtx PROTO((rtx, rtx));
441 static int reload_cse_regno_equal_p PROTO((int, rtx, enum machine_mode));
442 static int reload_cse_noop_set_p PROTO((rtx, rtx));
443 static int reload_cse_simplify_set PROTO((rtx, rtx));
444 static int reload_cse_simplify_operands PROTO((rtx));
445 static void reload_cse_check_clobber PROTO((rtx, rtx));
446 static void reload_cse_record_set PROTO((rtx, rtx));
447 static void reload_combine PROTO((void));
448 static void reload_combine_note_use PROTO((rtx *, rtx));
449 static void reload_combine_note_store PROTO((rtx, rtx));
450 static void reload_cse_move2add PROTO((rtx));
451 static void move2add_note_store PROTO((rtx, rtx));
453 static void add_auto_inc_notes PROTO((rtx, rtx));
455 static rtx gen_mode_int PROTO((enum machine_mode,
457 extern void dump_needs PROTO((struct insn_chain *, FILE *));
459 /* Initialize the reload pass once per compilation. */
466 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
467 Set spill_indirect_levels to the number of levels such addressing is
468 permitted, zero if it is not permitted at all. */
471 = gen_rtx_MEM (Pmode,
474 LAST_VIRTUAL_REGISTER + 1),
476 spill_indirect_levels = 0;
478 while (memory_address_p (QImode, tem))
480 spill_indirect_levels++;
481 tem = gen_rtx_MEM (Pmode, tem);
484 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
486 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
487 indirect_symref_ok = memory_address_p (QImode, tem);
489 /* See if reg+reg is a valid (and offsettable) address. */
491 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
493 tem = gen_rtx_PLUS (Pmode,
494 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
495 gen_rtx_REG (Pmode, i));
497 /* This way, we make sure that reg+reg is an offsettable address. */
498 tem = plus_constant (tem, 4);
500 if (memory_address_p (QImode, tem))
502 double_reg_address_ok = 1;
507 /* Initialize obstack for our rtl allocation. */
508 gcc_obstack_init (&reload_obstack);
509 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
512 /* List of insn chains that are currently unused. */
513 static struct insn_chain *unused_insn_chains = 0;
515 /* Allocate an empty insn_chain structure. */
519 struct insn_chain *c;
521 if (unused_insn_chains == 0)
523 c = (struct insn_chain *)
524 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
525 c->live_before = OBSTACK_ALLOC_REG_SET (&reload_obstack);
526 c->live_after = OBSTACK_ALLOC_REG_SET (&reload_obstack);
530 c = unused_insn_chains;
531 unused_insn_chains = c->next;
533 c->is_caller_save_insn = 0;
534 c->need_operand_change = 0;
540 /* Small utility function to set all regs in hard reg set TO which are
541 allocated to pseudos in regset FROM. */
543 compute_use_by_pseudos (to, from)
548 EXECUTE_IF_SET_IN_REG_SET
549 (from, FIRST_PSEUDO_REGISTER, regno,
551 int r = reg_renumber[regno];
555 /* reload_combine uses the information from
556 BASIC_BLOCK->global_live_at_start, which might still
557 contain registers that have not actually been allocated
558 since they have an equivalence. */
559 if (! reload_completed)
564 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
566 SET_HARD_REG_BIT (*to, r + nregs);
571 /* Global variables used by reload and its subroutines. */
573 /* Set during calculate_needs if an insn needs register elimination. */
574 static int something_needs_elimination;
575 /* Set during calculate_needs if an insn needs an operand changed. */
576 int something_needs_operands_changed;
578 /* Nonzero means we couldn't get enough spill regs. */
581 /* Main entry point for the reload pass.
583 FIRST is the first insn of the function being compiled.
585 GLOBAL nonzero means we were called from global_alloc
586 and should attempt to reallocate any pseudoregs that we
587 displace from hard regs we will use for reloads.
588 If GLOBAL is zero, we do not have enough information to do that,
589 so any pseudo reg that is spilled must go to the stack.
591 DUMPFILE is the global-reg debugging dump file stream, or 0.
592 If it is nonzero, messages are written to it to describe
593 which registers are seized as reload regs, which pseudo regs
594 are spilled from them, and where the pseudo regs are reallocated to.
596 Return value is nonzero if reload failed
597 and we must not do any more for this function. */
600 reload (first, global, dumpfile)
607 register struct elim_table *ep;
609 /* The two pointers used to track the true location of the memory used
610 for label offsets. */
611 char *real_known_ptr = NULL_PTR;
612 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
614 /* Make sure even insns with volatile mem refs are recognizable. */
619 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
621 /* Make sure that the last insn in the chain
622 is not something that needs reloading. */
623 emit_note (NULL_PTR, NOTE_INSN_DELETED);
625 /* Enable find_equiv_reg to distinguish insns made by reload. */
626 reload_first_uid = get_max_uid ();
628 #ifdef SECONDARY_MEMORY_NEEDED
629 /* Initialize the secondary memory table. */
630 clear_secondary_mem ();
633 /* We don't have a stack slot for any spill reg yet. */
634 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
635 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
637 /* Initialize the save area information for caller-save, in case some
641 /* Compute which hard registers are now in use
642 as homes for pseudo registers.
643 This is done here rather than (eg) in global_alloc
644 because this point is reached even if not optimizing. */
645 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
648 /* A function that receives a nonlocal goto must save all call-saved
650 if (current_function_has_nonlocal_label)
651 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
653 if (! call_used_regs[i] && ! fixed_regs[i])
654 regs_ever_live[i] = 1;
657 /* Find all the pseudo registers that didn't get hard regs
658 but do have known equivalent constants or memory slots.
659 These include parameters (known equivalent to parameter slots)
660 and cse'd or loop-moved constant memory addresses.
662 Record constant equivalents in reg_equiv_constant
663 so they will be substituted by find_reloads.
664 Record memory equivalents in reg_mem_equiv so they can
665 be substituted eventually by altering the REG-rtx's. */
667 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
668 reg_equiv_memory_loc = (rtx *) xcalloc (max_regno, sizeof (rtx));
669 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
670 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
671 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
672 reg_max_ref_width = (int *) xcalloc (max_regno, sizeof (int));
673 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
674 bcopy ((PTR) reg_renumber, (PTR) reg_old_renumber, max_regno * sizeof (short));
675 pseudo_forbidden_regs
676 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
678 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
680 CLEAR_HARD_REG_SET (bad_spill_regs_global);
682 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
683 Also find all paradoxical subregs and find largest such for each pseudo.
684 On machines with small register classes, record hard registers that
685 are used for user variables. These can never be used for spills.
686 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
687 caller-saved registers must be marked live. */
689 num_eliminable_invariants = 0;
690 for (insn = first; insn; insn = NEXT_INSN (insn))
692 rtx set = single_set (insn);
694 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
695 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
696 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
697 if (! call_used_regs[i])
698 regs_ever_live[i] = 1;
700 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
702 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
704 #ifdef LEGITIMATE_PIC_OPERAND_P
705 && (! function_invariant_p (XEXP (note, 0))
707 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
711 rtx x = XEXP (note, 0);
712 i = REGNO (SET_DEST (set));
713 if (i > LAST_VIRTUAL_REGISTER)
715 if (GET_CODE (x) == MEM)
717 /* If the operand is a PLUS, the MEM may be shared,
718 so make sure we have an unshared copy here. */
719 if (GET_CODE (XEXP (x, 0)) == PLUS)
722 reg_equiv_memory_loc[i] = x;
724 else if (function_invariant_p (x))
726 if (GET_CODE (x) == PLUS)
728 /* This is PLUS of frame pointer and a constant,
729 and might be shared. Unshare it. */
730 reg_equiv_constant[i] = copy_rtx (x);
731 num_eliminable_invariants++;
733 else if (x == frame_pointer_rtx
734 || x == arg_pointer_rtx)
736 reg_equiv_constant[i] = x;
737 num_eliminable_invariants++;
739 else if (LEGITIMATE_CONSTANT_P (x))
740 reg_equiv_constant[i] = x;
742 reg_equiv_memory_loc[i]
743 = force_const_mem (GET_MODE (SET_DEST (set)), x);
748 /* If this register is being made equivalent to a MEM
749 and the MEM is not SET_SRC, the equivalencing insn
750 is one with the MEM as a SET_DEST and it occurs later.
751 So don't mark this insn now. */
752 if (GET_CODE (x) != MEM
753 || rtx_equal_p (SET_SRC (set), x))
755 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
760 /* If this insn is setting a MEM from a register equivalent to it,
761 this is the equivalencing insn. */
762 else if (set && GET_CODE (SET_DEST (set)) == MEM
763 && GET_CODE (SET_SRC (set)) == REG
764 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
765 && rtx_equal_p (SET_DEST (set),
766 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
767 reg_equiv_init[REGNO (SET_SRC (set))]
768 = gen_rtx_INSN_LIST (VOIDmode, insn,
769 reg_equiv_init[REGNO (SET_SRC (set))]);
771 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
772 scan_paradoxical_subregs (PATTERN (insn));
777 num_labels = max_label_num () - get_first_label_num ();
779 /* Allocate the tables used to store offset information at labels. */
780 /* We used to use alloca here, but the size of what it would try to
781 allocate would occasionally cause it to exceed the stack limit and
782 cause a core dump. */
783 real_known_ptr = xmalloc (num_labels);
785 = (int (*)[NUM_ELIMINABLE_REGS])
786 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
788 offsets_known_at = real_known_ptr - get_first_label_num ();
790 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
792 /* Alter each pseudo-reg rtx to contain its hard reg number.
793 Assign stack slots to the pseudos that lack hard regs or equivalents.
794 Do not touch virtual registers. */
796 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
799 /* If we have some registers we think can be eliminated, scan all insns to
800 see if there is an insn that sets one of these registers to something
801 other than itself plus a constant. If so, the register cannot be
802 eliminated. Doing this scan here eliminates an extra pass through the
803 main reload loop in the most common case where register elimination
805 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
806 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
807 || GET_CODE (insn) == CALL_INSN)
808 note_stores (PATTERN (insn), mark_not_eliminable);
810 maybe_fix_stack_asms ();
812 insns_need_reload = 0;
813 something_needs_elimination = 0;
815 /* Initialize to -1, which means take the first spill register. */
818 spilled_pseudos = ALLOCA_REG_SET ();
820 /* Spill any hard regs that we know we can't eliminate. */
821 CLEAR_HARD_REG_SET (used_spill_regs);
822 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
823 if (! ep->can_eliminate)
824 spill_hard_reg (ep->from, dumpfile, 1);
826 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
827 if (frame_pointer_needed)
828 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, dumpfile, 1);
830 finish_spills (global, dumpfile);
832 /* From now on, we may need to generate moves differently. We may also
833 allow modifications of insns which cause them to not be recognized.
834 Any such modifications will be cleaned up during reload itself. */
835 reload_in_progress = 1;
837 /* This loop scans the entire function each go-round
838 and repeats until one repetition spills no additional hard regs. */
841 int something_changed;
843 struct insn_chain *chain;
845 HOST_WIDE_INT starting_frame_size;
847 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done
848 here because the stack size may be a part of the offset computation
849 for register elimination, and there might have been new stack slots
850 created in the last iteration of this loop. */
851 assign_stack_local (BLKmode, 0, 0);
853 starting_frame_size = get_frame_size ();
855 set_initial_elim_offsets ();
856 set_initial_label_offsets ();
858 /* For each pseudo register that has an equivalent location defined,
859 try to eliminate any eliminable registers (such as the frame pointer)
860 assuming initial offsets for the replacement register, which
863 If the resulting location is directly addressable, substitute
864 the MEM we just got directly for the old REG.
866 If it is not addressable but is a constant or the sum of a hard reg
867 and constant, it is probably not addressable because the constant is
868 out of range, in that case record the address; we will generate
869 hairy code to compute the address in a register each time it is
870 needed. Similarly if it is a hard register, but one that is not
871 valid as an address register.
873 If the location is not addressable, but does not have one of the
874 above forms, assign a stack slot. We have to do this to avoid the
875 potential of producing lots of reloads if, e.g., a location involves
876 a pseudo that didn't get a hard register and has an equivalent memory
877 location that also involves a pseudo that didn't get a hard register.
879 Perhaps at some point we will improve reload_when_needed handling
880 so this problem goes away. But that's very hairy. */
882 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
883 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
885 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
887 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
889 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
890 else if (CONSTANT_P (XEXP (x, 0))
891 || (GET_CODE (XEXP (x, 0)) == REG
892 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
893 || (GET_CODE (XEXP (x, 0)) == PLUS
894 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
895 && (REGNO (XEXP (XEXP (x, 0), 0))
896 < FIRST_PSEUDO_REGISTER)
897 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
898 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
901 /* Make a new stack slot. Then indicate that something
902 changed so we go back and recompute offsets for
903 eliminable registers because the allocation of memory
904 below might change some offset. reg_equiv_{mem,address}
905 will be set up for this pseudo on the next pass around
907 reg_equiv_memory_loc[i] = 0;
908 reg_equiv_init[i] = 0;
913 if (caller_save_needed)
916 /* If we allocated another stack slot, redo elimination bookkeeping. */
917 if (starting_frame_size != get_frame_size ())
920 if (caller_save_needed)
922 save_call_clobbered_regs ();
923 /* That might have allocated new insn_chain structures. */
924 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
927 calculate_needs_all_insns (global);
929 CLEAR_REG_SET (spilled_pseudos);
932 something_changed = 0;
934 /* If we allocated any new memory locations, make another pass
935 since it might have changed elimination offsets. */
936 if (starting_frame_size != get_frame_size ())
937 something_changed = 1;
940 HARD_REG_SET to_spill;
941 CLEAR_HARD_REG_SET (to_spill);
942 update_eliminables (&to_spill);
943 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
944 if (TEST_HARD_REG_BIT (to_spill, i))
946 spill_hard_reg (i, dumpfile, 1);
949 /* Regardless of the state of spills, if we previously had
950 a register that we thought we could eliminate, but no can
951 not eliminate, we must run another pass.
953 Consider pseudos which have an entry in reg_equiv_* which
954 reference an eliminable register. We must make another pass
955 to update reg_equiv_* so that we do not substitute in the
956 old value from when we thought the elimination could be
958 something_changed = 1;
962 CLEAR_HARD_REG_SET (used_spill_regs);
963 /* Try to satisfy the needs for each insn. */
964 for (chain = insns_need_reload; chain != 0;
965 chain = chain->next_need_reload)
966 find_reload_regs (chain, dumpfile);
971 if (insns_need_reload != 0 || did_spill)
972 something_changed |= finish_spills (global, dumpfile);
974 if (! something_changed)
977 if (caller_save_needed)
978 delete_caller_save_insns ();
981 /* If global-alloc was run, notify it of any register eliminations we have
984 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
985 if (ep->can_eliminate)
986 mark_elimination (ep->from, ep->to);
988 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
989 If that insn didn't set the register (i.e., it copied the register to
990 memory), just delete that insn instead of the equivalencing insn plus
991 anything now dead. If we call delete_dead_insn on that insn, we may
992 delete the insn that actually sets the register if the register dies
993 there and that is incorrect. */
995 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
997 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1000 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1002 rtx equiv_insn = XEXP (list, 0);
1003 if (GET_CODE (equiv_insn) == NOTE)
1005 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1006 delete_dead_insn (equiv_insn);
1009 PUT_CODE (equiv_insn, NOTE);
1010 NOTE_SOURCE_FILE (equiv_insn) = 0;
1011 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1017 /* Use the reload registers where necessary
1018 by generating move instructions to move the must-be-register
1019 values into or out of the reload registers. */
1021 if (insns_need_reload != 0 || something_needs_elimination
1022 || something_needs_operands_changed)
1024 int old_frame_size = get_frame_size ();
1026 reload_as_needed (global);
1028 if (old_frame_size != get_frame_size ())
1032 verify_initial_elim_offsets ();
1035 /* If we were able to eliminate the frame pointer, show that it is no
1036 longer live at the start of any basic block. If it ls live by
1037 virtue of being in a pseudo, that pseudo will be marked live
1038 and hence the frame pointer will be known to be live via that
1041 if (! frame_pointer_needed)
1042 for (i = 0; i < n_basic_blocks; i++)
1043 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1044 HARD_FRAME_POINTER_REGNUM);
1046 /* Come here (with failure set nonzero) if we can't get enough spill regs
1047 and we decide not to abort about it. */
1050 reload_in_progress = 0;
1052 /* Now eliminate all pseudo regs by modifying them into
1053 their equivalent memory references.
1054 The REG-rtx's for the pseudos are modified in place,
1055 so all insns that used to refer to them now refer to memory.
1057 For a reg that has a reg_equiv_address, all those insns
1058 were changed by reloading so that no insns refer to it any longer;
1059 but the DECL_RTL of a variable decl may refer to it,
1060 and if so this causes the debugging info to mention the variable. */
1062 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1067 int is_readonly = 0;
1069 if (reg_equiv_memory_loc[i])
1071 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1072 is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]);
1073 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1076 if (reg_equiv_mem[i])
1077 addr = XEXP (reg_equiv_mem[i], 0);
1079 if (reg_equiv_address[i])
1080 addr = reg_equiv_address[i];
1084 if (reg_renumber[i] < 0)
1086 rtx reg = regno_reg_rtx[i];
1087 PUT_CODE (reg, MEM);
1088 XEXP (reg, 0) = addr;
1089 REG_USERVAR_P (reg) = 0;
1090 RTX_UNCHANGING_P (reg) = is_readonly;
1091 MEM_IN_STRUCT_P (reg) = in_struct;
1092 MEM_SCALAR_P (reg) = is_scalar;
1093 /* We have no alias information about this newly created
1095 MEM_ALIAS_SET (reg) = 0;
1097 else if (reg_equiv_mem[i])
1098 XEXP (reg_equiv_mem[i], 0) = addr;
1102 /* We must set reload_completed now since the cleanup_subreg_operands call
1103 below will re-recognize each insn and reload may have generated insns
1104 which are only valid during and after reload. */
1105 reload_completed = 1;
1107 /* Make a pass over all the insns and delete all USEs which we
1108 inserted only to tag a REG_EQUAL note on them. Remove all
1109 REG_DEAD and REG_UNUSED notes. Delete all CLOBBER insns and
1110 simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1111 REG_LIBCALL notes since they are no longer useful or accurate.
1112 Strip and regenerate REG_INC notes that may have been moved
1115 for (insn = first; insn; insn = NEXT_INSN (insn))
1116 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1120 if ((GET_CODE (PATTERN (insn)) == USE
1121 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1122 || GET_CODE (PATTERN (insn)) == CLOBBER)
1124 PUT_CODE (insn, NOTE);
1125 NOTE_SOURCE_FILE (insn) = 0;
1126 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1130 pnote = ®_NOTES (insn);
1133 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1134 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1135 || REG_NOTE_KIND (*pnote) == REG_INC
1136 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1137 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1138 *pnote = XEXP (*pnote, 1);
1140 pnote = &XEXP (*pnote, 1);
1144 add_auto_inc_notes (insn, PATTERN (insn));
1147 /* And simplify (subreg (reg)) if it appears as an operand. */
1148 cleanup_subreg_operands (insn);
1151 /* If we are doing stack checking, give a warning if this function's
1152 frame size is larger than we expect. */
1153 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1155 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1156 static int verbose_warned = 0;
1158 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1159 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1160 size += UNITS_PER_WORD;
1162 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1164 warning ("frame size too large for reliable stack checking");
1165 if (! verbose_warned)
1167 warning ("try reducing the number of local variables");
1173 /* Indicate that we no longer have known memory locations or constants. */
1174 if (reg_equiv_constant)
1175 free (reg_equiv_constant);
1176 reg_equiv_constant = 0;
1177 if (reg_equiv_memory_loc)
1178 free (reg_equiv_memory_loc);
1179 reg_equiv_memory_loc = 0;
1182 free (real_known_ptr);
1186 free (reg_equiv_mem);
1187 free (reg_equiv_init);
1188 free (reg_equiv_address);
1189 free (reg_max_ref_width);
1190 free (reg_old_renumber);
1191 free (pseudo_previous_regs);
1192 free (pseudo_forbidden_regs);
1194 FREE_REG_SET (spilled_pseudos);
1196 CLEAR_HARD_REG_SET (used_spill_regs);
1197 for (i = 0; i < n_spills; i++)
1198 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1200 /* Free all the insn_chain structures at once. */
1201 obstack_free (&reload_obstack, reload_startobj);
1202 unused_insn_chains = 0;
1207 /* Yet another special case. Unfortunately, reg-stack forces people to
1208 write incorrect clobbers in asm statements. These clobbers must not
1209 cause the register to appear in bad_spill_regs, otherwise we'll call
1210 fatal_insn later. We clear the corresponding regnos in the live
1211 register sets to avoid this.
1212 The whole thing is rather sick, I'm afraid. */
1214 maybe_fix_stack_asms ()
1217 const char *constraints[MAX_RECOG_OPERANDS];
1218 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1219 struct insn_chain *chain;
1221 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1224 HARD_REG_SET clobbered, allowed;
1227 if (GET_RTX_CLASS (GET_CODE (chain->insn)) != 'i'
1228 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1230 pat = PATTERN (chain->insn);
1231 if (GET_CODE (pat) != PARALLEL)
1234 CLEAR_HARD_REG_SET (clobbered);
1235 CLEAR_HARD_REG_SET (allowed);
1237 /* First, make a mask of all stack regs that are clobbered. */
1238 for (i = 0; i < XVECLEN (pat, 0); i++)
1240 rtx t = XVECEXP (pat, 0, i);
1241 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1242 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1245 /* Get the operand values and constraints out of the insn. */
1246 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1247 constraints, operand_mode);
1249 /* For every operand, see what registers are allowed. */
1250 for (i = 0; i < noperands; i++)
1252 const char *p = constraints[i];
1253 /* For every alternative, we compute the class of registers allowed
1254 for reloading in CLS, and merge its contents into the reg set
1256 int cls = (int) NO_REGS;
1262 if (c == '\0' || c == ',' || c == '#')
1264 /* End of one alternative - mark the regs in the current
1265 class, and reset the class. */
1266 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1271 } while (c != '\0' && c != ',');
1279 case '=': case '+': case '*': case '%': case '?': case '!':
1280 case '0': case '1': case '2': case '3': case '4': case 'm':
1281 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1282 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1283 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1285 #ifdef EXTRA_CONSTRAINT
1286 case 'Q': case 'R': case 'S': case 'T': case 'U':
1291 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1296 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1300 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1305 /* Those of the registers which are clobbered, but allowed by the
1306 constraints, must be usable as reload registers. So clear them
1307 out of the life information. */
1308 AND_HARD_REG_SET (allowed, clobbered);
1309 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1310 if (TEST_HARD_REG_BIT (allowed, i))
1312 CLEAR_REGNO_REG_SET (chain->live_before, i);
1313 CLEAR_REGNO_REG_SET (chain->live_after, i);
1321 /* Walk the chain of insns, and determine for each whether it needs reloads
1322 and/or eliminations. Build the corresponding insns_need_reload list, and
1323 set something_needs_elimination as appropriate. */
1325 calculate_needs_all_insns (global)
1328 struct insn_chain **pprev_reload = &insns_need_reload;
1329 struct insn_chain *chain;
1331 something_needs_elimination = 0;
1333 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1335 rtx insn = chain->insn;
1337 /* Clear out the shortcuts, in case they were set last time through. */
1338 chain->need_elim = 0;
1339 chain->need_reload = 0;
1340 chain->need_operand_change = 0;
1342 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1343 include REG_LABEL), we need to see what effects this has on the
1344 known offsets at labels. */
1346 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1347 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1348 && REG_NOTES (insn) != 0))
1349 set_label_offsets (insn, insn, 0);
1351 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1353 rtx old_body = PATTERN (insn);
1354 int old_code = INSN_CODE (insn);
1355 rtx old_notes = REG_NOTES (insn);
1356 int did_elimination = 0;
1357 int operands_changed = 0;
1358 rtx set = single_set (insn);
1360 /* Skip insns that only set an equivalence. */
1361 if (set && GET_CODE (SET_DEST (set)) == REG
1362 && reg_renumber[REGNO (SET_DEST (set))] < 0
1363 && reg_equiv_constant[REGNO (SET_DEST (set))])
1366 /* If needed, eliminate any eliminable registers. */
1367 if (num_eliminable || num_eliminable_invariants)
1368 did_elimination = eliminate_regs_in_insn (insn, 0);
1370 /* Analyze the instruction. */
1371 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1372 global, spill_reg_order);
1374 /* If a no-op set needs more than one reload, this is likely
1375 to be something that needs input address reloads. We
1376 can't get rid of this cleanly later, and it is of no use
1377 anyway, so discard it now.
1378 We only do this when expensive_optimizations is enabled,
1379 since this complements reload inheritance / output
1380 reload deletion, and it can make debugging harder. */
1381 if (flag_expensive_optimizations && n_reloads > 1)
1383 rtx set = single_set (insn);
1385 && SET_SRC (set) == SET_DEST (set)
1386 && GET_CODE (SET_SRC (set)) == REG
1387 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1389 PUT_CODE (insn, NOTE);
1390 NOTE_SOURCE_FILE (insn) = 0;
1391 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1396 update_eliminable_offsets ();
1398 /* Remember for later shortcuts which insns had any reloads or
1399 register eliminations. */
1400 chain->need_elim = did_elimination;
1401 chain->need_reload = n_reloads > 0;
1402 chain->need_operand_change = operands_changed;
1404 /* Discard any register replacements done. */
1405 if (did_elimination)
1407 obstack_free (&reload_obstack, reload_firstobj);
1408 PATTERN (insn) = old_body;
1409 INSN_CODE (insn) = old_code;
1410 REG_NOTES (insn) = old_notes;
1411 something_needs_elimination = 1;
1414 something_needs_operands_changed |= operands_changed;
1418 *pprev_reload = chain;
1419 pprev_reload = &chain->next_need_reload;
1421 calculate_needs (chain);
1428 /* Compute the most additional registers needed by one instruction,
1429 given by CHAIN. Collect information separately for each class of regs.
1431 To compute the number of reload registers of each class needed for an
1432 insn, we must simulate what choose_reload_regs can do. We do this by
1433 splitting an insn into an "input" and an "output" part. RELOAD_OTHER
1434 reloads are used in both. The input part uses those reloads,
1435 RELOAD_FOR_INPUT reloads, which must be live over the entire input section
1436 of reloads, and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
1437 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the inputs.
1439 The registers needed for output are RELOAD_OTHER and RELOAD_FOR_OUTPUT,
1440 which are live for the entire output portion, and the maximum of all the
1441 RELOAD_FOR_OUTPUT_ADDRESS reloads for each operand.
1443 The total number of registers needed is the maximum of the
1444 inputs and outputs. */
1447 calculate_needs (chain)
1448 struct insn_chain *chain;
1452 /* Each `struct needs' corresponds to one RELOAD_... type. */
1456 struct needs output;
1458 struct needs other_addr;
1459 struct needs op_addr;
1460 struct needs op_addr_reload;
1461 struct needs in_addr[MAX_RECOG_OPERANDS];
1462 struct needs in_addr_addr[MAX_RECOG_OPERANDS];
1463 struct needs out_addr[MAX_RECOG_OPERANDS];
1464 struct needs out_addr_addr[MAX_RECOG_OPERANDS];
1467 bzero ((char *) chain->group_size, sizeof chain->group_size);
1468 for (i = 0; i < N_REG_CLASSES; i++)
1469 chain->group_mode[i] = VOIDmode;
1470 bzero ((char *) &insn_needs, sizeof insn_needs);
1472 /* Count each reload once in every class
1473 containing the reload's own class. */
1475 for (i = 0; i < n_reloads; i++)
1477 register enum reg_class *p;
1478 enum reg_class class = rld[i].class;
1480 enum machine_mode mode;
1481 struct needs *this_needs;
1483 /* Don't count the dummy reloads, for which one of the
1484 regs mentioned in the insn can be used for reloading.
1485 Don't count optional reloads.
1486 Don't count reloads that got combined with others. */
1487 if (rld[i].reg_rtx != 0
1488 || rld[i].optional != 0
1489 || (rld[i].out == 0 && rld[i].in == 0
1490 && ! rld[i].secondary_p))
1494 size = rld[i].nregs;
1496 /* Decide which time-of-use to count this reload for. */
1497 switch (rld[i].when_needed)
1500 this_needs = &insn_needs.other;
1502 case RELOAD_FOR_INPUT:
1503 this_needs = &insn_needs.input;
1505 case RELOAD_FOR_OUTPUT:
1506 this_needs = &insn_needs.output;
1508 case RELOAD_FOR_INSN:
1509 this_needs = &insn_needs.insn;
1511 case RELOAD_FOR_OTHER_ADDRESS:
1512 this_needs = &insn_needs.other_addr;
1514 case RELOAD_FOR_INPUT_ADDRESS:
1515 this_needs = &insn_needs.in_addr[rld[i].opnum];
1517 case RELOAD_FOR_INPADDR_ADDRESS:
1518 this_needs = &insn_needs.in_addr_addr[rld[i].opnum];
1520 case RELOAD_FOR_OUTPUT_ADDRESS:
1521 this_needs = &insn_needs.out_addr[rld[i].opnum];
1523 case RELOAD_FOR_OUTADDR_ADDRESS:
1524 this_needs = &insn_needs.out_addr_addr[rld[i].opnum];
1526 case RELOAD_FOR_OPERAND_ADDRESS:
1527 this_needs = &insn_needs.op_addr;
1529 case RELOAD_FOR_OPADDR_ADDR:
1530 this_needs = &insn_needs.op_addr_reload;
1538 enum machine_mode other_mode, allocate_mode;
1540 /* Count number of groups needed separately from
1541 number of individual regs needed. */
1542 this_needs->groups[(int) class]++;
1543 p = reg_class_superclasses[(int) class];
1544 while (*p != LIM_REG_CLASSES)
1545 this_needs->groups[(int) *p++]++;
1547 /* Record size and mode of a group of this class. */
1548 /* If more than one size group is needed,
1549 make all groups the largest needed size. */
1550 if (chain->group_size[(int) class] < size)
1552 other_mode = chain->group_mode[(int) class];
1553 allocate_mode = mode;
1555 chain->group_size[(int) class] = size;
1556 chain->group_mode[(int) class] = mode;
1561 allocate_mode = chain->group_mode[(int) class];
1564 /* Crash if two dissimilar machine modes both need
1565 groups of consecutive regs of the same class. */
1567 if (other_mode != VOIDmode && other_mode != allocate_mode
1568 && ! modes_equiv_for_class_p (allocate_mode,
1570 fatal_insn ("Two dissimilar machine modes both need groups of consecutive regs of the same class",
1575 this_needs->regs[(unsigned char)rld[i].nongroup][(int) class] += 1;
1576 p = reg_class_superclasses[(int) class];
1577 while (*p != LIM_REG_CLASSES)
1578 this_needs->regs[(unsigned char)rld[i].nongroup][(int) *p++] += 1;
1584 /* All reloads have been counted for this insn;
1585 now merge the various times of use.
1586 This sets insn_needs, etc., to the maximum total number
1587 of registers needed at any point in this insn. */
1589 for (i = 0; i < N_REG_CLASSES; i++)
1591 int j, in_max, out_max;
1593 /* Compute normal and nongroup needs. */
1594 for (j = 0; j <= 1; j++)
1597 for (in_max = 0, out_max = 0, k = 0; k < reload_n_operands; k++)
1599 in_max = MAX (in_max,
1600 (insn_needs.in_addr[k].regs[j][i]
1601 + insn_needs.in_addr_addr[k].regs[j][i]));
1602 out_max = MAX (out_max, insn_needs.out_addr[k].regs[j][i]);
1603 out_max = MAX (out_max,
1604 insn_needs.out_addr_addr[k].regs[j][i]);
1607 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1608 and operand addresses but not things used to reload
1609 them. Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads
1610 don't conflict with things needed to reload inputs or
1613 in_max = MAX (MAX (insn_needs.op_addr.regs[j][i],
1614 insn_needs.op_addr_reload.regs[j][i]),
1617 out_max = MAX (out_max, insn_needs.insn.regs[j][i]);
1619 insn_needs.input.regs[j][i]
1620 = MAX (insn_needs.input.regs[j][i]
1621 + insn_needs.op_addr.regs[j][i]
1622 + insn_needs.insn.regs[j][i],
1623 in_max + insn_needs.input.regs[j][i]);
1625 insn_needs.output.regs[j][i] += out_max;
1626 insn_needs.other.regs[j][i]
1627 += MAX (MAX (insn_needs.input.regs[j][i],
1628 insn_needs.output.regs[j][i]),
1629 insn_needs.other_addr.regs[j][i]);
1633 /* Now compute group needs. */
1634 for (in_max = 0, out_max = 0, j = 0; j < reload_n_operands; j++)
1636 in_max = MAX (in_max, insn_needs.in_addr[j].groups[i]);
1637 in_max = MAX (in_max, insn_needs.in_addr_addr[j].groups[i]);
1638 out_max = MAX (out_max, insn_needs.out_addr[j].groups[i]);
1639 out_max = MAX (out_max, insn_needs.out_addr_addr[j].groups[i]);
1642 in_max = MAX (MAX (insn_needs.op_addr.groups[i],
1643 insn_needs.op_addr_reload.groups[i]),
1645 out_max = MAX (out_max, insn_needs.insn.groups[i]);
1647 insn_needs.input.groups[i]
1648 = MAX (insn_needs.input.groups[i]
1649 + insn_needs.op_addr.groups[i]
1650 + insn_needs.insn.groups[i],
1651 in_max + insn_needs.input.groups[i]);
1653 insn_needs.output.groups[i] += out_max;
1654 insn_needs.other.groups[i]
1655 += MAX (MAX (insn_needs.input.groups[i],
1656 insn_needs.output.groups[i]),
1657 insn_needs.other_addr.groups[i]);
1660 /* Record the needs for later. */
1661 chain->need = insn_needs.other;
1664 /* Find a group of exactly 2 registers.
1666 First try to fill out the group by spilling a single register which
1667 would allow completion of the group.
1669 Then try to create a new group from a pair of registers, neither of
1670 which are explicitly used.
1672 Then try to create a group from any pair of registers. */
1675 find_tworeg_group (chain, class, dumpfile)
1676 struct insn_chain *chain;
1681 /* First, look for a register that will complete a group. */
1682 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1686 j = potential_reload_regs[i];
1687 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1688 && ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1689 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1690 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1691 && HARD_REGNO_MODE_OK (other, chain->group_mode[class])
1692 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, other)
1693 /* We don't want one part of another group.
1694 We could get "two groups" that overlap! */
1695 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, other))
1696 || (j < FIRST_PSEUDO_REGISTER - 1
1697 && (other = j + 1, spill_reg_order[other] >= 0)
1698 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1699 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1700 && HARD_REGNO_MODE_OK (j, chain->group_mode[class])
1701 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, other)
1702 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, other))))
1704 register enum reg_class *p;
1706 /* We have found one that will complete a group,
1707 so count off one group as provided. */
1708 chain->need.groups[class]--;
1709 p = reg_class_superclasses[class];
1710 while (*p != LIM_REG_CLASSES)
1712 if (chain->group_size [(int) *p] <= chain->group_size [class])
1713 chain->need.groups[(int) *p]--;
1717 /* Indicate both these regs are part of a group. */
1718 SET_HARD_REG_BIT (chain->counted_for_groups, j);
1719 SET_HARD_REG_BIT (chain->counted_for_groups, other);
1723 /* We can't complete a group, so start one. */
1724 if (i == FIRST_PSEUDO_REGISTER)
1725 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1728 j = potential_reload_regs[i];
1729 /* Verify that J+1 is a potential reload reg. */
1730 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1731 if (potential_reload_regs[k] == j + 1)
1733 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1734 && k < FIRST_PSEUDO_REGISTER
1735 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1736 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1737 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1738 && HARD_REGNO_MODE_OK (j, chain->group_mode[class])
1739 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, j + 1)
1740 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1))
1744 /* I should be the index in potential_reload_regs
1745 of the new reload reg we have found. */
1747 new_spill_reg (chain, i, class, 0, dumpfile);
1750 /* Find a group of more than 2 registers.
1751 Look for a sufficient sequence of unspilled registers, and spill them all
1755 find_group (chain, class, dumpfile)
1756 struct insn_chain *chain;
1762 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1764 int j = potential_reload_regs[i];
1767 && j + chain->group_size[class] <= FIRST_PSEUDO_REGISTER
1768 && HARD_REGNO_MODE_OK (j, chain->group_mode[class]))
1771 /* Check each reg in the sequence. */
1772 for (k = 0; k < chain->group_size[class]; k++)
1773 if (! (spill_reg_order[j + k] < 0
1774 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1775 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1777 /* We got a full sequence, so spill them all. */
1778 if (k == chain->group_size[class])
1780 register enum reg_class *p;
1781 for (k = 0; k < chain->group_size[class]; k++)
1784 SET_HARD_REG_BIT (chain->counted_for_groups, j + k);
1785 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1786 if (potential_reload_regs[idx] == j + k)
1788 new_spill_reg (chain, idx, class, 0, dumpfile);
1791 /* We have found one that will complete a group,
1792 so count off one group as provided. */
1793 chain->need.groups[class]--;
1794 p = reg_class_superclasses[class];
1795 while (*p != LIM_REG_CLASSES)
1797 if (chain->group_size [(int) *p]
1798 <= chain->group_size [class])
1799 chain->need.groups[(int) *p]--;
1806 /* There are no groups left. */
1807 spill_failure (chain->insn);
1811 /* If pseudo REG conflicts with one of our reload registers, mark it as
1814 maybe_mark_pseudo_spilled (reg)
1818 int r = reg_renumber[reg];
1823 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1824 for (i = 0; i < n_spills; i++)
1825 if (r <= spill_regs[i] && r + nregs > spill_regs[i])
1827 SET_REGNO_REG_SET (spilled_pseudos, reg);
1832 /* Find more reload regs to satisfy the remaining need of an insn, which
1834 Do it by ascending class number, since otherwise a reg
1835 might be spilled for a big class and might fail to count
1836 for a smaller class even though it belongs to that class.
1838 Count spilled regs in `spills', and add entries to
1839 `spill_regs' and `spill_reg_order'.
1841 ??? Note there is a problem here.
1842 When there is a need for a group in a high-numbered class,
1843 and also need for non-group regs that come from a lower class,
1844 the non-group regs are chosen first. If there aren't many regs,
1845 they might leave no room for a group.
1847 This was happening on the 386. To fix it, we added the code
1848 that calls possible_group_p, so that the lower class won't
1849 break up the last possible group.
1851 Really fixing the problem would require changes above
1852 in counting the regs already spilled, and in choose_reload_regs.
1853 It might be hard to avoid introducing bugs there. */
1856 find_reload_regs (chain, dumpfile)
1857 struct insn_chain *chain;
1861 short *group_needs = chain->need.groups;
1862 short *simple_needs = chain->need.regs[0];
1863 short *nongroup_needs = chain->need.regs[1];
1866 fprintf (dumpfile, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1868 /* Compute the order of preference for hard registers to spill.
1869 Store them by decreasing preference in potential_reload_regs. */
1871 order_regs_for_reload (chain);
1873 /* So far, no hard regs have been spilled. */
1875 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1876 spill_reg_order[i] = -1;
1878 CLEAR_HARD_REG_SET (chain->used_spill_regs);
1879 CLEAR_HARD_REG_SET (chain->counted_for_groups);
1880 CLEAR_HARD_REG_SET (chain->counted_for_nongroups);
1882 for (class = 0; class < N_REG_CLASSES; class++)
1884 /* First get the groups of registers.
1885 If we got single registers first, we might fragment
1887 while (group_needs[class] > 0)
1889 /* If any single spilled regs happen to form groups,
1890 count them now. Maybe we don't really need
1891 to spill another group. */
1892 count_possible_groups (chain, class);
1894 if (group_needs[class] <= 0)
1897 /* Groups of size 2, the only groups used on most machines,
1898 are treated specially. */
1899 if (chain->group_size[class] == 2)
1900 find_tworeg_group (chain, class, dumpfile);
1902 find_group (chain, class, dumpfile);
1907 /* Now similarly satisfy all need for single registers. */
1909 while (simple_needs[class] > 0 || nongroup_needs[class] > 0)
1911 /* If we spilled enough regs, but they weren't counted
1912 against the non-group need, see if we can count them now.
1913 If so, we can avoid some actual spilling. */
1914 if (simple_needs[class] <= 0 && nongroup_needs[class] > 0)
1915 for (i = 0; i < n_spills; i++)
1917 int regno = spill_regs[i];
1918 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1919 && !TEST_HARD_REG_BIT (chain->counted_for_groups, regno)
1920 && !TEST_HARD_REG_BIT (chain->counted_for_nongroups, regno)
1921 && nongroup_needs[class] > 0)
1923 register enum reg_class *p;
1925 SET_HARD_REG_BIT (chain->counted_for_nongroups, regno);
1926 nongroup_needs[class]--;
1927 p = reg_class_superclasses[class];
1928 while (*p != LIM_REG_CLASSES)
1929 nongroup_needs[(int) *p++]--;
1933 if (simple_needs[class] <= 0 && nongroup_needs[class] <= 0)
1936 /* Consider the potential reload regs that aren't
1937 yet in use as reload regs, in order of preference.
1938 Find the most preferred one that's in this class. */
1940 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1942 int regno = potential_reload_regs[i];
1944 && TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1945 /* If this reg will not be available for groups,
1946 pick one that does not foreclose possible groups.
1947 This is a kludge, and not very general,
1948 but it should be sufficient to make the 386 work,
1949 and the problem should not occur on machines with
1951 && (nongroup_needs[class] == 0
1952 || possible_group_p (chain, regno)))
1956 /* If we couldn't get a register, try to get one even if we
1957 might foreclose possible groups. This may cause problems
1958 later, but that's better than aborting now, since it is
1959 possible that we will, in fact, be able to form the needed
1960 group even with this allocation. */
1962 if (i >= FIRST_PSEUDO_REGISTER
1963 && asm_noperands (chain->insn) < 0)
1964 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1965 if (potential_reload_regs[i] >= 0
1966 && TEST_HARD_REG_BIT (reg_class_contents[class],
1967 potential_reload_regs[i]))
1970 /* I should be the index in potential_reload_regs
1971 of the new reload reg we have found. */
1973 new_spill_reg (chain, i, class, 1, dumpfile);
1979 /* We know which hard regs to use, now mark the pseudos that live in them
1980 as needing to be kicked out. */
1981 EXECUTE_IF_SET_IN_REG_SET
1982 (chain->live_before, FIRST_PSEUDO_REGISTER, i,
1984 maybe_mark_pseudo_spilled (i);
1986 EXECUTE_IF_SET_IN_REG_SET
1987 (chain->live_after, FIRST_PSEUDO_REGISTER, i,
1989 maybe_mark_pseudo_spilled (i);
1992 IOR_HARD_REG_SET (used_spill_regs, chain->used_spill_regs);
1996 dump_needs (chain, dumpfile)
1997 struct insn_chain *chain;
2000 static const char * const reg_class_names[] = REG_CLASS_NAMES;
2002 struct needs *n = &chain->need;
2004 for (i = 0; i < N_REG_CLASSES; i++)
2006 if (n->regs[i][0] > 0)
2008 ";; Need %d reg%s of class %s.\n",
2009 n->regs[i][0], n->regs[i][0] == 1 ? "" : "s",
2010 reg_class_names[i]);
2011 if (n->regs[i][1] > 0)
2013 ";; Need %d nongroup reg%s of class %s.\n",
2014 n->regs[i][1], n->regs[i][1] == 1 ? "" : "s",
2015 reg_class_names[i]);
2016 if (n->groups[i] > 0)
2018 ";; Need %d group%s (%smode) of class %s.\n",
2019 n->groups[i], n->groups[i] == 1 ? "" : "s",
2020 GET_MODE_NAME(chain->group_mode[i]),
2021 reg_class_names[i]);
2025 /* Delete all insns that were inserted by emit_caller_save_insns during
2028 delete_caller_save_insns ()
2030 struct insn_chain *c = reload_insn_chain;
2034 while (c != 0 && c->is_caller_save_insn)
2036 struct insn_chain *next = c->next;
2039 if (insn == BLOCK_HEAD (c->block))
2040 BLOCK_HEAD (c->block) = NEXT_INSN (insn);
2041 if (insn == BLOCK_END (c->block))
2042 BLOCK_END (c->block) = PREV_INSN (insn);
2043 if (c == reload_insn_chain)
2044 reload_insn_chain = next;
2046 if (NEXT_INSN (insn) != 0)
2047 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2048 if (PREV_INSN (insn) != 0)
2049 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2052 next->prev = c->prev;
2054 c->prev->next = next;
2055 c->next = unused_insn_chains;
2056 unused_insn_chains = c;
2064 /* Nonzero if, after spilling reg REGNO for non-groups,
2065 it will still be possible to find a group if we still need one. */
2068 possible_group_p (chain, regno)
2069 struct insn_chain *chain;
2073 int class = (int) NO_REGS;
2075 for (i = 0; i < (int) N_REG_CLASSES; i++)
2076 if (chain->need.groups[i] > 0)
2082 if (class == (int) NO_REGS)
2085 /* Consider each pair of consecutive registers. */
2086 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
2088 /* Ignore pairs that include reg REGNO. */
2089 if (i == regno || i + 1 == regno)
2092 /* Ignore pairs that are outside the class that needs the group.
2093 ??? Here we fail to handle the case where two different classes
2094 independently need groups. But this never happens with our
2095 current machine descriptions. */
2096 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
2097 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
2100 /* A pair of consecutive regs we can still spill does the trick. */
2101 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
2102 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2103 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
2106 /* A pair of one already spilled and one we can spill does it
2107 provided the one already spilled is not otherwise reserved. */
2108 if (spill_reg_order[i] < 0
2109 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2110 && spill_reg_order[i + 1] >= 0
2111 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, i + 1)
2112 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, i + 1))
2114 if (spill_reg_order[i + 1] < 0
2115 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
2116 && spill_reg_order[i] >= 0
2117 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, i)
2118 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, i))
2125 /* Count any groups of CLASS that can be formed from the registers recently
2129 count_possible_groups (chain, class)
2130 struct insn_chain *chain;
2136 /* Now find all consecutive groups of spilled registers
2137 and mark each group off against the need for such groups.
2138 But don't count them against ordinary need, yet. */
2140 if (chain->group_size[class] == 0)
2143 CLEAR_HARD_REG_SET (new);
2145 /* Make a mask of all the regs that are spill regs in class I. */
2146 for (i = 0; i < n_spills; i++)
2148 int regno = spill_regs[i];
2150 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
2151 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, regno)
2152 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, regno))
2153 SET_HARD_REG_BIT (new, regno);
2156 /* Find each consecutive group of them. */
2157 for (i = 0; i < FIRST_PSEUDO_REGISTER && chain->need.groups[class] > 0; i++)
2158 if (TEST_HARD_REG_BIT (new, i)
2159 && i + chain->group_size[class] <= FIRST_PSEUDO_REGISTER
2160 && HARD_REGNO_MODE_OK (i, chain->group_mode[class]))
2162 for (j = 1; j < chain->group_size[class]; j++)
2163 if (! TEST_HARD_REG_BIT (new, i + j))
2166 if (j == chain->group_size[class])
2168 /* We found a group. Mark it off against this class's need for
2169 groups, and against each superclass too. */
2170 register enum reg_class *p;
2172 chain->need.groups[class]--;
2173 p = reg_class_superclasses[class];
2174 while (*p != LIM_REG_CLASSES)
2176 if (chain->group_size [(int) *p] <= chain->group_size [class])
2177 chain->need.groups[(int) *p]--;
2181 /* Don't count these registers again. */
2182 for (j = 0; j < chain->group_size[class]; j++)
2183 SET_HARD_REG_BIT (chain->counted_for_groups, i + j);
2186 /* Skip to the last reg in this group. When i is incremented above,
2187 it will then point to the first reg of the next possible group. */
2192 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2193 another mode that needs to be reloaded for the same register class CLASS.
2194 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2195 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2197 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2198 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2199 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2200 causes unnecessary failures on machines requiring alignment of register
2201 groups when the two modes are different sizes, because the larger mode has
2202 more strict alignment rules than the smaller mode. */
2205 modes_equiv_for_class_p (allocate_mode, other_mode, class)
2206 enum machine_mode allocate_mode, other_mode;
2207 enum reg_class class;
2210 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2212 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
2213 && HARD_REGNO_MODE_OK (regno, allocate_mode)
2214 && ! HARD_REGNO_MODE_OK (regno, other_mode))
2220 /* Handle the failure to find a register to spill.
2221 INSN should be one of the insns which needed this particular spill reg. */
2224 spill_failure (insn)
2227 if (asm_noperands (PATTERN (insn)) >= 0)
2228 error_for_asm (insn, "`asm' needs too many reloads");
2230 fatal_insn ("Unable to find a register to spill.", insn);
2233 /* Add a new register to the tables of available spill-registers.
2234 CHAIN is the insn for which the register will be used; we decrease the
2236 I is the index of this register in potential_reload_regs.
2237 CLASS is the regclass whose need is being satisfied.
2238 NONGROUP is 0 if this register is part of a group.
2239 DUMPFILE is the same as the one that `reload' got. */
2242 new_spill_reg (chain, i, class, nongroup, dumpfile)
2243 struct insn_chain *chain;
2249 register enum reg_class *p;
2250 int regno = potential_reload_regs[i];
2252 if (i >= FIRST_PSEUDO_REGISTER)
2254 spill_failure (chain->insn);
2259 if (TEST_HARD_REG_BIT (bad_spill_regs, regno))
2261 static const char * const reg_class_names[] = REG_CLASS_NAMES;
2263 if (asm_noperands (PATTERN (chain->insn)) < 0)
2265 /* The error message is still correct - we know only that it wasn't
2266 an asm statement that caused the problem, but one of the global
2267 registers declared by the users might have screwed us. */
2268 error ("fixed or forbidden register %d (%s) was spilled for class %s.",
2269 regno, reg_names[regno], reg_class_names[class]);
2270 error ("This may be due to a compiler bug or to impossible asm");
2271 error ("statements or clauses.");
2272 fatal_insn ("This is the instruction:", chain->insn);
2274 error_for_asm (chain->insn, "Invalid `asm' statement:");
2275 error_for_asm (chain->insn,
2276 "fixed or forbidden register %d (%s) was spilled for class %s.",
2277 regno, reg_names[regno], reg_class_names[class]);
2282 /* Make reg REGNO an additional reload reg. */
2284 potential_reload_regs[i] = -1;
2285 spill_regs[n_spills] = regno;
2286 spill_reg_order[regno] = n_spills;
2288 fprintf (dumpfile, "Spilling reg %d.\n", regno);
2289 SET_HARD_REG_BIT (chain->used_spill_regs, regno);
2291 /* Clear off the needs we just satisfied. */
2293 chain->need.regs[0][class]--;
2294 p = reg_class_superclasses[class];
2295 while (*p != LIM_REG_CLASSES)
2296 chain->need.regs[0][(int) *p++]--;
2298 if (nongroup && chain->need.regs[1][class] > 0)
2300 SET_HARD_REG_BIT (chain->counted_for_nongroups, regno);
2301 chain->need.regs[1][class]--;
2302 p = reg_class_superclasses[class];
2303 while (*p != LIM_REG_CLASSES)
2304 chain->need.regs[1][(int) *p++]--;
2310 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2311 data that is dead in INSN. */
2314 delete_dead_insn (insn)
2317 rtx prev = prev_real_insn (insn);
2320 /* If the previous insn sets a register that dies in our insn, delete it
2322 if (prev && GET_CODE (PATTERN (prev)) == SET
2323 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2324 && reg_mentioned_p (prev_dest, PATTERN (insn))
2325 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2326 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2327 delete_dead_insn (prev);
2329 PUT_CODE (insn, NOTE);
2330 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2331 NOTE_SOURCE_FILE (insn) = 0;
2334 /* Modify the home of pseudo-reg I.
2335 The new home is present in reg_renumber[I].
2337 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2338 or it may be -1, meaning there is none or it is not relevant.
2339 This is used so that all pseudos spilled from a given hard reg
2340 can share one stack slot. */
2343 alter_reg (i, from_reg)
2347 /* When outputting an inline function, this can happen
2348 for a reg that isn't actually used. */
2349 if (regno_reg_rtx[i] == 0)
2352 /* If the reg got changed to a MEM at rtl-generation time,
2354 if (GET_CODE (regno_reg_rtx[i]) != REG)
2357 /* Modify the reg-rtx to contain the new hard reg
2358 number or else to contain its pseudo reg number. */
2359 REGNO (regno_reg_rtx[i])
2360 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2362 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2363 allocate a stack slot for it. */
2365 if (reg_renumber[i] < 0
2366 && REG_N_REFS (i) > 0
2367 && reg_equiv_constant[i] == 0
2368 && reg_equiv_memory_loc[i] == 0)
2371 int inherent_size = PSEUDO_REGNO_BYTES (i);
2372 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2375 /* Each pseudo reg has an inherent size which comes from its own mode,
2376 and a total size which provides room for paradoxical subregs
2377 which refer to the pseudo reg in wider modes.
2379 We can use a slot already allocated if it provides both
2380 enough inherent space and enough total space.
2381 Otherwise, we allocate a new slot, making sure that it has no less
2382 inherent space, and no less total space, then the previous slot. */
2385 /* No known place to spill from => no slot to reuse. */
2386 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
2387 inherent_size == total_size ? 0 : -1);
2388 if (BYTES_BIG_ENDIAN)
2389 /* Cancel the big-endian correction done in assign_stack_local.
2390 Get the address of the beginning of the slot.
2391 This is so we can do a big-endian correction unconditionally
2393 adjust = inherent_size - total_size;
2395 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2397 /* Reuse a stack slot if possible. */
2398 else if (spill_stack_slot[from_reg] != 0
2399 && spill_stack_slot_width[from_reg] >= total_size
2400 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2402 x = spill_stack_slot[from_reg];
2403 /* Allocate a bigger slot. */
2406 /* Compute maximum size needed, both for inherent size
2407 and for total size. */
2408 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2410 if (spill_stack_slot[from_reg])
2412 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2414 mode = GET_MODE (spill_stack_slot[from_reg]);
2415 if (spill_stack_slot_width[from_reg] > total_size)
2416 total_size = spill_stack_slot_width[from_reg];
2418 /* Make a slot with that size. */
2419 x = assign_stack_local (mode, total_size,
2420 inherent_size == total_size ? 0 : -1);
2422 if (BYTES_BIG_ENDIAN)
2424 /* Cancel the big-endian correction done in assign_stack_local.
2425 Get the address of the beginning of the slot.
2426 This is so we can do a big-endian correction unconditionally
2428 adjust = GET_MODE_SIZE (mode) - total_size;
2430 stack_slot = gen_rtx_MEM (mode_for_size (total_size
2433 plus_constant (XEXP (x, 0), adjust));
2435 spill_stack_slot[from_reg] = stack_slot;
2436 spill_stack_slot_width[from_reg] = total_size;
2439 /* On a big endian machine, the "address" of the slot
2440 is the address of the low part that fits its inherent mode. */
2441 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2442 adjust += (total_size - inherent_size);
2444 /* If we have any adjustment to make, or if the stack slot is the
2445 wrong mode, make a new stack slot. */
2446 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2448 x = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
2449 plus_constant (XEXP (x, 0), adjust));
2451 /* If this was shared among registers, must ensure we never
2452 set it readonly since that can cause scheduling
2453 problems. Note we would only have in this adjustment
2454 case in any event, since the code above doesn't set it. */
2457 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2460 /* Save the stack slot for later. */
2461 reg_equiv_memory_loc[i] = x;
2465 /* Mark the slots in regs_ever_live for the hard regs
2466 used by pseudo-reg number REGNO. */
2469 mark_home_live (regno)
2472 register int i, lim;
2473 i = reg_renumber[regno];
2476 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2478 regs_ever_live[i++] = 1;
2481 /* This function handles the tracking of elimination offsets around branches.
2483 X is a piece of RTL being scanned.
2485 INSN is the insn that it came from, if any.
2487 INITIAL_P is non-zero if we are to set the offset to be the initial
2488 offset and zero if we are setting the offset of the label to be the
2492 set_label_offsets (x, insn, initial_p)
2497 enum rtx_code code = GET_CODE (x);
2500 struct elim_table *p;
2505 if (LABEL_REF_NONLOCAL_P (x))
2510 /* ... fall through ... */
2513 /* If we know nothing about this label, set the desired offsets. Note
2514 that this sets the offset at a label to be the offset before a label
2515 if we don't know anything about the label. This is not correct for
2516 the label after a BARRIER, but is the best guess we can make. If
2517 we guessed wrong, we will suppress an elimination that might have
2518 been possible had we been able to guess correctly. */
2520 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2522 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2523 offsets_at[CODE_LABEL_NUMBER (x)][i]
2524 = (initial_p ? reg_eliminate[i].initial_offset
2525 : reg_eliminate[i].offset);
2526 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2529 /* Otherwise, if this is the definition of a label and it is
2530 preceded by a BARRIER, set our offsets to the known offset of
2534 && (tem = prev_nonnote_insn (insn)) != 0
2535 && GET_CODE (tem) == BARRIER)
2536 set_offsets_for_label (insn);
2538 /* If neither of the above cases is true, compare each offset
2539 with those previously recorded and suppress any eliminations
2540 where the offsets disagree. */
2542 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2543 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2544 != (initial_p ? reg_eliminate[i].initial_offset
2545 : reg_eliminate[i].offset))
2546 reg_eliminate[i].can_eliminate = 0;
2551 set_label_offsets (PATTERN (insn), insn, initial_p);
2553 /* ... fall through ... */
2557 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2558 and hence must have all eliminations at their initial offsets. */
2559 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2560 if (REG_NOTE_KIND (tem) == REG_LABEL)
2561 set_label_offsets (XEXP (tem, 0), insn, 1);
2566 /* Each of the labels in the address vector must be at their initial
2567 offsets. We want the first field for ADDR_VEC and the second
2568 field for ADDR_DIFF_VEC. */
2570 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2571 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2576 /* We only care about setting PC. If the source is not RETURN,
2577 IF_THEN_ELSE, or a label, disable any eliminations not at
2578 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2579 isn't one of those possibilities. For branches to a label,
2580 call ourselves recursively.
2582 Note that this can disable elimination unnecessarily when we have
2583 a non-local goto since it will look like a non-constant jump to
2584 someplace in the current function. This isn't a significant
2585 problem since such jumps will normally be when all elimination
2586 pairs are back to their initial offsets. */
2588 if (SET_DEST (x) != pc_rtx)
2591 switch (GET_CODE (SET_SRC (x)))
2598 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2602 tem = XEXP (SET_SRC (x), 1);
2603 if (GET_CODE (tem) == LABEL_REF)
2604 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2605 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2608 tem = XEXP (SET_SRC (x), 2);
2609 if (GET_CODE (tem) == LABEL_REF)
2610 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2611 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2619 /* If we reach here, all eliminations must be at their initial
2620 offset because we are doing a jump to a variable address. */
2621 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2622 if (p->offset != p->initial_offset)
2623 p->can_eliminate = 0;
2631 /* Scan X and replace any eliminable registers (such as fp) with a
2632 replacement (such as sp), plus an offset.
2634 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2635 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2636 MEM, we are allowed to replace a sum of a register and the constant zero
2637 with the register, which we cannot do outside a MEM. In addition, we need
2638 to record the fact that a register is referenced outside a MEM.
2640 If INSN is an insn, it is the insn containing X. If we replace a REG
2641 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2642 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2643 the REG is being modified.
2645 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2646 That's used when we eliminate in expressions stored in notes.
2647 This means, do not set ref_outside_mem even if the reference
2650 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2651 replacements done assuming all offsets are at their initial values. If
2652 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2653 encounter, return the actual location so that find_reloads will do
2654 the proper thing. */
2657 eliminate_regs (x, mem_mode, insn)
2659 enum machine_mode mem_mode;
2662 enum rtx_code code = GET_CODE (x);
2663 struct elim_table *ep;
2670 if (! current_function_decl)
2689 /* This is only for the benefit of the debugging backends, which call
2690 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2691 removed after CSE. */
2692 new = eliminate_regs (XEXP (x, 0), 0, insn);
2693 if (GET_CODE (new) == MEM)
2694 return XEXP (new, 0);
2700 /* First handle the case where we encounter a bare register that
2701 is eliminable. Replace it with a PLUS. */
2702 if (regno < FIRST_PSEUDO_REGISTER)
2704 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2706 if (ep->from_rtx == x && ep->can_eliminate)
2707 return plus_constant (ep->to_rtx, ep->previous_offset);
2710 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2711 && reg_equiv_constant[regno]
2712 && ! CONSTANT_P (reg_equiv_constant[regno]))
2713 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2717 /* You might think handling MINUS in a manner similar to PLUS is a
2718 good idea. It is not. It has been tried multiple times and every
2719 time the change has had to have been reverted.
2721 Other parts of reload know a PLUS is special (gen_reload for example)
2722 and require special code to handle code a reloaded PLUS operand.
2724 Also consider backends where the flags register is clobbered by a
2725 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2726 lea instruction comes to mind). If we try to reload a MINUS, we
2727 may kill the flags register that was holding a useful value.
2729 So, please before trying to handle MINUS, consider reload as a
2730 whole instead of this little section as well as the backend issues. */
2732 /* If this is the sum of an eliminable register and a constant, rework
2734 if (GET_CODE (XEXP (x, 0)) == REG
2735 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2736 && CONSTANT_P (XEXP (x, 1)))
2738 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2740 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2742 /* The only time we want to replace a PLUS with a REG (this
2743 occurs when the constant operand of the PLUS is the negative
2744 of the offset) is when we are inside a MEM. We won't want
2745 to do so at other times because that would change the
2746 structure of the insn in a way that reload can't handle.
2747 We special-case the commonest situation in
2748 eliminate_regs_in_insn, so just replace a PLUS with a
2749 PLUS here, unless inside a MEM. */
2750 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2751 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2754 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2755 plus_constant (XEXP (x, 1),
2756 ep->previous_offset));
2759 /* If the register is not eliminable, we are done since the other
2760 operand is a constant. */
2764 /* If this is part of an address, we want to bring any constant to the
2765 outermost PLUS. We will do this by doing register replacement in
2766 our operands and seeing if a constant shows up in one of them.
2768 Note that there is no risk of modifying the structure of the insn,
2769 since we only get called for its operands, thus we are either
2770 modifying the address inside a MEM, or something like an address
2771 operand of a load-address insn. */
2774 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2775 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2777 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2779 /* If one side is a PLUS and the other side is a pseudo that
2780 didn't get a hard register but has a reg_equiv_constant,
2781 we must replace the constant here since it may no longer
2782 be in the position of any operand. */
2783 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2784 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2785 && reg_renumber[REGNO (new1)] < 0
2786 && reg_equiv_constant != 0
2787 && reg_equiv_constant[REGNO (new1)] != 0)
2788 new1 = reg_equiv_constant[REGNO (new1)];
2789 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2790 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2791 && reg_renumber[REGNO (new0)] < 0
2792 && reg_equiv_constant[REGNO (new0)] != 0)
2793 new0 = reg_equiv_constant[REGNO (new0)];
2795 new = form_sum (new0, new1);
2797 /* As above, if we are not inside a MEM we do not want to
2798 turn a PLUS into something else. We might try to do so here
2799 for an addition of 0 if we aren't optimizing. */
2800 if (! mem_mode && GET_CODE (new) != PLUS)
2801 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2809 /* If this is the product of an eliminable register and a
2810 constant, apply the distribute law and move the constant out
2811 so that we have (plus (mult ..) ..). This is needed in order
2812 to keep load-address insns valid. This case is pathological.
2813 We ignore the possibility of overflow here. */
2814 if (GET_CODE (XEXP (x, 0)) == REG
2815 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2816 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2817 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2819 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2822 /* Refs inside notes don't count for this purpose. */
2823 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2824 || GET_CODE (insn) == INSN_LIST)))
2825 ep->ref_outside_mem = 1;
2828 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2829 ep->previous_offset * INTVAL (XEXP (x, 1)));
2832 /* ... fall through ... */
2836 /* See comments before PLUS about handling MINUS. */
2838 case DIV: case UDIV:
2839 case MOD: case UMOD:
2840 case AND: case IOR: case XOR:
2841 case ROTATERT: case ROTATE:
2842 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2844 case GE: case GT: case GEU: case GTU:
2845 case LE: case LT: case LEU: case LTU:
2847 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2849 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2851 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2852 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2857 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2860 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2861 if (new != XEXP (x, 0))
2863 /* If this is a REG_DEAD note, it is not valid anymore.
2864 Using the eliminated version could result in creating a
2865 REG_DEAD note for the stack or frame pointer. */
2866 if (GET_MODE (x) == REG_DEAD)
2868 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2871 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2875 /* ... fall through ... */
2878 /* Now do eliminations in the rest of the chain. If this was
2879 an EXPR_LIST, this might result in allocating more memory than is
2880 strictly needed, but it simplifies the code. */
2883 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2884 if (new != XEXP (x, 1))
2885 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2893 case STRICT_LOW_PART:
2895 case SIGN_EXTEND: case ZERO_EXTEND:
2896 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2897 case FLOAT: case FIX:
2898 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2902 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2903 if (new != XEXP (x, 0))
2904 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2908 /* Similar to above processing, but preserve SUBREG_WORD.
2909 Convert (subreg (mem)) to (mem) if not paradoxical.
2910 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2911 pseudo didn't get a hard reg, we must replace this with the
2912 eliminated version of the memory location because push_reloads
2913 may do the replacement in certain circumstances. */
2914 if (GET_CODE (SUBREG_REG (x)) == REG
2915 && (GET_MODE_SIZE (GET_MODE (x))
2916 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2917 && reg_equiv_memory_loc != 0
2918 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2920 new = SUBREG_REG (x);
2923 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2925 if (new != XEXP (x, 0))
2927 int x_size = GET_MODE_SIZE (GET_MODE (x));
2928 int new_size = GET_MODE_SIZE (GET_MODE (new));
2930 if (GET_CODE (new) == MEM
2931 && ((x_size < new_size
2932 #ifdef WORD_REGISTER_OPERATIONS
2933 /* On these machines, combine can create rtl of the form
2934 (set (subreg:m1 (reg:m2 R) 0) ...)
2935 where m1 < m2, and expects something interesting to
2936 happen to the entire word. Moreover, it will use the
2937 (reg:m2 R) later, expecting all bits to be preserved.
2938 So if the number of words is the same, preserve the
2939 subreg so that push_reloads can see it. */
2940 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
2943 || (x_size == new_size))
2946 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2947 enum machine_mode mode = GET_MODE (x);
2949 if (BYTES_BIG_ENDIAN)
2950 offset += (MIN (UNITS_PER_WORD,
2951 GET_MODE_SIZE (GET_MODE (new)))
2952 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2954 PUT_MODE (new, mode);
2955 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2959 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
2965 /* This is only for the benefit of the debugging backends, which call
2966 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2967 removed after CSE. */
2968 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2969 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2971 /* Our only special processing is to pass the mode of the MEM to our
2972 recursive call and copy the flags. While we are here, handle this
2973 case more efficiently. */
2974 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
2975 if (new != XEXP (x, 0))
2977 new = gen_rtx_MEM (GET_MODE (x), new);
2978 new->volatil = x->volatil;
2979 new->unchanging = x->unchanging;
2980 new->in_struct = x->in_struct;
2996 /* Process each of our operands recursively. If any have changed, make a
2998 fmt = GET_RTX_FORMAT (code);
2999 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3003 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
3004 if (new != XEXP (x, i) && ! copied)
3006 rtx new_x = rtx_alloc (code);
3007 bcopy ((char *) x, (char *) new_x,
3008 (sizeof (*new_x) - sizeof (new_x->fld)
3009 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
3015 else if (*fmt == 'E')
3018 for (j = 0; j < XVECLEN (x, i); j++)
3020 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
3021 if (new != XVECEXP (x, i, j) && ! copied_vec)
3023 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
3027 rtx new_x = rtx_alloc (code);
3028 bcopy ((char *) x, (char *) new_x,
3029 (sizeof (*new_x) - sizeof (new_x->fld)
3030 + (sizeof (new_x->fld[0])
3031 * GET_RTX_LENGTH (code))));
3035 XVEC (x, i) = new_v;
3038 XVECEXP (x, i, j) = new;
3046 /* Scan rtx X for modifications of elimination target registers. Update
3047 the table of eliminables to reflect the changed state. MEM_MODE is
3048 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
3051 elimination_effects (x, mem_mode)
3053 enum machine_mode mem_mode;
3056 enum rtx_code code = GET_CODE (x);
3057 struct elim_table *ep;
3083 /* First handle the case where we encounter a bare register that
3084 is eliminable. Replace it with a PLUS. */
3085 if (regno < FIRST_PSEUDO_REGISTER)
3087 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3089 if (ep->from_rtx == x && ep->can_eliminate)
3092 ep->ref_outside_mem = 1;
3097 else if (reg_renumber[regno] < 0 && reg_equiv_constant
3098 && reg_equiv_constant[regno]
3099 && ! CONSTANT_P (reg_equiv_constant[regno]))
3100 elimination_effects (reg_equiv_constant[regno], mem_mode);
3107 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3108 if (ep->to_rtx == XEXP (x, 0))
3110 int size = GET_MODE_SIZE (mem_mode);
3112 /* If more bytes than MEM_MODE are pushed, account for them. */
3113 #ifdef PUSH_ROUNDING
3114 if (ep->to_rtx == stack_pointer_rtx)
3115 size = PUSH_ROUNDING (size);
3117 if (code == PRE_DEC || code == POST_DEC)
3123 /* Fall through to generic unary operation case. */
3124 case STRICT_LOW_PART:
3126 case SIGN_EXTEND: case ZERO_EXTEND:
3127 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3128 case FLOAT: case FIX:
3129 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3133 elimination_effects (XEXP (x, 0), mem_mode);
3137 if (GET_CODE (SUBREG_REG (x)) == REG
3138 && (GET_MODE_SIZE (GET_MODE (x))
3139 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3140 && reg_equiv_memory_loc != 0
3141 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
3144 elimination_effects (SUBREG_REG (x), mem_mode);
3148 /* If using a register that is the source of an eliminate we still
3149 think can be performed, note it cannot be performed since we don't
3150 know how this register is used. */
3151 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3152 if (ep->from_rtx == XEXP (x, 0))
3153 ep->can_eliminate = 0;
3155 elimination_effects (XEXP (x, 0), mem_mode);
3159 /* If clobbering a register that is the replacement register for an
3160 elimination we still think can be performed, note that it cannot
3161 be performed. Otherwise, we need not be concerned about it. */
3162 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3163 if (ep->to_rtx == XEXP (x, 0))
3164 ep->can_eliminate = 0;
3166 elimination_effects (XEXP (x, 0), mem_mode);
3170 /* Check for setting a register that we know about. */
3171 if (GET_CODE (SET_DEST (x)) == REG)
3173 /* See if this is setting the replacement register for an
3176 If DEST is the hard frame pointer, we do nothing because we
3177 assume that all assignments to the frame pointer are for
3178 non-local gotos and are being done at a time when they are valid
3179 and do not disturb anything else. Some machines want to
3180 eliminate a fake argument pointer (or even a fake frame pointer)
3181 with either the real frame or the stack pointer. Assignments to
3182 the hard frame pointer must not prevent this elimination. */
3184 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3186 if (ep->to_rtx == SET_DEST (x)
3187 && SET_DEST (x) != hard_frame_pointer_rtx)
3189 /* If it is being incremented, adjust the offset. Otherwise,
3190 this elimination can't be done. */
3191 rtx src = SET_SRC (x);
3193 if (GET_CODE (src) == PLUS
3194 && XEXP (src, 0) == SET_DEST (x)
3195 && GET_CODE (XEXP (src, 1)) == CONST_INT)
3196 ep->offset -= INTVAL (XEXP (src, 1));
3198 ep->can_eliminate = 0;
3202 elimination_effects (SET_DEST (x), 0);
3203 elimination_effects (SET_SRC (x), 0);
3207 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
3210 /* Our only special processing is to pass the mode of the MEM to our
3212 elimination_effects (XEXP (x, 0), GET_MODE (x));
3219 fmt = GET_RTX_FORMAT (code);
3220 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3223 elimination_effects (XEXP (x, i), mem_mode);
3224 else if (*fmt == 'E')
3225 for (j = 0; j < XVECLEN (x, i); j++)
3226 elimination_effects (XVECEXP (x, i, j), mem_mode);
3230 /* Descend through rtx X and verify that no references to eliminable registers
3231 remain. If any do remain, mark the involved register as not
3234 check_eliminable_occurrences (x)
3244 code = GET_CODE (x);
3246 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3248 struct elim_table *ep;
3250 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3251 if (ep->from_rtx == x && ep->can_eliminate)
3252 ep->can_eliminate = 0;
3256 fmt = GET_RTX_FORMAT (code);
3257 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3260 check_eliminable_occurrences (XEXP (x, i));
3261 else if (*fmt == 'E')
3264 for (j = 0; j < XVECLEN (x, i); j++)
3265 check_eliminable_occurrences (XVECEXP (x, i, j));
3270 /* Scan INSN and eliminate all eliminable registers in it.
3272 If REPLACE is nonzero, do the replacement destructively. Also
3273 delete the insn as dead it if it is setting an eliminable register.
3275 If REPLACE is zero, do all our allocations in reload_obstack.
3277 If no eliminations were done and this insn doesn't require any elimination
3278 processing (these are not identical conditions: it might be updating sp,
3279 but not referencing fp; this needs to be seen during reload_as_needed so
3280 that the offset between fp and sp can be taken into consideration), zero
3281 is returned. Otherwise, 1 is returned. */
3284 eliminate_regs_in_insn (insn, replace)
3288 int icode = recog_memoized (insn);
3289 rtx old_body = PATTERN (insn);
3290 int insn_is_asm = asm_noperands (old_body) >= 0;
3291 rtx old_set = single_set (insn);
3295 rtx substed_operand[MAX_RECOG_OPERANDS];
3296 rtx orig_operand[MAX_RECOG_OPERANDS];
3297 struct elim_table *ep;
3299 if (! insn_is_asm && icode < 0)
3301 if (GET_CODE (PATTERN (insn)) == USE
3302 || GET_CODE (PATTERN (insn)) == CLOBBER
3303 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3304 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3305 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
3311 push_obstacks (&reload_obstack, &reload_obstack);
3313 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
3314 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3316 /* Check for setting an eliminable register. */
3317 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3318 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3320 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3321 /* If this is setting the frame pointer register to the
3322 hardware frame pointer register and this is an elimination
3323 that will be done (tested above), this insn is really
3324 adjusting the frame pointer downward to compensate for
3325 the adjustment done before a nonlocal goto. */
3326 if (ep->from == FRAME_POINTER_REGNUM
3327 && ep->to == HARD_FRAME_POINTER_REGNUM)
3329 rtx src = SET_SRC (old_set);
3330 int offset = 0, ok = 0;
3331 rtx prev_insn, prev_set;
3333 if (src == ep->to_rtx)
3335 else if (GET_CODE (src) == PLUS
3336 && GET_CODE (XEXP (src, 0)) == CONST_INT
3337 && XEXP (src, 1) == ep->to_rtx)
3338 offset = INTVAL (XEXP (src, 0)), ok = 1;
3339 else if (GET_CODE (src) == PLUS
3340 && GET_CODE (XEXP (src, 1)) == CONST_INT
3341 && XEXP (src, 0) == ep->to_rtx)
3342 offset = INTVAL (XEXP (src, 1)), ok = 1;
3343 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
3344 && (prev_set = single_set (prev_insn)) != 0
3345 && rtx_equal_p (SET_DEST (prev_set), src))
3347 src = SET_SRC (prev_set);
3348 if (src == ep->to_rtx)
3350 else if (GET_CODE (src) == PLUS
3351 && GET_CODE (XEXP (src, 0)) == CONST_INT
3352 && XEXP (src, 1) == ep->to_rtx)
3353 offset = INTVAL (XEXP (src, 0)), ok = 1;
3354 else if (GET_CODE (src) == PLUS
3355 && GET_CODE (XEXP (src, 1)) == CONST_INT
3356 && XEXP (src, 0) == ep->to_rtx)
3357 offset = INTVAL (XEXP (src, 1)), ok = 1;
3365 = plus_constant (ep->to_rtx, offset - ep->offset);
3367 /* First see if this insn remains valid when we
3368 make the change. If not, keep the INSN_CODE
3369 the same and let reload fit it up. */
3370 validate_change (insn, &SET_SRC (old_set), src, 1);
3371 validate_change (insn, &SET_DEST (old_set),
3373 if (! apply_change_group ())
3375 SET_SRC (old_set) = src;
3376 SET_DEST (old_set) = ep->to_rtx;
3386 /* In this case this insn isn't serving a useful purpose. We
3387 will delete it in reload_as_needed once we know that this
3388 elimination is, in fact, being done.
3390 If REPLACE isn't set, we can't delete this insn, but needn't
3391 process it since it won't be used unless something changes. */
3394 delete_dead_insn (insn);
3401 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3402 in the insn is the negative of the offset in FROM. Substitute
3403 (set (reg) (reg to)) for the insn and change its code.
3405 We have to do this here, rather than in eliminate_regs, so that we can
3406 change the insn code. */
3408 if (GET_CODE (SET_SRC (old_set)) == PLUS
3409 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3410 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT)
3411 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3413 if (ep->from_rtx == XEXP (SET_SRC (old_set), 0)
3414 && ep->can_eliminate)
3416 /* We must stop at the first elimination that will be used.
3417 If this one would replace the PLUS with a REG, do it
3418 now. Otherwise, quit the loop and let eliminate_regs
3419 do its normal replacement. */
3420 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_set), 1)))
3422 /* We assume here that we don't need a PARALLEL of
3423 any CLOBBERs for this assignment. There's not
3424 much we can do if we do need it. */
3425 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3428 INSN_CODE (insn) = -1;
3437 /* Determine the effects of this insn on elimination offsets. */
3438 elimination_effects (old_body, 0);
3440 /* Eliminate all eliminable registers occurring in operands that
3441 can be handled by reload. */
3442 extract_insn (insn);
3444 for (i = 0; i < recog_data.n_operands; i++)
3446 orig_operand[i] = recog_data.operand[i];
3447 substed_operand[i] = recog_data.operand[i];
3449 /* For an asm statement, every operand is eliminable. */
3450 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3452 /* Check for setting a register that we know about. */
3453 if (recog_data.operand_type[i] != OP_IN
3454 && GET_CODE (orig_operand[i]) == REG)
3456 /* If we are assigning to a register that can be eliminated, it
3457 must be as part of a PARALLEL, since the code above handles
3458 single SETs. We must indicate that we can no longer
3459 eliminate this reg. */
3460 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3462 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3463 ep->can_eliminate = 0;
3466 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3467 replace ? insn : NULL_RTX);
3468 if (substed_operand[i] != orig_operand[i])
3469 val = any_changes = 1;
3470 /* Terminate the search in check_eliminable_occurrences at
3472 *recog_data.operand_loc[i] = 0;
3474 /* If an output operand changed from a REG to a MEM and INSN is an
3475 insn, write a CLOBBER insn. */
3476 if (recog_data.operand_type[i] != OP_IN
3477 && GET_CODE (orig_operand[i]) == REG
3478 && GET_CODE (substed_operand[i]) == MEM
3480 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3485 for (i = 0; i < recog_data.n_dups; i++)
3486 *recog_data.dup_loc[i]
3487 = *recog_data.operand_loc[(int)recog_data.dup_num[i]];
3489 /* If any eliminable remain, they aren't eliminable anymore. */
3490 check_eliminable_occurrences (old_body);
3492 /* Substitute the operands; the new values are in the substed_operand
3494 for (i = 0; i < recog_data.n_operands; i++)
3495 *recog_data.operand_loc[i] = substed_operand[i];
3496 for (i = 0; i < recog_data.n_dups; i++)
3497 *recog_data.dup_loc[i] = substed_operand[(int)recog_data.dup_num[i]];
3499 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3500 re-recognize the insn. We do this in case we had a simple addition
3501 but now can do this as a load-address. This saves an insn in this
3503 If re-recognition fails, the old insn code number will still be used,
3504 and some register operands may have changed into PLUS expressions.
3505 These will be handled by find_reloads by loading them into a register
3510 /* If we aren't replacing things permanently and we changed something,
3511 make another copy to ensure that all the RTL is new. Otherwise
3512 things can go wrong if find_reload swaps commutative operands
3513 and one is inside RTL that has been copied while the other is not. */
3514 new_body = old_body;
3516 new_body = copy_insn (old_body);
3517 PATTERN (insn) = new_body;
3519 /* If we had a move insn but now we don't, rerecognize it. This will
3520 cause spurious re-recognition if the old move had a PARALLEL since
3521 the new one still will, but we can't call single_set without
3522 having put NEW_BODY into the insn and the re-recognition won't
3523 hurt in this rare case. */
3524 /* ??? Why this huge if statement - why don't we just rerecognize the
3528 && ((GET_CODE (SET_SRC (old_set)) == REG
3529 && (GET_CODE (new_body) != SET
3530 || GET_CODE (SET_SRC (new_body)) != REG))
3531 /* If this was a load from or store to memory, compare
3532 the MEM in recog_data.operand to the one in the insn.
3533 If they are not equal, then rerecognize the insn. */
3535 && ((GET_CODE (SET_SRC (old_set)) == MEM
3536 && SET_SRC (old_set) != recog_data.operand[1])
3537 || (GET_CODE (SET_DEST (old_set)) == MEM
3538 && SET_DEST (old_set) != recog_data.operand[0])))
3539 /* If this was an add insn before, rerecognize. */
3540 || GET_CODE (SET_SRC (old_set)) == PLUS))
3542 int new_icode = recog (PATTERN (insn), insn, 0);
3544 INSN_CODE (insn) = icode;
3548 /* Restore the old body. If there were any changes to it, we made a copy
3549 of it while the changes were still in place, so we'll correctly return
3550 a modified insn below. */
3553 /* Restore the old body. */
3554 for (i = 0; i < recog_data.n_operands; i++)
3555 *recog_data.operand_loc[i] = orig_operand[i];
3556 for (i = 0; i < recog_data.n_dups; i++)
3557 *recog_data.dup_loc[i] = orig_operand[(int)recog_data.dup_num[i]];
3560 /* Update all elimination pairs to reflect the status after the current
3561 insn. The changes we make were determined by the earlier call to
3562 elimination_effects.
3564 We also detect a cases where register elimination cannot be done,
3565 namely, if a register would be both changed and referenced outside a MEM
3566 in the resulting insn since such an insn is often undefined and, even if
3567 not, we cannot know what meaning will be given to it. Note that it is
3568 valid to have a register used in an address in an insn that changes it
3569 (presumably with a pre- or post-increment or decrement).
3571 If anything changes, return nonzero. */
3573 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3575 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3576 ep->can_eliminate = 0;
3578 ep->ref_outside_mem = 0;
3580 if (ep->previous_offset != ep->offset)
3585 /* If we changed something, perform elimination in REG_NOTES. This is
3586 needed even when REPLACE is zero because a REG_DEAD note might refer
3587 to a register that we eliminate and could cause a different number
3588 of spill registers to be needed in the final reload pass than in
3590 if (val && REG_NOTES (insn) != 0)
3591 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3599 /* Loop through all elimination pairs.
3600 Recalculate the number not at initial offset.
3602 Compute the maximum offset (minimum offset if the stack does not
3603 grow downward) for each elimination pair. */
3606 update_eliminable_offsets ()
3608 struct elim_table *ep;
3610 num_not_at_initial_offset = 0;
3611 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3613 ep->previous_offset = ep->offset;
3614 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3615 num_not_at_initial_offset++;
3619 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3620 replacement we currently believe is valid, mark it as not eliminable if X
3621 modifies DEST in any way other than by adding a constant integer to it.
3623 If DEST is the frame pointer, we do nothing because we assume that
3624 all assignments to the hard frame pointer are nonlocal gotos and are being
3625 done at a time when they are valid and do not disturb anything else.
3626 Some machines want to eliminate a fake argument pointer with either the
3627 frame or stack pointer. Assignments to the hard frame pointer must not
3628 prevent this elimination.
3630 Called via note_stores from reload before starting its passes to scan
3631 the insns of the function. */
3634 mark_not_eliminable (dest, x)
3638 register unsigned int i;
3640 /* A SUBREG of a hard register here is just changing its mode. We should
3641 not see a SUBREG of an eliminable hard register, but check just in
3643 if (GET_CODE (dest) == SUBREG)
3644 dest = SUBREG_REG (dest);
3646 if (dest == hard_frame_pointer_rtx)
3649 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3650 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3651 && (GET_CODE (x) != SET
3652 || GET_CODE (SET_SRC (x)) != PLUS
3653 || XEXP (SET_SRC (x), 0) != dest
3654 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3656 reg_eliminate[i].can_eliminate_previous
3657 = reg_eliminate[i].can_eliminate = 0;
3662 /* Verify that the initial elimination offsets did not change since the
3663 last call to set_initial_elim_offsets. This is used to catch cases
3664 where something illegal happened during reload_as_needed that could
3665 cause incorrect code to be generated if we did not check for it. */
3667 verify_initial_elim_offsets ()
3671 #ifdef ELIMINABLE_REGS
3672 struct elim_table *ep;
3674 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3676 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3677 if (t != ep->initial_offset)
3681 INITIAL_FRAME_POINTER_OFFSET (t);
3682 if (t != reg_eliminate[0].initial_offset)
3687 /* Reset all offsets on eliminable registers to their initial values. */
3689 set_initial_elim_offsets ()
3691 struct elim_table *ep = reg_eliminate;
3693 #ifdef ELIMINABLE_REGS
3694 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3696 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3697 ep->previous_offset = ep->offset = ep->initial_offset;
3700 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3701 ep->previous_offset = ep->offset = ep->initial_offset;
3704 num_not_at_initial_offset = 0;
3707 /* Initialize the known label offsets.
3708 Set a known offset for each forced label to be at the initial offset
3709 of each elimination. We do this because we assume that all
3710 computed jumps occur from a location where each elimination is
3711 at its initial offset.
3712 For all other labels, show that we don't know the offsets. */
3715 set_initial_label_offsets ()
3718 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
3720 for (x = forced_labels; x; x = XEXP (x, 1))
3722 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3725 /* Set all elimination offsets to the known values for the code label given
3728 set_offsets_for_label (insn)
3732 int label_nr = CODE_LABEL_NUMBER (insn);
3733 struct elim_table *ep;
3735 num_not_at_initial_offset = 0;
3736 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3738 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3739 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3740 num_not_at_initial_offset++;
3744 /* See if anything that happened changes which eliminations are valid.
3745 For example, on the Sparc, whether or not the frame pointer can
3746 be eliminated can depend on what registers have been used. We need
3747 not check some conditions again (such as flag_omit_frame_pointer)
3748 since they can't have changed. */
3751 update_eliminables (pset)
3754 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3755 int previous_frame_pointer_needed = frame_pointer_needed;
3757 struct elim_table *ep;
3759 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3760 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3761 #ifdef ELIMINABLE_REGS
3762 || ! CAN_ELIMINATE (ep->from, ep->to)
3765 ep->can_eliminate = 0;
3767 /* Look for the case where we have discovered that we can't replace
3768 register A with register B and that means that we will now be
3769 trying to replace register A with register C. This means we can
3770 no longer replace register C with register B and we need to disable
3771 such an elimination, if it exists. This occurs often with A == ap,
3772 B == sp, and C == fp. */
3774 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3776 struct elim_table *op;
3777 register int new_to = -1;
3779 if (! ep->can_eliminate && ep->can_eliminate_previous)
3781 /* Find the current elimination for ep->from, if there is a
3783 for (op = reg_eliminate;
3784 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3785 if (op->from == ep->from && op->can_eliminate)
3791 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3793 for (op = reg_eliminate;
3794 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3795 if (op->from == new_to && op->to == ep->to)
3796 op->can_eliminate = 0;
3800 /* See if any registers that we thought we could eliminate the previous
3801 time are no longer eliminable. If so, something has changed and we
3802 must spill the register. Also, recompute the number of eliminable
3803 registers and see if the frame pointer is needed; it is if there is
3804 no elimination of the frame pointer that we can perform. */
3806 frame_pointer_needed = 1;
3807 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3809 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3810 && ep->to != HARD_FRAME_POINTER_REGNUM)
3811 frame_pointer_needed = 0;
3813 if (! ep->can_eliminate && ep->can_eliminate_previous)
3815 ep->can_eliminate_previous = 0;
3816 SET_HARD_REG_BIT (*pset, ep->from);
3821 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3822 /* If we didn't need a frame pointer last time, but we do now, spill
3823 the hard frame pointer. */
3824 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3825 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3829 /* Initialize the table of registers to eliminate. */
3833 struct elim_table *ep;
3834 #ifdef ELIMINABLE_REGS
3835 struct elim_table_1 *ep1;
3839 reg_eliminate = (struct elim_table *)
3840 xcalloc(sizeof(struct elim_table), NUM_ELIMINABLE_REGS);
3842 /* Does this function require a frame pointer? */
3844 frame_pointer_needed = (! flag_omit_frame_pointer
3845 #ifdef EXIT_IGNORE_STACK
3846 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3847 and restore sp for alloca. So we can't eliminate
3848 the frame pointer in that case. At some point,
3849 we should improve this by emitting the
3850 sp-adjusting insns for this case. */
3851 || (current_function_calls_alloca
3852 && EXIT_IGNORE_STACK)
3854 || FRAME_POINTER_REQUIRED);
3858 #ifdef ELIMINABLE_REGS
3859 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3860 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3862 ep->from = ep1->from;
3864 ep->can_eliminate = ep->can_eliminate_previous
3865 = (CAN_ELIMINATE (ep->from, ep->to)
3866 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3869 reg_eliminate[0].from = reg_eliminate_1[0].from;
3870 reg_eliminate[0].to = reg_eliminate_1[0].to;
3871 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3872 = ! frame_pointer_needed;
3875 /* Count the number of eliminable registers and build the FROM and TO
3876 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3877 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3878 We depend on this. */
3879 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3881 num_eliminable += ep->can_eliminate;
3882 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3883 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3887 /* Kick all pseudos out of hard register REGNO.
3888 If DUMPFILE is nonzero, log actions taken on that file.
3890 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3891 because we found we can't eliminate some register. In the case, no pseudos
3892 are allowed to be in the register, even if they are only in a block that
3893 doesn't require spill registers, unlike the case when we are spilling this
3894 hard reg to produce another spill register.
3896 Return nonzero if any pseudos needed to be kicked out. */
3899 spill_hard_reg (regno, dumpfile, cant_eliminate)
3901 FILE *dumpfile ATTRIBUTE_UNUSED;
3908 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3909 regs_ever_live[regno] = 1;
3912 /* Spill every pseudo reg that was allocated to this reg
3913 or to something that overlaps this reg. */
3915 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3916 if (reg_renumber[i] >= 0
3917 && reg_renumber[i] <= regno
3919 + HARD_REGNO_NREGS (reg_renumber[i],
3920 PSEUDO_REGNO_MODE (i))
3922 SET_REGNO_REG_SET (spilled_pseudos, i);
3925 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3926 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3928 ior_hard_reg_set (set1, set2)
3929 HARD_REG_SET *set1, *set2;
3931 IOR_HARD_REG_SET (*set1, *set2);
3934 /* After find_reload_regs has been run for all insn that need reloads,
3935 and/or spill_hard_regs was called, this function is used to actually
3936 spill pseudo registers and try to reallocate them. It also sets up the
3937 spill_regs array for use by choose_reload_regs. */
3940 finish_spills (global, dumpfile)
3944 struct insn_chain *chain;
3945 int something_changed = 0;
3948 /* Build the spill_regs array for the function. */
3949 /* If there are some registers still to eliminate and one of the spill regs
3950 wasn't ever used before, additional stack space may have to be
3951 allocated to store this register. Thus, we may have changed the offset
3952 between the stack and frame pointers, so mark that something has changed.
3954 One might think that we need only set VAL to 1 if this is a call-used
3955 register. However, the set of registers that must be saved by the
3956 prologue is not identical to the call-used set. For example, the
3957 register used by the call insn for the return PC is a call-used register,
3958 but must be saved by the prologue. */
3961 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3962 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3964 spill_reg_order[i] = n_spills;
3965 spill_regs[n_spills++] = i;
3966 if (num_eliminable && ! regs_ever_live[i])
3967 something_changed = 1;
3968 regs_ever_live[i] = 1;
3971 spill_reg_order[i] = -1;
3973 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3974 if (REGNO_REG_SET_P (spilled_pseudos, i))
3976 /* Record the current hard register the pseudo is allocated to in
3977 pseudo_previous_regs so we avoid reallocating it to the same
3978 hard reg in a later pass. */
3979 if (reg_renumber[i] < 0)
3981 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3982 /* Mark it as no longer having a hard register home. */
3983 reg_renumber[i] = -1;
3984 /* We will need to scan everything again. */
3985 something_changed = 1;
3988 /* Retry global register allocation if possible. */
3991 bzero ((char *) pseudo_forbidden_regs, max_regno * sizeof (HARD_REG_SET));
3992 /* For every insn that needs reloads, set the registers used as spill
3993 regs in pseudo_forbidden_regs for every pseudo live across the
3995 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3997 EXECUTE_IF_SET_IN_REG_SET
3998 (chain->live_before, FIRST_PSEUDO_REGISTER, i,
4000 ior_hard_reg_set (pseudo_forbidden_regs + i,
4001 &chain->used_spill_regs);
4003 EXECUTE_IF_SET_IN_REG_SET
4004 (chain->live_after, FIRST_PSEUDO_REGISTER, i,
4006 ior_hard_reg_set (pseudo_forbidden_regs + i,
4007 &chain->used_spill_regs);
4011 /* Retry allocating the spilled pseudos. For each reg, merge the
4012 various reg sets that indicate which hard regs can't be used,
4013 and call retry_global_alloc.
4014 We change spill_pseudos here to only contain pseudos that did not
4015 get a new hard register. */
4016 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4017 if (reg_old_renumber[i] != reg_renumber[i])
4019 HARD_REG_SET forbidden;
4020 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
4021 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
4022 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
4023 retry_global_alloc (i, forbidden);
4024 if (reg_renumber[i] >= 0)
4025 CLEAR_REGNO_REG_SET (spilled_pseudos, i);
4029 /* Fix up the register information in the insn chain.
4030 This involves deleting those of the spilled pseudos which did not get
4031 a new hard register home from the live_{before,after} sets. */
4032 for (chain = reload_insn_chain; chain; chain = chain->next)
4034 HARD_REG_SET used_by_pseudos;
4035 HARD_REG_SET used_by_pseudos2;
4037 AND_COMPL_REG_SET (chain->live_before, spilled_pseudos);
4038 AND_COMPL_REG_SET (chain->live_after, spilled_pseudos);
4040 /* Mark any unallocated hard regs as available for spills. That
4041 makes inheritance work somewhat better. */
4042 if (chain->need_reload)
4044 REG_SET_TO_HARD_REG_SET (used_by_pseudos, chain->live_before);
4045 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, chain->live_after);
4046 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4048 /* Save the old value for the sanity test below. */
4049 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
4051 compute_use_by_pseudos (&used_by_pseudos, chain->live_before);
4052 compute_use_by_pseudos (&used_by_pseudos, chain->live_after);
4053 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4054 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4056 /* Make sure we only enlarge the set. */
4057 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
4063 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4064 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4066 int regno = reg_renumber[i];
4067 if (reg_old_renumber[i] == regno)
4070 alter_reg (i, reg_old_renumber[i]);
4071 reg_old_renumber[i] = regno;
4075 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
4077 fprintf (dumpfile, " Register %d now in %d.\n\n",
4078 i, reg_renumber[i]);
4082 return something_changed;
4085 /* Find all paradoxical subregs within X and update reg_max_ref_width.
4086 Also mark any hard registers used to store user variables as
4087 forbidden from being used for spill registers. */
4090 scan_paradoxical_subregs (x)
4094 register const char *fmt;
4095 register enum rtx_code code = GET_CODE (x);
4101 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
4102 && REG_USERVAR_P (x))
4103 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
4119 if (GET_CODE (SUBREG_REG (x)) == REG
4120 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
4121 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4122 = GET_MODE_SIZE (GET_MODE (x));
4129 fmt = GET_RTX_FORMAT (code);
4130 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4133 scan_paradoxical_subregs (XEXP (x, i));
4134 else if (fmt[i] == 'E')
4137 for (j = XVECLEN (x, i) - 1; j >=0; j--)
4138 scan_paradoxical_subregs (XVECEXP (x, i, j));
4144 hard_reg_use_compare (p1p, p2p)
4148 const struct hard_reg_n_uses *p1 = (const struct hard_reg_n_uses *)p1p;
4149 const struct hard_reg_n_uses *p2 = (const struct hard_reg_n_uses *)p2p;
4150 int bad1 = TEST_HARD_REG_BIT (bad_spill_regs, p1->regno);
4151 int bad2 = TEST_HARD_REG_BIT (bad_spill_regs, p2->regno);
4153 return p1->regno - p2->regno;
4158 if (p1->uses > p2->uses)
4160 if (p1->uses < p2->uses)
4162 /* If regs are equally good, sort by regno,
4163 so that the results of qsort leave nothing to chance. */
4164 return p1->regno - p2->regno;
4167 /* Used for communication between order_regs_for_reload and count_pseudo.
4168 Used to avoid counting one pseudo twice. */
4169 static regset pseudos_counted;
4171 /* Update the costs in N_USES, considering that pseudo REG is live. */
4173 count_pseudo (n_uses, reg)
4174 struct hard_reg_n_uses *n_uses;
4177 int r = reg_renumber[reg];
4180 if (REGNO_REG_SET_P (pseudos_counted, reg))
4182 SET_REGNO_REG_SET (pseudos_counted, reg);
4187 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
4189 n_uses[r++].uses += REG_N_REFS (reg);
4191 /* Choose the order to consider regs for use as reload registers
4192 based on how much trouble would be caused by spilling one.
4193 Store them in order of decreasing preference in potential_reload_regs. */
4196 order_regs_for_reload (chain)
4197 struct insn_chain *chain;
4201 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
4203 pseudos_counted = ALLOCA_REG_SET ();
4205 COPY_HARD_REG_SET (bad_spill_regs, bad_spill_regs_global);
4207 /* Count number of uses of each hard reg by pseudo regs allocated to it
4208 and then order them by decreasing use. */
4210 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4212 hard_reg_n_uses[i].regno = i;
4213 hard_reg_n_uses[i].uses = 0;
4215 /* Test the various reasons why we can't use a register for
4216 spilling in this insn. */
4218 || REGNO_REG_SET_P (chain->live_before, i)
4219 || REGNO_REG_SET_P (chain->live_after, i))
4220 SET_HARD_REG_BIT (bad_spill_regs, i);
4223 /* Now compute hard_reg_n_uses. */
4224 CLEAR_REG_SET (pseudos_counted);
4226 EXECUTE_IF_SET_IN_REG_SET
4227 (chain->live_before, FIRST_PSEUDO_REGISTER, i,
4229 count_pseudo (hard_reg_n_uses, i);
4231 EXECUTE_IF_SET_IN_REG_SET
4232 (chain->live_after, FIRST_PSEUDO_REGISTER, i,
4234 count_pseudo (hard_reg_n_uses, i);
4237 FREE_REG_SET (pseudos_counted);
4239 /* Prefer registers not so far used, for use in temporary loading.
4240 Among them, if REG_ALLOC_ORDER is defined, use that order.
4241 Otherwise, prefer registers not preserved by calls. */
4243 #ifdef REG_ALLOC_ORDER
4244 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4246 int regno = reg_alloc_order[i];
4248 if (hard_reg_n_uses[regno].uses == 0
4249 && ! TEST_HARD_REG_BIT (bad_spill_regs, regno))
4250 potential_reload_regs[o++] = regno;
4253 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4255 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i]
4256 && ! TEST_HARD_REG_BIT (bad_spill_regs, i))
4257 potential_reload_regs[o++] = i;
4259 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4261 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i]
4262 && ! TEST_HARD_REG_BIT (bad_spill_regs, i))
4263 potential_reload_regs[o++] = i;
4267 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
4268 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
4270 /* Now add the regs that are already used,
4271 preferring those used less often. The fixed and otherwise forbidden
4272 registers will be at the end of this list. */
4274 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4275 if (hard_reg_n_uses[i].uses != 0
4276 && ! TEST_HARD_REG_BIT (bad_spill_regs, hard_reg_n_uses[i].regno))
4277 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
4278 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4279 if (TEST_HARD_REG_BIT (bad_spill_regs, hard_reg_n_uses[i].regno))
4280 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
4283 /* Reload pseudo-registers into hard regs around each insn as needed.
4284 Additional register load insns are output before the insn that needs it
4285 and perhaps store insns after insns that modify the reloaded pseudo reg.
4287 reg_last_reload_reg and reg_reloaded_contents keep track of
4288 which registers are already available in reload registers.
4289 We update these for the reloads that we perform,
4290 as the insns are scanned. */
4293 reload_as_needed (live_known)
4296 struct insn_chain *chain;
4297 #if defined (AUTO_INC_DEC) || defined (INSN_CLOBBERS_REGNO_P)
4302 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
4303 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
4304 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
4305 bzero ((char *) reg_last_reload_reg, max_regno * sizeof (rtx));
4306 reg_has_output_reload = (char *) alloca (max_regno);
4307 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4309 set_initial_elim_offsets ();
4311 for (chain = reload_insn_chain; chain; chain = chain->next)
4314 rtx insn = chain->insn;
4315 rtx old_next = NEXT_INSN (insn);
4317 /* If we pass a label, copy the offsets from the label information
4318 into the current offsets of each elimination. */
4319 if (GET_CODE (insn) == CODE_LABEL)
4320 set_offsets_for_label (insn);
4322 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
4324 rtx oldpat = PATTERN (insn);
4326 /* If this is a USE and CLOBBER of a MEM, ensure that any
4327 references to eliminable registers have been removed. */
4329 if ((GET_CODE (PATTERN (insn)) == USE
4330 || GET_CODE (PATTERN (insn)) == CLOBBER)
4331 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
4332 XEXP (XEXP (PATTERN (insn), 0), 0)
4333 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4334 GET_MODE (XEXP (PATTERN (insn), 0)),
4337 /* If we need to do register elimination processing, do so.
4338 This might delete the insn, in which case we are done. */
4339 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4341 eliminate_regs_in_insn (insn, 1);
4342 if (GET_CODE (insn) == NOTE)
4344 update_eliminable_offsets ();
4349 /* If need_elim is nonzero but need_reload is zero, one might think
4350 that we could simply set n_reloads to 0. However, find_reloads
4351 could have done some manipulation of the insn (such as swapping
4352 commutative operands), and these manipulations are lost during
4353 the first pass for every insn that needs register elimination.
4354 So the actions of find_reloads must be redone here. */
4356 if (! chain->need_elim && ! chain->need_reload
4357 && ! chain->need_operand_change)
4359 /* First find the pseudo regs that must be reloaded for this insn.
4360 This info is returned in the tables reload_... (see reload.h).
4361 Also modify the body of INSN by substituting RELOAD
4362 rtx's for those pseudo regs. */
4365 bzero (reg_has_output_reload, max_regno);
4366 CLEAR_HARD_REG_SET (reg_is_output_reload);
4368 find_reloads (insn, 1, spill_indirect_levels, live_known,
4372 if (num_eliminable && chain->need_elim)
4373 update_eliminable_offsets ();
4377 rtx next = NEXT_INSN (insn);
4380 prev = PREV_INSN (insn);
4382 /* Now compute which reload regs to reload them into. Perhaps
4383 reusing reload regs from previous insns, or else output
4384 load insns to reload them. Maybe output store insns too.
4385 Record the choices of reload reg in reload_reg_rtx. */
4386 choose_reload_regs (chain);
4388 /* Merge any reloads that we didn't combine for fear of
4389 increasing the number of spill registers needed but now
4390 discover can be safely merged. */
4391 if (SMALL_REGISTER_CLASSES)
4392 merge_assigned_reloads (insn);
4394 /* Generate the insns to reload operands into or out of
4395 their reload regs. */
4396 emit_reload_insns (chain);
4398 /* Substitute the chosen reload regs from reload_reg_rtx
4399 into the insn's body (or perhaps into the bodies of other
4400 load and store insn that we just made for reloading
4401 and that we moved the structure into). */
4404 /* If this was an ASM, make sure that all the reload insns
4405 we have generated are valid. If not, give an error
4408 if (asm_noperands (PATTERN (insn)) >= 0)
4409 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4410 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
4411 && (recog_memoized (p) < 0
4412 || (extract_insn (p), ! constrain_operands (1))))
4414 error_for_asm (insn,
4415 "`asm' operand requires impossible reload");
4417 NOTE_SOURCE_FILE (p) = 0;
4418 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
4421 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4422 is no longer validly lying around to save a future reload.
4423 Note that this does not detect pseudos that were reloaded
4424 for this insn in order to be stored in
4425 (obeying register constraints). That is correct; such reload
4426 registers ARE still valid. */
4427 note_stores (oldpat, forget_old_reloads_1);
4429 /* There may have been CLOBBER insns placed after INSN. So scan
4430 between INSN and NEXT and use them to forget old reloads. */
4431 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4432 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
4433 note_stores (PATTERN (x), forget_old_reloads_1);
4436 /* Likewise for regs altered by auto-increment in this insn.
4437 REG_INC notes have been changed by reloading:
4438 find_reloads_address_1 records substitutions for them,
4439 which have been performed by subst_reloads above. */
4440 for (i = n_reloads - 1; i >= 0; i--)
4442 rtx in_reg = rld[i].in_reg;
4445 enum rtx_code code = GET_CODE (in_reg);
4446 /* PRE_INC / PRE_DEC will have the reload register ending up
4447 with the same value as the stack slot, but that doesn't
4448 hold true for POST_INC / POST_DEC. Either we have to
4449 convert the memory access to a true POST_INC / POST_DEC,
4450 or we can't use the reload register for inheritance. */
4451 if ((code == POST_INC || code == POST_DEC)
4452 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4453 REGNO (rld[i].reg_rtx))
4454 /* Make sure it is the inc/dec pseudo, and not
4455 some other (e.g. output operand) pseudo. */
4456 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4457 == REGNO (XEXP (in_reg, 0))))
4460 rtx reload_reg = rld[i].reg_rtx;
4461 enum machine_mode mode = GET_MODE (reload_reg);
4465 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4467 /* We really want to ignore REG_INC notes here, so
4468 use PATTERN (p) as argument to reg_set_p . */
4469 if (reg_set_p (reload_reg, PATTERN (p)))
4471 n = count_occurrences (PATTERN (p), reload_reg);
4476 n = validate_replace_rtx (reload_reg,
4477 gen_rtx (code, mode,
4481 /* We must also verify that the constraints
4482 are met after the replacement. */
4485 n = constrain_operands (1);
4489 /* If the constraints were not met, then
4490 undo the replacement. */
4493 validate_replace_rtx (gen_rtx (code, mode,
4505 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4507 /* Mark this as having an output reload so that the
4508 REG_INC processing code below won't invalidate
4509 the reload for inheritance. */
4510 SET_HARD_REG_BIT (reg_is_output_reload,
4511 REGNO (reload_reg));
4512 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4515 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX);
4517 else if ((code == PRE_INC || code == PRE_DEC)
4518 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4519 REGNO (rld[i].reg_rtx))
4520 /* Make sure it is the inc/dec pseudo, and not
4521 some other (e.g. output operand) pseudo. */
4522 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4523 == REGNO (XEXP (in_reg, 0))))
4525 SET_HARD_REG_BIT (reg_is_output_reload,
4526 REGNO (rld[i].reg_rtx));
4527 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4531 /* If a pseudo that got a hard register is auto-incremented,
4532 we must purge records of copying it into pseudos without
4534 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4535 if (REG_NOTE_KIND (x) == REG_INC)
4537 /* See if this pseudo reg was reloaded in this insn.
4538 If so, its last-reload info is still valid
4539 because it is based on this insn's reload. */
4540 for (i = 0; i < n_reloads; i++)
4541 if (rld[i].out == XEXP (x, 0))
4545 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX);
4549 /* A reload reg's contents are unknown after a label. */
4550 if (GET_CODE (insn) == CODE_LABEL)
4551 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4553 /* Don't assume a reload reg is still good after a call insn
4554 if it is a call-used reg. */
4555 else if (GET_CODE (insn) == CALL_INSN)
4556 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
4558 /* In case registers overlap, allow certain insns to invalidate
4559 particular hard registers. */
4561 #ifdef INSN_CLOBBERS_REGNO_P
4562 for (i = 0 ; i < FIRST_PSEUDO_REGISTER; i++)
4563 if (TEST_HARD_REG_BIT (reg_reloaded_valid, i)
4564 && INSN_CLOBBERS_REGNO_P (insn, i))
4565 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i);
4574 /* Discard all record of any value reloaded from X,
4575 or reloaded in X from someplace else;
4576 unless X is an output reload reg of the current insn.
4578 X may be a hard reg (the reload reg)
4579 or it may be a pseudo reg that was reloaded from. */
4582 forget_old_reloads_1 (x, ignored)
4584 rtx ignored ATTRIBUTE_UNUSED;
4590 /* note_stores does give us subregs of hard regs. */
4591 while (GET_CODE (x) == SUBREG)
4593 offset += SUBREG_WORD (x);
4597 if (GET_CODE (x) != REG)
4600 regno = REGNO (x) + offset;
4602 if (regno >= FIRST_PSEUDO_REGISTER)
4607 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4608 /* Storing into a spilled-reg invalidates its contents.
4609 This can happen if a block-local pseudo is allocated to that reg
4610 and it wasn't spilled because this block's total need is 0.
4611 Then some insn might have an optional reload and use this reg. */
4612 for (i = 0; i < nr; i++)
4613 /* But don't do this if the reg actually serves as an output
4614 reload reg in the current instruction. */
4616 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4617 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4620 /* Since value of X has changed,
4621 forget any value previously copied from it. */
4624 /* But don't forget a copy if this is the output reload
4625 that establishes the copy's validity. */
4626 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4627 reg_last_reload_reg[regno + nr] = 0;
4630 /* Comparison function for qsort to decide which of two reloads
4631 should be handled first. *P1 and *P2 are the reload numbers. */
4634 reload_reg_class_lower (r1p, r2p)
4638 register int r1 = *(const short *)r1p, r2 = *(const short *)r2p;
4641 /* Consider required reloads before optional ones. */
4642 t = rld[r1].optional - rld[r2].optional;
4646 /* Count all solitary classes before non-solitary ones. */
4647 t = ((reg_class_size[(int) rld[r2].class] == 1)
4648 - (reg_class_size[(int) rld[r1].class] == 1));
4652 /* Aside from solitaires, consider all multi-reg groups first. */
4653 t = rld[r2].nregs - rld[r1].nregs;
4657 /* Consider reloads in order of increasing reg-class number. */
4658 t = (int) rld[r1].class - (int) rld[r2].class;
4662 /* If reloads are equally urgent, sort by reload number,
4663 so that the results of qsort leave nothing to chance. */
4667 /* The following HARD_REG_SETs indicate when each hard register is
4668 used for a reload of various parts of the current insn. */
4670 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4671 static HARD_REG_SET reload_reg_used;
4672 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4673 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4674 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4675 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4676 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4677 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4678 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4679 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4680 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4681 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4682 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4683 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4684 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4685 static HARD_REG_SET reload_reg_used_in_op_addr;
4686 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4687 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4688 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4689 static HARD_REG_SET reload_reg_used_in_insn;
4690 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4691 static HARD_REG_SET reload_reg_used_in_other_addr;
4693 /* If reg is in use as a reload reg for any sort of reload. */
4694 static HARD_REG_SET reload_reg_used_at_all;
4696 /* If reg is use as an inherited reload. We just mark the first register
4698 static HARD_REG_SET reload_reg_used_for_inherit;
4700 /* Records which hard regs are used in any way, either as explicit use or
4701 by being allocated to a pseudo during any point of the current insn. */
4702 static HARD_REG_SET reg_used_in_insn;
4704 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4705 TYPE. MODE is used to indicate how many consecutive regs are
4709 mark_reload_reg_in_use (regno, opnum, type, mode)
4712 enum reload_type type;
4713 enum machine_mode mode;
4715 int nregs = HARD_REGNO_NREGS (regno, mode);
4718 for (i = regno; i < nregs + regno; i++)
4723 SET_HARD_REG_BIT (reload_reg_used, i);
4726 case RELOAD_FOR_INPUT_ADDRESS:
4727 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4730 case RELOAD_FOR_INPADDR_ADDRESS:
4731 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4734 case RELOAD_FOR_OUTPUT_ADDRESS:
4735 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4738 case RELOAD_FOR_OUTADDR_ADDRESS:
4739 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4742 case RELOAD_FOR_OPERAND_ADDRESS:
4743 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4746 case RELOAD_FOR_OPADDR_ADDR:
4747 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4750 case RELOAD_FOR_OTHER_ADDRESS:
4751 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4754 case RELOAD_FOR_INPUT:
4755 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4758 case RELOAD_FOR_OUTPUT:
4759 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4762 case RELOAD_FOR_INSN:
4763 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4767 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4771 /* Similarly, but show REGNO is no longer in use for a reload. */
4774 clear_reload_reg_in_use (regno, opnum, type, mode)
4777 enum reload_type type;
4778 enum machine_mode mode;
4780 int nregs = HARD_REGNO_NREGS (regno, mode);
4781 int start_regno, end_regno;
4783 /* A complication is that for some reload types, inheritance might
4784 allow multiple reloads of the same types to share a reload register.
4785 We set check_opnum if we have to check only reloads with the same
4786 operand number, and check_any if we have to check all reloads. */
4787 int check_opnum = 0;
4789 HARD_REG_SET *used_in_set;
4794 used_in_set = &reload_reg_used;
4797 case RELOAD_FOR_INPUT_ADDRESS:
4798 used_in_set = &reload_reg_used_in_input_addr[opnum];
4801 case RELOAD_FOR_INPADDR_ADDRESS:
4803 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4806 case RELOAD_FOR_OUTPUT_ADDRESS:
4807 used_in_set = &reload_reg_used_in_output_addr[opnum];
4810 case RELOAD_FOR_OUTADDR_ADDRESS:
4812 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4815 case RELOAD_FOR_OPERAND_ADDRESS:
4816 used_in_set = &reload_reg_used_in_op_addr;
4819 case RELOAD_FOR_OPADDR_ADDR:
4821 used_in_set = &reload_reg_used_in_op_addr_reload;
4824 case RELOAD_FOR_OTHER_ADDRESS:
4825 used_in_set = &reload_reg_used_in_other_addr;
4829 case RELOAD_FOR_INPUT:
4830 used_in_set = &reload_reg_used_in_input[opnum];
4833 case RELOAD_FOR_OUTPUT:
4834 used_in_set = &reload_reg_used_in_output[opnum];
4837 case RELOAD_FOR_INSN:
4838 used_in_set = &reload_reg_used_in_insn;
4843 /* We resolve conflicts with remaining reloads of the same type by
4844 excluding the intervals of of reload registers by them from the
4845 interval of freed reload registers. Since we only keep track of
4846 one set of interval bounds, we might have to exclude somewhat
4847 more then what would be necessary if we used a HARD_REG_SET here.
4848 But this should only happen very infrequently, so there should
4849 be no reason to worry about it. */
4851 start_regno = regno;
4852 end_regno = regno + nregs;
4853 if (check_opnum || check_any)
4855 for (i = n_reloads - 1; i >= 0; i--)
4857 if (rld[i].when_needed == type
4858 && (check_any || rld[i].opnum == opnum)
4861 int conflict_start = true_regnum (rld[i].reg_rtx);
4864 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4866 /* If there is an overlap with the first to-be-freed register,
4867 adjust the interval start. */
4868 if (conflict_start <= start_regno && conflict_end > start_regno)
4869 start_regno = conflict_end;
4870 /* Otherwise, if there is a conflict with one of the other
4871 to-be-freed registers, adjust the interval end. */
4872 if (conflict_start > start_regno && conflict_start < end_regno)
4873 end_regno = conflict_start;
4877 for (i = start_regno; i < end_regno; i++)
4878 CLEAR_HARD_REG_BIT (*used_in_set, i);
4881 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4882 specified by OPNUM and TYPE. */
4885 reload_reg_free_p (regno, opnum, type)
4888 enum reload_type type;
4892 /* In use for a RELOAD_OTHER means it's not available for anything. */
4893 if (TEST_HARD_REG_BIT (reload_reg_used, regno))
4899 /* In use for anything means we can't use it for RELOAD_OTHER. */
4900 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4901 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4902 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4905 for (i = 0; i < reload_n_operands; i++)
4906 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4907 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4908 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4909 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4910 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4911 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4916 case RELOAD_FOR_INPUT:
4917 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4918 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4921 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4924 /* If it is used for some other input, can't use it. */
4925 for (i = 0; i < reload_n_operands; i++)
4926 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4929 /* If it is used in a later operand's address, can't use it. */
4930 for (i = opnum + 1; i < reload_n_operands; i++)
4931 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4932 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4937 case RELOAD_FOR_INPUT_ADDRESS:
4938 /* Can't use a register if it is used for an input address for this
4939 operand or used as an input in an earlier one. */
4940 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4941 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4944 for (i = 0; i < opnum; i++)
4945 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4950 case RELOAD_FOR_INPADDR_ADDRESS:
4951 /* Can't use a register if it is used for an input address
4952 for this operand or used as an input in an earlier
4954 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4957 for (i = 0; i < opnum; i++)
4958 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4963 case RELOAD_FOR_OUTPUT_ADDRESS:
4964 /* Can't use a register if it is used for an output address for this
4965 operand or used as an output in this or a later operand. */
4966 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4969 for (i = opnum; i < reload_n_operands; i++)
4970 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4975 case RELOAD_FOR_OUTADDR_ADDRESS:
4976 /* Can't use a register if it is used for an output address
4977 for this operand or used as an output in this or a
4979 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4982 for (i = opnum; i < reload_n_operands; i++)
4983 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4988 case RELOAD_FOR_OPERAND_ADDRESS:
4989 for (i = 0; i < reload_n_operands; i++)
4990 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4993 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4994 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4996 case RELOAD_FOR_OPADDR_ADDR:
4997 for (i = 0; i < reload_n_operands; i++)
4998 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5001 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
5003 case RELOAD_FOR_OUTPUT:
5004 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5005 outputs, or an operand address for this or an earlier output. */
5006 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5009 for (i = 0; i < reload_n_operands; i++)
5010 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5013 for (i = 0; i <= opnum; i++)
5014 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5015 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5020 case RELOAD_FOR_INSN:
5021 for (i = 0; i < reload_n_operands; i++)
5022 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5023 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5026 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5027 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5029 case RELOAD_FOR_OTHER_ADDRESS:
5030 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
5035 /* Return 1 if the value in reload reg REGNO, as used by a reload
5036 needed for the part of the insn specified by OPNUM and TYPE,
5037 is still available in REGNO at the end of the insn.
5039 We can assume that the reload reg was already tested for availability
5040 at the time it is needed, and we should not check this again,
5041 in case the reg has already been marked in use. */
5044 reload_reg_reaches_end_p (regno, opnum, type)
5047 enum reload_type type;
5054 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5055 its value must reach the end. */
5058 /* If this use is for part of the insn,
5059 its value reaches if no subsequent part uses the same register.
5060 Just like the above function, don't try to do this with lots
5063 case RELOAD_FOR_OTHER_ADDRESS:
5064 /* Here we check for everything else, since these don't conflict
5065 with anything else and everything comes later. */
5067 for (i = 0; i < reload_n_operands; i++)
5068 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5069 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5070 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
5071 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5072 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5073 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5076 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5077 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5078 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5080 case RELOAD_FOR_INPUT_ADDRESS:
5081 case RELOAD_FOR_INPADDR_ADDRESS:
5082 /* Similar, except that we check only for this and subsequent inputs
5083 and the address of only subsequent inputs and we do not need
5084 to check for RELOAD_OTHER objects since they are known not to
5087 for (i = opnum; i < reload_n_operands; i++)
5088 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5091 for (i = opnum + 1; i < reload_n_operands; i++)
5092 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5093 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5096 for (i = 0; i < reload_n_operands; i++)
5097 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5098 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5099 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5102 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5105 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5106 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
5108 case RELOAD_FOR_INPUT:
5109 /* Similar to input address, except we start at the next operand for
5110 both input and input address and we do not check for
5111 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5114 for (i = opnum + 1; i < reload_n_operands; i++)
5115 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5116 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5117 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5120 /* ... fall through ... */
5122 case RELOAD_FOR_OPERAND_ADDRESS:
5123 /* Check outputs and their addresses. */
5125 for (i = 0; i < reload_n_operands; i++)
5126 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5127 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5128 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5133 case RELOAD_FOR_OPADDR_ADDR:
5134 for (i = 0; i < reload_n_operands; i++)
5135 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5136 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5137 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5140 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5141 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
5143 case RELOAD_FOR_INSN:
5144 /* These conflict with other outputs with RELOAD_OTHER. So
5145 we need only check for output addresses. */
5149 /* ... fall through ... */
5151 case RELOAD_FOR_OUTPUT:
5152 case RELOAD_FOR_OUTPUT_ADDRESS:
5153 case RELOAD_FOR_OUTADDR_ADDRESS:
5154 /* We already know these can't conflict with a later output. So the
5155 only thing to check are later output addresses. */
5156 for (i = opnum + 1; i < reload_n_operands; i++)
5157 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5158 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5167 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5170 This function uses the same algorithm as reload_reg_free_p above. */
5173 reloads_conflict (r1, r2)
5176 enum reload_type r1_type = rld[r1].when_needed;
5177 enum reload_type r2_type = rld[r2].when_needed;
5178 int r1_opnum = rld[r1].opnum;
5179 int r2_opnum = rld[r2].opnum;
5181 /* RELOAD_OTHER conflicts with everything. */
5182 if (r2_type == RELOAD_OTHER)
5185 /* Otherwise, check conflicts differently for each type. */
5189 case RELOAD_FOR_INPUT:
5190 return (r2_type == RELOAD_FOR_INSN
5191 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5192 || r2_type == RELOAD_FOR_OPADDR_ADDR
5193 || r2_type == RELOAD_FOR_INPUT
5194 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5195 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5196 && r2_opnum > r1_opnum));
5198 case RELOAD_FOR_INPUT_ADDRESS:
5199 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5200 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5202 case RELOAD_FOR_INPADDR_ADDRESS:
5203 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5204 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5206 case RELOAD_FOR_OUTPUT_ADDRESS:
5207 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5208 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
5210 case RELOAD_FOR_OUTADDR_ADDRESS:
5211 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5212 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
5214 case RELOAD_FOR_OPERAND_ADDRESS:
5215 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5216 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5218 case RELOAD_FOR_OPADDR_ADDR:
5219 return (r2_type == RELOAD_FOR_INPUT
5220 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5222 case RELOAD_FOR_OUTPUT:
5223 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5224 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5225 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5226 && r2_opnum >= r1_opnum));
5228 case RELOAD_FOR_INSN:
5229 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5230 || r2_type == RELOAD_FOR_INSN
5231 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5233 case RELOAD_FOR_OTHER_ADDRESS:
5234 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5244 /* Vector of reload-numbers showing the order in which the reloads should
5246 short reload_order[MAX_RELOADS];
5248 /* Indexed by reload number, 1 if incoming value
5249 inherited from previous insns. */
5250 char reload_inherited[MAX_RELOADS];
5252 /* For an inherited reload, this is the insn the reload was inherited from,
5253 if we know it. Otherwise, this is 0. */
5254 rtx reload_inheritance_insn[MAX_RELOADS];
5256 /* If non-zero, this is a place to get the value of the reload,
5257 rather than using reload_in. */
5258 rtx reload_override_in[MAX_RELOADS];
5260 /* For each reload, the hard register number of the register used,
5261 or -1 if we did not need a register for this reload. */
5262 int reload_spill_index[MAX_RELOADS];
5264 /* Return 1 if the value in reload reg REGNO, as used by a reload
5265 needed for the part of the insn specified by OPNUM and TYPE,
5266 may be used to load VALUE into it.
5268 Other read-only reloads with the same value do not conflict
5269 unless OUT is non-zero and these other reloads have to live while
5270 output reloads live.
5271 If OUT is CONST0_RTX, this is a special case: it means that the
5272 test should not be for using register REGNO as reload register, but
5273 for copying from register REGNO into the reload register.
5275 RELOADNUM is the number of the reload we want to load this value for;
5276 a reload does not conflict with itself.
5278 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5279 reloads that load an address for the very reload we are considering.
5281 The caller has to make sure that there is no conflict with the return
5284 reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum,
5285 ignore_address_reloads)
5288 enum reload_type type;
5291 int ignore_address_reloads;
5297 if (out == const0_rtx)
5303 /* We use some pseudo 'time' value to check if the lifetimes of the
5304 new register use would overlap with the one of a previous reload
5305 that is not read-only or uses a different value.
5306 The 'time' used doesn't have to be linear in any shape or form, just
5308 Some reload types use different 'buckets' for each operand.
5309 So there are MAX_RECOG_OPERANDS different time values for each
5311 We compute TIME1 as the time when the register for the prospective
5312 new reload ceases to be live, and TIME2 for each existing
5313 reload as the time when that the reload register of that reload
5315 Where there is little to be gained by exact lifetime calculations,
5316 we just make conservative assumptions, i.e. a longer lifetime;
5317 this is done in the 'default:' cases. */
5320 case RELOAD_FOR_OTHER_ADDRESS:
5321 /* RELOAD_FOR_OTHER_ADDRESS conflits with RELOAD_OTHER reloads. */
5322 time1 = copy ? 0 : 1;
5325 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5327 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5328 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5329 respectively, to the time values for these, we get distinct time
5330 values. To get distinct time values for each operand, we have to
5331 multiply opnum by at least three. We round that up to four because
5332 multiply by four is often cheaper. */
5333 case RELOAD_FOR_INPADDR_ADDRESS:
5334 time1 = opnum * 4 + 2;
5336 case RELOAD_FOR_INPUT_ADDRESS:
5337 time1 = opnum * 4 + 3;
5339 case RELOAD_FOR_INPUT:
5340 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5341 executes (inclusive). */
5342 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5344 case RELOAD_FOR_OPADDR_ADDR:
5346 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5347 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5349 case RELOAD_FOR_OPERAND_ADDRESS:
5350 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5352 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5354 case RELOAD_FOR_OUTADDR_ADDRESS:
5355 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5357 case RELOAD_FOR_OUTPUT_ADDRESS:
5358 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5361 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5364 for (i = 0; i < n_reloads; i++)
5366 rtx reg = rld[i].reg_rtx;
5367 if (reg && GET_CODE (reg) == REG
5368 && ((unsigned) regno - true_regnum (reg)
5369 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
5372 if (! rld[i].in || ! rtx_equal_p (rld[i].in, value)
5373 || rld[i].out || out)
5376 switch (rld[i].when_needed)
5378 case RELOAD_FOR_OTHER_ADDRESS:
5381 case RELOAD_FOR_INPADDR_ADDRESS:
5382 /* find_reloads makes sure that a
5383 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5384 by at most one - the first -
5385 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5386 address reload is inherited, the address address reload
5387 goes away, so we can ignore this conflict. */
5388 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5389 && ignore_address_reloads
5390 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5391 Then the address address is still needed to store
5392 back the new address. */
5393 && ! rld[reloadnum].out)
5395 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5396 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5398 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5399 && ignore_address_reloads
5400 /* Unless we are reloading an auto_inc expression. */
5401 && ! rld[reloadnum].out)
5403 time2 = rld[i].opnum * 4 + 2;
5405 case RELOAD_FOR_INPUT_ADDRESS:
5406 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5407 && ignore_address_reloads
5408 && ! rld[reloadnum].out)
5410 time2 = rld[i].opnum * 4 + 3;
5412 case RELOAD_FOR_INPUT:
5413 time2 = rld[i].opnum * 4 + 4;
5415 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5416 == MAX_RECOG_OPERAND * 4 */
5417 case RELOAD_FOR_OPADDR_ADDR:
5418 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5419 && ignore_address_reloads
5420 && ! rld[reloadnum].out)
5422 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5424 case RELOAD_FOR_OPERAND_ADDRESS:
5425 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5427 case RELOAD_FOR_INSN:
5428 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5430 case RELOAD_FOR_OUTPUT:
5431 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5432 instruction is executed. */
5433 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5435 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5436 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5438 case RELOAD_FOR_OUTADDR_ADDRESS:
5439 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5440 && ignore_address_reloads
5441 && ! rld[reloadnum].out)
5443 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5445 case RELOAD_FOR_OUTPUT_ADDRESS:
5446 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5449 /* If there is no conflict in the input part, handle this
5450 like an output reload. */
5451 if (! rld[i].in || rtx_equal_p (rld[i].in, value))
5453 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5454 /* Earlyclobbered outputs must conflict with inputs. */
5455 for (j = 0; j < n_earlyclobbers; j++)
5456 if (rld[i].out == reload_earlyclobbers[j])
5457 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5462 /* RELOAD_OTHER might be live beyond instruction execution,
5463 but this is not obvious when we set time2 = 1. So check
5464 here if there might be a problem with the new reload
5465 clobbering the register used by the RELOAD_OTHER. */
5473 && (! rld[i].in || rld[i].out
5474 || ! rtx_equal_p (rld[i].in, value)))
5475 || (out && rld[reloadnum].out_reg
5476 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5484 /* Give an error message saying we failed to find a reload for INSN,
5485 and clear out reload R. */
5487 failed_reload (insn, r)
5491 if (asm_noperands (PATTERN (insn)) < 0)
5492 /* It's the compiler's fault. */
5493 fatal_insn ("Could not find a spill register", insn);
5495 /* It's the user's fault; the operand's mode and constraint
5496 don't match. Disable this reload so we don't crash in final. */
5497 error_for_asm (insn,
5498 "`asm' operand constraint incompatible with operand size");
5502 rld[r].optional = 1;
5503 rld[r].secondary_p = 1;
5506 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5507 for reload R. If it's valid, get an rtx for it. Return nonzero if
5510 set_reload_reg (i, r)
5514 rtx reg = spill_reg_rtx[i];
5516 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5517 spill_reg_rtx[i] = reg
5518 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5520 regno = true_regnum (reg);
5522 /* Detect when the reload reg can't hold the reload mode.
5523 This used to be one `if', but Sequent compiler can't handle that. */
5524 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5526 enum machine_mode test_mode = VOIDmode;
5528 test_mode = GET_MODE (rld[r].in);
5529 /* If rld[r].in has VOIDmode, it means we will load it
5530 in whatever mode the reload reg has: to wit, rld[r].mode.
5531 We have already tested that for validity. */
5532 /* Aside from that, we need to test that the expressions
5533 to reload from or into have modes which are valid for this
5534 reload register. Otherwise the reload insns would be invalid. */
5535 if (! (rld[r].in != 0 && test_mode != VOIDmode
5536 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5537 if (! (rld[r].out != 0
5538 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5540 /* The reg is OK. */
5543 /* Mark as in use for this insn the reload regs we use
5545 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5546 rld[r].when_needed, rld[r].mode);
5548 rld[r].reg_rtx = reg;
5549 reload_spill_index[r] = spill_regs[i];
5556 /* Find a spill register to use as a reload register for reload R.
5557 LAST_RELOAD is non-zero if this is the last reload for the insn being
5560 Set rld[R].reg_rtx to the register allocated.
5562 If NOERROR is nonzero, we return 1 if successful,
5563 or 0 if we couldn't find a spill reg and we didn't change anything. */
5566 allocate_reload_reg (chain, r, last_reload, noerror)
5567 struct insn_chain *chain;
5572 rtx insn = chain->insn;
5575 /* If we put this reload ahead, thinking it is a group,
5576 then insist on finding a group. Otherwise we can grab a
5577 reg that some other reload needs.
5578 (That can happen when we have a 68000 DATA_OR_FP_REG
5579 which is a group of data regs or one fp reg.)
5580 We need not be so restrictive if there are no more reloads
5583 ??? Really it would be nicer to have smarter handling
5584 for that kind of reg class, where a problem like this is normal.
5585 Perhaps those classes should be avoided for reloading
5586 by use of more alternatives. */
5588 int force_group = rld[r].nregs > 1 && ! last_reload;
5590 /* If we want a single register and haven't yet found one,
5591 take any reg in the right class and not in use.
5592 If we want a consecutive group, here is where we look for it.
5594 We use two passes so we can first look for reload regs to
5595 reuse, which are already in use for other reloads in this insn,
5596 and only then use additional registers.
5597 I think that maximizing reuse is needed to make sure we don't
5598 run out of reload regs. Suppose we have three reloads, and
5599 reloads A and B can share regs. These need two regs.
5600 Suppose A and B are given different regs.
5601 That leaves none for C. */
5602 for (pass = 0; pass < 2; pass++)
5604 /* I is the index in spill_regs.
5605 We advance it round-robin between insns to use all spill regs
5606 equally, so that inherited reloads have a chance
5607 of leapfrogging each other. Don't do this, however, when we have
5608 group needs and failure would be fatal; if we only have a relatively
5609 small number of spill registers, and more than one of them has
5610 group needs, then by starting in the middle, we may end up
5611 allocating the first one in such a way that we are not left with
5612 sufficient groups to handle the rest. */
5614 if (noerror || ! force_group)
5619 for (count = 0; count < n_spills; count++)
5621 int class = (int) rld[r].class;
5627 regnum = spill_regs[i];
5629 if ((reload_reg_free_p (regnum, rld[r].opnum,
5632 /* We check reload_reg_used to make sure we
5633 don't clobber the return register. */
5634 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5635 && reload_reg_free_for_value_p (regnum,
5640 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5641 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5642 /* Look first for regs to share, then for unshared. But
5643 don't share regs used for inherited reloads; they are
5644 the ones we want to preserve. */
5646 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5648 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5651 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5652 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5653 (on 68000) got us two FP regs. If NR is 1,
5654 we would reject both of them. */
5657 /* If we need only one reg, we have already won. */
5660 /* But reject a single reg if we demand a group. */
5665 /* Otherwise check that as many consecutive regs as we need
5667 Also, don't use for a group registers that are
5668 needed for nongroups. */
5669 if (! TEST_HARD_REG_BIT (chain->counted_for_nongroups, regnum))
5672 int regno = regnum + nr - 1;
5673 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5674 && spill_reg_order[regno] >= 0
5675 && reload_reg_free_p (regno, rld[r].opnum,
5677 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups,
5687 /* If we found something on pass 1, omit pass 2. */
5688 if (count < n_spills)
5692 /* We should have found a spill register by now. */
5693 if (count == n_spills)
5700 if (set_reload_reg (i, r))
5703 /* The reg is not OK. */
5708 failed_reload (insn, r);
5713 /* Initialize all the tables needed to allocate reload registers.
5714 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5715 is the array we use to restore the reg_rtx field for every reload. */
5717 choose_reload_regs_init (chain, save_reload_reg_rtx)
5718 struct insn_chain *chain;
5719 rtx *save_reload_reg_rtx;
5723 for (i = 0; i < n_reloads; i++)
5724 rld[i].reg_rtx = save_reload_reg_rtx[i];
5726 bzero (reload_inherited, MAX_RELOADS);
5727 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5728 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5730 CLEAR_HARD_REG_SET (reload_reg_used);
5731 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5732 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5733 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5734 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5735 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5737 CLEAR_HARD_REG_SET (reg_used_in_insn);
5740 REG_SET_TO_HARD_REG_SET (tmp, chain->live_before);
5741 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5742 REG_SET_TO_HARD_REG_SET (tmp, chain->live_after);
5743 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5744 compute_use_by_pseudos (®_used_in_insn, chain->live_before);
5745 compute_use_by_pseudos (®_used_in_insn, chain->live_after);
5747 for (i = 0; i < reload_n_operands; i++)
5749 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5750 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5751 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5752 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5753 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5754 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5757 IOR_COMPL_HARD_REG_SET (reload_reg_used, chain->used_spill_regs);
5759 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5761 for (i = 0; i < n_reloads; i++)
5762 /* If we have already decided to use a certain register,
5763 don't use it in another way. */
5765 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5766 rld[i].when_needed, rld[i].mode);
5769 /* Assign hard reg targets for the pseudo-registers we must reload
5770 into hard regs for this insn.
5771 Also output the instructions to copy them in and out of the hard regs.
5773 For machines with register classes, we are responsible for
5774 finding a reload reg in the proper class. */
5777 choose_reload_regs (chain)
5778 struct insn_chain *chain;
5780 rtx insn = chain->insn;
5782 int max_group_size = 1;
5783 enum reg_class group_class = NO_REGS;
5787 rtx save_reload_reg_rtx[MAX_RELOADS];
5789 /* In order to be certain of getting the registers we need,
5790 we must sort the reloads into order of increasing register class.
5791 Then our grabbing of reload registers will parallel the process
5792 that provided the reload registers.
5794 Also note whether any of the reloads wants a consecutive group of regs.
5795 If so, record the maximum size of the group desired and what
5796 register class contains all the groups needed by this insn. */
5798 for (j = 0; j < n_reloads; j++)
5800 reload_order[j] = j;
5801 reload_spill_index[j] = -1;
5803 if (rld[j].nregs > 1)
5805 max_group_size = MAX (rld[j].nregs, max_group_size);
5806 group_class = reg_class_superunion[(int)rld[j].class][(int)group_class];
5809 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5813 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5815 /* If -O, try first with inheritance, then turning it off.
5816 If not -O, don't do inheritance.
5817 Using inheritance when not optimizing leads to paradoxes
5818 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5819 because one side of the comparison might be inherited. */
5821 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5823 choose_reload_regs_init (chain, save_reload_reg_rtx);
5825 /* Process the reloads in order of preference just found.
5826 Beyond this point, subregs can be found in reload_reg_rtx.
5828 This used to look for an existing reloaded home for all
5829 of the reloads, and only then perform any new reloads.
5830 But that could lose if the reloads were done out of reg-class order
5831 because a later reload with a looser constraint might have an old
5832 home in a register needed by an earlier reload with a tighter constraint.
5834 To solve this, we make two passes over the reloads, in the order
5835 described above. In the first pass we try to inherit a reload
5836 from a previous insn. If there is a later reload that needs a
5837 class that is a proper subset of the class being processed, we must
5838 also allocate a spill register during the first pass.
5840 Then make a second pass over the reloads to allocate any reloads
5841 that haven't been given registers yet. */
5843 for (j = 0; j < n_reloads; j++)
5845 register int r = reload_order[j];
5846 rtx search_equiv = NULL_RTX;
5848 /* Ignore reloads that got marked inoperative. */
5849 if (rld[r].out == 0 && rld[r].in == 0
5850 && ! rld[r].secondary_p)
5853 /* If find_reloads chose to use reload_in or reload_out as a reload
5854 register, we don't need to chose one. Otherwise, try even if it
5855 found one since we might save an insn if we find the value lying
5857 Try also when reload_in is a pseudo without a hard reg. */
5858 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5859 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5860 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5861 && GET_CODE (rld[r].in) != MEM
5862 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5865 #if 0 /* No longer needed for correct operation.
5866 It might give better code, or might not; worth an experiment? */
5867 /* If this is an optional reload, we can't inherit from earlier insns
5868 until we are sure that any non-optional reloads have been allocated.
5869 The following code takes advantage of the fact that optional reloads
5870 are at the end of reload_order. */
5871 if (rld[r].optional != 0)
5872 for (i = 0; i < j; i++)
5873 if ((rld[reload_order[i]].out != 0
5874 || rld[reload_order[i]].in != 0
5875 || rld[reload_order[i]].secondary_p)
5876 && ! rld[reload_order[i]].optional
5877 && rld[reload_order[i]].reg_rtx == 0)
5878 allocate_reload_reg (chain, reload_order[i], 0, inheritance);
5881 /* First see if this pseudo is already available as reloaded
5882 for a previous insn. We cannot try to inherit for reloads
5883 that are smaller than the maximum number of registers needed
5884 for groups unless the register we would allocate cannot be used
5887 We could check here to see if this is a secondary reload for
5888 an object that is already in a register of the desired class.
5889 This would avoid the need for the secondary reload register.
5890 But this is complex because we can't easily determine what
5891 objects might want to be loaded via this reload. So let a
5892 register be allocated here. In `emit_reload_insns' we suppress
5893 one of the loads in the case described above. */
5898 register int regno = -1;
5899 enum machine_mode mode = VOIDmode;
5903 else if (GET_CODE (rld[r].in) == REG)
5905 regno = REGNO (rld[r].in);
5906 mode = GET_MODE (rld[r].in);
5908 else if (GET_CODE (rld[r].in_reg) == REG)
5910 regno = REGNO (rld[r].in_reg);
5911 mode = GET_MODE (rld[r].in_reg);
5913 else if (GET_CODE (rld[r].in_reg) == SUBREG
5914 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5916 word = SUBREG_WORD (rld[r].in_reg);
5917 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5918 if (regno < FIRST_PSEUDO_REGISTER)
5920 mode = GET_MODE (rld[r].in_reg);
5923 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5924 || GET_CODE (rld[r].in_reg) == PRE_DEC
5925 || GET_CODE (rld[r].in_reg) == POST_INC
5926 || GET_CODE (rld[r].in_reg) == POST_DEC)
5927 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5929 regno = REGNO (XEXP (rld[r].in_reg, 0));
5930 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5931 rld[r].out = rld[r].in;
5935 /* This won't work, since REGNO can be a pseudo reg number.
5936 Also, it takes much more hair to keep track of all the things
5937 that can invalidate an inherited reload of part of a pseudoreg. */
5938 else if (GET_CODE (rld[r].in) == SUBREG
5939 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5940 regno = REGNO (SUBREG_REG (rld[r].in)) + SUBREG_WORD (rld[r].in);
5943 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5945 enum reg_class class = rld[r].class, last_class;
5946 rtx last_reg = reg_last_reload_reg[regno];
5948 i = REGNO (last_reg) + word;
5949 last_class = REGNO_REG_CLASS (i);
5950 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5951 >= GET_MODE_SIZE (mode) + word * UNITS_PER_WORD)
5952 && reg_reloaded_contents[i] == regno
5953 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5954 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5955 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5956 /* Even if we can't use this register as a reload
5957 register, we might use it for reload_override_in,
5958 if copying it to the desired class is cheap
5960 || ((REGISTER_MOVE_COST (last_class, class)
5961 < MEMORY_MOVE_COST (mode, class, 1))
5962 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5963 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5967 #ifdef SECONDARY_MEMORY_NEEDED
5968 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5973 && (rld[r].nregs == max_group_size
5974 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5976 && reload_reg_free_for_value_p (i, rld[r].opnum,
5981 /* If a group is needed, verify that all the subsequent
5982 registers still have their values intact. */
5984 = HARD_REGNO_NREGS (i, rld[r].mode);
5987 for (k = 1; k < nr; k++)
5988 if (reg_reloaded_contents[i + k] != regno
5989 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5996 last_reg = (GET_MODE (last_reg) == mode
5997 ? last_reg : gen_rtx_REG (mode, i));
5999 /* We found a register that contains the
6000 value we need. If this register is the
6001 same as an `earlyclobber' operand of the
6002 current insn, just mark it as a place to
6003 reload from since we can't use it as the
6004 reload register itself. */
6006 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6007 if (reg_overlap_mentioned_for_reload_p
6008 (reg_last_reload_reg[regno],
6009 reload_earlyclobbers[i1]))
6012 if (i1 != n_earlyclobbers
6013 || ! (reload_reg_free_for_value_p
6014 (i, rld[r].opnum, rld[r].when_needed,
6015 rld[r].in, rld[r].out, r, 1))
6016 /* Don't use it if we'd clobber a pseudo reg. */
6017 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6019 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6020 /* Don't clobber the frame pointer. */
6021 || (i == HARD_FRAME_POINTER_REGNUM && rld[r].out)
6022 /* Don't really use the inherited spill reg
6023 if we need it wider than we've got it. */
6024 || (GET_MODE_SIZE (rld[r].mode)
6025 > GET_MODE_SIZE (mode))
6026 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
6029 /* If find_reloads chose reload_out as reload
6030 register, stay with it - that leaves the
6031 inherited register for subsequent reloads. */
6032 || (rld[r].out && rld[r].reg_rtx
6033 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6035 reload_override_in[r] = last_reg;
6036 reload_inheritance_insn[r]
6037 = reg_reloaded_insn[i];
6042 /* We can use this as a reload reg. */
6043 /* Mark the register as in use for this part of
6045 mark_reload_reg_in_use (i,
6049 rld[r].reg_rtx = last_reg;
6050 reload_inherited[r] = 1;
6051 reload_inheritance_insn[r]
6052 = reg_reloaded_insn[i];
6053 reload_spill_index[r] = i;
6054 for (k = 0; k < nr; k++)
6055 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6063 /* Here's another way to see if the value is already lying around. */
6066 && ! reload_inherited[r]
6068 && (CONSTANT_P (rld[r].in)
6069 || GET_CODE (rld[r].in) == PLUS
6070 || GET_CODE (rld[r].in) == REG
6071 || GET_CODE (rld[r].in) == MEM)
6072 && (rld[r].nregs == max_group_size
6073 || ! reg_classes_intersect_p (rld[r].class, group_class)))
6074 search_equiv = rld[r].in;
6075 /* If this is an output reload from a simple move insn, look
6076 if an equivalence for the input is available. */
6077 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
6079 rtx set = single_set (insn);
6082 && rtx_equal_p (rld[r].out, SET_DEST (set))
6083 && CONSTANT_P (SET_SRC (set)))
6084 search_equiv = SET_SRC (set);
6090 = find_equiv_reg (search_equiv, insn, rld[r].class,
6091 -1, NULL_PTR, 0, rld[r].mode);
6096 if (GET_CODE (equiv) == REG)
6097 regno = REGNO (equiv);
6098 else if (GET_CODE (equiv) == SUBREG)
6100 /* This must be a SUBREG of a hard register.
6101 Make a new REG since this might be used in an
6102 address and not all machines support SUBREGs
6104 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
6105 equiv = gen_rtx_REG (rld[r].mode, regno);
6111 /* If we found a spill reg, reject it unless it is free
6112 and of the desired class. */
6114 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
6115 && ! reload_reg_free_for_value_p (regno, rld[r].opnum,
6119 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
6123 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6126 /* We found a register that contains the value we need.
6127 If this register is the same as an `earlyclobber' operand
6128 of the current insn, just mark it as a place to reload from
6129 since we can't use it as the reload register itself. */
6132 for (i = 0; i < n_earlyclobbers; i++)
6133 if (reg_overlap_mentioned_for_reload_p (equiv,
6134 reload_earlyclobbers[i]))
6136 reload_override_in[r] = equiv;
6141 /* If the equiv register we have found is explicitly clobbered
6142 in the current insn, it depends on the reload type if we
6143 can use it, use it for reload_override_in, or not at all.
6144 In particular, we then can't use EQUIV for a
6145 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6147 if (equiv != 0 && regno_clobbered_p (regno, insn))
6149 switch (rld[r].when_needed)
6151 case RELOAD_FOR_OTHER_ADDRESS:
6152 case RELOAD_FOR_INPADDR_ADDRESS:
6153 case RELOAD_FOR_INPUT_ADDRESS:
6154 case RELOAD_FOR_OPADDR_ADDR:
6157 case RELOAD_FOR_INPUT:
6158 case RELOAD_FOR_OPERAND_ADDRESS:
6159 reload_override_in[r] = equiv;
6167 /* If we found an equivalent reg, say no code need be generated
6168 to load it, and use it as our reload reg. */
6169 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
6171 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
6173 rld[r].reg_rtx = equiv;
6174 reload_inherited[r] = 1;
6176 /* If reg_reloaded_valid is not set for this register,
6177 there might be a stale spill_reg_store lying around.
6178 We must clear it, since otherwise emit_reload_insns
6179 might delete the store. */
6180 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6181 spill_reg_store[regno] = NULL_RTX;
6182 /* If any of the hard registers in EQUIV are spill
6183 registers, mark them as in use for this insn. */
6184 for (k = 0; k < nr; k++)
6186 i = spill_reg_order[regno + k];
6189 mark_reload_reg_in_use (regno, rld[r].opnum,
6192 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6199 /* If we found a register to use already, or if this is an optional
6200 reload, we are done. */
6201 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6204 #if 0 /* No longer needed for correct operation. Might or might not
6205 give better code on the average. Want to experiment? */
6207 /* See if there is a later reload that has a class different from our
6208 class that intersects our class or that requires less register
6209 than our reload. If so, we must allocate a register to this
6210 reload now, since that reload might inherit a previous reload
6211 and take the only available register in our class. Don't do this
6212 for optional reloads since they will force all previous reloads
6213 to be allocated. Also don't do this for reloads that have been
6216 for (i = j + 1; i < n_reloads; i++)
6218 int s = reload_order[i];
6220 if ((rld[s].in == 0 && rld[s].out == 0
6221 && ! rld[s].secondary_p)
6225 if ((rld[s].class != rld[r].class
6226 && reg_classes_intersect_p (rld[r].class,
6228 || rld[s].nregs < rld[r].nregs)
6235 allocate_reload_reg (chain, r, j == n_reloads - 1, inheritance);
6239 /* Now allocate reload registers for anything non-optional that
6240 didn't get one yet. */
6241 for (j = 0; j < n_reloads; j++)
6243 register int r = reload_order[j];
6245 /* Ignore reloads that got marked inoperative. */
6246 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6249 /* Skip reloads that already have a register allocated or are
6251 if (rld[r].reg_rtx != 0 || rld[r].optional)
6254 if (! allocate_reload_reg (chain, r, j == n_reloads - 1, inheritance))
6258 /* If that loop got all the way, we have won. */
6262 /* Loop around and try without any inheritance. */
6265 /* If we thought we could inherit a reload, because it seemed that
6266 nothing else wanted the same reload register earlier in the insn,
6267 verify that assumption, now that all reloads have been assigned.
6268 Likewise for reloads where reload_override_in has been set. */
6270 /* If doing expensive optimizations, do one preliminary pass that doesn't
6271 cancel any inheritance, but removes reloads that have been needed only
6272 for reloads that we know can be inherited. */
6273 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6275 for (j = 0; j < n_reloads; j++)
6277 register int r = reload_order[j];
6279 if (reload_inherited[r] && rld[r].reg_rtx)
6280 check_reg = rld[r].reg_rtx;
6281 else if (reload_override_in[r]
6282 && (GET_CODE (reload_override_in[r]) == REG
6283 || GET_CODE (reload_override_in[r]) == SUBREG))
6284 check_reg = reload_override_in[r];
6287 if (! reload_reg_free_for_value_p (true_regnum (check_reg),
6291 (reload_inherited[r]
6292 ? rld[r].out : const0_rtx),
6297 reload_inherited[r] = 0;
6298 reload_override_in[r] = 0;
6300 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6301 reload_override_in, then we do not need its related
6302 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6303 likewise for other reload types.
6304 We handle this by removing a reload when its only replacement
6305 is mentioned in reload_in of the reload we are going to inherit.
6306 A special case are auto_inc expressions; even if the input is
6307 inherited, we still need the address for the output. We can
6308 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6309 If we suceeded removing some reload and we are doing a preliminary
6310 pass just to remove such reloads, make another pass, since the
6311 removal of one reload might allow us to inherit another one. */
6313 && rld[r].out != rld[r].in
6314 && remove_address_replacements (rld[r].in) && pass)
6319 /* Now that reload_override_in is known valid,
6320 actually override reload_in. */
6321 for (j = 0; j < n_reloads; j++)
6322 if (reload_override_in[j])
6323 rld[j].in = reload_override_in[j];
6325 /* If this reload won't be done because it has been cancelled or is
6326 optional and not inherited, clear reload_reg_rtx so other
6327 routines (such as subst_reloads) don't get confused. */
6328 for (j = 0; j < n_reloads; j++)
6329 if (rld[j].reg_rtx != 0
6330 && ((rld[j].optional && ! reload_inherited[j])
6331 || (rld[j].in == 0 && rld[j].out == 0
6332 && ! rld[j].secondary_p)))
6334 int regno = true_regnum (rld[j].reg_rtx);
6336 if (spill_reg_order[regno] >= 0)
6337 clear_reload_reg_in_use (regno, rld[j].opnum,
6338 rld[j].when_needed, rld[j].mode);
6342 /* Record which pseudos and which spill regs have output reloads. */
6343 for (j = 0; j < n_reloads; j++)
6345 register int r = reload_order[j];
6347 i = reload_spill_index[r];
6349 /* I is nonneg if this reload uses a register.
6350 If rld[r].reg_rtx is 0, this is an optional reload
6351 that we opted to ignore. */
6352 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
6353 && rld[r].reg_rtx != 0)
6355 register int nregno = REGNO (rld[r].out_reg);
6358 if (nregno < FIRST_PSEUDO_REGISTER)
6359 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
6362 reg_has_output_reload[nregno + nr] = 1;
6366 nr = HARD_REGNO_NREGS (i, rld[r].mode);
6368 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6371 if (rld[r].when_needed != RELOAD_OTHER
6372 && rld[r].when_needed != RELOAD_FOR_OUTPUT
6373 && rld[r].when_needed != RELOAD_FOR_INSN)
6379 /* Deallocate the reload register for reload R. This is called from
6380 remove_address_replacements. */
6382 deallocate_reload_reg (r)
6387 if (! rld[r].reg_rtx)
6389 regno = true_regnum (rld[r].reg_rtx);
6391 if (spill_reg_order[regno] >= 0)
6392 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6394 reload_spill_index[r] = -1;
6397 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
6398 reloads of the same item for fear that we might not have enough reload
6399 registers. However, normally they will get the same reload register
6400 and hence actually need not be loaded twice.
6402 Here we check for the most common case of this phenomenon: when we have
6403 a number of reloads for the same object, each of which were allocated
6404 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6405 reload, and is not modified in the insn itself. If we find such,
6406 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6407 This will not increase the number of spill registers needed and will
6408 prevent redundant code. */
6411 merge_assigned_reloads (insn)
6416 /* Scan all the reloads looking for ones that only load values and
6417 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6418 assigned and not modified by INSN. */
6420 for (i = 0; i < n_reloads; i++)
6422 int conflicting_input = 0;
6423 int max_input_address_opnum = -1;
6424 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6426 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6427 || rld[i].out != 0 || rld[i].reg_rtx == 0
6428 || reg_set_p (rld[i].reg_rtx, insn))
6431 /* Look at all other reloads. Ensure that the only use of this
6432 reload_reg_rtx is in a reload that just loads the same value
6433 as we do. Note that any secondary reloads must be of the identical
6434 class since the values, modes, and result registers are the
6435 same, so we need not do anything with any secondary reloads. */
6437 for (j = 0; j < n_reloads; j++)
6439 if (i == j || rld[j].reg_rtx == 0
6440 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6444 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6445 && rld[j].opnum > max_input_address_opnum)
6446 max_input_address_opnum = rld[j].opnum;
6448 /* If the reload regs aren't exactly the same (e.g, different modes)
6449 or if the values are different, we can't merge this reload.
6450 But if it is an input reload, we might still merge
6451 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6453 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6454 || rld[j].out != 0 || rld[j].in == 0
6455 || ! rtx_equal_p (rld[i].in, rld[j].in))
6457 if (rld[j].when_needed != RELOAD_FOR_INPUT
6458 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6459 || rld[i].opnum > rld[j].opnum)
6460 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6462 conflicting_input = 1;
6463 if (min_conflicting_input_opnum > rld[j].opnum)
6464 min_conflicting_input_opnum = rld[j].opnum;
6468 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6469 we, in fact, found any matching reloads. */
6472 && max_input_address_opnum <= min_conflicting_input_opnum)
6474 for (j = 0; j < n_reloads; j++)
6475 if (i != j && rld[j].reg_rtx != 0
6476 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6477 && (! conflicting_input
6478 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6479 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6481 rld[i].when_needed = RELOAD_OTHER;
6483 reload_spill_index[j] = -1;
6484 transfer_replacements (i, j);
6487 /* If this is now RELOAD_OTHER, look for any reloads that load
6488 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6489 if they were for inputs, RELOAD_OTHER for outputs. Note that
6490 this test is equivalent to looking for reloads for this operand
6493 if (rld[i].when_needed == RELOAD_OTHER)
6494 for (j = 0; j < n_reloads; j++)
6496 && rld[i].when_needed != RELOAD_OTHER
6497 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6500 = ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
6501 || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6502 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6508 /* Output insns to reload values in and out of the chosen reload regs. */
6511 emit_reload_insns (chain)
6512 struct insn_chain *chain;
6514 rtx insn = chain->insn;
6517 rtx input_reload_insns[MAX_RECOG_OPERANDS];
6518 rtx other_input_address_reload_insns = 0;
6519 rtx other_input_reload_insns = 0;
6520 rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6521 rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6522 rtx output_reload_insns[MAX_RECOG_OPERANDS];
6523 rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6524 rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6525 rtx operand_reload_insns = 0;
6526 rtx other_operand_reload_insns = 0;
6527 rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6528 rtx following_insn = NEXT_INSN (insn);
6529 rtx before_insn = PREV_INSN (insn);
6531 /* Values to be put in spill_reg_store are put here first. */
6532 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6533 HARD_REG_SET reg_reloaded_died;
6535 CLEAR_HARD_REG_SET (reg_reloaded_died);
6537 for (j = 0; j < reload_n_operands; j++)
6538 input_reload_insns[j] = input_address_reload_insns[j]
6539 = inpaddr_address_reload_insns[j]
6540 = output_reload_insns[j] = output_address_reload_insns[j]
6541 = outaddr_address_reload_insns[j]
6542 = other_output_reload_insns[j] = 0;
6544 /* Now output the instructions to copy the data into and out of the
6545 reload registers. Do these in the order that the reloads were reported,
6546 since reloads of base and index registers precede reloads of operands
6547 and the operands may need the base and index registers reloaded. */
6549 for (j = 0; j < n_reloads; j++)
6552 rtx oldequiv_reg = 0;
6553 rtx this_reload_insn = 0;
6554 int expect_occurrences = 1;
6557 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6558 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6560 old = (rld[j].in && GET_CODE (rld[j].in) == MEM
6561 ? rld[j].in_reg : rld[j].in);
6564 /* AUTO_INC reloads need to be handled even if inherited. We got an
6565 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6566 && (! reload_inherited[j] || (rld[j].out && ! rld[j].out_reg))
6567 && ! rtx_equal_p (rld[j].reg_rtx, old)
6568 && rld[j].reg_rtx != 0)
6570 register rtx reloadreg = rld[j].reg_rtx;
6572 enum machine_mode mode;
6575 /* Determine the mode to reload in.
6576 This is very tricky because we have three to choose from.
6577 There is the mode the insn operand wants (rld[J].inmode).
6578 There is the mode of the reload register RELOADREG.
6579 There is the intrinsic mode of the operand, which we could find
6580 by stripping some SUBREGs.
6581 It turns out that RELOADREG's mode is irrelevant:
6582 we can change that arbitrarily.
6584 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6585 then the reload reg may not support QImode moves, so use SImode.
6586 If foo is in memory due to spilling a pseudo reg, this is safe,
6587 because the QImode value is in the least significant part of a
6588 slot big enough for a SImode. If foo is some other sort of
6589 memory reference, then it is impossible to reload this case,
6590 so previous passes had better make sure this never happens.
6592 Then consider a one-word union which has SImode and one of its
6593 members is a float, being fetched as (SUBREG:SF union:SI).
6594 We must fetch that as SFmode because we could be loading into
6595 a float-only register. In this case OLD's mode is correct.
6597 Consider an immediate integer: it has VOIDmode. Here we need
6598 to get a mode from something else.
6600 In some cases, there is a fourth mode, the operand's
6601 containing mode. If the insn specifies a containing mode for
6602 this operand, it overrides all others.
6604 I am not sure whether the algorithm here is always right,
6605 but it does the right things in those cases. */
6607 mode = GET_MODE (old);
6608 if (mode == VOIDmode)
6609 mode = rld[j].inmode;
6611 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6612 /* If we need a secondary register for this operation, see if
6613 the value is already in a register in that class. Don't
6614 do this if the secondary register will be used as a scratch
6617 if (rld[j].secondary_in_reload >= 0
6618 && rld[j].secondary_in_icode == CODE_FOR_nothing
6621 = find_equiv_reg (old, insn,
6622 rld[rld[j].secondary_in_reload].class,
6623 -1, NULL_PTR, 0, mode);
6626 /* If reloading from memory, see if there is a register
6627 that already holds the same value. If so, reload from there.
6628 We can pass 0 as the reload_reg_p argument because
6629 any other reload has either already been emitted,
6630 in which case find_equiv_reg will see the reload-insn,
6631 or has yet to be emitted, in which case it doesn't matter
6632 because we will use this equiv reg right away. */
6634 if (oldequiv == 0 && optimize
6635 && (GET_CODE (old) == MEM
6636 || (GET_CODE (old) == REG
6637 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6638 && reg_renumber[REGNO (old)] < 0)))
6639 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6640 -1, NULL_PTR, 0, mode);
6644 int regno = true_regnum (oldequiv);
6646 /* Don't use OLDEQUIV if any other reload changes it at an
6647 earlier stage of this insn or at this stage. */
6648 if (! reload_reg_free_for_value_p (regno, rld[j].opnum,
6650 rld[j].in, const0_rtx, j,
6654 /* If it is no cheaper to copy from OLDEQUIV into the
6655 reload register than it would be to move from memory,
6656 don't use it. Likewise, if we need a secondary register
6660 && ((REGNO_REG_CLASS (regno) != rld[j].class
6661 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
6663 >= MEMORY_MOVE_COST (mode, rld[j].class, 1)))
6664 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6665 || (SECONDARY_INPUT_RELOAD_CLASS (rld[j].class,
6669 #ifdef SECONDARY_MEMORY_NEEDED
6670 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6678 /* delete_output_reload is only invoked properly if old contains
6679 the original pseudo register. Since this is replaced with a
6680 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6681 find the pseudo in RELOAD_IN_REG. */
6683 && reload_override_in[j]
6684 && GET_CODE (rld[j].in_reg) == REG)
6687 old = rld[j].in_reg;
6691 else if (GET_CODE (oldequiv) == REG)
6692 oldequiv_reg = oldequiv;
6693 else if (GET_CODE (oldequiv) == SUBREG)
6694 oldequiv_reg = SUBREG_REG (oldequiv);
6696 /* If we are reloading from a register that was recently stored in
6697 with an output-reload, see if we can prove there was
6698 actually no need to store the old value in it. */
6700 if (optimize && GET_CODE (oldequiv) == REG
6701 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6702 && spill_reg_store[REGNO (oldequiv)]
6703 && GET_CODE (old) == REG
6704 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6705 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6707 delete_output_reload (insn, j, REGNO (oldequiv));
6709 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6710 then load RELOADREG from OLDEQUIV. Note that we cannot use
6711 gen_lowpart_common since it can do the wrong thing when
6712 RELOADREG has a multi-word mode. Note that RELOADREG
6713 must always be a REG here. */
6715 if (GET_MODE (reloadreg) != mode)
6716 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6717 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6718 oldequiv = SUBREG_REG (oldequiv);
6719 if (GET_MODE (oldequiv) != VOIDmode
6720 && mode != GET_MODE (oldequiv))
6721 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6723 /* Switch to the right place to emit the reload insns. */
6724 switch (rld[j].when_needed)
6727 where = &other_input_reload_insns;
6729 case RELOAD_FOR_INPUT:
6730 where = &input_reload_insns[rld[j].opnum];
6732 case RELOAD_FOR_INPUT_ADDRESS:
6733 where = &input_address_reload_insns[rld[j].opnum];
6735 case RELOAD_FOR_INPADDR_ADDRESS:
6736 where = &inpaddr_address_reload_insns[rld[j].opnum];
6738 case RELOAD_FOR_OUTPUT_ADDRESS:
6739 where = &output_address_reload_insns[rld[j].opnum];
6741 case RELOAD_FOR_OUTADDR_ADDRESS:
6742 where = &outaddr_address_reload_insns[rld[j].opnum];
6744 case RELOAD_FOR_OPERAND_ADDRESS:
6745 where = &operand_reload_insns;
6747 case RELOAD_FOR_OPADDR_ADDR:
6748 where = &other_operand_reload_insns;
6750 case RELOAD_FOR_OTHER_ADDRESS:
6751 where = &other_input_address_reload_insns;
6757 push_to_sequence (*where);
6760 /* Auto-increment addresses must be reloaded in a special way. */
6761 if (rld[j].out && ! rld[j].out_reg)
6763 /* We are not going to bother supporting the case where a
6764 incremented register can't be copied directly from
6765 OLDEQUIV since this seems highly unlikely. */
6766 if (rld[j].secondary_in_reload >= 0)
6769 if (reload_inherited[j])
6770 oldequiv = reloadreg;
6772 old = XEXP (rld[j].in_reg, 0);
6774 if (optimize && GET_CODE (oldequiv) == REG
6775 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6776 && spill_reg_store[REGNO (oldequiv)]
6777 && GET_CODE (old) == REG
6778 && (dead_or_set_p (insn,
6779 spill_reg_stored_to[REGNO (oldequiv)])
6780 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6782 delete_output_reload (insn, j, REGNO (oldequiv));
6784 /* Prevent normal processing of this reload. */
6786 /* Output a special code sequence for this case. */
6787 new_spill_reg_store[REGNO (reloadreg)]
6788 = inc_for_reload (reloadreg, oldequiv, rld[j].out,
6792 /* If we are reloading a pseudo-register that was set by the previous
6793 insn, see if we can get rid of that pseudo-register entirely
6794 by redirecting the previous insn into our reload register. */
6796 else if (optimize && GET_CODE (old) == REG
6797 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6798 && dead_or_set_p (insn, old)
6799 /* This is unsafe if some other reload
6800 uses the same reg first. */
6801 && reload_reg_free_for_value_p (REGNO (reloadreg),
6807 rtx temp = PREV_INSN (insn);
6808 while (temp && GET_CODE (temp) == NOTE)
6809 temp = PREV_INSN (temp);
6811 && GET_CODE (temp) == INSN
6812 && GET_CODE (PATTERN (temp)) == SET
6813 && SET_DEST (PATTERN (temp)) == old
6814 /* Make sure we can access insn_operand_constraint. */
6815 && asm_noperands (PATTERN (temp)) < 0
6816 /* This is unsafe if prev insn rejects our reload reg. */
6817 && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint,
6819 /* This is unsafe if operand occurs more than once in current
6820 insn. Perhaps some occurrences aren't reloaded. */
6821 && count_occurrences (PATTERN (insn), old) == 1
6822 /* Don't risk splitting a matching pair of operands. */
6823 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6825 /* Store into the reload register instead of the pseudo. */
6826 SET_DEST (PATTERN (temp)) = reloadreg;
6828 /* If the previous insn is an output reload, the source is
6829 a reload register, and its spill_reg_store entry will
6830 contain the previous destination. This is now
6832 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6833 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6835 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6836 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6839 /* If these are the only uses of the pseudo reg,
6840 pretend for GDB it lives in the reload reg we used. */
6841 if (REG_N_DEATHS (REGNO (old)) == 1
6842 && REG_N_SETS (REGNO (old)) == 1)
6844 reg_renumber[REGNO (old)] = REGNO (rld[j].reg_rtx);
6845 alter_reg (REGNO (old), -1);
6851 /* We can't do that, so output an insn to load RELOADREG. */
6855 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6856 rtx second_reload_reg = 0;
6857 enum insn_code icode;
6859 /* If we have a secondary reload, pick up the secondary register
6860 and icode, if any. If OLDEQUIV and OLD are different or
6861 if this is an in-out reload, recompute whether or not we
6862 still need a secondary register and what the icode should
6863 be. If we still need a secondary register and the class or
6864 icode is different, go back to reloading from OLD if using
6865 OLDEQUIV means that we got the wrong type of register. We
6866 cannot have different class or icode due to an in-out reload
6867 because we don't make such reloads when both the input and
6868 output need secondary reload registers. */
6870 if (rld[j].secondary_in_reload >= 0)
6872 int secondary_reload = rld[j].secondary_in_reload;
6873 rtx real_oldequiv = oldequiv;
6877 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6878 and similarly for OLD.
6879 See comments in get_secondary_reload in reload.c. */
6880 /* If it is a pseudo that cannot be replaced with its
6881 equivalent MEM, we must fall back to reload_in, which
6882 will have all the necessary substitutions registered.
6883 Likewise for a pseudo that can't be replaced with its
6884 equivalent constant.
6886 Take extra care for subregs of such pseudos. Note that
6887 we cannot use reg_equiv_mem in this case because it is
6888 not in the right mode. */
6891 if (GET_CODE (tmp) == SUBREG)
6892 tmp = SUBREG_REG (tmp);
6893 if (GET_CODE (tmp) == REG
6894 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6895 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6896 || reg_equiv_constant[REGNO (tmp)] != 0))
6898 if (! reg_equiv_mem[REGNO (tmp)]
6899 || num_not_at_initial_offset
6900 || GET_CODE (oldequiv) == SUBREG)
6901 real_oldequiv = rld[j].in;
6903 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6907 if (GET_CODE (tmp) == SUBREG)
6908 tmp = SUBREG_REG (tmp);
6909 if (GET_CODE (tmp) == REG
6910 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6911 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6912 || reg_equiv_constant[REGNO (tmp)] != 0))
6914 if (! reg_equiv_mem[REGNO (tmp)]
6915 || num_not_at_initial_offset
6916 || GET_CODE (old) == SUBREG)
6917 real_old = rld[j].in;
6919 real_old = reg_equiv_mem[REGNO (tmp)];
6922 second_reload_reg = rld[secondary_reload].reg_rtx;
6923 icode = rld[j].secondary_in_icode;
6925 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6926 || (rld[j].in != 0 && rld[j].out != 0))
6928 enum reg_class new_class
6929 = SECONDARY_INPUT_RELOAD_CLASS (rld[j].class,
6930 mode, real_oldequiv);
6932 if (new_class == NO_REGS)
6933 second_reload_reg = 0;
6936 enum insn_code new_icode;
6937 enum machine_mode new_mode;
6939 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6940 REGNO (second_reload_reg)))
6941 oldequiv = old, real_oldequiv = real_old;
6944 new_icode = reload_in_optab[(int) mode];
6945 if (new_icode != CODE_FOR_nothing
6946 && ((insn_data[(int) new_icode].operand[0].predicate
6947 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6949 || (insn_data[(int) new_icode].operand[1].predicate
6950 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6951 (real_oldequiv, mode)))))
6952 new_icode = CODE_FOR_nothing;
6954 if (new_icode == CODE_FOR_nothing)
6957 new_mode = insn_data[(int) new_icode].operand[2].mode;
6959 if (GET_MODE (second_reload_reg) != new_mode)
6961 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6963 oldequiv = old, real_oldequiv = real_old;
6966 = gen_rtx_REG (new_mode,
6967 REGNO (second_reload_reg));
6973 /* If we still need a secondary reload register, check
6974 to see if it is being used as a scratch or intermediate
6975 register and generate code appropriately. If we need
6976 a scratch register, use REAL_OLDEQUIV since the form of
6977 the insn may depend on the actual address if it is
6980 if (second_reload_reg)
6982 if (icode != CODE_FOR_nothing)
6984 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6985 second_reload_reg));
6990 /* See if we need a scratch register to load the
6991 intermediate register (a tertiary reload). */
6992 enum insn_code tertiary_icode
6993 = rld[secondary_reload].secondary_in_icode;
6995 if (tertiary_icode != CODE_FOR_nothing)
6997 rtx third_reload_reg
6998 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
7000 emit_insn ((GEN_FCN (tertiary_icode)
7001 (second_reload_reg, real_oldequiv,
7002 third_reload_reg)));
7005 gen_reload (second_reload_reg, real_oldequiv,
7007 rld[j].when_needed);
7009 oldequiv = second_reload_reg;
7015 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7017 rtx real_oldequiv = oldequiv;
7019 if ((GET_CODE (oldequiv) == REG
7020 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7021 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
7022 || reg_equiv_constant[REGNO (oldequiv)] != 0))
7023 || (GET_CODE (oldequiv) == SUBREG
7024 && GET_CODE (SUBREG_REG (oldequiv)) == REG
7025 && (REGNO (SUBREG_REG (oldequiv))
7026 >= FIRST_PSEUDO_REGISTER)
7027 && ((reg_equiv_memory_loc
7028 [REGNO (SUBREG_REG (oldequiv))] != 0)
7029 || (reg_equiv_constant
7030 [REGNO (SUBREG_REG (oldequiv))] != 0))))
7031 real_oldequiv = rld[j].in;
7032 gen_reload (reloadreg, real_oldequiv, rld[j].opnum,
7033 rld[j].when_needed);
7038 this_reload_insn = get_last_insn ();
7039 /* End this sequence. */
7040 *where = get_insns ();
7043 /* Update reload_override_in so that delete_address_reloads_1
7044 can see the actual register usage. */
7046 reload_override_in[j] = oldequiv;
7049 /* When inheriting a wider reload, we have a MEM in rld[j].in,
7050 e.g. inheriting a SImode output reload for
7051 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7052 if (optimize && reload_inherited[j] && rld[j].in
7053 && GET_CODE (rld[j].in) == MEM
7054 && GET_CODE (rld[j].in_reg) == MEM
7055 && reload_spill_index[j] >= 0
7056 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7059 = count_occurrences (PATTERN (insn), rld[j].in) == 1 ? 0 : -1;
7061 = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7064 /* If we are reloading a register that was recently stored in with an
7065 output-reload, see if we can prove there was
7066 actually no need to store the old value in it. */
7069 && (reload_inherited[j] || reload_override_in[j])
7071 && GET_CODE (rld[j].reg_rtx) == REG
7072 && spill_reg_store[REGNO (rld[j].reg_rtx)] != 0
7074 /* There doesn't seem to be any reason to restrict this to pseudos
7075 and doing so loses in the case where we are copying from a
7076 register of the wrong class. */
7077 && (REGNO (spill_reg_stored_to[REGNO (rld[j].reg_rtx)])
7078 >= FIRST_PSEUDO_REGISTER)
7080 /* The insn might have already some references to stackslots
7081 replaced by MEMs, while reload_out_reg still names the
7083 && (dead_or_set_p (insn,
7084 spill_reg_stored_to[REGNO (rld[j].reg_rtx)])
7085 || rtx_equal_p (spill_reg_stored_to[REGNO (rld[j].reg_rtx)],
7087 delete_output_reload (insn, j, REGNO (rld[j].reg_rtx));
7089 /* Input-reloading is done. Now do output-reloading,
7090 storing the value from the reload-register after the main insn
7091 if rld[j].out is nonzero.
7093 ??? At some point we need to support handling output reloads of
7094 JUMP_INSNs or insns that set cc0. */
7096 /* If this is an output reload that stores something that is
7097 not loaded in this same reload, see if we can eliminate a previous
7100 rtx pseudo = rld[j].out_reg;
7103 && GET_CODE (pseudo) == REG
7104 && ! rtx_equal_p (rld[j].in_reg, pseudo)
7105 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7106 && reg_last_reload_reg[REGNO (pseudo)])
7108 int pseudo_no = REGNO (pseudo);
7109 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7111 /* We don't need to test full validity of last_regno for
7112 inherit here; we only want to know if the store actually
7113 matches the pseudo. */
7114 if (reg_reloaded_contents[last_regno] == pseudo_no
7115 && spill_reg_store[last_regno]
7116 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7117 delete_output_reload (insn, j, last_regno);
7121 old = rld[j].out_reg;
7123 && rld[j].reg_rtx != old
7124 && rld[j].reg_rtx != 0)
7126 register rtx reloadreg = rld[j].reg_rtx;
7127 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7128 register rtx second_reloadreg = 0;
7131 enum machine_mode mode;
7134 /* An output operand that dies right away does need a reload,
7135 but need not be copied from it. Show the new location in the
7137 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
7138 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7140 XEXP (note, 0) = rld[j].reg_rtx;
7143 /* Likewise for a SUBREG of an operand that dies. */
7144 else if (GET_CODE (old) == SUBREG
7145 && GET_CODE (SUBREG_REG (old)) == REG
7146 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7149 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7153 else if (GET_CODE (old) == SCRATCH)
7154 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7155 but we don't want to make an output reload. */
7159 /* Strip off of OLD any size-increasing SUBREGs such as
7160 (SUBREG:SI foo:QI 0). */
7162 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
7163 && (GET_MODE_SIZE (GET_MODE (old))
7164 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
7165 old = SUBREG_REG (old);
7168 /* If is a JUMP_INSN, we can't support output reloads yet. */
7169 if (GET_CODE (insn) == JUMP_INSN)
7172 if (rld[j].when_needed == RELOAD_OTHER)
7175 push_to_sequence (output_reload_insns[rld[j].opnum]);
7179 /* Determine the mode to reload in.
7180 See comments above (for input reloading). */
7182 mode = GET_MODE (old);
7183 if (mode == VOIDmode)
7185 /* VOIDmode should never happen for an output. */
7186 if (asm_noperands (PATTERN (insn)) < 0)
7187 /* It's the compiler's fault. */
7188 fatal_insn ("VOIDmode on an output", insn);
7189 error_for_asm (insn, "output operand is constant in `asm'");
7190 /* Prevent crash--use something we know is valid. */
7192 old = gen_rtx_REG (mode, REGNO (reloadreg));
7195 if (GET_MODE (reloadreg) != mode)
7196 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
7198 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7200 /* If we need two reload regs, set RELOADREG to the intermediate
7201 one, since it will be stored into OLD. We might need a secondary
7202 register only for an input reload, so check again here. */
7204 if (rld[j].secondary_out_reload >= 0)
7208 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
7209 && reg_equiv_mem[REGNO (old)] != 0)
7210 real_old = reg_equiv_mem[REGNO (old)];
7212 if((SECONDARY_OUTPUT_RELOAD_CLASS (rld[j].class,
7216 second_reloadreg = reloadreg;
7217 reloadreg = rld[rld[j].secondary_out_reload].reg_rtx;
7219 /* See if RELOADREG is to be used as a scratch register
7220 or as an intermediate register. */
7221 if (rld[j].secondary_out_icode != CODE_FOR_nothing)
7223 emit_insn ((GEN_FCN (rld[j].secondary_out_icode)
7224 (real_old, second_reloadreg, reloadreg)));
7229 /* See if we need both a scratch and intermediate reload
7232 int secondary_reload = rld[j].secondary_out_reload;
7233 enum insn_code tertiary_icode
7234 = rld[secondary_reload].secondary_out_icode;
7236 if (GET_MODE (reloadreg) != mode)
7237 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
7239 if (tertiary_icode != CODE_FOR_nothing)
7242 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
7245 /* Copy primary reload reg to secondary reload reg.
7246 (Note that these have been swapped above, then
7247 secondary reload reg to OLD using our insn. */
7249 /* If REAL_OLD is a paradoxical SUBREG, remove it
7250 and try to put the opposite SUBREG on
7252 if (GET_CODE (real_old) == SUBREG
7253 && (GET_MODE_SIZE (GET_MODE (real_old))
7254 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7255 && 0 != (tem = gen_lowpart_common
7256 (GET_MODE (SUBREG_REG (real_old)),
7258 real_old = SUBREG_REG (real_old), reloadreg = tem;
7260 gen_reload (reloadreg, second_reloadreg,
7261 rld[j].opnum, rld[j].when_needed);
7262 emit_insn ((GEN_FCN (tertiary_icode)
7263 (real_old, reloadreg, third_reloadreg)));
7268 /* Copy between the reload regs here and then to
7271 gen_reload (reloadreg, second_reloadreg,
7272 rld[j].opnum, rld[j].when_needed);
7278 /* Output the last reload insn. */
7283 /* Don't output the last reload if OLD is not the dest of
7284 INSN and is in the src and is clobbered by INSN. */
7285 if (! flag_expensive_optimizations
7286 || GET_CODE (old) != REG
7287 || !(set = single_set (insn))
7288 || rtx_equal_p (old, SET_DEST (set))
7289 || !reg_mentioned_p (old, SET_SRC (set))
7290 || !regno_clobbered_p (REGNO (old), insn))
7291 gen_reload (old, reloadreg, rld[j].opnum,
7292 rld[j].when_needed);
7295 /* Look at all insns we emitted, just to be safe. */
7296 for (p = get_insns (); p; p = NEXT_INSN (p))
7297 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
7299 rtx pat = PATTERN (p);
7301 /* If this output reload doesn't come from a spill reg,
7302 clear any memory of reloaded copies of the pseudo reg.
7303 If this output reload comes from a spill reg,
7304 reg_has_output_reload will make this do nothing. */
7305 note_stores (pat, forget_old_reloads_1);
7307 if (reg_mentioned_p (rld[j].reg_rtx, pat))
7309 rtx set = single_set (insn);
7310 if (reload_spill_index[j] < 0
7312 && SET_SRC (set) == rld[j].reg_rtx)
7314 int src = REGNO (SET_SRC (set));
7316 reload_spill_index[j] = src;
7317 SET_HARD_REG_BIT (reg_is_output_reload, src);
7318 if (find_regno_note (insn, REG_DEAD, src))
7319 SET_HARD_REG_BIT (reg_reloaded_died, src);
7321 if (REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7323 int s = rld[j].secondary_out_reload;
7324 set = single_set (p);
7325 /* If this reload copies only to the secondary reload
7326 register, the secondary reload does the actual
7328 if (s >= 0 && set == NULL_RTX)
7329 ; /* We can't tell what function the secondary reload
7330 has and where the actual store to the pseudo is
7331 made; leave new_spill_reg_store alone. */
7333 && SET_SRC (set) == rld[j].reg_rtx
7334 && SET_DEST (set) == rld[s].reg_rtx)
7336 /* Usually the next instruction will be the
7337 secondary reload insn; if we can confirm
7338 that it is, setting new_spill_reg_store to
7339 that insn will allow an extra optimization. */
7340 rtx s_reg = rld[s].reg_rtx;
7341 rtx next = NEXT_INSN (p);
7342 rld[s].out = rld[j].out;
7343 rld[s].out_reg = rld[j].out_reg;
7344 set = single_set (next);
7345 if (set && SET_SRC (set) == s_reg
7346 && ! new_spill_reg_store[REGNO (s_reg)])
7348 SET_HARD_REG_BIT (reg_is_output_reload,
7350 new_spill_reg_store[REGNO (s_reg)] = next;
7354 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = p;
7359 if (rld[j].when_needed == RELOAD_OTHER)
7361 emit_insns (other_output_reload_insns[rld[j].opnum]);
7362 other_output_reload_insns[rld[j].opnum] = get_insns ();
7365 output_reload_insns[rld[j].opnum] = get_insns ();
7371 /* Now write all the insns we made for reloads in the order expected by
7372 the allocation functions. Prior to the insn being reloaded, we write
7373 the following reloads:
7375 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7377 RELOAD_OTHER reloads.
7379 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7380 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7381 RELOAD_FOR_INPUT reload for the operand.
7383 RELOAD_FOR_OPADDR_ADDRS reloads.
7385 RELOAD_FOR_OPERAND_ADDRESS reloads.
7387 After the insn being reloaded, we write the following:
7389 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7390 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7391 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7392 reloads for the operand. The RELOAD_OTHER output reloads are
7393 output in descending order by reload number. */
7395 emit_insns_before (other_input_address_reload_insns, insn);
7396 emit_insns_before (other_input_reload_insns, insn);
7398 for (j = 0; j < reload_n_operands; j++)
7400 emit_insns_before (inpaddr_address_reload_insns[j], insn);
7401 emit_insns_before (input_address_reload_insns[j], insn);
7402 emit_insns_before (input_reload_insns[j], insn);
7405 emit_insns_before (other_operand_reload_insns, insn);
7406 emit_insns_before (operand_reload_insns, insn);
7408 for (j = 0; j < reload_n_operands; j++)
7410 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
7411 emit_insns_before (output_address_reload_insns[j], following_insn);
7412 emit_insns_before (output_reload_insns[j], following_insn);
7413 emit_insns_before (other_output_reload_insns[j], following_insn);
7416 /* Keep basic block info up to date. */
7419 if (BLOCK_HEAD (chain->block) == insn)
7420 BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
7421 if (BLOCK_END (chain->block) == insn)
7422 BLOCK_END (chain->block) = PREV_INSN (following_insn);
7425 /* For all the spill regs newly reloaded in this instruction,
7426 record what they were reloaded from, so subsequent instructions
7427 can inherit the reloads.
7429 Update spill_reg_store for the reloads of this insn.
7430 Copy the elements that were updated in the loop above. */
7432 for (j = 0; j < n_reloads; j++)
7434 register int r = reload_order[j];
7435 register int i = reload_spill_index[r];
7437 /* If this is a non-inherited input reload from a pseudo, we must
7438 clear any memory of a previous store to the same pseudo. Only do
7439 something if there will not be an output reload for the pseudo
7441 if (rld[r].in_reg != 0
7442 && ! (reload_inherited[r] || reload_override_in[r]))
7444 rtx reg = rld[r].in_reg;
7446 if (GET_CODE (reg) == SUBREG)
7447 reg = SUBREG_REG (reg);
7449 if (GET_CODE (reg) == REG
7450 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7451 && ! reg_has_output_reload[REGNO (reg)])
7453 int nregno = REGNO (reg);
7455 if (reg_last_reload_reg[nregno])
7457 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7459 if (reg_reloaded_contents[last_regno] == nregno)
7460 spill_reg_store[last_regno] = 0;
7465 /* I is nonneg if this reload used a register.
7466 If rld[r].reg_rtx is 0, this is an optional reload
7467 that we opted to ignore. */
7469 if (i >= 0 && rld[r].reg_rtx != 0)
7472 = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7474 int part_reaches_end = 0;
7475 int all_reaches_end = 1;
7477 /* For a multi register reload, we need to check if all or part
7478 of the value lives to the end. */
7479 for (k = 0; k < nr; k++)
7481 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7482 rld[r].when_needed))
7483 part_reaches_end = 1;
7485 all_reaches_end = 0;
7488 /* Ignore reloads that don't reach the end of the insn in
7490 if (all_reaches_end)
7492 /* First, clear out memory of what used to be in this spill reg.
7493 If consecutive registers are used, clear them all. */
7495 for (k = 0; k < nr; k++)
7496 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7498 /* Maybe the spill reg contains a copy of reload_out. */
7500 && (GET_CODE (rld[r].out) == REG
7504 || GET_CODE (rld[r].out_reg) == REG))
7506 rtx out = (GET_CODE (rld[r].out) == REG
7510 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7511 register int nregno = REGNO (out);
7512 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7513 : HARD_REGNO_NREGS (nregno,
7514 GET_MODE (rld[r].reg_rtx)));
7516 spill_reg_store[i] = new_spill_reg_store[i];
7517 spill_reg_stored_to[i] = out;
7518 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7520 /* If NREGNO is a hard register, it may occupy more than
7521 one register. If it does, say what is in the
7522 rest of the registers assuming that both registers
7523 agree on how many words the object takes. If not,
7524 invalidate the subsequent registers. */
7526 if (nregno < FIRST_PSEUDO_REGISTER)
7527 for (k = 1; k < nnr; k++)
7528 reg_last_reload_reg[nregno + k]
7530 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7531 REGNO (rld[r].reg_rtx) + k)
7534 /* Now do the inverse operation. */
7535 for (k = 0; k < nr; k++)
7537 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7538 reg_reloaded_contents[i + k]
7539 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7542 reg_reloaded_insn[i + k] = insn;
7543 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7547 /* Maybe the spill reg contains a copy of reload_in. Only do
7548 something if there will not be an output reload for
7549 the register being reloaded. */
7550 else if (rld[r].out_reg == 0
7552 && ((GET_CODE (rld[r].in) == REG
7553 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7554 && ! reg_has_output_reload[REGNO (rld[r].in)])
7555 || (GET_CODE (rld[r].in_reg) == REG
7556 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7557 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7559 register int nregno;
7562 if (GET_CODE (rld[r].in) == REG
7563 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7564 nregno = REGNO (rld[r].in);
7565 else if (GET_CODE (rld[r].in_reg) == REG)
7566 nregno = REGNO (rld[r].in_reg);
7568 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7570 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7571 : HARD_REGNO_NREGS (nregno,
7572 GET_MODE (rld[r].reg_rtx)));
7574 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7576 if (nregno < FIRST_PSEUDO_REGISTER)
7577 for (k = 1; k < nnr; k++)
7578 reg_last_reload_reg[nregno + k]
7580 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7581 REGNO (rld[r].reg_rtx) + k)
7584 /* Unless we inherited this reload, show we haven't
7585 recently done a store.
7586 Previous stores of inherited auto_inc expressions
7587 also have to be discarded. */
7588 if (! reload_inherited[r]
7589 || (rld[r].out && ! rld[r].out_reg))
7590 spill_reg_store[i] = 0;
7592 for (k = 0; k < nr; k++)
7594 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7595 reg_reloaded_contents[i + k]
7596 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7599 reg_reloaded_insn[i + k] = insn;
7600 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7605 /* However, if part of the reload reaches the end, then we must
7606 invalidate the old info for the part that survives to the end. */
7607 else if (part_reaches_end)
7609 for (k = 0; k < nr; k++)
7610 if (reload_reg_reaches_end_p (i + k,
7612 rld[r].when_needed))
7613 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7617 /* The following if-statement was #if 0'd in 1.34 (or before...).
7618 It's reenabled in 1.35 because supposedly nothing else
7619 deals with this problem. */
7621 /* If a register gets output-reloaded from a non-spill register,
7622 that invalidates any previous reloaded copy of it.
7623 But forget_old_reloads_1 won't get to see it, because
7624 it thinks only about the original insn. So invalidate it here. */
7625 if (i < 0 && rld[r].out != 0
7626 && (GET_CODE (rld[r].out) == REG
7627 || (GET_CODE (rld[r].out) == MEM
7628 && GET_CODE (rld[r].out_reg) == REG)))
7630 rtx out = (GET_CODE (rld[r].out) == REG
7631 ? rld[r].out : rld[r].out_reg);
7632 register int nregno = REGNO (out);
7633 if (nregno >= FIRST_PSEUDO_REGISTER)
7635 rtx src_reg, store_insn = NULL_RTX;
7637 reg_last_reload_reg[nregno] = 0;
7639 /* If we can find a hard register that is stored, record
7640 the storing insn so that we may delete this insn with
7641 delete_output_reload. */
7642 src_reg = rld[r].reg_rtx;
7644 /* If this is an optional reload, try to find the source reg
7645 from an input reload. */
7648 rtx set = single_set (insn);
7649 if (set && SET_DEST (set) == rld[r].out)
7653 src_reg = SET_SRC (set);
7655 for (k = 0; k < n_reloads; k++)
7657 if (rld[k].in == src_reg)
7659 src_reg = rld[k].reg_rtx;
7666 store_insn = new_spill_reg_store[REGNO (src_reg)];
7667 if (src_reg && GET_CODE (src_reg) == REG
7668 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7670 int src_regno = REGNO (src_reg);
7671 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7672 /* The place where to find a death note varies with
7673 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7674 necessarily checked exactly in the code that moves
7675 notes, so just check both locations. */
7676 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7678 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7681 spill_reg_store[src_regno + nr] = store_insn;
7682 spill_reg_stored_to[src_regno + nr] = out;
7683 reg_reloaded_contents[src_regno + nr] = nregno;
7684 reg_reloaded_insn[src_regno + nr] = store_insn;
7685 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7686 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7687 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7689 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7691 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7693 reg_last_reload_reg[nregno] = src_reg;
7698 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (rld[r].out));
7700 while (num_regs-- > 0)
7701 reg_last_reload_reg[nregno + num_regs] = 0;
7705 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7708 /* Emit code to perform a reload from IN (which may be a reload register) to
7709 OUT (which may also be a reload register). IN or OUT is from operand
7710 OPNUM with reload type TYPE.
7712 Returns first insn emitted. */
7715 gen_reload (out, in, opnum, type)
7719 enum reload_type type;
7721 rtx last = get_last_insn ();
7724 /* If IN is a paradoxical SUBREG, remove it and try to put the
7725 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7726 if (GET_CODE (in) == SUBREG
7727 && (GET_MODE_SIZE (GET_MODE (in))
7728 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7729 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7730 in = SUBREG_REG (in), out = tem;
7731 else if (GET_CODE (out) == SUBREG
7732 && (GET_MODE_SIZE (GET_MODE (out))
7733 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7734 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7735 out = SUBREG_REG (out), in = tem;
7737 /* How to do this reload can get quite tricky. Normally, we are being
7738 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7739 register that didn't get a hard register. In that case we can just
7740 call emit_move_insn.
7742 We can also be asked to reload a PLUS that adds a register or a MEM to
7743 another register, constant or MEM. This can occur during frame pointer
7744 elimination and while reloading addresses. This case is handled by
7745 trying to emit a single insn to perform the add. If it is not valid,
7746 we use a two insn sequence.
7748 Finally, we could be called to handle an 'o' constraint by putting
7749 an address into a register. In that case, we first try to do this
7750 with a named pattern of "reload_load_address". If no such pattern
7751 exists, we just emit a SET insn and hope for the best (it will normally
7752 be valid on machines that use 'o').
7754 This entire process is made complex because reload will never
7755 process the insns we generate here and so we must ensure that
7756 they will fit their constraints and also by the fact that parts of
7757 IN might be being reloaded separately and replaced with spill registers.
7758 Because of this, we are, in some sense, just guessing the right approach
7759 here. The one listed above seems to work.
7761 ??? At some point, this whole thing needs to be rethought. */
7763 if (GET_CODE (in) == PLUS
7764 && (GET_CODE (XEXP (in, 0)) == REG
7765 || GET_CODE (XEXP (in, 0)) == SUBREG
7766 || GET_CODE (XEXP (in, 0)) == MEM)
7767 && (GET_CODE (XEXP (in, 1)) == REG
7768 || GET_CODE (XEXP (in, 1)) == SUBREG
7769 || CONSTANT_P (XEXP (in, 1))
7770 || GET_CODE (XEXP (in, 1)) == MEM))
7772 /* We need to compute the sum of a register or a MEM and another
7773 register, constant, or MEM, and put it into the reload
7774 register. The best possible way of doing this is if the machine
7775 has a three-operand ADD insn that accepts the required operands.
7777 The simplest approach is to try to generate such an insn and see if it
7778 is recognized and matches its constraints. If so, it can be used.
7780 It might be better not to actually emit the insn unless it is valid,
7781 but we need to pass the insn as an operand to `recog' and
7782 `extract_insn' and it is simpler to emit and then delete the insn if
7783 not valid than to dummy things up. */
7785 rtx op0, op1, tem, insn;
7788 op0 = find_replacement (&XEXP (in, 0));
7789 op1 = find_replacement (&XEXP (in, 1));
7791 /* Since constraint checking is strict, commutativity won't be
7792 checked, so we need to do that here to avoid spurious failure
7793 if the add instruction is two-address and the second operand
7794 of the add is the same as the reload reg, which is frequently
7795 the case. If the insn would be A = B + A, rearrange it so
7796 it will be A = A + B as constrain_operands expects. */
7798 if (GET_CODE (XEXP (in, 1)) == REG
7799 && REGNO (out) == REGNO (XEXP (in, 1)))
7800 tem = op0, op0 = op1, op1 = tem;
7802 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7803 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7805 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7806 code = recog_memoized (insn);
7810 extract_insn (insn);
7811 /* We want constrain operands to treat this insn strictly in
7812 its validity determination, i.e., the way it would after reload
7814 if (constrain_operands (1))
7818 delete_insns_since (last);
7820 /* If that failed, we must use a conservative two-insn sequence.
7822 Use a move to copy one operand into the reload register. Prefer
7823 to reload a constant, MEM or pseudo since the move patterns can
7824 handle an arbitrary operand. If OP1 is not a constant, MEM or
7825 pseudo and OP1 is not a valid operand for an add instruction, then
7828 After reloading one of the operands into the reload register, add
7829 the reload register to the output register.
7831 If there is another way to do this for a specific machine, a
7832 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7835 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7837 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7838 || (GET_CODE (op1) == REG
7839 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7840 || (code != CODE_FOR_nothing
7841 && ! ((*insn_data[code].operand[2].predicate)
7842 (op1, insn_data[code].operand[2].mode))))
7843 tem = op0, op0 = op1, op1 = tem;
7845 gen_reload (out, op0, opnum, type);
7847 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7848 This fixes a problem on the 32K where the stack pointer cannot
7849 be used as an operand of an add insn. */
7851 if (rtx_equal_p (op0, op1))
7854 insn = emit_insn (gen_add2_insn (out, op1));
7856 /* If that failed, copy the address register to the reload register.
7857 Then add the constant to the reload register. */
7859 code = recog_memoized (insn);
7863 extract_insn (insn);
7864 /* We want constrain operands to treat this insn strictly in
7865 its validity determination, i.e., the way it would after reload
7867 if (constrain_operands (1))
7869 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7871 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7876 delete_insns_since (last);
7878 gen_reload (out, op1, opnum, type);
7879 insn = emit_insn (gen_add2_insn (out, op0));
7880 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7883 #ifdef SECONDARY_MEMORY_NEEDED
7884 /* If we need a memory location to do the move, do it that way. */
7885 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7886 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7887 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7888 REGNO_REG_CLASS (REGNO (out)),
7891 /* Get the memory to use and rewrite both registers to its mode. */
7892 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7894 if (GET_MODE (loc) != GET_MODE (out))
7895 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7897 if (GET_MODE (loc) != GET_MODE (in))
7898 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7900 gen_reload (loc, in, opnum, type);
7901 gen_reload (out, loc, opnum, type);
7905 /* If IN is a simple operand, use gen_move_insn. */
7906 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7907 emit_insn (gen_move_insn (out, in));
7909 #ifdef HAVE_reload_load_address
7910 else if (HAVE_reload_load_address)
7911 emit_insn (gen_reload_load_address (out, in));
7914 /* Otherwise, just write (set OUT IN) and hope for the best. */
7916 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7918 /* Return the first insn emitted.
7919 We can not just return get_last_insn, because there may have
7920 been multiple instructions emitted. Also note that gen_move_insn may
7921 emit more than one insn itself, so we can not assume that there is one
7922 insn emitted per emit_insn_before call. */
7924 return last ? NEXT_INSN (last) : get_insns ();
7927 /* Delete a previously made output-reload
7928 whose result we now believe is not needed.
7929 First we double-check.
7931 INSN is the insn now being processed.
7932 LAST_RELOAD_REG is the hard register number for which we want to delete
7933 the last output reload.
7934 J is the reload-number that originally used REG. The caller has made
7935 certain that reload J doesn't use REG any longer for input. */
7938 delete_output_reload (insn, j, last_reload_reg)
7941 int last_reload_reg;
7943 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7944 rtx reg = spill_reg_stored_to[last_reload_reg];
7947 int n_inherited = 0;
7951 /* Get the raw pseudo-register referred to. */
7953 while (GET_CODE (reg) == SUBREG)
7954 reg = SUBREG_REG (reg);
7955 substed = reg_equiv_memory_loc[REGNO (reg)];
7957 /* This is unsafe if the operand occurs more often in the current
7958 insn than it is inherited. */
7959 for (k = n_reloads - 1; k >= 0; k--)
7961 rtx reg2 = rld[k].in;
7964 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7965 reg2 = rld[k].in_reg;
7967 if (rld[k].out && ! rld[k].out_reg)
7968 reg2 = XEXP (rld[k].in_reg, 0);
7970 while (GET_CODE (reg2) == SUBREG)
7971 reg2 = SUBREG_REG (reg2);
7972 if (rtx_equal_p (reg2, reg))
7974 if (reload_inherited[k] || reload_override_in[k] || k == j)
7977 reg2 = rld[k].out_reg;
7980 while (GET_CODE (reg2) == SUBREG)
7981 reg2 = XEXP (reg2, 0);
7982 if (rtx_equal_p (reg2, reg))
7989 n_occurrences = count_occurrences (PATTERN (insn), reg);
7991 n_occurrences += count_occurrences (PATTERN (insn), substed);
7992 if (n_occurrences > n_inherited)
7995 /* If the pseudo-reg we are reloading is no longer referenced
7996 anywhere between the store into it and here,
7997 and no jumps or labels intervene, then the value can get
7998 here through the reload reg alone.
7999 Otherwise, give up--return. */
8000 for (i1 = NEXT_INSN (output_reload_insn);
8001 i1 != insn; i1 = NEXT_INSN (i1))
8003 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
8005 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
8006 && reg_mentioned_p (reg, PATTERN (i1)))
8008 /* If this is USE in front of INSN, we only have to check that
8009 there are no more references than accounted for by inheritance. */
8010 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
8012 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8013 i1 = NEXT_INSN (i1);
8015 if (n_occurrences <= n_inherited && i1 == insn)
8021 /* The caller has already checked that REG dies or is set in INSN.
8022 It has also checked that we are optimizing, and thus some inaccurancies
8023 in the debugging information are acceptable.
8024 So we could just delete output_reload_insn.
8025 But in some cases we can improve the debugging information without
8026 sacrificing optimization - maybe even improving the code:
8027 See if the pseudo reg has been completely replaced
8028 with reload regs. If so, delete the store insn
8029 and forget we had a stack slot for the pseudo. */
8030 if (rld[j].out != rld[j].in
8031 && REG_N_DEATHS (REGNO (reg)) == 1
8032 && REG_N_SETS (REGNO (reg)) == 1
8033 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
8034 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8038 /* We know that it was used only between here
8039 and the beginning of the current basic block.
8040 (We also know that the last use before INSN was
8041 the output reload we are thinking of deleting, but never mind that.)
8042 Search that range; see if any ref remains. */
8043 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8045 rtx set = single_set (i2);
8047 /* Uses which just store in the pseudo don't count,
8048 since if they are the only uses, they are dead. */
8049 if (set != 0 && SET_DEST (set) == reg)
8051 if (GET_CODE (i2) == CODE_LABEL
8052 || GET_CODE (i2) == JUMP_INSN)
8054 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
8055 && reg_mentioned_p (reg, PATTERN (i2)))
8057 /* Some other ref remains; just delete the output reload we
8059 delete_address_reloads (output_reload_insn, insn);
8060 PUT_CODE (output_reload_insn, NOTE);
8061 NOTE_SOURCE_FILE (output_reload_insn) = 0;
8062 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
8067 /* Delete the now-dead stores into this pseudo. */
8068 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8070 rtx set = single_set (i2);
8072 if (set != 0 && SET_DEST (set) == reg)
8074 delete_address_reloads (i2, insn);
8075 /* This might be a basic block head,
8076 thus don't use delete_insn. */
8077 PUT_CODE (i2, NOTE);
8078 NOTE_SOURCE_FILE (i2) = 0;
8079 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
8081 if (GET_CODE (i2) == CODE_LABEL
8082 || GET_CODE (i2) == JUMP_INSN)
8086 /* For the debugging info,
8087 say the pseudo lives in this reload reg. */
8088 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
8089 alter_reg (REGNO (reg), -1);
8091 delete_address_reloads (output_reload_insn, insn);
8092 PUT_CODE (output_reload_insn, NOTE);
8093 NOTE_SOURCE_FILE (output_reload_insn) = 0;
8094 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
8098 /* We are going to delete DEAD_INSN. Recursively delete loads of
8099 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8100 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8102 delete_address_reloads (dead_insn, current_insn)
8103 rtx dead_insn, current_insn;
8105 rtx set = single_set (dead_insn);
8106 rtx set2, dst, prev, next;
8109 rtx dst = SET_DEST (set);
8110 if (GET_CODE (dst) == MEM)
8111 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8113 /* If we deleted the store from a reloaded post_{in,de}c expression,
8114 we can delete the matching adds. */
8115 prev = PREV_INSN (dead_insn);
8116 next = NEXT_INSN (dead_insn);
8117 if (! prev || ! next)
8119 set = single_set (next);
8120 set2 = single_set (prev);
8122 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8123 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8124 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8126 dst = SET_DEST (set);
8127 if (! rtx_equal_p (dst, SET_DEST (set2))
8128 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8129 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8130 || (INTVAL (XEXP (SET_SRC (set), 1))
8131 != - INTVAL (XEXP (SET_SRC (set2), 1))))
8137 /* Subfunction of delete_address_reloads: process registers found in X. */
8139 delete_address_reloads_1 (dead_insn, x, current_insn)
8140 rtx dead_insn, x, current_insn;
8142 rtx prev, set, dst, i2;
8144 enum rtx_code code = GET_CODE (x);
8148 const char *fmt= GET_RTX_FORMAT (code);
8149 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8152 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8153 else if (fmt[i] == 'E')
8155 for (j = XVECLEN (x, i) - 1; j >=0; j--)
8156 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8163 if (spill_reg_order[REGNO (x)] < 0)
8166 /* Scan backwards for the insn that sets x. This might be a way back due
8168 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8170 code = GET_CODE (prev);
8171 if (code == CODE_LABEL || code == JUMP_INSN)
8173 if (GET_RTX_CLASS (code) != 'i')
8175 if (reg_set_p (x, PATTERN (prev)))
8177 if (reg_referenced_p (x, PATTERN (prev)))
8180 if (! prev || INSN_UID (prev) < reload_first_uid)
8182 /* Check that PREV only sets the reload register. */
8183 set = single_set (prev);
8186 dst = SET_DEST (set);
8187 if (GET_CODE (dst) != REG
8188 || ! rtx_equal_p (dst, x))
8190 if (! reg_set_p (dst, PATTERN (dead_insn)))
8192 /* Check if DST was used in a later insn -
8193 it might have been inherited. */
8194 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8196 if (GET_CODE (i2) == CODE_LABEL)
8198 if (GET_RTX_CLASS (GET_CODE (i2)) != 'i')
8200 if (reg_referenced_p (dst, PATTERN (i2)))
8202 /* If there is a reference to the register in the current insn,
8203 it might be loaded in a non-inherited reload. If no other
8204 reload uses it, that means the register is set before
8206 if (i2 == current_insn)
8208 for (j = n_reloads - 1; j >= 0; j--)
8209 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8210 || reload_override_in[j] == dst)
8212 for (j = n_reloads - 1; j >= 0; j--)
8213 if (rld[j].in && rld[j].reg_rtx == dst)
8220 if (GET_CODE (i2) == JUMP_INSN)
8222 /* If DST is still live at CURRENT_INSN, check if it is used for
8223 any reload. Note that even if CURRENT_INSN sets DST, we still
8224 have to check the reloads. */
8225 if (i2 == current_insn)
8227 for (j = n_reloads - 1; j >= 0; j--)
8228 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8229 || reload_override_in[j] == dst)
8231 /* ??? We can't finish the loop here, because dst might be
8232 allocated to a pseudo in this block if no reload in this
8233 block needs any of the clsses containing DST - see
8234 spill_hard_reg. There is no easy way to tell this, so we
8235 have to scan till the end of the basic block. */
8237 if (reg_set_p (dst, PATTERN (i2)))
8241 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8242 reg_reloaded_contents[REGNO (dst)] = -1;
8243 /* Can't use delete_insn here because PREV might be a basic block head. */
8244 PUT_CODE (prev, NOTE);
8245 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
8246 NOTE_SOURCE_FILE (prev) = 0;
8249 /* Output reload-insns to reload VALUE into RELOADREG.
8250 VALUE is an autoincrement or autodecrement RTX whose operand
8251 is a register or memory location;
8252 so reloading involves incrementing that location.
8253 IN is either identical to VALUE, or some cheaper place to reload from.
8255 INC_AMOUNT is the number to increment or decrement by (always positive).
8256 This cannot be deduced from VALUE.
8258 Return the instruction that stores into RELOADREG. */
8261 inc_for_reload (reloadreg, in, value, inc_amount)
8266 /* REG or MEM to be copied and incremented. */
8267 rtx incloc = XEXP (value, 0);
8268 /* Nonzero if increment after copying. */
8269 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
8275 rtx real_in = in == value ? XEXP (in, 0) : in;
8277 /* No hard register is equivalent to this register after
8278 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
8279 we could inc/dec that register as well (maybe even using it for
8280 the source), but I'm not sure it's worth worrying about. */
8281 if (GET_CODE (incloc) == REG)
8282 reg_last_reload_reg[REGNO (incloc)] = 0;
8284 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8285 inc_amount = - inc_amount;
8287 inc = GEN_INT (inc_amount);
8289 /* If this is post-increment, first copy the location to the reload reg. */
8290 if (post && real_in != reloadreg)
8291 emit_insn (gen_move_insn (reloadreg, real_in));
8295 /* See if we can directly increment INCLOC. Use a method similar to
8296 that in gen_reload. */
8298 last = get_last_insn ();
8299 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8300 gen_rtx_PLUS (GET_MODE (incloc),
8303 code = recog_memoized (add_insn);
8306 extract_insn (add_insn);
8307 if (constrain_operands (1))
8309 /* If this is a pre-increment and we have incremented the value
8310 where it lives, copy the incremented value to RELOADREG to
8311 be used as an address. */
8314 emit_insn (gen_move_insn (reloadreg, incloc));
8319 delete_insns_since (last);
8322 /* If couldn't do the increment directly, must increment in RELOADREG.
8323 The way we do this depends on whether this is pre- or post-increment.
8324 For pre-increment, copy INCLOC to the reload register, increment it
8325 there, then save back. */
8329 if (in != reloadreg)
8330 emit_insn (gen_move_insn (reloadreg, real_in));
8331 emit_insn (gen_add2_insn (reloadreg, inc));
8332 store = emit_insn (gen_move_insn (incloc, reloadreg));
8337 Because this might be a jump insn or a compare, and because RELOADREG
8338 may not be available after the insn in an input reload, we must do
8339 the incrementation before the insn being reloaded for.
8341 We have already copied IN to RELOADREG. Increment the copy in
8342 RELOADREG, save that back, then decrement RELOADREG so it has
8343 the original value. */
8345 emit_insn (gen_add2_insn (reloadreg, inc));
8346 store = emit_insn (gen_move_insn (incloc, reloadreg));
8347 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8353 /* Return 1 if we are certain that the constraint-string STRING allows
8354 the hard register REG. Return 0 if we can't be sure of this. */
8357 constraint_accepts_reg_p (string, reg)
8362 int regno = true_regnum (reg);
8365 /* Initialize for first alternative. */
8367 /* Check that each alternative contains `g' or `r'. */
8369 switch (c = *string++)
8372 /* If an alternative lacks `g' or `r', we lose. */
8375 /* If an alternative lacks `g' or `r', we lose. */
8378 /* Initialize for next alternative. */
8383 /* Any general reg wins for this alternative. */
8384 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
8388 /* Any reg in specified class wins for this alternative. */
8390 enum reg_class class = REG_CLASS_FROM_LETTER (c);
8392 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
8398 /* Return the number of places FIND appears within X, but don't count
8399 an occurrence if some SET_DEST is FIND. */
8402 count_occurrences (x, find)
8403 register rtx x, find;
8406 register enum rtx_code code;
8407 register const char *format_ptr;
8415 code = GET_CODE (x);
8430 if (GET_CODE (find) == MEM && rtx_equal_p (x, find))
8434 if (SET_DEST (x) == find)
8435 return count_occurrences (SET_SRC (x), find);
8442 format_ptr = GET_RTX_FORMAT (code);
8445 for (i = 0; i < GET_RTX_LENGTH (code); i++)
8447 switch (*format_ptr++)
8450 count += count_occurrences (XEXP (x, i), find);
8454 if (XVEC (x, i) != NULL)
8456 for (j = 0; j < XVECLEN (x, i); j++)
8457 count += count_occurrences (XVECEXP (x, i, j), find);
8465 /* This array holds values which are equivalent to a hard register
8466 during reload_cse_regs. Each array element is an EXPR_LIST of
8467 values. Each time a hard register is set, we set the corresponding
8468 array element to the value. Each time a hard register is copied
8469 into memory, we add the memory location to the corresponding array
8470 element. We don't store values or memory addresses with side
8471 effects in this array.
8473 If the value is a CONST_INT, then the mode of the containing
8474 EXPR_LIST is the mode in which that CONST_INT was referenced.
8476 We sometimes clobber a specific entry in a list. In that case, we
8477 just set XEXP (list-entry, 0) to 0. */
8479 static rtx *reg_values;
8481 /* This is a preallocated REG rtx which we use as a temporary in
8482 reload_cse_invalidate_regno, so that we don't need to allocate a
8483 new one each time through a loop in that function. */
8485 static rtx invalidate_regno_rtx;
8487 /* Invalidate any entries in reg_values which depend on REGNO,
8488 including those for REGNO itself. This is called if REGNO is
8489 changing. If CLOBBER is true, then always forget anything we
8490 currently know about REGNO. MODE is the mode of the assignment to
8491 REGNO, which is used to determine how many hard registers are being
8492 changed. If MODE is VOIDmode, then only REGNO is being changed;
8493 this is used when invalidating call clobbered registers across a
8497 reload_cse_invalidate_regno (regno, mode, clobber)
8499 enum machine_mode mode;
8505 /* Our callers don't always go through true_regnum; we may see a
8506 pseudo-register here from a CLOBBER or the like. We probably
8507 won't ever see a pseudo-register that has a real register number,
8508 for we check anyhow for safety. */
8509 if (regno >= FIRST_PSEUDO_REGISTER)
8510 regno = reg_renumber[regno];
8514 if (mode == VOIDmode)
8515 endregno = regno + 1;
8517 endregno = regno + HARD_REGNO_NREGS (regno, mode);
8520 for (i = regno; i < endregno; i++)
8523 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8527 for (x = reg_values[i]; x; x = XEXP (x, 1))
8529 if (XEXP (x, 0) != 0
8530 && refers_to_regno_p (regno, endregno, XEXP (x, 0), NULL_PTR))
8532 /* If this is the only entry on the list, clear
8533 reg_values[i]. Otherwise, just clear this entry on
8535 if (XEXP (x, 1) == 0 && x == reg_values[i])
8545 /* We must look at earlier registers, in case REGNO is part of a
8546 multi word value but is not the first register. If an earlier
8547 register has a value in a mode which overlaps REGNO, then we must
8548 invalidate that earlier register. Note that we do not need to
8549 check REGNO or later registers (we must not check REGNO itself,
8550 because we would incorrectly conclude that there was a conflict). */
8552 for (i = 0; i < regno; i++)
8556 for (x = reg_values[i]; x; x = XEXP (x, 1))
8558 if (XEXP (x, 0) != 0)
8560 PUT_MODE (invalidate_regno_rtx, GET_MODE (x));
8561 REGNO (invalidate_regno_rtx) = i;
8562 if (refers_to_regno_p (regno, endregno, invalidate_regno_rtx,
8565 reload_cse_invalidate_regno (i, VOIDmode, 1);
8573 /* The memory at address MEM_BASE is being changed.
8574 Return whether this change will invalidate VAL. */
8577 reload_cse_mem_conflict_p (mem_base, val)
8585 code = GET_CODE (val);
8588 /* Get rid of a few simple cases quickly. */
8601 if (GET_MODE (mem_base) == BLKmode
8602 || GET_MODE (val) == BLKmode)
8604 if (anti_dependence (val, mem_base))
8606 /* The address may contain nested MEMs. */
8613 fmt = GET_RTX_FORMAT (code);
8615 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8619 if (reload_cse_mem_conflict_p (mem_base, XEXP (val, i)))
8622 else if (fmt[i] == 'E')
8626 for (j = 0; j < XVECLEN (val, i); j++)
8627 if (reload_cse_mem_conflict_p (mem_base, XVECEXP (val, i, j)))
8635 /* Invalidate any entries in reg_values which are changed because of a
8636 store to MEM_RTX. If this is called because of a non-const call
8637 instruction, MEM_RTX is (mem:BLK const0_rtx). */
8640 reload_cse_invalidate_mem (mem_rtx)
8645 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8649 for (x = reg_values[i]; x; x = XEXP (x, 1))
8651 if (XEXP (x, 0) != 0
8652 && reload_cse_mem_conflict_p (mem_rtx, XEXP (x, 0)))
8654 /* If this is the only entry on the list, clear
8655 reg_values[i]. Otherwise, just clear this entry on
8657 if (XEXP (x, 1) == 0 && x == reg_values[i])
8668 /* Invalidate DEST, which is being assigned to or clobbered. The
8669 second parameter exists so that this function can be passed to
8670 note_stores; it is ignored. */
8673 reload_cse_invalidate_rtx (dest, ignore)
8675 rtx ignore ATTRIBUTE_UNUSED;
8677 while (GET_CODE (dest) == STRICT_LOW_PART
8678 || GET_CODE (dest) == SIGN_EXTRACT
8679 || GET_CODE (dest) == ZERO_EXTRACT
8680 || GET_CODE (dest) == SUBREG)
8681 dest = XEXP (dest, 0);
8683 if (GET_CODE (dest) == REG)
8684 reload_cse_invalidate_regno (REGNO (dest), GET_MODE (dest), 1);
8685 else if (GET_CODE (dest) == MEM)
8686 reload_cse_invalidate_mem (dest);
8689 /* Do a very simple CSE pass over the hard registers.
8691 This function detects no-op moves where we happened to assign two
8692 different pseudo-registers to the same hard register, and then
8693 copied one to the other. Reload will generate a useless
8694 instruction copying a register to itself.
8696 This function also detects cases where we load a value from memory
8697 into two different registers, and (if memory is more expensive than
8698 registers) changes it to simply copy the first register into the
8701 Another optimization is performed that scans the operands of each
8702 instruction to see whether the value is already available in a
8703 hard register. It then replaces the operand with the hard register
8704 if possible, much like an optional reload would. */
8707 reload_cse_regs_1 (first)
8715 init_alias_analysis ();
8717 reg_values = (rtx *) alloca (FIRST_PSEUDO_REGISTER * sizeof (rtx));
8718 bzero ((char *)reg_values, FIRST_PSEUDO_REGISTER * sizeof (rtx));
8720 /* Create our EXPR_LIST structures on reload_obstack, so that we can
8721 free them when we are done. */
8722 push_obstacks (&reload_obstack, &reload_obstack);
8723 firstobj = (char *) obstack_alloc (&reload_obstack, 0);
8725 /* We pass this to reload_cse_invalidate_mem to invalidate all of
8726 memory for a non-const call instruction. */
8727 callmem = gen_rtx_MEM (BLKmode, const0_rtx);
8729 /* This is used in reload_cse_invalidate_regno to avoid consing a
8730 new REG in a loop in that function. */
8731 invalidate_regno_rtx = gen_rtx_REG (VOIDmode, 0);
8733 for (insn = first; insn; insn = NEXT_INSN (insn))
8737 if (GET_CODE (insn) == CODE_LABEL)
8739 /* Forget all the register values at a code label. We don't
8740 try to do anything clever around jumps. */
8741 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8747 #ifdef NON_SAVING_SETJMP
8748 if (NON_SAVING_SETJMP && GET_CODE (insn) == NOTE
8749 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
8751 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8758 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8761 /* If this is a call instruction, forget anything stored in a
8762 call clobbered register, or, if this is not a const call, in
8764 if (GET_CODE (insn) == CALL_INSN)
8766 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8767 if (call_used_regs[i])
8768 reload_cse_invalidate_regno (i, VOIDmode, 1);
8770 if (! CONST_CALL_P (insn))
8771 reload_cse_invalidate_mem (callmem);
8775 /* Forget all the register values at a volatile asm. */
8776 if (GET_CODE (insn) == INSN
8777 && GET_CODE (PATTERN (insn)) == ASM_OPERANDS
8778 && MEM_VOLATILE_P (PATTERN (insn)))
8779 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8782 body = PATTERN (insn);
8783 if (GET_CODE (body) == SET)
8786 if (reload_cse_noop_set_p (body, insn))
8788 /* If this sets the return value of the function, we must keep
8789 a USE around, in case this is in a different basic block
8790 than the final USE. Otherwise, we could loose important
8791 register lifeness information on SMALL_REGISTER_CLASSES
8792 machines, where return registers might be used as spills:
8793 subsequent passes assume that spill registers are dead at
8794 the end of a basic block. */
8795 if (REG_FUNCTION_VALUE_P (SET_DEST (body)))
8798 PATTERN (insn) = gen_rtx_USE (VOIDmode, SET_DEST (body));
8799 INSN_CODE (insn) = -1;
8800 REG_NOTES (insn) = NULL_RTX;
8801 push_obstacks (&reload_obstack, &reload_obstack);
8805 PUT_CODE (insn, NOTE);
8806 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8807 NOTE_SOURCE_FILE (insn) = 0;
8810 /* We're done with this insn. */
8814 /* It's not a no-op, but we can try to simplify it. */
8815 count += reload_cse_simplify_set (body, insn);
8818 apply_change_group ();
8820 reload_cse_simplify_operands (insn);
8822 reload_cse_record_set (body, body);
8824 else if (GET_CODE (body) == PARALLEL)
8827 rtx value = NULL_RTX;
8829 /* If every action in a PARALLEL is a noop, we can delete
8830 the entire PARALLEL. */
8831 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8833 rtx part = XVECEXP (body, 0, i);
8834 if (GET_CODE (part) == SET)
8836 if (! reload_cse_noop_set_p (part, insn))
8838 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8842 value = SET_DEST (part);
8845 else if (GET_CODE (part) != CLOBBER)
8853 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
8854 INSN_CODE (insn) = -1;
8855 REG_NOTES (insn) = NULL_RTX;
8856 push_obstacks (&reload_obstack, &reload_obstack);
8860 PUT_CODE (insn, NOTE);
8861 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8862 NOTE_SOURCE_FILE (insn) = 0;
8865 /* We're done with this insn. */
8869 /* It's not a no-op, but we can try to simplify it. */
8870 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8871 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8872 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8875 apply_change_group ();
8877 reload_cse_simplify_operands (insn);
8879 /* Look through the PARALLEL and record the values being
8880 set, if possible. Also handle any CLOBBERs. */
8881 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8883 rtx x = XVECEXP (body, 0, i);
8885 if (GET_CODE (x) == SET)
8886 reload_cse_record_set (x, body);
8888 note_stores (x, reload_cse_invalidate_rtx);
8892 note_stores (body, reload_cse_invalidate_rtx);
8895 /* Clobber any registers which appear in REG_INC notes. We
8896 could keep track of the changes to their values, but it is
8897 unlikely to help. */
8901 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
8902 if (REG_NOTE_KIND (x) == REG_INC)
8903 reload_cse_invalidate_rtx (XEXP (x, 0), NULL_RTX);
8907 /* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only
8908 after we have processed the insn. */
8909 if (GET_CODE (insn) == CALL_INSN)
8913 for (x = CALL_INSN_FUNCTION_USAGE (insn); x; x = XEXP (x, 1))
8914 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
8915 reload_cse_invalidate_rtx (XEXP (XEXP (x, 0), 0), NULL_RTX);
8919 /* Free all the temporary structures we created, and go back to the
8920 regular obstacks. */
8921 obstack_free (&reload_obstack, firstobj);
8925 /* Call cse / combine like post-reload optimization phases.
8926 FIRST is the first instruction. */
8928 reload_cse_regs (first)
8931 reload_cse_regs_1 (first);
8933 reload_cse_move2add (first);
8934 if (flag_expensive_optimizations)
8935 reload_cse_regs_1 (first);
8938 /* Return whether the values known for REGNO are equal to VAL. MODE
8939 is the mode of the object that VAL is being copied to; this matters
8940 if VAL is a CONST_INT. */
8943 reload_cse_regno_equal_p (regno, val, mode)
8946 enum machine_mode mode;
8953 for (x = reg_values[regno]; x; x = XEXP (x, 1))
8954 if (XEXP (x, 0) != 0
8955 && rtx_equal_p (XEXP (x, 0), val)
8956 && (! flag_float_store || GET_CODE (XEXP (x, 0)) != MEM
8957 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
8958 && (GET_CODE (val) != CONST_INT
8959 || mode == GET_MODE (x)
8960 || (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8961 /* On a big endian machine if the value spans more than
8962 one register then this register holds the high part of
8963 it and we can't use it.
8965 ??? We should also compare with the high part of the
8967 && !(WORDS_BIG_ENDIAN
8968 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
8969 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
8970 GET_MODE_BITSIZE (GET_MODE (x))))))
8976 /* See whether a single set is a noop. SET is the set instruction we
8977 are should check, and INSN is the instruction from which it came. */
8980 reload_cse_noop_set_p (set, insn)
8982 rtx insn ATTRIBUTE_UNUSED;
8985 enum machine_mode dest_mode;
8989 src = SET_SRC (set);
8990 dest = SET_DEST (set);
8991 dest_mode = GET_MODE (dest);
8993 if (side_effects_p (src))
8996 dreg = true_regnum (dest);
8997 sreg = true_regnum (src);
8999 /* Check for setting a register to itself. In this case, we don't
9000 have to worry about REG_DEAD notes. */
9001 if (dreg >= 0 && dreg == sreg)
9007 /* Check for setting a register to itself. */
9011 /* Check for setting a register to a value which we already know
9012 is in the register. */
9013 else if (reload_cse_regno_equal_p (dreg, src, dest_mode))
9016 /* Check for setting a register DREG to another register SREG
9017 where SREG is equal to a value which is already in DREG. */
9022 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
9026 if (XEXP (x, 0) == 0)
9029 if (dest_mode == GET_MODE (x))
9031 else if (GET_MODE_BITSIZE (dest_mode)
9032 < GET_MODE_BITSIZE (GET_MODE (x)))
9033 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
9038 && reload_cse_regno_equal_p (dreg, tmp, dest_mode))
9046 else if (GET_CODE (dest) == MEM)
9048 /* Check for storing a register to memory when we know that the
9049 register is equivalent to the memory location. */
9051 && reload_cse_regno_equal_p (sreg, dest, dest_mode)
9052 && ! side_effects_p (dest))
9059 /* Try to simplify a single SET instruction. SET is the set pattern.
9060 INSN is the instruction it came from.
9061 This function only handles one case: if we set a register to a value
9062 which is not a register, we try to find that value in some other register
9063 and change the set into a register copy. */
9066 reload_cse_simplify_set (set, insn)
9072 enum machine_mode dest_mode;
9073 enum reg_class dclass;
9076 dreg = true_regnum (SET_DEST (set));
9080 src = SET_SRC (set);
9081 if (side_effects_p (src) || true_regnum (src) >= 0)
9084 dclass = REGNO_REG_CLASS (dreg);
9086 /* If memory loads are cheaper than register copies, don't change them. */
9087 if (GET_CODE (src) == MEM
9088 && MEMORY_MOVE_COST (GET_MODE (src), dclass, 1) < 2)
9091 /* If the constant is cheaper than a register, don't change it. */
9092 if (CONSTANT_P (src)
9093 && rtx_cost (src, SET) < 2)
9096 dest_mode = GET_MODE (SET_DEST (set));
9097 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
9100 && REGISTER_MOVE_COST (REGNO_REG_CLASS (i), dclass) == 2
9101 && reload_cse_regno_equal_p (i, src, dest_mode))
9105 /* Pop back to the real obstacks while changing the insn. */
9108 validated = validate_change (insn, &SET_SRC (set),
9109 gen_rtx_REG (dest_mode, i), 1);
9111 /* Go back to the obstack we are using for temporary
9113 push_obstacks (&reload_obstack, &reload_obstack);
9122 /* Try to replace operands in INSN with equivalent values that are already
9123 in registers. This can be viewed as optional reloading.
9125 For each non-register operand in the insn, see if any hard regs are
9126 known to be equivalent to that operand. Record the alternatives which
9127 can accept these hard registers. Among all alternatives, select the
9128 ones which are better or equal to the one currently matching, where
9129 "better" is in terms of '?' and '!' constraints. Among the remaining
9130 alternatives, select the one which replaces most operands with
9134 reload_cse_simplify_operands (insn)
9139 const char *constraints[MAX_RECOG_OPERANDS];
9141 /* Vector recording how bad an alternative is. */
9142 int *alternative_reject;
9143 /* Vector recording how many registers can be introduced by choosing
9144 this alternative. */
9145 int *alternative_nregs;
9146 /* Array of vectors recording, for each operand and each alternative,
9147 which hard register to substitute, or -1 if the operand should be
9149 int *op_alt_regno[MAX_RECOG_OPERANDS];
9150 /* Array of alternatives, sorted in order of decreasing desirability. */
9151 int *alternative_order;
9152 rtx reg = gen_rtx_REG (VOIDmode, -1);
9154 extract_insn (insn);
9156 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
9159 /* Figure out which alternative currently matches. */
9160 if (! constrain_operands (1))
9161 fatal_insn_not_found (insn);
9163 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
9164 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
9165 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
9166 bzero ((char *)alternative_reject, recog_data.n_alternatives * sizeof (int));
9167 bzero ((char *)alternative_nregs, recog_data.n_alternatives * sizeof (int));
9169 for (i = 0; i < recog_data.n_operands; i++)
9171 enum machine_mode mode;
9175 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
9176 for (j = 0; j < recog_data.n_alternatives; j++)
9177 op_alt_regno[i][j] = -1;
9179 p = constraints[i] = recog_data.constraints[i];
9180 mode = recog_data.operand_mode[i];
9182 /* Add the reject values for each alternative given by the constraints
9183 for this operand. */
9191 alternative_reject[j] += 3;
9193 alternative_reject[j] += 300;
9196 /* We won't change operands which are already registers. We
9197 also don't want to modify output operands. */
9198 regno = true_regnum (recog_data.operand[i]);
9200 || constraints[i][0] == '='
9201 || constraints[i][0] == '+')
9204 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
9206 int class = (int) NO_REGS;
9208 if (! reload_cse_regno_equal_p (regno, recog_data.operand[i], mode))
9211 REGNO (reg) = regno;
9212 PUT_MODE (reg, mode);
9214 /* We found a register equal to this operand. Now look for all
9215 alternatives that can accept this register and have not been
9216 assigned a register they can use yet. */
9225 case '=': case '+': case '?':
9226 case '#': case '&': case '!':
9228 case '0': case '1': case '2': case '3': case '4':
9229 case '5': case '6': case '7': case '8': case '9':
9230 case 'm': case '<': case '>': case 'V': case 'o':
9231 case 'E': case 'F': case 'G': case 'H':
9232 case 's': case 'i': case 'n':
9233 case 'I': case 'J': case 'K': case 'L':
9234 case 'M': case 'N': case 'O': case 'P':
9235 #ifdef EXTRA_CONSTRAINT
9236 case 'Q': case 'R': case 'S': case 'T': case 'U':
9239 /* These don't say anything we care about. */
9243 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
9248 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
9251 case ',': case '\0':
9252 /* See if REGNO fits this alternative, and set it up as the
9253 replacement register if we don't have one for this
9254 alternative yet and the operand being replaced is not
9255 a cheap CONST_INT. */
9256 if (op_alt_regno[i][j] == -1
9257 && reg_fits_class_p (reg, class, 0, mode)
9258 && (GET_CODE (recog_data.operand[i]) != CONST_INT
9259 || (rtx_cost (recog_data.operand[i], SET)
9260 > rtx_cost (reg, SET))))
9262 alternative_nregs[j]++;
9263 op_alt_regno[i][j] = regno;
9275 /* Record all alternatives which are better or equal to the currently
9276 matching one in the alternative_order array. */
9277 for (i = j = 0; i < recog_data.n_alternatives; i++)
9278 if (alternative_reject[i] <= alternative_reject[which_alternative])
9279 alternative_order[j++] = i;
9280 recog_data.n_alternatives = j;
9282 /* Sort it. Given a small number of alternatives, a dumb algorithm
9283 won't hurt too much. */
9284 for (i = 0; i < recog_data.n_alternatives - 1; i++)
9287 int best_reject = alternative_reject[alternative_order[i]];
9288 int best_nregs = alternative_nregs[alternative_order[i]];
9291 for (j = i + 1; j < recog_data.n_alternatives; j++)
9293 int this_reject = alternative_reject[alternative_order[j]];
9294 int this_nregs = alternative_nregs[alternative_order[j]];
9296 if (this_reject < best_reject
9297 || (this_reject == best_reject && this_nregs < best_nregs))
9300 best_reject = this_reject;
9301 best_nregs = this_nregs;
9305 tmp = alternative_order[best];
9306 alternative_order[best] = alternative_order[i];
9307 alternative_order[i] = tmp;
9310 /* Substitute the operands as determined by op_alt_regno for the best
9312 j = alternative_order[0];
9314 /* Pop back to the real obstacks while changing the insn. */
9317 for (i = 0; i < recog_data.n_operands; i++)
9319 enum machine_mode mode = recog_data.operand_mode[i];
9320 if (op_alt_regno[i][j] == -1)
9323 validate_change (insn, recog_data.operand_loc[i],
9324 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
9327 for (i = recog_data.n_dups - 1; i >= 0; i--)
9329 int op = recog_data.dup_num[i];
9330 enum machine_mode mode = recog_data.operand_mode[op];
9332 if (op_alt_regno[op][j] == -1)
9335 validate_change (insn, recog_data.dup_loc[i],
9336 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
9339 /* Go back to the obstack we are using for temporary
9341 push_obstacks (&reload_obstack, &reload_obstack);
9343 return apply_change_group ();
9346 /* These two variables are used to pass information from
9347 reload_cse_record_set to reload_cse_check_clobber. */
9349 static int reload_cse_check_clobbered;
9350 static rtx reload_cse_check_src;
9352 /* See if DEST overlaps with RELOAD_CSE_CHECK_SRC. If it does, set
9353 RELOAD_CSE_CHECK_CLOBBERED. This is called via note_stores. The
9354 second argument, which is passed by note_stores, is ignored. */
9357 reload_cse_check_clobber (dest, ignore)
9359 rtx ignore ATTRIBUTE_UNUSED;
9361 if (reg_overlap_mentioned_p (dest, reload_cse_check_src))
9362 reload_cse_check_clobbered = 1;
9365 /* Record the result of a SET instruction. SET is the set pattern.
9366 BODY is the pattern of the insn that it came from. */
9369 reload_cse_record_set (set, body)
9375 enum machine_mode dest_mode;
9377 dest = SET_DEST (set);
9378 src = SET_SRC (set);
9379 dreg = true_regnum (dest);
9380 sreg = true_regnum (src);
9381 dest_mode = GET_MODE (dest);
9383 /* Some machines don't define AUTO_INC_DEC, but they still use push
9384 instructions. We need to catch that case here in order to
9385 invalidate the stack pointer correctly. Note that invalidating
9386 the stack pointer is different from invalidating DEST. */
9388 while (GET_CODE (x) == SUBREG
9389 || GET_CODE (x) == ZERO_EXTRACT
9390 || GET_CODE (x) == SIGN_EXTRACT
9391 || GET_CODE (x) == STRICT_LOW_PART)
9393 if (push_operand (x, GET_MODE (x)))
9395 reload_cse_invalidate_rtx (stack_pointer_rtx, NULL_RTX);
9396 reload_cse_invalidate_rtx (dest, NULL_RTX);
9400 /* We can only handle an assignment to a register, or a store of a
9401 register to a memory location. For other cases, we just clobber
9402 the destination. We also have to just clobber if there are side
9403 effects in SRC or DEST. */
9404 if ((dreg < 0 && GET_CODE (dest) != MEM)
9405 || side_effects_p (src)
9406 || side_effects_p (dest))
9408 reload_cse_invalidate_rtx (dest, NULL_RTX);
9413 /* We don't try to handle values involving CC, because it's a pain
9414 to keep track of when they have to be invalidated. */
9415 if (reg_mentioned_p (cc0_rtx, src)
9416 || reg_mentioned_p (cc0_rtx, dest))
9418 reload_cse_invalidate_rtx (dest, NULL_RTX);
9423 /* If BODY is a PARALLEL, then we need to see whether the source of
9424 SET is clobbered by some other instruction in the PARALLEL. */
9425 if (GET_CODE (body) == PARALLEL)
9429 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
9433 x = XVECEXP (body, 0, i);
9437 reload_cse_check_clobbered = 0;
9438 reload_cse_check_src = src;
9439 note_stores (x, reload_cse_check_clobber);
9440 if (reload_cse_check_clobbered)
9442 reload_cse_invalidate_rtx (dest, NULL_RTX);
9452 /* This is an assignment to a register. Update the value we
9453 have stored for the register. */
9458 /* This is a copy from one register to another. Any values
9459 which were valid for SREG are now valid for DREG. If the
9460 mode changes, we use gen_lowpart_common to extract only
9461 the part of the value that is copied. */
9462 reg_values[dreg] = 0;
9463 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
9467 if (XEXP (x, 0) == 0)
9469 if (dest_mode == GET_MODE (XEXP (x, 0)))
9471 else if (GET_MODE_BITSIZE (dest_mode)
9472 > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
9475 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
9477 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, tmp,
9482 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, src, NULL_RTX);
9484 /* We've changed DREG, so invalidate any values held by other
9485 registers that depend upon it. */
9486 reload_cse_invalidate_regno (dreg, dest_mode, 0);
9488 /* If this assignment changes more than one hard register,
9489 forget anything we know about the others. */
9490 for (i = 1; i < HARD_REGNO_NREGS (dreg, dest_mode); i++)
9491 reg_values[dreg + i] = 0;
9493 else if (GET_CODE (dest) == MEM)
9495 /* Invalidate conflicting memory locations. */
9496 reload_cse_invalidate_mem (dest);
9498 /* If we're storing a register to memory, add DEST to the list
9500 if (sreg >= 0 && ! side_effects_p (dest))
9501 reg_values[sreg] = gen_rtx_EXPR_LIST (dest_mode, dest,
9506 /* We should have bailed out earlier. */
9511 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
9513 This code might also be useful when reload gave up on reg+reg addresssing
9514 because of clashes between the return register and INDEX_REG_CLASS. */
9516 /* The maximum number of uses of a register we can keep track of to
9517 replace them with reg+reg addressing. */
9518 #define RELOAD_COMBINE_MAX_USES 6
9520 /* INSN is the insn where a register has ben used, and USEP points to the
9521 location of the register within the rtl. */
9522 struct reg_use { rtx insn, *usep; };
9524 /* If the register is used in some unknown fashion, USE_INDEX is negative.
9525 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
9526 indicates where it becomes live again.
9527 Otherwise, USE_INDEX is the index of the last encountered use of the
9528 register (which is first among these we have seen since we scan backwards),
9529 OFFSET contains the constant offset that is added to the register in
9530 all encountered uses, and USE_RUID indicates the first encountered, i.e.
9531 last, of these uses.
9532 STORE_RUID is always meaningful if we only want to use a value in a
9533 register in a different place: it denotes the next insn in the insn
9534 stream (i.e. the last ecountered) that sets or clobbers the register. */
9537 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
9542 } reg_state[FIRST_PSEUDO_REGISTER];
9544 /* Reverse linear uid. This is increased in reload_combine while scanning
9545 the instructions from last to first. It is used to set last_label_ruid
9546 and the store_ruid / use_ruid fields in reg_state. */
9547 static int reload_combine_ruid;
9549 #define LABEL_LIVE(LABEL) \
9550 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
9556 int first_index_reg = 1, last_index_reg = 0;
9558 int last_label_ruid;
9559 int min_labelno, n_labels;
9560 HARD_REG_SET ever_live_at_start, *label_live;
9562 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
9563 reload has already used it where appropriate, so there is no use in
9564 trying to generate it now. */
9565 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
9568 /* To avoid wasting too much time later searching for an index register,
9569 determine the minimum and maximum index register numbers. */
9570 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9572 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i))
9574 if (! last_index_reg)
9576 first_index_reg = i;
9579 /* If no index register is available, we can quit now. */
9580 if (first_index_reg > last_index_reg)
9583 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
9584 information is a bit fuzzy immediately after reload, but it's
9585 still good enough to determine which registers are live at a jump
9587 min_labelno = get_first_label_num ();
9588 n_labels = max_label_num () - min_labelno;
9589 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
9590 CLEAR_HARD_REG_SET (ever_live_at_start);
9591 for (i = n_basic_blocks - 1; i >= 0; i--)
9593 insn = BLOCK_HEAD (i);
9594 if (GET_CODE (insn) == CODE_LABEL)
9598 REG_SET_TO_HARD_REG_SET (live, BASIC_BLOCK (i)->global_live_at_start);
9599 compute_use_by_pseudos (&live, BASIC_BLOCK (i)->global_live_at_start);
9600 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
9601 IOR_HARD_REG_SET (ever_live_at_start, live);
9605 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
9606 last_label_ruid = reload_combine_ruid = 0;
9607 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9609 reg_state[i].store_ruid = reload_combine_ruid;
9611 reg_state[i].use_index = -1;
9613 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9616 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
9620 /* We cannot do our optimization across labels. Invalidating all the use
9621 information we have would be costly, so we just note where the label
9622 is and then later disable any optimization that would cross it. */
9623 if (GET_CODE (insn) == CODE_LABEL)
9624 last_label_ruid = reload_combine_ruid;
9625 if (GET_CODE (insn) == BARRIER)
9627 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9628 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9630 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
9632 reload_combine_ruid++;
9634 /* Look for (set (REGX) (CONST_INT))
9635 (set (REGX) (PLUS (REGX) (REGY)))
9637 ... (MEM (REGX)) ...
9639 (set (REGZ) (CONST_INT))
9641 ... (MEM (PLUS (REGZ) (REGY)))... .
9643 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
9644 and that we know all uses of REGX before it dies. */
9645 set = single_set (insn);
9647 && GET_CODE (SET_DEST (set)) == REG
9648 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
9649 GET_MODE (SET_DEST (set)))
9651 && GET_CODE (SET_SRC (set)) == PLUS
9652 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
9653 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
9654 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
9656 rtx reg = SET_DEST (set);
9657 rtx plus = SET_SRC (set);
9658 rtx base = XEXP (plus, 1);
9659 rtx prev = prev_nonnote_insn (insn);
9660 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
9661 int regno = REGNO (reg);
9662 rtx const_reg = NULL_RTX;
9663 rtx reg_sum = NULL_RTX;
9665 /* Now, we need an index register.
9666 We'll set index_reg to this index register, const_reg to the
9667 register that is to be loaded with the constant
9668 (denoted as REGZ in the substitution illustration above),
9669 and reg_sum to the register-register that we want to use to
9670 substitute uses of REG (typically in MEMs) with.
9671 First check REG and BASE for being index registers;
9672 we can use them even if they are not dead. */
9673 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
9674 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
9682 /* Otherwise, look for a free index register. Since we have
9683 checked above that neiter REG nor BASE are index registers,
9684 if we find anything at all, it will be different from these
9686 for (i = first_index_reg; i <= last_index_reg; i++)
9688 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
9689 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
9690 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
9691 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
9693 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
9694 const_reg = index_reg;
9695 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
9700 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
9701 (REGY), i.e. BASE, is not clobbered before the last use we'll
9704 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
9705 && rtx_equal_p (SET_DEST (prev_set), reg)
9706 && reg_state[regno].use_index >= 0
9707 && reg_state[REGNO (base)].store_ruid <= reg_state[regno].use_ruid
9712 /* Change destination register and - if necessary - the
9713 constant value in PREV, the constant loading instruction. */
9714 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
9715 if (reg_state[regno].offset != const0_rtx)
9716 validate_change (prev,
9717 &SET_SRC (prev_set),
9718 GEN_INT (INTVAL (SET_SRC (prev_set))
9719 + INTVAL (reg_state[regno].offset)),
9721 /* Now for every use of REG that we have recorded, replace REG
9723 for (i = reg_state[regno].use_index;
9724 i < RELOAD_COMBINE_MAX_USES; i++)
9725 validate_change (reg_state[regno].reg_use[i].insn,
9726 reg_state[regno].reg_use[i].usep,
9729 if (apply_change_group ())
9733 /* Delete the reg-reg addition. */
9734 PUT_CODE (insn, NOTE);
9735 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9736 NOTE_SOURCE_FILE (insn) = 0;
9738 if (reg_state[regno].offset != const0_rtx)
9740 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
9742 for (np = ®_NOTES (prev); *np; )
9744 if (REG_NOTE_KIND (*np) == REG_EQUAL
9745 || REG_NOTE_KIND (*np) == REG_EQUIV)
9746 *np = XEXP (*np, 1);
9748 np = &XEXP (*np, 1);
9751 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9752 reg_state[REGNO (const_reg)].store_ruid = reload_combine_ruid;
9757 note_stores (PATTERN (insn), reload_combine_note_store);
9758 if (GET_CODE (insn) == CALL_INSN)
9762 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9764 if (call_used_regs[i])
9766 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9767 reg_state[i].store_ruid = reload_combine_ruid;
9770 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
9771 link = XEXP (link, 1))
9773 rtx use = XEXP (link, 0);
9774 int regno = REGNO (XEXP (use, 0));
9775 if (GET_CODE (use) == CLOBBER)
9777 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9778 reg_state[regno].store_ruid = reload_combine_ruid;
9781 reg_state[regno].use_index = -1;
9784 if (GET_CODE (insn) == JUMP_INSN && GET_CODE (PATTERN (insn)) != RETURN)
9786 /* Non-spill registers might be used at the call destination in
9787 some unknown fashion, so we have to mark the unknown use. */
9789 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
9790 && JUMP_LABEL (insn))
9791 live = &LABEL_LIVE (JUMP_LABEL (insn));
9793 live = &ever_live_at_start;
9794 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9796 if (TEST_HARD_REG_BIT (*live, i))
9797 reg_state[i].use_index = -1;
9800 reload_combine_note_use (&PATTERN (insn), insn);
9801 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9803 if (REG_NOTE_KIND (note) == REG_INC
9804 && GET_CODE (XEXP (note, 0)) == REG)
9806 int regno = REGNO (XEXP (note, 0));
9808 reg_state[regno].store_ruid = reload_combine_ruid;
9809 reg_state[regno].use_index = -1;
9816 /* Check if DST is a register or a subreg of a register; if it is,
9817 update reg_state[regno].store_ruid and reg_state[regno].use_index
9818 accordingly. Called via note_stores from reload_combine. */
9820 reload_combine_note_store (dst, set)
9825 unsigned size = GET_MODE_SIZE (GET_MODE (dst));
9827 if (GET_CODE (dst) == SUBREG)
9829 regno = SUBREG_WORD (dst);
9830 dst = SUBREG_REG (dst);
9832 if (GET_CODE (dst) != REG)
9834 regno += REGNO (dst);
9836 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
9837 careful with registers / register parts that are not full words.
9839 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
9840 if (GET_CODE (set) != SET
9841 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
9842 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
9843 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
9845 for (i = (size - 1) / UNITS_PER_WORD + regno; i >= regno; i--)
9847 reg_state[i].use_index = -1;
9848 reg_state[i].store_ruid = reload_combine_ruid;
9853 for (i = (size - 1) / UNITS_PER_WORD + regno; i >= regno; i--)
9855 reg_state[i].store_ruid = reload_combine_ruid;
9856 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9861 /* XP points to a piece of rtl that has to be checked for any uses of
9863 *XP is the pattern of INSN, or a part of it.
9864 Called from reload_combine, and recursively by itself. */
9866 reload_combine_note_use (xp, insn)
9870 enum rtx_code code = x->code;
9873 rtx offset = const0_rtx; /* For the REG case below. */
9878 if (GET_CODE (SET_DEST (x)) == REG)
9880 reload_combine_note_use (&SET_SRC (x), insn);
9886 if (GET_CODE (SET_DEST (x)) == REG)
9891 /* We are interested in (plus (reg) (const_int)) . */
9892 if (GET_CODE (XEXP (x, 0)) != REG || GET_CODE (XEXP (x, 1)) != CONST_INT)
9894 offset = XEXP (x, 1);
9899 int regno = REGNO (x);
9902 /* Some spurious USEs of pseudo registers might remain.
9903 Just ignore them. */
9904 if (regno >= FIRST_PSEUDO_REGISTER)
9907 /* If this register is already used in some unknown fashion, we
9909 If we decrement the index from zero to -1, we can't store more
9910 uses, so this register becomes used in an unknown fashion. */
9911 use_index = --reg_state[regno].use_index;
9915 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
9917 /* We have found another use for a register that is already
9918 used later. Check if the offsets match; if not, mark the
9919 register as used in an unknown fashion. */
9920 if (! rtx_equal_p (offset, reg_state[regno].offset))
9922 reg_state[regno].use_index = -1;
9928 /* This is the first use of this register we have seen since we
9929 marked it as dead. */
9930 reg_state[regno].offset = offset;
9931 reg_state[regno].use_ruid = reload_combine_ruid;
9933 reg_state[regno].reg_use[use_index].insn = insn;
9934 reg_state[regno].reg_use[use_index].usep = xp;
9942 /* Recursively process the components of X. */
9943 fmt = GET_RTX_FORMAT (code);
9944 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9947 reload_combine_note_use (&XEXP (x, i), insn);
9948 else if (fmt[i] == 'E')
9950 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9951 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9956 /* See if we can reduce the cost of a constant by replacing a move with
9958 /* We cannot do our optimization across labels. Invalidating all the
9959 information about register contents we have would be costly, so we
9960 use last_label_luid (local variable of reload_cse_move2add) to note
9961 where the label is and then later disable any optimization that would
9963 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9964 reg_set_luid[n] is larger than last_label_luid[n] . */
9965 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9966 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
9967 reg_mode[n] to be valid.
9968 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
9969 has been set to reg_offset[n] in mode reg_mode[n] .
9970 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
9971 register n has been set to the sum of reg_offset[n] and register
9972 reg_base_reg[n], calculated in mode reg_mode[n] . */
9973 static rtx reg_offset[FIRST_PSEUDO_REGISTER];
9974 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9975 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9976 /* move2add_luid is linearily increased while scanning the instructions
9977 from first to last. It is used to set reg_set_luid in
9978 reload_cse_move2add and move2add_note_store. */
9979 static int move2add_luid;
9981 /* Generate a CONST_INT and force it in the range of MODE. */
9983 gen_mode_int (mode, value)
9984 enum machine_mode mode;
9985 HOST_WIDE_INT value;
9987 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
9988 int width = GET_MODE_BITSIZE (mode);
9990 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
9992 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
9993 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
9994 cval |= (HOST_WIDE_INT) -1 << width;
9996 return GEN_INT (cval);
10000 reload_cse_move2add (first)
10005 int last_label_luid;
10007 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
10008 reg_set_luid[i] = 0;
10010 last_label_luid = 0;
10012 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
10016 if (GET_CODE (insn) == CODE_LABEL)
10017 last_label_luid = move2add_luid;
10018 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
10020 pat = PATTERN (insn);
10021 /* For simplicity, we only perform this optimization on
10022 straightforward SETs. */
10023 if (GET_CODE (pat) == SET
10024 && GET_CODE (SET_DEST (pat)) == REG)
10026 rtx reg = SET_DEST (pat);
10027 int regno = REGNO (reg);
10028 rtx src = SET_SRC (pat);
10030 /* Check if we have valid information on the contents of this
10031 register in the mode of REG. */
10032 /* ??? We don't know how zero / sign extension is handled, hence
10033 we can't go from a narrower to a wider mode. */
10034 if (reg_set_luid[regno] > last_label_luid
10035 && (GET_MODE_SIZE (GET_MODE (reg))
10036 <= GET_MODE_SIZE (reg_mode[regno]))
10037 && GET_CODE (reg_offset[regno]) == CONST_INT)
10039 /* Try to transform (set (REGX) (CONST_INT A))
10041 (set (REGX) (CONST_INT B))
10043 (set (REGX) (CONST_INT A))
10045 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
10047 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
10051 = gen_mode_int (GET_MODE (reg),
10052 INTVAL (src) - INTVAL (reg_offset[regno]));
10053 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
10054 use (set (reg) (reg)) instead.
10055 We don't delete this insn, nor do we convert it into a
10056 note, to avoid losing register notes or the return
10057 value flag. jump2 already knowns how to get rid of
10059 if (new_src == const0_rtx)
10060 success = validate_change (insn, &SET_SRC (pat), reg, 0);
10061 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
10062 && have_add2_insn (GET_MODE (reg)))
10063 success = validate_change (insn, &PATTERN (insn),
10064 gen_add2_insn (reg, new_src), 0);
10065 reg_set_luid[regno] = move2add_luid;
10066 reg_mode[regno] = GET_MODE (reg);
10067 reg_offset[regno] = src;
10071 /* Try to transform (set (REGX) (REGY))
10072 (set (REGX) (PLUS (REGX) (CONST_INT A)))
10074 (set (REGX) (REGY))
10075 (set (REGX) (PLUS (REGX) (CONST_INT B)))
10078 (set (REGX) (PLUS (REGX) (CONST_INT A)))
10080 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
10081 else if (GET_CODE (src) == REG
10082 && reg_base_reg[regno] == REGNO (src)
10083 && reg_set_luid[regno] > reg_set_luid[REGNO (src)])
10085 rtx next = next_nonnote_insn (insn);
10086 rtx set = NULL_RTX;
10088 set = single_set (next);
10091 && SET_DEST (set) == reg
10092 && GET_CODE (SET_SRC (set)) == PLUS
10093 && XEXP (SET_SRC (set), 0) == reg
10094 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
10096 rtx src3 = XEXP (SET_SRC (set), 1);
10098 = gen_mode_int (GET_MODE (reg),
10100 - INTVAL (reg_offset[regno]));
10103 if (new_src == const0_rtx)
10104 /* See above why we create (set (reg) (reg)) here. */
10106 = validate_change (next, &SET_SRC (set), reg, 0);
10107 else if ((rtx_cost (new_src, PLUS)
10108 < 2 + rtx_cost (src3, SET))
10109 && have_add2_insn (GET_MODE (reg)))
10111 = validate_change (next, &PATTERN (next),
10112 gen_add2_insn (reg, new_src), 0);
10115 /* INSN might be the first insn in a basic block
10116 if the preceding insn is a conditional jump
10117 or a possible-throwing call. */
10118 PUT_CODE (insn, NOTE);
10119 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
10120 NOTE_SOURCE_FILE (insn) = 0;
10123 reg_set_luid[regno] = move2add_luid;
10124 reg_mode[regno] = GET_MODE (reg);
10125 reg_offset[regno] = src3;
10132 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
10134 if (REG_NOTE_KIND (note) == REG_INC
10135 && GET_CODE (XEXP (note, 0)) == REG)
10137 /* Indicate that this register has been recently written to,
10138 but the exact contents are not available. */
10139 int regno = REGNO (XEXP (note, 0));
10140 if (regno < FIRST_PSEUDO_REGISTER)
10142 reg_set_luid[regno] = move2add_luid;
10143 reg_offset[regno] = note;
10147 note_stores (PATTERN (insn), move2add_note_store);
10148 /* If this is a CALL_INSN, all call used registers are stored with
10150 if (GET_CODE (insn) == CALL_INSN)
10152 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
10154 if (call_used_regs[i])
10156 reg_set_luid[i] = move2add_luid;
10157 reg_offset[i] = insn; /* Invalidate contents. */
10164 /* SET is a SET or CLOBBER that sets DST.
10165 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
10166 Called from reload_cse_move2add via note_stores. */
10168 move2add_note_store (dst, set)
10174 enum machine_mode mode = GET_MODE (dst);
10175 if (GET_CODE (dst) == SUBREG)
10177 regno = SUBREG_WORD (dst);
10178 dst = SUBREG_REG (dst);
10180 if (GET_CODE (dst) != REG)
10183 regno += REGNO (dst);
10185 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
10186 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
10187 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
10188 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
10190 rtx src = SET_SRC (set);
10192 reg_mode[regno] = mode;
10193 switch (GET_CODE (src))
10197 rtx src0 = XEXP (src, 0);
10198 if (GET_CODE (src0) == REG)
10200 if (REGNO (src0) != regno
10201 || reg_offset[regno] != const0_rtx)
10203 reg_base_reg[regno] = REGNO (src0);
10204 reg_set_luid[regno] = move2add_luid;
10206 reg_offset[regno] = XEXP (src, 1);
10209 reg_set_luid[regno] = move2add_luid;
10210 reg_offset[regno] = set; /* Invalidate contents. */
10215 reg_base_reg[regno] = REGNO (SET_SRC (set));
10216 reg_offset[regno] = const0_rtx;
10217 reg_set_luid[regno] = move2add_luid;
10221 reg_base_reg[regno] = -1;
10222 reg_offset[regno] = SET_SRC (set);
10223 reg_set_luid[regno] = move2add_luid;
10229 for (i = regno + HARD_REGNO_NREGS (regno, mode) - 1; i >= regno; i--)
10231 /* Indicate that this register has been recently written to,
10232 but the exact contents are not available. */
10233 reg_set_luid[i] = move2add_luid;
10234 reg_offset[i] = dst;
10239 #ifdef AUTO_INC_DEC
10241 add_auto_inc_notes (insn, x)
10245 enum rtx_code code = GET_CODE (x);
10249 if (code == MEM && auto_inc_p (XEXP (x, 0)))
10252 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
10256 /* Scan all the operand sub-expressions. */
10257 fmt = GET_RTX_FORMAT (code);
10258 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10261 add_auto_inc_notes (insn, XEXP (x, i));
10262 else if (fmt[i] == 'E')
10263 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10264 add_auto_inc_notes (insn, XVECEXP (x, i, j));