1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "addresses.h"
39 #include "basic-block.h"
52 /* This file contains the reload pass of the compiler, which is
53 run after register allocation has been done. It checks that
54 each insn is valid (operands required to be in registers really
55 are in registers of the proper class) and fixes up invalid ones
56 by copying values temporarily into registers for the insns
59 The results of register allocation are described by the vector
60 reg_renumber; the insns still contain pseudo regs, but reg_renumber
61 can be used to find which hard reg, if any, a pseudo reg is in.
63 The technique we always use is to free up a few hard regs that are
64 called ``reload regs'', and for each place where a pseudo reg
65 must be in a hard reg, copy it temporarily into one of the reload regs.
67 Reload regs are allocated locally for every instruction that needs
68 reloads. When there are pseudos which are allocated to a register that
69 has been chosen as a reload reg, such pseudos must be ``spilled''.
70 This means that they go to other hard regs, or to stack slots if no other
71 available hard regs can be found. Spilling can invalidate more
72 insns, requiring additional need for reloads, so we must keep checking
73 until the process stabilizes.
75 For machines with different classes of registers, we must keep track
76 of the register class needed for each reload, and make sure that
77 we allocate enough reload registers of each class.
79 The file reload.c contains the code that checks one insn for
80 validity and reports the reloads that it needs. This file
81 is in charge of scanning the entire rtl code, accumulating the
82 reload needs, spilling, assigning reload registers to use for
83 fixing up each insn, and generating the new insns to copy values
84 into the reload registers. */
86 /* During reload_as_needed, element N contains a REG rtx for the hard reg
87 into which reg N has been reloaded (perhaps for a previous insn). */
88 static rtx *reg_last_reload_reg;
90 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
91 for an output reload that stores into reg N. */
92 static regset_head reg_has_output_reload;
94 /* Indicates which hard regs are reload-registers for an output reload
95 in the current insn. */
96 static HARD_REG_SET reg_is_output_reload;
98 /* Element N is the constant value to which pseudo reg N is equivalent,
99 or zero if pseudo reg N is not equivalent to a constant.
100 find_reloads looks at this in order to replace pseudo reg N
101 with the constant it stands for. */
102 rtx *reg_equiv_constant;
104 /* Element N is an invariant value to which pseudo reg N is equivalent.
105 eliminate_regs_in_insn uses this to replace pseudos in particular
107 rtx *reg_equiv_invariant;
109 /* Element N is a memory location to which pseudo reg N is equivalent,
110 prior to any register elimination (such as frame pointer to stack
111 pointer). Depending on whether or not it is a valid address, this value
112 is transferred to either reg_equiv_address or reg_equiv_mem. */
113 rtx *reg_equiv_memory_loc;
115 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
116 collector can keep track of what is inside. */
117 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
119 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
120 This is used when the address is not valid as a memory address
121 (because its displacement is too big for the machine.) */
122 rtx *reg_equiv_address;
124 /* Element N is the memory slot to which pseudo reg N is equivalent,
125 or zero if pseudo reg N is not equivalent to a memory slot. */
128 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
129 alternate representations of the location of pseudo reg N. */
130 rtx *reg_equiv_alt_mem_list;
132 /* Widest width in which each pseudo reg is referred to (via subreg). */
133 static unsigned int *reg_max_ref_width;
135 /* Element N is the list of insns that initialized reg N from its equivalent
136 constant or memory slot. */
138 int reg_equiv_init_size;
140 /* Vector to remember old contents of reg_renumber before spilling. */
141 static short *reg_old_renumber;
143 /* During reload_as_needed, element N contains the last pseudo regno reloaded
144 into hard register N. If that pseudo reg occupied more than one register,
145 reg_reloaded_contents points to that pseudo for each spill register in
146 use; all of these must remain set for an inheritance to occur. */
147 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
149 /* During reload_as_needed, element N contains the insn for which
150 hard register N was last used. Its contents are significant only
151 when reg_reloaded_valid is set for this register. */
152 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
154 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
155 static HARD_REG_SET reg_reloaded_valid;
156 /* Indicate if the register was dead at the end of the reload.
157 This is only valid if reg_reloaded_contents is set and valid. */
158 static HARD_REG_SET reg_reloaded_dead;
160 /* Indicate whether the register's current value is one that is not
161 safe to retain across a call, even for registers that are normally
162 call-saved. This is only meaningful for members of reg_reloaded_valid. */
163 static HARD_REG_SET reg_reloaded_call_part_clobbered;
165 /* Number of spill-regs so far; number of valid elements of spill_regs. */
168 /* In parallel with spill_regs, contains REG rtx's for those regs.
169 Holds the last rtx used for any given reg, or 0 if it has never
170 been used for spilling yet. This rtx is reused, provided it has
172 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
174 /* In parallel with spill_regs, contains nonzero for a spill reg
175 that was stored after the last time it was used.
176 The precise value is the insn generated to do the store. */
177 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
179 /* This is the register that was stored with spill_reg_store. This is a
180 copy of reload_out / reload_out_reg when the value was stored; if
181 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
182 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
184 /* This table is the inverse mapping of spill_regs:
185 indexed by hard reg number,
186 it contains the position of that reg in spill_regs,
187 or -1 for something that is not in spill_regs.
189 ?!? This is no longer accurate. */
190 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
192 /* This reg set indicates registers that can't be used as spill registers for
193 the currently processed insn. These are the hard registers which are live
194 during the insn, but not allocated to pseudos, as well as fixed
196 static HARD_REG_SET bad_spill_regs;
198 /* These are the hard registers that can't be used as spill register for any
199 insn. This includes registers used for user variables and registers that
200 we can't eliminate. A register that appears in this set also can't be used
201 to retry register allocation. */
202 static HARD_REG_SET bad_spill_regs_global;
204 /* Describes order of use of registers for reloading
205 of spilled pseudo-registers. `n_spills' is the number of
206 elements that are actually valid; new ones are added at the end.
208 Both spill_regs and spill_reg_order are used on two occasions:
209 once during find_reload_regs, where they keep track of the spill registers
210 for a single insn, but also during reload_as_needed where they show all
211 the registers ever used by reload. For the latter case, the information
212 is calculated during finish_spills. */
213 static short spill_regs[FIRST_PSEUDO_REGISTER];
215 /* This vector of reg sets indicates, for each pseudo, which hard registers
216 may not be used for retrying global allocation because the register was
217 formerly spilled from one of them. If we allowed reallocating a pseudo to
218 a register that it was already allocated to, reload might not
220 static HARD_REG_SET *pseudo_previous_regs;
222 /* This vector of reg sets indicates, for each pseudo, which hard
223 registers may not be used for retrying global allocation because they
224 are used as spill registers during one of the insns in which the
226 static HARD_REG_SET *pseudo_forbidden_regs;
228 /* All hard regs that have been used as spill registers for any insn are
229 marked in this set. */
230 static HARD_REG_SET used_spill_regs;
232 /* Index of last register assigned as a spill register. We allocate in
233 a round-robin fashion. */
234 static int last_spill_reg;
236 /* Nonzero if indirect addressing is supported on the machine; this means
237 that spilling (REG n) does not require reloading it into a register in
238 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
239 value indicates the level of indirect addressing supported, e.g., two
240 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
242 static char spill_indirect_levels;
244 /* Nonzero if indirect addressing is supported when the innermost MEM is
245 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
246 which these are valid is the same as spill_indirect_levels, above. */
247 char indirect_symref_ok;
249 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
250 char double_reg_address_ok;
252 /* Record the stack slot for each spilled hard register. */
253 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
255 /* Width allocated so far for that stack slot. */
256 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
258 /* Record which pseudos needed to be spilled. */
259 static regset_head spilled_pseudos;
261 /* Record which pseudos changed their allocation in finish_spills. */
262 static regset_head changed_allocation_pseudos;
264 /* Used for communication between order_regs_for_reload and count_pseudo.
265 Used to avoid counting one pseudo twice. */
266 static regset_head pseudos_counted;
268 /* First uid used by insns created by reload in this function.
269 Used in find_equiv_reg. */
270 int reload_first_uid;
272 /* Flag set by local-alloc or global-alloc if anything is live in
273 a call-clobbered reg across calls. */
274 int caller_save_needed;
276 /* Set to 1 while reload_as_needed is operating.
277 Required by some machines to handle any generated moves differently. */
278 int reload_in_progress = 0;
280 /* These arrays record the insn_code of insns that may be needed to
281 perform input and output reloads of special objects. They provide a
282 place to pass a scratch register. */
283 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
284 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
286 /* This obstack is used for allocation of rtl during register elimination.
287 The allocated storage can be freed once find_reloads has processed the
289 static struct obstack reload_obstack;
291 /* Points to the beginning of the reload_obstack. All insn_chain structures
292 are allocated first. */
293 static char *reload_startobj;
295 /* The point after all insn_chain structures. Used to quickly deallocate
296 memory allocated in copy_reloads during calculate_needs_all_insns. */
297 static char *reload_firstobj;
299 /* This points before all local rtl generated by register elimination.
300 Used to quickly free all memory after processing one insn. */
301 static char *reload_insn_firstobj;
303 /* List of insn_chain instructions, one for every insn that reload needs to
305 struct insn_chain *reload_insn_chain;
307 /* List of all insns needing reloads. */
308 static struct insn_chain *insns_need_reload;
310 /* This structure is used to record information about register eliminations.
311 Each array entry describes one possible way of eliminating a register
312 in favor of another. If there is more than one way of eliminating a
313 particular register, the most preferred should be specified first. */
317 int from; /* Register number to be eliminated. */
318 int to; /* Register number used as replacement. */
319 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
320 int can_eliminate; /* Nonzero if this elimination can be done. */
321 int can_eliminate_previous; /* Value returned by TARGET_CAN_ELIMINATE
322 target hook in previous scan over insns
324 HOST_WIDE_INT offset; /* Current offset between the two regs. */
325 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
326 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
327 rtx from_rtx; /* REG rtx for the register to be eliminated.
328 We cannot simply compare the number since
329 we might then spuriously replace a hard
330 register corresponding to a pseudo
331 assigned to the reg to be eliminated. */
332 rtx to_rtx; /* REG rtx for the replacement. */
335 static struct elim_table *reg_eliminate = 0;
337 /* This is an intermediate structure to initialize the table. It has
338 exactly the members provided by ELIMINABLE_REGS. */
339 static const struct elim_table_1
343 } reg_eliminate_1[] =
345 /* If a set of eliminable registers was specified, define the table from it.
346 Otherwise, default to the normal case of the frame pointer being
347 replaced by the stack pointer. */
349 #ifdef ELIMINABLE_REGS
352 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
355 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
357 /* Record the number of pending eliminations that have an offset not equal
358 to their initial offset. If nonzero, we use a new copy of each
359 replacement result in any insns encountered. */
360 int num_not_at_initial_offset;
362 /* Count the number of registers that we may be able to eliminate. */
363 static int num_eliminable;
364 /* And the number of registers that are equivalent to a constant that
365 can be eliminated to frame_pointer / arg_pointer + constant. */
366 static int num_eliminable_invariants;
368 /* For each label, we record the offset of each elimination. If we reach
369 a label by more than one path and an offset differs, we cannot do the
370 elimination. This information is indexed by the difference of the
371 number of the label and the first label number. We can't offset the
372 pointer itself as this can cause problems on machines with segmented
373 memory. The first table is an array of flags that records whether we
374 have yet encountered a label and the second table is an array of arrays,
375 one entry in the latter array for each elimination. */
377 static int first_label_num;
378 static char *offsets_known_at;
379 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
381 /* Stack of addresses where an rtx has been changed. We can undo the
382 changes by popping items off the stack and restoring the original
383 value at each location.
385 We use this simplistic undo capability rather than copy_rtx as copy_rtx
386 will not make a deep copy of a normally sharable rtx, such as
387 (const (plus (symbol_ref) (const_int))). If such an expression appears
388 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
389 rtx expression would be changed. See PR 42431. */
393 DEF_VEC_ALLOC_P(rtx_p,heap);
394 static VEC(rtx_p,heap) *substitute_stack;
396 /* Number of labels in the current function. */
398 static int num_labels;
400 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
401 static void maybe_fix_stack_asms (void);
402 static void copy_reloads (struct insn_chain *);
403 static void calculate_needs_all_insns (int);
404 static int find_reg (struct insn_chain *, int);
405 static void find_reload_regs (struct insn_chain *);
406 static void select_reload_regs (void);
407 static void delete_caller_save_insns (void);
409 static void spill_failure (rtx, enum reg_class);
410 static void count_spilled_pseudo (int, int, int);
411 static void delete_dead_insn (rtx);
412 static void alter_reg (int, int, bool);
413 static void set_label_offsets (rtx, rtx, int);
414 static void check_eliminable_occurrences (rtx);
415 static void elimination_effects (rtx, enum machine_mode);
416 static int eliminate_regs_in_insn (rtx, int);
417 static void update_eliminable_offsets (void);
418 static void mark_not_eliminable (rtx, const_rtx, void *);
419 static void set_initial_elim_offsets (void);
420 static bool verify_initial_elim_offsets (void);
421 static void set_initial_label_offsets (void);
422 static void set_offsets_for_label (rtx);
423 static void init_elim_table (void);
424 static void update_eliminables (HARD_REG_SET *);
425 static void spill_hard_reg (unsigned int, int);
426 static int finish_spills (int);
427 static void scan_paradoxical_subregs (rtx);
428 static void count_pseudo (int);
429 static void order_regs_for_reload (struct insn_chain *);
430 static void reload_as_needed (int);
431 static void forget_old_reloads_1 (rtx, const_rtx, void *);
432 static void forget_marked_reloads (regset);
433 static int reload_reg_class_lower (const void *, const void *);
434 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
436 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
438 static int reload_reg_free_p (unsigned int, int, enum reload_type);
439 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
441 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
443 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
444 static int allocate_reload_reg (struct insn_chain *, int, int);
445 static int conflicts_with_override (rtx);
446 static void failed_reload (rtx, int);
447 static int set_reload_reg (int, int);
448 static void choose_reload_regs_init (struct insn_chain *, rtx *);
449 static void choose_reload_regs (struct insn_chain *);
450 static void merge_assigned_reloads (rtx);
451 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
453 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
455 static void do_input_reload (struct insn_chain *, struct reload *, int);
456 static void do_output_reload (struct insn_chain *, struct reload *, int);
457 static void emit_reload_insns (struct insn_chain *);
458 static void delete_output_reload (rtx, int, int, rtx);
459 static void delete_address_reloads (rtx, rtx);
460 static void delete_address_reloads_1 (rtx, rtx, rtx);
461 static rtx inc_for_reload (rtx, rtx, rtx, int);
463 static void add_auto_inc_notes (rtx, rtx);
465 static void substitute (rtx *, const_rtx, rtx);
466 static bool gen_reload_chain_without_interm_reg_p (int, int);
467 static int reloads_conflict (int, int);
468 static rtx gen_reload (rtx, rtx, int, enum reload_type);
469 static rtx emit_insn_if_valid_for_reload (rtx);
471 /* Initialize the reload pass. This is called at the beginning of compilation
472 and may be called again if the target is reinitialized. */
479 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
480 Set spill_indirect_levels to the number of levels such addressing is
481 permitted, zero if it is not permitted at all. */
484 = gen_rtx_MEM (Pmode,
487 LAST_VIRTUAL_REGISTER + 1),
489 spill_indirect_levels = 0;
491 while (memory_address_p (QImode, tem))
493 spill_indirect_levels++;
494 tem = gen_rtx_MEM (Pmode, tem);
497 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
499 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
500 indirect_symref_ok = memory_address_p (QImode, tem);
502 /* See if reg+reg is a valid (and offsettable) address. */
504 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
506 tem = gen_rtx_PLUS (Pmode,
507 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
508 gen_rtx_REG (Pmode, i));
510 /* This way, we make sure that reg+reg is an offsettable address. */
511 tem = plus_constant (tem, 4);
513 if (memory_address_p (QImode, tem))
515 double_reg_address_ok = 1;
520 /* Initialize obstack for our rtl allocation. */
521 gcc_obstack_init (&reload_obstack);
522 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
524 INIT_REG_SET (&spilled_pseudos);
525 INIT_REG_SET (&changed_allocation_pseudos);
526 INIT_REG_SET (&pseudos_counted);
529 /* List of insn chains that are currently unused. */
530 static struct insn_chain *unused_insn_chains = 0;
532 /* Allocate an empty insn_chain structure. */
534 new_insn_chain (void)
536 struct insn_chain *c;
538 if (unused_insn_chains == 0)
540 c = XOBNEW (&reload_obstack, struct insn_chain);
541 INIT_REG_SET (&c->live_throughout);
542 INIT_REG_SET (&c->dead_or_set);
546 c = unused_insn_chains;
547 unused_insn_chains = c->next;
549 c->is_caller_save_insn = 0;
550 c->need_operand_change = 0;
556 /* Small utility function to set all regs in hard reg set TO which are
557 allocated to pseudos in regset FROM. */
560 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
563 reg_set_iterator rsi;
565 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
567 int r = reg_renumber[regno];
571 /* reload_combine uses the information from DF_LIVE_IN,
572 which might still contain registers that have not
573 actually been allocated since they have an
575 gcc_assert (ira_conflicts_p || reload_completed);
578 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
582 /* Replace all pseudos found in LOC with their corresponding
586 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
599 unsigned int regno = REGNO (x);
601 if (regno < FIRST_PSEUDO_REGISTER)
604 x = eliminate_regs (x, mem_mode, usage);
608 replace_pseudos_in (loc, mem_mode, usage);
612 if (reg_equiv_constant[regno])
613 *loc = reg_equiv_constant[regno];
614 else if (reg_equiv_mem[regno])
615 *loc = reg_equiv_mem[regno];
616 else if (reg_equiv_address[regno])
617 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
620 gcc_assert (!REG_P (regno_reg_rtx[regno])
621 || REGNO (regno_reg_rtx[regno]) != regno);
622 *loc = regno_reg_rtx[regno];
627 else if (code == MEM)
629 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
633 /* Process each of our operands recursively. */
634 fmt = GET_RTX_FORMAT (code);
635 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
637 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
638 else if (*fmt == 'E')
639 for (j = 0; j < XVECLEN (x, i); j++)
640 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
643 /* Determine if the current function has an exception receiver block
644 that reaches the exit block via non-exceptional edges */
647 has_nonexceptional_receiver (void)
651 basic_block *tos, *worklist, bb;
653 /* If we're not optimizing, then just err on the safe side. */
657 /* First determine which blocks can reach exit via normal paths. */
658 tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1);
661 bb->flags &= ~BB_REACHABLE;
663 /* Place the exit block on our worklist. */
664 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
665 *tos++ = EXIT_BLOCK_PTR;
667 /* Iterate: find everything reachable from what we've already seen. */
668 while (tos != worklist)
672 FOR_EACH_EDGE (e, ei, bb->preds)
673 if (!(e->flags & EDGE_ABNORMAL))
675 basic_block src = e->src;
677 if (!(src->flags & BB_REACHABLE))
679 src->flags |= BB_REACHABLE;
686 /* Now see if there's a reachable block with an exceptional incoming
689 if (bb->flags & BB_REACHABLE)
690 FOR_EACH_EDGE (e, ei, bb->preds)
691 if (e->flags & EDGE_ABNORMAL)
694 /* No exceptional block reached exit unexceptionally. */
699 /* Global variables used by reload and its subroutines. */
701 /* Set during calculate_needs if an insn needs register elimination. */
702 static int something_needs_elimination;
703 /* Set during calculate_needs if an insn needs an operand changed. */
704 static int something_needs_operands_changed;
705 /* Set by alter_regs if we spilled a register to the stack. */
706 static bool something_was_spilled;
708 /* Nonzero means we couldn't get enough spill regs. */
711 /* Temporary array of pseudo-register number. */
712 static int *temp_pseudo_reg_arr;
714 /* Main entry point for the reload pass.
716 FIRST is the first insn of the function being compiled.
718 GLOBAL nonzero means we were called from global_alloc
719 and should attempt to reallocate any pseudoregs that we
720 displace from hard regs we will use for reloads.
721 If GLOBAL is zero, we do not have enough information to do that,
722 so any pseudo reg that is spilled must go to the stack.
724 Return value is nonzero if reload failed
725 and we must not do any more for this function. */
728 reload (rtx first, int global)
732 struct elim_table *ep;
735 /* Make sure even insns with volatile mem refs are recognizable. */
740 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
742 /* Make sure that the last insn in the chain
743 is not something that needs reloading. */
744 emit_note (NOTE_INSN_DELETED);
746 /* Enable find_equiv_reg to distinguish insns made by reload. */
747 reload_first_uid = get_max_uid ();
749 #ifdef SECONDARY_MEMORY_NEEDED
750 /* Initialize the secondary memory table. */
751 clear_secondary_mem ();
754 /* We don't have a stack slot for any spill reg yet. */
755 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
756 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
758 /* Initialize the save area information for caller-save, in case some
762 /* Compute which hard registers are now in use
763 as homes for pseudo registers.
764 This is done here rather than (eg) in global_alloc
765 because this point is reached even if not optimizing. */
766 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
769 /* A function that has a nonlocal label that can reach the exit
770 block via non-exceptional paths must save all call-saved
772 if (cfun->has_nonlocal_label
773 && has_nonexceptional_receiver ())
774 crtl->saves_all_registers = 1;
776 if (crtl->saves_all_registers)
777 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
778 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
779 df_set_regs_ever_live (i, true);
781 /* Find all the pseudo registers that didn't get hard regs
782 but do have known equivalent constants or memory slots.
783 These include parameters (known equivalent to parameter slots)
784 and cse'd or loop-moved constant memory addresses.
786 Record constant equivalents in reg_equiv_constant
787 so they will be substituted by find_reloads.
788 Record memory equivalents in reg_mem_equiv so they can
789 be substituted eventually by altering the REG-rtx's. */
791 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
792 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
793 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
794 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
795 reg_equiv_address = XCNEWVEC (rtx, max_regno);
796 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
797 reg_old_renumber = XCNEWVEC (short, max_regno);
798 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
799 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
800 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
802 CLEAR_HARD_REG_SET (bad_spill_regs_global);
804 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
805 to. Also find all paradoxical subregs and find largest such for
808 num_eliminable_invariants = 0;
809 for (insn = first; insn; insn = NEXT_INSN (insn))
811 rtx set = single_set (insn);
813 /* We may introduce USEs that we want to remove at the end, so
814 we'll mark them with QImode. Make sure there are no
815 previously-marked insns left by say regmove. */
816 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
817 && GET_MODE (insn) != VOIDmode)
818 PUT_MODE (insn, VOIDmode);
820 if (NONDEBUG_INSN_P (insn))
821 scan_paradoxical_subregs (PATTERN (insn));
823 if (set != 0 && REG_P (SET_DEST (set)))
825 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
831 i = REGNO (SET_DEST (set));
834 if (i <= LAST_VIRTUAL_REGISTER)
837 if (! function_invariant_p (x)
839 /* A function invariant is often CONSTANT_P but may
840 include a register. We promise to only pass
841 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
843 && LEGITIMATE_PIC_OPERAND_P (x)))
845 /* It can happen that a REG_EQUIV note contains a MEM
846 that is not a legitimate memory operand. As later
847 stages of reload assume that all addresses found
848 in the reg_equiv_* arrays were originally legitimate,
849 we ignore such REG_EQUIV notes. */
850 if (memory_operand (x, VOIDmode))
852 /* Always unshare the equivalence, so we can
853 substitute into this insn without touching the
855 reg_equiv_memory_loc[i] = copy_rtx (x);
857 else if (function_invariant_p (x))
859 if (GET_CODE (x) == PLUS)
861 /* This is PLUS of frame pointer and a constant,
862 and might be shared. Unshare it. */
863 reg_equiv_invariant[i] = copy_rtx (x);
864 num_eliminable_invariants++;
866 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
868 reg_equiv_invariant[i] = x;
869 num_eliminable_invariants++;
871 else if (LEGITIMATE_CONSTANT_P (x))
872 reg_equiv_constant[i] = x;
875 reg_equiv_memory_loc[i]
876 = force_const_mem (GET_MODE (SET_DEST (set)), x);
877 if (! reg_equiv_memory_loc[i])
878 reg_equiv_init[i] = NULL_RTX;
883 reg_equiv_init[i] = NULL_RTX;
888 reg_equiv_init[i] = NULL_RTX;
893 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
894 if (reg_equiv_init[i])
896 fprintf (dump_file, "init_insns for %u: ", i);
897 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
898 fprintf (dump_file, "\n");
903 first_label_num = get_first_label_num ();
904 num_labels = max_label_num () - first_label_num;
906 /* Allocate the tables used to store offset information at labels. */
907 /* We used to use alloca here, but the size of what it would try to
908 allocate would occasionally cause it to exceed the stack limit and
909 cause a core dump. */
910 offsets_known_at = XNEWVEC (char, num_labels);
911 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
913 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
914 stack slots to the pseudos that lack hard regs or equivalents.
915 Do not touch virtual registers. */
917 temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
918 for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
919 temp_pseudo_reg_arr[n++] = i;
922 /* Ask IRA to order pseudo-registers for better stack slot
924 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
926 for (i = 0; i < n; i++)
927 alter_reg (temp_pseudo_reg_arr[i], -1, false);
929 /* If we have some registers we think can be eliminated, scan all insns to
930 see if there is an insn that sets one of these registers to something
931 other than itself plus a constant. If so, the register cannot be
932 eliminated. Doing this scan here eliminates an extra pass through the
933 main reload loop in the most common case where register elimination
935 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
937 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
939 maybe_fix_stack_asms ();
941 insns_need_reload = 0;
942 something_needs_elimination = 0;
944 /* Initialize to -1, which means take the first spill register. */
947 /* Spill any hard regs that we know we can't eliminate. */
948 CLEAR_HARD_REG_SET (used_spill_regs);
949 /* There can be multiple ways to eliminate a register;
950 they should be listed adjacently.
951 Elimination for any register fails only if all possible ways fail. */
952 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
955 int can_eliminate = 0;
958 can_eliminate |= ep->can_eliminate;
961 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
963 spill_hard_reg (from, 1);
966 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
967 if (frame_pointer_needed)
968 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
970 finish_spills (global);
972 /* From now on, we may need to generate moves differently. We may also
973 allow modifications of insns which cause them to not be recognized.
974 Any such modifications will be cleaned up during reload itself. */
975 reload_in_progress = 1;
977 /* This loop scans the entire function each go-round
978 and repeats until one repetition spills no additional hard regs. */
981 int something_changed;
983 HOST_WIDE_INT starting_frame_size;
985 starting_frame_size = get_frame_size ();
986 something_was_spilled = false;
988 set_initial_elim_offsets ();
989 set_initial_label_offsets ();
991 /* For each pseudo register that has an equivalent location defined,
992 try to eliminate any eliminable registers (such as the frame pointer)
993 assuming initial offsets for the replacement register, which
996 If the resulting location is directly addressable, substitute
997 the MEM we just got directly for the old REG.
999 If it is not addressable but is a constant or the sum of a hard reg
1000 and constant, it is probably not addressable because the constant is
1001 out of range, in that case record the address; we will generate
1002 hairy code to compute the address in a register each time it is
1003 needed. Similarly if it is a hard register, but one that is not
1004 valid as an address register.
1006 If the location is not addressable, but does not have one of the
1007 above forms, assign a stack slot. We have to do this to avoid the
1008 potential of producing lots of reloads if, e.g., a location involves
1009 a pseudo that didn't get a hard register and has an equivalent memory
1010 location that also involves a pseudo that didn't get a hard register.
1012 Perhaps at some point we will improve reload_when_needed handling
1013 so this problem goes away. But that's very hairy. */
1015 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1016 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
1018 rtx x = eliminate_regs (reg_equiv_memory_loc[i], VOIDmode,
1021 if (strict_memory_address_addr_space_p
1022 (GET_MODE (regno_reg_rtx[i]), XEXP (x, 0),
1023 MEM_ADDR_SPACE (x)))
1024 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
1025 else if (CONSTANT_P (XEXP (x, 0))
1026 || (REG_P (XEXP (x, 0))
1027 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
1028 || (GET_CODE (XEXP (x, 0)) == PLUS
1029 && REG_P (XEXP (XEXP (x, 0), 0))
1030 && (REGNO (XEXP (XEXP (x, 0), 0))
1031 < FIRST_PSEUDO_REGISTER)
1032 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
1033 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
1036 /* Make a new stack slot. Then indicate that something
1037 changed so we go back and recompute offsets for
1038 eliminable registers because the allocation of memory
1039 below might change some offset. reg_equiv_{mem,address}
1040 will be set up for this pseudo on the next pass around
1042 reg_equiv_memory_loc[i] = 0;
1043 reg_equiv_init[i] = 0;
1044 alter_reg (i, -1, true);
1048 if (caller_save_needed)
1049 setup_save_areas ();
1051 /* If we allocated another stack slot, redo elimination bookkeeping. */
1052 if (something_was_spilled || starting_frame_size != get_frame_size ())
1054 if (starting_frame_size && crtl->stack_alignment_needed)
1056 /* If we have a stack frame, we must align it now. The
1057 stack size may be a part of the offset computation for
1058 register elimination. So if this changes the stack size,
1059 then repeat the elimination bookkeeping. We don't
1060 realign when there is no stack, as that will cause a
1061 stack frame when none is needed should
1062 STARTING_FRAME_OFFSET not be already aligned to
1064 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
1065 if (starting_frame_size != get_frame_size ())
1069 if (caller_save_needed)
1071 save_call_clobbered_regs ();
1072 /* That might have allocated new insn_chain structures. */
1073 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1076 calculate_needs_all_insns (global);
1078 if (! ira_conflicts_p)
1079 /* Don't do it for IRA. We need this info because we don't
1080 change live_throughout and dead_or_set for chains when IRA
1082 CLEAR_REG_SET (&spilled_pseudos);
1086 something_changed = 0;
1088 /* If we allocated any new memory locations, make another pass
1089 since it might have changed elimination offsets. */
1090 if (something_was_spilled || starting_frame_size != get_frame_size ())
1091 something_changed = 1;
1093 /* Even if the frame size remained the same, we might still have
1094 changed elimination offsets, e.g. if find_reloads called
1095 force_const_mem requiring the back end to allocate a constant
1096 pool base register that needs to be saved on the stack. */
1097 else if (!verify_initial_elim_offsets ())
1098 something_changed = 1;
1101 HARD_REG_SET to_spill;
1102 CLEAR_HARD_REG_SET (to_spill);
1103 update_eliminables (&to_spill);
1104 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
1106 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1107 if (TEST_HARD_REG_BIT (to_spill, i))
1109 spill_hard_reg (i, 1);
1112 /* Regardless of the state of spills, if we previously had
1113 a register that we thought we could eliminate, but now can
1114 not eliminate, we must run another pass.
1116 Consider pseudos which have an entry in reg_equiv_* which
1117 reference an eliminable register. We must make another pass
1118 to update reg_equiv_* so that we do not substitute in the
1119 old value from when we thought the elimination could be
1121 something_changed = 1;
1125 select_reload_regs ();
1129 if (insns_need_reload != 0 || did_spill)
1130 something_changed |= finish_spills (global);
1132 if (! something_changed)
1135 if (caller_save_needed)
1136 delete_caller_save_insns ();
1138 obstack_free (&reload_obstack, reload_firstobj);
1141 /* If global-alloc was run, notify it of any register eliminations we have
1144 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1145 if (ep->can_eliminate)
1146 mark_elimination (ep->from, ep->to);
1148 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1149 If that insn didn't set the register (i.e., it copied the register to
1150 memory), just delete that insn instead of the equivalencing insn plus
1151 anything now dead. If we call delete_dead_insn on that insn, we may
1152 delete the insn that actually sets the register if the register dies
1153 there and that is incorrect. */
1155 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1157 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1160 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1162 rtx equiv_insn = XEXP (list, 0);
1164 /* If we already deleted the insn or if it may trap, we can't
1165 delete it. The latter case shouldn't happen, but can
1166 if an insn has a variable address, gets a REG_EH_REGION
1167 note added to it, and then gets converted into a load
1168 from a constant address. */
1169 if (NOTE_P (equiv_insn)
1170 || can_throw_internal (equiv_insn))
1172 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1173 delete_dead_insn (equiv_insn);
1175 SET_INSN_DELETED (equiv_insn);
1180 /* Use the reload registers where necessary
1181 by generating move instructions to move the must-be-register
1182 values into or out of the reload registers. */
1184 if (insns_need_reload != 0 || something_needs_elimination
1185 || something_needs_operands_changed)
1187 HOST_WIDE_INT old_frame_size = get_frame_size ();
1189 reload_as_needed (global);
1191 gcc_assert (old_frame_size == get_frame_size ());
1193 gcc_assert (verify_initial_elim_offsets ());
1196 /* If we were able to eliminate the frame pointer, show that it is no
1197 longer live at the start of any basic block. If it ls live by
1198 virtue of being in a pseudo, that pseudo will be marked live
1199 and hence the frame pointer will be known to be live via that
1202 if (! frame_pointer_needed)
1204 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1206 /* Come here (with failure set nonzero) if we can't get enough spill
1210 CLEAR_REG_SET (&changed_allocation_pseudos);
1211 CLEAR_REG_SET (&spilled_pseudos);
1212 reload_in_progress = 0;
1214 /* Now eliminate all pseudo regs by modifying them into
1215 their equivalent memory references.
1216 The REG-rtx's for the pseudos are modified in place,
1217 so all insns that used to refer to them now refer to memory.
1219 For a reg that has a reg_equiv_address, all those insns
1220 were changed by reloading so that no insns refer to it any longer;
1221 but the DECL_RTL of a variable decl may refer to it,
1222 and if so this causes the debugging info to mention the variable. */
1224 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1228 if (reg_equiv_mem[i])
1229 addr = XEXP (reg_equiv_mem[i], 0);
1231 if (reg_equiv_address[i])
1232 addr = reg_equiv_address[i];
1236 if (reg_renumber[i] < 0)
1238 rtx reg = regno_reg_rtx[i];
1240 REG_USERVAR_P (reg) = 0;
1241 PUT_CODE (reg, MEM);
1242 XEXP (reg, 0) = addr;
1243 if (reg_equiv_memory_loc[i])
1244 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1247 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1248 MEM_ATTRS (reg) = 0;
1250 MEM_NOTRAP_P (reg) = 1;
1252 else if (reg_equiv_mem[i])
1253 XEXP (reg_equiv_mem[i], 0) = addr;
1256 /* We don't want complex addressing modes in debug insns
1257 if simpler ones will do, so delegitimize equivalences
1259 if (MAY_HAVE_DEBUG_INSNS && reg_renumber[i] < 0)
1261 rtx reg = regno_reg_rtx[i];
1265 if (reg_equiv_constant[i])
1266 equiv = reg_equiv_constant[i];
1267 else if (reg_equiv_invariant[i])
1268 equiv = reg_equiv_invariant[i];
1269 else if (reg && MEM_P (reg))
1270 equiv = targetm.delegitimize_address (reg);
1271 else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
1277 for (use = DF_REG_USE_CHAIN (i); use; use = next)
1279 insn = DF_REF_INSN (use);
1281 /* Make sure the next ref is for a different instruction,
1282 so that we're not affected by the rescan. */
1283 next = DF_REF_NEXT_REG (use);
1284 while (next && DF_REF_INSN (next) == insn)
1285 next = DF_REF_NEXT_REG (next);
1287 if (DEBUG_INSN_P (insn))
1291 INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
1292 df_insn_rescan_debug_internal (insn);
1295 INSN_VAR_LOCATION_LOC (insn)
1296 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn),
1303 /* We must set reload_completed now since the cleanup_subreg_operands call
1304 below will re-recognize each insn and reload may have generated insns
1305 which are only valid during and after reload. */
1306 reload_completed = 1;
1308 /* Make a pass over all the insns and delete all USEs which we inserted
1309 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1310 notes. Delete all CLOBBER insns, except those that refer to the return
1311 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1312 from misarranging variable-array code, and simplify (subreg (reg))
1313 operands. Strip and regenerate REG_INC notes that may have been moved
1316 for (insn = first; insn; insn = NEXT_INSN (insn))
1322 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1323 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1325 if ((GET_CODE (PATTERN (insn)) == USE
1326 /* We mark with QImode USEs introduced by reload itself. */
1327 && (GET_MODE (insn) == QImode
1328 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1329 || (GET_CODE (PATTERN (insn)) == CLOBBER
1330 && (!MEM_P (XEXP (PATTERN (insn), 0))
1331 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1332 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1333 && XEXP (XEXP (PATTERN (insn), 0), 0)
1334 != stack_pointer_rtx))
1335 && (!REG_P (XEXP (PATTERN (insn), 0))
1336 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1342 /* Some CLOBBERs may survive until here and still reference unassigned
1343 pseudos with const equivalent, which may in turn cause ICE in later
1344 passes if the reference remains in place. */
1345 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1346 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1347 VOIDmode, PATTERN (insn));
1349 /* Discard obvious no-ops, even without -O. This optimization
1350 is fast and doesn't interfere with debugging. */
1351 if (NONJUMP_INSN_P (insn)
1352 && GET_CODE (PATTERN (insn)) == SET
1353 && REG_P (SET_SRC (PATTERN (insn)))
1354 && REG_P (SET_DEST (PATTERN (insn)))
1355 && (REGNO (SET_SRC (PATTERN (insn)))
1356 == REGNO (SET_DEST (PATTERN (insn)))))
1362 pnote = ®_NOTES (insn);
1365 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1366 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1367 || REG_NOTE_KIND (*pnote) == REG_INC)
1368 *pnote = XEXP (*pnote, 1);
1370 pnote = &XEXP (*pnote, 1);
1374 add_auto_inc_notes (insn, PATTERN (insn));
1377 /* Simplify (subreg (reg)) if it appears as an operand. */
1378 cleanup_subreg_operands (insn);
1380 /* Clean up invalid ASMs so that they don't confuse later passes.
1382 if (asm_noperands (PATTERN (insn)) >= 0)
1384 extract_insn (insn);
1385 if (!constrain_operands (1))
1387 error_for_asm (insn,
1388 "%<asm%> operand has impossible constraints");
1395 /* If we are doing generic stack checking, give a warning if this
1396 function's frame size is larger than we expect. */
1397 if (flag_stack_check == GENERIC_STACK_CHECK)
1399 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1400 static int verbose_warned = 0;
1402 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1403 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1404 size += UNITS_PER_WORD;
1406 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1408 warning (0, "frame size too large for reliable stack checking");
1409 if (! verbose_warned)
1411 warning (0, "try reducing the number of local variables");
1417 /* Indicate that we no longer have known memory locations or constants. */
1418 if (reg_equiv_constant)
1419 free (reg_equiv_constant);
1420 if (reg_equiv_invariant)
1421 free (reg_equiv_invariant);
1422 reg_equiv_constant = 0;
1423 reg_equiv_invariant = 0;
1424 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1425 reg_equiv_memory_loc = 0;
1427 free (temp_pseudo_reg_arr);
1429 if (offsets_known_at)
1430 free (offsets_known_at);
1434 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1435 if (reg_equiv_alt_mem_list[i])
1436 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1437 free (reg_equiv_alt_mem_list);
1439 free (reg_equiv_mem);
1441 free (reg_equiv_address);
1442 free (reg_max_ref_width);
1443 free (reg_old_renumber);
1444 free (pseudo_previous_regs);
1445 free (pseudo_forbidden_regs);
1447 CLEAR_HARD_REG_SET (used_spill_regs);
1448 for (i = 0; i < n_spills; i++)
1449 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1451 /* Free all the insn_chain structures at once. */
1452 obstack_free (&reload_obstack, reload_startobj);
1453 unused_insn_chains = 0;
1454 fixup_abnormal_edges ();
1456 /* Replacing pseudos with their memory equivalents might have
1457 created shared rtx. Subsequent passes would get confused
1458 by this, so unshare everything here. */
1459 unshare_all_rtl_again (first);
1461 #ifdef STACK_BOUNDARY
1462 /* init_emit has set the alignment of the hard frame pointer
1463 to STACK_BOUNDARY. It is very likely no longer valid if
1464 the hard frame pointer was used for register allocation. */
1465 if (!frame_pointer_needed)
1466 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1469 VEC_free (rtx_p, heap, substitute_stack);
1474 /* Yet another special case. Unfortunately, reg-stack forces people to
1475 write incorrect clobbers in asm statements. These clobbers must not
1476 cause the register to appear in bad_spill_regs, otherwise we'll call
1477 fatal_insn later. We clear the corresponding regnos in the live
1478 register sets to avoid this.
1479 The whole thing is rather sick, I'm afraid. */
1482 maybe_fix_stack_asms (void)
1485 const char *constraints[MAX_RECOG_OPERANDS];
1486 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1487 struct insn_chain *chain;
1489 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1492 HARD_REG_SET clobbered, allowed;
1495 if (! INSN_P (chain->insn)
1496 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1498 pat = PATTERN (chain->insn);
1499 if (GET_CODE (pat) != PARALLEL)
1502 CLEAR_HARD_REG_SET (clobbered);
1503 CLEAR_HARD_REG_SET (allowed);
1505 /* First, make a mask of all stack regs that are clobbered. */
1506 for (i = 0; i < XVECLEN (pat, 0); i++)
1508 rtx t = XVECEXP (pat, 0, i);
1509 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1510 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1513 /* Get the operand values and constraints out of the insn. */
1514 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1515 constraints, operand_mode, NULL);
1517 /* For every operand, see what registers are allowed. */
1518 for (i = 0; i < noperands; i++)
1520 const char *p = constraints[i];
1521 /* For every alternative, we compute the class of registers allowed
1522 for reloading in CLS, and merge its contents into the reg set
1524 int cls = (int) NO_REGS;
1530 if (c == '\0' || c == ',' || c == '#')
1532 /* End of one alternative - mark the regs in the current
1533 class, and reset the class. */
1534 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1540 } while (c != '\0' && c != ',');
1548 case '=': case '+': case '*': case '%': case '?': case '!':
1549 case '0': case '1': case '2': case '3': case '4': case '<':
1550 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1551 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1552 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1553 case TARGET_MEM_CONSTRAINT:
1557 cls = (int) reg_class_subunion[cls]
1558 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1563 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1567 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1568 cls = (int) reg_class_subunion[cls]
1569 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1571 cls = (int) reg_class_subunion[cls]
1572 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1574 p += CONSTRAINT_LEN (c, p);
1577 /* Those of the registers which are clobbered, but allowed by the
1578 constraints, must be usable as reload registers. So clear them
1579 out of the life information. */
1580 AND_HARD_REG_SET (allowed, clobbered);
1581 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1582 if (TEST_HARD_REG_BIT (allowed, i))
1584 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1585 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1592 /* Copy the global variables n_reloads and rld into the corresponding elts
1595 copy_reloads (struct insn_chain *chain)
1597 chain->n_reloads = n_reloads;
1598 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1599 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1600 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1603 /* Walk the chain of insns, and determine for each whether it needs reloads
1604 and/or eliminations. Build the corresponding insns_need_reload list, and
1605 set something_needs_elimination as appropriate. */
1607 calculate_needs_all_insns (int global)
1609 struct insn_chain **pprev_reload = &insns_need_reload;
1610 struct insn_chain *chain, *next = 0;
1612 something_needs_elimination = 0;
1614 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1615 for (chain = reload_insn_chain; chain != 0; chain = next)
1617 rtx insn = chain->insn;
1621 /* Clear out the shortcuts. */
1622 chain->n_reloads = 0;
1623 chain->need_elim = 0;
1624 chain->need_reload = 0;
1625 chain->need_operand_change = 0;
1627 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1628 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1629 what effects this has on the known offsets at labels. */
1631 if (LABEL_P (insn) || JUMP_P (insn)
1632 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1633 set_label_offsets (insn, insn, 0);
1637 rtx old_body = PATTERN (insn);
1638 int old_code = INSN_CODE (insn);
1639 rtx old_notes = REG_NOTES (insn);
1640 int did_elimination = 0;
1641 int operands_changed = 0;
1642 rtx set = single_set (insn);
1644 /* Skip insns that only set an equivalence. */
1645 if (set && REG_P (SET_DEST (set))
1646 && reg_renumber[REGNO (SET_DEST (set))] < 0
1647 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1648 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1649 && reg_equiv_init[REGNO (SET_DEST (set))])
1652 /* If needed, eliminate any eliminable registers. */
1653 if (num_eliminable || num_eliminable_invariants)
1654 did_elimination = eliminate_regs_in_insn (insn, 0);
1656 /* Analyze the instruction. */
1657 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1658 global, spill_reg_order);
1660 /* If a no-op set needs more than one reload, this is likely
1661 to be something that needs input address reloads. We
1662 can't get rid of this cleanly later, and it is of no use
1663 anyway, so discard it now.
1664 We only do this when expensive_optimizations is enabled,
1665 since this complements reload inheritance / output
1666 reload deletion, and it can make debugging harder. */
1667 if (flag_expensive_optimizations && n_reloads > 1)
1669 rtx set = single_set (insn);
1672 ((SET_SRC (set) == SET_DEST (set)
1673 && REG_P (SET_SRC (set))
1674 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1675 || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1676 && reg_renumber[REGNO (SET_SRC (set))] < 0
1677 && reg_renumber[REGNO (SET_DEST (set))] < 0
1678 && reg_equiv_memory_loc[REGNO (SET_SRC (set))] != NULL
1679 && reg_equiv_memory_loc[REGNO (SET_DEST (set))] != NULL
1680 && rtx_equal_p (reg_equiv_memory_loc
1681 [REGNO (SET_SRC (set))],
1682 reg_equiv_memory_loc
1683 [REGNO (SET_DEST (set))]))))
1685 if (ira_conflicts_p)
1686 /* Inform IRA about the insn deletion. */
1687 ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1688 REGNO (SET_SRC (set)));
1690 /* Delete it from the reload chain. */
1692 chain->prev->next = next;
1694 reload_insn_chain = next;
1696 next->prev = chain->prev;
1697 chain->next = unused_insn_chains;
1698 unused_insn_chains = chain;
1703 update_eliminable_offsets ();
1705 /* Remember for later shortcuts which insns had any reloads or
1706 register eliminations. */
1707 chain->need_elim = did_elimination;
1708 chain->need_reload = n_reloads > 0;
1709 chain->need_operand_change = operands_changed;
1711 /* Discard any register replacements done. */
1712 if (did_elimination)
1714 obstack_free (&reload_obstack, reload_insn_firstobj);
1715 PATTERN (insn) = old_body;
1716 INSN_CODE (insn) = old_code;
1717 REG_NOTES (insn) = old_notes;
1718 something_needs_elimination = 1;
1721 something_needs_operands_changed |= operands_changed;
1725 copy_reloads (chain);
1726 *pprev_reload = chain;
1727 pprev_reload = &chain->next_need_reload;
1734 /* Comparison function for qsort to decide which of two reloads
1735 should be handled first. *P1 and *P2 are the reload numbers. */
1738 reload_reg_class_lower (const void *r1p, const void *r2p)
1740 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1743 /* Consider required reloads before optional ones. */
1744 t = rld[r1].optional - rld[r2].optional;
1748 /* Count all solitary classes before non-solitary ones. */
1749 t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1750 - (reg_class_size[(int) rld[r1].rclass] == 1));
1754 /* Aside from solitaires, consider all multi-reg groups first. */
1755 t = rld[r2].nregs - rld[r1].nregs;
1759 /* Consider reloads in order of increasing reg-class number. */
1760 t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1764 /* If reloads are equally urgent, sort by reload number,
1765 so that the results of qsort leave nothing to chance. */
1769 /* The cost of spilling each hard reg. */
1770 static int spill_cost[FIRST_PSEUDO_REGISTER];
1772 /* When spilling multiple hard registers, we use SPILL_COST for the first
1773 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1774 only the first hard reg for a multi-reg pseudo. */
1775 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1777 /* Map of hard regno to pseudo regno currently occupying the hard
1779 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1781 /* Update the spill cost arrays, considering that pseudo REG is live. */
1784 count_pseudo (int reg)
1786 int freq = REG_FREQ (reg);
1787 int r = reg_renumber[reg];
1790 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1791 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1792 /* Ignore spilled pseudo-registers which can be here only if IRA
1794 || (ira_conflicts_p && r < 0))
1797 SET_REGNO_REG_SET (&pseudos_counted, reg);
1799 gcc_assert (r >= 0);
1801 spill_add_cost[r] += freq;
1802 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1805 hard_regno_to_pseudo_regno[r + nregs] = reg;
1806 spill_cost[r + nregs] += freq;
1810 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1811 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1814 order_regs_for_reload (struct insn_chain *chain)
1817 HARD_REG_SET used_by_pseudos;
1818 HARD_REG_SET used_by_pseudos2;
1819 reg_set_iterator rsi;
1821 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1823 memset (spill_cost, 0, sizeof spill_cost);
1824 memset (spill_add_cost, 0, sizeof spill_add_cost);
1825 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1826 hard_regno_to_pseudo_regno[i] = -1;
1828 /* Count number of uses of each hard reg by pseudo regs allocated to it
1829 and then order them by decreasing use. First exclude hard registers
1830 that are live in or across this insn. */
1832 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1833 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1834 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1835 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1837 /* Now find out which pseudos are allocated to it, and update
1839 CLEAR_REG_SET (&pseudos_counted);
1841 EXECUTE_IF_SET_IN_REG_SET
1842 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1846 EXECUTE_IF_SET_IN_REG_SET
1847 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1851 CLEAR_REG_SET (&pseudos_counted);
1854 /* Vector of reload-numbers showing the order in which the reloads should
1856 static short reload_order[MAX_RELOADS];
1858 /* This is used to keep track of the spill regs used in one insn. */
1859 static HARD_REG_SET used_spill_regs_local;
1861 /* We decided to spill hard register SPILLED, which has a size of
1862 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1863 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1864 update SPILL_COST/SPILL_ADD_COST. */
1867 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1869 int freq = REG_FREQ (reg);
1870 int r = reg_renumber[reg];
1871 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1873 /* Ignore spilled pseudo-registers which can be here only if IRA is
1875 if ((ira_conflicts_p && r < 0)
1876 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1877 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1880 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1882 spill_add_cost[r] -= freq;
1885 hard_regno_to_pseudo_regno[r + nregs] = -1;
1886 spill_cost[r + nregs] -= freq;
1890 /* Find reload register to use for reload number ORDER. */
1893 find_reg (struct insn_chain *chain, int order)
1895 int rnum = reload_order[order];
1896 struct reload *rl = rld + rnum;
1897 int best_cost = INT_MAX;
1899 unsigned int i, j, n;
1901 HARD_REG_SET not_usable;
1902 HARD_REG_SET used_by_other_reload;
1903 reg_set_iterator rsi;
1904 static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1905 static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1907 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1908 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1909 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1911 CLEAR_HARD_REG_SET (used_by_other_reload);
1912 for (k = 0; k < order; k++)
1914 int other = reload_order[k];
1916 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1917 for (j = 0; j < rld[other].nregs; j++)
1918 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1921 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1923 #ifdef REG_ALLOC_ORDER
1924 unsigned int regno = reg_alloc_order[i];
1926 unsigned int regno = i;
1929 if (! TEST_HARD_REG_BIT (not_usable, regno)
1930 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1931 && HARD_REGNO_MODE_OK (regno, rl->mode))
1933 int this_cost = spill_cost[regno];
1935 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1937 for (j = 1; j < this_nregs; j++)
1939 this_cost += spill_add_cost[regno + j];
1940 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1941 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1947 if (ira_conflicts_p)
1949 /* Ask IRA to find a better pseudo-register for
1951 for (n = j = 0; j < this_nregs; j++)
1953 int r = hard_regno_to_pseudo_regno[regno + j];
1957 if (n == 0 || regno_pseudo_regs[n - 1] != r)
1958 regno_pseudo_regs[n++] = r;
1960 regno_pseudo_regs[n++] = -1;
1962 || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1963 best_regno_pseudo_regs,
1970 best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1971 if (regno_pseudo_regs[j] < 0)
1978 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1980 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1982 if (this_cost < best_cost
1983 /* Among registers with equal cost, prefer caller-saved ones, or
1984 use REG_ALLOC_ORDER if it is defined. */
1985 || (this_cost == best_cost
1986 #ifdef REG_ALLOC_ORDER
1987 && (inv_reg_alloc_order[regno]
1988 < inv_reg_alloc_order[best_reg])
1990 && call_used_regs[regno]
1991 && ! call_used_regs[best_reg]
1996 best_cost = this_cost;
2004 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
2006 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
2007 rl->regno = best_reg;
2009 EXECUTE_IF_SET_IN_REG_SET
2010 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
2012 count_spilled_pseudo (best_reg, rl->nregs, j);
2015 EXECUTE_IF_SET_IN_REG_SET
2016 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
2018 count_spilled_pseudo (best_reg, rl->nregs, j);
2021 for (i = 0; i < rl->nregs; i++)
2023 gcc_assert (spill_cost[best_reg + i] == 0);
2024 gcc_assert (spill_add_cost[best_reg + i] == 0);
2025 gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
2026 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
2031 /* Find more reload regs to satisfy the remaining need of an insn, which
2033 Do it by ascending class number, since otherwise a reg
2034 might be spilled for a big class and might fail to count
2035 for a smaller class even though it belongs to that class. */
2038 find_reload_regs (struct insn_chain *chain)
2042 /* In order to be certain of getting the registers we need,
2043 we must sort the reloads into order of increasing register class.
2044 Then our grabbing of reload registers will parallel the process
2045 that provided the reload registers. */
2046 for (i = 0; i < chain->n_reloads; i++)
2048 /* Show whether this reload already has a hard reg. */
2049 if (chain->rld[i].reg_rtx)
2051 int regno = REGNO (chain->rld[i].reg_rtx);
2052 chain->rld[i].regno = regno;
2054 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
2057 chain->rld[i].regno = -1;
2058 reload_order[i] = i;
2061 n_reloads = chain->n_reloads;
2062 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
2064 CLEAR_HARD_REG_SET (used_spill_regs_local);
2067 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
2069 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
2071 /* Compute the order of preference for hard registers to spill. */
2073 order_regs_for_reload (chain);
2075 for (i = 0; i < n_reloads; i++)
2077 int r = reload_order[i];
2079 /* Ignore reloads that got marked inoperative. */
2080 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2081 && ! rld[r].optional
2082 && rld[r].regno == -1)
2083 if (! find_reg (chain, i))
2086 fprintf (dump_file, "reload failure for reload %d\n", r);
2087 spill_failure (chain->insn, rld[r].rclass);
2093 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2094 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2096 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2100 select_reload_regs (void)
2102 struct insn_chain *chain;
2104 /* Try to satisfy the needs for each insn. */
2105 for (chain = insns_need_reload; chain != 0;
2106 chain = chain->next_need_reload)
2107 find_reload_regs (chain);
2110 /* Delete all insns that were inserted by emit_caller_save_insns during
2113 delete_caller_save_insns (void)
2115 struct insn_chain *c = reload_insn_chain;
2119 while (c != 0 && c->is_caller_save_insn)
2121 struct insn_chain *next = c->next;
2124 if (c == reload_insn_chain)
2125 reload_insn_chain = next;
2129 next->prev = c->prev;
2131 c->prev->next = next;
2132 c->next = unused_insn_chains;
2133 unused_insn_chains = c;
2141 /* Handle the failure to find a register to spill.
2142 INSN should be one of the insns which needed this particular spill reg. */
2145 spill_failure (rtx insn, enum reg_class rclass)
2147 if (asm_noperands (PATTERN (insn)) >= 0)
2148 error_for_asm (insn, "can't find a register in class %qs while "
2149 "reloading %<asm%>",
2150 reg_class_names[rclass]);
2153 error ("unable to find a register to spill in class %qs",
2154 reg_class_names[rclass]);
2158 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2159 debug_reload_to_stream (dump_file);
2161 fatal_insn ("this is the insn:", insn);
2165 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2166 data that is dead in INSN. */
2169 delete_dead_insn (rtx insn)
2171 rtx prev = prev_real_insn (insn);
2174 /* If the previous insn sets a register that dies in our insn, delete it
2176 if (prev && GET_CODE (PATTERN (prev)) == SET
2177 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2178 && reg_mentioned_p (prev_dest, PATTERN (insn))
2179 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2180 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2181 delete_dead_insn (prev);
2183 SET_INSN_DELETED (insn);
2186 /* Modify the home of pseudo-reg I.
2187 The new home is present in reg_renumber[I].
2189 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2190 or it may be -1, meaning there is none or it is not relevant.
2191 This is used so that all pseudos spilled from a given hard reg
2192 can share one stack slot. */
2195 alter_reg (int i, int from_reg, bool dont_share_p)
2197 /* When outputting an inline function, this can happen
2198 for a reg that isn't actually used. */
2199 if (regno_reg_rtx[i] == 0)
2202 /* If the reg got changed to a MEM at rtl-generation time,
2204 if (!REG_P (regno_reg_rtx[i]))
2207 /* Modify the reg-rtx to contain the new hard reg
2208 number or else to contain its pseudo reg number. */
2209 SET_REGNO (regno_reg_rtx[i],
2210 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2212 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2213 allocate a stack slot for it. */
2215 if (reg_renumber[i] < 0
2216 && REG_N_REFS (i) > 0
2217 && reg_equiv_constant[i] == 0
2218 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
2219 && reg_equiv_memory_loc[i] == 0)
2222 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2223 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2224 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2225 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2226 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2229 something_was_spilled = true;
2231 if (ira_conflicts_p)
2233 /* Mark the spill for IRA. */
2234 SET_REGNO_REG_SET (&spilled_pseudos, i);
2236 x = ira_reuse_stack_slot (i, inherent_size, total_size);
2242 /* Each pseudo reg has an inherent size which comes from its own mode,
2243 and a total size which provides room for paradoxical subregs
2244 which refer to the pseudo reg in wider modes.
2246 We can use a slot already allocated if it provides both
2247 enough inherent space and enough total space.
2248 Otherwise, we allocate a new slot, making sure that it has no less
2249 inherent space, and no less total space, then the previous slot. */
2250 else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2254 /* No known place to spill from => no slot to reuse. */
2255 x = assign_stack_local (mode, total_size,
2256 min_align > inherent_align
2257 || total_size > inherent_size ? -1 : 0);
2261 /* Cancel the big-endian correction done in assign_stack_local.
2262 Get the address of the beginning of the slot. This is so we
2263 can do a big-endian correction unconditionally below. */
2264 if (BYTES_BIG_ENDIAN)
2266 adjust = inherent_size - total_size;
2269 = adjust_address_nv (x, mode_for_size (total_size
2275 if (! dont_share_p && ira_conflicts_p)
2276 /* Inform IRA about allocation a new stack slot. */
2277 ira_mark_new_stack_slot (stack_slot, i, total_size);
2280 /* Reuse a stack slot if possible. */
2281 else if (spill_stack_slot[from_reg] != 0
2282 && spill_stack_slot_width[from_reg] >= total_size
2283 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2285 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2286 x = spill_stack_slot[from_reg];
2288 /* Allocate a bigger slot. */
2291 /* Compute maximum size needed, both for inherent size
2292 and for total size. */
2295 if (spill_stack_slot[from_reg])
2297 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2299 mode = GET_MODE (spill_stack_slot[from_reg]);
2300 if (spill_stack_slot_width[from_reg] > total_size)
2301 total_size = spill_stack_slot_width[from_reg];
2302 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2303 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2306 /* Make a slot with that size. */
2307 x = assign_stack_local (mode, total_size,
2308 min_align > inherent_align
2309 || total_size > inherent_size ? -1 : 0);
2312 /* Cancel the big-endian correction done in assign_stack_local.
2313 Get the address of the beginning of the slot. This is so we
2314 can do a big-endian correction unconditionally below. */
2315 if (BYTES_BIG_ENDIAN)
2317 adjust = GET_MODE_SIZE (mode) - total_size;
2320 = adjust_address_nv (x, mode_for_size (total_size
2326 spill_stack_slot[from_reg] = stack_slot;
2327 spill_stack_slot_width[from_reg] = total_size;
2330 /* On a big endian machine, the "address" of the slot
2331 is the address of the low part that fits its inherent mode. */
2332 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2333 adjust += (total_size - inherent_size);
2335 /* If we have any adjustment to make, or if the stack slot is the
2336 wrong mode, make a new stack slot. */
2337 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2339 /* Set all of the memory attributes as appropriate for a spill. */
2340 set_mem_attrs_for_spill (x);
2342 /* Save the stack slot for later. */
2343 reg_equiv_memory_loc[i] = x;
2347 /* Mark the slots in regs_ever_live for the hard regs used by
2348 pseudo-reg number REGNO, accessed in MODE. */
2351 mark_home_live_1 (int regno, enum machine_mode mode)
2355 i = reg_renumber[regno];
2358 lim = end_hard_regno (mode, i);
2360 df_set_regs_ever_live(i++, true);
2363 /* Mark the slots in regs_ever_live for the hard regs
2364 used by pseudo-reg number REGNO. */
2367 mark_home_live (int regno)
2369 if (reg_renumber[regno] >= 0)
2370 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2373 /* This function handles the tracking of elimination offsets around branches.
2375 X is a piece of RTL being scanned.
2377 INSN is the insn that it came from, if any.
2379 INITIAL_P is nonzero if we are to set the offset to be the initial
2380 offset and zero if we are setting the offset of the label to be the
2384 set_label_offsets (rtx x, rtx insn, int initial_p)
2386 enum rtx_code code = GET_CODE (x);
2389 struct elim_table *p;
2394 if (LABEL_REF_NONLOCAL_P (x))
2399 /* ... fall through ... */
2402 /* If we know nothing about this label, set the desired offsets. Note
2403 that this sets the offset at a label to be the offset before a label
2404 if we don't know anything about the label. This is not correct for
2405 the label after a BARRIER, but is the best guess we can make. If
2406 we guessed wrong, we will suppress an elimination that might have
2407 been possible had we been able to guess correctly. */
2409 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2411 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2412 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2413 = (initial_p ? reg_eliminate[i].initial_offset
2414 : reg_eliminate[i].offset);
2415 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2418 /* Otherwise, if this is the definition of a label and it is
2419 preceded by a BARRIER, set our offsets to the known offset of
2423 && (tem = prev_nonnote_insn (insn)) != 0
2425 set_offsets_for_label (insn);
2427 /* If neither of the above cases is true, compare each offset
2428 with those previously recorded and suppress any eliminations
2429 where the offsets disagree. */
2431 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2432 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2433 != (initial_p ? reg_eliminate[i].initial_offset
2434 : reg_eliminate[i].offset))
2435 reg_eliminate[i].can_eliminate = 0;
2440 set_label_offsets (PATTERN (insn), insn, initial_p);
2442 /* ... fall through ... */
2446 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2447 to indirectly and hence must have all eliminations at their
2449 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2450 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2451 set_label_offsets (XEXP (tem, 0), insn, 1);
2457 /* Each of the labels in the parallel or address vector must be
2458 at their initial offsets. We want the first field for PARALLEL
2459 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2461 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2462 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2467 /* We only care about setting PC. If the source is not RETURN,
2468 IF_THEN_ELSE, or a label, disable any eliminations not at
2469 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2470 isn't one of those possibilities. For branches to a label,
2471 call ourselves recursively.
2473 Note that this can disable elimination unnecessarily when we have
2474 a non-local goto since it will look like a non-constant jump to
2475 someplace in the current function. This isn't a significant
2476 problem since such jumps will normally be when all elimination
2477 pairs are back to their initial offsets. */
2479 if (SET_DEST (x) != pc_rtx)
2482 switch (GET_CODE (SET_SRC (x)))
2489 set_label_offsets (SET_SRC (x), insn, initial_p);
2493 tem = XEXP (SET_SRC (x), 1);
2494 if (GET_CODE (tem) == LABEL_REF)
2495 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2496 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2499 tem = XEXP (SET_SRC (x), 2);
2500 if (GET_CODE (tem) == LABEL_REF)
2501 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2502 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2510 /* If we reach here, all eliminations must be at their initial
2511 offset because we are doing a jump to a variable address. */
2512 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2513 if (p->offset != p->initial_offset)
2514 p->can_eliminate = 0;
2522 /* Scan X and replace any eliminable registers (such as fp) with a
2523 replacement (such as sp), plus an offset.
2525 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2526 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2527 MEM, we are allowed to replace a sum of a register and the constant zero
2528 with the register, which we cannot do outside a MEM. In addition, we need
2529 to record the fact that a register is referenced outside a MEM.
2531 If INSN is an insn, it is the insn containing X. If we replace a REG
2532 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2533 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2534 the REG is being modified.
2536 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2537 That's used when we eliminate in expressions stored in notes.
2538 This means, do not set ref_outside_mem even if the reference
2541 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2542 replacements done assuming all offsets are at their initial values. If
2543 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2544 encounter, return the actual location so that find_reloads will do
2545 the proper thing. */
2548 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2549 bool may_use_invariant)
2551 enum rtx_code code = GET_CODE (x);
2552 struct elim_table *ep;
2559 if (! current_function_decl)
2582 /* First handle the case where we encounter a bare register that
2583 is eliminable. Replace it with a PLUS. */
2584 if (regno < FIRST_PSEUDO_REGISTER)
2586 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2588 if (ep->from_rtx == x && ep->can_eliminate)
2589 return plus_constant (ep->to_rtx, ep->previous_offset);
2592 else if (reg_renumber && reg_renumber[regno] < 0
2593 && reg_equiv_invariant && reg_equiv_invariant[regno])
2595 if (may_use_invariant || (insn && DEBUG_INSN_P (insn)))
2596 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2597 mem_mode, insn, true);
2598 /* There exists at least one use of REGNO that cannot be
2599 eliminated. Prevent the defining insn from being deleted. */
2600 reg_equiv_init[regno] = NULL_RTX;
2601 alter_reg (regno, -1, true);
2605 /* You might think handling MINUS in a manner similar to PLUS is a
2606 good idea. It is not. It has been tried multiple times and every
2607 time the change has had to have been reverted.
2609 Other parts of reload know a PLUS is special (gen_reload for example)
2610 and require special code to handle code a reloaded PLUS operand.
2612 Also consider backends where the flags register is clobbered by a
2613 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2614 lea instruction comes to mind). If we try to reload a MINUS, we
2615 may kill the flags register that was holding a useful value.
2617 So, please before trying to handle MINUS, consider reload as a
2618 whole instead of this little section as well as the backend issues. */
2620 /* If this is the sum of an eliminable register and a constant, rework
2622 if (REG_P (XEXP (x, 0))
2623 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2624 && CONSTANT_P (XEXP (x, 1)))
2626 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2628 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2630 /* The only time we want to replace a PLUS with a REG (this
2631 occurs when the constant operand of the PLUS is the negative
2632 of the offset) is when we are inside a MEM. We won't want
2633 to do so at other times because that would change the
2634 structure of the insn in a way that reload can't handle.
2635 We special-case the commonest situation in
2636 eliminate_regs_in_insn, so just replace a PLUS with a
2637 PLUS here, unless inside a MEM. */
2638 if (mem_mode != 0 && CONST_INT_P (XEXP (x, 1))
2639 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2642 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2643 plus_constant (XEXP (x, 1),
2644 ep->previous_offset));
2647 /* If the register is not eliminable, we are done since the other
2648 operand is a constant. */
2652 /* If this is part of an address, we want to bring any constant to the
2653 outermost PLUS. We will do this by doing register replacement in
2654 our operands and seeing if a constant shows up in one of them.
2656 Note that there is no risk of modifying the structure of the insn,
2657 since we only get called for its operands, thus we are either
2658 modifying the address inside a MEM, or something like an address
2659 operand of a load-address insn. */
2662 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2663 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2665 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2667 /* If one side is a PLUS and the other side is a pseudo that
2668 didn't get a hard register but has a reg_equiv_constant,
2669 we must replace the constant here since it may no longer
2670 be in the position of any operand. */
2671 if (GET_CODE (new0) == PLUS && REG_P (new1)
2672 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2673 && reg_renumber[REGNO (new1)] < 0
2674 && reg_equiv_constant != 0
2675 && reg_equiv_constant[REGNO (new1)] != 0)
2676 new1 = reg_equiv_constant[REGNO (new1)];
2677 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2678 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2679 && reg_renumber[REGNO (new0)] < 0
2680 && reg_equiv_constant[REGNO (new0)] != 0)
2681 new0 = reg_equiv_constant[REGNO (new0)];
2683 new_rtx = form_sum (GET_MODE (x), new0, new1);
2685 /* As above, if we are not inside a MEM we do not want to
2686 turn a PLUS into something else. We might try to do so here
2687 for an addition of 0 if we aren't optimizing. */
2688 if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2689 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2697 /* If this is the product of an eliminable register and a
2698 constant, apply the distribute law and move the constant out
2699 so that we have (plus (mult ..) ..). This is needed in order
2700 to keep load-address insns valid. This case is pathological.
2701 We ignore the possibility of overflow here. */
2702 if (REG_P (XEXP (x, 0))
2703 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2704 && CONST_INT_P (XEXP (x, 1)))
2705 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2707 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2710 /* Refs inside notes or in DEBUG_INSNs don't count for
2712 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2713 || GET_CODE (insn) == INSN_LIST
2714 || DEBUG_INSN_P (insn))))
2715 ep->ref_outside_mem = 1;
2718 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2719 ep->previous_offset * INTVAL (XEXP (x, 1)));
2722 /* ... fall through ... */
2726 /* See comments before PLUS about handling MINUS. */
2728 case DIV: case UDIV:
2729 case MOD: case UMOD:
2730 case AND: case IOR: case XOR:
2731 case ROTATERT: case ROTATE:
2732 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2734 case GE: case GT: case GEU: case GTU:
2735 case LE: case LT: case LEU: case LTU:
2737 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2738 rtx new1 = XEXP (x, 1)
2739 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2741 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2742 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2747 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2750 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2751 if (new_rtx != XEXP (x, 0))
2753 /* If this is a REG_DEAD note, it is not valid anymore.
2754 Using the eliminated version could result in creating a
2755 REG_DEAD note for the stack or frame pointer. */
2756 if (REG_NOTE_KIND (x) == REG_DEAD)
2758 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2761 x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2765 /* ... fall through ... */
2768 /* Now do eliminations in the rest of the chain. If this was
2769 an EXPR_LIST, this might result in allocating more memory than is
2770 strictly needed, but it simplifies the code. */
2773 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2774 if (new_rtx != XEXP (x, 1))
2776 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2784 /* We do not support elimination of a register that is modified.
2785 elimination_effects has already make sure that this does not
2791 /* We do not support elimination of a register that is modified.
2792 elimination_effects has already make sure that this does not
2793 happen. The only remaining case we need to consider here is
2794 that the increment value may be an eliminable register. */
2795 if (GET_CODE (XEXP (x, 1)) == PLUS
2796 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2798 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2801 if (new_rtx != XEXP (XEXP (x, 1), 1))
2802 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2803 gen_rtx_PLUS (GET_MODE (x),
2804 XEXP (x, 0), new_rtx));
2808 case STRICT_LOW_PART:
2810 case SIGN_EXTEND: case ZERO_EXTEND:
2811 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2812 case FLOAT: case FIX:
2813 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2822 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2823 if (new_rtx != XEXP (x, 0))
2824 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2828 /* Similar to above processing, but preserve SUBREG_BYTE.
2829 Convert (subreg (mem)) to (mem) if not paradoxical.
2830 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2831 pseudo didn't get a hard reg, we must replace this with the
2832 eliminated version of the memory location because push_reload
2833 may do the replacement in certain circumstances. */
2834 if (REG_P (SUBREG_REG (x))
2835 && (GET_MODE_SIZE (GET_MODE (x))
2836 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2837 && reg_equiv_memory_loc != 0
2838 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2840 new_rtx = SUBREG_REG (x);
2843 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2845 if (new_rtx != SUBREG_REG (x))
2847 int x_size = GET_MODE_SIZE (GET_MODE (x));
2848 int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2851 && ((x_size < new_size
2852 #ifdef WORD_REGISTER_OPERATIONS
2853 /* On these machines, combine can create rtl of the form
2854 (set (subreg:m1 (reg:m2 R) 0) ...)
2855 where m1 < m2, and expects something interesting to
2856 happen to the entire word. Moreover, it will use the
2857 (reg:m2 R) later, expecting all bits to be preserved.
2858 So if the number of words is the same, preserve the
2859 subreg so that push_reload can see it. */
2860 && ! ((x_size - 1) / UNITS_PER_WORD
2861 == (new_size -1 ) / UNITS_PER_WORD)
2864 || x_size == new_size)
2866 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2868 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2874 /* Our only special processing is to pass the mode of the MEM to our
2875 recursive call and copy the flags. While we are here, handle this
2876 case more efficiently. */
2878 replace_equiv_address_nv (x,
2879 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2883 /* Handle insn_list USE that a call to a pure function may generate. */
2884 new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false);
2885 if (new_rtx != XEXP (x, 0))
2886 return gen_rtx_USE (GET_MODE (x), new_rtx);
2890 gcc_assert (insn && DEBUG_INSN_P (insn));
2901 /* Process each of our operands recursively. If any have changed, make a
2903 fmt = GET_RTX_FORMAT (code);
2904 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2908 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2909 if (new_rtx != XEXP (x, i) && ! copied)
2911 x = shallow_copy_rtx (x);
2914 XEXP (x, i) = new_rtx;
2916 else if (*fmt == 'E')
2919 for (j = 0; j < XVECLEN (x, i); j++)
2921 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2922 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2924 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2928 x = shallow_copy_rtx (x);
2931 XVEC (x, i) = new_v;
2934 XVECEXP (x, i, j) = new_rtx;
2943 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2945 return eliminate_regs_1 (x, mem_mode, insn, false);
2948 /* Scan rtx X for modifications of elimination target registers. Update
2949 the table of eliminables to reflect the changed state. MEM_MODE is
2950 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2953 elimination_effects (rtx x, enum machine_mode mem_mode)
2955 enum rtx_code code = GET_CODE (x);
2956 struct elim_table *ep;
2981 /* First handle the case where we encounter a bare register that
2982 is eliminable. Replace it with a PLUS. */
2983 if (regno < FIRST_PSEUDO_REGISTER)
2985 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2987 if (ep->from_rtx == x && ep->can_eliminate)
2990 ep->ref_outside_mem = 1;
2995 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2996 && reg_equiv_constant[regno]
2997 && ! function_invariant_p (reg_equiv_constant[regno]))
2998 elimination_effects (reg_equiv_constant[regno], mem_mode);
3007 /* If we modify the source of an elimination rule, disable it. */
3008 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3009 if (ep->from_rtx == XEXP (x, 0))
3010 ep->can_eliminate = 0;
3012 /* If we modify the target of an elimination rule by adding a constant,
3013 update its offset. If we modify the target in any other way, we'll
3014 have to disable the rule as well. */
3015 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3016 if (ep->to_rtx == XEXP (x, 0))
3018 int size = GET_MODE_SIZE (mem_mode);
3020 /* If more bytes than MEM_MODE are pushed, account for them. */
3021 #ifdef PUSH_ROUNDING
3022 if (ep->to_rtx == stack_pointer_rtx)
3023 size = PUSH_ROUNDING (size);
3025 if (code == PRE_DEC || code == POST_DEC)
3027 else if (code == PRE_INC || code == POST_INC)
3029 else if (code == PRE_MODIFY || code == POST_MODIFY)
3031 if (GET_CODE (XEXP (x, 1)) == PLUS
3032 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
3033 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
3034 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
3036 ep->can_eliminate = 0;
3040 /* These two aren't unary operators. */
3041 if (code == POST_MODIFY || code == PRE_MODIFY)
3044 /* Fall through to generic unary operation case. */
3045 case STRICT_LOW_PART:
3047 case SIGN_EXTEND: case ZERO_EXTEND:
3048 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3049 case FLOAT: case FIX:
3050 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3059 elimination_effects (XEXP (x, 0), mem_mode);
3063 if (REG_P (SUBREG_REG (x))
3064 && (GET_MODE_SIZE (GET_MODE (x))
3065 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3066 && reg_equiv_memory_loc != 0
3067 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
3070 elimination_effects (SUBREG_REG (x), mem_mode);
3074 /* If using a register that is the source of an eliminate we still
3075 think can be performed, note it cannot be performed since we don't
3076 know how this register is used. */
3077 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3078 if (ep->from_rtx == XEXP (x, 0))
3079 ep->can_eliminate = 0;
3081 elimination_effects (XEXP (x, 0), mem_mode);
3085 /* If clobbering a register that is the replacement register for an
3086 elimination we still think can be performed, note that it cannot
3087 be performed. Otherwise, we need not be concerned about it. */
3088 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3089 if (ep->to_rtx == XEXP (x, 0))
3090 ep->can_eliminate = 0;
3092 elimination_effects (XEXP (x, 0), mem_mode);
3096 /* Check for setting a register that we know about. */
3097 if (REG_P (SET_DEST (x)))
3099 /* See if this is setting the replacement register for an
3102 If DEST is the hard frame pointer, we do nothing because we
3103 assume that all assignments to the frame pointer are for
3104 non-local gotos and are being done at a time when they are valid
3105 and do not disturb anything else. Some machines want to
3106 eliminate a fake argument pointer (or even a fake frame pointer)
3107 with either the real frame or the stack pointer. Assignments to
3108 the hard frame pointer must not prevent this elimination. */
3110 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3112 if (ep->to_rtx == SET_DEST (x)
3113 && SET_DEST (x) != hard_frame_pointer_rtx)
3115 /* If it is being incremented, adjust the offset. Otherwise,
3116 this elimination can't be done. */
3117 rtx src = SET_SRC (x);
3119 if (GET_CODE (src) == PLUS
3120 && XEXP (src, 0) == SET_DEST (x)
3121 && CONST_INT_P (XEXP (src, 1)))
3122 ep->offset -= INTVAL (XEXP (src, 1));
3124 ep->can_eliminate = 0;
3128 elimination_effects (SET_DEST (x), VOIDmode);
3129 elimination_effects (SET_SRC (x), VOIDmode);
3133 /* Our only special processing is to pass the mode of the MEM to our
3135 elimination_effects (XEXP (x, 0), GET_MODE (x));
3142 fmt = GET_RTX_FORMAT (code);
3143 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3146 elimination_effects (XEXP (x, i), mem_mode);
3147 else if (*fmt == 'E')
3148 for (j = 0; j < XVECLEN (x, i); j++)
3149 elimination_effects (XVECEXP (x, i, j), mem_mode);
3153 /* Descend through rtx X and verify that no references to eliminable registers
3154 remain. If any do remain, mark the involved register as not
3158 check_eliminable_occurrences (rtx x)
3167 code = GET_CODE (x);
3169 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3171 struct elim_table *ep;
3173 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3174 if (ep->from_rtx == x)
3175 ep->can_eliminate = 0;
3179 fmt = GET_RTX_FORMAT (code);
3180 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3183 check_eliminable_occurrences (XEXP (x, i));
3184 else if (*fmt == 'E')
3187 for (j = 0; j < XVECLEN (x, i); j++)
3188 check_eliminable_occurrences (XVECEXP (x, i, j));
3193 /* Scan INSN and eliminate all eliminable registers in it.
3195 If REPLACE is nonzero, do the replacement destructively. Also
3196 delete the insn as dead it if it is setting an eliminable register.
3198 If REPLACE is zero, do all our allocations in reload_obstack.
3200 If no eliminations were done and this insn doesn't require any elimination
3201 processing (these are not identical conditions: it might be updating sp,
3202 but not referencing fp; this needs to be seen during reload_as_needed so
3203 that the offset between fp and sp can be taken into consideration), zero
3204 is returned. Otherwise, 1 is returned. */
3207 eliminate_regs_in_insn (rtx insn, int replace)
3209 int icode = recog_memoized (insn);
3210 rtx old_body = PATTERN (insn);
3211 int insn_is_asm = asm_noperands (old_body) >= 0;
3212 rtx old_set = single_set (insn);
3216 rtx substed_operand[MAX_RECOG_OPERANDS];
3217 rtx orig_operand[MAX_RECOG_OPERANDS];
3218 struct elim_table *ep;
3219 rtx plus_src, plus_cst_src;
3221 if (! insn_is_asm && icode < 0)
3223 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3224 || GET_CODE (PATTERN (insn)) == CLOBBER
3225 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3226 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3227 || GET_CODE (PATTERN (insn)) == ASM_INPUT
3228 || DEBUG_INSN_P (insn));
3229 if (DEBUG_INSN_P (insn))
3230 INSN_VAR_LOCATION_LOC (insn)
3231 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn), VOIDmode, insn);
3235 if (old_set != 0 && REG_P (SET_DEST (old_set))
3236 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3238 /* Check for setting an eliminable register. */
3239 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3240 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3242 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3243 /* If this is setting the frame pointer register to the
3244 hardware frame pointer register and this is an elimination
3245 that will be done (tested above), this insn is really
3246 adjusting the frame pointer downward to compensate for
3247 the adjustment done before a nonlocal goto. */
3248 if (ep->from == FRAME_POINTER_REGNUM
3249 && ep->to == HARD_FRAME_POINTER_REGNUM)
3251 rtx base = SET_SRC (old_set);
3252 rtx base_insn = insn;
3253 HOST_WIDE_INT offset = 0;
3255 while (base != ep->to_rtx)
3257 rtx prev_insn, prev_set;
3259 if (GET_CODE (base) == PLUS
3260 && CONST_INT_P (XEXP (base, 1)))
3262 offset += INTVAL (XEXP (base, 1));
3263 base = XEXP (base, 0);
3265 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3266 && (prev_set = single_set (prev_insn)) != 0
3267 && rtx_equal_p (SET_DEST (prev_set), base))
3269 base = SET_SRC (prev_set);
3270 base_insn = prev_insn;
3276 if (base == ep->to_rtx)
3279 = plus_constant (ep->to_rtx, offset - ep->offset);
3281 new_body = old_body;
3284 new_body = copy_insn (old_body);
3285 if (REG_NOTES (insn))
3286 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3288 PATTERN (insn) = new_body;
3289 old_set = single_set (insn);
3291 /* First see if this insn remains valid when we
3292 make the change. If not, keep the INSN_CODE
3293 the same and let reload fit it up. */
3294 validate_change (insn, &SET_SRC (old_set), src, 1);
3295 validate_change (insn, &SET_DEST (old_set),
3297 if (! apply_change_group ())
3299 SET_SRC (old_set) = src;
3300 SET_DEST (old_set) = ep->to_rtx;
3309 /* In this case this insn isn't serving a useful purpose. We
3310 will delete it in reload_as_needed once we know that this
3311 elimination is, in fact, being done.
3313 If REPLACE isn't set, we can't delete this insn, but needn't
3314 process it since it won't be used unless something changes. */
3317 delete_dead_insn (insn);
3325 /* We allow one special case which happens to work on all machines we
3326 currently support: a single set with the source or a REG_EQUAL
3327 note being a PLUS of an eliminable register and a constant. */
3328 plus_src = plus_cst_src = 0;
3329 if (old_set && REG_P (SET_DEST (old_set)))
3331 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3332 plus_src = SET_SRC (old_set);
3333 /* First see if the source is of the form (plus (...) CST). */
3335 && CONST_INT_P (XEXP (plus_src, 1)))
3336 plus_cst_src = plus_src;
3337 else if (REG_P (SET_SRC (old_set))
3340 /* Otherwise, see if we have a REG_EQUAL note of the form
3341 (plus (...) CST). */
3343 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3345 if ((REG_NOTE_KIND (links) == REG_EQUAL
3346 || REG_NOTE_KIND (links) == REG_EQUIV)
3347 && GET_CODE (XEXP (links, 0)) == PLUS
3348 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3350 plus_cst_src = XEXP (links, 0);
3356 /* Check that the first operand of the PLUS is a hard reg or
3357 the lowpart subreg of one. */
3360 rtx reg = XEXP (plus_cst_src, 0);
3361 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3362 reg = SUBREG_REG (reg);
3364 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3370 rtx reg = XEXP (plus_cst_src, 0);
3371 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3373 if (GET_CODE (reg) == SUBREG)
3374 reg = SUBREG_REG (reg);
3376 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3377 if (ep->from_rtx == reg && ep->can_eliminate)
3379 rtx to_rtx = ep->to_rtx;
3380 offset += ep->offset;
3381 offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3383 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3384 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3386 /* If we have a nonzero offset, and the source is already
3387 a simple REG, the following transformation would
3388 increase the cost of the insn by replacing a simple REG
3389 with (plus (reg sp) CST). So try only when we already
3390 had a PLUS before. */
3391 if (offset == 0 || plus_src)
3393 rtx new_src = plus_constant (to_rtx, offset);
3395 new_body = old_body;
3398 new_body = copy_insn (old_body);
3399 if (REG_NOTES (insn))
3400 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3402 PATTERN (insn) = new_body;
3403 old_set = single_set (insn);
3405 /* First see if this insn remains valid when we make the
3406 change. If not, try to replace the whole pattern with
3407 a simple set (this may help if the original insn was a
3408 PARALLEL that was only recognized as single_set due to
3409 REG_UNUSED notes). If this isn't valid either, keep
3410 the INSN_CODE the same and let reload fix it up. */
3411 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3413 rtx new_pat = gen_rtx_SET (VOIDmode,
3414 SET_DEST (old_set), new_src);
3416 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3417 SET_SRC (old_set) = new_src;
3424 /* This can't have an effect on elimination offsets, so skip right
3430 /* Determine the effects of this insn on elimination offsets. */
3431 elimination_effects (old_body, VOIDmode);
3433 /* Eliminate all eliminable registers occurring in operands that
3434 can be handled by reload. */
3435 extract_insn (insn);
3436 for (i = 0; i < recog_data.n_operands; i++)
3438 orig_operand[i] = recog_data.operand[i];
3439 substed_operand[i] = recog_data.operand[i];
3441 /* For an asm statement, every operand is eliminable. */
3442 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3444 bool is_set_src, in_plus;
3446 /* Check for setting a register that we know about. */
3447 if (recog_data.operand_type[i] != OP_IN
3448 && REG_P (orig_operand[i]))
3450 /* If we are assigning to a register that can be eliminated, it
3451 must be as part of a PARALLEL, since the code above handles
3452 single SETs. We must indicate that we can no longer
3453 eliminate this reg. */
3454 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3456 if (ep->from_rtx == orig_operand[i])
3457 ep->can_eliminate = 0;
3460 /* Companion to the above plus substitution, we can allow
3461 invariants as the source of a plain move. */
3463 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3467 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3468 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3472 = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3473 replace ? insn : NULL_RTX,
3474 is_set_src || in_plus);
3475 if (substed_operand[i] != orig_operand[i])
3477 /* Terminate the search in check_eliminable_occurrences at
3479 *recog_data.operand_loc[i] = 0;
3481 /* If an output operand changed from a REG to a MEM and INSN is an
3482 insn, write a CLOBBER insn. */
3483 if (recog_data.operand_type[i] != OP_IN
3484 && REG_P (orig_operand[i])
3485 && MEM_P (substed_operand[i])
3487 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3491 for (i = 0; i < recog_data.n_dups; i++)
3492 *recog_data.dup_loc[i]
3493 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3495 /* If any eliminable remain, they aren't eliminable anymore. */
3496 check_eliminable_occurrences (old_body);
3498 /* Substitute the operands; the new values are in the substed_operand
3500 for (i = 0; i < recog_data.n_operands; i++)
3501 *recog_data.operand_loc[i] = substed_operand[i];
3502 for (i = 0; i < recog_data.n_dups; i++)
3503 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3505 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3506 re-recognize the insn. We do this in case we had a simple addition
3507 but now can do this as a load-address. This saves an insn in this
3509 If re-recognition fails, the old insn code number will still be used,
3510 and some register operands may have changed into PLUS expressions.
3511 These will be handled by find_reloads by loading them into a register
3516 /* If we aren't replacing things permanently and we changed something,
3517 make another copy to ensure that all the RTL is new. Otherwise
3518 things can go wrong if find_reload swaps commutative operands
3519 and one is inside RTL that has been copied while the other is not. */
3520 new_body = old_body;
3523 new_body = copy_insn (old_body);
3524 if (REG_NOTES (insn))
3525 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3527 PATTERN (insn) = new_body;
3529 /* If we had a move insn but now we don't, rerecognize it. This will
3530 cause spurious re-recognition if the old move had a PARALLEL since
3531 the new one still will, but we can't call single_set without
3532 having put NEW_BODY into the insn and the re-recognition won't
3533 hurt in this rare case. */
3534 /* ??? Why this huge if statement - why don't we just rerecognize the
3538 && ((REG_P (SET_SRC (old_set))
3539 && (GET_CODE (new_body) != SET
3540 || !REG_P (SET_SRC (new_body))))
3541 /* If this was a load from or store to memory, compare
3542 the MEM in recog_data.operand to the one in the insn.
3543 If they are not equal, then rerecognize the insn. */
3545 && ((MEM_P (SET_SRC (old_set))
3546 && SET_SRC (old_set) != recog_data.operand[1])
3547 || (MEM_P (SET_DEST (old_set))
3548 && SET_DEST (old_set) != recog_data.operand[0])))
3549 /* If this was an add insn before, rerecognize. */
3550 || GET_CODE (SET_SRC (old_set)) == PLUS))
3552 int new_icode = recog (PATTERN (insn), insn, 0);
3554 INSN_CODE (insn) = new_icode;
3558 /* Restore the old body. If there were any changes to it, we made a copy
3559 of it while the changes were still in place, so we'll correctly return
3560 a modified insn below. */
3563 /* Restore the old body. */
3564 for (i = 0; i < recog_data.n_operands; i++)
3565 /* Restoring a top-level match_parallel would clobber the new_body
3566 we installed in the insn. */
3567 if (recog_data.operand_loc[i] != &PATTERN (insn))
3568 *recog_data.operand_loc[i] = orig_operand[i];
3569 for (i = 0; i < recog_data.n_dups; i++)
3570 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3573 /* Update all elimination pairs to reflect the status after the current
3574 insn. The changes we make were determined by the earlier call to
3575 elimination_effects.
3577 We also detect cases where register elimination cannot be done,
3578 namely, if a register would be both changed and referenced outside a MEM
3579 in the resulting insn since such an insn is often undefined and, even if
3580 not, we cannot know what meaning will be given to it. Note that it is
3581 valid to have a register used in an address in an insn that changes it
3582 (presumably with a pre- or post-increment or decrement).
3584 If anything changes, return nonzero. */
3586 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3588 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3589 ep->can_eliminate = 0;
3591 ep->ref_outside_mem = 0;
3593 if (ep->previous_offset != ep->offset)
3598 /* If we changed something, perform elimination in REG_NOTES. This is
3599 needed even when REPLACE is zero because a REG_DEAD note might refer
3600 to a register that we eliminate and could cause a different number
3601 of spill registers to be needed in the final reload pass than in
3603 if (val && REG_NOTES (insn) != 0)
3605 = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true);
3610 /* Loop through all elimination pairs.
3611 Recalculate the number not at initial offset.
3613 Compute the maximum offset (minimum offset if the stack does not
3614 grow downward) for each elimination pair. */
3617 update_eliminable_offsets (void)
3619 struct elim_table *ep;
3621 num_not_at_initial_offset = 0;
3622 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3624 ep->previous_offset = ep->offset;
3625 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3626 num_not_at_initial_offset++;
3630 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3631 replacement we currently believe is valid, mark it as not eliminable if X
3632 modifies DEST in any way other than by adding a constant integer to it.
3634 If DEST is the frame pointer, we do nothing because we assume that
3635 all assignments to the hard frame pointer are nonlocal gotos and are being
3636 done at a time when they are valid and do not disturb anything else.
3637 Some machines want to eliminate a fake argument pointer with either the
3638 frame or stack pointer. Assignments to the hard frame pointer must not
3639 prevent this elimination.
3641 Called via note_stores from reload before starting its passes to scan
3642 the insns of the function. */
3645 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3649 /* A SUBREG of a hard register here is just changing its mode. We should
3650 not see a SUBREG of an eliminable hard register, but check just in
3652 if (GET_CODE (dest) == SUBREG)
3653 dest = SUBREG_REG (dest);
3655 if (dest == hard_frame_pointer_rtx)
3658 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3659 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3660 && (GET_CODE (x) != SET
3661 || GET_CODE (SET_SRC (x)) != PLUS
3662 || XEXP (SET_SRC (x), 0) != dest
3663 || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
3665 reg_eliminate[i].can_eliminate_previous
3666 = reg_eliminate[i].can_eliminate = 0;
3671 /* Verify that the initial elimination offsets did not change since the
3672 last call to set_initial_elim_offsets. This is used to catch cases
3673 where something illegal happened during reload_as_needed that could
3674 cause incorrect code to be generated if we did not check for it. */
3677 verify_initial_elim_offsets (void)
3681 if (!num_eliminable)
3684 #ifdef ELIMINABLE_REGS
3686 struct elim_table *ep;
3688 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3690 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3691 if (t != ep->initial_offset)
3696 INITIAL_FRAME_POINTER_OFFSET (t);
3697 if (t != reg_eliminate[0].initial_offset)
3704 /* Reset all offsets on eliminable registers to their initial values. */
3707 set_initial_elim_offsets (void)
3709 struct elim_table *ep = reg_eliminate;
3711 #ifdef ELIMINABLE_REGS
3712 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3714 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3715 ep->previous_offset = ep->offset = ep->initial_offset;
3718 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3719 ep->previous_offset = ep->offset = ep->initial_offset;
3722 num_not_at_initial_offset = 0;
3725 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3728 set_initial_eh_label_offset (rtx label)
3730 set_label_offsets (label, NULL_RTX, 1);
3733 /* Initialize the known label offsets.
3734 Set a known offset for each forced label to be at the initial offset
3735 of each elimination. We do this because we assume that all
3736 computed jumps occur from a location where each elimination is
3737 at its initial offset.
3738 For all other labels, show that we don't know the offsets. */
3741 set_initial_label_offsets (void)
3744 memset (offsets_known_at, 0, num_labels);
3746 for (x = forced_labels; x; x = XEXP (x, 1))
3748 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3750 for_each_eh_label (set_initial_eh_label_offset);
3753 /* Set all elimination offsets to the known values for the code label given
3757 set_offsets_for_label (rtx insn)
3760 int label_nr = CODE_LABEL_NUMBER (insn);
3761 struct elim_table *ep;
3763 num_not_at_initial_offset = 0;
3764 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3766 ep->offset = ep->previous_offset
3767 = offsets_at[label_nr - first_label_num][i];
3768 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3769 num_not_at_initial_offset++;
3773 /* See if anything that happened changes which eliminations are valid.
3774 For example, on the SPARC, whether or not the frame pointer can
3775 be eliminated can depend on what registers have been used. We need
3776 not check some conditions again (such as flag_omit_frame_pointer)
3777 since they can't have changed. */
3780 update_eliminables (HARD_REG_SET *pset)
3782 int previous_frame_pointer_needed = frame_pointer_needed;
3783 struct elim_table *ep;
3785 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3786 if ((ep->from == HARD_FRAME_POINTER_REGNUM
3787 && targetm.frame_pointer_required ())
3788 #ifdef ELIMINABLE_REGS
3789 || ! targetm.can_eliminate (ep->from, ep->to)
3792 ep->can_eliminate = 0;
3794 /* Look for the case where we have discovered that we can't replace
3795 register A with register B and that means that we will now be
3796 trying to replace register A with register C. This means we can
3797 no longer replace register C with register B and we need to disable
3798 such an elimination, if it exists. This occurs often with A == ap,
3799 B == sp, and C == fp. */
3801 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3803 struct elim_table *op;
3806 if (! ep->can_eliminate && ep->can_eliminate_previous)
3808 /* Find the current elimination for ep->from, if there is a
3810 for (op = reg_eliminate;
3811 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3812 if (op->from == ep->from && op->can_eliminate)
3818 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3820 for (op = reg_eliminate;
3821 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3822 if (op->from == new_to && op->to == ep->to)
3823 op->can_eliminate = 0;
3827 /* See if any registers that we thought we could eliminate the previous
3828 time are no longer eliminable. If so, something has changed and we
3829 must spill the register. Also, recompute the number of eliminable
3830 registers and see if the frame pointer is needed; it is if there is
3831 no elimination of the frame pointer that we can perform. */
3833 frame_pointer_needed = 1;
3834 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3836 if (ep->can_eliminate
3837 && ep->from == FRAME_POINTER_REGNUM
3838 && ep->to != HARD_FRAME_POINTER_REGNUM
3839 && (! SUPPORTS_STACK_ALIGNMENT
3840 || ! crtl->stack_realign_needed))
3841 frame_pointer_needed = 0;
3843 if (! ep->can_eliminate && ep->can_eliminate_previous)
3845 ep->can_eliminate_previous = 0;
3846 SET_HARD_REG_BIT (*pset, ep->from);
3851 /* If we didn't need a frame pointer last time, but we do now, spill
3852 the hard frame pointer. */
3853 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3854 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3857 /* Return true if X is used as the target register of an elimination. */
3860 elimination_target_reg_p (rtx x)
3862 struct elim_table *ep;
3864 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3865 if (ep->to_rtx == x && ep->can_eliminate)
3871 /* Initialize the table of registers to eliminate.
3872 Pre-condition: global flag frame_pointer_needed has been set before
3873 calling this function. */
3876 init_elim_table (void)
3878 struct elim_table *ep;
3879 #ifdef ELIMINABLE_REGS
3880 const struct elim_table_1 *ep1;
3884 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
3888 #ifdef ELIMINABLE_REGS
3889 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3890 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3892 ep->from = ep1->from;
3894 ep->can_eliminate = ep->can_eliminate_previous
3895 = (targetm.can_eliminate (ep->from, ep->to)
3896 && ! (ep->to == STACK_POINTER_REGNUM
3897 && frame_pointer_needed
3898 && (! SUPPORTS_STACK_ALIGNMENT
3899 || ! stack_realign_fp)));
3902 reg_eliminate[0].from = reg_eliminate_1[0].from;
3903 reg_eliminate[0].to = reg_eliminate_1[0].to;
3904 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3905 = ! frame_pointer_needed;
3908 /* Count the number of eliminable registers and build the FROM and TO
3909 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3910 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3911 We depend on this. */
3912 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3914 num_eliminable += ep->can_eliminate;
3915 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3916 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3920 /* Kick all pseudos out of hard register REGNO.
3922 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3923 because we found we can't eliminate some register. In the case, no pseudos
3924 are allowed to be in the register, even if they are only in a block that
3925 doesn't require spill registers, unlike the case when we are spilling this
3926 hard reg to produce another spill register.
3928 Return nonzero if any pseudos needed to be kicked out. */
3931 spill_hard_reg (unsigned int regno, int cant_eliminate)
3937 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3938 df_set_regs_ever_live (regno, true);
3941 /* Spill every pseudo reg that was allocated to this reg
3942 or to something that overlaps this reg. */
3944 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3945 if (reg_renumber[i] >= 0
3946 && (unsigned int) reg_renumber[i] <= regno
3947 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
3948 SET_REGNO_REG_SET (&spilled_pseudos, i);
3951 /* After find_reload_regs has been run for all insn that need reloads,
3952 and/or spill_hard_regs was called, this function is used to actually
3953 spill pseudo registers and try to reallocate them. It also sets up the
3954 spill_regs array for use by choose_reload_regs. */
3957 finish_spills (int global)
3959 struct insn_chain *chain;
3960 int something_changed = 0;
3962 reg_set_iterator rsi;
3964 /* Build the spill_regs array for the function. */
3965 /* If there are some registers still to eliminate and one of the spill regs
3966 wasn't ever used before, additional stack space may have to be
3967 allocated to store this register. Thus, we may have changed the offset
3968 between the stack and frame pointers, so mark that something has changed.
3970 One might think that we need only set VAL to 1 if this is a call-used
3971 register. However, the set of registers that must be saved by the
3972 prologue is not identical to the call-used set. For example, the
3973 register used by the call insn for the return PC is a call-used register,
3974 but must be saved by the prologue. */
3977 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3978 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3980 spill_reg_order[i] = n_spills;
3981 spill_regs[n_spills++] = i;
3982 if (num_eliminable && ! df_regs_ever_live_p (i))
3983 something_changed = 1;
3984 df_set_regs_ever_live (i, true);
3987 spill_reg_order[i] = -1;
3989 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3990 if (! ira_conflicts_p || reg_renumber[i] >= 0)
3992 /* Record the current hard register the pseudo is allocated to
3993 in pseudo_previous_regs so we avoid reallocating it to the
3994 same hard reg in a later pass. */
3995 gcc_assert (reg_renumber[i] >= 0);
3997 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3998 /* Mark it as no longer having a hard register home. */
3999 reg_renumber[i] = -1;
4000 if (ira_conflicts_p)
4001 /* Inform IRA about the change. */
4002 ira_mark_allocation_change (i);
4003 /* We will need to scan everything again. */
4004 something_changed = 1;
4007 /* Retry global register allocation if possible. */
4008 if (global && ira_conflicts_p)
4012 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
4013 /* For every insn that needs reloads, set the registers used as spill
4014 regs in pseudo_forbidden_regs for every pseudo live across the
4016 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
4018 EXECUTE_IF_SET_IN_REG_SET
4019 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
4021 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4022 chain->used_spill_regs);
4024 EXECUTE_IF_SET_IN_REG_SET
4025 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
4027 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4028 chain->used_spill_regs);
4032 /* Retry allocating the pseudos spilled in IRA and the
4033 reload. For each reg, merge the various reg sets that
4034 indicate which hard regs can't be used, and call
4035 ira_reassign_pseudos. */
4036 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4037 if (reg_old_renumber[i] != reg_renumber[i])
4039 if (reg_renumber[i] < 0)
4040 temp_pseudo_reg_arr[n++] = i;
4042 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4044 if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4045 bad_spill_regs_global,
4046 pseudo_forbidden_regs, pseudo_previous_regs,
4048 something_changed = 1;
4050 /* Fix up the register information in the insn chain.
4051 This involves deleting those of the spilled pseudos which did not get
4052 a new hard register home from the live_{before,after} sets. */
4053 for (chain = reload_insn_chain; chain; chain = chain->next)
4055 HARD_REG_SET used_by_pseudos;
4056 HARD_REG_SET used_by_pseudos2;
4058 if (! ira_conflicts_p)
4060 /* Don't do it for IRA because IRA and the reload still can
4061 assign hard registers to the spilled pseudos on next
4062 reload iterations. */
4063 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4064 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4066 /* Mark any unallocated hard regs as available for spills. That
4067 makes inheritance work somewhat better. */
4068 if (chain->need_reload)
4070 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4071 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4072 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4074 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4075 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4076 /* Value of chain->used_spill_regs from previous iteration
4077 may be not included in the value calculated here because
4078 of possible removing caller-saves insns (see function
4079 delete_caller_save_insns. */
4080 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4081 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4085 CLEAR_REG_SET (&changed_allocation_pseudos);
4086 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4087 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4089 int regno = reg_renumber[i];
4090 if (reg_old_renumber[i] == regno)
4093 SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4095 alter_reg (i, reg_old_renumber[i], false);
4096 reg_old_renumber[i] = regno;
4100 fprintf (dump_file, " Register %d now on stack.\n\n", i);
4102 fprintf (dump_file, " Register %d now in %d.\n\n",
4103 i, reg_renumber[i]);
4107 return something_changed;
4110 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4113 scan_paradoxical_subregs (rtx x)
4117 enum rtx_code code = GET_CODE (x);
4128 case CONST_VECTOR: /* shouldn't happen, but just in case. */
4136 if (REG_P (SUBREG_REG (x))
4137 && (GET_MODE_SIZE (GET_MODE (x))
4138 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
4140 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4141 = GET_MODE_SIZE (GET_MODE (x));
4142 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
4150 fmt = GET_RTX_FORMAT (code);
4151 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4154 scan_paradoxical_subregs (XEXP (x, i));
4155 else if (fmt[i] == 'E')
4158 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4159 scan_paradoxical_subregs (XVECEXP (x, i, j));
4164 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4165 examine all of the reload insns between PREV and NEXT exclusive, and
4166 annotate all that may trap. */
4169 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
4171 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4174 if (!insn_could_throw_p (insn))
4175 remove_note (insn, note);
4176 copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next);
4179 /* Reload pseudo-registers into hard regs around each insn as needed.
4180 Additional register load insns are output before the insn that needs it
4181 and perhaps store insns after insns that modify the reloaded pseudo reg.
4183 reg_last_reload_reg and reg_reloaded_contents keep track of
4184 which registers are already available in reload registers.
4185 We update these for the reloads that we perform,
4186 as the insns are scanned. */
4189 reload_as_needed (int live_known)
4191 struct insn_chain *chain;
4192 #if defined (AUTO_INC_DEC)
4197 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4198 memset (spill_reg_store, 0, sizeof spill_reg_store);
4199 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4200 INIT_REG_SET (®_has_output_reload);
4201 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4202 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4204 set_initial_elim_offsets ();
4206 for (chain = reload_insn_chain; chain; chain = chain->next)
4209 rtx insn = chain->insn;
4210 rtx old_next = NEXT_INSN (insn);
4212 rtx old_prev = PREV_INSN (insn);
4215 /* If we pass a label, copy the offsets from the label information
4216 into the current offsets of each elimination. */
4218 set_offsets_for_label (insn);
4220 else if (INSN_P (insn))
4222 regset_head regs_to_forget;
4223 INIT_REG_SET (®s_to_forget);
4224 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4226 /* If this is a USE and CLOBBER of a MEM, ensure that any
4227 references to eliminable registers have been removed. */
4229 if ((GET_CODE (PATTERN (insn)) == USE
4230 || GET_CODE (PATTERN (insn)) == CLOBBER)
4231 && MEM_P (XEXP (PATTERN (insn), 0)))
4232 XEXP (XEXP (PATTERN (insn), 0), 0)
4233 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4234 GET_MODE (XEXP (PATTERN (insn), 0)),
4237 /* If we need to do register elimination processing, do so.
4238 This might delete the insn, in which case we are done. */
4239 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4241 eliminate_regs_in_insn (insn, 1);
4244 update_eliminable_offsets ();
4245 CLEAR_REG_SET (®s_to_forget);
4250 /* If need_elim is nonzero but need_reload is zero, one might think
4251 that we could simply set n_reloads to 0. However, find_reloads
4252 could have done some manipulation of the insn (such as swapping
4253 commutative operands), and these manipulations are lost during
4254 the first pass for every insn that needs register elimination.
4255 So the actions of find_reloads must be redone here. */
4257 if (! chain->need_elim && ! chain->need_reload
4258 && ! chain->need_operand_change)
4260 /* First find the pseudo regs that must be reloaded for this insn.
4261 This info is returned in the tables reload_... (see reload.h).
4262 Also modify the body of INSN by substituting RELOAD
4263 rtx's for those pseudo regs. */
4266 CLEAR_REG_SET (®_has_output_reload);
4267 CLEAR_HARD_REG_SET (reg_is_output_reload);
4269 find_reloads (insn, 1, spill_indirect_levels, live_known,
4275 rtx next = NEXT_INSN (insn);
4278 prev = PREV_INSN (insn);
4280 /* Now compute which reload regs to reload them into. Perhaps
4281 reusing reload regs from previous insns, or else output
4282 load insns to reload them. Maybe output store insns too.
4283 Record the choices of reload reg in reload_reg_rtx. */
4284 choose_reload_regs (chain);
4286 /* Merge any reloads that we didn't combine for fear of
4287 increasing the number of spill registers needed but now
4288 discover can be safely merged. */
4289 if (targetm.small_register_classes_for_mode_p (VOIDmode))
4290 merge_assigned_reloads (insn);
4292 /* Generate the insns to reload operands into or out of
4293 their reload regs. */
4294 emit_reload_insns (chain);
4296 /* Substitute the chosen reload regs from reload_reg_rtx
4297 into the insn's body (or perhaps into the bodies of other
4298 load and store insn that we just made for reloading
4299 and that we moved the structure into). */
4300 subst_reloads (insn);
4302 /* Adjust the exception region notes for loads and stores. */
4303 if (flag_non_call_exceptions && !CALL_P (insn))
4304 fixup_eh_region_note (insn, prev, next);
4306 /* If this was an ASM, make sure that all the reload insns
4307 we have generated are valid. If not, give an error
4309 if (asm_noperands (PATTERN (insn)) >= 0)
4310 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4311 if (p != insn && INSN_P (p)
4312 && GET_CODE (PATTERN (p)) != USE
4313 && (recog_memoized (p) < 0
4314 || (extract_insn (p), ! constrain_operands (1))))
4316 error_for_asm (insn,
4317 "%<asm%> operand requires "
4318 "impossible reload");
4323 if (num_eliminable && chain->need_elim)
4324 update_eliminable_offsets ();
4326 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4327 is no longer validly lying around to save a future reload.
4328 Note that this does not detect pseudos that were reloaded
4329 for this insn in order to be stored in
4330 (obeying register constraints). That is correct; such reload
4331 registers ARE still valid. */
4332 forget_marked_reloads (®s_to_forget);
4333 CLEAR_REG_SET (®s_to_forget);
4335 /* There may have been CLOBBER insns placed after INSN. So scan
4336 between INSN and NEXT and use them to forget old reloads. */
4337 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4338 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4339 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4342 /* Likewise for regs altered by auto-increment in this insn.
4343 REG_INC notes have been changed by reloading:
4344 find_reloads_address_1 records substitutions for them,
4345 which have been performed by subst_reloads above. */
4346 for (i = n_reloads - 1; i >= 0; i--)
4348 rtx in_reg = rld[i].in_reg;
4351 enum rtx_code code = GET_CODE (in_reg);
4352 /* PRE_INC / PRE_DEC will have the reload register ending up
4353 with the same value as the stack slot, but that doesn't
4354 hold true for POST_INC / POST_DEC. Either we have to
4355 convert the memory access to a true POST_INC / POST_DEC,
4356 or we can't use the reload register for inheritance. */
4357 if ((code == POST_INC || code == POST_DEC)
4358 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4359 REGNO (rld[i].reg_rtx))
4360 /* Make sure it is the inc/dec pseudo, and not
4361 some other (e.g. output operand) pseudo. */
4362 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4363 == REGNO (XEXP (in_reg, 0))))
4366 rtx reload_reg = rld[i].reg_rtx;
4367 enum machine_mode mode = GET_MODE (reload_reg);
4371 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4373 /* We really want to ignore REG_INC notes here, so
4374 use PATTERN (p) as argument to reg_set_p . */
4375 if (reg_set_p (reload_reg, PATTERN (p)))
4377 n = count_occurrences (PATTERN (p), reload_reg, 0);
4383 = gen_rtx_fmt_e (code, mode, reload_reg);
4385 validate_replace_rtx_group (reload_reg,
4387 n = verify_changes (0);
4389 /* We must also verify that the constraints
4390 are met after the replacement. Make sure
4391 extract_insn is only called for an insn
4392 where the replacements were found to be
4397 n = constrain_operands (1);
4400 /* If the constraints were not met, then
4401 undo the replacement, else confirm it. */
4405 confirm_change_group ();
4411 add_reg_note (p, REG_INC, reload_reg);
4412 /* Mark this as having an output reload so that the
4413 REG_INC processing code below won't invalidate
4414 the reload for inheritance. */
4415 SET_HARD_REG_BIT (reg_is_output_reload,
4416 REGNO (reload_reg));
4417 SET_REGNO_REG_SET (®_has_output_reload,
4418 REGNO (XEXP (in_reg, 0)));
4421 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4424 else if ((code == PRE_INC || code == PRE_DEC)
4425 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4426 REGNO (rld[i].reg_rtx))
4427 /* Make sure it is the inc/dec pseudo, and not
4428 some other (e.g. output operand) pseudo. */
4429 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4430 == REGNO (XEXP (in_reg, 0))))
4432 SET_HARD_REG_BIT (reg_is_output_reload,
4433 REGNO (rld[i].reg_rtx));
4434 SET_REGNO_REG_SET (®_has_output_reload,
4435 REGNO (XEXP (in_reg, 0)));
4437 else if (code == PRE_INC || code == PRE_DEC
4438 || code == POST_INC || code == POST_DEC)
4440 int in_regno = REGNO (XEXP (in_reg, 0));
4442 if (reg_last_reload_reg[in_regno] != NULL_RTX)
4445 bool forget_p = true;
4447 in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4448 if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4451 for (x = old_prev ? NEXT_INSN (old_prev) : insn;
4454 if (x == reg_reloaded_insn[in_hard_regno])
4460 /* If for some reasons, we didn't set up
4461 reg_last_reload_reg in this insn,
4462 invalidate inheritance from previous
4463 insns for the incremented/decremented
4464 register. Such registers will be not in
4465 reg_has_output_reload. Invalidate it
4466 also if the corresponding element in
4467 reg_reloaded_insn is also
4470 forget_old_reloads_1 (XEXP (in_reg, 0),
4476 /* If a pseudo that got a hard register is auto-incremented,
4477 we must purge records of copying it into pseudos without
4479 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4480 if (REG_NOTE_KIND (x) == REG_INC)
4482 /* See if this pseudo reg was reloaded in this insn.
4483 If so, its last-reload info is still valid
4484 because it is based on this insn's reload. */
4485 for (i = 0; i < n_reloads; i++)
4486 if (rld[i].out == XEXP (x, 0))
4490 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4494 /* A reload reg's contents are unknown after a label. */
4496 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4498 /* Don't assume a reload reg is still good after a call insn
4499 if it is a call-used reg, or if it contains a value that will
4500 be partially clobbered by the call. */
4501 else if (CALL_P (insn))
4503 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4504 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4509 free (reg_last_reload_reg);
4510 CLEAR_REG_SET (®_has_output_reload);
4513 /* Discard all record of any value reloaded from X,
4514 or reloaded in X from someplace else;
4515 unless X is an output reload reg of the current insn.
4517 X may be a hard reg (the reload reg)
4518 or it may be a pseudo reg that was reloaded from.
4520 When DATA is non-NULL just mark the registers in regset
4521 to be forgotten later. */
4524 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4529 regset regs = (regset) data;
4531 /* note_stores does give us subregs of hard regs,
4532 subreg_regno_offset requires a hard reg. */
4533 while (GET_CODE (x) == SUBREG)
4535 /* We ignore the subreg offset when calculating the regno,
4536 because we are using the entire underlying hard register
4546 if (regno >= FIRST_PSEUDO_REGISTER)
4552 nr = hard_regno_nregs[regno][GET_MODE (x)];
4553 /* Storing into a spilled-reg invalidates its contents.
4554 This can happen if a block-local pseudo is allocated to that reg
4555 and it wasn't spilled because this block's total need is 0.
4556 Then some insn might have an optional reload and use this reg. */
4558 for (i = 0; i < nr; i++)
4559 /* But don't do this if the reg actually serves as an output
4560 reload reg in the current instruction. */
4562 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4564 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4565 spill_reg_store[regno + i] = 0;
4571 SET_REGNO_REG_SET (regs, regno + nr);
4574 /* Since value of X has changed,
4575 forget any value previously copied from it. */
4578 /* But don't forget a copy if this is the output reload
4579 that establishes the copy's validity. */
4581 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4582 reg_last_reload_reg[regno + nr] = 0;
4586 /* Forget the reloads marked in regset by previous function. */
4588 forget_marked_reloads (regset regs)
4591 reg_set_iterator rsi;
4592 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4594 if (reg < FIRST_PSEUDO_REGISTER
4595 /* But don't do this if the reg actually serves as an output
4596 reload reg in the current instruction. */
4598 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4600 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4601 spill_reg_store[reg] = 0;
4604 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4605 reg_last_reload_reg[reg] = 0;
4609 /* The following HARD_REG_SETs indicate when each hard register is
4610 used for a reload of various parts of the current insn. */
4612 /* If reg is unavailable for all reloads. */
4613 static HARD_REG_SET reload_reg_unavailable;
4614 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4615 static HARD_REG_SET reload_reg_used;
4616 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4617 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4618 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4619 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4620 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4621 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4622 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4623 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4624 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4625 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4626 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4627 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4628 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4629 static HARD_REG_SET reload_reg_used_in_op_addr;
4630 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4631 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4632 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4633 static HARD_REG_SET reload_reg_used_in_insn;
4634 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4635 static HARD_REG_SET reload_reg_used_in_other_addr;
4637 /* If reg is in use as a reload reg for any sort of reload. */
4638 static HARD_REG_SET reload_reg_used_at_all;
4640 /* If reg is use as an inherited reload. We just mark the first register
4642 static HARD_REG_SET reload_reg_used_for_inherit;
4644 /* Records which hard regs are used in any way, either as explicit use or
4645 by being allocated to a pseudo during any point of the current insn. */
4646 static HARD_REG_SET reg_used_in_insn;
4648 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4649 TYPE. MODE is used to indicate how many consecutive regs are
4653 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4654 enum machine_mode mode)
4656 unsigned int nregs = hard_regno_nregs[regno][mode];
4659 for (i = regno; i < nregs + regno; i++)
4664 SET_HARD_REG_BIT (reload_reg_used, i);
4667 case RELOAD_FOR_INPUT_ADDRESS:
4668 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4671 case RELOAD_FOR_INPADDR_ADDRESS:
4672 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4675 case RELOAD_FOR_OUTPUT_ADDRESS:
4676 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4679 case RELOAD_FOR_OUTADDR_ADDRESS:
4680 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4683 case RELOAD_FOR_OPERAND_ADDRESS:
4684 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4687 case RELOAD_FOR_OPADDR_ADDR:
4688 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4691 case RELOAD_FOR_OTHER_ADDRESS:
4692 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4695 case RELOAD_FOR_INPUT:
4696 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4699 case RELOAD_FOR_OUTPUT:
4700 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4703 case RELOAD_FOR_INSN:
4704 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4708 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4712 /* Similarly, but show REGNO is no longer in use for a reload. */
4715 clear_reload_reg_in_use (unsigned int regno, int opnum,
4716 enum reload_type type, enum machine_mode mode)
4718 unsigned int nregs = hard_regno_nregs[regno][mode];
4719 unsigned int start_regno, end_regno, r;
4721 /* A complication is that for some reload types, inheritance might
4722 allow multiple reloads of the same types to share a reload register.
4723 We set check_opnum if we have to check only reloads with the same
4724 operand number, and check_any if we have to check all reloads. */
4725 int check_opnum = 0;
4727 HARD_REG_SET *used_in_set;
4732 used_in_set = &reload_reg_used;
4735 case RELOAD_FOR_INPUT_ADDRESS:
4736 used_in_set = &reload_reg_used_in_input_addr[opnum];
4739 case RELOAD_FOR_INPADDR_ADDRESS:
4741 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4744 case RELOAD_FOR_OUTPUT_ADDRESS:
4745 used_in_set = &reload_reg_used_in_output_addr[opnum];
4748 case RELOAD_FOR_OUTADDR_ADDRESS:
4750 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4753 case RELOAD_FOR_OPERAND_ADDRESS:
4754 used_in_set = &reload_reg_used_in_op_addr;
4757 case RELOAD_FOR_OPADDR_ADDR:
4759 used_in_set = &reload_reg_used_in_op_addr_reload;
4762 case RELOAD_FOR_OTHER_ADDRESS:
4763 used_in_set = &reload_reg_used_in_other_addr;
4767 case RELOAD_FOR_INPUT:
4768 used_in_set = &reload_reg_used_in_input[opnum];
4771 case RELOAD_FOR_OUTPUT:
4772 used_in_set = &reload_reg_used_in_output[opnum];
4775 case RELOAD_FOR_INSN:
4776 used_in_set = &reload_reg_used_in_insn;
4781 /* We resolve conflicts with remaining reloads of the same type by
4782 excluding the intervals of reload registers by them from the
4783 interval of freed reload registers. Since we only keep track of
4784 one set of interval bounds, we might have to exclude somewhat
4785 more than what would be necessary if we used a HARD_REG_SET here.
4786 But this should only happen very infrequently, so there should
4787 be no reason to worry about it. */
4789 start_regno = regno;
4790 end_regno = regno + nregs;
4791 if (check_opnum || check_any)
4793 for (i = n_reloads - 1; i >= 0; i--)
4795 if (rld[i].when_needed == type
4796 && (check_any || rld[i].opnum == opnum)
4799 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4800 unsigned int conflict_end
4801 = end_hard_regno (rld[i].mode, conflict_start);
4803 /* If there is an overlap with the first to-be-freed register,
4804 adjust the interval start. */
4805 if (conflict_start <= start_regno && conflict_end > start_regno)
4806 start_regno = conflict_end;
4807 /* Otherwise, if there is a conflict with one of the other
4808 to-be-freed registers, adjust the interval end. */
4809 if (conflict_start > start_regno && conflict_start < end_regno)
4810 end_regno = conflict_start;
4815 for (r = start_regno; r < end_regno; r++)
4816 CLEAR_HARD_REG_BIT (*used_in_set, r);
4819 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4820 specified by OPNUM and TYPE. */
4823 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4827 /* In use for a RELOAD_OTHER means it's not available for anything. */
4828 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4829 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4835 /* In use for anything means we can't use it for RELOAD_OTHER. */
4836 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4837 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4838 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4839 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4842 for (i = 0; i < reload_n_operands; i++)
4843 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4844 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4845 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4846 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4847 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4848 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4853 case RELOAD_FOR_INPUT:
4854 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4855 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4858 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4861 /* If it is used for some other input, can't use it. */
4862 for (i = 0; i < reload_n_operands; i++)
4863 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4866 /* If it is used in a later operand's address, can't use it. */
4867 for (i = opnum + 1; i < reload_n_operands; i++)
4868 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4869 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4874 case RELOAD_FOR_INPUT_ADDRESS:
4875 /* Can't use a register if it is used for an input address for this
4876 operand or used as an input in an earlier one. */
4877 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4878 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4881 for (i = 0; i < opnum; i++)
4882 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4887 case RELOAD_FOR_INPADDR_ADDRESS:
4888 /* Can't use a register if it is used for an input address
4889 for this operand or used as an input in an earlier
4891 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4894 for (i = 0; i < opnum; i++)
4895 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4900 case RELOAD_FOR_OUTPUT_ADDRESS:
4901 /* Can't use a register if it is used for an output address for this
4902 operand or used as an output in this or a later operand. Note
4903 that multiple output operands are emitted in reverse order, so
4904 the conflicting ones are those with lower indices. */
4905 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4908 for (i = 0; i <= opnum; i++)
4909 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4914 case RELOAD_FOR_OUTADDR_ADDRESS:
4915 /* Can't use a register if it is used for an output address
4916 for this operand or used as an output in this or a
4917 later operand. Note that multiple output operands are
4918 emitted in reverse order, so the conflicting ones are
4919 those with lower indices. */
4920 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4923 for (i = 0; i <= opnum; i++)
4924 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4929 case RELOAD_FOR_OPERAND_ADDRESS:
4930 for (i = 0; i < reload_n_operands; i++)
4931 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4934 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4935 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4937 case RELOAD_FOR_OPADDR_ADDR:
4938 for (i = 0; i < reload_n_operands; i++)
4939 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4942 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4944 case RELOAD_FOR_OUTPUT:
4945 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4946 outputs, or an operand address for this or an earlier output.
4947 Note that multiple output operands are emitted in reverse order,
4948 so the conflicting ones are those with higher indices. */
4949 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4952 for (i = 0; i < reload_n_operands; i++)
4953 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4956 for (i = opnum; i < reload_n_operands; i++)
4957 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4958 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4963 case RELOAD_FOR_INSN:
4964 for (i = 0; i < reload_n_operands; i++)
4965 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4966 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4969 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4970 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4972 case RELOAD_FOR_OTHER_ADDRESS:
4973 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4980 /* Return 1 if the value in reload reg REGNO, as used by a reload
4981 needed for the part of the insn specified by OPNUM and TYPE,
4982 is still available in REGNO at the end of the insn.
4984 We can assume that the reload reg was already tested for availability
4985 at the time it is needed, and we should not check this again,
4986 in case the reg has already been marked in use. */
4989 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4996 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4997 its value must reach the end. */
5000 /* If this use is for part of the insn,
5001 its value reaches if no subsequent part uses the same register.
5002 Just like the above function, don't try to do this with lots
5005 case RELOAD_FOR_OTHER_ADDRESS:
5006 /* Here we check for everything else, since these don't conflict
5007 with anything else and everything comes later. */
5009 for (i = 0; i < reload_n_operands; i++)
5010 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5011 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5012 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
5013 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5014 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5015 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5018 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5019 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5020 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5021 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5023 case RELOAD_FOR_INPUT_ADDRESS:
5024 case RELOAD_FOR_INPADDR_ADDRESS:
5025 /* Similar, except that we check only for this and subsequent inputs
5026 and the address of only subsequent inputs and we do not need
5027 to check for RELOAD_OTHER objects since they are known not to
5030 for (i = opnum; i < reload_n_operands; i++)
5031 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5034 for (i = opnum + 1; i < reload_n_operands; i++)
5035 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5036 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5039 for (i = 0; i < reload_n_operands; i++)
5040 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5041 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5042 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5045 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5048 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5049 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5050 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5052 case RELOAD_FOR_INPUT:
5053 /* Similar to input address, except we start at the next operand for
5054 both input and input address and we do not check for
5055 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5058 for (i = opnum + 1; i < reload_n_operands; i++)
5059 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5060 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5061 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5064 /* ... fall through ... */
5066 case RELOAD_FOR_OPERAND_ADDRESS:
5067 /* Check outputs and their addresses. */
5069 for (i = 0; i < reload_n_operands; i++)
5070 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5071 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5072 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5075 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5077 case RELOAD_FOR_OPADDR_ADDR:
5078 for (i = 0; i < reload_n_operands; i++)
5079 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5080 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5081 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5084 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5085 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5086 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5088 case RELOAD_FOR_INSN:
5089 /* These conflict with other outputs with RELOAD_OTHER. So
5090 we need only check for output addresses. */
5092 opnum = reload_n_operands;
5094 /* ... fall through ... */
5096 case RELOAD_FOR_OUTPUT:
5097 case RELOAD_FOR_OUTPUT_ADDRESS:
5098 case RELOAD_FOR_OUTADDR_ADDRESS:
5099 /* We already know these can't conflict with a later output. So the
5100 only thing to check are later output addresses.
5101 Note that multiple output operands are emitted in reverse order,
5102 so the conflicting ones are those with lower indices. */
5103 for (i = 0; i < opnum; i++)
5104 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5105 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5115 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5116 every register in the range [REGNO, REGNO + NREGS). */
5119 reload_regs_reach_end_p (unsigned int regno, int nregs,
5120 int opnum, enum reload_type type)
5124 for (i = 0; i < nregs; i++)
5125 if (!reload_reg_reaches_end_p (regno + i, opnum, type))
5131 /* Returns whether R1 and R2 are uniquely chained: the value of one
5132 is used by the other, and that value is not used by any other
5133 reload for this insn. This is used to partially undo the decision
5134 made in find_reloads when in the case of multiple
5135 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5136 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5137 reloads. This code tries to avoid the conflict created by that
5138 change. It might be cleaner to explicitly keep track of which
5139 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5140 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5141 this after the fact. */
5143 reloads_unique_chain_p (int r1, int r2)
5147 /* We only check input reloads. */
5148 if (! rld[r1].in || ! rld[r2].in)
5151 /* Avoid anything with output reloads. */
5152 if (rld[r1].out || rld[r2].out)
5155 /* "chained" means one reload is a component of the other reload,
5156 not the same as the other reload. */
5157 if (rld[r1].opnum != rld[r2].opnum
5158 || rtx_equal_p (rld[r1].in, rld[r2].in)
5159 || rld[r1].optional || rld[r2].optional
5160 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5161 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5164 for (i = 0; i < n_reloads; i ++)
5165 /* Look for input reloads that aren't our two */
5166 if (i != r1 && i != r2 && rld[i].in)
5168 /* If our reload is mentioned at all, it isn't a simple chain. */
5169 if (reg_mentioned_p (rld[r1].in, rld[i].in))
5175 /* The recursive function change all occurrences of WHAT in *WHERE
5178 substitute (rtx *where, const_rtx what, rtx repl)
5187 if (*where == what || rtx_equal_p (*where, what))
5189 /* Record the location of the changed rtx. */
5190 VEC_safe_push (rtx_p, heap, substitute_stack, where);
5195 code = GET_CODE (*where);
5196 fmt = GET_RTX_FORMAT (code);
5197 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5203 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5204 substitute (&XVECEXP (*where, i, j), what, repl);
5206 else if (fmt[i] == 'e')
5207 substitute (&XEXP (*where, i), what, repl);
5211 /* The function returns TRUE if chain of reload R1 and R2 (in any
5212 order) can be evaluated without usage of intermediate register for
5213 the reload containing another reload. It is important to see
5214 gen_reload to understand what the function is trying to do. As an
5215 example, let us have reload chain
5218 r1: <something> + const
5220 and reload R2 got reload reg HR. The function returns true if
5221 there is a correct insn HR = HR + <something>. Otherwise,
5222 gen_reload will use intermediate register (and this is the reload
5223 reg for R1) to reload <something>.
5225 We need this function to find a conflict for chain reloads. In our
5226 example, if HR = HR + <something> is incorrect insn, then we cannot
5227 use HR as a reload register for R2. If we do use it then we get a
5236 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5238 /* Assume other cases in gen_reload are not possible for
5239 chain reloads or do need an intermediate hard registers. */
5242 rtx out, in, tem, insn;
5243 rtx last = get_last_insn ();
5245 /* Make r2 a component of r1. */
5246 if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5252 gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5253 regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5254 gcc_assert (regno >= 0);
5255 out = gen_rtx_REG (rld[r1].mode, regno);
5257 substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5259 /* If IN is a paradoxical SUBREG, remove it and try to put the
5260 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5261 if (GET_CODE (in) == SUBREG
5262 && (GET_MODE_SIZE (GET_MODE (in))
5263 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
5264 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
5265 in = SUBREG_REG (in), out = tem;
5267 if (GET_CODE (in) == PLUS
5268 && (REG_P (XEXP (in, 0))
5269 || GET_CODE (XEXP (in, 0)) == SUBREG
5270 || MEM_P (XEXP (in, 0)))
5271 && (REG_P (XEXP (in, 1))
5272 || GET_CODE (XEXP (in, 1)) == SUBREG
5273 || CONSTANT_P (XEXP (in, 1))
5274 || MEM_P (XEXP (in, 1))))
5276 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
5277 code = recog_memoized (insn);
5282 extract_insn (insn);
5283 /* We want constrain operands to treat this insn strictly in
5284 its validity determination, i.e., the way it would after
5285 reload has completed. */
5286 result = constrain_operands (1);
5289 delete_insns_since (last);
5292 /* Restore the original value at each changed address within R1. */
5293 while (!VEC_empty (rtx_p, substitute_stack))
5295 rtx *where = VEC_pop (rtx_p, substitute_stack);
5296 *where = rld[r2].in;
5302 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5305 This function uses the same algorithm as reload_reg_free_p above. */
5308 reloads_conflict (int r1, int r2)
5310 enum reload_type r1_type = rld[r1].when_needed;
5311 enum reload_type r2_type = rld[r2].when_needed;
5312 int r1_opnum = rld[r1].opnum;
5313 int r2_opnum = rld[r2].opnum;
5315 /* RELOAD_OTHER conflicts with everything. */
5316 if (r2_type == RELOAD_OTHER)
5319 /* Otherwise, check conflicts differently for each type. */
5323 case RELOAD_FOR_INPUT:
5324 return (r2_type == RELOAD_FOR_INSN
5325 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5326 || r2_type == RELOAD_FOR_OPADDR_ADDR
5327 || r2_type == RELOAD_FOR_INPUT
5328 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5329 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5330 && r2_opnum > r1_opnum));
5332 case RELOAD_FOR_INPUT_ADDRESS:
5333 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5334 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5336 case RELOAD_FOR_INPADDR_ADDRESS:
5337 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5338 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5340 case RELOAD_FOR_OUTPUT_ADDRESS:
5341 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5342 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5344 case RELOAD_FOR_OUTADDR_ADDRESS:
5345 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5346 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5348 case RELOAD_FOR_OPERAND_ADDRESS:
5349 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5350 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5351 && (!reloads_unique_chain_p (r1, r2)
5352 || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5354 case RELOAD_FOR_OPADDR_ADDR:
5355 return (r2_type == RELOAD_FOR_INPUT
5356 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5358 case RELOAD_FOR_OUTPUT:
5359 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5360 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5361 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5362 && r2_opnum >= r1_opnum));
5364 case RELOAD_FOR_INSN:
5365 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5366 || r2_type == RELOAD_FOR_INSN
5367 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5369 case RELOAD_FOR_OTHER_ADDRESS:
5370 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5380 /* Indexed by reload number, 1 if incoming value
5381 inherited from previous insns. */
5382 static char reload_inherited[MAX_RELOADS];
5384 /* For an inherited reload, this is the insn the reload was inherited from,
5385 if we know it. Otherwise, this is 0. */
5386 static rtx reload_inheritance_insn[MAX_RELOADS];
5388 /* If nonzero, this is a place to get the value of the reload,
5389 rather than using reload_in. */
5390 static rtx reload_override_in[MAX_RELOADS];
5392 /* For each reload, the hard register number of the register used,
5393 or -1 if we did not need a register for this reload. */
5394 static int reload_spill_index[MAX_RELOADS];
5396 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5397 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5399 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5400 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5402 /* Subroutine of free_for_value_p, used to check a single register.
5403 START_REGNO is the starting regno of the full reload register
5404 (possibly comprising multiple hard registers) that we are considering. */
5407 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5408 enum reload_type type, rtx value, rtx out,
5409 int reloadnum, int ignore_address_reloads)
5412 /* Set if we see an input reload that must not share its reload register
5413 with any new earlyclobber, but might otherwise share the reload
5414 register with an output or input-output reload. */
5415 int check_earlyclobber = 0;
5419 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5422 if (out == const0_rtx)
5428 /* We use some pseudo 'time' value to check if the lifetimes of the
5429 new register use would overlap with the one of a previous reload
5430 that is not read-only or uses a different value.
5431 The 'time' used doesn't have to be linear in any shape or form, just
5433 Some reload types use different 'buckets' for each operand.
5434 So there are MAX_RECOG_OPERANDS different time values for each
5436 We compute TIME1 as the time when the register for the prospective
5437 new reload ceases to be live, and TIME2 for each existing
5438 reload as the time when that the reload register of that reload
5440 Where there is little to be gained by exact lifetime calculations,
5441 we just make conservative assumptions, i.e. a longer lifetime;
5442 this is done in the 'default:' cases. */
5445 case RELOAD_FOR_OTHER_ADDRESS:
5446 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5447 time1 = copy ? 0 : 1;
5450 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5452 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5453 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5454 respectively, to the time values for these, we get distinct time
5455 values. To get distinct time values for each operand, we have to
5456 multiply opnum by at least three. We round that up to four because
5457 multiply by four is often cheaper. */
5458 case RELOAD_FOR_INPADDR_ADDRESS:
5459 time1 = opnum * 4 + 2;
5461 case RELOAD_FOR_INPUT_ADDRESS:
5462 time1 = opnum * 4 + 3;
5464 case RELOAD_FOR_INPUT:
5465 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5466 executes (inclusive). */
5467 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5469 case RELOAD_FOR_OPADDR_ADDR:
5471 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5472 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5474 case RELOAD_FOR_OPERAND_ADDRESS:
5475 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5477 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5479 case RELOAD_FOR_OUTADDR_ADDRESS:
5480 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5482 case RELOAD_FOR_OUTPUT_ADDRESS:
5483 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5486 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5489 for (i = 0; i < n_reloads; i++)
5491 rtx reg = rld[i].reg_rtx;
5492 if (reg && REG_P (reg)
5493 && ((unsigned) regno - true_regnum (reg)
5494 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5497 rtx other_input = rld[i].in;
5499 /* If the other reload loads the same input value, that
5500 will not cause a conflict only if it's loading it into
5501 the same register. */
5502 if (true_regnum (reg) != start_regno)
5503 other_input = NULL_RTX;
5504 if (! other_input || ! rtx_equal_p (other_input, value)
5505 || rld[i].out || out)
5508 switch (rld[i].when_needed)
5510 case RELOAD_FOR_OTHER_ADDRESS:
5513 case RELOAD_FOR_INPADDR_ADDRESS:
5514 /* find_reloads makes sure that a
5515 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5516 by at most one - the first -
5517 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5518 address reload is inherited, the address address reload
5519 goes away, so we can ignore this conflict. */
5520 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5521 && ignore_address_reloads
5522 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5523 Then the address address is still needed to store
5524 back the new address. */
5525 && ! rld[reloadnum].out)
5527 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5528 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5530 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5531 && ignore_address_reloads
5532 /* Unless we are reloading an auto_inc expression. */
5533 && ! rld[reloadnum].out)
5535 time2 = rld[i].opnum * 4 + 2;
5537 case RELOAD_FOR_INPUT_ADDRESS:
5538 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5539 && ignore_address_reloads
5540 && ! rld[reloadnum].out)
5542 time2 = rld[i].opnum * 4 + 3;
5544 case RELOAD_FOR_INPUT:
5545 time2 = rld[i].opnum * 4 + 4;
5546 check_earlyclobber = 1;
5548 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5549 == MAX_RECOG_OPERAND * 4 */
5550 case RELOAD_FOR_OPADDR_ADDR:
5551 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5552 && ignore_address_reloads
5553 && ! rld[reloadnum].out)
5555 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5557 case RELOAD_FOR_OPERAND_ADDRESS:
5558 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5559 check_earlyclobber = 1;
5561 case RELOAD_FOR_INSN:
5562 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5564 case RELOAD_FOR_OUTPUT:
5565 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5566 instruction is executed. */
5567 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5569 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5570 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5572 case RELOAD_FOR_OUTADDR_ADDRESS:
5573 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5574 && ignore_address_reloads
5575 && ! rld[reloadnum].out)
5577 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5579 case RELOAD_FOR_OUTPUT_ADDRESS:
5580 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5583 /* If there is no conflict in the input part, handle this
5584 like an output reload. */
5585 if (! rld[i].in || rtx_equal_p (other_input, value))
5587 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5588 /* Earlyclobbered outputs must conflict with inputs. */
5589 if (earlyclobber_operand_p (rld[i].out))
5590 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5595 /* RELOAD_OTHER might be live beyond instruction execution,
5596 but this is not obvious when we set time2 = 1. So check
5597 here if there might be a problem with the new reload
5598 clobbering the register used by the RELOAD_OTHER. */
5606 && (! rld[i].in || rld[i].out
5607 || ! rtx_equal_p (other_input, value)))
5608 || (out && rld[reloadnum].out_reg
5609 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5615 /* Earlyclobbered outputs must conflict with inputs. */
5616 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5622 /* Return 1 if the value in reload reg REGNO, as used by a reload
5623 needed for the part of the insn specified by OPNUM and TYPE,
5624 may be used to load VALUE into it.
5626 MODE is the mode in which the register is used, this is needed to
5627 determine how many hard regs to test.
5629 Other read-only reloads with the same value do not conflict
5630 unless OUT is nonzero and these other reloads have to live while
5631 output reloads live.
5632 If OUT is CONST0_RTX, this is a special case: it means that the
5633 test should not be for using register REGNO as reload register, but
5634 for copying from register REGNO into the reload register.
5636 RELOADNUM is the number of the reload we want to load this value for;
5637 a reload does not conflict with itself.
5639 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5640 reloads that load an address for the very reload we are considering.
5642 The caller has to make sure that there is no conflict with the return
5646 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5647 enum reload_type type, rtx value, rtx out, int reloadnum,
5648 int ignore_address_reloads)
5650 int nregs = hard_regno_nregs[regno][mode];
5652 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5653 value, out, reloadnum,
5654 ignore_address_reloads))
5659 /* Return nonzero if the rtx X is invariant over the current function. */
5660 /* ??? Actually, the places where we use this expect exactly what is
5661 tested here, and not everything that is function invariant. In
5662 particular, the frame pointer and arg pointer are special cased;
5663 pic_offset_table_rtx is not, and we must not spill these things to
5667 function_invariant_p (const_rtx x)
5671 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5673 if (GET_CODE (x) == PLUS
5674 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5675 && CONSTANT_P (XEXP (x, 1)))
5680 /* Determine whether the reload reg X overlaps any rtx'es used for
5681 overriding inheritance. Return nonzero if so. */
5684 conflicts_with_override (rtx x)
5687 for (i = 0; i < n_reloads; i++)
5688 if (reload_override_in[i]
5689 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5694 /* Give an error message saying we failed to find a reload for INSN,
5695 and clear out reload R. */
5697 failed_reload (rtx insn, int r)
5699 if (asm_noperands (PATTERN (insn)) < 0)
5700 /* It's the compiler's fault. */
5701 fatal_insn ("could not find a spill register", insn);
5703 /* It's the user's fault; the operand's mode and constraint
5704 don't match. Disable this reload so we don't crash in final. */
5705 error_for_asm (insn,
5706 "%<asm%> operand constraint incompatible with operand size");
5710 rld[r].optional = 1;
5711 rld[r].secondary_p = 1;
5714 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5715 for reload R. If it's valid, get an rtx for it. Return nonzero if
5718 set_reload_reg (int i, int r)
5721 rtx reg = spill_reg_rtx[i];
5723 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5724 spill_reg_rtx[i] = reg
5725 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5727 regno = true_regnum (reg);
5729 /* Detect when the reload reg can't hold the reload mode.
5730 This used to be one `if', but Sequent compiler can't handle that. */
5731 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5733 enum machine_mode test_mode = VOIDmode;
5735 test_mode = GET_MODE (rld[r].in);
5736 /* If rld[r].in has VOIDmode, it means we will load it
5737 in whatever mode the reload reg has: to wit, rld[r].mode.
5738 We have already tested that for validity. */
5739 /* Aside from that, we need to test that the expressions
5740 to reload from or into have modes which are valid for this
5741 reload register. Otherwise the reload insns would be invalid. */
5742 if (! (rld[r].in != 0 && test_mode != VOIDmode
5743 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5744 if (! (rld[r].out != 0
5745 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5747 /* The reg is OK. */
5750 /* Mark as in use for this insn the reload regs we use
5752 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5753 rld[r].when_needed, rld[r].mode);
5755 rld[r].reg_rtx = reg;
5756 reload_spill_index[r] = spill_regs[i];
5763 /* Find a spill register to use as a reload register for reload R.
5764 LAST_RELOAD is nonzero if this is the last reload for the insn being
5767 Set rld[R].reg_rtx to the register allocated.
5769 We return 1 if successful, or 0 if we couldn't find a spill reg and
5770 we didn't change anything. */
5773 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5778 /* If we put this reload ahead, thinking it is a group,
5779 then insist on finding a group. Otherwise we can grab a
5780 reg that some other reload needs.
5781 (That can happen when we have a 68000 DATA_OR_FP_REG
5782 which is a group of data regs or one fp reg.)
5783 We need not be so restrictive if there are no more reloads
5786 ??? Really it would be nicer to have smarter handling
5787 for that kind of reg class, where a problem like this is normal.
5788 Perhaps those classes should be avoided for reloading
5789 by use of more alternatives. */
5791 int force_group = rld[r].nregs > 1 && ! last_reload;
5793 /* If we want a single register and haven't yet found one,
5794 take any reg in the right class and not in use.
5795 If we want a consecutive group, here is where we look for it.
5797 We use two passes so we can first look for reload regs to
5798 reuse, which are already in use for other reloads in this insn,
5799 and only then use additional registers.
5800 I think that maximizing reuse is needed to make sure we don't
5801 run out of reload regs. Suppose we have three reloads, and
5802 reloads A and B can share regs. These need two regs.
5803 Suppose A and B are given different regs.
5804 That leaves none for C. */
5805 for (pass = 0; pass < 2; pass++)
5807 /* I is the index in spill_regs.
5808 We advance it round-robin between insns to use all spill regs
5809 equally, so that inherited reloads have a chance
5810 of leapfrogging each other. */
5814 for (count = 0; count < n_spills; count++)
5816 int rclass = (int) rld[r].rclass;
5822 regnum = spill_regs[i];
5824 if ((reload_reg_free_p (regnum, rld[r].opnum,
5827 /* We check reload_reg_used to make sure we
5828 don't clobber the return register. */
5829 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5830 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5831 rld[r].when_needed, rld[r].in,
5833 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
5834 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5835 /* Look first for regs to share, then for unshared. But
5836 don't share regs used for inherited reloads; they are
5837 the ones we want to preserve. */
5839 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5841 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5844 int nr = hard_regno_nregs[regnum][rld[r].mode];
5845 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5846 (on 68000) got us two FP regs. If NR is 1,
5847 we would reject both of them. */
5850 /* If we need only one reg, we have already won. */
5853 /* But reject a single reg if we demand a group. */
5858 /* Otherwise check that as many consecutive regs as we need
5859 are available here. */
5862 int regno = regnum + nr - 1;
5863 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
5864 && spill_reg_order[regno] >= 0
5865 && reload_reg_free_p (regno, rld[r].opnum,
5866 rld[r].when_needed)))
5875 /* If we found something on pass 1, omit pass 2. */
5876 if (count < n_spills)
5880 /* We should have found a spill register by now. */
5881 if (count >= n_spills)
5884 /* I is the index in SPILL_REG_RTX of the reload register we are to
5885 allocate. Get an rtx for it and find its register number. */
5887 return set_reload_reg (i, r);
5890 /* Initialize all the tables needed to allocate reload registers.
5891 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5892 is the array we use to restore the reg_rtx field for every reload. */
5895 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5899 for (i = 0; i < n_reloads; i++)
5900 rld[i].reg_rtx = save_reload_reg_rtx[i];
5902 memset (reload_inherited, 0, MAX_RELOADS);
5903 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5904 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5906 CLEAR_HARD_REG_SET (reload_reg_used);
5907 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5908 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5909 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5910 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5911 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5913 CLEAR_HARD_REG_SET (reg_used_in_insn);
5916 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5917 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5918 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5919 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5920 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5921 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5924 for (i = 0; i < reload_n_operands; i++)
5926 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5927 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5928 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5929 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5930 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5931 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5934 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5936 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5938 for (i = 0; i < n_reloads; i++)
5939 /* If we have already decided to use a certain register,
5940 don't use it in another way. */
5942 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5943 rld[i].when_needed, rld[i].mode);
5946 /* Assign hard reg targets for the pseudo-registers we must reload
5947 into hard regs for this insn.
5948 Also output the instructions to copy them in and out of the hard regs.
5950 For machines with register classes, we are responsible for
5951 finding a reload reg in the proper class. */
5954 choose_reload_regs (struct insn_chain *chain)
5956 rtx insn = chain->insn;
5958 unsigned int max_group_size = 1;
5959 enum reg_class group_class = NO_REGS;
5960 int pass, win, inheritance;
5962 rtx save_reload_reg_rtx[MAX_RELOADS];
5964 /* In order to be certain of getting the registers we need,
5965 we must sort the reloads into order of increasing register class.
5966 Then our grabbing of reload registers will parallel the process
5967 that provided the reload registers.
5969 Also note whether any of the reloads wants a consecutive group of regs.
5970 If so, record the maximum size of the group desired and what
5971 register class contains all the groups needed by this insn. */
5973 for (j = 0; j < n_reloads; j++)
5975 reload_order[j] = j;
5976 if (rld[j].reg_rtx != NULL_RTX)
5978 gcc_assert (REG_P (rld[j].reg_rtx)
5979 && HARD_REGISTER_P (rld[j].reg_rtx));
5980 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
5983 reload_spill_index[j] = -1;
5985 if (rld[j].nregs > 1)
5987 max_group_size = MAX (rld[j].nregs, max_group_size);
5989 = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
5992 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5996 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5998 /* If -O, try first with inheritance, then turning it off.
5999 If not -O, don't do inheritance.
6000 Using inheritance when not optimizing leads to paradoxes
6001 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6002 because one side of the comparison might be inherited. */
6004 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
6006 choose_reload_regs_init (chain, save_reload_reg_rtx);
6008 /* Process the reloads in order of preference just found.
6009 Beyond this point, subregs can be found in reload_reg_rtx.
6011 This used to look for an existing reloaded home for all of the
6012 reloads, and only then perform any new reloads. But that could lose
6013 if the reloads were done out of reg-class order because a later
6014 reload with a looser constraint might have an old home in a register
6015 needed by an earlier reload with a tighter constraint.
6017 To solve this, we make two passes over the reloads, in the order
6018 described above. In the first pass we try to inherit a reload
6019 from a previous insn. If there is a later reload that needs a
6020 class that is a proper subset of the class being processed, we must
6021 also allocate a spill register during the first pass.
6023 Then make a second pass over the reloads to allocate any reloads
6024 that haven't been given registers yet. */
6026 for (j = 0; j < n_reloads; j++)
6028 int r = reload_order[j];
6029 rtx search_equiv = NULL_RTX;
6031 /* Ignore reloads that got marked inoperative. */
6032 if (rld[r].out == 0 && rld[r].in == 0
6033 && ! rld[r].secondary_p)
6036 /* If find_reloads chose to use reload_in or reload_out as a reload
6037 register, we don't need to chose one. Otherwise, try even if it
6038 found one since we might save an insn if we find the value lying
6040 Try also when reload_in is a pseudo without a hard reg. */
6041 if (rld[r].in != 0 && rld[r].reg_rtx != 0
6042 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
6043 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
6044 && !MEM_P (rld[r].in)
6045 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
6048 #if 0 /* No longer needed for correct operation.
6049 It might give better code, or might not; worth an experiment? */
6050 /* If this is an optional reload, we can't inherit from earlier insns
6051 until we are sure that any non-optional reloads have been allocated.
6052 The following code takes advantage of the fact that optional reloads
6053 are at the end of reload_order. */
6054 if (rld[r].optional != 0)
6055 for (i = 0; i < j; i++)
6056 if ((rld[reload_order[i]].out != 0
6057 || rld[reload_order[i]].in != 0
6058 || rld[reload_order[i]].secondary_p)
6059 && ! rld[reload_order[i]].optional
6060 && rld[reload_order[i]].reg_rtx == 0)
6061 allocate_reload_reg (chain, reload_order[i], 0);
6064 /* First see if this pseudo is already available as reloaded
6065 for a previous insn. We cannot try to inherit for reloads
6066 that are smaller than the maximum number of registers needed
6067 for groups unless the register we would allocate cannot be used
6070 We could check here to see if this is a secondary reload for
6071 an object that is already in a register of the desired class.
6072 This would avoid the need for the secondary reload register.
6073 But this is complex because we can't easily determine what
6074 objects might want to be loaded via this reload. So let a
6075 register be allocated here. In `emit_reload_insns' we suppress
6076 one of the loads in the case described above. */
6082 enum machine_mode mode = VOIDmode;
6086 else if (REG_P (rld[r].in))
6088 regno = REGNO (rld[r].in);
6089 mode = GET_MODE (rld[r].in);
6091 else if (REG_P (rld[r].in_reg))
6093 regno = REGNO (rld[r].in_reg);
6094 mode = GET_MODE (rld[r].in_reg);
6096 else if (GET_CODE (rld[r].in_reg) == SUBREG
6097 && REG_P (SUBREG_REG (rld[r].in_reg)))
6099 regno = REGNO (SUBREG_REG (rld[r].in_reg));
6100 if (regno < FIRST_PSEUDO_REGISTER)
6101 regno = subreg_regno (rld[r].in_reg);
6103 byte = SUBREG_BYTE (rld[r].in_reg);
6104 mode = GET_MODE (rld[r].in_reg);
6107 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6108 && REG_P (XEXP (rld[r].in_reg, 0)))
6110 regno = REGNO (XEXP (rld[r].in_reg, 0));
6111 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6112 rld[r].out = rld[r].in;
6116 /* This won't work, since REGNO can be a pseudo reg number.
6117 Also, it takes much more hair to keep track of all the things
6118 that can invalidate an inherited reload of part of a pseudoreg. */
6119 else if (GET_CODE (rld[r].in) == SUBREG
6120 && REG_P (SUBREG_REG (rld[r].in)))
6121 regno = subreg_regno (rld[r].in);
6125 && reg_last_reload_reg[regno] != 0
6126 #ifdef CANNOT_CHANGE_MODE_CLASS
6127 /* Verify that the register it's in can be used in
6129 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
6130 GET_MODE (reg_last_reload_reg[regno]),
6135 enum reg_class rclass = rld[r].rclass, last_class;
6136 rtx last_reg = reg_last_reload_reg[regno];
6137 enum machine_mode need_mode;
6139 i = REGNO (last_reg);
6140 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6141 last_class = REGNO_REG_CLASS (i);
6147 = smallest_mode_for_size
6148 (GET_MODE_BITSIZE (mode) + byte * BITS_PER_UNIT,
6149 GET_MODE_CLASS (mode) == MODE_PARTIAL_INT
6150 ? MODE_INT : GET_MODE_CLASS (mode));
6152 if ((GET_MODE_SIZE (GET_MODE (last_reg))
6153 >= GET_MODE_SIZE (need_mode))
6154 && reg_reloaded_contents[i] == regno
6155 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6156 && HARD_REGNO_MODE_OK (i, rld[r].mode)
6157 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6158 /* Even if we can't use this register as a reload
6159 register, we might use it for reload_override_in,
6160 if copying it to the desired class is cheap
6162 || ((REGISTER_MOVE_COST (mode, last_class, rclass)
6163 < MEMORY_MOVE_COST (mode, rclass, 1))
6164 && (secondary_reload_class (1, rclass, mode,
6167 #ifdef SECONDARY_MEMORY_NEEDED
6168 && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
6173 && (rld[r].nregs == max_group_size
6174 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6176 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6177 rld[r].when_needed, rld[r].in,
6180 /* If a group is needed, verify that all the subsequent
6181 registers still have their values intact. */
6182 int nr = hard_regno_nregs[i][rld[r].mode];
6185 for (k = 1; k < nr; k++)
6186 if (reg_reloaded_contents[i + k] != regno
6187 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6195 last_reg = (GET_MODE (last_reg) == mode
6196 ? last_reg : gen_rtx_REG (mode, i));
6199 for (k = 0; k < nr; k++)
6200 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6203 /* We found a register that contains the
6204 value we need. If this register is the
6205 same as an `earlyclobber' operand of the
6206 current insn, just mark it as a place to
6207 reload from since we can't use it as the
6208 reload register itself. */
6210 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6211 if (reg_overlap_mentioned_for_reload_p
6212 (reg_last_reload_reg[regno],
6213 reload_earlyclobbers[i1]))
6216 if (i1 != n_earlyclobbers
6217 || ! (free_for_value_p (i, rld[r].mode,
6219 rld[r].when_needed, rld[r].in,
6221 /* Don't use it if we'd clobber a pseudo reg. */
6222 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6224 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6225 /* Don't clobber the frame pointer. */
6226 || (i == HARD_FRAME_POINTER_REGNUM
6227 && frame_pointer_needed
6229 /* Don't really use the inherited spill reg
6230 if we need it wider than we've got it. */
6231 || (GET_MODE_SIZE (rld[r].mode)
6232 > GET_MODE_SIZE (mode))
6235 /* If find_reloads chose reload_out as reload
6236 register, stay with it - that leaves the
6237 inherited register for subsequent reloads. */
6238 || (rld[r].out && rld[r].reg_rtx
6239 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6241 if (! rld[r].optional)
6243 reload_override_in[r] = last_reg;
6244 reload_inheritance_insn[r]
6245 = reg_reloaded_insn[i];
6251 /* We can use this as a reload reg. */
6252 /* Mark the register as in use for this part of
6254 mark_reload_reg_in_use (i,
6258 rld[r].reg_rtx = last_reg;
6259 reload_inherited[r] = 1;
6260 reload_inheritance_insn[r]
6261 = reg_reloaded_insn[i];
6262 reload_spill_index[r] = i;
6263 for (k = 0; k < nr; k++)
6264 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6272 /* Here's another way to see if the value is already lying around. */
6275 && ! reload_inherited[r]
6277 && (CONSTANT_P (rld[r].in)
6278 || GET_CODE (rld[r].in) == PLUS
6279 || REG_P (rld[r].in)
6280 || MEM_P (rld[r].in))
6281 && (rld[r].nregs == max_group_size
6282 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6283 search_equiv = rld[r].in;
6284 /* If this is an output reload from a simple move insn, look
6285 if an equivalence for the input is available. */
6286 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
6288 rtx set = single_set (insn);
6291 && rtx_equal_p (rld[r].out, SET_DEST (set))
6292 && CONSTANT_P (SET_SRC (set)))
6293 search_equiv = SET_SRC (set);
6299 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6300 -1, NULL, 0, rld[r].mode);
6306 regno = REGNO (equiv);
6309 /* This must be a SUBREG of a hard register.
6310 Make a new REG since this might be used in an
6311 address and not all machines support SUBREGs
6313 gcc_assert (GET_CODE (equiv) == SUBREG);
6314 regno = subreg_regno (equiv);
6315 equiv = gen_rtx_REG (rld[r].mode, regno);
6316 /* If we choose EQUIV as the reload register, but the
6317 loop below decides to cancel the inheritance, we'll
6318 end up reloading EQUIV in rld[r].mode, not the mode
6319 it had originally. That isn't safe when EQUIV isn't
6320 available as a spill register since its value might
6321 still be live at this point. */
6322 for (i = regno; i < regno + (int) rld[r].nregs; i++)
6323 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6328 /* If we found a spill reg, reject it unless it is free
6329 and of the desired class. */
6333 int bad_for_class = 0;
6334 int max_regno = regno + rld[r].nregs;
6336 for (i = regno; i < max_regno; i++)
6338 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6340 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6345 && ! free_for_value_p (regno, rld[r].mode,
6346 rld[r].opnum, rld[r].when_needed,
6347 rld[r].in, rld[r].out, r, 1))
6352 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6355 /* We found a register that contains the value we need.
6356 If this register is the same as an `earlyclobber' operand
6357 of the current insn, just mark it as a place to reload from
6358 since we can't use it as the reload register itself. */
6361 for (i = 0; i < n_earlyclobbers; i++)
6362 if (reg_overlap_mentioned_for_reload_p (equiv,
6363 reload_earlyclobbers[i]))
6365 if (! rld[r].optional)
6366 reload_override_in[r] = equiv;
6371 /* If the equiv register we have found is explicitly clobbered
6372 in the current insn, it depends on the reload type if we
6373 can use it, use it for reload_override_in, or not at all.
6374 In particular, we then can't use EQUIV for a
6375 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6379 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6380 switch (rld[r].when_needed)
6382 case RELOAD_FOR_OTHER_ADDRESS:
6383 case RELOAD_FOR_INPADDR_ADDRESS:
6384 case RELOAD_FOR_INPUT_ADDRESS:
6385 case RELOAD_FOR_OPADDR_ADDR:
6388 case RELOAD_FOR_INPUT:
6389 case RELOAD_FOR_OPERAND_ADDRESS:
6390 if (! rld[r].optional)
6391 reload_override_in[r] = equiv;
6397 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6398 switch (rld[r].when_needed)
6400 case RELOAD_FOR_OTHER_ADDRESS:
6401 case RELOAD_FOR_INPADDR_ADDRESS:
6402 case RELOAD_FOR_INPUT_ADDRESS:
6403 case RELOAD_FOR_OPADDR_ADDR:
6404 case RELOAD_FOR_OPERAND_ADDRESS:
6405 case RELOAD_FOR_INPUT:
6408 if (! rld[r].optional)
6409 reload_override_in[r] = equiv;
6417 /* If we found an equivalent reg, say no code need be generated
6418 to load it, and use it as our reload reg. */
6420 && (regno != HARD_FRAME_POINTER_REGNUM
6421 || !frame_pointer_needed))
6423 int nr = hard_regno_nregs[regno][rld[r].mode];
6425 rld[r].reg_rtx = equiv;
6426 reload_spill_index[r] = regno;
6427 reload_inherited[r] = 1;
6429 /* If reg_reloaded_valid is not set for this register,
6430 there might be a stale spill_reg_store lying around.
6431 We must clear it, since otherwise emit_reload_insns
6432 might delete the store. */
6433 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6434 spill_reg_store[regno] = NULL_RTX;
6435 /* If any of the hard registers in EQUIV are spill
6436 registers, mark them as in use for this insn. */
6437 for (k = 0; k < nr; k++)
6439 i = spill_reg_order[regno + k];
6442 mark_reload_reg_in_use (regno, rld[r].opnum,
6445 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6452 /* If we found a register to use already, or if this is an optional
6453 reload, we are done. */
6454 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6458 /* No longer needed for correct operation. Might or might
6459 not give better code on the average. Want to experiment? */
6461 /* See if there is a later reload that has a class different from our
6462 class that intersects our class or that requires less register
6463 than our reload. If so, we must allocate a register to this
6464 reload now, since that reload might inherit a previous reload
6465 and take the only available register in our class. Don't do this
6466 for optional reloads since they will force all previous reloads
6467 to be allocated. Also don't do this for reloads that have been
6470 for (i = j + 1; i < n_reloads; i++)
6472 int s = reload_order[i];
6474 if ((rld[s].in == 0 && rld[s].out == 0
6475 && ! rld[s].secondary_p)
6479 if ((rld[s].rclass != rld[r].rclass
6480 && reg_classes_intersect_p (rld[r].rclass,
6482 || rld[s].nregs < rld[r].nregs)
6489 allocate_reload_reg (chain, r, j == n_reloads - 1);
6493 /* Now allocate reload registers for anything non-optional that
6494 didn't get one yet. */
6495 for (j = 0; j < n_reloads; j++)
6497 int r = reload_order[j];
6499 /* Ignore reloads that got marked inoperative. */
6500 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6503 /* Skip reloads that already have a register allocated or are
6505 if (rld[r].reg_rtx != 0 || rld[r].optional)
6508 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6512 /* If that loop got all the way, we have won. */
6519 /* Loop around and try without any inheritance. */
6524 /* First undo everything done by the failed attempt
6525 to allocate with inheritance. */
6526 choose_reload_regs_init (chain, save_reload_reg_rtx);
6528 /* Some sanity tests to verify that the reloads found in the first
6529 pass are identical to the ones we have now. */
6530 gcc_assert (chain->n_reloads == n_reloads);
6532 for (i = 0; i < n_reloads; i++)
6534 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6536 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6537 for (j = 0; j < n_spills; j++)
6538 if (spill_regs[j] == chain->rld[i].regno)
6539 if (! set_reload_reg (j, i))
6540 failed_reload (chain->insn, i);
6544 /* If we thought we could inherit a reload, because it seemed that
6545 nothing else wanted the same reload register earlier in the insn,
6546 verify that assumption, now that all reloads have been assigned.
6547 Likewise for reloads where reload_override_in has been set. */
6549 /* If doing expensive optimizations, do one preliminary pass that doesn't
6550 cancel any inheritance, but removes reloads that have been needed only
6551 for reloads that we know can be inherited. */
6552 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6554 for (j = 0; j < n_reloads; j++)
6556 int r = reload_order[j];
6558 if (reload_inherited[r] && rld[r].reg_rtx)
6559 check_reg = rld[r].reg_rtx;
6560 else if (reload_override_in[r]
6561 && (REG_P (reload_override_in[r])
6562 || GET_CODE (reload_override_in[r]) == SUBREG))
6563 check_reg = reload_override_in[r];
6566 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6567 rld[r].opnum, rld[r].when_needed, rld[r].in,
6568 (reload_inherited[r]
6569 ? rld[r].out : const0_rtx),
6574 reload_inherited[r] = 0;
6575 reload_override_in[r] = 0;
6577 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6578 reload_override_in, then we do not need its related
6579 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6580 likewise for other reload types.
6581 We handle this by removing a reload when its only replacement
6582 is mentioned in reload_in of the reload we are going to inherit.
6583 A special case are auto_inc expressions; even if the input is
6584 inherited, we still need the address for the output. We can
6585 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6586 If we succeeded removing some reload and we are doing a preliminary
6587 pass just to remove such reloads, make another pass, since the
6588 removal of one reload might allow us to inherit another one. */
6590 && rld[r].out != rld[r].in
6591 && remove_address_replacements (rld[r].in) && pass)
6596 /* Now that reload_override_in is known valid,
6597 actually override reload_in. */
6598 for (j = 0; j < n_reloads; j++)
6599 if (reload_override_in[j])
6600 rld[j].in = reload_override_in[j];
6602 /* If this reload won't be done because it has been canceled or is
6603 optional and not inherited, clear reload_reg_rtx so other
6604 routines (such as subst_reloads) don't get confused. */
6605 for (j = 0; j < n_reloads; j++)
6606 if (rld[j].reg_rtx != 0
6607 && ((rld[j].optional && ! reload_inherited[j])
6608 || (rld[j].in == 0 && rld[j].out == 0
6609 && ! rld[j].secondary_p)))
6611 int regno = true_regnum (rld[j].reg_rtx);
6613 if (spill_reg_order[regno] >= 0)
6614 clear_reload_reg_in_use (regno, rld[j].opnum,
6615 rld[j].when_needed, rld[j].mode);
6617 reload_spill_index[j] = -1;
6620 /* Record which pseudos and which spill regs have output reloads. */
6621 for (j = 0; j < n_reloads; j++)
6623 int r = reload_order[j];
6625 i = reload_spill_index[r];
6627 /* I is nonneg if this reload uses a register.
6628 If rld[r].reg_rtx is 0, this is an optional reload
6629 that we opted to ignore. */
6630 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6631 && rld[r].reg_rtx != 0)
6633 int nregno = REGNO (rld[r].out_reg);
6636 if (nregno < FIRST_PSEUDO_REGISTER)
6637 nr = hard_regno_nregs[nregno][rld[r].mode];
6640 SET_REGNO_REG_SET (®_has_output_reload,
6645 nr = hard_regno_nregs[i][rld[r].mode];
6647 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6650 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6651 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6652 || rld[r].when_needed == RELOAD_FOR_INSN);
6657 /* Deallocate the reload register for reload R. This is called from
6658 remove_address_replacements. */
6661 deallocate_reload_reg (int r)
6665 if (! rld[r].reg_rtx)
6667 regno = true_regnum (rld[r].reg_rtx);
6669 if (spill_reg_order[regno] >= 0)
6670 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6672 reload_spill_index[r] = -1;
6675 /* If the small_register_classes_for_mode_p target hook returns true for
6676 some machine modes, we may not have merged two reloads of the same item
6677 for fear that we might not have enough reload registers. However,
6678 normally they will get the same reload register and hence actually need
6679 not be loaded twice.
6681 Here we check for the most common case of this phenomenon: when we have
6682 a number of reloads for the same object, each of which were allocated
6683 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6684 reload, and is not modified in the insn itself. If we find such,
6685 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6686 This will not increase the number of spill registers needed and will
6687 prevent redundant code. */
6690 merge_assigned_reloads (rtx insn)
6694 /* Scan all the reloads looking for ones that only load values and
6695 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6696 assigned and not modified by INSN. */
6698 for (i = 0; i < n_reloads; i++)
6700 int conflicting_input = 0;
6701 int max_input_address_opnum = -1;
6702 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6704 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6705 || rld[i].out != 0 || rld[i].reg_rtx == 0
6706 || reg_set_p (rld[i].reg_rtx, insn))
6709 /* Look at all other reloads. Ensure that the only use of this
6710 reload_reg_rtx is in a reload that just loads the same value
6711 as we do. Note that any secondary reloads must be of the identical
6712 class since the values, modes, and result registers are the
6713 same, so we need not do anything with any secondary reloads. */
6715 for (j = 0; j < n_reloads; j++)
6717 if (i == j || rld[j].reg_rtx == 0
6718 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6722 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6723 && rld[j].opnum > max_input_address_opnum)
6724 max_input_address_opnum = rld[j].opnum;
6726 /* If the reload regs aren't exactly the same (e.g, different modes)
6727 or if the values are different, we can't merge this reload.
6728 But if it is an input reload, we might still merge
6729 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6731 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6732 || rld[j].out != 0 || rld[j].in == 0
6733 || ! rtx_equal_p (rld[i].in, rld[j].in))
6735 if (rld[j].when_needed != RELOAD_FOR_INPUT
6736 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6737 || rld[i].opnum > rld[j].opnum)
6738 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6740 conflicting_input = 1;
6741 if (min_conflicting_input_opnum > rld[j].opnum)
6742 min_conflicting_input_opnum = rld[j].opnum;
6746 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6747 we, in fact, found any matching reloads. */
6750 && max_input_address_opnum <= min_conflicting_input_opnum)
6752 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6754 for (j = 0; j < n_reloads; j++)
6755 if (i != j && rld[j].reg_rtx != 0
6756 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6757 && (! conflicting_input
6758 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6759 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6761 rld[i].when_needed = RELOAD_OTHER;
6763 reload_spill_index[j] = -1;
6764 transfer_replacements (i, j);
6767 /* If this is now RELOAD_OTHER, look for any reloads that
6768 load parts of this operand and set them to
6769 RELOAD_FOR_OTHER_ADDRESS if they were for inputs,
6770 RELOAD_OTHER for outputs. Note that this test is
6771 equivalent to looking for reloads for this operand
6774 We must take special care with RELOAD_FOR_OUTPUT_ADDRESS;
6775 it may share registers with a RELOAD_FOR_INPUT, so we can
6776 not change it to RELOAD_FOR_OTHER_ADDRESS. We should
6777 never need to, since we do not modify RELOAD_FOR_OUTPUT.
6779 It is possible that the RELOAD_FOR_OPERAND_ADDRESS
6780 instruction is assigned the same register as the earlier
6781 RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two
6782 instructions will cause the RELOAD_FOR_OTHER_ADDRESS
6783 instruction to be deleted later on. */
6785 if (rld[i].when_needed == RELOAD_OTHER)
6786 for (j = 0; j < n_reloads; j++)
6788 && rld[j].when_needed != RELOAD_OTHER
6789 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6790 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6791 && rld[j].when_needed != RELOAD_FOR_OPERAND_ADDRESS
6792 && (! conflicting_input
6793 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6794 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6795 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6801 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6802 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6803 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6805 /* Check to see if we accidentally converted two
6806 reloads that use the same reload register with
6807 different inputs to the same type. If so, the
6808 resulting code won't work. */
6810 for (k = 0; k < j; k++)
6811 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6812 || rld[k].when_needed != rld[j].when_needed
6813 || !rtx_equal_p (rld[k].reg_rtx,
6815 || rtx_equal_p (rld[k].in,
6822 /* These arrays are filled by emit_reload_insns and its subroutines. */
6823 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6824 static rtx other_input_address_reload_insns = 0;
6825 static rtx other_input_reload_insns = 0;
6826 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6827 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6828 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6829 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6830 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6831 static rtx operand_reload_insns = 0;
6832 static rtx other_operand_reload_insns = 0;
6833 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6835 /* Values to be put in spill_reg_store are put here first. */
6836 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6837 static HARD_REG_SET reg_reloaded_died;
6839 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6840 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6841 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6842 adjusted register, and return true. Otherwise, return false. */
6844 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6845 enum reg_class new_class,
6846 enum machine_mode new_mode)
6851 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6853 unsigned regno = REGNO (reg);
6855 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6857 if (GET_MODE (reg) != new_mode)
6859 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6861 if (hard_regno_nregs[regno][new_mode]
6862 > hard_regno_nregs[regno][GET_MODE (reg)])
6864 reg = reload_adjust_reg_for_mode (reg, new_mode);
6872 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6873 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6874 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6875 adjusted register, and return true. Otherwise, return false. */
6877 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6878 enum insn_code icode)
6881 enum reg_class new_class = scratch_reload_class (icode);
6882 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6884 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6885 new_class, new_mode);
6888 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6889 has the number J. OLD contains the value to be used as input. */
6892 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6895 rtx insn = chain->insn;
6897 rtx oldequiv_reg = 0;
6900 enum machine_mode mode;
6903 /* delete_output_reload is only invoked properly if old contains
6904 the original pseudo register. Since this is replaced with a
6905 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6906 find the pseudo in RELOAD_IN_REG. */
6907 if (reload_override_in[j]
6908 && REG_P (rl->in_reg))
6915 else if (REG_P (oldequiv))
6916 oldequiv_reg = oldequiv;
6917 else if (GET_CODE (oldequiv) == SUBREG)
6918 oldequiv_reg = SUBREG_REG (oldequiv);
6920 reloadreg = reload_reg_rtx_for_input[j];
6921 mode = GET_MODE (reloadreg);
6923 /* If we are reloading from a register that was recently stored in
6924 with an output-reload, see if we can prove there was
6925 actually no need to store the old value in it. */
6927 if (optimize && REG_P (oldequiv)
6928 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6929 && spill_reg_store[REGNO (oldequiv)]
6931 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6932 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6934 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6936 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
6939 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6940 oldequiv = SUBREG_REG (oldequiv);
6941 if (GET_MODE (oldequiv) != VOIDmode
6942 && mode != GET_MODE (oldequiv))
6943 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6945 /* Switch to the right place to emit the reload insns. */
6946 switch (rl->when_needed)
6949 where = &other_input_reload_insns;
6951 case RELOAD_FOR_INPUT:
6952 where = &input_reload_insns[rl->opnum];
6954 case RELOAD_FOR_INPUT_ADDRESS:
6955 where = &input_address_reload_insns[rl->opnum];
6957 case RELOAD_FOR_INPADDR_ADDRESS:
6958 where = &inpaddr_address_reload_insns[rl->opnum];
6960 case RELOAD_FOR_OUTPUT_ADDRESS:
6961 where = &output_address_reload_insns[rl->opnum];
6963 case RELOAD_FOR_OUTADDR_ADDRESS:
6964 where = &outaddr_address_reload_insns[rl->opnum];
6966 case RELOAD_FOR_OPERAND_ADDRESS:
6967 where = &operand_reload_insns;
6969 case RELOAD_FOR_OPADDR_ADDR:
6970 where = &other_operand_reload_insns;
6972 case RELOAD_FOR_OTHER_ADDRESS:
6973 where = &other_input_address_reload_insns;
6979 push_to_sequence (*where);
6981 /* Auto-increment addresses must be reloaded in a special way. */
6982 if (rl->out && ! rl->out_reg)
6984 /* We are not going to bother supporting the case where a
6985 incremented register can't be copied directly from
6986 OLDEQUIV since this seems highly unlikely. */
6987 gcc_assert (rl->secondary_in_reload < 0);
6989 if (reload_inherited[j])
6990 oldequiv = reloadreg;
6992 old = XEXP (rl->in_reg, 0);
6994 if (optimize && REG_P (oldequiv)
6995 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6996 && spill_reg_store[REGNO (oldequiv)]
6998 && (dead_or_set_p (insn,
6999 spill_reg_stored_to[REGNO (oldequiv)])
7000 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
7002 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
7004 /* Prevent normal processing of this reload. */
7006 /* Output a special code sequence for this case. */
7007 new_spill_reg_store[REGNO (reloadreg)]
7008 = inc_for_reload (reloadreg, oldequiv, rl->out,
7012 /* If we are reloading a pseudo-register that was set by the previous
7013 insn, see if we can get rid of that pseudo-register entirely
7014 by redirecting the previous insn into our reload register. */
7016 else if (optimize && REG_P (old)
7017 && REGNO (old) >= FIRST_PSEUDO_REGISTER
7018 && dead_or_set_p (insn, old)
7019 /* This is unsafe if some other reload
7020 uses the same reg first. */
7021 && ! conflicts_with_override (reloadreg)
7022 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
7023 rl->when_needed, old, rl->out, j, 0))
7025 rtx temp = PREV_INSN (insn);
7026 while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp)))
7027 temp = PREV_INSN (temp);
7029 && NONJUMP_INSN_P (temp)
7030 && GET_CODE (PATTERN (temp)) == SET
7031 && SET_DEST (PATTERN (temp)) == old
7032 /* Make sure we can access insn_operand_constraint. */
7033 && asm_noperands (PATTERN (temp)) < 0
7034 /* This is unsafe if operand occurs more than once in current
7035 insn. Perhaps some occurrences aren't reloaded. */
7036 && count_occurrences (PATTERN (insn), old, 0) == 1)
7038 rtx old = SET_DEST (PATTERN (temp));
7039 /* Store into the reload register instead of the pseudo. */
7040 SET_DEST (PATTERN (temp)) = reloadreg;
7042 /* Verify that resulting insn is valid. */
7043 extract_insn (temp);
7044 if (constrain_operands (1))
7046 /* If the previous insn is an output reload, the source is
7047 a reload register, and its spill_reg_store entry will
7048 contain the previous destination. This is now
7050 if (REG_P (SET_SRC (PATTERN (temp)))
7051 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
7053 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7054 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7057 /* If these are the only uses of the pseudo reg,
7058 pretend for GDB it lives in the reload reg we used. */
7059 if (REG_N_DEATHS (REGNO (old)) == 1
7060 && REG_N_SETS (REGNO (old)) == 1)
7062 reg_renumber[REGNO (old)] = REGNO (reloadreg);
7063 if (ira_conflicts_p)
7064 /* Inform IRA about the change. */
7065 ira_mark_allocation_change (REGNO (old));
7066 alter_reg (REGNO (old), -1, false);
7070 /* Adjust any debug insns between temp and insn. */
7071 while ((temp = NEXT_INSN (temp)) != insn)
7072 if (DEBUG_INSN_P (temp))
7073 replace_rtx (PATTERN (temp), old, reloadreg);
7075 gcc_assert (NOTE_P (temp));
7079 SET_DEST (PATTERN (temp)) = old;
7084 /* We can't do that, so output an insn to load RELOADREG. */
7086 /* If we have a secondary reload, pick up the secondary register
7087 and icode, if any. If OLDEQUIV and OLD are different or
7088 if this is an in-out reload, recompute whether or not we
7089 still need a secondary register and what the icode should
7090 be. If we still need a secondary register and the class or
7091 icode is different, go back to reloading from OLD if using
7092 OLDEQUIV means that we got the wrong type of register. We
7093 cannot have different class or icode due to an in-out reload
7094 because we don't make such reloads when both the input and
7095 output need secondary reload registers. */
7097 if (! special && rl->secondary_in_reload >= 0)
7099 rtx second_reload_reg = 0;
7100 rtx third_reload_reg = 0;
7101 int secondary_reload = rl->secondary_in_reload;
7102 rtx real_oldequiv = oldequiv;
7105 enum insn_code icode;
7106 enum insn_code tertiary_icode = CODE_FOR_nothing;
7108 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7109 and similarly for OLD.
7110 See comments in get_secondary_reload in reload.c. */
7111 /* If it is a pseudo that cannot be replaced with its
7112 equivalent MEM, we must fall back to reload_in, which
7113 will have all the necessary substitutions registered.
7114 Likewise for a pseudo that can't be replaced with its
7115 equivalent constant.
7117 Take extra care for subregs of such pseudos. Note that
7118 we cannot use reg_equiv_mem in this case because it is
7119 not in the right mode. */
7122 if (GET_CODE (tmp) == SUBREG)
7123 tmp = SUBREG_REG (tmp);
7125 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7126 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7127 || reg_equiv_constant[REGNO (tmp)] != 0))
7129 if (! reg_equiv_mem[REGNO (tmp)]
7130 || num_not_at_initial_offset
7131 || GET_CODE (oldequiv) == SUBREG)
7132 real_oldequiv = rl->in;
7134 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
7138 if (GET_CODE (tmp) == SUBREG)
7139 tmp = SUBREG_REG (tmp);
7141 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7142 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7143 || reg_equiv_constant[REGNO (tmp)] != 0))
7145 if (! reg_equiv_mem[REGNO (tmp)]
7146 || num_not_at_initial_offset
7147 || GET_CODE (old) == SUBREG)
7150 real_old = reg_equiv_mem[REGNO (tmp)];
7153 second_reload_reg = rld[secondary_reload].reg_rtx;
7154 if (rld[secondary_reload].secondary_in_reload >= 0)
7156 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7158 third_reload_reg = rld[tertiary_reload].reg_rtx;
7159 tertiary_icode = rld[secondary_reload].secondary_in_icode;
7160 /* We'd have to add more code for quartary reloads. */
7161 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7163 icode = rl->secondary_in_icode;
7165 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7166 || (rl->in != 0 && rl->out != 0))
7168 secondary_reload_info sri, sri2;
7169 enum reg_class new_class, new_t_class;
7171 sri.icode = CODE_FOR_nothing;
7172 sri.prev_sri = NULL;
7173 new_class = targetm.secondary_reload (1, real_oldequiv, rl->rclass,
7176 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7177 second_reload_reg = 0;
7178 else if (new_class == NO_REGS)
7180 if (reload_adjust_reg_for_icode (&second_reload_reg,
7182 (enum insn_code) sri.icode))
7184 icode = (enum insn_code) sri.icode;
7185 third_reload_reg = 0;
7190 real_oldequiv = real_old;
7193 else if (sri.icode != CODE_FOR_nothing)
7194 /* We currently lack a way to express this in reloads. */
7198 sri2.icode = CODE_FOR_nothing;
7199 sri2.prev_sri = &sri;
7200 new_t_class = targetm.secondary_reload (1, real_oldequiv,
7201 new_class, mode, &sri);
7202 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7204 if (reload_adjust_reg_for_temp (&second_reload_reg,
7208 third_reload_reg = 0;
7209 tertiary_icode = (enum insn_code) sri2.icode;
7214 real_oldequiv = real_old;
7217 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7219 rtx intermediate = second_reload_reg;
7221 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7223 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7227 second_reload_reg = intermediate;
7228 tertiary_icode = (enum insn_code) sri2.icode;
7233 real_oldequiv = real_old;
7236 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7238 rtx intermediate = second_reload_reg;
7240 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7242 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7245 second_reload_reg = intermediate;
7246 tertiary_icode = (enum insn_code) sri2.icode;
7251 real_oldequiv = real_old;
7256 /* This could be handled more intelligently too. */
7258 real_oldequiv = real_old;
7263 /* If we still need a secondary reload register, check
7264 to see if it is being used as a scratch or intermediate
7265 register and generate code appropriately. If we need
7266 a scratch register, use REAL_OLDEQUIV since the form of
7267 the insn may depend on the actual address if it is
7270 if (second_reload_reg)
7272 if (icode != CODE_FOR_nothing)
7274 /* We'd have to add extra code to handle this case. */
7275 gcc_assert (!third_reload_reg);
7277 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7278 second_reload_reg));
7283 /* See if we need a scratch register to load the
7284 intermediate register (a tertiary reload). */
7285 if (tertiary_icode != CODE_FOR_nothing)
7287 emit_insn ((GEN_FCN (tertiary_icode)
7288 (second_reload_reg, real_oldequiv,
7289 third_reload_reg)));
7291 else if (third_reload_reg)
7293 gen_reload (third_reload_reg, real_oldequiv,
7296 gen_reload (second_reload_reg, third_reload_reg,
7301 gen_reload (second_reload_reg, real_oldequiv,
7305 oldequiv = second_reload_reg;
7310 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7312 rtx real_oldequiv = oldequiv;
7314 if ((REG_P (oldequiv)
7315 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7316 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
7317 || reg_equiv_constant[REGNO (oldequiv)] != 0))
7318 || (GET_CODE (oldequiv) == SUBREG
7319 && REG_P (SUBREG_REG (oldequiv))
7320 && (REGNO (SUBREG_REG (oldequiv))
7321 >= FIRST_PSEUDO_REGISTER)
7322 && ((reg_equiv_memory_loc
7323 [REGNO (SUBREG_REG (oldequiv))] != 0)
7324 || (reg_equiv_constant
7325 [REGNO (SUBREG_REG (oldequiv))] != 0)))
7326 || (CONSTANT_P (oldequiv)
7327 && (PREFERRED_RELOAD_CLASS (oldequiv,
7328 REGNO_REG_CLASS (REGNO (reloadreg)))
7330 real_oldequiv = rl->in;
7331 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7335 if (flag_non_call_exceptions)
7336 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7338 /* End this sequence. */
7339 *where = get_insns ();
7342 /* Update reload_override_in so that delete_address_reloads_1
7343 can see the actual register usage. */
7345 reload_override_in[j] = oldequiv;
7348 /* Generate insns to for the output reload RL, which is for the insn described
7349 by CHAIN and has the number J. */
7351 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7355 rtx insn = chain->insn;
7358 enum machine_mode mode;
7362 if (rl->when_needed == RELOAD_OTHER)
7365 push_to_sequence (output_reload_insns[rl->opnum]);
7367 rl_reg_rtx = reload_reg_rtx_for_output[j];
7368 mode = GET_MODE (rl_reg_rtx);
7370 reloadreg = rl_reg_rtx;
7372 /* If we need two reload regs, set RELOADREG to the intermediate
7373 one, since it will be stored into OLD. We might need a secondary
7374 register only for an input reload, so check again here. */
7376 if (rl->secondary_out_reload >= 0)
7379 int secondary_reload = rl->secondary_out_reload;
7380 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7382 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7383 && reg_equiv_mem[REGNO (old)] != 0)
7384 real_old = reg_equiv_mem[REGNO (old)];
7386 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7388 rtx second_reloadreg = reloadreg;
7389 reloadreg = rld[secondary_reload].reg_rtx;
7391 /* See if RELOADREG is to be used as a scratch register
7392 or as an intermediate register. */
7393 if (rl->secondary_out_icode != CODE_FOR_nothing)
7395 /* We'd have to add extra code to handle this case. */
7396 gcc_assert (tertiary_reload < 0);
7398 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7399 (real_old, second_reloadreg, reloadreg)));
7404 /* See if we need both a scratch and intermediate reload
7407 enum insn_code tertiary_icode
7408 = rld[secondary_reload].secondary_out_icode;
7410 /* We'd have to add more code for quartary reloads. */
7411 gcc_assert (tertiary_reload < 0
7412 || rld[tertiary_reload].secondary_out_reload < 0);
7414 if (GET_MODE (reloadreg) != mode)
7415 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7417 if (tertiary_icode != CODE_FOR_nothing)
7419 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7422 /* Copy primary reload reg to secondary reload reg.
7423 (Note that these have been swapped above, then
7424 secondary reload reg to OLD using our insn.) */
7426 /* If REAL_OLD is a paradoxical SUBREG, remove it
7427 and try to put the opposite SUBREG on
7429 if (GET_CODE (real_old) == SUBREG
7430 && (GET_MODE_SIZE (GET_MODE (real_old))
7431 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7432 && 0 != (tem = gen_lowpart_common
7433 (GET_MODE (SUBREG_REG (real_old)),
7435 real_old = SUBREG_REG (real_old), reloadreg = tem;
7437 gen_reload (reloadreg, second_reloadreg,
7438 rl->opnum, rl->when_needed);
7439 emit_insn ((GEN_FCN (tertiary_icode)
7440 (real_old, reloadreg, third_reloadreg)));
7446 /* Copy between the reload regs here and then to
7449 gen_reload (reloadreg, second_reloadreg,
7450 rl->opnum, rl->when_needed);
7451 if (tertiary_reload >= 0)
7453 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7455 gen_reload (third_reloadreg, reloadreg,
7456 rl->opnum, rl->when_needed);
7457 reloadreg = third_reloadreg;
7464 /* Output the last reload insn. */
7469 /* Don't output the last reload if OLD is not the dest of
7470 INSN and is in the src and is clobbered by INSN. */
7471 if (! flag_expensive_optimizations
7473 || !(set = single_set (insn))
7474 || rtx_equal_p (old, SET_DEST (set))
7475 || !reg_mentioned_p (old, SET_SRC (set))
7476 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7477 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7478 gen_reload (old, reloadreg, rl->opnum,
7482 /* Look at all insns we emitted, just to be safe. */
7483 for (p = get_insns (); p; p = NEXT_INSN (p))
7486 rtx pat = PATTERN (p);
7488 /* If this output reload doesn't come from a spill reg,
7489 clear any memory of reloaded copies of the pseudo reg.
7490 If this output reload comes from a spill reg,
7491 reg_has_output_reload will make this do nothing. */
7492 note_stores (pat, forget_old_reloads_1, NULL);
7494 if (reg_mentioned_p (rl_reg_rtx, pat))
7496 rtx set = single_set (insn);
7497 if (reload_spill_index[j] < 0
7499 && SET_SRC (set) == rl_reg_rtx)
7501 int src = REGNO (SET_SRC (set));
7503 reload_spill_index[j] = src;
7504 SET_HARD_REG_BIT (reg_is_output_reload, src);
7505 if (find_regno_note (insn, REG_DEAD, src))
7506 SET_HARD_REG_BIT (reg_reloaded_died, src);
7508 if (HARD_REGISTER_P (rl_reg_rtx))
7510 int s = rl->secondary_out_reload;
7511 set = single_set (p);
7512 /* If this reload copies only to the secondary reload
7513 register, the secondary reload does the actual
7515 if (s >= 0 && set == NULL_RTX)
7516 /* We can't tell what function the secondary reload
7517 has and where the actual store to the pseudo is
7518 made; leave new_spill_reg_store alone. */
7521 && SET_SRC (set) == rl_reg_rtx
7522 && SET_DEST (set) == rld[s].reg_rtx)
7524 /* Usually the next instruction will be the
7525 secondary reload insn; if we can confirm
7526 that it is, setting new_spill_reg_store to
7527 that insn will allow an extra optimization. */
7528 rtx s_reg = rld[s].reg_rtx;
7529 rtx next = NEXT_INSN (p);
7530 rld[s].out = rl->out;
7531 rld[s].out_reg = rl->out_reg;
7532 set = single_set (next);
7533 if (set && SET_SRC (set) == s_reg
7534 && ! new_spill_reg_store[REGNO (s_reg)])
7536 SET_HARD_REG_BIT (reg_is_output_reload,
7538 new_spill_reg_store[REGNO (s_reg)] = next;
7542 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7547 if (rl->when_needed == RELOAD_OTHER)
7549 emit_insn (other_output_reload_insns[rl->opnum]);
7550 other_output_reload_insns[rl->opnum] = get_insns ();
7553 output_reload_insns[rl->opnum] = get_insns ();
7555 if (flag_non_call_exceptions)
7556 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7561 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7562 and has the number J. */
7564 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7566 rtx insn = chain->insn;
7567 rtx old = (rl->in && MEM_P (rl->in)
7568 ? rl->in_reg : rl->in);
7569 rtx reg_rtx = rl->reg_rtx;
7573 enum machine_mode mode;
7575 /* Determine the mode to reload in.
7576 This is very tricky because we have three to choose from.
7577 There is the mode the insn operand wants (rl->inmode).
7578 There is the mode of the reload register RELOADREG.
7579 There is the intrinsic mode of the operand, which we could find
7580 by stripping some SUBREGs.
7581 It turns out that RELOADREG's mode is irrelevant:
7582 we can change that arbitrarily.
7584 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7585 then the reload reg may not support QImode moves, so use SImode.
7586 If foo is in memory due to spilling a pseudo reg, this is safe,
7587 because the QImode value is in the least significant part of a
7588 slot big enough for a SImode. If foo is some other sort of
7589 memory reference, then it is impossible to reload this case,
7590 so previous passes had better make sure this never happens.
7592 Then consider a one-word union which has SImode and one of its
7593 members is a float, being fetched as (SUBREG:SF union:SI).
7594 We must fetch that as SFmode because we could be loading into
7595 a float-only register. In this case OLD's mode is correct.
7597 Consider an immediate integer: it has VOIDmode. Here we need
7598 to get a mode from something else.
7600 In some cases, there is a fourth mode, the operand's
7601 containing mode. If the insn specifies a containing mode for
7602 this operand, it overrides all others.
7604 I am not sure whether the algorithm here is always right,
7605 but it does the right things in those cases. */
7607 mode = GET_MODE (old);
7608 if (mode == VOIDmode)
7611 /* We cannot use gen_lowpart_common since it can do the wrong thing
7612 when REG_RTX has a multi-word mode. Note that REG_RTX must
7613 always be a REG here. */
7614 if (GET_MODE (reg_rtx) != mode)
7615 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7617 reload_reg_rtx_for_input[j] = reg_rtx;
7620 /* AUTO_INC reloads need to be handled even if inherited. We got an
7621 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7622 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7623 && ! rtx_equal_p (reg_rtx, old)
7625 emit_input_reload_insns (chain, rld + j, old, j);
7627 /* When inheriting a wider reload, we have a MEM in rl->in,
7628 e.g. inheriting a SImode output reload for
7629 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7630 if (optimize && reload_inherited[j] && rl->in
7632 && MEM_P (rl->in_reg)
7633 && reload_spill_index[j] >= 0
7634 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7635 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7637 /* If we are reloading a register that was recently stored in with an
7638 output-reload, see if we can prove there was
7639 actually no need to store the old value in it. */
7642 && (reload_inherited[j] || reload_override_in[j])
7645 && spill_reg_store[REGNO (reg_rtx)] != 0
7647 /* There doesn't seem to be any reason to restrict this to pseudos
7648 and doing so loses in the case where we are copying from a
7649 register of the wrong class. */
7650 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7652 /* The insn might have already some references to stackslots
7653 replaced by MEMs, while reload_out_reg still names the
7655 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7656 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7657 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7660 /* Do output reloading for reload RL, which is for the insn described by
7661 CHAIN and has the number J.
7662 ??? At some point we need to support handling output reloads of
7663 JUMP_INSNs or insns that set cc0. */
7665 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7668 rtx insn = chain->insn;
7669 /* If this is an output reload that stores something that is
7670 not loaded in this same reload, see if we can eliminate a previous
7672 rtx pseudo = rl->out_reg;
7673 rtx reg_rtx = rl->reg_rtx;
7675 if (rl->out && reg_rtx)
7677 enum machine_mode mode;
7679 /* Determine the mode to reload in.
7680 See comments above (for input reloading). */
7681 mode = GET_MODE (rl->out);
7682 if (mode == VOIDmode)
7684 /* VOIDmode should never happen for an output. */
7685 if (asm_noperands (PATTERN (insn)) < 0)
7686 /* It's the compiler's fault. */
7687 fatal_insn ("VOIDmode on an output", insn);
7688 error_for_asm (insn, "output operand is constant in %<asm%>");
7689 /* Prevent crash--use something we know is valid. */
7691 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7693 if (GET_MODE (reg_rtx) != mode)
7694 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7696 reload_reg_rtx_for_output[j] = reg_rtx;
7701 && ! rtx_equal_p (rl->in_reg, pseudo)
7702 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7703 && reg_last_reload_reg[REGNO (pseudo)])
7705 int pseudo_no = REGNO (pseudo);
7706 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7708 /* We don't need to test full validity of last_regno for
7709 inherit here; we only want to know if the store actually
7710 matches the pseudo. */
7711 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7712 && reg_reloaded_contents[last_regno] == pseudo_no
7713 && spill_reg_store[last_regno]
7714 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7715 delete_output_reload (insn, j, last_regno, reg_rtx);
7721 || rtx_equal_p (old, reg_rtx))
7724 /* An output operand that dies right away does need a reload,
7725 but need not be copied from it. Show the new location in the
7727 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7728 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7730 XEXP (note, 0) = reg_rtx;
7733 /* Likewise for a SUBREG of an operand that dies. */
7734 else if (GET_CODE (old) == SUBREG
7735 && REG_P (SUBREG_REG (old))
7736 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7739 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7742 else if (GET_CODE (old) == SCRATCH)
7743 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7744 but we don't want to make an output reload. */
7747 /* If is a JUMP_INSN, we can't support output reloads yet. */
7748 gcc_assert (NONJUMP_INSN_P (insn));
7750 emit_output_reload_insns (chain, rld + j, j);
7753 /* A reload copies values of MODE from register SRC to register DEST.
7754 Return true if it can be treated for inheritance purposes like a
7755 group of reloads, each one reloading a single hard register. The
7756 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7757 occupy the same number of hard registers. */
7760 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
7761 int src ATTRIBUTE_UNUSED,
7762 enum machine_mode mode ATTRIBUTE_UNUSED)
7764 #ifdef CANNOT_CHANGE_MODE_CLASS
7765 return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
7766 && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
7772 /* Output insns to reload values in and out of the chosen reload regs. */
7775 emit_reload_insns (struct insn_chain *chain)
7777 rtx insn = chain->insn;
7781 CLEAR_HARD_REG_SET (reg_reloaded_died);
7783 for (j = 0; j < reload_n_operands; j++)
7784 input_reload_insns[j] = input_address_reload_insns[j]
7785 = inpaddr_address_reload_insns[j]
7786 = output_reload_insns[j] = output_address_reload_insns[j]
7787 = outaddr_address_reload_insns[j]
7788 = other_output_reload_insns[j] = 0;
7789 other_input_address_reload_insns = 0;
7790 other_input_reload_insns = 0;
7791 operand_reload_insns = 0;
7792 other_operand_reload_insns = 0;
7794 /* Dump reloads into the dump file. */
7797 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7798 debug_reload_to_stream (dump_file);
7801 /* Now output the instructions to copy the data into and out of the
7802 reload registers. Do these in the order that the reloads were reported,
7803 since reloads of base and index registers precede reloads of operands
7804 and the operands may need the base and index registers reloaded. */
7806 for (j = 0; j < n_reloads; j++)
7808 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
7812 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
7813 new_spill_reg_store[i] = 0;
7816 do_input_reload (chain, rld + j, j);
7817 do_output_reload (chain, rld + j, j);
7820 /* Now write all the insns we made for reloads in the order expected by
7821 the allocation functions. Prior to the insn being reloaded, we write
7822 the following reloads:
7824 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7826 RELOAD_OTHER reloads.
7828 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7829 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7830 RELOAD_FOR_INPUT reload for the operand.
7832 RELOAD_FOR_OPADDR_ADDRS reloads.
7834 RELOAD_FOR_OPERAND_ADDRESS reloads.
7836 After the insn being reloaded, we write the following:
7838 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7839 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7840 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7841 reloads for the operand. The RELOAD_OTHER output reloads are
7842 output in descending order by reload number. */
7844 emit_insn_before (other_input_address_reload_insns, insn);
7845 emit_insn_before (other_input_reload_insns, insn);
7847 for (j = 0; j < reload_n_operands; j++)
7849 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7850 emit_insn_before (input_address_reload_insns[j], insn);
7851 emit_insn_before (input_reload_insns[j], insn);
7854 emit_insn_before (other_operand_reload_insns, insn);
7855 emit_insn_before (operand_reload_insns, insn);
7857 for (j = 0; j < reload_n_operands; j++)
7859 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7860 x = emit_insn_after (output_address_reload_insns[j], x);
7861 x = emit_insn_after (output_reload_insns[j], x);
7862 emit_insn_after (other_output_reload_insns[j], x);
7865 /* For all the spill regs newly reloaded in this instruction,
7866 record what they were reloaded from, so subsequent instructions
7867 can inherit the reloads.
7869 Update spill_reg_store for the reloads of this insn.
7870 Copy the elements that were updated in the loop above. */
7872 for (j = 0; j < n_reloads; j++)
7874 int r = reload_order[j];
7875 int i = reload_spill_index[r];
7877 /* If this is a non-inherited input reload from a pseudo, we must
7878 clear any memory of a previous store to the same pseudo. Only do
7879 something if there will not be an output reload for the pseudo
7881 if (rld[r].in_reg != 0
7882 && ! (reload_inherited[r] || reload_override_in[r]))
7884 rtx reg = rld[r].in_reg;
7886 if (GET_CODE (reg) == SUBREG)
7887 reg = SUBREG_REG (reg);
7890 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7891 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7893 int nregno = REGNO (reg);
7895 if (reg_last_reload_reg[nregno])
7897 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7899 if (reg_reloaded_contents[last_regno] == nregno)
7900 spill_reg_store[last_regno] = 0;
7905 /* I is nonneg if this reload used a register.
7906 If rld[r].reg_rtx is 0, this is an optional reload
7907 that we opted to ignore. */
7909 if (i >= 0 && rld[r].reg_rtx != 0)
7911 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7914 /* For a multi register reload, we need to check if all or part
7915 of the value lives to the end. */
7916 for (k = 0; k < nr; k++)
7917 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7918 rld[r].when_needed))
7919 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7921 /* Maybe the spill reg contains a copy of reload_out. */
7923 && (REG_P (rld[r].out)
7927 || REG_P (rld[r].out_reg)))
7930 enum machine_mode mode;
7933 reg = reload_reg_rtx_for_output[r];
7934 mode = GET_MODE (reg);
7935 regno = REGNO (reg);
7936 nregs = hard_regno_nregs[regno][mode];
7937 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7938 rld[r].when_needed))
7940 rtx out = (REG_P (rld[r].out)
7944 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7945 int out_regno = REGNO (out);
7946 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
7947 : hard_regno_nregs[out_regno][mode]);
7950 spill_reg_store[regno] = new_spill_reg_store[regno];
7951 spill_reg_stored_to[regno] = out;
7952 reg_last_reload_reg[out_regno] = reg;
7954 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
7955 && nregs == out_nregs
7956 && inherit_piecemeal_p (out_regno, regno, mode));
7958 /* If OUT_REGNO is a hard register, it may occupy more than
7959 one register. If it does, say what is in the
7960 rest of the registers assuming that both registers
7961 agree on how many words the object takes. If not,
7962 invalidate the subsequent registers. */
7964 if (HARD_REGISTER_NUM_P (out_regno))
7965 for (k = 1; k < out_nregs; k++)
7966 reg_last_reload_reg[out_regno + k]
7967 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7969 /* Now do the inverse operation. */
7970 for (k = 0; k < nregs; k++)
7972 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
7973 reg_reloaded_contents[regno + k]
7974 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
7977 reg_reloaded_insn[regno + k] = insn;
7978 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
7979 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
7980 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7983 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7988 /* Maybe the spill reg contains a copy of reload_in. Only do
7989 something if there will not be an output reload for
7990 the register being reloaded. */
7991 else if (rld[r].out_reg == 0
7993 && ((REG_P (rld[r].in)
7994 && !HARD_REGISTER_P (rld[r].in)
7995 && !REGNO_REG_SET_P (®_has_output_reload,
7997 || (REG_P (rld[r].in_reg)
7998 && !REGNO_REG_SET_P (®_has_output_reload,
7999 REGNO (rld[r].in_reg))))
8000 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
8003 enum machine_mode mode;
8006 reg = reload_reg_rtx_for_input[r];
8007 mode = GET_MODE (reg);
8008 regno = REGNO (reg);
8009 nregs = hard_regno_nregs[regno][mode];
8010 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
8011 rld[r].when_needed))
8018 if (REG_P (rld[r].in)
8019 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
8021 else if (REG_P (rld[r].in_reg))
8024 in = XEXP (rld[r].in_reg, 0);
8025 in_regno = REGNO (in);
8027 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
8028 : hard_regno_nregs[in_regno][mode]);
8030 reg_last_reload_reg[in_regno] = reg;
8032 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
8033 && nregs == in_nregs
8034 && inherit_piecemeal_p (regno, in_regno, mode));
8036 if (HARD_REGISTER_NUM_P (in_regno))
8037 for (k = 1; k < in_nregs; k++)
8038 reg_last_reload_reg[in_regno + k]
8039 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8041 /* Unless we inherited this reload, show we haven't
8042 recently done a store.
8043 Previous stores of inherited auto_inc expressions
8044 also have to be discarded. */
8045 if (! reload_inherited[r]
8046 || (rld[r].out && ! rld[r].out_reg))
8047 spill_reg_store[regno] = 0;
8049 for (k = 0; k < nregs; k++)
8051 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8052 reg_reloaded_contents[regno + k]
8053 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
8056 reg_reloaded_insn[regno + k] = insn;
8057 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8058 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8059 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8062 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8069 /* The following if-statement was #if 0'd in 1.34 (or before...).
8070 It's reenabled in 1.35 because supposedly nothing else
8071 deals with this problem. */
8073 /* If a register gets output-reloaded from a non-spill register,
8074 that invalidates any previous reloaded copy of it.
8075 But forget_old_reloads_1 won't get to see it, because
8076 it thinks only about the original insn. So invalidate it here.
8077 Also do the same thing for RELOAD_OTHER constraints where the
8078 output is discarded. */
8080 && ((rld[r].out != 0
8081 && (REG_P (rld[r].out)
8082 || (MEM_P (rld[r].out)
8083 && REG_P (rld[r].out_reg))))
8084 || (rld[r].out == 0 && rld[r].out_reg
8085 && REG_P (rld[r].out_reg))))
8087 rtx out = ((rld[r].out && REG_P (rld[r].out))
8088 ? rld[r].out : rld[r].out_reg);
8089 int out_regno = REGNO (out);
8090 enum machine_mode mode = GET_MODE (out);
8092 /* REG_RTX is now set or clobbered by the main instruction.
8093 As the comment above explains, forget_old_reloads_1 only
8094 sees the original instruction, and there is no guarantee
8095 that the original instruction also clobbered REG_RTX.
8096 For example, if find_reloads sees that the input side of
8097 a matched operand pair dies in this instruction, it may
8098 use the input register as the reload register.
8100 Calling forget_old_reloads_1 is a waste of effort if
8101 REG_RTX is also the output register.
8103 If we know that REG_RTX holds the value of a pseudo
8104 register, the code after the call will record that fact. */
8105 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8106 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8108 if (!HARD_REGISTER_NUM_P (out_regno))
8110 rtx src_reg, store_insn = NULL_RTX;
8112 reg_last_reload_reg[out_regno] = 0;
8114 /* If we can find a hard register that is stored, record
8115 the storing insn so that we may delete this insn with
8116 delete_output_reload. */
8117 src_reg = reload_reg_rtx_for_output[r];
8119 /* If this is an optional reload, try to find the source reg
8120 from an input reload. */
8123 rtx set = single_set (insn);
8124 if (set && SET_DEST (set) == rld[r].out)
8128 src_reg = SET_SRC (set);
8130 for (k = 0; k < n_reloads; k++)
8132 if (rld[k].in == src_reg)
8134 src_reg = reload_reg_rtx_for_input[k];
8141 store_insn = new_spill_reg_store[REGNO (src_reg)];
8142 if (src_reg && REG_P (src_reg)
8143 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8145 int src_regno, src_nregs, k;
8148 gcc_assert (GET_MODE (src_reg) == mode);
8149 src_regno = REGNO (src_reg);
8150 src_nregs = hard_regno_nregs[src_regno][mode];
8151 /* The place where to find a death note varies with
8152 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8153 necessarily checked exactly in the code that moves
8154 notes, so just check both locations. */
8155 note = find_regno_note (insn, REG_DEAD, src_regno);
8156 if (! note && store_insn)
8157 note = find_regno_note (store_insn, REG_DEAD, src_regno);
8158 for (k = 0; k < src_nregs; k++)
8160 spill_reg_store[src_regno + k] = store_insn;
8161 spill_reg_stored_to[src_regno + k] = out;
8162 reg_reloaded_contents[src_regno + k] = out_regno;
8163 reg_reloaded_insn[src_regno + k] = store_insn;
8164 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8165 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8166 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
8168 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8171 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8173 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8175 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8177 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8179 reg_last_reload_reg[out_regno] = src_reg;
8180 /* We have to set reg_has_output_reload here, or else
8181 forget_old_reloads_1 will clear reg_last_reload_reg
8183 SET_REGNO_REG_SET (®_has_output_reload,
8189 int k, out_nregs = hard_regno_nregs[out_regno][mode];
8191 for (k = 0; k < out_nregs; k++)
8192 reg_last_reload_reg[out_regno + k] = 0;
8196 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8199 /* Go through the motions to emit INSN and test if it is strictly valid.
8200 Return the emitted insn if valid, else return NULL. */
8203 emit_insn_if_valid_for_reload (rtx insn)
8205 rtx last = get_last_insn ();
8208 insn = emit_insn (insn);
8209 code = recog_memoized (insn);
8213 extract_insn (insn);
8214 /* We want constrain operands to treat this insn strictly in its
8215 validity determination, i.e., the way it would after reload has
8217 if (constrain_operands (1))
8221 delete_insns_since (last);
8225 /* Emit code to perform a reload from IN (which may be a reload register) to
8226 OUT (which may also be a reload register). IN or OUT is from operand
8227 OPNUM with reload type TYPE.
8229 Returns first insn emitted. */
8232 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8234 rtx last = get_last_insn ();
8237 /* If IN is a paradoxical SUBREG, remove it and try to put the
8238 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8239 if (GET_CODE (in) == SUBREG
8240 && (GET_MODE_SIZE (GET_MODE (in))
8241 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
8242 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
8243 in = SUBREG_REG (in), out = tem;
8244 else if (GET_CODE (out) == SUBREG
8245 && (GET_MODE_SIZE (GET_MODE (out))
8246 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
8247 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
8248 out = SUBREG_REG (out), in = tem;
8250 /* How to do this reload can get quite tricky. Normally, we are being
8251 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8252 register that didn't get a hard register. In that case we can just
8253 call emit_move_insn.
8255 We can also be asked to reload a PLUS that adds a register or a MEM to
8256 another register, constant or MEM. This can occur during frame pointer
8257 elimination and while reloading addresses. This case is handled by
8258 trying to emit a single insn to perform the add. If it is not valid,
8259 we use a two insn sequence.
8261 Or we can be asked to reload an unary operand that was a fragment of
8262 an addressing mode, into a register. If it isn't recognized as-is,
8263 we try making the unop operand and the reload-register the same:
8264 (set reg:X (unop:X expr:Y))
8265 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8267 Finally, we could be called to handle an 'o' constraint by putting
8268 an address into a register. In that case, we first try to do this
8269 with a named pattern of "reload_load_address". If no such pattern
8270 exists, we just emit a SET insn and hope for the best (it will normally
8271 be valid on machines that use 'o').
8273 This entire process is made complex because reload will never
8274 process the insns we generate here and so we must ensure that
8275 they will fit their constraints and also by the fact that parts of
8276 IN might be being reloaded separately and replaced with spill registers.
8277 Because of this, we are, in some sense, just guessing the right approach
8278 here. The one listed above seems to work.
8280 ??? At some point, this whole thing needs to be rethought. */
8282 if (GET_CODE (in) == PLUS
8283 && (REG_P (XEXP (in, 0))
8284 || GET_CODE (XEXP (in, 0)) == SUBREG
8285 || MEM_P (XEXP (in, 0)))
8286 && (REG_P (XEXP (in, 1))
8287 || GET_CODE (XEXP (in, 1)) == SUBREG
8288 || CONSTANT_P (XEXP (in, 1))
8289 || MEM_P (XEXP (in, 1))))
8291 /* We need to compute the sum of a register or a MEM and another
8292 register, constant, or MEM, and put it into the reload
8293 register. The best possible way of doing this is if the machine
8294 has a three-operand ADD insn that accepts the required operands.
8296 The simplest approach is to try to generate such an insn and see if it
8297 is recognized and matches its constraints. If so, it can be used.
8299 It might be better not to actually emit the insn unless it is valid,
8300 but we need to pass the insn as an operand to `recog' and
8301 `extract_insn' and it is simpler to emit and then delete the insn if
8302 not valid than to dummy things up. */
8304 rtx op0, op1, tem, insn;
8307 op0 = find_replacement (&XEXP (in, 0));
8308 op1 = find_replacement (&XEXP (in, 1));
8310 /* Since constraint checking is strict, commutativity won't be
8311 checked, so we need to do that here to avoid spurious failure
8312 if the add instruction is two-address and the second operand
8313 of the add is the same as the reload reg, which is frequently
8314 the case. If the insn would be A = B + A, rearrange it so
8315 it will be A = A + B as constrain_operands expects. */
8317 if (REG_P (XEXP (in, 1))
8318 && REGNO (out) == REGNO (XEXP (in, 1)))
8319 tem = op0, op0 = op1, op1 = tem;
8321 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8322 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8324 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8328 /* If that failed, we must use a conservative two-insn sequence.
8330 Use a move to copy one operand into the reload register. Prefer
8331 to reload a constant, MEM or pseudo since the move patterns can
8332 handle an arbitrary operand. If OP1 is not a constant, MEM or
8333 pseudo and OP1 is not a valid operand for an add instruction, then
8336 After reloading one of the operands into the reload register, add
8337 the reload register to the output register.
8339 If there is another way to do this for a specific machine, a
8340 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8343 code = (int) optab_handler (add_optab, GET_MODE (out))->insn_code;
8345 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8347 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8348 || (code != CODE_FOR_nothing
8349 && ! ((*insn_data[code].operand[2].predicate)
8350 (op1, insn_data[code].operand[2].mode))))
8351 tem = op0, op0 = op1, op1 = tem;
8353 gen_reload (out, op0, opnum, type);
8355 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8356 This fixes a problem on the 32K where the stack pointer cannot
8357 be used as an operand of an add insn. */
8359 if (rtx_equal_p (op0, op1))
8362 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8365 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8366 set_unique_reg_note (insn, REG_EQUIV, in);
8370 /* If that failed, copy the address register to the reload register.
8371 Then add the constant to the reload register. */
8373 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8374 gen_reload (out, op1, opnum, type);
8375 insn = emit_insn (gen_add2_insn (out, op0));
8376 set_unique_reg_note (insn, REG_EQUIV, in);
8379 #ifdef SECONDARY_MEMORY_NEEDED
8380 /* If we need a memory location to do the move, do it that way. */
8381 else if ((REG_P (in)
8382 || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
8383 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
8385 || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
8386 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
8387 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
8388 REGNO_REG_CLASS (reg_or_subregno (out)),
8391 /* Get the memory to use and rewrite both registers to its mode. */
8392 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8394 if (GET_MODE (loc) != GET_MODE (out))
8395 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
8397 if (GET_MODE (loc) != GET_MODE (in))
8398 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
8400 gen_reload (loc, in, opnum, type);
8401 gen_reload (out, loc, opnum, type);
8404 else if (REG_P (out) && UNARY_P (in))
8411 op1 = find_replacement (&XEXP (in, 0));
8412 if (op1 != XEXP (in, 0))
8413 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8415 /* First, try a plain SET. */
8416 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8420 /* If that failed, move the inner operand to the reload
8421 register, and try the same unop with the inner expression
8422 replaced with the reload register. */
8424 if (GET_MODE (op1) != GET_MODE (out))
8425 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8429 gen_reload (out_moded, op1, opnum, type);
8432 = gen_rtx_SET (VOIDmode, out,
8433 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8435 insn = emit_insn_if_valid_for_reload (insn);
8438 set_unique_reg_note (insn, REG_EQUIV, in);
8442 fatal_insn ("Failure trying to reload:", set);
8444 /* If IN is a simple operand, use gen_move_insn. */
8445 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8447 tem = emit_insn (gen_move_insn (out, in));
8448 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8449 mark_jump_label (in, tem, 0);
8452 #ifdef HAVE_reload_load_address
8453 else if (HAVE_reload_load_address)
8454 emit_insn (gen_reload_load_address (out, in));
8457 /* Otherwise, just write (set OUT IN) and hope for the best. */
8459 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8461 /* Return the first insn emitted.
8462 We can not just return get_last_insn, because there may have
8463 been multiple instructions emitted. Also note that gen_move_insn may
8464 emit more than one insn itself, so we can not assume that there is one
8465 insn emitted per emit_insn_before call. */
8467 return last ? NEXT_INSN (last) : get_insns ();
8470 /* Delete a previously made output-reload whose result we now believe
8471 is not needed. First we double-check.
8473 INSN is the insn now being processed.
8474 LAST_RELOAD_REG is the hard register number for which we want to delete
8475 the last output reload.
8476 J is the reload-number that originally used REG. The caller has made
8477 certain that reload J doesn't use REG any longer for input.
8478 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8481 delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg)
8483 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8484 rtx reg = spill_reg_stored_to[last_reload_reg];
8487 int n_inherited = 0;
8491 /* It is possible that this reload has been only used to set another reload
8492 we eliminated earlier and thus deleted this instruction too. */
8493 if (INSN_DELETED_P (output_reload_insn))
8496 /* Get the raw pseudo-register referred to. */
8498 while (GET_CODE (reg) == SUBREG)
8499 reg = SUBREG_REG (reg);
8500 substed = reg_equiv_memory_loc[REGNO (reg)];
8502 /* This is unsafe if the operand occurs more often in the current
8503 insn than it is inherited. */
8504 for (k = n_reloads - 1; k >= 0; k--)
8506 rtx reg2 = rld[k].in;
8509 if (MEM_P (reg2) || reload_override_in[k])
8510 reg2 = rld[k].in_reg;
8512 if (rld[k].out && ! rld[k].out_reg)
8513 reg2 = XEXP (rld[k].in_reg, 0);
8515 while (GET_CODE (reg2) == SUBREG)
8516 reg2 = SUBREG_REG (reg2);
8517 if (rtx_equal_p (reg2, reg))
8519 if (reload_inherited[k] || reload_override_in[k] || k == j)
8525 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8526 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8527 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8530 n_occurrences += count_occurrences (PATTERN (insn),
8531 eliminate_regs (substed, VOIDmode,
8533 for (i1 = reg_equiv_alt_mem_list[REGNO (reg)]; i1; i1 = XEXP (i1, 1))
8535 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8536 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8538 if (n_occurrences > n_inherited)
8541 /* If the pseudo-reg we are reloading is no longer referenced
8542 anywhere between the store into it and here,
8543 and we're within the same basic block, then the value can only
8544 pass through the reload reg and end up here.
8545 Otherwise, give up--return. */
8546 for (i1 = NEXT_INSN (output_reload_insn);
8547 i1 != insn; i1 = NEXT_INSN (i1))
8549 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8551 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8552 && reg_mentioned_p (reg, PATTERN (i1)))
8554 /* If this is USE in front of INSN, we only have to check that
8555 there are no more references than accounted for by inheritance. */
8556 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8558 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8559 i1 = NEXT_INSN (i1);
8561 if (n_occurrences <= n_inherited && i1 == insn)
8567 /* We will be deleting the insn. Remove the spill reg information. */
8568 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8570 spill_reg_store[last_reload_reg + k] = 0;
8571 spill_reg_stored_to[last_reload_reg + k] = 0;
8574 /* The caller has already checked that REG dies or is set in INSN.
8575 It has also checked that we are optimizing, and thus some
8576 inaccuracies in the debugging information are acceptable.
8577 So we could just delete output_reload_insn. But in some cases
8578 we can improve the debugging information without sacrificing
8579 optimization - maybe even improving the code: See if the pseudo
8580 reg has been completely replaced with reload regs. If so, delete
8581 the store insn and forget we had a stack slot for the pseudo. */
8582 if (rld[j].out != rld[j].in
8583 && REG_N_DEATHS (REGNO (reg)) == 1
8584 && REG_N_SETS (REGNO (reg)) == 1
8585 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8586 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8590 /* We know that it was used only between here and the beginning of
8591 the current basic block. (We also know that the last use before
8592 INSN was the output reload we are thinking of deleting, but never
8593 mind that.) Search that range; see if any ref remains. */
8594 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8596 rtx set = single_set (i2);
8598 /* Uses which just store in the pseudo don't count,
8599 since if they are the only uses, they are dead. */
8600 if (set != 0 && SET_DEST (set) == reg)
8605 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8606 && reg_mentioned_p (reg, PATTERN (i2)))
8608 /* Some other ref remains; just delete the output reload we
8610 delete_address_reloads (output_reload_insn, insn);
8611 delete_insn (output_reload_insn);
8616 /* Delete the now-dead stores into this pseudo. Note that this
8617 loop also takes care of deleting output_reload_insn. */
8618 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8620 rtx set = single_set (i2);
8622 if (set != 0 && SET_DEST (set) == reg)
8624 delete_address_reloads (i2, insn);
8632 /* For the debugging info, say the pseudo lives in this reload reg. */
8633 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8634 if (ira_conflicts_p)
8635 /* Inform IRA about the change. */
8636 ira_mark_allocation_change (REGNO (reg));
8637 alter_reg (REGNO (reg), -1, false);
8641 delete_address_reloads (output_reload_insn, insn);
8642 delete_insn (output_reload_insn);
8646 /* We are going to delete DEAD_INSN. Recursively delete loads of
8647 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8648 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8650 delete_address_reloads (rtx dead_insn, rtx current_insn)
8652 rtx set = single_set (dead_insn);
8653 rtx set2, dst, prev, next;
8656 rtx dst = SET_DEST (set);
8658 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8660 /* If we deleted the store from a reloaded post_{in,de}c expression,
8661 we can delete the matching adds. */
8662 prev = PREV_INSN (dead_insn);
8663 next = NEXT_INSN (dead_insn);
8664 if (! prev || ! next)
8666 set = single_set (next);
8667 set2 = single_set (prev);
8669 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8670 || !CONST_INT_P (XEXP (SET_SRC (set), 1))
8671 || !CONST_INT_P (XEXP (SET_SRC (set2), 1)))
8673 dst = SET_DEST (set);
8674 if (! rtx_equal_p (dst, SET_DEST (set2))
8675 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8676 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8677 || (INTVAL (XEXP (SET_SRC (set), 1))
8678 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8680 delete_related_insns (prev);
8681 delete_related_insns (next);
8684 /* Subfunction of delete_address_reloads: process registers found in X. */
8686 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8688 rtx prev, set, dst, i2;
8690 enum rtx_code code = GET_CODE (x);
8694 const char *fmt = GET_RTX_FORMAT (code);
8695 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8698 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8699 else if (fmt[i] == 'E')
8701 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8702 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8709 if (spill_reg_order[REGNO (x)] < 0)
8712 /* Scan backwards for the insn that sets x. This might be a way back due
8714 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8716 code = GET_CODE (prev);
8717 if (code == CODE_LABEL || code == JUMP_INSN)
8721 if (reg_set_p (x, PATTERN (prev)))
8723 if (reg_referenced_p (x, PATTERN (prev)))
8726 if (! prev || INSN_UID (prev) < reload_first_uid)
8728 /* Check that PREV only sets the reload register. */
8729 set = single_set (prev);
8732 dst = SET_DEST (set);
8734 || ! rtx_equal_p (dst, x))
8736 if (! reg_set_p (dst, PATTERN (dead_insn)))
8738 /* Check if DST was used in a later insn -
8739 it might have been inherited. */
8740 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8746 if (reg_referenced_p (dst, PATTERN (i2)))
8748 /* If there is a reference to the register in the current insn,
8749 it might be loaded in a non-inherited reload. If no other
8750 reload uses it, that means the register is set before
8752 if (i2 == current_insn)
8754 for (j = n_reloads - 1; j >= 0; j--)
8755 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8756 || reload_override_in[j] == dst)
8758 for (j = n_reloads - 1; j >= 0; j--)
8759 if (rld[j].in && rld[j].reg_rtx == dst)
8768 /* If DST is still live at CURRENT_INSN, check if it is used for
8769 any reload. Note that even if CURRENT_INSN sets DST, we still
8770 have to check the reloads. */
8771 if (i2 == current_insn)
8773 for (j = n_reloads - 1; j >= 0; j--)
8774 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8775 || reload_override_in[j] == dst)
8777 /* ??? We can't finish the loop here, because dst might be
8778 allocated to a pseudo in this block if no reload in this
8779 block needs any of the classes containing DST - see
8780 spill_hard_reg. There is no easy way to tell this, so we
8781 have to scan till the end of the basic block. */
8783 if (reg_set_p (dst, PATTERN (i2)))
8787 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8788 reg_reloaded_contents[REGNO (dst)] = -1;
8792 /* Output reload-insns to reload VALUE into RELOADREG.
8793 VALUE is an autoincrement or autodecrement RTX whose operand
8794 is a register or memory location;
8795 so reloading involves incrementing that location.
8796 IN is either identical to VALUE, or some cheaper place to reload from.
8798 INC_AMOUNT is the number to increment or decrement by (always positive).
8799 This cannot be deduced from VALUE.
8801 Return the instruction that stores into RELOADREG. */
8804 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8806 /* REG or MEM to be copied and incremented. */
8807 rtx incloc = find_replacement (&XEXP (value, 0));
8808 /* Nonzero if increment after copying. */
8809 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8810 || GET_CODE (value) == POST_MODIFY);
8816 rtx real_in = in == value ? incloc : in;
8818 /* No hard register is equivalent to this register after
8819 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8820 we could inc/dec that register as well (maybe even using it for
8821 the source), but I'm not sure it's worth worrying about. */
8823 reg_last_reload_reg[REGNO (incloc)] = 0;
8825 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8827 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8828 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8832 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8833 inc_amount = -inc_amount;
8835 inc = GEN_INT (inc_amount);
8838 /* If this is post-increment, first copy the location to the reload reg. */
8839 if (post && real_in != reloadreg)
8840 emit_insn (gen_move_insn (reloadreg, real_in));
8844 /* See if we can directly increment INCLOC. Use a method similar to
8845 that in gen_reload. */
8847 last = get_last_insn ();
8848 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8849 gen_rtx_PLUS (GET_MODE (incloc),
8852 code = recog_memoized (add_insn);
8855 extract_insn (add_insn);
8856 if (constrain_operands (1))
8858 /* If this is a pre-increment and we have incremented the value
8859 where it lives, copy the incremented value to RELOADREG to
8860 be used as an address. */
8863 emit_insn (gen_move_insn (reloadreg, incloc));
8868 delete_insns_since (last);
8871 /* If couldn't do the increment directly, must increment in RELOADREG.
8872 The way we do this depends on whether this is pre- or post-increment.
8873 For pre-increment, copy INCLOC to the reload register, increment it
8874 there, then save back. */
8878 if (in != reloadreg)
8879 emit_insn (gen_move_insn (reloadreg, real_in));
8880 emit_insn (gen_add2_insn (reloadreg, inc));
8881 store = emit_insn (gen_move_insn (incloc, reloadreg));
8886 Because this might be a jump insn or a compare, and because RELOADREG
8887 may not be available after the insn in an input reload, we must do
8888 the incrementation before the insn being reloaded for.
8890 We have already copied IN to RELOADREG. Increment the copy in
8891 RELOADREG, save that back, then decrement RELOADREG so it has
8892 the original value. */
8894 emit_insn (gen_add2_insn (reloadreg, inc));
8895 store = emit_insn (gen_move_insn (incloc, reloadreg));
8896 if (CONST_INT_P (inc))
8897 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
8899 emit_insn (gen_sub2_insn (reloadreg, inc));
8907 add_auto_inc_notes (rtx insn, rtx x)
8909 enum rtx_code code = GET_CODE (x);
8913 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8915 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
8919 /* Scan all the operand sub-expressions. */
8920 fmt = GET_RTX_FORMAT (code);
8921 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8924 add_auto_inc_notes (insn, XEXP (x, i));
8925 else if (fmt[i] == 'E')
8926 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8927 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8932 /* This is used by reload pass, that does emit some instructions after
8933 abnormal calls moving basic block end, but in fact it wants to emit
8934 them on the edge. Looks for abnormal call edges, find backward the
8935 proper call and fix the damage.
8937 Similar handle instructions throwing exceptions internally. */
8939 fixup_abnormal_edges (void)
8941 bool inserted = false;
8949 /* Look for cases we are interested in - calls or instructions causing
8951 FOR_EACH_EDGE (e, ei, bb->succs)
8953 if (e->flags & EDGE_ABNORMAL_CALL)
8955 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8956 == (EDGE_ABNORMAL | EDGE_EH))
8959 if (e && !CALL_P (BB_END (bb))
8960 && !can_throw_internal (BB_END (bb)))
8964 /* Get past the new insns generated. Allow notes, as the insns
8965 may be already deleted. */
8967 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8968 && !can_throw_internal (insn)
8969 && insn != BB_HEAD (bb))
8970 insn = PREV_INSN (insn);
8972 if (CALL_P (insn) || can_throw_internal (insn))
8976 stop = NEXT_INSN (BB_END (bb));
8978 insn = NEXT_INSN (insn);
8980 FOR_EACH_EDGE (e, ei, bb->succs)
8981 if (e->flags & EDGE_FALLTHRU)
8984 while (insn && insn != stop)
8986 next = NEXT_INSN (insn);
8991 /* Sometimes there's still the return value USE.
8992 If it's placed after a trapping call (i.e. that
8993 call is the last insn anyway), we have no fallthru
8994 edge. Simply delete this use and don't try to insert
8995 on the non-existent edge. */
8996 if (GET_CODE (PATTERN (insn)) != USE)
8998 /* We're not deleting it, we're moving it. */
8999 INSN_DELETED_P (insn) = 0;
9000 PREV_INSN (insn) = NULL_RTX;
9001 NEXT_INSN (insn) = NULL_RTX;
9003 insert_insn_on_edge (insn, e);
9007 else if (!BARRIER_P (insn))
9008 set_block_for_insn (insn, NULL);
9013 /* It may be that we don't find any such trapping insn. In this
9014 case we discovered quite late that the insn that had been
9015 marked as can_throw_internal in fact couldn't trap at all.
9016 So we should in fact delete the EH edges out of the block. */
9018 purge_dead_edges (bb);
9022 /* We've possibly turned single trapping insn into multiple ones. */
9023 if (flag_non_call_exceptions)
9026 blocks = sbitmap_alloc (last_basic_block);
9027 sbitmap_ones (blocks);
9028 find_many_sub_basic_blocks (blocks);
9029 sbitmap_free (blocks);
9033 commit_edge_insertions ();
9035 #ifdef ENABLE_CHECKING
9036 /* Verify that we didn't turn one trapping insn into many, and that
9037 we found and corrected all of the problems wrt fixups on the
9039 verify_flow_info ();