1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
106 This is used when the address is not valid as a memory address
107 (because its displacement is too big for the machine.) */
108 rtx *reg_equiv_address;
110 /* Element N is the memory slot to which pseudo reg N is equivalent,
111 or zero if pseudo reg N is not equivalent to a memory slot. */
114 /* Widest width in which each pseudo reg is referred to (via subreg). */
115 static unsigned int *reg_max_ref_width;
117 /* Element N is the list of insns that initialized reg N from its equivalent
118 constant or memory slot. */
119 static rtx *reg_equiv_init;
121 /* Vector to remember old contents of reg_renumber before spilling. */
122 static short *reg_old_renumber;
124 /* During reload_as_needed, element N contains the last pseudo regno reloaded
125 into hard register N. If that pseudo reg occupied more than one register,
126 reg_reloaded_contents points to that pseudo for each spill register in
127 use; all of these must remain set for an inheritance to occur. */
128 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
130 /* During reload_as_needed, element N contains the insn for which
131 hard register N was last used. Its contents are significant only
132 when reg_reloaded_valid is set for this register. */
133 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
135 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
136 static HARD_REG_SET reg_reloaded_valid;
137 /* Indicate if the register was dead at the end of the reload.
138 This is only valid if reg_reloaded_contents is set and valid. */
139 static HARD_REG_SET reg_reloaded_dead;
141 /* Indicate whether the register's current value is one that is not
142 safe to retain across a call, even for registers that are normally
144 static HARD_REG_SET reg_reloaded_call_part_clobbered;
146 /* Number of spill-regs so far; number of valid elements of spill_regs. */
149 /* In parallel with spill_regs, contains REG rtx's for those regs.
150 Holds the last rtx used for any given reg, or 0 if it has never
151 been used for spilling yet. This rtx is reused, provided it has
153 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
155 /* In parallel with spill_regs, contains nonzero for a spill reg
156 that was stored after the last time it was used.
157 The precise value is the insn generated to do the store. */
158 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
160 /* This is the register that was stored with spill_reg_store. This is a
161 copy of reload_out / reload_out_reg when the value was stored; if
162 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
163 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
165 /* This table is the inverse mapping of spill_regs:
166 indexed by hard reg number,
167 it contains the position of that reg in spill_regs,
168 or -1 for something that is not in spill_regs.
170 ?!? This is no longer accurate. */
171 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
173 /* This reg set indicates registers that can't be used as spill registers for
174 the currently processed insn. These are the hard registers which are live
175 during the insn, but not allocated to pseudos, as well as fixed
177 static HARD_REG_SET bad_spill_regs;
179 /* These are the hard registers that can't be used as spill register for any
180 insn. This includes registers used for user variables and registers that
181 we can't eliminate. A register that appears in this set also can't be used
182 to retry register allocation. */
183 static HARD_REG_SET bad_spill_regs_global;
185 /* Describes order of use of registers for reloading
186 of spilled pseudo-registers. `n_spills' is the number of
187 elements that are actually valid; new ones are added at the end.
189 Both spill_regs and spill_reg_order are used on two occasions:
190 once during find_reload_regs, where they keep track of the spill registers
191 for a single insn, but also during reload_as_needed where they show all
192 the registers ever used by reload. For the latter case, the information
193 is calculated during finish_spills. */
194 static short spill_regs[FIRST_PSEUDO_REGISTER];
196 /* This vector of reg sets indicates, for each pseudo, which hard registers
197 may not be used for retrying global allocation because the register was
198 formerly spilled from one of them. If we allowed reallocating a pseudo to
199 a register that it was already allocated to, reload might not
201 static HARD_REG_SET *pseudo_previous_regs;
203 /* This vector of reg sets indicates, for each pseudo, which hard
204 registers may not be used for retrying global allocation because they
205 are used as spill registers during one of the insns in which the
207 static HARD_REG_SET *pseudo_forbidden_regs;
209 /* All hard regs that have been used as spill registers for any insn are
210 marked in this set. */
211 static HARD_REG_SET used_spill_regs;
213 /* Index of last register assigned as a spill register. We allocate in
214 a round-robin fashion. */
215 static int last_spill_reg;
217 /* Nonzero if indirect addressing is supported on the machine; this means
218 that spilling (REG n) does not require reloading it into a register in
219 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
220 value indicates the level of indirect addressing supported, e.g., two
221 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
223 static char spill_indirect_levels;
225 /* Nonzero if indirect addressing is supported when the innermost MEM is
226 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
227 which these are valid is the same as spill_indirect_levels, above. */
228 char indirect_symref_ok;
230 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
231 char double_reg_address_ok;
233 /* Record the stack slot for each spilled hard register. */
234 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
236 /* Width allocated so far for that stack slot. */
237 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
239 /* Record which pseudos needed to be spilled. */
240 static regset_head spilled_pseudos;
242 /* Used for communication between order_regs_for_reload and count_pseudo.
243 Used to avoid counting one pseudo twice. */
244 static regset_head pseudos_counted;
246 /* First uid used by insns created by reload in this function.
247 Used in find_equiv_reg. */
248 int reload_first_uid;
250 /* Flag set by local-alloc or global-alloc if anything is live in
251 a call-clobbered reg across calls. */
252 int caller_save_needed;
254 /* Set to 1 while reload_as_needed is operating.
255 Required by some machines to handle any generated moves differently. */
256 int reload_in_progress = 0;
258 /* These arrays record the insn_code of insns that may be needed to
259 perform input and output reloads of special objects. They provide a
260 place to pass a scratch register. */
261 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
262 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
264 /* This obstack is used for allocation of rtl during register elimination.
265 The allocated storage can be freed once find_reloads has processed the
267 struct obstack reload_obstack;
269 /* Points to the beginning of the reload_obstack. All insn_chain structures
270 are allocated first. */
271 char *reload_startobj;
273 /* The point after all insn_chain structures. Used to quickly deallocate
274 memory allocated in copy_reloads during calculate_needs_all_insns. */
275 char *reload_firstobj;
277 /* This points before all local rtl generated by register elimination.
278 Used to quickly free all memory after processing one insn. */
279 static char *reload_insn_firstobj;
281 /* List of insn_chain instructions, one for every insn that reload needs to
283 struct insn_chain *reload_insn_chain;
285 /* List of all insns needing reloads. */
286 static struct insn_chain *insns_need_reload;
288 /* This structure is used to record information about register eliminations.
289 Each array entry describes one possible way of eliminating a register
290 in favor of another. If there is more than one way of eliminating a
291 particular register, the most preferred should be specified first. */
295 int from; /* Register number to be eliminated. */
296 int to; /* Register number used as replacement. */
297 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
298 int can_eliminate; /* Nonzero if this elimination can be done. */
299 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
300 insns made by reload. */
301 HOST_WIDE_INT offset; /* Current offset between the two regs. */
302 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
303 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
304 rtx from_rtx; /* REG rtx for the register to be eliminated.
305 We cannot simply compare the number since
306 we might then spuriously replace a hard
307 register corresponding to a pseudo
308 assigned to the reg to be eliminated. */
309 rtx to_rtx; /* REG rtx for the replacement. */
312 static struct elim_table *reg_eliminate = 0;
314 /* This is an intermediate structure to initialize the table. It has
315 exactly the members provided by ELIMINABLE_REGS. */
316 static const struct elim_table_1
320 } reg_eliminate_1[] =
322 /* If a set of eliminable registers was specified, define the table from it.
323 Otherwise, default to the normal case of the frame pointer being
324 replaced by the stack pointer. */
326 #ifdef ELIMINABLE_REGS
329 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
332 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
334 /* Record the number of pending eliminations that have an offset not equal
335 to their initial offset. If nonzero, we use a new copy of each
336 replacement result in any insns encountered. */
337 int num_not_at_initial_offset;
339 /* Count the number of registers that we may be able to eliminate. */
340 static int num_eliminable;
341 /* And the number of registers that are equivalent to a constant that
342 can be eliminated to frame_pointer / arg_pointer + constant. */
343 static int num_eliminable_invariants;
345 /* For each label, we record the offset of each elimination. If we reach
346 a label by more than one path and an offset differs, we cannot do the
347 elimination. This information is indexed by the difference of the
348 number of the label and the first label number. We can't offset the
349 pointer itself as this can cause problems on machines with segmented
350 memory. The first table is an array of flags that records whether we
351 have yet encountered a label and the second table is an array of arrays,
352 one entry in the latter array for each elimination. */
354 static int first_label_num;
355 static char *offsets_known_at;
356 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
358 /* Number of labels in the current function. */
360 static int num_labels;
362 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
363 static void maybe_fix_stack_asms (void);
364 static void copy_reloads (struct insn_chain *);
365 static void calculate_needs_all_insns (int);
366 static int find_reg (struct insn_chain *, int);
367 static void find_reload_regs (struct insn_chain *);
368 static void select_reload_regs (void);
369 static void delete_caller_save_insns (void);
371 static void spill_failure (rtx, enum reg_class);
372 static void count_spilled_pseudo (int, int, int);
373 static void delete_dead_insn (rtx);
374 static void alter_reg (int, int);
375 static void set_label_offsets (rtx, rtx, int);
376 static void check_eliminable_occurrences (rtx);
377 static void elimination_effects (rtx, enum machine_mode);
378 static int eliminate_regs_in_insn (rtx, int);
379 static void update_eliminable_offsets (void);
380 static void mark_not_eliminable (rtx, rtx, void *);
381 static void set_initial_elim_offsets (void);
382 static void verify_initial_elim_offsets (void);
383 static void set_initial_label_offsets (void);
384 static void set_offsets_for_label (rtx);
385 static void init_elim_table (void);
386 static void update_eliminables (HARD_REG_SET *);
387 static void spill_hard_reg (unsigned int, int);
388 static int finish_spills (int);
389 static void ior_hard_reg_set (HARD_REG_SET *, HARD_REG_SET *);
390 static void scan_paradoxical_subregs (rtx);
391 static void count_pseudo (int);
392 static void order_regs_for_reload (struct insn_chain *);
393 static void reload_as_needed (int);
394 static void forget_old_reloads_1 (rtx, rtx, void *);
395 static int reload_reg_class_lower (const void *, const void *);
396 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
398 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
400 static int reload_reg_free_p (unsigned int, int, enum reload_type);
401 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
403 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
405 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
406 static int allocate_reload_reg (struct insn_chain *, int, int);
407 static int conflicts_with_override (rtx);
408 static void failed_reload (rtx, int);
409 static int set_reload_reg (int, int);
410 static void choose_reload_regs_init (struct insn_chain *, rtx *);
411 static void choose_reload_regs (struct insn_chain *);
412 static void merge_assigned_reloads (rtx);
413 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
415 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
417 static void do_input_reload (struct insn_chain *, struct reload *, int);
418 static void do_output_reload (struct insn_chain *, struct reload *, int);
419 static void emit_reload_insns (struct insn_chain *);
420 static void delete_output_reload (rtx, int, int);
421 static void delete_address_reloads (rtx, rtx);
422 static void delete_address_reloads_1 (rtx, rtx, rtx);
423 static rtx inc_for_reload (rtx, rtx, rtx, int);
425 static void add_auto_inc_notes (rtx, rtx);
427 static void copy_eh_notes (rtx, rtx);
429 /* Initialize the reload pass once per compilation. */
436 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
437 Set spill_indirect_levels to the number of levels such addressing is
438 permitted, zero if it is not permitted at all. */
441 = gen_rtx_MEM (Pmode,
444 LAST_VIRTUAL_REGISTER + 1),
446 spill_indirect_levels = 0;
448 while (memory_address_p (QImode, tem))
450 spill_indirect_levels++;
451 tem = gen_rtx_MEM (Pmode, tem);
454 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
456 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
457 indirect_symref_ok = memory_address_p (QImode, tem);
459 /* See if reg+reg is a valid (and offsettable) address. */
461 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
463 tem = gen_rtx_PLUS (Pmode,
464 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
465 gen_rtx_REG (Pmode, i));
467 /* This way, we make sure that reg+reg is an offsettable address. */
468 tem = plus_constant (tem, 4);
470 if (memory_address_p (QImode, tem))
472 double_reg_address_ok = 1;
477 /* Initialize obstack for our rtl allocation. */
478 gcc_obstack_init (&reload_obstack);
479 reload_startobj = obstack_alloc (&reload_obstack, 0);
481 INIT_REG_SET (&spilled_pseudos);
482 INIT_REG_SET (&pseudos_counted);
485 /* List of insn chains that are currently unused. */
486 static struct insn_chain *unused_insn_chains = 0;
488 /* Allocate an empty insn_chain structure. */
490 new_insn_chain (void)
492 struct insn_chain *c;
494 if (unused_insn_chains == 0)
496 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
497 INIT_REG_SET (&c->live_throughout);
498 INIT_REG_SET (&c->dead_or_set);
502 c = unused_insn_chains;
503 unused_insn_chains = c->next;
505 c->is_caller_save_insn = 0;
506 c->need_operand_change = 0;
512 /* Small utility function to set all regs in hard reg set TO which are
513 allocated to pseudos in regset FROM. */
516 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
520 EXECUTE_IF_SET_IN_REG_SET
521 (from, FIRST_PSEUDO_REGISTER, regno,
523 int r = reg_renumber[regno];
528 /* reload_combine uses the information from
529 BASIC_BLOCK->global_live_at_start, which might still
530 contain registers that have not actually been allocated
531 since they have an equivalence. */
532 if (! reload_completed)
537 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
539 SET_HARD_REG_BIT (*to, r + nregs);
544 /* Replace all pseudos found in LOC with their corresponding
548 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
561 unsigned int regno = REGNO (x);
563 if (regno < FIRST_PSEUDO_REGISTER)
566 x = eliminate_regs (x, mem_mode, usage);
570 replace_pseudos_in (loc, mem_mode, usage);
574 if (reg_equiv_constant[regno])
575 *loc = reg_equiv_constant[regno];
576 else if (reg_equiv_mem[regno])
577 *loc = reg_equiv_mem[regno];
578 else if (reg_equiv_address[regno])
579 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
580 else if (GET_CODE (regno_reg_rtx[regno]) != REG
581 || REGNO (regno_reg_rtx[regno]) != regno)
582 *loc = regno_reg_rtx[regno];
588 else if (code == MEM)
590 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
594 /* Process each of our operands recursively. */
595 fmt = GET_RTX_FORMAT (code);
596 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
598 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
599 else if (*fmt == 'E')
600 for (j = 0; j < XVECLEN (x, i); j++)
601 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
605 /* Global variables used by reload and its subroutines. */
607 /* Set during calculate_needs if an insn needs register elimination. */
608 static int something_needs_elimination;
609 /* Set during calculate_needs if an insn needs an operand changed. */
610 int something_needs_operands_changed;
612 /* Nonzero means we couldn't get enough spill regs. */
615 /* Main entry point for the reload pass.
617 FIRST is the first insn of the function being compiled.
619 GLOBAL nonzero means we were called from global_alloc
620 and should attempt to reallocate any pseudoregs that we
621 displace from hard regs we will use for reloads.
622 If GLOBAL is zero, we do not have enough information to do that,
623 so any pseudo reg that is spilled must go to the stack.
625 Return value is nonzero if reload failed
626 and we must not do any more for this function. */
629 reload (rtx first, int global)
633 struct elim_table *ep;
636 /* Make sure even insns with volatile mem refs are recognizable. */
641 reload_firstobj = obstack_alloc (&reload_obstack, 0);
643 /* Make sure that the last insn in the chain
644 is not something that needs reloading. */
645 emit_note (NOTE_INSN_DELETED);
647 /* Enable find_equiv_reg to distinguish insns made by reload. */
648 reload_first_uid = get_max_uid ();
650 #ifdef SECONDARY_MEMORY_NEEDED
651 /* Initialize the secondary memory table. */
652 clear_secondary_mem ();
655 /* We don't have a stack slot for any spill reg yet. */
656 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
657 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
659 /* Initialize the save area information for caller-save, in case some
663 /* Compute which hard registers are now in use
664 as homes for pseudo registers.
665 This is done here rather than (eg) in global_alloc
666 because this point is reached even if not optimizing. */
667 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
670 /* A function that receives a nonlocal goto must save all call-saved
672 if (current_function_has_nonlocal_label)
673 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
674 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
675 regs_ever_live[i] = 1;
677 #ifdef NON_SAVING_SETJMP
678 /* A function that calls setjmp should save and restore all the
679 call-saved registers on a system where longjmp clobbers them. */
680 if (NON_SAVING_SETJMP && current_function_calls_setjmp)
682 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
683 if (! call_used_regs[i])
684 regs_ever_live[i] = 1;
688 /* Find all the pseudo registers that didn't get hard regs
689 but do have known equivalent constants or memory slots.
690 These include parameters (known equivalent to parameter slots)
691 and cse'd or loop-moved constant memory addresses.
693 Record constant equivalents in reg_equiv_constant
694 so they will be substituted by find_reloads.
695 Record memory equivalents in reg_mem_equiv so they can
696 be substituted eventually by altering the REG-rtx's. */
698 reg_equiv_constant = xcalloc (max_regno, sizeof (rtx));
699 reg_equiv_mem = xcalloc (max_regno, sizeof (rtx));
700 reg_equiv_init = xcalloc (max_regno, sizeof (rtx));
701 reg_equiv_address = xcalloc (max_regno, sizeof (rtx));
702 reg_max_ref_width = xcalloc (max_regno, sizeof (int));
703 reg_old_renumber = xcalloc (max_regno, sizeof (short));
704 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
705 pseudo_forbidden_regs = xmalloc (max_regno * sizeof (HARD_REG_SET));
706 pseudo_previous_regs = xcalloc (max_regno, sizeof (HARD_REG_SET));
708 CLEAR_HARD_REG_SET (bad_spill_regs_global);
710 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
711 Also find all paradoxical subregs and find largest such for each pseudo.
712 On machines with small register classes, record hard registers that
713 are used for user variables. These can never be used for spills. */
715 num_eliminable_invariants = 0;
716 for (insn = first; insn; insn = NEXT_INSN (insn))
718 rtx set = single_set (insn);
720 /* We may introduce USEs that we want to remove at the end, so
721 we'll mark them with QImode. Make sure there are no
722 previously-marked insns left by say regmove. */
723 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
724 && GET_MODE (insn) != VOIDmode)
725 PUT_MODE (insn, VOIDmode);
727 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
729 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
731 #ifdef LEGITIMATE_PIC_OPERAND_P
732 && (! function_invariant_p (XEXP (note, 0))
734 /* A function invariant is often CONSTANT_P but may
735 include a register. We promise to only pass
736 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
737 || (CONSTANT_P (XEXP (note, 0))
738 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))))
742 rtx x = XEXP (note, 0);
743 i = REGNO (SET_DEST (set));
744 if (i > LAST_VIRTUAL_REGISTER)
746 /* It can happen that a REG_EQUIV note contains a MEM
747 that is not a legitimate memory operand. As later
748 stages of reload assume that all addresses found
749 in the reg_equiv_* arrays were originally legitimate,
750 we ignore such REG_EQUIV notes. */
751 if (memory_operand (x, VOIDmode))
753 /* Always unshare the equivalence, so we can
754 substitute into this insn without touching the
756 reg_equiv_memory_loc[i] = copy_rtx (x);
758 else if (function_invariant_p (x))
760 if (GET_CODE (x) == PLUS)
762 /* This is PLUS of frame pointer and a constant,
763 and might be shared. Unshare it. */
764 reg_equiv_constant[i] = copy_rtx (x);
765 num_eliminable_invariants++;
767 else if (x == frame_pointer_rtx
768 || x == arg_pointer_rtx)
770 reg_equiv_constant[i] = x;
771 num_eliminable_invariants++;
773 else if (LEGITIMATE_CONSTANT_P (x))
774 reg_equiv_constant[i] = x;
777 reg_equiv_memory_loc[i]
778 = force_const_mem (GET_MODE (SET_DEST (set)), x);
779 if (!reg_equiv_memory_loc[i])
786 /* If this register is being made equivalent to a MEM
787 and the MEM is not SET_SRC, the equivalencing insn
788 is one with the MEM as a SET_DEST and it occurs later.
789 So don't mark this insn now. */
790 if (GET_CODE (x) != MEM
791 || rtx_equal_p (SET_SRC (set), x))
793 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
798 /* If this insn is setting a MEM from a register equivalent to it,
799 this is the equivalencing insn. */
800 else if (set && GET_CODE (SET_DEST (set)) == MEM
801 && GET_CODE (SET_SRC (set)) == REG
802 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
803 && rtx_equal_p (SET_DEST (set),
804 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
805 reg_equiv_init[REGNO (SET_SRC (set))]
806 = gen_rtx_INSN_LIST (VOIDmode, insn,
807 reg_equiv_init[REGNO (SET_SRC (set))]);
810 scan_paradoxical_subregs (PATTERN (insn));
815 first_label_num = get_first_label_num ();
816 num_labels = max_label_num () - first_label_num;
818 /* Allocate the tables used to store offset information at labels. */
819 /* We used to use alloca here, but the size of what it would try to
820 allocate would occasionally cause it to exceed the stack limit and
821 cause a core dump. */
822 offsets_known_at = xmalloc (num_labels);
823 offsets_at = xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
825 /* Alter each pseudo-reg rtx to contain its hard reg number.
826 Assign stack slots to the pseudos that lack hard regs or equivalents.
827 Do not touch virtual registers. */
829 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
832 /* If we have some registers we think can be eliminated, scan all insns to
833 see if there is an insn that sets one of these registers to something
834 other than itself plus a constant. If so, the register cannot be
835 eliminated. Doing this scan here eliminates an extra pass through the
836 main reload loop in the most common case where register elimination
838 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
839 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
840 || GET_CODE (insn) == CALL_INSN)
841 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
843 maybe_fix_stack_asms ();
845 insns_need_reload = 0;
846 something_needs_elimination = 0;
848 /* Initialize to -1, which means take the first spill register. */
851 /* Spill any hard regs that we know we can't eliminate. */
852 CLEAR_HARD_REG_SET (used_spill_regs);
853 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
854 if (! ep->can_eliminate)
855 spill_hard_reg (ep->from, 1);
857 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
858 if (frame_pointer_needed)
859 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
861 finish_spills (global);
863 /* From now on, we may need to generate moves differently. We may also
864 allow modifications of insns which cause them to not be recognized.
865 Any such modifications will be cleaned up during reload itself. */
866 reload_in_progress = 1;
868 /* This loop scans the entire function each go-round
869 and repeats until one repetition spills no additional hard regs. */
872 int something_changed;
875 HOST_WIDE_INT starting_frame_size;
877 /* Round size of stack frame to stack_alignment_needed. This must be done
878 here because the stack size may be a part of the offset computation
879 for register elimination, and there might have been new stack slots
880 created in the last iteration of this loop. */
881 if (cfun->stack_alignment_needed)
882 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
884 starting_frame_size = get_frame_size ();
886 set_initial_elim_offsets ();
887 set_initial_label_offsets ();
889 /* For each pseudo register that has an equivalent location defined,
890 try to eliminate any eliminable registers (such as the frame pointer)
891 assuming initial offsets for the replacement register, which
894 If the resulting location is directly addressable, substitute
895 the MEM we just got directly for the old REG.
897 If it is not addressable but is a constant or the sum of a hard reg
898 and constant, it is probably not addressable because the constant is
899 out of range, in that case record the address; we will generate
900 hairy code to compute the address in a register each time it is
901 needed. Similarly if it is a hard register, but one that is not
902 valid as an address register.
904 If the location is not addressable, but does not have one of the
905 above forms, assign a stack slot. We have to do this to avoid the
906 potential of producing lots of reloads if, e.g., a location involves
907 a pseudo that didn't get a hard register and has an equivalent memory
908 location that also involves a pseudo that didn't get a hard register.
910 Perhaps at some point we will improve reload_when_needed handling
911 so this problem goes away. But that's very hairy. */
913 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
914 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
916 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
918 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
920 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
921 else if (CONSTANT_P (XEXP (x, 0))
922 || (GET_CODE (XEXP (x, 0)) == REG
923 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
924 || (GET_CODE (XEXP (x, 0)) == PLUS
925 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
926 && (REGNO (XEXP (XEXP (x, 0), 0))
927 < FIRST_PSEUDO_REGISTER)
928 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
929 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
932 /* Make a new stack slot. Then indicate that something
933 changed so we go back and recompute offsets for
934 eliminable registers because the allocation of memory
935 below might change some offset. reg_equiv_{mem,address}
936 will be set up for this pseudo on the next pass around
938 reg_equiv_memory_loc[i] = 0;
939 reg_equiv_init[i] = 0;
944 if (caller_save_needed)
947 /* If we allocated another stack slot, redo elimination bookkeeping. */
948 if (starting_frame_size != get_frame_size ())
951 if (caller_save_needed)
953 save_call_clobbered_regs ();
954 /* That might have allocated new insn_chain structures. */
955 reload_firstobj = obstack_alloc (&reload_obstack, 0);
958 calculate_needs_all_insns (global);
960 CLEAR_REG_SET (&spilled_pseudos);
963 something_changed = 0;
965 /* If we allocated any new memory locations, make another pass
966 since it might have changed elimination offsets. */
967 if (starting_frame_size != get_frame_size ())
968 something_changed = 1;
971 HARD_REG_SET to_spill;
972 CLEAR_HARD_REG_SET (to_spill);
973 update_eliminables (&to_spill);
974 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
975 if (TEST_HARD_REG_BIT (to_spill, i))
977 spill_hard_reg (i, 1);
980 /* Regardless of the state of spills, if we previously had
981 a register that we thought we could eliminate, but now can
982 not eliminate, we must run another pass.
984 Consider pseudos which have an entry in reg_equiv_* which
985 reference an eliminable register. We must make another pass
986 to update reg_equiv_* so that we do not substitute in the
987 old value from when we thought the elimination could be
989 something_changed = 1;
993 select_reload_regs ();
997 if (insns_need_reload != 0 || did_spill)
998 something_changed |= finish_spills (global);
1000 if (! something_changed)
1003 if (caller_save_needed)
1004 delete_caller_save_insns ();
1006 obstack_free (&reload_obstack, reload_firstobj);
1009 /* If global-alloc was run, notify it of any register eliminations we have
1012 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1013 if (ep->can_eliminate)
1014 mark_elimination (ep->from, ep->to);
1016 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1017 If that insn didn't set the register (i.e., it copied the register to
1018 memory), just delete that insn instead of the equivalencing insn plus
1019 anything now dead. If we call delete_dead_insn on that insn, we may
1020 delete the insn that actually sets the register if the register dies
1021 there and that is incorrect. */
1023 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1025 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1028 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1030 rtx equiv_insn = XEXP (list, 0);
1032 /* If we already deleted the insn or if it may trap, we can't
1033 delete it. The latter case shouldn't happen, but can
1034 if an insn has a variable address, gets a REG_EH_REGION
1035 note added to it, and then gets converted into an load
1036 from a constant address. */
1037 if (GET_CODE (equiv_insn) == NOTE
1038 || can_throw_internal (equiv_insn))
1040 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1041 delete_dead_insn (equiv_insn);
1044 PUT_CODE (equiv_insn, NOTE);
1045 NOTE_SOURCE_FILE (equiv_insn) = 0;
1046 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1052 /* Use the reload registers where necessary
1053 by generating move instructions to move the must-be-register
1054 values into or out of the reload registers. */
1056 if (insns_need_reload != 0 || something_needs_elimination
1057 || something_needs_operands_changed)
1059 HOST_WIDE_INT old_frame_size = get_frame_size ();
1061 reload_as_needed (global);
1063 if (old_frame_size != get_frame_size ())
1067 verify_initial_elim_offsets ();
1070 /* If we were able to eliminate the frame pointer, show that it is no
1071 longer live at the start of any basic block. If it ls live by
1072 virtue of being in a pseudo, that pseudo will be marked live
1073 and hence the frame pointer will be known to be live via that
1076 if (! frame_pointer_needed)
1078 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1079 HARD_FRAME_POINTER_REGNUM);
1081 /* Come here (with failure set nonzero) if we can't get enough spill regs
1082 and we decide not to abort about it. */
1085 CLEAR_REG_SET (&spilled_pseudos);
1086 reload_in_progress = 0;
1088 /* Now eliminate all pseudo regs by modifying them into
1089 their equivalent memory references.
1090 The REG-rtx's for the pseudos are modified in place,
1091 so all insns that used to refer to them now refer to memory.
1093 For a reg that has a reg_equiv_address, all those insns
1094 were changed by reloading so that no insns refer to it any longer;
1095 but the DECL_RTL of a variable decl may refer to it,
1096 and if so this causes the debugging info to mention the variable. */
1098 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1102 if (reg_equiv_mem[i])
1103 addr = XEXP (reg_equiv_mem[i], 0);
1105 if (reg_equiv_address[i])
1106 addr = reg_equiv_address[i];
1110 if (reg_renumber[i] < 0)
1112 rtx reg = regno_reg_rtx[i];
1114 REG_USERVAR_P (reg) = 0;
1115 PUT_CODE (reg, MEM);
1116 XEXP (reg, 0) = addr;
1117 if (reg_equiv_memory_loc[i])
1118 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1121 RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg)
1122 = MEM_SCALAR_P (reg) = 0;
1123 MEM_ATTRS (reg) = 0;
1126 else if (reg_equiv_mem[i])
1127 XEXP (reg_equiv_mem[i], 0) = addr;
1131 /* We must set reload_completed now since the cleanup_subreg_operands call
1132 below will re-recognize each insn and reload may have generated insns
1133 which are only valid during and after reload. */
1134 reload_completed = 1;
1136 /* Make a pass over all the insns and delete all USEs which we inserted
1137 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1138 notes. Delete all CLOBBER insns, except those that refer to the return
1139 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1140 from misarranging variable-array code, and simplify (subreg (reg))
1141 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1142 are no longer useful or accurate. Strip and regenerate REG_INC notes
1143 that may have been moved around. */
1145 for (insn = first; insn; insn = NEXT_INSN (insn))
1150 if (GET_CODE (insn) == CALL_INSN)
1151 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1152 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1154 if ((GET_CODE (PATTERN (insn)) == USE
1155 /* We mark with QImode USEs introduced by reload itself. */
1156 && (GET_MODE (insn) == QImode
1157 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1158 || (GET_CODE (PATTERN (insn)) == CLOBBER
1159 && (GET_CODE (XEXP (PATTERN (insn), 0)) != MEM
1160 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1161 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1162 && XEXP (XEXP (PATTERN (insn), 0), 0)
1163 != stack_pointer_rtx))
1164 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1165 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1171 /* Some CLOBBERs may survive until here and still reference unassigned
1172 pseudos with const equivalent, which may in turn cause ICE in later
1173 passes if the reference remains in place. */
1174 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1175 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1176 VOIDmode, PATTERN (insn));
1178 pnote = ®_NOTES (insn);
1181 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1182 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1183 || REG_NOTE_KIND (*pnote) == REG_INC
1184 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1185 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1186 *pnote = XEXP (*pnote, 1);
1188 pnote = &XEXP (*pnote, 1);
1192 add_auto_inc_notes (insn, PATTERN (insn));
1195 /* And simplify (subreg (reg)) if it appears as an operand. */
1196 cleanup_subreg_operands (insn);
1199 /* If we are doing stack checking, give a warning if this function's
1200 frame size is larger than we expect. */
1201 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1203 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1204 static int verbose_warned = 0;
1206 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1207 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1208 size += UNITS_PER_WORD;
1210 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1212 warning ("frame size too large for reliable stack checking");
1213 if (! verbose_warned)
1215 warning ("try reducing the number of local variables");
1221 /* Indicate that we no longer have known memory locations or constants. */
1222 if (reg_equiv_constant)
1223 free (reg_equiv_constant);
1224 reg_equiv_constant = 0;
1225 if (reg_equiv_memory_loc)
1226 free (reg_equiv_memory_loc);
1227 reg_equiv_memory_loc = 0;
1229 if (offsets_known_at)
1230 free (offsets_known_at);
1234 free (reg_equiv_mem);
1235 free (reg_equiv_init);
1236 free (reg_equiv_address);
1237 free (reg_max_ref_width);
1238 free (reg_old_renumber);
1239 free (pseudo_previous_regs);
1240 free (pseudo_forbidden_regs);
1242 CLEAR_HARD_REG_SET (used_spill_regs);
1243 for (i = 0; i < n_spills; i++)
1244 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1246 /* Free all the insn_chain structures at once. */
1247 obstack_free (&reload_obstack, reload_startobj);
1248 unused_insn_chains = 0;
1249 fixup_abnormal_edges ();
1251 /* Replacing pseudos with their memory equivalents might have
1252 created shared rtx. Subsequent passes would get confused
1253 by this, so unshare everything here. */
1254 unshare_all_rtl_again (first);
1256 #ifdef STACK_BOUNDARY
1257 /* init_emit has set the alignment of the hard frame pointer
1258 to STACK_BOUNDARY. It is very likely no longer valid if
1259 the hard frame pointer was used for register allocation. */
1260 if (!frame_pointer_needed)
1261 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1267 /* Yet another special case. Unfortunately, reg-stack forces people to
1268 write incorrect clobbers in asm statements. These clobbers must not
1269 cause the register to appear in bad_spill_regs, otherwise we'll call
1270 fatal_insn later. We clear the corresponding regnos in the live
1271 register sets to avoid this.
1272 The whole thing is rather sick, I'm afraid. */
1275 maybe_fix_stack_asms (void)
1278 const char *constraints[MAX_RECOG_OPERANDS];
1279 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1280 struct insn_chain *chain;
1282 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1285 HARD_REG_SET clobbered, allowed;
1288 if (! INSN_P (chain->insn)
1289 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1291 pat = PATTERN (chain->insn);
1292 if (GET_CODE (pat) != PARALLEL)
1295 CLEAR_HARD_REG_SET (clobbered);
1296 CLEAR_HARD_REG_SET (allowed);
1298 /* First, make a mask of all stack regs that are clobbered. */
1299 for (i = 0; i < XVECLEN (pat, 0); i++)
1301 rtx t = XVECEXP (pat, 0, i);
1302 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1303 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1306 /* Get the operand values and constraints out of the insn. */
1307 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1308 constraints, operand_mode);
1310 /* For every operand, see what registers are allowed. */
1311 for (i = 0; i < noperands; i++)
1313 const char *p = constraints[i];
1314 /* For every alternative, we compute the class of registers allowed
1315 for reloading in CLS, and merge its contents into the reg set
1317 int cls = (int) NO_REGS;
1323 if (c == '\0' || c == ',' || c == '#')
1325 /* End of one alternative - mark the regs in the current
1326 class, and reset the class. */
1327 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1333 } while (c != '\0' && c != ',');
1341 case '=': case '+': case '*': case '%': case '?': case '!':
1342 case '0': case '1': case '2': case '3': case '4': case 'm':
1343 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1344 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1345 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1350 cls = (int) reg_class_subunion[cls]
1351 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1356 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1360 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1361 cls = (int) reg_class_subunion[cls]
1362 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1364 cls = (int) reg_class_subunion[cls]
1365 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1367 p += CONSTRAINT_LEN (c, p);
1370 /* Those of the registers which are clobbered, but allowed by the
1371 constraints, must be usable as reload registers. So clear them
1372 out of the life information. */
1373 AND_HARD_REG_SET (allowed, clobbered);
1374 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1375 if (TEST_HARD_REG_BIT (allowed, i))
1377 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1378 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1385 /* Copy the global variables n_reloads and rld into the corresponding elts
1388 copy_reloads (struct insn_chain *chain)
1390 chain->n_reloads = n_reloads;
1391 chain->rld = obstack_alloc (&reload_obstack,
1392 n_reloads * sizeof (struct reload));
1393 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1394 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1397 /* Walk the chain of insns, and determine for each whether it needs reloads
1398 and/or eliminations. Build the corresponding insns_need_reload list, and
1399 set something_needs_elimination as appropriate. */
1401 calculate_needs_all_insns (int global)
1403 struct insn_chain **pprev_reload = &insns_need_reload;
1404 struct insn_chain *chain, *next = 0;
1406 something_needs_elimination = 0;
1408 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1409 for (chain = reload_insn_chain; chain != 0; chain = next)
1411 rtx insn = chain->insn;
1415 /* Clear out the shortcuts. */
1416 chain->n_reloads = 0;
1417 chain->need_elim = 0;
1418 chain->need_reload = 0;
1419 chain->need_operand_change = 0;
1421 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1422 include REG_LABEL), we need to see what effects this has on the
1423 known offsets at labels. */
1425 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1426 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1427 set_label_offsets (insn, insn, 0);
1431 rtx old_body = PATTERN (insn);
1432 int old_code = INSN_CODE (insn);
1433 rtx old_notes = REG_NOTES (insn);
1434 int did_elimination = 0;
1435 int operands_changed = 0;
1436 rtx set = single_set (insn);
1438 /* Skip insns that only set an equivalence. */
1439 if (set && GET_CODE (SET_DEST (set)) == REG
1440 && reg_renumber[REGNO (SET_DEST (set))] < 0
1441 && reg_equiv_constant[REGNO (SET_DEST (set))])
1444 /* If needed, eliminate any eliminable registers. */
1445 if (num_eliminable || num_eliminable_invariants)
1446 did_elimination = eliminate_regs_in_insn (insn, 0);
1448 /* Analyze the instruction. */
1449 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1450 global, spill_reg_order);
1452 /* If a no-op set needs more than one reload, this is likely
1453 to be something that needs input address reloads. We
1454 can't get rid of this cleanly later, and it is of no use
1455 anyway, so discard it now.
1456 We only do this when expensive_optimizations is enabled,
1457 since this complements reload inheritance / output
1458 reload deletion, and it can make debugging harder. */
1459 if (flag_expensive_optimizations && n_reloads > 1)
1461 rtx set = single_set (insn);
1463 && SET_SRC (set) == SET_DEST (set)
1464 && GET_CODE (SET_SRC (set)) == REG
1465 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1468 /* Delete it from the reload chain. */
1470 chain->prev->next = next;
1472 reload_insn_chain = next;
1474 next->prev = chain->prev;
1475 chain->next = unused_insn_chains;
1476 unused_insn_chains = chain;
1481 update_eliminable_offsets ();
1483 /* Remember for later shortcuts which insns had any reloads or
1484 register eliminations. */
1485 chain->need_elim = did_elimination;
1486 chain->need_reload = n_reloads > 0;
1487 chain->need_operand_change = operands_changed;
1489 /* Discard any register replacements done. */
1490 if (did_elimination)
1492 obstack_free (&reload_obstack, reload_insn_firstobj);
1493 PATTERN (insn) = old_body;
1494 INSN_CODE (insn) = old_code;
1495 REG_NOTES (insn) = old_notes;
1496 something_needs_elimination = 1;
1499 something_needs_operands_changed |= operands_changed;
1503 copy_reloads (chain);
1504 *pprev_reload = chain;
1505 pprev_reload = &chain->next_need_reload;
1512 /* Comparison function for qsort to decide which of two reloads
1513 should be handled first. *P1 and *P2 are the reload numbers. */
1516 reload_reg_class_lower (const void *r1p, const void *r2p)
1518 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1521 /* Consider required reloads before optional ones. */
1522 t = rld[r1].optional - rld[r2].optional;
1526 /* Count all solitary classes before non-solitary ones. */
1527 t = ((reg_class_size[(int) rld[r2].class] == 1)
1528 - (reg_class_size[(int) rld[r1].class] == 1));
1532 /* Aside from solitaires, consider all multi-reg groups first. */
1533 t = rld[r2].nregs - rld[r1].nregs;
1537 /* Consider reloads in order of increasing reg-class number. */
1538 t = (int) rld[r1].class - (int) rld[r2].class;
1542 /* If reloads are equally urgent, sort by reload number,
1543 so that the results of qsort leave nothing to chance. */
1547 /* The cost of spilling each hard reg. */
1548 static int spill_cost[FIRST_PSEUDO_REGISTER];
1550 /* When spilling multiple hard registers, we use SPILL_COST for the first
1551 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1552 only the first hard reg for a multi-reg pseudo. */
1553 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1555 /* Update the spill cost arrays, considering that pseudo REG is live. */
1558 count_pseudo (int reg)
1560 int freq = REG_FREQ (reg);
1561 int r = reg_renumber[reg];
1564 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1565 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1568 SET_REGNO_REG_SET (&pseudos_counted, reg);
1573 spill_add_cost[r] += freq;
1575 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1577 spill_cost[r + nregs] += freq;
1580 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1581 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1584 order_regs_for_reload (struct insn_chain *chain)
1587 HARD_REG_SET used_by_pseudos;
1588 HARD_REG_SET used_by_pseudos2;
1590 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1592 memset (spill_cost, 0, sizeof spill_cost);
1593 memset (spill_add_cost, 0, sizeof spill_add_cost);
1595 /* Count number of uses of each hard reg by pseudo regs allocated to it
1596 and then order them by decreasing use. First exclude hard registers
1597 that are live in or across this insn. */
1599 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1600 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1601 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1602 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1604 /* Now find out which pseudos are allocated to it, and update
1606 CLEAR_REG_SET (&pseudos_counted);
1608 EXECUTE_IF_SET_IN_REG_SET
1609 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1613 EXECUTE_IF_SET_IN_REG_SET
1614 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1618 CLEAR_REG_SET (&pseudos_counted);
1621 /* Vector of reload-numbers showing the order in which the reloads should
1623 static short reload_order[MAX_RELOADS];
1625 /* This is used to keep track of the spill regs used in one insn. */
1626 static HARD_REG_SET used_spill_regs_local;
1628 /* We decided to spill hard register SPILLED, which has a size of
1629 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1630 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1631 update SPILL_COST/SPILL_ADD_COST. */
1634 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1636 int r = reg_renumber[reg];
1637 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1639 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1640 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1643 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1645 spill_add_cost[r] -= REG_FREQ (reg);
1647 spill_cost[r + nregs] -= REG_FREQ (reg);
1650 /* Find reload register to use for reload number ORDER. */
1653 find_reg (struct insn_chain *chain, int order)
1655 int rnum = reload_order[order];
1656 struct reload *rl = rld + rnum;
1657 int best_cost = INT_MAX;
1661 HARD_REG_SET not_usable;
1662 HARD_REG_SET used_by_other_reload;
1664 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1665 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1666 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1668 CLEAR_HARD_REG_SET (used_by_other_reload);
1669 for (k = 0; k < order; k++)
1671 int other = reload_order[k];
1673 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1674 for (j = 0; j < rld[other].nregs; j++)
1675 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1678 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1680 unsigned int regno = i;
1682 if (! TEST_HARD_REG_BIT (not_usable, regno)
1683 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1684 && HARD_REGNO_MODE_OK (regno, rl->mode))
1686 int this_cost = spill_cost[regno];
1688 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1690 for (j = 1; j < this_nregs; j++)
1692 this_cost += spill_add_cost[regno + j];
1693 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1694 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1699 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1701 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1703 if (this_cost < best_cost
1704 /* Among registers with equal cost, prefer caller-saved ones, or
1705 use REG_ALLOC_ORDER if it is defined. */
1706 || (this_cost == best_cost
1707 #ifdef REG_ALLOC_ORDER
1708 && (inv_reg_alloc_order[regno]
1709 < inv_reg_alloc_order[best_reg])
1711 && call_used_regs[regno]
1712 && ! call_used_regs[best_reg]
1717 best_cost = this_cost;
1725 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1727 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1728 rl->regno = best_reg;
1730 EXECUTE_IF_SET_IN_REG_SET
1731 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1733 count_spilled_pseudo (best_reg, rl->nregs, j);
1736 EXECUTE_IF_SET_IN_REG_SET
1737 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1739 count_spilled_pseudo (best_reg, rl->nregs, j);
1742 for (i = 0; i < rl->nregs; i++)
1744 if (spill_cost[best_reg + i] != 0
1745 || spill_add_cost[best_reg + i] != 0)
1747 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1752 /* Find more reload regs to satisfy the remaining need of an insn, which
1754 Do it by ascending class number, since otherwise a reg
1755 might be spilled for a big class and might fail to count
1756 for a smaller class even though it belongs to that class. */
1759 find_reload_regs (struct insn_chain *chain)
1763 /* In order to be certain of getting the registers we need,
1764 we must sort the reloads into order of increasing register class.
1765 Then our grabbing of reload registers will parallel the process
1766 that provided the reload registers. */
1767 for (i = 0; i < chain->n_reloads; i++)
1769 /* Show whether this reload already has a hard reg. */
1770 if (chain->rld[i].reg_rtx)
1772 int regno = REGNO (chain->rld[i].reg_rtx);
1773 chain->rld[i].regno = regno;
1775 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1778 chain->rld[i].regno = -1;
1779 reload_order[i] = i;
1782 n_reloads = chain->n_reloads;
1783 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1785 CLEAR_HARD_REG_SET (used_spill_regs_local);
1788 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1790 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1792 /* Compute the order of preference for hard registers to spill. */
1794 order_regs_for_reload (chain);
1796 for (i = 0; i < n_reloads; i++)
1798 int r = reload_order[i];
1800 /* Ignore reloads that got marked inoperative. */
1801 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1802 && ! rld[r].optional
1803 && rld[r].regno == -1)
1804 if (! find_reg (chain, i))
1806 spill_failure (chain->insn, rld[r].class);
1812 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1813 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1815 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1819 select_reload_regs (void)
1821 struct insn_chain *chain;
1823 /* Try to satisfy the needs for each insn. */
1824 for (chain = insns_need_reload; chain != 0;
1825 chain = chain->next_need_reload)
1826 find_reload_regs (chain);
1829 /* Delete all insns that were inserted by emit_caller_save_insns during
1832 delete_caller_save_insns (void)
1834 struct insn_chain *c = reload_insn_chain;
1838 while (c != 0 && c->is_caller_save_insn)
1840 struct insn_chain *next = c->next;
1843 if (c == reload_insn_chain)
1844 reload_insn_chain = next;
1848 next->prev = c->prev;
1850 c->prev->next = next;
1851 c->next = unused_insn_chains;
1852 unused_insn_chains = c;
1860 /* Handle the failure to find a register to spill.
1861 INSN should be one of the insns which needed this particular spill reg. */
1864 spill_failure (rtx insn, enum reg_class class)
1866 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1867 if (asm_noperands (PATTERN (insn)) >= 0)
1868 error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'",
1869 reg_class_names[class]);
1872 error ("unable to find a register to spill in class `%s'",
1873 reg_class_names[class]);
1874 fatal_insn ("this is the insn:", insn);
1878 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1879 data that is dead in INSN. */
1882 delete_dead_insn (rtx insn)
1884 rtx prev = prev_real_insn (insn);
1887 /* If the previous insn sets a register that dies in our insn, delete it
1889 if (prev && GET_CODE (PATTERN (prev)) == SET
1890 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1891 && reg_mentioned_p (prev_dest, PATTERN (insn))
1892 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1893 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1894 delete_dead_insn (prev);
1896 PUT_CODE (insn, NOTE);
1897 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1898 NOTE_SOURCE_FILE (insn) = 0;
1901 /* Modify the home of pseudo-reg I.
1902 The new home is present in reg_renumber[I].
1904 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1905 or it may be -1, meaning there is none or it is not relevant.
1906 This is used so that all pseudos spilled from a given hard reg
1907 can share one stack slot. */
1910 alter_reg (int i, int from_reg)
1912 /* When outputting an inline function, this can happen
1913 for a reg that isn't actually used. */
1914 if (regno_reg_rtx[i] == 0)
1917 /* If the reg got changed to a MEM at rtl-generation time,
1919 if (GET_CODE (regno_reg_rtx[i]) != REG)
1922 /* Modify the reg-rtx to contain the new hard reg
1923 number or else to contain its pseudo reg number. */
1924 REGNO (regno_reg_rtx[i])
1925 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1927 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1928 allocate a stack slot for it. */
1930 if (reg_renumber[i] < 0
1931 && REG_N_REFS (i) > 0
1932 && reg_equiv_constant[i] == 0
1933 && reg_equiv_memory_loc[i] == 0)
1936 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1937 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1940 /* Each pseudo reg has an inherent size which comes from its own mode,
1941 and a total size which provides room for paradoxical subregs
1942 which refer to the pseudo reg in wider modes.
1944 We can use a slot already allocated if it provides both
1945 enough inherent space and enough total space.
1946 Otherwise, we allocate a new slot, making sure that it has no less
1947 inherent space, and no less total space, then the previous slot. */
1950 /* No known place to spill from => no slot to reuse. */
1951 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1952 inherent_size == total_size ? 0 : -1);
1953 if (BYTES_BIG_ENDIAN)
1954 /* Cancel the big-endian correction done in assign_stack_local.
1955 Get the address of the beginning of the slot.
1956 This is so we can do a big-endian correction unconditionally
1958 adjust = inherent_size - total_size;
1960 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1962 /* Nothing can alias this slot except this pseudo. */
1963 set_mem_alias_set (x, new_alias_set ());
1966 /* Reuse a stack slot if possible. */
1967 else if (spill_stack_slot[from_reg] != 0
1968 && spill_stack_slot_width[from_reg] >= total_size
1969 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1971 x = spill_stack_slot[from_reg];
1973 /* Allocate a bigger slot. */
1976 /* Compute maximum size needed, both for inherent size
1977 and for total size. */
1978 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1981 if (spill_stack_slot[from_reg])
1983 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1985 mode = GET_MODE (spill_stack_slot[from_reg]);
1986 if (spill_stack_slot_width[from_reg] > total_size)
1987 total_size = spill_stack_slot_width[from_reg];
1990 /* Make a slot with that size. */
1991 x = assign_stack_local (mode, total_size,
1992 inherent_size == total_size ? 0 : -1);
1995 /* All pseudos mapped to this slot can alias each other. */
1996 if (spill_stack_slot[from_reg])
1997 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
1999 set_mem_alias_set (x, new_alias_set ());
2001 if (BYTES_BIG_ENDIAN)
2003 /* Cancel the big-endian correction done in assign_stack_local.
2004 Get the address of the beginning of the slot.
2005 This is so we can do a big-endian correction unconditionally
2007 adjust = GET_MODE_SIZE (mode) - total_size;
2010 = adjust_address_nv (x, mode_for_size (total_size
2016 spill_stack_slot[from_reg] = stack_slot;
2017 spill_stack_slot_width[from_reg] = total_size;
2020 /* On a big endian machine, the "address" of the slot
2021 is the address of the low part that fits its inherent mode. */
2022 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2023 adjust += (total_size - inherent_size);
2025 /* If we have any adjustment to make, or if the stack slot is the
2026 wrong mode, make a new stack slot. */
2027 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2029 /* If we have a decl for the original register, set it for the
2030 memory. If this is a shared MEM, make a copy. */
2031 if (REG_EXPR (regno_reg_rtx[i])
2032 && TREE_CODE_CLASS (TREE_CODE (REG_EXPR (regno_reg_rtx[i]))) == 'd')
2034 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2036 /* We can do this only for the DECLs home pseudo, not for
2037 any copies of it, since otherwise when the stack slot
2038 is reused, nonoverlapping_memrefs_p might think they
2040 if (decl && GET_CODE (decl) == REG && REGNO (decl) == (unsigned) i)
2042 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2045 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2049 /* Save the stack slot for later. */
2050 reg_equiv_memory_loc[i] = x;
2054 /* Mark the slots in regs_ever_live for the hard regs
2055 used by pseudo-reg number REGNO. */
2058 mark_home_live (int regno)
2062 i = reg_renumber[regno];
2065 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2067 regs_ever_live[i++] = 1;
2070 /* This function handles the tracking of elimination offsets around branches.
2072 X is a piece of RTL being scanned.
2074 INSN is the insn that it came from, if any.
2076 INITIAL_P is nonzero if we are to set the offset to be the initial
2077 offset and zero if we are setting the offset of the label to be the
2081 set_label_offsets (rtx x, rtx insn, int initial_p)
2083 enum rtx_code code = GET_CODE (x);
2086 struct elim_table *p;
2091 if (LABEL_REF_NONLOCAL_P (x))
2096 /* ... fall through ... */
2099 /* If we know nothing about this label, set the desired offsets. Note
2100 that this sets the offset at a label to be the offset before a label
2101 if we don't know anything about the label. This is not correct for
2102 the label after a BARRIER, but is the best guess we can make. If
2103 we guessed wrong, we will suppress an elimination that might have
2104 been possible had we been able to guess correctly. */
2106 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2108 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2109 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2110 = (initial_p ? reg_eliminate[i].initial_offset
2111 : reg_eliminate[i].offset);
2112 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2115 /* Otherwise, if this is the definition of a label and it is
2116 preceded by a BARRIER, set our offsets to the known offset of
2120 && (tem = prev_nonnote_insn (insn)) != 0
2121 && GET_CODE (tem) == BARRIER)
2122 set_offsets_for_label (insn);
2124 /* If neither of the above cases is true, compare each offset
2125 with those previously recorded and suppress any eliminations
2126 where the offsets disagree. */
2128 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2129 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2130 != (initial_p ? reg_eliminate[i].initial_offset
2131 : reg_eliminate[i].offset))
2132 reg_eliminate[i].can_eliminate = 0;
2137 set_label_offsets (PATTERN (insn), insn, initial_p);
2139 /* ... fall through ... */
2143 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2144 and hence must have all eliminations at their initial offsets. */
2145 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2146 if (REG_NOTE_KIND (tem) == REG_LABEL)
2147 set_label_offsets (XEXP (tem, 0), insn, 1);
2153 /* Each of the labels in the parallel or address vector must be
2154 at their initial offsets. We want the first field for PARALLEL
2155 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2157 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2158 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2163 /* We only care about setting PC. If the source is not RETURN,
2164 IF_THEN_ELSE, or a label, disable any eliminations not at
2165 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2166 isn't one of those possibilities. For branches to a label,
2167 call ourselves recursively.
2169 Note that this can disable elimination unnecessarily when we have
2170 a non-local goto since it will look like a non-constant jump to
2171 someplace in the current function. This isn't a significant
2172 problem since such jumps will normally be when all elimination
2173 pairs are back to their initial offsets. */
2175 if (SET_DEST (x) != pc_rtx)
2178 switch (GET_CODE (SET_SRC (x)))
2185 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2189 tem = XEXP (SET_SRC (x), 1);
2190 if (GET_CODE (tem) == LABEL_REF)
2191 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2192 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2195 tem = XEXP (SET_SRC (x), 2);
2196 if (GET_CODE (tem) == LABEL_REF)
2197 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2198 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2206 /* If we reach here, all eliminations must be at their initial
2207 offset because we are doing a jump to a variable address. */
2208 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2209 if (p->offset != p->initial_offset)
2210 p->can_eliminate = 0;
2218 /* Scan X and replace any eliminable registers (such as fp) with a
2219 replacement (such as sp), plus an offset.
2221 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2222 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2223 MEM, we are allowed to replace a sum of a register and the constant zero
2224 with the register, which we cannot do outside a MEM. In addition, we need
2225 to record the fact that a register is referenced outside a MEM.
2227 If INSN is an insn, it is the insn containing X. If we replace a REG
2228 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2229 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2230 the REG is being modified.
2232 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2233 That's used when we eliminate in expressions stored in notes.
2234 This means, do not set ref_outside_mem even if the reference
2237 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2238 replacements done assuming all offsets are at their initial values. If
2239 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2240 encounter, return the actual location so that find_reloads will do
2241 the proper thing. */
2244 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2246 enum rtx_code code = GET_CODE (x);
2247 struct elim_table *ep;
2254 if (! current_function_decl)
2274 /* This is only for the benefit of the debugging backends, which call
2275 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2276 removed after CSE. */
2277 new = eliminate_regs (XEXP (x, 0), 0, insn);
2278 if (GET_CODE (new) == MEM)
2279 return XEXP (new, 0);
2285 /* First handle the case where we encounter a bare register that
2286 is eliminable. Replace it with a PLUS. */
2287 if (regno < FIRST_PSEUDO_REGISTER)
2289 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2291 if (ep->from_rtx == x && ep->can_eliminate)
2292 return plus_constant (ep->to_rtx, ep->previous_offset);
2295 else if (reg_renumber && reg_renumber[regno] < 0
2296 && reg_equiv_constant && reg_equiv_constant[regno]
2297 && ! CONSTANT_P (reg_equiv_constant[regno]))
2298 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2302 /* You might think handling MINUS in a manner similar to PLUS is a
2303 good idea. It is not. It has been tried multiple times and every
2304 time the change has had to have been reverted.
2306 Other parts of reload know a PLUS is special (gen_reload for example)
2307 and require special code to handle code a reloaded PLUS operand.
2309 Also consider backends where the flags register is clobbered by a
2310 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2311 lea instruction comes to mind). If we try to reload a MINUS, we
2312 may kill the flags register that was holding a useful value.
2314 So, please before trying to handle MINUS, consider reload as a
2315 whole instead of this little section as well as the backend issues. */
2317 /* If this is the sum of an eliminable register and a constant, rework
2319 if (GET_CODE (XEXP (x, 0)) == REG
2320 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2321 && CONSTANT_P (XEXP (x, 1)))
2323 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2325 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2327 /* The only time we want to replace a PLUS with a REG (this
2328 occurs when the constant operand of the PLUS is the negative
2329 of the offset) is when we are inside a MEM. We won't want
2330 to do so at other times because that would change the
2331 structure of the insn in a way that reload can't handle.
2332 We special-case the commonest situation in
2333 eliminate_regs_in_insn, so just replace a PLUS with a
2334 PLUS here, unless inside a MEM. */
2335 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2336 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2339 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2340 plus_constant (XEXP (x, 1),
2341 ep->previous_offset));
2344 /* If the register is not eliminable, we are done since the other
2345 operand is a constant. */
2349 /* If this is part of an address, we want to bring any constant to the
2350 outermost PLUS. We will do this by doing register replacement in
2351 our operands and seeing if a constant shows up in one of them.
2353 Note that there is no risk of modifying the structure of the insn,
2354 since we only get called for its operands, thus we are either
2355 modifying the address inside a MEM, or something like an address
2356 operand of a load-address insn. */
2359 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2360 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2362 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2364 /* If one side is a PLUS and the other side is a pseudo that
2365 didn't get a hard register but has a reg_equiv_constant,
2366 we must replace the constant here since it may no longer
2367 be in the position of any operand. */
2368 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2369 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2370 && reg_renumber[REGNO (new1)] < 0
2371 && reg_equiv_constant != 0
2372 && reg_equiv_constant[REGNO (new1)] != 0)
2373 new1 = reg_equiv_constant[REGNO (new1)];
2374 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2375 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2376 && reg_renumber[REGNO (new0)] < 0
2377 && reg_equiv_constant[REGNO (new0)] != 0)
2378 new0 = reg_equiv_constant[REGNO (new0)];
2380 new = form_sum (new0, new1);
2382 /* As above, if we are not inside a MEM we do not want to
2383 turn a PLUS into something else. We might try to do so here
2384 for an addition of 0 if we aren't optimizing. */
2385 if (! mem_mode && GET_CODE (new) != PLUS)
2386 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2394 /* If this is the product of an eliminable register and a
2395 constant, apply the distribute law and move the constant out
2396 so that we have (plus (mult ..) ..). This is needed in order
2397 to keep load-address insns valid. This case is pathological.
2398 We ignore the possibility of overflow here. */
2399 if (GET_CODE (XEXP (x, 0)) == REG
2400 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2401 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2402 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2404 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2407 /* Refs inside notes don't count for this purpose. */
2408 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2409 || GET_CODE (insn) == INSN_LIST)))
2410 ep->ref_outside_mem = 1;
2413 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2414 ep->previous_offset * INTVAL (XEXP (x, 1)));
2417 /* ... fall through ... */
2421 /* See comments before PLUS about handling MINUS. */
2423 case DIV: case UDIV:
2424 case MOD: case UMOD:
2425 case AND: case IOR: case XOR:
2426 case ROTATERT: case ROTATE:
2427 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2429 case GE: case GT: case GEU: case GTU:
2430 case LE: case LT: case LEU: case LTU:
2432 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2434 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2436 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2437 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2442 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2445 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2446 if (new != XEXP (x, 0))
2448 /* If this is a REG_DEAD note, it is not valid anymore.
2449 Using the eliminated version could result in creating a
2450 REG_DEAD note for the stack or frame pointer. */
2451 if (GET_MODE (x) == REG_DEAD)
2453 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2456 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2460 /* ... fall through ... */
2463 /* Now do eliminations in the rest of the chain. If this was
2464 an EXPR_LIST, this might result in allocating more memory than is
2465 strictly needed, but it simplifies the code. */
2468 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2469 if (new != XEXP (x, 1))
2471 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2479 case STRICT_LOW_PART:
2481 case SIGN_EXTEND: case ZERO_EXTEND:
2482 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2483 case FLOAT: case FIX:
2484 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2492 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2493 if (new != XEXP (x, 0))
2494 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2498 /* Similar to above processing, but preserve SUBREG_BYTE.
2499 Convert (subreg (mem)) to (mem) if not paradoxical.
2500 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2501 pseudo didn't get a hard reg, we must replace this with the
2502 eliminated version of the memory location because push_reload
2503 may do the replacement in certain circumstances. */
2504 if (GET_CODE (SUBREG_REG (x)) == REG
2505 && (GET_MODE_SIZE (GET_MODE (x))
2506 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2507 && reg_equiv_memory_loc != 0
2508 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2510 new = SUBREG_REG (x);
2513 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2515 if (new != SUBREG_REG (x))
2517 int x_size = GET_MODE_SIZE (GET_MODE (x));
2518 int new_size = GET_MODE_SIZE (GET_MODE (new));
2520 if (GET_CODE (new) == MEM
2521 && ((x_size < new_size
2522 #ifdef WORD_REGISTER_OPERATIONS
2523 /* On these machines, combine can create rtl of the form
2524 (set (subreg:m1 (reg:m2 R) 0) ...)
2525 where m1 < m2, and expects something interesting to
2526 happen to the entire word. Moreover, it will use the
2527 (reg:m2 R) later, expecting all bits to be preserved.
2528 So if the number of words is the same, preserve the
2529 subreg so that push_reload can see it. */
2530 && ! ((x_size - 1) / UNITS_PER_WORD
2531 == (new_size -1 ) / UNITS_PER_WORD)
2534 || x_size == new_size)
2536 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2538 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2544 /* This is only for the benefit of the debugging backends, which call
2545 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2546 removed after CSE. */
2547 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2548 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2550 /* Our only special processing is to pass the mode of the MEM to our
2551 recursive call and copy the flags. While we are here, handle this
2552 case more efficiently. */
2554 replace_equiv_address_nv (x,
2555 eliminate_regs (XEXP (x, 0),
2556 GET_MODE (x), insn));
2559 /* Handle insn_list USE that a call to a pure function may generate. */
2560 new = eliminate_regs (XEXP (x, 0), 0, insn);
2561 if (new != XEXP (x, 0))
2562 return gen_rtx_USE (GET_MODE (x), new);
2574 /* Process each of our operands recursively. If any have changed, make a
2576 fmt = GET_RTX_FORMAT (code);
2577 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2581 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2582 if (new != XEXP (x, i) && ! copied)
2584 rtx new_x = rtx_alloc (code);
2585 memcpy (new_x, x, RTX_SIZE (code));
2591 else if (*fmt == 'E')
2594 for (j = 0; j < XVECLEN (x, i); j++)
2596 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2597 if (new != XVECEXP (x, i, j) && ! copied_vec)
2599 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2603 rtx new_x = rtx_alloc (code);
2604 memcpy (new_x, x, RTX_SIZE (code));
2608 XVEC (x, i) = new_v;
2611 XVECEXP (x, i, j) = new;
2619 /* Scan rtx X for modifications of elimination target registers. Update
2620 the table of eliminables to reflect the changed state. MEM_MODE is
2621 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2624 elimination_effects (rtx x, enum machine_mode mem_mode)
2626 enum rtx_code code = GET_CODE (x);
2627 struct elim_table *ep;
2654 /* First handle the case where we encounter a bare register that
2655 is eliminable. Replace it with a PLUS. */
2656 if (regno < FIRST_PSEUDO_REGISTER)
2658 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2660 if (ep->from_rtx == x && ep->can_eliminate)
2663 ep->ref_outside_mem = 1;
2668 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2669 && reg_equiv_constant[regno]
2670 && ! function_invariant_p (reg_equiv_constant[regno]))
2671 elimination_effects (reg_equiv_constant[regno], mem_mode);
2680 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2681 if (ep->to_rtx == XEXP (x, 0))
2683 int size = GET_MODE_SIZE (mem_mode);
2685 /* If more bytes than MEM_MODE are pushed, account for them. */
2686 #ifdef PUSH_ROUNDING
2687 if (ep->to_rtx == stack_pointer_rtx)
2688 size = PUSH_ROUNDING (size);
2690 if (code == PRE_DEC || code == POST_DEC)
2692 else if (code == PRE_INC || code == POST_INC)
2694 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2695 && GET_CODE (XEXP (x, 1)) == PLUS
2696 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2697 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2698 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2701 /* These two aren't unary operators. */
2702 if (code == POST_MODIFY || code == PRE_MODIFY)
2705 /* Fall through to generic unary operation case. */
2706 case STRICT_LOW_PART:
2708 case SIGN_EXTEND: case ZERO_EXTEND:
2709 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2710 case FLOAT: case FIX:
2711 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2719 elimination_effects (XEXP (x, 0), mem_mode);
2723 if (GET_CODE (SUBREG_REG (x)) == REG
2724 && (GET_MODE_SIZE (GET_MODE (x))
2725 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2726 && reg_equiv_memory_loc != 0
2727 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2730 elimination_effects (SUBREG_REG (x), mem_mode);
2734 /* If using a register that is the source of an eliminate we still
2735 think can be performed, note it cannot be performed since we don't
2736 know how this register is used. */
2737 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2738 if (ep->from_rtx == XEXP (x, 0))
2739 ep->can_eliminate = 0;
2741 elimination_effects (XEXP (x, 0), mem_mode);
2745 /* If clobbering a register that is the replacement register for an
2746 elimination we still think can be performed, note that it cannot
2747 be performed. Otherwise, we need not be concerned about it. */
2748 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2749 if (ep->to_rtx == XEXP (x, 0))
2750 ep->can_eliminate = 0;
2752 elimination_effects (XEXP (x, 0), mem_mode);
2756 /* Check for setting a register that we know about. */
2757 if (GET_CODE (SET_DEST (x)) == REG)
2759 /* See if this is setting the replacement register for an
2762 If DEST is the hard frame pointer, we do nothing because we
2763 assume that all assignments to the frame pointer are for
2764 non-local gotos and are being done at a time when they are valid
2765 and do not disturb anything else. Some machines want to
2766 eliminate a fake argument pointer (or even a fake frame pointer)
2767 with either the real frame or the stack pointer. Assignments to
2768 the hard frame pointer must not prevent this elimination. */
2770 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2772 if (ep->to_rtx == SET_DEST (x)
2773 && SET_DEST (x) != hard_frame_pointer_rtx)
2775 /* If it is being incremented, adjust the offset. Otherwise,
2776 this elimination can't be done. */
2777 rtx src = SET_SRC (x);
2779 if (GET_CODE (src) == PLUS
2780 && XEXP (src, 0) == SET_DEST (x)
2781 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2782 ep->offset -= INTVAL (XEXP (src, 1));
2784 ep->can_eliminate = 0;
2788 elimination_effects (SET_DEST (x), 0);
2789 elimination_effects (SET_SRC (x), 0);
2793 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2796 /* Our only special processing is to pass the mode of the MEM to our
2798 elimination_effects (XEXP (x, 0), GET_MODE (x));
2805 fmt = GET_RTX_FORMAT (code);
2806 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2809 elimination_effects (XEXP (x, i), mem_mode);
2810 else if (*fmt == 'E')
2811 for (j = 0; j < XVECLEN (x, i); j++)
2812 elimination_effects (XVECEXP (x, i, j), mem_mode);
2816 /* Descend through rtx X and verify that no references to eliminable registers
2817 remain. If any do remain, mark the involved register as not
2821 check_eliminable_occurrences (rtx x)
2830 code = GET_CODE (x);
2832 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2834 struct elim_table *ep;
2836 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2837 if (ep->from_rtx == x && ep->can_eliminate)
2838 ep->can_eliminate = 0;
2842 fmt = GET_RTX_FORMAT (code);
2843 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2846 check_eliminable_occurrences (XEXP (x, i));
2847 else if (*fmt == 'E')
2850 for (j = 0; j < XVECLEN (x, i); j++)
2851 check_eliminable_occurrences (XVECEXP (x, i, j));
2856 /* Scan INSN and eliminate all eliminable registers in it.
2858 If REPLACE is nonzero, do the replacement destructively. Also
2859 delete the insn as dead it if it is setting an eliminable register.
2861 If REPLACE is zero, do all our allocations in reload_obstack.
2863 If no eliminations were done and this insn doesn't require any elimination
2864 processing (these are not identical conditions: it might be updating sp,
2865 but not referencing fp; this needs to be seen during reload_as_needed so
2866 that the offset between fp and sp can be taken into consideration), zero
2867 is returned. Otherwise, 1 is returned. */
2870 eliminate_regs_in_insn (rtx insn, int replace)
2872 int icode = recog_memoized (insn);
2873 rtx old_body = PATTERN (insn);
2874 int insn_is_asm = asm_noperands (old_body) >= 0;
2875 rtx old_set = single_set (insn);
2879 rtx substed_operand[MAX_RECOG_OPERANDS];
2880 rtx orig_operand[MAX_RECOG_OPERANDS];
2881 struct elim_table *ep;
2883 if (! insn_is_asm && icode < 0)
2885 if (GET_CODE (PATTERN (insn)) == USE
2886 || GET_CODE (PATTERN (insn)) == CLOBBER
2887 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2888 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2889 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2894 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2895 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2897 /* Check for setting an eliminable register. */
2898 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2899 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2901 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2902 /* If this is setting the frame pointer register to the
2903 hardware frame pointer register and this is an elimination
2904 that will be done (tested above), this insn is really
2905 adjusting the frame pointer downward to compensate for
2906 the adjustment done before a nonlocal goto. */
2907 if (ep->from == FRAME_POINTER_REGNUM
2908 && ep->to == HARD_FRAME_POINTER_REGNUM)
2910 rtx base = SET_SRC (old_set);
2911 rtx base_insn = insn;
2912 HOST_WIDE_INT offset = 0;
2914 while (base != ep->to_rtx)
2916 rtx prev_insn, prev_set;
2918 if (GET_CODE (base) == PLUS
2919 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2921 offset += INTVAL (XEXP (base, 1));
2922 base = XEXP (base, 0);
2924 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2925 && (prev_set = single_set (prev_insn)) != 0
2926 && rtx_equal_p (SET_DEST (prev_set), base))
2928 base = SET_SRC (prev_set);
2929 base_insn = prev_insn;
2935 if (base == ep->to_rtx)
2938 = plus_constant (ep->to_rtx, offset - ep->offset);
2940 new_body = old_body;
2943 new_body = copy_insn (old_body);
2944 if (REG_NOTES (insn))
2945 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2947 PATTERN (insn) = new_body;
2948 old_set = single_set (insn);
2950 /* First see if this insn remains valid when we
2951 make the change. If not, keep the INSN_CODE
2952 the same and let reload fit it up. */
2953 validate_change (insn, &SET_SRC (old_set), src, 1);
2954 validate_change (insn, &SET_DEST (old_set),
2956 if (! apply_change_group ())
2958 SET_SRC (old_set) = src;
2959 SET_DEST (old_set) = ep->to_rtx;
2968 /* In this case this insn isn't serving a useful purpose. We
2969 will delete it in reload_as_needed once we know that this
2970 elimination is, in fact, being done.
2972 If REPLACE isn't set, we can't delete this insn, but needn't
2973 process it since it won't be used unless something changes. */
2976 delete_dead_insn (insn);
2984 /* We allow one special case which happens to work on all machines we
2985 currently support: a single set with the source being a PLUS of an
2986 eliminable register and a constant. */
2988 && GET_CODE (SET_DEST (old_set)) == REG
2989 && GET_CODE (SET_SRC (old_set)) == PLUS
2990 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
2991 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
2992 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
2994 rtx reg = XEXP (SET_SRC (old_set), 0);
2995 HOST_WIDE_INT offset = INTVAL (XEXP (SET_SRC (old_set), 1));
2997 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2998 if (ep->from_rtx == reg && ep->can_eliminate)
3000 offset += ep->offset;
3005 /* We assume here that if we need a PARALLEL with
3006 CLOBBERs for this assignment, we can do with the
3007 MATCH_SCRATCHes that add_clobbers allocates.
3008 There's not much we can do if that doesn't work. */
3009 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3013 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3016 rtvec vec = rtvec_alloc (num_clobbers + 1);
3018 vec->elem[0] = PATTERN (insn);
3019 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3020 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3022 if (INSN_CODE (insn) < 0)
3027 new_body = old_body;
3030 new_body = copy_insn (old_body);
3031 if (REG_NOTES (insn))
3032 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3034 PATTERN (insn) = new_body;
3035 old_set = single_set (insn);
3037 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3038 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3041 /* This can't have an effect on elimination offsets, so skip right
3047 /* Determine the effects of this insn on elimination offsets. */
3048 elimination_effects (old_body, 0);
3050 /* Eliminate all eliminable registers occurring in operands that
3051 can be handled by reload. */
3052 extract_insn (insn);
3053 for (i = 0; i < recog_data.n_operands; i++)
3055 orig_operand[i] = recog_data.operand[i];
3056 substed_operand[i] = recog_data.operand[i];
3058 /* For an asm statement, every operand is eliminable. */
3059 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3061 /* Check for setting a register that we know about. */
3062 if (recog_data.operand_type[i] != OP_IN
3063 && GET_CODE (orig_operand[i]) == REG)
3065 /* If we are assigning to a register that can be eliminated, it
3066 must be as part of a PARALLEL, since the code above handles
3067 single SETs. We must indicate that we can no longer
3068 eliminate this reg. */
3069 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3071 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3072 ep->can_eliminate = 0;
3075 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3076 replace ? insn : NULL_RTX);
3077 if (substed_operand[i] != orig_operand[i])
3079 /* Terminate the search in check_eliminable_occurrences at
3081 *recog_data.operand_loc[i] = 0;
3083 /* If an output operand changed from a REG to a MEM and INSN is an
3084 insn, write a CLOBBER insn. */
3085 if (recog_data.operand_type[i] != OP_IN
3086 && GET_CODE (orig_operand[i]) == REG
3087 && GET_CODE (substed_operand[i]) == MEM
3089 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3094 for (i = 0; i < recog_data.n_dups; i++)
3095 *recog_data.dup_loc[i]
3096 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3098 /* If any eliminable remain, they aren't eliminable anymore. */
3099 check_eliminable_occurrences (old_body);
3101 /* Substitute the operands; the new values are in the substed_operand
3103 for (i = 0; i < recog_data.n_operands; i++)
3104 *recog_data.operand_loc[i] = substed_operand[i];
3105 for (i = 0; i < recog_data.n_dups; i++)
3106 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3108 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3109 re-recognize the insn. We do this in case we had a simple addition
3110 but now can do this as a load-address. This saves an insn in this
3112 If re-recognition fails, the old insn code number will still be used,
3113 and some register operands may have changed into PLUS expressions.
3114 These will be handled by find_reloads by loading them into a register
3119 /* If we aren't replacing things permanently and we changed something,
3120 make another copy to ensure that all the RTL is new. Otherwise
3121 things can go wrong if find_reload swaps commutative operands
3122 and one is inside RTL that has been copied while the other is not. */
3123 new_body = old_body;
3126 new_body = copy_insn (old_body);
3127 if (REG_NOTES (insn))
3128 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3130 PATTERN (insn) = new_body;
3132 /* If we had a move insn but now we don't, rerecognize it. This will
3133 cause spurious re-recognition if the old move had a PARALLEL since
3134 the new one still will, but we can't call single_set without
3135 having put NEW_BODY into the insn and the re-recognition won't
3136 hurt in this rare case. */
3137 /* ??? Why this huge if statement - why don't we just rerecognize the
3141 && ((GET_CODE (SET_SRC (old_set)) == REG
3142 && (GET_CODE (new_body) != SET
3143 || GET_CODE (SET_SRC (new_body)) != REG))
3144 /* If this was a load from or store to memory, compare
3145 the MEM in recog_data.operand to the one in the insn.
3146 If they are not equal, then rerecognize the insn. */
3148 && ((GET_CODE (SET_SRC (old_set)) == MEM
3149 && SET_SRC (old_set) != recog_data.operand[1])
3150 || (GET_CODE (SET_DEST (old_set)) == MEM
3151 && SET_DEST (old_set) != recog_data.operand[0])))
3152 /* If this was an add insn before, rerecognize. */
3153 || GET_CODE (SET_SRC (old_set)) == PLUS))
3155 int new_icode = recog (PATTERN (insn), insn, 0);
3157 INSN_CODE (insn) = icode;
3161 /* Restore the old body. If there were any changes to it, we made a copy
3162 of it while the changes were still in place, so we'll correctly return
3163 a modified insn below. */
3166 /* Restore the old body. */
3167 for (i = 0; i < recog_data.n_operands; i++)
3168 *recog_data.operand_loc[i] = orig_operand[i];
3169 for (i = 0; i < recog_data.n_dups; i++)
3170 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3173 /* Update all elimination pairs to reflect the status after the current
3174 insn. The changes we make were determined by the earlier call to
3175 elimination_effects.
3177 We also detect cases where register elimination cannot be done,
3178 namely, if a register would be both changed and referenced outside a MEM
3179 in the resulting insn since such an insn is often undefined and, even if
3180 not, we cannot know what meaning will be given to it. Note that it is
3181 valid to have a register used in an address in an insn that changes it
3182 (presumably with a pre- or post-increment or decrement).
3184 If anything changes, return nonzero. */
3186 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3188 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3189 ep->can_eliminate = 0;
3191 ep->ref_outside_mem = 0;
3193 if (ep->previous_offset != ep->offset)
3198 /* If we changed something, perform elimination in REG_NOTES. This is
3199 needed even when REPLACE is zero because a REG_DEAD note might refer
3200 to a register that we eliminate and could cause a different number
3201 of spill registers to be needed in the final reload pass than in
3203 if (val && REG_NOTES (insn) != 0)
3204 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3209 /* Loop through all elimination pairs.
3210 Recalculate the number not at initial offset.
3212 Compute the maximum offset (minimum offset if the stack does not
3213 grow downward) for each elimination pair. */
3216 update_eliminable_offsets (void)
3218 struct elim_table *ep;
3220 num_not_at_initial_offset = 0;
3221 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3223 ep->previous_offset = ep->offset;
3224 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3225 num_not_at_initial_offset++;
3229 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3230 replacement we currently believe is valid, mark it as not eliminable if X
3231 modifies DEST in any way other than by adding a constant integer to it.
3233 If DEST is the frame pointer, we do nothing because we assume that
3234 all assignments to the hard frame pointer are nonlocal gotos and are being
3235 done at a time when they are valid and do not disturb anything else.
3236 Some machines want to eliminate a fake argument pointer with either the
3237 frame or stack pointer. Assignments to the hard frame pointer must not
3238 prevent this elimination.
3240 Called via note_stores from reload before starting its passes to scan
3241 the insns of the function. */
3244 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3248 /* A SUBREG of a hard register here is just changing its mode. We should
3249 not see a SUBREG of an eliminable hard register, but check just in
3251 if (GET_CODE (dest) == SUBREG)
3252 dest = SUBREG_REG (dest);
3254 if (dest == hard_frame_pointer_rtx)
3257 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3258 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3259 && (GET_CODE (x) != SET
3260 || GET_CODE (SET_SRC (x)) != PLUS
3261 || XEXP (SET_SRC (x), 0) != dest
3262 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3264 reg_eliminate[i].can_eliminate_previous
3265 = reg_eliminate[i].can_eliminate = 0;
3270 /* Verify that the initial elimination offsets did not change since the
3271 last call to set_initial_elim_offsets. This is used to catch cases
3272 where something illegal happened during reload_as_needed that could
3273 cause incorrect code to be generated if we did not check for it. */
3276 verify_initial_elim_offsets (void)
3280 #ifdef ELIMINABLE_REGS
3281 struct elim_table *ep;
3283 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3285 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3286 if (t != ep->initial_offset)
3290 INITIAL_FRAME_POINTER_OFFSET (t);
3291 if (t != reg_eliminate[0].initial_offset)
3296 /* Reset all offsets on eliminable registers to their initial values. */
3299 set_initial_elim_offsets (void)
3301 struct elim_table *ep = reg_eliminate;
3303 #ifdef ELIMINABLE_REGS
3304 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3306 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3307 ep->previous_offset = ep->offset = ep->initial_offset;
3310 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3311 ep->previous_offset = ep->offset = ep->initial_offset;
3314 num_not_at_initial_offset = 0;
3317 /* Initialize the known label offsets.
3318 Set a known offset for each forced label to be at the initial offset
3319 of each elimination. We do this because we assume that all
3320 computed jumps occur from a location where each elimination is
3321 at its initial offset.
3322 For all other labels, show that we don't know the offsets. */
3325 set_initial_label_offsets (void)
3328 memset (offsets_known_at, 0, num_labels);
3330 for (x = forced_labels; x; x = XEXP (x, 1))
3332 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3335 /* Set all elimination offsets to the known values for the code label given
3339 set_offsets_for_label (rtx insn)
3342 int label_nr = CODE_LABEL_NUMBER (insn);
3343 struct elim_table *ep;
3345 num_not_at_initial_offset = 0;
3346 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3348 ep->offset = ep->previous_offset
3349 = offsets_at[label_nr - first_label_num][i];
3350 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3351 num_not_at_initial_offset++;
3355 /* See if anything that happened changes which eliminations are valid.
3356 For example, on the SPARC, whether or not the frame pointer can
3357 be eliminated can depend on what registers have been used. We need
3358 not check some conditions again (such as flag_omit_frame_pointer)
3359 since they can't have changed. */
3362 update_eliminables (HARD_REG_SET *pset)
3364 int previous_frame_pointer_needed = frame_pointer_needed;
3365 struct elim_table *ep;
3367 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3368 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3369 #ifdef ELIMINABLE_REGS
3370 || ! CAN_ELIMINATE (ep->from, ep->to)
3373 ep->can_eliminate = 0;
3375 /* Look for the case where we have discovered that we can't replace
3376 register A with register B and that means that we will now be
3377 trying to replace register A with register C. This means we can
3378 no longer replace register C with register B and we need to disable
3379 such an elimination, if it exists. This occurs often with A == ap,
3380 B == sp, and C == fp. */
3382 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3384 struct elim_table *op;
3387 if (! ep->can_eliminate && ep->can_eliminate_previous)
3389 /* Find the current elimination for ep->from, if there is a
3391 for (op = reg_eliminate;
3392 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3393 if (op->from == ep->from && op->can_eliminate)
3399 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3401 for (op = reg_eliminate;
3402 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3403 if (op->from == new_to && op->to == ep->to)
3404 op->can_eliminate = 0;
3408 /* See if any registers that we thought we could eliminate the previous
3409 time are no longer eliminable. If so, something has changed and we
3410 must spill the register. Also, recompute the number of eliminable
3411 registers and see if the frame pointer is needed; it is if there is
3412 no elimination of the frame pointer that we can perform. */
3414 frame_pointer_needed = 1;
3415 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3417 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3418 && ep->to != HARD_FRAME_POINTER_REGNUM)
3419 frame_pointer_needed = 0;
3421 if (! ep->can_eliminate && ep->can_eliminate_previous)
3423 ep->can_eliminate_previous = 0;
3424 SET_HARD_REG_BIT (*pset, ep->from);
3429 /* If we didn't need a frame pointer last time, but we do now, spill
3430 the hard frame pointer. */
3431 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3432 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3435 /* Initialize the table of registers to eliminate. */
3438 init_elim_table (void)
3440 struct elim_table *ep;
3441 #ifdef ELIMINABLE_REGS
3442 const struct elim_table_1 *ep1;
3446 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3448 /* Does this function require a frame pointer? */
3450 frame_pointer_needed = (! flag_omit_frame_pointer
3451 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3452 and restore sp for alloca. So we can't eliminate
3453 the frame pointer in that case. At some point,
3454 we should improve this by emitting the
3455 sp-adjusting insns for this case. */
3456 || (current_function_calls_alloca
3457 && EXIT_IGNORE_STACK)
3458 || FRAME_POINTER_REQUIRED);
3462 #ifdef ELIMINABLE_REGS
3463 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3464 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3466 ep->from = ep1->from;
3468 ep->can_eliminate = ep->can_eliminate_previous
3469 = (CAN_ELIMINATE (ep->from, ep->to)
3470 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3473 reg_eliminate[0].from = reg_eliminate_1[0].from;
3474 reg_eliminate[0].to = reg_eliminate_1[0].to;
3475 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3476 = ! frame_pointer_needed;
3479 /* Count the number of eliminable registers and build the FROM and TO
3480 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3481 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3482 We depend on this. */
3483 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3485 num_eliminable += ep->can_eliminate;
3486 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3487 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3491 /* Kick all pseudos out of hard register REGNO.
3493 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3494 because we found we can't eliminate some register. In the case, no pseudos
3495 are allowed to be in the register, even if they are only in a block that
3496 doesn't require spill registers, unlike the case when we are spilling this
3497 hard reg to produce another spill register.
3499 Return nonzero if any pseudos needed to be kicked out. */
3502 spill_hard_reg (unsigned int regno, int cant_eliminate)
3508 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3509 regs_ever_live[regno] = 1;
3512 /* Spill every pseudo reg that was allocated to this reg
3513 or to something that overlaps this reg. */
3515 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3516 if (reg_renumber[i] >= 0
3517 && (unsigned int) reg_renumber[i] <= regno
3518 && ((unsigned int) reg_renumber[i]
3519 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3520 PSEUDO_REGNO_MODE (i))
3522 SET_REGNO_REG_SET (&spilled_pseudos, i);
3525 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3526 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3529 ior_hard_reg_set (HARD_REG_SET *set1, HARD_REG_SET *set2)
3531 IOR_HARD_REG_SET (*set1, *set2);
3534 /* After find_reload_regs has been run for all insn that need reloads,
3535 and/or spill_hard_regs was called, this function is used to actually
3536 spill pseudo registers and try to reallocate them. It also sets up the
3537 spill_regs array for use by choose_reload_regs. */
3540 finish_spills (int global)
3542 struct insn_chain *chain;
3543 int something_changed = 0;
3546 /* Build the spill_regs array for the function. */
3547 /* If there are some registers still to eliminate and one of the spill regs
3548 wasn't ever used before, additional stack space may have to be
3549 allocated to store this register. Thus, we may have changed the offset
3550 between the stack and frame pointers, so mark that something has changed.
3552 One might think that we need only set VAL to 1 if this is a call-used
3553 register. However, the set of registers that must be saved by the
3554 prologue is not identical to the call-used set. For example, the
3555 register used by the call insn for the return PC is a call-used register,
3556 but must be saved by the prologue. */
3559 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3560 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3562 spill_reg_order[i] = n_spills;
3563 spill_regs[n_spills++] = i;
3564 if (num_eliminable && ! regs_ever_live[i])
3565 something_changed = 1;
3566 regs_ever_live[i] = 1;
3569 spill_reg_order[i] = -1;
3571 EXECUTE_IF_SET_IN_REG_SET
3572 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3574 /* Record the current hard register the pseudo is allocated to in
3575 pseudo_previous_regs so we avoid reallocating it to the same
3576 hard reg in a later pass. */
3577 if (reg_renumber[i] < 0)
3580 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3581 /* Mark it as no longer having a hard register home. */
3582 reg_renumber[i] = -1;
3583 /* We will need to scan everything again. */
3584 something_changed = 1;
3587 /* Retry global register allocation if possible. */
3590 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3591 /* For every insn that needs reloads, set the registers used as spill
3592 regs in pseudo_forbidden_regs for every pseudo live across the
3594 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3596 EXECUTE_IF_SET_IN_REG_SET
3597 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3599 ior_hard_reg_set (pseudo_forbidden_regs + i,
3600 &chain->used_spill_regs);
3602 EXECUTE_IF_SET_IN_REG_SET
3603 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3605 ior_hard_reg_set (pseudo_forbidden_regs + i,
3606 &chain->used_spill_regs);
3610 /* Retry allocating the spilled pseudos. For each reg, merge the
3611 various reg sets that indicate which hard regs can't be used,
3612 and call retry_global_alloc.
3613 We change spill_pseudos here to only contain pseudos that did not
3614 get a new hard register. */
3615 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3616 if (reg_old_renumber[i] != reg_renumber[i])
3618 HARD_REG_SET forbidden;
3619 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3620 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3621 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3622 retry_global_alloc (i, forbidden);
3623 if (reg_renumber[i] >= 0)
3624 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3628 /* Fix up the register information in the insn chain.
3629 This involves deleting those of the spilled pseudos which did not get
3630 a new hard register home from the live_{before,after} sets. */
3631 for (chain = reload_insn_chain; chain; chain = chain->next)
3633 HARD_REG_SET used_by_pseudos;
3634 HARD_REG_SET used_by_pseudos2;
3636 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3637 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3639 /* Mark any unallocated hard regs as available for spills. That
3640 makes inheritance work somewhat better. */
3641 if (chain->need_reload)
3643 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3644 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3645 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3647 /* Save the old value for the sanity test below. */
3648 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3650 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3651 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3652 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3653 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3655 /* Make sure we only enlarge the set. */
3656 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3662 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3663 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3665 int regno = reg_renumber[i];
3666 if (reg_old_renumber[i] == regno)
3669 alter_reg (i, reg_old_renumber[i]);
3670 reg_old_renumber[i] = regno;
3674 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3676 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3677 i, reg_renumber[i]);
3681 return something_changed;
3684 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3685 Also mark any hard registers used to store user variables as
3686 forbidden from being used for spill registers. */
3689 scan_paradoxical_subregs (rtx x)
3693 enum rtx_code code = GET_CODE (x);
3699 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3700 && REG_USERVAR_P (x))
3701 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3710 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3718 if (GET_CODE (SUBREG_REG (x)) == REG
3719 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3720 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3721 = GET_MODE_SIZE (GET_MODE (x));
3728 fmt = GET_RTX_FORMAT (code);
3729 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3732 scan_paradoxical_subregs (XEXP (x, i));
3733 else if (fmt[i] == 'E')
3736 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3737 scan_paradoxical_subregs (XVECEXP (x, i, j));
3742 /* Reload pseudo-registers into hard regs around each insn as needed.
3743 Additional register load insns are output before the insn that needs it
3744 and perhaps store insns after insns that modify the reloaded pseudo reg.
3746 reg_last_reload_reg and reg_reloaded_contents keep track of
3747 which registers are already available in reload registers.
3748 We update these for the reloads that we perform,
3749 as the insns are scanned. */
3752 reload_as_needed (int live_known)
3754 struct insn_chain *chain;
3755 #if defined (AUTO_INC_DEC)
3760 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3761 memset (spill_reg_store, 0, sizeof spill_reg_store);
3762 reg_last_reload_reg = xcalloc (max_regno, sizeof (rtx));
3763 reg_has_output_reload = xmalloc (max_regno);
3764 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3765 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3767 set_initial_elim_offsets ();
3769 for (chain = reload_insn_chain; chain; chain = chain->next)
3772 rtx insn = chain->insn;
3773 rtx old_next = NEXT_INSN (insn);
3775 /* If we pass a label, copy the offsets from the label information
3776 into the current offsets of each elimination. */
3777 if (GET_CODE (insn) == CODE_LABEL)
3778 set_offsets_for_label (insn);
3780 else if (INSN_P (insn))
3782 rtx oldpat = copy_rtx (PATTERN (insn));
3784 /* If this is a USE and CLOBBER of a MEM, ensure that any
3785 references to eliminable registers have been removed. */
3787 if ((GET_CODE (PATTERN (insn)) == USE
3788 || GET_CODE (PATTERN (insn)) == CLOBBER)
3789 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3790 XEXP (XEXP (PATTERN (insn), 0), 0)
3791 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3792 GET_MODE (XEXP (PATTERN (insn), 0)),
3795 /* If we need to do register elimination processing, do so.
3796 This might delete the insn, in which case we are done. */
3797 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3799 eliminate_regs_in_insn (insn, 1);
3800 if (GET_CODE (insn) == NOTE)
3802 update_eliminable_offsets ();
3807 /* If need_elim is nonzero but need_reload is zero, one might think
3808 that we could simply set n_reloads to 0. However, find_reloads
3809 could have done some manipulation of the insn (such as swapping
3810 commutative operands), and these manipulations are lost during
3811 the first pass for every insn that needs register elimination.
3812 So the actions of find_reloads must be redone here. */
3814 if (! chain->need_elim && ! chain->need_reload
3815 && ! chain->need_operand_change)
3817 /* First find the pseudo regs that must be reloaded for this insn.
3818 This info is returned in the tables reload_... (see reload.h).
3819 Also modify the body of INSN by substituting RELOAD
3820 rtx's for those pseudo regs. */
3823 memset (reg_has_output_reload, 0, max_regno);
3824 CLEAR_HARD_REG_SET (reg_is_output_reload);
3826 find_reloads (insn, 1, spill_indirect_levels, live_known,
3832 rtx next = NEXT_INSN (insn);
3835 prev = PREV_INSN (insn);
3837 /* Now compute which reload regs to reload them into. Perhaps
3838 reusing reload regs from previous insns, or else output
3839 load insns to reload them. Maybe output store insns too.
3840 Record the choices of reload reg in reload_reg_rtx. */
3841 choose_reload_regs (chain);
3843 /* Merge any reloads that we didn't combine for fear of
3844 increasing the number of spill registers needed but now
3845 discover can be safely merged. */
3846 if (SMALL_REGISTER_CLASSES)
3847 merge_assigned_reloads (insn);
3849 /* Generate the insns to reload operands into or out of
3850 their reload regs. */
3851 emit_reload_insns (chain);
3853 /* Substitute the chosen reload regs from reload_reg_rtx
3854 into the insn's body (or perhaps into the bodies of other
3855 load and store insn that we just made for reloading
3856 and that we moved the structure into). */
3857 subst_reloads (insn);
3859 /* If this was an ASM, make sure that all the reload insns
3860 we have generated are valid. If not, give an error
3863 if (asm_noperands (PATTERN (insn)) >= 0)
3864 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3865 if (p != insn && INSN_P (p)
3866 && GET_CODE (PATTERN (p)) != USE
3867 && (recog_memoized (p) < 0
3868 || (extract_insn (p), ! constrain_operands (1))))
3870 error_for_asm (insn,
3871 "`asm' operand requires impossible reload");
3876 if (num_eliminable && chain->need_elim)
3877 update_eliminable_offsets ();
3879 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3880 is no longer validly lying around to save a future reload.
3881 Note that this does not detect pseudos that were reloaded
3882 for this insn in order to be stored in
3883 (obeying register constraints). That is correct; such reload
3884 registers ARE still valid. */
3885 note_stores (oldpat, forget_old_reloads_1, NULL);
3887 /* There may have been CLOBBER insns placed after INSN. So scan
3888 between INSN and NEXT and use them to forget old reloads. */
3889 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3890 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3891 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3894 /* Likewise for regs altered by auto-increment in this insn.
3895 REG_INC notes have been changed by reloading:
3896 find_reloads_address_1 records substitutions for them,
3897 which have been performed by subst_reloads above. */
3898 for (i = n_reloads - 1; i >= 0; i--)
3900 rtx in_reg = rld[i].in_reg;
3903 enum rtx_code code = GET_CODE (in_reg);
3904 /* PRE_INC / PRE_DEC will have the reload register ending up
3905 with the same value as the stack slot, but that doesn't
3906 hold true for POST_INC / POST_DEC. Either we have to
3907 convert the memory access to a true POST_INC / POST_DEC,
3908 or we can't use the reload register for inheritance. */
3909 if ((code == POST_INC || code == POST_DEC)
3910 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3911 REGNO (rld[i].reg_rtx))
3912 /* Make sure it is the inc/dec pseudo, and not
3913 some other (e.g. output operand) pseudo. */
3914 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3915 == REGNO (XEXP (in_reg, 0))))
3918 rtx reload_reg = rld[i].reg_rtx;
3919 enum machine_mode mode = GET_MODE (reload_reg);
3923 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3925 /* We really want to ignore REG_INC notes here, so
3926 use PATTERN (p) as argument to reg_set_p . */
3927 if (reg_set_p (reload_reg, PATTERN (p)))
3929 n = count_occurrences (PATTERN (p), reload_reg, 0);
3934 n = validate_replace_rtx (reload_reg,
3935 gen_rtx (code, mode,
3939 /* We must also verify that the constraints
3940 are met after the replacement. */
3943 n = constrain_operands (1);
3947 /* If the constraints were not met, then
3948 undo the replacement. */
3951 validate_replace_rtx (gen_rtx (code, mode,
3963 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3965 /* Mark this as having an output reload so that the
3966 REG_INC processing code below won't invalidate
3967 the reload for inheritance. */
3968 SET_HARD_REG_BIT (reg_is_output_reload,
3969 REGNO (reload_reg));
3970 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3973 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3976 else if ((code == PRE_INC || code == PRE_DEC)
3977 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3978 REGNO (rld[i].reg_rtx))
3979 /* Make sure it is the inc/dec pseudo, and not
3980 some other (e.g. output operand) pseudo. */
3981 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3982 == REGNO (XEXP (in_reg, 0))))
3984 SET_HARD_REG_BIT (reg_is_output_reload,
3985 REGNO (rld[i].reg_rtx));
3986 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3990 /* If a pseudo that got a hard register is auto-incremented,
3991 we must purge records of copying it into pseudos without
3993 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3994 if (REG_NOTE_KIND (x) == REG_INC)
3996 /* See if this pseudo reg was reloaded in this insn.
3997 If so, its last-reload info is still valid
3998 because it is based on this insn's reload. */
3999 for (i = 0; i < n_reloads; i++)
4000 if (rld[i].out == XEXP (x, 0))
4004 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4008 /* A reload reg's contents are unknown after a label. */
4009 if (GET_CODE (insn) == CODE_LABEL)
4010 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4012 /* Don't assume a reload reg is still good after a call insn
4013 if it is a call-used reg, or if it contains a value that will
4014 be partially clobbered by the call. */
4015 else if (GET_CODE (insn) == CALL_INSN)
4017 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4018 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4023 free (reg_last_reload_reg);
4024 free (reg_has_output_reload);
4027 /* Discard all record of any value reloaded from X,
4028 or reloaded in X from someplace else;
4029 unless X is an output reload reg of the current insn.
4031 X may be a hard reg (the reload reg)
4032 or it may be a pseudo reg that was reloaded from. */
4035 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4036 void *data ATTRIBUTE_UNUSED)
4041 /* note_stores does give us subregs of hard regs,
4042 subreg_regno_offset will abort if it is not a hard reg. */
4043 while (GET_CODE (x) == SUBREG)
4045 /* We ignore the subreg offset when calculating the regno,
4046 because we are using the entire underlying hard register
4051 if (GET_CODE (x) != REG)
4056 if (regno >= FIRST_PSEUDO_REGISTER)
4062 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4063 /* Storing into a spilled-reg invalidates its contents.
4064 This can happen if a block-local pseudo is allocated to that reg
4065 and it wasn't spilled because this block's total need is 0.
4066 Then some insn might have an optional reload and use this reg. */
4067 for (i = 0; i < nr; i++)
4068 /* But don't do this if the reg actually serves as an output
4069 reload reg in the current instruction. */
4071 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4073 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4074 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4075 spill_reg_store[regno + i] = 0;
4079 /* Since value of X has changed,
4080 forget any value previously copied from it. */
4083 /* But don't forget a copy if this is the output reload
4084 that establishes the copy's validity. */
4085 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4086 reg_last_reload_reg[regno + nr] = 0;
4089 /* The following HARD_REG_SETs indicate when each hard register is
4090 used for a reload of various parts of the current insn. */
4092 /* If reg is unavailable for all reloads. */
4093 static HARD_REG_SET reload_reg_unavailable;
4094 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4095 static HARD_REG_SET reload_reg_used;
4096 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4097 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4098 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4099 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4100 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4101 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4102 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4103 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4104 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4105 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4106 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4107 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4108 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4109 static HARD_REG_SET reload_reg_used_in_op_addr;
4110 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4111 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4112 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4113 static HARD_REG_SET reload_reg_used_in_insn;
4114 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4115 static HARD_REG_SET reload_reg_used_in_other_addr;
4117 /* If reg is in use as a reload reg for any sort of reload. */
4118 static HARD_REG_SET reload_reg_used_at_all;
4120 /* If reg is use as an inherited reload. We just mark the first register
4122 static HARD_REG_SET reload_reg_used_for_inherit;
4124 /* Records which hard regs are used in any way, either as explicit use or
4125 by being allocated to a pseudo during any point of the current insn. */
4126 static HARD_REG_SET reg_used_in_insn;
4128 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4129 TYPE. MODE is used to indicate how many consecutive regs are
4133 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4134 enum machine_mode mode)
4136 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4139 for (i = regno; i < nregs + regno; i++)
4144 SET_HARD_REG_BIT (reload_reg_used, i);
4147 case RELOAD_FOR_INPUT_ADDRESS:
4148 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4151 case RELOAD_FOR_INPADDR_ADDRESS:
4152 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4155 case RELOAD_FOR_OUTPUT_ADDRESS:
4156 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4159 case RELOAD_FOR_OUTADDR_ADDRESS:
4160 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4163 case RELOAD_FOR_OPERAND_ADDRESS:
4164 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4167 case RELOAD_FOR_OPADDR_ADDR:
4168 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4171 case RELOAD_FOR_OTHER_ADDRESS:
4172 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4175 case RELOAD_FOR_INPUT:
4176 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4179 case RELOAD_FOR_OUTPUT:
4180 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4183 case RELOAD_FOR_INSN:
4184 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4188 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4192 /* Similarly, but show REGNO is no longer in use for a reload. */
4195 clear_reload_reg_in_use (unsigned int regno, int opnum,
4196 enum reload_type type, enum machine_mode mode)
4198 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4199 unsigned int start_regno, end_regno, r;
4201 /* A complication is that for some reload types, inheritance might
4202 allow multiple reloads of the same types to share a reload register.
4203 We set check_opnum if we have to check only reloads with the same
4204 operand number, and check_any if we have to check all reloads. */
4205 int check_opnum = 0;
4207 HARD_REG_SET *used_in_set;
4212 used_in_set = &reload_reg_used;
4215 case RELOAD_FOR_INPUT_ADDRESS:
4216 used_in_set = &reload_reg_used_in_input_addr[opnum];
4219 case RELOAD_FOR_INPADDR_ADDRESS:
4221 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4224 case RELOAD_FOR_OUTPUT_ADDRESS:
4225 used_in_set = &reload_reg_used_in_output_addr[opnum];
4228 case RELOAD_FOR_OUTADDR_ADDRESS:
4230 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4233 case RELOAD_FOR_OPERAND_ADDRESS:
4234 used_in_set = &reload_reg_used_in_op_addr;
4237 case RELOAD_FOR_OPADDR_ADDR:
4239 used_in_set = &reload_reg_used_in_op_addr_reload;
4242 case RELOAD_FOR_OTHER_ADDRESS:
4243 used_in_set = &reload_reg_used_in_other_addr;
4247 case RELOAD_FOR_INPUT:
4248 used_in_set = &reload_reg_used_in_input[opnum];
4251 case RELOAD_FOR_OUTPUT:
4252 used_in_set = &reload_reg_used_in_output[opnum];
4255 case RELOAD_FOR_INSN:
4256 used_in_set = &reload_reg_used_in_insn;
4261 /* We resolve conflicts with remaining reloads of the same type by
4262 excluding the intervals of reload registers by them from the
4263 interval of freed reload registers. Since we only keep track of
4264 one set of interval bounds, we might have to exclude somewhat
4265 more than what would be necessary if we used a HARD_REG_SET here.
4266 But this should only happen very infrequently, so there should
4267 be no reason to worry about it. */
4269 start_regno = regno;
4270 end_regno = regno + nregs;
4271 if (check_opnum || check_any)
4273 for (i = n_reloads - 1; i >= 0; i--)
4275 if (rld[i].when_needed == type
4276 && (check_any || rld[i].opnum == opnum)
4279 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4280 unsigned int conflict_end
4282 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4284 /* If there is an overlap with the first to-be-freed register,
4285 adjust the interval start. */
4286 if (conflict_start <= start_regno && conflict_end > start_regno)
4287 start_regno = conflict_end;
4288 /* Otherwise, if there is a conflict with one of the other
4289 to-be-freed registers, adjust the interval end. */
4290 if (conflict_start > start_regno && conflict_start < end_regno)
4291 end_regno = conflict_start;
4296 for (r = start_regno; r < end_regno; r++)
4297 CLEAR_HARD_REG_BIT (*used_in_set, r);
4300 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4301 specified by OPNUM and TYPE. */
4304 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4308 /* In use for a RELOAD_OTHER means it's not available for anything. */
4309 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4310 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4316 /* In use for anything means we can't use it for RELOAD_OTHER. */
4317 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4318 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4319 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4320 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4323 for (i = 0; i < reload_n_operands; i++)
4324 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4325 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4326 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4327 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4328 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4329 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4334 case RELOAD_FOR_INPUT:
4335 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4336 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4339 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4342 /* If it is used for some other input, can't use it. */
4343 for (i = 0; i < reload_n_operands; i++)
4344 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4347 /* If it is used in a later operand's address, can't use it. */
4348 for (i = opnum + 1; i < reload_n_operands; i++)
4349 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4350 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4355 case RELOAD_FOR_INPUT_ADDRESS:
4356 /* Can't use a register if it is used for an input address for this
4357 operand or used as an input in an earlier one. */
4358 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4359 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4362 for (i = 0; i < opnum; i++)
4363 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4368 case RELOAD_FOR_INPADDR_ADDRESS:
4369 /* Can't use a register if it is used for an input address
4370 for this operand or used as an input in an earlier
4372 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4375 for (i = 0; i < opnum; i++)
4376 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4381 case RELOAD_FOR_OUTPUT_ADDRESS:
4382 /* Can't use a register if it is used for an output address for this
4383 operand or used as an output in this or a later operand. Note
4384 that multiple output operands are emitted in reverse order, so
4385 the conflicting ones are those with lower indices. */
4386 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4389 for (i = 0; i <= opnum; i++)
4390 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4395 case RELOAD_FOR_OUTADDR_ADDRESS:
4396 /* Can't use a register if it is used for an output address
4397 for this operand or used as an output in this or a
4398 later operand. Note that multiple output operands are
4399 emitted in reverse order, so the conflicting ones are
4400 those with lower indices. */
4401 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4404 for (i = 0; i <= opnum; i++)
4405 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4410 case RELOAD_FOR_OPERAND_ADDRESS:
4411 for (i = 0; i < reload_n_operands; i++)
4412 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4415 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4416 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4418 case RELOAD_FOR_OPADDR_ADDR:
4419 for (i = 0; i < reload_n_operands; i++)
4420 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4423 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4425 case RELOAD_FOR_OUTPUT:
4426 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4427 outputs, or an operand address for this or an earlier output.
4428 Note that multiple output operands are emitted in reverse order,
4429 so the conflicting ones are those with higher indices. */
4430 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4433 for (i = 0; i < reload_n_operands; i++)
4434 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4437 for (i = opnum; i < reload_n_operands; i++)
4438 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4439 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4444 case RELOAD_FOR_INSN:
4445 for (i = 0; i < reload_n_operands; i++)
4446 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4447 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4450 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4451 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4453 case RELOAD_FOR_OTHER_ADDRESS:
4454 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4459 /* Return 1 if the value in reload reg REGNO, as used by a reload
4460 needed for the part of the insn specified by OPNUM and TYPE,
4461 is still available in REGNO at the end of the insn.
4463 We can assume that the reload reg was already tested for availability
4464 at the time it is needed, and we should not check this again,
4465 in case the reg has already been marked in use. */
4468 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4475 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4476 its value must reach the end. */
4479 /* If this use is for part of the insn,
4480 its value reaches if no subsequent part uses the same register.
4481 Just like the above function, don't try to do this with lots
4484 case RELOAD_FOR_OTHER_ADDRESS:
4485 /* Here we check for everything else, since these don't conflict
4486 with anything else and everything comes later. */
4488 for (i = 0; i < reload_n_operands; i++)
4489 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4490 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4491 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4492 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4493 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4494 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4497 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4498 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4499 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4500 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4502 case RELOAD_FOR_INPUT_ADDRESS:
4503 case RELOAD_FOR_INPADDR_ADDRESS:
4504 /* Similar, except that we check only for this and subsequent inputs
4505 and the address of only subsequent inputs and we do not need
4506 to check for RELOAD_OTHER objects since they are known not to
4509 for (i = opnum; i < reload_n_operands; i++)
4510 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4513 for (i = opnum + 1; i < reload_n_operands; i++)
4514 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4515 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4518 for (i = 0; i < reload_n_operands; i++)
4519 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4520 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4521 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4524 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4527 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4528 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4529 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4531 case RELOAD_FOR_INPUT:
4532 /* Similar to input address, except we start at the next operand for
4533 both input and input address and we do not check for
4534 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4537 for (i = opnum + 1; i < reload_n_operands; i++)
4538 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4539 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4540 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4543 /* ... fall through ... */
4545 case RELOAD_FOR_OPERAND_ADDRESS:
4546 /* Check outputs and their addresses. */
4548 for (i = 0; i < reload_n_operands; i++)
4549 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4550 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4551 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4554 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4556 case RELOAD_FOR_OPADDR_ADDR:
4557 for (i = 0; i < reload_n_operands; i++)
4558 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4559 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4560 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4563 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4564 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4565 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4567 case RELOAD_FOR_INSN:
4568 /* These conflict with other outputs with RELOAD_OTHER. So
4569 we need only check for output addresses. */
4571 opnum = reload_n_operands;
4573 /* ... fall through ... */
4575 case RELOAD_FOR_OUTPUT:
4576 case RELOAD_FOR_OUTPUT_ADDRESS:
4577 case RELOAD_FOR_OUTADDR_ADDRESS:
4578 /* We already know these can't conflict with a later output. So the
4579 only thing to check are later output addresses.
4580 Note that multiple output operands are emitted in reverse order,
4581 so the conflicting ones are those with lower indices. */
4582 for (i = 0; i < opnum; i++)
4583 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4584 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4593 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4596 This function uses the same algorithm as reload_reg_free_p above. */
4599 reloads_conflict (int r1, int r2)
4601 enum reload_type r1_type = rld[r1].when_needed;
4602 enum reload_type r2_type = rld[r2].when_needed;
4603 int r1_opnum = rld[r1].opnum;
4604 int r2_opnum = rld[r2].opnum;
4606 /* RELOAD_OTHER conflicts with everything. */
4607 if (r2_type == RELOAD_OTHER)
4610 /* Otherwise, check conflicts differently for each type. */
4614 case RELOAD_FOR_INPUT:
4615 return (r2_type == RELOAD_FOR_INSN
4616 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4617 || r2_type == RELOAD_FOR_OPADDR_ADDR
4618 || r2_type == RELOAD_FOR_INPUT
4619 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4620 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4621 && r2_opnum > r1_opnum));
4623 case RELOAD_FOR_INPUT_ADDRESS:
4624 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4625 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4627 case RELOAD_FOR_INPADDR_ADDRESS:
4628 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4629 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4631 case RELOAD_FOR_OUTPUT_ADDRESS:
4632 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4633 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4635 case RELOAD_FOR_OUTADDR_ADDRESS:
4636 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4637 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4639 case RELOAD_FOR_OPERAND_ADDRESS:
4640 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4641 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4643 case RELOAD_FOR_OPADDR_ADDR:
4644 return (r2_type == RELOAD_FOR_INPUT
4645 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4647 case RELOAD_FOR_OUTPUT:
4648 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4649 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4650 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4651 && r2_opnum >= r1_opnum));
4653 case RELOAD_FOR_INSN:
4654 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4655 || r2_type == RELOAD_FOR_INSN
4656 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4658 case RELOAD_FOR_OTHER_ADDRESS:
4659 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4669 /* Indexed by reload number, 1 if incoming value
4670 inherited from previous insns. */
4671 char reload_inherited[MAX_RELOADS];
4673 /* For an inherited reload, this is the insn the reload was inherited from,
4674 if we know it. Otherwise, this is 0. */
4675 rtx reload_inheritance_insn[MAX_RELOADS];
4677 /* If nonzero, this is a place to get the value of the reload,
4678 rather than using reload_in. */
4679 rtx reload_override_in[MAX_RELOADS];
4681 /* For each reload, the hard register number of the register used,
4682 or -1 if we did not need a register for this reload. */
4683 int reload_spill_index[MAX_RELOADS];
4685 /* Subroutine of free_for_value_p, used to check a single register.
4686 START_REGNO is the starting regno of the full reload register
4687 (possibly comprising multiple hard registers) that we are considering. */
4690 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4691 enum reload_type type, rtx value, rtx out,
4692 int reloadnum, int ignore_address_reloads)
4695 /* Set if we see an input reload that must not share its reload register
4696 with any new earlyclobber, but might otherwise share the reload
4697 register with an output or input-output reload. */
4698 int check_earlyclobber = 0;
4702 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4705 if (out == const0_rtx)
4711 /* We use some pseudo 'time' value to check if the lifetimes of the
4712 new register use would overlap with the one of a previous reload
4713 that is not read-only or uses a different value.
4714 The 'time' used doesn't have to be linear in any shape or form, just
4716 Some reload types use different 'buckets' for each operand.
4717 So there are MAX_RECOG_OPERANDS different time values for each
4719 We compute TIME1 as the time when the register for the prospective
4720 new reload ceases to be live, and TIME2 for each existing
4721 reload as the time when that the reload register of that reload
4723 Where there is little to be gained by exact lifetime calculations,
4724 we just make conservative assumptions, i.e. a longer lifetime;
4725 this is done in the 'default:' cases. */
4728 case RELOAD_FOR_OTHER_ADDRESS:
4729 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4730 time1 = copy ? 0 : 1;
4733 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4735 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4736 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4737 respectively, to the time values for these, we get distinct time
4738 values. To get distinct time values for each operand, we have to
4739 multiply opnum by at least three. We round that up to four because
4740 multiply by four is often cheaper. */
4741 case RELOAD_FOR_INPADDR_ADDRESS:
4742 time1 = opnum * 4 + 2;
4744 case RELOAD_FOR_INPUT_ADDRESS:
4745 time1 = opnum * 4 + 3;
4747 case RELOAD_FOR_INPUT:
4748 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4749 executes (inclusive). */
4750 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4752 case RELOAD_FOR_OPADDR_ADDR:
4754 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4755 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4757 case RELOAD_FOR_OPERAND_ADDRESS:
4758 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4760 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4762 case RELOAD_FOR_OUTADDR_ADDRESS:
4763 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4765 case RELOAD_FOR_OUTPUT_ADDRESS:
4766 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4769 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4772 for (i = 0; i < n_reloads; i++)
4774 rtx reg = rld[i].reg_rtx;
4775 if (reg && GET_CODE (reg) == REG
4776 && ((unsigned) regno - true_regnum (reg)
4777 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned) 1)
4780 rtx other_input = rld[i].in;
4782 /* If the other reload loads the same input value, that
4783 will not cause a conflict only if it's loading it into
4784 the same register. */
4785 if (true_regnum (reg) != start_regno)
4786 other_input = NULL_RTX;
4787 if (! other_input || ! rtx_equal_p (other_input, value)
4788 || rld[i].out || out)
4791 switch (rld[i].when_needed)
4793 case RELOAD_FOR_OTHER_ADDRESS:
4796 case RELOAD_FOR_INPADDR_ADDRESS:
4797 /* find_reloads makes sure that a
4798 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4799 by at most one - the first -
4800 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4801 address reload is inherited, the address address reload
4802 goes away, so we can ignore this conflict. */
4803 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4804 && ignore_address_reloads
4805 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4806 Then the address address is still needed to store
4807 back the new address. */
4808 && ! rld[reloadnum].out)
4810 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4811 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4813 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4814 && ignore_address_reloads
4815 /* Unless we are reloading an auto_inc expression. */
4816 && ! rld[reloadnum].out)
4818 time2 = rld[i].opnum * 4 + 2;
4820 case RELOAD_FOR_INPUT_ADDRESS:
4821 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4822 && ignore_address_reloads
4823 && ! rld[reloadnum].out)
4825 time2 = rld[i].opnum * 4 + 3;
4827 case RELOAD_FOR_INPUT:
4828 time2 = rld[i].opnum * 4 + 4;
4829 check_earlyclobber = 1;
4831 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4832 == MAX_RECOG_OPERAND * 4 */
4833 case RELOAD_FOR_OPADDR_ADDR:
4834 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4835 && ignore_address_reloads
4836 && ! rld[reloadnum].out)
4838 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4840 case RELOAD_FOR_OPERAND_ADDRESS:
4841 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4842 check_earlyclobber = 1;
4844 case RELOAD_FOR_INSN:
4845 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4847 case RELOAD_FOR_OUTPUT:
4848 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4849 instruction is executed. */
4850 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4852 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4853 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4855 case RELOAD_FOR_OUTADDR_ADDRESS:
4856 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4857 && ignore_address_reloads
4858 && ! rld[reloadnum].out)
4860 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4862 case RELOAD_FOR_OUTPUT_ADDRESS:
4863 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4866 /* If there is no conflict in the input part, handle this
4867 like an output reload. */
4868 if (! rld[i].in || rtx_equal_p (other_input, value))
4870 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4871 /* Earlyclobbered outputs must conflict with inputs. */
4872 if (earlyclobber_operand_p (rld[i].out))
4873 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4878 /* RELOAD_OTHER might be live beyond instruction execution,
4879 but this is not obvious when we set time2 = 1. So check
4880 here if there might be a problem with the new reload
4881 clobbering the register used by the RELOAD_OTHER. */
4889 && (! rld[i].in || rld[i].out
4890 || ! rtx_equal_p (other_input, value)))
4891 || (out && rld[reloadnum].out_reg
4892 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4898 /* Earlyclobbered outputs must conflict with inputs. */
4899 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4905 /* Return 1 if the value in reload reg REGNO, as used by a reload
4906 needed for the part of the insn specified by OPNUM and TYPE,
4907 may be used to load VALUE into it.
4909 MODE is the mode in which the register is used, this is needed to
4910 determine how many hard regs to test.
4912 Other read-only reloads with the same value do not conflict
4913 unless OUT is nonzero and these other reloads have to live while
4914 output reloads live.
4915 If OUT is CONST0_RTX, this is a special case: it means that the
4916 test should not be for using register REGNO as reload register, but
4917 for copying from register REGNO into the reload register.
4919 RELOADNUM is the number of the reload we want to load this value for;
4920 a reload does not conflict with itself.
4922 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4923 reloads that load an address for the very reload we are considering.
4925 The caller has to make sure that there is no conflict with the return
4929 free_for_value_p (int regno, enum machine_mode mode, int opnum,
4930 enum reload_type type, rtx value, rtx out, int reloadnum,
4931 int ignore_address_reloads)
4933 int nregs = HARD_REGNO_NREGS (regno, mode);
4935 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4936 value, out, reloadnum,
4937 ignore_address_reloads))
4942 /* Determine whether the reload reg X overlaps any rtx'es used for
4943 overriding inheritance. Return nonzero if so. */
4946 conflicts_with_override (rtx x)
4949 for (i = 0; i < n_reloads; i++)
4950 if (reload_override_in[i]
4951 && reg_overlap_mentioned_p (x, reload_override_in[i]))
4956 /* Give an error message saying we failed to find a reload for INSN,
4957 and clear out reload R. */
4959 failed_reload (rtx insn, int r)
4961 if (asm_noperands (PATTERN (insn)) < 0)
4962 /* It's the compiler's fault. */
4963 fatal_insn ("could not find a spill register", insn);
4965 /* It's the user's fault; the operand's mode and constraint
4966 don't match. Disable this reload so we don't crash in final. */
4967 error_for_asm (insn,
4968 "`asm' operand constraint incompatible with operand size");
4972 rld[r].optional = 1;
4973 rld[r].secondary_p = 1;
4976 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
4977 for reload R. If it's valid, get an rtx for it. Return nonzero if
4980 set_reload_reg (int i, int r)
4983 rtx reg = spill_reg_rtx[i];
4985 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
4986 spill_reg_rtx[i] = reg
4987 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
4989 regno = true_regnum (reg);
4991 /* Detect when the reload reg can't hold the reload mode.
4992 This used to be one `if', but Sequent compiler can't handle that. */
4993 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
4995 enum machine_mode test_mode = VOIDmode;
4997 test_mode = GET_MODE (rld[r].in);
4998 /* If rld[r].in has VOIDmode, it means we will load it
4999 in whatever mode the reload reg has: to wit, rld[r].mode.
5000 We have already tested that for validity. */
5001 /* Aside from that, we need to test that the expressions
5002 to reload from or into have modes which are valid for this
5003 reload register. Otherwise the reload insns would be invalid. */
5004 if (! (rld[r].in != 0 && test_mode != VOIDmode
5005 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5006 if (! (rld[r].out != 0
5007 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5009 /* The reg is OK. */
5012 /* Mark as in use for this insn the reload regs we use
5014 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5015 rld[r].when_needed, rld[r].mode);
5017 rld[r].reg_rtx = reg;
5018 reload_spill_index[r] = spill_regs[i];
5025 /* Find a spill register to use as a reload register for reload R.
5026 LAST_RELOAD is nonzero if this is the last reload for the insn being
5029 Set rld[R].reg_rtx to the register allocated.
5031 We return 1 if successful, or 0 if we couldn't find a spill reg and
5032 we didn't change anything. */
5035 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5040 /* If we put this reload ahead, thinking it is a group,
5041 then insist on finding a group. Otherwise we can grab a
5042 reg that some other reload needs.
5043 (That can happen when we have a 68000 DATA_OR_FP_REG
5044 which is a group of data regs or one fp reg.)
5045 We need not be so restrictive if there are no more reloads
5048 ??? Really it would be nicer to have smarter handling
5049 for that kind of reg class, where a problem like this is normal.
5050 Perhaps those classes should be avoided for reloading
5051 by use of more alternatives. */
5053 int force_group = rld[r].nregs > 1 && ! last_reload;
5055 /* If we want a single register and haven't yet found one,
5056 take any reg in the right class and not in use.
5057 If we want a consecutive group, here is where we look for it.
5059 We use two passes so we can first look for reload regs to
5060 reuse, which are already in use for other reloads in this insn,
5061 and only then use additional registers.
5062 I think that maximizing reuse is needed to make sure we don't
5063 run out of reload regs. Suppose we have three reloads, and
5064 reloads A and B can share regs. These need two regs.
5065 Suppose A and B are given different regs.
5066 That leaves none for C. */
5067 for (pass = 0; pass < 2; pass++)
5069 /* I is the index in spill_regs.
5070 We advance it round-robin between insns to use all spill regs
5071 equally, so that inherited reloads have a chance
5072 of leapfrogging each other. */
5076 for (count = 0; count < n_spills; count++)
5078 int class = (int) rld[r].class;
5084 regnum = spill_regs[i];
5086 if ((reload_reg_free_p (regnum, rld[r].opnum,
5089 /* We check reload_reg_used to make sure we
5090 don't clobber the return register. */
5091 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5092 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5093 rld[r].when_needed, rld[r].in,
5095 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5096 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5097 /* Look first for regs to share, then for unshared. But
5098 don't share regs used for inherited reloads; they are
5099 the ones we want to preserve. */
5101 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5103 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5106 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5107 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5108 (on 68000) got us two FP regs. If NR is 1,
5109 we would reject both of them. */
5112 /* If we need only one reg, we have already won. */
5115 /* But reject a single reg if we demand a group. */
5120 /* Otherwise check that as many consecutive regs as we need
5121 are available here. */
5124 int regno = regnum + nr - 1;
5125 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5126 && spill_reg_order[regno] >= 0
5127 && reload_reg_free_p (regno, rld[r].opnum,
5128 rld[r].when_needed)))
5137 /* If we found something on pass 1, omit pass 2. */
5138 if (count < n_spills)
5142 /* We should have found a spill register by now. */
5143 if (count >= n_spills)
5146 /* I is the index in SPILL_REG_RTX of the reload register we are to
5147 allocate. Get an rtx for it and find its register number. */
5149 return set_reload_reg (i, r);
5152 /* Initialize all the tables needed to allocate reload registers.
5153 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5154 is the array we use to restore the reg_rtx field for every reload. */
5157 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5161 for (i = 0; i < n_reloads; i++)
5162 rld[i].reg_rtx = save_reload_reg_rtx[i];
5164 memset (reload_inherited, 0, MAX_RELOADS);
5165 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5166 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5168 CLEAR_HARD_REG_SET (reload_reg_used);
5169 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5170 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5171 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5172 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5173 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5175 CLEAR_HARD_REG_SET (reg_used_in_insn);
5178 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5179 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5180 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5181 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5182 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5183 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5186 for (i = 0; i < reload_n_operands; i++)
5188 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5189 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5190 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5191 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5192 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5193 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5196 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5198 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5200 for (i = 0; i < n_reloads; i++)
5201 /* If we have already decided to use a certain register,
5202 don't use it in another way. */
5204 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5205 rld[i].when_needed, rld[i].mode);
5208 /* Assign hard reg targets for the pseudo-registers we must reload
5209 into hard regs for this insn.
5210 Also output the instructions to copy them in and out of the hard regs.
5212 For machines with register classes, we are responsible for
5213 finding a reload reg in the proper class. */
5216 choose_reload_regs (struct insn_chain *chain)
5218 rtx insn = chain->insn;
5220 unsigned int max_group_size = 1;
5221 enum reg_class group_class = NO_REGS;
5222 int pass, win, inheritance;
5224 rtx save_reload_reg_rtx[MAX_RELOADS];
5226 /* In order to be certain of getting the registers we need,
5227 we must sort the reloads into order of increasing register class.
5228 Then our grabbing of reload registers will parallel the process
5229 that provided the reload registers.
5231 Also note whether any of the reloads wants a consecutive group of regs.
5232 If so, record the maximum size of the group desired and what
5233 register class contains all the groups needed by this insn. */
5235 for (j = 0; j < n_reloads; j++)
5237 reload_order[j] = j;
5238 reload_spill_index[j] = -1;
5240 if (rld[j].nregs > 1)
5242 max_group_size = MAX (rld[j].nregs, max_group_size);
5244 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5247 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5251 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5253 /* If -O, try first with inheritance, then turning it off.
5254 If not -O, don't do inheritance.
5255 Using inheritance when not optimizing leads to paradoxes
5256 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5257 because one side of the comparison might be inherited. */
5259 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5261 choose_reload_regs_init (chain, save_reload_reg_rtx);
5263 /* Process the reloads in order of preference just found.
5264 Beyond this point, subregs can be found in reload_reg_rtx.
5266 This used to look for an existing reloaded home for all of the
5267 reloads, and only then perform any new reloads. But that could lose
5268 if the reloads were done out of reg-class order because a later
5269 reload with a looser constraint might have an old home in a register
5270 needed by an earlier reload with a tighter constraint.
5272 To solve this, we make two passes over the reloads, in the order
5273 described above. In the first pass we try to inherit a reload
5274 from a previous insn. If there is a later reload that needs a
5275 class that is a proper subset of the class being processed, we must
5276 also allocate a spill register during the first pass.
5278 Then make a second pass over the reloads to allocate any reloads
5279 that haven't been given registers yet. */
5281 for (j = 0; j < n_reloads; j++)
5283 int r = reload_order[j];
5284 rtx search_equiv = NULL_RTX;
5286 /* Ignore reloads that got marked inoperative. */
5287 if (rld[r].out == 0 && rld[r].in == 0
5288 && ! rld[r].secondary_p)
5291 /* If find_reloads chose to use reload_in or reload_out as a reload
5292 register, we don't need to chose one. Otherwise, try even if it
5293 found one since we might save an insn if we find the value lying
5295 Try also when reload_in is a pseudo without a hard reg. */
5296 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5297 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5298 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5299 && GET_CODE (rld[r].in) != MEM
5300 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5303 #if 0 /* No longer needed for correct operation.
5304 It might give better code, or might not; worth an experiment? */
5305 /* If this is an optional reload, we can't inherit from earlier insns
5306 until we are sure that any non-optional reloads have been allocated.
5307 The following code takes advantage of the fact that optional reloads
5308 are at the end of reload_order. */
5309 if (rld[r].optional != 0)
5310 for (i = 0; i < j; i++)
5311 if ((rld[reload_order[i]].out != 0
5312 || rld[reload_order[i]].in != 0
5313 || rld[reload_order[i]].secondary_p)
5314 && ! rld[reload_order[i]].optional
5315 && rld[reload_order[i]].reg_rtx == 0)
5316 allocate_reload_reg (chain, reload_order[i], 0);
5319 /* First see if this pseudo is already available as reloaded
5320 for a previous insn. We cannot try to inherit for reloads
5321 that are smaller than the maximum number of registers needed
5322 for groups unless the register we would allocate cannot be used
5325 We could check here to see if this is a secondary reload for
5326 an object that is already in a register of the desired class.
5327 This would avoid the need for the secondary reload register.
5328 But this is complex because we can't easily determine what
5329 objects might want to be loaded via this reload. So let a
5330 register be allocated here. In `emit_reload_insns' we suppress
5331 one of the loads in the case described above. */
5337 enum machine_mode mode = VOIDmode;
5341 else if (GET_CODE (rld[r].in) == REG)
5343 regno = REGNO (rld[r].in);
5344 mode = GET_MODE (rld[r].in);
5346 else if (GET_CODE (rld[r].in_reg) == REG)
5348 regno = REGNO (rld[r].in_reg);
5349 mode = GET_MODE (rld[r].in_reg);
5351 else if (GET_CODE (rld[r].in_reg) == SUBREG
5352 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5354 byte = SUBREG_BYTE (rld[r].in_reg);
5355 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5356 if (regno < FIRST_PSEUDO_REGISTER)
5357 regno = subreg_regno (rld[r].in_reg);
5358 mode = GET_MODE (rld[r].in_reg);
5361 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5362 || GET_CODE (rld[r].in_reg) == PRE_DEC
5363 || GET_CODE (rld[r].in_reg) == POST_INC
5364 || GET_CODE (rld[r].in_reg) == POST_DEC)
5365 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5367 regno = REGNO (XEXP (rld[r].in_reg, 0));
5368 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5369 rld[r].out = rld[r].in;
5373 /* This won't work, since REGNO can be a pseudo reg number.
5374 Also, it takes much more hair to keep track of all the things
5375 that can invalidate an inherited reload of part of a pseudoreg. */
5376 else if (GET_CODE (rld[r].in) == SUBREG
5377 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5378 regno = subreg_regno (rld[r].in);
5381 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5383 enum reg_class class = rld[r].class, last_class;
5384 rtx last_reg = reg_last_reload_reg[regno];
5385 enum machine_mode need_mode;
5387 i = REGNO (last_reg);
5388 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5389 last_class = REGNO_REG_CLASS (i);
5395 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5396 GET_MODE_CLASS (mode));
5399 #ifdef CANNOT_CHANGE_MODE_CLASS
5400 (!REG_CANNOT_CHANGE_MODE_P (i, GET_MODE (last_reg),
5404 (GET_MODE_SIZE (GET_MODE (last_reg))
5405 >= GET_MODE_SIZE (need_mode))
5406 #ifdef CANNOT_CHANGE_MODE_CLASS
5409 && reg_reloaded_contents[i] == regno
5410 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5411 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5412 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5413 /* Even if we can't use this register as a reload
5414 register, we might use it for reload_override_in,
5415 if copying it to the desired class is cheap
5417 || ((REGISTER_MOVE_COST (mode, last_class, class)
5418 < MEMORY_MOVE_COST (mode, class, 1))
5419 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5420 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5424 #ifdef SECONDARY_MEMORY_NEEDED
5425 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5430 && (rld[r].nregs == max_group_size
5431 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5433 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5434 rld[r].when_needed, rld[r].in,
5437 /* If a group is needed, verify that all the subsequent
5438 registers still have their values intact. */
5439 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5442 for (k = 1; k < nr; k++)
5443 if (reg_reloaded_contents[i + k] != regno
5444 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5452 last_reg = (GET_MODE (last_reg) == mode
5453 ? last_reg : gen_rtx_REG (mode, i));
5456 for (k = 0; k < nr; k++)
5457 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5460 /* We found a register that contains the
5461 value we need. If this register is the
5462 same as an `earlyclobber' operand of the
5463 current insn, just mark it as a place to
5464 reload from since we can't use it as the
5465 reload register itself. */
5467 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5468 if (reg_overlap_mentioned_for_reload_p
5469 (reg_last_reload_reg[regno],
5470 reload_earlyclobbers[i1]))
5473 if (i1 != n_earlyclobbers
5474 || ! (free_for_value_p (i, rld[r].mode,
5476 rld[r].when_needed, rld[r].in,
5478 /* Don't use it if we'd clobber a pseudo reg. */
5479 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5481 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5482 /* Don't clobber the frame pointer. */
5483 || (i == HARD_FRAME_POINTER_REGNUM
5484 && frame_pointer_needed
5486 /* Don't really use the inherited spill reg
5487 if we need it wider than we've got it. */
5488 || (GET_MODE_SIZE (rld[r].mode)
5489 > GET_MODE_SIZE (mode))
5492 /* If find_reloads chose reload_out as reload
5493 register, stay with it - that leaves the
5494 inherited register for subsequent reloads. */
5495 || (rld[r].out && rld[r].reg_rtx
5496 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5498 if (! rld[r].optional)
5500 reload_override_in[r] = last_reg;
5501 reload_inheritance_insn[r]
5502 = reg_reloaded_insn[i];
5508 /* We can use this as a reload reg. */
5509 /* Mark the register as in use for this part of
5511 mark_reload_reg_in_use (i,
5515 rld[r].reg_rtx = last_reg;
5516 reload_inherited[r] = 1;
5517 reload_inheritance_insn[r]
5518 = reg_reloaded_insn[i];
5519 reload_spill_index[r] = i;
5520 for (k = 0; k < nr; k++)
5521 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5529 /* Here's another way to see if the value is already lying around. */
5532 && ! reload_inherited[r]
5534 && (CONSTANT_P (rld[r].in)
5535 || GET_CODE (rld[r].in) == PLUS
5536 || GET_CODE (rld[r].in) == REG
5537 || GET_CODE (rld[r].in) == MEM)
5538 && (rld[r].nregs == max_group_size
5539 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5540 search_equiv = rld[r].in;
5541 /* If this is an output reload from a simple move insn, look
5542 if an equivalence for the input is available. */
5543 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5545 rtx set = single_set (insn);
5548 && rtx_equal_p (rld[r].out, SET_DEST (set))
5549 && CONSTANT_P (SET_SRC (set)))
5550 search_equiv = SET_SRC (set);
5556 = find_equiv_reg (search_equiv, insn, rld[r].class,
5557 -1, NULL, 0, rld[r].mode);
5562 if (GET_CODE (equiv) == REG)
5563 regno = REGNO (equiv);
5564 else if (GET_CODE (equiv) == SUBREG)
5566 /* This must be a SUBREG of a hard register.
5567 Make a new REG since this might be used in an
5568 address and not all machines support SUBREGs
5570 regno = subreg_regno (equiv);
5571 equiv = gen_rtx_REG (rld[r].mode, regno);
5577 /* If we found a spill reg, reject it unless it is free
5578 and of the desired class. */
5582 int bad_for_class = 0;
5583 int max_regno = regno + rld[r].nregs;
5585 for (i = regno; i < max_regno; i++)
5587 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5589 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5594 && ! free_for_value_p (regno, rld[r].mode,
5595 rld[r].opnum, rld[r].when_needed,
5596 rld[r].in, rld[r].out, r, 1))
5601 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5604 /* We found a register that contains the value we need.
5605 If this register is the same as an `earlyclobber' operand
5606 of the current insn, just mark it as a place to reload from
5607 since we can't use it as the reload register itself. */
5610 for (i = 0; i < n_earlyclobbers; i++)
5611 if (reg_overlap_mentioned_for_reload_p (equiv,
5612 reload_earlyclobbers[i]))
5614 if (! rld[r].optional)
5615 reload_override_in[r] = equiv;
5620 /* If the equiv register we have found is explicitly clobbered
5621 in the current insn, it depends on the reload type if we
5622 can use it, use it for reload_override_in, or not at all.
5623 In particular, we then can't use EQUIV for a
5624 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5628 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5629 switch (rld[r].when_needed)
5631 case RELOAD_FOR_OTHER_ADDRESS:
5632 case RELOAD_FOR_INPADDR_ADDRESS:
5633 case RELOAD_FOR_INPUT_ADDRESS:
5634 case RELOAD_FOR_OPADDR_ADDR:
5637 case RELOAD_FOR_INPUT:
5638 case RELOAD_FOR_OPERAND_ADDRESS:
5639 if (! rld[r].optional)
5640 reload_override_in[r] = equiv;
5646 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5647 switch (rld[r].when_needed)
5649 case RELOAD_FOR_OTHER_ADDRESS:
5650 case RELOAD_FOR_INPADDR_ADDRESS:
5651 case RELOAD_FOR_INPUT_ADDRESS:
5652 case RELOAD_FOR_OPADDR_ADDR:
5653 case RELOAD_FOR_OPERAND_ADDRESS:
5654 case RELOAD_FOR_INPUT:
5657 if (! rld[r].optional)
5658 reload_override_in[r] = equiv;
5666 /* If we found an equivalent reg, say no code need be generated
5667 to load it, and use it as our reload reg. */
5669 && (regno != HARD_FRAME_POINTER_REGNUM
5670 || !frame_pointer_needed))
5672 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5674 rld[r].reg_rtx = equiv;
5675 reload_inherited[r] = 1;
5677 /* If reg_reloaded_valid is not set for this register,
5678 there might be a stale spill_reg_store lying around.
5679 We must clear it, since otherwise emit_reload_insns
5680 might delete the store. */
5681 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5682 spill_reg_store[regno] = NULL_RTX;
5683 /* If any of the hard registers in EQUIV are spill
5684 registers, mark them as in use for this insn. */
5685 for (k = 0; k < nr; k++)
5687 i = spill_reg_order[regno + k];
5690 mark_reload_reg_in_use (regno, rld[r].opnum,
5693 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5700 /* If we found a register to use already, or if this is an optional
5701 reload, we are done. */
5702 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5706 /* No longer needed for correct operation. Might or might
5707 not give better code on the average. Want to experiment? */
5709 /* See if there is a later reload that has a class different from our
5710 class that intersects our class or that requires less register
5711 than our reload. If so, we must allocate a register to this
5712 reload now, since that reload might inherit a previous reload
5713 and take the only available register in our class. Don't do this
5714 for optional reloads since they will force all previous reloads
5715 to be allocated. Also don't do this for reloads that have been
5718 for (i = j + 1; i < n_reloads; i++)
5720 int s = reload_order[i];
5722 if ((rld[s].in == 0 && rld[s].out == 0
5723 && ! rld[s].secondary_p)
5727 if ((rld[s].class != rld[r].class
5728 && reg_classes_intersect_p (rld[r].class,
5730 || rld[s].nregs < rld[r].nregs)
5737 allocate_reload_reg (chain, r, j == n_reloads - 1);
5741 /* Now allocate reload registers for anything non-optional that
5742 didn't get one yet. */
5743 for (j = 0; j < n_reloads; j++)
5745 int r = reload_order[j];
5747 /* Ignore reloads that got marked inoperative. */
5748 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5751 /* Skip reloads that already have a register allocated or are
5753 if (rld[r].reg_rtx != 0 || rld[r].optional)
5756 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5760 /* If that loop got all the way, we have won. */
5767 /* Loop around and try without any inheritance. */
5772 /* First undo everything done by the failed attempt
5773 to allocate with inheritance. */
5774 choose_reload_regs_init (chain, save_reload_reg_rtx);
5776 /* Some sanity tests to verify that the reloads found in the first
5777 pass are identical to the ones we have now. */
5778 if (chain->n_reloads != n_reloads)
5781 for (i = 0; i < n_reloads; i++)
5783 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5785 if (chain->rld[i].when_needed != rld[i].when_needed)
5787 for (j = 0; j < n_spills; j++)
5788 if (spill_regs[j] == chain->rld[i].regno)
5789 if (! set_reload_reg (j, i))
5790 failed_reload (chain->insn, i);
5794 /* If we thought we could inherit a reload, because it seemed that
5795 nothing else wanted the same reload register earlier in the insn,
5796 verify that assumption, now that all reloads have been assigned.
5797 Likewise for reloads where reload_override_in has been set. */
5799 /* If doing expensive optimizations, do one preliminary pass that doesn't
5800 cancel any inheritance, but removes reloads that have been needed only
5801 for reloads that we know can be inherited. */
5802 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5804 for (j = 0; j < n_reloads; j++)
5806 int r = reload_order[j];
5808 if (reload_inherited[r] && rld[r].reg_rtx)
5809 check_reg = rld[r].reg_rtx;
5810 else if (reload_override_in[r]
5811 && (GET_CODE (reload_override_in[r]) == REG
5812 || GET_CODE (reload_override_in[r]) == SUBREG))
5813 check_reg = reload_override_in[r];
5816 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5817 rld[r].opnum, rld[r].when_needed, rld[r].in,
5818 (reload_inherited[r]
5819 ? rld[r].out : const0_rtx),
5824 reload_inherited[r] = 0;
5825 reload_override_in[r] = 0;
5827 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5828 reload_override_in, then we do not need its related
5829 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5830 likewise for other reload types.
5831 We handle this by removing a reload when its only replacement
5832 is mentioned in reload_in of the reload we are going to inherit.
5833 A special case are auto_inc expressions; even if the input is
5834 inherited, we still need the address for the output. We can
5835 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5836 If we succeeded removing some reload and we are doing a preliminary
5837 pass just to remove such reloads, make another pass, since the
5838 removal of one reload might allow us to inherit another one. */
5840 && rld[r].out != rld[r].in
5841 && remove_address_replacements (rld[r].in) && pass)
5846 /* Now that reload_override_in is known valid,
5847 actually override reload_in. */
5848 for (j = 0; j < n_reloads; j++)
5849 if (reload_override_in[j])
5850 rld[j].in = reload_override_in[j];
5852 /* If this reload won't be done because it has been canceled or is
5853 optional and not inherited, clear reload_reg_rtx so other
5854 routines (such as subst_reloads) don't get confused. */
5855 for (j = 0; j < n_reloads; j++)
5856 if (rld[j].reg_rtx != 0
5857 && ((rld[j].optional && ! reload_inherited[j])
5858 || (rld[j].in == 0 && rld[j].out == 0
5859 && ! rld[j].secondary_p)))
5861 int regno = true_regnum (rld[j].reg_rtx);
5863 if (spill_reg_order[regno] >= 0)
5864 clear_reload_reg_in_use (regno, rld[j].opnum,
5865 rld[j].when_needed, rld[j].mode);
5867 reload_spill_index[j] = -1;
5870 /* Record which pseudos and which spill regs have output reloads. */
5871 for (j = 0; j < n_reloads; j++)
5873 int r = reload_order[j];
5875 i = reload_spill_index[r];
5877 /* I is nonneg if this reload uses a register.
5878 If rld[r].reg_rtx is 0, this is an optional reload
5879 that we opted to ignore. */
5880 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5881 && rld[r].reg_rtx != 0)
5883 int nregno = REGNO (rld[r].out_reg);
5886 if (nregno < FIRST_PSEUDO_REGISTER)
5887 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5890 reg_has_output_reload[nregno + nr] = 1;
5894 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5896 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5899 if (rld[r].when_needed != RELOAD_OTHER
5900 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5901 && rld[r].when_needed != RELOAD_FOR_INSN)
5907 /* Deallocate the reload register for reload R. This is called from
5908 remove_address_replacements. */
5911 deallocate_reload_reg (int r)
5915 if (! rld[r].reg_rtx)
5917 regno = true_regnum (rld[r].reg_rtx);
5919 if (spill_reg_order[regno] >= 0)
5920 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5922 reload_spill_index[r] = -1;
5925 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
5926 reloads of the same item for fear that we might not have enough reload
5927 registers. However, normally they will get the same reload register
5928 and hence actually need not be loaded twice.
5930 Here we check for the most common case of this phenomenon: when we have
5931 a number of reloads for the same object, each of which were allocated
5932 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5933 reload, and is not modified in the insn itself. If we find such,
5934 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5935 This will not increase the number of spill registers needed and will
5936 prevent redundant code. */
5939 merge_assigned_reloads (rtx insn)
5943 /* Scan all the reloads looking for ones that only load values and
5944 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5945 assigned and not modified by INSN. */
5947 for (i = 0; i < n_reloads; i++)
5949 int conflicting_input = 0;
5950 int max_input_address_opnum = -1;
5951 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5953 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5954 || rld[i].out != 0 || rld[i].reg_rtx == 0
5955 || reg_set_p (rld[i].reg_rtx, insn))
5958 /* Look at all other reloads. Ensure that the only use of this
5959 reload_reg_rtx is in a reload that just loads the same value
5960 as we do. Note that any secondary reloads must be of the identical
5961 class since the values, modes, and result registers are the
5962 same, so we need not do anything with any secondary reloads. */
5964 for (j = 0; j < n_reloads; j++)
5966 if (i == j || rld[j].reg_rtx == 0
5967 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
5971 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5972 && rld[j].opnum > max_input_address_opnum)
5973 max_input_address_opnum = rld[j].opnum;
5975 /* If the reload regs aren't exactly the same (e.g, different modes)
5976 or if the values are different, we can't merge this reload.
5977 But if it is an input reload, we might still merge
5978 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
5980 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5981 || rld[j].out != 0 || rld[j].in == 0
5982 || ! rtx_equal_p (rld[i].in, rld[j].in))
5984 if (rld[j].when_needed != RELOAD_FOR_INPUT
5985 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
5986 || rld[i].opnum > rld[j].opnum)
5987 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
5989 conflicting_input = 1;
5990 if (min_conflicting_input_opnum > rld[j].opnum)
5991 min_conflicting_input_opnum = rld[j].opnum;
5995 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5996 we, in fact, found any matching reloads. */
5999 && max_input_address_opnum <= min_conflicting_input_opnum)
6001 for (j = 0; j < n_reloads; j++)
6002 if (i != j && rld[j].reg_rtx != 0
6003 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6004 && (! conflicting_input
6005 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6006 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6008 rld[i].when_needed = RELOAD_OTHER;
6010 reload_spill_index[j] = -1;
6011 transfer_replacements (i, j);
6014 /* If this is now RELOAD_OTHER, look for any reloads that load
6015 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6016 if they were for inputs, RELOAD_OTHER for outputs. Note that
6017 this test is equivalent to looking for reloads for this operand
6019 /* We must take special care when there are two or more reloads to
6020 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6021 same value or a part of it; we must not change its type if there
6022 is a conflicting input. */
6024 if (rld[i].when_needed == RELOAD_OTHER)
6025 for (j = 0; j < n_reloads; j++)
6027 && rld[j].when_needed != RELOAD_OTHER
6028 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6029 && (! conflicting_input
6030 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6031 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6032 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6038 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6039 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6040 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6042 /* Check to see if we accidentally converted two reloads
6043 that use the same reload register with different inputs
6044 to the same type. If so, the resulting code won't work,
6047 for (k = 0; k < j; k++)
6048 if (rld[k].in != 0 && rld[k].reg_rtx != 0
6049 && rld[k].when_needed == rld[j].when_needed
6050 && rtx_equal_p (rld[k].reg_rtx, rld[j].reg_rtx)
6051 && ! rtx_equal_p (rld[k].in, rld[j].in))
6058 /* These arrays are filled by emit_reload_insns and its subroutines. */
6059 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6060 static rtx other_input_address_reload_insns = 0;
6061 static rtx other_input_reload_insns = 0;
6062 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6063 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6064 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6065 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6066 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6067 static rtx operand_reload_insns = 0;
6068 static rtx other_operand_reload_insns = 0;
6069 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6071 /* Values to be put in spill_reg_store are put here first. */
6072 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6073 static HARD_REG_SET reg_reloaded_died;
6075 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6076 has the number J. OLD contains the value to be used as input. */
6079 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6082 rtx insn = chain->insn;
6083 rtx reloadreg = rl->reg_rtx;
6084 rtx oldequiv_reg = 0;
6087 enum machine_mode mode;
6090 /* Determine the mode to reload in.
6091 This is very tricky because we have three to choose from.
6092 There is the mode the insn operand wants (rl->inmode).
6093 There is the mode of the reload register RELOADREG.
6094 There is the intrinsic mode of the operand, which we could find
6095 by stripping some SUBREGs.
6096 It turns out that RELOADREG's mode is irrelevant:
6097 we can change that arbitrarily.
6099 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6100 then the reload reg may not support QImode moves, so use SImode.
6101 If foo is in memory due to spilling a pseudo reg, this is safe,
6102 because the QImode value is in the least significant part of a
6103 slot big enough for a SImode. If foo is some other sort of
6104 memory reference, then it is impossible to reload this case,
6105 so previous passes had better make sure this never happens.
6107 Then consider a one-word union which has SImode and one of its
6108 members is a float, being fetched as (SUBREG:SF union:SI).
6109 We must fetch that as SFmode because we could be loading into
6110 a float-only register. In this case OLD's mode is correct.
6112 Consider an immediate integer: it has VOIDmode. Here we need
6113 to get a mode from something else.
6115 In some cases, there is a fourth mode, the operand's
6116 containing mode. If the insn specifies a containing mode for
6117 this operand, it overrides all others.
6119 I am not sure whether the algorithm here is always right,
6120 but it does the right things in those cases. */
6122 mode = GET_MODE (old);
6123 if (mode == VOIDmode)
6126 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6127 /* If we need a secondary register for this operation, see if
6128 the value is already in a register in that class. Don't
6129 do this if the secondary register will be used as a scratch
6132 if (rl->secondary_in_reload >= 0
6133 && rl->secondary_in_icode == CODE_FOR_nothing
6136 = find_equiv_reg (old, insn,
6137 rld[rl->secondary_in_reload].class,
6141 /* If reloading from memory, see if there is a register
6142 that already holds the same value. If so, reload from there.
6143 We can pass 0 as the reload_reg_p argument because
6144 any other reload has either already been emitted,
6145 in which case find_equiv_reg will see the reload-insn,
6146 or has yet to be emitted, in which case it doesn't matter
6147 because we will use this equiv reg right away. */
6149 if (oldequiv == 0 && optimize
6150 && (GET_CODE (old) == MEM
6151 || (GET_CODE (old) == REG
6152 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6153 && reg_renumber[REGNO (old)] < 0)))
6154 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6158 unsigned int regno = true_regnum (oldequiv);
6160 /* Don't use OLDEQUIV if any other reload changes it at an
6161 earlier stage of this insn or at this stage. */
6162 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6163 rl->in, const0_rtx, j, 0))
6166 /* If it is no cheaper to copy from OLDEQUIV into the
6167 reload register than it would be to move from memory,
6168 don't use it. Likewise, if we need a secondary register
6172 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6173 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6175 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6176 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6177 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6181 #ifdef SECONDARY_MEMORY_NEEDED
6182 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6190 /* delete_output_reload is only invoked properly if old contains
6191 the original pseudo register. Since this is replaced with a
6192 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6193 find the pseudo in RELOAD_IN_REG. */
6195 && reload_override_in[j]
6196 && GET_CODE (rl->in_reg) == REG)
6203 else if (GET_CODE (oldequiv) == REG)
6204 oldequiv_reg = oldequiv;
6205 else if (GET_CODE (oldequiv) == SUBREG)
6206 oldequiv_reg = SUBREG_REG (oldequiv);
6208 /* If we are reloading from a register that was recently stored in
6209 with an output-reload, see if we can prove there was
6210 actually no need to store the old value in it. */
6212 if (optimize && GET_CODE (oldequiv) == REG
6213 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6214 && spill_reg_store[REGNO (oldequiv)]
6215 && GET_CODE (old) == REG
6216 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6217 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6219 delete_output_reload (insn, j, REGNO (oldequiv));
6221 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6222 then load RELOADREG from OLDEQUIV. Note that we cannot use
6223 gen_lowpart_common since it can do the wrong thing when
6224 RELOADREG has a multi-word mode. Note that RELOADREG
6225 must always be a REG here. */
6227 if (GET_MODE (reloadreg) != mode)
6228 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6229 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6230 oldequiv = SUBREG_REG (oldequiv);
6231 if (GET_MODE (oldequiv) != VOIDmode
6232 && mode != GET_MODE (oldequiv))
6233 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6235 /* Switch to the right place to emit the reload insns. */
6236 switch (rl->when_needed)
6239 where = &other_input_reload_insns;
6241 case RELOAD_FOR_INPUT:
6242 where = &input_reload_insns[rl->opnum];
6244 case RELOAD_FOR_INPUT_ADDRESS:
6245 where = &input_address_reload_insns[rl->opnum];
6247 case RELOAD_FOR_INPADDR_ADDRESS:
6248 where = &inpaddr_address_reload_insns[rl->opnum];
6250 case RELOAD_FOR_OUTPUT_ADDRESS:
6251 where = &output_address_reload_insns[rl->opnum];
6253 case RELOAD_FOR_OUTADDR_ADDRESS:
6254 where = &outaddr_address_reload_insns[rl->opnum];
6256 case RELOAD_FOR_OPERAND_ADDRESS:
6257 where = &operand_reload_insns;
6259 case RELOAD_FOR_OPADDR_ADDR:
6260 where = &other_operand_reload_insns;
6262 case RELOAD_FOR_OTHER_ADDRESS:
6263 where = &other_input_address_reload_insns;
6269 push_to_sequence (*where);
6271 /* Auto-increment addresses must be reloaded in a special way. */
6272 if (rl->out && ! rl->out_reg)
6274 /* We are not going to bother supporting the case where a
6275 incremented register can't be copied directly from
6276 OLDEQUIV since this seems highly unlikely. */
6277 if (rl->secondary_in_reload >= 0)
6280 if (reload_inherited[j])
6281 oldequiv = reloadreg;
6283 old = XEXP (rl->in_reg, 0);
6285 if (optimize && GET_CODE (oldequiv) == REG
6286 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6287 && spill_reg_store[REGNO (oldequiv)]
6288 && GET_CODE (old) == REG
6289 && (dead_or_set_p (insn,
6290 spill_reg_stored_to[REGNO (oldequiv)])
6291 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6293 delete_output_reload (insn, j, REGNO (oldequiv));
6295 /* Prevent normal processing of this reload. */
6297 /* Output a special code sequence for this case. */
6298 new_spill_reg_store[REGNO (reloadreg)]
6299 = inc_for_reload (reloadreg, oldequiv, rl->out,
6303 /* If we are reloading a pseudo-register that was set by the previous
6304 insn, see if we can get rid of that pseudo-register entirely
6305 by redirecting the previous insn into our reload register. */
6307 else if (optimize && GET_CODE (old) == REG
6308 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6309 && dead_or_set_p (insn, old)
6310 /* This is unsafe if some other reload
6311 uses the same reg first. */
6312 && ! conflicts_with_override (reloadreg)
6313 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6314 rl->when_needed, old, rl->out, j, 0))
6316 rtx temp = PREV_INSN (insn);
6317 while (temp && GET_CODE (temp) == NOTE)
6318 temp = PREV_INSN (temp);
6320 && GET_CODE (temp) == INSN
6321 && GET_CODE (PATTERN (temp)) == SET
6322 && SET_DEST (PATTERN (temp)) == old
6323 /* Make sure we can access insn_operand_constraint. */
6324 && asm_noperands (PATTERN (temp)) < 0
6325 /* This is unsafe if operand occurs more than once in current
6326 insn. Perhaps some occurrences aren't reloaded. */
6327 && count_occurrences (PATTERN (insn), old, 0) == 1)
6329 rtx old = SET_DEST (PATTERN (temp));
6330 /* Store into the reload register instead of the pseudo. */
6331 SET_DEST (PATTERN (temp)) = reloadreg;
6333 /* Verify that resulting insn is valid. */
6334 extract_insn (temp);
6335 if (constrain_operands (1))
6337 /* If the previous insn is an output reload, the source is
6338 a reload register, and its spill_reg_store entry will
6339 contain the previous destination. This is now
6341 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6342 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6344 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6345 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6348 /* If these are the only uses of the pseudo reg,
6349 pretend for GDB it lives in the reload reg we used. */
6350 if (REG_N_DEATHS (REGNO (old)) == 1
6351 && REG_N_SETS (REGNO (old)) == 1)
6353 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6354 alter_reg (REGNO (old), -1);
6360 SET_DEST (PATTERN (temp)) = old;
6365 /* We can't do that, so output an insn to load RELOADREG. */
6367 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6368 /* If we have a secondary reload, pick up the secondary register
6369 and icode, if any. If OLDEQUIV and OLD are different or
6370 if this is an in-out reload, recompute whether or not we
6371 still need a secondary register and what the icode should
6372 be. If we still need a secondary register and the class or
6373 icode is different, go back to reloading from OLD if using
6374 OLDEQUIV means that we got the wrong type of register. We
6375 cannot have different class or icode due to an in-out reload
6376 because we don't make such reloads when both the input and
6377 output need secondary reload registers. */
6379 if (! special && rl->secondary_in_reload >= 0)
6381 rtx second_reload_reg = 0;
6382 int secondary_reload = rl->secondary_in_reload;
6383 rtx real_oldequiv = oldequiv;
6386 enum insn_code icode;
6388 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6389 and similarly for OLD.
6390 See comments in get_secondary_reload in reload.c. */
6391 /* If it is a pseudo that cannot be replaced with its
6392 equivalent MEM, we must fall back to reload_in, which
6393 will have all the necessary substitutions registered.
6394 Likewise for a pseudo that can't be replaced with its
6395 equivalent constant.
6397 Take extra care for subregs of such pseudos. Note that
6398 we cannot use reg_equiv_mem in this case because it is
6399 not in the right mode. */
6402 if (GET_CODE (tmp) == SUBREG)
6403 tmp = SUBREG_REG (tmp);
6404 if (GET_CODE (tmp) == REG
6405 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6406 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6407 || reg_equiv_constant[REGNO (tmp)] != 0))
6409 if (! reg_equiv_mem[REGNO (tmp)]
6410 || num_not_at_initial_offset
6411 || GET_CODE (oldequiv) == SUBREG)
6412 real_oldequiv = rl->in;
6414 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6418 if (GET_CODE (tmp) == SUBREG)
6419 tmp = SUBREG_REG (tmp);
6420 if (GET_CODE (tmp) == REG
6421 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6422 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6423 || reg_equiv_constant[REGNO (tmp)] != 0))
6425 if (! reg_equiv_mem[REGNO (tmp)]
6426 || num_not_at_initial_offset
6427 || GET_CODE (old) == SUBREG)
6430 real_old = reg_equiv_mem[REGNO (tmp)];
6433 second_reload_reg = rld[secondary_reload].reg_rtx;
6434 icode = rl->secondary_in_icode;
6436 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6437 || (rl->in != 0 && rl->out != 0))
6439 enum reg_class new_class
6440 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6441 mode, real_oldequiv);
6443 if (new_class == NO_REGS)
6444 second_reload_reg = 0;
6447 enum insn_code new_icode;
6448 enum machine_mode new_mode;
6450 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6451 REGNO (second_reload_reg)))
6452 oldequiv = old, real_oldequiv = real_old;
6455 new_icode = reload_in_optab[(int) mode];
6456 if (new_icode != CODE_FOR_nothing
6457 && ((insn_data[(int) new_icode].operand[0].predicate
6458 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6460 || (insn_data[(int) new_icode].operand[1].predicate
6461 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6462 (real_oldequiv, mode)))))
6463 new_icode = CODE_FOR_nothing;
6465 if (new_icode == CODE_FOR_nothing)
6468 new_mode = insn_data[(int) new_icode].operand[2].mode;
6470 if (GET_MODE (second_reload_reg) != new_mode)
6472 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6474 oldequiv = old, real_oldequiv = real_old;
6477 = reload_adjust_reg_for_mode (second_reload_reg,
6484 /* If we still need a secondary reload register, check
6485 to see if it is being used as a scratch or intermediate
6486 register and generate code appropriately. If we need
6487 a scratch register, use REAL_OLDEQUIV since the form of
6488 the insn may depend on the actual address if it is
6491 if (second_reload_reg)
6493 if (icode != CODE_FOR_nothing)
6495 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6496 second_reload_reg));
6501 /* See if we need a scratch register to load the
6502 intermediate register (a tertiary reload). */
6503 enum insn_code tertiary_icode
6504 = rld[secondary_reload].secondary_in_icode;
6506 if (tertiary_icode != CODE_FOR_nothing)
6508 rtx third_reload_reg
6509 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6511 emit_insn ((GEN_FCN (tertiary_icode)
6512 (second_reload_reg, real_oldequiv,
6513 third_reload_reg)));
6516 gen_reload (second_reload_reg, real_oldequiv,
6520 oldequiv = second_reload_reg;
6526 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6528 rtx real_oldequiv = oldequiv;
6530 if ((GET_CODE (oldequiv) == REG
6531 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6532 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6533 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6534 || (GET_CODE (oldequiv) == SUBREG
6535 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6536 && (REGNO (SUBREG_REG (oldequiv))
6537 >= FIRST_PSEUDO_REGISTER)
6538 && ((reg_equiv_memory_loc
6539 [REGNO (SUBREG_REG (oldequiv))] != 0)
6540 || (reg_equiv_constant
6541 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6542 || (CONSTANT_P (oldequiv)
6543 && (PREFERRED_RELOAD_CLASS (oldequiv,
6544 REGNO_REG_CLASS (REGNO (reloadreg)))
6546 real_oldequiv = rl->in;
6547 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6551 if (flag_non_call_exceptions)
6552 copy_eh_notes (insn, get_insns ());
6554 /* End this sequence. */
6555 *where = get_insns ();
6558 /* Update reload_override_in so that delete_address_reloads_1
6559 can see the actual register usage. */
6561 reload_override_in[j] = oldequiv;
6564 /* Generate insns to for the output reload RL, which is for the insn described
6565 by CHAIN and has the number J. */
6567 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6570 rtx reloadreg = rl->reg_rtx;
6571 rtx insn = chain->insn;
6574 enum machine_mode mode = GET_MODE (old);
6577 if (rl->when_needed == RELOAD_OTHER)
6580 push_to_sequence (output_reload_insns[rl->opnum]);
6582 /* Determine the mode to reload in.
6583 See comments above (for input reloading). */
6585 if (mode == VOIDmode)
6587 /* VOIDmode should never happen for an output. */
6588 if (asm_noperands (PATTERN (insn)) < 0)
6589 /* It's the compiler's fault. */
6590 fatal_insn ("VOIDmode on an output", insn);
6591 error_for_asm (insn, "output operand is constant in `asm'");
6592 /* Prevent crash--use something we know is valid. */
6594 old = gen_rtx_REG (mode, REGNO (reloadreg));
6597 if (GET_MODE (reloadreg) != mode)
6598 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6600 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6602 /* If we need two reload regs, set RELOADREG to the intermediate
6603 one, since it will be stored into OLD. We might need a secondary
6604 register only for an input reload, so check again here. */
6606 if (rl->secondary_out_reload >= 0)
6610 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6611 && reg_equiv_mem[REGNO (old)] != 0)
6612 real_old = reg_equiv_mem[REGNO (old)];
6614 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6618 rtx second_reloadreg = reloadreg;
6619 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6621 /* See if RELOADREG is to be used as a scratch register
6622 or as an intermediate register. */
6623 if (rl->secondary_out_icode != CODE_FOR_nothing)
6625 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6626 (real_old, second_reloadreg, reloadreg)));
6631 /* See if we need both a scratch and intermediate reload
6634 int secondary_reload = rl->secondary_out_reload;
6635 enum insn_code tertiary_icode
6636 = rld[secondary_reload].secondary_out_icode;
6638 if (GET_MODE (reloadreg) != mode)
6639 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6641 if (tertiary_icode != CODE_FOR_nothing)
6644 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6647 /* Copy primary reload reg to secondary reload reg.
6648 (Note that these have been swapped above, then
6649 secondary reload reg to OLD using our insn.) */
6651 /* If REAL_OLD is a paradoxical SUBREG, remove it
6652 and try to put the opposite SUBREG on
6654 if (GET_CODE (real_old) == SUBREG
6655 && (GET_MODE_SIZE (GET_MODE (real_old))
6656 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6657 && 0 != (tem = gen_lowpart_common
6658 (GET_MODE (SUBREG_REG (real_old)),
6660 real_old = SUBREG_REG (real_old), reloadreg = tem;
6662 gen_reload (reloadreg, second_reloadreg,
6663 rl->opnum, rl->when_needed);
6664 emit_insn ((GEN_FCN (tertiary_icode)
6665 (real_old, reloadreg, third_reloadreg)));
6670 /* Copy between the reload regs here and then to
6673 gen_reload (reloadreg, second_reloadreg,
6674 rl->opnum, rl->when_needed);
6680 /* Output the last reload insn. */
6685 /* Don't output the last reload if OLD is not the dest of
6686 INSN and is in the src and is clobbered by INSN. */
6687 if (! flag_expensive_optimizations
6688 || GET_CODE (old) != REG
6689 || !(set = single_set (insn))
6690 || rtx_equal_p (old, SET_DEST (set))
6691 || !reg_mentioned_p (old, SET_SRC (set))
6692 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6693 gen_reload (old, reloadreg, rl->opnum,
6697 /* Look at all insns we emitted, just to be safe. */
6698 for (p = get_insns (); p; p = NEXT_INSN (p))
6701 rtx pat = PATTERN (p);
6703 /* If this output reload doesn't come from a spill reg,
6704 clear any memory of reloaded copies of the pseudo reg.
6705 If this output reload comes from a spill reg,
6706 reg_has_output_reload will make this do nothing. */
6707 note_stores (pat, forget_old_reloads_1, NULL);
6709 if (reg_mentioned_p (rl->reg_rtx, pat))
6711 rtx set = single_set (insn);
6712 if (reload_spill_index[j] < 0
6714 && SET_SRC (set) == rl->reg_rtx)
6716 int src = REGNO (SET_SRC (set));
6718 reload_spill_index[j] = src;
6719 SET_HARD_REG_BIT (reg_is_output_reload, src);
6720 if (find_regno_note (insn, REG_DEAD, src))
6721 SET_HARD_REG_BIT (reg_reloaded_died, src);
6723 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6725 int s = rl->secondary_out_reload;
6726 set = single_set (p);
6727 /* If this reload copies only to the secondary reload
6728 register, the secondary reload does the actual
6730 if (s >= 0 && set == NULL_RTX)
6731 /* We can't tell what function the secondary reload
6732 has and where the actual store to the pseudo is
6733 made; leave new_spill_reg_store alone. */
6736 && SET_SRC (set) == rl->reg_rtx
6737 && SET_DEST (set) == rld[s].reg_rtx)
6739 /* Usually the next instruction will be the
6740 secondary reload insn; if we can confirm
6741 that it is, setting new_spill_reg_store to
6742 that insn will allow an extra optimization. */
6743 rtx s_reg = rld[s].reg_rtx;
6744 rtx next = NEXT_INSN (p);
6745 rld[s].out = rl->out;
6746 rld[s].out_reg = rl->out_reg;
6747 set = single_set (next);
6748 if (set && SET_SRC (set) == s_reg
6749 && ! new_spill_reg_store[REGNO (s_reg)])
6751 SET_HARD_REG_BIT (reg_is_output_reload,
6753 new_spill_reg_store[REGNO (s_reg)] = next;
6757 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6762 if (rl->when_needed == RELOAD_OTHER)
6764 emit_insn (other_output_reload_insns[rl->opnum]);
6765 other_output_reload_insns[rl->opnum] = get_insns ();
6768 output_reload_insns[rl->opnum] = get_insns ();
6770 if (flag_non_call_exceptions)
6771 copy_eh_notes (insn, get_insns ());
6776 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6777 and has the number J. */
6779 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
6781 rtx insn = chain->insn;
6782 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6783 ? rl->in_reg : rl->in);
6786 /* AUTO_INC reloads need to be handled even if inherited. We got an
6787 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6788 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6789 && ! rtx_equal_p (rl->reg_rtx, old)
6790 && rl->reg_rtx != 0)
6791 emit_input_reload_insns (chain, rld + j, old, j);
6793 /* When inheriting a wider reload, we have a MEM in rl->in,
6794 e.g. inheriting a SImode output reload for
6795 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6796 if (optimize && reload_inherited[j] && rl->in
6797 && GET_CODE (rl->in) == MEM
6798 && GET_CODE (rl->in_reg) == MEM
6799 && reload_spill_index[j] >= 0
6800 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6801 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6803 /* If we are reloading a register that was recently stored in with an
6804 output-reload, see if we can prove there was
6805 actually no need to store the old value in it. */
6808 && (reload_inherited[j] || reload_override_in[j])
6810 && GET_CODE (rl->reg_rtx) == REG
6811 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6813 /* There doesn't seem to be any reason to restrict this to pseudos
6814 and doing so loses in the case where we are copying from a
6815 register of the wrong class. */
6816 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6817 >= FIRST_PSEUDO_REGISTER)
6819 /* The insn might have already some references to stackslots
6820 replaced by MEMs, while reload_out_reg still names the
6822 && (dead_or_set_p (insn,
6823 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6824 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6826 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6829 /* Do output reloading for reload RL, which is for the insn described by
6830 CHAIN and has the number J.
6831 ??? At some point we need to support handling output reloads of
6832 JUMP_INSNs or insns that set cc0. */
6834 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
6837 rtx insn = chain->insn;
6838 /* If this is an output reload that stores something that is
6839 not loaded in this same reload, see if we can eliminate a previous
6841 rtx pseudo = rl->out_reg;
6845 && GET_CODE (pseudo) == REG
6846 && ! rtx_equal_p (rl->in_reg, pseudo)
6847 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6848 && reg_last_reload_reg[REGNO (pseudo)])
6850 int pseudo_no = REGNO (pseudo);
6851 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6853 /* We don't need to test full validity of last_regno for
6854 inherit here; we only want to know if the store actually
6855 matches the pseudo. */
6856 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6857 && reg_reloaded_contents[last_regno] == pseudo_no
6858 && spill_reg_store[last_regno]
6859 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6860 delete_output_reload (insn, j, last_regno);
6865 || rl->reg_rtx == old
6866 || rl->reg_rtx == 0)
6869 /* An output operand that dies right away does need a reload,
6870 but need not be copied from it. Show the new location in the
6872 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6873 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6875 XEXP (note, 0) = rl->reg_rtx;
6878 /* Likewise for a SUBREG of an operand that dies. */
6879 else if (GET_CODE (old) == SUBREG
6880 && GET_CODE (SUBREG_REG (old)) == REG
6881 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6884 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6888 else if (GET_CODE (old) == SCRATCH)
6889 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6890 but we don't want to make an output reload. */
6893 /* If is a JUMP_INSN, we can't support output reloads yet. */
6894 if (GET_CODE (insn) == JUMP_INSN)
6897 emit_output_reload_insns (chain, rld + j, j);
6900 /* Output insns to reload values in and out of the chosen reload regs. */
6903 emit_reload_insns (struct insn_chain *chain)
6905 rtx insn = chain->insn;
6909 CLEAR_HARD_REG_SET (reg_reloaded_died);
6911 for (j = 0; j < reload_n_operands; j++)
6912 input_reload_insns[j] = input_address_reload_insns[j]
6913 = inpaddr_address_reload_insns[j]
6914 = output_reload_insns[j] = output_address_reload_insns[j]
6915 = outaddr_address_reload_insns[j]
6916 = other_output_reload_insns[j] = 0;
6917 other_input_address_reload_insns = 0;
6918 other_input_reload_insns = 0;
6919 operand_reload_insns = 0;
6920 other_operand_reload_insns = 0;
6922 /* Dump reloads into the dump file. */
6925 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6926 debug_reload_to_stream (rtl_dump_file);
6929 /* Now output the instructions to copy the data into and out of the
6930 reload registers. Do these in the order that the reloads were reported,
6931 since reloads of base and index registers precede reloads of operands
6932 and the operands may need the base and index registers reloaded. */
6934 for (j = 0; j < n_reloads; j++)
6937 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6938 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6940 do_input_reload (chain, rld + j, j);
6941 do_output_reload (chain, rld + j, j);
6944 /* Now write all the insns we made for reloads in the order expected by
6945 the allocation functions. Prior to the insn being reloaded, we write
6946 the following reloads:
6948 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6950 RELOAD_OTHER reloads.
6952 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6953 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6954 RELOAD_FOR_INPUT reload for the operand.
6956 RELOAD_FOR_OPADDR_ADDRS reloads.
6958 RELOAD_FOR_OPERAND_ADDRESS reloads.
6960 After the insn being reloaded, we write the following:
6962 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6963 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6964 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6965 reloads for the operand. The RELOAD_OTHER output reloads are
6966 output in descending order by reload number. */
6968 emit_insn_before_sameloc (other_input_address_reload_insns, insn);
6969 emit_insn_before_sameloc (other_input_reload_insns, insn);
6971 for (j = 0; j < reload_n_operands; j++)
6973 emit_insn_before_sameloc (inpaddr_address_reload_insns[j], insn);
6974 emit_insn_before_sameloc (input_address_reload_insns[j], insn);
6975 emit_insn_before_sameloc (input_reload_insns[j], insn);
6978 emit_insn_before_sameloc (other_operand_reload_insns, insn);
6979 emit_insn_before_sameloc (operand_reload_insns, insn);
6981 for (j = 0; j < reload_n_operands; j++)
6983 rtx x = emit_insn_after_sameloc (outaddr_address_reload_insns[j], insn);
6984 x = emit_insn_after_sameloc (output_address_reload_insns[j], x);
6985 x = emit_insn_after_sameloc (output_reload_insns[j], x);
6986 emit_insn_after_sameloc (other_output_reload_insns[j], x);
6989 /* For all the spill regs newly reloaded in this instruction,
6990 record what they were reloaded from, so subsequent instructions
6991 can inherit the reloads.
6993 Update spill_reg_store for the reloads of this insn.
6994 Copy the elements that were updated in the loop above. */
6996 for (j = 0; j < n_reloads; j++)
6998 int r = reload_order[j];
6999 int i = reload_spill_index[r];
7001 /* If this is a non-inherited input reload from a pseudo, we must
7002 clear any memory of a previous store to the same pseudo. Only do
7003 something if there will not be an output reload for the pseudo
7005 if (rld[r].in_reg != 0
7006 && ! (reload_inherited[r] || reload_override_in[r]))
7008 rtx reg = rld[r].in_reg;
7010 if (GET_CODE (reg) == SUBREG)
7011 reg = SUBREG_REG (reg);
7013 if (GET_CODE (reg) == REG
7014 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7015 && ! reg_has_output_reload[REGNO (reg)])
7017 int nregno = REGNO (reg);
7019 if (reg_last_reload_reg[nregno])
7021 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7023 if (reg_reloaded_contents[last_regno] == nregno)
7024 spill_reg_store[last_regno] = 0;
7029 /* I is nonneg if this reload used a register.
7030 If rld[r].reg_rtx is 0, this is an optional reload
7031 that we opted to ignore. */
7033 if (i >= 0 && rld[r].reg_rtx != 0)
7035 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7037 int part_reaches_end = 0;
7038 int all_reaches_end = 1;
7040 /* For a multi register reload, we need to check if all or part
7041 of the value lives to the end. */
7042 for (k = 0; k < nr; k++)
7044 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7045 rld[r].when_needed))
7046 part_reaches_end = 1;
7048 all_reaches_end = 0;
7051 /* Ignore reloads that don't reach the end of the insn in
7053 if (all_reaches_end)
7055 /* First, clear out memory of what used to be in this spill reg.
7056 If consecutive registers are used, clear them all. */
7058 for (k = 0; k < nr; k++)
7060 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7061 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7064 /* Maybe the spill reg contains a copy of reload_out. */
7066 && (GET_CODE (rld[r].out) == REG
7070 || GET_CODE (rld[r].out_reg) == REG))
7072 rtx out = (GET_CODE (rld[r].out) == REG
7076 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7077 int nregno = REGNO (out);
7078 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7079 : HARD_REGNO_NREGS (nregno,
7080 GET_MODE (rld[r].reg_rtx)));
7082 spill_reg_store[i] = new_spill_reg_store[i];
7083 spill_reg_stored_to[i] = out;
7084 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7086 /* If NREGNO is a hard register, it may occupy more than
7087 one register. If it does, say what is in the
7088 rest of the registers assuming that both registers
7089 agree on how many words the object takes. If not,
7090 invalidate the subsequent registers. */
7092 if (nregno < FIRST_PSEUDO_REGISTER)
7093 for (k = 1; k < nnr; k++)
7094 reg_last_reload_reg[nregno + k]
7096 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7099 /* Now do the inverse operation. */
7100 for (k = 0; k < nr; k++)
7102 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7103 reg_reloaded_contents[i + k]
7104 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7107 reg_reloaded_insn[i + k] = insn;
7108 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7109 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7110 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7114 /* Maybe the spill reg contains a copy of reload_in. Only do
7115 something if there will not be an output reload for
7116 the register being reloaded. */
7117 else if (rld[r].out_reg == 0
7119 && ((GET_CODE (rld[r].in) == REG
7120 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7121 && ! reg_has_output_reload[REGNO (rld[r].in)])
7122 || (GET_CODE (rld[r].in_reg) == REG
7123 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7124 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7130 if (GET_CODE (rld[r].in) == REG
7131 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7133 else if (GET_CODE (rld[r].in_reg) == REG)
7136 in = XEXP (rld[r].in_reg, 0);
7137 nregno = REGNO (in);
7139 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7140 : HARD_REGNO_NREGS (nregno,
7141 GET_MODE (rld[r].reg_rtx)));
7143 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7145 if (nregno < FIRST_PSEUDO_REGISTER)
7146 for (k = 1; k < nnr; k++)
7147 reg_last_reload_reg[nregno + k]
7149 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7152 /* Unless we inherited this reload, show we haven't
7153 recently done a store.
7154 Previous stores of inherited auto_inc expressions
7155 also have to be discarded. */
7156 if (! reload_inherited[r]
7157 || (rld[r].out && ! rld[r].out_reg))
7158 spill_reg_store[i] = 0;
7160 for (k = 0; k < nr; k++)
7162 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7163 reg_reloaded_contents[i + k]
7164 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7167 reg_reloaded_insn[i + k] = insn;
7168 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7169 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7170 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7175 /* However, if part of the reload reaches the end, then we must
7176 invalidate the old info for the part that survives to the end. */
7177 else if (part_reaches_end)
7179 for (k = 0; k < nr; k++)
7180 if (reload_reg_reaches_end_p (i + k,
7182 rld[r].when_needed))
7183 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7187 /* The following if-statement was #if 0'd in 1.34 (or before...).
7188 It's reenabled in 1.35 because supposedly nothing else
7189 deals with this problem. */
7191 /* If a register gets output-reloaded from a non-spill register,
7192 that invalidates any previous reloaded copy of it.
7193 But forget_old_reloads_1 won't get to see it, because
7194 it thinks only about the original insn. So invalidate it here. */
7195 if (i < 0 && rld[r].out != 0
7196 && (GET_CODE (rld[r].out) == REG
7197 || (GET_CODE (rld[r].out) == MEM
7198 && GET_CODE (rld[r].out_reg) == REG)))
7200 rtx out = (GET_CODE (rld[r].out) == REG
7201 ? rld[r].out : rld[r].out_reg);
7202 int nregno = REGNO (out);
7203 if (nregno >= FIRST_PSEUDO_REGISTER)
7205 rtx src_reg, store_insn = NULL_RTX;
7207 reg_last_reload_reg[nregno] = 0;
7209 /* If we can find a hard register that is stored, record
7210 the storing insn so that we may delete this insn with
7211 delete_output_reload. */
7212 src_reg = rld[r].reg_rtx;
7214 /* If this is an optional reload, try to find the source reg
7215 from an input reload. */
7218 rtx set = single_set (insn);
7219 if (set && SET_DEST (set) == rld[r].out)
7223 src_reg = SET_SRC (set);
7225 for (k = 0; k < n_reloads; k++)
7227 if (rld[k].in == src_reg)
7229 src_reg = rld[k].reg_rtx;
7236 store_insn = new_spill_reg_store[REGNO (src_reg)];
7237 if (src_reg && GET_CODE (src_reg) == REG
7238 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7240 int src_regno = REGNO (src_reg);
7241 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7242 /* The place where to find a death note varies with
7243 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7244 necessarily checked exactly in the code that moves
7245 notes, so just check both locations. */
7246 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7247 if (! note && store_insn)
7248 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7251 spill_reg_store[src_regno + nr] = store_insn;
7252 spill_reg_stored_to[src_regno + nr] = out;
7253 reg_reloaded_contents[src_regno + nr] = nregno;
7254 reg_reloaded_insn[src_regno + nr] = store_insn;
7255 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7256 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7257 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7258 GET_MODE (src_reg)))
7259 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7261 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7263 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7265 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7267 reg_last_reload_reg[nregno] = src_reg;
7272 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7274 while (num_regs-- > 0)
7275 reg_last_reload_reg[nregno + num_regs] = 0;
7279 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7282 /* Emit code to perform a reload from IN (which may be a reload register) to
7283 OUT (which may also be a reload register). IN or OUT is from operand
7284 OPNUM with reload type TYPE.
7286 Returns first insn emitted. */
7289 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7291 rtx last = get_last_insn ();
7294 /* If IN is a paradoxical SUBREG, remove it and try to put the
7295 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7296 if (GET_CODE (in) == SUBREG
7297 && (GET_MODE_SIZE (GET_MODE (in))
7298 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7299 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7300 in = SUBREG_REG (in), out = tem;
7301 else if (GET_CODE (out) == SUBREG
7302 && (GET_MODE_SIZE (GET_MODE (out))
7303 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7304 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7305 out = SUBREG_REG (out), in = tem;
7307 /* How to do this reload can get quite tricky. Normally, we are being
7308 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7309 register that didn't get a hard register. In that case we can just
7310 call emit_move_insn.
7312 We can also be asked to reload a PLUS that adds a register or a MEM to
7313 another register, constant or MEM. This can occur during frame pointer
7314 elimination and while reloading addresses. This case is handled by
7315 trying to emit a single insn to perform the add. If it is not valid,
7316 we use a two insn sequence.
7318 Finally, we could be called to handle an 'o' constraint by putting
7319 an address into a register. In that case, we first try to do this
7320 with a named pattern of "reload_load_address". If no such pattern
7321 exists, we just emit a SET insn and hope for the best (it will normally
7322 be valid on machines that use 'o').
7324 This entire process is made complex because reload will never
7325 process the insns we generate here and so we must ensure that
7326 they will fit their constraints and also by the fact that parts of
7327 IN might be being reloaded separately and replaced with spill registers.
7328 Because of this, we are, in some sense, just guessing the right approach
7329 here. The one listed above seems to work.
7331 ??? At some point, this whole thing needs to be rethought. */
7333 if (GET_CODE (in) == PLUS
7334 && (GET_CODE (XEXP (in, 0)) == REG
7335 || GET_CODE (XEXP (in, 0)) == SUBREG
7336 || GET_CODE (XEXP (in, 0)) == MEM)
7337 && (GET_CODE (XEXP (in, 1)) == REG
7338 || GET_CODE (XEXP (in, 1)) == SUBREG
7339 || CONSTANT_P (XEXP (in, 1))
7340 || GET_CODE (XEXP (in, 1)) == MEM))
7342 /* We need to compute the sum of a register or a MEM and another
7343 register, constant, or MEM, and put it into the reload
7344 register. The best possible way of doing this is if the machine
7345 has a three-operand ADD insn that accepts the required operands.
7347 The simplest approach is to try to generate such an insn and see if it
7348 is recognized and matches its constraints. If so, it can be used.
7350 It might be better not to actually emit the insn unless it is valid,
7351 but we need to pass the insn as an operand to `recog' and
7352 `extract_insn' and it is simpler to emit and then delete the insn if
7353 not valid than to dummy things up. */
7355 rtx op0, op1, tem, insn;
7358 op0 = find_replacement (&XEXP (in, 0));
7359 op1 = find_replacement (&XEXP (in, 1));
7361 /* Since constraint checking is strict, commutativity won't be
7362 checked, so we need to do that here to avoid spurious failure
7363 if the add instruction is two-address and the second operand
7364 of the add is the same as the reload reg, which is frequently
7365 the case. If the insn would be A = B + A, rearrange it so
7366 it will be A = A + B as constrain_operands expects. */
7368 if (GET_CODE (XEXP (in, 1)) == REG
7369 && REGNO (out) == REGNO (XEXP (in, 1)))
7370 tem = op0, op0 = op1, op1 = tem;
7372 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7373 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7375 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7376 code = recog_memoized (insn);
7380 extract_insn (insn);
7381 /* We want constrain operands to treat this insn strictly in
7382 its validity determination, i.e., the way it would after reload
7384 if (constrain_operands (1))
7388 delete_insns_since (last);
7390 /* If that failed, we must use a conservative two-insn sequence.
7392 Use a move to copy one operand into the reload register. Prefer
7393 to reload a constant, MEM or pseudo since the move patterns can
7394 handle an arbitrary operand. If OP1 is not a constant, MEM or
7395 pseudo and OP1 is not a valid operand for an add instruction, then
7398 After reloading one of the operands into the reload register, add
7399 the reload register to the output register.
7401 If there is another way to do this for a specific machine, a
7402 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7405 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7407 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7408 || (GET_CODE (op1) == REG
7409 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7410 || (code != CODE_FOR_nothing
7411 && ! ((*insn_data[code].operand[2].predicate)
7412 (op1, insn_data[code].operand[2].mode))))
7413 tem = op0, op0 = op1, op1 = tem;
7415 gen_reload (out, op0, opnum, type);
7417 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7418 This fixes a problem on the 32K where the stack pointer cannot
7419 be used as an operand of an add insn. */
7421 if (rtx_equal_p (op0, op1))
7424 insn = emit_insn (gen_add2_insn (out, op1));
7426 /* If that failed, copy the address register to the reload register.
7427 Then add the constant to the reload register. */
7429 code = recog_memoized (insn);
7433 extract_insn (insn);
7434 /* We want constrain operands to treat this insn strictly in
7435 its validity determination, i.e., the way it would after reload
7437 if (constrain_operands (1))
7439 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7441 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7446 delete_insns_since (last);
7448 gen_reload (out, op1, opnum, type);
7449 insn = emit_insn (gen_add2_insn (out, op0));
7450 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7453 #ifdef SECONDARY_MEMORY_NEEDED
7454 /* If we need a memory location to do the move, do it that way. */
7455 else if ((GET_CODE (in) == REG || GET_CODE (in) == SUBREG)
7456 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7457 && (GET_CODE (out) == REG || GET_CODE (out) == SUBREG)
7458 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7459 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7460 REGNO_REG_CLASS (reg_or_subregno (out)),
7463 /* Get the memory to use and rewrite both registers to its mode. */
7464 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7466 if (GET_MODE (loc) != GET_MODE (out))
7467 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7469 if (GET_MODE (loc) != GET_MODE (in))
7470 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7472 gen_reload (loc, in, opnum, type);
7473 gen_reload (out, loc, opnum, type);
7477 /* If IN is a simple operand, use gen_move_insn. */
7478 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7479 emit_insn (gen_move_insn (out, in));
7481 #ifdef HAVE_reload_load_address
7482 else if (HAVE_reload_load_address)
7483 emit_insn (gen_reload_load_address (out, in));
7486 /* Otherwise, just write (set OUT IN) and hope for the best. */
7488 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7490 /* Return the first insn emitted.
7491 We can not just return get_last_insn, because there may have
7492 been multiple instructions emitted. Also note that gen_move_insn may
7493 emit more than one insn itself, so we can not assume that there is one
7494 insn emitted per emit_insn_before call. */
7496 return last ? NEXT_INSN (last) : get_insns ();
7499 /* Delete a previously made output-reload whose result we now believe
7500 is not needed. First we double-check.
7502 INSN is the insn now being processed.
7503 LAST_RELOAD_REG is the hard register number for which we want to delete
7504 the last output reload.
7505 J is the reload-number that originally used REG. The caller has made
7506 certain that reload J doesn't use REG any longer for input. */
7509 delete_output_reload (rtx insn, int j, int last_reload_reg)
7511 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7512 rtx reg = spill_reg_stored_to[last_reload_reg];
7515 int n_inherited = 0;
7519 /* It is possible that this reload has been only used to set another reload
7520 we eliminated earlier and thus deleted this instruction too. */
7521 if (INSN_DELETED_P (output_reload_insn))
7524 /* Get the raw pseudo-register referred to. */
7526 while (GET_CODE (reg) == SUBREG)
7527 reg = SUBREG_REG (reg);
7528 substed = reg_equiv_memory_loc[REGNO (reg)];
7530 /* This is unsafe if the operand occurs more often in the current
7531 insn than it is inherited. */
7532 for (k = n_reloads - 1; k >= 0; k--)
7534 rtx reg2 = rld[k].in;
7537 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7538 reg2 = rld[k].in_reg;
7540 if (rld[k].out && ! rld[k].out_reg)
7541 reg2 = XEXP (rld[k].in_reg, 0);
7543 while (GET_CODE (reg2) == SUBREG)
7544 reg2 = SUBREG_REG (reg2);
7545 if (rtx_equal_p (reg2, reg))
7547 if (reload_inherited[k] || reload_override_in[k] || k == j)
7550 reg2 = rld[k].out_reg;
7553 while (GET_CODE (reg2) == SUBREG)
7554 reg2 = XEXP (reg2, 0);
7555 if (rtx_equal_p (reg2, reg))
7562 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7564 n_occurrences += count_occurrences (PATTERN (insn),
7565 eliminate_regs (substed, 0,
7567 if (n_occurrences > n_inherited)
7570 /* If the pseudo-reg we are reloading is no longer referenced
7571 anywhere between the store into it and here,
7572 and no jumps or labels intervene, then the value can get
7573 here through the reload reg alone.
7574 Otherwise, give up--return. */
7575 for (i1 = NEXT_INSN (output_reload_insn);
7576 i1 != insn; i1 = NEXT_INSN (i1))
7578 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7580 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7581 && reg_mentioned_p (reg, PATTERN (i1)))
7583 /* If this is USE in front of INSN, we only have to check that
7584 there are no more references than accounted for by inheritance. */
7585 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7587 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7588 i1 = NEXT_INSN (i1);
7590 if (n_occurrences <= n_inherited && i1 == insn)
7596 /* We will be deleting the insn. Remove the spill reg information. */
7597 for (k = HARD_REGNO_NREGS (last_reload_reg, GET_MODE (reg)); k-- > 0; )
7599 spill_reg_store[last_reload_reg + k] = 0;
7600 spill_reg_stored_to[last_reload_reg + k] = 0;
7603 /* The caller has already checked that REG dies or is set in INSN.
7604 It has also checked that we are optimizing, and thus some
7605 inaccuracies in the debugging information are acceptable.
7606 So we could just delete output_reload_insn. But in some cases
7607 we can improve the debugging information without sacrificing
7608 optimization - maybe even improving the code: See if the pseudo
7609 reg has been completely replaced with reload regs. If so, delete
7610 the store insn and forget we had a stack slot for the pseudo. */
7611 if (rld[j].out != rld[j].in
7612 && REG_N_DEATHS (REGNO (reg)) == 1
7613 && REG_N_SETS (REGNO (reg)) == 1
7614 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7615 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7619 /* We know that it was used only between here and the beginning of
7620 the current basic block. (We also know that the last use before
7621 INSN was the output reload we are thinking of deleting, but never
7622 mind that.) Search that range; see if any ref remains. */
7623 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7625 rtx set = single_set (i2);
7627 /* Uses which just store in the pseudo don't count,
7628 since if they are the only uses, they are dead. */
7629 if (set != 0 && SET_DEST (set) == reg)
7631 if (GET_CODE (i2) == CODE_LABEL
7632 || GET_CODE (i2) == JUMP_INSN)
7634 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7635 && reg_mentioned_p (reg, PATTERN (i2)))
7637 /* Some other ref remains; just delete the output reload we
7639 delete_address_reloads (output_reload_insn, insn);
7640 delete_insn (output_reload_insn);
7645 /* Delete the now-dead stores into this pseudo. Note that this
7646 loop also takes care of deleting output_reload_insn. */
7647 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7649 rtx set = single_set (i2);
7651 if (set != 0 && SET_DEST (set) == reg)
7653 delete_address_reloads (i2, insn);
7656 if (GET_CODE (i2) == CODE_LABEL
7657 || GET_CODE (i2) == JUMP_INSN)
7661 /* For the debugging info, say the pseudo lives in this reload reg. */
7662 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7663 alter_reg (REGNO (reg), -1);
7667 delete_address_reloads (output_reload_insn, insn);
7668 delete_insn (output_reload_insn);
7672 /* We are going to delete DEAD_INSN. Recursively delete loads of
7673 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7674 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7676 delete_address_reloads (rtx dead_insn, rtx current_insn)
7678 rtx set = single_set (dead_insn);
7679 rtx set2, dst, prev, next;
7682 rtx dst = SET_DEST (set);
7683 if (GET_CODE (dst) == MEM)
7684 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7686 /* If we deleted the store from a reloaded post_{in,de}c expression,
7687 we can delete the matching adds. */
7688 prev = PREV_INSN (dead_insn);
7689 next = NEXT_INSN (dead_insn);
7690 if (! prev || ! next)
7692 set = single_set (next);
7693 set2 = single_set (prev);
7695 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7696 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7697 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7699 dst = SET_DEST (set);
7700 if (! rtx_equal_p (dst, SET_DEST (set2))
7701 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7702 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7703 || (INTVAL (XEXP (SET_SRC (set), 1))
7704 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7706 delete_related_insns (prev);
7707 delete_related_insns (next);
7710 /* Subfunction of delete_address_reloads: process registers found in X. */
7712 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
7714 rtx prev, set, dst, i2;
7716 enum rtx_code code = GET_CODE (x);
7720 const char *fmt = GET_RTX_FORMAT (code);
7721 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7724 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7725 else if (fmt[i] == 'E')
7727 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7728 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7735 if (spill_reg_order[REGNO (x)] < 0)
7738 /* Scan backwards for the insn that sets x. This might be a way back due
7740 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7742 code = GET_CODE (prev);
7743 if (code == CODE_LABEL || code == JUMP_INSN)
7745 if (GET_RTX_CLASS (code) != 'i')
7747 if (reg_set_p (x, PATTERN (prev)))
7749 if (reg_referenced_p (x, PATTERN (prev)))
7752 if (! prev || INSN_UID (prev) < reload_first_uid)
7754 /* Check that PREV only sets the reload register. */
7755 set = single_set (prev);
7758 dst = SET_DEST (set);
7759 if (GET_CODE (dst) != REG
7760 || ! rtx_equal_p (dst, x))
7762 if (! reg_set_p (dst, PATTERN (dead_insn)))
7764 /* Check if DST was used in a later insn -
7765 it might have been inherited. */
7766 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7768 if (GET_CODE (i2) == CODE_LABEL)
7772 if (reg_referenced_p (dst, PATTERN (i2)))
7774 /* If there is a reference to the register in the current insn,
7775 it might be loaded in a non-inherited reload. If no other
7776 reload uses it, that means the register is set before
7778 if (i2 == current_insn)
7780 for (j = n_reloads - 1; j >= 0; j--)
7781 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7782 || reload_override_in[j] == dst)
7784 for (j = n_reloads - 1; j >= 0; j--)
7785 if (rld[j].in && rld[j].reg_rtx == dst)
7792 if (GET_CODE (i2) == JUMP_INSN)
7794 /* If DST is still live at CURRENT_INSN, check if it is used for
7795 any reload. Note that even if CURRENT_INSN sets DST, we still
7796 have to check the reloads. */
7797 if (i2 == current_insn)
7799 for (j = n_reloads - 1; j >= 0; j--)
7800 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7801 || reload_override_in[j] == dst)
7803 /* ??? We can't finish the loop here, because dst might be
7804 allocated to a pseudo in this block if no reload in this
7805 block needs any of the classes containing DST - see
7806 spill_hard_reg. There is no easy way to tell this, so we
7807 have to scan till the end of the basic block. */
7809 if (reg_set_p (dst, PATTERN (i2)))
7813 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7814 reg_reloaded_contents[REGNO (dst)] = -1;
7818 /* Output reload-insns to reload VALUE into RELOADREG.
7819 VALUE is an autoincrement or autodecrement RTX whose operand
7820 is a register or memory location;
7821 so reloading involves incrementing that location.
7822 IN is either identical to VALUE, or some cheaper place to reload from.
7824 INC_AMOUNT is the number to increment or decrement by (always positive).
7825 This cannot be deduced from VALUE.
7827 Return the instruction that stores into RELOADREG. */
7830 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
7832 /* REG or MEM to be copied and incremented. */
7833 rtx incloc = XEXP (value, 0);
7834 /* Nonzero if increment after copying. */
7835 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7841 rtx real_in = in == value ? XEXP (in, 0) : in;
7843 /* No hard register is equivalent to this register after
7844 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7845 we could inc/dec that register as well (maybe even using it for
7846 the source), but I'm not sure it's worth worrying about. */
7847 if (GET_CODE (incloc) == REG)
7848 reg_last_reload_reg[REGNO (incloc)] = 0;
7850 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7851 inc_amount = -inc_amount;
7853 inc = GEN_INT (inc_amount);
7855 /* If this is post-increment, first copy the location to the reload reg. */
7856 if (post && real_in != reloadreg)
7857 emit_insn (gen_move_insn (reloadreg, real_in));
7861 /* See if we can directly increment INCLOC. Use a method similar to
7862 that in gen_reload. */
7864 last = get_last_insn ();
7865 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7866 gen_rtx_PLUS (GET_MODE (incloc),
7869 code = recog_memoized (add_insn);
7872 extract_insn (add_insn);
7873 if (constrain_operands (1))
7875 /* If this is a pre-increment and we have incremented the value
7876 where it lives, copy the incremented value to RELOADREG to
7877 be used as an address. */
7880 emit_insn (gen_move_insn (reloadreg, incloc));
7885 delete_insns_since (last);
7888 /* If couldn't do the increment directly, must increment in RELOADREG.
7889 The way we do this depends on whether this is pre- or post-increment.
7890 For pre-increment, copy INCLOC to the reload register, increment it
7891 there, then save back. */
7895 if (in != reloadreg)
7896 emit_insn (gen_move_insn (reloadreg, real_in));
7897 emit_insn (gen_add2_insn (reloadreg, inc));
7898 store = emit_insn (gen_move_insn (incloc, reloadreg));
7903 Because this might be a jump insn or a compare, and because RELOADREG
7904 may not be available after the insn in an input reload, we must do
7905 the incrementation before the insn being reloaded for.
7907 We have already copied IN to RELOADREG. Increment the copy in
7908 RELOADREG, save that back, then decrement RELOADREG so it has
7909 the original value. */
7911 emit_insn (gen_add2_insn (reloadreg, inc));
7912 store = emit_insn (gen_move_insn (incloc, reloadreg));
7913 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7921 add_auto_inc_notes (rtx insn, rtx x)
7923 enum rtx_code code = GET_CODE (x);
7927 if (code == MEM && auto_inc_p (XEXP (x, 0)))
7930 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
7934 /* Scan all the operand sub-expressions. */
7935 fmt = GET_RTX_FORMAT (code);
7936 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7939 add_auto_inc_notes (insn, XEXP (x, i));
7940 else if (fmt[i] == 'E')
7941 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7942 add_auto_inc_notes (insn, XVECEXP (x, i, j));
7947 /* Copy EH notes from an insn to its reloads. */
7949 copy_eh_notes (rtx insn, rtx x)
7951 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
7954 for (; x != 0; x = NEXT_INSN (x))
7956 if (may_trap_p (PATTERN (x)))
7958 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
7964 /* This is used by reload pass, that does emit some instructions after
7965 abnormal calls moving basic block end, but in fact it wants to emit
7966 them on the edge. Looks for abnormal call edges, find backward the
7967 proper call and fix the damage.
7969 Similar handle instructions throwing exceptions internally. */
7971 fixup_abnormal_edges (void)
7973 bool inserted = false;
7980 /* Look for cases we are interested in - calls or instructions causing
7982 for (e = bb->succ; e; e = e->succ_next)
7984 if (e->flags & EDGE_ABNORMAL_CALL)
7986 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
7987 == (EDGE_ABNORMAL | EDGE_EH))
7990 if (e && GET_CODE (BB_END (bb)) != CALL_INSN
7991 && !can_throw_internal (BB_END (bb)))
7993 rtx insn = BB_END (bb), stop = NEXT_INSN (BB_END (bb));
7995 for (e = bb->succ; e; e = e->succ_next)
7996 if (e->flags & EDGE_FALLTHRU)
7998 /* Get past the new insns generated. Allow notes, as the insns may
7999 be already deleted. */
8000 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE)
8001 && !can_throw_internal (insn)
8002 && insn != BB_HEAD (bb))
8003 insn = PREV_INSN (insn);
8004 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn))
8008 insn = NEXT_INSN (insn);
8009 while (insn && insn != stop)
8011 next = NEXT_INSN (insn);
8016 /* Sometimes there's still the return value USE.
8017 If it's placed after a trapping call (i.e. that
8018 call is the last insn anyway), we have no fallthru
8019 edge. Simply delete this use and don't try to insert
8020 on the non-existent edge. */
8021 if (GET_CODE (PATTERN (insn)) != USE)
8023 /* We're not deleting it, we're moving it. */
8024 INSN_DELETED_P (insn) = 0;
8025 PREV_INSN (insn) = NULL_RTX;
8026 NEXT_INSN (insn) = NULL_RTX;
8028 insert_insn_on_edge (insn, e);
8035 /* We've possibly turned single trapping insn into multiple ones. */
8036 if (flag_non_call_exceptions)
8039 blocks = sbitmap_alloc (last_basic_block);
8040 sbitmap_ones (blocks);
8041 find_many_sub_basic_blocks (blocks);
8044 commit_edge_insertions ();
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