1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "insn-flags.h"
32 #include "insn-codes.h"
37 #include "basic-block.h"
45 #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY
46 #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
49 /* This file contains the reload pass of the compiler, which is
50 run after register allocation has been done. It checks that
51 each insn is valid (operands required to be in registers really
52 are in registers of the proper class) and fixes up invalid ones
53 by copying values temporarily into registers for the insns
56 The results of register allocation are described by the vector
57 reg_renumber; the insns still contain pseudo regs, but reg_renumber
58 can be used to find which hard reg, if any, a pseudo reg is in.
60 The technique we always use is to free up a few hard regs that are
61 called ``reload regs'', and for each place where a pseudo reg
62 must be in a hard reg, copy it temporarily into one of the reload regs.
64 Reload regs are allocated locally for every instruction that needs
65 reloads. When there are pseudos which are allocated to a register that
66 has been chosen as a reload reg, such pseudos must be ``spilled''.
67 This means that they go to other hard regs, or to stack slots if no other
68 available hard regs can be found. Spilling can invalidate more
69 insns, requiring additional need for reloads, so we must keep checking
70 until the process stabilizes.
72 For machines with different classes of registers, we must keep track
73 of the register class needed for each reload, and make sure that
74 we allocate enough reload registers of each class.
76 The file reload.c contains the code that checks one insn for
77 validity and reports the reloads that it needs. This file
78 is in charge of scanning the entire rtl code, accumulating the
79 reload needs, spilling, assigning reload registers to use for
80 fixing up each insn, and generating the new insns to copy values
81 into the reload registers. */
83 #ifndef REGISTER_MOVE_COST
84 #define REGISTER_MOVE_COST(x, y) 2
88 #define LOCAL_REGNO(REGNO) 0
91 /* During reload_as_needed, element N contains a REG rtx for the hard reg
92 into which reg N has been reloaded (perhaps for a previous insn). */
93 static rtx *reg_last_reload_reg;
95 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
96 for an output reload that stores into reg N. */
97 static char *reg_has_output_reload;
99 /* Indicates which hard regs are reload-registers for an output reload
100 in the current insn. */
101 static HARD_REG_SET reg_is_output_reload;
103 /* Element N is the constant value to which pseudo reg N is equivalent,
104 or zero if pseudo reg N is not equivalent to a constant.
105 find_reloads looks at this in order to replace pseudo reg N
106 with the constant it stands for. */
107 rtx *reg_equiv_constant;
109 /* Element N is a memory location to which pseudo reg N is equivalent,
110 prior to any register elimination (such as frame pointer to stack
111 pointer). Depending on whether or not it is a valid address, this value
112 is transferred to either reg_equiv_address or reg_equiv_mem. */
113 rtx *reg_equiv_memory_loc;
115 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
116 This is used when the address is not valid as a memory address
117 (because its displacement is too big for the machine.) */
118 rtx *reg_equiv_address;
120 /* Element N is the memory slot to which pseudo reg N is equivalent,
121 or zero if pseudo reg N is not equivalent to a memory slot. */
124 /* Widest width in which each pseudo reg is referred to (via subreg). */
125 static unsigned int *reg_max_ref_width;
127 /* Element N is the list of insns that initialized reg N from its equivalent
128 constant or memory slot. */
129 static rtx *reg_equiv_init;
131 /* Vector to remember old contents of reg_renumber before spilling. */
132 static short *reg_old_renumber;
134 /* During reload_as_needed, element N contains the last pseudo regno reloaded
135 into hard register N. If that pseudo reg occupied more than one register,
136 reg_reloaded_contents points to that pseudo for each spill register in
137 use; all of these must remain set for an inheritance to occur. */
138 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
140 /* During reload_as_needed, element N contains the insn for which
141 hard register N was last used. Its contents are significant only
142 when reg_reloaded_valid is set for this register. */
143 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
145 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
146 static HARD_REG_SET reg_reloaded_valid;
147 /* Indicate if the register was dead at the end of the reload.
148 This is only valid if reg_reloaded_contents is set and valid. */
149 static HARD_REG_SET reg_reloaded_dead;
151 /* Number of spill-regs so far; number of valid elements of spill_regs. */
154 /* In parallel with spill_regs, contains REG rtx's for those regs.
155 Holds the last rtx used for any given reg, or 0 if it has never
156 been used for spilling yet. This rtx is reused, provided it has
158 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
160 /* In parallel with spill_regs, contains nonzero for a spill reg
161 that was stored after the last time it was used.
162 The precise value is the insn generated to do the store. */
163 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
165 /* This is the register that was stored with spill_reg_store. This is a
166 copy of reload_out / reload_out_reg when the value was stored; if
167 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
168 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
170 /* This table is the inverse mapping of spill_regs:
171 indexed by hard reg number,
172 it contains the position of that reg in spill_regs,
173 or -1 for something that is not in spill_regs.
175 ?!? This is no longer accurate. */
176 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
178 /* This reg set indicates registers that can't be used as spill registers for
179 the currently processed insn. These are the hard registers which are live
180 during the insn, but not allocated to pseudos, as well as fixed
182 static HARD_REG_SET bad_spill_regs;
184 /* These are the hard registers that can't be used as spill register for any
185 insn. This includes registers used for user variables and registers that
186 we can't eliminate. A register that appears in this set also can't be used
187 to retry register allocation. */
188 static HARD_REG_SET bad_spill_regs_global;
190 /* Describes order of use of registers for reloading
191 of spilled pseudo-registers. `n_spills' is the number of
192 elements that are actually valid; new ones are added at the end.
194 Both spill_regs and spill_reg_order are used on two occasions:
195 once during find_reload_regs, where they keep track of the spill registers
196 for a single insn, but also during reload_as_needed where they show all
197 the registers ever used by reload. For the latter case, the information
198 is calculated during finish_spills. */
199 static short spill_regs[FIRST_PSEUDO_REGISTER];
201 /* This vector of reg sets indicates, for each pseudo, which hard registers
202 may not be used for retrying global allocation because the register was
203 formerly spilled from one of them. If we allowed reallocating a pseudo to
204 a register that it was already allocated to, reload might not
206 static HARD_REG_SET *pseudo_previous_regs;
208 /* This vector of reg sets indicates, for each pseudo, which hard
209 registers may not be used for retrying global allocation because they
210 are used as spill registers during one of the insns in which the
212 static HARD_REG_SET *pseudo_forbidden_regs;
214 /* All hard regs that have been used as spill registers for any insn are
215 marked in this set. */
216 static HARD_REG_SET used_spill_regs;
218 /* Index of last register assigned as a spill register. We allocate in
219 a round-robin fashion. */
220 static int last_spill_reg;
222 /* Nonzero if indirect addressing is supported on the machine; this means
223 that spilling (REG n) does not require reloading it into a register in
224 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
225 value indicates the level of indirect addressing supported, e.g., two
226 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
228 static char spill_indirect_levels;
230 /* Nonzero if indirect addressing is supported when the innermost MEM is
231 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
232 which these are valid is the same as spill_indirect_levels, above. */
233 char indirect_symref_ok;
235 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
236 char double_reg_address_ok;
238 /* Record the stack slot for each spilled hard register. */
239 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
241 /* Width allocated so far for that stack slot. */
242 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
244 /* Record which pseudos needed to be spilled. */
245 static regset_head spilled_pseudos;
247 /* Used for communication between order_regs_for_reload and count_pseudo.
248 Used to avoid counting one pseudo twice. */
249 static regset_head pseudos_counted;
251 /* First uid used by insns created by reload in this function.
252 Used in find_equiv_reg. */
253 int reload_first_uid;
255 /* Flag set by local-alloc or global-alloc if anything is live in
256 a call-clobbered reg across calls. */
257 int caller_save_needed;
259 /* Set to 1 while reload_as_needed is operating.
260 Required by some machines to handle any generated moves differently. */
261 int reload_in_progress = 0;
263 /* These arrays record the insn_code of insns that may be needed to
264 perform input and output reloads of special objects. They provide a
265 place to pass a scratch register. */
266 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
267 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
269 /* This obstack is used for allocation of rtl during register elimination.
270 The allocated storage can be freed once find_reloads has processed the
272 struct obstack reload_obstack;
274 /* Points to the beginning of the reload_obstack. All insn_chain structures
275 are allocated first. */
276 char *reload_startobj;
278 /* The point after all insn_chain structures. Used to quickly deallocate
279 memory allocated in copy_reloads during calculate_needs_all_insns. */
280 char *reload_firstobj;
282 /* This points before all local rtl generated by register elimination.
283 Used to quickly free all memory after processing one insn. */
284 static char *reload_insn_firstobj;
286 #define obstack_chunk_alloc xmalloc
287 #define obstack_chunk_free free
289 /* List of insn_chain instructions, one for every insn that reload needs to
291 struct insn_chain *reload_insn_chain;
294 extern tree current_function_decl;
296 extern union tree_node *current_function_decl;
299 /* List of all insns needing reloads. */
300 static struct insn_chain *insns_need_reload;
302 /* This structure is used to record information about register eliminations.
303 Each array entry describes one possible way of eliminating a register
304 in favor of another. If there is more than one way of eliminating a
305 particular register, the most preferred should be specified first. */
309 int from; /* Register number to be eliminated. */
310 int to; /* Register number used as replacement. */
311 int initial_offset; /* Initial difference between values. */
312 int can_eliminate; /* Non-zero if this elimination can be done. */
313 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
314 insns made by reload. */
315 int offset; /* Current offset between the two regs. */
316 int previous_offset; /* Offset at end of previous insn. */
317 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
318 rtx from_rtx; /* REG rtx for the register to be eliminated.
319 We cannot simply compare the number since
320 we might then spuriously replace a hard
321 register corresponding to a pseudo
322 assigned to the reg to be eliminated. */
323 rtx to_rtx; /* REG rtx for the replacement. */
326 static struct elim_table *reg_eliminate = 0;
328 /* This is an intermediate structure to initialize the table. It has
329 exactly the members provided by ELIMINABLE_REGS. */
330 static struct elim_table_1
334 } reg_eliminate_1[] =
336 /* If a set of eliminable registers was specified, define the table from it.
337 Otherwise, default to the normal case of the frame pointer being
338 replaced by the stack pointer. */
340 #ifdef ELIMINABLE_REGS
343 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
346 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
348 /* Record the number of pending eliminations that have an offset not equal
349 to their initial offset. If non-zero, we use a new copy of each
350 replacement result in any insns encountered. */
351 int num_not_at_initial_offset;
353 /* Count the number of registers that we may be able to eliminate. */
354 static int num_eliminable;
355 /* And the number of registers that are equivalent to a constant that
356 can be eliminated to frame_pointer / arg_pointer + constant. */
357 static int num_eliminable_invariants;
359 /* For each label, we record the offset of each elimination. If we reach
360 a label by more than one path and an offset differs, we cannot do the
361 elimination. This information is indexed by the number of the label.
362 The first table is an array of flags that records whether we have yet
363 encountered a label and the second table is an array of arrays, one
364 entry in the latter array for each elimination. */
366 static char *offsets_known_at;
367 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
369 /* Number of labels in the current function. */
371 static int num_labels;
373 static void maybe_fix_stack_asms PARAMS ((void));
374 static void copy_reloads PARAMS ((struct insn_chain *));
375 static void calculate_needs_all_insns PARAMS ((int));
376 static int find_reg PARAMS ((struct insn_chain *, int));
377 static void find_reload_regs PARAMS ((struct insn_chain *));
378 static void select_reload_regs PARAMS ((void));
379 static void delete_caller_save_insns PARAMS ((void));
381 static void spill_failure PARAMS ((rtx, enum reg_class));
382 static void count_spilled_pseudo PARAMS ((int, int, int));
383 static void delete_dead_insn PARAMS ((rtx));
384 static void alter_reg PARAMS ((int, int));
385 static void set_label_offsets PARAMS ((rtx, rtx, int));
386 static void check_eliminable_occurrences PARAMS ((rtx));
387 static void elimination_effects PARAMS ((rtx, enum machine_mode));
388 static int eliminate_regs_in_insn PARAMS ((rtx, int));
389 static void update_eliminable_offsets PARAMS ((void));
390 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
391 static void set_initial_elim_offsets PARAMS ((void));
392 static void verify_initial_elim_offsets PARAMS ((void));
393 static void set_initial_label_offsets PARAMS ((void));
394 static void set_offsets_for_label PARAMS ((rtx));
395 static void init_elim_table PARAMS ((void));
396 static void update_eliminables PARAMS ((HARD_REG_SET *));
397 static void spill_hard_reg PARAMS ((unsigned int, int));
398 static int finish_spills PARAMS ((int));
399 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
400 static void scan_paradoxical_subregs PARAMS ((rtx));
401 static void count_pseudo PARAMS ((int));
402 static void order_regs_for_reload PARAMS ((struct insn_chain *));
403 static void reload_as_needed PARAMS ((int));
404 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
405 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
406 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
409 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
412 static int reload_reg_free_p PARAMS ((unsigned int, int,
414 static int reload_reg_free_for_value_p PARAMS ((int, int, enum reload_type,
415 rtx, rtx, int, int));
416 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
418 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
420 static void failed_reload PARAMS ((rtx, int));
421 static int set_reload_reg PARAMS ((int, int));
422 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
423 static void choose_reload_regs PARAMS ((struct insn_chain *));
424 static void merge_assigned_reloads PARAMS ((rtx));
425 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
426 struct reload *, rtx, int));
427 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
428 struct reload *, int));
429 static void do_input_reload PARAMS ((struct insn_chain *,
430 struct reload *, int));
431 static void do_output_reload PARAMS ((struct insn_chain *,
432 struct reload *, int));
433 static void emit_reload_insns PARAMS ((struct insn_chain *));
434 static void delete_output_reload PARAMS ((rtx, int, int));
435 static void delete_address_reloads PARAMS ((rtx, rtx));
436 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
437 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
438 static int constraint_accepts_reg_p PARAMS ((const char *, rtx));
439 static void reload_cse_regs_1 PARAMS ((rtx));
440 static int reload_cse_noop_set_p PARAMS ((rtx));
441 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
442 static int reload_cse_simplify_operands PARAMS ((rtx));
443 static void reload_combine PARAMS ((void));
444 static void reload_combine_note_use PARAMS ((rtx *, rtx));
445 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
446 static void reload_cse_move2add PARAMS ((rtx));
447 static void move2add_note_store PARAMS ((rtx, rtx, void *));
449 static void add_auto_inc_notes PARAMS ((rtx, rtx));
451 static rtx gen_mode_int PARAMS ((enum machine_mode,
453 static void failed_reload PARAMS ((rtx, int));
454 static int set_reload_reg PARAMS ((int, int));
455 static void reload_cse_delete_noop_set PARAMS ((rtx, rtx));
456 static void reload_cse_simplify PARAMS ((rtx));
457 extern void dump_needs PARAMS ((struct insn_chain *));
459 /* Initialize the reload pass once per compilation. */
466 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
467 Set spill_indirect_levels to the number of levels such addressing is
468 permitted, zero if it is not permitted at all. */
471 = gen_rtx_MEM (Pmode,
474 LAST_VIRTUAL_REGISTER + 1),
476 spill_indirect_levels = 0;
478 while (memory_address_p (QImode, tem))
480 spill_indirect_levels++;
481 tem = gen_rtx_MEM (Pmode, tem);
484 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
486 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
487 indirect_symref_ok = memory_address_p (QImode, tem);
489 /* See if reg+reg is a valid (and offsettable) address. */
491 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
493 tem = gen_rtx_PLUS (Pmode,
494 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
495 gen_rtx_REG (Pmode, i));
497 /* This way, we make sure that reg+reg is an offsettable address. */
498 tem = plus_constant (tem, 4);
500 if (memory_address_p (QImode, tem))
502 double_reg_address_ok = 1;
507 /* Initialize obstack for our rtl allocation. */
508 gcc_obstack_init (&reload_obstack);
509 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
511 INIT_REG_SET (&spilled_pseudos);
512 INIT_REG_SET (&pseudos_counted);
515 /* List of insn chains that are currently unused. */
516 static struct insn_chain *unused_insn_chains = 0;
518 /* Allocate an empty insn_chain structure. */
522 struct insn_chain *c;
524 if (unused_insn_chains == 0)
526 c = (struct insn_chain *)
527 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
528 INIT_REG_SET (&c->live_throughout);
529 INIT_REG_SET (&c->dead_or_set);
533 c = unused_insn_chains;
534 unused_insn_chains = c->next;
536 c->is_caller_save_insn = 0;
537 c->need_operand_change = 0;
543 /* Small utility function to set all regs in hard reg set TO which are
544 allocated to pseudos in regset FROM. */
547 compute_use_by_pseudos (to, from)
553 EXECUTE_IF_SET_IN_REG_SET
554 (from, FIRST_PSEUDO_REGISTER, regno,
556 int r = reg_renumber[regno];
561 /* reload_combine uses the information from
562 BASIC_BLOCK->global_live_at_start, which might still
563 contain registers that have not actually been allocated
564 since they have an equivalence. */
565 if (! reload_completed)
570 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
572 SET_HARD_REG_BIT (*to, r + nregs);
577 /* Global variables used by reload and its subroutines. */
579 /* Set during calculate_needs if an insn needs register elimination. */
580 static int something_needs_elimination;
581 /* Set during calculate_needs if an insn needs an operand changed. */
582 int something_needs_operands_changed;
584 /* Nonzero means we couldn't get enough spill regs. */
587 /* Main entry point for the reload pass.
589 FIRST is the first insn of the function being compiled.
591 GLOBAL nonzero means we were called from global_alloc
592 and should attempt to reallocate any pseudoregs that we
593 displace from hard regs we will use for reloads.
594 If GLOBAL is zero, we do not have enough information to do that,
595 so any pseudo reg that is spilled must go to the stack.
597 Return value is nonzero if reload failed
598 and we must not do any more for this function. */
601 reload (first, global)
607 register struct elim_table *ep;
609 /* The two pointers used to track the true location of the memory used
610 for label offsets. */
611 char *real_known_ptr = NULL_PTR;
612 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
614 /* Make sure even insns with volatile mem refs are recognizable. */
619 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
621 /* Make sure that the last insn in the chain
622 is not something that needs reloading. */
623 emit_note (NULL_PTR, NOTE_INSN_DELETED);
625 /* Enable find_equiv_reg to distinguish insns made by reload. */
626 reload_first_uid = get_max_uid ();
628 #ifdef SECONDARY_MEMORY_NEEDED
629 /* Initialize the secondary memory table. */
630 clear_secondary_mem ();
633 /* We don't have a stack slot for any spill reg yet. */
634 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
635 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
637 /* Initialize the save area information for caller-save, in case some
641 /* Compute which hard registers are now in use
642 as homes for pseudo registers.
643 This is done here rather than (eg) in global_alloc
644 because this point is reached even if not optimizing. */
645 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
648 /* A function that receives a nonlocal goto must save all call-saved
650 if (current_function_has_nonlocal_label)
651 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
652 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
653 regs_ever_live[i] = 1;
655 /* Find all the pseudo registers that didn't get hard regs
656 but do have known equivalent constants or memory slots.
657 These include parameters (known equivalent to parameter slots)
658 and cse'd or loop-moved constant memory addresses.
660 Record constant equivalents in reg_equiv_constant
661 so they will be substituted by find_reloads.
662 Record memory equivalents in reg_mem_equiv so they can
663 be substituted eventually by altering the REG-rtx's. */
665 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
666 reg_equiv_memory_loc = (rtx *) xcalloc (max_regno, sizeof (rtx));
667 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
668 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
669 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
670 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
671 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
672 bcopy ((PTR) reg_renumber, (PTR) reg_old_renumber, max_regno * sizeof (short));
673 pseudo_forbidden_regs
674 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
676 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
678 CLEAR_HARD_REG_SET (bad_spill_regs_global);
680 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
681 Also find all paradoxical subregs and find largest such for each pseudo.
682 On machines with small register classes, record hard registers that
683 are used for user variables. These can never be used for spills.
684 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
685 caller-saved registers must be marked live. */
687 num_eliminable_invariants = 0;
688 for (insn = first; insn; insn = NEXT_INSN (insn))
690 rtx set = single_set (insn);
692 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
693 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
694 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
695 if (! call_used_regs[i])
696 regs_ever_live[i] = 1;
698 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
700 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
702 #ifdef LEGITIMATE_PIC_OPERAND_P
703 && (! function_invariant_p (XEXP (note, 0))
705 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
709 rtx x = XEXP (note, 0);
710 i = REGNO (SET_DEST (set));
711 if (i > LAST_VIRTUAL_REGISTER)
713 if (GET_CODE (x) == MEM)
715 /* If the operand is a PLUS, the MEM may be shared,
716 so make sure we have an unshared copy here. */
717 if (GET_CODE (XEXP (x, 0)) == PLUS)
720 reg_equiv_memory_loc[i] = x;
722 else if (function_invariant_p (x))
724 if (GET_CODE (x) == PLUS)
726 /* This is PLUS of frame pointer and a constant,
727 and might be shared. Unshare it. */
728 reg_equiv_constant[i] = copy_rtx (x);
729 num_eliminable_invariants++;
731 else if (x == frame_pointer_rtx
732 || x == arg_pointer_rtx)
734 reg_equiv_constant[i] = x;
735 num_eliminable_invariants++;
737 else if (LEGITIMATE_CONSTANT_P (x))
738 reg_equiv_constant[i] = x;
740 reg_equiv_memory_loc[i]
741 = force_const_mem (GET_MODE (SET_DEST (set)), x);
746 /* If this register is being made equivalent to a MEM
747 and the MEM is not SET_SRC, the equivalencing insn
748 is one with the MEM as a SET_DEST and it occurs later.
749 So don't mark this insn now. */
750 if (GET_CODE (x) != MEM
751 || rtx_equal_p (SET_SRC (set), x))
753 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
758 /* If this insn is setting a MEM from a register equivalent to it,
759 this is the equivalencing insn. */
760 else if (set && GET_CODE (SET_DEST (set)) == MEM
761 && GET_CODE (SET_SRC (set)) == REG
762 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
763 && rtx_equal_p (SET_DEST (set),
764 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
765 reg_equiv_init[REGNO (SET_SRC (set))]
766 = gen_rtx_INSN_LIST (VOIDmode, insn,
767 reg_equiv_init[REGNO (SET_SRC (set))]);
770 scan_paradoxical_subregs (PATTERN (insn));
775 num_labels = max_label_num () - get_first_label_num ();
777 /* Allocate the tables used to store offset information at labels. */
778 /* We used to use alloca here, but the size of what it would try to
779 allocate would occasionally cause it to exceed the stack limit and
780 cause a core dump. */
781 real_known_ptr = xmalloc (num_labels);
783 = (int (*)[NUM_ELIMINABLE_REGS])
784 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
786 offsets_known_at = real_known_ptr - get_first_label_num ();
788 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
790 /* Alter each pseudo-reg rtx to contain its hard reg number.
791 Assign stack slots to the pseudos that lack hard regs or equivalents.
792 Do not touch virtual registers. */
794 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
797 /* If we have some registers we think can be eliminated, scan all insns to
798 see if there is an insn that sets one of these registers to something
799 other than itself plus a constant. If so, the register cannot be
800 eliminated. Doing this scan here eliminates an extra pass through the
801 main reload loop in the most common case where register elimination
803 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
804 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
805 || GET_CODE (insn) == CALL_INSN)
806 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
808 maybe_fix_stack_asms ();
810 insns_need_reload = 0;
811 something_needs_elimination = 0;
813 /* Initialize to -1, which means take the first spill register. */
816 /* Spill any hard regs that we know we can't eliminate. */
817 CLEAR_HARD_REG_SET (used_spill_regs);
818 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
819 if (! ep->can_eliminate)
820 spill_hard_reg (ep->from, 1);
822 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
823 if (frame_pointer_needed)
824 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
826 finish_spills (global);
828 /* From now on, we may need to generate moves differently. We may also
829 allow modifications of insns which cause them to not be recognized.
830 Any such modifications will be cleaned up during reload itself. */
831 reload_in_progress = 1;
833 /* This loop scans the entire function each go-round
834 and repeats until one repetition spills no additional hard regs. */
837 int something_changed;
840 HOST_WIDE_INT starting_frame_size;
842 /* Round size of stack frame to stack_alignment_needed. This must be done
843 here because the stack size may be a part of the offset computation
844 for register elimination, and there might have been new stack slots
845 created in the last iteration of this loop. */
846 if (cfun->stack_alignment_needed)
847 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
849 starting_frame_size = get_frame_size ();
851 set_initial_elim_offsets ();
852 set_initial_label_offsets ();
854 /* For each pseudo register that has an equivalent location defined,
855 try to eliminate any eliminable registers (such as the frame pointer)
856 assuming initial offsets for the replacement register, which
859 If the resulting location is directly addressable, substitute
860 the MEM we just got directly for the old REG.
862 If it is not addressable but is a constant or the sum of a hard reg
863 and constant, it is probably not addressable because the constant is
864 out of range, in that case record the address; we will generate
865 hairy code to compute the address in a register each time it is
866 needed. Similarly if it is a hard register, but one that is not
867 valid as an address register.
869 If the location is not addressable, but does not have one of the
870 above forms, assign a stack slot. We have to do this to avoid the
871 potential of producing lots of reloads if, e.g., a location involves
872 a pseudo that didn't get a hard register and has an equivalent memory
873 location that also involves a pseudo that didn't get a hard register.
875 Perhaps at some point we will improve reload_when_needed handling
876 so this problem goes away. But that's very hairy. */
878 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
879 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
881 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
883 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
885 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
886 else if (CONSTANT_P (XEXP (x, 0))
887 || (GET_CODE (XEXP (x, 0)) == REG
888 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
889 || (GET_CODE (XEXP (x, 0)) == PLUS
890 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
891 && (REGNO (XEXP (XEXP (x, 0), 0))
892 < FIRST_PSEUDO_REGISTER)
893 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
894 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
897 /* Make a new stack slot. Then indicate that something
898 changed so we go back and recompute offsets for
899 eliminable registers because the allocation of memory
900 below might change some offset. reg_equiv_{mem,address}
901 will be set up for this pseudo on the next pass around
903 reg_equiv_memory_loc[i] = 0;
904 reg_equiv_init[i] = 0;
909 if (caller_save_needed)
912 /* If we allocated another stack slot, redo elimination bookkeeping. */
913 if (starting_frame_size != get_frame_size ())
916 if (caller_save_needed)
918 save_call_clobbered_regs ();
919 /* That might have allocated new insn_chain structures. */
920 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
923 calculate_needs_all_insns (global);
925 CLEAR_REG_SET (&spilled_pseudos);
928 something_changed = 0;
930 /* If we allocated any new memory locations, make another pass
931 since it might have changed elimination offsets. */
932 if (starting_frame_size != get_frame_size ())
933 something_changed = 1;
936 HARD_REG_SET to_spill;
937 CLEAR_HARD_REG_SET (to_spill);
938 update_eliminables (&to_spill);
939 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
940 if (TEST_HARD_REG_BIT (to_spill, i))
942 spill_hard_reg (i, 1);
945 /* Regardless of the state of spills, if we previously had
946 a register that we thought we could eliminate, but no can
947 not eliminate, we must run another pass.
949 Consider pseudos which have an entry in reg_equiv_* which
950 reference an eliminable register. We must make another pass
951 to update reg_equiv_* so that we do not substitute in the
952 old value from when we thought the elimination could be
954 something_changed = 1;
958 select_reload_regs ();
962 if (insns_need_reload != 0 || did_spill)
963 something_changed |= finish_spills (global);
965 if (! something_changed)
968 if (caller_save_needed)
969 delete_caller_save_insns ();
971 obstack_free (&reload_obstack, reload_firstobj);
974 /* If global-alloc was run, notify it of any register eliminations we have
977 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
978 if (ep->can_eliminate)
979 mark_elimination (ep->from, ep->to);
981 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
982 If that insn didn't set the register (i.e., it copied the register to
983 memory), just delete that insn instead of the equivalencing insn plus
984 anything now dead. If we call delete_dead_insn on that insn, we may
985 delete the insn that actually sets the register if the register dies
986 there and that is incorrect. */
988 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
990 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
993 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
995 rtx equiv_insn = XEXP (list, 0);
996 if (GET_CODE (equiv_insn) == NOTE)
998 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
999 delete_dead_insn (equiv_insn);
1002 PUT_CODE (equiv_insn, NOTE);
1003 NOTE_SOURCE_FILE (equiv_insn) = 0;
1004 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1010 /* Use the reload registers where necessary
1011 by generating move instructions to move the must-be-register
1012 values into or out of the reload registers. */
1014 if (insns_need_reload != 0 || something_needs_elimination
1015 || something_needs_operands_changed)
1017 int old_frame_size = get_frame_size ();
1019 reload_as_needed (global);
1021 if (old_frame_size != get_frame_size ())
1025 verify_initial_elim_offsets ();
1028 /* If we were able to eliminate the frame pointer, show that it is no
1029 longer live at the start of any basic block. If it ls live by
1030 virtue of being in a pseudo, that pseudo will be marked live
1031 and hence the frame pointer will be known to be live via that
1034 if (! frame_pointer_needed)
1035 for (i = 0; i < n_basic_blocks; i++)
1036 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1037 HARD_FRAME_POINTER_REGNUM);
1039 /* Come here (with failure set nonzero) if we can't get enough spill regs
1040 and we decide not to abort about it. */
1043 CLEAR_REG_SET (&spilled_pseudos);
1044 reload_in_progress = 0;
1046 /* Now eliminate all pseudo regs by modifying them into
1047 their equivalent memory references.
1048 The REG-rtx's for the pseudos are modified in place,
1049 so all insns that used to refer to them now refer to memory.
1051 For a reg that has a reg_equiv_address, all those insns
1052 were changed by reloading so that no insns refer to it any longer;
1053 but the DECL_RTL of a variable decl may refer to it,
1054 and if so this causes the debugging info to mention the variable. */
1056 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1061 int is_readonly = 0;
1063 if (reg_equiv_memory_loc[i])
1065 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1066 is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]);
1067 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1070 if (reg_equiv_mem[i])
1071 addr = XEXP (reg_equiv_mem[i], 0);
1073 if (reg_equiv_address[i])
1074 addr = reg_equiv_address[i];
1078 if (reg_renumber[i] < 0)
1080 rtx reg = regno_reg_rtx[i];
1081 PUT_CODE (reg, MEM);
1082 XEXP (reg, 0) = addr;
1083 REG_USERVAR_P (reg) = 0;
1084 RTX_UNCHANGING_P (reg) = is_readonly;
1085 MEM_IN_STRUCT_P (reg) = in_struct;
1086 MEM_SCALAR_P (reg) = is_scalar;
1087 /* We have no alias information about this newly created
1089 MEM_ALIAS_SET (reg) = 0;
1091 else if (reg_equiv_mem[i])
1092 XEXP (reg_equiv_mem[i], 0) = addr;
1096 /* We must set reload_completed now since the cleanup_subreg_operands call
1097 below will re-recognize each insn and reload may have generated insns
1098 which are only valid during and after reload. */
1099 reload_completed = 1;
1101 /* Make a pass over all the insns and delete all USEs which we inserted
1102 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1103 notes. Delete all CLOBBER insns that don't refer to the return value
1104 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1105 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1106 and regenerate REG_INC notes that may have been moved around. */
1108 for (insn = first; insn; insn = NEXT_INSN (insn))
1113 if ((GET_CODE (PATTERN (insn)) == USE
1114 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1115 || (GET_CODE (PATTERN (insn)) == CLOBBER
1116 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1117 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1119 PUT_CODE (insn, NOTE);
1120 NOTE_SOURCE_FILE (insn) = 0;
1121 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1125 pnote = ®_NOTES (insn);
1128 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1129 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1130 || REG_NOTE_KIND (*pnote) == REG_INC
1131 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1132 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1133 *pnote = XEXP (*pnote, 1);
1135 pnote = &XEXP (*pnote, 1);
1139 add_auto_inc_notes (insn, PATTERN (insn));
1142 /* And simplify (subreg (reg)) if it appears as an operand. */
1143 cleanup_subreg_operands (insn);
1146 /* If we are doing stack checking, give a warning if this function's
1147 frame size is larger than we expect. */
1148 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1150 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1151 static int verbose_warned = 0;
1153 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1154 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1155 size += UNITS_PER_WORD;
1157 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1159 warning ("frame size too large for reliable stack checking");
1160 if (! verbose_warned)
1162 warning ("try reducing the number of local variables");
1168 /* Indicate that we no longer have known memory locations or constants. */
1169 if (reg_equiv_constant)
1170 free (reg_equiv_constant);
1171 reg_equiv_constant = 0;
1172 if (reg_equiv_memory_loc)
1173 free (reg_equiv_memory_loc);
1174 reg_equiv_memory_loc = 0;
1177 free (real_known_ptr);
1181 free (reg_equiv_mem);
1182 free (reg_equiv_init);
1183 free (reg_equiv_address);
1184 free (reg_max_ref_width);
1185 free (reg_old_renumber);
1186 free (pseudo_previous_regs);
1187 free (pseudo_forbidden_regs);
1189 CLEAR_HARD_REG_SET (used_spill_regs);
1190 for (i = 0; i < n_spills; i++)
1191 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1193 /* Free all the insn_chain structures at once. */
1194 obstack_free (&reload_obstack, reload_startobj);
1195 unused_insn_chains = 0;
1200 /* Yet another special case. Unfortunately, reg-stack forces people to
1201 write incorrect clobbers in asm statements. These clobbers must not
1202 cause the register to appear in bad_spill_regs, otherwise we'll call
1203 fatal_insn later. We clear the corresponding regnos in the live
1204 register sets to avoid this.
1205 The whole thing is rather sick, I'm afraid. */
1208 maybe_fix_stack_asms ()
1211 const char *constraints[MAX_RECOG_OPERANDS];
1212 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1213 struct insn_chain *chain;
1215 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1218 HARD_REG_SET clobbered, allowed;
1221 if (! INSN_P (chain->insn)
1222 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1224 pat = PATTERN (chain->insn);
1225 if (GET_CODE (pat) != PARALLEL)
1228 CLEAR_HARD_REG_SET (clobbered);
1229 CLEAR_HARD_REG_SET (allowed);
1231 /* First, make a mask of all stack regs that are clobbered. */
1232 for (i = 0; i < XVECLEN (pat, 0); i++)
1234 rtx t = XVECEXP (pat, 0, i);
1235 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1236 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1239 /* Get the operand values and constraints out of the insn. */
1240 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1241 constraints, operand_mode);
1243 /* For every operand, see what registers are allowed. */
1244 for (i = 0; i < noperands; i++)
1246 const char *p = constraints[i];
1247 /* For every alternative, we compute the class of registers allowed
1248 for reloading in CLS, and merge its contents into the reg set
1250 int cls = (int) NO_REGS;
1256 if (c == '\0' || c == ',' || c == '#')
1258 /* End of one alternative - mark the regs in the current
1259 class, and reset the class. */
1260 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1265 } while (c != '\0' && c != ',');
1273 case '=': case '+': case '*': case '%': case '?': case '!':
1274 case '0': case '1': case '2': case '3': case '4': case 'm':
1275 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1276 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1277 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1279 #ifdef EXTRA_CONSTRAINT
1280 case 'Q': case 'R': case 'S': case 'T': case 'U':
1285 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1290 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1294 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1299 /* Those of the registers which are clobbered, but allowed by the
1300 constraints, must be usable as reload registers. So clear them
1301 out of the life information. */
1302 AND_HARD_REG_SET (allowed, clobbered);
1303 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1304 if (TEST_HARD_REG_BIT (allowed, i))
1306 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1307 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1314 /* Copy the global variables n_reloads and rld into the corresponding elts
1317 copy_reloads (chain)
1318 struct insn_chain *chain;
1320 chain->n_reloads = n_reloads;
1322 = (struct reload *) obstack_alloc (&reload_obstack,
1323 n_reloads * sizeof (struct reload));
1324 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1325 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1328 /* Walk the chain of insns, and determine for each whether it needs reloads
1329 and/or eliminations. Build the corresponding insns_need_reload list, and
1330 set something_needs_elimination as appropriate. */
1332 calculate_needs_all_insns (global)
1335 struct insn_chain **pprev_reload = &insns_need_reload;
1336 struct insn_chain *chain;
1338 something_needs_elimination = 0;
1340 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1341 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1343 rtx insn = chain->insn;
1345 /* Clear out the shortcuts. */
1346 chain->n_reloads = 0;
1347 chain->need_elim = 0;
1348 chain->need_reload = 0;
1349 chain->need_operand_change = 0;
1351 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1352 include REG_LABEL), we need to see what effects this has on the
1353 known offsets at labels. */
1355 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1356 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1357 set_label_offsets (insn, insn, 0);
1361 rtx old_body = PATTERN (insn);
1362 int old_code = INSN_CODE (insn);
1363 rtx old_notes = REG_NOTES (insn);
1364 int did_elimination = 0;
1365 int operands_changed = 0;
1366 rtx set = single_set (insn);
1368 /* Skip insns that only set an equivalence. */
1369 if (set && GET_CODE (SET_DEST (set)) == REG
1370 && reg_renumber[REGNO (SET_DEST (set))] < 0
1371 && reg_equiv_constant[REGNO (SET_DEST (set))])
1374 /* If needed, eliminate any eliminable registers. */
1375 if (num_eliminable || num_eliminable_invariants)
1376 did_elimination = eliminate_regs_in_insn (insn, 0);
1378 /* Analyze the instruction. */
1379 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1380 global, spill_reg_order);
1382 /* If a no-op set needs more than one reload, this is likely
1383 to be something that needs input address reloads. We
1384 can't get rid of this cleanly later, and it is of no use
1385 anyway, so discard it now.
1386 We only do this when expensive_optimizations is enabled,
1387 since this complements reload inheritance / output
1388 reload deletion, and it can make debugging harder. */
1389 if (flag_expensive_optimizations && n_reloads > 1)
1391 rtx set = single_set (insn);
1393 && SET_SRC (set) == SET_DEST (set)
1394 && GET_CODE (SET_SRC (set)) == REG
1395 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1397 PUT_CODE (insn, NOTE);
1398 NOTE_SOURCE_FILE (insn) = 0;
1399 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1404 update_eliminable_offsets ();
1406 /* Remember for later shortcuts which insns had any reloads or
1407 register eliminations. */
1408 chain->need_elim = did_elimination;
1409 chain->need_reload = n_reloads > 0;
1410 chain->need_operand_change = operands_changed;
1412 /* Discard any register replacements done. */
1413 if (did_elimination)
1415 obstack_free (&reload_obstack, reload_insn_firstobj);
1416 PATTERN (insn) = old_body;
1417 INSN_CODE (insn) = old_code;
1418 REG_NOTES (insn) = old_notes;
1419 something_needs_elimination = 1;
1422 something_needs_operands_changed |= operands_changed;
1426 copy_reloads (chain);
1427 *pprev_reload = chain;
1428 pprev_reload = &chain->next_need_reload;
1435 /* Comparison function for qsort to decide which of two reloads
1436 should be handled first. *P1 and *P2 are the reload numbers. */
1439 reload_reg_class_lower (r1p, r2p)
1443 register int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1446 /* Consider required reloads before optional ones. */
1447 t = rld[r1].optional - rld[r2].optional;
1451 /* Count all solitary classes before non-solitary ones. */
1452 t = ((reg_class_size[(int) rld[r2].class] == 1)
1453 - (reg_class_size[(int) rld[r1].class] == 1));
1457 /* Aside from solitaires, consider all multi-reg groups first. */
1458 t = rld[r2].nregs - rld[r1].nregs;
1462 /* Consider reloads in order of increasing reg-class number. */
1463 t = (int) rld[r1].class - (int) rld[r2].class;
1467 /* If reloads are equally urgent, sort by reload number,
1468 so that the results of qsort leave nothing to chance. */
1472 /* The cost of spilling each hard reg. */
1473 static int spill_cost[FIRST_PSEUDO_REGISTER];
1475 /* When spilling multiple hard registers, we use SPILL_COST for the first
1476 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1477 only the first hard reg for a multi-reg pseudo. */
1478 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1480 /* Update the spill cost arrays, considering that pseudo REG is live. */
1486 int n_refs = REG_N_REFS (reg);
1487 int r = reg_renumber[reg];
1490 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1491 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1494 SET_REGNO_REG_SET (&pseudos_counted, reg);
1499 spill_add_cost[r] += n_refs;
1501 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1503 spill_cost[r + nregs] += n_refs;
1506 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1507 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1510 order_regs_for_reload (chain)
1511 struct insn_chain *chain;
1514 HARD_REG_SET used_by_pseudos;
1515 HARD_REG_SET used_by_pseudos2;
1517 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1519 memset (spill_cost, 0, sizeof spill_cost);
1520 memset (spill_add_cost, 0, sizeof spill_add_cost);
1522 /* Count number of uses of each hard reg by pseudo regs allocated to it
1523 and then order them by decreasing use. First exclude hard registers
1524 that are live in or across this insn. */
1526 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1527 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1528 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1529 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1531 /* Now find out which pseudos are allocated to it, and update
1533 CLEAR_REG_SET (&pseudos_counted);
1535 EXECUTE_IF_SET_IN_REG_SET
1536 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1540 EXECUTE_IF_SET_IN_REG_SET
1541 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1545 CLEAR_REG_SET (&pseudos_counted);
1548 /* Vector of reload-numbers showing the order in which the reloads should
1550 static short reload_order[MAX_RELOADS];
1552 /* This is used to keep track of the spill regs used in one insn. */
1553 static HARD_REG_SET used_spill_regs_local;
1555 /* We decided to spill hard register SPILLED, which has a size of
1556 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1557 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1558 update SPILL_COST/SPILL_ADD_COST. */
1561 count_spilled_pseudo (spilled, spilled_nregs, reg)
1562 int spilled, spilled_nregs, reg;
1564 int r = reg_renumber[reg];
1565 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1567 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1568 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1571 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1573 spill_add_cost[r] -= REG_N_REFS (reg);
1575 spill_cost[r + nregs] -= REG_N_REFS (reg);
1578 /* Find reload register to use for reload number ORDER. */
1581 find_reg (chain, order)
1582 struct insn_chain *chain;
1585 int rnum = reload_order[order];
1586 struct reload *rl = rld + rnum;
1587 int best_cost = INT_MAX;
1591 HARD_REG_SET not_usable;
1592 HARD_REG_SET used_by_other_reload;
1594 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1595 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1596 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1598 CLEAR_HARD_REG_SET (used_by_other_reload);
1599 for (k = 0; k < order; k++)
1601 int other = reload_order[k];
1603 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1604 for (j = 0; j < rld[other].nregs; j++)
1605 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1608 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1610 unsigned int regno = i;
1612 if (! TEST_HARD_REG_BIT (not_usable, regno)
1613 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1614 && HARD_REGNO_MODE_OK (regno, rl->mode))
1616 int this_cost = spill_cost[regno];
1618 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1620 for (j = 1; j < this_nregs; j++)
1622 this_cost += spill_add_cost[regno + j];
1623 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1624 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1629 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1631 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1633 if (this_cost < best_cost
1634 /* Among registers with equal cost, prefer caller-saved ones, or
1635 use REG_ALLOC_ORDER if it is defined. */
1636 || (this_cost == best_cost
1637 #ifdef REG_ALLOC_ORDER
1638 && (inv_reg_alloc_order[regno]
1639 < inv_reg_alloc_order[best_reg])
1641 && call_used_regs[regno]
1642 && ! call_used_regs[best_reg]
1647 best_cost = this_cost;
1655 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1657 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1658 rl->regno = best_reg;
1660 EXECUTE_IF_SET_IN_REG_SET
1661 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1663 count_spilled_pseudo (best_reg, rl->nregs, j);
1666 EXECUTE_IF_SET_IN_REG_SET
1667 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1669 count_spilled_pseudo (best_reg, rl->nregs, j);
1672 for (i = 0; i < rl->nregs; i++)
1674 if (spill_cost[best_reg + i] != 0
1675 || spill_add_cost[best_reg + i] != 0)
1677 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1682 /* Find more reload regs to satisfy the remaining need of an insn, which
1684 Do it by ascending class number, since otherwise a reg
1685 might be spilled for a big class and might fail to count
1686 for a smaller class even though it belongs to that class. */
1689 find_reload_regs (chain)
1690 struct insn_chain *chain;
1694 /* In order to be certain of getting the registers we need,
1695 we must sort the reloads into order of increasing register class.
1696 Then our grabbing of reload registers will parallel the process
1697 that provided the reload registers. */
1698 for (i = 0; i < chain->n_reloads; i++)
1700 /* Show whether this reload already has a hard reg. */
1701 if (chain->rld[i].reg_rtx)
1703 int regno = REGNO (chain->rld[i].reg_rtx);
1704 chain->rld[i].regno = regno;
1706 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1709 chain->rld[i].regno = -1;
1710 reload_order[i] = i;
1713 n_reloads = chain->n_reloads;
1714 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1716 CLEAR_HARD_REG_SET (used_spill_regs_local);
1719 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1721 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1723 /* Compute the order of preference for hard registers to spill. */
1725 order_regs_for_reload (chain);
1727 for (i = 0; i < n_reloads; i++)
1729 int r = reload_order[i];
1731 /* Ignore reloads that got marked inoperative. */
1732 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1733 && ! rld[r].optional
1734 && rld[r].regno == -1)
1735 if (! find_reg (chain, i))
1737 spill_failure (chain->insn, rld[r].class);
1743 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1744 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1746 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1750 select_reload_regs ()
1752 struct insn_chain *chain;
1754 /* Try to satisfy the needs for each insn. */
1755 for (chain = insns_need_reload; chain != 0;
1756 chain = chain->next_need_reload)
1757 find_reload_regs (chain);
1760 /* Delete all insns that were inserted by emit_caller_save_insns during
1763 delete_caller_save_insns ()
1765 struct insn_chain *c = reload_insn_chain;
1769 while (c != 0 && c->is_caller_save_insn)
1771 struct insn_chain *next = c->next;
1774 if (insn == BLOCK_HEAD (c->block))
1775 BLOCK_HEAD (c->block) = NEXT_INSN (insn);
1776 if (insn == BLOCK_END (c->block))
1777 BLOCK_END (c->block) = PREV_INSN (insn);
1778 if (c == reload_insn_chain)
1779 reload_insn_chain = next;
1781 if (NEXT_INSN (insn) != 0)
1782 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
1783 if (PREV_INSN (insn) != 0)
1784 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
1787 next->prev = c->prev;
1789 c->prev->next = next;
1790 c->next = unused_insn_chains;
1791 unused_insn_chains = c;
1799 /* Handle the failure to find a register to spill.
1800 INSN should be one of the insns which needed this particular spill reg. */
1803 spill_failure (insn, class)
1805 enum reg_class class;
1807 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1808 if (asm_noperands (PATTERN (insn)) >= 0)
1809 error_for_asm (insn, "Can't find a register in class `%s' while reloading `asm'.",
1810 reg_class_names[class]);
1813 error ("Unable to find a register to spill in class `%s'.",
1814 reg_class_names[class]);
1815 fatal_insn ("This is the insn:", insn);
1819 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1820 data that is dead in INSN. */
1823 delete_dead_insn (insn)
1826 rtx prev = prev_real_insn (insn);
1829 /* If the previous insn sets a register that dies in our insn, delete it
1831 if (prev && GET_CODE (PATTERN (prev)) == SET
1832 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1833 && reg_mentioned_p (prev_dest, PATTERN (insn))
1834 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1835 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1836 delete_dead_insn (prev);
1838 PUT_CODE (insn, NOTE);
1839 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1840 NOTE_SOURCE_FILE (insn) = 0;
1843 /* Modify the home of pseudo-reg I.
1844 The new home is present in reg_renumber[I].
1846 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1847 or it may be -1, meaning there is none or it is not relevant.
1848 This is used so that all pseudos spilled from a given hard reg
1849 can share one stack slot. */
1852 alter_reg (i, from_reg)
1856 /* When outputting an inline function, this can happen
1857 for a reg that isn't actually used. */
1858 if (regno_reg_rtx[i] == 0)
1861 /* If the reg got changed to a MEM at rtl-generation time,
1863 if (GET_CODE (regno_reg_rtx[i]) != REG)
1866 /* Modify the reg-rtx to contain the new hard reg
1867 number or else to contain its pseudo reg number. */
1868 REGNO (regno_reg_rtx[i])
1869 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1871 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1872 allocate a stack slot for it. */
1874 if (reg_renumber[i] < 0
1875 && REG_N_REFS (i) > 0
1876 && reg_equiv_constant[i] == 0
1877 && reg_equiv_memory_loc[i] == 0)
1880 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1881 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1884 /* Each pseudo reg has an inherent size which comes from its own mode,
1885 and a total size which provides room for paradoxical subregs
1886 which refer to the pseudo reg in wider modes.
1888 We can use a slot already allocated if it provides both
1889 enough inherent space and enough total space.
1890 Otherwise, we allocate a new slot, making sure that it has no less
1891 inherent space, and no less total space, then the previous slot. */
1894 /* No known place to spill from => no slot to reuse. */
1895 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1896 inherent_size == total_size ? 0 : -1);
1897 if (BYTES_BIG_ENDIAN)
1898 /* Cancel the big-endian correction done in assign_stack_local.
1899 Get the address of the beginning of the slot.
1900 This is so we can do a big-endian correction unconditionally
1902 adjust = inherent_size - total_size;
1904 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1906 /* Nothing can alias this slot except this pseudo. */
1907 MEM_ALIAS_SET (x) = new_alias_set ();
1910 /* Reuse a stack slot if possible. */
1911 else if (spill_stack_slot[from_reg] != 0
1912 && spill_stack_slot_width[from_reg] >= total_size
1913 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1915 x = spill_stack_slot[from_reg];
1917 /* Allocate a bigger slot. */
1920 /* Compute maximum size needed, both for inherent size
1921 and for total size. */
1922 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1925 if (spill_stack_slot[from_reg])
1927 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1929 mode = GET_MODE (spill_stack_slot[from_reg]);
1930 if (spill_stack_slot_width[from_reg] > total_size)
1931 total_size = spill_stack_slot_width[from_reg];
1934 /* Make a slot with that size. */
1935 x = assign_stack_local (mode, total_size,
1936 inherent_size == total_size ? 0 : -1);
1939 /* All pseudos mapped to this slot can alias each other. */
1940 if (spill_stack_slot[from_reg])
1941 MEM_ALIAS_SET (x) = MEM_ALIAS_SET (spill_stack_slot[from_reg]);
1943 MEM_ALIAS_SET (x) = new_alias_set ();
1945 if (BYTES_BIG_ENDIAN)
1947 /* Cancel the big-endian correction done in assign_stack_local.
1948 Get the address of the beginning of the slot.
1949 This is so we can do a big-endian correction unconditionally
1951 adjust = GET_MODE_SIZE (mode) - total_size;
1953 stack_slot = gen_rtx_MEM (mode_for_size (total_size
1956 plus_constant (XEXP (x, 0), adjust));
1959 spill_stack_slot[from_reg] = stack_slot;
1960 spill_stack_slot_width[from_reg] = total_size;
1963 /* On a big endian machine, the "address" of the slot
1964 is the address of the low part that fits its inherent mode. */
1965 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
1966 adjust += (total_size - inherent_size);
1968 /* If we have any adjustment to make, or if the stack slot is the
1969 wrong mode, make a new stack slot. */
1970 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
1972 rtx new = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
1973 plus_constant (XEXP (x, 0), adjust));
1975 MEM_COPY_ATTRIBUTES (new, x);
1979 /* Save the stack slot for later. */
1980 reg_equiv_memory_loc[i] = x;
1984 /* Mark the slots in regs_ever_live for the hard regs
1985 used by pseudo-reg number REGNO. */
1988 mark_home_live (regno)
1991 register int i, lim;
1993 i = reg_renumber[regno];
1996 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
1998 regs_ever_live[i++] = 1;
2001 /* This function handles the tracking of elimination offsets around branches.
2003 X is a piece of RTL being scanned.
2005 INSN is the insn that it came from, if any.
2007 INITIAL_P is non-zero if we are to set the offset to be the initial
2008 offset and zero if we are setting the offset of the label to be the
2012 set_label_offsets (x, insn, initial_p)
2017 enum rtx_code code = GET_CODE (x);
2020 struct elim_table *p;
2025 if (LABEL_REF_NONLOCAL_P (x))
2030 /* ... fall through ... */
2033 /* If we know nothing about this label, set the desired offsets. Note
2034 that this sets the offset at a label to be the offset before a label
2035 if we don't know anything about the label. This is not correct for
2036 the label after a BARRIER, but is the best guess we can make. If
2037 we guessed wrong, we will suppress an elimination that might have
2038 been possible had we been able to guess correctly. */
2040 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2042 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2043 offsets_at[CODE_LABEL_NUMBER (x)][i]
2044 = (initial_p ? reg_eliminate[i].initial_offset
2045 : reg_eliminate[i].offset);
2046 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2049 /* Otherwise, if this is the definition of a label and it is
2050 preceded by a BARRIER, set our offsets to the known offset of
2054 && (tem = prev_nonnote_insn (insn)) != 0
2055 && GET_CODE (tem) == BARRIER)
2056 set_offsets_for_label (insn);
2058 /* If neither of the above cases is true, compare each offset
2059 with those previously recorded and suppress any eliminations
2060 where the offsets disagree. */
2062 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2063 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2064 != (initial_p ? reg_eliminate[i].initial_offset
2065 : reg_eliminate[i].offset))
2066 reg_eliminate[i].can_eliminate = 0;
2071 set_label_offsets (PATTERN (insn), insn, initial_p);
2073 /* ... fall through ... */
2077 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2078 and hence must have all eliminations at their initial offsets. */
2079 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2080 if (REG_NOTE_KIND (tem) == REG_LABEL)
2081 set_label_offsets (XEXP (tem, 0), insn, 1);
2086 /* Each of the labels in the address vector must be at their initial
2087 offsets. We want the first field for ADDR_VEC and the second
2088 field for ADDR_DIFF_VEC. */
2090 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2091 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2096 /* We only care about setting PC. If the source is not RETURN,
2097 IF_THEN_ELSE, or a label, disable any eliminations not at
2098 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2099 isn't one of those possibilities. For branches to a label,
2100 call ourselves recursively.
2102 Note that this can disable elimination unnecessarily when we have
2103 a non-local goto since it will look like a non-constant jump to
2104 someplace in the current function. This isn't a significant
2105 problem since such jumps will normally be when all elimination
2106 pairs are back to their initial offsets. */
2108 if (SET_DEST (x) != pc_rtx)
2111 switch (GET_CODE (SET_SRC (x)))
2118 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2122 tem = XEXP (SET_SRC (x), 1);
2123 if (GET_CODE (tem) == LABEL_REF)
2124 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2125 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2128 tem = XEXP (SET_SRC (x), 2);
2129 if (GET_CODE (tem) == LABEL_REF)
2130 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2131 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2139 /* If we reach here, all eliminations must be at their initial
2140 offset because we are doing a jump to a variable address. */
2141 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2142 if (p->offset != p->initial_offset)
2143 p->can_eliminate = 0;
2151 /* Scan X and replace any eliminable registers (such as fp) with a
2152 replacement (such as sp), plus an offset.
2154 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2155 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2156 MEM, we are allowed to replace a sum of a register and the constant zero
2157 with the register, which we cannot do outside a MEM. In addition, we need
2158 to record the fact that a register is referenced outside a MEM.
2160 If INSN is an insn, it is the insn containing X. If we replace a REG
2161 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2162 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2163 the REG is being modified.
2165 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2166 That's used when we eliminate in expressions stored in notes.
2167 This means, do not set ref_outside_mem even if the reference
2170 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2171 replacements done assuming all offsets are at their initial values. If
2172 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2173 encounter, return the actual location so that find_reloads will do
2174 the proper thing. */
2177 eliminate_regs (x, mem_mode, insn)
2179 enum machine_mode mem_mode;
2182 enum rtx_code code = GET_CODE (x);
2183 struct elim_table *ep;
2190 if (! current_function_decl)
2209 /* This is only for the benefit of the debugging backends, which call
2210 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2211 removed after CSE. */
2212 new = eliminate_regs (XEXP (x, 0), 0, insn);
2213 if (GET_CODE (new) == MEM)
2214 return XEXP (new, 0);
2220 /* First handle the case where we encounter a bare register that
2221 is eliminable. Replace it with a PLUS. */
2222 if (regno < FIRST_PSEUDO_REGISTER)
2224 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2226 if (ep->from_rtx == x && ep->can_eliminate)
2227 return plus_constant (ep->to_rtx, ep->previous_offset);
2230 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2231 && reg_equiv_constant[regno]
2232 && ! CONSTANT_P (reg_equiv_constant[regno]))
2233 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2237 /* You might think handling MINUS in a manner similar to PLUS is a
2238 good idea. It is not. It has been tried multiple times and every
2239 time the change has had to have been reverted.
2241 Other parts of reload know a PLUS is special (gen_reload for example)
2242 and require special code to handle code a reloaded PLUS operand.
2244 Also consider backends where the flags register is clobbered by a
2245 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2246 lea instruction comes to mind). If we try to reload a MINUS, we
2247 may kill the flags register that was holding a useful value.
2249 So, please before trying to handle MINUS, consider reload as a
2250 whole instead of this little section as well as the backend issues. */
2252 /* If this is the sum of an eliminable register and a constant, rework
2254 if (GET_CODE (XEXP (x, 0)) == REG
2255 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2256 && CONSTANT_P (XEXP (x, 1)))
2258 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2260 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2262 /* The only time we want to replace a PLUS with a REG (this
2263 occurs when the constant operand of the PLUS is the negative
2264 of the offset) is when we are inside a MEM. We won't want
2265 to do so at other times because that would change the
2266 structure of the insn in a way that reload can't handle.
2267 We special-case the commonest situation in
2268 eliminate_regs_in_insn, so just replace a PLUS with a
2269 PLUS here, unless inside a MEM. */
2270 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2271 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2274 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2275 plus_constant (XEXP (x, 1),
2276 ep->previous_offset));
2279 /* If the register is not eliminable, we are done since the other
2280 operand is a constant. */
2284 /* If this is part of an address, we want to bring any constant to the
2285 outermost PLUS. We will do this by doing register replacement in
2286 our operands and seeing if a constant shows up in one of them.
2288 Note that there is no risk of modifying the structure of the insn,
2289 since we only get called for its operands, thus we are either
2290 modifying the address inside a MEM, or something like an address
2291 operand of a load-address insn. */
2294 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2295 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2297 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2299 /* If one side is a PLUS and the other side is a pseudo that
2300 didn't get a hard register but has a reg_equiv_constant,
2301 we must replace the constant here since it may no longer
2302 be in the position of any operand. */
2303 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2304 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2305 && reg_renumber[REGNO (new1)] < 0
2306 && reg_equiv_constant != 0
2307 && reg_equiv_constant[REGNO (new1)] != 0)
2308 new1 = reg_equiv_constant[REGNO (new1)];
2309 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2310 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2311 && reg_renumber[REGNO (new0)] < 0
2312 && reg_equiv_constant[REGNO (new0)] != 0)
2313 new0 = reg_equiv_constant[REGNO (new0)];
2315 new = form_sum (new0, new1);
2317 /* As above, if we are not inside a MEM we do not want to
2318 turn a PLUS into something else. We might try to do so here
2319 for an addition of 0 if we aren't optimizing. */
2320 if (! mem_mode && GET_CODE (new) != PLUS)
2321 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2329 /* If this is the product of an eliminable register and a
2330 constant, apply the distribute law and move the constant out
2331 so that we have (plus (mult ..) ..). This is needed in order
2332 to keep load-address insns valid. This case is pathological.
2333 We ignore the possibility of overflow here. */
2334 if (GET_CODE (XEXP (x, 0)) == REG
2335 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2336 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2337 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2339 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2342 /* Refs inside notes don't count for this purpose. */
2343 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2344 || GET_CODE (insn) == INSN_LIST)))
2345 ep->ref_outside_mem = 1;
2348 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2349 ep->previous_offset * INTVAL (XEXP (x, 1)));
2352 /* ... fall through ... */
2356 /* See comments before PLUS about handling MINUS. */
2358 case DIV: case UDIV:
2359 case MOD: case UMOD:
2360 case AND: case IOR: case XOR:
2361 case ROTATERT: case ROTATE:
2362 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2364 case GE: case GT: case GEU: case GTU:
2365 case LE: case LT: case LEU: case LTU:
2367 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2369 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2371 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2372 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2377 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2380 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2381 if (new != XEXP (x, 0))
2383 /* If this is a REG_DEAD note, it is not valid anymore.
2384 Using the eliminated version could result in creating a
2385 REG_DEAD note for the stack or frame pointer. */
2386 if (GET_MODE (x) == REG_DEAD)
2388 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2391 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2395 /* ... fall through ... */
2398 /* Now do eliminations in the rest of the chain. If this was
2399 an EXPR_LIST, this might result in allocating more memory than is
2400 strictly needed, but it simplifies the code. */
2403 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2404 if (new != XEXP (x, 1))
2405 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2413 case STRICT_LOW_PART:
2415 case SIGN_EXTEND: case ZERO_EXTEND:
2416 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2417 case FLOAT: case FIX:
2418 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2422 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2423 if (new != XEXP (x, 0))
2424 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2428 /* Similar to above processing, but preserve SUBREG_WORD.
2429 Convert (subreg (mem)) to (mem) if not paradoxical.
2430 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2431 pseudo didn't get a hard reg, we must replace this with the
2432 eliminated version of the memory location because push_reloads
2433 may do the replacement in certain circumstances. */
2434 if (GET_CODE (SUBREG_REG (x)) == REG
2435 && (GET_MODE_SIZE (GET_MODE (x))
2436 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2437 && reg_equiv_memory_loc != 0
2438 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2440 new = SUBREG_REG (x);
2443 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2445 if (new != XEXP (x, 0))
2447 int x_size = GET_MODE_SIZE (GET_MODE (x));
2448 int new_size = GET_MODE_SIZE (GET_MODE (new));
2450 if (GET_CODE (new) == MEM
2451 && ((x_size < new_size
2452 #ifdef WORD_REGISTER_OPERATIONS
2453 /* On these machines, combine can create rtl of the form
2454 (set (subreg:m1 (reg:m2 R) 0) ...)
2455 where m1 < m2, and expects something interesting to
2456 happen to the entire word. Moreover, it will use the
2457 (reg:m2 R) later, expecting all bits to be preserved.
2458 So if the number of words is the same, preserve the
2459 subreg so that push_reloads can see it. */
2460 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
2463 || (x_size == new_size))
2466 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2467 enum machine_mode mode = GET_MODE (x);
2469 if (BYTES_BIG_ENDIAN)
2470 offset += (MIN (UNITS_PER_WORD,
2471 GET_MODE_SIZE (GET_MODE (new)))
2472 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2474 PUT_MODE (new, mode);
2475 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2479 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
2485 /* This is only for the benefit of the debugging backends, which call
2486 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2487 removed after CSE. */
2488 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2489 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2491 /* Our only special processing is to pass the mode of the MEM to our
2492 recursive call and copy the flags. While we are here, handle this
2493 case more efficiently. */
2494 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
2495 if (new != XEXP (x, 0))
2497 new = gen_rtx_MEM (GET_MODE (x), new);
2498 MEM_COPY_ATTRIBUTES (new, x);
2514 /* Process each of our operands recursively. If any have changed, make a
2516 fmt = GET_RTX_FORMAT (code);
2517 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2521 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2522 if (new != XEXP (x, i) && ! copied)
2524 rtx new_x = rtx_alloc (code);
2525 bcopy ((char *) x, (char *) new_x,
2526 (sizeof (*new_x) - sizeof (new_x->fld)
2527 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2533 else if (*fmt == 'E')
2536 for (j = 0; j < XVECLEN (x, i); j++)
2538 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2539 if (new != XVECEXP (x, i, j) && ! copied_vec)
2541 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2545 rtx new_x = rtx_alloc (code);
2546 bcopy ((char *) x, (char *) new_x,
2547 (sizeof (*new_x) - sizeof (new_x->fld)
2548 + (sizeof (new_x->fld[0])
2549 * GET_RTX_LENGTH (code))));
2553 XVEC (x, i) = new_v;
2556 XVECEXP (x, i, j) = new;
2564 /* Scan rtx X for modifications of elimination target registers. Update
2565 the table of eliminables to reflect the changed state. MEM_MODE is
2566 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2569 elimination_effects (x, mem_mode)
2571 enum machine_mode mem_mode;
2574 enum rtx_code code = GET_CODE (x);
2575 struct elim_table *ep;
2601 /* First handle the case where we encounter a bare register that
2602 is eliminable. Replace it with a PLUS. */
2603 if (regno < FIRST_PSEUDO_REGISTER)
2605 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2607 if (ep->from_rtx == x && ep->can_eliminate)
2610 ep->ref_outside_mem = 1;
2615 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2616 && reg_equiv_constant[regno]
2617 && ! CONSTANT_P (reg_equiv_constant[regno]))
2618 elimination_effects (reg_equiv_constant[regno], mem_mode);
2627 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2628 if (ep->to_rtx == XEXP (x, 0))
2630 int size = GET_MODE_SIZE (mem_mode);
2632 /* If more bytes than MEM_MODE are pushed, account for them. */
2633 #ifdef PUSH_ROUNDING
2634 if (ep->to_rtx == stack_pointer_rtx)
2635 size = PUSH_ROUNDING (size);
2637 if (code == PRE_DEC || code == POST_DEC)
2639 else if (code == PRE_INC || code == POST_INC)
2641 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2642 && GET_CODE (XEXP (x, 1)) == PLUS
2643 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2644 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2645 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2648 /* These two aren't unary operators. */
2649 if (code == POST_MODIFY || code == PRE_MODIFY)
2652 /* Fall through to generic unary operation case. */
2653 case STRICT_LOW_PART:
2655 case SIGN_EXTEND: case ZERO_EXTEND:
2656 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2657 case FLOAT: case FIX:
2658 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2662 elimination_effects (XEXP (x, 0), mem_mode);
2666 if (GET_CODE (SUBREG_REG (x)) == REG
2667 && (GET_MODE_SIZE (GET_MODE (x))
2668 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2669 && reg_equiv_memory_loc != 0
2670 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2673 elimination_effects (SUBREG_REG (x), mem_mode);
2677 /* If using a register that is the source of an eliminate we still
2678 think can be performed, note it cannot be performed since we don't
2679 know how this register is used. */
2680 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2681 if (ep->from_rtx == XEXP (x, 0))
2682 ep->can_eliminate = 0;
2684 elimination_effects (XEXP (x, 0), mem_mode);
2688 /* If clobbering a register that is the replacement register for an
2689 elimination we still think can be performed, note that it cannot
2690 be performed. Otherwise, we need not be concerned about it. */
2691 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2692 if (ep->to_rtx == XEXP (x, 0))
2693 ep->can_eliminate = 0;
2695 elimination_effects (XEXP (x, 0), mem_mode);
2699 /* Check for setting a register that we know about. */
2700 if (GET_CODE (SET_DEST (x)) == REG)
2702 /* See if this is setting the replacement register for an
2705 If DEST is the hard frame pointer, we do nothing because we
2706 assume that all assignments to the frame pointer are for
2707 non-local gotos and are being done at a time when they are valid
2708 and do not disturb anything else. Some machines want to
2709 eliminate a fake argument pointer (or even a fake frame pointer)
2710 with either the real frame or the stack pointer. Assignments to
2711 the hard frame pointer must not prevent this elimination. */
2713 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2715 if (ep->to_rtx == SET_DEST (x)
2716 && SET_DEST (x) != hard_frame_pointer_rtx)
2718 /* If it is being incremented, adjust the offset. Otherwise,
2719 this elimination can't be done. */
2720 rtx src = SET_SRC (x);
2722 if (GET_CODE (src) == PLUS
2723 && XEXP (src, 0) == SET_DEST (x)
2724 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2725 ep->offset -= INTVAL (XEXP (src, 1));
2727 ep->can_eliminate = 0;
2731 elimination_effects (SET_DEST (x), 0);
2732 elimination_effects (SET_SRC (x), 0);
2736 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2739 /* Our only special processing is to pass the mode of the MEM to our
2741 elimination_effects (XEXP (x, 0), GET_MODE (x));
2748 fmt = GET_RTX_FORMAT (code);
2749 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2752 elimination_effects (XEXP (x, i), mem_mode);
2753 else if (*fmt == 'E')
2754 for (j = 0; j < XVECLEN (x, i); j++)
2755 elimination_effects (XVECEXP (x, i, j), mem_mode);
2759 /* Descend through rtx X and verify that no references to eliminable registers
2760 remain. If any do remain, mark the involved register as not
2764 check_eliminable_occurrences (x)
2774 code = GET_CODE (x);
2776 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2778 struct elim_table *ep;
2780 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2781 if (ep->from_rtx == x && ep->can_eliminate)
2782 ep->can_eliminate = 0;
2786 fmt = GET_RTX_FORMAT (code);
2787 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2790 check_eliminable_occurrences (XEXP (x, i));
2791 else if (*fmt == 'E')
2794 for (j = 0; j < XVECLEN (x, i); j++)
2795 check_eliminable_occurrences (XVECEXP (x, i, j));
2800 /* Scan INSN and eliminate all eliminable registers in it.
2802 If REPLACE is nonzero, do the replacement destructively. Also
2803 delete the insn as dead it if it is setting an eliminable register.
2805 If REPLACE is zero, do all our allocations in reload_obstack.
2807 If no eliminations were done and this insn doesn't require any elimination
2808 processing (these are not identical conditions: it might be updating sp,
2809 but not referencing fp; this needs to be seen during reload_as_needed so
2810 that the offset between fp and sp can be taken into consideration), zero
2811 is returned. Otherwise, 1 is returned. */
2814 eliminate_regs_in_insn (insn, replace)
2818 int icode = recog_memoized (insn);
2819 rtx old_body = PATTERN (insn);
2820 int insn_is_asm = asm_noperands (old_body) >= 0;
2821 rtx old_set = single_set (insn);
2825 rtx substed_operand[MAX_RECOG_OPERANDS];
2826 rtx orig_operand[MAX_RECOG_OPERANDS];
2827 struct elim_table *ep;
2829 if (! insn_is_asm && icode < 0)
2831 if (GET_CODE (PATTERN (insn)) == USE
2832 || GET_CODE (PATTERN (insn)) == CLOBBER
2833 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2834 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2835 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2841 push_obstacks (&reload_obstack, &reload_obstack);
2843 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2844 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2846 /* Check for setting an eliminable register. */
2847 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2848 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2850 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2851 /* If this is setting the frame pointer register to the
2852 hardware frame pointer register and this is an elimination
2853 that will be done (tested above), this insn is really
2854 adjusting the frame pointer downward to compensate for
2855 the adjustment done before a nonlocal goto. */
2856 if (ep->from == FRAME_POINTER_REGNUM
2857 && ep->to == HARD_FRAME_POINTER_REGNUM)
2859 rtx src = SET_SRC (old_set);
2860 int offset = 0, ok = 0;
2861 rtx prev_insn, prev_set;
2863 if (src == ep->to_rtx)
2865 else if (GET_CODE (src) == PLUS
2866 && GET_CODE (XEXP (src, 0)) == CONST_INT
2867 && XEXP (src, 1) == ep->to_rtx)
2868 offset = INTVAL (XEXP (src, 0)), ok = 1;
2869 else if (GET_CODE (src) == PLUS
2870 && GET_CODE (XEXP (src, 1)) == CONST_INT
2871 && XEXP (src, 0) == ep->to_rtx)
2872 offset = INTVAL (XEXP (src, 1)), ok = 1;
2873 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
2874 && (prev_set = single_set (prev_insn)) != 0
2875 && rtx_equal_p (SET_DEST (prev_set), src))
2877 src = SET_SRC (prev_set);
2878 if (src == ep->to_rtx)
2880 else if (GET_CODE (src) == PLUS
2881 && GET_CODE (XEXP (src, 0)) == CONST_INT
2882 && XEXP (src, 1) == ep->to_rtx)
2883 offset = INTVAL (XEXP (src, 0)), ok = 1;
2884 else if (GET_CODE (src) == PLUS
2885 && GET_CODE (XEXP (src, 1)) == CONST_INT
2886 && XEXP (src, 0) == ep->to_rtx)
2887 offset = INTVAL (XEXP (src, 1)), ok = 1;
2895 = plus_constant (ep->to_rtx, offset - ep->offset);
2897 /* First see if this insn remains valid when we
2898 make the change. If not, keep the INSN_CODE
2899 the same and let reload fit it up. */
2900 validate_change (insn, &SET_SRC (old_set), src, 1);
2901 validate_change (insn, &SET_DEST (old_set),
2903 if (! apply_change_group ())
2905 SET_SRC (old_set) = src;
2906 SET_DEST (old_set) = ep->to_rtx;
2916 /* In this case this insn isn't serving a useful purpose. We
2917 will delete it in reload_as_needed once we know that this
2918 elimination is, in fact, being done.
2920 If REPLACE isn't set, we can't delete this insn, but needn't
2921 process it since it won't be used unless something changes. */
2924 delete_dead_insn (insn);
2932 /* We allow one special case which happens to work on all machines we
2933 currently support: a single set with the source being a PLUS of an
2934 eliminable register and a constant. */
2936 && GET_CODE (SET_SRC (old_set)) == PLUS
2937 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
2938 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
2939 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
2941 rtx reg = XEXP (SET_SRC (old_set), 0);
2942 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
2944 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2945 if (ep->from_rtx == reg && ep->can_eliminate)
2947 offset += ep->offset;
2951 /* We assume here that we don't need a PARALLEL of
2952 any CLOBBERs for this assignment. There's not
2953 much we can do if we do need it. */
2954 PATTERN (insn) = gen_rtx_SET (VOIDmode,
2957 INSN_CODE (insn) = recog (PATTERN (insn), insn, 0);
2958 if (INSN_CODE (insn) < 0)
2963 new_body = old_body;
2966 new_body = copy_insn (old_body);
2967 if (REG_NOTES (insn))
2968 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2970 PATTERN (insn) = new_body;
2971 old_set = single_set (insn);
2973 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
2974 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
2977 /* This can't have an effect on elimination offsets, so skip right
2983 /* Determine the effects of this insn on elimination offsets. */
2984 elimination_effects (old_body, 0);
2986 /* Eliminate all eliminable registers occurring in operands that
2987 can be handled by reload. */
2988 extract_insn (insn);
2990 for (i = 0; i < recog_data.n_operands; i++)
2992 orig_operand[i] = recog_data.operand[i];
2993 substed_operand[i] = recog_data.operand[i];
2995 /* For an asm statement, every operand is eliminable. */
2996 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
2998 /* Check for setting a register that we know about. */
2999 if (recog_data.operand_type[i] != OP_IN
3000 && GET_CODE (orig_operand[i]) == REG)
3002 /* If we are assigning to a register that can be eliminated, it
3003 must be as part of a PARALLEL, since the code above handles
3004 single SETs. We must indicate that we can no longer
3005 eliminate this reg. */
3006 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3008 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3009 ep->can_eliminate = 0;
3012 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3013 replace ? insn : NULL_RTX);
3014 if (substed_operand[i] != orig_operand[i])
3015 val = any_changes = 1;
3016 /* Terminate the search in check_eliminable_occurrences at
3018 *recog_data.operand_loc[i] = 0;
3020 /* If an output operand changed from a REG to a MEM and INSN is an
3021 insn, write a CLOBBER insn. */
3022 if (recog_data.operand_type[i] != OP_IN
3023 && GET_CODE (orig_operand[i]) == REG
3024 && GET_CODE (substed_operand[i]) == MEM
3026 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3031 for (i = 0; i < recog_data.n_dups; i++)
3032 *recog_data.dup_loc[i]
3033 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3035 /* If any eliminable remain, they aren't eliminable anymore. */
3036 check_eliminable_occurrences (old_body);
3038 /* Substitute the operands; the new values are in the substed_operand
3040 for (i = 0; i < recog_data.n_operands; i++)
3041 *recog_data.operand_loc[i] = substed_operand[i];
3042 for (i = 0; i < recog_data.n_dups; i++)
3043 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3045 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3046 re-recognize the insn. We do this in case we had a simple addition
3047 but now can do this as a load-address. This saves an insn in this
3049 If re-recognition fails, the old insn code number will still be used,
3050 and some register operands may have changed into PLUS expressions.
3051 These will be handled by find_reloads by loading them into a register
3056 /* If we aren't replacing things permanently and we changed something,
3057 make another copy to ensure that all the RTL is new. Otherwise
3058 things can go wrong if find_reload swaps commutative operands
3059 and one is inside RTL that has been copied while the other is not. */
3060 new_body = old_body;
3063 new_body = copy_insn (old_body);
3064 if (REG_NOTES (insn))
3065 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3067 PATTERN (insn) = new_body;
3069 /* If we had a move insn but now we don't, rerecognize it. This will
3070 cause spurious re-recognition if the old move had a PARALLEL since
3071 the new one still will, but we can't call single_set without
3072 having put NEW_BODY into the insn and the re-recognition won't
3073 hurt in this rare case. */
3074 /* ??? Why this huge if statement - why don't we just rerecognize the
3078 && ((GET_CODE (SET_SRC (old_set)) == REG
3079 && (GET_CODE (new_body) != SET
3080 || GET_CODE (SET_SRC (new_body)) != REG))
3081 /* If this was a load from or store to memory, compare
3082 the MEM in recog_data.operand to the one in the insn.
3083 If they are not equal, then rerecognize the insn. */
3085 && ((GET_CODE (SET_SRC (old_set)) == MEM
3086 && SET_SRC (old_set) != recog_data.operand[1])
3087 || (GET_CODE (SET_DEST (old_set)) == MEM
3088 && SET_DEST (old_set) != recog_data.operand[0])))
3089 /* If this was an add insn before, rerecognize. */
3090 || GET_CODE (SET_SRC (old_set)) == PLUS))
3092 int new_icode = recog (PATTERN (insn), insn, 0);
3094 INSN_CODE (insn) = icode;
3098 /* Restore the old body. If there were any changes to it, we made a copy
3099 of it while the changes were still in place, so we'll correctly return
3100 a modified insn below. */
3103 /* Restore the old body. */
3104 for (i = 0; i < recog_data.n_operands; i++)
3105 *recog_data.operand_loc[i] = orig_operand[i];
3106 for (i = 0; i < recog_data.n_dups; i++)
3107 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3110 /* Update all elimination pairs to reflect the status after the current
3111 insn. The changes we make were determined by the earlier call to
3112 elimination_effects.
3114 We also detect a cases where register elimination cannot be done,
3115 namely, if a register would be both changed and referenced outside a MEM
3116 in the resulting insn since such an insn is often undefined and, even if
3117 not, we cannot know what meaning will be given to it. Note that it is
3118 valid to have a register used in an address in an insn that changes it
3119 (presumably with a pre- or post-increment or decrement).
3121 If anything changes, return nonzero. */
3123 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3125 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3126 ep->can_eliminate = 0;
3128 ep->ref_outside_mem = 0;
3130 if (ep->previous_offset != ep->offset)
3135 /* If we changed something, perform elimination in REG_NOTES. This is
3136 needed even when REPLACE is zero because a REG_DEAD note might refer
3137 to a register that we eliminate and could cause a different number
3138 of spill registers to be needed in the final reload pass than in
3140 if (val && REG_NOTES (insn) != 0)
3141 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3149 /* Loop through all elimination pairs.
3150 Recalculate the number not at initial offset.
3152 Compute the maximum offset (minimum offset if the stack does not
3153 grow downward) for each elimination pair. */
3156 update_eliminable_offsets ()
3158 struct elim_table *ep;
3160 num_not_at_initial_offset = 0;
3161 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3163 ep->previous_offset = ep->offset;
3164 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3165 num_not_at_initial_offset++;
3169 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3170 replacement we currently believe is valid, mark it as not eliminable if X
3171 modifies DEST in any way other than by adding a constant integer to it.
3173 If DEST is the frame pointer, we do nothing because we assume that
3174 all assignments to the hard frame pointer are nonlocal gotos and are being
3175 done at a time when they are valid and do not disturb anything else.
3176 Some machines want to eliminate a fake argument pointer with either the
3177 frame or stack pointer. Assignments to the hard frame pointer must not
3178 prevent this elimination.
3180 Called via note_stores from reload before starting its passes to scan
3181 the insns of the function. */
3184 mark_not_eliminable (dest, x, data)
3187 void *data ATTRIBUTE_UNUSED;
3189 register unsigned int i;
3191 /* A SUBREG of a hard register here is just changing its mode. We should
3192 not see a SUBREG of an eliminable hard register, but check just in
3194 if (GET_CODE (dest) == SUBREG)
3195 dest = SUBREG_REG (dest);
3197 if (dest == hard_frame_pointer_rtx)
3200 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3201 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3202 && (GET_CODE (x) != SET
3203 || GET_CODE (SET_SRC (x)) != PLUS
3204 || XEXP (SET_SRC (x), 0) != dest
3205 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3207 reg_eliminate[i].can_eliminate_previous
3208 = reg_eliminate[i].can_eliminate = 0;
3213 /* Verify that the initial elimination offsets did not change since the
3214 last call to set_initial_elim_offsets. This is used to catch cases
3215 where something illegal happened during reload_as_needed that could
3216 cause incorrect code to be generated if we did not check for it. */
3219 verify_initial_elim_offsets ()
3223 #ifdef ELIMINABLE_REGS
3224 struct elim_table *ep;
3226 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3228 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3229 if (t != ep->initial_offset)
3233 INITIAL_FRAME_POINTER_OFFSET (t);
3234 if (t != reg_eliminate[0].initial_offset)
3239 /* Reset all offsets on eliminable registers to their initial values. */
3242 set_initial_elim_offsets ()
3244 struct elim_table *ep = reg_eliminate;
3246 #ifdef ELIMINABLE_REGS
3247 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3249 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3250 ep->previous_offset = ep->offset = ep->initial_offset;
3253 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3254 ep->previous_offset = ep->offset = ep->initial_offset;
3257 num_not_at_initial_offset = 0;
3260 /* Initialize the known label offsets.
3261 Set a known offset for each forced label to be at the initial offset
3262 of each elimination. We do this because we assume that all
3263 computed jumps occur from a location where each elimination is
3264 at its initial offset.
3265 For all other labels, show that we don't know the offsets. */
3268 set_initial_label_offsets ()
3271 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
3273 for (x = forced_labels; x; x = XEXP (x, 1))
3275 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3278 /* Set all elimination offsets to the known values for the code label given
3282 set_offsets_for_label (insn)
3286 int label_nr = CODE_LABEL_NUMBER (insn);
3287 struct elim_table *ep;
3289 num_not_at_initial_offset = 0;
3290 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3292 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3293 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3294 num_not_at_initial_offset++;
3298 /* See if anything that happened changes which eliminations are valid.
3299 For example, on the Sparc, whether or not the frame pointer can
3300 be eliminated can depend on what registers have been used. We need
3301 not check some conditions again (such as flag_omit_frame_pointer)
3302 since they can't have changed. */
3305 update_eliminables (pset)
3308 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3309 int previous_frame_pointer_needed = frame_pointer_needed;
3311 struct elim_table *ep;
3313 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3314 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3315 #ifdef ELIMINABLE_REGS
3316 || ! CAN_ELIMINATE (ep->from, ep->to)
3319 ep->can_eliminate = 0;
3321 /* Look for the case where we have discovered that we can't replace
3322 register A with register B and that means that we will now be
3323 trying to replace register A with register C. This means we can
3324 no longer replace register C with register B and we need to disable
3325 such an elimination, if it exists. This occurs often with A == ap,
3326 B == sp, and C == fp. */
3328 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3330 struct elim_table *op;
3331 register int new_to = -1;
3333 if (! ep->can_eliminate && ep->can_eliminate_previous)
3335 /* Find the current elimination for ep->from, if there is a
3337 for (op = reg_eliminate;
3338 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3339 if (op->from == ep->from && op->can_eliminate)
3345 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3347 for (op = reg_eliminate;
3348 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3349 if (op->from == new_to && op->to == ep->to)
3350 op->can_eliminate = 0;
3354 /* See if any registers that we thought we could eliminate the previous
3355 time are no longer eliminable. If so, something has changed and we
3356 must spill the register. Also, recompute the number of eliminable
3357 registers and see if the frame pointer is needed; it is if there is
3358 no elimination of the frame pointer that we can perform. */
3360 frame_pointer_needed = 1;
3361 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3363 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3364 && ep->to != HARD_FRAME_POINTER_REGNUM)
3365 frame_pointer_needed = 0;
3367 if (! ep->can_eliminate && ep->can_eliminate_previous)
3369 ep->can_eliminate_previous = 0;
3370 SET_HARD_REG_BIT (*pset, ep->from);
3375 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3376 /* If we didn't need a frame pointer last time, but we do now, spill
3377 the hard frame pointer. */
3378 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3379 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3383 /* Initialize the table of registers to eliminate. */
3388 struct elim_table *ep;
3389 #ifdef ELIMINABLE_REGS
3390 struct elim_table_1 *ep1;
3394 reg_eliminate = (struct elim_table *)
3395 xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3397 /* Does this function require a frame pointer? */
3399 frame_pointer_needed = (! flag_omit_frame_pointer
3400 #ifdef EXIT_IGNORE_STACK
3401 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3402 and restore sp for alloca. So we can't eliminate
3403 the frame pointer in that case. At some point,
3404 we should improve this by emitting the
3405 sp-adjusting insns for this case. */
3406 || (current_function_calls_alloca
3407 && EXIT_IGNORE_STACK)
3409 || FRAME_POINTER_REQUIRED);
3413 #ifdef ELIMINABLE_REGS
3414 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3415 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3417 ep->from = ep1->from;
3419 ep->can_eliminate = ep->can_eliminate_previous
3420 = (CAN_ELIMINATE (ep->from, ep->to)
3421 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3424 reg_eliminate[0].from = reg_eliminate_1[0].from;
3425 reg_eliminate[0].to = reg_eliminate_1[0].to;
3426 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3427 = ! frame_pointer_needed;
3430 /* Count the number of eliminable registers and build the FROM and TO
3431 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3432 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3433 We depend on this. */
3434 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3436 num_eliminable += ep->can_eliminate;
3437 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3438 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3442 /* Kick all pseudos out of hard register REGNO.
3444 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3445 because we found we can't eliminate some register. In the case, no pseudos
3446 are allowed to be in the register, even if they are only in a block that
3447 doesn't require spill registers, unlike the case when we are spilling this
3448 hard reg to produce another spill register.
3450 Return nonzero if any pseudos needed to be kicked out. */
3453 spill_hard_reg (regno, cant_eliminate)
3461 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3462 regs_ever_live[regno] = 1;
3465 /* Spill every pseudo reg that was allocated to this reg
3466 or to something that overlaps this reg. */
3468 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3469 if (reg_renumber[i] >= 0
3470 && (unsigned int) reg_renumber[i] <= regno
3471 && ((unsigned int) reg_renumber[i]
3472 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3473 PSEUDO_REGNO_MODE (i))
3475 SET_REGNO_REG_SET (&spilled_pseudos, i);
3478 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3479 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3482 ior_hard_reg_set (set1, set2)
3483 HARD_REG_SET *set1, *set2;
3485 IOR_HARD_REG_SET (*set1, *set2);
3488 /* After find_reload_regs has been run for all insn that need reloads,
3489 and/or spill_hard_regs was called, this function is used to actually
3490 spill pseudo registers and try to reallocate them. It also sets up the
3491 spill_regs array for use by choose_reload_regs. */
3494 finish_spills (global)
3497 struct insn_chain *chain;
3498 int something_changed = 0;
3501 /* Build the spill_regs array for the function. */
3502 /* If there are some registers still to eliminate and one of the spill regs
3503 wasn't ever used before, additional stack space may have to be
3504 allocated to store this register. Thus, we may have changed the offset
3505 between the stack and frame pointers, so mark that something has changed.
3507 One might think that we need only set VAL to 1 if this is a call-used
3508 register. However, the set of registers that must be saved by the
3509 prologue is not identical to the call-used set. For example, the
3510 register used by the call insn for the return PC is a call-used register,
3511 but must be saved by the prologue. */
3514 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3515 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3517 spill_reg_order[i] = n_spills;
3518 spill_regs[n_spills++] = i;
3519 if (num_eliminable && ! regs_ever_live[i])
3520 something_changed = 1;
3521 regs_ever_live[i] = 1;
3524 spill_reg_order[i] = -1;
3526 EXECUTE_IF_SET_IN_REG_SET
3527 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3529 /* Record the current hard register the pseudo is allocated to in
3530 pseudo_previous_regs so we avoid reallocating it to the same
3531 hard reg in a later pass. */
3532 if (reg_renumber[i] < 0)
3535 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3536 /* Mark it as no longer having a hard register home. */
3537 reg_renumber[i] = -1;
3538 /* We will need to scan everything again. */
3539 something_changed = 1;
3542 /* Retry global register allocation if possible. */
3545 bzero ((char *) pseudo_forbidden_regs, max_regno * sizeof (HARD_REG_SET));
3546 /* For every insn that needs reloads, set the registers used as spill
3547 regs in pseudo_forbidden_regs for every pseudo live across the
3549 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3551 EXECUTE_IF_SET_IN_REG_SET
3552 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3554 ior_hard_reg_set (pseudo_forbidden_regs + i,
3555 &chain->used_spill_regs);
3557 EXECUTE_IF_SET_IN_REG_SET
3558 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3560 ior_hard_reg_set (pseudo_forbidden_regs + i,
3561 &chain->used_spill_regs);
3565 /* Retry allocating the spilled pseudos. For each reg, merge the
3566 various reg sets that indicate which hard regs can't be used,
3567 and call retry_global_alloc.
3568 We change spill_pseudos here to only contain pseudos that did not
3569 get a new hard register. */
3570 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3571 if (reg_old_renumber[i] != reg_renumber[i])
3573 HARD_REG_SET forbidden;
3574 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3575 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3576 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3577 retry_global_alloc (i, forbidden);
3578 if (reg_renumber[i] >= 0)
3579 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3583 /* Fix up the register information in the insn chain.
3584 This involves deleting those of the spilled pseudos which did not get
3585 a new hard register home from the live_{before,after} sets. */
3586 for (chain = reload_insn_chain; chain; chain = chain->next)
3588 HARD_REG_SET used_by_pseudos;
3589 HARD_REG_SET used_by_pseudos2;
3591 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3592 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3594 /* Mark any unallocated hard regs as available for spills. That
3595 makes inheritance work somewhat better. */
3596 if (chain->need_reload)
3598 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3599 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3600 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3602 /* Save the old value for the sanity test below. */
3603 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3605 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3606 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3607 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3608 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3610 /* Make sure we only enlarge the set. */
3611 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3617 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3618 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3620 int regno = reg_renumber[i];
3621 if (reg_old_renumber[i] == regno)
3624 alter_reg (i, reg_old_renumber[i]);
3625 reg_old_renumber[i] = regno;
3629 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3631 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3632 i, reg_renumber[i]);
3636 return something_changed;
3639 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3640 Also mark any hard registers used to store user variables as
3641 forbidden from being used for spill registers. */
3644 scan_paradoxical_subregs (x)
3648 register const char *fmt;
3649 register enum rtx_code code = GET_CODE (x);
3655 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3656 && REG_USERVAR_P (x))
3657 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3673 if (GET_CODE (SUBREG_REG (x)) == REG
3674 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3675 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3676 = GET_MODE_SIZE (GET_MODE (x));
3683 fmt = GET_RTX_FORMAT (code);
3684 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3687 scan_paradoxical_subregs (XEXP (x, i));
3688 else if (fmt[i] == 'E')
3691 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3692 scan_paradoxical_subregs (XVECEXP (x, i, j));
3697 /* Reload pseudo-registers into hard regs around each insn as needed.
3698 Additional register load insns are output before the insn that needs it
3699 and perhaps store insns after insns that modify the reloaded pseudo reg.
3701 reg_last_reload_reg and reg_reloaded_contents keep track of
3702 which registers are already available in reload registers.
3703 We update these for the reloads that we perform,
3704 as the insns are scanned. */
3707 reload_as_needed (live_known)
3710 struct insn_chain *chain;
3711 #if defined (AUTO_INC_DEC)
3716 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
3717 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
3718 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3719 reg_has_output_reload = (char *) xmalloc (max_regno);
3720 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3722 set_initial_elim_offsets ();
3724 for (chain = reload_insn_chain; chain; chain = chain->next)
3727 rtx insn = chain->insn;
3728 rtx old_next = NEXT_INSN (insn);
3730 /* If we pass a label, copy the offsets from the label information
3731 into the current offsets of each elimination. */
3732 if (GET_CODE (insn) == CODE_LABEL)
3733 set_offsets_for_label (insn);
3735 else if (INSN_P (insn))
3737 rtx oldpat = PATTERN (insn);
3739 /* If this is a USE and CLOBBER of a MEM, ensure that any
3740 references to eliminable registers have been removed. */
3742 if ((GET_CODE (PATTERN (insn)) == USE
3743 || GET_CODE (PATTERN (insn)) == CLOBBER)
3744 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3745 XEXP (XEXP (PATTERN (insn), 0), 0)
3746 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3747 GET_MODE (XEXP (PATTERN (insn), 0)),
3750 /* If we need to do register elimination processing, do so.
3751 This might delete the insn, in which case we are done. */
3752 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3754 eliminate_regs_in_insn (insn, 1);
3755 if (GET_CODE (insn) == NOTE)
3757 update_eliminable_offsets ();
3762 /* If need_elim is nonzero but need_reload is zero, one might think
3763 that we could simply set n_reloads to 0. However, find_reloads
3764 could have done some manipulation of the insn (such as swapping
3765 commutative operands), and these manipulations are lost during
3766 the first pass for every insn that needs register elimination.
3767 So the actions of find_reloads must be redone here. */
3769 if (! chain->need_elim && ! chain->need_reload
3770 && ! chain->need_operand_change)
3772 /* First find the pseudo regs that must be reloaded for this insn.
3773 This info is returned in the tables reload_... (see reload.h).
3774 Also modify the body of INSN by substituting RELOAD
3775 rtx's for those pseudo regs. */
3778 bzero (reg_has_output_reload, max_regno);
3779 CLEAR_HARD_REG_SET (reg_is_output_reload);
3781 find_reloads (insn, 1, spill_indirect_levels, live_known,
3785 if (num_eliminable && chain->need_elim)
3786 update_eliminable_offsets ();
3790 rtx next = NEXT_INSN (insn);
3793 prev = PREV_INSN (insn);
3795 /* Now compute which reload regs to reload them into. Perhaps
3796 reusing reload regs from previous insns, or else output
3797 load insns to reload them. Maybe output store insns too.
3798 Record the choices of reload reg in reload_reg_rtx. */
3799 choose_reload_regs (chain);
3801 /* Merge any reloads that we didn't combine for fear of
3802 increasing the number of spill registers needed but now
3803 discover can be safely merged. */
3804 if (SMALL_REGISTER_CLASSES)
3805 merge_assigned_reloads (insn);
3807 /* Generate the insns to reload operands into or out of
3808 their reload regs. */
3809 emit_reload_insns (chain);
3811 /* Substitute the chosen reload regs from reload_reg_rtx
3812 into the insn's body (or perhaps into the bodies of other
3813 load and store insn that we just made for reloading
3814 and that we moved the structure into). */
3817 /* If this was an ASM, make sure that all the reload insns
3818 we have generated are valid. If not, give an error
3821 if (asm_noperands (PATTERN (insn)) >= 0)
3822 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3823 if (p != insn && INSN_P (p)
3824 && (recog_memoized (p) < 0
3825 || (extract_insn (p), ! constrain_operands (1))))
3827 error_for_asm (insn,
3828 "`asm' operand requires impossible reload");
3830 NOTE_SOURCE_FILE (p) = 0;
3831 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3834 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3835 is no longer validly lying around to save a future reload.
3836 Note that this does not detect pseudos that were reloaded
3837 for this insn in order to be stored in
3838 (obeying register constraints). That is correct; such reload
3839 registers ARE still valid. */
3840 note_stores (oldpat, forget_old_reloads_1, NULL);
3842 /* There may have been CLOBBER insns placed after INSN. So scan
3843 between INSN and NEXT and use them to forget old reloads. */
3844 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3845 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3846 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3849 /* Likewise for regs altered by auto-increment in this insn.
3850 REG_INC notes have been changed by reloading:
3851 find_reloads_address_1 records substitutions for them,
3852 which have been performed by subst_reloads above. */
3853 for (i = n_reloads - 1; i >= 0; i--)
3855 rtx in_reg = rld[i].in_reg;
3858 enum rtx_code code = GET_CODE (in_reg);
3859 /* PRE_INC / PRE_DEC will have the reload register ending up
3860 with the same value as the stack slot, but that doesn't
3861 hold true for POST_INC / POST_DEC. Either we have to
3862 convert the memory access to a true POST_INC / POST_DEC,
3863 or we can't use the reload register for inheritance. */
3864 if ((code == POST_INC || code == POST_DEC)
3865 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3866 REGNO (rld[i].reg_rtx))
3867 /* Make sure it is the inc/dec pseudo, and not
3868 some other (e.g. output operand) pseudo. */
3869 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3870 == REGNO (XEXP (in_reg, 0))))
3873 rtx reload_reg = rld[i].reg_rtx;
3874 enum machine_mode mode = GET_MODE (reload_reg);
3878 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3880 /* We really want to ignore REG_INC notes here, so
3881 use PATTERN (p) as argument to reg_set_p . */
3882 if (reg_set_p (reload_reg, PATTERN (p)))
3884 n = count_occurrences (PATTERN (p), reload_reg, 0);
3889 n = validate_replace_rtx (reload_reg,
3890 gen_rtx (code, mode,
3894 /* We must also verify that the constraints
3895 are met after the replacement. */
3898 n = constrain_operands (1);
3902 /* If the constraints were not met, then
3903 undo the replacement. */
3906 validate_replace_rtx (gen_rtx (code, mode,
3918 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3920 /* Mark this as having an output reload so that the
3921 REG_INC processing code below won't invalidate
3922 the reload for inheritance. */
3923 SET_HARD_REG_BIT (reg_is_output_reload,
3924 REGNO (reload_reg));
3925 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3928 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3931 else if ((code == PRE_INC || code == PRE_DEC)
3932 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3933 REGNO (rld[i].reg_rtx))
3934 /* Make sure it is the inc/dec pseudo, and not
3935 some other (e.g. output operand) pseudo. */
3936 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3937 == REGNO (XEXP (in_reg, 0))))
3939 SET_HARD_REG_BIT (reg_is_output_reload,
3940 REGNO (rld[i].reg_rtx));
3941 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3945 /* If a pseudo that got a hard register is auto-incremented,
3946 we must purge records of copying it into pseudos without
3948 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3949 if (REG_NOTE_KIND (x) == REG_INC)
3951 /* See if this pseudo reg was reloaded in this insn.
3952 If so, its last-reload info is still valid
3953 because it is based on this insn's reload. */
3954 for (i = 0; i < n_reloads; i++)
3955 if (rld[i].out == XEXP (x, 0))
3959 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
3963 /* A reload reg's contents are unknown after a label. */
3964 if (GET_CODE (insn) == CODE_LABEL)
3965 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3967 /* Don't assume a reload reg is still good after a call insn
3968 if it is a call-used reg. */
3969 else if (GET_CODE (insn) == CALL_INSN)
3970 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
3974 free (reg_last_reload_reg);
3975 free (reg_has_output_reload);
3978 /* Discard all record of any value reloaded from X,
3979 or reloaded in X from someplace else;
3980 unless X is an output reload reg of the current insn.
3982 X may be a hard reg (the reload reg)
3983 or it may be a pseudo reg that was reloaded from. */
3986 forget_old_reloads_1 (x, ignored, data)
3988 rtx ignored ATTRIBUTE_UNUSED;
3989 void *data ATTRIBUTE_UNUSED;
3995 /* note_stores does give us subregs of hard regs. */
3996 while (GET_CODE (x) == SUBREG)
3998 offset += SUBREG_WORD (x);
4002 if (GET_CODE (x) != REG)
4005 regno = REGNO (x) + offset;
4007 if (regno >= FIRST_PSEUDO_REGISTER)
4013 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4014 /* Storing into a spilled-reg invalidates its contents.
4015 This can happen if a block-local pseudo is allocated to that reg
4016 and it wasn't spilled because this block's total need is 0.
4017 Then some insn might have an optional reload and use this reg. */
4018 for (i = 0; i < nr; i++)
4019 /* But don't do this if the reg actually serves as an output
4020 reload reg in the current instruction. */
4022 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4023 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4026 /* Since value of X has changed,
4027 forget any value previously copied from it. */
4030 /* But don't forget a copy if this is the output reload
4031 that establishes the copy's validity. */
4032 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4033 reg_last_reload_reg[regno + nr] = 0;
4036 /* The following HARD_REG_SETs indicate when each hard register is
4037 used for a reload of various parts of the current insn. */
4039 /* If reg is unavailable for all reloads. */
4040 static HARD_REG_SET reload_reg_unavailable;
4041 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4042 static HARD_REG_SET reload_reg_used;
4043 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4044 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4045 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4046 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4047 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4048 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4049 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4050 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4051 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4052 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4053 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4054 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4055 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4056 static HARD_REG_SET reload_reg_used_in_op_addr;
4057 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4058 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4059 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4060 static HARD_REG_SET reload_reg_used_in_insn;
4061 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4062 static HARD_REG_SET reload_reg_used_in_other_addr;
4064 /* If reg is in use as a reload reg for any sort of reload. */
4065 static HARD_REG_SET reload_reg_used_at_all;
4067 /* If reg is use as an inherited reload. We just mark the first register
4069 static HARD_REG_SET reload_reg_used_for_inherit;
4071 /* Records which hard regs are used in any way, either as explicit use or
4072 by being allocated to a pseudo during any point of the current insn. */
4073 static HARD_REG_SET reg_used_in_insn;
4075 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4076 TYPE. MODE is used to indicate how many consecutive regs are
4080 mark_reload_reg_in_use (regno, opnum, type, mode)
4083 enum reload_type type;
4084 enum machine_mode mode;
4086 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4089 for (i = regno; i < nregs + regno; i++)
4094 SET_HARD_REG_BIT (reload_reg_used, i);
4097 case RELOAD_FOR_INPUT_ADDRESS:
4098 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4101 case RELOAD_FOR_INPADDR_ADDRESS:
4102 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4105 case RELOAD_FOR_OUTPUT_ADDRESS:
4106 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4109 case RELOAD_FOR_OUTADDR_ADDRESS:
4110 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4113 case RELOAD_FOR_OPERAND_ADDRESS:
4114 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4117 case RELOAD_FOR_OPADDR_ADDR:
4118 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4121 case RELOAD_FOR_OTHER_ADDRESS:
4122 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4125 case RELOAD_FOR_INPUT:
4126 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4129 case RELOAD_FOR_OUTPUT:
4130 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4133 case RELOAD_FOR_INSN:
4134 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4138 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4142 /* Similarly, but show REGNO is no longer in use for a reload. */
4145 clear_reload_reg_in_use (regno, opnum, type, mode)
4148 enum reload_type type;
4149 enum machine_mode mode;
4151 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4152 unsigned int start_regno, end_regno, r;
4154 /* A complication is that for some reload types, inheritance might
4155 allow multiple reloads of the same types to share a reload register.
4156 We set check_opnum if we have to check only reloads with the same
4157 operand number, and check_any if we have to check all reloads. */
4158 int check_opnum = 0;
4160 HARD_REG_SET *used_in_set;
4165 used_in_set = &reload_reg_used;
4168 case RELOAD_FOR_INPUT_ADDRESS:
4169 used_in_set = &reload_reg_used_in_input_addr[opnum];
4172 case RELOAD_FOR_INPADDR_ADDRESS:
4174 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4177 case RELOAD_FOR_OUTPUT_ADDRESS:
4178 used_in_set = &reload_reg_used_in_output_addr[opnum];
4181 case RELOAD_FOR_OUTADDR_ADDRESS:
4183 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4186 case RELOAD_FOR_OPERAND_ADDRESS:
4187 used_in_set = &reload_reg_used_in_op_addr;
4190 case RELOAD_FOR_OPADDR_ADDR:
4192 used_in_set = &reload_reg_used_in_op_addr_reload;
4195 case RELOAD_FOR_OTHER_ADDRESS:
4196 used_in_set = &reload_reg_used_in_other_addr;
4200 case RELOAD_FOR_INPUT:
4201 used_in_set = &reload_reg_used_in_input[opnum];
4204 case RELOAD_FOR_OUTPUT:
4205 used_in_set = &reload_reg_used_in_output[opnum];
4208 case RELOAD_FOR_INSN:
4209 used_in_set = &reload_reg_used_in_insn;
4214 /* We resolve conflicts with remaining reloads of the same type by
4215 excluding the intervals of of reload registers by them from the
4216 interval of freed reload registers. Since we only keep track of
4217 one set of interval bounds, we might have to exclude somewhat
4218 more then what would be necessary if we used a HARD_REG_SET here.
4219 But this should only happen very infrequently, so there should
4220 be no reason to worry about it. */
4222 start_regno = regno;
4223 end_regno = regno + nregs;
4224 if (check_opnum || check_any)
4226 for (i = n_reloads - 1; i >= 0; i--)
4228 if (rld[i].when_needed == type
4229 && (check_any || rld[i].opnum == opnum)
4232 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4233 unsigned int conflict_end
4235 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4237 /* If there is an overlap with the first to-be-freed register,
4238 adjust the interval start. */
4239 if (conflict_start <= start_regno && conflict_end > start_regno)
4240 start_regno = conflict_end;
4241 /* Otherwise, if there is a conflict with one of the other
4242 to-be-freed registers, adjust the interval end. */
4243 if (conflict_start > start_regno && conflict_start < end_regno)
4244 end_regno = conflict_start;
4249 for (r = start_regno; r < end_regno; r++)
4250 CLEAR_HARD_REG_BIT (*used_in_set, r);
4253 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4254 specified by OPNUM and TYPE. */
4257 reload_reg_free_p (regno, opnum, type)
4260 enum reload_type type;
4264 /* In use for a RELOAD_OTHER means it's not available for anything. */
4265 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4266 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4272 /* In use for anything means we can't use it for RELOAD_OTHER. */
4273 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4274 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4275 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4278 for (i = 0; i < reload_n_operands; i++)
4279 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4280 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4281 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4282 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4283 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4284 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4289 case RELOAD_FOR_INPUT:
4290 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4291 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4294 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4297 /* If it is used for some other input, can't use it. */
4298 for (i = 0; i < reload_n_operands; i++)
4299 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4302 /* If it is used in a later operand's address, can't use it. */
4303 for (i = opnum + 1; i < reload_n_operands; i++)
4304 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4305 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4310 case RELOAD_FOR_INPUT_ADDRESS:
4311 /* Can't use a register if it is used for an input address for this
4312 operand or used as an input in an earlier one. */
4313 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4314 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4317 for (i = 0; i < opnum; i++)
4318 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4323 case RELOAD_FOR_INPADDR_ADDRESS:
4324 /* Can't use a register if it is used for an input address
4325 for this operand or used as an input in an earlier
4327 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4330 for (i = 0; i < opnum; i++)
4331 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4336 case RELOAD_FOR_OUTPUT_ADDRESS:
4337 /* Can't use a register if it is used for an output address for this
4338 operand or used as an output in this or a later operand. */
4339 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4342 for (i = opnum; i < reload_n_operands; i++)
4343 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4348 case RELOAD_FOR_OUTADDR_ADDRESS:
4349 /* Can't use a register if it is used for an output address
4350 for this operand or used as an output in this or a
4352 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4355 for (i = opnum; i < reload_n_operands; i++)
4356 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4361 case RELOAD_FOR_OPERAND_ADDRESS:
4362 for (i = 0; i < reload_n_operands; i++)
4363 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4366 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4367 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4369 case RELOAD_FOR_OPADDR_ADDR:
4370 for (i = 0; i < reload_n_operands; i++)
4371 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4374 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4376 case RELOAD_FOR_OUTPUT:
4377 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4378 outputs, or an operand address for this or an earlier output. */
4379 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4382 for (i = 0; i < reload_n_operands; i++)
4383 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4386 for (i = 0; i <= opnum; i++)
4387 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4388 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4393 case RELOAD_FOR_INSN:
4394 for (i = 0; i < reload_n_operands; i++)
4395 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4396 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4399 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4400 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4402 case RELOAD_FOR_OTHER_ADDRESS:
4403 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4408 /* Return 1 if the value in reload reg REGNO, as used by a reload
4409 needed for the part of the insn specified by OPNUM and TYPE,
4410 is still available in REGNO at the end of the insn.
4412 We can assume that the reload reg was already tested for availability
4413 at the time it is needed, and we should not check this again,
4414 in case the reg has already been marked in use. */
4417 reload_reg_reaches_end_p (regno, opnum, type)
4420 enum reload_type type;
4427 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4428 its value must reach the end. */
4431 /* If this use is for part of the insn,
4432 its value reaches if no subsequent part uses the same register.
4433 Just like the above function, don't try to do this with lots
4436 case RELOAD_FOR_OTHER_ADDRESS:
4437 /* Here we check for everything else, since these don't conflict
4438 with anything else and everything comes later. */
4440 for (i = 0; i < reload_n_operands; i++)
4441 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4442 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4443 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4444 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4445 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4446 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4449 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4450 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4451 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4453 case RELOAD_FOR_INPUT_ADDRESS:
4454 case RELOAD_FOR_INPADDR_ADDRESS:
4455 /* Similar, except that we check only for this and subsequent inputs
4456 and the address of only subsequent inputs and we do not need
4457 to check for RELOAD_OTHER objects since they are known not to
4460 for (i = opnum; i < reload_n_operands; i++)
4461 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4464 for (i = opnum + 1; i < reload_n_operands; i++)
4465 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4466 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4469 for (i = 0; i < reload_n_operands; i++)
4470 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4471 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4472 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4475 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4478 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4479 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4481 case RELOAD_FOR_INPUT:
4482 /* Similar to input address, except we start at the next operand for
4483 both input and input address and we do not check for
4484 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4487 for (i = opnum + 1; i < reload_n_operands; i++)
4488 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4489 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4490 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4493 /* ... fall through ... */
4495 case RELOAD_FOR_OPERAND_ADDRESS:
4496 /* Check outputs and their addresses. */
4498 for (i = 0; i < reload_n_operands; i++)
4499 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4500 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4501 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4506 case RELOAD_FOR_OPADDR_ADDR:
4507 for (i = 0; i < reload_n_operands; i++)
4508 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4509 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4510 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4513 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4514 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4516 case RELOAD_FOR_INSN:
4517 /* These conflict with other outputs with RELOAD_OTHER. So
4518 we need only check for output addresses. */
4522 /* ... fall through ... */
4524 case RELOAD_FOR_OUTPUT:
4525 case RELOAD_FOR_OUTPUT_ADDRESS:
4526 case RELOAD_FOR_OUTADDR_ADDRESS:
4527 /* We already know these can't conflict with a later output. So the
4528 only thing to check are later output addresses. */
4529 for (i = opnum + 1; i < reload_n_operands; i++)
4530 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4531 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4540 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4543 This function uses the same algorithm as reload_reg_free_p above. */
4546 reloads_conflict (r1, r2)
4549 enum reload_type r1_type = rld[r1].when_needed;
4550 enum reload_type r2_type = rld[r2].when_needed;
4551 int r1_opnum = rld[r1].opnum;
4552 int r2_opnum = rld[r2].opnum;
4554 /* RELOAD_OTHER conflicts with everything. */
4555 if (r2_type == RELOAD_OTHER)
4558 /* Otherwise, check conflicts differently for each type. */
4562 case RELOAD_FOR_INPUT:
4563 return (r2_type == RELOAD_FOR_INSN
4564 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4565 || r2_type == RELOAD_FOR_OPADDR_ADDR
4566 || r2_type == RELOAD_FOR_INPUT
4567 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4568 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4569 && r2_opnum > r1_opnum));
4571 case RELOAD_FOR_INPUT_ADDRESS:
4572 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4573 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4575 case RELOAD_FOR_INPADDR_ADDRESS:
4576 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4577 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4579 case RELOAD_FOR_OUTPUT_ADDRESS:
4580 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4581 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4583 case RELOAD_FOR_OUTADDR_ADDRESS:
4584 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4585 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4587 case RELOAD_FOR_OPERAND_ADDRESS:
4588 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4589 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4591 case RELOAD_FOR_OPADDR_ADDR:
4592 return (r2_type == RELOAD_FOR_INPUT
4593 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4595 case RELOAD_FOR_OUTPUT:
4596 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4597 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4598 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4599 && r2_opnum <= r1_opnum));
4601 case RELOAD_FOR_INSN:
4602 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4603 || r2_type == RELOAD_FOR_INSN
4604 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4606 case RELOAD_FOR_OTHER_ADDRESS:
4607 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4617 /* Indexed by reload number, 1 if incoming value
4618 inherited from previous insns. */
4619 char reload_inherited[MAX_RELOADS];
4621 /* For an inherited reload, this is the insn the reload was inherited from,
4622 if we know it. Otherwise, this is 0. */
4623 rtx reload_inheritance_insn[MAX_RELOADS];
4625 /* If non-zero, this is a place to get the value of the reload,
4626 rather than using reload_in. */
4627 rtx reload_override_in[MAX_RELOADS];
4629 /* For each reload, the hard register number of the register used,
4630 or -1 if we did not need a register for this reload. */
4631 int reload_spill_index[MAX_RELOADS];
4633 /* Return 1 if the value in reload reg REGNO, as used by a reload
4634 needed for the part of the insn specified by OPNUM and TYPE,
4635 may be used to load VALUE into it.
4637 Other read-only reloads with the same value do not conflict
4638 unless OUT is non-zero and these other reloads have to live while
4639 output reloads live.
4640 If OUT is CONST0_RTX, this is a special case: it means that the
4641 test should not be for using register REGNO as reload register, but
4642 for copying from register REGNO into the reload register.
4644 RELOADNUM is the number of the reload we want to load this value for;
4645 a reload does not conflict with itself.
4647 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4648 reloads that load an address for the very reload we are considering.
4650 The caller has to make sure that there is no conflict with the return
4653 reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum,
4654 ignore_address_reloads)
4657 enum reload_type type;
4660 int ignore_address_reloads;
4663 /* Set if we see an input reload that must not share its reload register
4664 with any new earlyclobber, but might otherwise share the reload
4665 register with an output or input-output reload. */
4666 int check_earlyclobber = 0;
4670 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4673 if (out == const0_rtx)
4679 /* We use some pseudo 'time' value to check if the lifetimes of the
4680 new register use would overlap with the one of a previous reload
4681 that is not read-only or uses a different value.
4682 The 'time' used doesn't have to be linear in any shape or form, just
4684 Some reload types use different 'buckets' for each operand.
4685 So there are MAX_RECOG_OPERANDS different time values for each
4687 We compute TIME1 as the time when the register for the prospective
4688 new reload ceases to be live, and TIME2 for each existing
4689 reload as the time when that the reload register of that reload
4691 Where there is little to be gained by exact lifetime calculations,
4692 we just make conservative assumptions, i.e. a longer lifetime;
4693 this is done in the 'default:' cases. */
4696 case RELOAD_FOR_OTHER_ADDRESS:
4697 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4698 time1 = copy ? 0 : 1;
4701 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4703 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4704 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4705 respectively, to the time values for these, we get distinct time
4706 values. To get distinct time values for each operand, we have to
4707 multiply opnum by at least three. We round that up to four because
4708 multiply by four is often cheaper. */
4709 case RELOAD_FOR_INPADDR_ADDRESS:
4710 time1 = opnum * 4 + 2;
4712 case RELOAD_FOR_INPUT_ADDRESS:
4713 time1 = opnum * 4 + 3;
4715 case RELOAD_FOR_INPUT:
4716 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4717 executes (inclusive). */
4718 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4720 case RELOAD_FOR_OPADDR_ADDR:
4722 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4723 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4725 case RELOAD_FOR_OPERAND_ADDRESS:
4726 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4728 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4730 case RELOAD_FOR_OUTADDR_ADDRESS:
4731 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4733 case RELOAD_FOR_OUTPUT_ADDRESS:
4734 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4737 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4740 for (i = 0; i < n_reloads; i++)
4742 rtx reg = rld[i].reg_rtx;
4743 if (reg && GET_CODE (reg) == REG
4744 && ((unsigned) regno - true_regnum (reg)
4745 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
4748 if (! rld[i].in || ! rtx_equal_p (rld[i].in, value)
4749 || rld[i].out || out)
4752 switch (rld[i].when_needed)
4754 case RELOAD_FOR_OTHER_ADDRESS:
4757 case RELOAD_FOR_INPADDR_ADDRESS:
4758 /* find_reloads makes sure that a
4759 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4760 by at most one - the first -
4761 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4762 address reload is inherited, the address address reload
4763 goes away, so we can ignore this conflict. */
4764 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4765 && ignore_address_reloads
4766 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4767 Then the address address is still needed to store
4768 back the new address. */
4769 && ! rld[reloadnum].out)
4771 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4772 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4774 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4775 && ignore_address_reloads
4776 /* Unless we are reloading an auto_inc expression. */
4777 && ! rld[reloadnum].out)
4779 time2 = rld[i].opnum * 4 + 2;
4781 case RELOAD_FOR_INPUT_ADDRESS:
4782 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4783 && ignore_address_reloads
4784 && ! rld[reloadnum].out)
4786 time2 = rld[i].opnum * 4 + 3;
4788 case RELOAD_FOR_INPUT:
4789 time2 = rld[i].opnum * 4 + 4;
4790 check_earlyclobber = 1;
4792 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4793 == MAX_RECOG_OPERAND * 4 */
4794 case RELOAD_FOR_OPADDR_ADDR:
4795 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4796 && ignore_address_reloads
4797 && ! rld[reloadnum].out)
4799 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4801 case RELOAD_FOR_OPERAND_ADDRESS:
4802 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4803 check_earlyclobber = 1;
4805 case RELOAD_FOR_INSN:
4806 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4808 case RELOAD_FOR_OUTPUT:
4809 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4810 instruction is executed. */
4811 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4813 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4814 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4816 case RELOAD_FOR_OUTADDR_ADDRESS:
4817 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4818 && ignore_address_reloads
4819 && ! rld[reloadnum].out)
4821 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4823 case RELOAD_FOR_OUTPUT_ADDRESS:
4824 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4827 /* If there is no conflict in the input part, handle this
4828 like an output reload. */
4829 if (! rld[i].in || rtx_equal_p (rld[i].in, value))
4831 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4832 /* Earlyclobbered outputs must conflict with inputs. */
4833 if (earlyclobber_operand_p (rld[i].out))
4834 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4839 /* RELOAD_OTHER might be live beyond instruction execution,
4840 but this is not obvious when we set time2 = 1. So check
4841 here if there might be a problem with the new reload
4842 clobbering the register used by the RELOAD_OTHER. */
4850 && (! rld[i].in || rld[i].out
4851 || ! rtx_equal_p (rld[i].in, value)))
4852 || (out && rld[reloadnum].out_reg
4853 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4859 /* Earlyclobbered outputs must conflict with inputs. */
4860 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4866 /* Give an error message saying we failed to find a reload for INSN,
4867 and clear out reload R. */
4869 failed_reload (insn, r)
4873 if (asm_noperands (PATTERN (insn)) < 0)
4874 /* It's the compiler's fault. */
4875 fatal_insn ("Could not find a spill register", insn);
4877 /* It's the user's fault; the operand's mode and constraint
4878 don't match. Disable this reload so we don't crash in final. */
4879 error_for_asm (insn,
4880 "`asm' operand constraint incompatible with operand size");
4884 rld[r].optional = 1;
4885 rld[r].secondary_p = 1;
4888 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
4889 for reload R. If it's valid, get an rtx for it. Return nonzero if
4892 set_reload_reg (i, r)
4896 rtx reg = spill_reg_rtx[i];
4898 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
4899 spill_reg_rtx[i] = reg
4900 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
4902 regno = true_regnum (reg);
4904 /* Detect when the reload reg can't hold the reload mode.
4905 This used to be one `if', but Sequent compiler can't handle that. */
4906 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
4908 enum machine_mode test_mode = VOIDmode;
4910 test_mode = GET_MODE (rld[r].in);
4911 /* If rld[r].in has VOIDmode, it means we will load it
4912 in whatever mode the reload reg has: to wit, rld[r].mode.
4913 We have already tested that for validity. */
4914 /* Aside from that, we need to test that the expressions
4915 to reload from or into have modes which are valid for this
4916 reload register. Otherwise the reload insns would be invalid. */
4917 if (! (rld[r].in != 0 && test_mode != VOIDmode
4918 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
4919 if (! (rld[r].out != 0
4920 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
4922 /* The reg is OK. */
4925 /* Mark as in use for this insn the reload regs we use
4927 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
4928 rld[r].when_needed, rld[r].mode);
4930 rld[r].reg_rtx = reg;
4931 reload_spill_index[r] = spill_regs[i];
4938 /* Find a spill register to use as a reload register for reload R.
4939 LAST_RELOAD is non-zero if this is the last reload for the insn being
4942 Set rld[R].reg_rtx to the register allocated.
4944 We return 1 if successful, or 0 if we couldn't find a spill reg and
4945 we didn't change anything. */
4948 allocate_reload_reg (chain, r, last_reload)
4949 struct insn_chain *chain ATTRIBUTE_UNUSED;
4955 /* If we put this reload ahead, thinking it is a group,
4956 then insist on finding a group. Otherwise we can grab a
4957 reg that some other reload needs.
4958 (That can happen when we have a 68000 DATA_OR_FP_REG
4959 which is a group of data regs or one fp reg.)
4960 We need not be so restrictive if there are no more reloads
4963 ??? Really it would be nicer to have smarter handling
4964 for that kind of reg class, where a problem like this is normal.
4965 Perhaps those classes should be avoided for reloading
4966 by use of more alternatives. */
4968 int force_group = rld[r].nregs > 1 && ! last_reload;
4970 /* If we want a single register and haven't yet found one,
4971 take any reg in the right class and not in use.
4972 If we want a consecutive group, here is where we look for it.
4974 We use two passes so we can first look for reload regs to
4975 reuse, which are already in use for other reloads in this insn,
4976 and only then use additional registers.
4977 I think that maximizing reuse is needed to make sure we don't
4978 run out of reload regs. Suppose we have three reloads, and
4979 reloads A and B can share regs. These need two regs.
4980 Suppose A and B are given different regs.
4981 That leaves none for C. */
4982 for (pass = 0; pass < 2; pass++)
4984 /* I is the index in spill_regs.
4985 We advance it round-robin between insns to use all spill regs
4986 equally, so that inherited reloads have a chance
4987 of leapfrogging each other. */
4991 for (count = 0; count < n_spills; count++)
4993 int class = (int) rld[r].class;
4999 regnum = spill_regs[i];
5001 if ((reload_reg_free_p (regnum, rld[r].opnum,
5004 /* We check reload_reg_used to make sure we
5005 don't clobber the return register. */
5006 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5007 && reload_reg_free_for_value_p (regnum,
5012 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5013 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5014 /* Look first for regs to share, then for unshared. But
5015 don't share regs used for inherited reloads; they are
5016 the ones we want to preserve. */
5018 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5020 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5023 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5024 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5025 (on 68000) got us two FP regs. If NR is 1,
5026 we would reject both of them. */
5029 /* If we need only one reg, we have already won. */
5032 /* But reject a single reg if we demand a group. */
5037 /* Otherwise check that as many consecutive regs as we need
5038 are available here. */
5041 int regno = regnum + nr - 1;
5042 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5043 && spill_reg_order[regno] >= 0
5044 && reload_reg_free_p (regno, rld[r].opnum,
5045 rld[r].when_needed)))
5054 /* If we found something on pass 1, omit pass 2. */
5055 if (count < n_spills)
5059 /* We should have found a spill register by now. */
5060 if (count >= n_spills)
5063 /* I is the index in SPILL_REG_RTX of the reload register we are to
5064 allocate. Get an rtx for it and find its register number. */
5066 return set_reload_reg (i, r);
5069 /* Initialize all the tables needed to allocate reload registers.
5070 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5071 is the array we use to restore the reg_rtx field for every reload. */
5074 choose_reload_regs_init (chain, save_reload_reg_rtx)
5075 struct insn_chain *chain;
5076 rtx *save_reload_reg_rtx;
5080 for (i = 0; i < n_reloads; i++)
5081 rld[i].reg_rtx = save_reload_reg_rtx[i];
5083 bzero (reload_inherited, MAX_RELOADS);
5084 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5085 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5087 CLEAR_HARD_REG_SET (reload_reg_used);
5088 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5089 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5090 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5091 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5092 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5094 CLEAR_HARD_REG_SET (reg_used_in_insn);
5097 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5098 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5099 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5100 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5101 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5102 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5105 for (i = 0; i < reload_n_operands; i++)
5107 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5108 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5109 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5110 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5111 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5112 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5115 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5117 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5119 for (i = 0; i < n_reloads; i++)
5120 /* If we have already decided to use a certain register,
5121 don't use it in another way. */
5123 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5124 rld[i].when_needed, rld[i].mode);
5127 /* Assign hard reg targets for the pseudo-registers we must reload
5128 into hard regs for this insn.
5129 Also output the instructions to copy them in and out of the hard regs.
5131 For machines with register classes, we are responsible for
5132 finding a reload reg in the proper class. */
5135 choose_reload_regs (chain)
5136 struct insn_chain *chain;
5138 rtx insn = chain->insn;
5140 unsigned int max_group_size = 1;
5141 enum reg_class group_class = NO_REGS;
5142 int pass, win, inheritance;
5144 rtx save_reload_reg_rtx[MAX_RELOADS];
5146 /* In order to be certain of getting the registers we need,
5147 we must sort the reloads into order of increasing register class.
5148 Then our grabbing of reload registers will parallel the process
5149 that provided the reload registers.
5151 Also note whether any of the reloads wants a consecutive group of regs.
5152 If so, record the maximum size of the group desired and what
5153 register class contains all the groups needed by this insn. */
5155 for (j = 0; j < n_reloads; j++)
5157 reload_order[j] = j;
5158 reload_spill_index[j] = -1;
5160 if (rld[j].nregs > 1)
5162 max_group_size = MAX (rld[j].nregs, max_group_size);
5164 = reg_class_superunion[(int) rld[j].class][(int)group_class];
5167 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5171 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5173 /* If -O, try first with inheritance, then turning it off.
5174 If not -O, don't do inheritance.
5175 Using inheritance when not optimizing leads to paradoxes
5176 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5177 because one side of the comparison might be inherited. */
5179 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5181 choose_reload_regs_init (chain, save_reload_reg_rtx);
5183 /* Process the reloads in order of preference just found.
5184 Beyond this point, subregs can be found in reload_reg_rtx.
5186 This used to look for an existing reloaded home for all of the
5187 reloads, and only then perform any new reloads. But that could lose
5188 if the reloads were done out of reg-class order because a later
5189 reload with a looser constraint might have an old home in a register
5190 needed by an earlier reload with a tighter constraint.
5192 To solve this, we make two passes over the reloads, in the order
5193 described above. In the first pass we try to inherit a reload
5194 from a previous insn. If there is a later reload that needs a
5195 class that is a proper subset of the class being processed, we must
5196 also allocate a spill register during the first pass.
5198 Then make a second pass over the reloads to allocate any reloads
5199 that haven't been given registers yet. */
5201 for (j = 0; j < n_reloads; j++)
5203 register int r = reload_order[j];
5204 rtx search_equiv = NULL_RTX;
5206 /* Ignore reloads that got marked inoperative. */
5207 if (rld[r].out == 0 && rld[r].in == 0
5208 && ! rld[r].secondary_p)
5211 /* If find_reloads chose to use reload_in or reload_out as a reload
5212 register, we don't need to chose one. Otherwise, try even if it
5213 found one since we might save an insn if we find the value lying
5215 Try also when reload_in is a pseudo without a hard reg. */
5216 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5217 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5218 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5219 && GET_CODE (rld[r].in) != MEM
5220 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5223 #if 0 /* No longer needed for correct operation.
5224 It might give better code, or might not; worth an experiment? */
5225 /* If this is an optional reload, we can't inherit from earlier insns
5226 until we are sure that any non-optional reloads have been allocated.
5227 The following code takes advantage of the fact that optional reloads
5228 are at the end of reload_order. */
5229 if (rld[r].optional != 0)
5230 for (i = 0; i < j; i++)
5231 if ((rld[reload_order[i]].out != 0
5232 || rld[reload_order[i]].in != 0
5233 || rld[reload_order[i]].secondary_p)
5234 && ! rld[reload_order[i]].optional
5235 && rld[reload_order[i]].reg_rtx == 0)
5236 allocate_reload_reg (chain, reload_order[i], 0);
5239 /* First see if this pseudo is already available as reloaded
5240 for a previous insn. We cannot try to inherit for reloads
5241 that are smaller than the maximum number of registers needed
5242 for groups unless the register we would allocate cannot be used
5245 We could check here to see if this is a secondary reload for
5246 an object that is already in a register of the desired class.
5247 This would avoid the need for the secondary reload register.
5248 But this is complex because we can't easily determine what
5249 objects might want to be loaded via this reload. So let a
5250 register be allocated here. In `emit_reload_insns' we suppress
5251 one of the loads in the case described above. */
5256 register int regno = -1;
5257 enum machine_mode mode = VOIDmode;
5261 else if (GET_CODE (rld[r].in) == REG)
5263 regno = REGNO (rld[r].in);
5264 mode = GET_MODE (rld[r].in);
5266 else if (GET_CODE (rld[r].in_reg) == REG)
5268 regno = REGNO (rld[r].in_reg);
5269 mode = GET_MODE (rld[r].in_reg);
5271 else if (GET_CODE (rld[r].in_reg) == SUBREG
5272 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5274 word = SUBREG_WORD (rld[r].in_reg);
5275 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5276 if (regno < FIRST_PSEUDO_REGISTER)
5278 mode = GET_MODE (rld[r].in_reg);
5281 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5282 || GET_CODE (rld[r].in_reg) == PRE_DEC
5283 || GET_CODE (rld[r].in_reg) == POST_INC
5284 || GET_CODE (rld[r].in_reg) == POST_DEC)
5285 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5287 regno = REGNO (XEXP (rld[r].in_reg, 0));
5288 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5289 rld[r].out = rld[r].in;
5293 /* This won't work, since REGNO can be a pseudo reg number.
5294 Also, it takes much more hair to keep track of all the things
5295 that can invalidate an inherited reload of part of a pseudoreg. */
5296 else if (GET_CODE (rld[r].in) == SUBREG
5297 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5298 regno = REGNO (SUBREG_REG (rld[r].in)) + SUBREG_WORD (rld[r].in);
5301 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5303 enum reg_class class = rld[r].class, last_class;
5304 rtx last_reg = reg_last_reload_reg[regno];
5305 enum machine_mode need_mode;
5307 i = REGNO (last_reg) + word;
5308 last_class = REGNO_REG_CLASS (i);
5310 need_mode = smallest_mode_for_size ((word+1) * UNITS_PER_WORD,
5311 GET_MODE_CLASS (mode));
5314 #ifdef CLASS_CANNOT_CHANGE_MODE
5316 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], i)
5317 ? ! CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (last_reg),
5319 : (GET_MODE_SIZE (GET_MODE (last_reg))
5320 >= GET_MODE_SIZE (need_mode)))
5322 (GET_MODE_SIZE (GET_MODE (last_reg))
5323 >= GET_MODE_SIZE (need_mode))
5325 && reg_reloaded_contents[i] == regno
5326 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5327 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5328 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5329 /* Even if we can't use this register as a reload
5330 register, we might use it for reload_override_in,
5331 if copying it to the desired class is cheap
5333 || ((REGISTER_MOVE_COST (last_class, class)
5334 < MEMORY_MOVE_COST (mode, class, 1))
5335 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5336 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5340 #ifdef SECONDARY_MEMORY_NEEDED
5341 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5346 && (rld[r].nregs == max_group_size
5347 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5349 && reload_reg_free_for_value_p (i, rld[r].opnum,
5354 /* If a group is needed, verify that all the subsequent
5355 registers still have their values intact. */
5356 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5359 for (k = 1; k < nr; k++)
5360 if (reg_reloaded_contents[i + k] != regno
5361 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5368 last_reg = (GET_MODE (last_reg) == mode
5369 ? last_reg : gen_rtx_REG (mode, i));
5371 /* We found a register that contains the
5372 value we need. If this register is the
5373 same as an `earlyclobber' operand of the
5374 current insn, just mark it as a place to
5375 reload from since we can't use it as the
5376 reload register itself. */
5378 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5379 if (reg_overlap_mentioned_for_reload_p
5380 (reg_last_reload_reg[regno],
5381 reload_earlyclobbers[i1]))
5384 if (i1 != n_earlyclobbers
5385 || ! (reload_reg_free_for_value_p
5386 (i, rld[r].opnum, rld[r].when_needed,
5387 rld[r].in, rld[r].out, r, 1))
5388 /* Don't use it if we'd clobber a pseudo reg. */
5389 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5391 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5392 /* Don't clobber the frame pointer. */
5393 || (i == HARD_FRAME_POINTER_REGNUM
5395 /* Don't really use the inherited spill reg
5396 if we need it wider than we've got it. */
5397 || (GET_MODE_SIZE (rld[r].mode)
5398 > GET_MODE_SIZE (mode))
5399 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5402 /* If find_reloads chose reload_out as reload
5403 register, stay with it - that leaves the
5404 inherited register for subsequent reloads. */
5405 || (rld[r].out && rld[r].reg_rtx
5406 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5408 reload_override_in[r] = last_reg;
5409 reload_inheritance_insn[r]
5410 = reg_reloaded_insn[i];
5415 /* We can use this as a reload reg. */
5416 /* Mark the register as in use for this part of
5418 mark_reload_reg_in_use (i,
5422 rld[r].reg_rtx = last_reg;
5423 reload_inherited[r] = 1;
5424 reload_inheritance_insn[r]
5425 = reg_reloaded_insn[i];
5426 reload_spill_index[r] = i;
5427 for (k = 0; k < nr; k++)
5428 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5436 /* Here's another way to see if the value is already lying around. */
5439 && ! reload_inherited[r]
5441 && (CONSTANT_P (rld[r].in)
5442 || GET_CODE (rld[r].in) == PLUS
5443 || GET_CODE (rld[r].in) == REG
5444 || GET_CODE (rld[r].in) == MEM)
5445 && (rld[r].nregs == max_group_size
5446 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5447 search_equiv = rld[r].in;
5448 /* If this is an output reload from a simple move insn, look
5449 if an equivalence for the input is available. */
5450 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5452 rtx set = single_set (insn);
5455 && rtx_equal_p (rld[r].out, SET_DEST (set))
5456 && CONSTANT_P (SET_SRC (set)))
5457 search_equiv = SET_SRC (set);
5463 = find_equiv_reg (search_equiv, insn, rld[r].class,
5464 -1, NULL_PTR, 0, rld[r].mode);
5469 if (GET_CODE (equiv) == REG)
5470 regno = REGNO (equiv);
5471 else if (GET_CODE (equiv) == SUBREG)
5473 /* This must be a SUBREG of a hard register.
5474 Make a new REG since this might be used in an
5475 address and not all machines support SUBREGs
5477 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5478 equiv = gen_rtx_REG (rld[r].mode, regno);
5484 /* If we found a spill reg, reject it unless it is free
5485 and of the desired class. */
5487 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5488 && ! reload_reg_free_for_value_p (regno, rld[r].opnum,
5492 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5496 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5499 /* We found a register that contains the value we need.
5500 If this register is the same as an `earlyclobber' operand
5501 of the current insn, just mark it as a place to reload from
5502 since we can't use it as the reload register itself. */
5505 for (i = 0; i < n_earlyclobbers; i++)
5506 if (reg_overlap_mentioned_for_reload_p (equiv,
5507 reload_earlyclobbers[i]))
5509 reload_override_in[r] = equiv;
5514 /* If the equiv register we have found is explicitly clobbered
5515 in the current insn, it depends on the reload type if we
5516 can use it, use it for reload_override_in, or not at all.
5517 In particular, we then can't use EQUIV for a
5518 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5520 if (equiv != 0 && regno_clobbered_p (regno, insn))
5522 switch (rld[r].when_needed)
5524 case RELOAD_FOR_OTHER_ADDRESS:
5525 case RELOAD_FOR_INPADDR_ADDRESS:
5526 case RELOAD_FOR_INPUT_ADDRESS:
5527 case RELOAD_FOR_OPADDR_ADDR:
5530 case RELOAD_FOR_INPUT:
5531 case RELOAD_FOR_OPERAND_ADDRESS:
5532 reload_override_in[r] = equiv;
5540 /* If we found an equivalent reg, say no code need be generated
5541 to load it, and use it as our reload reg. */
5542 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5544 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5546 rld[r].reg_rtx = equiv;
5547 reload_inherited[r] = 1;
5549 /* If reg_reloaded_valid is not set for this register,
5550 there might be a stale spill_reg_store lying around.
5551 We must clear it, since otherwise emit_reload_insns
5552 might delete the store. */
5553 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5554 spill_reg_store[regno] = NULL_RTX;
5555 /* If any of the hard registers in EQUIV are spill
5556 registers, mark them as in use for this insn. */
5557 for (k = 0; k < nr; k++)
5559 i = spill_reg_order[regno + k];
5562 mark_reload_reg_in_use (regno, rld[r].opnum,
5565 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5572 /* If we found a register to use already, or if this is an optional
5573 reload, we are done. */
5574 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5578 /* No longer needed for correct operation. Might or might
5579 not give better code on the average. Want to experiment? */
5581 /* See if there is a later reload that has a class different from our
5582 class that intersects our class or that requires less register
5583 than our reload. If so, we must allocate a register to this
5584 reload now, since that reload might inherit a previous reload
5585 and take the only available register in our class. Don't do this
5586 for optional reloads since they will force all previous reloads
5587 to be allocated. Also don't do this for reloads that have been
5590 for (i = j + 1; i < n_reloads; i++)
5592 int s = reload_order[i];
5594 if ((rld[s].in == 0 && rld[s].out == 0
5595 && ! rld[s].secondary_p)
5599 if ((rld[s].class != rld[r].class
5600 && reg_classes_intersect_p (rld[r].class,
5602 || rld[s].nregs < rld[r].nregs)
5609 allocate_reload_reg (chain, r, j == n_reloads - 1);
5613 /* Now allocate reload registers for anything non-optional that
5614 didn't get one yet. */
5615 for (j = 0; j < n_reloads; j++)
5617 register int r = reload_order[j];
5619 /* Ignore reloads that got marked inoperative. */
5620 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5623 /* Skip reloads that already have a register allocated or are
5625 if (rld[r].reg_rtx != 0 || rld[r].optional)
5628 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5632 /* If that loop got all the way, we have won. */
5639 /* Loop around and try without any inheritance. */
5644 /* First undo everything done by the failed attempt
5645 to allocate with inheritance. */
5646 choose_reload_regs_init (chain, save_reload_reg_rtx);
5648 /* Some sanity tests to verify that the reloads found in the first
5649 pass are identical to the ones we have now. */
5650 if (chain->n_reloads != n_reloads)
5653 for (i = 0; i < n_reloads; i++)
5655 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5657 if (chain->rld[i].when_needed != rld[i].when_needed)
5659 for (j = 0; j < n_spills; j++)
5660 if (spill_regs[j] == chain->rld[i].regno)
5661 if (! set_reload_reg (j, i))
5662 failed_reload (chain->insn, i);
5666 /* If we thought we could inherit a reload, because it seemed that
5667 nothing else wanted the same reload register earlier in the insn,
5668 verify that assumption, now that all reloads have been assigned.
5669 Likewise for reloads where reload_override_in has been set. */
5671 /* If doing expensive optimizations, do one preliminary pass that doesn't
5672 cancel any inheritance, but removes reloads that have been needed only
5673 for reloads that we know can be inherited. */
5674 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5676 for (j = 0; j < n_reloads; j++)
5678 register int r = reload_order[j];
5680 if (reload_inherited[r] && rld[r].reg_rtx)
5681 check_reg = rld[r].reg_rtx;
5682 else if (reload_override_in[r]
5683 && (GET_CODE (reload_override_in[r]) == REG
5684 || GET_CODE (reload_override_in[r]) == SUBREG))
5685 check_reg = reload_override_in[r];
5688 if (! reload_reg_free_for_value_p (true_regnum (check_reg),
5692 (reload_inherited[r]
5693 ? rld[r].out : const0_rtx),
5698 reload_inherited[r] = 0;
5699 reload_override_in[r] = 0;
5701 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5702 reload_override_in, then we do not need its related
5703 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5704 likewise for other reload types.
5705 We handle this by removing a reload when its only replacement
5706 is mentioned in reload_in of the reload we are going to inherit.
5707 A special case are auto_inc expressions; even if the input is
5708 inherited, we still need the address for the output. We can
5709 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5710 If we suceeded removing some reload and we are doing a preliminary
5711 pass just to remove such reloads, make another pass, since the
5712 removal of one reload might allow us to inherit another one. */
5714 && rld[r].out != rld[r].in
5715 && remove_address_replacements (rld[r].in) && pass)
5720 /* Now that reload_override_in is known valid,
5721 actually override reload_in. */
5722 for (j = 0; j < n_reloads; j++)
5723 if (reload_override_in[j])
5724 rld[j].in = reload_override_in[j];
5726 /* If this reload won't be done because it has been cancelled or is
5727 optional and not inherited, clear reload_reg_rtx so other
5728 routines (such as subst_reloads) don't get confused. */
5729 for (j = 0; j < n_reloads; j++)
5730 if (rld[j].reg_rtx != 0
5731 && ((rld[j].optional && ! reload_inherited[j])
5732 || (rld[j].in == 0 && rld[j].out == 0
5733 && ! rld[j].secondary_p)))
5735 int regno = true_regnum (rld[j].reg_rtx);
5737 if (spill_reg_order[regno] >= 0)
5738 clear_reload_reg_in_use (regno, rld[j].opnum,
5739 rld[j].when_needed, rld[j].mode);
5741 reload_spill_index[j] = -1;
5744 /* Record which pseudos and which spill regs have output reloads. */
5745 for (j = 0; j < n_reloads; j++)
5747 register int r = reload_order[j];
5749 i = reload_spill_index[r];
5751 /* I is nonneg if this reload uses a register.
5752 If rld[r].reg_rtx is 0, this is an optional reload
5753 that we opted to ignore. */
5754 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5755 && rld[r].reg_rtx != 0)
5757 register int nregno = REGNO (rld[r].out_reg);
5760 if (nregno < FIRST_PSEUDO_REGISTER)
5761 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5764 reg_has_output_reload[nregno + nr] = 1;
5768 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5770 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5773 if (rld[r].when_needed != RELOAD_OTHER
5774 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5775 && rld[r].when_needed != RELOAD_FOR_INSN)
5781 /* Deallocate the reload register for reload R. This is called from
5782 remove_address_replacements. */
5785 deallocate_reload_reg (r)
5790 if (! rld[r].reg_rtx)
5792 regno = true_regnum (rld[r].reg_rtx);
5794 if (spill_reg_order[regno] >= 0)
5795 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5797 reload_spill_index[r] = -1;
5800 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5801 reloads of the same item for fear that we might not have enough reload
5802 registers. However, normally they will get the same reload register
5803 and hence actually need not be loaded twice.
5805 Here we check for the most common case of this phenomenon: when we have
5806 a number of reloads for the same object, each of which were allocated
5807 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5808 reload, and is not modified in the insn itself. If we find such,
5809 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5810 This will not increase the number of spill registers needed and will
5811 prevent redundant code. */
5814 merge_assigned_reloads (insn)
5819 /* Scan all the reloads looking for ones that only load values and
5820 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5821 assigned and not modified by INSN. */
5823 for (i = 0; i < n_reloads; i++)
5825 int conflicting_input = 0;
5826 int max_input_address_opnum = -1;
5827 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5829 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5830 || rld[i].out != 0 || rld[i].reg_rtx == 0
5831 || reg_set_p (rld[i].reg_rtx, insn))
5834 /* Look at all other reloads. Ensure that the only use of this
5835 reload_reg_rtx is in a reload that just loads the same value
5836 as we do. Note that any secondary reloads must be of the identical
5837 class since the values, modes, and result registers are the
5838 same, so we need not do anything with any secondary reloads. */
5840 for (j = 0; j < n_reloads; j++)
5842 if (i == j || rld[j].reg_rtx == 0
5843 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
5847 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5848 && rld[j].opnum > max_input_address_opnum)
5849 max_input_address_opnum = rld[j].opnum;
5851 /* If the reload regs aren't exactly the same (e.g, different modes)
5852 or if the values are different, we can't merge this reload.
5853 But if it is an input reload, we might still merge
5854 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
5856 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5857 || rld[j].out != 0 || rld[j].in == 0
5858 || ! rtx_equal_p (rld[i].in, rld[j].in))
5860 if (rld[j].when_needed != RELOAD_FOR_INPUT
5861 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
5862 || rld[i].opnum > rld[j].opnum)
5863 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
5865 conflicting_input = 1;
5866 if (min_conflicting_input_opnum > rld[j].opnum)
5867 min_conflicting_input_opnum = rld[j].opnum;
5871 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5872 we, in fact, found any matching reloads. */
5875 && max_input_address_opnum <= min_conflicting_input_opnum)
5877 for (j = 0; j < n_reloads; j++)
5878 if (i != j && rld[j].reg_rtx != 0
5879 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5880 && (! conflicting_input
5881 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5882 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
5884 rld[i].when_needed = RELOAD_OTHER;
5886 reload_spill_index[j] = -1;
5887 transfer_replacements (i, j);
5890 /* If this is now RELOAD_OTHER, look for any reloads that load
5891 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5892 if they were for inputs, RELOAD_OTHER for outputs. Note that
5893 this test is equivalent to looking for reloads for this operand
5896 if (rld[i].when_needed == RELOAD_OTHER)
5897 for (j = 0; j < n_reloads; j++)
5899 && rld[i].when_needed != RELOAD_OTHER
5900 && reg_overlap_mentioned_for_reload_p (rld[j].in,
5903 = ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
5904 || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
5905 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
5910 /* These arrays are filled by emit_reload_insns and its subroutines. */
5911 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
5912 static rtx other_input_address_reload_insns = 0;
5913 static rtx other_input_reload_insns = 0;
5914 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
5915 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5916 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
5917 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
5918 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5919 static rtx operand_reload_insns = 0;
5920 static rtx other_operand_reload_insns = 0;
5921 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
5923 /* Values to be put in spill_reg_store are put here first. */
5924 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
5925 static HARD_REG_SET reg_reloaded_died;
5927 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
5928 has the number J. OLD contains the value to be used as input. */
5931 emit_input_reload_insns (chain, rl, old, j)
5932 struct insn_chain *chain;
5937 rtx insn = chain->insn;
5938 register rtx reloadreg = rl->reg_rtx;
5939 rtx oldequiv_reg = 0;
5942 enum machine_mode mode;
5945 /* Determine the mode to reload in.
5946 This is very tricky because we have three to choose from.
5947 There is the mode the insn operand wants (rl->inmode).
5948 There is the mode of the reload register RELOADREG.
5949 There is the intrinsic mode of the operand, which we could find
5950 by stripping some SUBREGs.
5951 It turns out that RELOADREG's mode is irrelevant:
5952 we can change that arbitrarily.
5954 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
5955 then the reload reg may not support QImode moves, so use SImode.
5956 If foo is in memory due to spilling a pseudo reg, this is safe,
5957 because the QImode value is in the least significant part of a
5958 slot big enough for a SImode. If foo is some other sort of
5959 memory reference, then it is impossible to reload this case,
5960 so previous passes had better make sure this never happens.
5962 Then consider a one-word union which has SImode and one of its
5963 members is a float, being fetched as (SUBREG:SF union:SI).
5964 We must fetch that as SFmode because we could be loading into
5965 a float-only register. In this case OLD's mode is correct.
5967 Consider an immediate integer: it has VOIDmode. Here we need
5968 to get a mode from something else.
5970 In some cases, there is a fourth mode, the operand's
5971 containing mode. If the insn specifies a containing mode for
5972 this operand, it overrides all others.
5974 I am not sure whether the algorithm here is always right,
5975 but it does the right things in those cases. */
5977 mode = GET_MODE (old);
5978 if (mode == VOIDmode)
5981 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5982 /* If we need a secondary register for this operation, see if
5983 the value is already in a register in that class. Don't
5984 do this if the secondary register will be used as a scratch
5987 if (rl->secondary_in_reload >= 0
5988 && rl->secondary_in_icode == CODE_FOR_nothing
5991 = find_equiv_reg (old, insn,
5992 rld[rl->secondary_in_reload].class,
5993 -1, NULL_PTR, 0, mode);
5996 /* If reloading from memory, see if there is a register
5997 that already holds the same value. If so, reload from there.
5998 We can pass 0 as the reload_reg_p argument because
5999 any other reload has either already been emitted,
6000 in which case find_equiv_reg will see the reload-insn,
6001 or has yet to be emitted, in which case it doesn't matter
6002 because we will use this equiv reg right away. */
6004 if (oldequiv == 0 && optimize
6005 && (GET_CODE (old) == MEM
6006 || (GET_CODE (old) == REG
6007 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6008 && reg_renumber[REGNO (old)] < 0)))
6009 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6010 -1, NULL_PTR, 0, mode);
6014 unsigned int regno = true_regnum (oldequiv);
6016 /* Don't use OLDEQUIV if any other reload changes it at an
6017 earlier stage of this insn or at this stage. */
6018 if (! reload_reg_free_for_value_p (regno, rl->opnum,
6020 rl->in, const0_rtx, j,
6024 /* If it is no cheaper to copy from OLDEQUIV into the
6025 reload register than it would be to move from memory,
6026 don't use it. Likewise, if we need a secondary register
6030 && ((REGNO_REG_CLASS (regno) != rl->class
6031 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
6033 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6034 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6035 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6039 #ifdef SECONDARY_MEMORY_NEEDED
6040 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6048 /* delete_output_reload is only invoked properly if old contains
6049 the original pseudo register. Since this is replaced with a
6050 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6051 find the pseudo in RELOAD_IN_REG. */
6053 && reload_override_in[j]
6054 && GET_CODE (rl->in_reg) == REG)
6061 else if (GET_CODE (oldequiv) == REG)
6062 oldequiv_reg = oldequiv;
6063 else if (GET_CODE (oldequiv) == SUBREG)
6064 oldequiv_reg = SUBREG_REG (oldequiv);
6066 /* If we are reloading from a register that was recently stored in
6067 with an output-reload, see if we can prove there was
6068 actually no need to store the old value in it. */
6070 if (optimize && GET_CODE (oldequiv) == REG
6071 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6072 && spill_reg_store[REGNO (oldequiv)]
6073 && GET_CODE (old) == REG
6074 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6075 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6077 delete_output_reload (insn, j, REGNO (oldequiv));
6079 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6080 then load RELOADREG from OLDEQUIV. Note that we cannot use
6081 gen_lowpart_common since it can do the wrong thing when
6082 RELOADREG has a multi-word mode. Note that RELOADREG
6083 must always be a REG here. */
6085 if (GET_MODE (reloadreg) != mode)
6086 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6087 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6088 oldequiv = SUBREG_REG (oldequiv);
6089 if (GET_MODE (oldequiv) != VOIDmode
6090 && mode != GET_MODE (oldequiv))
6091 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6093 /* Switch to the right place to emit the reload insns. */
6094 switch (rl->when_needed)
6097 where = &other_input_reload_insns;
6099 case RELOAD_FOR_INPUT:
6100 where = &input_reload_insns[rl->opnum];
6102 case RELOAD_FOR_INPUT_ADDRESS:
6103 where = &input_address_reload_insns[rl->opnum];
6105 case RELOAD_FOR_INPADDR_ADDRESS:
6106 where = &inpaddr_address_reload_insns[rl->opnum];
6108 case RELOAD_FOR_OUTPUT_ADDRESS:
6109 where = &output_address_reload_insns[rl->opnum];
6111 case RELOAD_FOR_OUTADDR_ADDRESS:
6112 where = &outaddr_address_reload_insns[rl->opnum];
6114 case RELOAD_FOR_OPERAND_ADDRESS:
6115 where = &operand_reload_insns;
6117 case RELOAD_FOR_OPADDR_ADDR:
6118 where = &other_operand_reload_insns;
6120 case RELOAD_FOR_OTHER_ADDRESS:
6121 where = &other_input_address_reload_insns;
6127 push_to_sequence (*where);
6129 /* Auto-increment addresses must be reloaded in a special way. */
6130 if (rl->out && ! rl->out_reg)
6132 /* We are not going to bother supporting the case where a
6133 incremented register can't be copied directly from
6134 OLDEQUIV since this seems highly unlikely. */
6135 if (rl->secondary_in_reload >= 0)
6138 if (reload_inherited[j])
6139 oldequiv = reloadreg;
6141 old = XEXP (rl->in_reg, 0);
6143 if (optimize && GET_CODE (oldequiv) == REG
6144 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6145 && spill_reg_store[REGNO (oldequiv)]
6146 && GET_CODE (old) == REG
6147 && (dead_or_set_p (insn,
6148 spill_reg_stored_to[REGNO (oldequiv)])
6149 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6151 delete_output_reload (insn, j, REGNO (oldequiv));
6153 /* Prevent normal processing of this reload. */
6155 /* Output a special code sequence for this case. */
6156 new_spill_reg_store[REGNO (reloadreg)]
6157 = inc_for_reload (reloadreg, oldequiv, rl->out,
6161 /* If we are reloading a pseudo-register that was set by the previous
6162 insn, see if we can get rid of that pseudo-register entirely
6163 by redirecting the previous insn into our reload register. */
6165 else if (optimize && GET_CODE (old) == REG
6166 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6167 && dead_or_set_p (insn, old)
6168 /* This is unsafe if some other reload
6169 uses the same reg first. */
6170 && reload_reg_free_for_value_p (REGNO (reloadreg),
6176 rtx temp = PREV_INSN (insn);
6177 while (temp && GET_CODE (temp) == NOTE)
6178 temp = PREV_INSN (temp);
6180 && GET_CODE (temp) == INSN
6181 && GET_CODE (PATTERN (temp)) == SET
6182 && SET_DEST (PATTERN (temp)) == old
6183 /* Make sure we can access insn_operand_constraint. */
6184 && asm_noperands (PATTERN (temp)) < 0
6185 /* This is unsafe if prev insn rejects our reload reg. */
6186 && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint,
6188 /* This is unsafe if operand occurs more than once in current
6189 insn. Perhaps some occurrences aren't reloaded. */
6190 && count_occurrences (PATTERN (insn), old, 0) == 1
6191 /* Don't risk splitting a matching pair of operands. */
6192 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6194 /* Store into the reload register instead of the pseudo. */
6195 SET_DEST (PATTERN (temp)) = reloadreg;
6197 /* If the previous insn is an output reload, the source is
6198 a reload register, and its spill_reg_store entry will
6199 contain the previous destination. This is now
6201 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6202 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6204 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6205 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6208 /* If these are the only uses of the pseudo reg,
6209 pretend for GDB it lives in the reload reg we used. */
6210 if (REG_N_DEATHS (REGNO (old)) == 1
6211 && REG_N_SETS (REGNO (old)) == 1)
6213 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6214 alter_reg (REGNO (old), -1);
6220 /* We can't do that, so output an insn to load RELOADREG. */
6222 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6223 /* If we have a secondary reload, pick up the secondary register
6224 and icode, if any. If OLDEQUIV and OLD are different or
6225 if this is an in-out reload, recompute whether or not we
6226 still need a secondary register and what the icode should
6227 be. If we still need a secondary register and the class or
6228 icode is different, go back to reloading from OLD if using
6229 OLDEQUIV means that we got the wrong type of register. We
6230 cannot have different class or icode due to an in-out reload
6231 because we don't make such reloads when both the input and
6232 output need secondary reload registers. */
6234 if (! special && rl->secondary_in_reload >= 0)
6236 rtx second_reload_reg = 0;
6237 int secondary_reload = rl->secondary_in_reload;
6238 rtx real_oldequiv = oldequiv;
6241 enum insn_code icode;
6243 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6244 and similarly for OLD.
6245 See comments in get_secondary_reload in reload.c. */
6246 /* If it is a pseudo that cannot be replaced with its
6247 equivalent MEM, we must fall back to reload_in, which
6248 will have all the necessary substitutions registered.
6249 Likewise for a pseudo that can't be replaced with its
6250 equivalent constant.
6252 Take extra care for subregs of such pseudos. Note that
6253 we cannot use reg_equiv_mem in this case because it is
6254 not in the right mode. */
6257 if (GET_CODE (tmp) == SUBREG)
6258 tmp = SUBREG_REG (tmp);
6259 if (GET_CODE (tmp) == REG
6260 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6261 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6262 || reg_equiv_constant[REGNO (tmp)] != 0))
6264 if (! reg_equiv_mem[REGNO (tmp)]
6265 || num_not_at_initial_offset
6266 || GET_CODE (oldequiv) == SUBREG)
6267 real_oldequiv = rl->in;
6269 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6273 if (GET_CODE (tmp) == SUBREG)
6274 tmp = SUBREG_REG (tmp);
6275 if (GET_CODE (tmp) == REG
6276 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6277 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6278 || reg_equiv_constant[REGNO (tmp)] != 0))
6280 if (! reg_equiv_mem[REGNO (tmp)]
6281 || num_not_at_initial_offset
6282 || GET_CODE (old) == SUBREG)
6285 real_old = reg_equiv_mem[REGNO (tmp)];
6288 second_reload_reg = rld[secondary_reload].reg_rtx;
6289 icode = rl->secondary_in_icode;
6291 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6292 || (rl->in != 0 && rl->out != 0))
6294 enum reg_class new_class
6295 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6296 mode, real_oldequiv);
6298 if (new_class == NO_REGS)
6299 second_reload_reg = 0;
6302 enum insn_code new_icode;
6303 enum machine_mode new_mode;
6305 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6306 REGNO (second_reload_reg)))
6307 oldequiv = old, real_oldequiv = real_old;
6310 new_icode = reload_in_optab[(int) mode];
6311 if (new_icode != CODE_FOR_nothing
6312 && ((insn_data[(int) new_icode].operand[0].predicate
6313 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6315 || (insn_data[(int) new_icode].operand[1].predicate
6316 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6317 (real_oldequiv, mode)))))
6318 new_icode = CODE_FOR_nothing;
6320 if (new_icode == CODE_FOR_nothing)
6323 new_mode = insn_data[(int) new_icode].operand[2].mode;
6325 if (GET_MODE (second_reload_reg) != new_mode)
6327 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6329 oldequiv = old, real_oldequiv = real_old;
6332 = gen_rtx_REG (new_mode,
6333 REGNO (second_reload_reg));
6339 /* If we still need a secondary reload register, check
6340 to see if it is being used as a scratch or intermediate
6341 register and generate code appropriately. If we need
6342 a scratch register, use REAL_OLDEQUIV since the form of
6343 the insn may depend on the actual address if it is
6346 if (second_reload_reg)
6348 if (icode != CODE_FOR_nothing)
6350 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6351 second_reload_reg));
6356 /* See if we need a scratch register to load the
6357 intermediate register (a tertiary reload). */
6358 enum insn_code tertiary_icode
6359 = rld[secondary_reload].secondary_in_icode;
6361 if (tertiary_icode != CODE_FOR_nothing)
6363 rtx third_reload_reg
6364 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6366 emit_insn ((GEN_FCN (tertiary_icode)
6367 (second_reload_reg, real_oldequiv,
6368 third_reload_reg)));
6371 gen_reload (second_reload_reg, real_oldequiv,
6375 oldequiv = second_reload_reg;
6381 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6383 rtx real_oldequiv = oldequiv;
6385 if ((GET_CODE (oldequiv) == REG
6386 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6387 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6388 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6389 || (GET_CODE (oldequiv) == SUBREG
6390 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6391 && (REGNO (SUBREG_REG (oldequiv))
6392 >= FIRST_PSEUDO_REGISTER)
6393 && ((reg_equiv_memory_loc
6394 [REGNO (SUBREG_REG (oldequiv))] != 0)
6395 || (reg_equiv_constant
6396 [REGNO (SUBREG_REG (oldequiv))] != 0))))
6397 real_oldequiv = rl->in;
6398 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6402 /* End this sequence. */
6403 *where = get_insns ();
6406 /* Update reload_override_in so that delete_address_reloads_1
6407 can see the actual register usage. */
6409 reload_override_in[j] = oldequiv;
6412 /* Generate insns to for the output reload RL, which is for the insn described
6413 by CHAIN and has the number J. */
6415 emit_output_reload_insns (chain, rl, j)
6416 struct insn_chain *chain;
6420 rtx reloadreg = rl->reg_rtx;
6421 rtx insn = chain->insn;
6424 enum machine_mode mode = GET_MODE (old);
6427 if (rl->when_needed == RELOAD_OTHER)
6430 push_to_sequence (output_reload_insns[rl->opnum]);
6432 /* Determine the mode to reload in.
6433 See comments above (for input reloading). */
6435 if (mode == VOIDmode)
6437 /* VOIDmode should never happen for an output. */
6438 if (asm_noperands (PATTERN (insn)) < 0)
6439 /* It's the compiler's fault. */
6440 fatal_insn ("VOIDmode on an output", insn);
6441 error_for_asm (insn, "output operand is constant in `asm'");
6442 /* Prevent crash--use something we know is valid. */
6444 old = gen_rtx_REG (mode, REGNO (reloadreg));
6447 if (GET_MODE (reloadreg) != mode)
6448 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6450 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6452 /* If we need two reload regs, set RELOADREG to the intermediate
6453 one, since it will be stored into OLD. We might need a secondary
6454 register only for an input reload, so check again here. */
6456 if (rl->secondary_out_reload >= 0)
6460 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6461 && reg_equiv_mem[REGNO (old)] != 0)
6462 real_old = reg_equiv_mem[REGNO (old)];
6464 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6468 rtx second_reloadreg = reloadreg;
6469 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6471 /* See if RELOADREG is to be used as a scratch register
6472 or as an intermediate register. */
6473 if (rl->secondary_out_icode != CODE_FOR_nothing)
6475 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6476 (real_old, second_reloadreg, reloadreg)));
6481 /* See if we need both a scratch and intermediate reload
6484 int secondary_reload = rl->secondary_out_reload;
6485 enum insn_code tertiary_icode
6486 = rld[secondary_reload].secondary_out_icode;
6488 if (GET_MODE (reloadreg) != mode)
6489 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6491 if (tertiary_icode != CODE_FOR_nothing)
6494 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6497 /* Copy primary reload reg to secondary reload reg.
6498 (Note that these have been swapped above, then
6499 secondary reload reg to OLD using our insn. */
6501 /* If REAL_OLD is a paradoxical SUBREG, remove it
6502 and try to put the opposite SUBREG on
6504 if (GET_CODE (real_old) == SUBREG
6505 && (GET_MODE_SIZE (GET_MODE (real_old))
6506 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6507 && 0 != (tem = gen_lowpart_common
6508 (GET_MODE (SUBREG_REG (real_old)),
6510 real_old = SUBREG_REG (real_old), reloadreg = tem;
6512 gen_reload (reloadreg, second_reloadreg,
6513 rl->opnum, rl->when_needed);
6514 emit_insn ((GEN_FCN (tertiary_icode)
6515 (real_old, reloadreg, third_reloadreg)));
6520 /* Copy between the reload regs here and then to
6523 gen_reload (reloadreg, second_reloadreg,
6524 rl->opnum, rl->when_needed);
6530 /* Output the last reload insn. */
6535 /* Don't output the last reload if OLD is not the dest of
6536 INSN and is in the src and is clobbered by INSN. */
6537 if (! flag_expensive_optimizations
6538 || GET_CODE (old) != REG
6539 || !(set = single_set (insn))
6540 || rtx_equal_p (old, SET_DEST (set))
6541 || !reg_mentioned_p (old, SET_SRC (set))
6542 || !regno_clobbered_p (REGNO (old), insn))
6543 gen_reload (old, reloadreg, rl->opnum,
6547 /* Look at all insns we emitted, just to be safe. */
6548 for (p = get_insns (); p; p = NEXT_INSN (p))
6551 rtx pat = PATTERN (p);
6553 /* If this output reload doesn't come from a spill reg,
6554 clear any memory of reloaded copies of the pseudo reg.
6555 If this output reload comes from a spill reg,
6556 reg_has_output_reload will make this do nothing. */
6557 note_stores (pat, forget_old_reloads_1, NULL);
6559 if (reg_mentioned_p (rl->reg_rtx, pat))
6561 rtx set = single_set (insn);
6562 if (reload_spill_index[j] < 0
6564 && SET_SRC (set) == rl->reg_rtx)
6566 int src = REGNO (SET_SRC (set));
6568 reload_spill_index[j] = src;
6569 SET_HARD_REG_BIT (reg_is_output_reload, src);
6570 if (find_regno_note (insn, REG_DEAD, src))
6571 SET_HARD_REG_BIT (reg_reloaded_died, src);
6573 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6575 int s = rl->secondary_out_reload;
6576 set = single_set (p);
6577 /* If this reload copies only to the secondary reload
6578 register, the secondary reload does the actual
6580 if (s >= 0 && set == NULL_RTX)
6581 /* We can't tell what function the secondary reload
6582 has and where the actual store to the pseudo is
6583 made; leave new_spill_reg_store alone. */
6586 && SET_SRC (set) == rl->reg_rtx
6587 && SET_DEST (set) == rld[s].reg_rtx)
6589 /* Usually the next instruction will be the
6590 secondary reload insn; if we can confirm
6591 that it is, setting new_spill_reg_store to
6592 that insn will allow an extra optimization. */
6593 rtx s_reg = rld[s].reg_rtx;
6594 rtx next = NEXT_INSN (p);
6595 rld[s].out = rl->out;
6596 rld[s].out_reg = rl->out_reg;
6597 set = single_set (next);
6598 if (set && SET_SRC (set) == s_reg
6599 && ! new_spill_reg_store[REGNO (s_reg)])
6601 SET_HARD_REG_BIT (reg_is_output_reload,
6603 new_spill_reg_store[REGNO (s_reg)] = next;
6607 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6612 if (rl->when_needed == RELOAD_OTHER)
6614 emit_insns (other_output_reload_insns[rl->opnum]);
6615 other_output_reload_insns[rl->opnum] = get_insns ();
6618 output_reload_insns[rl->opnum] = get_insns ();
6623 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6624 and has the number J. */
6626 do_input_reload (chain, rl, j)
6627 struct insn_chain *chain;
6631 int expect_occurrences = 1;
6632 rtx insn = chain->insn;
6633 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6634 ? rl->in_reg : rl->in);
6637 /* AUTO_INC reloads need to be handled even if inherited. We got an
6638 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6639 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6640 && ! rtx_equal_p (rl->reg_rtx, old)
6641 && rl->reg_rtx != 0)
6642 emit_input_reload_insns (chain, rld + j, old, j);
6644 /* When inheriting a wider reload, we have a MEM in rl->in,
6645 e.g. inheriting a SImode output reload for
6646 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6647 if (optimize && reload_inherited[j] && rl->in
6648 && GET_CODE (rl->in) == MEM
6649 && GET_CODE (rl->in_reg) == MEM
6650 && reload_spill_index[j] >= 0
6651 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6654 = count_occurrences (PATTERN (insn), rl->in, 0) == 1 ? 0 : -1;
6655 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6658 /* If we are reloading a register that was recently stored in with an
6659 output-reload, see if we can prove there was
6660 actually no need to store the old value in it. */
6663 && (reload_inherited[j] || reload_override_in[j])
6665 && GET_CODE (rl->reg_rtx) == REG
6666 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6668 /* There doesn't seem to be any reason to restrict this to pseudos
6669 and doing so loses in the case where we are copying from a
6670 register of the wrong class. */
6671 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6672 >= FIRST_PSEUDO_REGISTER)
6674 /* The insn might have already some references to stackslots
6675 replaced by MEMs, while reload_out_reg still names the
6677 && (dead_or_set_p (insn,
6678 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6679 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6681 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6684 /* Do output reloading for reload RL, which is for the insn described by
6685 CHAIN and has the number J.
6686 ??? At some point we need to support handling output reloads of
6687 JUMP_INSNs or insns that set cc0. */
6689 do_output_reload (chain, rl, j)
6690 struct insn_chain *chain;
6695 rtx insn = chain->insn;
6696 /* If this is an output reload that stores something that is
6697 not loaded in this same reload, see if we can eliminate a previous
6699 rtx pseudo = rl->out_reg;
6702 && GET_CODE (pseudo) == REG
6703 && ! rtx_equal_p (rl->in_reg, pseudo)
6704 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6705 && reg_last_reload_reg[REGNO (pseudo)])
6707 int pseudo_no = REGNO (pseudo);
6708 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6710 /* We don't need to test full validity of last_regno for
6711 inherit here; we only want to know if the store actually
6712 matches the pseudo. */
6713 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6714 && reg_reloaded_contents[last_regno] == pseudo_no
6715 && spill_reg_store[last_regno]
6716 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6717 delete_output_reload (insn, j, last_regno);
6722 || rl->reg_rtx == old
6723 || rl->reg_rtx == 0)
6726 /* An output operand that dies right away does need a reload,
6727 but need not be copied from it. Show the new location in the
6729 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6730 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6732 XEXP (note, 0) = rl->reg_rtx;
6735 /* Likewise for a SUBREG of an operand that dies. */
6736 else if (GET_CODE (old) == SUBREG
6737 && GET_CODE (SUBREG_REG (old)) == REG
6738 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6741 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6745 else if (GET_CODE (old) == SCRATCH)
6746 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6747 but we don't want to make an output reload. */
6750 /* If is a JUMP_INSN, we can't support output reloads yet. */
6751 if (GET_CODE (insn) == JUMP_INSN)
6754 emit_output_reload_insns (chain, rld + j, j);
6757 /* Output insns to reload values in and out of the chosen reload regs. */
6760 emit_reload_insns (chain)
6761 struct insn_chain *chain;
6763 rtx insn = chain->insn;
6766 rtx following_insn = NEXT_INSN (insn);
6767 rtx before_insn = PREV_INSN (insn);
6769 CLEAR_HARD_REG_SET (reg_reloaded_died);
6771 for (j = 0; j < reload_n_operands; j++)
6772 input_reload_insns[j] = input_address_reload_insns[j]
6773 = inpaddr_address_reload_insns[j]
6774 = output_reload_insns[j] = output_address_reload_insns[j]
6775 = outaddr_address_reload_insns[j]
6776 = other_output_reload_insns[j] = 0;
6777 other_input_address_reload_insns = 0;
6778 other_input_reload_insns = 0;
6779 operand_reload_insns = 0;
6780 other_operand_reload_insns = 0;
6782 /* Dump reloads into the dump file. */
6785 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6786 debug_reload_to_stream (rtl_dump_file);
6789 /* Now output the instructions to copy the data into and out of the
6790 reload registers. Do these in the order that the reloads were reported,
6791 since reloads of base and index registers precede reloads of operands
6792 and the operands may need the base and index registers reloaded. */
6794 for (j = 0; j < n_reloads; j++)
6797 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6798 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6800 do_input_reload (chain, rld + j, j);
6801 do_output_reload (chain, rld + j, j);
6804 /* Now write all the insns we made for reloads in the order expected by
6805 the allocation functions. Prior to the insn being reloaded, we write
6806 the following reloads:
6808 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6810 RELOAD_OTHER reloads.
6812 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6813 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6814 RELOAD_FOR_INPUT reload for the operand.
6816 RELOAD_FOR_OPADDR_ADDRS reloads.
6818 RELOAD_FOR_OPERAND_ADDRESS reloads.
6820 After the insn being reloaded, we write the following:
6822 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6823 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6824 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6825 reloads for the operand. The RELOAD_OTHER output reloads are
6826 output in descending order by reload number. */
6828 emit_insns_before (other_input_address_reload_insns, insn);
6829 emit_insns_before (other_input_reload_insns, insn);
6831 for (j = 0; j < reload_n_operands; j++)
6833 emit_insns_before (inpaddr_address_reload_insns[j], insn);
6834 emit_insns_before (input_address_reload_insns[j], insn);
6835 emit_insns_before (input_reload_insns[j], insn);
6838 emit_insns_before (other_operand_reload_insns, insn);
6839 emit_insns_before (operand_reload_insns, insn);
6841 for (j = 0; j < reload_n_operands; j++)
6843 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
6844 emit_insns_before (output_address_reload_insns[j], following_insn);
6845 emit_insns_before (output_reload_insns[j], following_insn);
6846 emit_insns_before (other_output_reload_insns[j], following_insn);
6849 /* Keep basic block info up to date. */
6852 if (BLOCK_HEAD (chain->block) == insn)
6853 BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
6854 if (BLOCK_END (chain->block) == insn)
6855 BLOCK_END (chain->block) = PREV_INSN (following_insn);
6858 /* For all the spill regs newly reloaded in this instruction,
6859 record what they were reloaded from, so subsequent instructions
6860 can inherit the reloads.
6862 Update spill_reg_store for the reloads of this insn.
6863 Copy the elements that were updated in the loop above. */
6865 for (j = 0; j < n_reloads; j++)
6867 register int r = reload_order[j];
6868 register int i = reload_spill_index[r];
6870 /* If this is a non-inherited input reload from a pseudo, we must
6871 clear any memory of a previous store to the same pseudo. Only do
6872 something if there will not be an output reload for the pseudo
6874 if (rld[r].in_reg != 0
6875 && ! (reload_inherited[r] || reload_override_in[r]))
6877 rtx reg = rld[r].in_reg;
6879 if (GET_CODE (reg) == SUBREG)
6880 reg = SUBREG_REG (reg);
6882 if (GET_CODE (reg) == REG
6883 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
6884 && ! reg_has_output_reload[REGNO (reg)])
6886 int nregno = REGNO (reg);
6888 if (reg_last_reload_reg[nregno])
6890 int last_regno = REGNO (reg_last_reload_reg[nregno]);
6892 if (reg_reloaded_contents[last_regno] == nregno)
6893 spill_reg_store[last_regno] = 0;
6898 /* I is nonneg if this reload used a register.
6899 If rld[r].reg_rtx is 0, this is an optional reload
6900 that we opted to ignore. */
6902 if (i >= 0 && rld[r].reg_rtx != 0)
6904 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
6906 int part_reaches_end = 0;
6907 int all_reaches_end = 1;
6909 /* For a multi register reload, we need to check if all or part
6910 of the value lives to the end. */
6911 for (k = 0; k < nr; k++)
6913 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
6914 rld[r].when_needed))
6915 part_reaches_end = 1;
6917 all_reaches_end = 0;
6920 /* Ignore reloads that don't reach the end of the insn in
6922 if (all_reaches_end)
6924 /* First, clear out memory of what used to be in this spill reg.
6925 If consecutive registers are used, clear them all. */
6927 for (k = 0; k < nr; k++)
6928 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
6930 /* Maybe the spill reg contains a copy of reload_out. */
6932 && (GET_CODE (rld[r].out) == REG
6936 || GET_CODE (rld[r].out_reg) == REG))
6938 rtx out = (GET_CODE (rld[r].out) == REG
6942 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
6943 register int nregno = REGNO (out);
6944 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6945 : HARD_REGNO_NREGS (nregno,
6946 GET_MODE (rld[r].reg_rtx)));
6948 spill_reg_store[i] = new_spill_reg_store[i];
6949 spill_reg_stored_to[i] = out;
6950 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
6952 /* If NREGNO is a hard register, it may occupy more than
6953 one register. If it does, say what is in the
6954 rest of the registers assuming that both registers
6955 agree on how many words the object takes. If not,
6956 invalidate the subsequent registers. */
6958 if (nregno < FIRST_PSEUDO_REGISTER)
6959 for (k = 1; k < nnr; k++)
6960 reg_last_reload_reg[nregno + k]
6962 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
6963 REGNO (rld[r].reg_rtx) + k)
6966 /* Now do the inverse operation. */
6967 for (k = 0; k < nr; k++)
6969 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
6970 reg_reloaded_contents[i + k]
6971 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
6974 reg_reloaded_insn[i + k] = insn;
6975 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
6979 /* Maybe the spill reg contains a copy of reload_in. Only do
6980 something if there will not be an output reload for
6981 the register being reloaded. */
6982 else if (rld[r].out_reg == 0
6984 && ((GET_CODE (rld[r].in) == REG
6985 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
6986 && ! reg_has_output_reload[REGNO (rld[r].in)])
6987 || (GET_CODE (rld[r].in_reg) == REG
6988 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
6989 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
6991 register int nregno;
6994 if (GET_CODE (rld[r].in) == REG
6995 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
6996 nregno = REGNO (rld[r].in);
6997 else if (GET_CODE (rld[r].in_reg) == REG)
6998 nregno = REGNO (rld[r].in_reg);
7000 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7002 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7003 : HARD_REGNO_NREGS (nregno,
7004 GET_MODE (rld[r].reg_rtx)));
7006 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7008 if (nregno < FIRST_PSEUDO_REGISTER)
7009 for (k = 1; k < nnr; k++)
7010 reg_last_reload_reg[nregno + k]
7012 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7013 REGNO (rld[r].reg_rtx) + k)
7016 /* Unless we inherited this reload, show we haven't
7017 recently done a store.
7018 Previous stores of inherited auto_inc expressions
7019 also have to be discarded. */
7020 if (! reload_inherited[r]
7021 || (rld[r].out && ! rld[r].out_reg))
7022 spill_reg_store[i] = 0;
7024 for (k = 0; k < nr; k++)
7026 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7027 reg_reloaded_contents[i + k]
7028 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7031 reg_reloaded_insn[i + k] = insn;
7032 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7037 /* However, if part of the reload reaches the end, then we must
7038 invalidate the old info for the part that survives to the end. */
7039 else if (part_reaches_end)
7041 for (k = 0; k < nr; k++)
7042 if (reload_reg_reaches_end_p (i + k,
7044 rld[r].when_needed))
7045 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7049 /* The following if-statement was #if 0'd in 1.34 (or before...).
7050 It's reenabled in 1.35 because supposedly nothing else
7051 deals with this problem. */
7053 /* If a register gets output-reloaded from a non-spill register,
7054 that invalidates any previous reloaded copy of it.
7055 But forget_old_reloads_1 won't get to see it, because
7056 it thinks only about the original insn. So invalidate it here. */
7057 if (i < 0 && rld[r].out != 0
7058 && (GET_CODE (rld[r].out) == REG
7059 || (GET_CODE (rld[r].out) == MEM
7060 && GET_CODE (rld[r].out_reg) == REG)))
7062 rtx out = (GET_CODE (rld[r].out) == REG
7063 ? rld[r].out : rld[r].out_reg);
7064 register int nregno = REGNO (out);
7065 if (nregno >= FIRST_PSEUDO_REGISTER)
7067 rtx src_reg, store_insn = NULL_RTX;
7069 reg_last_reload_reg[nregno] = 0;
7071 /* If we can find a hard register that is stored, record
7072 the storing insn so that we may delete this insn with
7073 delete_output_reload. */
7074 src_reg = rld[r].reg_rtx;
7076 /* If this is an optional reload, try to find the source reg
7077 from an input reload. */
7080 rtx set = single_set (insn);
7081 if (set && SET_DEST (set) == rld[r].out)
7085 src_reg = SET_SRC (set);
7087 for (k = 0; k < n_reloads; k++)
7089 if (rld[k].in == src_reg)
7091 src_reg = rld[k].reg_rtx;
7098 store_insn = new_spill_reg_store[REGNO (src_reg)];
7099 if (src_reg && GET_CODE (src_reg) == REG
7100 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7102 int src_regno = REGNO (src_reg);
7103 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7104 /* The place where to find a death note varies with
7105 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7106 necessarily checked exactly in the code that moves
7107 notes, so just check both locations. */
7108 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7110 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7113 spill_reg_store[src_regno + nr] = store_insn;
7114 spill_reg_stored_to[src_regno + nr] = out;
7115 reg_reloaded_contents[src_regno + nr] = nregno;
7116 reg_reloaded_insn[src_regno + nr] = store_insn;
7117 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7118 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7119 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7121 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7123 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7125 reg_last_reload_reg[nregno] = src_reg;
7130 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7132 while (num_regs-- > 0)
7133 reg_last_reload_reg[nregno + num_regs] = 0;
7137 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7140 /* Emit code to perform a reload from IN (which may be a reload register) to
7141 OUT (which may also be a reload register). IN or OUT is from operand
7142 OPNUM with reload type TYPE.
7144 Returns first insn emitted. */
7147 gen_reload (out, in, opnum, type)
7151 enum reload_type type;
7153 rtx last = get_last_insn ();
7156 /* If IN is a paradoxical SUBREG, remove it and try to put the
7157 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7158 if (GET_CODE (in) == SUBREG
7159 && (GET_MODE_SIZE (GET_MODE (in))
7160 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7161 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7162 in = SUBREG_REG (in), out = tem;
7163 else if (GET_CODE (out) == SUBREG
7164 && (GET_MODE_SIZE (GET_MODE (out))
7165 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7166 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7167 out = SUBREG_REG (out), in = tem;
7169 /* How to do this reload can get quite tricky. Normally, we are being
7170 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7171 register that didn't get a hard register. In that case we can just
7172 call emit_move_insn.
7174 We can also be asked to reload a PLUS that adds a register or a MEM to
7175 another register, constant or MEM. This can occur during frame pointer
7176 elimination and while reloading addresses. This case is handled by
7177 trying to emit a single insn to perform the add. If it is not valid,
7178 we use a two insn sequence.
7180 Finally, we could be called to handle an 'o' constraint by putting
7181 an address into a register. In that case, we first try to do this
7182 with a named pattern of "reload_load_address". If no such pattern
7183 exists, we just emit a SET insn and hope for the best (it will normally
7184 be valid on machines that use 'o').
7186 This entire process is made complex because reload will never
7187 process the insns we generate here and so we must ensure that
7188 they will fit their constraints and also by the fact that parts of
7189 IN might be being reloaded separately and replaced with spill registers.
7190 Because of this, we are, in some sense, just guessing the right approach
7191 here. The one listed above seems to work.
7193 ??? At some point, this whole thing needs to be rethought. */
7195 if (GET_CODE (in) == PLUS
7196 && (GET_CODE (XEXP (in, 0)) == REG
7197 || GET_CODE (XEXP (in, 0)) == SUBREG
7198 || GET_CODE (XEXP (in, 0)) == MEM)
7199 && (GET_CODE (XEXP (in, 1)) == REG
7200 || GET_CODE (XEXP (in, 1)) == SUBREG
7201 || CONSTANT_P (XEXP (in, 1))
7202 || GET_CODE (XEXP (in, 1)) == MEM))
7204 /* We need to compute the sum of a register or a MEM and another
7205 register, constant, or MEM, and put it into the reload
7206 register. The best possible way of doing this is if the machine
7207 has a three-operand ADD insn that accepts the required operands.
7209 The simplest approach is to try to generate such an insn and see if it
7210 is recognized and matches its constraints. If so, it can be used.
7212 It might be better not to actually emit the insn unless it is valid,
7213 but we need to pass the insn as an operand to `recog' and
7214 `extract_insn' and it is simpler to emit and then delete the insn if
7215 not valid than to dummy things up. */
7217 rtx op0, op1, tem, insn;
7220 op0 = find_replacement (&XEXP (in, 0));
7221 op1 = find_replacement (&XEXP (in, 1));
7223 /* Since constraint checking is strict, commutativity won't be
7224 checked, so we need to do that here to avoid spurious failure
7225 if the add instruction is two-address and the second operand
7226 of the add is the same as the reload reg, which is frequently
7227 the case. If the insn would be A = B + A, rearrange it so
7228 it will be A = A + B as constrain_operands expects. */
7230 if (GET_CODE (XEXP (in, 1)) == REG
7231 && REGNO (out) == REGNO (XEXP (in, 1)))
7232 tem = op0, op0 = op1, op1 = tem;
7234 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7235 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7237 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7238 code = recog_memoized (insn);
7242 extract_insn (insn);
7243 /* We want constrain operands to treat this insn strictly in
7244 its validity determination, i.e., the way it would after reload
7246 if (constrain_operands (1))
7250 delete_insns_since (last);
7252 /* If that failed, we must use a conservative two-insn sequence.
7254 Use a move to copy one operand into the reload register. Prefer
7255 to reload a constant, MEM or pseudo since the move patterns can
7256 handle an arbitrary operand. If OP1 is not a constant, MEM or
7257 pseudo and OP1 is not a valid operand for an add instruction, then
7260 After reloading one of the operands into the reload register, add
7261 the reload register to the output register.
7263 If there is another way to do this for a specific machine, a
7264 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7267 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7269 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7270 || (GET_CODE (op1) == REG
7271 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7272 || (code != CODE_FOR_nothing
7273 && ! ((*insn_data[code].operand[2].predicate)
7274 (op1, insn_data[code].operand[2].mode))))
7275 tem = op0, op0 = op1, op1 = tem;
7277 gen_reload (out, op0, opnum, type);
7279 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7280 This fixes a problem on the 32K where the stack pointer cannot
7281 be used as an operand of an add insn. */
7283 if (rtx_equal_p (op0, op1))
7286 insn = emit_insn (gen_add2_insn (out, op1));
7288 /* If that failed, copy the address register to the reload register.
7289 Then add the constant to the reload register. */
7291 code = recog_memoized (insn);
7295 extract_insn (insn);
7296 /* We want constrain operands to treat this insn strictly in
7297 its validity determination, i.e., the way it would after reload
7299 if (constrain_operands (1))
7301 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7303 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7308 delete_insns_since (last);
7310 gen_reload (out, op1, opnum, type);
7311 insn = emit_insn (gen_add2_insn (out, op0));
7312 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7315 #ifdef SECONDARY_MEMORY_NEEDED
7316 /* If we need a memory location to do the move, do it that way. */
7317 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7318 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7319 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7320 REGNO_REG_CLASS (REGNO (out)),
7323 /* Get the memory to use and rewrite both registers to its mode. */
7324 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7326 if (GET_MODE (loc) != GET_MODE (out))
7327 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7329 if (GET_MODE (loc) != GET_MODE (in))
7330 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7332 gen_reload (loc, in, opnum, type);
7333 gen_reload (out, loc, opnum, type);
7337 /* If IN is a simple operand, use gen_move_insn. */
7338 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7339 emit_insn (gen_move_insn (out, in));
7341 #ifdef HAVE_reload_load_address
7342 else if (HAVE_reload_load_address)
7343 emit_insn (gen_reload_load_address (out, in));
7346 /* Otherwise, just write (set OUT IN) and hope for the best. */
7348 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7350 /* Return the first insn emitted.
7351 We can not just return get_last_insn, because there may have
7352 been multiple instructions emitted. Also note that gen_move_insn may
7353 emit more than one insn itself, so we can not assume that there is one
7354 insn emitted per emit_insn_before call. */
7356 return last ? NEXT_INSN (last) : get_insns ();
7359 /* Delete a previously made output-reload
7360 whose result we now believe is not needed.
7361 First we double-check.
7363 INSN is the insn now being processed.
7364 LAST_RELOAD_REG is the hard register number for which we want to delete
7365 the last output reload.
7366 J is the reload-number that originally used REG. The caller has made
7367 certain that reload J doesn't use REG any longer for input. */
7370 delete_output_reload (insn, j, last_reload_reg)
7373 int last_reload_reg;
7375 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7376 rtx reg = spill_reg_stored_to[last_reload_reg];
7379 int n_inherited = 0;
7383 /* Get the raw pseudo-register referred to. */
7385 while (GET_CODE (reg) == SUBREG)
7386 reg = SUBREG_REG (reg);
7387 substed = reg_equiv_memory_loc[REGNO (reg)];
7389 /* This is unsafe if the operand occurs more often in the current
7390 insn than it is inherited. */
7391 for (k = n_reloads - 1; k >= 0; k--)
7393 rtx reg2 = rld[k].in;
7396 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7397 reg2 = rld[k].in_reg;
7399 if (rld[k].out && ! rld[k].out_reg)
7400 reg2 = XEXP (rld[k].in_reg, 0);
7402 while (GET_CODE (reg2) == SUBREG)
7403 reg2 = SUBREG_REG (reg2);
7404 if (rtx_equal_p (reg2, reg))
7406 if (reload_inherited[k] || reload_override_in[k] || k == j)
7409 reg2 = rld[k].out_reg;
7412 while (GET_CODE (reg2) == SUBREG)
7413 reg2 = XEXP (reg2, 0);
7414 if (rtx_equal_p (reg2, reg))
7421 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7423 n_occurrences += count_occurrences (PATTERN (insn), substed, 0);
7424 if (n_occurrences > n_inherited)
7427 /* If the pseudo-reg we are reloading is no longer referenced
7428 anywhere between the store into it and here,
7429 and no jumps or labels intervene, then the value can get
7430 here through the reload reg alone.
7431 Otherwise, give up--return. */
7432 for (i1 = NEXT_INSN (output_reload_insn);
7433 i1 != insn; i1 = NEXT_INSN (i1))
7435 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7437 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7438 && reg_mentioned_p (reg, PATTERN (i1)))
7440 /* If this is USE in front of INSN, we only have to check that
7441 there are no more references than accounted for by inheritance. */
7442 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7444 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7445 i1 = NEXT_INSN (i1);
7447 if (n_occurrences <= n_inherited && i1 == insn)
7453 /* The caller has already checked that REG dies or is set in INSN.
7454 It has also checked that we are optimizing, and thus some inaccurancies
7455 in the debugging information are acceptable.
7456 So we could just delete output_reload_insn.
7457 But in some cases we can improve the debugging information without
7458 sacrificing optimization - maybe even improving the code:
7459 See if the pseudo reg has been completely replaced
7460 with reload regs. If so, delete the store insn
7461 and forget we had a stack slot for the pseudo. */
7462 if (rld[j].out != rld[j].in
7463 && REG_N_DEATHS (REGNO (reg)) == 1
7464 && REG_N_SETS (REGNO (reg)) == 1
7465 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7466 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7470 /* We know that it was used only between here
7471 and the beginning of the current basic block.
7472 (We also know that the last use before INSN was
7473 the output reload we are thinking of deleting, but never mind that.)
7474 Search that range; see if any ref remains. */
7475 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7477 rtx set = single_set (i2);
7479 /* Uses which just store in the pseudo don't count,
7480 since if they are the only uses, they are dead. */
7481 if (set != 0 && SET_DEST (set) == reg)
7483 if (GET_CODE (i2) == CODE_LABEL
7484 || GET_CODE (i2) == JUMP_INSN)
7486 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7487 && reg_mentioned_p (reg, PATTERN (i2)))
7489 /* Some other ref remains; just delete the output reload we
7491 delete_address_reloads (output_reload_insn, insn);
7492 PUT_CODE (output_reload_insn, NOTE);
7493 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7494 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7499 /* Delete the now-dead stores into this pseudo. */
7500 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7502 rtx set = single_set (i2);
7504 if (set != 0 && SET_DEST (set) == reg)
7506 delete_address_reloads (i2, insn);
7507 /* This might be a basic block head,
7508 thus don't use delete_insn. */
7509 PUT_CODE (i2, NOTE);
7510 NOTE_SOURCE_FILE (i2) = 0;
7511 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7513 if (GET_CODE (i2) == CODE_LABEL
7514 || GET_CODE (i2) == JUMP_INSN)
7518 /* For the debugging info,
7519 say the pseudo lives in this reload reg. */
7520 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7521 alter_reg (REGNO (reg), -1);
7523 delete_address_reloads (output_reload_insn, insn);
7524 PUT_CODE (output_reload_insn, NOTE);
7525 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7526 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7530 /* We are going to delete DEAD_INSN. Recursively delete loads of
7531 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7532 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7534 delete_address_reloads (dead_insn, current_insn)
7535 rtx dead_insn, current_insn;
7537 rtx set = single_set (dead_insn);
7538 rtx set2, dst, prev, next;
7541 rtx dst = SET_DEST (set);
7542 if (GET_CODE (dst) == MEM)
7543 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7545 /* If we deleted the store from a reloaded post_{in,de}c expression,
7546 we can delete the matching adds. */
7547 prev = PREV_INSN (dead_insn);
7548 next = NEXT_INSN (dead_insn);
7549 if (! prev || ! next)
7551 set = single_set (next);
7552 set2 = single_set (prev);
7554 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7555 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7556 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7558 dst = SET_DEST (set);
7559 if (! rtx_equal_p (dst, SET_DEST (set2))
7560 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7561 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7562 || (INTVAL (XEXP (SET_SRC (set), 1))
7563 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7569 /* Subfunction of delete_address_reloads: process registers found in X. */
7571 delete_address_reloads_1 (dead_insn, x, current_insn)
7572 rtx dead_insn, x, current_insn;
7574 rtx prev, set, dst, i2;
7576 enum rtx_code code = GET_CODE (x);
7580 const char *fmt = GET_RTX_FORMAT (code);
7581 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7584 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7585 else if (fmt[i] == 'E')
7587 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7588 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7595 if (spill_reg_order[REGNO (x)] < 0)
7598 /* Scan backwards for the insn that sets x. This might be a way back due
7600 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7602 code = GET_CODE (prev);
7603 if (code == CODE_LABEL || code == JUMP_INSN)
7605 if (GET_RTX_CLASS (code) != 'i')
7607 if (reg_set_p (x, PATTERN (prev)))
7609 if (reg_referenced_p (x, PATTERN (prev)))
7612 if (! prev || INSN_UID (prev) < reload_first_uid)
7614 /* Check that PREV only sets the reload register. */
7615 set = single_set (prev);
7618 dst = SET_DEST (set);
7619 if (GET_CODE (dst) != REG
7620 || ! rtx_equal_p (dst, x))
7622 if (! reg_set_p (dst, PATTERN (dead_insn)))
7624 /* Check if DST was used in a later insn -
7625 it might have been inherited. */
7626 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7628 if (GET_CODE (i2) == CODE_LABEL)
7632 if (reg_referenced_p (dst, PATTERN (i2)))
7634 /* If there is a reference to the register in the current insn,
7635 it might be loaded in a non-inherited reload. If no other
7636 reload uses it, that means the register is set before
7638 if (i2 == current_insn)
7640 for (j = n_reloads - 1; j >= 0; j--)
7641 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7642 || reload_override_in[j] == dst)
7644 for (j = n_reloads - 1; j >= 0; j--)
7645 if (rld[j].in && rld[j].reg_rtx == dst)
7652 if (GET_CODE (i2) == JUMP_INSN)
7654 /* If DST is still live at CURRENT_INSN, check if it is used for
7655 any reload. Note that even if CURRENT_INSN sets DST, we still
7656 have to check the reloads. */
7657 if (i2 == current_insn)
7659 for (j = n_reloads - 1; j >= 0; j--)
7660 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7661 || reload_override_in[j] == dst)
7663 /* ??? We can't finish the loop here, because dst might be
7664 allocated to a pseudo in this block if no reload in this
7665 block needs any of the clsses containing DST - see
7666 spill_hard_reg. There is no easy way to tell this, so we
7667 have to scan till the end of the basic block. */
7669 if (reg_set_p (dst, PATTERN (i2)))
7673 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7674 reg_reloaded_contents[REGNO (dst)] = -1;
7675 /* Can't use delete_insn here because PREV might be a basic block head. */
7676 PUT_CODE (prev, NOTE);
7677 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
7678 NOTE_SOURCE_FILE (prev) = 0;
7681 /* Output reload-insns to reload VALUE into RELOADREG.
7682 VALUE is an autoincrement or autodecrement RTX whose operand
7683 is a register or memory location;
7684 so reloading involves incrementing that location.
7685 IN is either identical to VALUE, or some cheaper place to reload from.
7687 INC_AMOUNT is the number to increment or decrement by (always positive).
7688 This cannot be deduced from VALUE.
7690 Return the instruction that stores into RELOADREG. */
7693 inc_for_reload (reloadreg, in, value, inc_amount)
7698 /* REG or MEM to be copied and incremented. */
7699 rtx incloc = XEXP (value, 0);
7700 /* Nonzero if increment after copying. */
7701 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7707 rtx real_in = in == value ? XEXP (in, 0) : in;
7709 /* No hard register is equivalent to this register after
7710 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7711 we could inc/dec that register as well (maybe even using it for
7712 the source), but I'm not sure it's worth worrying about. */
7713 if (GET_CODE (incloc) == REG)
7714 reg_last_reload_reg[REGNO (incloc)] = 0;
7716 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7717 inc_amount = -inc_amount;
7719 inc = GEN_INT (inc_amount);
7721 /* If this is post-increment, first copy the location to the reload reg. */
7722 if (post && real_in != reloadreg)
7723 emit_insn (gen_move_insn (reloadreg, real_in));
7727 /* See if we can directly increment INCLOC. Use a method similar to
7728 that in gen_reload. */
7730 last = get_last_insn ();
7731 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7732 gen_rtx_PLUS (GET_MODE (incloc),
7735 code = recog_memoized (add_insn);
7738 extract_insn (add_insn);
7739 if (constrain_operands (1))
7741 /* If this is a pre-increment and we have incremented the value
7742 where it lives, copy the incremented value to RELOADREG to
7743 be used as an address. */
7746 emit_insn (gen_move_insn (reloadreg, incloc));
7751 delete_insns_since (last);
7754 /* If couldn't do the increment directly, must increment in RELOADREG.
7755 The way we do this depends on whether this is pre- or post-increment.
7756 For pre-increment, copy INCLOC to the reload register, increment it
7757 there, then save back. */
7761 if (in != reloadreg)
7762 emit_insn (gen_move_insn (reloadreg, real_in));
7763 emit_insn (gen_add2_insn (reloadreg, inc));
7764 store = emit_insn (gen_move_insn (incloc, reloadreg));
7769 Because this might be a jump insn or a compare, and because RELOADREG
7770 may not be available after the insn in an input reload, we must do
7771 the incrementation before the insn being reloaded for.
7773 We have already copied IN to RELOADREG. Increment the copy in
7774 RELOADREG, save that back, then decrement RELOADREG so it has
7775 the original value. */
7777 emit_insn (gen_add2_insn (reloadreg, inc));
7778 store = emit_insn (gen_move_insn (incloc, reloadreg));
7779 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7785 /* Return 1 if we are certain that the constraint-string STRING allows
7786 the hard register REG. Return 0 if we can't be sure of this. */
7789 constraint_accepts_reg_p (string, reg)
7794 int regno = true_regnum (reg);
7797 /* Initialize for first alternative. */
7799 /* Check that each alternative contains `g' or `r'. */
7801 switch (c = *string++)
7804 /* If an alternative lacks `g' or `r', we lose. */
7807 /* If an alternative lacks `g' or `r', we lose. */
7810 /* Initialize for next alternative. */
7815 /* Any general reg wins for this alternative. */
7816 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7820 /* Any reg in specified class wins for this alternative. */
7822 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7824 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
7830 /* INSN is a no-op; delete it.
7831 If this sets the return value of the function, we must keep a USE around,
7832 in case this is in a different basic block than the final USE. Otherwise,
7833 we could loose important register lifeness information on
7834 SMALL_REGISTER_CLASSES machines, where return registers might be used as
7835 spills: subsequent passes assume that spill registers are dead at the end
7837 VALUE must be the return value in such a case, NULL otherwise. */
7839 reload_cse_delete_noop_set (insn, value)
7844 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
7845 INSN_CODE (insn) = -1;
7846 REG_NOTES (insn) = NULL_RTX;
7850 PUT_CODE (insn, NOTE);
7851 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
7852 NOTE_SOURCE_FILE (insn) = 0;
7856 /* See whether a single set SET is a noop. */
7858 reload_cse_noop_set_p (set)
7861 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
7864 /* Try to simplify INSN. */
7866 reload_cse_simplify (insn)
7869 rtx body = PATTERN (insn);
7871 if (GET_CODE (body) == SET)
7874 if (reload_cse_noop_set_p (body))
7876 rtx value = SET_DEST (body);
7877 if (! REG_FUNCTION_VALUE_P (SET_DEST (body)))
7879 reload_cse_delete_noop_set (insn, value);
7883 /* It's not a no-op, but we can try to simplify it. */
7884 count += reload_cse_simplify_set (body, insn);
7887 apply_change_group ();
7889 reload_cse_simplify_operands (insn);
7891 else if (GET_CODE (body) == PARALLEL)
7895 rtx value = NULL_RTX;
7897 /* If every action in a PARALLEL is a noop, we can delete
7898 the entire PARALLEL. */
7899 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
7901 rtx part = XVECEXP (body, 0, i);
7902 if (GET_CODE (part) == SET)
7904 if (! reload_cse_noop_set_p (part))
7906 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
7910 value = SET_DEST (part);
7913 else if (GET_CODE (part) != CLOBBER)
7919 reload_cse_delete_noop_set (insn, value);
7920 /* We're done with this insn. */
7924 /* It's not a no-op, but we can try to simplify it. */
7925 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
7926 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
7927 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
7930 apply_change_group ();
7932 reload_cse_simplify_operands (insn);
7936 /* Do a very simple CSE pass over the hard registers.
7938 This function detects no-op moves where we happened to assign two
7939 different pseudo-registers to the same hard register, and then
7940 copied one to the other. Reload will generate a useless
7941 instruction copying a register to itself.
7943 This function also detects cases where we load a value from memory
7944 into two different registers, and (if memory is more expensive than
7945 registers) changes it to simply copy the first register into the
7948 Another optimization is performed that scans the operands of each
7949 instruction to see whether the value is already available in a
7950 hard register. It then replaces the operand with the hard register
7951 if possible, much like an optional reload would. */
7954 reload_cse_regs_1 (first)
7960 init_alias_analysis ();
7962 for (insn = first; insn; insn = NEXT_INSN (insn))
7965 reload_cse_simplify (insn);
7967 cselib_process_insn (insn);
7971 end_alias_analysis ();
7975 /* Call cse / combine like post-reload optimization phases.
7976 FIRST is the first instruction. */
7978 reload_cse_regs (first)
7981 reload_cse_regs_1 (first);
7983 reload_cse_move2add (first);
7984 if (flag_expensive_optimizations)
7985 reload_cse_regs_1 (first);
7988 /* Try to simplify a single SET instruction. SET is the set pattern.
7989 INSN is the instruction it came from.
7990 This function only handles one case: if we set a register to a value
7991 which is not a register, we try to find that value in some other register
7992 and change the set into a register copy. */
7995 reload_cse_simplify_set (set, insn)
8002 enum reg_class dclass;
8005 struct elt_loc_list *l;
8007 dreg = true_regnum (SET_DEST (set));
8011 src = SET_SRC (set);
8012 if (side_effects_p (src) || true_regnum (src) >= 0)
8015 dclass = REGNO_REG_CLASS (dreg);
8017 /* If memory loads are cheaper than register copies, don't change them. */
8018 if (GET_CODE (src) == MEM)
8019 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8020 else if (CONSTANT_P (src))
8021 old_cost = rtx_cost (src, SET);
8022 else if (GET_CODE (src) == REG)
8023 old_cost = REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (src)), dclass);
8026 old_cost = rtx_cost (src, SET);
8028 val = cselib_lookup (src, VOIDmode, 0);
8031 for (l = val->locs; l; l = l->next)
8034 if (CONSTANT_P (l->loc) && ! references_value_p (l->loc, 0))
8035 this_cost = rtx_cost (l->loc, SET);
8036 else if (GET_CODE (l->loc) == REG)
8037 this_cost = REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (l->loc)),
8041 /* If equal costs, prefer registers over anything else. That tends to
8042 lead to smaller instructions on some machines. */
8043 if ((this_cost < old_cost
8044 || (this_cost == old_cost
8045 && GET_CODE (l->loc) == REG
8046 && GET_CODE (SET_SRC (set)) != REG))
8047 && validate_change (insn, &SET_SRC (set), copy_rtx (l->loc), 1))
8048 old_cost = this_cost, did_change = 1;
8054 /* Try to replace operands in INSN with equivalent values that are already
8055 in registers. This can be viewed as optional reloading.
8057 For each non-register operand in the insn, see if any hard regs are
8058 known to be equivalent to that operand. Record the alternatives which
8059 can accept these hard registers. Among all alternatives, select the
8060 ones which are better or equal to the one currently matching, where
8061 "better" is in terms of '?' and '!' constraints. Among the remaining
8062 alternatives, select the one which replaces most operands with
8066 reload_cse_simplify_operands (insn)
8071 /* For each operand, all registers that are equivalent to it. */
8072 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8074 const char *constraints[MAX_RECOG_OPERANDS];
8076 /* Vector recording how bad an alternative is. */
8077 int *alternative_reject;
8078 /* Vector recording how many registers can be introduced by choosing
8079 this alternative. */
8080 int *alternative_nregs;
8081 /* Array of vectors recording, for each operand and each alternative,
8082 which hard register to substitute, or -1 if the operand should be
8084 int *op_alt_regno[MAX_RECOG_OPERANDS];
8085 /* Array of alternatives, sorted in order of decreasing desirability. */
8086 int *alternative_order;
8087 rtx reg = gen_rtx_REG (VOIDmode, -1);
8089 extract_insn (insn);
8091 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8094 /* Figure out which alternative currently matches. */
8095 if (! constrain_operands (1))
8096 fatal_insn_not_found (insn);
8098 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8099 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8100 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8101 bzero ((char *)alternative_reject, recog_data.n_alternatives * sizeof (int));
8102 bzero ((char *)alternative_nregs, recog_data.n_alternatives * sizeof (int));
8104 /* For each operand, find out which regs are equivalent. */
8105 for (i = 0; i < recog_data.n_operands; i++)
8108 struct elt_loc_list *l;
8110 CLEAR_HARD_REG_SET (equiv_regs[i]);
8112 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8113 right, so avoid the problem here. */
8114 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL)
8117 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8121 for (l = v->locs; l; l = l->next)
8122 if (GET_CODE (l->loc) == REG)
8123 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8126 for (i = 0; i < recog_data.n_operands; i++)
8128 enum machine_mode mode;
8132 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8133 for (j = 0; j < recog_data.n_alternatives; j++)
8134 op_alt_regno[i][j] = -1;
8136 p = constraints[i] = recog_data.constraints[i];
8137 mode = recog_data.operand_mode[i];
8139 /* Add the reject values for each alternative given by the constraints
8140 for this operand. */
8148 alternative_reject[j] += 3;
8150 alternative_reject[j] += 300;
8153 /* We won't change operands which are already registers. We
8154 also don't want to modify output operands. */
8155 regno = true_regnum (recog_data.operand[i]);
8157 || constraints[i][0] == '='
8158 || constraints[i][0] == '+')
8161 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8163 int class = (int) NO_REGS;
8165 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8168 REGNO (reg) = regno;
8169 PUT_MODE (reg, mode);
8171 /* We found a register equal to this operand. Now look for all
8172 alternatives that can accept this register and have not been
8173 assigned a register they can use yet. */
8182 case '=': case '+': case '?':
8183 case '#': case '&': case '!':
8185 case '0': case '1': case '2': case '3': case '4':
8186 case '5': case '6': case '7': case '8': case '9':
8187 case 'm': case '<': case '>': case 'V': case 'o':
8188 case 'E': case 'F': case 'G': case 'H':
8189 case 's': case 'i': case 'n':
8190 case 'I': case 'J': case 'K': case 'L':
8191 case 'M': case 'N': case 'O': case 'P':
8192 #ifdef EXTRA_CONSTRAINT
8193 case 'Q': case 'R': case 'S': case 'T': case 'U':
8196 /* These don't say anything we care about. */
8200 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8205 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
8208 case ',': case '\0':
8209 /* See if REGNO fits this alternative, and set it up as the
8210 replacement register if we don't have one for this
8211 alternative yet and the operand being replaced is not
8212 a cheap CONST_INT. */
8213 if (op_alt_regno[i][j] == -1
8214 && reg_fits_class_p (reg, class, 0, mode)
8215 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8216 || (rtx_cost (recog_data.operand[i], SET)
8217 > rtx_cost (reg, SET))))
8219 alternative_nregs[j]++;
8220 op_alt_regno[i][j] = regno;
8232 /* Record all alternatives which are better or equal to the currently
8233 matching one in the alternative_order array. */
8234 for (i = j = 0; i < recog_data.n_alternatives; i++)
8235 if (alternative_reject[i] <= alternative_reject[which_alternative])
8236 alternative_order[j++] = i;
8237 recog_data.n_alternatives = j;
8239 /* Sort it. Given a small number of alternatives, a dumb algorithm
8240 won't hurt too much. */
8241 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8244 int best_reject = alternative_reject[alternative_order[i]];
8245 int best_nregs = alternative_nregs[alternative_order[i]];
8248 for (j = i + 1; j < recog_data.n_alternatives; j++)
8250 int this_reject = alternative_reject[alternative_order[j]];
8251 int this_nregs = alternative_nregs[alternative_order[j]];
8253 if (this_reject < best_reject
8254 || (this_reject == best_reject && this_nregs < best_nregs))
8257 best_reject = this_reject;
8258 best_nregs = this_nregs;
8262 tmp = alternative_order[best];
8263 alternative_order[best] = alternative_order[i];
8264 alternative_order[i] = tmp;
8267 /* Substitute the operands as determined by op_alt_regno for the best
8269 j = alternative_order[0];
8271 for (i = 0; i < recog_data.n_operands; i++)
8273 enum machine_mode mode = recog_data.operand_mode[i];
8274 if (op_alt_regno[i][j] == -1)
8277 validate_change (insn, recog_data.operand_loc[i],
8278 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8281 for (i = recog_data.n_dups - 1; i >= 0; i--)
8283 int op = recog_data.dup_num[i];
8284 enum machine_mode mode = recog_data.operand_mode[op];
8286 if (op_alt_regno[op][j] == -1)
8289 validate_change (insn, recog_data.dup_loc[i],
8290 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8293 return apply_change_group ();
8296 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8298 This code might also be useful when reload gave up on reg+reg addresssing
8299 because of clashes between the return register and INDEX_REG_CLASS. */
8301 /* The maximum number of uses of a register we can keep track of to
8302 replace them with reg+reg addressing. */
8303 #define RELOAD_COMBINE_MAX_USES 6
8305 /* INSN is the insn where a register has ben used, and USEP points to the
8306 location of the register within the rtl. */
8307 struct reg_use { rtx insn, *usep; };
8309 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8310 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8311 indicates where it becomes live again.
8312 Otherwise, USE_INDEX is the index of the last encountered use of the
8313 register (which is first among these we have seen since we scan backwards),
8314 OFFSET contains the constant offset that is added to the register in
8315 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8316 last, of these uses.
8317 STORE_RUID is always meaningful if we only want to use a value in a
8318 register in a different place: it denotes the next insn in the insn
8319 stream (i.e. the last ecountered) that sets or clobbers the register. */
8322 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8327 } reg_state[FIRST_PSEUDO_REGISTER];
8329 /* Reverse linear uid. This is increased in reload_combine while scanning
8330 the instructions from last to first. It is used to set last_label_ruid
8331 and the store_ruid / use_ruid fields in reg_state. */
8332 static int reload_combine_ruid;
8334 #define LABEL_LIVE(LABEL) \
8335 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8341 int first_index_reg = 1, last_index_reg = 0;
8344 int last_label_ruid;
8345 int min_labelno, n_labels;
8346 HARD_REG_SET ever_live_at_start, *label_live;
8348 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
8349 reload has already used it where appropriate, so there is no use in
8350 trying to generate it now. */
8351 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8354 /* To avoid wasting too much time later searching for an index register,
8355 determine the minimum and maximum index register numbers. */
8356 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8357 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
8359 if (! first_index_reg)
8360 first_index_reg = r;
8365 /* If no index register is available, we can quit now. */
8366 if (first_index_reg > last_index_reg)
8369 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8370 information is a bit fuzzy immediately after reload, but it's
8371 still good enough to determine which registers are live at a jump
8373 min_labelno = get_first_label_num ();
8374 n_labels = max_label_num () - min_labelno;
8375 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8376 CLEAR_HARD_REG_SET (ever_live_at_start);
8378 for (i = n_basic_blocks - 1; i >= 0; i--)
8380 insn = BLOCK_HEAD (i);
8381 if (GET_CODE (insn) == CODE_LABEL)
8385 REG_SET_TO_HARD_REG_SET (live,
8386 BASIC_BLOCK (i)->global_live_at_start);
8387 compute_use_by_pseudos (&live,
8388 BASIC_BLOCK (i)->global_live_at_start);
8389 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8390 IOR_HARD_REG_SET (ever_live_at_start, live);
8394 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8395 last_label_ruid = reload_combine_ruid = 0;
8396 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8398 reg_state[r].store_ruid = reload_combine_ruid;
8400 reg_state[r].use_index = -1;
8402 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8405 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8409 /* We cannot do our optimization across labels. Invalidating all the use
8410 information we have would be costly, so we just note where the label
8411 is and then later disable any optimization that would cross it. */
8412 if (GET_CODE (insn) == CODE_LABEL)
8413 last_label_ruid = reload_combine_ruid;
8414 else if (GET_CODE (insn) == BARRIER)
8415 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8416 if (! fixed_regs[r])
8417 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8419 if (! INSN_P (insn))
8422 reload_combine_ruid++;
8424 /* Look for (set (REGX) (CONST_INT))
8425 (set (REGX) (PLUS (REGX) (REGY)))
8427 ... (MEM (REGX)) ...
8429 (set (REGZ) (CONST_INT))
8431 ... (MEM (PLUS (REGZ) (REGY)))... .
8433 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8434 and that we know all uses of REGX before it dies. */
8435 set = single_set (insn);
8437 && GET_CODE (SET_DEST (set)) == REG
8438 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8439 GET_MODE (SET_DEST (set)))
8441 && GET_CODE (SET_SRC (set)) == PLUS
8442 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8443 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8444 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8446 rtx reg = SET_DEST (set);
8447 rtx plus = SET_SRC (set);
8448 rtx base = XEXP (plus, 1);
8449 rtx prev = prev_nonnote_insn (insn);
8450 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8451 unsigned int regno = REGNO (reg);
8452 rtx const_reg = NULL_RTX;
8453 rtx reg_sum = NULL_RTX;
8455 /* Now, we need an index register.
8456 We'll set index_reg to this index register, const_reg to the
8457 register that is to be loaded with the constant
8458 (denoted as REGZ in the substitution illustration above),
8459 and reg_sum to the register-register that we want to use to
8460 substitute uses of REG (typically in MEMs) with.
8461 First check REG and BASE for being index registers;
8462 we can use them even if they are not dead. */
8463 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8464 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8472 /* Otherwise, look for a free index register. Since we have
8473 checked above that neiter REG nor BASE are index registers,
8474 if we find anything at all, it will be different from these
8476 for (i = first_index_reg; i <= last_index_reg; i++)
8478 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8480 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8481 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8482 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8484 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8486 const_reg = index_reg;
8487 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8493 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8494 (REGY), i.e. BASE, is not clobbered before the last use we'll
8497 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8498 && rtx_equal_p (SET_DEST (prev_set), reg)
8499 && reg_state[regno].use_index >= 0
8500 && (reg_state[REGNO (base)].store_ruid
8501 <= reg_state[regno].use_ruid)
8506 /* Change destination register and, if necessary, the
8507 constant value in PREV, the constant loading instruction. */
8508 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8509 if (reg_state[regno].offset != const0_rtx)
8510 validate_change (prev,
8511 &SET_SRC (prev_set),
8512 GEN_INT (INTVAL (SET_SRC (prev_set))
8513 + INTVAL (reg_state[regno].offset)),
8516 /* Now for every use of REG that we have recorded, replace REG
8518 for (i = reg_state[regno].use_index;
8519 i < RELOAD_COMBINE_MAX_USES; i++)
8520 validate_change (reg_state[regno].reg_use[i].insn,
8521 reg_state[regno].reg_use[i].usep,
8524 if (apply_change_group ())
8528 /* Delete the reg-reg addition. */
8529 PUT_CODE (insn, NOTE);
8530 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8531 NOTE_SOURCE_FILE (insn) = 0;
8533 if (reg_state[regno].offset != const0_rtx)
8534 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8536 for (np = ®_NOTES (prev); *np;)
8538 if (REG_NOTE_KIND (*np) == REG_EQUAL
8539 || REG_NOTE_KIND (*np) == REG_EQUIV)
8540 *np = XEXP (*np, 1);
8542 np = &XEXP (*np, 1);
8545 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8546 reg_state[REGNO (const_reg)].store_ruid
8547 = reload_combine_ruid;
8553 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8555 if (GET_CODE (insn) == CALL_INSN)
8559 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8560 if (call_used_regs[r])
8562 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8563 reg_state[r].store_ruid = reload_combine_ruid;
8566 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8567 link = XEXP (link, 1))
8568 if (GET_CODE (XEXP (XEXP (link, 0), 0)) == REG)
8570 unsigned int regno = REGNO (XEXP (XEXP (link, 0), 0));
8572 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
8574 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8575 reg_state[regno].store_ruid = reload_combine_ruid;
8578 reg_state[regno].use_index = -1;
8582 else if (GET_CODE (insn) == JUMP_INSN
8583 && GET_CODE (PATTERN (insn)) != RETURN)
8585 /* Non-spill registers might be used at the call destination in
8586 some unknown fashion, so we have to mark the unknown use. */
8589 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8590 && JUMP_LABEL (insn))
8591 live = &LABEL_LIVE (JUMP_LABEL (insn));
8593 live = &ever_live_at_start;
8595 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8596 if (TEST_HARD_REG_BIT (*live, i))
8597 reg_state[i].use_index = -1;
8600 reload_combine_note_use (&PATTERN (insn), insn);
8601 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8603 if (REG_NOTE_KIND (note) == REG_INC
8604 && GET_CODE (XEXP (note, 0)) == REG)
8606 int regno = REGNO (XEXP (note, 0));
8608 reg_state[regno].store_ruid = reload_combine_ruid;
8609 reg_state[regno].use_index = -1;
8617 /* Check if DST is a register or a subreg of a register; if it is,
8618 update reg_state[regno].store_ruid and reg_state[regno].use_index
8619 accordingly. Called via note_stores from reload_combine. */
8622 reload_combine_note_store (dst, set, data)
8624 void *data ATTRIBUTE_UNUSED;
8628 enum machine_mode mode = GET_MODE (dst);
8630 if (GET_CODE (dst) == SUBREG)
8632 regno = SUBREG_WORD (dst);
8633 dst = SUBREG_REG (dst);
8635 if (GET_CODE (dst) != REG)
8637 regno += REGNO (dst);
8639 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8640 careful with registers / register parts that are not full words.
8642 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8643 if (GET_CODE (set) != SET
8644 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8645 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8646 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8648 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8650 reg_state[i].use_index = -1;
8651 reg_state[i].store_ruid = reload_combine_ruid;
8656 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8658 reg_state[i].store_ruid = reload_combine_ruid;
8659 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8664 /* XP points to a piece of rtl that has to be checked for any uses of
8666 *XP is the pattern of INSN, or a part of it.
8667 Called from reload_combine, and recursively by itself. */
8669 reload_combine_note_use (xp, insn)
8673 enum rtx_code code = x->code;
8676 rtx offset = const0_rtx; /* For the REG case below. */
8681 if (GET_CODE (SET_DEST (x)) == REG)
8683 reload_combine_note_use (&SET_SRC (x), insn);
8689 /* If this is the USE of a return value, we can't change it. */
8690 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8692 /* Mark the return register as used in an unknown fashion. */
8693 rtx reg = XEXP (x, 0);
8694 int regno = REGNO (reg);
8695 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8697 while (--nregs >= 0)
8698 reg_state[regno + nregs].use_index = -1;
8704 if (GET_CODE (SET_DEST (x)) == REG)
8709 /* We are interested in (plus (reg) (const_int)) . */
8710 if (GET_CODE (XEXP (x, 0)) != REG
8711 || GET_CODE (XEXP (x, 1)) != CONST_INT)
8713 offset = XEXP (x, 1);
8718 int regno = REGNO (x);
8722 /* Some spurious USEs of pseudo registers might remain.
8723 Just ignore them. */
8724 if (regno >= FIRST_PSEUDO_REGISTER)
8727 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
8729 /* We can't substitute into multi-hard-reg uses. */
8732 while (--nregs >= 0)
8733 reg_state[regno + nregs].use_index = -1;
8737 /* If this register is already used in some unknown fashion, we
8739 If we decrement the index from zero to -1, we can't store more
8740 uses, so this register becomes used in an unknown fashion. */
8741 use_index = --reg_state[regno].use_index;
8745 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
8747 /* We have found another use for a register that is already
8748 used later. Check if the offsets match; if not, mark the
8749 register as used in an unknown fashion. */
8750 if (! rtx_equal_p (offset, reg_state[regno].offset))
8752 reg_state[regno].use_index = -1;
8758 /* This is the first use of this register we have seen since we
8759 marked it as dead. */
8760 reg_state[regno].offset = offset;
8761 reg_state[regno].use_ruid = reload_combine_ruid;
8763 reg_state[regno].reg_use[use_index].insn = insn;
8764 reg_state[regno].reg_use[use_index].usep = xp;
8772 /* Recursively process the components of X. */
8773 fmt = GET_RTX_FORMAT (code);
8774 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8777 reload_combine_note_use (&XEXP (x, i), insn);
8778 else if (fmt[i] == 'E')
8780 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8781 reload_combine_note_use (&XVECEXP (x, i, j), insn);
8786 /* See if we can reduce the cost of a constant by replacing a move with
8788 /* We cannot do our optimization across labels. Invalidating all the
8789 information about register contents we have would be costly, so we
8790 use last_label_luid (local variable of reload_cse_move2add) to note
8791 where the label is and then later disable any optimization that would
8793 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
8794 reg_set_luid[n] is larger than last_label_luid[n] . */
8795 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
8797 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
8798 reg_mode[n] to be valid.
8799 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
8800 has been set to reg_offset[n] in mode reg_mode[n] .
8801 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
8802 register n has been set to the sum of reg_offset[n] and register
8803 reg_base_reg[n], calculated in mode reg_mode[n] . */
8804 static rtx reg_offset[FIRST_PSEUDO_REGISTER];
8805 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
8806 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
8808 /* move2add_luid is linearily increased while scanning the instructions
8809 from first to last. It is used to set reg_set_luid in
8810 reload_cse_move2add and move2add_note_store. */
8811 static int move2add_luid;
8813 /* Generate a CONST_INT and force it in the range of MODE. */
8816 gen_mode_int (mode, value)
8817 enum machine_mode mode;
8818 HOST_WIDE_INT value;
8820 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
8821 int width = GET_MODE_BITSIZE (mode);
8823 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
8825 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
8826 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
8827 cval |= (HOST_WIDE_INT) -1 << width;
8829 return GEN_INT (cval);
8833 reload_cse_move2add (first)
8838 int last_label_luid;
8840 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
8841 reg_set_luid[i] = 0;
8843 last_label_luid = 0;
8845 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
8849 if (GET_CODE (insn) == CODE_LABEL)
8850 last_label_luid = move2add_luid;
8851 if (! INSN_P (insn))
8853 pat = PATTERN (insn);
8854 /* For simplicity, we only perform this optimization on
8855 straightforward SETs. */
8856 if (GET_CODE (pat) == SET
8857 && GET_CODE (SET_DEST (pat)) == REG)
8859 rtx reg = SET_DEST (pat);
8860 int regno = REGNO (reg);
8861 rtx src = SET_SRC (pat);
8863 /* Check if we have valid information on the contents of this
8864 register in the mode of REG. */
8865 /* ??? We don't know how zero / sign extension is handled, hence
8866 we can't go from a narrower to a wider mode. */
8867 if (reg_set_luid[regno] > last_label_luid
8868 && ((GET_MODE_SIZE (GET_MODE (reg))
8869 == GET_MODE_SIZE (reg_mode[regno]))
8870 || ((GET_MODE_SIZE (GET_MODE (reg))
8871 <= GET_MODE_SIZE (reg_mode[regno]))
8872 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (reg)),
8873 GET_MODE_BITSIZE (reg_mode[regno]))))
8874 && GET_CODE (reg_offset[regno]) == CONST_INT)
8876 /* Try to transform (set (REGX) (CONST_INT A))
8878 (set (REGX) (CONST_INT B))
8880 (set (REGX) (CONST_INT A))
8882 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
8884 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
8888 = gen_mode_int (GET_MODE (reg),
8889 INTVAL (src) - INTVAL (reg_offset[regno]));
8890 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
8891 use (set (reg) (reg)) instead.
8892 We don't delete this insn, nor do we convert it into a
8893 note, to avoid losing register notes or the return
8894 value flag. jump2 already knowns how to get rid of
8896 if (new_src == const0_rtx)
8897 success = validate_change (insn, &SET_SRC (pat), reg, 0);
8898 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
8899 && have_add2_insn (GET_MODE (reg)))
8900 success = validate_change (insn, &PATTERN (insn),
8901 gen_add2_insn (reg, new_src), 0);
8902 reg_set_luid[regno] = move2add_luid;
8903 reg_mode[regno] = GET_MODE (reg);
8904 reg_offset[regno] = src;
8908 /* Try to transform (set (REGX) (REGY))
8909 (set (REGX) (PLUS (REGX) (CONST_INT A)))
8912 (set (REGX) (PLUS (REGX) (CONST_INT B)))
8915 (set (REGX) (PLUS (REGX) (CONST_INT A)))
8917 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
8918 else if (GET_CODE (src) == REG
8919 && reg_base_reg[regno] == (int) REGNO (src)
8920 && reg_set_luid[regno] > reg_set_luid[REGNO (src)])
8922 rtx next = next_nonnote_insn (insn);
8925 set = single_set (next);
8928 && SET_DEST (set) == reg
8929 && GET_CODE (SET_SRC (set)) == PLUS
8930 && XEXP (SET_SRC (set), 0) == reg
8931 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
8933 rtx src3 = XEXP (SET_SRC (set), 1);
8935 = gen_mode_int (GET_MODE (reg),
8937 - INTVAL (reg_offset[regno]));
8940 if (new_src == const0_rtx)
8941 /* See above why we create (set (reg) (reg)) here. */
8943 = validate_change (next, &SET_SRC (set), reg, 0);
8944 else if ((rtx_cost (new_src, PLUS)
8945 < 2 + rtx_cost (src3, SET))
8946 && have_add2_insn (GET_MODE (reg)))
8948 = validate_change (next, &PATTERN (next),
8949 gen_add2_insn (reg, new_src), 0);
8952 /* INSN might be the first insn in a basic block
8953 if the preceding insn is a conditional jump
8954 or a possible-throwing call. */
8955 PUT_CODE (insn, NOTE);
8956 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8957 NOTE_SOURCE_FILE (insn) = 0;
8960 reg_set_luid[regno] = move2add_luid;
8961 reg_mode[regno] = GET_MODE (reg);
8962 reg_offset[regno] = src3;
8969 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8971 if (REG_NOTE_KIND (note) == REG_INC
8972 && GET_CODE (XEXP (note, 0)) == REG)
8974 /* Indicate that this register has been recently written to,
8975 but the exact contents are not available. */
8976 int regno = REGNO (XEXP (note, 0));
8977 if (regno < FIRST_PSEUDO_REGISTER)
8979 reg_set_luid[regno] = move2add_luid;
8980 reg_offset[regno] = note;
8984 note_stores (PATTERN (insn), move2add_note_store, NULL);
8985 /* If this is a CALL_INSN, all call used registers are stored with
8987 if (GET_CODE (insn) == CALL_INSN)
8989 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
8991 if (call_used_regs[i])
8993 reg_set_luid[i] = move2add_luid;
8994 reg_offset[i] = insn; /* Invalidate contents. */
9001 /* SET is a SET or CLOBBER that sets DST.
9002 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9003 Called from reload_cse_move2add via note_stores. */
9006 move2add_note_store (dst, set, data)
9008 void *data ATTRIBUTE_UNUSED;
9010 unsigned int regno = 0;
9012 enum machine_mode mode = GET_MODE (dst);
9014 if (GET_CODE (dst) == SUBREG)
9016 regno = SUBREG_WORD (dst);
9017 dst = SUBREG_REG (dst);
9020 if (GET_CODE (dst) != REG)
9023 regno += REGNO (dst);
9025 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9026 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9027 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9028 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9030 rtx src = SET_SRC (set);
9032 reg_mode[regno] = mode;
9033 switch (GET_CODE (src))
9037 rtx src0 = XEXP (src, 0);
9039 if (GET_CODE (src0) == REG)
9041 if (REGNO (src0) != regno
9042 || reg_offset[regno] != const0_rtx)
9044 reg_base_reg[regno] = REGNO (src0);
9045 reg_set_luid[regno] = move2add_luid;
9048 reg_offset[regno] = XEXP (src, 1);
9052 reg_set_luid[regno] = move2add_luid;
9053 reg_offset[regno] = set; /* Invalidate contents. */
9058 reg_base_reg[regno] = REGNO (SET_SRC (set));
9059 reg_offset[regno] = const0_rtx;
9060 reg_set_luid[regno] = move2add_luid;
9064 reg_base_reg[regno] = -1;
9065 reg_offset[regno] = SET_SRC (set);
9066 reg_set_luid[regno] = move2add_luid;
9072 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9074 for (i = regno; i < endregno; i++)
9076 /* Indicate that this register has been recently written to,
9077 but the exact contents are not available. */
9078 reg_set_luid[i] = move2add_luid;
9079 reg_offset[i] = dst;
9086 add_auto_inc_notes (insn, x)
9090 enum rtx_code code = GET_CODE (x);
9094 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9097 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9101 /* Scan all the operand sub-expressions. */
9102 fmt = GET_RTX_FORMAT (code);
9103 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9106 add_auto_inc_notes (insn, XEXP (x, i));
9107 else if (fmt[i] == 'E')
9108 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9109 add_auto_inc_notes (insn, XVECEXP (x, i, j));
OSDN Git Service
