1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 88, 89, 92-97, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "insn-flags.h"
31 #include "insn-codes.h"
37 #include "basic-block.h"
42 /* This file contains the reload pass of the compiler, which is
43 run after register allocation has been done. It checks that
44 each insn is valid (operands required to be in registers really
45 are in registers of the proper class) and fixes up invalid ones
46 by copying values temporarily into registers for the insns
49 The results of register allocation are described by the vector
50 reg_renumber; the insns still contain pseudo regs, but reg_renumber
51 can be used to find which hard reg, if any, a pseudo reg is in.
53 The technique we always use is to free up a few hard regs that are
54 called ``reload regs'', and for each place where a pseudo reg
55 must be in a hard reg, copy it temporarily into one of the reload regs.
57 All the pseudos that were formerly allocated to the hard regs that
58 are now in use as reload regs must be ``spilled''. This means
59 that they go to other hard regs, or to stack slots if no other
60 available hard regs can be found. Spilling can invalidate more
61 insns, requiring additional need for reloads, so we must keep checking
62 until the process stabilizes.
64 For machines with different classes of registers, we must keep track
65 of the register class needed for each reload, and make sure that
66 we allocate enough reload registers of each class.
68 The file reload.c contains the code that checks one insn for
69 validity and reports the reloads that it needs. This file
70 is in charge of scanning the entire rtl code, accumulating the
71 reload needs, spilling, assigning reload registers to use for
72 fixing up each insn, and generating the new insns to copy values
73 into the reload registers. */
76 #ifndef REGISTER_MOVE_COST
77 #define REGISTER_MOVE_COST(x, y) 2
80 /* During reload_as_needed, element N contains a REG rtx for the hard reg
81 into which reg N has been reloaded (perhaps for a previous insn). */
82 static rtx *reg_last_reload_reg;
84 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
85 for an output reload that stores into reg N. */
86 static char *reg_has_output_reload;
88 /* Indicates which hard regs are reload-registers for an output reload
89 in the current insn. */
90 static HARD_REG_SET reg_is_output_reload;
92 /* Element N is the constant value to which pseudo reg N is equivalent,
93 or zero if pseudo reg N is not equivalent to a constant.
94 find_reloads looks at this in order to replace pseudo reg N
95 with the constant it stands for. */
96 rtx *reg_equiv_constant;
98 /* Element N is a memory location to which pseudo reg N is equivalent,
99 prior to any register elimination (such as frame pointer to stack
100 pointer). Depending on whether or not it is a valid address, this value
101 is transferred to either reg_equiv_address or reg_equiv_mem. */
102 rtx *reg_equiv_memory_loc;
104 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
105 This is used when the address is not valid as a memory address
106 (because its displacement is too big for the machine.) */
107 rtx *reg_equiv_address;
109 /* Element N is the memory slot to which pseudo reg N is equivalent,
110 or zero if pseudo reg N is not equivalent to a memory slot. */
113 /* Widest width in which each pseudo reg is referred to (via subreg). */
114 static int *reg_max_ref_width;
116 /* Element N is the insn that initialized reg N from its equivalent
117 constant or memory slot. */
118 static rtx *reg_equiv_init;
120 /* During reload_as_needed, element N contains the last pseudo regno reloaded
121 into hard register N. If that pseudo reg occupied more than one register,
122 reg_reloaded_contents points to that pseudo for each spill register in
123 use; all of these must remain set for an inheritance to occur. */
124 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
126 /* During reload_as_needed, element N contains the insn for which
127 hard register N was last used. Its contents are significant only
128 when reg_reloaded_valid is set for this register. */
129 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
131 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
132 static HARD_REG_SET reg_reloaded_valid;
133 /* Indicate if the register was dead at the end of the reload.
134 This is only valid if reg_reloaded_contents is set and valid. */
135 static HARD_REG_SET reg_reloaded_dead;
137 /* Number of spill-regs so far; number of valid elements of spill_regs. */
140 /* In parallel with spill_regs, contains REG rtx's for those regs.
141 Holds the last rtx used for any given reg, or 0 if it has never
142 been used for spilling yet. This rtx is reused, provided it has
144 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
146 /* In parallel with spill_regs, contains nonzero for a spill reg
147 that was stored after the last time it was used.
148 The precise value is the insn generated to do the store. */
149 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
151 /* This table is the inverse mapping of spill_regs:
152 indexed by hard reg number,
153 it contains the position of that reg in spill_regs,
154 or -1 for something that is not in spill_regs. */
155 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
157 /* This reg set indicates registers that may not be used for retrying global
158 allocation. The registers that may not be used include all spill registers
159 and the frame pointer (if we are using one). */
160 HARD_REG_SET forbidden_regs;
162 /* This reg set indicates registers that are not good for spill registers.
163 They will not be used to complete groups of spill registers. This includes
164 all fixed registers, registers that may be eliminated, and, if
165 SMALL_REGISTER_CLASSES is zero, registers explicitly used in the rtl.
167 (spill_reg_order prevents these registers from being used to start a
169 static HARD_REG_SET bad_spill_regs;
171 /* Describes order of use of registers for reloading
172 of spilled pseudo-registers. `spills' is the number of
173 elements that are actually valid; new ones are added at the end. */
174 static short spill_regs[FIRST_PSEUDO_REGISTER];
176 /* This reg set indicates those registers that have been used a spill
177 registers. This information is used in reorg.c, to help figure out
178 what registers are live at any point. It is assumed that all spill_regs
179 are dead at every CODE_LABEL. */
181 HARD_REG_SET used_spill_regs;
183 /* Index of last register assigned as a spill register. We allocate in
184 a round-robin fashion. */
186 static int last_spill_reg;
188 /* Describes order of preference for putting regs into spill_regs.
189 Contains the numbers of all the hard regs, in order most preferred first.
190 This order is different for each function.
191 It is set up by order_regs_for_reload.
192 Empty elements at the end contain -1. */
193 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
195 /* 1 for a hard register that appears explicitly in the rtl
196 (for example, function value registers, special registers
197 used by insns, structure value pointer registers). */
198 static char regs_explicitly_used[FIRST_PSEUDO_REGISTER];
200 /* Indicates if a register was counted against the need for
201 groups. 0 means it can count against max_nongroup instead. */
202 static HARD_REG_SET counted_for_groups;
204 /* Indicates if a register was counted against the need for
205 non-groups. 0 means it can become part of a new group.
206 During choose_reload_regs, 1 here means don't use this reg
207 as part of a group, even if it seems to be otherwise ok. */
208 static HARD_REG_SET counted_for_nongroups;
210 /* Nonzero if indirect addressing is supported on the machine; this means
211 that spilling (REG n) does not require reloading it into a register in
212 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
213 value indicates the level of indirect addressing supported, e.g., two
214 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
217 static char spill_indirect_levels;
219 /* Nonzero if indirect addressing is supported when the innermost MEM is
220 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
221 which these are valid is the same as spill_indirect_levels, above. */
223 char indirect_symref_ok;
225 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
227 char double_reg_address_ok;
229 /* Record the stack slot for each spilled hard register. */
231 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
233 /* Width allocated so far for that stack slot. */
235 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
237 /* Indexed by register class and basic block number, nonzero if there is
238 any need for a spill register of that class in that basic block.
239 The pointer is 0 if we did stupid allocation and don't know
240 the structure of basic blocks. */
242 char *basic_block_needs[N_REG_CLASSES];
244 /* First uid used by insns created by reload in this function.
245 Used in find_equiv_reg. */
246 int reload_first_uid;
248 /* Flag set by local-alloc or global-alloc if anything is live in
249 a call-clobbered reg across calls. */
251 int caller_save_needed;
253 /* The register class to use for a base register when reloading an
254 address. This is normally BASE_REG_CLASS, but it may be different
255 when using SMALL_REGISTER_CLASSES and passing parameters in
257 enum reg_class reload_address_base_reg_class;
259 /* The register class to use for an index register when reloading an
260 address. This is normally INDEX_REG_CLASS, but it may be different
261 when using SMALL_REGISTER_CLASSES and passing parameters in
263 enum reg_class reload_address_index_reg_class;
265 /* Set to 1 while reload_as_needed is operating.
266 Required by some machines to handle any generated moves differently. */
268 int reload_in_progress = 0;
270 /* These arrays record the insn_code of insns that may be needed to
271 perform input and output reloads of special objects. They provide a
272 place to pass a scratch register. */
274 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
275 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
277 /* This obstack is used for allocation of rtl during register elimination.
278 The allocated storage can be freed once find_reloads has processed the
281 struct obstack reload_obstack;
282 char *reload_firstobj;
284 #define obstack_chunk_alloc xmalloc
285 #define obstack_chunk_free free
287 /* List of labels that must never be deleted. */
288 extern rtx forced_labels;
290 /* Allocation number table from global register allocation. */
291 extern int *reg_allocno;
293 /* This structure is used to record information about register eliminations.
294 Each array entry describes one possible way of eliminating a register
295 in favor of another. If there is more than one way of eliminating a
296 particular register, the most preferred should be specified first. */
298 static struct elim_table
300 int from; /* Register number to be eliminated. */
301 int to; /* Register number used as replacement. */
302 int initial_offset; /* Initial difference between values. */
303 int can_eliminate; /* Non-zero if this elimination can be done. */
304 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
305 insns made by reload. */
306 int offset; /* Current offset between the two regs. */
307 int max_offset; /* Maximum offset between the two regs. */
308 int previous_offset; /* Offset at end of previous insn. */
309 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
310 rtx from_rtx; /* REG rtx for the register to be eliminated.
311 We cannot simply compare the number since
312 we might then spuriously replace a hard
313 register corresponding to a pseudo
314 assigned to the reg to be eliminated. */
315 rtx to_rtx; /* REG rtx for the replacement. */
318 /* If a set of eliminable registers was specified, define the table from it.
319 Otherwise, default to the normal case of the frame pointer being
320 replaced by the stack pointer. */
322 #ifdef ELIMINABLE_REGS
325 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
328 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0])
330 /* Record the number of pending eliminations that have an offset not equal
331 to their initial offset. If non-zero, we use a new copy of each
332 replacement result in any insns encountered. */
333 static int num_not_at_initial_offset;
335 /* Count the number of registers that we may be able to eliminate. */
336 static int num_eliminable;
338 /* For each label, we record the offset of each elimination. If we reach
339 a label by more than one path and an offset differs, we cannot do the
340 elimination. This information is indexed by the number of the label.
341 The first table is an array of flags that records whether we have yet
342 encountered a label and the second table is an array of arrays, one
343 entry in the latter array for each elimination. */
345 static char *offsets_known_at;
346 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
348 /* Number of labels in the current function. */
350 static int num_labels;
352 struct hard_reg_n_uses { int regno; int uses; };
354 static int possible_group_p PROTO((int, int *));
355 static void count_possible_groups PROTO((int *, enum machine_mode *,
357 static int modes_equiv_for_class_p PROTO((enum machine_mode,
360 static void spill_failure PROTO((rtx));
361 static int new_spill_reg PROTO((int, int, int *, int *, int,
363 static void delete_dead_insn PROTO((rtx));
364 static void alter_reg PROTO((int, int));
365 static void mark_scratch_live PROTO((rtx));
366 static void set_label_offsets PROTO((rtx, rtx, int));
367 static int eliminate_regs_in_insn PROTO((rtx, int));
368 static void mark_not_eliminable PROTO((rtx, rtx));
369 static int spill_hard_reg PROTO((int, int, FILE *, int));
370 static void scan_paradoxical_subregs PROTO((rtx));
371 static int hard_reg_use_compare PROTO((const GENERIC_PTR, const GENERIC_PTR));
372 static void order_regs_for_reload PROTO((int));
373 static int compare_spill_regs PROTO((const GENERIC_PTR, const GENERIC_PTR));
374 static void reload_as_needed PROTO((rtx, int));
375 static void forget_old_reloads_1 PROTO((rtx, rtx));
376 static int reload_reg_class_lower PROTO((const GENERIC_PTR, const GENERIC_PTR));
377 static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
379 static void clear_reload_reg_in_use PROTO((int, int, enum reload_type,
381 static int reload_reg_free_p PROTO((int, int, enum reload_type));
382 static int reload_reg_free_before_p PROTO((int, int, enum reload_type));
383 static int reload_reg_free_for_value_p PROTO((int, int, enum reload_type, rtx, rtx, int));
384 static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
385 static int allocate_reload_reg PROTO((int, rtx, int, int));
386 static void choose_reload_regs PROTO((rtx, rtx));
387 static void merge_assigned_reloads PROTO((rtx));
388 static void emit_reload_insns PROTO((rtx));
389 static void delete_output_reload PROTO((rtx, int, rtx));
390 static void inc_for_reload PROTO((rtx, rtx, int));
391 static int constraint_accepts_reg_p PROTO((char *, rtx));
392 static void reload_cse_invalidate_regno PROTO((int, enum machine_mode, int));
393 static int reload_cse_mem_conflict_p PROTO((rtx, rtx));
394 static void reload_cse_invalidate_mem PROTO((rtx));
395 static void reload_cse_invalidate_rtx PROTO((rtx, rtx));
396 static int reload_cse_regno_equal_p PROTO((int, rtx, enum machine_mode));
397 static int reload_cse_noop_set_p PROTO((rtx, rtx));
398 static int reload_cse_simplify_set PROTO((rtx, rtx));
399 static int reload_cse_simplify_operands PROTO((rtx));
400 static void reload_cse_check_clobber PROTO((rtx, rtx));
401 static void reload_cse_record_set PROTO((rtx, rtx));
402 static void reload_cse_delete_death_notes PROTO((rtx));
403 static void reload_cse_no_longer_dead PROTO((int, enum machine_mode));
405 /* Initialize the reload pass once per compilation. */
412 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
413 Set spill_indirect_levels to the number of levels such addressing is
414 permitted, zero if it is not permitted at all. */
417 = gen_rtx_MEM (Pmode,
419 gen_rtx_REG (Pmode, LAST_VIRTUAL_REGISTER + 1),
421 spill_indirect_levels = 0;
423 while (memory_address_p (QImode, tem))
425 spill_indirect_levels++;
426 tem = gen_rtx_MEM (Pmode, tem);
429 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
431 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
432 indirect_symref_ok = memory_address_p (QImode, tem);
434 /* See if reg+reg is a valid (and offsettable) address. */
436 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
438 tem = gen_rtx_PLUS (Pmode,
439 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
440 gen_rtx_REG (Pmode, i));
441 /* This way, we make sure that reg+reg is an offsettable address. */
442 tem = plus_constant (tem, 4);
444 if (memory_address_p (QImode, tem))
446 double_reg_address_ok = 1;
451 /* Initialize obstack for our rtl allocation. */
452 gcc_obstack_init (&reload_obstack);
453 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
455 /* Decide which register class should be used when reloading
456 addresses. If we are using SMALL_REGISTER_CLASSES, and any
457 parameters are passed in registers, then we do not want to use
458 those registers when reloading an address. Otherwise, if a
459 function argument needs a reload, we may wind up clobbering
460 another argument to the function which was already computed. If
461 we find a subset class which simply avoids those registers, we
462 use it instead. ??? It would be better to only use the
463 restricted class when we actually are loading function arguments,
464 but that is hard to determine. */
465 reload_address_base_reg_class = BASE_REG_CLASS;
466 reload_address_index_reg_class = INDEX_REG_CLASS;
467 if (SMALL_REGISTER_CLASSES)
470 HARD_REG_SET base, index;
473 COPY_HARD_REG_SET (base, reg_class_contents[BASE_REG_CLASS]);
474 COPY_HARD_REG_SET (index, reg_class_contents[INDEX_REG_CLASS]);
475 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
477 if (FUNCTION_ARG_REGNO_P (regno))
479 CLEAR_HARD_REG_BIT (base, regno);
480 CLEAR_HARD_REG_BIT (index, regno);
484 GO_IF_HARD_REG_EQUAL (base, reg_class_contents[BASE_REG_CLASS],
486 for (p = reg_class_subclasses[BASE_REG_CLASS];
487 *p != LIM_REG_CLASSES;
490 GO_IF_HARD_REG_EQUAL (base, reg_class_contents[*p], usebase);
493 reload_address_base_reg_class = *p;
498 GO_IF_HARD_REG_EQUAL (index, reg_class_contents[INDEX_REG_CLASS],
500 for (p = reg_class_subclasses[INDEX_REG_CLASS];
501 *p != LIM_REG_CLASSES;
504 GO_IF_HARD_REG_EQUAL (index, reg_class_contents[*p], useindex);
507 reload_address_index_reg_class = *p;
514 /* Main entry point for the reload pass.
516 FIRST is the first insn of the function being compiled.
518 GLOBAL nonzero means we were called from global_alloc
519 and should attempt to reallocate any pseudoregs that we
520 displace from hard regs we will use for reloads.
521 If GLOBAL is zero, we do not have enough information to do that,
522 so any pseudo reg that is spilled must go to the stack.
524 DUMPFILE is the global-reg debugging dump file stream, or 0.
525 If it is nonzero, messages are written to it to describe
526 which registers are seized as reload regs, which pseudo regs
527 are spilled from them, and where the pseudo regs are reallocated to.
529 Return value is nonzero if reload failed
530 and we must not do any more for this function. */
533 reload (first, global, dumpfile)
539 register int i, j, k;
541 register struct elim_table *ep;
543 /* The two pointers used to track the true location of the memory used
544 for label offsets. */
545 char *real_known_ptr = NULL_PTR;
546 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
548 int something_changed;
549 int something_needs_reloads;
550 int something_needs_elimination;
551 int new_basic_block_needs;
552 enum reg_class caller_save_spill_class = NO_REGS;
553 int caller_save_group_size = 1;
555 /* Nonzero means we couldn't get enough spill regs. */
558 /* The basic block number currently being processed for INSN. */
561 /* Make sure even insns with volatile mem refs are recognizable. */
564 /* Enable find_equiv_reg to distinguish insns made by reload. */
565 reload_first_uid = get_max_uid ();
567 for (i = 0; i < N_REG_CLASSES; i++)
568 basic_block_needs[i] = 0;
570 #ifdef SECONDARY_MEMORY_NEEDED
571 /* Initialize the secondary memory table. */
572 clear_secondary_mem ();
575 /* Remember which hard regs appear explicitly
576 before we merge into `regs_ever_live' the ones in which
577 pseudo regs have been allocated. */
578 bcopy (regs_ever_live, regs_explicitly_used, sizeof regs_ever_live);
580 /* We don't have a stack slot for any spill reg yet. */
581 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
582 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
584 /* Initialize the save area information for caller-save, in case some
588 /* Compute which hard registers are now in use
589 as homes for pseudo registers.
590 This is done here rather than (eg) in global_alloc
591 because this point is reached even if not optimizing. */
592 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
595 /* A function that receives a nonlocal goto must save all call-saved
597 if (current_function_has_nonlocal_label)
598 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
600 if (! call_used_regs[i] && ! fixed_regs[i])
601 regs_ever_live[i] = 1;
604 for (i = 0; i < scratch_list_length; i++)
606 mark_scratch_live (scratch_list[i]);
608 /* Make sure that the last insn in the chain
609 is not something that needs reloading. */
610 emit_note (NULL_PTR, NOTE_INSN_DELETED);
612 /* Find all the pseudo registers that didn't get hard regs
613 but do have known equivalent constants or memory slots.
614 These include parameters (known equivalent to parameter slots)
615 and cse'd or loop-moved constant memory addresses.
617 Record constant equivalents in reg_equiv_constant
618 so they will be substituted by find_reloads.
619 Record memory equivalents in reg_mem_equiv so they can
620 be substituted eventually by altering the REG-rtx's. */
622 reg_equiv_constant = (rtx *) alloca (max_regno * sizeof (rtx));
623 bzero ((char *) reg_equiv_constant, max_regno * sizeof (rtx));
624 reg_equiv_memory_loc = (rtx *) alloca (max_regno * sizeof (rtx));
625 bzero ((char *) reg_equiv_memory_loc, max_regno * sizeof (rtx));
626 reg_equiv_mem = (rtx *) alloca (max_regno * sizeof (rtx));
627 bzero ((char *) reg_equiv_mem, max_regno * sizeof (rtx));
628 reg_equiv_init = (rtx *) alloca (max_regno * sizeof (rtx));
629 bzero ((char *) reg_equiv_init, max_regno * sizeof (rtx));
630 reg_equiv_address = (rtx *) alloca (max_regno * sizeof (rtx));
631 bzero ((char *) reg_equiv_address, max_regno * sizeof (rtx));
632 reg_max_ref_width = (int *) alloca (max_regno * sizeof (int));
633 bzero ((char *) reg_max_ref_width, max_regno * sizeof (int));
635 if (SMALL_REGISTER_CLASSES)
636 CLEAR_HARD_REG_SET (forbidden_regs);
638 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
639 Also find all paradoxical subregs and find largest such for each pseudo.
640 On machines with small register classes, record hard registers that
641 are used for user variables. These can never be used for spills.
642 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
643 caller-saved registers must be marked live. */
645 for (insn = first; insn; insn = NEXT_INSN (insn))
647 rtx set = single_set (insn);
649 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
650 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
651 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
652 if (! call_used_regs[i])
653 regs_ever_live[i] = 1;
655 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
657 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
659 #ifdef LEGITIMATE_PIC_OPERAND_P
660 && (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic
661 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
665 rtx x = XEXP (note, 0);
666 i = REGNO (SET_DEST (set));
667 if (i > LAST_VIRTUAL_REGISTER)
669 if (GET_CODE (x) == MEM)
671 /* If the operand is a PLUS, the MEM may be shared,
672 so make sure we have an unshared copy here. */
673 if (GET_CODE (XEXP (x, 0)) == PLUS)
676 reg_equiv_memory_loc[i] = x;
678 else if (CONSTANT_P (x))
680 if (LEGITIMATE_CONSTANT_P (x))
681 reg_equiv_constant[i] = x;
683 reg_equiv_memory_loc[i]
684 = force_const_mem (GET_MODE (SET_DEST (set)), x);
689 /* If this register is being made equivalent to a MEM
690 and the MEM is not SET_SRC, the equivalencing insn
691 is one with the MEM as a SET_DEST and it occurs later.
692 So don't mark this insn now. */
693 if (GET_CODE (x) != MEM
694 || rtx_equal_p (SET_SRC (set), x))
695 reg_equiv_init[i] = insn;
700 /* If this insn is setting a MEM from a register equivalent to it,
701 this is the equivalencing insn. */
702 else if (set && GET_CODE (SET_DEST (set)) == MEM
703 && GET_CODE (SET_SRC (set)) == REG
704 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
705 && rtx_equal_p (SET_DEST (set),
706 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
707 reg_equiv_init[REGNO (SET_SRC (set))] = insn;
709 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
710 scan_paradoxical_subregs (PATTERN (insn));
713 /* Does this function require a frame pointer? */
715 frame_pointer_needed = (! flag_omit_frame_pointer
716 #ifdef EXIT_IGNORE_STACK
717 /* ?? If EXIT_IGNORE_STACK is set, we will not save
718 and restore sp for alloca. So we can't eliminate
719 the frame pointer in that case. At some point,
720 we should improve this by emitting the
721 sp-adjusting insns for this case. */
722 || (current_function_calls_alloca
723 && EXIT_IGNORE_STACK)
725 || FRAME_POINTER_REQUIRED);
729 /* Initialize the table of registers to eliminate. The way we do this
730 depends on how the eliminable registers were defined. */
731 #ifdef ELIMINABLE_REGS
732 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
734 ep->can_eliminate = ep->can_eliminate_previous
735 = (CAN_ELIMINATE (ep->from, ep->to)
736 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
739 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
740 = ! frame_pointer_needed;
743 /* Count the number of eliminable registers and build the FROM and TO
744 REG rtx's. Note that code in gen_rtx will cause, e.g.,
745 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
746 We depend on this. */
747 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
749 num_eliminable += ep->can_eliminate;
750 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
751 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
754 num_labels = max_label_num () - get_first_label_num ();
756 /* Allocate the tables used to store offset information at labels. */
757 /* We used to use alloca here, but the size of what it would try to
758 allocate would occasionally cause it to exceed the stack limit and
759 cause a core dump. */
760 real_known_ptr = xmalloc (num_labels);
762 = (int (*)[NUM_ELIMINABLE_REGS])
763 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
765 offsets_known_at = real_known_ptr - get_first_label_num ();
767 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
769 /* Alter each pseudo-reg rtx to contain its hard reg number.
770 Assign stack slots to the pseudos that lack hard regs or equivalents.
771 Do not touch virtual registers. */
773 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
776 /* If we have some registers we think can be eliminated, scan all insns to
777 see if there is an insn that sets one of these registers to something
778 other than itself plus a constant. If so, the register cannot be
779 eliminated. Doing this scan here eliminates an extra pass through the
780 main reload loop in the most common case where register elimination
782 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
783 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
784 || GET_CODE (insn) == CALL_INSN)
785 note_stores (PATTERN (insn), mark_not_eliminable);
787 #ifndef REGISTER_CONSTRAINTS
788 /* If all the pseudo regs have hard regs,
789 except for those that are never referenced,
790 we know that no reloads are needed. */
791 /* But that is not true if there are register constraints, since
792 in that case some pseudos might be in the wrong kind of hard reg. */
794 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
795 if (reg_renumber[i] == -1 && REG_N_REFS (i) != 0)
798 if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
800 free (real_known_ptr);
806 /* Compute the order of preference for hard registers to spill.
807 Store them by decreasing preference in potential_reload_regs. */
809 order_regs_for_reload (global);
811 /* So far, no hard regs have been spilled. */
813 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
814 spill_reg_order[i] = -1;
816 /* Initialize to -1, which means take the first spill register. */
819 /* On most machines, we can't use any register explicitly used in the
820 rtl as a spill register. But on some, we have to. Those will have
821 taken care to keep the life of hard regs as short as possible. */
823 if (! SMALL_REGISTER_CLASSES)
824 COPY_HARD_REG_SET (forbidden_regs, bad_spill_regs);
826 /* Spill any hard regs that we know we can't eliminate. */
827 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
828 if (! ep->can_eliminate)
829 spill_hard_reg (ep->from, global, dumpfile, 1);
831 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
832 if (frame_pointer_needed)
833 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, global, dumpfile, 1);
837 for (i = 0; i < N_REG_CLASSES; i++)
839 basic_block_needs[i] = (char *) alloca (n_basic_blocks);
840 bzero (basic_block_needs[i], n_basic_blocks);
843 /* From now on, we need to emit any moves without making new pseudos. */
844 reload_in_progress = 1;
846 /* This loop scans the entire function each go-round
847 and repeats until one repetition spills no additional hard regs. */
849 /* This flag is set when a pseudo reg is spilled,
850 to require another pass. Note that getting an additional reload
851 reg does not necessarily imply any pseudo reg was spilled;
852 sometimes we find a reload reg that no pseudo reg was allocated in. */
853 something_changed = 1;
854 /* This flag is set if there are any insns that require reloading. */
855 something_needs_reloads = 0;
856 /* This flag is set if there are any insns that require register
858 something_needs_elimination = 0;
859 while (something_changed)
863 /* For each class, number of reload regs needed in that class.
864 This is the maximum over all insns of the needs in that class
865 of the individual insn. */
866 int max_needs[N_REG_CLASSES];
867 /* For each class, size of group of consecutive regs
868 that is needed for the reloads of this class. */
869 int group_size[N_REG_CLASSES];
870 /* For each class, max number of consecutive groups needed.
871 (Each group contains group_size[CLASS] consecutive registers.) */
872 int max_groups[N_REG_CLASSES];
873 /* For each class, max number needed of regs that don't belong
874 to any of the groups. */
875 int max_nongroups[N_REG_CLASSES];
876 /* For each class, the machine mode which requires consecutive
877 groups of regs of that class.
878 If two different modes ever require groups of one class,
879 they must be the same size and equally restrictive for that class,
880 otherwise we can't handle the complexity. */
881 enum machine_mode group_mode[N_REG_CLASSES];
882 /* Record the insn where each maximum need is first found. */
883 rtx max_needs_insn[N_REG_CLASSES];
884 rtx max_groups_insn[N_REG_CLASSES];
885 rtx max_nongroups_insn[N_REG_CLASSES];
887 HOST_WIDE_INT starting_frame_size;
888 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
889 int previous_frame_pointer_needed = frame_pointer_needed;
891 static char *reg_class_names[] = REG_CLASS_NAMES;
893 something_changed = 0;
894 bzero ((char *) max_needs, sizeof max_needs);
895 bzero ((char *) max_groups, sizeof max_groups);
896 bzero ((char *) max_nongroups, sizeof max_nongroups);
897 bzero ((char *) max_needs_insn, sizeof max_needs_insn);
898 bzero ((char *) max_groups_insn, sizeof max_groups_insn);
899 bzero ((char *) max_nongroups_insn, sizeof max_nongroups_insn);
900 bzero ((char *) group_size, sizeof group_size);
901 for (i = 0; i < N_REG_CLASSES; i++)
902 group_mode[i] = VOIDmode;
904 /* Keep track of which basic blocks are needing the reloads. */
907 /* Remember whether any element of basic_block_needs
908 changes from 0 to 1 in this pass. */
909 new_basic_block_needs = 0;
911 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done
912 here because the stack size may be a part of the offset computation
913 for register elimination, and there might have been new stack slots
914 created in the last iteration of this loop. */
915 assign_stack_local (BLKmode, 0, 0);
917 starting_frame_size = get_frame_size ();
919 /* Reset all offsets on eliminable registers to their initial values. */
920 #ifdef ELIMINABLE_REGS
921 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
923 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
924 ep->previous_offset = ep->offset
925 = ep->max_offset = ep->initial_offset;
928 #ifdef INITIAL_FRAME_POINTER_OFFSET
929 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
931 if (!FRAME_POINTER_REQUIRED)
933 reg_eliminate[0].initial_offset = 0;
935 reg_eliminate[0].previous_offset = reg_eliminate[0].max_offset
936 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
939 num_not_at_initial_offset = 0;
941 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
943 /* Set a known offset for each forced label to be at the initial offset
944 of each elimination. We do this because we assume that all
945 computed jumps occur from a location where each elimination is
946 at its initial offset. */
948 for (x = forced_labels; x; x = XEXP (x, 1))
950 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
952 /* For each pseudo register that has an equivalent location defined,
953 try to eliminate any eliminable registers (such as the frame pointer)
954 assuming initial offsets for the replacement register, which
957 If the resulting location is directly addressable, substitute
958 the MEM we just got directly for the old REG.
960 If it is not addressable but is a constant or the sum of a hard reg
961 and constant, it is probably not addressable because the constant is
962 out of range, in that case record the address; we will generate
963 hairy code to compute the address in a register each time it is
964 needed. Similarly if it is a hard register, but one that is not
965 valid as an address register.
967 If the location is not addressable, but does not have one of the
968 above forms, assign a stack slot. We have to do this to avoid the
969 potential of producing lots of reloads if, e.g., a location involves
970 a pseudo that didn't get a hard register and has an equivalent memory
971 location that also involves a pseudo that didn't get a hard register.
973 Perhaps at some point we will improve reload_when_needed handling
974 so this problem goes away. But that's very hairy. */
976 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
977 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
979 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
981 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
983 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
984 else if (CONSTANT_P (XEXP (x, 0))
985 || (GET_CODE (XEXP (x, 0)) == REG
986 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
987 || (GET_CODE (XEXP (x, 0)) == PLUS
988 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
989 && (REGNO (XEXP (XEXP (x, 0), 0))
990 < FIRST_PSEUDO_REGISTER)
991 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
992 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
995 /* Make a new stack slot. Then indicate that something
996 changed so we go back and recompute offsets for
997 eliminable registers because the allocation of memory
998 below might change some offset. reg_equiv_{mem,address}
999 will be set up for this pseudo on the next pass around
1001 reg_equiv_memory_loc[i] = 0;
1002 reg_equiv_init[i] = 0;
1004 something_changed = 1;
1008 /* If we allocated another pseudo to the stack, redo elimination
1010 if (something_changed)
1013 /* If caller-saves needs a group, initialize the group to include
1014 the size and mode required for caller-saves. */
1016 if (caller_save_group_size > 1)
1018 group_mode[(int) caller_save_spill_class] = Pmode;
1019 group_size[(int) caller_save_spill_class] = caller_save_group_size;
1022 /* Compute the most additional registers needed by any instruction.
1023 Collect information separately for each class of regs. */
1025 for (insn = first; insn; insn = NEXT_INSN (insn))
1027 if (global && this_block + 1 < n_basic_blocks
1028 && insn == basic_block_head[this_block+1])
1031 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which
1032 might include REG_LABEL), we need to see what effects this
1033 has on the known offsets at labels. */
1035 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1036 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1037 && REG_NOTES (insn) != 0))
1038 set_label_offsets (insn, insn, 0);
1040 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1042 /* Nonzero means don't use a reload reg that overlaps
1043 the place where a function value can be returned. */
1044 rtx avoid_return_reg = 0;
1046 rtx old_body = PATTERN (insn);
1047 int old_code = INSN_CODE (insn);
1048 rtx old_notes = REG_NOTES (insn);
1049 int did_elimination = 0;
1051 /* To compute the number of reload registers of each class
1052 needed for an insn, we must simulate what choose_reload_regs
1053 can do. We do this by splitting an insn into an "input" and
1054 an "output" part. RELOAD_OTHER reloads are used in both.
1055 The input part uses those reloads, RELOAD_FOR_INPUT reloads,
1056 which must be live over the entire input section of reloads,
1057 and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
1058 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the
1061 The registers needed for output are RELOAD_OTHER and
1062 RELOAD_FOR_OUTPUT, which are live for the entire output
1063 portion, and the maximum of all the RELOAD_FOR_OUTPUT_ADDRESS
1064 reloads for each operand.
1066 The total number of registers needed is the maximum of the
1067 inputs and outputs. */
1071 /* [0] is normal, [1] is nongroup. */
1072 int regs[2][N_REG_CLASSES];
1073 int groups[N_REG_CLASSES];
1076 /* Each `struct needs' corresponds to one RELOAD_... type. */
1080 struct needs output;
1082 struct needs other_addr;
1083 struct needs op_addr;
1084 struct needs op_addr_reload;
1085 struct needs in_addr[MAX_RECOG_OPERANDS];
1086 struct needs in_addr_addr[MAX_RECOG_OPERANDS];
1087 struct needs out_addr[MAX_RECOG_OPERANDS];
1088 struct needs out_addr_addr[MAX_RECOG_OPERANDS];
1091 /* If needed, eliminate any eliminable registers. */
1093 did_elimination = eliminate_regs_in_insn (insn, 0);
1095 /* Set avoid_return_reg if this is an insn
1096 that might use the value of a function call. */
1097 if (SMALL_REGISTER_CLASSES && GET_CODE (insn) == CALL_INSN)
1099 if (GET_CODE (PATTERN (insn)) == SET)
1100 after_call = SET_DEST (PATTERN (insn));
1101 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1102 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1103 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
1107 else if (SMALL_REGISTER_CLASSES && after_call != 0
1108 && !(GET_CODE (PATTERN (insn)) == SET
1109 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx)
1110 && GET_CODE (PATTERN (insn)) != USE)
1112 if (reg_referenced_p (after_call, PATTERN (insn)))
1113 avoid_return_reg = after_call;
1117 /* Analyze the instruction. */
1118 find_reloads (insn, 0, spill_indirect_levels, global,
1121 /* Remember for later shortcuts which insns had any reloads or
1122 register eliminations.
1124 One might think that it would be worthwhile to mark insns
1125 that need register replacements but not reloads, but this is
1126 not safe because find_reloads may do some manipulation of
1127 the insn (such as swapping commutative operands), which would
1128 be lost when we restore the old pattern after register
1129 replacement. So the actions of find_reloads must be redone in
1130 subsequent passes or in reload_as_needed.
1132 However, it is safe to mark insns that need reloads
1133 but not register replacement. */
1135 PUT_MODE (insn, (did_elimination ? QImode
1136 : n_reloads ? HImode
1137 : GET_MODE (insn) == DImode ? DImode
1140 /* Discard any register replacements done. */
1141 if (did_elimination)
1143 obstack_free (&reload_obstack, reload_firstobj);
1144 PATTERN (insn) = old_body;
1145 INSN_CODE (insn) = old_code;
1146 REG_NOTES (insn) = old_notes;
1147 something_needs_elimination = 1;
1150 /* If this insn has no reloads, we need not do anything except
1151 in the case of a CALL_INSN when we have caller-saves and
1152 caller-save needs reloads. */
1155 && ! (GET_CODE (insn) == CALL_INSN
1156 && caller_save_spill_class != NO_REGS))
1159 something_needs_reloads = 1;
1160 bzero ((char *) &insn_needs, sizeof insn_needs);
1162 /* Count each reload once in every class
1163 containing the reload's own class. */
1165 for (i = 0; i < n_reloads; i++)
1167 register enum reg_class *p;
1168 enum reg_class class = reload_reg_class[i];
1170 enum machine_mode mode;
1171 struct needs *this_needs;
1173 /* Don't count the dummy reloads, for which one of the
1174 regs mentioned in the insn can be used for reloading.
1175 Don't count optional reloads.
1176 Don't count reloads that got combined with others. */
1177 if (reload_reg_rtx[i] != 0
1178 || reload_optional[i] != 0
1179 || (reload_out[i] == 0 && reload_in[i] == 0
1180 && ! reload_secondary_p[i]))
1183 /* Show that a reload register of this class is needed
1184 in this basic block. We do not use insn_needs and
1185 insn_groups because they are overly conservative for
1187 if (global && ! basic_block_needs[(int) class][this_block])
1189 basic_block_needs[(int) class][this_block] = 1;
1190 new_basic_block_needs = 1;
1193 mode = reload_inmode[i];
1194 if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1195 mode = reload_outmode[i];
1196 size = CLASS_MAX_NREGS (class, mode);
1198 /* Decide which time-of-use to count this reload for. */
1199 switch (reload_when_needed[i])
1202 this_needs = &insn_needs.other;
1204 case RELOAD_FOR_INPUT:
1205 this_needs = &insn_needs.input;
1207 case RELOAD_FOR_OUTPUT:
1208 this_needs = &insn_needs.output;
1210 case RELOAD_FOR_INSN:
1211 this_needs = &insn_needs.insn;
1213 case RELOAD_FOR_OTHER_ADDRESS:
1214 this_needs = &insn_needs.other_addr;
1216 case RELOAD_FOR_INPUT_ADDRESS:
1217 this_needs = &insn_needs.in_addr[reload_opnum[i]];
1219 case RELOAD_FOR_INPADDR_ADDRESS:
1220 this_needs = &insn_needs.in_addr_addr[reload_opnum[i]];
1222 case RELOAD_FOR_OUTPUT_ADDRESS:
1223 this_needs = &insn_needs.out_addr[reload_opnum[i]];
1225 case RELOAD_FOR_OUTADDR_ADDRESS:
1226 this_needs = &insn_needs.out_addr_addr[reload_opnum[i]];
1228 case RELOAD_FOR_OPERAND_ADDRESS:
1229 this_needs = &insn_needs.op_addr;
1231 case RELOAD_FOR_OPADDR_ADDR:
1232 this_needs = &insn_needs.op_addr_reload;
1238 enum machine_mode other_mode, allocate_mode;
1240 /* Count number of groups needed separately from
1241 number of individual regs needed. */
1242 this_needs->groups[(int) class]++;
1243 p = reg_class_superclasses[(int) class];
1244 while (*p != LIM_REG_CLASSES)
1245 this_needs->groups[(int) *p++]++;
1247 /* Record size and mode of a group of this class. */
1248 /* If more than one size group is needed,
1249 make all groups the largest needed size. */
1250 if (group_size[(int) class] < size)
1252 other_mode = group_mode[(int) class];
1253 allocate_mode = mode;
1255 group_size[(int) class] = size;
1256 group_mode[(int) class] = mode;
1261 allocate_mode = group_mode[(int) class];
1264 /* Crash if two dissimilar machine modes both need
1265 groups of consecutive regs of the same class. */
1267 if (other_mode != VOIDmode && other_mode != allocate_mode
1268 && ! modes_equiv_for_class_p (allocate_mode,
1270 fatal_insn ("Two dissimilar machine modes both need groups of consecutive regs of the same class",
1275 this_needs->regs[reload_nongroup[i]][(int) class] += 1;
1276 p = reg_class_superclasses[(int) class];
1277 while (*p != LIM_REG_CLASSES)
1278 this_needs->regs[reload_nongroup[i]][(int) *p++] += 1;
1284 /* All reloads have been counted for this insn;
1285 now merge the various times of use.
1286 This sets insn_needs, etc., to the maximum total number
1287 of registers needed at any point in this insn. */
1289 for (i = 0; i < N_REG_CLASSES; i++)
1291 int in_max, out_max;
1293 /* Compute normal and nongroup needs. */
1294 for (j = 0; j <= 1; j++)
1296 for (in_max = 0, out_max = 0, k = 0;
1297 k < reload_n_operands; k++)
1301 (insn_needs.in_addr[k].regs[j][i]
1302 + insn_needs.in_addr_addr[k].regs[j][i]));
1304 = MAX (out_max, insn_needs.out_addr[k].regs[j][i]);
1307 insn_needs.out_addr_addr[k].regs[j][i]);
1310 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1311 and operand addresses but not things used to reload
1312 them. Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads
1313 don't conflict with things needed to reload inputs or
1316 in_max = MAX (MAX (insn_needs.op_addr.regs[j][i],
1317 insn_needs.op_addr_reload.regs[j][i]),
1320 out_max = MAX (out_max, insn_needs.insn.regs[j][i]);
1322 insn_needs.input.regs[j][i]
1323 = MAX (insn_needs.input.regs[j][i]
1324 + insn_needs.op_addr.regs[j][i]
1325 + insn_needs.insn.regs[j][i],
1326 in_max + insn_needs.input.regs[j][i]);
1328 insn_needs.output.regs[j][i] += out_max;
1329 insn_needs.other.regs[j][i]
1330 += MAX (MAX (insn_needs.input.regs[j][i],
1331 insn_needs.output.regs[j][i]),
1332 insn_needs.other_addr.regs[j][i]);
1336 /* Now compute group needs. */
1337 for (in_max = 0, out_max = 0, j = 0;
1338 j < reload_n_operands; j++)
1340 in_max = MAX (in_max, insn_needs.in_addr[j].groups[i]);
1341 in_max = MAX (in_max,
1342 insn_needs.in_addr_addr[j].groups[i]);
1344 = MAX (out_max, insn_needs.out_addr[j].groups[i]);
1346 = MAX (out_max, insn_needs.out_addr_addr[j].groups[i]);
1349 in_max = MAX (MAX (insn_needs.op_addr.groups[i],
1350 insn_needs.op_addr_reload.groups[i]),
1352 out_max = MAX (out_max, insn_needs.insn.groups[i]);
1354 insn_needs.input.groups[i]
1355 = MAX (insn_needs.input.groups[i]
1356 + insn_needs.op_addr.groups[i]
1357 + insn_needs.insn.groups[i],
1358 in_max + insn_needs.input.groups[i]);
1360 insn_needs.output.groups[i] += out_max;
1361 insn_needs.other.groups[i]
1362 += MAX (MAX (insn_needs.input.groups[i],
1363 insn_needs.output.groups[i]),
1364 insn_needs.other_addr.groups[i]);
1367 /* If this is a CALL_INSN and caller-saves will need
1368 a spill register, act as if the spill register is
1369 needed for this insn. However, the spill register
1370 can be used by any reload of this insn, so we only
1371 need do something if no need for that class has
1374 The assumption that every CALL_INSN will trigger a
1375 caller-save is highly conservative, however, the number
1376 of cases where caller-saves will need a spill register but
1377 a block containing a CALL_INSN won't need a spill register
1378 of that class should be quite rare.
1380 If a group is needed, the size and mode of the group will
1381 have been set up at the beginning of this loop. */
1383 if (GET_CODE (insn) == CALL_INSN
1384 && caller_save_spill_class != NO_REGS)
1386 /* See if this register would conflict with any reload that
1387 needs a group or any reload that needs a nongroup. */
1388 int nongroup_need = 0;
1389 int *caller_save_needs;
1391 for (j = 0; j < n_reloads; j++)
1392 if (reg_classes_intersect_p (caller_save_spill_class,
1393 reload_reg_class[j])
1394 && ((CLASS_MAX_NREGS
1395 (reload_reg_class[j],
1396 (GET_MODE_SIZE (reload_outmode[j])
1397 > GET_MODE_SIZE (reload_inmode[j]))
1398 ? reload_outmode[j] : reload_inmode[j])
1400 || reload_nongroup[j]))
1407 = (caller_save_group_size > 1
1408 ? insn_needs.other.groups
1409 : insn_needs.other.regs[nongroup_need]);
1411 if (caller_save_needs[(int) caller_save_spill_class] == 0)
1413 register enum reg_class *p
1414 = reg_class_superclasses[(int) caller_save_spill_class];
1416 caller_save_needs[(int) caller_save_spill_class]++;
1418 while (*p != LIM_REG_CLASSES)
1419 caller_save_needs[(int) *p++] += 1;
1422 /* Show that this basic block will need a register of
1426 && ! (basic_block_needs[(int) caller_save_spill_class]
1429 basic_block_needs[(int) caller_save_spill_class]
1431 new_basic_block_needs = 1;
1435 /* If this insn stores the value of a function call,
1436 and that value is in a register that has been spilled,
1437 and if the insn needs a reload in a class
1438 that might use that register as the reload register,
1439 then add an extra need in that class.
1440 This makes sure we have a register available that does
1441 not overlap the return value. */
1443 if (SMALL_REGISTER_CLASSES && avoid_return_reg)
1445 int regno = REGNO (avoid_return_reg);
1447 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
1449 int basic_needs[N_REG_CLASSES], basic_groups[N_REG_CLASSES];
1451 /* First compute the "basic needs", which counts a
1452 need only in the smallest class in which it
1455 bcopy ((char *) insn_needs.other.regs[0],
1456 (char *) basic_needs, sizeof basic_needs);
1457 bcopy ((char *) insn_needs.other.groups,
1458 (char *) basic_groups, sizeof basic_groups);
1460 for (i = 0; i < N_REG_CLASSES; i++)
1464 if (basic_needs[i] >= 0)
1465 for (p = reg_class_superclasses[i];
1466 *p != LIM_REG_CLASSES; p++)
1467 basic_needs[(int) *p] -= basic_needs[i];
1469 if (basic_groups[i] >= 0)
1470 for (p = reg_class_superclasses[i];
1471 *p != LIM_REG_CLASSES; p++)
1472 basic_groups[(int) *p] -= basic_groups[i];
1475 /* Now count extra regs if there might be a conflict with
1476 the return value register. */
1478 for (r = regno; r < regno + nregs; r++)
1479 if (spill_reg_order[r] >= 0)
1480 for (i = 0; i < N_REG_CLASSES; i++)
1481 if (TEST_HARD_REG_BIT (reg_class_contents[i], r))
1483 if (basic_needs[i] > 0)
1487 insn_needs.other.regs[0][i]++;
1488 p = reg_class_superclasses[i];
1489 while (*p != LIM_REG_CLASSES)
1490 insn_needs.other.regs[0][(int) *p++]++;
1492 if (basic_groups[i] > 0)
1496 insn_needs.other.groups[i]++;
1497 p = reg_class_superclasses[i];
1498 while (*p != LIM_REG_CLASSES)
1499 insn_needs.other.groups[(int) *p++]++;
1504 /* For each class, collect maximum need of any insn. */
1506 for (i = 0; i < N_REG_CLASSES; i++)
1508 if (max_needs[i] < insn_needs.other.regs[0][i])
1510 max_needs[i] = insn_needs.other.regs[0][i];
1511 max_needs_insn[i] = insn;
1513 if (max_groups[i] < insn_needs.other.groups[i])
1515 max_groups[i] = insn_needs.other.groups[i];
1516 max_groups_insn[i] = insn;
1518 if (max_nongroups[i] < insn_needs.other.regs[1][i])
1520 max_nongroups[i] = insn_needs.other.regs[1][i];
1521 max_nongroups_insn[i] = insn;
1525 /* Note that there is a continue statement above. */
1528 /* If we allocated any new memory locations, make another pass
1529 since it might have changed elimination offsets. */
1530 if (starting_frame_size != get_frame_size ())
1531 something_changed = 1;
1534 for (i = 0; i < N_REG_CLASSES; i++)
1536 if (max_needs[i] > 0)
1538 ";; Need %d reg%s of class %s (for insn %d).\n",
1539 max_needs[i], max_needs[i] == 1 ? "" : "s",
1540 reg_class_names[i], INSN_UID (max_needs_insn[i]));
1541 if (max_nongroups[i] > 0)
1543 ";; Need %d nongroup reg%s of class %s (for insn %d).\n",
1544 max_nongroups[i], max_nongroups[i] == 1 ? "" : "s",
1545 reg_class_names[i], INSN_UID (max_nongroups_insn[i]));
1546 if (max_groups[i] > 0)
1548 ";; Need %d group%s (%smode) of class %s (for insn %d).\n",
1549 max_groups[i], max_groups[i] == 1 ? "" : "s",
1550 mode_name[(int) group_mode[i]],
1551 reg_class_names[i], INSN_UID (max_groups_insn[i]));
1554 /* If we have caller-saves, set up the save areas and see if caller-save
1555 will need a spill register. */
1557 if (caller_save_needed)
1559 /* Set the offsets for setup_save_areas. */
1560 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
1562 ep->previous_offset = ep->max_offset;
1564 if ( ! setup_save_areas (&something_changed)
1565 && caller_save_spill_class == NO_REGS)
1567 /* The class we will need depends on whether the machine
1568 supports the sum of two registers for an address; see
1569 find_address_reloads for details. */
1571 caller_save_spill_class
1572 = double_reg_address_ok ? INDEX_REG_CLASS : BASE_REG_CLASS;
1573 caller_save_group_size
1574 = CLASS_MAX_NREGS (caller_save_spill_class, Pmode);
1575 something_changed = 1;
1579 /* See if anything that happened changes which eliminations are valid.
1580 For example, on the Sparc, whether or not the frame pointer can
1581 be eliminated can depend on what registers have been used. We need
1582 not check some conditions again (such as flag_omit_frame_pointer)
1583 since they can't have changed. */
1585 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1586 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
1587 #ifdef ELIMINABLE_REGS
1588 || ! CAN_ELIMINATE (ep->from, ep->to)
1591 ep->can_eliminate = 0;
1593 /* Look for the case where we have discovered that we can't replace
1594 register A with register B and that means that we will now be
1595 trying to replace register A with register C. This means we can
1596 no longer replace register C with register B and we need to disable
1597 such an elimination, if it exists. This occurs often with A == ap,
1598 B == sp, and C == fp. */
1600 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1602 struct elim_table *op;
1603 register int new_to = -1;
1605 if (! ep->can_eliminate && ep->can_eliminate_previous)
1607 /* Find the current elimination for ep->from, if there is a
1609 for (op = reg_eliminate;
1610 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1611 if (op->from == ep->from && op->can_eliminate)
1617 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
1619 for (op = reg_eliminate;
1620 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1621 if (op->from == new_to && op->to == ep->to)
1622 op->can_eliminate = 0;
1626 /* See if any registers that we thought we could eliminate the previous
1627 time are no longer eliminable. If so, something has changed and we
1628 must spill the register. Also, recompute the number of eliminable
1629 registers and see if the frame pointer is needed; it is if there is
1630 no elimination of the frame pointer that we can perform. */
1632 frame_pointer_needed = 1;
1633 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1635 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
1636 && ep->to != HARD_FRAME_POINTER_REGNUM)
1637 frame_pointer_needed = 0;
1639 if (! ep->can_eliminate && ep->can_eliminate_previous)
1641 ep->can_eliminate_previous = 0;
1642 spill_hard_reg (ep->from, global, dumpfile, 1);
1643 something_changed = 1;
1648 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1649 /* If we didn't need a frame pointer last time, but we do now, spill
1650 the hard frame pointer. */
1651 if (frame_pointer_needed && ! previous_frame_pointer_needed)
1653 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, global, dumpfile, 1);
1654 something_changed = 1;
1658 /* If all needs are met, we win. */
1660 for (i = 0; i < N_REG_CLASSES; i++)
1661 if (max_needs[i] > 0 || max_groups[i] > 0 || max_nongroups[i] > 0)
1663 if (i == N_REG_CLASSES && !new_basic_block_needs && ! something_changed)
1666 /* Not all needs are met; must spill some hard regs. */
1668 /* Put all registers spilled so far back in potential_reload_regs, but
1669 put them at the front, since we've already spilled most of the
1670 pseudos in them (we might have left some pseudos unspilled if they
1671 were in a block that didn't need any spill registers of a conflicting
1672 class. We used to try to mark off the need for those registers,
1673 but doing so properly is very complex and reallocating them is the
1674 simpler approach. First, "pack" potential_reload_regs by pushing
1675 any nonnegative entries towards the end. That will leave room
1676 for the registers we already spilled.
1678 Also, undo the marking of the spill registers from the last time
1679 around in FORBIDDEN_REGS since we will be probably be allocating
1682 ??? It is theoretically possible that we might end up not using one
1683 of our previously-spilled registers in this allocation, even though
1684 they are at the head of the list. It's not clear what to do about
1685 this, but it was no better before, when we marked off the needs met
1686 by the previously-spilled registers. With the current code, globals
1687 can be allocated into these registers, but locals cannot. */
1691 for (i = j = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
1692 if (potential_reload_regs[i] != -1)
1693 potential_reload_regs[j--] = potential_reload_regs[i];
1695 for (i = 0; i < n_spills; i++)
1697 potential_reload_regs[i] = spill_regs[i];
1698 spill_reg_order[spill_regs[i]] = -1;
1699 CLEAR_HARD_REG_BIT (forbidden_regs, spill_regs[i]);
1705 /* Now find more reload regs to satisfy the remaining need
1706 Do it by ascending class number, since otherwise a reg
1707 might be spilled for a big class and might fail to count
1708 for a smaller class even though it belongs to that class.
1710 Count spilled regs in `spills', and add entries to
1711 `spill_regs' and `spill_reg_order'.
1713 ??? Note there is a problem here.
1714 When there is a need for a group in a high-numbered class,
1715 and also need for non-group regs that come from a lower class,
1716 the non-group regs are chosen first. If there aren't many regs,
1717 they might leave no room for a group.
1719 This was happening on the 386. To fix it, we added the code
1720 that calls possible_group_p, so that the lower class won't
1721 break up the last possible group.
1723 Really fixing the problem would require changes above
1724 in counting the regs already spilled, and in choose_reload_regs.
1725 It might be hard to avoid introducing bugs there. */
1727 CLEAR_HARD_REG_SET (counted_for_groups);
1728 CLEAR_HARD_REG_SET (counted_for_nongroups);
1730 for (class = 0; class < N_REG_CLASSES; class++)
1732 /* First get the groups of registers.
1733 If we got single registers first, we might fragment
1735 while (max_groups[class] > 0)
1737 /* If any single spilled regs happen to form groups,
1738 count them now. Maybe we don't really need
1739 to spill another group. */
1740 count_possible_groups (group_size, group_mode, max_groups,
1743 if (max_groups[class] <= 0)
1746 /* Groups of size 2 (the only groups used on most machines)
1747 are treated specially. */
1748 if (group_size[class] == 2)
1750 /* First, look for a register that will complete a group. */
1751 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1755 j = potential_reload_regs[i];
1756 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1758 ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1759 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1760 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1761 && HARD_REGNO_MODE_OK (other, group_mode[class])
1762 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1764 /* We don't want one part of another group.
1765 We could get "two groups" that overlap! */
1766 && ! TEST_HARD_REG_BIT (counted_for_groups, other))
1768 (j < FIRST_PSEUDO_REGISTER - 1
1769 && (other = j + 1, spill_reg_order[other] >= 0)
1770 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1771 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1772 && HARD_REGNO_MODE_OK (j, group_mode[class])
1773 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1775 && ! TEST_HARD_REG_BIT (counted_for_groups,
1778 register enum reg_class *p;
1780 /* We have found one that will complete a group,
1781 so count off one group as provided. */
1782 max_groups[class]--;
1783 p = reg_class_superclasses[class];
1784 while (*p != LIM_REG_CLASSES)
1786 if (group_size [(int) *p] <= group_size [class])
1787 max_groups[(int) *p]--;
1791 /* Indicate both these regs are part of a group. */
1792 SET_HARD_REG_BIT (counted_for_groups, j);
1793 SET_HARD_REG_BIT (counted_for_groups, other);
1797 /* We can't complete a group, so start one. */
1798 /* Look for a pair neither of which is explicitly used. */
1799 if (SMALL_REGISTER_CLASSES && i == FIRST_PSEUDO_REGISTER)
1800 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1803 j = potential_reload_regs[i];
1804 /* Verify that J+1 is a potential reload reg. */
1805 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1806 if (potential_reload_regs[k] == j + 1)
1808 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1809 && k < FIRST_PSEUDO_REGISTER
1810 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1811 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1812 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1813 && HARD_REGNO_MODE_OK (j, group_mode[class])
1814 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1816 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1)
1817 /* Reject J at this stage
1818 if J+1 was explicitly used. */
1819 && ! regs_explicitly_used[j + 1])
1822 /* Now try any group at all
1823 whose registers are not in bad_spill_regs. */
1824 if (i == FIRST_PSEUDO_REGISTER)
1825 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1828 j = potential_reload_regs[i];
1829 /* Verify that J+1 is a potential reload reg. */
1830 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1831 if (potential_reload_regs[k] == j + 1)
1833 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1834 && k < FIRST_PSEUDO_REGISTER
1835 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1836 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1837 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1838 && HARD_REGNO_MODE_OK (j, group_mode[class])
1839 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1841 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1))
1845 /* I should be the index in potential_reload_regs
1846 of the new reload reg we have found. */
1848 if (i >= FIRST_PSEUDO_REGISTER)
1850 /* There are no groups left to spill. */
1851 spill_failure (max_groups_insn[class]);
1857 |= new_spill_reg (i, class, max_needs, NULL_PTR,
1862 /* For groups of more than 2 registers,
1863 look for a sufficient sequence of unspilled registers,
1864 and spill them all at once. */
1865 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1869 j = potential_reload_regs[i];
1871 && j + group_size[class] <= FIRST_PSEUDO_REGISTER
1872 && HARD_REGNO_MODE_OK (j, group_mode[class]))
1874 /* Check each reg in the sequence. */
1875 for (k = 0; k < group_size[class]; k++)
1876 if (! (spill_reg_order[j + k] < 0
1877 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1878 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1880 /* We got a full sequence, so spill them all. */
1881 if (k == group_size[class])
1883 register enum reg_class *p;
1884 for (k = 0; k < group_size[class]; k++)
1887 SET_HARD_REG_BIT (counted_for_groups, j + k);
1888 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1889 if (potential_reload_regs[idx] == j + k)
1892 |= new_spill_reg (idx, class,
1893 max_needs, NULL_PTR,
1897 /* We have found one that will complete a group,
1898 so count off one group as provided. */
1899 max_groups[class]--;
1900 p = reg_class_superclasses[class];
1901 while (*p != LIM_REG_CLASSES)
1903 if (group_size [(int) *p]
1904 <= group_size [class])
1905 max_groups[(int) *p]--;
1912 /* We couldn't find any registers for this reload.
1913 Avoid going into an infinite loop. */
1914 if (i >= FIRST_PSEUDO_REGISTER)
1916 /* There are no groups left. */
1917 spill_failure (max_groups_insn[class]);
1924 /* Now similarly satisfy all need for single registers. */
1926 while (max_needs[class] > 0 || max_nongroups[class] > 0)
1928 /* If we spilled enough regs, but they weren't counted
1929 against the non-group need, see if we can count them now.
1930 If so, we can avoid some actual spilling. */
1931 if (max_needs[class] <= 0 && max_nongroups[class] > 0)
1932 for (i = 0; i < n_spills; i++)
1933 if (TEST_HARD_REG_BIT (reg_class_contents[class],
1935 && !TEST_HARD_REG_BIT (counted_for_groups,
1937 && !TEST_HARD_REG_BIT (counted_for_nongroups,
1939 && max_nongroups[class] > 0)
1941 register enum reg_class *p;
1943 SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]);
1944 max_nongroups[class]--;
1945 p = reg_class_superclasses[class];
1946 while (*p != LIM_REG_CLASSES)
1947 max_nongroups[(int) *p++]--;
1949 if (max_needs[class] <= 0 && max_nongroups[class] <= 0)
1952 /* Consider the potential reload regs that aren't
1953 yet in use as reload regs, in order of preference.
1954 Find the most preferred one that's in this class. */
1956 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1957 if (potential_reload_regs[i] >= 0
1958 && TEST_HARD_REG_BIT (reg_class_contents[class],
1959 potential_reload_regs[i])
1960 /* If this reg will not be available for groups,
1961 pick one that does not foreclose possible groups.
1962 This is a kludge, and not very general,
1963 but it should be sufficient to make the 386 work,
1964 and the problem should not occur on machines with
1966 && (max_nongroups[class] == 0
1967 || possible_group_p (potential_reload_regs[i], max_groups)))
1970 /* If we couldn't get a register, try to get one even if we
1971 might foreclose possible groups. This may cause problems
1972 later, but that's better than aborting now, since it is
1973 possible that we will, in fact, be able to form the needed
1974 group even with this allocation. */
1976 if (i >= FIRST_PSEUDO_REGISTER
1977 && (asm_noperands (max_needs[class] > 0
1978 ? max_needs_insn[class]
1979 : max_nongroups_insn[class])
1981 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1982 if (potential_reload_regs[i] >= 0
1983 && TEST_HARD_REG_BIT (reg_class_contents[class],
1984 potential_reload_regs[i]))
1987 /* I should be the index in potential_reload_regs
1988 of the new reload reg we have found. */
1990 if (i >= FIRST_PSEUDO_REGISTER)
1992 /* There are no possible registers left to spill. */
1993 spill_failure (max_needs[class] > 0 ? max_needs_insn[class]
1994 : max_nongroups_insn[class]);
2000 |= new_spill_reg (i, class, max_needs, max_nongroups,
2006 /* If global-alloc was run, notify it of any register eliminations we have
2009 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2010 if (ep->can_eliminate)
2011 mark_elimination (ep->from, ep->to);
2013 /* Insert code to save and restore call-clobbered hard regs
2014 around calls. Tell if what mode to use so that we will process
2015 those insns in reload_as_needed if we have to. */
2017 if (caller_save_needed)
2018 save_call_clobbered_regs (num_eliminable ? QImode
2019 : caller_save_spill_class != NO_REGS ? HImode
2022 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
2023 If that insn didn't set the register (i.e., it copied the register to
2024 memory), just delete that insn instead of the equivalencing insn plus
2025 anything now dead. If we call delete_dead_insn on that insn, we may
2026 delete the insn that actually sets the register if the register die
2027 there and that is incorrect. */
2029 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2030 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0
2031 && GET_CODE (reg_equiv_init[i]) != NOTE)
2033 if (reg_set_p (regno_reg_rtx[i], PATTERN (reg_equiv_init[i])))
2034 delete_dead_insn (reg_equiv_init[i]);
2037 PUT_CODE (reg_equiv_init[i], NOTE);
2038 NOTE_SOURCE_FILE (reg_equiv_init[i]) = 0;
2039 NOTE_LINE_NUMBER (reg_equiv_init[i]) = NOTE_INSN_DELETED;
2043 /* Use the reload registers where necessary
2044 by generating move instructions to move the must-be-register
2045 values into or out of the reload registers. */
2047 if (something_needs_reloads || something_needs_elimination
2048 || (caller_save_needed && num_eliminable)
2049 || caller_save_spill_class != NO_REGS)
2050 reload_as_needed (first, global);
2052 /* If we were able to eliminate the frame pointer, show that it is no
2053 longer live at the start of any basic block. If it ls live by
2054 virtue of being in a pseudo, that pseudo will be marked live
2055 and hence the frame pointer will be known to be live via that
2058 if (! frame_pointer_needed)
2059 for (i = 0; i < n_basic_blocks; i++)
2060 CLEAR_REGNO_REG_SET (basic_block_live_at_start[i],
2061 HARD_FRAME_POINTER_REGNUM);
2063 /* Come here (with failure set nonzero) if we can't get enough spill regs
2064 and we decide not to abort about it. */
2067 reload_in_progress = 0;
2069 /* Now eliminate all pseudo regs by modifying them into
2070 their equivalent memory references.
2071 The REG-rtx's for the pseudos are modified in place,
2072 so all insns that used to refer to them now refer to memory.
2074 For a reg that has a reg_equiv_address, all those insns
2075 were changed by reloading so that no insns refer to it any longer;
2076 but the DECL_RTL of a variable decl may refer to it,
2077 and if so this causes the debugging info to mention the variable. */
2079 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2083 int is_readonly = 0;
2085 if (reg_equiv_memory_loc[i])
2087 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
2088 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
2091 if (reg_equiv_mem[i])
2092 addr = XEXP (reg_equiv_mem[i], 0);
2094 if (reg_equiv_address[i])
2095 addr = reg_equiv_address[i];
2099 if (reg_renumber[i] < 0)
2101 rtx reg = regno_reg_rtx[i];
2102 XEXP (reg, 0) = addr;
2103 REG_USERVAR_P (reg) = 0;
2104 RTX_UNCHANGING_P (reg) = is_readonly;
2105 MEM_IN_STRUCT_P (reg) = in_struct;
2106 /* We have no alias information about this newly created
2108 MEM_ALIAS_SET (reg) = 0;
2109 PUT_CODE (reg, MEM);
2111 else if (reg_equiv_mem[i])
2112 XEXP (reg_equiv_mem[i], 0) = addr;
2116 /* Make a pass over all the insns and delete all USEs which we inserted
2117 only to tag a REG_EQUAL note on them; if PRESERVE_DEATH_INFO_REGNO_P
2118 is defined, also remove death notes for things that are no longer
2119 registers or no longer die in the insn (e.g., an input and output
2120 pseudo being tied). */
2122 for (insn = first; insn; insn = NEXT_INSN (insn))
2123 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
2125 #ifdef PRESERVE_DEATH_INFO_REGNO_P
2129 if (GET_CODE (PATTERN (insn)) == USE
2130 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
2132 PUT_CODE (insn, NOTE);
2133 NOTE_SOURCE_FILE (insn) = 0;
2134 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2137 #ifdef PRESERVE_DEATH_INFO_REGNO_P
2138 for (note = REG_NOTES (insn); note; note = next)
2140 next = XEXP (note, 1);
2141 if (REG_NOTE_KIND (note) == REG_DEAD
2142 && (GET_CODE (XEXP (note, 0)) != REG
2143 || reg_set_p (XEXP (note, 0), PATTERN (insn))))
2144 remove_note (insn, note);
2149 /* If we are doing stack checking, give a warning if this function's
2150 frame size is larger than we expect. */
2151 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
2153 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
2155 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2156 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
2157 size += UNITS_PER_WORD;
2159 if (size > STACK_CHECK_MAX_FRAME_SIZE)
2160 warning ("frame size too large for reliable stack checking");
2163 /* Indicate that we no longer have known memory locations or constants. */
2164 reg_equiv_constant = 0;
2165 reg_equiv_memory_loc = 0;
2168 free (real_known_ptr);
2173 free (scratch_list);
2176 free (scratch_block);
2179 CLEAR_HARD_REG_SET (used_spill_regs);
2180 for (i = 0; i < n_spills; i++)
2181 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
2186 /* Nonzero if, after spilling reg REGNO for non-groups,
2187 it will still be possible to find a group if we still need one. */
2190 possible_group_p (regno, max_groups)
2195 int class = (int) NO_REGS;
2197 for (i = 0; i < (int) N_REG_CLASSES; i++)
2198 if (max_groups[i] > 0)
2204 if (class == (int) NO_REGS)
2207 /* Consider each pair of consecutive registers. */
2208 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
2210 /* Ignore pairs that include reg REGNO. */
2211 if (i == regno || i + 1 == regno)
2214 /* Ignore pairs that are outside the class that needs the group.
2215 ??? Here we fail to handle the case where two different classes
2216 independently need groups. But this never happens with our
2217 current machine descriptions. */
2218 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
2219 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
2222 /* A pair of consecutive regs we can still spill does the trick. */
2223 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
2224 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2225 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
2228 /* A pair of one already spilled and one we can spill does it
2229 provided the one already spilled is not otherwise reserved. */
2230 if (spill_reg_order[i] < 0
2231 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2232 && spill_reg_order[i + 1] >= 0
2233 && ! TEST_HARD_REG_BIT (counted_for_groups, i + 1)
2234 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i + 1))
2236 if (spill_reg_order[i + 1] < 0
2237 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
2238 && spill_reg_order[i] >= 0
2239 && ! TEST_HARD_REG_BIT (counted_for_groups, i)
2240 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i))
2247 /* Count any groups of CLASS that can be formed from the registers recently
2251 count_possible_groups (group_size, group_mode, max_groups, class)
2253 enum machine_mode *group_mode;
2260 /* Now find all consecutive groups of spilled registers
2261 and mark each group off against the need for such groups.
2262 But don't count them against ordinary need, yet. */
2264 if (group_size[class] == 0)
2267 CLEAR_HARD_REG_SET (new);
2269 /* Make a mask of all the regs that are spill regs in class I. */
2270 for (i = 0; i < n_spills; i++)
2271 if (TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
2272 && ! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[i])
2273 && ! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
2274 SET_HARD_REG_BIT (new, spill_regs[i]);
2276 /* Find each consecutive group of them. */
2277 for (i = 0; i < FIRST_PSEUDO_REGISTER && max_groups[class] > 0; i++)
2278 if (TEST_HARD_REG_BIT (new, i)
2279 && i + group_size[class] <= FIRST_PSEUDO_REGISTER
2280 && HARD_REGNO_MODE_OK (i, group_mode[class]))
2282 for (j = 1; j < group_size[class]; j++)
2283 if (! TEST_HARD_REG_BIT (new, i + j))
2286 if (j == group_size[class])
2288 /* We found a group. Mark it off against this class's need for
2289 groups, and against each superclass too. */
2290 register enum reg_class *p;
2292 max_groups[class]--;
2293 p = reg_class_superclasses[class];
2294 while (*p != LIM_REG_CLASSES)
2296 if (group_size [(int) *p] <= group_size [class])
2297 max_groups[(int) *p]--;
2301 /* Don't count these registers again. */
2302 for (j = 0; j < group_size[class]; j++)
2303 SET_HARD_REG_BIT (counted_for_groups, i + j);
2306 /* Skip to the last reg in this group. When i is incremented above,
2307 it will then point to the first reg of the next possible group. */
2312 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2313 another mode that needs to be reloaded for the same register class CLASS.
2314 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2315 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2317 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2318 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2319 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2320 causes unnecessary failures on machines requiring alignment of register
2321 groups when the two modes are different sizes, because the larger mode has
2322 more strict alignment rules than the smaller mode. */
2325 modes_equiv_for_class_p (allocate_mode, other_mode, class)
2326 enum machine_mode allocate_mode, other_mode;
2327 enum reg_class class;
2330 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2332 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
2333 && HARD_REGNO_MODE_OK (regno, allocate_mode)
2334 && ! HARD_REGNO_MODE_OK (regno, other_mode))
2340 /* Handle the failure to find a register to spill.
2341 INSN should be one of the insns which needed this particular spill reg. */
2344 spill_failure (insn)
2347 if (asm_noperands (PATTERN (insn)) >= 0)
2348 error_for_asm (insn, "`asm' needs too many reloads");
2350 fatal_insn ("Unable to find a register to spill.", insn);
2353 /* Add a new register to the tables of available spill-registers
2354 (as well as spilling all pseudos allocated to the register).
2355 I is the index of this register in potential_reload_regs.
2356 CLASS is the regclass whose need is being satisfied.
2357 MAX_NEEDS and MAX_NONGROUPS are the vectors of needs,
2358 so that this register can count off against them.
2359 MAX_NONGROUPS is 0 if this register is part of a group.
2360 GLOBAL and DUMPFILE are the same as the args that `reload' got. */
2363 new_spill_reg (i, class, max_needs, max_nongroups, global, dumpfile)
2371 register enum reg_class *p;
2373 int regno = potential_reload_regs[i];
2375 if (i >= FIRST_PSEUDO_REGISTER)
2376 abort (); /* Caller failed to find any register. */
2378 if (fixed_regs[regno] || TEST_HARD_REG_BIT (forbidden_regs, regno))
2380 static char *reg_class_names[] = REG_CLASS_NAMES;
2381 fatal ("fixed or forbidden register %d (%s) was spilled for class %s.\n\
2382 This may be due to a compiler bug or to impossible asm\n\
2383 statements or clauses.", regno, reg_names[regno], reg_class_names[class]);
2386 /* Make reg REGNO an additional reload reg. */
2388 potential_reload_regs[i] = -1;
2389 spill_regs[n_spills] = regno;
2390 spill_reg_order[regno] = n_spills;
2392 fprintf (dumpfile, "Spilling reg %d.\n", spill_regs[n_spills]);
2394 /* Clear off the needs we just satisfied. */
2397 p = reg_class_superclasses[class];
2398 while (*p != LIM_REG_CLASSES)
2399 max_needs[(int) *p++]--;
2401 if (max_nongroups && max_nongroups[class] > 0)
2403 SET_HARD_REG_BIT (counted_for_nongroups, regno);
2404 max_nongroups[class]--;
2405 p = reg_class_superclasses[class];
2406 while (*p != LIM_REG_CLASSES)
2407 max_nongroups[(int) *p++]--;
2410 /* Spill every pseudo reg that was allocated to this reg
2411 or to something that overlaps this reg. */
2413 val = spill_hard_reg (spill_regs[n_spills], global, dumpfile, 0);
2415 /* If there are some registers still to eliminate and this register
2416 wasn't ever used before, additional stack space may have to be
2417 allocated to store this register. Thus, we may have changed the offset
2418 between the stack and frame pointers, so mark that something has changed.
2419 (If new pseudos were spilled, thus requiring more space, VAL would have
2420 been set non-zero by the call to spill_hard_reg above since additional
2421 reloads may be needed in that case.
2423 One might think that we need only set VAL to 1 if this is a call-used
2424 register. However, the set of registers that must be saved by the
2425 prologue is not identical to the call-used set. For example, the
2426 register used by the call insn for the return PC is a call-used register,
2427 but must be saved by the prologue. */
2428 if (num_eliminable && ! regs_ever_live[spill_regs[n_spills]])
2431 regs_ever_live[spill_regs[n_spills]] = 1;
2437 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2438 data that is dead in INSN. */
2441 delete_dead_insn (insn)
2444 rtx prev = prev_real_insn (insn);
2447 /* If the previous insn sets a register that dies in our insn, delete it
2449 if (prev && GET_CODE (PATTERN (prev)) == SET
2450 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2451 && reg_mentioned_p (prev_dest, PATTERN (insn))
2452 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2453 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2454 delete_dead_insn (prev);
2456 PUT_CODE (insn, NOTE);
2457 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2458 NOTE_SOURCE_FILE (insn) = 0;
2461 /* Modify the home of pseudo-reg I.
2462 The new home is present in reg_renumber[I].
2464 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2465 or it may be -1, meaning there is none or it is not relevant.
2466 This is used so that all pseudos spilled from a given hard reg
2467 can share one stack slot. */
2470 alter_reg (i, from_reg)
2474 /* When outputting an inline function, this can happen
2475 for a reg that isn't actually used. */
2476 if (regno_reg_rtx[i] == 0)
2479 /* If the reg got changed to a MEM at rtl-generation time,
2481 if (GET_CODE (regno_reg_rtx[i]) != REG)
2484 /* Modify the reg-rtx to contain the new hard reg
2485 number or else to contain its pseudo reg number. */
2486 REGNO (regno_reg_rtx[i])
2487 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2489 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2490 allocate a stack slot for it. */
2492 if (reg_renumber[i] < 0
2493 && REG_N_REFS (i) > 0
2494 && reg_equiv_constant[i] == 0
2495 && reg_equiv_memory_loc[i] == 0)
2498 int inherent_size = PSEUDO_REGNO_BYTES (i);
2499 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2502 /* Each pseudo reg has an inherent size which comes from its own mode,
2503 and a total size which provides room for paradoxical subregs
2504 which refer to the pseudo reg in wider modes.
2506 We can use a slot already allocated if it provides both
2507 enough inherent space and enough total space.
2508 Otherwise, we allocate a new slot, making sure that it has no less
2509 inherent space, and no less total space, then the previous slot. */
2512 /* No known place to spill from => no slot to reuse. */
2513 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
2514 inherent_size == total_size ? 0 : -1);
2515 if (BYTES_BIG_ENDIAN)
2516 /* Cancel the big-endian correction done in assign_stack_local.
2517 Get the address of the beginning of the slot.
2518 This is so we can do a big-endian correction unconditionally
2520 adjust = inherent_size - total_size;
2522 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2524 /* Reuse a stack slot if possible. */
2525 else if (spill_stack_slot[from_reg] != 0
2526 && spill_stack_slot_width[from_reg] >= total_size
2527 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2529 x = spill_stack_slot[from_reg];
2530 /* Allocate a bigger slot. */
2533 /* Compute maximum size needed, both for inherent size
2534 and for total size. */
2535 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2537 if (spill_stack_slot[from_reg])
2539 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2541 mode = GET_MODE (spill_stack_slot[from_reg]);
2542 if (spill_stack_slot_width[from_reg] > total_size)
2543 total_size = spill_stack_slot_width[from_reg];
2545 /* Make a slot with that size. */
2546 x = assign_stack_local (mode, total_size,
2547 inherent_size == total_size ? 0 : -1);
2549 if (BYTES_BIG_ENDIAN)
2551 /* Cancel the big-endian correction done in assign_stack_local.
2552 Get the address of the beginning of the slot.
2553 This is so we can do a big-endian correction unconditionally
2555 adjust = GET_MODE_SIZE (mode) - total_size;
2557 stack_slot = gen_rtx_MEM (mode_for_size (total_size
2560 plus_constant (XEXP (x, 0), adjust));
2562 spill_stack_slot[from_reg] = stack_slot;
2563 spill_stack_slot_width[from_reg] = total_size;
2566 /* On a big endian machine, the "address" of the slot
2567 is the address of the low part that fits its inherent mode. */
2568 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2569 adjust += (total_size - inherent_size);
2571 /* If we have any adjustment to make, or if the stack slot is the
2572 wrong mode, make a new stack slot. */
2573 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2575 x = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
2576 plus_constant (XEXP (x, 0), adjust));
2578 /* If this was shared among registers, must ensure we never
2579 set it readonly since that can cause scheduling
2580 problems. Note we would only have in this adjustment
2581 case in any event, since the code above doesn't set it. */
2584 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2587 /* Save the stack slot for later. */
2588 reg_equiv_memory_loc[i] = x;
2592 /* Mark the slots in regs_ever_live for the hard regs
2593 used by pseudo-reg number REGNO. */
2596 mark_home_live (regno)
2599 register int i, lim;
2600 i = reg_renumber[regno];
2603 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2605 regs_ever_live[i++] = 1;
2608 /* Mark the registers used in SCRATCH as being live. */
2611 mark_scratch_live (scratch)
2615 int regno = REGNO (scratch);
2616 int lim = regno + HARD_REGNO_NREGS (regno, GET_MODE (scratch));
2618 for (i = regno; i < lim; i++)
2619 regs_ever_live[i] = 1;
2622 /* This function handles the tracking of elimination offsets around branches.
2624 X is a piece of RTL being scanned.
2626 INSN is the insn that it came from, if any.
2628 INITIAL_P is non-zero if we are to set the offset to be the initial
2629 offset and zero if we are setting the offset of the label to be the
2633 set_label_offsets (x, insn, initial_p)
2638 enum rtx_code code = GET_CODE (x);
2641 struct elim_table *p;
2646 if (LABEL_REF_NONLOCAL_P (x))
2651 /* ... fall through ... */
2654 /* If we know nothing about this label, set the desired offsets. Note
2655 that this sets the offset at a label to be the offset before a label
2656 if we don't know anything about the label. This is not correct for
2657 the label after a BARRIER, but is the best guess we can make. If
2658 we guessed wrong, we will suppress an elimination that might have
2659 been possible had we been able to guess correctly. */
2661 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2663 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2664 offsets_at[CODE_LABEL_NUMBER (x)][i]
2665 = (initial_p ? reg_eliminate[i].initial_offset
2666 : reg_eliminate[i].offset);
2667 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2670 /* Otherwise, if this is the definition of a label and it is
2671 preceded by a BARRIER, set our offsets to the known offset of
2675 && (tem = prev_nonnote_insn (insn)) != 0
2676 && GET_CODE (tem) == BARRIER)
2678 num_not_at_initial_offset = 0;
2679 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2681 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
2682 = offsets_at[CODE_LABEL_NUMBER (x)][i];
2683 if (reg_eliminate[i].can_eliminate
2684 && (reg_eliminate[i].offset
2685 != reg_eliminate[i].initial_offset))
2686 num_not_at_initial_offset++;
2691 /* If neither of the above cases is true, compare each offset
2692 with those previously recorded and suppress any eliminations
2693 where the offsets disagree. */
2695 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2696 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2697 != (initial_p ? reg_eliminate[i].initial_offset
2698 : reg_eliminate[i].offset))
2699 reg_eliminate[i].can_eliminate = 0;
2704 set_label_offsets (PATTERN (insn), insn, initial_p);
2706 /* ... fall through ... */
2710 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2711 and hence must have all eliminations at their initial offsets. */
2712 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2713 if (REG_NOTE_KIND (tem) == REG_LABEL)
2714 set_label_offsets (XEXP (tem, 0), insn, 1);
2719 /* Each of the labels in the address vector must be at their initial
2720 offsets. We want the first field for ADDR_VEC and the second
2721 field for ADDR_DIFF_VEC. */
2723 for (i = 0; i < XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2724 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2729 /* We only care about setting PC. If the source is not RETURN,
2730 IF_THEN_ELSE, or a label, disable any eliminations not at
2731 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2732 isn't one of those possibilities. For branches to a label,
2733 call ourselves recursively.
2735 Note that this can disable elimination unnecessarily when we have
2736 a non-local goto since it will look like a non-constant jump to
2737 someplace in the current function. This isn't a significant
2738 problem since such jumps will normally be when all elimination
2739 pairs are back to their initial offsets. */
2741 if (SET_DEST (x) != pc_rtx)
2744 switch (GET_CODE (SET_SRC (x)))
2751 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2755 tem = XEXP (SET_SRC (x), 1);
2756 if (GET_CODE (tem) == LABEL_REF)
2757 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2758 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2761 tem = XEXP (SET_SRC (x), 2);
2762 if (GET_CODE (tem) == LABEL_REF)
2763 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2764 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2772 /* If we reach here, all eliminations must be at their initial
2773 offset because we are doing a jump to a variable address. */
2774 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2775 if (p->offset != p->initial_offset)
2776 p->can_eliminate = 0;
2784 /* Used for communication between the next two function to properly share
2785 the vector for an ASM_OPERANDS. */
2787 static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2789 /* Scan X and replace any eliminable registers (such as fp) with a
2790 replacement (such as sp), plus an offset.
2792 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2793 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2794 MEM, we are allowed to replace a sum of a register and the constant zero
2795 with the register, which we cannot do outside a MEM. In addition, we need
2796 to record the fact that a register is referenced outside a MEM.
2798 If INSN is an insn, it is the insn containing X. If we replace a REG
2799 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2800 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2801 the REG is being modified.
2803 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2804 That's used when we eliminate in expressions stored in notes.
2805 This means, do not set ref_outside_mem even if the reference
2808 If we see a modification to a register we know about, take the
2809 appropriate action (see case SET, below).
2811 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2812 replacements done assuming all offsets are at their initial values. If
2813 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2814 encounter, return the actual location so that find_reloads will do
2815 the proper thing. */
2818 eliminate_regs (x, mem_mode, insn)
2820 enum machine_mode mem_mode;
2823 enum rtx_code code = GET_CODE (x);
2824 struct elim_table *ep;
2847 /* This is only for the benefit of the debugging backends, which call
2848 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2849 removed after CSE. */
2850 new = eliminate_regs (XEXP (x, 0), 0, insn);
2851 if (GET_CODE (new) == MEM)
2852 return XEXP (new, 0);
2858 /* First handle the case where we encounter a bare register that
2859 is eliminable. Replace it with a PLUS. */
2860 if (regno < FIRST_PSEUDO_REGISTER)
2862 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2864 if (ep->from_rtx == x && ep->can_eliminate)
2867 /* Refs inside notes don't count for this purpose. */
2868 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2869 || GET_CODE (insn) == INSN_LIST)))
2870 ep->ref_outside_mem = 1;
2871 return plus_constant (ep->to_rtx, ep->previous_offset);
2875 else if (reg_equiv_memory_loc && reg_equiv_memory_loc[regno]
2876 && (reg_equiv_address[regno] || num_not_at_initial_offset))
2878 /* In this case, find_reloads would attempt to either use an
2879 incorrect address (if something is not at its initial offset)
2880 or substitute an replaced address into an insn (which loses
2881 if the offset is changed by some later action). So we simply
2882 return the replaced stack slot (assuming it is changed by
2883 elimination) and ignore the fact that this is actually a
2884 reference to the pseudo. Ensure we make a copy of the
2885 address in case it is shared. */
2886 new = eliminate_regs (reg_equiv_memory_loc[regno], mem_mode, insn);
2887 if (new != reg_equiv_memory_loc[regno])
2889 if (insn != 0 && GET_CODE (insn) != EXPR_LIST
2890 && GET_CODE (insn) != INSN_LIST)
2891 REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode, x), insn))
2892 = gen_rtx_EXPR_LIST (REG_EQUAL, new, NULL_RTX);
2893 return copy_rtx (new);
2899 /* If this is the sum of an eliminable register and a constant, rework
2901 if (GET_CODE (XEXP (x, 0)) == REG
2902 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2903 && CONSTANT_P (XEXP (x, 1)))
2905 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2907 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2910 /* Refs inside notes don't count for this purpose. */
2911 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2912 || GET_CODE (insn) == INSN_LIST)))
2913 ep->ref_outside_mem = 1;
2915 /* The only time we want to replace a PLUS with a REG (this
2916 occurs when the constant operand of the PLUS is the negative
2917 of the offset) is when we are inside a MEM. We won't want
2918 to do so at other times because that would change the
2919 structure of the insn in a way that reload can't handle.
2920 We special-case the commonest situation in
2921 eliminate_regs_in_insn, so just replace a PLUS with a
2922 PLUS here, unless inside a MEM. */
2923 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2924 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2927 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2928 plus_constant (XEXP (x, 1),
2929 ep->previous_offset));
2932 /* If the register is not eliminable, we are done since the other
2933 operand is a constant. */
2937 /* If this is part of an address, we want to bring any constant to the
2938 outermost PLUS. We will do this by doing register replacement in
2939 our operands and seeing if a constant shows up in one of them.
2941 We assume here this is part of an address (or a "load address" insn)
2942 since an eliminable register is not likely to appear in any other
2945 If we have (plus (eliminable) (reg)), we want to produce
2946 (plus (plus (replacement) (reg) (const))). If this was part of a
2947 normal add insn, (plus (replacement) (reg)) will be pushed as a
2948 reload. This is the desired action. */
2951 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2952 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2954 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2956 /* If one side is a PLUS and the other side is a pseudo that
2957 didn't get a hard register but has a reg_equiv_constant,
2958 we must replace the constant here since it may no longer
2959 be in the position of any operand. */
2960 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2961 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2962 && reg_renumber[REGNO (new1)] < 0
2963 && reg_equiv_constant != 0
2964 && reg_equiv_constant[REGNO (new1)] != 0)
2965 new1 = reg_equiv_constant[REGNO (new1)];
2966 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2967 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2968 && reg_renumber[REGNO (new0)] < 0
2969 && reg_equiv_constant[REGNO (new0)] != 0)
2970 new0 = reg_equiv_constant[REGNO (new0)];
2972 new = form_sum (new0, new1);
2974 /* As above, if we are not inside a MEM we do not want to
2975 turn a PLUS into something else. We might try to do so here
2976 for an addition of 0 if we aren't optimizing. */
2977 if (! mem_mode && GET_CODE (new) != PLUS)
2978 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2986 /* If this is the product of an eliminable register and a
2987 constant, apply the distribute law and move the constant out
2988 so that we have (plus (mult ..) ..). This is needed in order
2989 to keep load-address insns valid. This case is pathological.
2990 We ignore the possibility of overflow here. */
2991 if (GET_CODE (XEXP (x, 0)) == REG
2992 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2993 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2994 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2996 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2999 /* Refs inside notes don't count for this purpose. */
3000 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
3001 || GET_CODE (insn) == INSN_LIST)))
3002 ep->ref_outside_mem = 1;
3005 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
3006 ep->previous_offset * INTVAL (XEXP (x, 1)));
3009 /* ... fall through ... */
3014 case DIV: case UDIV:
3015 case MOD: case UMOD:
3016 case AND: case IOR: case XOR:
3017 case ROTATERT: case ROTATE:
3018 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
3020 case GE: case GT: case GEU: case GTU:
3021 case LE: case LT: case LEU: case LTU:
3023 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3025 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
3027 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
3028 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
3033 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
3036 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3037 if (new != XEXP (x, 0))
3038 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
3041 /* ... fall through ... */
3044 /* Now do eliminations in the rest of the chain. If this was
3045 an EXPR_LIST, this might result in allocating more memory than is
3046 strictly needed, but it simplifies the code. */
3049 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
3050 if (new != XEXP (x, 1))
3051 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
3059 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3060 if (ep->to_rtx == XEXP (x, 0))
3062 int size = GET_MODE_SIZE (mem_mode);
3064 /* If more bytes than MEM_MODE are pushed, account for them. */
3065 #ifdef PUSH_ROUNDING
3066 if (ep->to_rtx == stack_pointer_rtx)
3067 size = PUSH_ROUNDING (size);
3069 if (code == PRE_DEC || code == POST_DEC)
3075 /* Fall through to generic unary operation case. */
3076 case STRICT_LOW_PART:
3078 case SIGN_EXTEND: case ZERO_EXTEND:
3079 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3080 case FLOAT: case FIX:
3081 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3085 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3086 if (new != XEXP (x, 0))
3087 return gen_rtx_fmt_e (code, GET_MODE (x), new);
3091 /* Similar to above processing, but preserve SUBREG_WORD.
3092 Convert (subreg (mem)) to (mem) if not paradoxical.
3093 Also, if we have a non-paradoxical (subreg (pseudo)) and the
3094 pseudo didn't get a hard reg, we must replace this with the
3095 eliminated version of the memory location because push_reloads
3096 may do the replacement in certain circumstances. */
3097 if (GET_CODE (SUBREG_REG (x)) == REG
3098 && (GET_MODE_SIZE (GET_MODE (x))
3099 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3100 && reg_equiv_memory_loc != 0
3101 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
3103 new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
3106 /* If we didn't change anything, we must retain the pseudo. */
3107 if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
3108 new = SUBREG_REG (x);
3111 /* In this case, we must show that the pseudo is used in this
3112 insn so that delete_output_reload will do the right thing. */
3113 if (insn != 0 && GET_CODE (insn) != EXPR_LIST
3114 && GET_CODE (insn) != INSN_LIST)
3115 REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode,
3118 = gen_rtx_EXPR_LIST (REG_EQUAL, new, NULL_RTX);
3120 /* Ensure NEW isn't shared in case we have to reload it. */
3121 new = copy_rtx (new);
3125 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
3127 if (new != XEXP (x, 0))
3129 int x_size = GET_MODE_SIZE (GET_MODE (x));
3130 int new_size = GET_MODE_SIZE (GET_MODE (new));
3132 if (GET_CODE (new) == MEM
3133 && ((x_size < new_size
3134 #ifdef WORD_REGISTER_OPERATIONS
3135 /* On these machines, combine can create rtl of the form
3136 (set (subreg:m1 (reg:m2 R) 0) ...)
3137 where m1 < m2, and expects something interesting to
3138 happen to the entire word. Moreover, it will use the
3139 (reg:m2 R) later, expecting all bits to be preserved.
3140 So if the number of words is the same, preserve the
3141 subreg so that push_reloads can see it. */
3142 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
3145 || (x_size == new_size))
3148 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
3149 enum machine_mode mode = GET_MODE (x);
3151 if (BYTES_BIG_ENDIAN)
3152 offset += (MIN (UNITS_PER_WORD,
3153 GET_MODE_SIZE (GET_MODE (new)))
3154 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
3156 PUT_MODE (new, mode);
3157 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
3161 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
3167 /* If using a register that is the source of an eliminate we still
3168 think can be performed, note it cannot be performed since we don't
3169 know how this register is used. */
3170 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3171 if (ep->from_rtx == XEXP (x, 0))
3172 ep->can_eliminate = 0;
3174 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3175 if (new != XEXP (x, 0))
3176 return gen_rtx_fmt_e (code, GET_MODE (x), new);
3180 /* If clobbering a register that is the replacement register for an
3181 elimination we still think can be performed, note that it cannot
3182 be performed. Otherwise, we need not be concerned about it. */
3183 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3184 if (ep->to_rtx == XEXP (x, 0))
3185 ep->can_eliminate = 0;
3187 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3188 if (new != XEXP (x, 0))
3189 return gen_rtx_fmt_e (code, GET_MODE (x), new);
3195 /* Properly handle sharing input and constraint vectors. */
3196 if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
3198 /* When we come to a new vector not seen before,
3199 scan all its elements; keep the old vector if none
3200 of them changes; otherwise, make a copy. */
3201 old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
3202 temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
3203 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3204 temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
3207 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3208 if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
3211 if (i == ASM_OPERANDS_INPUT_LENGTH (x))
3212 new_asm_operands_vec = old_asm_operands_vec;
3214 new_asm_operands_vec
3215 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
3218 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
3219 if (new_asm_operands_vec == old_asm_operands_vec)
3222 new = gen_rtx_ASM_OPERANDS (VOIDmode, ASM_OPERANDS_TEMPLATE (x),
3223 ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
3224 ASM_OPERANDS_OUTPUT_IDX (x),
3225 new_asm_operands_vec,
3226 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
3227 ASM_OPERANDS_SOURCE_FILE (x),
3228 ASM_OPERANDS_SOURCE_LINE (x));
3229 new->volatil = x->volatil;
3234 /* Check for setting a register that we know about. */
3235 if (GET_CODE (SET_DEST (x)) == REG)
3237 /* See if this is setting the replacement register for an
3240 If DEST is the hard frame pointer, we do nothing because we
3241 assume that all assignments to the frame pointer are for
3242 non-local gotos and are being done at a time when they are valid
3243 and do not disturb anything else. Some machines want to
3244 eliminate a fake argument pointer (or even a fake frame pointer)
3245 with either the real frame or the stack pointer. Assignments to
3246 the hard frame pointer must not prevent this elimination. */
3248 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3250 if (ep->to_rtx == SET_DEST (x)
3251 && SET_DEST (x) != hard_frame_pointer_rtx)
3253 /* If it is being incremented, adjust the offset. Otherwise,
3254 this elimination can't be done. */
3255 rtx src = SET_SRC (x);
3257 if (GET_CODE (src) == PLUS
3258 && XEXP (src, 0) == SET_DEST (x)
3259 && GET_CODE (XEXP (src, 1)) == CONST_INT)
3260 ep->offset -= INTVAL (XEXP (src, 1));
3262 ep->can_eliminate = 0;
3265 /* Now check to see we are assigning to a register that can be
3266 eliminated. If so, it must be as part of a PARALLEL, since we
3267 will not have been called if this is a single SET. So indicate
3268 that we can no longer eliminate this reg. */
3269 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3271 if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
3272 ep->can_eliminate = 0;
3275 /* Now avoid the loop below in this common case. */
3277 rtx new0 = eliminate_regs (SET_DEST (x), 0, insn);
3278 rtx new1 = eliminate_regs (SET_SRC (x), 0, insn);
3280 /* If SET_DEST changed from a REG to a MEM and INSN is an insn,
3281 write a CLOBBER insn. */
3282 if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
3283 && insn != 0 && GET_CODE (insn) != EXPR_LIST
3284 && GET_CODE (insn) != INSN_LIST)
3285 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, SET_DEST (x)), insn);
3287 if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
3288 return gen_rtx_SET (VOIDmode, new0, new1);
3294 /* This is only for the benefit of the debugging backends, which call
3295 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
3296 removed after CSE. */
3297 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
3298 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
3300 /* Our only special processing is to pass the mode of the MEM to our
3301 recursive call and copy the flags. While we are here, handle this
3302 case more efficiently. */
3303 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
3304 if (new != XEXP (x, 0))
3306 new = gen_rtx_MEM (GET_MODE (x), new);
3307 new->volatil = x->volatil;
3308 new->unchanging = x->unchanging;
3309 new->in_struct = x->in_struct;
3319 /* Process each of our operands recursively. If any have changed, make a
3321 fmt = GET_RTX_FORMAT (code);
3322 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3326 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
3327 if (new != XEXP (x, i) && ! copied)
3329 rtx new_x = rtx_alloc (code);
3330 bcopy ((char *) x, (char *) new_x,
3331 (sizeof (*new_x) - sizeof (new_x->fld)
3332 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
3338 else if (*fmt == 'E')
3341 for (j = 0; j < XVECLEN (x, i); j++)
3343 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
3344 if (new != XVECEXP (x, i, j) && ! copied_vec)
3346 rtvec new_v = gen_rtvec_vv (XVECLEN (x, i),
3350 rtx new_x = rtx_alloc (code);
3351 bcopy ((char *) x, (char *) new_x,
3352 (sizeof (*new_x) - sizeof (new_x->fld)
3353 + (sizeof (new_x->fld[0])
3354 * GET_RTX_LENGTH (code))));
3358 XVEC (x, i) = new_v;
3361 XVECEXP (x, i, j) = new;
3369 /* Scan INSN and eliminate all eliminable registers in it.
3371 If REPLACE is nonzero, do the replacement destructively. Also
3372 delete the insn as dead it if it is setting an eliminable register.
3374 If REPLACE is zero, do all our allocations in reload_obstack.
3376 If no eliminations were done and this insn doesn't require any elimination
3377 processing (these are not identical conditions: it might be updating sp,
3378 but not referencing fp; this needs to be seen during reload_as_needed so
3379 that the offset between fp and sp can be taken into consideration), zero
3380 is returned. Otherwise, 1 is returned. */
3383 eliminate_regs_in_insn (insn, replace)
3387 rtx old_body = PATTERN (insn);
3388 rtx old_set = single_set (insn);
3391 struct elim_table *ep;
3394 push_obstacks (&reload_obstack, &reload_obstack);
3396 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
3397 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3399 /* Check for setting an eliminable register. */
3400 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3401 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3403 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3404 /* If this is setting the frame pointer register to the
3405 hardware frame pointer register and this is an elimination
3406 that will be done (tested above), this insn is really
3407 adjusting the frame pointer downward to compensate for
3408 the adjustment done before a nonlocal goto. */
3409 if (ep->from == FRAME_POINTER_REGNUM
3410 && ep->to == HARD_FRAME_POINTER_REGNUM)
3412 rtx src = SET_SRC (old_set);
3414 rtx prev_insn, prev_set;
3416 if (src == ep->to_rtx)
3418 else if (GET_CODE (src) == PLUS
3419 && GET_CODE (XEXP (src, 0)) == CONST_INT)
3420 offset = INTVAL (XEXP (src, 0)), ok = 1;
3421 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
3422 && (prev_set = single_set (prev_insn)) != 0
3423 && rtx_equal_p (SET_DEST (prev_set), src))
3425 src = SET_SRC (prev_set);
3426 if (src == ep->to_rtx)
3428 else if (GET_CODE (src) == PLUS
3429 && GET_CODE (XEXP (src, 0)) == CONST_INT
3430 && XEXP (src, 1) == ep->to_rtx)
3431 offset = INTVAL (XEXP (src, 0)), ok = 1;
3432 else if (GET_CODE (src) == PLUS
3433 && GET_CODE (XEXP (src, 1)) == CONST_INT
3434 && XEXP (src, 0) == ep->to_rtx)
3435 offset = INTVAL (XEXP (src, 1)), ok = 1;
3443 = plus_constant (ep->to_rtx, offset - ep->offset);
3445 /* First see if this insn remains valid when we
3446 make the change. If not, keep the INSN_CODE
3447 the same and let reload fit it up. */
3448 validate_change (insn, &SET_SRC (old_set), src, 1);
3449 validate_change (insn, &SET_DEST (old_set),
3451 if (! apply_change_group ())
3453 SET_SRC (old_set) = src;
3454 SET_DEST (old_set) = ep->to_rtx;
3464 /* In this case this insn isn't serving a useful purpose. We
3465 will delete it in reload_as_needed once we know that this
3466 elimination is, in fact, being done.
3468 If REPLACE isn't set, we can't delete this insn, but needn't
3469 process it since it won't be used unless something changes. */
3471 delete_dead_insn (insn);
3476 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3477 in the insn is the negative of the offset in FROM. Substitute
3478 (set (reg) (reg to)) for the insn and change its code.
3480 We have to do this here, rather than in eliminate_regs, do that we can
3481 change the insn code. */
3483 if (GET_CODE (SET_SRC (old_set)) == PLUS
3484 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3485 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT)
3486 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3488 if (ep->from_rtx == XEXP (SET_SRC (old_set), 0)
3489 && ep->can_eliminate)
3491 /* We must stop at the first elimination that will be used.
3492 If this one would replace the PLUS with a REG, do it
3493 now. Otherwise, quit the loop and let eliminate_regs
3494 do its normal replacement. */
3495 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_set), 1)))
3497 /* We assume here that we don't need a PARALLEL of
3498 any CLOBBERs for this assignment. There's not
3499 much we can do if we do need it. */
3500 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3503 INSN_CODE (insn) = -1;
3512 old_asm_operands_vec = 0;
3514 /* Replace the body of this insn with a substituted form. If we changed
3515 something, return non-zero.
3517 If we are replacing a body that was a (set X (plus Y Z)), try to
3518 re-recognize the insn. We do this in case we had a simple addition
3519 but now can do this as a load-address. This saves an insn in this
3522 new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX);
3523 if (new_body != old_body)
3525 /* If we aren't replacing things permanently and we changed something,
3526 make another copy to ensure that all the RTL is new. Otherwise
3527 things can go wrong if find_reload swaps commutative operands
3528 and one is inside RTL that has been copied while the other is not. */
3530 /* Don't copy an asm_operands because (1) there's no need and (2)
3531 copy_rtx can't do it properly when there are multiple outputs. */
3532 if (! replace && asm_noperands (old_body) < 0)
3533 new_body = copy_rtx (new_body);
3535 /* If we had a move insn but now we don't, rerecognize it. This will
3536 cause spurious re-recognition if the old move had a PARALLEL since
3537 the new one still will, but we can't call single_set without
3538 having put NEW_BODY into the insn and the re-recognition won't
3539 hurt in this rare case. */
3541 && ((GET_CODE (SET_SRC (old_set)) == REG
3542 && (GET_CODE (new_body) != SET
3543 || GET_CODE (SET_SRC (new_body)) != REG))
3544 /* If this was a load from or store to memory, compare
3545 the MEM in recog_operand to the one in the insn. If they
3546 are not equal, then rerecognize the insn. */
3548 && ((GET_CODE (SET_SRC (old_set)) == MEM
3549 && SET_SRC (old_set) != recog_operand[1])
3550 || (GET_CODE (SET_DEST (old_set)) == MEM
3551 && SET_DEST (old_set) != recog_operand[0])))
3552 /* If this was an add insn before, rerecognize. */
3553 || GET_CODE (SET_SRC (old_set)) == PLUS))
3555 if (! validate_change (insn, &PATTERN (insn), new_body, 0))
3556 /* If recognition fails, store the new body anyway.
3557 It's normal to have recognition failures here
3558 due to bizarre memory addresses; reloading will fix them. */
3559 PATTERN (insn) = new_body;
3562 PATTERN (insn) = new_body;
3567 /* Loop through all elimination pairs. See if any have changed and
3568 recalculate the number not at initial offset.
3570 Compute the maximum offset (minimum offset if the stack does not
3571 grow downward) for each elimination pair.
3573 We also detect a cases where register elimination cannot be done,
3574 namely, if a register would be both changed and referenced outside a MEM
3575 in the resulting insn since such an insn is often undefined and, even if
3576 not, we cannot know what meaning will be given to it. Note that it is
3577 valid to have a register used in an address in an insn that changes it
3578 (presumably with a pre- or post-increment or decrement).
3580 If anything changes, return nonzero. */
3582 num_not_at_initial_offset = 0;
3583 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3585 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3586 ep->can_eliminate = 0;
3588 ep->ref_outside_mem = 0;
3590 if (ep->previous_offset != ep->offset)
3593 ep->previous_offset = ep->offset;
3594 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3595 num_not_at_initial_offset++;
3597 #ifdef STACK_GROWS_DOWNWARD
3598 ep->max_offset = MAX (ep->max_offset, ep->offset);
3600 ep->max_offset = MIN (ep->max_offset, ep->offset);
3605 /* If we changed something, perform elimination in REG_NOTES. This is
3606 needed even when REPLACE is zero because a REG_DEAD note might refer
3607 to a register that we eliminate and could cause a different number
3608 of spill registers to be needed in the final reload pass than in
3610 if (val && REG_NOTES (insn) != 0)
3611 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3619 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3620 replacement we currently believe is valid, mark it as not eliminable if X
3621 modifies DEST in any way other than by adding a constant integer to it.
3623 If DEST is the frame pointer, we do nothing because we assume that
3624 all assignments to the hard frame pointer are nonlocal gotos and are being
3625 done at a time when they are valid and do not disturb anything else.
3626 Some machines want to eliminate a fake argument pointer with either the
3627 frame or stack pointer. Assignments to the hard frame pointer must not
3628 prevent this elimination.
3630 Called via note_stores from reload before starting its passes to scan
3631 the insns of the function. */
3634 mark_not_eliminable (dest, x)
3640 /* A SUBREG of a hard register here is just changing its mode. We should
3641 not see a SUBREG of an eliminable hard register, but check just in
3643 if (GET_CODE (dest) == SUBREG)
3644 dest = SUBREG_REG (dest);
3646 if (dest == hard_frame_pointer_rtx)
3649 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3650 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3651 && (GET_CODE (x) != SET
3652 || GET_CODE (SET_SRC (x)) != PLUS
3653 || XEXP (SET_SRC (x), 0) != dest
3654 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3656 reg_eliminate[i].can_eliminate_previous
3657 = reg_eliminate[i].can_eliminate = 0;
3662 /* Kick all pseudos out of hard register REGNO.
3663 If GLOBAL is nonzero, try to find someplace else to put them.
3664 If DUMPFILE is nonzero, log actions taken on that file.
3666 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3667 because we found we can't eliminate some register. In the case, no pseudos
3668 are allowed to be in the register, even if they are only in a block that
3669 doesn't require spill registers, unlike the case when we are spilling this
3670 hard reg to produce another spill register.
3672 Return nonzero if any pseudos needed to be kicked out. */
3675 spill_hard_reg (regno, global, dumpfile, cant_eliminate)
3681 enum reg_class class = REGNO_REG_CLASS (regno);
3682 int something_changed = 0;
3685 SET_HARD_REG_BIT (forbidden_regs, regno);
3688 regs_ever_live[regno] = 1;
3690 /* Spill every pseudo reg that was allocated to this reg
3691 or to something that overlaps this reg. */
3693 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3694 if (reg_renumber[i] >= 0
3695 && reg_renumber[i] <= regno
3697 + HARD_REGNO_NREGS (reg_renumber[i],
3698 PSEUDO_REGNO_MODE (i))
3701 /* If this register belongs solely to a basic block which needed no
3702 spilling of any class that this register is contained in,
3703 leave it be, unless we are spilling this register because
3704 it was a hard register that can't be eliminated. */
3706 if (! cant_eliminate
3707 && basic_block_needs[0]
3708 && REG_BASIC_BLOCK (i) >= 0
3709 && basic_block_needs[(int) class][REG_BASIC_BLOCK (i)] == 0)
3713 for (p = reg_class_superclasses[(int) class];
3714 *p != LIM_REG_CLASSES; p++)
3715 if (basic_block_needs[(int) *p][REG_BASIC_BLOCK (i)] > 0)
3718 if (*p == LIM_REG_CLASSES)
3722 /* Mark it as no longer having a hard register home. */
3723 reg_renumber[i] = -1;
3724 /* We will need to scan everything again. */
3725 something_changed = 1;
3727 retry_global_alloc (i, forbidden_regs);
3729 alter_reg (i, regno);
3732 if (reg_renumber[i] == -1)
3733 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3735 fprintf (dumpfile, " Register %d now in %d.\n\n",
3736 i, reg_renumber[i]);
3739 for (i = 0; i < scratch_list_length; i++)
3742 && regno >= REGNO (scratch_list[i])
3743 && regno < REGNO (scratch_list[i])
3744 + HARD_REGNO_NREGS (REGNO (scratch_list[i]),
3745 GET_MODE (scratch_list[i])))
3747 if (! cant_eliminate && basic_block_needs[0]
3748 && ! basic_block_needs[(int) class][scratch_block[i]])
3752 for (p = reg_class_superclasses[(int) class];
3753 *p != LIM_REG_CLASSES; p++)
3754 if (basic_block_needs[(int) *p][scratch_block[i]] > 0)
3757 if (*p == LIM_REG_CLASSES)
3760 PUT_CODE (scratch_list[i], SCRATCH);
3761 scratch_list[i] = 0;
3762 something_changed = 1;
3767 return something_changed;
3770 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3771 Also mark any hard registers used to store user variables as
3772 forbidden from being used for spill registers. */
3775 scan_paradoxical_subregs (x)
3780 register enum rtx_code code = GET_CODE (x);
3785 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3786 && REG_USERVAR_P (x))
3787 SET_HARD_REG_BIT (forbidden_regs, REGNO (x));
3802 if (GET_CODE (SUBREG_REG (x)) == REG
3803 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3804 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3805 = GET_MODE_SIZE (GET_MODE (x));
3812 fmt = GET_RTX_FORMAT (code);
3813 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3816 scan_paradoxical_subregs (XEXP (x, i));
3817 else if (fmt[i] == 'E')
3820 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3821 scan_paradoxical_subregs (XVECEXP (x, i, j));
3827 hard_reg_use_compare (p1p, p2p)
3828 const GENERIC_PTR p1p;
3829 const GENERIC_PTR p2p;
3831 struct hard_reg_n_uses *p1 = (struct hard_reg_n_uses *)p1p,
3832 *p2 = (struct hard_reg_n_uses *)p2p;
3833 int tem = p1->uses - p2->uses;
3834 if (tem != 0) return tem;
3835 /* If regs are equally good, sort by regno,
3836 so that the results of qsort leave nothing to chance. */
3837 return p1->regno - p2->regno;
3840 /* Choose the order to consider regs for use as reload registers
3841 based on how much trouble would be caused by spilling one.
3842 Store them in order of decreasing preference in potential_reload_regs. */
3845 order_regs_for_reload (global)
3852 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
3854 CLEAR_HARD_REG_SET (bad_spill_regs);
3856 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3857 potential_reload_regs[i] = -1;
3859 /* Count number of uses of each hard reg by pseudo regs allocated to it
3860 and then order them by decreasing use. */
3862 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3864 hard_reg_n_uses[i].uses = 0;
3865 hard_reg_n_uses[i].regno = i;
3868 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3870 int regno = reg_renumber[i];
3873 int lim = regno + HARD_REGNO_NREGS (regno, PSEUDO_REGNO_MODE (i));
3876 /* If allocated by local-alloc, show more uses since
3877 we're not going to be able to reallocate it, but
3878 we might if allocated by global alloc. */
3879 if (global && reg_allocno[i] < 0)
3880 hard_reg_n_uses[regno].uses += (REG_N_REFS (i) + 1) / 2;
3882 hard_reg_n_uses[regno++].uses += REG_N_REFS (i);
3885 large += REG_N_REFS (i);
3888 /* Now fixed registers (which cannot safely be used for reloading)
3889 get a very high use count so they will be considered least desirable.
3890 Registers used explicitly in the rtl code are almost as bad. */
3892 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3896 hard_reg_n_uses[i].uses += 2 * large + 2;
3897 SET_HARD_REG_BIT (bad_spill_regs, i);
3899 else if (regs_explicitly_used[i])
3901 hard_reg_n_uses[i].uses += large + 1;
3902 if (! SMALL_REGISTER_CLASSES)
3903 /* ??? We are doing this here because of the potential
3904 that bad code may be generated if a register explicitly
3905 used in an insn was used as a spill register for that
3906 insn. But not using these are spill registers may lose
3907 on some machine. We'll have to see how this works out. */
3908 SET_HARD_REG_BIT (bad_spill_regs, i);
3911 hard_reg_n_uses[HARD_FRAME_POINTER_REGNUM].uses += 2 * large + 2;
3912 SET_HARD_REG_BIT (bad_spill_regs, HARD_FRAME_POINTER_REGNUM);
3914 #ifdef ELIMINABLE_REGS
3915 /* If registers other than the frame pointer are eliminable, mark them as
3917 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3919 hard_reg_n_uses[reg_eliminate[i].from].uses += 2 * large + 2;
3920 SET_HARD_REG_BIT (bad_spill_regs, reg_eliminate[i].from);
3924 /* Prefer registers not so far used, for use in temporary loading.
3925 Among them, if REG_ALLOC_ORDER is defined, use that order.
3926 Otherwise, prefer registers not preserved by calls. */
3928 #ifdef REG_ALLOC_ORDER
3929 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3931 int regno = reg_alloc_order[i];
3933 if (hard_reg_n_uses[regno].uses == 0)
3934 potential_reload_regs[o++] = regno;
3937 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3939 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i])
3940 potential_reload_regs[o++] = i;
3942 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3944 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i])
3945 potential_reload_regs[o++] = i;
3949 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
3950 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
3952 /* Now add the regs that are already used,
3953 preferring those used less often. The fixed and otherwise forbidden
3954 registers will be at the end of this list. */
3956 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3957 if (hard_reg_n_uses[i].uses != 0)
3958 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
3961 /* Used in reload_as_needed to sort the spilled regs. */
3964 compare_spill_regs (r1p, r2p)
3965 const GENERIC_PTR r1p;
3966 const GENERIC_PTR r2p;
3968 short r1 = *(short *)r1p, r2 = *(short *)r2p;
3972 /* Reload pseudo-registers into hard regs around each insn as needed.
3973 Additional register load insns are output before the insn that needs it
3974 and perhaps store insns after insns that modify the reloaded pseudo reg.
3976 reg_last_reload_reg and reg_reloaded_contents keep track of
3977 which registers are already available in reload registers.
3978 We update these for the reloads that we perform,
3979 as the insns are scanned. */
3982 reload_as_needed (first, live_known)
3992 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
3993 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
3994 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
3995 bzero ((char *) reg_last_reload_reg, max_regno * sizeof (rtx));
3996 reg_has_output_reload = (char *) alloca (max_regno);
3997 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3999 /* Reset all offsets on eliminable registers to their initial values. */
4000 #ifdef ELIMINABLE_REGS
4001 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
4003 INITIAL_ELIMINATION_OFFSET (reg_eliminate[i].from, reg_eliminate[i].to,
4004 reg_eliminate[i].initial_offset);
4005 reg_eliminate[i].previous_offset
4006 = reg_eliminate[i].offset = reg_eliminate[i].initial_offset;
4009 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
4010 reg_eliminate[0].previous_offset
4011 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
4014 num_not_at_initial_offset = 0;
4016 /* Order the spilled regs, so that allocate_reload_regs can guarantee to
4017 pack registers with group needs. */
4020 qsort (spill_regs, n_spills, sizeof (short), compare_spill_regs);
4021 for (i = 0; i < n_spills; i++)
4022 spill_reg_order[spill_regs[i]] = i;
4025 for (insn = first; insn;)
4027 register rtx next = NEXT_INSN (insn);
4029 /* Notice when we move to a new basic block. */
4030 if (live_known && this_block + 1 < n_basic_blocks
4031 && insn == basic_block_head[this_block+1])
4034 /* If we pass a label, copy the offsets from the label information
4035 into the current offsets of each elimination. */
4036 if (GET_CODE (insn) == CODE_LABEL)
4038 num_not_at_initial_offset = 0;
4039 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
4041 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
4042 = offsets_at[CODE_LABEL_NUMBER (insn)][i];
4043 if (reg_eliminate[i].can_eliminate
4044 && (reg_eliminate[i].offset
4045 != reg_eliminate[i].initial_offset))
4046 num_not_at_initial_offset++;
4050 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
4052 rtx avoid_return_reg = 0;
4053 rtx oldpat = PATTERN (insn);
4055 /* Set avoid_return_reg if this is an insn
4056 that might use the value of a function call. */
4057 if (SMALL_REGISTER_CLASSES && GET_CODE (insn) == CALL_INSN)
4059 if (GET_CODE (PATTERN (insn)) == SET)
4060 after_call = SET_DEST (PATTERN (insn));
4061 else if (GET_CODE (PATTERN (insn)) == PARALLEL
4062 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
4063 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
4067 else if (SMALL_REGISTER_CLASSES && after_call != 0
4068 && !(GET_CODE (PATTERN (insn)) == SET
4069 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx)
4070 && GET_CODE (PATTERN (insn)) != USE)
4072 if (reg_referenced_p (after_call, PATTERN (insn)))
4073 avoid_return_reg = after_call;
4077 /* If this is a USE and CLOBBER of a MEM, ensure that any
4078 references to eliminable registers have been removed. */
4080 if ((GET_CODE (PATTERN (insn)) == USE
4081 || GET_CODE (PATTERN (insn)) == CLOBBER)
4082 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
4083 XEXP (XEXP (PATTERN (insn), 0), 0)
4084 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4085 GET_MODE (XEXP (PATTERN (insn), 0)),
4088 /* If we need to do register elimination processing, do so.
4089 This might delete the insn, in which case we are done. */
4090 if (num_eliminable && GET_MODE (insn) == QImode)
4092 eliminate_regs_in_insn (insn, 1);
4093 if (GET_CODE (insn) == NOTE)
4100 if (GET_MODE (insn) == VOIDmode)
4102 /* First find the pseudo regs that must be reloaded for this insn.
4103 This info is returned in the tables reload_... (see reload.h).
4104 Also modify the body of INSN by substituting RELOAD
4105 rtx's for those pseudo regs. */
4108 bzero (reg_has_output_reload, max_regno);
4109 CLEAR_HARD_REG_SET (reg_is_output_reload);
4111 find_reloads (insn, 1, spill_indirect_levels, live_known,
4117 rtx prev = PREV_INSN (insn), next = NEXT_INSN (insn);
4121 /* If this block has not had spilling done for a
4122 particular clas and we have any non-optionals that need a
4123 spill reg in that class, abort. */
4125 for (class = 0; class < N_REG_CLASSES; class++)
4126 if (basic_block_needs[class] != 0
4127 && basic_block_needs[class][this_block] == 0)
4128 for (i = 0; i < n_reloads; i++)
4129 if (class == (int) reload_reg_class[i]
4130 && reload_reg_rtx[i] == 0
4131 && ! reload_optional[i]
4132 && (reload_in[i] != 0 || reload_out[i] != 0
4133 || reload_secondary_p[i] != 0))
4134 fatal_insn ("Non-optional registers need a spill register", insn);
4136 /* Now compute which reload regs to reload them into. Perhaps
4137 reusing reload regs from previous insns, or else output
4138 load insns to reload them. Maybe output store insns too.
4139 Record the choices of reload reg in reload_reg_rtx. */
4140 choose_reload_regs (insn, avoid_return_reg);
4142 /* Merge any reloads that we didn't combine for fear of
4143 increasing the number of spill registers needed but now
4144 discover can be safely merged. */
4145 if (SMALL_REGISTER_CLASSES)
4146 merge_assigned_reloads (insn);
4148 /* Generate the insns to reload operands into or out of
4149 their reload regs. */
4150 emit_reload_insns (insn);
4152 /* Substitute the chosen reload regs from reload_reg_rtx
4153 into the insn's body (or perhaps into the bodies of other
4154 load and store insn that we just made for reloading
4155 and that we moved the structure into). */
4158 /* If this was an ASM, make sure that all the reload insns
4159 we have generated are valid. If not, give an error
4162 if (asm_noperands (PATTERN (insn)) >= 0)
4163 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4164 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
4165 && (recog_memoized (p) < 0
4166 || (insn_extract (p),
4167 ! constrain_operands (INSN_CODE (p), 1))))
4169 error_for_asm (insn,
4170 "`asm' operand requires impossible reload");
4172 NOTE_SOURCE_FILE (p) = 0;
4173 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
4176 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4177 is no longer validly lying around to save a future reload.
4178 Note that this does not detect pseudos that were reloaded
4179 for this insn in order to be stored in
4180 (obeying register constraints). That is correct; such reload
4181 registers ARE still valid. */
4182 note_stores (oldpat, forget_old_reloads_1);
4184 /* There may have been CLOBBER insns placed after INSN. So scan
4185 between INSN and NEXT and use them to forget old reloads. */
4186 for (x = NEXT_INSN (insn); x != next; x = NEXT_INSN (x))
4187 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
4188 note_stores (PATTERN (x), forget_old_reloads_1);
4191 /* Likewise for regs altered by auto-increment in this insn.
4192 But note that the reg-notes are not changed by reloading:
4193 they still contain the pseudo-regs, not the spill regs. */
4194 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4195 if (REG_NOTE_KIND (x) == REG_INC)
4197 /* See if this pseudo reg was reloaded in this insn.
4198 If so, its last-reload info is still valid
4199 because it is based on this insn's reload. */
4200 for (i = 0; i < n_reloads; i++)
4201 if (reload_out[i] == XEXP (x, 0))
4205 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX);
4209 /* A reload reg's contents are unknown after a label. */
4210 if (GET_CODE (insn) == CODE_LABEL)
4211 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4213 /* Don't assume a reload reg is still good after a call insn
4214 if it is a call-used reg. */
4215 else if (GET_CODE (insn) == CALL_INSN)
4216 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
4218 /* In case registers overlap, allow certain insns to invalidate
4219 particular hard registers. */
4221 #ifdef INSN_CLOBBERS_REGNO_P
4222 for (i = 0 ; i < FIRST_PSEUDO_REGISTER; i++)
4223 if (TEST_HARD_REG_BIT (reg_reloaded_valid, i)
4224 && INSN_CLOBBERS_REGNO_P (insn, i))
4225 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i);
4236 /* Discard all record of any value reloaded from X,
4237 or reloaded in X from someplace else;
4238 unless X is an output reload reg of the current insn.
4240 X may be a hard reg (the reload reg)
4241 or it may be a pseudo reg that was reloaded from. */
4244 forget_old_reloads_1 (x, ignored)
4246 rtx ignored ATTRIBUTE_UNUSED;
4252 /* note_stores does give us subregs of hard regs. */
4253 while (GET_CODE (x) == SUBREG)
4255 offset += SUBREG_WORD (x);
4259 if (GET_CODE (x) != REG)
4262 regno = REGNO (x) + offset;
4264 if (regno >= FIRST_PSEUDO_REGISTER)
4269 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4270 /* Storing into a spilled-reg invalidates its contents.
4271 This can happen if a block-local pseudo is allocated to that reg
4272 and it wasn't spilled because this block's total need is 0.
4273 Then some insn might have an optional reload and use this reg. */
4274 for (i = 0; i < nr; i++)
4275 /* But don't do this if the reg actually serves as an output
4276 reload reg in the current instruction. */
4278 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4279 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4282 /* Since value of X has changed,
4283 forget any value previously copied from it. */
4286 /* But don't forget a copy if this is the output reload
4287 that establishes the copy's validity. */
4288 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4289 reg_last_reload_reg[regno + nr] = 0;
4292 /* For each reload, the mode of the reload register. */
4293 static enum machine_mode reload_mode[MAX_RELOADS];
4295 /* For each reload, the largest number of registers it will require. */
4296 static int reload_nregs[MAX_RELOADS];
4298 /* Comparison function for qsort to decide which of two reloads
4299 should be handled first. *P1 and *P2 are the reload numbers. */
4302 reload_reg_class_lower (r1p, r2p)
4303 const GENERIC_PTR r1p;
4304 const GENERIC_PTR r2p;
4306 register int r1 = *(short *)r1p, r2 = *(short *)r2p;
4309 /* Consider required reloads before optional ones. */
4310 t = reload_optional[r1] - reload_optional[r2];
4314 /* Count all solitary classes before non-solitary ones. */
4315 t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
4316 - (reg_class_size[(int) reload_reg_class[r1]] == 1));
4320 /* Aside from solitaires, consider all multi-reg groups first. */
4321 t = reload_nregs[r2] - reload_nregs[r1];
4325 /* Consider reloads in order of increasing reg-class number. */
4326 t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
4330 /* If reloads are equally urgent, sort by reload number,
4331 so that the results of qsort leave nothing to chance. */
4335 /* The following HARD_REG_SETs indicate when each hard register is
4336 used for a reload of various parts of the current insn. */
4338 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4339 static HARD_REG_SET reload_reg_used;
4340 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4341 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4342 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4343 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4344 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4345 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4346 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4347 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4348 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4349 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4350 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4351 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4352 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4353 static HARD_REG_SET reload_reg_used_in_op_addr;
4354 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4355 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4356 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4357 static HARD_REG_SET reload_reg_used_in_insn;
4358 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4359 static HARD_REG_SET reload_reg_used_in_other_addr;
4361 /* If reg is in use as a reload reg for any sort of reload. */
4362 static HARD_REG_SET reload_reg_used_at_all;
4364 /* If reg is use as an inherited reload. We just mark the first register
4366 static HARD_REG_SET reload_reg_used_for_inherit;
4368 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4369 TYPE. MODE is used to indicate how many consecutive regs are
4373 mark_reload_reg_in_use (regno, opnum, type, mode)
4376 enum reload_type type;
4377 enum machine_mode mode;
4379 int nregs = HARD_REGNO_NREGS (regno, mode);
4382 for (i = regno; i < nregs + regno; i++)
4387 SET_HARD_REG_BIT (reload_reg_used, i);
4390 case RELOAD_FOR_INPUT_ADDRESS:
4391 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4394 case RELOAD_FOR_INPADDR_ADDRESS:
4395 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4398 case RELOAD_FOR_OUTPUT_ADDRESS:
4399 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4402 case RELOAD_FOR_OUTADDR_ADDRESS:
4403 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4406 case RELOAD_FOR_OPERAND_ADDRESS:
4407 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4410 case RELOAD_FOR_OPADDR_ADDR:
4411 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4414 case RELOAD_FOR_OTHER_ADDRESS:
4415 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4418 case RELOAD_FOR_INPUT:
4419 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4422 case RELOAD_FOR_OUTPUT:
4423 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4426 case RELOAD_FOR_INSN:
4427 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4431 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4435 /* Similarly, but show REGNO is no longer in use for a reload. */
4438 clear_reload_reg_in_use (regno, opnum, type, mode)
4441 enum reload_type type;
4442 enum machine_mode mode;
4444 int nregs = HARD_REGNO_NREGS (regno, mode);
4447 for (i = regno; i < nregs + regno; i++)
4452 CLEAR_HARD_REG_BIT (reload_reg_used, i);
4455 case RELOAD_FOR_INPUT_ADDRESS:
4456 CLEAR_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4459 case RELOAD_FOR_INPADDR_ADDRESS:
4460 CLEAR_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4463 case RELOAD_FOR_OUTPUT_ADDRESS:
4464 CLEAR_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4467 case RELOAD_FOR_OUTADDR_ADDRESS:
4468 CLEAR_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4471 case RELOAD_FOR_OPERAND_ADDRESS:
4472 CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4475 case RELOAD_FOR_OPADDR_ADDR:
4476 CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4479 case RELOAD_FOR_OTHER_ADDRESS:
4480 CLEAR_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4483 case RELOAD_FOR_INPUT:
4484 CLEAR_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4487 case RELOAD_FOR_OUTPUT:
4488 CLEAR_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4491 case RELOAD_FOR_INSN:
4492 CLEAR_HARD_REG_BIT (reload_reg_used_in_insn, i);
4498 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4499 specified by OPNUM and TYPE. */
4502 reload_reg_free_p (regno, opnum, type)
4505 enum reload_type type;
4509 /* In use for a RELOAD_OTHER means it's not available for anything. */
4510 if (TEST_HARD_REG_BIT (reload_reg_used, regno))
4516 /* In use for anything means we can't use it for RELOAD_OTHER. */
4517 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4518 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4519 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4522 for (i = 0; i < reload_n_operands; i++)
4523 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4524 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4525 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4526 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4527 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4528 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4533 case RELOAD_FOR_INPUT:
4534 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4535 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4538 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4541 /* If it is used for some other input, can't use it. */
4542 for (i = 0; i < reload_n_operands; i++)
4543 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4546 /* If it is used in a later operand's address, can't use it. */
4547 for (i = opnum + 1; i < reload_n_operands; i++)
4548 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4549 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4554 case RELOAD_FOR_INPUT_ADDRESS:
4555 /* Can't use a register if it is used for an input address for this
4556 operand or used as an input in an earlier one. */
4557 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4558 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4561 for (i = 0; i < opnum; i++)
4562 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4567 case RELOAD_FOR_INPADDR_ADDRESS:
4568 /* Can't use a register if it is used for an input address
4569 for this operand or used as an input in an earlier
4571 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4574 for (i = 0; i < opnum; i++)
4575 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4580 case RELOAD_FOR_OUTPUT_ADDRESS:
4581 /* Can't use a register if it is used for an output address for this
4582 operand or used as an output in this or a later operand. */
4583 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4586 for (i = opnum; i < reload_n_operands; i++)
4587 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4592 case RELOAD_FOR_OUTADDR_ADDRESS:
4593 /* Can't use a register if it is used for an output address
4594 for this operand or used as an output in this or a
4596 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4599 for (i = opnum; i < reload_n_operands; i++)
4600 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4605 case RELOAD_FOR_OPERAND_ADDRESS:
4606 for (i = 0; i < reload_n_operands; i++)
4607 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4610 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4611 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4613 case RELOAD_FOR_OPADDR_ADDR:
4614 for (i = 0; i < reload_n_operands; i++)
4615 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4618 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4620 case RELOAD_FOR_OUTPUT:
4621 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4622 outputs, or an operand address for this or an earlier output. */
4623 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4626 for (i = 0; i < reload_n_operands; i++)
4627 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4630 for (i = 0; i <= opnum; i++)
4631 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4632 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4637 case RELOAD_FOR_INSN:
4638 for (i = 0; i < reload_n_operands; i++)
4639 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4640 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4643 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4644 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4646 case RELOAD_FOR_OTHER_ADDRESS:
4647 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4652 /* Return 1 if the value in reload reg REGNO, as used by a reload
4653 needed for the part of the insn specified by OPNUM and TYPE,
4654 is not in use for a reload in any prior part of the insn.
4656 We can assume that the reload reg was already tested for availability
4657 at the time it is needed, and we should not check this again,
4658 in case the reg has already been marked in use. */
4661 reload_reg_free_before_p (regno, opnum, type)
4664 enum reload_type type;
4670 case RELOAD_FOR_OTHER_ADDRESS:
4671 /* These always come first. */
4675 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4677 /* If this use is for part of the insn,
4678 check the reg is not in use for any prior part. It is tempting
4679 to try to do this by falling through from objecs that occur
4680 later in the insn to ones that occur earlier, but that will not
4681 correctly take into account the fact that here we MUST ignore
4682 things that would prevent the register from being allocated in
4683 the first place, since we know that it was allocated. */
4685 case RELOAD_FOR_OUTPUT_ADDRESS:
4686 /* Earlier reloads include RELOAD_FOR_OUTADDR_ADDRESS reloads. */
4687 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4689 /* ... fall through ... */
4690 case RELOAD_FOR_OUTADDR_ADDRESS:
4691 /* Earlier reloads are for earlier outputs or their addresses,
4692 any RELOAD_FOR_INSN reloads, any inputs or their addresses, or any
4693 RELOAD_FOR_OTHER_ADDRESS reloads (we know it can't conflict with
4695 for (i = 0; i < opnum; i++)
4696 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4697 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4698 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4701 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4704 for (i = 0; i < reload_n_operands; i++)
4705 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4706 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4707 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4710 return (! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4711 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4712 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4713 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4715 case RELOAD_FOR_OUTPUT:
4716 /* There is no reason to call this function for output reloads, thus
4717 anything we'd put here wouldn't be tested. So just abort. */
4720 case RELOAD_FOR_OPERAND_ADDRESS:
4721 /* Earlier reloads include RELOAD_FOR_OPADDR_ADDR reloads. */
4722 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4725 /* ... fall through ... */
4727 case RELOAD_FOR_OPADDR_ADDR:
4728 case RELOAD_FOR_INSN:
4729 /* These can't conflict with inputs, or each other, so all we have to
4730 test is input addresses and the addresses of OTHER items. */
4732 for (i = 0; i < reload_n_operands; i++)
4733 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4734 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4737 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4739 case RELOAD_FOR_INPUT:
4740 /* The only things earlier are the address for this and
4741 earlier inputs, other inputs (which we know we don't conflict
4742 with), and addresses of RELOAD_OTHER objects. */
4744 for (i = 0; i <= opnum; i++)
4745 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4746 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4749 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4751 case RELOAD_FOR_INPUT_ADDRESS:
4752 /* Earlier reloads include RELOAD_FOR_INPADDR_ADDRESS reloads. */
4753 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4755 /* ... fall through ... */
4756 case RELOAD_FOR_INPADDR_ADDRESS:
4757 /* Similarly, all we have to check is for use in earlier inputs'
4759 for (i = 0; i < opnum; i++)
4760 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4761 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4764 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4769 /* Return 1 if the value in reload reg REGNO, as used by a reload
4770 needed for the part of the insn specified by OPNUM and TYPE,
4771 is still available in REGNO at the end of the insn.
4773 We can assume that the reload reg was already tested for availability
4774 at the time it is needed, and we should not check this again,
4775 in case the reg has already been marked in use. */
4778 reload_reg_reaches_end_p (regno, opnum, type)
4781 enum reload_type type;
4788 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4789 its value must reach the end. */
4792 /* If this use is for part of the insn,
4793 its value reaches if no subsequent part uses the same register.
4794 Just like the above function, don't try to do this with lots
4797 case RELOAD_FOR_OTHER_ADDRESS:
4798 /* Here we check for everything else, since these don't conflict
4799 with anything else and everything comes later. */
4801 for (i = 0; i < reload_n_operands; i++)
4802 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4803 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4804 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4805 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4806 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4807 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4810 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4811 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4812 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4814 case RELOAD_FOR_INPUT_ADDRESS:
4815 case RELOAD_FOR_INPADDR_ADDRESS:
4816 /* Similar, except that we check only for this and subsequent inputs
4817 and the address of only subsequent inputs and we do not need
4818 to check for RELOAD_OTHER objects since they are known not to
4821 for (i = opnum; i < reload_n_operands; i++)
4822 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4825 for (i = opnum + 1; i < reload_n_operands; i++)
4826 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4827 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4830 for (i = 0; i < reload_n_operands; i++)
4831 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4832 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4833 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4836 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4839 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4840 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4842 case RELOAD_FOR_INPUT:
4843 /* Similar to input address, except we start at the next operand for
4844 both input and input address and we do not check for
4845 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4848 for (i = opnum + 1; i < reload_n_operands; i++)
4849 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4850 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4851 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4854 /* ... fall through ... */
4856 case RELOAD_FOR_OPERAND_ADDRESS:
4857 /* Check outputs and their addresses. */
4859 for (i = 0; i < reload_n_operands; i++)
4860 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4861 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4862 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4867 case RELOAD_FOR_OPADDR_ADDR:
4868 for (i = 0; i < reload_n_operands; i++)
4869 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4870 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4871 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4874 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4875 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4877 case RELOAD_FOR_INSN:
4878 /* These conflict with other outputs with RELOAD_OTHER. So
4879 we need only check for output addresses. */
4883 /* ... fall through ... */
4885 case RELOAD_FOR_OUTPUT:
4886 case RELOAD_FOR_OUTPUT_ADDRESS:
4887 case RELOAD_FOR_OUTADDR_ADDRESS:
4888 /* We already know these can't conflict with a later output. So the
4889 only thing to check are later output addresses. */
4890 for (i = opnum + 1; i < reload_n_operands; i++)
4891 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4892 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4901 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4904 This function uses the same algorithm as reload_reg_free_p above. */
4907 reloads_conflict (r1, r2)
4910 enum reload_type r1_type = reload_when_needed[r1];
4911 enum reload_type r2_type = reload_when_needed[r2];
4912 int r1_opnum = reload_opnum[r1];
4913 int r2_opnum = reload_opnum[r2];
4915 /* RELOAD_OTHER conflicts with everything. */
4916 if (r2_type == RELOAD_OTHER)
4919 /* Otherwise, check conflicts differently for each type. */
4923 case RELOAD_FOR_INPUT:
4924 return (r2_type == RELOAD_FOR_INSN
4925 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4926 || r2_type == RELOAD_FOR_OPADDR_ADDR
4927 || r2_type == RELOAD_FOR_INPUT
4928 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4929 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4930 && r2_opnum > r1_opnum));
4932 case RELOAD_FOR_INPUT_ADDRESS:
4933 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4934 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4936 case RELOAD_FOR_INPADDR_ADDRESS:
4937 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4938 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4940 case RELOAD_FOR_OUTPUT_ADDRESS:
4941 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4942 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4944 case RELOAD_FOR_OUTADDR_ADDRESS:
4945 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4946 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4948 case RELOAD_FOR_OPERAND_ADDRESS:
4949 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4950 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4952 case RELOAD_FOR_OPADDR_ADDR:
4953 return (r2_type == RELOAD_FOR_INPUT
4954 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4956 case RELOAD_FOR_OUTPUT:
4957 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4958 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4959 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4960 && r2_opnum >= r1_opnum));
4962 case RELOAD_FOR_INSN:
4963 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4964 || r2_type == RELOAD_FOR_INSN
4965 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4967 case RELOAD_FOR_OTHER_ADDRESS:
4968 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4978 /* Vector of reload-numbers showing the order in which the reloads should
4980 short reload_order[MAX_RELOADS];
4982 /* Indexed by reload number, 1 if incoming value
4983 inherited from previous insns. */
4984 char reload_inherited[MAX_RELOADS];
4986 /* For an inherited reload, this is the insn the reload was inherited from,
4987 if we know it. Otherwise, this is 0. */
4988 rtx reload_inheritance_insn[MAX_RELOADS];
4990 /* If non-zero, this is a place to get the value of the reload,
4991 rather than using reload_in. */
4992 rtx reload_override_in[MAX_RELOADS];
4994 /* For each reload, the hard register number of the register used,
4995 or -1 if we did not need a register for this reload. */
4996 int reload_spill_index[MAX_RELOADS];
4998 /* Return 1 if the value in reload reg REGNO, as used by a reload
4999 needed for the part of the insn specified by OPNUM and TYPE,
5000 may be used to load VALUE into it.
5002 Other read-only reloads with the same value do not conflict
5003 unless OUT is non-zero and these other reloads have to live while
5004 output reloads live.
5006 RELOADNUM is the number of the reload we want to load this value for;
5007 a reload does not conflict with itself.
5009 The caller has to make sure that there is no conflict with the return
5012 reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum)
5015 enum reload_type type;
5022 /* We use some pseudo 'time' value to check if the lifetimes of the
5023 new register use would overlap with the one of a previous reload
5024 that is not read-only or uses a different value.
5025 The 'time' used doesn't have to be linear in any shape or form, just
5027 Some reload types use different 'buckets' for each operand.
5028 So there are MAX_RECOG_OPERANDS different time values for each
5030 We compute TIME1 as the time when the register for the prospective
5031 new reload ceases to be live, and TIME2 for each existing
5032 reload as the time when that the reload register of that reload
5034 Where there is little to be gained by exact lifetime calculations,
5035 we just make conservative assumptions, i.e. a longer lifetime;
5036 this is done in the 'default:' cases. */
5039 case RELOAD_FOR_OTHER_ADDRESS:
5042 /* For each input, we might have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5043 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5044 respectively, to the time values for these, we get distinct time
5045 values. To get distinct time values for each operand, we have to
5046 multiply opnum by at least three. We round that up to four because
5047 multiply by four is often cheaper. */
5048 case RELOAD_FOR_INPADDR_ADDRESS:
5049 time1 = opnum * 4 + 1;
5051 case RELOAD_FOR_INPUT_ADDRESS:
5052 time1 = opnum * 4 + 2;
5054 case RELOAD_FOR_INPUT:
5055 /* All RELOAD_FOR_INPUT reloads remain live till just before the
5056 instruction is executed. */
5057 time1 = (MAX_RECOG_OPERANDS - 1) * 4 + 3;
5059 /* opnum * 4 + 3 < opnum * 4 + 4
5060 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5061 case RELOAD_FOR_OUTPUT_ADDRESS:
5062 time1 = MAX_RECOG_OPERANDS * 4 + opnum;
5065 time1 = MAX_RECOG_OPERANDS * 5;
5068 for (i = 0; i < n_reloads; i++)
5070 rtx reg = reload_reg_rtx[i];
5071 if (reg && GET_CODE (reg) == REG
5072 && ((unsigned) regno - true_regnum (reg)
5073 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
5077 && reload_when_needed[i] != RELOAD_FOR_INPUT
5078 && reload_when_needed[i] != RELOAD_FOR_INPUT_ADDRESS
5079 && reload_when_needed[i] != RELOAD_FOR_INPADDR_ADDRESS)
5081 if (! reload_in[i] || ! rtx_equal_p (reload_in[i], value)
5085 switch (reload_when_needed[i])
5087 case RELOAD_FOR_OTHER_ADDRESS:
5090 case RELOAD_FOR_INPADDR_ADDRESS:
5091 time2 = reload_opnum[i] * 4 + 1;
5093 case RELOAD_FOR_INPUT_ADDRESS:
5094 time2 = reload_opnum[i] * 4 + 2;
5096 case RELOAD_FOR_INPUT:
5097 time2 = reload_opnum[i] * 4 + 3;
5099 case RELOAD_FOR_OUTPUT:
5100 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5101 instruction is executed. */
5102 time2 = MAX_RECOG_OPERANDS * 4;
5104 /* The first RELOAD_FOR_OUTPUT_ADDRESS reload conflicts with the
5105 RELOAD_FOR_OUTPUT reloads, so assign it the same time value. */
5106 case RELOAD_FOR_OUTPUT_ADDRESS:
5107 time2 = MAX_RECOG_OPERANDS * 4 + reload_opnum[i];
5110 if (! reload_in[i] || rtx_equal_p (reload_in[i], value))
5112 time2 = MAX_RECOG_OPERANDS * 4;
5126 /* Find a spill register to use as a reload register for reload R.
5127 LAST_RELOAD is non-zero if this is the last reload for the insn being
5130 Set reload_reg_rtx[R] to the register allocated.
5132 If NOERROR is nonzero, we return 1 if successful,
5133 or 0 if we couldn't find a spill reg and we didn't change anything. */
5136 allocate_reload_reg (r, insn, last_reload, noerror)
5148 /* If we put this reload ahead, thinking it is a group,
5149 then insist on finding a group. Otherwise we can grab a
5150 reg that some other reload needs.
5151 (That can happen when we have a 68000 DATA_OR_FP_REG
5152 which is a group of data regs or one fp reg.)
5153 We need not be so restrictive if there are no more reloads
5156 ??? Really it would be nicer to have smarter handling
5157 for that kind of reg class, where a problem like this is normal.
5158 Perhaps those classes should be avoided for reloading
5159 by use of more alternatives. */
5161 int force_group = reload_nregs[r] > 1 && ! last_reload;
5163 /* If we want a single register and haven't yet found one,
5164 take any reg in the right class and not in use.
5165 If we want a consecutive group, here is where we look for it.
5167 We use two passes so we can first look for reload regs to
5168 reuse, which are already in use for other reloads in this insn,
5169 and only then use additional registers.
5170 I think that maximizing reuse is needed to make sure we don't
5171 run out of reload regs. Suppose we have three reloads, and
5172 reloads A and B can share regs. These need two regs.
5173 Suppose A and B are given different regs.
5174 That leaves none for C. */
5175 for (pass = 0; pass < 2; pass++)
5177 /* I is the index in spill_regs.
5178 We advance it round-robin between insns to use all spill regs
5179 equally, so that inherited reloads have a chance
5180 of leapfrogging each other. Don't do this, however, when we have
5181 group needs and failure would be fatal; if we only have a relatively
5182 small number of spill registers, and more than one of them has
5183 group needs, then by starting in the middle, we may end up
5184 allocating the first one in such a way that we are not left with
5185 sufficient groups to handle the rest. */
5187 if (noerror || ! force_group)
5192 for (count = 0; count < n_spills; count++)
5194 int class = (int) reload_reg_class[r];
5196 i = (i + 1) % n_spills;
5198 if ((reload_reg_free_p (spill_regs[i], reload_opnum[r],
5199 reload_when_needed[r])
5201 /* We check reload_reg_used to make sure we
5202 don't clobber the return register. */
5203 && ! TEST_HARD_REG_BIT (reload_reg_used, spill_regs[i])
5204 && reload_reg_free_for_value_p (spill_regs[i],
5206 reload_when_needed[r],
5209 && TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
5210 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
5211 /* Look first for regs to share, then for unshared. But
5212 don't share regs used for inherited reloads; they are
5213 the ones we want to preserve. */
5215 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5217 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5220 int nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
5221 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5222 (on 68000) got us two FP regs. If NR is 1,
5223 we would reject both of them. */
5225 nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
5226 /* If we need only one reg, we have already won. */
5229 /* But reject a single reg if we demand a group. */
5234 /* Otherwise check that as many consecutive regs as we need
5236 Also, don't use for a group registers that are
5237 needed for nongroups. */
5238 if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
5241 regno = spill_regs[i] + nr - 1;
5242 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5243 && spill_reg_order[regno] >= 0
5244 && reload_reg_free_p (regno, reload_opnum[r],
5245 reload_when_needed[r])
5246 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
5256 /* If we found something on pass 1, omit pass 2. */
5257 if (count < n_spills)
5261 /* We should have found a spill register by now. */
5262 if (count == n_spills)
5269 /* I is the index in SPILL_REG_RTX of the reload register we are to
5270 allocate. Get an rtx for it and find its register number. */
5272 new = spill_reg_rtx[i];
5274 if (new == 0 || GET_MODE (new) != reload_mode[r])
5275 spill_reg_rtx[i] = new
5276 = gen_rtx_REG (reload_mode[r], spill_regs[i]);
5278 regno = true_regnum (new);
5280 /* Detect when the reload reg can't hold the reload mode.
5281 This used to be one `if', but Sequent compiler can't handle that. */
5282 if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5284 enum machine_mode test_mode = VOIDmode;
5286 test_mode = GET_MODE (reload_in[r]);
5287 /* If reload_in[r] has VOIDmode, it means we will load it
5288 in whatever mode the reload reg has: to wit, reload_mode[r].
5289 We have already tested that for validity. */
5290 /* Aside from that, we need to test that the expressions
5291 to reload from or into have modes which are valid for this
5292 reload register. Otherwise the reload insns would be invalid. */
5293 if (! (reload_in[r] != 0 && test_mode != VOIDmode
5294 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5295 if (! (reload_out[r] != 0
5296 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
5298 /* The reg is OK. */
5301 /* Mark as in use for this insn the reload regs we use
5303 mark_reload_reg_in_use (spill_regs[i], reload_opnum[r],
5304 reload_when_needed[r], reload_mode[r]);
5306 reload_reg_rtx[r] = new;
5307 reload_spill_index[r] = spill_regs[i];
5312 /* The reg is not OK. */
5317 if (asm_noperands (PATTERN (insn)) < 0)
5318 /* It's the compiler's fault. */
5319 fatal_insn ("Could not find a spill register", insn);
5321 /* It's the user's fault; the operand's mode and constraint
5322 don't match. Disable this reload so we don't crash in final. */
5323 error_for_asm (insn,
5324 "`asm' operand constraint incompatible with operand size");
5327 reload_reg_rtx[r] = 0;
5328 reload_optional[r] = 1;
5329 reload_secondary_p[r] = 1;
5334 /* Assign hard reg targets for the pseudo-registers we must reload
5335 into hard regs for this insn.
5336 Also output the instructions to copy them in and out of the hard regs.
5338 For machines with register classes, we are responsible for
5339 finding a reload reg in the proper class. */
5342 choose_reload_regs (insn, avoid_return_reg)
5344 rtx avoid_return_reg;
5347 int max_group_size = 1;
5348 enum reg_class group_class = NO_REGS;
5351 rtx save_reload_reg_rtx[MAX_RELOADS];
5352 char save_reload_inherited[MAX_RELOADS];
5353 rtx save_reload_inheritance_insn[MAX_RELOADS];
5354 rtx save_reload_override_in[MAX_RELOADS];
5355 int save_reload_spill_index[MAX_RELOADS];
5356 HARD_REG_SET save_reload_reg_used;
5357 HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
5358 HARD_REG_SET save_reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
5359 HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
5360 HARD_REG_SET save_reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
5361 HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS];
5362 HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS];
5363 HARD_REG_SET save_reload_reg_used_in_op_addr;
5364 HARD_REG_SET save_reload_reg_used_in_op_addr_reload;
5365 HARD_REG_SET save_reload_reg_used_in_insn;
5366 HARD_REG_SET save_reload_reg_used_in_other_addr;
5367 HARD_REG_SET save_reload_reg_used_at_all;
5369 bzero (reload_inherited, MAX_RELOADS);
5370 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5371 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5373 CLEAR_HARD_REG_SET (reload_reg_used);
5374 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5375 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5376 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5377 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5378 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5380 for (i = 0; i < reload_n_operands; i++)
5382 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5383 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5384 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5385 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5386 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5387 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5390 /* Don't bother with avoiding the return reg
5391 if we have no mandatory reload that could use it. */
5392 if (SMALL_REGISTER_CLASSES && avoid_return_reg)
5395 int regno = REGNO (avoid_return_reg);
5397 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
5400 for (r = regno; r < regno + nregs; r++)
5401 if (spill_reg_order[r] >= 0)
5402 for (j = 0; j < n_reloads; j++)
5403 if (!reload_optional[j] && reload_reg_rtx[j] == 0
5404 && (reload_in[j] != 0 || reload_out[j] != 0
5405 || reload_secondary_p[j])
5407 TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[j]], r))
5410 avoid_return_reg = 0;
5413 #if 0 /* Not needed, now that we can always retry without inheritance. */
5414 /* See if we have more mandatory reloads than spill regs.
5415 If so, then we cannot risk optimizations that could prevent
5416 reloads from sharing one spill register.
5418 Since we will try finding a better register than reload_reg_rtx
5419 unless it is equal to reload_in or reload_out, count such reloads. */
5422 int tem = SMALL_REGISTER_CLASSES? (avoid_return_reg != 0): 0;
5423 for (j = 0; j < n_reloads; j++)
5424 if (! reload_optional[j]
5425 && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
5426 && (reload_reg_rtx[j] == 0
5427 || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
5428 && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
5435 /* Don't use the subroutine call return reg for a reload
5436 if we are supposed to avoid it. */
5437 if (SMALL_REGISTER_CLASSES && avoid_return_reg)
5439 int regno = REGNO (avoid_return_reg);
5441 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
5444 for (r = regno; r < regno + nregs; r++)
5445 if (spill_reg_order[r] >= 0)
5446 SET_HARD_REG_BIT (reload_reg_used, r);
5449 /* In order to be certain of getting the registers we need,
5450 we must sort the reloads into order of increasing register class.
5451 Then our grabbing of reload registers will parallel the process
5452 that provided the reload registers.
5454 Also note whether any of the reloads wants a consecutive group of regs.
5455 If so, record the maximum size of the group desired and what
5456 register class contains all the groups needed by this insn. */
5458 for (j = 0; j < n_reloads; j++)
5460 reload_order[j] = j;
5461 reload_spill_index[j] = -1;
5464 = (reload_inmode[j] == VOIDmode
5465 || (GET_MODE_SIZE (reload_outmode[j])
5466 > GET_MODE_SIZE (reload_inmode[j])))
5467 ? reload_outmode[j] : reload_inmode[j];
5469 reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
5471 if (reload_nregs[j] > 1)
5473 max_group_size = MAX (reload_nregs[j], max_group_size);
5474 group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
5477 /* If we have already decided to use a certain register,
5478 don't use it in another way. */
5479 if (reload_reg_rtx[j])
5480 mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j],
5481 reload_when_needed[j], reload_mode[j]);
5485 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5487 bcopy ((char *) reload_reg_rtx, (char *) save_reload_reg_rtx,
5488 sizeof reload_reg_rtx);
5489 bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
5490 bcopy ((char *) reload_inheritance_insn,
5491 (char *) save_reload_inheritance_insn,
5492 sizeof reload_inheritance_insn);
5493 bcopy ((char *) reload_override_in, (char *) save_reload_override_in,
5494 sizeof reload_override_in);
5495 bcopy ((char *) reload_spill_index, (char *) save_reload_spill_index,
5496 sizeof reload_spill_index);
5497 COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
5498 COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
5499 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
5500 reload_reg_used_in_op_addr);
5502 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr_reload,
5503 reload_reg_used_in_op_addr_reload);
5505 COPY_HARD_REG_SET (save_reload_reg_used_in_insn,
5506 reload_reg_used_in_insn);
5507 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr,
5508 reload_reg_used_in_other_addr);
5510 for (i = 0; i < reload_n_operands; i++)
5512 COPY_HARD_REG_SET (save_reload_reg_used_in_output[i],
5513 reload_reg_used_in_output[i]);
5514 COPY_HARD_REG_SET (save_reload_reg_used_in_input[i],
5515 reload_reg_used_in_input[i]);
5516 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i],
5517 reload_reg_used_in_input_addr[i]);
5518 COPY_HARD_REG_SET (save_reload_reg_used_in_inpaddr_addr[i],
5519 reload_reg_used_in_inpaddr_addr[i]);
5520 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i],
5521 reload_reg_used_in_output_addr[i]);
5522 COPY_HARD_REG_SET (save_reload_reg_used_in_outaddr_addr[i],
5523 reload_reg_used_in_outaddr_addr[i]);
5526 /* If -O, try first with inheritance, then turning it off.
5527 If not -O, don't do inheritance.
5528 Using inheritance when not optimizing leads to paradoxes
5529 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5530 because one side of the comparison might be inherited. */
5532 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5534 /* Process the reloads in order of preference just found.
5535 Beyond this point, subregs can be found in reload_reg_rtx.
5537 This used to look for an existing reloaded home for all
5538 of the reloads, and only then perform any new reloads.
5539 But that could lose if the reloads were done out of reg-class order
5540 because a later reload with a looser constraint might have an old
5541 home in a register needed by an earlier reload with a tighter constraint.
5543 To solve this, we make two passes over the reloads, in the order
5544 described above. In the first pass we try to inherit a reload
5545 from a previous insn. If there is a later reload that needs a
5546 class that is a proper subset of the class being processed, we must
5547 also allocate a spill register during the first pass.
5549 Then make a second pass over the reloads to allocate any reloads
5550 that haven't been given registers yet. */
5552 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5554 for (j = 0; j < n_reloads; j++)
5556 register int r = reload_order[j];
5558 /* Ignore reloads that got marked inoperative. */
5559 if (reload_out[r] == 0 && reload_in[r] == 0
5560 && ! reload_secondary_p[r])
5563 /* If find_reloads chose a to use reload_in or reload_out as a reload
5564 register, we don't need to chose one. Otherwise, try even if it
5565 found one since we might save an insn if we find the value lying
5567 if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
5568 && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
5569 || rtx_equal_p (reload_out[r], reload_reg_rtx[r])))
5572 #if 0 /* No longer needed for correct operation.
5573 It might give better code, or might not; worth an experiment? */
5574 /* If this is an optional reload, we can't inherit from earlier insns
5575 until we are sure that any non-optional reloads have been allocated.
5576 The following code takes advantage of the fact that optional reloads
5577 are at the end of reload_order. */
5578 if (reload_optional[r] != 0)
5579 for (i = 0; i < j; i++)
5580 if ((reload_out[reload_order[i]] != 0
5581 || reload_in[reload_order[i]] != 0
5582 || reload_secondary_p[reload_order[i]])
5583 && ! reload_optional[reload_order[i]]
5584 && reload_reg_rtx[reload_order[i]] == 0)
5585 allocate_reload_reg (reload_order[i], insn, 0, inheritance);
5588 /* First see if this pseudo is already available as reloaded
5589 for a previous insn. We cannot try to inherit for reloads
5590 that are smaller than the maximum number of registers needed
5591 for groups unless the register we would allocate cannot be used
5594 We could check here to see if this is a secondary reload for
5595 an object that is already in a register of the desired class.
5596 This would avoid the need for the secondary reload register.
5597 But this is complex because we can't easily determine what
5598 objects might want to be loaded via this reload. So let a
5599 register be allocated here. In `emit_reload_insns' we suppress
5600 one of the loads in the case described above. */
5604 register int regno = -1;
5605 enum machine_mode mode;
5607 if (reload_in[r] == 0)
5609 else if (GET_CODE (reload_in[r]) == REG)
5611 regno = REGNO (reload_in[r]);
5612 mode = GET_MODE (reload_in[r]);
5614 else if (GET_CODE (reload_in_reg[r]) == REG)
5616 regno = REGNO (reload_in_reg[r]);
5617 mode = GET_MODE (reload_in_reg[r]);
5619 else if (GET_CODE (reload_in[r]) == MEM)
5621 rtx prev = prev_nonnote_insn (insn), note;
5623 if (prev && GET_CODE (prev) == INSN
5624 && GET_CODE (PATTERN (prev)) == USE
5625 && GET_CODE (XEXP (PATTERN (prev), 0)) == REG
5626 && (REGNO (XEXP (PATTERN (prev), 0))
5627 >= FIRST_PSEUDO_REGISTER)
5628 && (note = find_reg_note (prev, REG_EQUAL, NULL_RTX))
5629 && GET_CODE (XEXP (note, 0)) == MEM)
5631 rtx addr = XEXP (XEXP (note, 0), 0);
5633 = (GET_MODE_SIZE (GET_MODE (addr))
5634 - GET_MODE_SIZE (GET_MODE (reload_in[r])));
5636 && rtx_equal_p ((BYTES_BIG_ENDIAN
5637 ? plus_constant (addr, size_diff)
5639 XEXP (reload_in[r], 0)))
5641 regno = REGNO (XEXP (PATTERN (prev), 0));
5642 mode = GET_MODE (reload_in[r]);
5647 /* This won't work, since REGNO can be a pseudo reg number.
5648 Also, it takes much more hair to keep track of all the things
5649 that can invalidate an inherited reload of part of a pseudoreg. */
5650 else if (GET_CODE (reload_in[r]) == SUBREG
5651 && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
5652 regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
5655 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5657 i = REGNO (reg_last_reload_reg[regno]);
5659 if (reg_reloaded_contents[i] == regno
5660 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5661 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
5662 >= GET_MODE_SIZE (mode))
5663 && HARD_REGNO_MODE_OK (i, reload_mode[r])
5664 && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5666 && (reload_nregs[r] == max_group_size
5667 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5669 && ((reload_reg_free_p (i, reload_opnum[r],
5670 reload_when_needed[r])
5671 && reload_reg_free_before_p (i, reload_opnum[r],
5672 reload_when_needed[r]))
5673 || reload_reg_free_for_value_p (i, reload_opnum[r],
5674 reload_when_needed[r],
5678 /* If a group is needed, verify that all the subsequent
5679 registers still have their values intact. */
5681 = HARD_REGNO_NREGS (i, reload_mode[r]);
5684 for (k = 1; k < nr; k++)
5685 if (reg_reloaded_contents[i + k] != regno
5686 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5693 /* We found a register that contains the
5694 value we need. If this register is the
5695 same as an `earlyclobber' operand of the
5696 current insn, just mark it as a place to
5697 reload from since we can't use it as the
5698 reload register itself. */
5700 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5701 if (reg_overlap_mentioned_for_reload_p
5702 (reg_last_reload_reg[regno],
5703 reload_earlyclobbers[i1]))
5706 if (i1 != n_earlyclobbers
5707 /* Don't use it if we'd clobber a pseudo reg. */
5708 || (spill_reg_order[i] < 0
5710 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5711 /* Don't really use the inherited spill reg
5712 if we need it wider than we've got it. */
5713 || (GET_MODE_SIZE (reload_mode[r])
5714 > GET_MODE_SIZE (mode)))
5715 reload_override_in[r] = reg_last_reload_reg[regno];
5719 /* We can use this as a reload reg. */
5720 /* Mark the register as in use for this part of
5722 mark_reload_reg_in_use (i,
5724 reload_when_needed[r],
5726 reload_reg_rtx[r] = reg_last_reload_reg[regno];
5727 reload_inherited[r] = 1;
5728 reload_inheritance_insn[r]
5729 = reg_reloaded_insn[i];
5730 reload_spill_index[r] = i;
5731 for (k = 0; k < nr; k++)
5732 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5740 /* Here's another way to see if the value is already lying around. */
5742 && reload_in[r] != 0
5743 && ! reload_inherited[r]
5744 && reload_out[r] == 0
5745 && (CONSTANT_P (reload_in[r])
5746 || GET_CODE (reload_in[r]) == PLUS
5747 || GET_CODE (reload_in[r]) == REG
5748 || GET_CODE (reload_in[r]) == MEM)
5749 && (reload_nregs[r] == max_group_size
5750 || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
5753 = find_equiv_reg (reload_in[r], insn, reload_reg_class[r],
5754 -1, NULL_PTR, 0, reload_mode[r]);
5759 if (GET_CODE (equiv) == REG)
5760 regno = REGNO (equiv);
5761 else if (GET_CODE (equiv) == SUBREG)
5763 /* This must be a SUBREG of a hard register.
5764 Make a new REG since this might be used in an
5765 address and not all machines support SUBREGs
5767 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5768 equiv = gen_rtx_REG (reload_mode[r], regno);
5774 /* If we found a spill reg, reject it unless it is free
5775 and of the desired class. */
5777 && ((spill_reg_order[regno] >= 0
5778 && ! (reload_reg_free_before_p (regno, reload_opnum[r],
5779 reload_when_needed[r])
5780 || reload_reg_free_for_value_p (regno,
5782 reload_when_needed[r],
5785 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5789 if (equiv != 0 && TEST_HARD_REG_BIT (reload_reg_used_at_all, regno))
5792 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5795 /* We found a register that contains the value we need.
5796 If this register is the same as an `earlyclobber' operand
5797 of the current insn, just mark it as a place to reload from
5798 since we can't use it as the reload register itself. */
5801 for (i = 0; i < n_earlyclobbers; i++)
5802 if (reg_overlap_mentioned_for_reload_p (equiv,
5803 reload_earlyclobbers[i]))
5805 reload_override_in[r] = equiv;
5810 /* If the equiv register we have found is explicitly clobbered
5811 in the current insn, it depends on the reload type if we
5812 can use it, use it for reload_override_in, or not at all.
5813 In particular, we then can't use EQUIV for a
5814 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5816 if (equiv != 0 && regno_clobbered_p (regno, insn))
5818 switch (reload_when_needed[r])
5820 case RELOAD_FOR_OTHER_ADDRESS:
5821 case RELOAD_FOR_INPADDR_ADDRESS:
5822 case RELOAD_FOR_INPUT_ADDRESS:
5823 case RELOAD_FOR_OPADDR_ADDR:
5826 case RELOAD_FOR_INPUT:
5827 case RELOAD_FOR_OPERAND_ADDRESS:
5828 reload_override_in[r] = equiv;
5836 /* If we found an equivalent reg, say no code need be generated
5837 to load it, and use it as our reload reg. */
5838 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5840 int nr = HARD_REGNO_NREGS (regno, reload_mode[r]);
5842 reload_reg_rtx[r] = equiv;
5843 reload_inherited[r] = 1;
5845 /* If reg_reloaded_valid is not set for this register,
5846 there might be a stale spill_reg_store lying around.
5847 We must clear it, since otherwise emit_reload_insns
5848 might delete the store. */
5849 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5850 spill_reg_store[regno] = NULL_RTX;
5851 /* If any of the hard registers in EQUIV are spill
5852 registers, mark them as in use for this insn. */
5853 for (k = 0; k < nr; k++)
5855 i = spill_reg_order[regno + k];
5858 mark_reload_reg_in_use (regno, reload_opnum[r],
5859 reload_when_needed[r],
5861 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5868 /* If we found a register to use already, or if this is an optional
5869 reload, we are done. */
5870 if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
5873 #if 0 /* No longer needed for correct operation. Might or might not
5874 give better code on the average. Want to experiment? */
5876 /* See if there is a later reload that has a class different from our
5877 class that intersects our class or that requires less register
5878 than our reload. If so, we must allocate a register to this
5879 reload now, since that reload might inherit a previous reload
5880 and take the only available register in our class. Don't do this
5881 for optional reloads since they will force all previous reloads
5882 to be allocated. Also don't do this for reloads that have been
5885 for (i = j + 1; i < n_reloads; i++)
5887 int s = reload_order[i];
5889 if ((reload_in[s] == 0 && reload_out[s] == 0
5890 && ! reload_secondary_p[s])
5891 || reload_optional[s])
5894 if ((reload_reg_class[s] != reload_reg_class[r]
5895 && reg_classes_intersect_p (reload_reg_class[r],
5896 reload_reg_class[s]))
5897 || reload_nregs[s] < reload_nregs[r])
5904 allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance);
5908 /* Now allocate reload registers for anything non-optional that
5909 didn't get one yet. */
5910 for (j = 0; j < n_reloads; j++)
5912 register int r = reload_order[j];
5914 /* Ignore reloads that got marked inoperative. */
5915 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
5918 /* Skip reloads that already have a register allocated or are
5920 if (reload_reg_rtx[r] != 0 || reload_optional[r])
5923 if (! allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance))
5927 /* If that loop got all the way, we have won. */
5932 /* Loop around and try without any inheritance. */
5933 /* First undo everything done by the failed attempt
5934 to allocate with inheritance. */
5935 bcopy ((char *) save_reload_reg_rtx, (char *) reload_reg_rtx,
5936 sizeof reload_reg_rtx);
5937 bcopy ((char *) save_reload_inherited, (char *) reload_inherited,
5938 sizeof reload_inherited);
5939 bcopy ((char *) save_reload_inheritance_insn,
5940 (char *) reload_inheritance_insn,
5941 sizeof reload_inheritance_insn);
5942 bcopy ((char *) save_reload_override_in, (char *) reload_override_in,
5943 sizeof reload_override_in);
5944 bcopy ((char *) save_reload_spill_index, (char *) reload_spill_index,
5945 sizeof reload_spill_index);
5946 COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
5947 COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
5948 COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
5949 save_reload_reg_used_in_op_addr);
5950 COPY_HARD_REG_SET (reload_reg_used_in_op_addr_reload,
5951 save_reload_reg_used_in_op_addr_reload);
5952 COPY_HARD_REG_SET (reload_reg_used_in_insn,
5953 save_reload_reg_used_in_insn);
5954 COPY_HARD_REG_SET (reload_reg_used_in_other_addr,
5955 save_reload_reg_used_in_other_addr);
5957 for (i = 0; i < reload_n_operands; i++)
5959 COPY_HARD_REG_SET (reload_reg_used_in_input[i],
5960 save_reload_reg_used_in_input[i]);
5961 COPY_HARD_REG_SET (reload_reg_used_in_output[i],
5962 save_reload_reg_used_in_output[i]);
5963 COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i],
5964 save_reload_reg_used_in_input_addr[i]);
5965 COPY_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i],
5966 save_reload_reg_used_in_inpaddr_addr[i]);
5967 COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i],
5968 save_reload_reg_used_in_output_addr[i]);
5969 COPY_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i],
5970 save_reload_reg_used_in_outaddr_addr[i]);
5974 /* If we thought we could inherit a reload, because it seemed that
5975 nothing else wanted the same reload register earlier in the insn,
5976 verify that assumption, now that all reloads have been assigned. */
5978 for (j = 0; j < n_reloads; j++)
5980 register int r = reload_order[j];
5982 if (reload_inherited[r] && reload_reg_rtx[r] != 0
5983 && ! (reload_reg_free_before_p (true_regnum (reload_reg_rtx[r]),
5985 reload_when_needed[r])
5986 || reload_reg_free_for_value_p (true_regnum (reload_reg_rtx[r]),
5988 reload_when_needed[r],
5991 reload_inherited[r] = 0;
5992 /* If we can inherit a RELOAD_FOR_INPUT, then we do not need its related
5993 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads.
5994 ??? This could be extended to other reload types, but these are
5995 more tricky to handle:
5996 RELOAD_FOR_OTHER_ADDRESS reloads might have been merged, so we
5997 can't eliminate them without a check that *all* references are
5998 now unused due to inheritance.
5999 While RELOAD_FOR_INPADDR_ADDRESS and RELOAD_FOR_OUTADDR_ADDRESS are
6000 not merged, we can't be sure that we have eliminated the use of
6001 that particular reload if we have seen just one
6002 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_OUTPUT_ADDRESS being inherited,
6003 since there might be multiple of the latter two reloads for a single
6005 RELOAD_FOR_OPADDR_ADDR reloads for different operands are not
6006 merged, but might share the same register by courtesy of
6007 reload_reg_free_for_value_p. reload_reg_used_in_op_addr_reload
6008 does not differentiate by opnum, thus calling clear_reload_reg_in_use
6009 for one of these reloads would mark the register as free even though
6010 another RELOAD_FOR_OPADDR_ADDR reload might still use it. */
6011 else if (reload_inherited[r] && reload_when_needed[r] == RELOAD_FOR_INPUT)
6013 for (i = 0; i < n_reloads; i++)
6015 if ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
6016 || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS)
6017 && reload_opnum[i] == reload_opnum[r]
6018 && reload_in[i] && reload_reg_rtx[i])
6020 int regno = true_regnum (reload_reg_rtx[i]);
6023 if (spill_reg_order[regno] >= 0)
6024 clear_reload_reg_in_use (regno, reload_opnum[i],
6025 reload_when_needed[i],
6027 reload_reg_rtx[i] = 0;
6028 reload_spill_index[i] = -1;
6029 remove_replacements (i);
6034 /* If we found a better place to reload from,
6035 validate it in the same fashion, if it is a reload reg. */
6036 if (reload_override_in[r]
6037 && (GET_CODE (reload_override_in[r]) == REG
6038 || GET_CODE (reload_override_in[r]) == SUBREG))
6040 int regno = true_regnum (reload_override_in[r]);
6041 if (spill_reg_order[regno] >= 0
6042 && ! reload_reg_free_before_p (regno, reload_opnum[r],
6043 reload_when_needed[r]))
6044 reload_override_in[r] = 0;
6048 /* Now that reload_override_in is known valid,
6049 actually override reload_in. */
6050 for (j = 0; j < n_reloads; j++)
6051 if (reload_override_in[j])
6052 reload_in[j] = reload_override_in[j];
6054 /* If this reload won't be done because it has been cancelled or is
6055 optional and not inherited, clear reload_reg_rtx so other
6056 routines (such as subst_reloads) don't get confused. */
6057 for (j = 0; j < n_reloads; j++)
6058 if (reload_reg_rtx[j] != 0
6059 && ((reload_optional[j] && ! reload_inherited[j])
6060 || (reload_in[j] == 0 && reload_out[j] == 0
6061 && ! reload_secondary_p[j])))
6063 int regno = true_regnum (reload_reg_rtx[j]);
6065 if (spill_reg_order[regno] >= 0)
6066 clear_reload_reg_in_use (regno, reload_opnum[j],
6067 reload_when_needed[j], reload_mode[j]);
6068 reload_reg_rtx[j] = 0;
6071 /* Record which pseudos and which spill regs have output reloads. */
6072 for (j = 0; j < n_reloads; j++)
6074 register int r = reload_order[j];
6076 i = reload_spill_index[r];
6078 /* I is nonneg if this reload uses a register.
6079 If reload_reg_rtx[r] is 0, this is an optional reload
6080 that we opted to ignore. */
6081 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG
6082 && reload_reg_rtx[r] != 0)
6084 register int nregno = REGNO (reload_out[r]);
6087 if (nregno < FIRST_PSEUDO_REGISTER)
6088 nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
6091 reg_has_output_reload[nregno + nr] = 1;
6095 nr = HARD_REGNO_NREGS (i, reload_mode[r]);
6097 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6100 if (reload_when_needed[r] != RELOAD_OTHER
6101 && reload_when_needed[r] != RELOAD_FOR_OUTPUT
6102 && reload_when_needed[r] != RELOAD_FOR_INSN)
6108 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
6109 reloads of the same item for fear that we might not have enough reload
6110 registers. However, normally they will get the same reload register
6111 and hence actually need not be loaded twice.
6113 Here we check for the most common case of this phenomenon: when we have
6114 a number of reloads for the same object, each of which were allocated
6115 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6116 reload, and is not modified in the insn itself. If we find such,
6117 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6118 This will not increase the number of spill registers needed and will
6119 prevent redundant code. */
6122 merge_assigned_reloads (insn)
6127 /* Scan all the reloads looking for ones that only load values and
6128 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6129 assigned and not modified by INSN. */
6131 for (i = 0; i < n_reloads; i++)
6133 int conflicting_input = 0;
6134 int max_input_address_opnum = -1;
6135 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6137 if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER
6138 || reload_out[i] != 0 || reload_reg_rtx[i] == 0
6139 || reg_set_p (reload_reg_rtx[i], insn))
6142 /* Look at all other reloads. Ensure that the only use of this
6143 reload_reg_rtx is in a reload that just loads the same value
6144 as we do. Note that any secondary reloads must be of the identical
6145 class since the values, modes, and result registers are the
6146 same, so we need not do anything with any secondary reloads. */
6148 for (j = 0; j < n_reloads; j++)
6150 if (i == j || reload_reg_rtx[j] == 0
6151 || ! reg_overlap_mentioned_p (reload_reg_rtx[j],
6155 if (reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS
6156 && reload_opnum[j] > max_input_address_opnum)
6157 max_input_address_opnum = reload_opnum[j];
6159 /* If the reload regs aren't exactly the same (e.g, different modes)
6160 or if the values are different, we can't merge this reload.
6161 But if it is an input reload, we might still merge
6162 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6164 if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
6165 || reload_out[j] != 0 || reload_in[j] == 0
6166 || ! rtx_equal_p (reload_in[i], reload_in[j]))
6168 if (reload_when_needed[j] != RELOAD_FOR_INPUT
6169 || ((reload_when_needed[i] != RELOAD_FOR_INPUT_ADDRESS
6170 || reload_opnum[i] > reload_opnum[j])
6171 && reload_when_needed[i] != RELOAD_FOR_OTHER_ADDRESS))
6173 conflicting_input = 1;
6174 if (min_conflicting_input_opnum > reload_opnum[j])
6175 min_conflicting_input_opnum = reload_opnum[j];
6179 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6180 we, in fact, found any matching reloads. */
6183 && max_input_address_opnum <= min_conflicting_input_opnum)
6185 for (j = 0; j < n_reloads; j++)
6186 if (i != j && reload_reg_rtx[j] != 0
6187 && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
6188 && (! conflicting_input
6189 || reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS
6190 || reload_when_needed[j] == RELOAD_FOR_OTHER_ADDRESS))
6192 reload_when_needed[i] = RELOAD_OTHER;
6194 reload_spill_index[j] = -1;
6195 transfer_replacements (i, j);
6198 /* If this is now RELOAD_OTHER, look for any reloads that load
6199 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6200 if they were for inputs, RELOAD_OTHER for outputs. Note that
6201 this test is equivalent to looking for reloads for this operand
6204 if (reload_when_needed[i] == RELOAD_OTHER)
6205 for (j = 0; j < n_reloads; j++)
6206 if (reload_in[j] != 0
6207 && reload_when_needed[i] != RELOAD_OTHER
6208 && reg_overlap_mentioned_for_reload_p (reload_in[j],
6210 reload_when_needed[j]
6211 = ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
6212 || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS)
6213 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6219 /* Output insns to reload values in and out of the chosen reload regs. */
6222 emit_reload_insns (insn)
6226 rtx input_reload_insns[MAX_RECOG_OPERANDS];
6227 rtx other_input_address_reload_insns = 0;
6228 rtx other_input_reload_insns = 0;
6229 rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6230 rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6231 rtx output_reload_insns[MAX_RECOG_OPERANDS];
6232 rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6233 rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6234 rtx operand_reload_insns = 0;
6235 rtx other_operand_reload_insns = 0;
6236 rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6237 rtx following_insn = NEXT_INSN (insn);
6238 rtx before_insn = insn;
6240 /* Values to be put in spill_reg_store are put here first. */
6241 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6242 HARD_REG_SET reg_reloaded_died;
6244 CLEAR_HARD_REG_SET (reg_reloaded_died);
6246 for (j = 0; j < reload_n_operands; j++)
6247 input_reload_insns[j] = input_address_reload_insns[j]
6248 = inpaddr_address_reload_insns[j]
6249 = output_reload_insns[j] = output_address_reload_insns[j]
6250 = outaddr_address_reload_insns[j]
6251 = other_output_reload_insns[j] = 0;
6253 /* Now output the instructions to copy the data into and out of the
6254 reload registers. Do these in the order that the reloads were reported,
6255 since reloads of base and index registers precede reloads of operands
6256 and the operands may need the base and index registers reloaded. */
6258 for (j = 0; j < n_reloads; j++)
6261 rtx oldequiv_reg = 0;
6262 rtx this_reload_insn = 0;
6263 int expect_occurrences = 1;
6265 if (reload_spill_index[j] >= 0)
6266 new_spill_reg_store[reload_spill_index[j]] = 0;
6269 if (old != 0 && ! reload_inherited[j]
6270 && ! rtx_equal_p (reload_reg_rtx[j], old)
6271 && reload_reg_rtx[j] != 0)
6273 register rtx reloadreg = reload_reg_rtx[j];
6275 enum machine_mode mode;
6278 /* Determine the mode to reload in.
6279 This is very tricky because we have three to choose from.
6280 There is the mode the insn operand wants (reload_inmode[J]).
6281 There is the mode of the reload register RELOADREG.
6282 There is the intrinsic mode of the operand, which we could find
6283 by stripping some SUBREGs.
6284 It turns out that RELOADREG's mode is irrelevant:
6285 we can change that arbitrarily.
6287 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6288 then the reload reg may not support QImode moves, so use SImode.
6289 If foo is in memory due to spilling a pseudo reg, this is safe,
6290 because the QImode value is in the least significant part of a
6291 slot big enough for a SImode. If foo is some other sort of
6292 memory reference, then it is impossible to reload this case,
6293 so previous passes had better make sure this never happens.
6295 Then consider a one-word union which has SImode and one of its
6296 members is a float, being fetched as (SUBREG:SF union:SI).
6297 We must fetch that as SFmode because we could be loading into
6298 a float-only register. In this case OLD's mode is correct.
6300 Consider an immediate integer: it has VOIDmode. Here we need
6301 to get a mode from something else.
6303 In some cases, there is a fourth mode, the operand's
6304 containing mode. If the insn specifies a containing mode for
6305 this operand, it overrides all others.
6307 I am not sure whether the algorithm here is always right,
6308 but it does the right things in those cases. */
6310 mode = GET_MODE (old);
6311 if (mode == VOIDmode)
6312 mode = reload_inmode[j];
6314 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6315 /* If we need a secondary register for this operation, see if
6316 the value is already in a register in that class. Don't
6317 do this if the secondary register will be used as a scratch
6320 if (reload_secondary_in_reload[j] >= 0
6321 && reload_secondary_in_icode[j] == CODE_FOR_nothing
6324 = find_equiv_reg (old, insn,
6325 reload_reg_class[reload_secondary_in_reload[j]],
6326 -1, NULL_PTR, 0, mode);
6329 /* If reloading from memory, see if there is a register
6330 that already holds the same value. If so, reload from there.
6331 We can pass 0 as the reload_reg_p argument because
6332 any other reload has either already been emitted,
6333 in which case find_equiv_reg will see the reload-insn,
6334 or has yet to be emitted, in which case it doesn't matter
6335 because we will use this equiv reg right away. */
6337 if (oldequiv == 0 && optimize
6338 && (GET_CODE (old) == MEM
6339 || (GET_CODE (old) == REG
6340 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6341 && reg_renumber[REGNO (old)] < 0)))
6342 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6343 -1, NULL_PTR, 0, mode);
6347 int regno = true_regnum (oldequiv);
6349 /* If OLDEQUIV is a spill register, don't use it for this
6350 if any other reload needs it at an earlier stage of this insn
6351 or at this stage. */
6352 if (spill_reg_order[regno] >= 0
6353 && (! reload_reg_free_p (regno, reload_opnum[j],
6354 reload_when_needed[j])
6355 || ! reload_reg_free_before_p (regno, reload_opnum[j],
6356 reload_when_needed[j])))
6359 /* If OLDEQUIV is not a spill register,
6360 don't use it if any other reload wants it. */
6361 if (spill_reg_order[regno] < 0)
6364 for (k = 0; k < n_reloads; k++)
6365 if (reload_reg_rtx[k] != 0 && k != j
6366 && reg_overlap_mentioned_for_reload_p (reload_reg_rtx[k],
6374 /* If it is no cheaper to copy from OLDEQUIV into the
6375 reload register than it would be to move from memory,
6376 don't use it. Likewise, if we need a secondary register
6380 && ((REGNO_REG_CLASS (regno) != reload_reg_class[j]
6381 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
6382 reload_reg_class[j])
6383 >= MEMORY_MOVE_COST (mode, reload_reg_class[j], 1)))
6384 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6385 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6389 #ifdef SECONDARY_MEMORY_NEEDED
6390 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6391 reload_reg_class[j],
6400 else if (GET_CODE (oldequiv) == REG)
6401 oldequiv_reg = oldequiv;
6402 else if (GET_CODE (oldequiv) == SUBREG)
6403 oldequiv_reg = SUBREG_REG (oldequiv);
6405 /* If we are reloading from a register that was recently stored in
6406 with an output-reload, see if we can prove there was
6407 actually no need to store the old value in it. */
6409 if (optimize && GET_CODE (oldequiv) == REG
6410 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6411 && spill_reg_store[REGNO (oldequiv)]
6412 && GET_CODE (old) == REG && dead_or_set_p (insn, old)
6413 /* This is unsafe if operand occurs more than once in current
6414 insn. Perhaps some occurrences weren't reloaded. */
6415 && count_occurrences (PATTERN (insn), old) == 1)
6416 delete_output_reload (insn, j, spill_reg_store[REGNO (oldequiv)]);
6418 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6419 then load RELOADREG from OLDEQUIV. Note that we cannot use
6420 gen_lowpart_common since it can do the wrong thing when
6421 RELOADREG has a multi-word mode. Note that RELOADREG
6422 must always be a REG here. */
6424 if (GET_MODE (reloadreg) != mode)
6425 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6426 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6427 oldequiv = SUBREG_REG (oldequiv);
6428 if (GET_MODE (oldequiv) != VOIDmode
6429 && mode != GET_MODE (oldequiv))
6430 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6432 /* Switch to the right place to emit the reload insns. */
6433 switch (reload_when_needed[j])
6436 where = &other_input_reload_insns;
6438 case RELOAD_FOR_INPUT:
6439 where = &input_reload_insns[reload_opnum[j]];
6441 case RELOAD_FOR_INPUT_ADDRESS:
6442 where = &input_address_reload_insns[reload_opnum[j]];
6444 case RELOAD_FOR_INPADDR_ADDRESS:
6445 where = &inpaddr_address_reload_insns[reload_opnum[j]];
6447 case RELOAD_FOR_OUTPUT_ADDRESS:
6448 where = &output_address_reload_insns[reload_opnum[j]];
6450 case RELOAD_FOR_OUTADDR_ADDRESS:
6451 where = &outaddr_address_reload_insns[reload_opnum[j]];
6453 case RELOAD_FOR_OPERAND_ADDRESS:
6454 where = &operand_reload_insns;
6456 case RELOAD_FOR_OPADDR_ADDR:
6457 where = &other_operand_reload_insns;
6459 case RELOAD_FOR_OTHER_ADDRESS:
6460 where = &other_input_address_reload_insns;
6466 push_to_sequence (*where);
6469 /* Auto-increment addresses must be reloaded in a special way. */
6470 if (GET_CODE (oldequiv) == POST_INC
6471 || GET_CODE (oldequiv) == POST_DEC
6472 || GET_CODE (oldequiv) == PRE_INC
6473 || GET_CODE (oldequiv) == PRE_DEC)
6475 /* We are not going to bother supporting the case where a
6476 incremented register can't be copied directly from
6477 OLDEQUIV since this seems highly unlikely. */
6478 if (reload_secondary_in_reload[j] >= 0)
6480 /* Prevent normal processing of this reload. */
6482 /* Output a special code sequence for this case. */
6483 inc_for_reload (reloadreg, oldequiv, reload_inc[j]);
6486 /* If we are reloading a pseudo-register that was set by the previous
6487 insn, see if we can get rid of that pseudo-register entirely
6488 by redirecting the previous insn into our reload register. */
6490 else if (optimize && GET_CODE (old) == REG
6491 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6492 && dead_or_set_p (insn, old)
6493 /* This is unsafe if some other reload
6494 uses the same reg first. */
6495 && reload_reg_free_before_p (REGNO (reloadreg),
6497 reload_when_needed[j]))
6499 rtx temp = PREV_INSN (insn);
6500 while (temp && GET_CODE (temp) == NOTE)
6501 temp = PREV_INSN (temp);
6503 && GET_CODE (temp) == INSN
6504 && GET_CODE (PATTERN (temp)) == SET
6505 && SET_DEST (PATTERN (temp)) == old
6506 /* Make sure we can access insn_operand_constraint. */
6507 && asm_noperands (PATTERN (temp)) < 0
6508 /* This is unsafe if prev insn rejects our reload reg. */
6509 && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
6511 /* This is unsafe if operand occurs more than once in current
6512 insn. Perhaps some occurrences aren't reloaded. */
6513 && count_occurrences (PATTERN (insn), old) == 1
6514 /* Don't risk splitting a matching pair of operands. */
6515 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6517 /* Store into the reload register instead of the pseudo. */
6518 SET_DEST (PATTERN (temp)) = reloadreg;
6519 /* If these are the only uses of the pseudo reg,
6520 pretend for GDB it lives in the reload reg we used. */
6521 if (REG_N_DEATHS (REGNO (old)) == 1
6522 && REG_N_SETS (REGNO (old)) == 1)
6524 reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
6525 alter_reg (REGNO (old), -1);
6531 /* We can't do that, so output an insn to load RELOADREG. */
6535 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6536 rtx second_reload_reg = 0;
6537 enum insn_code icode;
6539 /* If we have a secondary reload, pick up the secondary register
6540 and icode, if any. If OLDEQUIV and OLD are different or
6541 if this is an in-out reload, recompute whether or not we
6542 still need a secondary register and what the icode should
6543 be. If we still need a secondary register and the class or
6544 icode is different, go back to reloading from OLD if using
6545 OLDEQUIV means that we got the wrong type of register. We
6546 cannot have different class or icode due to an in-out reload
6547 because we don't make such reloads when both the input and
6548 output need secondary reload registers. */
6550 if (reload_secondary_in_reload[j] >= 0)
6552 int secondary_reload = reload_secondary_in_reload[j];
6553 rtx real_oldequiv = oldequiv;
6556 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6557 and similarly for OLD.
6558 See comments in get_secondary_reload in reload.c. */
6559 if (GET_CODE (oldequiv) == REG
6560 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6561 && reg_equiv_mem[REGNO (oldequiv)] != 0)
6562 real_oldequiv = reg_equiv_mem[REGNO (oldequiv)];
6564 if (GET_CODE (old) == REG
6565 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6566 && reg_equiv_mem[REGNO (old)] != 0)
6567 real_old = reg_equiv_mem[REGNO (old)];
6569 second_reload_reg = reload_reg_rtx[secondary_reload];
6570 icode = reload_secondary_in_icode[j];
6572 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6573 || (reload_in[j] != 0 && reload_out[j] != 0))
6575 enum reg_class new_class
6576 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6577 mode, real_oldequiv);
6579 if (new_class == NO_REGS)
6580 second_reload_reg = 0;
6583 enum insn_code new_icode;
6584 enum machine_mode new_mode;
6586 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6587 REGNO (second_reload_reg)))
6588 oldequiv = old, real_oldequiv = real_old;
6591 new_icode = reload_in_optab[(int) mode];
6592 if (new_icode != CODE_FOR_nothing
6593 && ((insn_operand_predicate[(int) new_icode][0]
6594 && ! ((*insn_operand_predicate[(int) new_icode][0])
6596 || (insn_operand_predicate[(int) new_icode][1]
6597 && ! ((*insn_operand_predicate[(int) new_icode][1])
6598 (real_oldequiv, mode)))))
6599 new_icode = CODE_FOR_nothing;
6601 if (new_icode == CODE_FOR_nothing)
6604 new_mode = insn_operand_mode[(int) new_icode][2];
6606 if (GET_MODE (second_reload_reg) != new_mode)
6608 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6610 oldequiv = old, real_oldequiv = real_old;
6613 = gen_rtx_REG (new_mode,
6614 REGNO (second_reload_reg));
6620 /* If we still need a secondary reload register, check
6621 to see if it is being used as a scratch or intermediate
6622 register and generate code appropriately. If we need
6623 a scratch register, use REAL_OLDEQUIV since the form of
6624 the insn may depend on the actual address if it is
6627 if (second_reload_reg)
6629 if (icode != CODE_FOR_nothing)
6631 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6632 second_reload_reg));
6637 /* See if we need a scratch register to load the
6638 intermediate register (a tertiary reload). */
6639 enum insn_code tertiary_icode
6640 = reload_secondary_in_icode[secondary_reload];
6642 if (tertiary_icode != CODE_FOR_nothing)
6644 rtx third_reload_reg
6645 = reload_reg_rtx[reload_secondary_in_reload[secondary_reload]];
6647 emit_insn ((GEN_FCN (tertiary_icode)
6648 (second_reload_reg, real_oldequiv,
6649 third_reload_reg)));
6652 gen_reload (second_reload_reg, oldequiv,
6654 reload_when_needed[j]);
6656 oldequiv = second_reload_reg;
6662 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6663 gen_reload (reloadreg, oldequiv, reload_opnum[j],
6664 reload_when_needed[j]);
6666 #if defined(SECONDARY_INPUT_RELOAD_CLASS) && defined(PRESERVE_DEATH_INFO_REGNO_P)
6667 /* We may have to make a REG_DEAD note for the secondary reload
6668 register in the insns we just made. Find the last insn that
6669 mentioned the register. */
6670 if (! special && second_reload_reg
6671 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reload_reg)))
6675 for (prev = get_last_insn (); prev;
6676 prev = PREV_INSN (prev))
6677 if (GET_RTX_CLASS (GET_CODE (prev) == 'i')
6678 && reg_overlap_mentioned_for_reload_p (second_reload_reg,
6681 REG_NOTES (prev) = gen_rtx_EXPR_LIST (REG_DEAD,
6690 this_reload_insn = get_last_insn ();
6691 /* End this sequence. */
6692 *where = get_insns ();
6696 /* When inheriting a wider reload, we have a MEM in reload_in[j],
6697 e.g. inheriting a SImode output reload for
6698 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6699 if (optimize && reload_inherited[j] && reload_in[j]
6700 && GET_CODE (reload_in[j]) == MEM
6701 && reload_spill_index[j] >= 0
6702 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6705 = count_occurrences (PATTERN (insn), reload_in[j]) == 1 ? 0 : -1;
6707 = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6709 /* Add a note saying the input reload reg
6710 dies in this insn, if anyone cares. */
6711 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6713 && reload_reg_rtx[j] != old
6714 && reload_reg_rtx[j] != 0
6715 && reload_out[j] == 0
6716 && ! reload_inherited[j]
6717 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j])))
6719 register rtx reloadreg = reload_reg_rtx[j];
6722 /* We can't abort here because we need to support this for sched.c.
6723 It's not terrible to miss a REG_DEAD note, but we should try
6724 to figure out how to do this correctly. */
6725 /* The code below is incorrect for address-only reloads. */
6726 if (reload_when_needed[j] != RELOAD_OTHER
6727 && reload_when_needed[j] != RELOAD_FOR_INPUT)
6731 /* Add a death note to this insn, for an input reload. */
6733 if ((reload_when_needed[j] == RELOAD_OTHER
6734 || reload_when_needed[j] == RELOAD_FOR_INPUT)
6735 && ! dead_or_set_p (insn, reloadreg))
6737 = gen_rtx_EXPR_LIST (REG_DEAD,
6738 reloadreg, REG_NOTES (insn));
6741 /* When we inherit a reload, the last marked death of the reload reg
6742 may no longer really be a death. */
6743 if (reload_reg_rtx[j] != 0
6744 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j]))
6745 && reload_inherited[j])
6747 /* Handle inheriting an output reload.
6748 Remove the death note from the output reload insn. */
6749 if (reload_spill_index[j] >= 0
6750 && GET_CODE (reload_in[j]) == REG
6751 && spill_reg_store[reload_spill_index[j]] != 0
6752 && find_regno_note (spill_reg_store[reload_spill_index[j]],
6753 REG_DEAD, REGNO (reload_reg_rtx[j])))
6754 remove_death (REGNO (reload_reg_rtx[j]),
6755 spill_reg_store[reload_spill_index[j]]);
6756 /* Likewise for input reloads that were inherited. */
6757 else if (reload_spill_index[j] >= 0
6758 && GET_CODE (reload_in[j]) == REG
6759 && spill_reg_store[reload_spill_index[j]] == 0
6760 && reload_inheritance_insn[j] != 0
6761 && find_regno_note (reload_inheritance_insn[j], REG_DEAD,
6762 REGNO (reload_reg_rtx[j])))
6763 remove_death (REGNO (reload_reg_rtx[j]),
6764 reload_inheritance_insn[j]);
6769 /* We got this register from find_equiv_reg.
6770 Search back for its last death note and get rid of it.
6771 But don't search back too far.
6772 Don't go past a place where this reg is set,
6773 since a death note before that remains valid. */
6774 for (prev = PREV_INSN (insn);
6775 prev && GET_CODE (prev) != CODE_LABEL;
6776 prev = PREV_INSN (prev))
6777 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
6778 && dead_or_set_p (prev, reload_reg_rtx[j]))
6780 if (find_regno_note (prev, REG_DEAD,
6781 REGNO (reload_reg_rtx[j])))
6782 remove_death (REGNO (reload_reg_rtx[j]), prev);
6788 /* We might have used find_equiv_reg above to choose an alternate
6789 place from which to reload. If so, and it died, we need to remove
6790 that death and move it to one of the insns we just made. */
6792 if (oldequiv_reg != 0
6793 && PRESERVE_DEATH_INFO_REGNO_P (true_regnum (oldequiv_reg)))
6797 for (prev = PREV_INSN (insn); prev && GET_CODE (prev) != CODE_LABEL;
6798 prev = PREV_INSN (prev))
6799 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
6800 && dead_or_set_p (prev, oldequiv_reg))
6802 if (find_regno_note (prev, REG_DEAD, REGNO (oldequiv_reg)))
6804 for (prev1 = this_reload_insn;
6805 prev1; prev1 = PREV_INSN (prev1))
6806 if (GET_RTX_CLASS (GET_CODE (prev1) == 'i')
6807 && reg_overlap_mentioned_for_reload_p (oldequiv_reg,
6810 REG_NOTES (prev1) = gen_rtx_EXPR_LIST (REG_DEAD,
6815 remove_death (REGNO (oldequiv_reg), prev);
6822 /* If we are reloading a register that was recently stored in with an
6823 output-reload, see if we can prove there was
6824 actually no need to store the old value in it. */
6826 if (optimize && reload_inherited[j] && reload_spill_index[j] >= 0
6827 && reload_in[j] != 0
6828 && GET_CODE (reload_in[j]) == REG
6830 /* There doesn't seem to be any reason to restrict this to pseudos
6831 and doing so loses in the case where we are copying from a
6832 register of the wrong class. */
6833 && REGNO (reload_in[j]) >= FIRST_PSEUDO_REGISTER
6835 && spill_reg_store[reload_spill_index[j]] != 0
6836 /* This is unsafe if some other reload uses the same reg first. */
6837 && reload_reg_free_before_p (reload_spill_index[j],
6838 reload_opnum[j], reload_when_needed[j])
6839 && dead_or_set_p (insn, reload_in[j])
6840 /* This is unsafe if operand occurs more than once in current
6841 insn. Perhaps some occurrences weren't reloaded. */
6842 && (count_occurrences (PATTERN (insn), reload_in[j])
6843 == expect_occurrences))
6844 delete_output_reload (insn, j,
6845 spill_reg_store[reload_spill_index[j]]);
6847 /* Input-reloading is done. Now do output-reloading,
6848 storing the value from the reload-register after the main insn
6849 if reload_out[j] is nonzero.
6851 ??? At some point we need to support handling output reloads of
6852 JUMP_INSNs or insns that set cc0. */
6853 old = reload_out[j];
6855 && reload_reg_rtx[j] != old
6856 && reload_reg_rtx[j] != 0)
6858 register rtx reloadreg = reload_reg_rtx[j];
6859 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6860 register rtx second_reloadreg = 0;
6863 enum machine_mode mode;
6866 /* An output operand that dies right away does need a reload,
6867 but need not be copied from it. Show the new location in the
6869 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6870 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6872 XEXP (note, 0) = reload_reg_rtx[j];
6875 /* Likewise for a SUBREG of an operand that dies. */
6876 else if (GET_CODE (old) == SUBREG
6877 && GET_CODE (SUBREG_REG (old)) == REG
6878 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6881 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6885 else if (GET_CODE (old) == SCRATCH)
6886 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6887 but we don't want to make an output reload. */
6891 /* Strip off of OLD any size-increasing SUBREGs such as
6892 (SUBREG:SI foo:QI 0). */
6894 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
6895 && (GET_MODE_SIZE (GET_MODE (old))
6896 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
6897 old = SUBREG_REG (old);
6900 /* If is a JUMP_INSN, we can't support output reloads yet. */
6901 if (GET_CODE (insn) == JUMP_INSN)
6904 if (reload_when_needed[j] == RELOAD_OTHER)
6907 push_to_sequence (output_reload_insns[reload_opnum[j]]);
6909 /* Determine the mode to reload in.
6910 See comments above (for input reloading). */
6912 mode = GET_MODE (old);
6913 if (mode == VOIDmode)
6915 /* VOIDmode should never happen for an output. */
6916 if (asm_noperands (PATTERN (insn)) < 0)
6917 /* It's the compiler's fault. */
6918 fatal_insn ("VOIDmode on an output", insn);
6919 error_for_asm (insn, "output operand is constant in `asm'");
6920 /* Prevent crash--use something we know is valid. */
6922 old = gen_rtx_REG (mode, REGNO (reloadreg));
6925 if (GET_MODE (reloadreg) != mode)
6926 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6928 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6930 /* If we need two reload regs, set RELOADREG to the intermediate
6931 one, since it will be stored into OLD. We might need a secondary
6932 register only for an input reload, so check again here. */
6934 if (reload_secondary_out_reload[j] >= 0)
6938 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6939 && reg_equiv_mem[REGNO (old)] != 0)
6940 real_old = reg_equiv_mem[REGNO (old)];
6942 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
6946 second_reloadreg = reloadreg;
6947 reloadreg = reload_reg_rtx[reload_secondary_out_reload[j]];
6949 /* See if RELOADREG is to be used as a scratch register
6950 or as an intermediate register. */
6951 if (reload_secondary_out_icode[j] != CODE_FOR_nothing)
6953 emit_insn ((GEN_FCN (reload_secondary_out_icode[j])
6954 (real_old, second_reloadreg, reloadreg)));
6959 /* See if we need both a scratch and intermediate reload
6962 int secondary_reload = reload_secondary_out_reload[j];
6963 enum insn_code tertiary_icode
6964 = reload_secondary_out_icode[secondary_reload];
6966 if (GET_MODE (reloadreg) != mode)
6967 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6969 if (tertiary_icode != CODE_FOR_nothing)
6972 = reload_reg_rtx[reload_secondary_out_reload[secondary_reload]];
6975 /* Copy primary reload reg to secondary reload reg.
6976 (Note that these have been swapped above, then
6977 secondary reload reg to OLD using our insn. */
6979 /* If REAL_OLD is a paradoxical SUBREG, remove it
6980 and try to put the opposite SUBREG on
6982 if (GET_CODE (real_old) == SUBREG
6983 && (GET_MODE_SIZE (GET_MODE (real_old))
6984 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6985 && 0 != (tem = gen_lowpart_common
6986 (GET_MODE (SUBREG_REG (real_old)),
6988 real_old = SUBREG_REG (real_old), reloadreg = tem;
6990 gen_reload (reloadreg, second_reloadreg,
6991 reload_opnum[j], reload_when_needed[j]);
6992 emit_insn ((GEN_FCN (tertiary_icode)
6993 (real_old, reloadreg, third_reloadreg)));
6998 /* Copy between the reload regs here and then to
7001 gen_reload (reloadreg, second_reloadreg,
7002 reload_opnum[j], reload_when_needed[j]);
7008 /* Output the last reload insn. */
7013 /* Don't output the last reload if OLD is not the dest of
7014 INSN and is in the src and is clobbered by INSN. */
7015 if (! flag_expensive_optimizations
7016 || GET_CODE (old) != REG
7017 || !(set = single_set (insn))
7018 || rtx_equal_p (old, SET_DEST (set))
7019 || !reg_mentioned_p (old, SET_SRC (set))
7020 || !regno_clobbered_p (REGNO (old), insn))
7021 gen_reload (old, reloadreg, reload_opnum[j],
7022 reload_when_needed[j]);
7025 #ifdef PRESERVE_DEATH_INFO_REGNO_P
7026 /* If final will look at death notes for this reg,
7027 put one on the last output-reload insn to use it. Similarly
7028 for any secondary register. */
7029 if (PRESERVE_DEATH_INFO_REGNO_P (REGNO (reloadreg)))
7030 for (p = get_last_insn (); p; p = PREV_INSN (p))
7031 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
7032 && reg_overlap_mentioned_for_reload_p (reloadreg,
7034 REG_NOTES (p) = gen_rtx_EXPR_LIST (REG_DEAD,
7035 reloadreg, REG_NOTES (p));
7037 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7038 if (! special && second_reloadreg
7039 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reloadreg)))
7040 for (p = get_last_insn (); p; p = PREV_INSN (p))
7041 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
7042 && reg_overlap_mentioned_for_reload_p (second_reloadreg,
7044 REG_NOTES (p) = gen_rtx_EXPR_LIST (REG_DEAD,
7049 /* Look at all insns we emitted, just to be safe. */
7050 for (p = get_insns (); p; p = NEXT_INSN (p))
7051 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
7053 rtx pat = PATTERN (p);
7055 /* If this output reload doesn't come from a spill reg,
7056 clear any memory of reloaded copies of the pseudo reg.
7057 If this output reload comes from a spill reg,
7058 reg_has_output_reload will make this do nothing. */
7059 note_stores (pat, forget_old_reloads_1);
7061 if (reg_mentioned_p (reload_reg_rtx[j], pat))
7063 if (reload_spill_index[j] < 0
7064 && GET_CODE (pat) == SET
7065 && SET_SRC (pat) == reload_reg_rtx[j])
7067 int src = REGNO (SET_SRC (pat));
7069 reload_spill_index[j] = src;
7070 SET_HARD_REG_BIT (reg_is_output_reload, src);
7071 if (find_regno_note (insn, REG_DEAD, src))
7072 SET_HARD_REG_BIT (reg_reloaded_died, src);
7074 if (reload_spill_index[j] >= 0)
7076 int s = reload_secondary_out_reload[j];
7077 rtx set = single_set (p);
7078 /* If this reload copies only to the secondary reload
7079 register, the secondary reload does the actual
7081 if (s >= 0 && set == NULL_RTX)
7082 ; /* We can't tell what function the secondary reload
7083 has and where the actual store to the pseudo is
7084 made; leave new_spill_reg_store alone. */
7086 && SET_SRC (set) == reload_reg_rtx[j]
7087 && SET_DEST (set) == reload_reg_rtx[s])
7089 /* Usually the next instruction will be the
7090 secondary reload insn; if we can confirm
7091 that it is, setting new_spill_reg_store to
7092 that insn will allow an extra optimization. */
7093 rtx s_reg = reload_reg_rtx[s];
7094 rtx next = NEXT_INSN (p);
7095 reload_out[s] = reload_out[j];
7096 set = single_set (next);
7097 if (set && SET_SRC (set) == s_reg
7098 && ! new_spill_reg_store[REGNO (s_reg)])
7099 new_spill_reg_store[REGNO (s_reg)] = next;
7102 new_spill_reg_store[reload_spill_index[j]] = p;
7107 if (reload_when_needed[j] == RELOAD_OTHER)
7109 emit_insns (other_output_reload_insns[reload_opnum[j]]);
7110 other_output_reload_insns[reload_opnum[j]] = get_insns ();
7113 output_reload_insns[reload_opnum[j]] = get_insns ();
7119 /* Now write all the insns we made for reloads in the order expected by
7120 the allocation functions. Prior to the insn being reloaded, we write
7121 the following reloads:
7123 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7125 RELOAD_OTHER reloads.
7127 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7128 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7129 RELOAD_FOR_INPUT reload for the operand.
7131 RELOAD_FOR_OPADDR_ADDRS reloads.
7133 RELOAD_FOR_OPERAND_ADDRESS reloads.
7135 After the insn being reloaded, we write the following:
7137 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7138 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7139 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7140 reloads for the operand. The RELOAD_OTHER output reloads are
7141 output in descending order by reload number. */
7143 emit_insns_before (other_input_address_reload_insns, before_insn);
7144 emit_insns_before (other_input_reload_insns, before_insn);
7146 for (j = 0; j < reload_n_operands; j++)
7148 emit_insns_before (inpaddr_address_reload_insns[j], before_insn);
7149 emit_insns_before (input_address_reload_insns[j], before_insn);
7150 emit_insns_before (input_reload_insns[j], before_insn);
7153 emit_insns_before (other_operand_reload_insns, before_insn);
7154 emit_insns_before (operand_reload_insns, before_insn);
7156 for (j = 0; j < reload_n_operands; j++)
7158 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
7159 emit_insns_before (output_address_reload_insns[j], following_insn);
7160 emit_insns_before (output_reload_insns[j], following_insn);
7161 emit_insns_before (other_output_reload_insns[j], following_insn);
7164 /* Move death notes from INSN
7165 to output-operand-address and output reload insns. */
7166 #ifdef PRESERVE_DEATH_INFO_REGNO_P
7169 /* Loop over those insns, last ones first. */
7170 for (insn1 = PREV_INSN (following_insn); insn1 != insn;
7171 insn1 = PREV_INSN (insn1))
7172 if (GET_CODE (insn1) == INSN && GET_CODE (PATTERN (insn1)) == SET)
7174 rtx source = SET_SRC (PATTERN (insn1));
7175 rtx dest = SET_DEST (PATTERN (insn1));
7177 /* The note we will examine next. */
7178 rtx reg_notes = REG_NOTES (insn);
7179 /* The place that pointed to this note. */
7180 rtx *prev_reg_note = ®_NOTES (insn);
7182 /* If the note is for something used in the source of this
7183 reload insn, or in the output address, move the note. */
7186 rtx next_reg_notes = XEXP (reg_notes, 1);
7187 if (REG_NOTE_KIND (reg_notes) == REG_DEAD
7188 && GET_CODE (XEXP (reg_notes, 0)) == REG
7189 && ((GET_CODE (dest) != REG
7190 && reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
7192 || reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
7195 *prev_reg_note = next_reg_notes;
7196 XEXP (reg_notes, 1) = REG_NOTES (insn1);
7197 REG_NOTES (insn1) = reg_notes;
7200 prev_reg_note = &XEXP (reg_notes, 1);
7202 reg_notes = next_reg_notes;
7208 /* For all the spill regs newly reloaded in this instruction,
7209 record what they were reloaded from, so subsequent instructions
7210 can inherit the reloads.
7212 Update spill_reg_store for the reloads of this insn.
7213 Copy the elements that were updated in the loop above. */
7215 for (j = 0; j < n_reloads; j++)
7217 register int r = reload_order[j];
7218 register int i = reload_spill_index[r];
7220 /* I is nonneg if this reload used a register.
7221 If reload_reg_rtx[r] is 0, this is an optional reload
7222 that we opted to ignore. */
7224 if (i >= 0 && reload_reg_rtx[r] != 0)
7227 = HARD_REGNO_NREGS (i, GET_MODE (reload_reg_rtx[r]));
7229 int part_reaches_end = 0;
7230 int all_reaches_end = 1;
7232 /* For a multi register reload, we need to check if all or part
7233 of the value lives to the end. */
7234 for (k = 0; k < nr; k++)
7236 if (reload_reg_reaches_end_p (i + k, reload_opnum[r],
7237 reload_when_needed[r]))
7238 part_reaches_end = 1;
7240 all_reaches_end = 0;
7243 /* Ignore reloads that don't reach the end of the insn in
7245 if (all_reaches_end)
7247 /* First, clear out memory of what used to be in this spill reg.
7248 If consecutive registers are used, clear them all. */
7250 for (k = 0; k < nr; k++)
7251 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7253 /* Maybe the spill reg contains a copy of reload_out. */
7254 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
7256 register int nregno = REGNO (reload_out[r]);
7257 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7258 : HARD_REGNO_NREGS (nregno,
7259 GET_MODE (reload_reg_rtx[r])));
7261 spill_reg_store[i] = new_spill_reg_store[i];
7262 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
7264 /* If NREGNO is a hard register, it may occupy more than
7265 one register. If it does, say what is in the
7266 rest of the registers assuming that both registers
7267 agree on how many words the object takes. If not,
7268 invalidate the subsequent registers. */
7270 if (nregno < FIRST_PSEUDO_REGISTER)
7271 for (k = 1; k < nnr; k++)
7272 reg_last_reload_reg[nregno + k]
7274 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
7275 REGNO (reload_reg_rtx[r]) + k)
7278 /* Now do the inverse operation. */
7279 for (k = 0; k < nr; k++)
7281 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7282 reg_reloaded_contents[i + k]
7283 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7286 reg_reloaded_insn[i + k] = insn;
7287 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7291 /* Maybe the spill reg contains a copy of reload_in. Only do
7292 something if there will not be an output reload for
7293 the register being reloaded. */
7294 else if (reload_out[r] == 0
7295 && reload_in[r] != 0
7296 && spill_reg_order[i] >= 0
7297 && ((GET_CODE (reload_in[r]) == REG
7298 && ! reg_has_output_reload[REGNO (reload_in[r])])
7299 || (GET_CODE (reload_in_reg[r]) == REG
7300 && ! reg_has_output_reload[REGNO (reload_in_reg[r])])))
7302 register int nregno;
7305 if (GET_CODE (reload_in[r]) == REG)
7306 nregno = REGNO (reload_in[r]);
7308 nregno = REGNO (reload_in_reg[r]);
7310 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7311 : HARD_REGNO_NREGS (nregno,
7312 GET_MODE (reload_reg_rtx[r])));
7314 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
7316 if (nregno < FIRST_PSEUDO_REGISTER)
7317 for (k = 1; k < nnr; k++)
7318 reg_last_reload_reg[nregno + k]
7320 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
7321 REGNO (reload_reg_rtx[r]) + k)
7324 /* Unless we inherited this reload, show we haven't
7325 recently done a store. */
7326 if (! reload_inherited[r])
7327 spill_reg_store[i] = 0;
7329 for (k = 0; k < nr; k++)
7331 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7332 reg_reloaded_contents[i + k]
7333 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7336 reg_reloaded_insn[i + k] = insn;
7337 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7342 /* However, if part of the reload reaches the end, then we must
7343 invalidate the old info for the part that survives to the end. */
7344 else if (part_reaches_end)
7346 for (k = 0; k < nr; k++)
7347 if (reload_reg_reaches_end_p (i + k,
7349 reload_when_needed[r]))
7350 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7354 /* The following if-statement was #if 0'd in 1.34 (or before...).
7355 It's reenabled in 1.35 because supposedly nothing else
7356 deals with this problem. */
7358 /* If a register gets output-reloaded from a non-spill register,
7359 that invalidates any previous reloaded copy of it.
7360 But forget_old_reloads_1 won't get to see it, because
7361 it thinks only about the original insn. So invalidate it here. */
7362 if (i < 0 && reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
7364 register int nregno = REGNO (reload_out[r]);
7365 if (nregno >= FIRST_PSEUDO_REGISTER)
7366 reg_last_reload_reg[nregno] = 0;
7369 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (reload_out[r]));
7371 while (num_regs-- > 0)
7372 reg_last_reload_reg[nregno + num_regs] = 0;
7376 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7379 /* Emit code to perform a reload from IN (which may be a reload register) to
7380 OUT (which may also be a reload register). IN or OUT is from operand
7381 OPNUM with reload type TYPE.
7383 Returns first insn emitted. */
7386 gen_reload (out, in, opnum, type)
7390 enum reload_type type;
7392 rtx last = get_last_insn ();
7395 /* If IN is a paradoxical SUBREG, remove it and try to put the
7396 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7397 if (GET_CODE (in) == SUBREG
7398 && (GET_MODE_SIZE (GET_MODE (in))
7399 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7400 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7401 in = SUBREG_REG (in), out = tem;
7402 else if (GET_CODE (out) == SUBREG
7403 && (GET_MODE_SIZE (GET_MODE (out))
7404 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7405 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7406 out = SUBREG_REG (out), in = tem;
7408 /* How to do this reload can get quite tricky. Normally, we are being
7409 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7410 register that didn't get a hard register. In that case we can just
7411 call emit_move_insn.
7413 We can also be asked to reload a PLUS that adds a register or a MEM to
7414 another register, constant or MEM. This can occur during frame pointer
7415 elimination and while reloading addresses. This case is handled by
7416 trying to emit a single insn to perform the add. If it is not valid,
7417 we use a two insn sequence.
7419 Finally, we could be called to handle an 'o' constraint by putting
7420 an address into a register. In that case, we first try to do this
7421 with a named pattern of "reload_load_address". If no such pattern
7422 exists, we just emit a SET insn and hope for the best (it will normally
7423 be valid on machines that use 'o').
7425 This entire process is made complex because reload will never
7426 process the insns we generate here and so we must ensure that
7427 they will fit their constraints and also by the fact that parts of
7428 IN might be being reloaded separately and replaced with spill registers.
7429 Because of this, we are, in some sense, just guessing the right approach
7430 here. The one listed above seems to work.
7432 ??? At some point, this whole thing needs to be rethought. */
7434 if (GET_CODE (in) == PLUS
7435 && (GET_CODE (XEXP (in, 0)) == REG
7436 || GET_CODE (XEXP (in, 0)) == SUBREG
7437 || GET_CODE (XEXP (in, 0)) == MEM)
7438 && (GET_CODE (XEXP (in, 1)) == REG
7439 || GET_CODE (XEXP (in, 1)) == SUBREG
7440 || CONSTANT_P (XEXP (in, 1))
7441 || GET_CODE (XEXP (in, 1)) == MEM))
7443 /* We need to compute the sum of a register or a MEM and another
7444 register, constant, or MEM, and put it into the reload
7445 register. The best possible way of doing this is if the machine
7446 has a three-operand ADD insn that accepts the required operands.
7448 The simplest approach is to try to generate such an insn and see if it
7449 is recognized and matches its constraints. If so, it can be used.
7451 It might be better not to actually emit the insn unless it is valid,
7452 but we need to pass the insn as an operand to `recog' and
7453 `insn_extract' and it is simpler to emit and then delete the insn if
7454 not valid than to dummy things up. */
7456 rtx op0, op1, tem, insn;
7459 op0 = find_replacement (&XEXP (in, 0));
7460 op1 = find_replacement (&XEXP (in, 1));
7462 /* Since constraint checking is strict, commutativity won't be
7463 checked, so we need to do that here to avoid spurious failure
7464 if the add instruction is two-address and the second operand
7465 of the add is the same as the reload reg, which is frequently
7466 the case. If the insn would be A = B + A, rearrange it so
7467 it will be A = A + B as constrain_operands expects. */
7469 if (GET_CODE (XEXP (in, 1)) == REG
7470 && REGNO (out) == REGNO (XEXP (in, 1)))
7471 tem = op0, op0 = op1, op1 = tem;
7473 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7474 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7476 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7477 code = recog_memoized (insn);
7481 insn_extract (insn);
7482 /* We want constrain operands to treat this insn strictly in
7483 its validity determination, i.e., the way it would after reload
7485 if (constrain_operands (code, 1))
7489 delete_insns_since (last);
7491 /* If that failed, we must use a conservative two-insn sequence.
7492 use move to copy constant, MEM, or pseudo register to the reload
7493 register since "move" will be able to handle an arbitrary operand,
7494 unlike add which can't, in general. Then add the registers.
7496 If there is another way to do this for a specific machine, a
7497 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7500 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7501 || (GET_CODE (op1) == REG
7502 && REGNO (op1) >= FIRST_PSEUDO_REGISTER))
7503 tem = op0, op0 = op1, op1 = tem;
7505 gen_reload (out, op0, opnum, type);
7507 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7508 This fixes a problem on the 32K where the stack pointer cannot
7509 be used as an operand of an add insn. */
7511 if (rtx_equal_p (op0, op1))
7514 insn = emit_insn (gen_add2_insn (out, op1));
7516 /* If that failed, copy the address register to the reload register.
7517 Then add the constant to the reload register. */
7519 code = recog_memoized (insn);
7523 insn_extract (insn);
7524 /* We want constrain operands to treat this insn strictly in
7525 its validity determination, i.e., the way it would after reload
7527 if (constrain_operands (code, 1))
7529 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7531 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7536 delete_insns_since (last);
7538 gen_reload (out, op1, opnum, type);
7539 insn = emit_insn (gen_add2_insn (out, op0));
7540 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7543 #ifdef SECONDARY_MEMORY_NEEDED
7544 /* If we need a memory location to do the move, do it that way. */
7545 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7546 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7547 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7548 REGNO_REG_CLASS (REGNO (out)),
7551 /* Get the memory to use and rewrite both registers to its mode. */
7552 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7554 if (GET_MODE (loc) != GET_MODE (out))
7555 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7557 if (GET_MODE (loc) != GET_MODE (in))
7558 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7560 gen_reload (loc, in, opnum, type);
7561 gen_reload (out, loc, opnum, type);
7565 /* If IN is a simple operand, use gen_move_insn. */
7566 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7567 emit_insn (gen_move_insn (out, in));
7569 #ifdef HAVE_reload_load_address
7570 else if (HAVE_reload_load_address)
7571 emit_insn (gen_reload_load_address (out, in));
7574 /* Otherwise, just write (set OUT IN) and hope for the best. */
7576 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7578 /* Return the first insn emitted.
7579 We can not just return get_last_insn, because there may have
7580 been multiple instructions emitted. Also note that gen_move_insn may
7581 emit more than one insn itself, so we can not assume that there is one
7582 insn emitted per emit_insn_before call. */
7584 return last ? NEXT_INSN (last) : get_insns ();
7587 /* Delete a previously made output-reload
7588 whose result we now believe is not needed.
7589 First we double-check.
7591 INSN is the insn now being processed.
7592 OUTPUT_RELOAD_INSN is the insn of the output reload.
7593 J is the reload-number for this insn. */
7596 delete_output_reload (insn, j, output_reload_insn)
7599 rtx output_reload_insn;
7603 /* Get the raw pseudo-register referred to. */
7605 rtx reg = reload_in[j];
7606 while (GET_CODE (reg) == SUBREG)
7607 reg = SUBREG_REG (reg);
7609 /* If the pseudo-reg we are reloading is no longer referenced
7610 anywhere between the store into it and here,
7611 and no jumps or labels intervene, then the value can get
7612 here through the reload reg alone.
7613 Otherwise, give up--return. */
7614 for (i1 = NEXT_INSN (output_reload_insn);
7615 i1 != insn; i1 = NEXT_INSN (i1))
7617 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7619 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7620 && reg_mentioned_p (reg, PATTERN (i1)))
7622 /* If this is just a single USE with an REG_EQUAL note in front
7623 of INSN, this is no problem, because this mentions just the
7624 address that we are using here.
7625 But if there is more than one such USE, the insn might use
7626 the operand directly, or another reload might do that.
7627 This is analogous to the count_occurences check in the callers. */
7628 int num_occurences = 0;
7630 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE
7631 && find_reg_note (i1, REG_EQUAL, NULL_RTX))
7633 num_occurences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7634 i1 = NEXT_INSN (i1);
7636 if (num_occurences == 1 && i1 == insn)
7642 /* The caller has already checked that REG dies or is set in INSN.
7643 It has also checked that we are optimizing, and thus some inaccurancies
7644 in the debugging information are acceptable.
7645 So we could just delete output_reload_insn.
7646 But in some cases we can improve the debugging information without
7647 sacrificing optimization - maybe even improving the code:
7648 See if the pseudo reg has been completely replaced
7649 with reload regs. If so, delete the store insn
7650 and forget we had a stack slot for the pseudo. */
7651 if (reload_out[j] != reload_in[j]
7652 && REG_N_DEATHS (REGNO (reg)) == 1
7653 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7654 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7658 /* We know that it was used only between here
7659 and the beginning of the current basic block.
7660 (We also know that the last use before INSN was
7661 the output reload we are thinking of deleting, but never mind that.)
7662 Search that range; see if any ref remains. */
7663 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7665 rtx set = single_set (i2);
7667 /* Uses which just store in the pseudo don't count,
7668 since if they are the only uses, they are dead. */
7669 if (set != 0 && SET_DEST (set) == reg)
7671 if (GET_CODE (i2) == CODE_LABEL
7672 || GET_CODE (i2) == JUMP_INSN)
7674 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7675 && reg_mentioned_p (reg, PATTERN (i2)))
7677 /* Some other ref remains; just delete the output reload we
7679 delete_insn (output_reload_insn);
7684 /* Delete the now-dead stores into this pseudo. */
7685 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7687 rtx set = single_set (i2);
7689 if (set != 0 && SET_DEST (set) == reg)
7691 /* This might be a basic block head,
7692 thus don't use delete_insn. */
7693 PUT_CODE (i2, NOTE);
7694 NOTE_SOURCE_FILE (i2) = 0;
7695 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7697 if (GET_CODE (i2) == CODE_LABEL
7698 || GET_CODE (i2) == JUMP_INSN)
7702 /* For the debugging info,
7703 say the pseudo lives in this reload reg. */
7704 reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
7705 alter_reg (REGNO (reg), -1);
7707 delete_insn (output_reload_insn);
7711 /* Output reload-insns to reload VALUE into RELOADREG.
7712 VALUE is an autoincrement or autodecrement RTX whose operand
7713 is a register or memory location;
7714 so reloading involves incrementing that location.
7716 INC_AMOUNT is the number to increment or decrement by (always positive).
7717 This cannot be deduced from VALUE. */
7720 inc_for_reload (reloadreg, value, inc_amount)
7725 /* REG or MEM to be copied and incremented. */
7726 rtx incloc = XEXP (value, 0);
7727 /* Nonzero if increment after copying. */
7728 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7734 /* No hard register is equivalent to this register after
7735 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7736 we could inc/dec that register as well (maybe even using it for
7737 the source), but I'm not sure it's worth worrying about. */
7738 if (GET_CODE (incloc) == REG)
7739 reg_last_reload_reg[REGNO (incloc)] = 0;
7741 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7742 inc_amount = - inc_amount;
7744 inc = GEN_INT (inc_amount);
7746 /* If this is post-increment, first copy the location to the reload reg. */
7748 emit_insn (gen_move_insn (reloadreg, incloc));
7750 /* See if we can directly increment INCLOC. Use a method similar to that
7753 last = get_last_insn ();
7754 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7755 gen_rtx_PLUS (GET_MODE (incloc),
7758 code = recog_memoized (add_insn);
7761 insn_extract (add_insn);
7762 if (constrain_operands (code, 1))
7764 /* If this is a pre-increment and we have incremented the value
7765 where it lives, copy the incremented value to RELOADREG to
7766 be used as an address. */
7769 emit_insn (gen_move_insn (reloadreg, incloc));
7775 delete_insns_since (last);
7777 /* If couldn't do the increment directly, must increment in RELOADREG.
7778 The way we do this depends on whether this is pre- or post-increment.
7779 For pre-increment, copy INCLOC to the reload register, increment it
7780 there, then save back. */
7784 emit_insn (gen_move_insn (reloadreg, incloc));
7785 emit_insn (gen_add2_insn (reloadreg, inc));
7786 emit_insn (gen_move_insn (incloc, reloadreg));
7791 Because this might be a jump insn or a compare, and because RELOADREG
7792 may not be available after the insn in an input reload, we must do
7793 the incrementation before the insn being reloaded for.
7795 We have already copied INCLOC to RELOADREG. Increment the copy in
7796 RELOADREG, save that back, then decrement RELOADREG so it has
7797 the original value. */
7799 emit_insn (gen_add2_insn (reloadreg, inc));
7800 emit_insn (gen_move_insn (incloc, reloadreg));
7801 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7807 /* Return 1 if we are certain that the constraint-string STRING allows
7808 the hard register REG. Return 0 if we can't be sure of this. */
7811 constraint_accepts_reg_p (string, reg)
7816 int regno = true_regnum (reg);
7819 /* Initialize for first alternative. */
7821 /* Check that each alternative contains `g' or `r'. */
7823 switch (c = *string++)
7826 /* If an alternative lacks `g' or `r', we lose. */
7829 /* If an alternative lacks `g' or `r', we lose. */
7832 /* Initialize for next alternative. */
7837 /* Any general reg wins for this alternative. */
7838 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7842 /* Any reg in specified class wins for this alternative. */
7844 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7846 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
7852 /* Return the number of places FIND appears within X, but don't count
7853 an occurrence if some SET_DEST is FIND. */
7856 count_occurrences (x, find)
7857 register rtx x, find;
7860 register enum rtx_code code;
7861 register char *format_ptr;
7869 code = GET_CODE (x);
7884 if (SET_DEST (x) == find)
7885 return count_occurrences (SET_SRC (x), find);
7892 format_ptr = GET_RTX_FORMAT (code);
7895 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7897 switch (*format_ptr++)
7900 count += count_occurrences (XEXP (x, i), find);
7904 if (XVEC (x, i) != NULL)
7906 for (j = 0; j < XVECLEN (x, i); j++)
7907 count += count_occurrences (XVECEXP (x, i, j), find);
7915 /* This array holds values which are equivalent to a hard register
7916 during reload_cse_regs. Each array element is an EXPR_LIST of
7917 values. Each time a hard register is set, we set the corresponding
7918 array element to the value. Each time a hard register is copied
7919 into memory, we add the memory location to the corresponding array
7920 element. We don't store values or memory addresses with side
7921 effects in this array.
7923 If the value is a CONST_INT, then the mode of the containing
7924 EXPR_LIST is the mode in which that CONST_INT was referenced.
7926 We sometimes clobber a specific entry in a list. In that case, we
7927 just set XEXP (list-entry, 0) to 0. */
7929 static rtx *reg_values;
7931 /* This is a preallocated REG rtx which we use as a temporary in
7932 reload_cse_invalidate_regno, so that we don't need to allocate a
7933 new one each time through a loop in that function. */
7935 static rtx invalidate_regno_rtx;
7937 /* This is a set of registers for which we must remove REG_DEAD notes in
7938 previous insns, because our modifications made them invalid. That can
7939 happen if we introduced the register into the current insn, or we deleted
7940 the current insn which used to set the register. */
7942 static HARD_REG_SET no_longer_dead_regs;
7944 /* Invalidate any entries in reg_values which depend on REGNO,
7945 including those for REGNO itself. This is called if REGNO is
7946 changing. If CLOBBER is true, then always forget anything we
7947 currently know about REGNO. MODE is the mode of the assignment to
7948 REGNO, which is used to determine how many hard registers are being
7949 changed. If MODE is VOIDmode, then only REGNO is being changed;
7950 this is used when invalidating call clobbered registers across a
7954 reload_cse_invalidate_regno (regno, mode, clobber)
7956 enum machine_mode mode;
7962 /* Our callers don't always go through true_regnum; we may see a
7963 pseudo-register here from a CLOBBER or the like. We probably
7964 won't ever see a pseudo-register that has a real register number,
7965 for we check anyhow for safety. */
7966 if (regno >= FIRST_PSEUDO_REGISTER)
7967 regno = reg_renumber[regno];
7971 if (mode == VOIDmode)
7972 endregno = regno + 1;
7974 endregno = regno + HARD_REGNO_NREGS (regno, mode);
7977 for (i = regno; i < endregno; i++)
7980 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
7984 for (x = reg_values[i]; x; x = XEXP (x, 1))
7986 if (XEXP (x, 0) != 0
7987 && refers_to_regno_p (regno, endregno, XEXP (x, 0), NULL_PTR))
7989 /* If this is the only entry on the list, clear
7990 reg_values[i]. Otherwise, just clear this entry on
7992 if (XEXP (x, 1) == 0 && x == reg_values[i])
8002 /* We must look at earlier registers, in case REGNO is part of a
8003 multi word value but is not the first register. If an earlier
8004 register has a value in a mode which overlaps REGNO, then we must
8005 invalidate that earlier register. Note that we do not need to
8006 check REGNO or later registers (we must not check REGNO itself,
8007 because we would incorrectly conclude that there was a conflict). */
8009 for (i = 0; i < regno; i++)
8013 for (x = reg_values[i]; x; x = XEXP (x, 1))
8015 if (XEXP (x, 0) != 0)
8017 PUT_MODE (invalidate_regno_rtx, GET_MODE (x));
8018 REGNO (invalidate_regno_rtx) = i;
8019 if (refers_to_regno_p (regno, endregno, invalidate_regno_rtx,
8022 reload_cse_invalidate_regno (i, VOIDmode, 1);
8030 /* The memory at address MEM_BASE is being changed.
8031 Return whether this change will invalidate VAL. */
8034 reload_cse_mem_conflict_p (mem_base, val)
8042 code = GET_CODE (val);
8045 /* Get rid of a few simple cases quickly. */
8058 if (GET_MODE (mem_base) == BLKmode
8059 || GET_MODE (val) == BLKmode)
8061 if (anti_dependence (val, mem_base))
8063 /* The address may contain nested MEMs. */
8070 fmt = GET_RTX_FORMAT (code);
8072 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8076 if (reload_cse_mem_conflict_p (mem_base, XEXP (val, i)))
8079 else if (fmt[i] == 'E')
8083 for (j = 0; j < XVECLEN (val, i); j++)
8084 if (reload_cse_mem_conflict_p (mem_base, XVECEXP (val, i, j)))
8092 /* Invalidate any entries in reg_values which are changed because of a
8093 store to MEM_RTX. If this is called because of a non-const call
8094 instruction, MEM_RTX is (mem:BLK const0_rtx). */
8097 reload_cse_invalidate_mem (mem_rtx)
8102 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8106 for (x = reg_values[i]; x; x = XEXP (x, 1))
8108 if (XEXP (x, 0) != 0
8109 && reload_cse_mem_conflict_p (mem_rtx, XEXP (x, 0)))
8111 /* If this is the only entry on the list, clear
8112 reg_values[i]. Otherwise, just clear this entry on
8114 if (XEXP (x, 1) == 0 && x == reg_values[i])
8125 /* Invalidate DEST, which is being assigned to or clobbered. The
8126 second parameter exists so that this function can be passed to
8127 note_stores; it is ignored. */
8130 reload_cse_invalidate_rtx (dest, ignore)
8132 rtx ignore ATTRIBUTE_UNUSED;
8134 while (GET_CODE (dest) == STRICT_LOW_PART
8135 || GET_CODE (dest) == SIGN_EXTRACT
8136 || GET_CODE (dest) == ZERO_EXTRACT
8137 || GET_CODE (dest) == SUBREG)
8138 dest = XEXP (dest, 0);
8140 if (GET_CODE (dest) == REG)
8141 reload_cse_invalidate_regno (REGNO (dest), GET_MODE (dest), 1);
8142 else if (GET_CODE (dest) == MEM)
8143 reload_cse_invalidate_mem (dest);
8146 /* Possibly delete death notes on the insns before INSN if modifying INSN
8147 extended the lifespan of the registers. */
8150 reload_cse_delete_death_notes (insn)
8155 for (dreg = 0; dreg < FIRST_PSEUDO_REGISTER; dreg++)
8159 if (! TEST_HARD_REG_BIT (no_longer_dead_regs, dreg))
8162 for (trial = prev_nonnote_insn (insn);
8164 && GET_CODE (trial) != CODE_LABEL
8165 && GET_CODE (trial) != BARRIER);
8166 trial = prev_nonnote_insn (trial))
8168 if (find_regno_note (trial, REG_DEAD, dreg))
8170 remove_death (dreg, trial);
8177 /* Record that the current insn uses hard reg REGNO in mode MODE. This
8178 will be used in reload_cse_delete_death_notes to delete prior REG_DEAD
8179 notes for this register. */
8182 reload_cse_no_longer_dead (regno, mode)
8184 enum machine_mode mode;
8186 int nregs = HARD_REGNO_NREGS (regno, mode);
8189 SET_HARD_REG_BIT (no_longer_dead_regs, regno);
8195 /* Do a very simple CSE pass over the hard registers.
8197 This function detects no-op moves where we happened to assign two
8198 different pseudo-registers to the same hard register, and then
8199 copied one to the other. Reload will generate a useless
8200 instruction copying a register to itself.
8202 This function also detects cases where we load a value from memory
8203 into two different registers, and (if memory is more expensive than
8204 registers) changes it to simply copy the first register into the
8207 Another optimization is performed that scans the operands of each
8208 instruction to see whether the value is already available in a
8209 hard register. It then replaces the operand with the hard register
8210 if possible, much like an optional reload would. */
8213 reload_cse_regs (first)
8221 init_alias_analysis ();
8223 reg_values = (rtx *) alloca (FIRST_PSEUDO_REGISTER * sizeof (rtx));
8224 bzero ((char *)reg_values, FIRST_PSEUDO_REGISTER * sizeof (rtx));
8226 /* Create our EXPR_LIST structures on reload_obstack, so that we can
8227 free them when we are done. */
8228 push_obstacks (&reload_obstack, &reload_obstack);
8229 firstobj = (char *) obstack_alloc (&reload_obstack, 0);
8231 /* We pass this to reload_cse_invalidate_mem to invalidate all of
8232 memory for a non-const call instruction. */
8233 callmem = gen_rtx_MEM (BLKmode, const0_rtx);
8235 /* This is used in reload_cse_invalidate_regno to avoid consing a
8236 new REG in a loop in that function. */
8237 invalidate_regno_rtx = gen_rtx_REG (VOIDmode, 0);
8239 for (insn = first; insn; insn = NEXT_INSN (insn))
8243 if (GET_CODE (insn) == CODE_LABEL)
8245 /* Forget all the register values at a code label. We don't
8246 try to do anything clever around jumps. */
8247 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8253 #ifdef NON_SAVING_SETJMP
8254 if (NON_SAVING_SETJMP && GET_CODE (insn) == NOTE
8255 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
8257 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8264 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8267 CLEAR_HARD_REG_SET (no_longer_dead_regs);
8269 /* If this is a call instruction, forget anything stored in a
8270 call clobbered register, or, if this is not a const call, in
8272 if (GET_CODE (insn) == CALL_INSN)
8274 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8275 if (call_used_regs[i])
8276 reload_cse_invalidate_regno (i, VOIDmode, 1);
8278 if (! CONST_CALL_P (insn))
8279 reload_cse_invalidate_mem (callmem);
8282 body = PATTERN (insn);
8283 if (GET_CODE (body) == SET)
8286 if (reload_cse_noop_set_p (body, insn))
8288 PUT_CODE (insn, NOTE);
8289 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8290 NOTE_SOURCE_FILE (insn) = 0;
8291 reload_cse_delete_death_notes (insn);
8293 /* We're done with this insn. */
8297 /* It's not a no-op, but we can try to simplify it. */
8298 CLEAR_HARD_REG_SET (no_longer_dead_regs);
8299 count += reload_cse_simplify_set (body, insn);
8301 if (count > 0 && apply_change_group ())
8302 reload_cse_delete_death_notes (insn);
8303 else if (reload_cse_simplify_operands (insn))
8304 reload_cse_delete_death_notes (insn);
8306 reload_cse_record_set (body, body);
8308 else if (GET_CODE (body) == PARALLEL)
8312 /* If every action in a PARALLEL is a noop, we can delete
8313 the entire PARALLEL. */
8314 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8315 if ((GET_CODE (XVECEXP (body, 0, i)) != SET
8316 || ! reload_cse_noop_set_p (XVECEXP (body, 0, i), insn))
8317 && GET_CODE (XVECEXP (body, 0, i)) != CLOBBER)
8321 PUT_CODE (insn, NOTE);
8322 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8323 NOTE_SOURCE_FILE (insn) = 0;
8324 reload_cse_delete_death_notes (insn);
8326 /* We're done with this insn. */
8330 /* It's not a no-op, but we can try to simplify it. */
8331 CLEAR_HARD_REG_SET (no_longer_dead_regs);
8332 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8333 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8334 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8336 if (count > 0 && apply_change_group ())
8337 reload_cse_delete_death_notes (insn);
8338 else if (reload_cse_simplify_operands (insn))
8339 reload_cse_delete_death_notes (insn);
8341 /* Look through the PARALLEL and record the values being
8342 set, if possible. Also handle any CLOBBERs. */
8343 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8345 rtx x = XVECEXP (body, 0, i);
8347 if (GET_CODE (x) == SET)
8348 reload_cse_record_set (x, body);
8350 note_stores (x, reload_cse_invalidate_rtx);
8354 note_stores (body, reload_cse_invalidate_rtx);
8357 /* Clobber any registers which appear in REG_INC notes. We
8358 could keep track of the changes to their values, but it is
8359 unlikely to help. */
8363 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
8364 if (REG_NOTE_KIND (x) == REG_INC)
8365 reload_cse_invalidate_rtx (XEXP (x, 0), NULL_RTX);
8369 /* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only
8370 after we have processed the insn. */
8371 if (GET_CODE (insn) == CALL_INSN)
8375 for (x = CALL_INSN_FUNCTION_USAGE (insn); x; x = XEXP (x, 1))
8376 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
8377 reload_cse_invalidate_rtx (XEXP (XEXP (x, 0), 0), NULL_RTX);
8381 /* Free all the temporary structures we created, and go back to the
8382 regular obstacks. */
8383 obstack_free (&reload_obstack, firstobj);
8387 /* Return whether the values known for REGNO are equal to VAL. MODE
8388 is the mode of the object that VAL is being copied to; this matters
8389 if VAL is a CONST_INT. */
8392 reload_cse_regno_equal_p (regno, val, mode)
8395 enum machine_mode mode;
8402 for (x = reg_values[regno]; x; x = XEXP (x, 1))
8403 if (XEXP (x, 0) != 0
8404 && rtx_equal_p (XEXP (x, 0), val)
8405 && (! flag_float_store || GET_CODE (XEXP (x, 0)) != MEM
8406 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
8407 && (GET_CODE (val) != CONST_INT
8408 || mode == GET_MODE (x)
8409 || (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8410 /* On a big endian machine if the value spans more than
8411 one register then this register holds the high part of
8412 it and we can't use it.
8414 ??? We should also compare with the high part of the
8416 && !(WORDS_BIG_ENDIAN
8417 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
8418 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
8419 GET_MODE_BITSIZE (GET_MODE (x))))))
8425 /* See whether a single set is a noop. SET is the set instruction we
8426 are should check, and INSN is the instruction from which it came. */
8429 reload_cse_noop_set_p (set, insn)
8434 enum machine_mode dest_mode;
8438 src = SET_SRC (set);
8439 dest = SET_DEST (set);
8440 dest_mode = GET_MODE (dest);
8442 if (side_effects_p (src))
8445 dreg = true_regnum (dest);
8446 sreg = true_regnum (src);
8448 /* Check for setting a register to itself. In this case, we don't
8449 have to worry about REG_DEAD notes. */
8450 if (dreg >= 0 && dreg == sreg)
8456 /* Check for setting a register to itself. */
8460 /* Check for setting a register to a value which we already know
8461 is in the register. */
8462 else if (reload_cse_regno_equal_p (dreg, src, dest_mode))
8465 /* Check for setting a register DREG to another register SREG
8466 where SREG is equal to a value which is already in DREG. */
8471 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
8475 if (XEXP (x, 0) == 0)
8478 if (dest_mode == GET_MODE (x))
8480 else if (GET_MODE_BITSIZE (dest_mode)
8481 < GET_MODE_BITSIZE (GET_MODE (x)))
8482 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
8487 && reload_cse_regno_equal_p (dreg, tmp, dest_mode))
8495 else if (GET_CODE (dest) == MEM)
8497 /* Check for storing a register to memory when we know that the
8498 register is equivalent to the memory location. */
8500 && reload_cse_regno_equal_p (sreg, dest, dest_mode)
8501 && ! side_effects_p (dest))
8505 /* If we can delete this SET, then we need to look for an earlier
8506 REG_DEAD note on DREG, and remove it if it exists. */
8507 if (ret && dreg >= 0)
8509 if (! find_regno_note (insn, REG_UNUSED, dreg))
8510 reload_cse_no_longer_dead (dreg, dest_mode);
8516 /* Try to simplify a single SET instruction. SET is the set pattern.
8517 INSN is the instruction it came from.
8518 This function only handles one case: if we set a register to a value
8519 which is not a register, we try to find that value in some other register
8520 and change the set into a register copy. */
8523 reload_cse_simplify_set (set, insn)
8529 enum machine_mode dest_mode;
8530 enum reg_class dclass;
8533 dreg = true_regnum (SET_DEST (set));
8537 src = SET_SRC (set);
8538 if (side_effects_p (src) || true_regnum (src) >= 0)
8541 dclass = REGNO_REG_CLASS (dreg);
8543 /* If memory loads are cheaper than register copies, don't change them. */
8544 if (GET_CODE (src) == MEM
8545 && MEMORY_MOVE_COST (GET_MODE (src), dclass, 1) < 2)
8548 /* If the constant is cheaper than a register, don't change it. */
8549 if (CONSTANT_P (src)
8550 && rtx_cost (src, SET) < 2)
8553 dest_mode = GET_MODE (SET_DEST (set));
8554 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8557 && REGISTER_MOVE_COST (REGNO_REG_CLASS (i), dclass) == 2
8558 && reload_cse_regno_equal_p (i, src, dest_mode))
8562 /* Pop back to the real obstacks while changing the insn. */
8565 validated = validate_change (insn, &SET_SRC (set),
8566 gen_rtx_REG (dest_mode, i), 1);
8568 /* Go back to the obstack we are using for temporary
8570 push_obstacks (&reload_obstack, &reload_obstack);
8572 if (validated && ! find_regno_note (insn, REG_UNUSED, i))
8574 reload_cse_no_longer_dead (i, dest_mode);
8582 /* Try to replace operands in INSN with equivalent values that are already
8583 in registers. This can be viewed as optional reloading.
8585 For each non-register operand in the insn, see if any hard regs are
8586 known to be equivalent to that operand. Record the alternatives which
8587 can accept these hard registers. Among all alternatives, select the
8588 ones which are better or equal to the one currently matching, where
8589 "better" is in terms of '?' and '!' constraints. Among the remaining
8590 alternatives, select the one which replaces most operands with
8594 reload_cse_simplify_operands (insn)
8597 #ifdef REGISTER_CONSTRAINTS
8598 int insn_code_number, n_operands, n_alternatives;
8601 char *constraints[MAX_RECOG_OPERANDS];
8603 /* Vector recording how bad an alternative is. */
8604 int *alternative_reject;
8605 /* Vector recording how many registers can be introduced by choosing
8606 this alternative. */
8607 int *alternative_nregs;
8608 /* Array of vectors recording, for each operand and each alternative,
8609 which hard register to substitute, or -1 if the operand should be
8611 int *op_alt_regno[MAX_RECOG_OPERANDS];
8612 /* Array of alternatives, sorted in order of decreasing desirability. */
8613 int *alternative_order;
8614 rtx reg = gen_rtx_REG (VOIDmode, -1);
8616 /* Find out some information about this insn. */
8617 insn_code_number = recog_memoized (insn);
8618 /* We don't modify asm instructions. */
8619 if (insn_code_number < 0)
8622 n_operands = insn_n_operands[insn_code_number];
8623 n_alternatives = insn_n_alternatives[insn_code_number];
8625 if (n_alternatives == 0 || n_operands == 0)
8627 insn_extract (insn);
8629 /* Figure out which alternative currently matches. */
8630 if (! constrain_operands (insn_code_number, 1))
8631 fatal_insn_not_found (insn);
8633 alternative_reject = (int *) alloca (n_alternatives * sizeof (int));
8634 alternative_nregs = (int *) alloca (n_alternatives * sizeof (int));
8635 alternative_order = (int *) alloca (n_alternatives * sizeof (int));
8636 bzero ((char *)alternative_reject, n_alternatives * sizeof (int));
8637 bzero ((char *)alternative_nregs, n_alternatives * sizeof (int));
8639 for (i = 0; i < n_operands; i++)
8641 enum machine_mode mode;
8645 op_alt_regno[i] = (int *) alloca (n_alternatives * sizeof (int));
8646 for (j = 0; j < n_alternatives; j++)
8647 op_alt_regno[i][j] = -1;
8649 p = constraints[i] = insn_operand_constraint[insn_code_number][i];
8650 mode = insn_operand_mode[insn_code_number][i];
8652 /* Add the reject values for each alternative given by the constraints
8653 for this operand. */
8661 alternative_reject[j] += 3;
8663 alternative_reject[j] += 300;
8666 /* We won't change operands which are already registers. We
8667 also don't want to modify output operands. */
8668 regno = true_regnum (recog_operand[i]);
8670 || constraints[i][0] == '='
8671 || constraints[i][0] == '+')
8674 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8676 int class = (int) NO_REGS;
8678 if (! reload_cse_regno_equal_p (regno, recog_operand[i], mode))
8681 REGNO (reg) = regno;
8682 PUT_MODE (reg, mode);
8684 /* We found a register equal to this operand. Now look for all
8685 alternatives that can accept this register and have not been
8686 assigned a register they can use yet. */
8695 case '=': case '+': case '?':
8696 case '#': case '&': case '!':
8698 case '0': case '1': case '2': case '3': case '4':
8699 case 'm': case '<': case '>': case 'V': case 'o':
8700 case 'E': case 'F': case 'G': case 'H':
8701 case 's': case 'i': case 'n':
8702 case 'I': case 'J': case 'K': case 'L':
8703 case 'M': case 'N': case 'O': case 'P':
8704 #ifdef EXTRA_CONSTRAINT
8705 case 'Q': case 'R': case 'S': case 'T': case 'U':
8708 /* These don't say anything we care about. */
8712 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8717 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER (c)];
8720 case ',': case '\0':
8721 /* See if REGNO fits this alternative, and set it up as the
8722 replacement register if we don't have one for this
8723 alternative yet and the operand being replaced is not
8724 a cheap CONST_INT. */
8725 if (op_alt_regno[i][j] == -1
8726 && reg_fits_class_p (reg, class, 0, mode)
8727 && (GET_CODE (recog_operand[i]) != CONST_INT
8728 || rtx_cost (recog_operand[i], SET) > rtx_cost (reg, SET)))
8730 alternative_nregs[j]++;
8731 op_alt_regno[i][j] = regno;
8743 /* Record all alternatives which are better or equal to the currently
8744 matching one in the alternative_order array. */
8745 for (i = j = 0; i < n_alternatives; i++)
8746 if (alternative_reject[i] <= alternative_reject[which_alternative])
8747 alternative_order[j++] = i;
8750 /* Sort it. Given a small number of alternatives, a dumb algorithm
8751 won't hurt too much. */
8752 for (i = 0; i < n_alternatives - 1; i++)
8755 int best_reject = alternative_reject[alternative_order[i]];
8756 int best_nregs = alternative_nregs[alternative_order[i]];
8759 for (j = i + 1; j < n_alternatives; j++)
8761 int this_reject = alternative_reject[alternative_order[j]];
8762 int this_nregs = alternative_nregs[alternative_order[j]];
8764 if (this_reject < best_reject
8765 || (this_reject == best_reject && this_nregs < best_nregs))
8768 best_reject = this_reject;
8769 best_nregs = this_nregs;
8773 tmp = alternative_order[best];
8774 alternative_order[best] = alternative_order[i];
8775 alternative_order[i] = tmp;
8778 /* Substitute the operands as determined by op_alt_regno for the best
8780 j = alternative_order[0];
8781 CLEAR_HARD_REG_SET (no_longer_dead_regs);
8783 /* Pop back to the real obstacks while changing the insn. */
8786 for (i = 0; i < n_operands; i++)
8788 enum machine_mode mode = insn_operand_mode[insn_code_number][i];
8789 if (op_alt_regno[i][j] == -1)
8792 reload_cse_no_longer_dead (op_alt_regno[i][j], mode);
8793 validate_change (insn, recog_operand_loc[i],
8794 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8797 for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--)
8799 int op = recog_dup_num[i];
8800 enum machine_mode mode = insn_operand_mode[insn_code_number][op];
8802 if (op_alt_regno[op][j] == -1)
8805 reload_cse_no_longer_dead (op_alt_regno[op][j], mode);
8806 validate_change (insn, recog_dup_loc[i],
8807 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8810 /* Go back to the obstack we are using for temporary
8812 push_obstacks (&reload_obstack, &reload_obstack);
8814 return apply_change_group ();
8820 /* These two variables are used to pass information from
8821 reload_cse_record_set to reload_cse_check_clobber. */
8823 static int reload_cse_check_clobbered;
8824 static rtx reload_cse_check_src;
8826 /* See if DEST overlaps with RELOAD_CSE_CHECK_SRC. If it does, set
8827 RELOAD_CSE_CHECK_CLOBBERED. This is called via note_stores. The
8828 second argument, which is passed by note_stores, is ignored. */
8831 reload_cse_check_clobber (dest, ignore)
8833 rtx ignore ATTRIBUTE_UNUSED;
8835 if (reg_overlap_mentioned_p (dest, reload_cse_check_src))
8836 reload_cse_check_clobbered = 1;
8839 /* Record the result of a SET instruction. SET is the set pattern.
8840 BODY is the pattern of the insn that it came from. */
8843 reload_cse_record_set (set, body)
8849 enum machine_mode dest_mode;
8851 dest = SET_DEST (set);
8852 src = SET_SRC (set);
8853 dreg = true_regnum (dest);
8854 sreg = true_regnum (src);
8855 dest_mode = GET_MODE (dest);
8857 /* Some machines don't define AUTO_INC_DEC, but they still use push
8858 instructions. We need to catch that case here in order to
8859 invalidate the stack pointer correctly. Note that invalidating
8860 the stack pointer is different from invalidating DEST. */
8862 while (GET_CODE (x) == SUBREG
8863 || GET_CODE (x) == ZERO_EXTRACT
8864 || GET_CODE (x) == SIGN_EXTRACT
8865 || GET_CODE (x) == STRICT_LOW_PART)
8867 if (push_operand (x, GET_MODE (x)))
8869 reload_cse_invalidate_rtx (stack_pointer_rtx, NULL_RTX);
8870 reload_cse_invalidate_rtx (dest, NULL_RTX);
8874 /* We can only handle an assignment to a register, or a store of a
8875 register to a memory location. For other cases, we just clobber
8876 the destination. We also have to just clobber if there are side
8877 effects in SRC or DEST. */
8878 if ((dreg < 0 && GET_CODE (dest) != MEM)
8879 || side_effects_p (src)
8880 || side_effects_p (dest))
8882 reload_cse_invalidate_rtx (dest, NULL_RTX);
8887 /* We don't try to handle values involving CC, because it's a pain
8888 to keep track of when they have to be invalidated. */
8889 if (reg_mentioned_p (cc0_rtx, src)
8890 || reg_mentioned_p (cc0_rtx, dest))
8892 reload_cse_invalidate_rtx (dest, NULL_RTX);
8897 /* If BODY is a PARALLEL, then we need to see whether the source of
8898 SET is clobbered by some other instruction in the PARALLEL. */
8899 if (GET_CODE (body) == PARALLEL)
8903 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8907 x = XVECEXP (body, 0, i);
8911 reload_cse_check_clobbered = 0;
8912 reload_cse_check_src = src;
8913 note_stores (x, reload_cse_check_clobber);
8914 if (reload_cse_check_clobbered)
8916 reload_cse_invalidate_rtx (dest, NULL_RTX);
8926 /* This is an assignment to a register. Update the value we
8927 have stored for the register. */
8932 /* This is a copy from one register to another. Any values
8933 which were valid for SREG are now valid for DREG. If the
8934 mode changes, we use gen_lowpart_common to extract only
8935 the part of the value that is copied. */
8936 reg_values[dreg] = 0;
8937 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
8941 if (XEXP (x, 0) == 0)
8943 if (dest_mode == GET_MODE (XEXP (x, 0)))
8945 else if (GET_MODE_BITSIZE (dest_mode)
8946 > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
8949 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
8951 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, tmp,
8956 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, src, NULL_RTX);
8958 /* We've changed DREG, so invalidate any values held by other
8959 registers that depend upon it. */
8960 reload_cse_invalidate_regno (dreg, dest_mode, 0);
8962 /* If this assignment changes more than one hard register,
8963 forget anything we know about the others. */
8964 for (i = 1; i < HARD_REGNO_NREGS (dreg, dest_mode); i++)
8965 reg_values[dreg + i] = 0;
8967 else if (GET_CODE (dest) == MEM)
8969 /* Invalidate conflicting memory locations. */
8970 reload_cse_invalidate_mem (dest);
8972 /* If we're storing a register to memory, add DEST to the list
8974 if (sreg >= 0 && ! side_effects_p (dest))
8975 reg_values[sreg] = gen_rtx_EXPR_LIST (dest_mode, dest,
8980 /* We should have bailed out earlier. */
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