1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 88, 89, 92-99, 2000 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "insn-flags.h"
32 #include "insn-codes.h"
37 #include "basic-block.h"
44 #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY
45 #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
48 /* This file contains the reload pass of the compiler, which is
49 run after register allocation has been done. It checks that
50 each insn is valid (operands required to be in registers really
51 are in registers of the proper class) and fixes up invalid ones
52 by copying values temporarily into registers for the insns
55 The results of register allocation are described by the vector
56 reg_renumber; the insns still contain pseudo regs, but reg_renumber
57 can be used to find which hard reg, if any, a pseudo reg is in.
59 The technique we always use is to free up a few hard regs that are
60 called ``reload regs'', and for each place where a pseudo reg
61 must be in a hard reg, copy it temporarily into one of the reload regs.
63 Reload regs are allocated locally for every instruction that needs
64 reloads. When there are pseudos which are allocated to a register that
65 has been chosen as a reload reg, such pseudos must be ``spilled''.
66 This means that they go to other hard regs, or to stack slots if no other
67 available hard regs can be found. Spilling can invalidate more
68 insns, requiring additional need for reloads, so we must keep checking
69 until the process stabilizes.
71 For machines with different classes of registers, we must keep track
72 of the register class needed for each reload, and make sure that
73 we allocate enough reload registers of each class.
75 The file reload.c contains the code that checks one insn for
76 validity and reports the reloads that it needs. This file
77 is in charge of scanning the entire rtl code, accumulating the
78 reload needs, spilling, assigning reload registers to use for
79 fixing up each insn, and generating the new insns to copy values
80 into the reload registers. */
83 #ifndef REGISTER_MOVE_COST
84 #define REGISTER_MOVE_COST(x, y) 2
87 /* During reload_as_needed, element N contains a REG rtx for the hard reg
88 into which reg N has been reloaded (perhaps for a previous insn). */
89 static rtx *reg_last_reload_reg;
91 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
92 for an output reload that stores into reg N. */
93 static char *reg_has_output_reload;
95 /* Indicates which hard regs are reload-registers for an output reload
96 in the current insn. */
97 static HARD_REG_SET reg_is_output_reload;
99 /* Element N is the constant value to which pseudo reg N is equivalent,
100 or zero if pseudo reg N is not equivalent to a constant.
101 find_reloads looks at this in order to replace pseudo reg N
102 with the constant it stands for. */
103 rtx *reg_equiv_constant;
105 /* Element N is a memory location to which pseudo reg N is equivalent,
106 prior to any register elimination (such as frame pointer to stack
107 pointer). Depending on whether or not it is a valid address, this value
108 is transferred to either reg_equiv_address or reg_equiv_mem. */
109 rtx *reg_equiv_memory_loc;
111 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
112 This is used when the address is not valid as a memory address
113 (because its displacement is too big for the machine.) */
114 rtx *reg_equiv_address;
116 /* Element N is the memory slot to which pseudo reg N is equivalent,
117 or zero if pseudo reg N is not equivalent to a memory slot. */
120 /* Widest width in which each pseudo reg is referred to (via subreg). */
121 static int *reg_max_ref_width;
123 /* Element N is the list of insns that initialized reg N from its equivalent
124 constant or memory slot. */
125 static rtx *reg_equiv_init;
127 /* Vector to remember old contents of reg_renumber before spilling. */
128 static short *reg_old_renumber;
130 /* During reload_as_needed, element N contains the last pseudo regno reloaded
131 into hard register N. If that pseudo reg occupied more than one register,
132 reg_reloaded_contents points to that pseudo for each spill register in
133 use; all of these must remain set for an inheritance to occur. */
134 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
136 /* During reload_as_needed, element N contains the insn for which
137 hard register N was last used. Its contents are significant only
138 when reg_reloaded_valid is set for this register. */
139 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
141 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
142 static HARD_REG_SET reg_reloaded_valid;
143 /* Indicate if the register was dead at the end of the reload.
144 This is only valid if reg_reloaded_contents is set and valid. */
145 static HARD_REG_SET reg_reloaded_dead;
147 /* Number of spill-regs so far; number of valid elements of spill_regs. */
150 /* In parallel with spill_regs, contains REG rtx's for those regs.
151 Holds the last rtx used for any given reg, or 0 if it has never
152 been used for spilling yet. This rtx is reused, provided it has
154 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
156 /* In parallel with spill_regs, contains nonzero for a spill reg
157 that was stored after the last time it was used.
158 The precise value is the insn generated to do the store. */
159 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
161 /* This is the register that was stored with spill_reg_store. This is a
162 copy of reload_out / reload_out_reg when the value was stored; if
163 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
164 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
166 /* This table is the inverse mapping of spill_regs:
167 indexed by hard reg number,
168 it contains the position of that reg in spill_regs,
169 or -1 for something that is not in spill_regs.
171 ?!? This is no longer accurate. */
172 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
174 /* This reg set indicates registers that can't be used as spill registers for
175 the currently processed insn. These are the hard registers which are live
176 during the insn, but not allocated to pseudos, as well as fixed
178 static HARD_REG_SET bad_spill_regs;
180 /* These are the hard registers that can't be used as spill register for any
181 insn. This includes registers used for user variables and registers that
182 we can't eliminate. A register that appears in this set also can't be used
183 to retry register allocation. */
184 static HARD_REG_SET bad_spill_regs_global;
186 /* Describes order of use of registers for reloading
187 of spilled pseudo-registers. `n_spills' is the number of
188 elements that are actually valid; new ones are added at the end.
190 Both spill_regs and spill_reg_order are used on two occasions:
191 once during find_reload_regs, where they keep track of the spill registers
192 for a single insn, but also during reload_as_needed where they show all
193 the registers ever used by reload. For the latter case, the information
194 is calculated during finish_spills. */
195 static short spill_regs[FIRST_PSEUDO_REGISTER];
197 /* This vector of reg sets indicates, for each pseudo, which hard registers
198 may not be used for retrying global allocation because the register was
199 formerly spilled from one of them. If we allowed reallocating a pseudo to
200 a register that it was already allocated to, reload might not
202 static HARD_REG_SET *pseudo_previous_regs;
204 /* This vector of reg sets indicates, for each pseudo, which hard
205 registers may not be used for retrying global allocation because they
206 are used as spill registers during one of the insns in which the
208 static HARD_REG_SET *pseudo_forbidden_regs;
210 /* All hard regs that have been used as spill registers for any insn are
211 marked in this set. */
212 static HARD_REG_SET used_spill_regs;
214 /* Index of last register assigned as a spill register. We allocate in
215 a round-robin fashion. */
216 static int last_spill_reg;
218 /* Nonzero if indirect addressing is supported on the machine; this means
219 that spilling (REG n) does not require reloading it into a register in
220 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
221 value indicates the level of indirect addressing supported, e.g., two
222 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
224 static char spill_indirect_levels;
226 /* Nonzero if indirect addressing is supported when the innermost MEM is
227 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
228 which these are valid is the same as spill_indirect_levels, above. */
229 char indirect_symref_ok;
231 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
232 char double_reg_address_ok;
234 /* Record the stack slot for each spilled hard register. */
235 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
237 /* Width allocated so far for that stack slot. */
238 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
240 /* Record which pseudos needed to be spilled. */
241 static regset_head spilled_pseudos;
243 /* Used for communication between order_regs_for_reload and count_pseudo.
244 Used to avoid counting one pseudo twice. */
245 static regset_head pseudos_counted;
247 /* First uid used by insns created by reload in this function.
248 Used in find_equiv_reg. */
249 int reload_first_uid;
251 /* Flag set by local-alloc or global-alloc if anything is live in
252 a call-clobbered reg across calls. */
253 int caller_save_needed;
255 /* Set to 1 while reload_as_needed is operating.
256 Required by some machines to handle any generated moves differently. */
257 int reload_in_progress = 0;
259 /* These arrays record the insn_code of insns that may be needed to
260 perform input and output reloads of special objects. They provide a
261 place to pass a scratch register. */
262 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
263 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
265 /* This obstack is used for allocation of rtl during register elimination.
266 The allocated storage can be freed once find_reloads has processed the
268 struct obstack reload_obstack;
270 /* Points to the beginning of the reload_obstack. All insn_chain structures
271 are allocated first. */
272 char *reload_startobj;
274 /* The point after all insn_chain structures. Used to quickly deallocate
275 memory allocated in copy_reloads during calculate_needs_all_insns. */
276 char *reload_firstobj;
278 /* This points before all local rtl generated by register elimination.
279 Used to quickly free all memory after processing one insn. */
280 static char *reload_insn_firstobj;
282 #define obstack_chunk_alloc xmalloc
283 #define obstack_chunk_free free
285 /* List of insn_chain instructions, one for every insn that reload needs to
287 struct insn_chain *reload_insn_chain;
290 extern tree current_function_decl;
292 extern union tree_node *current_function_decl;
295 /* List of all insns needing reloads. */
296 static struct insn_chain *insns_need_reload;
298 /* This structure is used to record information about register eliminations.
299 Each array entry describes one possible way of eliminating a register
300 in favor of another. If there is more than one way of eliminating a
301 particular register, the most preferred should be specified first. */
305 int from; /* Register number to be eliminated. */
306 int to; /* Register number used as replacement. */
307 int initial_offset; /* Initial difference between values. */
308 int can_eliminate; /* Non-zero if this elimination can be done. */
309 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
310 insns made by reload. */
311 int offset; /* Current offset between the two regs. */
312 int previous_offset; /* Offset at end of previous insn. */
313 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
314 rtx from_rtx; /* REG rtx for the register to be eliminated.
315 We cannot simply compare the number since
316 we might then spuriously replace a hard
317 register corresponding to a pseudo
318 assigned to the reg to be eliminated. */
319 rtx to_rtx; /* REG rtx for the replacement. */
322 static struct elim_table * reg_eliminate = 0;
324 /* This is an intermediate structure to initialize the table. It has
325 exactly the members provided by ELIMINABLE_REGS. */
326 static struct elim_table_1
330 } reg_eliminate_1[] =
332 /* If a set of eliminable registers was specified, define the table from it.
333 Otherwise, default to the normal case of the frame pointer being
334 replaced by the stack pointer. */
336 #ifdef ELIMINABLE_REGS
339 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
342 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate_1/sizeof reg_eliminate_1[0])
344 /* Record the number of pending eliminations that have an offset not equal
345 to their initial offset. If non-zero, we use a new copy of each
346 replacement result in any insns encountered. */
347 int num_not_at_initial_offset;
349 /* Count the number of registers that we may be able to eliminate. */
350 static int num_eliminable;
351 /* And the number of registers that are equivalent to a constant that
352 can be eliminated to frame_pointer / arg_pointer + constant. */
353 static int num_eliminable_invariants;
355 /* For each label, we record the offset of each elimination. If we reach
356 a label by more than one path and an offset differs, we cannot do the
357 elimination. This information is indexed by the number of the label.
358 The first table is an array of flags that records whether we have yet
359 encountered a label and the second table is an array of arrays, one
360 entry in the latter array for each elimination. */
362 static char *offsets_known_at;
363 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
365 /* Number of labels in the current function. */
367 static int num_labels;
369 static void maybe_fix_stack_asms PARAMS ((void));
370 static void copy_reloads PARAMS ((struct insn_chain *));
371 static void calculate_needs_all_insns PARAMS ((int));
372 static int find_reg PARAMS ((struct insn_chain *, int,
374 static void find_reload_regs PARAMS ((struct insn_chain *, FILE *));
375 static void select_reload_regs PARAMS ((FILE *));
376 static void delete_caller_save_insns PARAMS ((void));
378 static void spill_failure PARAMS ((rtx, enum reg_class));
379 static void count_spilled_pseudo PARAMS ((int, int, int));
380 static void delete_dead_insn PARAMS ((rtx));
381 static void alter_reg PARAMS ((int, int));
382 static void set_label_offsets PARAMS ((rtx, rtx, int));
383 static void check_eliminable_occurrences PARAMS ((rtx));
384 static void elimination_effects PARAMS ((rtx, enum machine_mode));
385 static int eliminate_regs_in_insn PARAMS ((rtx, int));
386 static void update_eliminable_offsets PARAMS ((void));
387 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
388 static void set_initial_elim_offsets PARAMS ((void));
389 static void verify_initial_elim_offsets PARAMS ((void));
390 static void set_initial_label_offsets PARAMS ((void));
391 static void set_offsets_for_label PARAMS ((rtx));
392 static void init_elim_table PARAMS ((void));
393 static void update_eliminables PARAMS ((HARD_REG_SET *));
394 static void spill_hard_reg PARAMS ((int, FILE *, int));
395 static int finish_spills PARAMS ((int, FILE *));
396 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
397 static void scan_paradoxical_subregs PARAMS ((rtx));
398 static void count_pseudo PARAMS ((int));
399 static void order_regs_for_reload PARAMS ((struct insn_chain *));
400 static void reload_as_needed PARAMS ((int));
401 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
402 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
403 static void mark_reload_reg_in_use PARAMS ((int, int, enum reload_type,
405 static void clear_reload_reg_in_use PARAMS ((int, int, enum reload_type,
407 static int reload_reg_free_p PARAMS ((int, int, enum reload_type));
408 static int reload_reg_free_for_value_p PARAMS ((int, int, enum reload_type,
409 rtx, rtx, int, int));
410 static int reload_reg_reaches_end_p PARAMS ((int, int, enum reload_type));
411 static int allocate_reload_reg PARAMS ((struct insn_chain *, int, int));
412 static void failed_reload PARAMS ((rtx, int));
413 static int set_reload_reg PARAMS ((int, int));
414 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
415 static void choose_reload_regs PARAMS ((struct insn_chain *));
416 static void merge_assigned_reloads PARAMS ((rtx));
417 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
418 struct reload *, rtx, int));
419 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
420 struct reload *, int));
421 static void do_input_reload PARAMS ((struct insn_chain *,
422 struct reload *, int));
423 static void do_output_reload PARAMS ((struct insn_chain *,
424 struct reload *, int));
425 static void emit_reload_insns PARAMS ((struct insn_chain *));
426 static void delete_output_reload PARAMS ((rtx, int, int));
427 static void delete_address_reloads PARAMS ((rtx, rtx));
428 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
429 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
430 static int constraint_accepts_reg_p PARAMS ((const char *, rtx));
431 static void reload_cse_regs_1 PARAMS ((rtx));
432 static void reload_cse_invalidate_regno PARAMS ((int, enum machine_mode, int));
433 static int reload_cse_mem_conflict_p PARAMS ((rtx, rtx));
434 static void reload_cse_invalidate_mem PARAMS ((rtx));
435 static void reload_cse_invalidate_rtx PARAMS ((rtx, rtx, void *));
436 static int reload_cse_regno_equal_p PARAMS ((int, rtx, enum machine_mode));
437 static int reload_cse_noop_set_p PARAMS ((rtx, rtx));
438 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
439 static int reload_cse_simplify_operands PARAMS ((rtx));
440 static void reload_cse_check_clobber PARAMS ((rtx, rtx, void *));
441 static void reload_cse_record_set PARAMS ((rtx, rtx));
442 static void reload_combine PARAMS ((void));
443 static void reload_combine_note_use PARAMS ((rtx *, rtx));
444 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
445 static void reload_cse_move2add PARAMS ((rtx));
446 static void move2add_note_store PARAMS ((rtx, rtx, void *));
448 static void add_auto_inc_notes PARAMS ((rtx, rtx));
450 static rtx gen_mode_int PARAMS ((enum machine_mode,
452 static void failed_reload PARAMS ((rtx, int));
453 static int set_reload_reg PARAMS ((int, int));
454 extern void dump_needs PARAMS ((struct insn_chain *, FILE *));
456 /* Initialize the reload pass once per compilation. */
463 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
464 Set spill_indirect_levels to the number of levels such addressing is
465 permitted, zero if it is not permitted at all. */
468 = gen_rtx_MEM (Pmode,
471 LAST_VIRTUAL_REGISTER + 1),
473 spill_indirect_levels = 0;
475 while (memory_address_p (QImode, tem))
477 spill_indirect_levels++;
478 tem = gen_rtx_MEM (Pmode, tem);
481 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
483 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
484 indirect_symref_ok = memory_address_p (QImode, tem);
486 /* See if reg+reg is a valid (and offsettable) address. */
488 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
490 tem = gen_rtx_PLUS (Pmode,
491 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
492 gen_rtx_REG (Pmode, i));
494 /* This way, we make sure that reg+reg is an offsettable address. */
495 tem = plus_constant (tem, 4);
497 if (memory_address_p (QImode, tem))
499 double_reg_address_ok = 1;
504 /* Initialize obstack for our rtl allocation. */
505 gcc_obstack_init (&reload_obstack);
506 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
508 INIT_REG_SET (&spilled_pseudos);
509 INIT_REG_SET (&pseudos_counted);
512 /* List of insn chains that are currently unused. */
513 static struct insn_chain *unused_insn_chains = 0;
515 /* Allocate an empty insn_chain structure. */
519 struct insn_chain *c;
521 if (unused_insn_chains == 0)
523 c = (struct insn_chain *)
524 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
525 INIT_REG_SET (&c->live_throughout);
526 INIT_REG_SET (&c->dead_or_set);
530 c = unused_insn_chains;
531 unused_insn_chains = c->next;
533 c->is_caller_save_insn = 0;
534 c->need_operand_change = 0;
540 /* Small utility function to set all regs in hard reg set TO which are
541 allocated to pseudos in regset FROM. */
543 compute_use_by_pseudos (to, from)
548 EXECUTE_IF_SET_IN_REG_SET
549 (from, FIRST_PSEUDO_REGISTER, regno,
551 int r = reg_renumber[regno];
555 /* reload_combine uses the information from
556 BASIC_BLOCK->global_live_at_start, which might still
557 contain registers that have not actually been allocated
558 since they have an equivalence. */
559 if (! reload_completed)
564 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
566 SET_HARD_REG_BIT (*to, r + nregs);
571 /* Global variables used by reload and its subroutines. */
573 /* Set during calculate_needs if an insn needs register elimination. */
574 static int something_needs_elimination;
575 /* Set during calculate_needs if an insn needs an operand changed. */
576 int something_needs_operands_changed;
578 /* Nonzero means we couldn't get enough spill regs. */
581 /* Main entry point for the reload pass.
583 FIRST is the first insn of the function being compiled.
585 GLOBAL nonzero means we were called from global_alloc
586 and should attempt to reallocate any pseudoregs that we
587 displace from hard regs we will use for reloads.
588 If GLOBAL is zero, we do not have enough information to do that,
589 so any pseudo reg that is spilled must go to the stack.
591 DUMPFILE is the global-reg debugging dump file stream, or 0.
592 If it is nonzero, messages are written to it to describe
593 which registers are seized as reload regs, which pseudo regs
594 are spilled from them, and where the pseudo regs are reallocated to.
596 Return value is nonzero if reload failed
597 and we must not do any more for this function. */
600 reload (first, global, dumpfile)
607 register struct elim_table *ep;
609 /* The two pointers used to track the true location of the memory used
610 for label offsets. */
611 char *real_known_ptr = NULL_PTR;
612 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
614 /* Make sure even insns with volatile mem refs are recognizable. */
619 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
621 /* Make sure that the last insn in the chain
622 is not something that needs reloading. */
623 emit_note (NULL_PTR, NOTE_INSN_DELETED);
625 /* Enable find_equiv_reg to distinguish insns made by reload. */
626 reload_first_uid = get_max_uid ();
628 #ifdef SECONDARY_MEMORY_NEEDED
629 /* Initialize the secondary memory table. */
630 clear_secondary_mem ();
633 /* We don't have a stack slot for any spill reg yet. */
634 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
635 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
637 /* Initialize the save area information for caller-save, in case some
641 /* Compute which hard registers are now in use
642 as homes for pseudo registers.
643 This is done here rather than (eg) in global_alloc
644 because this point is reached even if not optimizing. */
645 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
648 /* A function that receives a nonlocal goto must save all call-saved
650 if (current_function_has_nonlocal_label)
651 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
653 if (! call_used_regs[i] && ! fixed_regs[i])
654 regs_ever_live[i] = 1;
657 /* Find all the pseudo registers that didn't get hard regs
658 but do have known equivalent constants or memory slots.
659 These include parameters (known equivalent to parameter slots)
660 and cse'd or loop-moved constant memory addresses.
662 Record constant equivalents in reg_equiv_constant
663 so they will be substituted by find_reloads.
664 Record memory equivalents in reg_mem_equiv so they can
665 be substituted eventually by altering the REG-rtx's. */
667 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
668 reg_equiv_memory_loc = (rtx *) xcalloc (max_regno, sizeof (rtx));
669 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
670 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
671 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
672 reg_max_ref_width = (int *) xcalloc (max_regno, sizeof (int));
673 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
674 bcopy ((PTR) reg_renumber, (PTR) reg_old_renumber, max_regno * sizeof (short));
675 pseudo_forbidden_regs
676 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
678 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
680 CLEAR_HARD_REG_SET (bad_spill_regs_global);
682 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
683 Also find all paradoxical subregs and find largest such for each pseudo.
684 On machines with small register classes, record hard registers that
685 are used for user variables. These can never be used for spills.
686 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
687 caller-saved registers must be marked live. */
689 num_eliminable_invariants = 0;
690 for (insn = first; insn; insn = NEXT_INSN (insn))
692 rtx set = single_set (insn);
694 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
695 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
696 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
697 if (! call_used_regs[i])
698 regs_ever_live[i] = 1;
700 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
702 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
704 #ifdef LEGITIMATE_PIC_OPERAND_P
705 && (! function_invariant_p (XEXP (note, 0))
707 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
711 rtx x = XEXP (note, 0);
712 i = REGNO (SET_DEST (set));
713 if (i > LAST_VIRTUAL_REGISTER)
715 if (GET_CODE (x) == MEM)
717 /* If the operand is a PLUS, the MEM may be shared,
718 so make sure we have an unshared copy here. */
719 if (GET_CODE (XEXP (x, 0)) == PLUS)
722 reg_equiv_memory_loc[i] = x;
724 else if (function_invariant_p (x))
726 if (GET_CODE (x) == PLUS)
728 /* This is PLUS of frame pointer and a constant,
729 and might be shared. Unshare it. */
730 reg_equiv_constant[i] = copy_rtx (x);
731 num_eliminable_invariants++;
733 else if (x == frame_pointer_rtx
734 || x == arg_pointer_rtx)
736 reg_equiv_constant[i] = x;
737 num_eliminable_invariants++;
739 else if (LEGITIMATE_CONSTANT_P (x))
740 reg_equiv_constant[i] = x;
742 reg_equiv_memory_loc[i]
743 = force_const_mem (GET_MODE (SET_DEST (set)), x);
748 /* If this register is being made equivalent to a MEM
749 and the MEM is not SET_SRC, the equivalencing insn
750 is one with the MEM as a SET_DEST and it occurs later.
751 So don't mark this insn now. */
752 if (GET_CODE (x) != MEM
753 || rtx_equal_p (SET_SRC (set), x))
755 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
760 /* If this insn is setting a MEM from a register equivalent to it,
761 this is the equivalencing insn. */
762 else if (set && GET_CODE (SET_DEST (set)) == MEM
763 && GET_CODE (SET_SRC (set)) == REG
764 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
765 && rtx_equal_p (SET_DEST (set),
766 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
767 reg_equiv_init[REGNO (SET_SRC (set))]
768 = gen_rtx_INSN_LIST (VOIDmode, insn,
769 reg_equiv_init[REGNO (SET_SRC (set))]);
771 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
772 scan_paradoxical_subregs (PATTERN (insn));
777 num_labels = max_label_num () - get_first_label_num ();
779 /* Allocate the tables used to store offset information at labels. */
780 /* We used to use alloca here, but the size of what it would try to
781 allocate would occasionally cause it to exceed the stack limit and
782 cause a core dump. */
783 real_known_ptr = xmalloc (num_labels);
785 = (int (*)[NUM_ELIMINABLE_REGS])
786 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
788 offsets_known_at = real_known_ptr - get_first_label_num ();
790 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
792 /* Alter each pseudo-reg rtx to contain its hard reg number.
793 Assign stack slots to the pseudos that lack hard regs or equivalents.
794 Do not touch virtual registers. */
796 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
799 /* If we have some registers we think can be eliminated, scan all insns to
800 see if there is an insn that sets one of these registers to something
801 other than itself plus a constant. If so, the register cannot be
802 eliminated. Doing this scan here eliminates an extra pass through the
803 main reload loop in the most common case where register elimination
805 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
806 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
807 || GET_CODE (insn) == CALL_INSN)
808 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
810 maybe_fix_stack_asms ();
812 insns_need_reload = 0;
813 something_needs_elimination = 0;
815 /* Initialize to -1, which means take the first spill register. */
818 /* Spill any hard regs that we know we can't eliminate. */
819 CLEAR_HARD_REG_SET (used_spill_regs);
820 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
821 if (! ep->can_eliminate)
822 spill_hard_reg (ep->from, dumpfile, 1);
824 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
825 if (frame_pointer_needed)
826 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, dumpfile, 1);
828 finish_spills (global, dumpfile);
830 /* From now on, we may need to generate moves differently. We may also
831 allow modifications of insns which cause them to not be recognized.
832 Any such modifications will be cleaned up during reload itself. */
833 reload_in_progress = 1;
835 /* This loop scans the entire function each go-round
836 and repeats until one repetition spills no additional hard regs. */
839 int something_changed;
842 HOST_WIDE_INT starting_frame_size;
844 /* Round size of stack frame to stack_alignment_needed. This must be done
845 here because the stack size may be a part of the offset computation
846 for register elimination, and there might have been new stack slots
847 created in the last iteration of this loop. */
848 if (cfun->stack_alignment_needed)
849 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
851 starting_frame_size = get_frame_size ();
853 set_initial_elim_offsets ();
854 set_initial_label_offsets ();
856 /* For each pseudo register that has an equivalent location defined,
857 try to eliminate any eliminable registers (such as the frame pointer)
858 assuming initial offsets for the replacement register, which
861 If the resulting location is directly addressable, substitute
862 the MEM we just got directly for the old REG.
864 If it is not addressable but is a constant or the sum of a hard reg
865 and constant, it is probably not addressable because the constant is
866 out of range, in that case record the address; we will generate
867 hairy code to compute the address in a register each time it is
868 needed. Similarly if it is a hard register, but one that is not
869 valid as an address register.
871 If the location is not addressable, but does not have one of the
872 above forms, assign a stack slot. We have to do this to avoid the
873 potential of producing lots of reloads if, e.g., a location involves
874 a pseudo that didn't get a hard register and has an equivalent memory
875 location that also involves a pseudo that didn't get a hard register.
877 Perhaps at some point we will improve reload_when_needed handling
878 so this problem goes away. But that's very hairy. */
880 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
881 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
883 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
885 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
887 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
888 else if (CONSTANT_P (XEXP (x, 0))
889 || (GET_CODE (XEXP (x, 0)) == REG
890 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
891 || (GET_CODE (XEXP (x, 0)) == PLUS
892 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
893 && (REGNO (XEXP (XEXP (x, 0), 0))
894 < FIRST_PSEUDO_REGISTER)
895 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
896 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
899 /* Make a new stack slot. Then indicate that something
900 changed so we go back and recompute offsets for
901 eliminable registers because the allocation of memory
902 below might change some offset. reg_equiv_{mem,address}
903 will be set up for this pseudo on the next pass around
905 reg_equiv_memory_loc[i] = 0;
906 reg_equiv_init[i] = 0;
911 if (caller_save_needed)
914 /* If we allocated another stack slot, redo elimination bookkeeping. */
915 if (starting_frame_size != get_frame_size ())
918 if (caller_save_needed)
920 save_call_clobbered_regs ();
921 /* That might have allocated new insn_chain structures. */
922 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
925 calculate_needs_all_insns (global);
927 CLEAR_REG_SET (&spilled_pseudos);
930 something_changed = 0;
932 /* If we allocated any new memory locations, make another pass
933 since it might have changed elimination offsets. */
934 if (starting_frame_size != get_frame_size ())
935 something_changed = 1;
938 HARD_REG_SET to_spill;
939 CLEAR_HARD_REG_SET (to_spill);
940 update_eliminables (&to_spill);
941 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
942 if (TEST_HARD_REG_BIT (to_spill, i))
944 spill_hard_reg (i, dumpfile, 1);
947 /* Regardless of the state of spills, if we previously had
948 a register that we thought we could eliminate, but no can
949 not eliminate, we must run another pass.
951 Consider pseudos which have an entry in reg_equiv_* which
952 reference an eliminable register. We must make another pass
953 to update reg_equiv_* so that we do not substitute in the
954 old value from when we thought the elimination could be
956 something_changed = 1;
960 select_reload_regs (dumpfile);
964 if (insns_need_reload != 0 || did_spill)
965 something_changed |= finish_spills (global, dumpfile);
967 if (! something_changed)
970 if (caller_save_needed)
971 delete_caller_save_insns ();
973 obstack_free (&reload_obstack, reload_firstobj);
976 /* If global-alloc was run, notify it of any register eliminations we have
979 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
980 if (ep->can_eliminate)
981 mark_elimination (ep->from, ep->to);
983 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
984 If that insn didn't set the register (i.e., it copied the register to
985 memory), just delete that insn instead of the equivalencing insn plus
986 anything now dead. If we call delete_dead_insn on that insn, we may
987 delete the insn that actually sets the register if the register dies
988 there and that is incorrect. */
990 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
992 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
995 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
997 rtx equiv_insn = XEXP (list, 0);
998 if (GET_CODE (equiv_insn) == NOTE)
1000 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1001 delete_dead_insn (equiv_insn);
1004 PUT_CODE (equiv_insn, NOTE);
1005 NOTE_SOURCE_FILE (equiv_insn) = 0;
1006 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1012 /* Use the reload registers where necessary
1013 by generating move instructions to move the must-be-register
1014 values into or out of the reload registers. */
1016 if (insns_need_reload != 0 || something_needs_elimination
1017 || something_needs_operands_changed)
1019 int old_frame_size = get_frame_size ();
1021 reload_as_needed (global);
1023 if (old_frame_size != get_frame_size ())
1027 verify_initial_elim_offsets ();
1030 /* If we were able to eliminate the frame pointer, show that it is no
1031 longer live at the start of any basic block. If it ls live by
1032 virtue of being in a pseudo, that pseudo will be marked live
1033 and hence the frame pointer will be known to be live via that
1036 if (! frame_pointer_needed)
1037 for (i = 0; i < n_basic_blocks; i++)
1038 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1039 HARD_FRAME_POINTER_REGNUM);
1041 /* Come here (with failure set nonzero) if we can't get enough spill regs
1042 and we decide not to abort about it. */
1045 CLEAR_REG_SET (&spilled_pseudos);
1046 reload_in_progress = 0;
1048 /* Now eliminate all pseudo regs by modifying them into
1049 their equivalent memory references.
1050 The REG-rtx's for the pseudos are modified in place,
1051 so all insns that used to refer to them now refer to memory.
1053 For a reg that has a reg_equiv_address, all those insns
1054 were changed by reloading so that no insns refer to it any longer;
1055 but the DECL_RTL of a variable decl may refer to it,
1056 and if so this causes the debugging info to mention the variable. */
1058 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1063 int is_readonly = 0;
1065 if (reg_equiv_memory_loc[i])
1067 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1068 is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]);
1069 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1072 if (reg_equiv_mem[i])
1073 addr = XEXP (reg_equiv_mem[i], 0);
1075 if (reg_equiv_address[i])
1076 addr = reg_equiv_address[i];
1080 if (reg_renumber[i] < 0)
1082 rtx reg = regno_reg_rtx[i];
1083 PUT_CODE (reg, MEM);
1084 XEXP (reg, 0) = addr;
1085 REG_USERVAR_P (reg) = 0;
1086 RTX_UNCHANGING_P (reg) = is_readonly;
1087 MEM_IN_STRUCT_P (reg) = in_struct;
1088 MEM_SCALAR_P (reg) = is_scalar;
1089 /* We have no alias information about this newly created
1091 MEM_ALIAS_SET (reg) = 0;
1093 else if (reg_equiv_mem[i])
1094 XEXP (reg_equiv_mem[i], 0) = addr;
1098 /* We must set reload_completed now since the cleanup_subreg_operands call
1099 below will re-recognize each insn and reload may have generated insns
1100 which are only valid during and after reload. */
1101 reload_completed = 1;
1103 /* Make a pass over all the insns and delete all USEs which we inserted
1104 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1105 notes. Delete all CLOBBER insns that don't refer to the return value
1106 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1107 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1108 and regenerate REG_INC notes that may have been moved around. */
1110 for (insn = first; insn; insn = NEXT_INSN (insn))
1111 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1115 if ((GET_CODE (PATTERN (insn)) == USE
1116 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1117 || (GET_CODE (PATTERN (insn)) == CLOBBER
1118 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1119 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1121 PUT_CODE (insn, NOTE);
1122 NOTE_SOURCE_FILE (insn) = 0;
1123 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1127 pnote = ®_NOTES (insn);
1130 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1131 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1132 || REG_NOTE_KIND (*pnote) == REG_INC
1133 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1134 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1135 *pnote = XEXP (*pnote, 1);
1137 pnote = &XEXP (*pnote, 1);
1141 add_auto_inc_notes (insn, PATTERN (insn));
1144 /* And simplify (subreg (reg)) if it appears as an operand. */
1145 cleanup_subreg_operands (insn);
1148 /* If we are doing stack checking, give a warning if this function's
1149 frame size is larger than we expect. */
1150 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1152 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1153 static int verbose_warned = 0;
1155 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1156 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1157 size += UNITS_PER_WORD;
1159 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1161 warning ("frame size too large for reliable stack checking");
1162 if (! verbose_warned)
1164 warning ("try reducing the number of local variables");
1170 /* Indicate that we no longer have known memory locations or constants. */
1171 if (reg_equiv_constant)
1172 free (reg_equiv_constant);
1173 reg_equiv_constant = 0;
1174 if (reg_equiv_memory_loc)
1175 free (reg_equiv_memory_loc);
1176 reg_equiv_memory_loc = 0;
1179 free (real_known_ptr);
1183 free (reg_equiv_mem);
1184 free (reg_equiv_init);
1185 free (reg_equiv_address);
1186 free (reg_max_ref_width);
1187 free (reg_old_renumber);
1188 free (pseudo_previous_regs);
1189 free (pseudo_forbidden_regs);
1191 CLEAR_HARD_REG_SET (used_spill_regs);
1192 for (i = 0; i < n_spills; i++)
1193 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1195 /* Free all the insn_chain structures at once. */
1196 obstack_free (&reload_obstack, reload_startobj);
1197 unused_insn_chains = 0;
1202 /* Yet another special case. Unfortunately, reg-stack forces people to
1203 write incorrect clobbers in asm statements. These clobbers must not
1204 cause the register to appear in bad_spill_regs, otherwise we'll call
1205 fatal_insn later. We clear the corresponding regnos in the live
1206 register sets to avoid this.
1207 The whole thing is rather sick, I'm afraid. */
1209 maybe_fix_stack_asms ()
1212 const char *constraints[MAX_RECOG_OPERANDS];
1213 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1214 struct insn_chain *chain;
1216 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1219 HARD_REG_SET clobbered, allowed;
1222 if (GET_RTX_CLASS (GET_CODE (chain->insn)) != 'i'
1223 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1225 pat = PATTERN (chain->insn);
1226 if (GET_CODE (pat) != PARALLEL)
1229 CLEAR_HARD_REG_SET (clobbered);
1230 CLEAR_HARD_REG_SET (allowed);
1232 /* First, make a mask of all stack regs that are clobbered. */
1233 for (i = 0; i < XVECLEN (pat, 0); i++)
1235 rtx t = XVECEXP (pat, 0, i);
1236 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1237 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1240 /* Get the operand values and constraints out of the insn. */
1241 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1242 constraints, operand_mode);
1244 /* For every operand, see what registers are allowed. */
1245 for (i = 0; i < noperands; i++)
1247 const char *p = constraints[i];
1248 /* For every alternative, we compute the class of registers allowed
1249 for reloading in CLS, and merge its contents into the reg set
1251 int cls = (int) NO_REGS;
1257 if (c == '\0' || c == ',' || c == '#')
1259 /* End of one alternative - mark the regs in the current
1260 class, and reset the class. */
1261 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1266 } while (c != '\0' && c != ',');
1274 case '=': case '+': case '*': case '%': case '?': case '!':
1275 case '0': case '1': case '2': case '3': case '4': case 'm':
1276 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1277 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1278 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1280 #ifdef EXTRA_CONSTRAINT
1281 case 'Q': case 'R': case 'S': case 'T': case 'U':
1286 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1291 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1295 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1300 /* Those of the registers which are clobbered, but allowed by the
1301 constraints, must be usable as reload registers. So clear them
1302 out of the life information. */
1303 AND_HARD_REG_SET (allowed, clobbered);
1304 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1305 if (TEST_HARD_REG_BIT (allowed, i))
1307 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1308 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1315 /* Copy the global variables n_reloads and rld into the corresponding elts
1318 copy_reloads (chain)
1319 struct insn_chain *chain;
1321 chain->n_reloads = n_reloads;
1323 = (struct reload *) obstack_alloc (&reload_obstack,
1324 n_reloads * sizeof (struct reload));
1325 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1326 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1329 /* Walk the chain of insns, and determine for each whether it needs reloads
1330 and/or eliminations. Build the corresponding insns_need_reload list, and
1331 set something_needs_elimination as appropriate. */
1333 calculate_needs_all_insns (global)
1336 struct insn_chain **pprev_reload = &insns_need_reload;
1337 struct insn_chain *chain;
1339 something_needs_elimination = 0;
1341 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1342 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1344 rtx insn = chain->insn;
1346 /* Clear out the shortcuts. */
1347 chain->n_reloads = 0;
1348 chain->need_elim = 0;
1349 chain->need_reload = 0;
1350 chain->need_operand_change = 0;
1352 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1353 include REG_LABEL), we need to see what effects this has on the
1354 known offsets at labels. */
1356 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1357 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1358 && REG_NOTES (insn) != 0))
1359 set_label_offsets (insn, insn, 0);
1361 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1363 rtx old_body = PATTERN (insn);
1364 int old_code = INSN_CODE (insn);
1365 rtx old_notes = REG_NOTES (insn);
1366 int did_elimination = 0;
1367 int operands_changed = 0;
1368 rtx set = single_set (insn);
1370 /* Skip insns that only set an equivalence. */
1371 if (set && GET_CODE (SET_DEST (set)) == REG
1372 && reg_renumber[REGNO (SET_DEST (set))] < 0
1373 && reg_equiv_constant[REGNO (SET_DEST (set))])
1376 /* If needed, eliminate any eliminable registers. */
1377 if (num_eliminable || num_eliminable_invariants)
1378 did_elimination = eliminate_regs_in_insn (insn, 0);
1380 /* Analyze the instruction. */
1381 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1382 global, spill_reg_order);
1384 /* If a no-op set needs more than one reload, this is likely
1385 to be something that needs input address reloads. We
1386 can't get rid of this cleanly later, and it is of no use
1387 anyway, so discard it now.
1388 We only do this when expensive_optimizations is enabled,
1389 since this complements reload inheritance / output
1390 reload deletion, and it can make debugging harder. */
1391 if (flag_expensive_optimizations && n_reloads > 1)
1393 rtx set = single_set (insn);
1395 && SET_SRC (set) == SET_DEST (set)
1396 && GET_CODE (SET_SRC (set)) == REG
1397 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1399 PUT_CODE (insn, NOTE);
1400 NOTE_SOURCE_FILE (insn) = 0;
1401 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1406 update_eliminable_offsets ();
1408 /* Remember for later shortcuts which insns had any reloads or
1409 register eliminations. */
1410 chain->need_elim = did_elimination;
1411 chain->need_reload = n_reloads > 0;
1412 chain->need_operand_change = operands_changed;
1414 /* Discard any register replacements done. */
1415 if (did_elimination)
1417 obstack_free (&reload_obstack, reload_insn_firstobj);
1418 PATTERN (insn) = old_body;
1419 INSN_CODE (insn) = old_code;
1420 REG_NOTES (insn) = old_notes;
1421 something_needs_elimination = 1;
1424 something_needs_operands_changed |= operands_changed;
1428 copy_reloads (chain);
1429 *pprev_reload = chain;
1430 pprev_reload = &chain->next_need_reload;
1437 /* Comparison function for qsort to decide which of two reloads
1438 should be handled first. *P1 and *P2 are the reload numbers. */
1441 reload_reg_class_lower (r1p, r2p)
1445 register int r1 = *(const short *)r1p, r2 = *(const short *)r2p;
1448 /* Consider required reloads before optional ones. */
1449 t = rld[r1].optional - rld[r2].optional;
1453 /* Count all solitary classes before non-solitary ones. */
1454 t = ((reg_class_size[(int) rld[r2].class] == 1)
1455 - (reg_class_size[(int) rld[r1].class] == 1));
1459 /* Aside from solitaires, consider all multi-reg groups first. */
1460 t = rld[r2].nregs - rld[r1].nregs;
1464 /* Consider reloads in order of increasing reg-class number. */
1465 t = (int) rld[r1].class - (int) rld[r2].class;
1469 /* If reloads are equally urgent, sort by reload number,
1470 so that the results of qsort leave nothing to chance. */
1474 /* The cost of spilling each hard reg. */
1475 static int spill_cost[FIRST_PSEUDO_REGISTER];
1477 /* When spilling multiple hard registers, we use SPILL_COST for the first
1478 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1479 only the first hard reg for a multi-reg pseudo. */
1480 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1482 /* Update the spill cost arrays, considering that pseudo REG is live. */
1487 int n_refs = REG_N_REFS (reg);
1488 int r = reg_renumber[reg];
1491 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1492 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1495 SET_REGNO_REG_SET (&pseudos_counted, reg);
1500 spill_add_cost[r] += n_refs;
1502 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1504 spill_cost[r + nregs] += n_refs;
1507 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1508 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1510 order_regs_for_reload (chain)
1511 struct insn_chain *chain;
1515 COPY_HARD_REG_SET (bad_spill_regs, bad_spill_regs_global);
1517 memset (spill_cost, 0, sizeof spill_cost);
1518 memset (spill_add_cost, 0, sizeof spill_add_cost);
1520 /* Count number of uses of each hard reg by pseudo regs allocated to it
1521 and then order them by decreasing use. */
1523 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1525 /* Test the various reasons why we can't use a register for
1526 spilling in this insn. */
1528 || REGNO_REG_SET_P (&chain->live_throughout, i)
1529 || REGNO_REG_SET_P (&chain->dead_or_set, i))
1530 SET_HARD_REG_BIT (bad_spill_regs, i);
1532 /* Now find out which pseudos are allocated to it, and update
1534 CLEAR_REG_SET (&pseudos_counted);
1536 EXECUTE_IF_SET_IN_REG_SET
1537 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1541 EXECUTE_IF_SET_IN_REG_SET
1542 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1546 CLEAR_REG_SET (&pseudos_counted);
1549 /* Vector of reload-numbers showing the order in which the reloads should
1551 static short reload_order[MAX_RELOADS];
1553 /* This is used to keep track of the spill regs used in one insn. */
1554 static HARD_REG_SET used_spill_regs_local;
1556 /* We decided to spill hard register SPILLED, which has a size of
1557 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1558 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1559 update SPILL_COST/SPILL_ADD_COST. */
1561 count_spilled_pseudo (spilled, spilled_nregs, reg)
1562 int spilled, spilled_nregs, reg;
1564 int r = reg_renumber[reg];
1565 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1567 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1568 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1571 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1573 spill_add_cost[r] -= REG_N_REFS (reg);
1575 spill_cost[r + nregs] -= REG_N_REFS (reg);
1578 /* Find reload register to use for reload number ORDER. */
1581 find_reg (chain, order, dumpfile)
1582 struct insn_chain *chain;
1586 int rnum = reload_order[order];
1587 struct reload *rl = rld + rnum;
1588 int best_cost = INT_MAX;
1591 HARD_REG_SET not_usable;
1592 HARD_REG_SET used_by_other_reload;
1594 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1595 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1596 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1598 CLEAR_HARD_REG_SET (used_by_other_reload);
1599 for (i = 0; i < order; i++)
1601 int other = reload_order[i];
1602 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1603 for (j = 0; j < rld[other].nregs; j++)
1604 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1607 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1610 if (! TEST_HARD_REG_BIT (not_usable, regno)
1611 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1612 && HARD_REGNO_MODE_OK (regno, rl->mode))
1614 int this_cost = spill_cost[regno];
1616 int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1618 for (j = 1; j < this_nregs; j++)
1620 this_cost += spill_add_cost[regno + j];
1621 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1622 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1627 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1629 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1631 if (this_cost < best_cost
1632 /* Among registers with equal cost, prefer caller-saved ones, or
1633 use REG_ALLOC_ORDER if it is defined. */
1634 || (this_cost == best_cost
1635 #ifdef REG_ALLOC_ORDER
1636 && (inv_reg_alloc_order[regno]
1637 < inv_reg_alloc_order[best_reg])
1639 && call_used_regs[regno]
1640 && ! call_used_regs[best_reg]
1645 best_cost = this_cost;
1652 fprintf (dumpfile, "Using reg %d for reload %d\n", best_reg, rnum);
1653 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1654 rl->regno = best_reg;
1656 EXECUTE_IF_SET_IN_REG_SET
1657 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1659 count_spilled_pseudo (best_reg, rl->nregs, j);
1661 EXECUTE_IF_SET_IN_REG_SET
1662 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1664 count_spilled_pseudo (best_reg, rl->nregs, j);
1667 for (i = 0; i < rl->nregs; i++)
1669 if (spill_cost[best_reg + i] != 0
1670 || spill_add_cost[best_reg + i] != 0)
1672 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1677 /* Find more reload regs to satisfy the remaining need of an insn, which
1679 Do it by ascending class number, since otherwise a reg
1680 might be spilled for a big class and might fail to count
1681 for a smaller class even though it belongs to that class. */
1684 find_reload_regs (chain, dumpfile)
1685 struct insn_chain *chain;
1690 /* In order to be certain of getting the registers we need,
1691 we must sort the reloads into order of increasing register class.
1692 Then our grabbing of reload registers will parallel the process
1693 that provided the reload registers. */
1694 for (i = 0; i < chain->n_reloads; i++)
1696 /* Show whether this reload already has a hard reg. */
1697 if (chain->rld[i].reg_rtx)
1699 int regno = REGNO (chain->rld[i].reg_rtx);
1700 chain->rld[i].regno = regno;
1701 chain->rld[i].nregs = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1704 chain->rld[i].regno = -1;
1705 reload_order[i] = i;
1708 n_reloads = chain->n_reloads;
1709 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1711 CLEAR_HARD_REG_SET (used_spill_regs_local);
1714 fprintf (dumpfile, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1716 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1718 /* Compute the order of preference for hard registers to spill. */
1720 order_regs_for_reload (chain);
1722 for (i = 0; i < n_reloads; i++)
1724 int r = reload_order[i];
1726 /* Ignore reloads that got marked inoperative. */
1727 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1728 && ! rld[r].optional
1729 && rld[r].regno == -1)
1730 if (! find_reg (chain, i, dumpfile))
1732 spill_failure (chain->insn, rld[r].class);
1738 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1739 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1741 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1745 select_reload_regs (dumpfile)
1748 struct insn_chain *chain;
1750 /* Try to satisfy the needs for each insn. */
1751 for (chain = insns_need_reload; chain != 0;
1752 chain = chain->next_need_reload)
1753 find_reload_regs (chain, dumpfile);
1756 /* Delete all insns that were inserted by emit_caller_save_insns during
1759 delete_caller_save_insns ()
1761 struct insn_chain *c = reload_insn_chain;
1765 while (c != 0 && c->is_caller_save_insn)
1767 struct insn_chain *next = c->next;
1770 if (insn == BLOCK_HEAD (c->block))
1771 BLOCK_HEAD (c->block) = NEXT_INSN (insn);
1772 if (insn == BLOCK_END (c->block))
1773 BLOCK_END (c->block) = PREV_INSN (insn);
1774 if (c == reload_insn_chain)
1775 reload_insn_chain = next;
1777 if (NEXT_INSN (insn) != 0)
1778 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
1779 if (PREV_INSN (insn) != 0)
1780 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
1783 next->prev = c->prev;
1785 c->prev->next = next;
1786 c->next = unused_insn_chains;
1787 unused_insn_chains = c;
1795 /* Handle the failure to find a register to spill.
1796 INSN should be one of the insns which needed this particular spill reg. */
1799 spill_failure (insn, class)
1801 enum reg_class class;
1803 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1804 if (asm_noperands (PATTERN (insn)) >= 0)
1805 error_for_asm (insn, "Can't find a register in class `%s' while reloading `asm'.",
1806 reg_class_names[class]);
1809 error ("Unable to find a register to spill in class `%s'.",
1810 reg_class_names[class]);
1811 fatal_insn ("This is the insn:", insn);
1815 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1816 data that is dead in INSN. */
1819 delete_dead_insn (insn)
1822 rtx prev = prev_real_insn (insn);
1825 /* If the previous insn sets a register that dies in our insn, delete it
1827 if (prev && GET_CODE (PATTERN (prev)) == SET
1828 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1829 && reg_mentioned_p (prev_dest, PATTERN (insn))
1830 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1831 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1832 delete_dead_insn (prev);
1834 PUT_CODE (insn, NOTE);
1835 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1836 NOTE_SOURCE_FILE (insn) = 0;
1839 /* Modify the home of pseudo-reg I.
1840 The new home is present in reg_renumber[I].
1842 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1843 or it may be -1, meaning there is none or it is not relevant.
1844 This is used so that all pseudos spilled from a given hard reg
1845 can share one stack slot. */
1848 alter_reg (i, from_reg)
1852 /* When outputting an inline function, this can happen
1853 for a reg that isn't actually used. */
1854 if (regno_reg_rtx[i] == 0)
1857 /* If the reg got changed to a MEM at rtl-generation time,
1859 if (GET_CODE (regno_reg_rtx[i]) != REG)
1862 /* Modify the reg-rtx to contain the new hard reg
1863 number or else to contain its pseudo reg number. */
1864 REGNO (regno_reg_rtx[i])
1865 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1867 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1868 allocate a stack slot for it. */
1870 if (reg_renumber[i] < 0
1871 && REG_N_REFS (i) > 0
1872 && reg_equiv_constant[i] == 0
1873 && reg_equiv_memory_loc[i] == 0)
1876 int inherent_size = PSEUDO_REGNO_BYTES (i);
1877 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1880 /* Each pseudo reg has an inherent size which comes from its own mode,
1881 and a total size which provides room for paradoxical subregs
1882 which refer to the pseudo reg in wider modes.
1884 We can use a slot already allocated if it provides both
1885 enough inherent space and enough total space.
1886 Otherwise, we allocate a new slot, making sure that it has no less
1887 inherent space, and no less total space, then the previous slot. */
1890 /* No known place to spill from => no slot to reuse. */
1891 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1892 inherent_size == total_size ? 0 : -1);
1893 if (BYTES_BIG_ENDIAN)
1894 /* Cancel the big-endian correction done in assign_stack_local.
1895 Get the address of the beginning of the slot.
1896 This is so we can do a big-endian correction unconditionally
1898 adjust = inherent_size - total_size;
1900 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1902 /* Reuse a stack slot if possible. */
1903 else if (spill_stack_slot[from_reg] != 0
1904 && spill_stack_slot_width[from_reg] >= total_size
1905 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1907 x = spill_stack_slot[from_reg];
1908 /* Allocate a bigger slot. */
1911 /* Compute maximum size needed, both for inherent size
1912 and for total size. */
1913 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1915 if (spill_stack_slot[from_reg])
1917 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1919 mode = GET_MODE (spill_stack_slot[from_reg]);
1920 if (spill_stack_slot_width[from_reg] > total_size)
1921 total_size = spill_stack_slot_width[from_reg];
1923 /* Make a slot with that size. */
1924 x = assign_stack_local (mode, total_size,
1925 inherent_size == total_size ? 0 : -1);
1927 if (BYTES_BIG_ENDIAN)
1929 /* Cancel the big-endian correction done in assign_stack_local.
1930 Get the address of the beginning of the slot.
1931 This is so we can do a big-endian correction unconditionally
1933 adjust = GET_MODE_SIZE (mode) - total_size;
1935 stack_slot = gen_rtx_MEM (mode_for_size (total_size
1938 plus_constant (XEXP (x, 0), adjust));
1940 spill_stack_slot[from_reg] = stack_slot;
1941 spill_stack_slot_width[from_reg] = total_size;
1944 /* On a big endian machine, the "address" of the slot
1945 is the address of the low part that fits its inherent mode. */
1946 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
1947 adjust += (total_size - inherent_size);
1949 /* If we have any adjustment to make, or if the stack slot is the
1950 wrong mode, make a new stack slot. */
1951 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
1953 x = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
1954 plus_constant (XEXP (x, 0), adjust));
1956 /* If this was shared among registers, must ensure we never
1957 set it readonly since that can cause scheduling
1958 problems. Note we would only have in this adjustment
1959 case in any event, since the code above doesn't set it. */
1962 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1965 /* Save the stack slot for later. */
1966 reg_equiv_memory_loc[i] = x;
1970 /* Mark the slots in regs_ever_live for the hard regs
1971 used by pseudo-reg number REGNO. */
1974 mark_home_live (regno)
1977 register int i, lim;
1978 i = reg_renumber[regno];
1981 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
1983 regs_ever_live[i++] = 1;
1986 /* This function handles the tracking of elimination offsets around branches.
1988 X is a piece of RTL being scanned.
1990 INSN is the insn that it came from, if any.
1992 INITIAL_P is non-zero if we are to set the offset to be the initial
1993 offset and zero if we are setting the offset of the label to be the
1997 set_label_offsets (x, insn, initial_p)
2002 enum rtx_code code = GET_CODE (x);
2005 struct elim_table *p;
2010 if (LABEL_REF_NONLOCAL_P (x))
2015 /* ... fall through ... */
2018 /* If we know nothing about this label, set the desired offsets. Note
2019 that this sets the offset at a label to be the offset before a label
2020 if we don't know anything about the label. This is not correct for
2021 the label after a BARRIER, but is the best guess we can make. If
2022 we guessed wrong, we will suppress an elimination that might have
2023 been possible had we been able to guess correctly. */
2025 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2027 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2028 offsets_at[CODE_LABEL_NUMBER (x)][i]
2029 = (initial_p ? reg_eliminate[i].initial_offset
2030 : reg_eliminate[i].offset);
2031 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2034 /* Otherwise, if this is the definition of a label and it is
2035 preceded by a BARRIER, set our offsets to the known offset of
2039 && (tem = prev_nonnote_insn (insn)) != 0
2040 && GET_CODE (tem) == BARRIER)
2041 set_offsets_for_label (insn);
2043 /* If neither of the above cases is true, compare each offset
2044 with those previously recorded and suppress any eliminations
2045 where the offsets disagree. */
2047 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2048 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2049 != (initial_p ? reg_eliminate[i].initial_offset
2050 : reg_eliminate[i].offset))
2051 reg_eliminate[i].can_eliminate = 0;
2056 set_label_offsets (PATTERN (insn), insn, initial_p);
2058 /* ... fall through ... */
2062 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2063 and hence must have all eliminations at their initial offsets. */
2064 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2065 if (REG_NOTE_KIND (tem) == REG_LABEL)
2066 set_label_offsets (XEXP (tem, 0), insn, 1);
2071 /* Each of the labels in the address vector must be at their initial
2072 offsets. We want the first field for ADDR_VEC and the second
2073 field for ADDR_DIFF_VEC. */
2075 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2076 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2081 /* We only care about setting PC. If the source is not RETURN,
2082 IF_THEN_ELSE, or a label, disable any eliminations not at
2083 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2084 isn't one of those possibilities. For branches to a label,
2085 call ourselves recursively.
2087 Note that this can disable elimination unnecessarily when we have
2088 a non-local goto since it will look like a non-constant jump to
2089 someplace in the current function. This isn't a significant
2090 problem since such jumps will normally be when all elimination
2091 pairs are back to their initial offsets. */
2093 if (SET_DEST (x) != pc_rtx)
2096 switch (GET_CODE (SET_SRC (x)))
2103 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2107 tem = XEXP (SET_SRC (x), 1);
2108 if (GET_CODE (tem) == LABEL_REF)
2109 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2110 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2113 tem = XEXP (SET_SRC (x), 2);
2114 if (GET_CODE (tem) == LABEL_REF)
2115 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2116 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2124 /* If we reach here, all eliminations must be at their initial
2125 offset because we are doing a jump to a variable address. */
2126 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2127 if (p->offset != p->initial_offset)
2128 p->can_eliminate = 0;
2136 /* Scan X and replace any eliminable registers (such as fp) with a
2137 replacement (such as sp), plus an offset.
2139 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2140 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2141 MEM, we are allowed to replace a sum of a register and the constant zero
2142 with the register, which we cannot do outside a MEM. In addition, we need
2143 to record the fact that a register is referenced outside a MEM.
2145 If INSN is an insn, it is the insn containing X. If we replace a REG
2146 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2147 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2148 the REG is being modified.
2150 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2151 That's used when we eliminate in expressions stored in notes.
2152 This means, do not set ref_outside_mem even if the reference
2155 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2156 replacements done assuming all offsets are at their initial values. If
2157 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2158 encounter, return the actual location so that find_reloads will do
2159 the proper thing. */
2162 eliminate_regs (x, mem_mode, insn)
2164 enum machine_mode mem_mode;
2167 enum rtx_code code = GET_CODE (x);
2168 struct elim_table *ep;
2175 if (! current_function_decl)
2194 /* This is only for the benefit of the debugging backends, which call
2195 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2196 removed after CSE. */
2197 new = eliminate_regs (XEXP (x, 0), 0, insn);
2198 if (GET_CODE (new) == MEM)
2199 return XEXP (new, 0);
2205 /* First handle the case where we encounter a bare register that
2206 is eliminable. Replace it with a PLUS. */
2207 if (regno < FIRST_PSEUDO_REGISTER)
2209 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2211 if (ep->from_rtx == x && ep->can_eliminate)
2212 return plus_constant (ep->to_rtx, ep->previous_offset);
2215 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2216 && reg_equiv_constant[regno]
2217 && ! CONSTANT_P (reg_equiv_constant[regno]))
2218 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2222 /* You might think handling MINUS in a manner similar to PLUS is a
2223 good idea. It is not. It has been tried multiple times and every
2224 time the change has had to have been reverted.
2226 Other parts of reload know a PLUS is special (gen_reload for example)
2227 and require special code to handle code a reloaded PLUS operand.
2229 Also consider backends where the flags register is clobbered by a
2230 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2231 lea instruction comes to mind). If we try to reload a MINUS, we
2232 may kill the flags register that was holding a useful value.
2234 So, please before trying to handle MINUS, consider reload as a
2235 whole instead of this little section as well as the backend issues. */
2237 /* If this is the sum of an eliminable register and a constant, rework
2239 if (GET_CODE (XEXP (x, 0)) == REG
2240 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2241 && CONSTANT_P (XEXP (x, 1)))
2243 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2245 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2247 /* The only time we want to replace a PLUS with a REG (this
2248 occurs when the constant operand of the PLUS is the negative
2249 of the offset) is when we are inside a MEM. We won't want
2250 to do so at other times because that would change the
2251 structure of the insn in a way that reload can't handle.
2252 We special-case the commonest situation in
2253 eliminate_regs_in_insn, so just replace a PLUS with a
2254 PLUS here, unless inside a MEM. */
2255 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2256 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2259 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2260 plus_constant (XEXP (x, 1),
2261 ep->previous_offset));
2264 /* If the register is not eliminable, we are done since the other
2265 operand is a constant. */
2269 /* If this is part of an address, we want to bring any constant to the
2270 outermost PLUS. We will do this by doing register replacement in
2271 our operands and seeing if a constant shows up in one of them.
2273 Note that there is no risk of modifying the structure of the insn,
2274 since we only get called for its operands, thus we are either
2275 modifying the address inside a MEM, or something like an address
2276 operand of a load-address insn. */
2279 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2280 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2282 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2284 /* If one side is a PLUS and the other side is a pseudo that
2285 didn't get a hard register but has a reg_equiv_constant,
2286 we must replace the constant here since it may no longer
2287 be in the position of any operand. */
2288 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2289 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2290 && reg_renumber[REGNO (new1)] < 0
2291 && reg_equiv_constant != 0
2292 && reg_equiv_constant[REGNO (new1)] != 0)
2293 new1 = reg_equiv_constant[REGNO (new1)];
2294 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2295 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2296 && reg_renumber[REGNO (new0)] < 0
2297 && reg_equiv_constant[REGNO (new0)] != 0)
2298 new0 = reg_equiv_constant[REGNO (new0)];
2300 new = form_sum (new0, new1);
2302 /* As above, if we are not inside a MEM we do not want to
2303 turn a PLUS into something else. We might try to do so here
2304 for an addition of 0 if we aren't optimizing. */
2305 if (! mem_mode && GET_CODE (new) != PLUS)
2306 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2314 /* If this is the product of an eliminable register and a
2315 constant, apply the distribute law and move the constant out
2316 so that we have (plus (mult ..) ..). This is needed in order
2317 to keep load-address insns valid. This case is pathological.
2318 We ignore the possibility of overflow here. */
2319 if (GET_CODE (XEXP (x, 0)) == REG
2320 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2321 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2322 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2324 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2327 /* Refs inside notes don't count for this purpose. */
2328 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2329 || GET_CODE (insn) == INSN_LIST)))
2330 ep->ref_outside_mem = 1;
2333 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2334 ep->previous_offset * INTVAL (XEXP (x, 1)));
2337 /* ... fall through ... */
2341 /* See comments before PLUS about handling MINUS. */
2343 case DIV: case UDIV:
2344 case MOD: case UMOD:
2345 case AND: case IOR: case XOR:
2346 case ROTATERT: case ROTATE:
2347 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2349 case GE: case GT: case GEU: case GTU:
2350 case LE: case LT: case LEU: case LTU:
2352 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2354 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2356 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2357 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2362 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2365 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2366 if (new != XEXP (x, 0))
2368 /* If this is a REG_DEAD note, it is not valid anymore.
2369 Using the eliminated version could result in creating a
2370 REG_DEAD note for the stack or frame pointer. */
2371 if (GET_MODE (x) == REG_DEAD)
2373 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2376 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2380 /* ... fall through ... */
2383 /* Now do eliminations in the rest of the chain. If this was
2384 an EXPR_LIST, this might result in allocating more memory than is
2385 strictly needed, but it simplifies the code. */
2388 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2389 if (new != XEXP (x, 1))
2390 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2398 case STRICT_LOW_PART:
2400 case SIGN_EXTEND: case ZERO_EXTEND:
2401 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2402 case FLOAT: case FIX:
2403 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2407 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2408 if (new != XEXP (x, 0))
2409 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2413 /* Similar to above processing, but preserve SUBREG_WORD.
2414 Convert (subreg (mem)) to (mem) if not paradoxical.
2415 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2416 pseudo didn't get a hard reg, we must replace this with the
2417 eliminated version of the memory location because push_reloads
2418 may do the replacement in certain circumstances. */
2419 if (GET_CODE (SUBREG_REG (x)) == REG
2420 && (GET_MODE_SIZE (GET_MODE (x))
2421 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2422 && reg_equiv_memory_loc != 0
2423 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2425 new = SUBREG_REG (x);
2428 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2430 if (new != XEXP (x, 0))
2432 int x_size = GET_MODE_SIZE (GET_MODE (x));
2433 int new_size = GET_MODE_SIZE (GET_MODE (new));
2435 if (GET_CODE (new) == MEM
2436 && ((x_size < new_size
2437 #ifdef WORD_REGISTER_OPERATIONS
2438 /* On these machines, combine can create rtl of the form
2439 (set (subreg:m1 (reg:m2 R) 0) ...)
2440 where m1 < m2, and expects something interesting to
2441 happen to the entire word. Moreover, it will use the
2442 (reg:m2 R) later, expecting all bits to be preserved.
2443 So if the number of words is the same, preserve the
2444 subreg so that push_reloads can see it. */
2445 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
2448 || (x_size == new_size))
2451 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2452 enum machine_mode mode = GET_MODE (x);
2454 if (BYTES_BIG_ENDIAN)
2455 offset += (MIN (UNITS_PER_WORD,
2456 GET_MODE_SIZE (GET_MODE (new)))
2457 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2459 PUT_MODE (new, mode);
2460 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2464 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
2470 /* This is only for the benefit of the debugging backends, which call
2471 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2472 removed after CSE. */
2473 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2474 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2476 /* Our only special processing is to pass the mode of the MEM to our
2477 recursive call and copy the flags. While we are here, handle this
2478 case more efficiently. */
2479 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
2480 if (new != XEXP (x, 0))
2482 new = gen_rtx_MEM (GET_MODE (x), new);
2483 new->volatil = x->volatil;
2484 new->unchanging = x->unchanging;
2485 new->in_struct = x->in_struct;
2501 /* Process each of our operands recursively. If any have changed, make a
2503 fmt = GET_RTX_FORMAT (code);
2504 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2508 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2509 if (new != XEXP (x, i) && ! copied)
2511 rtx new_x = rtx_alloc (code);
2512 bcopy ((char *) x, (char *) new_x,
2513 (sizeof (*new_x) - sizeof (new_x->fld)
2514 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2520 else if (*fmt == 'E')
2523 for (j = 0; j < XVECLEN (x, i); j++)
2525 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2526 if (new != XVECEXP (x, i, j) && ! copied_vec)
2528 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2532 rtx new_x = rtx_alloc (code);
2533 bcopy ((char *) x, (char *) new_x,
2534 (sizeof (*new_x) - sizeof (new_x->fld)
2535 + (sizeof (new_x->fld[0])
2536 * GET_RTX_LENGTH (code))));
2540 XVEC (x, i) = new_v;
2543 XVECEXP (x, i, j) = new;
2551 /* Scan rtx X for modifications of elimination target registers. Update
2552 the table of eliminables to reflect the changed state. MEM_MODE is
2553 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2556 elimination_effects (x, mem_mode)
2558 enum machine_mode mem_mode;
2561 enum rtx_code code = GET_CODE (x);
2562 struct elim_table *ep;
2588 /* First handle the case where we encounter a bare register that
2589 is eliminable. Replace it with a PLUS. */
2590 if (regno < FIRST_PSEUDO_REGISTER)
2592 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2594 if (ep->from_rtx == x && ep->can_eliminate)
2597 ep->ref_outside_mem = 1;
2602 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2603 && reg_equiv_constant[regno]
2604 && ! CONSTANT_P (reg_equiv_constant[regno]))
2605 elimination_effects (reg_equiv_constant[regno], mem_mode);
2612 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2613 if (ep->to_rtx == XEXP (x, 0))
2615 int size = GET_MODE_SIZE (mem_mode);
2617 /* If more bytes than MEM_MODE are pushed, account for them. */
2618 #ifdef PUSH_ROUNDING
2619 if (ep->to_rtx == stack_pointer_rtx)
2620 size = PUSH_ROUNDING (size);
2622 if (code == PRE_DEC || code == POST_DEC)
2628 /* Fall through to generic unary operation case. */
2629 case STRICT_LOW_PART:
2631 case SIGN_EXTEND: case ZERO_EXTEND:
2632 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2633 case FLOAT: case FIX:
2634 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2638 elimination_effects (XEXP (x, 0), mem_mode);
2642 if (GET_CODE (SUBREG_REG (x)) == REG
2643 && (GET_MODE_SIZE (GET_MODE (x))
2644 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2645 && reg_equiv_memory_loc != 0
2646 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2649 elimination_effects (SUBREG_REG (x), mem_mode);
2653 /* If using a register that is the source of an eliminate we still
2654 think can be performed, note it cannot be performed since we don't
2655 know how this register is used. */
2656 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2657 if (ep->from_rtx == XEXP (x, 0))
2658 ep->can_eliminate = 0;
2660 elimination_effects (XEXP (x, 0), mem_mode);
2664 /* If clobbering a register that is the replacement register for an
2665 elimination we still think can be performed, note that it cannot
2666 be performed. Otherwise, we need not be concerned about it. */
2667 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2668 if (ep->to_rtx == XEXP (x, 0))
2669 ep->can_eliminate = 0;
2671 elimination_effects (XEXP (x, 0), mem_mode);
2675 /* Check for setting a register that we know about. */
2676 if (GET_CODE (SET_DEST (x)) == REG)
2678 /* See if this is setting the replacement register for an
2681 If DEST is the hard frame pointer, we do nothing because we
2682 assume that all assignments to the frame pointer are for
2683 non-local gotos and are being done at a time when they are valid
2684 and do not disturb anything else. Some machines want to
2685 eliminate a fake argument pointer (or even a fake frame pointer)
2686 with either the real frame or the stack pointer. Assignments to
2687 the hard frame pointer must not prevent this elimination. */
2689 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2691 if (ep->to_rtx == SET_DEST (x)
2692 && SET_DEST (x) != hard_frame_pointer_rtx)
2694 /* If it is being incremented, adjust the offset. Otherwise,
2695 this elimination can't be done. */
2696 rtx src = SET_SRC (x);
2698 if (GET_CODE (src) == PLUS
2699 && XEXP (src, 0) == SET_DEST (x)
2700 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2701 ep->offset -= INTVAL (XEXP (src, 1));
2703 ep->can_eliminate = 0;
2707 elimination_effects (SET_DEST (x), 0);
2708 elimination_effects (SET_SRC (x), 0);
2712 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2715 /* Our only special processing is to pass the mode of the MEM to our
2717 elimination_effects (XEXP (x, 0), GET_MODE (x));
2724 fmt = GET_RTX_FORMAT (code);
2725 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2728 elimination_effects (XEXP (x, i), mem_mode);
2729 else if (*fmt == 'E')
2730 for (j = 0; j < XVECLEN (x, i); j++)
2731 elimination_effects (XVECEXP (x, i, j), mem_mode);
2735 /* Descend through rtx X and verify that no references to eliminable registers
2736 remain. If any do remain, mark the involved register as not
2739 check_eliminable_occurrences (x)
2749 code = GET_CODE (x);
2751 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2753 struct elim_table *ep;
2755 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2756 if (ep->from_rtx == x && ep->can_eliminate)
2757 ep->can_eliminate = 0;
2761 fmt = GET_RTX_FORMAT (code);
2762 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2765 check_eliminable_occurrences (XEXP (x, i));
2766 else if (*fmt == 'E')
2769 for (j = 0; j < XVECLEN (x, i); j++)
2770 check_eliminable_occurrences (XVECEXP (x, i, j));
2775 /* Scan INSN and eliminate all eliminable registers in it.
2777 If REPLACE is nonzero, do the replacement destructively. Also
2778 delete the insn as dead it if it is setting an eliminable register.
2780 If REPLACE is zero, do all our allocations in reload_obstack.
2782 If no eliminations were done and this insn doesn't require any elimination
2783 processing (these are not identical conditions: it might be updating sp,
2784 but not referencing fp; this needs to be seen during reload_as_needed so
2785 that the offset between fp and sp can be taken into consideration), zero
2786 is returned. Otherwise, 1 is returned. */
2789 eliminate_regs_in_insn (insn, replace)
2793 int icode = recog_memoized (insn);
2794 rtx old_body = PATTERN (insn);
2795 int insn_is_asm = asm_noperands (old_body) >= 0;
2796 rtx old_set = single_set (insn);
2800 rtx substed_operand[MAX_RECOG_OPERANDS];
2801 rtx orig_operand[MAX_RECOG_OPERANDS];
2802 struct elim_table *ep;
2804 if (! insn_is_asm && icode < 0)
2806 if (GET_CODE (PATTERN (insn)) == USE
2807 || GET_CODE (PATTERN (insn)) == CLOBBER
2808 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2809 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2810 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2816 push_obstacks (&reload_obstack, &reload_obstack);
2818 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2819 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2821 /* Check for setting an eliminable register. */
2822 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2823 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2825 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2826 /* If this is setting the frame pointer register to the
2827 hardware frame pointer register and this is an elimination
2828 that will be done (tested above), this insn is really
2829 adjusting the frame pointer downward to compensate for
2830 the adjustment done before a nonlocal goto. */
2831 if (ep->from == FRAME_POINTER_REGNUM
2832 && ep->to == HARD_FRAME_POINTER_REGNUM)
2834 rtx src = SET_SRC (old_set);
2835 int offset = 0, ok = 0;
2836 rtx prev_insn, prev_set;
2838 if (src == ep->to_rtx)
2840 else if (GET_CODE (src) == PLUS
2841 && GET_CODE (XEXP (src, 0)) == CONST_INT
2842 && XEXP (src, 1) == ep->to_rtx)
2843 offset = INTVAL (XEXP (src, 0)), ok = 1;
2844 else if (GET_CODE (src) == PLUS
2845 && GET_CODE (XEXP (src, 1)) == CONST_INT
2846 && XEXP (src, 0) == ep->to_rtx)
2847 offset = INTVAL (XEXP (src, 1)), ok = 1;
2848 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
2849 && (prev_set = single_set (prev_insn)) != 0
2850 && rtx_equal_p (SET_DEST (prev_set), src))
2852 src = SET_SRC (prev_set);
2853 if (src == ep->to_rtx)
2855 else if (GET_CODE (src) == PLUS
2856 && GET_CODE (XEXP (src, 0)) == CONST_INT
2857 && XEXP (src, 1) == ep->to_rtx)
2858 offset = INTVAL (XEXP (src, 0)), ok = 1;
2859 else if (GET_CODE (src) == PLUS
2860 && GET_CODE (XEXP (src, 1)) == CONST_INT
2861 && XEXP (src, 0) == ep->to_rtx)
2862 offset = INTVAL (XEXP (src, 1)), ok = 1;
2870 = plus_constant (ep->to_rtx, offset - ep->offset);
2872 /* First see if this insn remains valid when we
2873 make the change. If not, keep the INSN_CODE
2874 the same and let reload fit it up. */
2875 validate_change (insn, &SET_SRC (old_set), src, 1);
2876 validate_change (insn, &SET_DEST (old_set),
2878 if (! apply_change_group ())
2880 SET_SRC (old_set) = src;
2881 SET_DEST (old_set) = ep->to_rtx;
2891 /* In this case this insn isn't serving a useful purpose. We
2892 will delete it in reload_as_needed once we know that this
2893 elimination is, in fact, being done.
2895 If REPLACE isn't set, we can't delete this insn, but needn't
2896 process it since it won't be used unless something changes. */
2899 delete_dead_insn (insn);
2906 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
2907 in the insn is the negative of the offset in FROM. Substitute
2908 (set (reg) (reg to)) for the insn and change its code.
2910 We have to do this here, rather than in eliminate_regs, so that we can
2911 change the insn code. */
2913 if (GET_CODE (SET_SRC (old_set)) == PLUS
2914 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
2915 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT)
2916 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2918 if (ep->from_rtx == XEXP (SET_SRC (old_set), 0)
2919 && ep->can_eliminate)
2921 /* We must stop at the first elimination that will be used.
2922 If this one would replace the PLUS with a REG, do it
2923 now. Otherwise, quit the loop and let eliminate_regs
2924 do its normal replacement. */
2925 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_set), 1)))
2927 /* We assume here that we don't need a PARALLEL of
2928 any CLOBBERs for this assignment. There's not
2929 much we can do if we do need it. */
2930 PATTERN (insn) = gen_rtx_SET (VOIDmode,
2933 INSN_CODE (insn) = -1;
2942 /* Determine the effects of this insn on elimination offsets. */
2943 elimination_effects (old_body, 0);
2945 /* Eliminate all eliminable registers occurring in operands that
2946 can be handled by reload. */
2947 extract_insn (insn);
2949 for (i = 0; i < recog_data.n_operands; i++)
2951 orig_operand[i] = recog_data.operand[i];
2952 substed_operand[i] = recog_data.operand[i];
2954 /* For an asm statement, every operand is eliminable. */
2955 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
2957 /* Check for setting a register that we know about. */
2958 if (recog_data.operand_type[i] != OP_IN
2959 && GET_CODE (orig_operand[i]) == REG)
2961 /* If we are assigning to a register that can be eliminated, it
2962 must be as part of a PARALLEL, since the code above handles
2963 single SETs. We must indicate that we can no longer
2964 eliminate this reg. */
2965 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2967 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
2968 ep->can_eliminate = 0;
2971 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
2972 replace ? insn : NULL_RTX);
2973 if (substed_operand[i] != orig_operand[i])
2974 val = any_changes = 1;
2975 /* Terminate the search in check_eliminable_occurrences at
2977 *recog_data.operand_loc[i] = 0;
2979 /* If an output operand changed from a REG to a MEM and INSN is an
2980 insn, write a CLOBBER insn. */
2981 if (recog_data.operand_type[i] != OP_IN
2982 && GET_CODE (orig_operand[i]) == REG
2983 && GET_CODE (substed_operand[i]) == MEM
2985 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
2990 for (i = 0; i < recog_data.n_dups; i++)
2991 *recog_data.dup_loc[i]
2992 = *recog_data.operand_loc[(int)recog_data.dup_num[i]];
2994 /* If any eliminable remain, they aren't eliminable anymore. */
2995 check_eliminable_occurrences (old_body);
2997 /* Substitute the operands; the new values are in the substed_operand
2999 for (i = 0; i < recog_data.n_operands; i++)
3000 *recog_data.operand_loc[i] = substed_operand[i];
3001 for (i = 0; i < recog_data.n_dups; i++)
3002 *recog_data.dup_loc[i] = substed_operand[(int)recog_data.dup_num[i]];
3004 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3005 re-recognize the insn. We do this in case we had a simple addition
3006 but now can do this as a load-address. This saves an insn in this
3008 If re-recognition fails, the old insn code number will still be used,
3009 and some register operands may have changed into PLUS expressions.
3010 These will be handled by find_reloads by loading them into a register
3015 /* If we aren't replacing things permanently and we changed something,
3016 make another copy to ensure that all the RTL is new. Otherwise
3017 things can go wrong if find_reload swaps commutative operands
3018 and one is inside RTL that has been copied while the other is not. */
3019 new_body = old_body;
3022 new_body = copy_insn (old_body);
3023 if (REG_NOTES (insn))
3024 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3026 PATTERN (insn) = new_body;
3028 /* If we had a move insn but now we don't, rerecognize it. This will
3029 cause spurious re-recognition if the old move had a PARALLEL since
3030 the new one still will, but we can't call single_set without
3031 having put NEW_BODY into the insn and the re-recognition won't
3032 hurt in this rare case. */
3033 /* ??? Why this huge if statement - why don't we just rerecognize the
3037 && ((GET_CODE (SET_SRC (old_set)) == REG
3038 && (GET_CODE (new_body) != SET
3039 || GET_CODE (SET_SRC (new_body)) != REG))
3040 /* If this was a load from or store to memory, compare
3041 the MEM in recog_data.operand to the one in the insn.
3042 If they are not equal, then rerecognize the insn. */
3044 && ((GET_CODE (SET_SRC (old_set)) == MEM
3045 && SET_SRC (old_set) != recog_data.operand[1])
3046 || (GET_CODE (SET_DEST (old_set)) == MEM
3047 && SET_DEST (old_set) != recog_data.operand[0])))
3048 /* If this was an add insn before, rerecognize. */
3049 || GET_CODE (SET_SRC (old_set)) == PLUS))
3051 int new_icode = recog (PATTERN (insn), insn, 0);
3053 INSN_CODE (insn) = icode;
3057 /* Restore the old body. If there were any changes to it, we made a copy
3058 of it while the changes were still in place, so we'll correctly return
3059 a modified insn below. */
3062 /* Restore the old body. */
3063 for (i = 0; i < recog_data.n_operands; i++)
3064 *recog_data.operand_loc[i] = orig_operand[i];
3065 for (i = 0; i < recog_data.n_dups; i++)
3066 *recog_data.dup_loc[i] = orig_operand[(int)recog_data.dup_num[i]];
3069 /* Update all elimination pairs to reflect the status after the current
3070 insn. The changes we make were determined by the earlier call to
3071 elimination_effects.
3073 We also detect a cases where register elimination cannot be done,
3074 namely, if a register would be both changed and referenced outside a MEM
3075 in the resulting insn since such an insn is often undefined and, even if
3076 not, we cannot know what meaning will be given to it. Note that it is
3077 valid to have a register used in an address in an insn that changes it
3078 (presumably with a pre- or post-increment or decrement).
3080 If anything changes, return nonzero. */
3082 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3084 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3085 ep->can_eliminate = 0;
3087 ep->ref_outside_mem = 0;
3089 if (ep->previous_offset != ep->offset)
3094 /* If we changed something, perform elimination in REG_NOTES. This is
3095 needed even when REPLACE is zero because a REG_DEAD note might refer
3096 to a register that we eliminate and could cause a different number
3097 of spill registers to be needed in the final reload pass than in
3099 if (val && REG_NOTES (insn) != 0)
3100 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3108 /* Loop through all elimination pairs.
3109 Recalculate the number not at initial offset.
3111 Compute the maximum offset (minimum offset if the stack does not
3112 grow downward) for each elimination pair. */
3115 update_eliminable_offsets ()
3117 struct elim_table *ep;
3119 num_not_at_initial_offset = 0;
3120 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3122 ep->previous_offset = ep->offset;
3123 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3124 num_not_at_initial_offset++;
3128 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3129 replacement we currently believe is valid, mark it as not eliminable if X
3130 modifies DEST in any way other than by adding a constant integer to it.
3132 If DEST is the frame pointer, we do nothing because we assume that
3133 all assignments to the hard frame pointer are nonlocal gotos and are being
3134 done at a time when they are valid and do not disturb anything else.
3135 Some machines want to eliminate a fake argument pointer with either the
3136 frame or stack pointer. Assignments to the hard frame pointer must not
3137 prevent this elimination.
3139 Called via note_stores from reload before starting its passes to scan
3140 the insns of the function. */
3143 mark_not_eliminable (dest, x, data)
3146 void *data ATTRIBUTE_UNUSED;
3148 register unsigned int i;
3150 /* A SUBREG of a hard register here is just changing its mode. We should
3151 not see a SUBREG of an eliminable hard register, but check just in
3153 if (GET_CODE (dest) == SUBREG)
3154 dest = SUBREG_REG (dest);
3156 if (dest == hard_frame_pointer_rtx)
3159 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3160 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3161 && (GET_CODE (x) != SET
3162 || GET_CODE (SET_SRC (x)) != PLUS
3163 || XEXP (SET_SRC (x), 0) != dest
3164 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3166 reg_eliminate[i].can_eliminate_previous
3167 = reg_eliminate[i].can_eliminate = 0;
3172 /* Verify that the initial elimination offsets did not change since the
3173 last call to set_initial_elim_offsets. This is used to catch cases
3174 where something illegal happened during reload_as_needed that could
3175 cause incorrect code to be generated if we did not check for it. */
3178 verify_initial_elim_offsets ()
3182 #ifdef ELIMINABLE_REGS
3183 struct elim_table *ep;
3185 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3187 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3188 if (t != ep->initial_offset)
3192 INITIAL_FRAME_POINTER_OFFSET (t);
3193 if (t != reg_eliminate[0].initial_offset)
3198 /* Reset all offsets on eliminable registers to their initial values. */
3200 set_initial_elim_offsets ()
3202 struct elim_table *ep = reg_eliminate;
3204 #ifdef ELIMINABLE_REGS
3205 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3207 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3208 ep->previous_offset = ep->offset = ep->initial_offset;
3211 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3212 ep->previous_offset = ep->offset = ep->initial_offset;
3215 num_not_at_initial_offset = 0;
3218 /* Initialize the known label offsets.
3219 Set a known offset for each forced label to be at the initial offset
3220 of each elimination. We do this because we assume that all
3221 computed jumps occur from a location where each elimination is
3222 at its initial offset.
3223 For all other labels, show that we don't know the offsets. */
3226 set_initial_label_offsets ()
3229 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
3231 for (x = forced_labels; x; x = XEXP (x, 1))
3233 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3236 /* Set all elimination offsets to the known values for the code label given
3239 set_offsets_for_label (insn)
3243 int label_nr = CODE_LABEL_NUMBER (insn);
3244 struct elim_table *ep;
3246 num_not_at_initial_offset = 0;
3247 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3249 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3250 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3251 num_not_at_initial_offset++;
3255 /* See if anything that happened changes which eliminations are valid.
3256 For example, on the Sparc, whether or not the frame pointer can
3257 be eliminated can depend on what registers have been used. We need
3258 not check some conditions again (such as flag_omit_frame_pointer)
3259 since they can't have changed. */
3262 update_eliminables (pset)
3265 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3266 int previous_frame_pointer_needed = frame_pointer_needed;
3268 struct elim_table *ep;
3270 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3271 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3272 #ifdef ELIMINABLE_REGS
3273 || ! CAN_ELIMINATE (ep->from, ep->to)
3276 ep->can_eliminate = 0;
3278 /* Look for the case where we have discovered that we can't replace
3279 register A with register B and that means that we will now be
3280 trying to replace register A with register C. This means we can
3281 no longer replace register C with register B and we need to disable
3282 such an elimination, if it exists. This occurs often with A == ap,
3283 B == sp, and C == fp. */
3285 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3287 struct elim_table *op;
3288 register int new_to = -1;
3290 if (! ep->can_eliminate && ep->can_eliminate_previous)
3292 /* Find the current elimination for ep->from, if there is a
3294 for (op = reg_eliminate;
3295 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3296 if (op->from == ep->from && op->can_eliminate)
3302 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3304 for (op = reg_eliminate;
3305 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3306 if (op->from == new_to && op->to == ep->to)
3307 op->can_eliminate = 0;
3311 /* See if any registers that we thought we could eliminate the previous
3312 time are no longer eliminable. If so, something has changed and we
3313 must spill the register. Also, recompute the number of eliminable
3314 registers and see if the frame pointer is needed; it is if there is
3315 no elimination of the frame pointer that we can perform. */
3317 frame_pointer_needed = 1;
3318 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3320 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3321 && ep->to != HARD_FRAME_POINTER_REGNUM)
3322 frame_pointer_needed = 0;
3324 if (! ep->can_eliminate && ep->can_eliminate_previous)
3326 ep->can_eliminate_previous = 0;
3327 SET_HARD_REG_BIT (*pset, ep->from);
3332 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3333 /* If we didn't need a frame pointer last time, but we do now, spill
3334 the hard frame pointer. */
3335 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3336 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3340 /* Initialize the table of registers to eliminate. */
3344 struct elim_table *ep;
3345 #ifdef ELIMINABLE_REGS
3346 struct elim_table_1 *ep1;
3350 reg_eliminate = (struct elim_table *)
3351 xcalloc(sizeof(struct elim_table), NUM_ELIMINABLE_REGS);
3353 /* Does this function require a frame pointer? */
3355 frame_pointer_needed = (! flag_omit_frame_pointer
3356 #ifdef EXIT_IGNORE_STACK
3357 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3358 and restore sp for alloca. So we can't eliminate
3359 the frame pointer in that case. At some point,
3360 we should improve this by emitting the
3361 sp-adjusting insns for this case. */
3362 || (current_function_calls_alloca
3363 && EXIT_IGNORE_STACK)
3365 || FRAME_POINTER_REQUIRED);
3369 #ifdef ELIMINABLE_REGS
3370 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3371 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3373 ep->from = ep1->from;
3375 ep->can_eliminate = ep->can_eliminate_previous
3376 = (CAN_ELIMINATE (ep->from, ep->to)
3377 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3380 reg_eliminate[0].from = reg_eliminate_1[0].from;
3381 reg_eliminate[0].to = reg_eliminate_1[0].to;
3382 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3383 = ! frame_pointer_needed;
3386 /* Count the number of eliminable registers and build the FROM and TO
3387 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3388 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3389 We depend on this. */
3390 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3392 num_eliminable += ep->can_eliminate;
3393 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3394 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3398 /* Kick all pseudos out of hard register REGNO.
3399 If DUMPFILE is nonzero, log actions taken on that file.
3401 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3402 because we found we can't eliminate some register. In the case, no pseudos
3403 are allowed to be in the register, even if they are only in a block that
3404 doesn't require spill registers, unlike the case when we are spilling this
3405 hard reg to produce another spill register.
3407 Return nonzero if any pseudos needed to be kicked out. */
3410 spill_hard_reg (regno, dumpfile, cant_eliminate)
3412 FILE *dumpfile ATTRIBUTE_UNUSED;
3419 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3420 regs_ever_live[regno] = 1;
3423 /* Spill every pseudo reg that was allocated to this reg
3424 or to something that overlaps this reg. */
3426 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3427 if (reg_renumber[i] >= 0
3428 && reg_renumber[i] <= regno
3430 + HARD_REGNO_NREGS (reg_renumber[i],
3431 PSEUDO_REGNO_MODE (i))
3433 SET_REGNO_REG_SET (&spilled_pseudos, i);
3436 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3437 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3439 ior_hard_reg_set (set1, set2)
3440 HARD_REG_SET *set1, *set2;
3442 IOR_HARD_REG_SET (*set1, *set2);
3445 /* After find_reload_regs has been run for all insn that need reloads,
3446 and/or spill_hard_regs was called, this function is used to actually
3447 spill pseudo registers and try to reallocate them. It also sets up the
3448 spill_regs array for use by choose_reload_regs. */
3451 finish_spills (global, dumpfile)
3455 struct insn_chain *chain;
3456 int something_changed = 0;
3459 /* Build the spill_regs array for the function. */
3460 /* If there are some registers still to eliminate and one of the spill regs
3461 wasn't ever used before, additional stack space may have to be
3462 allocated to store this register. Thus, we may have changed the offset
3463 between the stack and frame pointers, so mark that something has changed.
3465 One might think that we need only set VAL to 1 if this is a call-used
3466 register. However, the set of registers that must be saved by the
3467 prologue is not identical to the call-used set. For example, the
3468 register used by the call insn for the return PC is a call-used register,
3469 but must be saved by the prologue. */
3472 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3473 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3475 spill_reg_order[i] = n_spills;
3476 spill_regs[n_spills++] = i;
3477 if (num_eliminable && ! regs_ever_live[i])
3478 something_changed = 1;
3479 regs_ever_live[i] = 1;
3482 spill_reg_order[i] = -1;
3484 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3485 if (REGNO_REG_SET_P (&spilled_pseudos, i))
3487 /* Record the current hard register the pseudo is allocated to in
3488 pseudo_previous_regs so we avoid reallocating it to the same
3489 hard reg in a later pass. */
3490 if (reg_renumber[i] < 0)
3492 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3493 /* Mark it as no longer having a hard register home. */
3494 reg_renumber[i] = -1;
3495 /* We will need to scan everything again. */
3496 something_changed = 1;
3499 /* Retry global register allocation if possible. */
3502 bzero ((char *) pseudo_forbidden_regs, max_regno * sizeof (HARD_REG_SET));
3503 /* For every insn that needs reloads, set the registers used as spill
3504 regs in pseudo_forbidden_regs for every pseudo live across the
3506 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3508 EXECUTE_IF_SET_IN_REG_SET
3509 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3511 ior_hard_reg_set (pseudo_forbidden_regs + i,
3512 &chain->used_spill_regs);
3514 EXECUTE_IF_SET_IN_REG_SET
3515 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3517 ior_hard_reg_set (pseudo_forbidden_regs + i,
3518 &chain->used_spill_regs);
3522 /* Retry allocating the spilled pseudos. For each reg, merge the
3523 various reg sets that indicate which hard regs can't be used,
3524 and call retry_global_alloc.
3525 We change spill_pseudos here to only contain pseudos that did not
3526 get a new hard register. */
3527 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3528 if (reg_old_renumber[i] != reg_renumber[i])
3530 HARD_REG_SET forbidden;
3531 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3532 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3533 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3534 retry_global_alloc (i, forbidden);
3535 if (reg_renumber[i] >= 0)
3536 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3540 /* Fix up the register information in the insn chain.
3541 This involves deleting those of the spilled pseudos which did not get
3542 a new hard register home from the live_{before,after} sets. */
3543 for (chain = reload_insn_chain; chain; chain = chain->next)
3545 HARD_REG_SET used_by_pseudos;
3546 HARD_REG_SET used_by_pseudos2;
3548 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3549 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3551 /* Mark any unallocated hard regs as available for spills. That
3552 makes inheritance work somewhat better. */
3553 if (chain->need_reload)
3555 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3556 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3557 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3559 /* Save the old value for the sanity test below. */
3560 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3562 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3563 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3564 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3565 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3567 /* Make sure we only enlarge the set. */
3568 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3574 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3575 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3577 int regno = reg_renumber[i];
3578 if (reg_old_renumber[i] == regno)
3581 alter_reg (i, reg_old_renumber[i]);
3582 reg_old_renumber[i] = regno;
3586 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3588 fprintf (dumpfile, " Register %d now in %d.\n\n",
3589 i, reg_renumber[i]);
3593 return something_changed;
3596 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3597 Also mark any hard registers used to store user variables as
3598 forbidden from being used for spill registers. */
3601 scan_paradoxical_subregs (x)
3605 register const char *fmt;
3606 register enum rtx_code code = GET_CODE (x);
3612 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3613 && REG_USERVAR_P (x))
3614 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3630 if (GET_CODE (SUBREG_REG (x)) == REG
3631 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3632 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3633 = GET_MODE_SIZE (GET_MODE (x));
3640 fmt = GET_RTX_FORMAT (code);
3641 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3644 scan_paradoxical_subregs (XEXP (x, i));
3645 else if (fmt[i] == 'E')
3648 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3649 scan_paradoxical_subregs (XVECEXP (x, i, j));
3654 /* Reload pseudo-registers into hard regs around each insn as needed.
3655 Additional register load insns are output before the insn that needs it
3656 and perhaps store insns after insns that modify the reloaded pseudo reg.
3658 reg_last_reload_reg and reg_reloaded_contents keep track of
3659 which registers are already available in reload registers.
3660 We update these for the reloads that we perform,
3661 as the insns are scanned. */
3664 reload_as_needed (live_known)
3667 struct insn_chain *chain;
3668 #if defined (AUTO_INC_DEC)
3673 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
3674 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
3675 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3676 reg_has_output_reload = (char *) xmalloc (max_regno);
3677 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3679 set_initial_elim_offsets ();
3681 for (chain = reload_insn_chain; chain; chain = chain->next)
3684 rtx insn = chain->insn;
3685 rtx old_next = NEXT_INSN (insn);
3687 /* If we pass a label, copy the offsets from the label information
3688 into the current offsets of each elimination. */
3689 if (GET_CODE (insn) == CODE_LABEL)
3690 set_offsets_for_label (insn);
3692 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3694 rtx oldpat = PATTERN (insn);
3696 /* If this is a USE and CLOBBER of a MEM, ensure that any
3697 references to eliminable registers have been removed. */
3699 if ((GET_CODE (PATTERN (insn)) == USE
3700 || GET_CODE (PATTERN (insn)) == CLOBBER)
3701 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3702 XEXP (XEXP (PATTERN (insn), 0), 0)
3703 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3704 GET_MODE (XEXP (PATTERN (insn), 0)),
3707 /* If we need to do register elimination processing, do so.
3708 This might delete the insn, in which case we are done. */
3709 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3711 eliminate_regs_in_insn (insn, 1);
3712 if (GET_CODE (insn) == NOTE)
3714 update_eliminable_offsets ();
3719 /* If need_elim is nonzero but need_reload is zero, one might think
3720 that we could simply set n_reloads to 0. However, find_reloads
3721 could have done some manipulation of the insn (such as swapping
3722 commutative operands), and these manipulations are lost during
3723 the first pass for every insn that needs register elimination.
3724 So the actions of find_reloads must be redone here. */
3726 if (! chain->need_elim && ! chain->need_reload
3727 && ! chain->need_operand_change)
3729 /* First find the pseudo regs that must be reloaded for this insn.
3730 This info is returned in the tables reload_... (see reload.h).
3731 Also modify the body of INSN by substituting RELOAD
3732 rtx's for those pseudo regs. */
3735 bzero (reg_has_output_reload, max_regno);
3736 CLEAR_HARD_REG_SET (reg_is_output_reload);
3738 find_reloads (insn, 1, spill_indirect_levels, live_known,
3742 if (num_eliminable && chain->need_elim)
3743 update_eliminable_offsets ();
3747 rtx next = NEXT_INSN (insn);
3750 prev = PREV_INSN (insn);
3752 /* Now compute which reload regs to reload them into. Perhaps
3753 reusing reload regs from previous insns, or else output
3754 load insns to reload them. Maybe output store insns too.
3755 Record the choices of reload reg in reload_reg_rtx. */
3756 choose_reload_regs (chain);
3758 /* Merge any reloads that we didn't combine for fear of
3759 increasing the number of spill registers needed but now
3760 discover can be safely merged. */
3761 if (SMALL_REGISTER_CLASSES)
3762 merge_assigned_reloads (insn);
3764 /* Generate the insns to reload operands into or out of
3765 their reload regs. */
3766 emit_reload_insns (chain);
3768 /* Substitute the chosen reload regs from reload_reg_rtx
3769 into the insn's body (or perhaps into the bodies of other
3770 load and store insn that we just made for reloading
3771 and that we moved the structure into). */
3774 /* If this was an ASM, make sure that all the reload insns
3775 we have generated are valid. If not, give an error
3778 if (asm_noperands (PATTERN (insn)) >= 0)
3779 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3780 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
3781 && (recog_memoized (p) < 0
3782 || (extract_insn (p), ! constrain_operands (1))))
3784 error_for_asm (insn,
3785 "`asm' operand requires impossible reload");
3787 NOTE_SOURCE_FILE (p) = 0;
3788 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3791 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3792 is no longer validly lying around to save a future reload.
3793 Note that this does not detect pseudos that were reloaded
3794 for this insn in order to be stored in
3795 (obeying register constraints). That is correct; such reload
3796 registers ARE still valid. */
3797 note_stores (oldpat, forget_old_reloads_1, NULL);
3799 /* There may have been CLOBBER insns placed after INSN. So scan
3800 between INSN and NEXT and use them to forget old reloads. */
3801 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3802 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3803 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3806 /* Likewise for regs altered by auto-increment in this insn.
3807 REG_INC notes have been changed by reloading:
3808 find_reloads_address_1 records substitutions for them,
3809 which have been performed by subst_reloads above. */
3810 for (i = n_reloads - 1; i >= 0; i--)
3812 rtx in_reg = rld[i].in_reg;
3815 enum rtx_code code = GET_CODE (in_reg);
3816 /* PRE_INC / PRE_DEC will have the reload register ending up
3817 with the same value as the stack slot, but that doesn't
3818 hold true for POST_INC / POST_DEC. Either we have to
3819 convert the memory access to a true POST_INC / POST_DEC,
3820 or we can't use the reload register for inheritance. */
3821 if ((code == POST_INC || code == POST_DEC)
3822 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3823 REGNO (rld[i].reg_rtx))
3824 /* Make sure it is the inc/dec pseudo, and not
3825 some other (e.g. output operand) pseudo. */
3826 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3827 == REGNO (XEXP (in_reg, 0))))
3830 rtx reload_reg = rld[i].reg_rtx;
3831 enum machine_mode mode = GET_MODE (reload_reg);
3835 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3837 /* We really want to ignore REG_INC notes here, so
3838 use PATTERN (p) as argument to reg_set_p . */
3839 if (reg_set_p (reload_reg, PATTERN (p)))
3841 n = count_occurrences (PATTERN (p), reload_reg);
3846 n = validate_replace_rtx (reload_reg,
3847 gen_rtx (code, mode,
3851 /* We must also verify that the constraints
3852 are met after the replacement. */
3855 n = constrain_operands (1);
3859 /* If the constraints were not met, then
3860 undo the replacement. */
3863 validate_replace_rtx (gen_rtx (code, mode,
3875 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3877 /* Mark this as having an output reload so that the
3878 REG_INC processing code below won't invalidate
3879 the reload for inheritance. */
3880 SET_HARD_REG_BIT (reg_is_output_reload,
3881 REGNO (reload_reg));
3882 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3885 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3888 else if ((code == PRE_INC || code == PRE_DEC)
3889 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3890 REGNO (rld[i].reg_rtx))
3891 /* Make sure it is the inc/dec pseudo, and not
3892 some other (e.g. output operand) pseudo. */
3893 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3894 == REGNO (XEXP (in_reg, 0))))
3896 SET_HARD_REG_BIT (reg_is_output_reload,
3897 REGNO (rld[i].reg_rtx));
3898 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3902 /* If a pseudo that got a hard register is auto-incremented,
3903 we must purge records of copying it into pseudos without
3905 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3906 if (REG_NOTE_KIND (x) == REG_INC)
3908 /* See if this pseudo reg was reloaded in this insn.
3909 If so, its last-reload info is still valid
3910 because it is based on this insn's reload. */
3911 for (i = 0; i < n_reloads; i++)
3912 if (rld[i].out == XEXP (x, 0))
3916 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
3920 /* A reload reg's contents are unknown after a label. */
3921 if (GET_CODE (insn) == CODE_LABEL)
3922 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3924 /* Don't assume a reload reg is still good after a call insn
3925 if it is a call-used reg. */
3926 else if (GET_CODE (insn) == CALL_INSN)
3927 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
3931 free (reg_last_reload_reg);
3932 free (reg_has_output_reload);
3935 /* Discard all record of any value reloaded from X,
3936 or reloaded in X from someplace else;
3937 unless X is an output reload reg of the current insn.
3939 X may be a hard reg (the reload reg)
3940 or it may be a pseudo reg that was reloaded from. */
3943 forget_old_reloads_1 (x, ignored, data)
3945 rtx ignored ATTRIBUTE_UNUSED;
3946 void *data ATTRIBUTE_UNUSED;
3952 /* note_stores does give us subregs of hard regs. */
3953 while (GET_CODE (x) == SUBREG)
3955 offset += SUBREG_WORD (x);
3959 if (GET_CODE (x) != REG)
3962 regno = REGNO (x) + offset;
3964 if (regno >= FIRST_PSEUDO_REGISTER)
3969 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
3970 /* Storing into a spilled-reg invalidates its contents.
3971 This can happen if a block-local pseudo is allocated to that reg
3972 and it wasn't spilled because this block's total need is 0.
3973 Then some insn might have an optional reload and use this reg. */
3974 for (i = 0; i < nr; i++)
3975 /* But don't do this if the reg actually serves as an output
3976 reload reg in the current instruction. */
3978 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
3979 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
3982 /* Since value of X has changed,
3983 forget any value previously copied from it. */
3986 /* But don't forget a copy if this is the output reload
3987 that establishes the copy's validity. */
3988 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
3989 reg_last_reload_reg[regno + nr] = 0;
3992 /* The following HARD_REG_SETs indicate when each hard register is
3993 used for a reload of various parts of the current insn. */
3995 /* If reg is unavailable for all reloads. */
3996 static HARD_REG_SET reload_reg_unavailable;
3997 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
3998 static HARD_REG_SET reload_reg_used;
3999 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4000 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4001 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4002 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4003 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4004 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4005 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4006 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4007 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4008 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4009 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4010 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4011 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4012 static HARD_REG_SET reload_reg_used_in_op_addr;
4013 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4014 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4015 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4016 static HARD_REG_SET reload_reg_used_in_insn;
4017 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4018 static HARD_REG_SET reload_reg_used_in_other_addr;
4020 /* If reg is in use as a reload reg for any sort of reload. */
4021 static HARD_REG_SET reload_reg_used_at_all;
4023 /* If reg is use as an inherited reload. We just mark the first register
4025 static HARD_REG_SET reload_reg_used_for_inherit;
4027 /* Records which hard regs are used in any way, either as explicit use or
4028 by being allocated to a pseudo during any point of the current insn. */
4029 static HARD_REG_SET reg_used_in_insn;
4031 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4032 TYPE. MODE is used to indicate how many consecutive regs are
4036 mark_reload_reg_in_use (regno, opnum, type, mode)
4039 enum reload_type type;
4040 enum machine_mode mode;
4042 int nregs = HARD_REGNO_NREGS (regno, mode);
4045 for (i = regno; i < nregs + regno; i++)
4050 SET_HARD_REG_BIT (reload_reg_used, i);
4053 case RELOAD_FOR_INPUT_ADDRESS:
4054 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4057 case RELOAD_FOR_INPADDR_ADDRESS:
4058 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4061 case RELOAD_FOR_OUTPUT_ADDRESS:
4062 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4065 case RELOAD_FOR_OUTADDR_ADDRESS:
4066 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4069 case RELOAD_FOR_OPERAND_ADDRESS:
4070 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4073 case RELOAD_FOR_OPADDR_ADDR:
4074 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4077 case RELOAD_FOR_OTHER_ADDRESS:
4078 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4081 case RELOAD_FOR_INPUT:
4082 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4085 case RELOAD_FOR_OUTPUT:
4086 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4089 case RELOAD_FOR_INSN:
4090 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4094 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4098 /* Similarly, but show REGNO is no longer in use for a reload. */
4101 clear_reload_reg_in_use (regno, opnum, type, mode)
4104 enum reload_type type;
4105 enum machine_mode mode;
4107 int nregs = HARD_REGNO_NREGS (regno, mode);
4108 int start_regno, end_regno;
4110 /* A complication is that for some reload types, inheritance might
4111 allow multiple reloads of the same types to share a reload register.
4112 We set check_opnum if we have to check only reloads with the same
4113 operand number, and check_any if we have to check all reloads. */
4114 int check_opnum = 0;
4116 HARD_REG_SET *used_in_set;
4121 used_in_set = &reload_reg_used;
4124 case RELOAD_FOR_INPUT_ADDRESS:
4125 used_in_set = &reload_reg_used_in_input_addr[opnum];
4128 case RELOAD_FOR_INPADDR_ADDRESS:
4130 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4133 case RELOAD_FOR_OUTPUT_ADDRESS:
4134 used_in_set = &reload_reg_used_in_output_addr[opnum];
4137 case RELOAD_FOR_OUTADDR_ADDRESS:
4139 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4142 case RELOAD_FOR_OPERAND_ADDRESS:
4143 used_in_set = &reload_reg_used_in_op_addr;
4146 case RELOAD_FOR_OPADDR_ADDR:
4148 used_in_set = &reload_reg_used_in_op_addr_reload;
4151 case RELOAD_FOR_OTHER_ADDRESS:
4152 used_in_set = &reload_reg_used_in_other_addr;
4156 case RELOAD_FOR_INPUT:
4157 used_in_set = &reload_reg_used_in_input[opnum];
4160 case RELOAD_FOR_OUTPUT:
4161 used_in_set = &reload_reg_used_in_output[opnum];
4164 case RELOAD_FOR_INSN:
4165 used_in_set = &reload_reg_used_in_insn;
4170 /* We resolve conflicts with remaining reloads of the same type by
4171 excluding the intervals of of reload registers by them from the
4172 interval of freed reload registers. Since we only keep track of
4173 one set of interval bounds, we might have to exclude somewhat
4174 more then what would be necessary if we used a HARD_REG_SET here.
4175 But this should only happen very infrequently, so there should
4176 be no reason to worry about it. */
4178 start_regno = regno;
4179 end_regno = regno + nregs;
4180 if (check_opnum || check_any)
4182 for (i = n_reloads - 1; i >= 0; i--)
4184 if (rld[i].when_needed == type
4185 && (check_any || rld[i].opnum == opnum)
4188 int conflict_start = true_regnum (rld[i].reg_rtx);
4191 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4193 /* If there is an overlap with the first to-be-freed register,
4194 adjust the interval start. */
4195 if (conflict_start <= start_regno && conflict_end > start_regno)
4196 start_regno = conflict_end;
4197 /* Otherwise, if there is a conflict with one of the other
4198 to-be-freed registers, adjust the interval end. */
4199 if (conflict_start > start_regno && conflict_start < end_regno)
4200 end_regno = conflict_start;
4204 for (i = start_regno; i < end_regno; i++)
4205 CLEAR_HARD_REG_BIT (*used_in_set, i);
4208 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4209 specified by OPNUM and TYPE. */
4212 reload_reg_free_p (regno, opnum, type)
4215 enum reload_type type;
4219 /* In use for a RELOAD_OTHER means it's not available for anything. */
4220 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4221 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4227 /* In use for anything means we can't use it for RELOAD_OTHER. */
4228 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4229 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4230 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4233 for (i = 0; i < reload_n_operands; i++)
4234 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4235 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4236 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4237 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4238 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4239 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4244 case RELOAD_FOR_INPUT:
4245 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4246 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4249 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4252 /* If it is used for some other input, can't use it. */
4253 for (i = 0; i < reload_n_operands; i++)
4254 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4257 /* If it is used in a later operand's address, can't use it. */
4258 for (i = opnum + 1; i < reload_n_operands; i++)
4259 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4260 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4265 case RELOAD_FOR_INPUT_ADDRESS:
4266 /* Can't use a register if it is used for an input address for this
4267 operand or used as an input in an earlier one. */
4268 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4269 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4272 for (i = 0; i < opnum; i++)
4273 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4278 case RELOAD_FOR_INPADDR_ADDRESS:
4279 /* Can't use a register if it is used for an input address
4280 for this operand or used as an input in an earlier
4282 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4285 for (i = 0; i < opnum; i++)
4286 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4291 case RELOAD_FOR_OUTPUT_ADDRESS:
4292 /* Can't use a register if it is used for an output address for this
4293 operand or used as an output in this or a later operand. */
4294 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4297 for (i = opnum; i < reload_n_operands; i++)
4298 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4303 case RELOAD_FOR_OUTADDR_ADDRESS:
4304 /* Can't use a register if it is used for an output address
4305 for this operand or used as an output in this or a
4307 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4310 for (i = opnum; i < reload_n_operands; i++)
4311 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4316 case RELOAD_FOR_OPERAND_ADDRESS:
4317 for (i = 0; i < reload_n_operands; i++)
4318 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4321 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4322 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4324 case RELOAD_FOR_OPADDR_ADDR:
4325 for (i = 0; i < reload_n_operands; i++)
4326 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4329 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4331 case RELOAD_FOR_OUTPUT:
4332 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4333 outputs, or an operand address for this or an earlier output. */
4334 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4337 for (i = 0; i < reload_n_operands; i++)
4338 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4341 for (i = 0; i <= opnum; i++)
4342 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4343 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4348 case RELOAD_FOR_INSN:
4349 for (i = 0; i < reload_n_operands; i++)
4350 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4351 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4354 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4355 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4357 case RELOAD_FOR_OTHER_ADDRESS:
4358 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4363 /* Return 1 if the value in reload reg REGNO, as used by a reload
4364 needed for the part of the insn specified by OPNUM and TYPE,
4365 is still available in REGNO at the end of the insn.
4367 We can assume that the reload reg was already tested for availability
4368 at the time it is needed, and we should not check this again,
4369 in case the reg has already been marked in use. */
4372 reload_reg_reaches_end_p (regno, opnum, type)
4375 enum reload_type type;
4382 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4383 its value must reach the end. */
4386 /* If this use is for part of the insn,
4387 its value reaches if no subsequent part uses the same register.
4388 Just like the above function, don't try to do this with lots
4391 case RELOAD_FOR_OTHER_ADDRESS:
4392 /* Here we check for everything else, since these don't conflict
4393 with anything else and everything comes later. */
4395 for (i = 0; i < reload_n_operands; i++)
4396 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4397 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4398 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4399 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4400 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4401 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4404 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4405 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4406 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4408 case RELOAD_FOR_INPUT_ADDRESS:
4409 case RELOAD_FOR_INPADDR_ADDRESS:
4410 /* Similar, except that we check only for this and subsequent inputs
4411 and the address of only subsequent inputs and we do not need
4412 to check for RELOAD_OTHER objects since they are known not to
4415 for (i = opnum; i < reload_n_operands; i++)
4416 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4419 for (i = opnum + 1; i < reload_n_operands; i++)
4420 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4421 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4424 for (i = 0; i < reload_n_operands; i++)
4425 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4426 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4427 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4430 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4433 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4434 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4436 case RELOAD_FOR_INPUT:
4437 /* Similar to input address, except we start at the next operand for
4438 both input and input address and we do not check for
4439 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4442 for (i = opnum + 1; i < reload_n_operands; i++)
4443 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4444 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4445 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4448 /* ... fall through ... */
4450 case RELOAD_FOR_OPERAND_ADDRESS:
4451 /* Check outputs and their addresses. */
4453 for (i = 0; i < reload_n_operands; i++)
4454 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4455 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4456 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4461 case RELOAD_FOR_OPADDR_ADDR:
4462 for (i = 0; i < reload_n_operands; i++)
4463 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4464 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4465 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4468 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4469 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4471 case RELOAD_FOR_INSN:
4472 /* These conflict with other outputs with RELOAD_OTHER. So
4473 we need only check for output addresses. */
4477 /* ... fall through ... */
4479 case RELOAD_FOR_OUTPUT:
4480 case RELOAD_FOR_OUTPUT_ADDRESS:
4481 case RELOAD_FOR_OUTADDR_ADDRESS:
4482 /* We already know these can't conflict with a later output. So the
4483 only thing to check are later output addresses. */
4484 for (i = opnum + 1; i < reload_n_operands; i++)
4485 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4486 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4495 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4498 This function uses the same algorithm as reload_reg_free_p above. */
4501 reloads_conflict (r1, r2)
4504 enum reload_type r1_type = rld[r1].when_needed;
4505 enum reload_type r2_type = rld[r2].when_needed;
4506 int r1_opnum = rld[r1].opnum;
4507 int r2_opnum = rld[r2].opnum;
4509 /* RELOAD_OTHER conflicts with everything. */
4510 if (r2_type == RELOAD_OTHER)
4513 /* Otherwise, check conflicts differently for each type. */
4517 case RELOAD_FOR_INPUT:
4518 return (r2_type == RELOAD_FOR_INSN
4519 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4520 || r2_type == RELOAD_FOR_OPADDR_ADDR
4521 || r2_type == RELOAD_FOR_INPUT
4522 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4523 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4524 && r2_opnum > r1_opnum));
4526 case RELOAD_FOR_INPUT_ADDRESS:
4527 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4528 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4530 case RELOAD_FOR_INPADDR_ADDRESS:
4531 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4532 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4534 case RELOAD_FOR_OUTPUT_ADDRESS:
4535 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4536 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4538 case RELOAD_FOR_OUTADDR_ADDRESS:
4539 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4540 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4542 case RELOAD_FOR_OPERAND_ADDRESS:
4543 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4544 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4546 case RELOAD_FOR_OPADDR_ADDR:
4547 return (r2_type == RELOAD_FOR_INPUT
4548 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4550 case RELOAD_FOR_OUTPUT:
4551 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4552 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4553 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4554 && r2_opnum <= r1_opnum));
4556 case RELOAD_FOR_INSN:
4557 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4558 || r2_type == RELOAD_FOR_INSN
4559 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4561 case RELOAD_FOR_OTHER_ADDRESS:
4562 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4572 /* Indexed by reload number, 1 if incoming value
4573 inherited from previous insns. */
4574 char reload_inherited[MAX_RELOADS];
4576 /* For an inherited reload, this is the insn the reload was inherited from,
4577 if we know it. Otherwise, this is 0. */
4578 rtx reload_inheritance_insn[MAX_RELOADS];
4580 /* If non-zero, this is a place to get the value of the reload,
4581 rather than using reload_in. */
4582 rtx reload_override_in[MAX_RELOADS];
4584 /* For each reload, the hard register number of the register used,
4585 or -1 if we did not need a register for this reload. */
4586 int reload_spill_index[MAX_RELOADS];
4588 /* Return 1 if the value in reload reg REGNO, as used by a reload
4589 needed for the part of the insn specified by OPNUM and TYPE,
4590 may be used to load VALUE into it.
4592 Other read-only reloads with the same value do not conflict
4593 unless OUT is non-zero and these other reloads have to live while
4594 output reloads live.
4595 If OUT is CONST0_RTX, this is a special case: it means that the
4596 test should not be for using register REGNO as reload register, but
4597 for copying from register REGNO into the reload register.
4599 RELOADNUM is the number of the reload we want to load this value for;
4600 a reload does not conflict with itself.
4602 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4603 reloads that load an address for the very reload we are considering.
4605 The caller has to make sure that there is no conflict with the return
4608 reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum,
4609 ignore_address_reloads)
4612 enum reload_type type;
4615 int ignore_address_reloads;
4618 /* Set if we see an input reload that must not share its reload register
4619 with any new earlyclobber, but might otherwise share the reload
4620 register with an output or input-output reload. */
4621 int check_earlyclobber = 0;
4625 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4628 if (out == const0_rtx)
4634 /* We use some pseudo 'time' value to check if the lifetimes of the
4635 new register use would overlap with the one of a previous reload
4636 that is not read-only or uses a different value.
4637 The 'time' used doesn't have to be linear in any shape or form, just
4639 Some reload types use different 'buckets' for each operand.
4640 So there are MAX_RECOG_OPERANDS different time values for each
4642 We compute TIME1 as the time when the register for the prospective
4643 new reload ceases to be live, and TIME2 for each existing
4644 reload as the time when that the reload register of that reload
4646 Where there is little to be gained by exact lifetime calculations,
4647 we just make conservative assumptions, i.e. a longer lifetime;
4648 this is done in the 'default:' cases. */
4651 case RELOAD_FOR_OTHER_ADDRESS:
4652 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4653 time1 = copy ? 0 : 1;
4656 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4658 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4659 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4660 respectively, to the time values for these, we get distinct time
4661 values. To get distinct time values for each operand, we have to
4662 multiply opnum by at least three. We round that up to four because
4663 multiply by four is often cheaper. */
4664 case RELOAD_FOR_INPADDR_ADDRESS:
4665 time1 = opnum * 4 + 2;
4667 case RELOAD_FOR_INPUT_ADDRESS:
4668 time1 = opnum * 4 + 3;
4670 case RELOAD_FOR_INPUT:
4671 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4672 executes (inclusive). */
4673 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4675 case RELOAD_FOR_OPADDR_ADDR:
4677 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4678 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4680 case RELOAD_FOR_OPERAND_ADDRESS:
4681 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4683 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4685 case RELOAD_FOR_OUTADDR_ADDRESS:
4686 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4688 case RELOAD_FOR_OUTPUT_ADDRESS:
4689 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4692 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4695 for (i = 0; i < n_reloads; i++)
4697 rtx reg = rld[i].reg_rtx;
4698 if (reg && GET_CODE (reg) == REG
4699 && ((unsigned) regno - true_regnum (reg)
4700 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
4703 if (! rld[i].in || ! rtx_equal_p (rld[i].in, value)
4704 || rld[i].out || out)
4707 switch (rld[i].when_needed)
4709 case RELOAD_FOR_OTHER_ADDRESS:
4712 case RELOAD_FOR_INPADDR_ADDRESS:
4713 /* find_reloads makes sure that a
4714 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4715 by at most one - the first -
4716 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4717 address reload is inherited, the address address reload
4718 goes away, so we can ignore this conflict. */
4719 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4720 && ignore_address_reloads
4721 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4722 Then the address address is still needed to store
4723 back the new address. */
4724 && ! rld[reloadnum].out)
4726 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4727 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4729 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4730 && ignore_address_reloads
4731 /* Unless we are reloading an auto_inc expression. */
4732 && ! rld[reloadnum].out)
4734 time2 = rld[i].opnum * 4 + 2;
4736 case RELOAD_FOR_INPUT_ADDRESS:
4737 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4738 && ignore_address_reloads
4739 && ! rld[reloadnum].out)
4741 time2 = rld[i].opnum * 4 + 3;
4743 case RELOAD_FOR_INPUT:
4744 time2 = rld[i].opnum * 4 + 4;
4745 check_earlyclobber = 1;
4747 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4748 == MAX_RECOG_OPERAND * 4 */
4749 case RELOAD_FOR_OPADDR_ADDR:
4750 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4751 && ignore_address_reloads
4752 && ! rld[reloadnum].out)
4754 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4756 case RELOAD_FOR_OPERAND_ADDRESS:
4757 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4758 check_earlyclobber = 1;
4760 case RELOAD_FOR_INSN:
4761 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4763 case RELOAD_FOR_OUTPUT:
4764 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4765 instruction is executed. */
4766 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4768 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4769 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4771 case RELOAD_FOR_OUTADDR_ADDRESS:
4772 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4773 && ignore_address_reloads
4774 && ! rld[reloadnum].out)
4776 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4778 case RELOAD_FOR_OUTPUT_ADDRESS:
4779 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4782 /* If there is no conflict in the input part, handle this
4783 like an output reload. */
4784 if (! rld[i].in || rtx_equal_p (rld[i].in, value))
4786 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4787 /* Earlyclobbered outputs must conflict with inputs. */
4788 if (earlyclobber_operand_p (rld[i].out))
4789 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4794 /* RELOAD_OTHER might be live beyond instruction execution,
4795 but this is not obvious when we set time2 = 1. So check
4796 here if there might be a problem with the new reload
4797 clobbering the register used by the RELOAD_OTHER. */
4805 && (! rld[i].in || rld[i].out
4806 || ! rtx_equal_p (rld[i].in, value)))
4807 || (out && rld[reloadnum].out_reg
4808 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4814 /* Earlyclobbered outputs must conflict with inputs. */
4815 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4821 /* Give an error message saying we failed to find a reload for INSN,
4822 and clear out reload R. */
4824 failed_reload (insn, r)
4828 if (asm_noperands (PATTERN (insn)) < 0)
4829 /* It's the compiler's fault. */
4830 fatal_insn ("Could not find a spill register", insn);
4832 /* It's the user's fault; the operand's mode and constraint
4833 don't match. Disable this reload so we don't crash in final. */
4834 error_for_asm (insn,
4835 "`asm' operand constraint incompatible with operand size");
4839 rld[r].optional = 1;
4840 rld[r].secondary_p = 1;
4843 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
4844 for reload R. If it's valid, get an rtx for it. Return nonzero if
4847 set_reload_reg (i, r)
4851 rtx reg = spill_reg_rtx[i];
4853 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
4854 spill_reg_rtx[i] = reg
4855 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
4857 regno = true_regnum (reg);
4859 /* Detect when the reload reg can't hold the reload mode.
4860 This used to be one `if', but Sequent compiler can't handle that. */
4861 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
4863 enum machine_mode test_mode = VOIDmode;
4865 test_mode = GET_MODE (rld[r].in);
4866 /* If rld[r].in has VOIDmode, it means we will load it
4867 in whatever mode the reload reg has: to wit, rld[r].mode.
4868 We have already tested that for validity. */
4869 /* Aside from that, we need to test that the expressions
4870 to reload from or into have modes which are valid for this
4871 reload register. Otherwise the reload insns would be invalid. */
4872 if (! (rld[r].in != 0 && test_mode != VOIDmode
4873 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
4874 if (! (rld[r].out != 0
4875 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
4877 /* The reg is OK. */
4880 /* Mark as in use for this insn the reload regs we use
4882 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
4883 rld[r].when_needed, rld[r].mode);
4885 rld[r].reg_rtx = reg;
4886 reload_spill_index[r] = spill_regs[i];
4893 /* Find a spill register to use as a reload register for reload R.
4894 LAST_RELOAD is non-zero if this is the last reload for the insn being
4897 Set rld[R].reg_rtx to the register allocated.
4899 We return 1 if successful, or 0 if we couldn't find a spill reg and
4900 we didn't change anything. */
4903 allocate_reload_reg (chain, r, last_reload)
4904 struct insn_chain *chain ATTRIBUTE_UNUSED;
4910 /* If we put this reload ahead, thinking it is a group,
4911 then insist on finding a group. Otherwise we can grab a
4912 reg that some other reload needs.
4913 (That can happen when we have a 68000 DATA_OR_FP_REG
4914 which is a group of data regs or one fp reg.)
4915 We need not be so restrictive if there are no more reloads
4918 ??? Really it would be nicer to have smarter handling
4919 for that kind of reg class, where a problem like this is normal.
4920 Perhaps those classes should be avoided for reloading
4921 by use of more alternatives. */
4923 int force_group = rld[r].nregs > 1 && ! last_reload;
4925 /* If we want a single register and haven't yet found one,
4926 take any reg in the right class and not in use.
4927 If we want a consecutive group, here is where we look for it.
4929 We use two passes so we can first look for reload regs to
4930 reuse, which are already in use for other reloads in this insn,
4931 and only then use additional registers.
4932 I think that maximizing reuse is needed to make sure we don't
4933 run out of reload regs. Suppose we have three reloads, and
4934 reloads A and B can share regs. These need two regs.
4935 Suppose A and B are given different regs.
4936 That leaves none for C. */
4937 for (pass = 0; pass < 2; pass++)
4939 /* I is the index in spill_regs.
4940 We advance it round-robin between insns to use all spill regs
4941 equally, so that inherited reloads have a chance
4942 of leapfrogging each other. */
4946 for (count = 0; count < n_spills; count++)
4948 int class = (int) rld[r].class;
4954 regnum = spill_regs[i];
4956 if ((reload_reg_free_p (regnum, rld[r].opnum,
4959 /* We check reload_reg_used to make sure we
4960 don't clobber the return register. */
4961 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
4962 && reload_reg_free_for_value_p (regnum,
4967 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
4968 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
4969 /* Look first for regs to share, then for unshared. But
4970 don't share regs used for inherited reloads; they are
4971 the ones we want to preserve. */
4973 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
4975 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
4978 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
4979 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
4980 (on 68000) got us two FP regs. If NR is 1,
4981 we would reject both of them. */
4984 /* If we need only one reg, we have already won. */
4987 /* But reject a single reg if we demand a group. */
4992 /* Otherwise check that as many consecutive regs as we need
4993 are available here. */
4996 int regno = regnum + nr - 1;
4997 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
4998 && spill_reg_order[regno] >= 0
4999 && reload_reg_free_p (regno, rld[r].opnum,
5000 rld[r].when_needed)))
5009 /* If we found something on pass 1, omit pass 2. */
5010 if (count < n_spills)
5014 /* We should have found a spill register by now. */
5015 if (count >= n_spills)
5018 /* I is the index in SPILL_REG_RTX of the reload register we are to
5019 allocate. Get an rtx for it and find its register number. */
5021 return set_reload_reg (i, r);
5024 /* Initialize all the tables needed to allocate reload registers.
5025 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5026 is the array we use to restore the reg_rtx field for every reload. */
5028 choose_reload_regs_init (chain, save_reload_reg_rtx)
5029 struct insn_chain *chain;
5030 rtx *save_reload_reg_rtx;
5034 for (i = 0; i < n_reloads; i++)
5035 rld[i].reg_rtx = save_reload_reg_rtx[i];
5037 bzero (reload_inherited, MAX_RELOADS);
5038 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5039 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5041 CLEAR_HARD_REG_SET (reload_reg_used);
5042 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5043 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5044 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5045 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5046 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5048 CLEAR_HARD_REG_SET (reg_used_in_insn);
5051 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5052 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5053 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5054 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5055 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5056 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5058 for (i = 0; i < reload_n_operands; i++)
5060 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5061 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5062 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5063 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5064 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5065 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5068 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5070 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5072 for (i = 0; i < n_reloads; i++)
5073 /* If we have already decided to use a certain register,
5074 don't use it in another way. */
5076 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5077 rld[i].when_needed, rld[i].mode);
5080 /* Assign hard reg targets for the pseudo-registers we must reload
5081 into hard regs for this insn.
5082 Also output the instructions to copy them in and out of the hard regs.
5084 For machines with register classes, we are responsible for
5085 finding a reload reg in the proper class. */
5088 choose_reload_regs (chain)
5089 struct insn_chain *chain;
5091 rtx insn = chain->insn;
5093 int max_group_size = 1;
5094 enum reg_class group_class = NO_REGS;
5095 int pass, win, inheritance;
5097 rtx save_reload_reg_rtx[MAX_RELOADS];
5099 /* In order to be certain of getting the registers we need,
5100 we must sort the reloads into order of increasing register class.
5101 Then our grabbing of reload registers will parallel the process
5102 that provided the reload registers.
5104 Also note whether any of the reloads wants a consecutive group of regs.
5105 If so, record the maximum size of the group desired and what
5106 register class contains all the groups needed by this insn. */
5108 for (j = 0; j < n_reloads; j++)
5110 reload_order[j] = j;
5111 reload_spill_index[j] = -1;
5113 if (rld[j].nregs > 1)
5115 max_group_size = MAX (rld[j].nregs, max_group_size);
5116 group_class = reg_class_superunion[(int)rld[j].class][(int)group_class];
5119 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5123 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5125 /* If -O, try first with inheritance, then turning it off.
5126 If not -O, don't do inheritance.
5127 Using inheritance when not optimizing leads to paradoxes
5128 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5129 because one side of the comparison might be inherited. */
5131 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5133 choose_reload_regs_init (chain, save_reload_reg_rtx);
5135 /* Process the reloads in order of preference just found.
5136 Beyond this point, subregs can be found in reload_reg_rtx.
5138 This used to look for an existing reloaded home for all
5139 of the reloads, and only then perform any new reloads.
5140 But that could lose if the reloads were done out of reg-class order
5141 because a later reload with a looser constraint might have an old
5142 home in a register needed by an earlier reload with a tighter constraint.
5144 To solve this, we make two passes over the reloads, in the order
5145 described above. In the first pass we try to inherit a reload
5146 from a previous insn. If there is a later reload that needs a
5147 class that is a proper subset of the class being processed, we must
5148 also allocate a spill register during the first pass.
5150 Then make a second pass over the reloads to allocate any reloads
5151 that haven't been given registers yet. */
5153 for (j = 0; j < n_reloads; j++)
5155 register int r = reload_order[j];
5156 rtx search_equiv = NULL_RTX;
5158 /* Ignore reloads that got marked inoperative. */
5159 if (rld[r].out == 0 && rld[r].in == 0
5160 && ! rld[r].secondary_p)
5163 /* If find_reloads chose to use reload_in or reload_out as a reload
5164 register, we don't need to chose one. Otherwise, try even if it
5165 found one since we might save an insn if we find the value lying
5167 Try also when reload_in is a pseudo without a hard reg. */
5168 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5169 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5170 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5171 && GET_CODE (rld[r].in) != MEM
5172 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5175 #if 0 /* No longer needed for correct operation.
5176 It might give better code, or might not; worth an experiment? */
5177 /* If this is an optional reload, we can't inherit from earlier insns
5178 until we are sure that any non-optional reloads have been allocated.
5179 The following code takes advantage of the fact that optional reloads
5180 are at the end of reload_order. */
5181 if (rld[r].optional != 0)
5182 for (i = 0; i < j; i++)
5183 if ((rld[reload_order[i]].out != 0
5184 || rld[reload_order[i]].in != 0
5185 || rld[reload_order[i]].secondary_p)
5186 && ! rld[reload_order[i]].optional
5187 && rld[reload_order[i]].reg_rtx == 0)
5188 allocate_reload_reg (chain, reload_order[i], 0);
5191 /* First see if this pseudo is already available as reloaded
5192 for a previous insn. We cannot try to inherit for reloads
5193 that are smaller than the maximum number of registers needed
5194 for groups unless the register we would allocate cannot be used
5197 We could check here to see if this is a secondary reload for
5198 an object that is already in a register of the desired class.
5199 This would avoid the need for the secondary reload register.
5200 But this is complex because we can't easily determine what
5201 objects might want to be loaded via this reload. So let a
5202 register be allocated here. In `emit_reload_insns' we suppress
5203 one of the loads in the case described above. */
5208 register int regno = -1;
5209 enum machine_mode mode = VOIDmode;
5213 else if (GET_CODE (rld[r].in) == REG)
5215 regno = REGNO (rld[r].in);
5216 mode = GET_MODE (rld[r].in);
5218 else if (GET_CODE (rld[r].in_reg) == REG)
5220 regno = REGNO (rld[r].in_reg);
5221 mode = GET_MODE (rld[r].in_reg);
5223 else if (GET_CODE (rld[r].in_reg) == SUBREG
5224 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5226 word = SUBREG_WORD (rld[r].in_reg);
5227 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5228 if (regno < FIRST_PSEUDO_REGISTER)
5230 mode = GET_MODE (rld[r].in_reg);
5233 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5234 || GET_CODE (rld[r].in_reg) == PRE_DEC
5235 || GET_CODE (rld[r].in_reg) == POST_INC
5236 || GET_CODE (rld[r].in_reg) == POST_DEC)
5237 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5239 regno = REGNO (XEXP (rld[r].in_reg, 0));
5240 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5241 rld[r].out = rld[r].in;
5245 /* This won't work, since REGNO can be a pseudo reg number.
5246 Also, it takes much more hair to keep track of all the things
5247 that can invalidate an inherited reload of part of a pseudoreg. */
5248 else if (GET_CODE (rld[r].in) == SUBREG
5249 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5250 regno = REGNO (SUBREG_REG (rld[r].in)) + SUBREG_WORD (rld[r].in);
5253 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5255 enum reg_class class = rld[r].class, last_class;
5256 rtx last_reg = reg_last_reload_reg[regno];
5258 i = REGNO (last_reg) + word;
5259 last_class = REGNO_REG_CLASS (i);
5260 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5261 >= GET_MODE_SIZE (mode) + word * UNITS_PER_WORD)
5262 && reg_reloaded_contents[i] == regno
5263 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5264 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5265 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5266 /* Even if we can't use this register as a reload
5267 register, we might use it for reload_override_in,
5268 if copying it to the desired class is cheap
5270 || ((REGISTER_MOVE_COST (last_class, class)
5271 < MEMORY_MOVE_COST (mode, class, 1))
5272 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5273 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5277 #ifdef SECONDARY_MEMORY_NEEDED
5278 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5283 && (rld[r].nregs == max_group_size
5284 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5286 && reload_reg_free_for_value_p (i, rld[r].opnum,
5291 /* If a group is needed, verify that all the subsequent
5292 registers still have their values intact. */
5294 = HARD_REGNO_NREGS (i, rld[r].mode);
5297 for (k = 1; k < nr; k++)
5298 if (reg_reloaded_contents[i + k] != regno
5299 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5306 last_reg = (GET_MODE (last_reg) == mode
5307 ? last_reg : gen_rtx_REG (mode, i));
5309 /* We found a register that contains the
5310 value we need. If this register is the
5311 same as an `earlyclobber' operand of the
5312 current insn, just mark it as a place to
5313 reload from since we can't use it as the
5314 reload register itself. */
5316 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5317 if (reg_overlap_mentioned_for_reload_p
5318 (reg_last_reload_reg[regno],
5319 reload_earlyclobbers[i1]))
5322 if (i1 != n_earlyclobbers
5323 || ! (reload_reg_free_for_value_p
5324 (i, rld[r].opnum, rld[r].when_needed,
5325 rld[r].in, rld[r].out, r, 1))
5326 /* Don't use it if we'd clobber a pseudo reg. */
5327 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5329 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5330 /* Don't clobber the frame pointer. */
5331 || (i == HARD_FRAME_POINTER_REGNUM && rld[r].out)
5332 /* Don't really use the inherited spill reg
5333 if we need it wider than we've got it. */
5334 || (GET_MODE_SIZE (rld[r].mode)
5335 > GET_MODE_SIZE (mode))
5336 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5339 /* If find_reloads chose reload_out as reload
5340 register, stay with it - that leaves the
5341 inherited register for subsequent reloads. */
5342 || (rld[r].out && rld[r].reg_rtx
5343 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5345 reload_override_in[r] = last_reg;
5346 reload_inheritance_insn[r]
5347 = reg_reloaded_insn[i];
5352 /* We can use this as a reload reg. */
5353 /* Mark the register as in use for this part of
5355 mark_reload_reg_in_use (i,
5359 rld[r].reg_rtx = last_reg;
5360 reload_inherited[r] = 1;
5361 reload_inheritance_insn[r]
5362 = reg_reloaded_insn[i];
5363 reload_spill_index[r] = i;
5364 for (k = 0; k < nr; k++)
5365 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5373 /* Here's another way to see if the value is already lying around. */
5376 && ! reload_inherited[r]
5378 && (CONSTANT_P (rld[r].in)
5379 || GET_CODE (rld[r].in) == PLUS
5380 || GET_CODE (rld[r].in) == REG
5381 || GET_CODE (rld[r].in) == MEM)
5382 && (rld[r].nregs == max_group_size
5383 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5384 search_equiv = rld[r].in;
5385 /* If this is an output reload from a simple move insn, look
5386 if an equivalence for the input is available. */
5387 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5389 rtx set = single_set (insn);
5392 && rtx_equal_p (rld[r].out, SET_DEST (set))
5393 && CONSTANT_P (SET_SRC (set)))
5394 search_equiv = SET_SRC (set);
5400 = find_equiv_reg (search_equiv, insn, rld[r].class,
5401 -1, NULL_PTR, 0, rld[r].mode);
5406 if (GET_CODE (equiv) == REG)
5407 regno = REGNO (equiv);
5408 else if (GET_CODE (equiv) == SUBREG)
5410 /* This must be a SUBREG of a hard register.
5411 Make a new REG since this might be used in an
5412 address and not all machines support SUBREGs
5414 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5415 equiv = gen_rtx_REG (rld[r].mode, regno);
5421 /* If we found a spill reg, reject it unless it is free
5422 and of the desired class. */
5424 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5425 && ! reload_reg_free_for_value_p (regno, rld[r].opnum,
5429 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5433 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5436 /* We found a register that contains the value we need.
5437 If this register is the same as an `earlyclobber' operand
5438 of the current insn, just mark it as a place to reload from
5439 since we can't use it as the reload register itself. */
5442 for (i = 0; i < n_earlyclobbers; i++)
5443 if (reg_overlap_mentioned_for_reload_p (equiv,
5444 reload_earlyclobbers[i]))
5446 reload_override_in[r] = equiv;
5451 /* If the equiv register we have found is explicitly clobbered
5452 in the current insn, it depends on the reload type if we
5453 can use it, use it for reload_override_in, or not at all.
5454 In particular, we then can't use EQUIV for a
5455 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5457 if (equiv != 0 && regno_clobbered_p (regno, insn))
5459 switch (rld[r].when_needed)
5461 case RELOAD_FOR_OTHER_ADDRESS:
5462 case RELOAD_FOR_INPADDR_ADDRESS:
5463 case RELOAD_FOR_INPUT_ADDRESS:
5464 case RELOAD_FOR_OPADDR_ADDR:
5467 case RELOAD_FOR_INPUT:
5468 case RELOAD_FOR_OPERAND_ADDRESS:
5469 reload_override_in[r] = equiv;
5477 /* If we found an equivalent reg, say no code need be generated
5478 to load it, and use it as our reload reg. */
5479 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5481 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5483 rld[r].reg_rtx = equiv;
5484 reload_inherited[r] = 1;
5486 /* If reg_reloaded_valid is not set for this register,
5487 there might be a stale spill_reg_store lying around.
5488 We must clear it, since otherwise emit_reload_insns
5489 might delete the store. */
5490 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5491 spill_reg_store[regno] = NULL_RTX;
5492 /* If any of the hard registers in EQUIV are spill
5493 registers, mark them as in use for this insn. */
5494 for (k = 0; k < nr; k++)
5496 i = spill_reg_order[regno + k];
5499 mark_reload_reg_in_use (regno, rld[r].opnum,
5502 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5509 /* If we found a register to use already, or if this is an optional
5510 reload, we are done. */
5511 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5514 #if 0 /* No longer needed for correct operation. Might or might not
5515 give better code on the average. Want to experiment? */
5517 /* See if there is a later reload that has a class different from our
5518 class that intersects our class or that requires less register
5519 than our reload. If so, we must allocate a register to this
5520 reload now, since that reload might inherit a previous reload
5521 and take the only available register in our class. Don't do this
5522 for optional reloads since they will force all previous reloads
5523 to be allocated. Also don't do this for reloads that have been
5526 for (i = j + 1; i < n_reloads; i++)
5528 int s = reload_order[i];
5530 if ((rld[s].in == 0 && rld[s].out == 0
5531 && ! rld[s].secondary_p)
5535 if ((rld[s].class != rld[r].class
5536 && reg_classes_intersect_p (rld[r].class,
5538 || rld[s].nregs < rld[r].nregs)
5545 allocate_reload_reg (chain, r, j == n_reloads - 1);
5549 /* Now allocate reload registers for anything non-optional that
5550 didn't get one yet. */
5551 for (j = 0; j < n_reloads; j++)
5553 register int r = reload_order[j];
5555 /* Ignore reloads that got marked inoperative. */
5556 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5559 /* Skip reloads that already have a register allocated or are
5561 if (rld[r].reg_rtx != 0 || rld[r].optional)
5564 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5568 /* If that loop got all the way, we have won. */
5575 /* Loop around and try without any inheritance. */
5580 /* First undo everything done by the failed attempt
5581 to allocate with inheritance. */
5582 choose_reload_regs_init (chain, save_reload_reg_rtx);
5584 /* Some sanity tests to verify that the reloads found in the first
5585 pass are identical to the ones we have now. */
5586 if (chain->n_reloads != n_reloads)
5589 for (i = 0; i < n_reloads; i++)
5591 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5593 if (chain->rld[i].when_needed != rld[i].when_needed)
5595 for (j = 0; j < n_spills; j++)
5596 if (spill_regs[j] == chain->rld[i].regno)
5597 if (! set_reload_reg (j, i))
5598 failed_reload (chain->insn, i);
5602 /* If we thought we could inherit a reload, because it seemed that
5603 nothing else wanted the same reload register earlier in the insn,
5604 verify that assumption, now that all reloads have been assigned.
5605 Likewise for reloads where reload_override_in has been set. */
5607 /* If doing expensive optimizations, do one preliminary pass that doesn't
5608 cancel any inheritance, but removes reloads that have been needed only
5609 for reloads that we know can be inherited. */
5610 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5612 for (j = 0; j < n_reloads; j++)
5614 register int r = reload_order[j];
5616 if (reload_inherited[r] && rld[r].reg_rtx)
5617 check_reg = rld[r].reg_rtx;
5618 else if (reload_override_in[r]
5619 && (GET_CODE (reload_override_in[r]) == REG
5620 || GET_CODE (reload_override_in[r]) == SUBREG))
5621 check_reg = reload_override_in[r];
5624 if (! reload_reg_free_for_value_p (true_regnum (check_reg),
5628 (reload_inherited[r]
5629 ? rld[r].out : const0_rtx),
5634 reload_inherited[r] = 0;
5635 reload_override_in[r] = 0;
5637 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5638 reload_override_in, then we do not need its related
5639 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5640 likewise for other reload types.
5641 We handle this by removing a reload when its only replacement
5642 is mentioned in reload_in of the reload we are going to inherit.
5643 A special case are auto_inc expressions; even if the input is
5644 inherited, we still need the address for the output. We can
5645 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5646 If we suceeded removing some reload and we are doing a preliminary
5647 pass just to remove such reloads, make another pass, since the
5648 removal of one reload might allow us to inherit another one. */
5650 && rld[r].out != rld[r].in
5651 && remove_address_replacements (rld[r].in) && pass)
5656 /* Now that reload_override_in is known valid,
5657 actually override reload_in. */
5658 for (j = 0; j < n_reloads; j++)
5659 if (reload_override_in[j])
5660 rld[j].in = reload_override_in[j];
5662 /* If this reload won't be done because it has been cancelled or is
5663 optional and not inherited, clear reload_reg_rtx so other
5664 routines (such as subst_reloads) don't get confused. */
5665 for (j = 0; j < n_reloads; j++)
5666 if (rld[j].reg_rtx != 0
5667 && ((rld[j].optional && ! reload_inherited[j])
5668 || (rld[j].in == 0 && rld[j].out == 0
5669 && ! rld[j].secondary_p)))
5671 int regno = true_regnum (rld[j].reg_rtx);
5673 if (spill_reg_order[regno] >= 0)
5674 clear_reload_reg_in_use (regno, rld[j].opnum,
5675 rld[j].when_needed, rld[j].mode);
5677 reload_spill_index[j] = -1;
5680 /* Record which pseudos and which spill regs have output reloads. */
5681 for (j = 0; j < n_reloads; j++)
5683 register int r = reload_order[j];
5685 i = reload_spill_index[r];
5687 /* I is nonneg if this reload uses a register.
5688 If rld[r].reg_rtx is 0, this is an optional reload
5689 that we opted to ignore. */
5690 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5691 && rld[r].reg_rtx != 0)
5693 register int nregno = REGNO (rld[r].out_reg);
5696 if (nregno < FIRST_PSEUDO_REGISTER)
5697 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5700 reg_has_output_reload[nregno + nr] = 1;
5704 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5706 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5709 if (rld[r].when_needed != RELOAD_OTHER
5710 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5711 && rld[r].when_needed != RELOAD_FOR_INSN)
5717 /* Deallocate the reload register for reload R. This is called from
5718 remove_address_replacements. */
5720 deallocate_reload_reg (r)
5725 if (! rld[r].reg_rtx)
5727 regno = true_regnum (rld[r].reg_rtx);
5729 if (spill_reg_order[regno] >= 0)
5730 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5732 reload_spill_index[r] = -1;
5735 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5736 reloads of the same item for fear that we might not have enough reload
5737 registers. However, normally they will get the same reload register
5738 and hence actually need not be loaded twice.
5740 Here we check for the most common case of this phenomenon: when we have
5741 a number of reloads for the same object, each of which were allocated
5742 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5743 reload, and is not modified in the insn itself. If we find such,
5744 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5745 This will not increase the number of spill registers needed and will
5746 prevent redundant code. */
5749 merge_assigned_reloads (insn)
5754 /* Scan all the reloads looking for ones that only load values and
5755 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5756 assigned and not modified by INSN. */
5758 for (i = 0; i < n_reloads; i++)
5760 int conflicting_input = 0;
5761 int max_input_address_opnum = -1;
5762 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5764 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5765 || rld[i].out != 0 || rld[i].reg_rtx == 0
5766 || reg_set_p (rld[i].reg_rtx, insn))
5769 /* Look at all other reloads. Ensure that the only use of this
5770 reload_reg_rtx is in a reload that just loads the same value
5771 as we do. Note that any secondary reloads must be of the identical
5772 class since the values, modes, and result registers are the
5773 same, so we need not do anything with any secondary reloads. */
5775 for (j = 0; j < n_reloads; j++)
5777 if (i == j || rld[j].reg_rtx == 0
5778 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
5782 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5783 && rld[j].opnum > max_input_address_opnum)
5784 max_input_address_opnum = rld[j].opnum;
5786 /* If the reload regs aren't exactly the same (e.g, different modes)
5787 or if the values are different, we can't merge this reload.
5788 But if it is an input reload, we might still merge
5789 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
5791 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5792 || rld[j].out != 0 || rld[j].in == 0
5793 || ! rtx_equal_p (rld[i].in, rld[j].in))
5795 if (rld[j].when_needed != RELOAD_FOR_INPUT
5796 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
5797 || rld[i].opnum > rld[j].opnum)
5798 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
5800 conflicting_input = 1;
5801 if (min_conflicting_input_opnum > rld[j].opnum)
5802 min_conflicting_input_opnum = rld[j].opnum;
5806 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5807 we, in fact, found any matching reloads. */
5810 && max_input_address_opnum <= min_conflicting_input_opnum)
5812 for (j = 0; j < n_reloads; j++)
5813 if (i != j && rld[j].reg_rtx != 0
5814 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5815 && (! conflicting_input
5816 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5817 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
5819 rld[i].when_needed = RELOAD_OTHER;
5821 reload_spill_index[j] = -1;
5822 transfer_replacements (i, j);
5825 /* If this is now RELOAD_OTHER, look for any reloads that load
5826 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5827 if they were for inputs, RELOAD_OTHER for outputs. Note that
5828 this test is equivalent to looking for reloads for this operand
5831 if (rld[i].when_needed == RELOAD_OTHER)
5832 for (j = 0; j < n_reloads; j++)
5834 && rld[i].when_needed != RELOAD_OTHER
5835 && reg_overlap_mentioned_for_reload_p (rld[j].in,
5838 = ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
5839 || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
5840 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
5846 /* These arrays are filled by emit_reload_insns and its subroutines. */
5847 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
5848 static rtx other_input_address_reload_insns = 0;
5849 static rtx other_input_reload_insns = 0;
5850 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
5851 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5852 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
5853 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
5854 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5855 static rtx operand_reload_insns = 0;
5856 static rtx other_operand_reload_insns = 0;
5857 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
5859 /* Values to be put in spill_reg_store are put here first. */
5860 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
5861 static HARD_REG_SET reg_reloaded_died;
5863 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
5864 has the number J. OLD contains the value to be used as input. */
5866 emit_input_reload_insns (chain, rl, old, j)
5867 struct insn_chain *chain;
5872 rtx insn = chain->insn;
5873 register rtx reloadreg = rl->reg_rtx;
5874 rtx oldequiv_reg = 0;
5877 enum machine_mode mode;
5880 /* Determine the mode to reload in.
5881 This is very tricky because we have three to choose from.
5882 There is the mode the insn operand wants (rl->inmode).
5883 There is the mode of the reload register RELOADREG.
5884 There is the intrinsic mode of the operand, which we could find
5885 by stripping some SUBREGs.
5886 It turns out that RELOADREG's mode is irrelevant:
5887 we can change that arbitrarily.
5889 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
5890 then the reload reg may not support QImode moves, so use SImode.
5891 If foo is in memory due to spilling a pseudo reg, this is safe,
5892 because the QImode value is in the least significant part of a
5893 slot big enough for a SImode. If foo is some other sort of
5894 memory reference, then it is impossible to reload this case,
5895 so previous passes had better make sure this never happens.
5897 Then consider a one-word union which has SImode and one of its
5898 members is a float, being fetched as (SUBREG:SF union:SI).
5899 We must fetch that as SFmode because we could be loading into
5900 a float-only register. In this case OLD's mode is correct.
5902 Consider an immediate integer: it has VOIDmode. Here we need
5903 to get a mode from something else.
5905 In some cases, there is a fourth mode, the operand's
5906 containing mode. If the insn specifies a containing mode for
5907 this operand, it overrides all others.
5909 I am not sure whether the algorithm here is always right,
5910 but it does the right things in those cases. */
5912 mode = GET_MODE (old);
5913 if (mode == VOIDmode)
5916 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5917 /* If we need a secondary register for this operation, see if
5918 the value is already in a register in that class. Don't
5919 do this if the secondary register will be used as a scratch
5922 if (rl->secondary_in_reload >= 0
5923 && rl->secondary_in_icode == CODE_FOR_nothing
5926 = find_equiv_reg (old, insn,
5927 rld[rl->secondary_in_reload].class,
5928 -1, NULL_PTR, 0, mode);
5931 /* If reloading from memory, see if there is a register
5932 that already holds the same value. If so, reload from there.
5933 We can pass 0 as the reload_reg_p argument because
5934 any other reload has either already been emitted,
5935 in which case find_equiv_reg will see the reload-insn,
5936 or has yet to be emitted, in which case it doesn't matter
5937 because we will use this equiv reg right away. */
5939 if (oldequiv == 0 && optimize
5940 && (GET_CODE (old) == MEM
5941 || (GET_CODE (old) == REG
5942 && REGNO (old) >= FIRST_PSEUDO_REGISTER
5943 && reg_renumber[REGNO (old)] < 0)))
5944 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
5945 -1, NULL_PTR, 0, mode);
5949 int regno = true_regnum (oldequiv);
5951 /* Don't use OLDEQUIV if any other reload changes it at an
5952 earlier stage of this insn or at this stage. */
5953 if (! reload_reg_free_for_value_p (regno, rl->opnum,
5955 rl->in, const0_rtx, j,
5959 /* If it is no cheaper to copy from OLDEQUIV into the
5960 reload register than it would be to move from memory,
5961 don't use it. Likewise, if we need a secondary register
5965 && ((REGNO_REG_CLASS (regno) != rl->class
5966 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
5968 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
5969 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5970 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
5974 #ifdef SECONDARY_MEMORY_NEEDED
5975 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
5983 /* delete_output_reload is only invoked properly if old contains
5984 the original pseudo register. Since this is replaced with a
5985 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
5986 find the pseudo in RELOAD_IN_REG. */
5988 && reload_override_in[j]
5989 && GET_CODE (rl->in_reg) == REG)
5996 else if (GET_CODE (oldequiv) == REG)
5997 oldequiv_reg = oldequiv;
5998 else if (GET_CODE (oldequiv) == SUBREG)
5999 oldequiv_reg = SUBREG_REG (oldequiv);
6001 /* If we are reloading from a register that was recently stored in
6002 with an output-reload, see if we can prove there was
6003 actually no need to store the old value in it. */
6005 if (optimize && GET_CODE (oldequiv) == REG
6006 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6007 && spill_reg_store[REGNO (oldequiv)]
6008 && GET_CODE (old) == REG
6009 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6010 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6012 delete_output_reload (insn, j, REGNO (oldequiv));
6014 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6015 then load RELOADREG from OLDEQUIV. Note that we cannot use
6016 gen_lowpart_common since it can do the wrong thing when
6017 RELOADREG has a multi-word mode. Note that RELOADREG
6018 must always be a REG here. */
6020 if (GET_MODE (reloadreg) != mode)
6021 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6022 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6023 oldequiv = SUBREG_REG (oldequiv);
6024 if (GET_MODE (oldequiv) != VOIDmode
6025 && mode != GET_MODE (oldequiv))
6026 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6028 /* Switch to the right place to emit the reload insns. */
6029 switch (rl->when_needed)
6032 where = &other_input_reload_insns;
6034 case RELOAD_FOR_INPUT:
6035 where = &input_reload_insns[rl->opnum];
6037 case RELOAD_FOR_INPUT_ADDRESS:
6038 where = &input_address_reload_insns[rl->opnum];
6040 case RELOAD_FOR_INPADDR_ADDRESS:
6041 where = &inpaddr_address_reload_insns[rl->opnum];
6043 case RELOAD_FOR_OUTPUT_ADDRESS:
6044 where = &output_address_reload_insns[rl->opnum];
6046 case RELOAD_FOR_OUTADDR_ADDRESS:
6047 where = &outaddr_address_reload_insns[rl->opnum];
6049 case RELOAD_FOR_OPERAND_ADDRESS:
6050 where = &operand_reload_insns;
6052 case RELOAD_FOR_OPADDR_ADDR:
6053 where = &other_operand_reload_insns;
6055 case RELOAD_FOR_OTHER_ADDRESS:
6056 where = &other_input_address_reload_insns;
6062 push_to_sequence (*where);
6064 /* Auto-increment addresses must be reloaded in a special way. */
6065 if (rl->out && ! rl->out_reg)
6067 /* We are not going to bother supporting the case where a
6068 incremented register can't be copied directly from
6069 OLDEQUIV since this seems highly unlikely. */
6070 if (rl->secondary_in_reload >= 0)
6073 if (reload_inherited[j])
6074 oldequiv = reloadreg;
6076 old = XEXP (rl->in_reg, 0);
6078 if (optimize && GET_CODE (oldequiv) == REG
6079 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6080 && spill_reg_store[REGNO (oldequiv)]
6081 && GET_CODE (old) == REG
6082 && (dead_or_set_p (insn,
6083 spill_reg_stored_to[REGNO (oldequiv)])
6084 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6086 delete_output_reload (insn, j, REGNO (oldequiv));
6088 /* Prevent normal processing of this reload. */
6090 /* Output a special code sequence for this case. */
6091 new_spill_reg_store[REGNO (reloadreg)]
6092 = inc_for_reload (reloadreg, oldequiv, rl->out,
6096 /* If we are reloading a pseudo-register that was set by the previous
6097 insn, see if we can get rid of that pseudo-register entirely
6098 by redirecting the previous insn into our reload register. */
6100 else if (optimize && GET_CODE (old) == REG
6101 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6102 && dead_or_set_p (insn, old)
6103 /* This is unsafe if some other reload
6104 uses the same reg first. */
6105 && reload_reg_free_for_value_p (REGNO (reloadreg),
6111 rtx temp = PREV_INSN (insn);
6112 while (temp && GET_CODE (temp) == NOTE)
6113 temp = PREV_INSN (temp);
6115 && GET_CODE (temp) == INSN
6116 && GET_CODE (PATTERN (temp)) == SET
6117 && SET_DEST (PATTERN (temp)) == old
6118 /* Make sure we can access insn_operand_constraint. */
6119 && asm_noperands (PATTERN (temp)) < 0
6120 /* This is unsafe if prev insn rejects our reload reg. */
6121 && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint,
6123 /* This is unsafe if operand occurs more than once in current
6124 insn. Perhaps some occurrences aren't reloaded. */
6125 && count_occurrences (PATTERN (insn), old) == 1
6126 /* Don't risk splitting a matching pair of operands. */
6127 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6129 /* Store into the reload register instead of the pseudo. */
6130 SET_DEST (PATTERN (temp)) = reloadreg;
6132 /* If the previous insn is an output reload, the source is
6133 a reload register, and its spill_reg_store entry will
6134 contain the previous destination. This is now
6136 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6137 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6139 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6140 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6143 /* If these are the only uses of the pseudo reg,
6144 pretend for GDB it lives in the reload reg we used. */
6145 if (REG_N_DEATHS (REGNO (old)) == 1
6146 && REG_N_SETS (REGNO (old)) == 1)
6148 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6149 alter_reg (REGNO (old), -1);
6155 /* We can't do that, so output an insn to load RELOADREG. */
6157 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6158 /* If we have a secondary reload, pick up the secondary register
6159 and icode, if any. If OLDEQUIV and OLD are different or
6160 if this is an in-out reload, recompute whether or not we
6161 still need a secondary register and what the icode should
6162 be. If we still need a secondary register and the class or
6163 icode is different, go back to reloading from OLD if using
6164 OLDEQUIV means that we got the wrong type of register. We
6165 cannot have different class or icode due to an in-out reload
6166 because we don't make such reloads when both the input and
6167 output need secondary reload registers. */
6169 if (! special && rl->secondary_in_reload >= 0)
6171 rtx second_reload_reg = 0;
6172 int secondary_reload = rl->secondary_in_reload;
6173 rtx real_oldequiv = oldequiv;
6176 enum insn_code icode;
6178 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6179 and similarly for OLD.
6180 See comments in get_secondary_reload in reload.c. */
6181 /* If it is a pseudo that cannot be replaced with its
6182 equivalent MEM, we must fall back to reload_in, which
6183 will have all the necessary substitutions registered.
6184 Likewise for a pseudo that can't be replaced with its
6185 equivalent constant.
6187 Take extra care for subregs of such pseudos. Note that
6188 we cannot use reg_equiv_mem in this case because it is
6189 not in the right mode. */
6192 if (GET_CODE (tmp) == SUBREG)
6193 tmp = SUBREG_REG (tmp);
6194 if (GET_CODE (tmp) == REG
6195 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6196 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6197 || reg_equiv_constant[REGNO (tmp)] != 0))
6199 if (! reg_equiv_mem[REGNO (tmp)]
6200 || num_not_at_initial_offset
6201 || GET_CODE (oldequiv) == SUBREG)
6202 real_oldequiv = rl->in;
6204 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6208 if (GET_CODE (tmp) == SUBREG)
6209 tmp = SUBREG_REG (tmp);
6210 if (GET_CODE (tmp) == REG
6211 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6212 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6213 || reg_equiv_constant[REGNO (tmp)] != 0))
6215 if (! reg_equiv_mem[REGNO (tmp)]
6216 || num_not_at_initial_offset
6217 || GET_CODE (old) == SUBREG)
6220 real_old = reg_equiv_mem[REGNO (tmp)];
6223 second_reload_reg = rld[secondary_reload].reg_rtx;
6224 icode = rl->secondary_in_icode;
6226 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6227 || (rl->in != 0 && rl->out != 0))
6229 enum reg_class new_class
6230 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6231 mode, real_oldequiv);
6233 if (new_class == NO_REGS)
6234 second_reload_reg = 0;
6237 enum insn_code new_icode;
6238 enum machine_mode new_mode;
6240 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6241 REGNO (second_reload_reg)))
6242 oldequiv = old, real_oldequiv = real_old;
6245 new_icode = reload_in_optab[(int) mode];
6246 if (new_icode != CODE_FOR_nothing
6247 && ((insn_data[(int) new_icode].operand[0].predicate
6248 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6250 || (insn_data[(int) new_icode].operand[1].predicate
6251 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6252 (real_oldequiv, mode)))))
6253 new_icode = CODE_FOR_nothing;
6255 if (new_icode == CODE_FOR_nothing)
6258 new_mode = insn_data[(int) new_icode].operand[2].mode;
6260 if (GET_MODE (second_reload_reg) != new_mode)
6262 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6264 oldequiv = old, real_oldequiv = real_old;
6267 = gen_rtx_REG (new_mode,
6268 REGNO (second_reload_reg));
6274 /* If we still need a secondary reload register, check
6275 to see if it is being used as a scratch or intermediate
6276 register and generate code appropriately. If we need
6277 a scratch register, use REAL_OLDEQUIV since the form of
6278 the insn may depend on the actual address if it is
6281 if (second_reload_reg)
6283 if (icode != CODE_FOR_nothing)
6285 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6286 second_reload_reg));
6291 /* See if we need a scratch register to load the
6292 intermediate register (a tertiary reload). */
6293 enum insn_code tertiary_icode
6294 = rld[secondary_reload].secondary_in_icode;
6296 if (tertiary_icode != CODE_FOR_nothing)
6298 rtx third_reload_reg
6299 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6301 emit_insn ((GEN_FCN (tertiary_icode)
6302 (second_reload_reg, real_oldequiv,
6303 third_reload_reg)));
6306 gen_reload (second_reload_reg, real_oldequiv,
6310 oldequiv = second_reload_reg;
6316 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6318 rtx real_oldequiv = oldequiv;
6320 if ((GET_CODE (oldequiv) == REG
6321 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6322 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6323 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6324 || (GET_CODE (oldequiv) == SUBREG
6325 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6326 && (REGNO (SUBREG_REG (oldequiv))
6327 >= FIRST_PSEUDO_REGISTER)
6328 && ((reg_equiv_memory_loc
6329 [REGNO (SUBREG_REG (oldequiv))] != 0)
6330 || (reg_equiv_constant
6331 [REGNO (SUBREG_REG (oldequiv))] != 0))))
6332 real_oldequiv = rl->in;
6333 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6337 /* End this sequence. */
6338 *where = get_insns ();
6341 /* Update reload_override_in so that delete_address_reloads_1
6342 can see the actual register usage. */
6344 reload_override_in[j] = oldequiv;
6347 /* Generate insns to for the output reload RL, which is for the insn described
6348 by CHAIN and has the number J. */
6350 emit_output_reload_insns (chain, rl, j)
6351 struct insn_chain *chain;
6355 rtx reloadreg = rl->reg_rtx;
6356 rtx insn = chain->insn;
6359 enum machine_mode mode = GET_MODE (old);
6362 if (rl->when_needed == RELOAD_OTHER)
6365 push_to_sequence (output_reload_insns[rl->opnum]);
6367 /* Determine the mode to reload in.
6368 See comments above (for input reloading). */
6370 if (mode == VOIDmode)
6372 /* VOIDmode should never happen for an output. */
6373 if (asm_noperands (PATTERN (insn)) < 0)
6374 /* It's the compiler's fault. */
6375 fatal_insn ("VOIDmode on an output", insn);
6376 error_for_asm (insn, "output operand is constant in `asm'");
6377 /* Prevent crash--use something we know is valid. */
6379 old = gen_rtx_REG (mode, REGNO (reloadreg));
6382 if (GET_MODE (reloadreg) != mode)
6383 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6385 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6387 /* If we need two reload regs, set RELOADREG to the intermediate
6388 one, since it will be stored into OLD. We might need a secondary
6389 register only for an input reload, so check again here. */
6391 if (rl->secondary_out_reload >= 0)
6395 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6396 && reg_equiv_mem[REGNO (old)] != 0)
6397 real_old = reg_equiv_mem[REGNO (old)];
6399 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6403 rtx second_reloadreg = reloadreg;
6404 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6406 /* See if RELOADREG is to be used as a scratch register
6407 or as an intermediate register. */
6408 if (rl->secondary_out_icode != CODE_FOR_nothing)
6410 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6411 (real_old, second_reloadreg, reloadreg)));
6416 /* See if we need both a scratch and intermediate reload
6419 int secondary_reload = rl->secondary_out_reload;
6420 enum insn_code tertiary_icode
6421 = rld[secondary_reload].secondary_out_icode;
6423 if (GET_MODE (reloadreg) != mode)
6424 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6426 if (tertiary_icode != CODE_FOR_nothing)
6429 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6432 /* Copy primary reload reg to secondary reload reg.
6433 (Note that these have been swapped above, then
6434 secondary reload reg to OLD using our insn. */
6436 /* If REAL_OLD is a paradoxical SUBREG, remove it
6437 and try to put the opposite SUBREG on
6439 if (GET_CODE (real_old) == SUBREG
6440 && (GET_MODE_SIZE (GET_MODE (real_old))
6441 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6442 && 0 != (tem = gen_lowpart_common
6443 (GET_MODE (SUBREG_REG (real_old)),
6445 real_old = SUBREG_REG (real_old), reloadreg = tem;
6447 gen_reload (reloadreg, second_reloadreg,
6448 rl->opnum, rl->when_needed);
6449 emit_insn ((GEN_FCN (tertiary_icode)
6450 (real_old, reloadreg, third_reloadreg)));
6455 /* Copy between the reload regs here and then to
6458 gen_reload (reloadreg, second_reloadreg,
6459 rl->opnum, rl->when_needed);
6465 /* Output the last reload insn. */
6470 /* Don't output the last reload if OLD is not the dest of
6471 INSN and is in the src and is clobbered by INSN. */
6472 if (! flag_expensive_optimizations
6473 || GET_CODE (old) != REG
6474 || !(set = single_set (insn))
6475 || rtx_equal_p (old, SET_DEST (set))
6476 || !reg_mentioned_p (old, SET_SRC (set))
6477 || !regno_clobbered_p (REGNO (old), insn))
6478 gen_reload (old, reloadreg, rl->opnum,
6482 /* Look at all insns we emitted, just to be safe. */
6483 for (p = get_insns (); p; p = NEXT_INSN (p))
6484 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
6486 rtx pat = PATTERN (p);
6488 /* If this output reload doesn't come from a spill reg,
6489 clear any memory of reloaded copies of the pseudo reg.
6490 If this output reload comes from a spill reg,
6491 reg_has_output_reload will make this do nothing. */
6492 note_stores (pat, forget_old_reloads_1, NULL);
6494 if (reg_mentioned_p (rl->reg_rtx, pat))
6496 rtx set = single_set (insn);
6497 if (reload_spill_index[j] < 0
6499 && SET_SRC (set) == rl->reg_rtx)
6501 int src = REGNO (SET_SRC (set));
6503 reload_spill_index[j] = src;
6504 SET_HARD_REG_BIT (reg_is_output_reload, src);
6505 if (find_regno_note (insn, REG_DEAD, src))
6506 SET_HARD_REG_BIT (reg_reloaded_died, src);
6508 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6510 int s = rl->secondary_out_reload;
6511 set = single_set (p);
6512 /* If this reload copies only to the secondary reload
6513 register, the secondary reload does the actual
6515 if (s >= 0 && set == NULL_RTX)
6516 ; /* We can't tell what function the secondary reload
6517 has and where the actual store to the pseudo is
6518 made; leave new_spill_reg_store alone. */
6520 && SET_SRC (set) == rl->reg_rtx
6521 && SET_DEST (set) == rld[s].reg_rtx)
6523 /* Usually the next instruction will be the
6524 secondary reload insn; if we can confirm
6525 that it is, setting new_spill_reg_store to
6526 that insn will allow an extra optimization. */
6527 rtx s_reg = rld[s].reg_rtx;
6528 rtx next = NEXT_INSN (p);
6529 rld[s].out = rl->out;
6530 rld[s].out_reg = rl->out_reg;
6531 set = single_set (next);
6532 if (set && SET_SRC (set) == s_reg
6533 && ! new_spill_reg_store[REGNO (s_reg)])
6535 SET_HARD_REG_BIT (reg_is_output_reload,
6537 new_spill_reg_store[REGNO (s_reg)] = next;
6541 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6546 if (rl->when_needed == RELOAD_OTHER)
6548 emit_insns (other_output_reload_insns[rl->opnum]);
6549 other_output_reload_insns[rl->opnum] = get_insns ();
6552 output_reload_insns[rl->opnum] = get_insns ();
6557 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6558 and has the number J. */
6560 do_input_reload (chain, rl, j)
6561 struct insn_chain *chain;
6565 int expect_occurrences = 1;
6566 rtx insn = chain->insn;
6567 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6568 ? rl->in_reg : rl->in);
6571 /* AUTO_INC reloads need to be handled even if inherited. We got an
6572 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6573 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6574 && ! rtx_equal_p (rl->reg_rtx, old)
6575 && rl->reg_rtx != 0)
6577 emit_input_reload_insns (chain, rld + j, old, j);
6580 /* When inheriting a wider reload, we have a MEM in rl->in,
6581 e.g. inheriting a SImode output reload for
6582 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6583 if (optimize && reload_inherited[j] && rl->in
6584 && GET_CODE (rl->in) == MEM
6585 && GET_CODE (rl->in_reg) == MEM
6586 && reload_spill_index[j] >= 0
6587 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6590 = count_occurrences (PATTERN (insn), rl->in) == 1 ? 0 : -1;
6592 = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6595 /* If we are reloading a register that was recently stored in with an
6596 output-reload, see if we can prove there was
6597 actually no need to store the old value in it. */
6600 && (reload_inherited[j] || reload_override_in[j])
6602 && GET_CODE (rl->reg_rtx) == REG
6603 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6605 /* There doesn't seem to be any reason to restrict this to pseudos
6606 and doing so loses in the case where we are copying from a
6607 register of the wrong class. */
6608 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6609 >= FIRST_PSEUDO_REGISTER)
6611 /* The insn might have already some references to stackslots
6612 replaced by MEMs, while reload_out_reg still names the
6614 && (dead_or_set_p (insn,
6615 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6616 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6618 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6621 /* Do output reloading for reload RL, which is for the insn described by
6622 CHAIN and has the number J.
6623 ??? At some point we need to support handling output reloads of
6624 JUMP_INSNs or insns that set cc0. */
6626 do_output_reload (chain, rl, j)
6627 struct insn_chain *chain;
6632 rtx insn = chain->insn;
6633 /* If this is an output reload that stores something that is
6634 not loaded in this same reload, see if we can eliminate a previous
6636 rtx pseudo = rl->out_reg;
6639 && GET_CODE (pseudo) == REG
6640 && ! rtx_equal_p (rl->in_reg, pseudo)
6641 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6642 && reg_last_reload_reg[REGNO (pseudo)])
6644 int pseudo_no = REGNO (pseudo);
6645 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6647 /* We don't need to test full validity of last_regno for
6648 inherit here; we only want to know if the store actually
6649 matches the pseudo. */
6650 if (reg_reloaded_contents[last_regno] == pseudo_no
6651 && spill_reg_store[last_regno]
6652 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6653 delete_output_reload (insn, j, last_regno);
6658 || rl->reg_rtx == old
6659 || rl->reg_rtx == 0)
6662 /* An output operand that dies right away does need a reload,
6663 but need not be copied from it. Show the new location in the
6665 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6666 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6668 XEXP (note, 0) = rl->reg_rtx;
6671 /* Likewise for a SUBREG of an operand that dies. */
6672 else if (GET_CODE (old) == SUBREG
6673 && GET_CODE (SUBREG_REG (old)) == REG
6674 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6677 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6681 else if (GET_CODE (old) == SCRATCH)
6682 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6683 but we don't want to make an output reload. */
6686 /* If is a JUMP_INSN, we can't support output reloads yet. */
6687 if (GET_CODE (insn) == JUMP_INSN)
6690 emit_output_reload_insns (chain, rld + j, j);
6693 /* Output insns to reload values in and out of the chosen reload regs. */
6696 emit_reload_insns (chain)
6697 struct insn_chain *chain;
6699 rtx insn = chain->insn;
6702 rtx following_insn = NEXT_INSN (insn);
6703 rtx before_insn = PREV_INSN (insn);
6705 CLEAR_HARD_REG_SET (reg_reloaded_died);
6707 for (j = 0; j < reload_n_operands; j++)
6708 input_reload_insns[j] = input_address_reload_insns[j]
6709 = inpaddr_address_reload_insns[j]
6710 = output_reload_insns[j] = output_address_reload_insns[j]
6711 = outaddr_address_reload_insns[j]
6712 = other_output_reload_insns[j] = 0;
6713 other_input_address_reload_insns = 0;
6714 other_input_reload_insns = 0;
6715 operand_reload_insns = 0;
6716 other_operand_reload_insns = 0;
6718 /* Now output the instructions to copy the data into and out of the
6719 reload registers. Do these in the order that the reloads were reported,
6720 since reloads of base and index registers precede reloads of operands
6721 and the operands may need the base and index registers reloaded. */
6723 for (j = 0; j < n_reloads; j++)
6726 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6727 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6729 do_input_reload (chain, rld + j, j);
6730 do_output_reload (chain, rld + j, j);
6733 /* Now write all the insns we made for reloads in the order expected by
6734 the allocation functions. Prior to the insn being reloaded, we write
6735 the following reloads:
6737 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6739 RELOAD_OTHER reloads.
6741 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6742 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6743 RELOAD_FOR_INPUT reload for the operand.
6745 RELOAD_FOR_OPADDR_ADDRS reloads.
6747 RELOAD_FOR_OPERAND_ADDRESS reloads.
6749 After the insn being reloaded, we write the following:
6751 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6752 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6753 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6754 reloads for the operand. The RELOAD_OTHER output reloads are
6755 output in descending order by reload number. */
6757 emit_insns_before (other_input_address_reload_insns, insn);
6758 emit_insns_before (other_input_reload_insns, insn);
6760 for (j = 0; j < reload_n_operands; j++)
6762 emit_insns_before (inpaddr_address_reload_insns[j], insn);
6763 emit_insns_before (input_address_reload_insns[j], insn);
6764 emit_insns_before (input_reload_insns[j], insn);
6767 emit_insns_before (other_operand_reload_insns, insn);
6768 emit_insns_before (operand_reload_insns, insn);
6770 for (j = 0; j < reload_n_operands; j++)
6772 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
6773 emit_insns_before (output_address_reload_insns[j], following_insn);
6774 emit_insns_before (output_reload_insns[j], following_insn);
6775 emit_insns_before (other_output_reload_insns[j], following_insn);
6778 /* Keep basic block info up to date. */
6781 if (BLOCK_HEAD (chain->block) == insn)
6782 BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
6783 if (BLOCK_END (chain->block) == insn)
6784 BLOCK_END (chain->block) = PREV_INSN (following_insn);
6787 /* For all the spill regs newly reloaded in this instruction,
6788 record what they were reloaded from, so subsequent instructions
6789 can inherit the reloads.
6791 Update spill_reg_store for the reloads of this insn.
6792 Copy the elements that were updated in the loop above. */
6794 for (j = 0; j < n_reloads; j++)
6796 register int r = reload_order[j];
6797 register int i = reload_spill_index[r];
6799 /* If this is a non-inherited input reload from a pseudo, we must
6800 clear any memory of a previous store to the same pseudo. Only do
6801 something if there will not be an output reload for the pseudo
6803 if (rld[r].in_reg != 0
6804 && ! (reload_inherited[r] || reload_override_in[r]))
6806 rtx reg = rld[r].in_reg;
6808 if (GET_CODE (reg) == SUBREG)
6809 reg = SUBREG_REG (reg);
6811 if (GET_CODE (reg) == REG
6812 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
6813 && ! reg_has_output_reload[REGNO (reg)])
6815 int nregno = REGNO (reg);
6817 if (reg_last_reload_reg[nregno])
6819 int last_regno = REGNO (reg_last_reload_reg[nregno]);
6821 if (reg_reloaded_contents[last_regno] == nregno)
6822 spill_reg_store[last_regno] = 0;
6827 /* I is nonneg if this reload used a register.
6828 If rld[r].reg_rtx is 0, this is an optional reload
6829 that we opted to ignore. */
6831 if (i >= 0 && rld[r].reg_rtx != 0)
6834 = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
6836 int part_reaches_end = 0;
6837 int all_reaches_end = 1;
6839 /* For a multi register reload, we need to check if all or part
6840 of the value lives to the end. */
6841 for (k = 0; k < nr; k++)
6843 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
6844 rld[r].when_needed))
6845 part_reaches_end = 1;
6847 all_reaches_end = 0;
6850 /* Ignore reloads that don't reach the end of the insn in
6852 if (all_reaches_end)
6854 /* First, clear out memory of what used to be in this spill reg.
6855 If consecutive registers are used, clear them all. */
6857 for (k = 0; k < nr; k++)
6858 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
6860 /* Maybe the spill reg contains a copy of reload_out. */
6862 && (GET_CODE (rld[r].out) == REG
6866 || GET_CODE (rld[r].out_reg) == REG))
6868 rtx out = (GET_CODE (rld[r].out) == REG
6872 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
6873 register int nregno = REGNO (out);
6874 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6875 : HARD_REGNO_NREGS (nregno,
6876 GET_MODE (rld[r].reg_rtx)));
6878 spill_reg_store[i] = new_spill_reg_store[i];
6879 spill_reg_stored_to[i] = out;
6880 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
6882 /* If NREGNO is a hard register, it may occupy more than
6883 one register. If it does, say what is in the
6884 rest of the registers assuming that both registers
6885 agree on how many words the object takes. If not,
6886 invalidate the subsequent registers. */
6888 if (nregno < FIRST_PSEUDO_REGISTER)
6889 for (k = 1; k < nnr; k++)
6890 reg_last_reload_reg[nregno + k]
6892 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
6893 REGNO (rld[r].reg_rtx) + k)
6896 /* Now do the inverse operation. */
6897 for (k = 0; k < nr; k++)
6899 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
6900 reg_reloaded_contents[i + k]
6901 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
6904 reg_reloaded_insn[i + k] = insn;
6905 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
6909 /* Maybe the spill reg contains a copy of reload_in. Only do
6910 something if there will not be an output reload for
6911 the register being reloaded. */
6912 else if (rld[r].out_reg == 0
6914 && ((GET_CODE (rld[r].in) == REG
6915 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
6916 && ! reg_has_output_reload[REGNO (rld[r].in)])
6917 || (GET_CODE (rld[r].in_reg) == REG
6918 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
6919 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
6921 register int nregno;
6924 if (GET_CODE (rld[r].in) == REG
6925 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
6926 nregno = REGNO (rld[r].in);
6927 else if (GET_CODE (rld[r].in_reg) == REG)
6928 nregno = REGNO (rld[r].in_reg);
6930 nregno = REGNO (XEXP (rld[r].in_reg, 0));
6932 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6933 : HARD_REGNO_NREGS (nregno,
6934 GET_MODE (rld[r].reg_rtx)));
6936 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
6938 if (nregno < FIRST_PSEUDO_REGISTER)
6939 for (k = 1; k < nnr; k++)
6940 reg_last_reload_reg[nregno + k]
6942 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
6943 REGNO (rld[r].reg_rtx) + k)
6946 /* Unless we inherited this reload, show we haven't
6947 recently done a store.
6948 Previous stores of inherited auto_inc expressions
6949 also have to be discarded. */
6950 if (! reload_inherited[r]
6951 || (rld[r].out && ! rld[r].out_reg))
6952 spill_reg_store[i] = 0;
6954 for (k = 0; k < nr; k++)
6956 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
6957 reg_reloaded_contents[i + k]
6958 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
6961 reg_reloaded_insn[i + k] = insn;
6962 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
6967 /* However, if part of the reload reaches the end, then we must
6968 invalidate the old info for the part that survives to the end. */
6969 else if (part_reaches_end)
6971 for (k = 0; k < nr; k++)
6972 if (reload_reg_reaches_end_p (i + k,
6974 rld[r].when_needed))
6975 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
6979 /* The following if-statement was #if 0'd in 1.34 (or before...).
6980 It's reenabled in 1.35 because supposedly nothing else
6981 deals with this problem. */
6983 /* If a register gets output-reloaded from a non-spill register,
6984 that invalidates any previous reloaded copy of it.
6985 But forget_old_reloads_1 won't get to see it, because
6986 it thinks only about the original insn. So invalidate it here. */
6987 if (i < 0 && rld[r].out != 0
6988 && (GET_CODE (rld[r].out) == REG
6989 || (GET_CODE (rld[r].out) == MEM
6990 && GET_CODE (rld[r].out_reg) == REG)))
6992 rtx out = (GET_CODE (rld[r].out) == REG
6993 ? rld[r].out : rld[r].out_reg);
6994 register int nregno = REGNO (out);
6995 if (nregno >= FIRST_PSEUDO_REGISTER)
6997 rtx src_reg, store_insn = NULL_RTX;
6999 reg_last_reload_reg[nregno] = 0;
7001 /* If we can find a hard register that is stored, record
7002 the storing insn so that we may delete this insn with
7003 delete_output_reload. */
7004 src_reg = rld[r].reg_rtx;
7006 /* If this is an optional reload, try to find the source reg
7007 from an input reload. */
7010 rtx set = single_set (insn);
7011 if (set && SET_DEST (set) == rld[r].out)
7015 src_reg = SET_SRC (set);
7017 for (k = 0; k < n_reloads; k++)
7019 if (rld[k].in == src_reg)
7021 src_reg = rld[k].reg_rtx;
7028 store_insn = new_spill_reg_store[REGNO (src_reg)];
7029 if (src_reg && GET_CODE (src_reg) == REG
7030 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7032 int src_regno = REGNO (src_reg);
7033 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7034 /* The place where to find a death note varies with
7035 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7036 necessarily checked exactly in the code that moves
7037 notes, so just check both locations. */
7038 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7040 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7043 spill_reg_store[src_regno + nr] = store_insn;
7044 spill_reg_stored_to[src_regno + nr] = out;
7045 reg_reloaded_contents[src_regno + nr] = nregno;
7046 reg_reloaded_insn[src_regno + nr] = store_insn;
7047 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7048 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7049 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7051 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7053 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7055 reg_last_reload_reg[nregno] = src_reg;
7060 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (rld[r].out));
7062 while (num_regs-- > 0)
7063 reg_last_reload_reg[nregno + num_regs] = 0;
7067 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7070 /* Emit code to perform a reload from IN (which may be a reload register) to
7071 OUT (which may also be a reload register). IN or OUT is from operand
7072 OPNUM with reload type TYPE.
7074 Returns first insn emitted. */
7077 gen_reload (out, in, opnum, type)
7081 enum reload_type type;
7083 rtx last = get_last_insn ();
7086 /* If IN is a paradoxical SUBREG, remove it and try to put the
7087 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7088 if (GET_CODE (in) == SUBREG
7089 && (GET_MODE_SIZE (GET_MODE (in))
7090 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7091 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7092 in = SUBREG_REG (in), out = tem;
7093 else if (GET_CODE (out) == SUBREG
7094 && (GET_MODE_SIZE (GET_MODE (out))
7095 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7096 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7097 out = SUBREG_REG (out), in = tem;
7099 /* How to do this reload can get quite tricky. Normally, we are being
7100 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7101 register that didn't get a hard register. In that case we can just
7102 call emit_move_insn.
7104 We can also be asked to reload a PLUS that adds a register or a MEM to
7105 another register, constant or MEM. This can occur during frame pointer
7106 elimination and while reloading addresses. This case is handled by
7107 trying to emit a single insn to perform the add. If it is not valid,
7108 we use a two insn sequence.
7110 Finally, we could be called to handle an 'o' constraint by putting
7111 an address into a register. In that case, we first try to do this
7112 with a named pattern of "reload_load_address". If no such pattern
7113 exists, we just emit a SET insn and hope for the best (it will normally
7114 be valid on machines that use 'o').
7116 This entire process is made complex because reload will never
7117 process the insns we generate here and so we must ensure that
7118 they will fit their constraints and also by the fact that parts of
7119 IN might be being reloaded separately and replaced with spill registers.
7120 Because of this, we are, in some sense, just guessing the right approach
7121 here. The one listed above seems to work.
7123 ??? At some point, this whole thing needs to be rethought. */
7125 if (GET_CODE (in) == PLUS
7126 && (GET_CODE (XEXP (in, 0)) == REG
7127 || GET_CODE (XEXP (in, 0)) == SUBREG
7128 || GET_CODE (XEXP (in, 0)) == MEM)
7129 && (GET_CODE (XEXP (in, 1)) == REG
7130 || GET_CODE (XEXP (in, 1)) == SUBREG
7131 || CONSTANT_P (XEXP (in, 1))
7132 || GET_CODE (XEXP (in, 1)) == MEM))
7134 /* We need to compute the sum of a register or a MEM and another
7135 register, constant, or MEM, and put it into the reload
7136 register. The best possible way of doing this is if the machine
7137 has a three-operand ADD insn that accepts the required operands.
7139 The simplest approach is to try to generate such an insn and see if it
7140 is recognized and matches its constraints. If so, it can be used.
7142 It might be better not to actually emit the insn unless it is valid,
7143 but we need to pass the insn as an operand to `recog' and
7144 `extract_insn' and it is simpler to emit and then delete the insn if
7145 not valid than to dummy things up. */
7147 rtx op0, op1, tem, insn;
7150 op0 = find_replacement (&XEXP (in, 0));
7151 op1 = find_replacement (&XEXP (in, 1));
7153 /* Since constraint checking is strict, commutativity won't be
7154 checked, so we need to do that here to avoid spurious failure
7155 if the add instruction is two-address and the second operand
7156 of the add is the same as the reload reg, which is frequently
7157 the case. If the insn would be A = B + A, rearrange it so
7158 it will be A = A + B as constrain_operands expects. */
7160 if (GET_CODE (XEXP (in, 1)) == REG
7161 && REGNO (out) == REGNO (XEXP (in, 1)))
7162 tem = op0, op0 = op1, op1 = tem;
7164 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7165 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7167 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7168 code = recog_memoized (insn);
7172 extract_insn (insn);
7173 /* We want constrain operands to treat this insn strictly in
7174 its validity determination, i.e., the way it would after reload
7176 if (constrain_operands (1))
7180 delete_insns_since (last);
7182 /* If that failed, we must use a conservative two-insn sequence.
7184 Use a move to copy one operand into the reload register. Prefer
7185 to reload a constant, MEM or pseudo since the move patterns can
7186 handle an arbitrary operand. If OP1 is not a constant, MEM or
7187 pseudo and OP1 is not a valid operand for an add instruction, then
7190 After reloading one of the operands into the reload register, add
7191 the reload register to the output register.
7193 If there is another way to do this for a specific machine, a
7194 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7197 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7199 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7200 || (GET_CODE (op1) == REG
7201 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7202 || (code != CODE_FOR_nothing
7203 && ! ((*insn_data[code].operand[2].predicate)
7204 (op1, insn_data[code].operand[2].mode))))
7205 tem = op0, op0 = op1, op1 = tem;
7207 gen_reload (out, op0, opnum, type);
7209 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7210 This fixes a problem on the 32K where the stack pointer cannot
7211 be used as an operand of an add insn. */
7213 if (rtx_equal_p (op0, op1))
7216 insn = emit_insn (gen_add2_insn (out, op1));
7218 /* If that failed, copy the address register to the reload register.
7219 Then add the constant to the reload register. */
7221 code = recog_memoized (insn);
7225 extract_insn (insn);
7226 /* We want constrain operands to treat this insn strictly in
7227 its validity determination, i.e., the way it would after reload
7229 if (constrain_operands (1))
7231 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7233 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7238 delete_insns_since (last);
7240 gen_reload (out, op1, opnum, type);
7241 insn = emit_insn (gen_add2_insn (out, op0));
7242 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7245 #ifdef SECONDARY_MEMORY_NEEDED
7246 /* If we need a memory location to do the move, do it that way. */
7247 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7248 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7249 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7250 REGNO_REG_CLASS (REGNO (out)),
7253 /* Get the memory to use and rewrite both registers to its mode. */
7254 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7256 if (GET_MODE (loc) != GET_MODE (out))
7257 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7259 if (GET_MODE (loc) != GET_MODE (in))
7260 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7262 gen_reload (loc, in, opnum, type);
7263 gen_reload (out, loc, opnum, type);
7267 /* If IN is a simple operand, use gen_move_insn. */
7268 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7269 emit_insn (gen_move_insn (out, in));
7271 #ifdef HAVE_reload_load_address
7272 else if (HAVE_reload_load_address)
7273 emit_insn (gen_reload_load_address (out, in));
7276 /* Otherwise, just write (set OUT IN) and hope for the best. */
7278 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7280 /* Return the first insn emitted.
7281 We can not just return get_last_insn, because there may have
7282 been multiple instructions emitted. Also note that gen_move_insn may
7283 emit more than one insn itself, so we can not assume that there is one
7284 insn emitted per emit_insn_before call. */
7286 return last ? NEXT_INSN (last) : get_insns ();
7289 /* Delete a previously made output-reload
7290 whose result we now believe is not needed.
7291 First we double-check.
7293 INSN is the insn now being processed.
7294 LAST_RELOAD_REG is the hard register number for which we want to delete
7295 the last output reload.
7296 J is the reload-number that originally used REG. The caller has made
7297 certain that reload J doesn't use REG any longer for input. */
7300 delete_output_reload (insn, j, last_reload_reg)
7303 int last_reload_reg;
7305 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7306 rtx reg = spill_reg_stored_to[last_reload_reg];
7309 int n_inherited = 0;
7313 /* Get the raw pseudo-register referred to. */
7315 while (GET_CODE (reg) == SUBREG)
7316 reg = SUBREG_REG (reg);
7317 substed = reg_equiv_memory_loc[REGNO (reg)];
7319 /* This is unsafe if the operand occurs more often in the current
7320 insn than it is inherited. */
7321 for (k = n_reloads - 1; k >= 0; k--)
7323 rtx reg2 = rld[k].in;
7326 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7327 reg2 = rld[k].in_reg;
7329 if (rld[k].out && ! rld[k].out_reg)
7330 reg2 = XEXP (rld[k].in_reg, 0);
7332 while (GET_CODE (reg2) == SUBREG)
7333 reg2 = SUBREG_REG (reg2);
7334 if (rtx_equal_p (reg2, reg))
7336 if (reload_inherited[k] || reload_override_in[k] || k == j)
7339 reg2 = rld[k].out_reg;
7342 while (GET_CODE (reg2) == SUBREG)
7343 reg2 = XEXP (reg2, 0);
7344 if (rtx_equal_p (reg2, reg))
7351 n_occurrences = count_occurrences (PATTERN (insn), reg);
7353 n_occurrences += count_occurrences (PATTERN (insn), substed);
7354 if (n_occurrences > n_inherited)
7357 /* If the pseudo-reg we are reloading is no longer referenced
7358 anywhere between the store into it and here,
7359 and no jumps or labels intervene, then the value can get
7360 here through the reload reg alone.
7361 Otherwise, give up--return. */
7362 for (i1 = NEXT_INSN (output_reload_insn);
7363 i1 != insn; i1 = NEXT_INSN (i1))
7365 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7367 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7368 && reg_mentioned_p (reg, PATTERN (i1)))
7370 /* If this is USE in front of INSN, we only have to check that
7371 there are no more references than accounted for by inheritance. */
7372 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7374 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7375 i1 = NEXT_INSN (i1);
7377 if (n_occurrences <= n_inherited && i1 == insn)
7383 /* The caller has already checked that REG dies or is set in INSN.
7384 It has also checked that we are optimizing, and thus some inaccurancies
7385 in the debugging information are acceptable.
7386 So we could just delete output_reload_insn.
7387 But in some cases we can improve the debugging information without
7388 sacrificing optimization - maybe even improving the code:
7389 See if the pseudo reg has been completely replaced
7390 with reload regs. If so, delete the store insn
7391 and forget we had a stack slot for the pseudo. */
7392 if (rld[j].out != rld[j].in
7393 && REG_N_DEATHS (REGNO (reg)) == 1
7394 && REG_N_SETS (REGNO (reg)) == 1
7395 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7396 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7400 /* We know that it was used only between here
7401 and the beginning of the current basic block.
7402 (We also know that the last use before INSN was
7403 the output reload we are thinking of deleting, but never mind that.)
7404 Search that range; see if any ref remains. */
7405 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7407 rtx set = single_set (i2);
7409 /* Uses which just store in the pseudo don't count,
7410 since if they are the only uses, they are dead. */
7411 if (set != 0 && SET_DEST (set) == reg)
7413 if (GET_CODE (i2) == CODE_LABEL
7414 || GET_CODE (i2) == JUMP_INSN)
7416 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7417 && reg_mentioned_p (reg, PATTERN (i2)))
7419 /* Some other ref remains; just delete the output reload we
7421 delete_address_reloads (output_reload_insn, insn);
7422 PUT_CODE (output_reload_insn, NOTE);
7423 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7424 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7429 /* Delete the now-dead stores into this pseudo. */
7430 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7432 rtx set = single_set (i2);
7434 if (set != 0 && SET_DEST (set) == reg)
7436 delete_address_reloads (i2, insn);
7437 /* This might be a basic block head,
7438 thus don't use delete_insn. */
7439 PUT_CODE (i2, NOTE);
7440 NOTE_SOURCE_FILE (i2) = 0;
7441 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7443 if (GET_CODE (i2) == CODE_LABEL
7444 || GET_CODE (i2) == JUMP_INSN)
7448 /* For the debugging info,
7449 say the pseudo lives in this reload reg. */
7450 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7451 alter_reg (REGNO (reg), -1);
7453 delete_address_reloads (output_reload_insn, insn);
7454 PUT_CODE (output_reload_insn, NOTE);
7455 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7456 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7460 /* We are going to delete DEAD_INSN. Recursively delete loads of
7461 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7462 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7464 delete_address_reloads (dead_insn, current_insn)
7465 rtx dead_insn, current_insn;
7467 rtx set = single_set (dead_insn);
7468 rtx set2, dst, prev, next;
7471 rtx dst = SET_DEST (set);
7472 if (GET_CODE (dst) == MEM)
7473 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7475 /* If we deleted the store from a reloaded post_{in,de}c expression,
7476 we can delete the matching adds. */
7477 prev = PREV_INSN (dead_insn);
7478 next = NEXT_INSN (dead_insn);
7479 if (! prev || ! next)
7481 set = single_set (next);
7482 set2 = single_set (prev);
7484 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7485 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7486 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7488 dst = SET_DEST (set);
7489 if (! rtx_equal_p (dst, SET_DEST (set2))
7490 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7491 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7492 || (INTVAL (XEXP (SET_SRC (set), 1))
7493 != - INTVAL (XEXP (SET_SRC (set2), 1))))
7499 /* Subfunction of delete_address_reloads: process registers found in X. */
7501 delete_address_reloads_1 (dead_insn, x, current_insn)
7502 rtx dead_insn, x, current_insn;
7504 rtx prev, set, dst, i2;
7506 enum rtx_code code = GET_CODE (x);
7510 const char *fmt= GET_RTX_FORMAT (code);
7511 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7514 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7515 else if (fmt[i] == 'E')
7517 for (j = XVECLEN (x, i) - 1; j >=0; j--)
7518 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7525 if (spill_reg_order[REGNO (x)] < 0)
7528 /* Scan backwards for the insn that sets x. This might be a way back due
7530 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7532 code = GET_CODE (prev);
7533 if (code == CODE_LABEL || code == JUMP_INSN)
7535 if (GET_RTX_CLASS (code) != 'i')
7537 if (reg_set_p (x, PATTERN (prev)))
7539 if (reg_referenced_p (x, PATTERN (prev)))
7542 if (! prev || INSN_UID (prev) < reload_first_uid)
7544 /* Check that PREV only sets the reload register. */
7545 set = single_set (prev);
7548 dst = SET_DEST (set);
7549 if (GET_CODE (dst) != REG
7550 || ! rtx_equal_p (dst, x))
7552 if (! reg_set_p (dst, PATTERN (dead_insn)))
7554 /* Check if DST was used in a later insn -
7555 it might have been inherited. */
7556 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7558 if (GET_CODE (i2) == CODE_LABEL)
7560 if (GET_RTX_CLASS (GET_CODE (i2)) != 'i')
7562 if (reg_referenced_p (dst, PATTERN (i2)))
7564 /* If there is a reference to the register in the current insn,
7565 it might be loaded in a non-inherited reload. If no other
7566 reload uses it, that means the register is set before
7568 if (i2 == current_insn)
7570 for (j = n_reloads - 1; j >= 0; j--)
7571 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7572 || reload_override_in[j] == dst)
7574 for (j = n_reloads - 1; j >= 0; j--)
7575 if (rld[j].in && rld[j].reg_rtx == dst)
7582 if (GET_CODE (i2) == JUMP_INSN)
7584 /* If DST is still live at CURRENT_INSN, check if it is used for
7585 any reload. Note that even if CURRENT_INSN sets DST, we still
7586 have to check the reloads. */
7587 if (i2 == current_insn)
7589 for (j = n_reloads - 1; j >= 0; j--)
7590 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7591 || reload_override_in[j] == dst)
7593 /* ??? We can't finish the loop here, because dst might be
7594 allocated to a pseudo in this block if no reload in this
7595 block needs any of the clsses containing DST - see
7596 spill_hard_reg. There is no easy way to tell this, so we
7597 have to scan till the end of the basic block. */
7599 if (reg_set_p (dst, PATTERN (i2)))
7603 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7604 reg_reloaded_contents[REGNO (dst)] = -1;
7605 /* Can't use delete_insn here because PREV might be a basic block head. */
7606 PUT_CODE (prev, NOTE);
7607 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
7608 NOTE_SOURCE_FILE (prev) = 0;
7611 /* Output reload-insns to reload VALUE into RELOADREG.
7612 VALUE is an autoincrement or autodecrement RTX whose operand
7613 is a register or memory location;
7614 so reloading involves incrementing that location.
7615 IN is either identical to VALUE, or some cheaper place to reload from.
7617 INC_AMOUNT is the number to increment or decrement by (always positive).
7618 This cannot be deduced from VALUE.
7620 Return the instruction that stores into RELOADREG. */
7623 inc_for_reload (reloadreg, in, value, inc_amount)
7628 /* REG or MEM to be copied and incremented. */
7629 rtx incloc = XEXP (value, 0);
7630 /* Nonzero if increment after copying. */
7631 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7637 rtx real_in = in == value ? XEXP (in, 0) : in;
7639 /* No hard register is equivalent to this register after
7640 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7641 we could inc/dec that register as well (maybe even using it for
7642 the source), but I'm not sure it's worth worrying about. */
7643 if (GET_CODE (incloc) == REG)
7644 reg_last_reload_reg[REGNO (incloc)] = 0;
7646 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7647 inc_amount = - inc_amount;
7649 inc = GEN_INT (inc_amount);
7651 /* If this is post-increment, first copy the location to the reload reg. */
7652 if (post && real_in != reloadreg)
7653 emit_insn (gen_move_insn (reloadreg, real_in));
7657 /* See if we can directly increment INCLOC. Use a method similar to
7658 that in gen_reload. */
7660 last = get_last_insn ();
7661 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7662 gen_rtx_PLUS (GET_MODE (incloc),
7665 code = recog_memoized (add_insn);
7668 extract_insn (add_insn);
7669 if (constrain_operands (1))
7671 /* If this is a pre-increment and we have incremented the value
7672 where it lives, copy the incremented value to RELOADREG to
7673 be used as an address. */
7676 emit_insn (gen_move_insn (reloadreg, incloc));
7681 delete_insns_since (last);
7684 /* If couldn't do the increment directly, must increment in RELOADREG.
7685 The way we do this depends on whether this is pre- or post-increment.
7686 For pre-increment, copy INCLOC to the reload register, increment it
7687 there, then save back. */
7691 if (in != reloadreg)
7692 emit_insn (gen_move_insn (reloadreg, real_in));
7693 emit_insn (gen_add2_insn (reloadreg, inc));
7694 store = emit_insn (gen_move_insn (incloc, reloadreg));
7699 Because this might be a jump insn or a compare, and because RELOADREG
7700 may not be available after the insn in an input reload, we must do
7701 the incrementation before the insn being reloaded for.
7703 We have already copied IN to RELOADREG. Increment the copy in
7704 RELOADREG, save that back, then decrement RELOADREG so it has
7705 the original value. */
7707 emit_insn (gen_add2_insn (reloadreg, inc));
7708 store = emit_insn (gen_move_insn (incloc, reloadreg));
7709 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7715 /* Return 1 if we are certain that the constraint-string STRING allows
7716 the hard register REG. Return 0 if we can't be sure of this. */
7719 constraint_accepts_reg_p (string, reg)
7724 int regno = true_regnum (reg);
7727 /* Initialize for first alternative. */
7729 /* Check that each alternative contains `g' or `r'. */
7731 switch (c = *string++)
7734 /* If an alternative lacks `g' or `r', we lose. */
7737 /* If an alternative lacks `g' or `r', we lose. */
7740 /* Initialize for next alternative. */
7745 /* Any general reg wins for this alternative. */
7746 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7750 /* Any reg in specified class wins for this alternative. */
7752 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7754 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
7760 /* Return the number of places FIND appears within X, but don't count
7761 an occurrence if some SET_DEST is FIND. */
7764 count_occurrences (x, find)
7765 register rtx x, find;
7768 register enum rtx_code code;
7769 register const char *format_ptr;
7777 code = GET_CODE (x);
7792 if (GET_CODE (find) == MEM && rtx_equal_p (x, find))
7796 if (SET_DEST (x) == find)
7797 return count_occurrences (SET_SRC (x), find);
7804 format_ptr = GET_RTX_FORMAT (code);
7807 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7809 switch (*format_ptr++)
7812 count += count_occurrences (XEXP (x, i), find);
7816 if (XVEC (x, i) != NULL)
7818 for (j = 0; j < XVECLEN (x, i); j++)
7819 count += count_occurrences (XVECEXP (x, i, j), find);
7827 /* This array holds values which are equivalent to a hard register
7828 during reload_cse_regs. Each array element is an EXPR_LIST of
7829 values. Each time a hard register is set, we set the corresponding
7830 array element to the value. Each time a hard register is copied
7831 into memory, we add the memory location to the corresponding array
7832 element. We don't store values or memory addresses with side
7833 effects in this array.
7835 If the value is a CONST_INT, then the mode of the containing
7836 EXPR_LIST is the mode in which that CONST_INT was referenced.
7838 We sometimes clobber a specific entry in a list. In that case, we
7839 just set XEXP (list-entry, 0) to 0. */
7841 static rtx *reg_values;
7843 /* This is a preallocated REG rtx which we use as a temporary in
7844 reload_cse_invalidate_regno, so that we don't need to allocate a
7845 new one each time through a loop in that function. */
7847 static rtx invalidate_regno_rtx;
7849 /* Invalidate any entries in reg_values which depend on REGNO,
7850 including those for REGNO itself. This is called if REGNO is
7851 changing. If CLOBBER is true, then always forget anything we
7852 currently know about REGNO. MODE is the mode of the assignment to
7853 REGNO, which is used to determine how many hard registers are being
7854 changed. If MODE is VOIDmode, then only REGNO is being changed;
7855 this is used when invalidating call clobbered registers across a
7859 reload_cse_invalidate_regno (regno, mode, clobber)
7861 enum machine_mode mode;
7867 /* Our callers don't always go through true_regnum; we may see a
7868 pseudo-register here from a CLOBBER or the like. We probably
7869 won't ever see a pseudo-register that has a real register number,
7870 for we check anyhow for safety. */
7871 if (regno >= FIRST_PSEUDO_REGISTER)
7872 regno = reg_renumber[regno];
7876 if (mode == VOIDmode)
7877 endregno = regno + 1;
7879 endregno = regno + HARD_REGNO_NREGS (regno, mode);
7882 for (i = regno; i < endregno; i++)
7885 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
7889 for (x = reg_values[i]; x; x = XEXP (x, 1))
7891 if (XEXP (x, 0) != 0
7892 && refers_to_regno_p (regno, endregno, XEXP (x, 0), NULL_PTR))
7894 /* If this is the only entry on the list, clear
7895 reg_values[i]. Otherwise, just clear this entry on
7897 if (XEXP (x, 1) == 0 && x == reg_values[i])
7907 /* We must look at earlier registers, in case REGNO is part of a
7908 multi word value but is not the first register. If an earlier
7909 register has a value in a mode which overlaps REGNO, then we must
7910 invalidate that earlier register. Note that we do not need to
7911 check REGNO or later registers (we must not check REGNO itself,
7912 because we would incorrectly conclude that there was a conflict). */
7914 for (i = 0; i < regno; i++)
7918 for (x = reg_values[i]; x; x = XEXP (x, 1))
7920 if (XEXP (x, 0) != 0)
7922 PUT_MODE (invalidate_regno_rtx, GET_MODE (x));
7923 REGNO (invalidate_regno_rtx) = i;
7924 if (refers_to_regno_p (regno, endregno, invalidate_regno_rtx,
7927 reload_cse_invalidate_regno (i, VOIDmode, 1);
7935 /* The memory at address MEM_BASE is being changed.
7936 Return whether this change will invalidate VAL. */
7939 reload_cse_mem_conflict_p (mem_base, val)
7947 code = GET_CODE (val);
7950 /* Get rid of a few simple cases quickly. */
7963 if (GET_MODE (mem_base) == BLKmode
7964 || GET_MODE (val) == BLKmode)
7966 if (anti_dependence (val, mem_base))
7968 /* The address may contain nested MEMs. */
7975 fmt = GET_RTX_FORMAT (code);
7977 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7981 if (reload_cse_mem_conflict_p (mem_base, XEXP (val, i)))
7984 else if (fmt[i] == 'E')
7988 for (j = 0; j < XVECLEN (val, i); j++)
7989 if (reload_cse_mem_conflict_p (mem_base, XVECEXP (val, i, j)))
7997 /* Invalidate any entries in reg_values which are changed because of a
7998 store to MEM_RTX. If this is called because of a non-const call
7999 instruction, MEM_RTX is (mem:BLK const0_rtx). */
8002 reload_cse_invalidate_mem (mem_rtx)
8007 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8011 for (x = reg_values[i]; x; x = XEXP (x, 1))
8013 if (XEXP (x, 0) != 0
8014 && reload_cse_mem_conflict_p (mem_rtx, XEXP (x, 0)))
8016 /* If this is the only entry on the list, clear
8017 reg_values[i]. Otherwise, just clear this entry on
8019 if (XEXP (x, 1) == 0 && x == reg_values[i])
8030 /* Invalidate DEST, which is being assigned to or clobbered. The
8031 second parameter exists so that this function can be passed to
8032 note_stores; it is ignored. */
8035 reload_cse_invalidate_rtx (dest, ignore, data)
8037 rtx ignore ATTRIBUTE_UNUSED;
8038 void *data ATTRIBUTE_UNUSED;
8040 while (GET_CODE (dest) == STRICT_LOW_PART
8041 || GET_CODE (dest) == SIGN_EXTRACT
8042 || GET_CODE (dest) == ZERO_EXTRACT
8043 || GET_CODE (dest) == SUBREG)
8044 dest = XEXP (dest, 0);
8046 if (GET_CODE (dest) == REG)
8047 reload_cse_invalidate_regno (REGNO (dest), GET_MODE (dest), 1);
8048 else if (GET_CODE (dest) == MEM)
8049 reload_cse_invalidate_mem (dest);
8052 /* Do a very simple CSE pass over the hard registers.
8054 This function detects no-op moves where we happened to assign two
8055 different pseudo-registers to the same hard register, and then
8056 copied one to the other. Reload will generate a useless
8057 instruction copying a register to itself.
8059 This function also detects cases where we load a value from memory
8060 into two different registers, and (if memory is more expensive than
8061 registers) changes it to simply copy the first register into the
8064 Another optimization is performed that scans the operands of each
8065 instruction to see whether the value is already available in a
8066 hard register. It then replaces the operand with the hard register
8067 if possible, much like an optional reload would. */
8070 reload_cse_regs_1 (first)
8078 init_alias_analysis ();
8080 reg_values = (rtx *) alloca (FIRST_PSEUDO_REGISTER * sizeof (rtx));
8081 bzero ((char *)reg_values, FIRST_PSEUDO_REGISTER * sizeof (rtx));
8083 /* Create our EXPR_LIST structures on reload_obstack, so that we can
8084 free them when we are done. */
8085 push_obstacks (&reload_obstack, &reload_obstack);
8086 firstobj = (char *) obstack_alloc (&reload_obstack, 0);
8088 /* We pass this to reload_cse_invalidate_mem to invalidate all of
8089 memory for a non-const call instruction. */
8090 callmem = gen_rtx_MEM (BLKmode, const0_rtx);
8092 /* This is used in reload_cse_invalidate_regno to avoid consing a
8093 new REG in a loop in that function. */
8094 invalidate_regno_rtx = gen_rtx_REG (VOIDmode, 0);
8096 for (insn = first; insn; insn = NEXT_INSN (insn))
8100 if (GET_CODE (insn) == CODE_LABEL)
8102 /* Forget all the register values at a code label. We don't
8103 try to do anything clever around jumps. */
8104 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8110 #ifdef NON_SAVING_SETJMP
8111 if (NON_SAVING_SETJMP && GET_CODE (insn) == NOTE
8112 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
8114 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8121 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8124 /* If this is a call instruction, forget anything stored in a
8125 call clobbered register, or, if this is not a const call, in
8127 if (GET_CODE (insn) == CALL_INSN)
8129 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8130 if (call_used_regs[i])
8131 reload_cse_invalidate_regno (i, VOIDmode, 1);
8133 if (! CONST_CALL_P (insn))
8134 reload_cse_invalidate_mem (callmem);
8138 /* Forget all the register values at a volatile asm. */
8139 if (GET_CODE (insn) == INSN
8140 && GET_CODE (PATTERN (insn)) == ASM_OPERANDS
8141 && MEM_VOLATILE_P (PATTERN (insn)))
8142 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8145 body = PATTERN (insn);
8146 if (GET_CODE (body) == SET)
8149 if (reload_cse_noop_set_p (body, insn))
8151 /* If this sets the return value of the function, we must keep
8152 a USE around, in case this is in a different basic block
8153 than the final USE. Otherwise, we could loose important
8154 register lifeness information on SMALL_REGISTER_CLASSES
8155 machines, where return registers might be used as spills:
8156 subsequent passes assume that spill registers are dead at
8157 the end of a basic block. */
8158 if (REG_FUNCTION_VALUE_P (SET_DEST (body)))
8161 PATTERN (insn) = gen_rtx_USE (VOIDmode, SET_DEST (body));
8162 INSN_CODE (insn) = -1;
8163 REG_NOTES (insn) = NULL_RTX;
8164 push_obstacks (&reload_obstack, &reload_obstack);
8168 PUT_CODE (insn, NOTE);
8169 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8170 NOTE_SOURCE_FILE (insn) = 0;
8173 /* We're done with this insn. */
8177 /* It's not a no-op, but we can try to simplify it. */
8178 count += reload_cse_simplify_set (body, insn);
8181 apply_change_group ();
8183 reload_cse_simplify_operands (insn);
8185 reload_cse_record_set (body, body);
8187 else if (GET_CODE (body) == PARALLEL)
8190 rtx value = NULL_RTX;
8192 /* If every action in a PARALLEL is a noop, we can delete
8193 the entire PARALLEL. */
8194 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8196 rtx part = XVECEXP (body, 0, i);
8197 if (GET_CODE (part) == SET)
8199 if (! reload_cse_noop_set_p (part, insn))
8201 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8205 value = SET_DEST (part);
8208 else if (GET_CODE (part) != CLOBBER)
8216 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
8217 INSN_CODE (insn) = -1;
8218 REG_NOTES (insn) = NULL_RTX;
8219 push_obstacks (&reload_obstack, &reload_obstack);
8223 PUT_CODE (insn, NOTE);
8224 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8225 NOTE_SOURCE_FILE (insn) = 0;
8228 /* We're done with this insn. */
8232 /* It's not a no-op, but we can try to simplify it. */
8233 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8234 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8235 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8238 apply_change_group ();
8240 reload_cse_simplify_operands (insn);
8242 /* Look through the PARALLEL and record the values being
8243 set, if possible. Also handle any CLOBBERs. */
8244 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8246 rtx x = XVECEXP (body, 0, i);
8248 if (GET_CODE (x) == SET)
8249 reload_cse_record_set (x, body);
8251 note_stores (x, reload_cse_invalidate_rtx, NULL);
8255 note_stores (body, reload_cse_invalidate_rtx, NULL);
8258 /* Clobber any registers which appear in REG_INC notes. We
8259 could keep track of the changes to their values, but it is
8260 unlikely to help. */
8264 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
8265 if (REG_NOTE_KIND (x) == REG_INC)
8266 reload_cse_invalidate_rtx (XEXP (x, 0), NULL_RTX, NULL);
8270 /* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only
8271 after we have processed the insn. */
8272 if (GET_CODE (insn) == CALL_INSN)
8276 for (x = CALL_INSN_FUNCTION_USAGE (insn); x; x = XEXP (x, 1))
8277 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
8278 reload_cse_invalidate_rtx (XEXP (XEXP (x, 0), 0), NULL_RTX,
8284 end_alias_analysis ();
8286 /* Free all the temporary structures we created, and go back to the
8287 regular obstacks. */
8288 obstack_free (&reload_obstack, firstobj);
8292 /* Call cse / combine like post-reload optimization phases.
8293 FIRST is the first instruction. */
8295 reload_cse_regs (first)
8298 reload_cse_regs_1 (first);
8300 reload_cse_move2add (first);
8301 if (flag_expensive_optimizations)
8302 reload_cse_regs_1 (first);
8305 /* Return whether the values known for REGNO are equal to VAL. MODE
8306 is the mode of the object that VAL is being copied to; this matters
8307 if VAL is a CONST_INT. */
8310 reload_cse_regno_equal_p (regno, val, mode)
8313 enum machine_mode mode;
8320 for (x = reg_values[regno]; x; x = XEXP (x, 1))
8321 if (XEXP (x, 0) != 0
8322 && rtx_equal_p (XEXP (x, 0), val)
8323 && (! flag_float_store || GET_CODE (XEXP (x, 0)) != MEM
8324 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
8325 && (GET_CODE (val) != CONST_INT
8326 || mode == GET_MODE (x)
8327 || (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8328 /* On a big endian machine if the value spans more than
8329 one register then this register holds the high part of
8330 it and we can't use it.
8332 ??? We should also compare with the high part of the
8334 && !(WORDS_BIG_ENDIAN
8335 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
8336 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
8337 GET_MODE_BITSIZE (GET_MODE (x))))))
8343 /* See whether a single set is a noop. SET is the set instruction we
8344 are should check, and INSN is the instruction from which it came. */
8347 reload_cse_noop_set_p (set, insn)
8349 rtx insn ATTRIBUTE_UNUSED;
8352 enum machine_mode dest_mode;
8356 src = SET_SRC (set);
8357 dest = SET_DEST (set);
8358 dest_mode = GET_MODE (dest);
8360 if (side_effects_p (src))
8363 dreg = true_regnum (dest);
8364 sreg = true_regnum (src);
8366 /* Check for setting a register to itself. In this case, we don't
8367 have to worry about REG_DEAD notes. */
8368 if (dreg >= 0 && dreg == sreg)
8374 /* Check for setting a register to itself. */
8378 /* Check for setting a register to a value which we already know
8379 is in the register. */
8380 else if (reload_cse_regno_equal_p (dreg, src, dest_mode))
8383 /* Check for setting a register DREG to another register SREG
8384 where SREG is equal to a value which is already in DREG. */
8389 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
8393 if (XEXP (x, 0) == 0)
8396 if (dest_mode == GET_MODE (x))
8398 else if (GET_MODE_BITSIZE (dest_mode)
8399 < GET_MODE_BITSIZE (GET_MODE (x)))
8400 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
8405 && reload_cse_regno_equal_p (dreg, tmp, dest_mode))
8413 else if (GET_CODE (dest) == MEM)
8415 /* Check for storing a register to memory when we know that the
8416 register is equivalent to the memory location. */
8418 && reload_cse_regno_equal_p (sreg, dest, dest_mode)
8419 && ! side_effects_p (dest))
8426 /* Try to simplify a single SET instruction. SET is the set pattern.
8427 INSN is the instruction it came from.
8428 This function only handles one case: if we set a register to a value
8429 which is not a register, we try to find that value in some other register
8430 and change the set into a register copy. */
8433 reload_cse_simplify_set (set, insn)
8439 enum machine_mode dest_mode;
8440 enum reg_class dclass;
8443 dreg = true_regnum (SET_DEST (set));
8447 src = SET_SRC (set);
8448 if (side_effects_p (src) || true_regnum (src) >= 0)
8451 dclass = REGNO_REG_CLASS (dreg);
8453 /* If memory loads are cheaper than register copies, don't change them. */
8454 if (GET_CODE (src) == MEM
8455 && MEMORY_MOVE_COST (GET_MODE (src), dclass, 1) < 2)
8458 /* If the constant is cheaper than a register, don't change it. */
8459 if (CONSTANT_P (src)
8460 && rtx_cost (src, SET) < 2)
8463 dest_mode = GET_MODE (SET_DEST (set));
8464 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8467 && REGISTER_MOVE_COST (REGNO_REG_CLASS (i), dclass) == 2
8468 && reload_cse_regno_equal_p (i, src, dest_mode))
8472 /* Pop back to the real obstacks while changing the insn. */
8475 validated = validate_change (insn, &SET_SRC (set),
8476 gen_rtx_REG (dest_mode, i), 1);
8478 /* Go back to the obstack we are using for temporary
8480 push_obstacks (&reload_obstack, &reload_obstack);
8489 /* Try to replace operands in INSN with equivalent values that are already
8490 in registers. This can be viewed as optional reloading.
8492 For each non-register operand in the insn, see if any hard regs are
8493 known to be equivalent to that operand. Record the alternatives which
8494 can accept these hard registers. Among all alternatives, select the
8495 ones which are better or equal to the one currently matching, where
8496 "better" is in terms of '?' and '!' constraints. Among the remaining
8497 alternatives, select the one which replaces most operands with
8501 reload_cse_simplify_operands (insn)
8506 const char *constraints[MAX_RECOG_OPERANDS];
8508 /* Vector recording how bad an alternative is. */
8509 int *alternative_reject;
8510 /* Vector recording how many registers can be introduced by choosing
8511 this alternative. */
8512 int *alternative_nregs;
8513 /* Array of vectors recording, for each operand and each alternative,
8514 which hard register to substitute, or -1 if the operand should be
8516 int *op_alt_regno[MAX_RECOG_OPERANDS];
8517 /* Array of alternatives, sorted in order of decreasing desirability. */
8518 int *alternative_order;
8519 rtx reg = gen_rtx_REG (VOIDmode, -1);
8521 extract_insn (insn);
8523 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8526 /* Figure out which alternative currently matches. */
8527 if (! constrain_operands (1))
8528 fatal_insn_not_found (insn);
8530 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8531 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8532 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8533 bzero ((char *)alternative_reject, recog_data.n_alternatives * sizeof (int));
8534 bzero ((char *)alternative_nregs, recog_data.n_alternatives * sizeof (int));
8536 for (i = 0; i < recog_data.n_operands; i++)
8538 enum machine_mode mode;
8542 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8543 for (j = 0; j < recog_data.n_alternatives; j++)
8544 op_alt_regno[i][j] = -1;
8546 p = constraints[i] = recog_data.constraints[i];
8547 mode = recog_data.operand_mode[i];
8549 /* Add the reject values for each alternative given by the constraints
8550 for this operand. */
8558 alternative_reject[j] += 3;
8560 alternative_reject[j] += 300;
8563 /* We won't change operands which are already registers. We
8564 also don't want to modify output operands. */
8565 regno = true_regnum (recog_data.operand[i]);
8567 || constraints[i][0] == '='
8568 || constraints[i][0] == '+')
8571 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8573 int class = (int) NO_REGS;
8575 if (! reload_cse_regno_equal_p (regno, recog_data.operand[i], mode))
8578 REGNO (reg) = regno;
8579 PUT_MODE (reg, mode);
8581 /* We found a register equal to this operand. Now look for all
8582 alternatives that can accept this register and have not been
8583 assigned a register they can use yet. */
8592 case '=': case '+': case '?':
8593 case '#': case '&': case '!':
8595 case '0': case '1': case '2': case '3': case '4':
8596 case '5': case '6': case '7': case '8': case '9':
8597 case 'm': case '<': case '>': case 'V': case 'o':
8598 case 'E': case 'F': case 'G': case 'H':
8599 case 's': case 'i': case 'n':
8600 case 'I': case 'J': case 'K': case 'L':
8601 case 'M': case 'N': case 'O': case 'P':
8602 #ifdef EXTRA_CONSTRAINT
8603 case 'Q': case 'R': case 'S': case 'T': case 'U':
8606 /* These don't say anything we care about. */
8610 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8615 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
8618 case ',': case '\0':
8619 /* See if REGNO fits this alternative, and set it up as the
8620 replacement register if we don't have one for this
8621 alternative yet and the operand being replaced is not
8622 a cheap CONST_INT. */
8623 if (op_alt_regno[i][j] == -1
8624 && reg_fits_class_p (reg, class, 0, mode)
8625 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8626 || (rtx_cost (recog_data.operand[i], SET)
8627 > rtx_cost (reg, SET))))
8629 alternative_nregs[j]++;
8630 op_alt_regno[i][j] = regno;
8642 /* Record all alternatives which are better or equal to the currently
8643 matching one in the alternative_order array. */
8644 for (i = j = 0; i < recog_data.n_alternatives; i++)
8645 if (alternative_reject[i] <= alternative_reject[which_alternative])
8646 alternative_order[j++] = i;
8647 recog_data.n_alternatives = j;
8649 /* Sort it. Given a small number of alternatives, a dumb algorithm
8650 won't hurt too much. */
8651 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8654 int best_reject = alternative_reject[alternative_order[i]];
8655 int best_nregs = alternative_nregs[alternative_order[i]];
8658 for (j = i + 1; j < recog_data.n_alternatives; j++)
8660 int this_reject = alternative_reject[alternative_order[j]];
8661 int this_nregs = alternative_nregs[alternative_order[j]];
8663 if (this_reject < best_reject
8664 || (this_reject == best_reject && this_nregs < best_nregs))
8667 best_reject = this_reject;
8668 best_nregs = this_nregs;
8672 tmp = alternative_order[best];
8673 alternative_order[best] = alternative_order[i];
8674 alternative_order[i] = tmp;
8677 /* Substitute the operands as determined by op_alt_regno for the best
8679 j = alternative_order[0];
8681 /* Pop back to the real obstacks while changing the insn. */
8684 for (i = 0; i < recog_data.n_operands; i++)
8686 enum machine_mode mode = recog_data.operand_mode[i];
8687 if (op_alt_regno[i][j] == -1)
8690 validate_change (insn, recog_data.operand_loc[i],
8691 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8694 for (i = recog_data.n_dups - 1; i >= 0; i--)
8696 int op = recog_data.dup_num[i];
8697 enum machine_mode mode = recog_data.operand_mode[op];
8699 if (op_alt_regno[op][j] == -1)
8702 validate_change (insn, recog_data.dup_loc[i],
8703 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8706 /* Go back to the obstack we are using for temporary
8708 push_obstacks (&reload_obstack, &reload_obstack);
8710 return apply_change_group ();
8713 /* These two variables are used to pass information from
8714 reload_cse_record_set to reload_cse_check_clobber. */
8716 static int reload_cse_check_clobbered;
8717 static rtx reload_cse_check_src;
8719 /* See if DEST overlaps with RELOAD_CSE_CHECK_SRC. If it does, set
8720 RELOAD_CSE_CHECK_CLOBBERED. This is called via note_stores. The
8721 second argument, which is passed by note_stores, is ignored. */
8724 reload_cse_check_clobber (dest, ignore, data)
8726 rtx ignore ATTRIBUTE_UNUSED;
8727 void *data ATTRIBUTE_UNUSED;
8729 if (reg_overlap_mentioned_p (dest, reload_cse_check_src))
8730 reload_cse_check_clobbered = 1;
8733 /* Record the result of a SET instruction. SET is the set pattern.
8734 BODY is the pattern of the insn that it came from. */
8737 reload_cse_record_set (set, body)
8743 enum machine_mode dest_mode;
8745 dest = SET_DEST (set);
8746 src = SET_SRC (set);
8747 dreg = true_regnum (dest);
8748 sreg = true_regnum (src);
8749 dest_mode = GET_MODE (dest);
8751 /* Some machines don't define AUTO_INC_DEC, but they still use push
8752 instructions. We need to catch that case here in order to
8753 invalidate the stack pointer correctly. Note that invalidating
8754 the stack pointer is different from invalidating DEST. */
8756 while (GET_CODE (x) == SUBREG
8757 || GET_CODE (x) == ZERO_EXTRACT
8758 || GET_CODE (x) == SIGN_EXTRACT
8759 || GET_CODE (x) == STRICT_LOW_PART)
8761 if (push_operand (x, GET_MODE (x)))
8763 reload_cse_invalidate_rtx (stack_pointer_rtx, NULL_RTX, NULL);
8764 reload_cse_invalidate_rtx (dest, NULL_RTX, NULL);
8768 /* We can only handle an assignment to a register, or a store of a
8769 register to a memory location. For other cases, we just clobber
8770 the destination. We also have to just clobber if there are side
8771 effects in SRC or DEST. */
8772 if ((dreg < 0 && GET_CODE (dest) != MEM)
8773 || side_effects_p (src)
8774 || side_effects_p (dest))
8776 reload_cse_invalidate_rtx (dest, NULL_RTX, NULL);
8781 /* We don't try to handle values involving CC, because it's a pain
8782 to keep track of when they have to be invalidated. */
8783 if (reg_mentioned_p (cc0_rtx, src)
8784 || reg_mentioned_p (cc0_rtx, dest))
8786 reload_cse_invalidate_rtx (dest, NULL_RTX, NULL);
8791 /* If BODY is a PARALLEL, then we need to see whether the source of
8792 SET is clobbered by some other instruction in the PARALLEL. */
8793 if (GET_CODE (body) == PARALLEL)
8797 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8801 x = XVECEXP (body, 0, i);
8805 reload_cse_check_clobbered = 0;
8806 reload_cse_check_src = src;
8807 note_stores (x, reload_cse_check_clobber, NULL);
8808 if (reload_cse_check_clobbered)
8810 reload_cse_invalidate_rtx (dest, NULL_RTX, NULL);
8820 /* This is an assignment to a register. Update the value we
8821 have stored for the register. */
8826 /* This is a copy from one register to another. Any values
8827 which were valid for SREG are now valid for DREG. If the
8828 mode changes, we use gen_lowpart_common to extract only
8829 the part of the value that is copied. */
8830 reg_values[dreg] = 0;
8831 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
8835 if (XEXP (x, 0) == 0)
8837 if (dest_mode == GET_MODE (XEXP (x, 0)))
8839 else if (GET_MODE_BITSIZE (dest_mode)
8840 > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
8843 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
8845 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, tmp,
8850 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, src, NULL_RTX);
8852 /* We've changed DREG, so invalidate any values held by other
8853 registers that depend upon it. */
8854 reload_cse_invalidate_regno (dreg, dest_mode, 0);
8856 /* If this assignment changes more than one hard register,
8857 forget anything we know about the others. */
8858 for (i = 1; i < HARD_REGNO_NREGS (dreg, dest_mode); i++)
8859 reg_values[dreg + i] = 0;
8861 else if (GET_CODE (dest) == MEM)
8863 /* Invalidate conflicting memory locations. */
8864 reload_cse_invalidate_mem (dest);
8866 /* If we're storing a register to memory, add DEST to the list
8868 if (sreg >= 0 && ! side_effects_p (dest))
8869 reg_values[sreg] = gen_rtx_EXPR_LIST (dest_mode, dest,
8874 /* We should have bailed out earlier. */
8879 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8881 This code might also be useful when reload gave up on reg+reg addresssing
8882 because of clashes between the return register and INDEX_REG_CLASS. */
8884 /* The maximum number of uses of a register we can keep track of to
8885 replace them with reg+reg addressing. */
8886 #define RELOAD_COMBINE_MAX_USES 6
8888 /* INSN is the insn where a register has ben used, and USEP points to the
8889 location of the register within the rtl. */
8890 struct reg_use { rtx insn, *usep; };
8892 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8893 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8894 indicates where it becomes live again.
8895 Otherwise, USE_INDEX is the index of the last encountered use of the
8896 register (which is first among these we have seen since we scan backwards),
8897 OFFSET contains the constant offset that is added to the register in
8898 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8899 last, of these uses.
8900 STORE_RUID is always meaningful if we only want to use a value in a
8901 register in a different place: it denotes the next insn in the insn
8902 stream (i.e. the last ecountered) that sets or clobbers the register. */
8905 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8910 } reg_state[FIRST_PSEUDO_REGISTER];
8912 /* Reverse linear uid. This is increased in reload_combine while scanning
8913 the instructions from last to first. It is used to set last_label_ruid
8914 and the store_ruid / use_ruid fields in reg_state. */
8915 static int reload_combine_ruid;
8917 #define LABEL_LIVE(LABEL) \
8918 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8924 int first_index_reg = 1, last_index_reg = 0;
8926 int last_label_ruid;
8927 int min_labelno, n_labels;
8928 HARD_REG_SET ever_live_at_start, *label_live;
8930 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
8931 reload has already used it where appropriate, so there is no use in
8932 trying to generate it now. */
8933 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8936 /* To avoid wasting too much time later searching for an index register,
8937 determine the minimum and maximum index register numbers. */
8938 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8940 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i))
8942 if (! last_index_reg)
8944 first_index_reg = i;
8947 /* If no index register is available, we can quit now. */
8948 if (first_index_reg > last_index_reg)
8951 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8952 information is a bit fuzzy immediately after reload, but it's
8953 still good enough to determine which registers are live at a jump
8955 min_labelno = get_first_label_num ();
8956 n_labels = max_label_num () - min_labelno;
8957 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8958 CLEAR_HARD_REG_SET (ever_live_at_start);
8959 for (i = n_basic_blocks - 1; i >= 0; i--)
8961 insn = BLOCK_HEAD (i);
8962 if (GET_CODE (insn) == CODE_LABEL)
8966 REG_SET_TO_HARD_REG_SET (live, BASIC_BLOCK (i)->global_live_at_start);
8967 compute_use_by_pseudos (&live, BASIC_BLOCK (i)->global_live_at_start);
8968 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8969 IOR_HARD_REG_SET (ever_live_at_start, live);
8973 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8974 last_label_ruid = reload_combine_ruid = 0;
8975 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8977 reg_state[i].store_ruid = reload_combine_ruid;
8979 reg_state[i].use_index = -1;
8981 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8984 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8988 /* We cannot do our optimization across labels. Invalidating all the use
8989 information we have would be costly, so we just note where the label
8990 is and then later disable any optimization that would cross it. */
8991 if (GET_CODE (insn) == CODE_LABEL)
8992 last_label_ruid = reload_combine_ruid;
8993 if (GET_CODE (insn) == BARRIER)
8995 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8996 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8998 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
9000 reload_combine_ruid++;
9002 /* Look for (set (REGX) (CONST_INT))
9003 (set (REGX) (PLUS (REGX) (REGY)))
9005 ... (MEM (REGX)) ...
9007 (set (REGZ) (CONST_INT))
9009 ... (MEM (PLUS (REGZ) (REGY)))... .
9011 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
9012 and that we know all uses of REGX before it dies. */
9013 set = single_set (insn);
9015 && GET_CODE (SET_DEST (set)) == REG
9016 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
9017 GET_MODE (SET_DEST (set)))
9019 && GET_CODE (SET_SRC (set)) == PLUS
9020 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
9021 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
9022 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
9024 rtx reg = SET_DEST (set);
9025 rtx plus = SET_SRC (set);
9026 rtx base = XEXP (plus, 1);
9027 rtx prev = prev_nonnote_insn (insn);
9028 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
9029 int regno = REGNO (reg);
9030 rtx const_reg = NULL_RTX;
9031 rtx reg_sum = NULL_RTX;
9033 /* Now, we need an index register.
9034 We'll set index_reg to this index register, const_reg to the
9035 register that is to be loaded with the constant
9036 (denoted as REGZ in the substitution illustration above),
9037 and reg_sum to the register-register that we want to use to
9038 substitute uses of REG (typically in MEMs) with.
9039 First check REG and BASE for being index registers;
9040 we can use them even if they are not dead. */
9041 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
9042 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
9050 /* Otherwise, look for a free index register. Since we have
9051 checked above that neiter REG nor BASE are index registers,
9052 if we find anything at all, it will be different from these
9054 for (i = first_index_reg; i <= last_index_reg; i++)
9056 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
9057 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
9058 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
9059 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
9061 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
9062 const_reg = index_reg;
9063 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
9068 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
9069 (REGY), i.e. BASE, is not clobbered before the last use we'll
9072 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
9073 && rtx_equal_p (SET_DEST (prev_set), reg)
9074 && reg_state[regno].use_index >= 0
9075 && reg_state[REGNO (base)].store_ruid <= reg_state[regno].use_ruid
9080 /* Change destination register and - if necessary - the
9081 constant value in PREV, the constant loading instruction. */
9082 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
9083 if (reg_state[regno].offset != const0_rtx)
9084 validate_change (prev,
9085 &SET_SRC (prev_set),
9086 GEN_INT (INTVAL (SET_SRC (prev_set))
9087 + INTVAL (reg_state[regno].offset)),
9089 /* Now for every use of REG that we have recorded, replace REG
9091 for (i = reg_state[regno].use_index;
9092 i < RELOAD_COMBINE_MAX_USES; i++)
9093 validate_change (reg_state[regno].reg_use[i].insn,
9094 reg_state[regno].reg_use[i].usep,
9097 if (apply_change_group ())
9101 /* Delete the reg-reg addition. */
9102 PUT_CODE (insn, NOTE);
9103 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9104 NOTE_SOURCE_FILE (insn) = 0;
9106 if (reg_state[regno].offset != const0_rtx)
9108 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
9110 for (np = ®_NOTES (prev); *np; )
9112 if (REG_NOTE_KIND (*np) == REG_EQUAL
9113 || REG_NOTE_KIND (*np) == REG_EQUIV)
9114 *np = XEXP (*np, 1);
9116 np = &XEXP (*np, 1);
9119 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9120 reg_state[REGNO (const_reg)].store_ruid = reload_combine_ruid;
9125 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
9126 if (GET_CODE (insn) == CALL_INSN)
9130 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9132 if (call_used_regs[i])
9134 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9135 reg_state[i].store_ruid = reload_combine_ruid;
9138 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
9139 link = XEXP (link, 1))
9141 rtx use = XEXP (link, 0);
9142 int regno = REGNO (XEXP (use, 0));
9143 if (GET_CODE (use) == CLOBBER)
9145 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9146 reg_state[regno].store_ruid = reload_combine_ruid;
9149 reg_state[regno].use_index = -1;
9152 if (GET_CODE (insn) == JUMP_INSN && GET_CODE (PATTERN (insn)) != RETURN)
9154 /* Non-spill registers might be used at the call destination in
9155 some unknown fashion, so we have to mark the unknown use. */
9157 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
9158 && JUMP_LABEL (insn))
9159 live = &LABEL_LIVE (JUMP_LABEL (insn));
9161 live = &ever_live_at_start;
9162 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9164 if (TEST_HARD_REG_BIT (*live, i))
9165 reg_state[i].use_index = -1;
9168 reload_combine_note_use (&PATTERN (insn), insn);
9169 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9171 if (REG_NOTE_KIND (note) == REG_INC
9172 && GET_CODE (XEXP (note, 0)) == REG)
9174 int regno = REGNO (XEXP (note, 0));
9176 reg_state[regno].store_ruid = reload_combine_ruid;
9177 reg_state[regno].use_index = -1;
9184 /* Check if DST is a register or a subreg of a register; if it is,
9185 update reg_state[regno].store_ruid and reg_state[regno].use_index
9186 accordingly. Called via note_stores from reload_combine. */
9188 reload_combine_note_store (dst, set, data)
9190 void *data ATTRIBUTE_UNUSED;
9194 enum machine_mode mode = GET_MODE (dst);
9196 if (GET_CODE (dst) == SUBREG)
9198 regno = SUBREG_WORD (dst);
9199 dst = SUBREG_REG (dst);
9201 if (GET_CODE (dst) != REG)
9203 regno += REGNO (dst);
9205 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
9206 careful with registers / register parts that are not full words.
9208 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
9209 if (GET_CODE (set) != SET
9210 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
9211 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
9212 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
9214 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
9216 reg_state[i].use_index = -1;
9217 reg_state[i].store_ruid = reload_combine_ruid;
9222 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
9224 reg_state[i].store_ruid = reload_combine_ruid;
9225 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9230 /* XP points to a piece of rtl that has to be checked for any uses of
9232 *XP is the pattern of INSN, or a part of it.
9233 Called from reload_combine, and recursively by itself. */
9235 reload_combine_note_use (xp, insn)
9239 enum rtx_code code = x->code;
9242 rtx offset = const0_rtx; /* For the REG case below. */
9247 if (GET_CODE (SET_DEST (x)) == REG)
9249 reload_combine_note_use (&SET_SRC (x), insn);
9255 if (GET_CODE (SET_DEST (x)) == REG)
9260 /* We are interested in (plus (reg) (const_int)) . */
9261 if (GET_CODE (XEXP (x, 0)) != REG || GET_CODE (XEXP (x, 1)) != CONST_INT)
9263 offset = XEXP (x, 1);
9268 int regno = REGNO (x);
9271 /* Some spurious USEs of pseudo registers might remain.
9272 Just ignore them. */
9273 if (regno >= FIRST_PSEUDO_REGISTER)
9276 /* If this register is already used in some unknown fashion, we
9278 If we decrement the index from zero to -1, we can't store more
9279 uses, so this register becomes used in an unknown fashion. */
9280 use_index = --reg_state[regno].use_index;
9284 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
9286 /* We have found another use for a register that is already
9287 used later. Check if the offsets match; if not, mark the
9288 register as used in an unknown fashion. */
9289 if (! rtx_equal_p (offset, reg_state[regno].offset))
9291 reg_state[regno].use_index = -1;
9297 /* This is the first use of this register we have seen since we
9298 marked it as dead. */
9299 reg_state[regno].offset = offset;
9300 reg_state[regno].use_ruid = reload_combine_ruid;
9302 reg_state[regno].reg_use[use_index].insn = insn;
9303 reg_state[regno].reg_use[use_index].usep = xp;
9311 /* Recursively process the components of X. */
9312 fmt = GET_RTX_FORMAT (code);
9313 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9316 reload_combine_note_use (&XEXP (x, i), insn);
9317 else if (fmt[i] == 'E')
9319 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9320 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9325 /* See if we can reduce the cost of a constant by replacing a move with
9327 /* We cannot do our optimization across labels. Invalidating all the
9328 information about register contents we have would be costly, so we
9329 use last_label_luid (local variable of reload_cse_move2add) to note
9330 where the label is and then later disable any optimization that would
9332 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9333 reg_set_luid[n] is larger than last_label_luid[n] . */
9334 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9335 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
9336 reg_mode[n] to be valid.
9337 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
9338 has been set to reg_offset[n] in mode reg_mode[n] .
9339 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
9340 register n has been set to the sum of reg_offset[n] and register
9341 reg_base_reg[n], calculated in mode reg_mode[n] . */
9342 static rtx reg_offset[FIRST_PSEUDO_REGISTER];
9343 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9344 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9345 /* move2add_luid is linearily increased while scanning the instructions
9346 from first to last. It is used to set reg_set_luid in
9347 reload_cse_move2add and move2add_note_store. */
9348 static int move2add_luid;
9350 /* Generate a CONST_INT and force it in the range of MODE. */
9352 gen_mode_int (mode, value)
9353 enum machine_mode mode;
9354 HOST_WIDE_INT value;
9356 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
9357 int width = GET_MODE_BITSIZE (mode);
9359 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
9361 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
9362 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
9363 cval |= (HOST_WIDE_INT) -1 << width;
9365 return GEN_INT (cval);
9369 reload_cse_move2add (first)
9374 int last_label_luid;
9376 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
9377 reg_set_luid[i] = 0;
9379 last_label_luid = 0;
9381 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9385 if (GET_CODE (insn) == CODE_LABEL)
9386 last_label_luid = move2add_luid;
9387 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
9389 pat = PATTERN (insn);
9390 /* For simplicity, we only perform this optimization on
9391 straightforward SETs. */
9392 if (GET_CODE (pat) == SET
9393 && GET_CODE (SET_DEST (pat)) == REG)
9395 rtx reg = SET_DEST (pat);
9396 int regno = REGNO (reg);
9397 rtx src = SET_SRC (pat);
9399 /* Check if we have valid information on the contents of this
9400 register in the mode of REG. */
9401 /* ??? We don't know how zero / sign extension is handled, hence
9402 we can't go from a narrower to a wider mode. */
9403 if (reg_set_luid[regno] > last_label_luid
9404 && (GET_MODE_SIZE (GET_MODE (reg))
9405 <= GET_MODE_SIZE (reg_mode[regno]))
9406 && GET_CODE (reg_offset[regno]) == CONST_INT)
9408 /* Try to transform (set (REGX) (CONST_INT A))
9410 (set (REGX) (CONST_INT B))
9412 (set (REGX) (CONST_INT A))
9414 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9416 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9420 = gen_mode_int (GET_MODE (reg),
9421 INTVAL (src) - INTVAL (reg_offset[regno]));
9422 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9423 use (set (reg) (reg)) instead.
9424 We don't delete this insn, nor do we convert it into a
9425 note, to avoid losing register notes or the return
9426 value flag. jump2 already knowns how to get rid of
9428 if (new_src == const0_rtx)
9429 success = validate_change (insn, &SET_SRC (pat), reg, 0);
9430 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9431 && have_add2_insn (GET_MODE (reg)))
9432 success = validate_change (insn, &PATTERN (insn),
9433 gen_add2_insn (reg, new_src), 0);
9434 reg_set_luid[regno] = move2add_luid;
9435 reg_mode[regno] = GET_MODE (reg);
9436 reg_offset[regno] = src;
9440 /* Try to transform (set (REGX) (REGY))
9441 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9444 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9447 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9449 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9450 else if (GET_CODE (src) == REG
9451 && reg_base_reg[regno] == REGNO (src)
9452 && reg_set_luid[regno] > reg_set_luid[REGNO (src)])
9454 rtx next = next_nonnote_insn (insn);
9457 set = single_set (next);
9460 && SET_DEST (set) == reg
9461 && GET_CODE (SET_SRC (set)) == PLUS
9462 && XEXP (SET_SRC (set), 0) == reg
9463 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9465 rtx src3 = XEXP (SET_SRC (set), 1);
9467 = gen_mode_int (GET_MODE (reg),
9469 - INTVAL (reg_offset[regno]));
9472 if (new_src == const0_rtx)
9473 /* See above why we create (set (reg) (reg)) here. */
9475 = validate_change (next, &SET_SRC (set), reg, 0);
9476 else if ((rtx_cost (new_src, PLUS)
9477 < 2 + rtx_cost (src3, SET))
9478 && have_add2_insn (GET_MODE (reg)))
9480 = validate_change (next, &PATTERN (next),
9481 gen_add2_insn (reg, new_src), 0);
9484 /* INSN might be the first insn in a basic block
9485 if the preceding insn is a conditional jump
9486 or a possible-throwing call. */
9487 PUT_CODE (insn, NOTE);
9488 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9489 NOTE_SOURCE_FILE (insn) = 0;
9492 reg_set_luid[regno] = move2add_luid;
9493 reg_mode[regno] = GET_MODE (reg);
9494 reg_offset[regno] = src3;
9501 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9503 if (REG_NOTE_KIND (note) == REG_INC
9504 && GET_CODE (XEXP (note, 0)) == REG)
9506 /* Indicate that this register has been recently written to,
9507 but the exact contents are not available. */
9508 int regno = REGNO (XEXP (note, 0));
9509 if (regno < FIRST_PSEUDO_REGISTER)
9511 reg_set_luid[regno] = move2add_luid;
9512 reg_offset[regno] = note;
9516 note_stores (PATTERN (insn), move2add_note_store, NULL);
9517 /* If this is a CALL_INSN, all call used registers are stored with
9519 if (GET_CODE (insn) == CALL_INSN)
9521 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
9523 if (call_used_regs[i])
9525 reg_set_luid[i] = move2add_luid;
9526 reg_offset[i] = insn; /* Invalidate contents. */
9533 /* SET is a SET or CLOBBER that sets DST.
9534 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9535 Called from reload_cse_move2add via note_stores. */
9537 move2add_note_store (dst, set, data)
9539 void *data ATTRIBUTE_UNUSED;
9544 enum machine_mode mode = GET_MODE (dst);
9545 if (GET_CODE (dst) == SUBREG)
9547 regno = SUBREG_WORD (dst);
9548 dst = SUBREG_REG (dst);
9550 if (GET_CODE (dst) != REG)
9553 regno += REGNO (dst);
9555 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9556 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9557 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9558 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9560 rtx src = SET_SRC (set);
9562 reg_mode[regno] = mode;
9563 switch (GET_CODE (src))
9567 rtx src0 = XEXP (src, 0);
9568 if (GET_CODE (src0) == REG)
9570 if (REGNO (src0) != regno
9571 || reg_offset[regno] != const0_rtx)
9573 reg_base_reg[regno] = REGNO (src0);
9574 reg_set_luid[regno] = move2add_luid;
9576 reg_offset[regno] = XEXP (src, 1);
9579 reg_set_luid[regno] = move2add_luid;
9580 reg_offset[regno] = set; /* Invalidate contents. */
9585 reg_base_reg[regno] = REGNO (SET_SRC (set));
9586 reg_offset[regno] = const0_rtx;
9587 reg_set_luid[regno] = move2add_luid;
9591 reg_base_reg[regno] = -1;
9592 reg_offset[regno] = SET_SRC (set);
9593 reg_set_luid[regno] = move2add_luid;
9599 for (i = regno + HARD_REGNO_NREGS (regno, mode) - 1; i >= regno; i--)
9601 /* Indicate that this register has been recently written to,
9602 but the exact contents are not available. */
9603 reg_set_luid[i] = move2add_luid;
9604 reg_offset[i] = dst;
9611 add_auto_inc_notes (insn, x)
9615 enum rtx_code code = GET_CODE (x);
9619 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9622 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9626 /* Scan all the operand sub-expressions. */
9627 fmt = GET_RTX_FORMAT (code);
9628 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9631 add_auto_inc_notes (insn, XEXP (x, i));
9632 else if (fmt[i] == 'E')
9633 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9634 add_auto_inc_notes (insn, XVECEXP (x, i, j));
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