1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
82 #define LOCAL_REGNO(REGNO) 0
85 /* During reload_as_needed, element N contains a REG rtx for the hard reg
86 into which reg N has been reloaded (perhaps for a previous insn). */
87 static rtx *reg_last_reload_reg;
89 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
90 for an output reload that stores into reg N. */
91 static char *reg_has_output_reload;
93 /* Indicates which hard regs are reload-registers for an output reload
94 in the current insn. */
95 static HARD_REG_SET reg_is_output_reload;
97 /* Element N is the constant value to which pseudo reg N is equivalent,
98 or zero if pseudo reg N is not equivalent to a constant.
99 find_reloads looks at this in order to replace pseudo reg N
100 with the constant it stands for. */
101 rtx *reg_equiv_constant;
103 /* Element N is a memory location to which pseudo reg N is equivalent,
104 prior to any register elimination (such as frame pointer to stack
105 pointer). Depending on whether or not it is a valid address, this value
106 is transferred to either reg_equiv_address or reg_equiv_mem. */
107 rtx *reg_equiv_memory_loc;
109 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
110 This is used when the address is not valid as a memory address
111 (because its displacement is too big for the machine.) */
112 rtx *reg_equiv_address;
114 /* Element N is the memory slot to which pseudo reg N is equivalent,
115 or zero if pseudo reg N is not equivalent to a memory slot. */
118 /* Widest width in which each pseudo reg is referred to (via subreg). */
119 static unsigned int *reg_max_ref_width;
121 /* Element N is the list of insns that initialized reg N from its equivalent
122 constant or memory slot. */
123 static rtx *reg_equiv_init;
125 /* Vector to remember old contents of reg_renumber before spilling. */
126 static short *reg_old_renumber;
128 /* During reload_as_needed, element N contains the last pseudo regno reloaded
129 into hard register N. If that pseudo reg occupied more than one register,
130 reg_reloaded_contents points to that pseudo for each spill register in
131 use; all of these must remain set for an inheritance to occur. */
132 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
134 /* During reload_as_needed, element N contains the insn for which
135 hard register N was last used. Its contents are significant only
136 when reg_reloaded_valid is set for this register. */
137 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
139 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
140 static HARD_REG_SET reg_reloaded_valid;
141 /* Indicate if the register was dead at the end of the reload.
142 This is only valid if reg_reloaded_contents is set and valid. */
143 static HARD_REG_SET reg_reloaded_dead;
145 /* Number of spill-regs so far; number of valid elements of spill_regs. */
148 /* In parallel with spill_regs, contains REG rtx's for those regs.
149 Holds the last rtx used for any given reg, or 0 if it has never
150 been used for spilling yet. This rtx is reused, provided it has
152 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
154 /* In parallel with spill_regs, contains nonzero for a spill reg
155 that was stored after the last time it was used.
156 The precise value is the insn generated to do the store. */
157 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
159 /* This is the register that was stored with spill_reg_store. This is a
160 copy of reload_out / reload_out_reg when the value was stored; if
161 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
162 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
164 /* This table is the inverse mapping of spill_regs:
165 indexed by hard reg number,
166 it contains the position of that reg in spill_regs,
167 or -1 for something that is not in spill_regs.
169 ?!? This is no longer accurate. */
170 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
172 /* This reg set indicates registers that can't be used as spill registers for
173 the currently processed insn. These are the hard registers which are live
174 during the insn, but not allocated to pseudos, as well as fixed
176 static HARD_REG_SET bad_spill_regs;
178 /* These are the hard registers that can't be used as spill register for any
179 insn. This includes registers used for user variables and registers that
180 we can't eliminate. A register that appears in this set also can't be used
181 to retry register allocation. */
182 static HARD_REG_SET bad_spill_regs_global;
184 /* Describes order of use of registers for reloading
185 of spilled pseudo-registers. `n_spills' is the number of
186 elements that are actually valid; new ones are added at the end.
188 Both spill_regs and spill_reg_order are used on two occasions:
189 once during find_reload_regs, where they keep track of the spill registers
190 for a single insn, but also during reload_as_needed where they show all
191 the registers ever used by reload. For the latter case, the information
192 is calculated during finish_spills. */
193 static short spill_regs[FIRST_PSEUDO_REGISTER];
195 /* This vector of reg sets indicates, for each pseudo, which hard registers
196 may not be used for retrying global allocation because the register was
197 formerly spilled from one of them. If we allowed reallocating a pseudo to
198 a register that it was already allocated to, reload might not
200 static HARD_REG_SET *pseudo_previous_regs;
202 /* This vector of reg sets indicates, for each pseudo, which hard
203 registers may not be used for retrying global allocation because they
204 are used as spill registers during one of the insns in which the
206 static HARD_REG_SET *pseudo_forbidden_regs;
208 /* All hard regs that have been used as spill registers for any insn are
209 marked in this set. */
210 static HARD_REG_SET used_spill_regs;
212 /* Index of last register assigned as a spill register. We allocate in
213 a round-robin fashion. */
214 static int last_spill_reg;
216 /* Nonzero if indirect addressing is supported on the machine; this means
217 that spilling (REG n) does not require reloading it into a register in
218 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
219 value indicates the level of indirect addressing supported, e.g., two
220 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
222 static char spill_indirect_levels;
224 /* Nonzero if indirect addressing is supported when the innermost MEM is
225 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
226 which these are valid is the same as spill_indirect_levels, above. */
227 char indirect_symref_ok;
229 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
230 char double_reg_address_ok;
232 /* Record the stack slot for each spilled hard register. */
233 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
235 /* Width allocated so far for that stack slot. */
236 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
238 /* Record which pseudos needed to be spilled. */
239 static regset_head spilled_pseudos;
241 /* Used for communication between order_regs_for_reload and count_pseudo.
242 Used to avoid counting one pseudo twice. */
243 static regset_head pseudos_counted;
245 /* First uid used by insns created by reload in this function.
246 Used in find_equiv_reg. */
247 int reload_first_uid;
249 /* Flag set by local-alloc or global-alloc if anything is live in
250 a call-clobbered reg across calls. */
251 int caller_save_needed;
253 /* Set to 1 while reload_as_needed is operating.
254 Required by some machines to handle any generated moves differently. */
255 int reload_in_progress = 0;
257 /* These arrays record the insn_code of insns that may be needed to
258 perform input and output reloads of special objects. They provide a
259 place to pass a scratch register. */
260 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
261 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
263 /* This obstack is used for allocation of rtl during register elimination.
264 The allocated storage can be freed once find_reloads has processed the
266 struct obstack reload_obstack;
268 /* Points to the beginning of the reload_obstack. All insn_chain structures
269 are allocated first. */
270 char *reload_startobj;
272 /* The point after all insn_chain structures. Used to quickly deallocate
273 memory allocated in copy_reloads during calculate_needs_all_insns. */
274 char *reload_firstobj;
276 /* This points before all local rtl generated by register elimination.
277 Used to quickly free all memory after processing one insn. */
278 static char *reload_insn_firstobj;
280 /* List of insn_chain instructions, one for every insn that reload needs to
282 struct insn_chain *reload_insn_chain;
284 /* List of all insns needing reloads. */
285 static struct insn_chain *insns_need_reload;
287 /* This structure is used to record information about register eliminations.
288 Each array entry describes one possible way of eliminating a register
289 in favor of another. If there is more than one way of eliminating a
290 particular register, the most preferred should be specified first. */
294 int from; /* Register number to be eliminated. */
295 int to; /* Register number used as replacement. */
296 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
297 int can_eliminate; /* Nonzero if this elimination can be done. */
298 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
299 insns made by reload. */
300 HOST_WIDE_INT offset; /* Current offset between the two regs. */
301 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
302 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
303 rtx from_rtx; /* REG rtx for the register to be eliminated.
304 We cannot simply compare the number since
305 we might then spuriously replace a hard
306 register corresponding to a pseudo
307 assigned to the reg to be eliminated. */
308 rtx to_rtx; /* REG rtx for the replacement. */
311 static struct elim_table *reg_eliminate = 0;
313 /* This is an intermediate structure to initialize the table. It has
314 exactly the members provided by ELIMINABLE_REGS. */
315 static const struct elim_table_1
319 } reg_eliminate_1[] =
321 /* If a set of eliminable registers was specified, define the table from it.
322 Otherwise, default to the normal case of the frame pointer being
323 replaced by the stack pointer. */
325 #ifdef ELIMINABLE_REGS
328 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
331 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
333 /* Record the number of pending eliminations that have an offset not equal
334 to their initial offset. If nonzero, we use a new copy of each
335 replacement result in any insns encountered. */
336 int num_not_at_initial_offset;
338 /* Count the number of registers that we may be able to eliminate. */
339 static int num_eliminable;
340 /* And the number of registers that are equivalent to a constant that
341 can be eliminated to frame_pointer / arg_pointer + constant. */
342 static int num_eliminable_invariants;
344 /* For each label, we record the offset of each elimination. If we reach
345 a label by more than one path and an offset differs, we cannot do the
346 elimination. This information is indexed by the difference of the
347 number of the label and the first label number. We can't offset the
348 pointer itself as this can cause problems on machines with segmented
349 memory. The first table is an array of flags that records whether we
350 have yet encountered a label and the second table is an array of arrays,
351 one entry in the latter array for each elimination. */
353 static int first_label_num;
354 static char *offsets_known_at;
355 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
357 /* Number of labels in the current function. */
359 static int num_labels;
361 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
362 static void maybe_fix_stack_asms (void);
363 static void copy_reloads (struct insn_chain *);
364 static void calculate_needs_all_insns (int);
365 static int find_reg (struct insn_chain *, int);
366 static void find_reload_regs (struct insn_chain *);
367 static void select_reload_regs (void);
368 static void delete_caller_save_insns (void);
370 static void spill_failure (rtx, enum reg_class);
371 static void count_spilled_pseudo (int, int, int);
372 static void delete_dead_insn (rtx);
373 static void alter_reg (int, int);
374 static void set_label_offsets (rtx, rtx, int);
375 static void check_eliminable_occurrences (rtx);
376 static void elimination_effects (rtx, enum machine_mode);
377 static int eliminate_regs_in_insn (rtx, int);
378 static void update_eliminable_offsets (void);
379 static void mark_not_eliminable (rtx, rtx, void *);
380 static void set_initial_elim_offsets (void);
381 static void verify_initial_elim_offsets (void);
382 static void set_initial_label_offsets (void);
383 static void set_offsets_for_label (rtx);
384 static void init_elim_table (void);
385 static void update_eliminables (HARD_REG_SET *);
386 static void spill_hard_reg (unsigned int, int);
387 static int finish_spills (int);
388 static void ior_hard_reg_set (HARD_REG_SET *, HARD_REG_SET *);
389 static void scan_paradoxical_subregs (rtx);
390 static void count_pseudo (int);
391 static void order_regs_for_reload (struct insn_chain *);
392 static void reload_as_needed (int);
393 static void forget_old_reloads_1 (rtx, rtx, void *);
394 static int reload_reg_class_lower (const void *, const void *);
395 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
397 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
399 static int reload_reg_free_p (unsigned int, int, enum reload_type);
400 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
402 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
404 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
405 static int allocate_reload_reg (struct insn_chain *, int, int);
406 static int conflicts_with_override (rtx);
407 static void failed_reload (rtx, int);
408 static int set_reload_reg (int, int);
409 static void choose_reload_regs_init (struct insn_chain *, rtx *);
410 static void choose_reload_regs (struct insn_chain *);
411 static void merge_assigned_reloads (rtx);
412 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
414 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
416 static void do_input_reload (struct insn_chain *, struct reload *, int);
417 static void do_output_reload (struct insn_chain *, struct reload *, int);
418 static void emit_reload_insns (struct insn_chain *);
419 static void delete_output_reload (rtx, int, int);
420 static void delete_address_reloads (rtx, rtx);
421 static void delete_address_reloads_1 (rtx, rtx, rtx);
422 static rtx inc_for_reload (rtx, rtx, rtx, int);
424 static void add_auto_inc_notes (rtx, rtx);
426 static void copy_eh_notes (rtx, rtx);
428 /* Initialize the reload pass once per compilation. */
435 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
436 Set spill_indirect_levels to the number of levels such addressing is
437 permitted, zero if it is not permitted at all. */
440 = gen_rtx_MEM (Pmode,
443 LAST_VIRTUAL_REGISTER + 1),
445 spill_indirect_levels = 0;
447 while (memory_address_p (QImode, tem))
449 spill_indirect_levels++;
450 tem = gen_rtx_MEM (Pmode, tem);
453 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
455 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
456 indirect_symref_ok = memory_address_p (QImode, tem);
458 /* See if reg+reg is a valid (and offsettable) address. */
460 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
462 tem = gen_rtx_PLUS (Pmode,
463 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
464 gen_rtx_REG (Pmode, i));
466 /* This way, we make sure that reg+reg is an offsettable address. */
467 tem = plus_constant (tem, 4);
469 if (memory_address_p (QImode, tem))
471 double_reg_address_ok = 1;
476 /* Initialize obstack for our rtl allocation. */
477 gcc_obstack_init (&reload_obstack);
478 reload_startobj = obstack_alloc (&reload_obstack, 0);
480 INIT_REG_SET (&spilled_pseudos);
481 INIT_REG_SET (&pseudos_counted);
484 /* List of insn chains that are currently unused. */
485 static struct insn_chain *unused_insn_chains = 0;
487 /* Allocate an empty insn_chain structure. */
489 new_insn_chain (void)
491 struct insn_chain *c;
493 if (unused_insn_chains == 0)
495 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
496 INIT_REG_SET (&c->live_throughout);
497 INIT_REG_SET (&c->dead_or_set);
501 c = unused_insn_chains;
502 unused_insn_chains = c->next;
504 c->is_caller_save_insn = 0;
505 c->need_operand_change = 0;
511 /* Small utility function to set all regs in hard reg set TO which are
512 allocated to pseudos in regset FROM. */
515 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
519 EXECUTE_IF_SET_IN_REG_SET
520 (from, FIRST_PSEUDO_REGISTER, regno,
522 int r = reg_renumber[regno];
527 /* reload_combine uses the information from
528 BASIC_BLOCK->global_live_at_start, which might still
529 contain registers that have not actually been allocated
530 since they have an equivalence. */
531 if (! reload_completed)
536 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
538 SET_HARD_REG_BIT (*to, r + nregs);
543 /* Replace all pseudos found in LOC with their corresponding
547 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
560 unsigned int regno = REGNO (x);
562 if (regno < FIRST_PSEUDO_REGISTER)
565 x = eliminate_regs (x, mem_mode, usage);
569 replace_pseudos_in (loc, mem_mode, usage);
573 if (reg_equiv_constant[regno])
574 *loc = reg_equiv_constant[regno];
575 else if (reg_equiv_mem[regno])
576 *loc = reg_equiv_mem[regno];
577 else if (reg_equiv_address[regno])
578 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
579 else if (GET_CODE (regno_reg_rtx[regno]) != REG
580 || REGNO (regno_reg_rtx[regno]) != regno)
581 *loc = regno_reg_rtx[regno];
587 else if (code == MEM)
589 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
593 /* Process each of our operands recursively. */
594 fmt = GET_RTX_FORMAT (code);
595 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
597 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
598 else if (*fmt == 'E')
599 for (j = 0; j < XVECLEN (x, i); j++)
600 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
604 /* Global variables used by reload and its subroutines. */
606 /* Set during calculate_needs if an insn needs register elimination. */
607 static int something_needs_elimination;
608 /* Set during calculate_needs if an insn needs an operand changed. */
609 int something_needs_operands_changed;
611 /* Nonzero means we couldn't get enough spill regs. */
614 /* Main entry point for the reload pass.
616 FIRST is the first insn of the function being compiled.
618 GLOBAL nonzero means we were called from global_alloc
619 and should attempt to reallocate any pseudoregs that we
620 displace from hard regs we will use for reloads.
621 If GLOBAL is zero, we do not have enough information to do that,
622 so any pseudo reg that is spilled must go to the stack.
624 Return value is nonzero if reload failed
625 and we must not do any more for this function. */
628 reload (rtx first, int global)
632 struct elim_table *ep;
635 /* Make sure even insns with volatile mem refs are recognizable. */
640 reload_firstobj = obstack_alloc (&reload_obstack, 0);
642 /* Make sure that the last insn in the chain
643 is not something that needs reloading. */
644 emit_note (NOTE_INSN_DELETED);
646 /* Enable find_equiv_reg to distinguish insns made by reload. */
647 reload_first_uid = get_max_uid ();
649 #ifdef SECONDARY_MEMORY_NEEDED
650 /* Initialize the secondary memory table. */
651 clear_secondary_mem ();
654 /* We don't have a stack slot for any spill reg yet. */
655 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
656 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
658 /* Initialize the save area information for caller-save, in case some
662 /* Compute which hard registers are now in use
663 as homes for pseudo registers.
664 This is done here rather than (eg) in global_alloc
665 because this point is reached even if not optimizing. */
666 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
669 /* A function that receives a nonlocal goto must save all call-saved
671 if (current_function_has_nonlocal_label)
672 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
673 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
674 regs_ever_live[i] = 1;
676 /* Find all the pseudo registers that didn't get hard regs
677 but do have known equivalent constants or memory slots.
678 These include parameters (known equivalent to parameter slots)
679 and cse'd or loop-moved constant memory addresses.
681 Record constant equivalents in reg_equiv_constant
682 so they will be substituted by find_reloads.
683 Record memory equivalents in reg_mem_equiv so they can
684 be substituted eventually by altering the REG-rtx's. */
686 reg_equiv_constant = xcalloc (max_regno, sizeof (rtx));
687 reg_equiv_mem = xcalloc (max_regno, sizeof (rtx));
688 reg_equiv_init = xcalloc (max_regno, sizeof (rtx));
689 reg_equiv_address = xcalloc (max_regno, sizeof (rtx));
690 reg_max_ref_width = xcalloc (max_regno, sizeof (int));
691 reg_old_renumber = xcalloc (max_regno, sizeof (short));
692 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
693 pseudo_forbidden_regs = xmalloc (max_regno * sizeof (HARD_REG_SET));
694 pseudo_previous_regs = xcalloc (max_regno, sizeof (HARD_REG_SET));
696 CLEAR_HARD_REG_SET (bad_spill_regs_global);
698 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
699 Also find all paradoxical subregs and find largest such for each pseudo.
700 On machines with small register classes, record hard registers that
701 are used for user variables. These can never be used for spills. */
703 num_eliminable_invariants = 0;
704 for (insn = first; insn; insn = NEXT_INSN (insn))
706 rtx set = single_set (insn);
708 /* We may introduce USEs that we want to remove at the end, so
709 we'll mark them with QImode. Make sure there are no
710 previously-marked insns left by say regmove. */
711 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
712 && GET_MODE (insn) != VOIDmode)
713 PUT_MODE (insn, VOIDmode);
715 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
717 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
719 #ifdef LEGITIMATE_PIC_OPERAND_P
720 && (! function_invariant_p (XEXP (note, 0))
722 /* A function invariant is often CONSTANT_P but may
723 include a register. We promise to only pass
724 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
725 || (CONSTANT_P (XEXP (note, 0))
726 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))))
730 rtx x = XEXP (note, 0);
731 i = REGNO (SET_DEST (set));
732 if (i > LAST_VIRTUAL_REGISTER)
734 /* It can happen that a REG_EQUIV note contains a MEM
735 that is not a legitimate memory operand. As later
736 stages of reload assume that all addresses found
737 in the reg_equiv_* arrays were originally legitimate,
738 we ignore such REG_EQUIV notes. */
739 if (memory_operand (x, VOIDmode))
741 /* Always unshare the equivalence, so we can
742 substitute into this insn without touching the
744 reg_equiv_memory_loc[i] = copy_rtx (x);
746 else if (function_invariant_p (x))
748 if (GET_CODE (x) == PLUS)
750 /* This is PLUS of frame pointer and a constant,
751 and might be shared. Unshare it. */
752 reg_equiv_constant[i] = copy_rtx (x);
753 num_eliminable_invariants++;
755 else if (x == frame_pointer_rtx
756 || x == arg_pointer_rtx)
758 reg_equiv_constant[i] = x;
759 num_eliminable_invariants++;
761 else if (LEGITIMATE_CONSTANT_P (x))
762 reg_equiv_constant[i] = x;
765 reg_equiv_memory_loc[i]
766 = force_const_mem (GET_MODE (SET_DEST (set)), x);
767 if (!reg_equiv_memory_loc[i])
774 /* If this register is being made equivalent to a MEM
775 and the MEM is not SET_SRC, the equivalencing insn
776 is one with the MEM as a SET_DEST and it occurs later.
777 So don't mark this insn now. */
778 if (GET_CODE (x) != MEM
779 || rtx_equal_p (SET_SRC (set), x))
781 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
786 /* If this insn is setting a MEM from a register equivalent to it,
787 this is the equivalencing insn. */
788 else if (set && GET_CODE (SET_DEST (set)) == MEM
789 && GET_CODE (SET_SRC (set)) == REG
790 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
791 && rtx_equal_p (SET_DEST (set),
792 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
793 reg_equiv_init[REGNO (SET_SRC (set))]
794 = gen_rtx_INSN_LIST (VOIDmode, insn,
795 reg_equiv_init[REGNO (SET_SRC (set))]);
798 scan_paradoxical_subregs (PATTERN (insn));
803 first_label_num = get_first_label_num ();
804 num_labels = max_label_num () - first_label_num;
806 /* Allocate the tables used to store offset information at labels. */
807 /* We used to use alloca here, but the size of what it would try to
808 allocate would occasionally cause it to exceed the stack limit and
809 cause a core dump. */
810 offsets_known_at = xmalloc (num_labels);
811 offsets_at = xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
813 /* Alter each pseudo-reg rtx to contain its hard reg number.
814 Assign stack slots to the pseudos that lack hard regs or equivalents.
815 Do not touch virtual registers. */
817 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
820 /* If we have some registers we think can be eliminated, scan all insns to
821 see if there is an insn that sets one of these registers to something
822 other than itself plus a constant. If so, the register cannot be
823 eliminated. Doing this scan here eliminates an extra pass through the
824 main reload loop in the most common case where register elimination
826 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
827 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
828 || GET_CODE (insn) == CALL_INSN)
829 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
831 maybe_fix_stack_asms ();
833 insns_need_reload = 0;
834 something_needs_elimination = 0;
836 /* Initialize to -1, which means take the first spill register. */
839 /* Spill any hard regs that we know we can't eliminate. */
840 CLEAR_HARD_REG_SET (used_spill_regs);
841 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
842 if (! ep->can_eliminate)
843 spill_hard_reg (ep->from, 1);
845 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
846 if (frame_pointer_needed)
847 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
849 finish_spills (global);
851 /* From now on, we may need to generate moves differently. We may also
852 allow modifications of insns which cause them to not be recognized.
853 Any such modifications will be cleaned up during reload itself. */
854 reload_in_progress = 1;
856 /* This loop scans the entire function each go-round
857 and repeats until one repetition spills no additional hard regs. */
860 int something_changed;
863 HOST_WIDE_INT starting_frame_size;
865 /* Round size of stack frame to stack_alignment_needed. This must be done
866 here because the stack size may be a part of the offset computation
867 for register elimination, and there might have been new stack slots
868 created in the last iteration of this loop. */
869 if (cfun->stack_alignment_needed)
870 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
872 starting_frame_size = get_frame_size ();
874 set_initial_elim_offsets ();
875 set_initial_label_offsets ();
877 /* For each pseudo register that has an equivalent location defined,
878 try to eliminate any eliminable registers (such as the frame pointer)
879 assuming initial offsets for the replacement register, which
882 If the resulting location is directly addressable, substitute
883 the MEM we just got directly for the old REG.
885 If it is not addressable but is a constant or the sum of a hard reg
886 and constant, it is probably not addressable because the constant is
887 out of range, in that case record the address; we will generate
888 hairy code to compute the address in a register each time it is
889 needed. Similarly if it is a hard register, but one that is not
890 valid as an address register.
892 If the location is not addressable, but does not have one of the
893 above forms, assign a stack slot. We have to do this to avoid the
894 potential of producing lots of reloads if, e.g., a location involves
895 a pseudo that didn't get a hard register and has an equivalent memory
896 location that also involves a pseudo that didn't get a hard register.
898 Perhaps at some point we will improve reload_when_needed handling
899 so this problem goes away. But that's very hairy. */
901 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
902 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
904 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
906 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
908 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
909 else if (CONSTANT_P (XEXP (x, 0))
910 || (GET_CODE (XEXP (x, 0)) == REG
911 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
912 || (GET_CODE (XEXP (x, 0)) == PLUS
913 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
914 && (REGNO (XEXP (XEXP (x, 0), 0))
915 < FIRST_PSEUDO_REGISTER)
916 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
917 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
920 /* Make a new stack slot. Then indicate that something
921 changed so we go back and recompute offsets for
922 eliminable registers because the allocation of memory
923 below might change some offset. reg_equiv_{mem,address}
924 will be set up for this pseudo on the next pass around
926 reg_equiv_memory_loc[i] = 0;
927 reg_equiv_init[i] = 0;
932 if (caller_save_needed)
935 /* If we allocated another stack slot, redo elimination bookkeeping. */
936 if (starting_frame_size != get_frame_size ())
939 if (caller_save_needed)
941 save_call_clobbered_regs ();
942 /* That might have allocated new insn_chain structures. */
943 reload_firstobj = obstack_alloc (&reload_obstack, 0);
946 calculate_needs_all_insns (global);
948 CLEAR_REG_SET (&spilled_pseudos);
951 something_changed = 0;
953 /* If we allocated any new memory locations, make another pass
954 since it might have changed elimination offsets. */
955 if (starting_frame_size != get_frame_size ())
956 something_changed = 1;
959 HARD_REG_SET to_spill;
960 CLEAR_HARD_REG_SET (to_spill);
961 update_eliminables (&to_spill);
962 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
963 if (TEST_HARD_REG_BIT (to_spill, i))
965 spill_hard_reg (i, 1);
968 /* Regardless of the state of spills, if we previously had
969 a register that we thought we could eliminate, but now can
970 not eliminate, we must run another pass.
972 Consider pseudos which have an entry in reg_equiv_* which
973 reference an eliminable register. We must make another pass
974 to update reg_equiv_* so that we do not substitute in the
975 old value from when we thought the elimination could be
977 something_changed = 1;
981 select_reload_regs ();
985 if (insns_need_reload != 0 || did_spill)
986 something_changed |= finish_spills (global);
988 if (! something_changed)
991 if (caller_save_needed)
992 delete_caller_save_insns ();
994 obstack_free (&reload_obstack, reload_firstobj);
997 /* If global-alloc was run, notify it of any register eliminations we have
1000 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1001 if (ep->can_eliminate)
1002 mark_elimination (ep->from, ep->to);
1004 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1005 If that insn didn't set the register (i.e., it copied the register to
1006 memory), just delete that insn instead of the equivalencing insn plus
1007 anything now dead. If we call delete_dead_insn on that insn, we may
1008 delete the insn that actually sets the register if the register dies
1009 there and that is incorrect. */
1011 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1013 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1016 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1018 rtx equiv_insn = XEXP (list, 0);
1020 /* If we already deleted the insn or if it may trap, we can't
1021 delete it. The latter case shouldn't happen, but can
1022 if an insn has a variable address, gets a REG_EH_REGION
1023 note added to it, and then gets converted into an load
1024 from a constant address. */
1025 if (GET_CODE (equiv_insn) == NOTE
1026 || can_throw_internal (equiv_insn))
1028 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1029 delete_dead_insn (equiv_insn);
1032 PUT_CODE (equiv_insn, NOTE);
1033 NOTE_SOURCE_FILE (equiv_insn) = 0;
1034 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1040 /* Use the reload registers where necessary
1041 by generating move instructions to move the must-be-register
1042 values into or out of the reload registers. */
1044 if (insns_need_reload != 0 || something_needs_elimination
1045 || something_needs_operands_changed)
1047 HOST_WIDE_INT old_frame_size = get_frame_size ();
1049 reload_as_needed (global);
1051 if (old_frame_size != get_frame_size ())
1055 verify_initial_elim_offsets ();
1058 /* If we were able to eliminate the frame pointer, show that it is no
1059 longer live at the start of any basic block. If it ls live by
1060 virtue of being in a pseudo, that pseudo will be marked live
1061 and hence the frame pointer will be known to be live via that
1064 if (! frame_pointer_needed)
1066 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1067 HARD_FRAME_POINTER_REGNUM);
1069 /* Come here (with failure set nonzero) if we can't get enough spill regs
1070 and we decide not to abort about it. */
1073 CLEAR_REG_SET (&spilled_pseudos);
1074 reload_in_progress = 0;
1076 /* Now eliminate all pseudo regs by modifying them into
1077 their equivalent memory references.
1078 The REG-rtx's for the pseudos are modified in place,
1079 so all insns that used to refer to them now refer to memory.
1081 For a reg that has a reg_equiv_address, all those insns
1082 were changed by reloading so that no insns refer to it any longer;
1083 but the DECL_RTL of a variable decl may refer to it,
1084 and if so this causes the debugging info to mention the variable. */
1086 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1090 if (reg_equiv_mem[i])
1091 addr = XEXP (reg_equiv_mem[i], 0);
1093 if (reg_equiv_address[i])
1094 addr = reg_equiv_address[i];
1098 if (reg_renumber[i] < 0)
1100 rtx reg = regno_reg_rtx[i];
1102 REG_USERVAR_P (reg) = 0;
1103 PUT_CODE (reg, MEM);
1104 XEXP (reg, 0) = addr;
1105 if (reg_equiv_memory_loc[i])
1106 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1109 RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg)
1110 = MEM_SCALAR_P (reg) = 0;
1111 MEM_ATTRS (reg) = 0;
1114 else if (reg_equiv_mem[i])
1115 XEXP (reg_equiv_mem[i], 0) = addr;
1119 /* We must set reload_completed now since the cleanup_subreg_operands call
1120 below will re-recognize each insn and reload may have generated insns
1121 which are only valid during and after reload. */
1122 reload_completed = 1;
1124 /* Make a pass over all the insns and delete all USEs which we inserted
1125 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1126 notes. Delete all CLOBBER insns, except those that refer to the return
1127 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1128 from misarranging variable-array code, and simplify (subreg (reg))
1129 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1130 are no longer useful or accurate. Strip and regenerate REG_INC notes
1131 that may have been moved around. */
1133 for (insn = first; insn; insn = NEXT_INSN (insn))
1138 if (GET_CODE (insn) == CALL_INSN)
1139 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1140 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1142 if ((GET_CODE (PATTERN (insn)) == USE
1143 /* We mark with QImode USEs introduced by reload itself. */
1144 && (GET_MODE (insn) == QImode
1145 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1146 || (GET_CODE (PATTERN (insn)) == CLOBBER
1147 && (GET_CODE (XEXP (PATTERN (insn), 0)) != MEM
1148 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1149 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1150 && XEXP (XEXP (PATTERN (insn), 0), 0)
1151 != stack_pointer_rtx))
1152 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1153 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1159 /* Some CLOBBERs may survive until here and still reference unassigned
1160 pseudos with const equivalent, which may in turn cause ICE in later
1161 passes if the reference remains in place. */
1162 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1163 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1164 VOIDmode, PATTERN (insn));
1166 pnote = ®_NOTES (insn);
1169 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1170 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1171 || REG_NOTE_KIND (*pnote) == REG_INC
1172 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1173 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1174 *pnote = XEXP (*pnote, 1);
1176 pnote = &XEXP (*pnote, 1);
1180 add_auto_inc_notes (insn, PATTERN (insn));
1183 /* And simplify (subreg (reg)) if it appears as an operand. */
1184 cleanup_subreg_operands (insn);
1187 /* If we are doing stack checking, give a warning if this function's
1188 frame size is larger than we expect. */
1189 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1191 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1192 static int verbose_warned = 0;
1194 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1195 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1196 size += UNITS_PER_WORD;
1198 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1200 warning ("frame size too large for reliable stack checking");
1201 if (! verbose_warned)
1203 warning ("try reducing the number of local variables");
1209 /* Indicate that we no longer have known memory locations or constants. */
1210 if (reg_equiv_constant)
1211 free (reg_equiv_constant);
1212 reg_equiv_constant = 0;
1213 if (reg_equiv_memory_loc)
1214 free (reg_equiv_memory_loc);
1215 reg_equiv_memory_loc = 0;
1217 if (offsets_known_at)
1218 free (offsets_known_at);
1222 free (reg_equiv_mem);
1223 free (reg_equiv_init);
1224 free (reg_equiv_address);
1225 free (reg_max_ref_width);
1226 free (reg_old_renumber);
1227 free (pseudo_previous_regs);
1228 free (pseudo_forbidden_regs);
1230 CLEAR_HARD_REG_SET (used_spill_regs);
1231 for (i = 0; i < n_spills; i++)
1232 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1234 /* Free all the insn_chain structures at once. */
1235 obstack_free (&reload_obstack, reload_startobj);
1236 unused_insn_chains = 0;
1237 fixup_abnormal_edges ();
1239 /* Replacing pseudos with their memory equivalents might have
1240 created shared rtx. Subsequent passes would get confused
1241 by this, so unshare everything here. */
1242 unshare_all_rtl_again (first);
1244 #ifdef STACK_BOUNDARY
1245 /* init_emit has set the alignment of the hard frame pointer
1246 to STACK_BOUNDARY. It is very likely no longer valid if
1247 the hard frame pointer was used for register allocation. */
1248 if (!frame_pointer_needed)
1249 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1255 /* Yet another special case. Unfortunately, reg-stack forces people to
1256 write incorrect clobbers in asm statements. These clobbers must not
1257 cause the register to appear in bad_spill_regs, otherwise we'll call
1258 fatal_insn later. We clear the corresponding regnos in the live
1259 register sets to avoid this.
1260 The whole thing is rather sick, I'm afraid. */
1263 maybe_fix_stack_asms (void)
1266 const char *constraints[MAX_RECOG_OPERANDS];
1267 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1268 struct insn_chain *chain;
1270 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1273 HARD_REG_SET clobbered, allowed;
1276 if (! INSN_P (chain->insn)
1277 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1279 pat = PATTERN (chain->insn);
1280 if (GET_CODE (pat) != PARALLEL)
1283 CLEAR_HARD_REG_SET (clobbered);
1284 CLEAR_HARD_REG_SET (allowed);
1286 /* First, make a mask of all stack regs that are clobbered. */
1287 for (i = 0; i < XVECLEN (pat, 0); i++)
1289 rtx t = XVECEXP (pat, 0, i);
1290 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1291 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1294 /* Get the operand values and constraints out of the insn. */
1295 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1296 constraints, operand_mode);
1298 /* For every operand, see what registers are allowed. */
1299 for (i = 0; i < noperands; i++)
1301 const char *p = constraints[i];
1302 /* For every alternative, we compute the class of registers allowed
1303 for reloading in CLS, and merge its contents into the reg set
1305 int cls = (int) NO_REGS;
1311 if (c == '\0' || c == ',' || c == '#')
1313 /* End of one alternative - mark the regs in the current
1314 class, and reset the class. */
1315 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1321 } while (c != '\0' && c != ',');
1329 case '=': case '+': case '*': case '%': case '?': case '!':
1330 case '0': case '1': case '2': case '3': case '4': case 'm':
1331 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1332 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1333 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1338 cls = (int) reg_class_subunion[cls]
1339 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1344 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1348 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1349 cls = (int) reg_class_subunion[cls]
1350 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1352 cls = (int) reg_class_subunion[cls]
1353 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1355 p += CONSTRAINT_LEN (c, p);
1358 /* Those of the registers which are clobbered, but allowed by the
1359 constraints, must be usable as reload registers. So clear them
1360 out of the life information. */
1361 AND_HARD_REG_SET (allowed, clobbered);
1362 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1363 if (TEST_HARD_REG_BIT (allowed, i))
1365 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1366 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1373 /* Copy the global variables n_reloads and rld into the corresponding elts
1376 copy_reloads (struct insn_chain *chain)
1378 chain->n_reloads = n_reloads;
1379 chain->rld = obstack_alloc (&reload_obstack,
1380 n_reloads * sizeof (struct reload));
1381 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1382 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1385 /* Walk the chain of insns, and determine for each whether it needs reloads
1386 and/or eliminations. Build the corresponding insns_need_reload list, and
1387 set something_needs_elimination as appropriate. */
1389 calculate_needs_all_insns (int global)
1391 struct insn_chain **pprev_reload = &insns_need_reload;
1392 struct insn_chain *chain, *next = 0;
1394 something_needs_elimination = 0;
1396 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1397 for (chain = reload_insn_chain; chain != 0; chain = next)
1399 rtx insn = chain->insn;
1403 /* Clear out the shortcuts. */
1404 chain->n_reloads = 0;
1405 chain->need_elim = 0;
1406 chain->need_reload = 0;
1407 chain->need_operand_change = 0;
1409 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1410 include REG_LABEL), we need to see what effects this has on the
1411 known offsets at labels. */
1413 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1414 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1415 set_label_offsets (insn, insn, 0);
1419 rtx old_body = PATTERN (insn);
1420 int old_code = INSN_CODE (insn);
1421 rtx old_notes = REG_NOTES (insn);
1422 int did_elimination = 0;
1423 int operands_changed = 0;
1424 rtx set = single_set (insn);
1426 /* Skip insns that only set an equivalence. */
1427 if (set && GET_CODE (SET_DEST (set)) == REG
1428 && reg_renumber[REGNO (SET_DEST (set))] < 0
1429 && reg_equiv_constant[REGNO (SET_DEST (set))])
1432 /* If needed, eliminate any eliminable registers. */
1433 if (num_eliminable || num_eliminable_invariants)
1434 did_elimination = eliminate_regs_in_insn (insn, 0);
1436 /* Analyze the instruction. */
1437 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1438 global, spill_reg_order);
1440 /* If a no-op set needs more than one reload, this is likely
1441 to be something that needs input address reloads. We
1442 can't get rid of this cleanly later, and it is of no use
1443 anyway, so discard it now.
1444 We only do this when expensive_optimizations is enabled,
1445 since this complements reload inheritance / output
1446 reload deletion, and it can make debugging harder. */
1447 if (flag_expensive_optimizations && n_reloads > 1)
1449 rtx set = single_set (insn);
1451 && SET_SRC (set) == SET_DEST (set)
1452 && GET_CODE (SET_SRC (set)) == REG
1453 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1456 /* Delete it from the reload chain. */
1458 chain->prev->next = next;
1460 reload_insn_chain = next;
1462 next->prev = chain->prev;
1463 chain->next = unused_insn_chains;
1464 unused_insn_chains = chain;
1469 update_eliminable_offsets ();
1471 /* Remember for later shortcuts which insns had any reloads or
1472 register eliminations. */
1473 chain->need_elim = did_elimination;
1474 chain->need_reload = n_reloads > 0;
1475 chain->need_operand_change = operands_changed;
1477 /* Discard any register replacements done. */
1478 if (did_elimination)
1480 obstack_free (&reload_obstack, reload_insn_firstobj);
1481 PATTERN (insn) = old_body;
1482 INSN_CODE (insn) = old_code;
1483 REG_NOTES (insn) = old_notes;
1484 something_needs_elimination = 1;
1487 something_needs_operands_changed |= operands_changed;
1491 copy_reloads (chain);
1492 *pprev_reload = chain;
1493 pprev_reload = &chain->next_need_reload;
1500 /* Comparison function for qsort to decide which of two reloads
1501 should be handled first. *P1 and *P2 are the reload numbers. */
1504 reload_reg_class_lower (const void *r1p, const void *r2p)
1506 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1509 /* Consider required reloads before optional ones. */
1510 t = rld[r1].optional - rld[r2].optional;
1514 /* Count all solitary classes before non-solitary ones. */
1515 t = ((reg_class_size[(int) rld[r2].class] == 1)
1516 - (reg_class_size[(int) rld[r1].class] == 1));
1520 /* Aside from solitaires, consider all multi-reg groups first. */
1521 t = rld[r2].nregs - rld[r1].nregs;
1525 /* Consider reloads in order of increasing reg-class number. */
1526 t = (int) rld[r1].class - (int) rld[r2].class;
1530 /* If reloads are equally urgent, sort by reload number,
1531 so that the results of qsort leave nothing to chance. */
1535 /* The cost of spilling each hard reg. */
1536 static int spill_cost[FIRST_PSEUDO_REGISTER];
1538 /* When spilling multiple hard registers, we use SPILL_COST for the first
1539 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1540 only the first hard reg for a multi-reg pseudo. */
1541 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1543 /* Update the spill cost arrays, considering that pseudo REG is live. */
1546 count_pseudo (int reg)
1548 int freq = REG_FREQ (reg);
1549 int r = reg_renumber[reg];
1552 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1553 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1556 SET_REGNO_REG_SET (&pseudos_counted, reg);
1561 spill_add_cost[r] += freq;
1563 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1565 spill_cost[r + nregs] += freq;
1568 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1569 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1572 order_regs_for_reload (struct insn_chain *chain)
1575 HARD_REG_SET used_by_pseudos;
1576 HARD_REG_SET used_by_pseudos2;
1578 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1580 memset (spill_cost, 0, sizeof spill_cost);
1581 memset (spill_add_cost, 0, sizeof spill_add_cost);
1583 /* Count number of uses of each hard reg by pseudo regs allocated to it
1584 and then order them by decreasing use. First exclude hard registers
1585 that are live in or across this insn. */
1587 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1588 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1589 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1590 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1592 /* Now find out which pseudos are allocated to it, and update
1594 CLEAR_REG_SET (&pseudos_counted);
1596 EXECUTE_IF_SET_IN_REG_SET
1597 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1601 EXECUTE_IF_SET_IN_REG_SET
1602 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1606 CLEAR_REG_SET (&pseudos_counted);
1609 /* Vector of reload-numbers showing the order in which the reloads should
1611 static short reload_order[MAX_RELOADS];
1613 /* This is used to keep track of the spill regs used in one insn. */
1614 static HARD_REG_SET used_spill_regs_local;
1616 /* We decided to spill hard register SPILLED, which has a size of
1617 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1618 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1619 update SPILL_COST/SPILL_ADD_COST. */
1622 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1624 int r = reg_renumber[reg];
1625 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1627 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1628 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1631 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1633 spill_add_cost[r] -= REG_FREQ (reg);
1635 spill_cost[r + nregs] -= REG_FREQ (reg);
1638 /* Find reload register to use for reload number ORDER. */
1641 find_reg (struct insn_chain *chain, int order)
1643 int rnum = reload_order[order];
1644 struct reload *rl = rld + rnum;
1645 int best_cost = INT_MAX;
1649 HARD_REG_SET not_usable;
1650 HARD_REG_SET used_by_other_reload;
1652 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1653 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1654 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1656 CLEAR_HARD_REG_SET (used_by_other_reload);
1657 for (k = 0; k < order; k++)
1659 int other = reload_order[k];
1661 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1662 for (j = 0; j < rld[other].nregs; j++)
1663 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1666 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1668 unsigned int regno = i;
1670 if (! TEST_HARD_REG_BIT (not_usable, regno)
1671 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1672 && HARD_REGNO_MODE_OK (regno, rl->mode))
1674 int this_cost = spill_cost[regno];
1676 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1678 for (j = 1; j < this_nregs; j++)
1680 this_cost += spill_add_cost[regno + j];
1681 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1682 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1687 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1689 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1691 if (this_cost < best_cost
1692 /* Among registers with equal cost, prefer caller-saved ones, or
1693 use REG_ALLOC_ORDER if it is defined. */
1694 || (this_cost == best_cost
1695 #ifdef REG_ALLOC_ORDER
1696 && (inv_reg_alloc_order[regno]
1697 < inv_reg_alloc_order[best_reg])
1699 && call_used_regs[regno]
1700 && ! call_used_regs[best_reg]
1705 best_cost = this_cost;
1713 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1715 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1716 rl->regno = best_reg;
1718 EXECUTE_IF_SET_IN_REG_SET
1719 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1721 count_spilled_pseudo (best_reg, rl->nregs, j);
1724 EXECUTE_IF_SET_IN_REG_SET
1725 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1727 count_spilled_pseudo (best_reg, rl->nregs, j);
1730 for (i = 0; i < rl->nregs; i++)
1732 if (spill_cost[best_reg + i] != 0
1733 || spill_add_cost[best_reg + i] != 0)
1735 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1740 /* Find more reload regs to satisfy the remaining need of an insn, which
1742 Do it by ascending class number, since otherwise a reg
1743 might be spilled for a big class and might fail to count
1744 for a smaller class even though it belongs to that class. */
1747 find_reload_regs (struct insn_chain *chain)
1751 /* In order to be certain of getting the registers we need,
1752 we must sort the reloads into order of increasing register class.
1753 Then our grabbing of reload registers will parallel the process
1754 that provided the reload registers. */
1755 for (i = 0; i < chain->n_reloads; i++)
1757 /* Show whether this reload already has a hard reg. */
1758 if (chain->rld[i].reg_rtx)
1760 int regno = REGNO (chain->rld[i].reg_rtx);
1761 chain->rld[i].regno = regno;
1763 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1766 chain->rld[i].regno = -1;
1767 reload_order[i] = i;
1770 n_reloads = chain->n_reloads;
1771 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1773 CLEAR_HARD_REG_SET (used_spill_regs_local);
1776 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1778 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1780 /* Compute the order of preference for hard registers to spill. */
1782 order_regs_for_reload (chain);
1784 for (i = 0; i < n_reloads; i++)
1786 int r = reload_order[i];
1788 /* Ignore reloads that got marked inoperative. */
1789 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1790 && ! rld[r].optional
1791 && rld[r].regno == -1)
1792 if (! find_reg (chain, i))
1794 spill_failure (chain->insn, rld[r].class);
1800 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1801 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1803 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1807 select_reload_regs (void)
1809 struct insn_chain *chain;
1811 /* Try to satisfy the needs for each insn. */
1812 for (chain = insns_need_reload; chain != 0;
1813 chain = chain->next_need_reload)
1814 find_reload_regs (chain);
1817 /* Delete all insns that were inserted by emit_caller_save_insns during
1820 delete_caller_save_insns (void)
1822 struct insn_chain *c = reload_insn_chain;
1826 while (c != 0 && c->is_caller_save_insn)
1828 struct insn_chain *next = c->next;
1831 if (c == reload_insn_chain)
1832 reload_insn_chain = next;
1836 next->prev = c->prev;
1838 c->prev->next = next;
1839 c->next = unused_insn_chains;
1840 unused_insn_chains = c;
1848 /* Handle the failure to find a register to spill.
1849 INSN should be one of the insns which needed this particular spill reg. */
1852 spill_failure (rtx insn, enum reg_class class)
1854 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1855 if (asm_noperands (PATTERN (insn)) >= 0)
1856 error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'",
1857 reg_class_names[class]);
1860 error ("unable to find a register to spill in class `%s'",
1861 reg_class_names[class]);
1862 fatal_insn ("this is the insn:", insn);
1866 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1867 data that is dead in INSN. */
1870 delete_dead_insn (rtx insn)
1872 rtx prev = prev_real_insn (insn);
1875 /* If the previous insn sets a register that dies in our insn, delete it
1877 if (prev && GET_CODE (PATTERN (prev)) == SET
1878 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1879 && reg_mentioned_p (prev_dest, PATTERN (insn))
1880 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1881 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1882 delete_dead_insn (prev);
1884 PUT_CODE (insn, NOTE);
1885 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1886 NOTE_SOURCE_FILE (insn) = 0;
1889 /* Modify the home of pseudo-reg I.
1890 The new home is present in reg_renumber[I].
1892 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1893 or it may be -1, meaning there is none or it is not relevant.
1894 This is used so that all pseudos spilled from a given hard reg
1895 can share one stack slot. */
1898 alter_reg (int i, int from_reg)
1900 /* When outputting an inline function, this can happen
1901 for a reg that isn't actually used. */
1902 if (regno_reg_rtx[i] == 0)
1905 /* If the reg got changed to a MEM at rtl-generation time,
1907 if (GET_CODE (regno_reg_rtx[i]) != REG)
1910 /* Modify the reg-rtx to contain the new hard reg
1911 number or else to contain its pseudo reg number. */
1912 REGNO (regno_reg_rtx[i])
1913 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1915 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1916 allocate a stack slot for it. */
1918 if (reg_renumber[i] < 0
1919 && REG_N_REFS (i) > 0
1920 && reg_equiv_constant[i] == 0
1921 && reg_equiv_memory_loc[i] == 0)
1924 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1925 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1928 /* Each pseudo reg has an inherent size which comes from its own mode,
1929 and a total size which provides room for paradoxical subregs
1930 which refer to the pseudo reg in wider modes.
1932 We can use a slot already allocated if it provides both
1933 enough inherent space and enough total space.
1934 Otherwise, we allocate a new slot, making sure that it has no less
1935 inherent space, and no less total space, then the previous slot. */
1938 /* No known place to spill from => no slot to reuse. */
1939 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1940 inherent_size == total_size ? 0 : -1);
1941 if (BYTES_BIG_ENDIAN)
1942 /* Cancel the big-endian correction done in assign_stack_local.
1943 Get the address of the beginning of the slot.
1944 This is so we can do a big-endian correction unconditionally
1946 adjust = inherent_size - total_size;
1948 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1950 /* Nothing can alias this slot except this pseudo. */
1951 set_mem_alias_set (x, new_alias_set ());
1954 /* Reuse a stack slot if possible. */
1955 else if (spill_stack_slot[from_reg] != 0
1956 && spill_stack_slot_width[from_reg] >= total_size
1957 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1959 x = spill_stack_slot[from_reg];
1961 /* Allocate a bigger slot. */
1964 /* Compute maximum size needed, both for inherent size
1965 and for total size. */
1966 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1969 if (spill_stack_slot[from_reg])
1971 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1973 mode = GET_MODE (spill_stack_slot[from_reg]);
1974 if (spill_stack_slot_width[from_reg] > total_size)
1975 total_size = spill_stack_slot_width[from_reg];
1978 /* Make a slot with that size. */
1979 x = assign_stack_local (mode, total_size,
1980 inherent_size == total_size ? 0 : -1);
1983 /* All pseudos mapped to this slot can alias each other. */
1984 if (spill_stack_slot[from_reg])
1985 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
1987 set_mem_alias_set (x, new_alias_set ());
1989 if (BYTES_BIG_ENDIAN)
1991 /* Cancel the big-endian correction done in assign_stack_local.
1992 Get the address of the beginning of the slot.
1993 This is so we can do a big-endian correction unconditionally
1995 adjust = GET_MODE_SIZE (mode) - total_size;
1998 = adjust_address_nv (x, mode_for_size (total_size
2004 spill_stack_slot[from_reg] = stack_slot;
2005 spill_stack_slot_width[from_reg] = total_size;
2008 /* On a big endian machine, the "address" of the slot
2009 is the address of the low part that fits its inherent mode. */
2010 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2011 adjust += (total_size - inherent_size);
2013 /* If we have any adjustment to make, or if the stack slot is the
2014 wrong mode, make a new stack slot. */
2015 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2017 /* If we have a decl for the original register, set it for the
2018 memory. If this is a shared MEM, make a copy. */
2019 if (REG_EXPR (regno_reg_rtx[i])
2020 && TREE_CODE_CLASS (TREE_CODE (REG_EXPR (regno_reg_rtx[i]))) == 'd')
2022 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2024 /* We can do this only for the DECLs home pseudo, not for
2025 any copies of it, since otherwise when the stack slot
2026 is reused, nonoverlapping_memrefs_p might think they
2028 if (decl && GET_CODE (decl) == REG && REGNO (decl) == (unsigned) i)
2030 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2033 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2037 /* Save the stack slot for later. */
2038 reg_equiv_memory_loc[i] = x;
2042 /* Mark the slots in regs_ever_live for the hard regs
2043 used by pseudo-reg number REGNO. */
2046 mark_home_live (int regno)
2050 i = reg_renumber[regno];
2053 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2055 regs_ever_live[i++] = 1;
2058 /* This function handles the tracking of elimination offsets around branches.
2060 X is a piece of RTL being scanned.
2062 INSN is the insn that it came from, if any.
2064 INITIAL_P is nonzero if we are to set the offset to be the initial
2065 offset and zero if we are setting the offset of the label to be the
2069 set_label_offsets (rtx x, rtx insn, int initial_p)
2071 enum rtx_code code = GET_CODE (x);
2074 struct elim_table *p;
2079 if (LABEL_REF_NONLOCAL_P (x))
2084 /* ... fall through ... */
2087 /* If we know nothing about this label, set the desired offsets. Note
2088 that this sets the offset at a label to be the offset before a label
2089 if we don't know anything about the label. This is not correct for
2090 the label after a BARRIER, but is the best guess we can make. If
2091 we guessed wrong, we will suppress an elimination that might have
2092 been possible had we been able to guess correctly. */
2094 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2096 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2097 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2098 = (initial_p ? reg_eliminate[i].initial_offset
2099 : reg_eliminate[i].offset);
2100 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2103 /* Otherwise, if this is the definition of a label and it is
2104 preceded by a BARRIER, set our offsets to the known offset of
2108 && (tem = prev_nonnote_insn (insn)) != 0
2109 && GET_CODE (tem) == BARRIER)
2110 set_offsets_for_label (insn);
2112 /* If neither of the above cases is true, compare each offset
2113 with those previously recorded and suppress any eliminations
2114 where the offsets disagree. */
2116 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2117 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2118 != (initial_p ? reg_eliminate[i].initial_offset
2119 : reg_eliminate[i].offset))
2120 reg_eliminate[i].can_eliminate = 0;
2125 set_label_offsets (PATTERN (insn), insn, initial_p);
2127 /* ... fall through ... */
2131 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2132 and hence must have all eliminations at their initial offsets. */
2133 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2134 if (REG_NOTE_KIND (tem) == REG_LABEL)
2135 set_label_offsets (XEXP (tem, 0), insn, 1);
2141 /* Each of the labels in the parallel or address vector must be
2142 at their initial offsets. We want the first field for PARALLEL
2143 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2145 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2146 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2151 /* We only care about setting PC. If the source is not RETURN,
2152 IF_THEN_ELSE, or a label, disable any eliminations not at
2153 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2154 isn't one of those possibilities. For branches to a label,
2155 call ourselves recursively.
2157 Note that this can disable elimination unnecessarily when we have
2158 a non-local goto since it will look like a non-constant jump to
2159 someplace in the current function. This isn't a significant
2160 problem since such jumps will normally be when all elimination
2161 pairs are back to their initial offsets. */
2163 if (SET_DEST (x) != pc_rtx)
2166 switch (GET_CODE (SET_SRC (x)))
2173 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2177 tem = XEXP (SET_SRC (x), 1);
2178 if (GET_CODE (tem) == LABEL_REF)
2179 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2180 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2183 tem = XEXP (SET_SRC (x), 2);
2184 if (GET_CODE (tem) == LABEL_REF)
2185 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2186 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2194 /* If we reach here, all eliminations must be at their initial
2195 offset because we are doing a jump to a variable address. */
2196 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2197 if (p->offset != p->initial_offset)
2198 p->can_eliminate = 0;
2206 /* Scan X and replace any eliminable registers (such as fp) with a
2207 replacement (such as sp), plus an offset.
2209 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2210 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2211 MEM, we are allowed to replace a sum of a register and the constant zero
2212 with the register, which we cannot do outside a MEM. In addition, we need
2213 to record the fact that a register is referenced outside a MEM.
2215 If INSN is an insn, it is the insn containing X. If we replace a REG
2216 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2217 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2218 the REG is being modified.
2220 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2221 That's used when we eliminate in expressions stored in notes.
2222 This means, do not set ref_outside_mem even if the reference
2225 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2226 replacements done assuming all offsets are at their initial values. If
2227 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2228 encounter, return the actual location so that find_reloads will do
2229 the proper thing. */
2232 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2234 enum rtx_code code = GET_CODE (x);
2235 struct elim_table *ep;
2242 if (! current_function_decl)
2262 /* This is only for the benefit of the debugging backends, which call
2263 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2264 removed after CSE. */
2265 new = eliminate_regs (XEXP (x, 0), 0, insn);
2266 if (GET_CODE (new) == MEM)
2267 return XEXP (new, 0);
2273 /* First handle the case where we encounter a bare register that
2274 is eliminable. Replace it with a PLUS. */
2275 if (regno < FIRST_PSEUDO_REGISTER)
2277 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2279 if (ep->from_rtx == x && ep->can_eliminate)
2280 return plus_constant (ep->to_rtx, ep->previous_offset);
2283 else if (reg_renumber && reg_renumber[regno] < 0
2284 && reg_equiv_constant && reg_equiv_constant[regno]
2285 && ! CONSTANT_P (reg_equiv_constant[regno]))
2286 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2290 /* You might think handling MINUS in a manner similar to PLUS is a
2291 good idea. It is not. It has been tried multiple times and every
2292 time the change has had to have been reverted.
2294 Other parts of reload know a PLUS is special (gen_reload for example)
2295 and require special code to handle code a reloaded PLUS operand.
2297 Also consider backends where the flags register is clobbered by a
2298 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2299 lea instruction comes to mind). If we try to reload a MINUS, we
2300 may kill the flags register that was holding a useful value.
2302 So, please before trying to handle MINUS, consider reload as a
2303 whole instead of this little section as well as the backend issues. */
2305 /* If this is the sum of an eliminable register and a constant, rework
2307 if (GET_CODE (XEXP (x, 0)) == REG
2308 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2309 && CONSTANT_P (XEXP (x, 1)))
2311 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2313 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2315 /* The only time we want to replace a PLUS with a REG (this
2316 occurs when the constant operand of the PLUS is the negative
2317 of the offset) is when we are inside a MEM. We won't want
2318 to do so at other times because that would change the
2319 structure of the insn in a way that reload can't handle.
2320 We special-case the commonest situation in
2321 eliminate_regs_in_insn, so just replace a PLUS with a
2322 PLUS here, unless inside a MEM. */
2323 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2324 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2327 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2328 plus_constant (XEXP (x, 1),
2329 ep->previous_offset));
2332 /* If the register is not eliminable, we are done since the other
2333 operand is a constant. */
2337 /* If this is part of an address, we want to bring any constant to the
2338 outermost PLUS. We will do this by doing register replacement in
2339 our operands and seeing if a constant shows up in one of them.
2341 Note that there is no risk of modifying the structure of the insn,
2342 since we only get called for its operands, thus we are either
2343 modifying the address inside a MEM, or something like an address
2344 operand of a load-address insn. */
2347 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2348 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2350 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2352 /* If one side is a PLUS and the other side is a pseudo that
2353 didn't get a hard register but has a reg_equiv_constant,
2354 we must replace the constant here since it may no longer
2355 be in the position of any operand. */
2356 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2357 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2358 && reg_renumber[REGNO (new1)] < 0
2359 && reg_equiv_constant != 0
2360 && reg_equiv_constant[REGNO (new1)] != 0)
2361 new1 = reg_equiv_constant[REGNO (new1)];
2362 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2363 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2364 && reg_renumber[REGNO (new0)] < 0
2365 && reg_equiv_constant[REGNO (new0)] != 0)
2366 new0 = reg_equiv_constant[REGNO (new0)];
2368 new = form_sum (new0, new1);
2370 /* As above, if we are not inside a MEM we do not want to
2371 turn a PLUS into something else. We might try to do so here
2372 for an addition of 0 if we aren't optimizing. */
2373 if (! mem_mode && GET_CODE (new) != PLUS)
2374 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2382 /* If this is the product of an eliminable register and a
2383 constant, apply the distribute law and move the constant out
2384 so that we have (plus (mult ..) ..). This is needed in order
2385 to keep load-address insns valid. This case is pathological.
2386 We ignore the possibility of overflow here. */
2387 if (GET_CODE (XEXP (x, 0)) == REG
2388 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2389 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2390 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2392 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2395 /* Refs inside notes don't count for this purpose. */
2396 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2397 || GET_CODE (insn) == INSN_LIST)))
2398 ep->ref_outside_mem = 1;
2401 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2402 ep->previous_offset * INTVAL (XEXP (x, 1)));
2405 /* ... fall through ... */
2409 /* See comments before PLUS about handling MINUS. */
2411 case DIV: case UDIV:
2412 case MOD: case UMOD:
2413 case AND: case IOR: case XOR:
2414 case ROTATERT: case ROTATE:
2415 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2417 case GE: case GT: case GEU: case GTU:
2418 case LE: case LT: case LEU: case LTU:
2420 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2422 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2424 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2425 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2430 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2433 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2434 if (new != XEXP (x, 0))
2436 /* If this is a REG_DEAD note, it is not valid anymore.
2437 Using the eliminated version could result in creating a
2438 REG_DEAD note for the stack or frame pointer. */
2439 if (GET_MODE (x) == REG_DEAD)
2441 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2444 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2448 /* ... fall through ... */
2451 /* Now do eliminations in the rest of the chain. If this was
2452 an EXPR_LIST, this might result in allocating more memory than is
2453 strictly needed, but it simplifies the code. */
2456 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2457 if (new != XEXP (x, 1))
2459 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2467 case STRICT_LOW_PART:
2469 case SIGN_EXTEND: case ZERO_EXTEND:
2470 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2471 case FLOAT: case FIX:
2472 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2480 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2481 if (new != XEXP (x, 0))
2482 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2486 /* Similar to above processing, but preserve SUBREG_BYTE.
2487 Convert (subreg (mem)) to (mem) if not paradoxical.
2488 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2489 pseudo didn't get a hard reg, we must replace this with the
2490 eliminated version of the memory location because push_reload
2491 may do the replacement in certain circumstances. */
2492 if (GET_CODE (SUBREG_REG (x)) == REG
2493 && (GET_MODE_SIZE (GET_MODE (x))
2494 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2495 && reg_equiv_memory_loc != 0
2496 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2498 new = SUBREG_REG (x);
2501 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2503 if (new != SUBREG_REG (x))
2505 int x_size = GET_MODE_SIZE (GET_MODE (x));
2506 int new_size = GET_MODE_SIZE (GET_MODE (new));
2508 if (GET_CODE (new) == MEM
2509 && ((x_size < new_size
2510 #ifdef WORD_REGISTER_OPERATIONS
2511 /* On these machines, combine can create rtl of the form
2512 (set (subreg:m1 (reg:m2 R) 0) ...)
2513 where m1 < m2, and expects something interesting to
2514 happen to the entire word. Moreover, it will use the
2515 (reg:m2 R) later, expecting all bits to be preserved.
2516 So if the number of words is the same, preserve the
2517 subreg so that push_reload can see it. */
2518 && ! ((x_size - 1) / UNITS_PER_WORD
2519 == (new_size -1 ) / UNITS_PER_WORD)
2522 || x_size == new_size)
2524 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2526 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2532 /* This is only for the benefit of the debugging backends, which call
2533 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2534 removed after CSE. */
2535 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2536 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2538 /* Our only special processing is to pass the mode of the MEM to our
2539 recursive call and copy the flags. While we are here, handle this
2540 case more efficiently. */
2542 replace_equiv_address_nv (x,
2543 eliminate_regs (XEXP (x, 0),
2544 GET_MODE (x), insn));
2547 /* Handle insn_list USE that a call to a pure function may generate. */
2548 new = eliminate_regs (XEXP (x, 0), 0, insn);
2549 if (new != XEXP (x, 0))
2550 return gen_rtx_USE (GET_MODE (x), new);
2562 /* Process each of our operands recursively. If any have changed, make a
2564 fmt = GET_RTX_FORMAT (code);
2565 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2569 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2570 if (new != XEXP (x, i) && ! copied)
2572 rtx new_x = rtx_alloc (code);
2573 memcpy (new_x, x, RTX_SIZE (code));
2579 else if (*fmt == 'E')
2582 for (j = 0; j < XVECLEN (x, i); j++)
2584 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2585 if (new != XVECEXP (x, i, j) && ! copied_vec)
2587 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2591 rtx new_x = rtx_alloc (code);
2592 memcpy (new_x, x, RTX_SIZE (code));
2596 XVEC (x, i) = new_v;
2599 XVECEXP (x, i, j) = new;
2607 /* Scan rtx X for modifications of elimination target registers. Update
2608 the table of eliminables to reflect the changed state. MEM_MODE is
2609 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2612 elimination_effects (rtx x, enum machine_mode mem_mode)
2614 enum rtx_code code = GET_CODE (x);
2615 struct elim_table *ep;
2642 /* First handle the case where we encounter a bare register that
2643 is eliminable. Replace it with a PLUS. */
2644 if (regno < FIRST_PSEUDO_REGISTER)
2646 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2648 if (ep->from_rtx == x && ep->can_eliminate)
2651 ep->ref_outside_mem = 1;
2656 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2657 && reg_equiv_constant[regno]
2658 && ! function_invariant_p (reg_equiv_constant[regno]))
2659 elimination_effects (reg_equiv_constant[regno], mem_mode);
2668 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2669 if (ep->to_rtx == XEXP (x, 0))
2671 int size = GET_MODE_SIZE (mem_mode);
2673 /* If more bytes than MEM_MODE are pushed, account for them. */
2674 #ifdef PUSH_ROUNDING
2675 if (ep->to_rtx == stack_pointer_rtx)
2676 size = PUSH_ROUNDING (size);
2678 if (code == PRE_DEC || code == POST_DEC)
2680 else if (code == PRE_INC || code == POST_INC)
2682 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2683 && GET_CODE (XEXP (x, 1)) == PLUS
2684 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2685 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2686 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2689 /* These two aren't unary operators. */
2690 if (code == POST_MODIFY || code == PRE_MODIFY)
2693 /* Fall through to generic unary operation case. */
2694 case STRICT_LOW_PART:
2696 case SIGN_EXTEND: case ZERO_EXTEND:
2697 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2698 case FLOAT: case FIX:
2699 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2707 elimination_effects (XEXP (x, 0), mem_mode);
2711 if (GET_CODE (SUBREG_REG (x)) == REG
2712 && (GET_MODE_SIZE (GET_MODE (x))
2713 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2714 && reg_equiv_memory_loc != 0
2715 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2718 elimination_effects (SUBREG_REG (x), mem_mode);
2722 /* If using a register that is the source of an eliminate we still
2723 think can be performed, note it cannot be performed since we don't
2724 know how this register is used. */
2725 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2726 if (ep->from_rtx == XEXP (x, 0))
2727 ep->can_eliminate = 0;
2729 elimination_effects (XEXP (x, 0), mem_mode);
2733 /* If clobbering a register that is the replacement register for an
2734 elimination we still think can be performed, note that it cannot
2735 be performed. Otherwise, we need not be concerned about it. */
2736 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2737 if (ep->to_rtx == XEXP (x, 0))
2738 ep->can_eliminate = 0;
2740 elimination_effects (XEXP (x, 0), mem_mode);
2744 /* Check for setting a register that we know about. */
2745 if (GET_CODE (SET_DEST (x)) == REG)
2747 /* See if this is setting the replacement register for an
2750 If DEST is the hard frame pointer, we do nothing because we
2751 assume that all assignments to the frame pointer are for
2752 non-local gotos and are being done at a time when they are valid
2753 and do not disturb anything else. Some machines want to
2754 eliminate a fake argument pointer (or even a fake frame pointer)
2755 with either the real frame or the stack pointer. Assignments to
2756 the hard frame pointer must not prevent this elimination. */
2758 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2760 if (ep->to_rtx == SET_DEST (x)
2761 && SET_DEST (x) != hard_frame_pointer_rtx)
2763 /* If it is being incremented, adjust the offset. Otherwise,
2764 this elimination can't be done. */
2765 rtx src = SET_SRC (x);
2767 if (GET_CODE (src) == PLUS
2768 && XEXP (src, 0) == SET_DEST (x)
2769 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2770 ep->offset -= INTVAL (XEXP (src, 1));
2772 ep->can_eliminate = 0;
2776 elimination_effects (SET_DEST (x), 0);
2777 elimination_effects (SET_SRC (x), 0);
2781 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2784 /* Our only special processing is to pass the mode of the MEM to our
2786 elimination_effects (XEXP (x, 0), GET_MODE (x));
2793 fmt = GET_RTX_FORMAT (code);
2794 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2797 elimination_effects (XEXP (x, i), mem_mode);
2798 else if (*fmt == 'E')
2799 for (j = 0; j < XVECLEN (x, i); j++)
2800 elimination_effects (XVECEXP (x, i, j), mem_mode);
2804 /* Descend through rtx X and verify that no references to eliminable registers
2805 remain. If any do remain, mark the involved register as not
2809 check_eliminable_occurrences (rtx x)
2818 code = GET_CODE (x);
2820 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2822 struct elim_table *ep;
2824 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2825 if (ep->from_rtx == x && ep->can_eliminate)
2826 ep->can_eliminate = 0;
2830 fmt = GET_RTX_FORMAT (code);
2831 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2834 check_eliminable_occurrences (XEXP (x, i));
2835 else if (*fmt == 'E')
2838 for (j = 0; j < XVECLEN (x, i); j++)
2839 check_eliminable_occurrences (XVECEXP (x, i, j));
2844 /* Scan INSN and eliminate all eliminable registers in it.
2846 If REPLACE is nonzero, do the replacement destructively. Also
2847 delete the insn as dead it if it is setting an eliminable register.
2849 If REPLACE is zero, do all our allocations in reload_obstack.
2851 If no eliminations were done and this insn doesn't require any elimination
2852 processing (these are not identical conditions: it might be updating sp,
2853 but not referencing fp; this needs to be seen during reload_as_needed so
2854 that the offset between fp and sp can be taken into consideration), zero
2855 is returned. Otherwise, 1 is returned. */
2858 eliminate_regs_in_insn (rtx insn, int replace)
2860 int icode = recog_memoized (insn);
2861 rtx old_body = PATTERN (insn);
2862 int insn_is_asm = asm_noperands (old_body) >= 0;
2863 rtx old_set = single_set (insn);
2867 rtx substed_operand[MAX_RECOG_OPERANDS];
2868 rtx orig_operand[MAX_RECOG_OPERANDS];
2869 struct elim_table *ep;
2871 if (! insn_is_asm && icode < 0)
2873 if (GET_CODE (PATTERN (insn)) == USE
2874 || GET_CODE (PATTERN (insn)) == CLOBBER
2875 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2876 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2877 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2882 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2883 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2885 /* Check for setting an eliminable register. */
2886 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2887 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2889 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2890 /* If this is setting the frame pointer register to the
2891 hardware frame pointer register and this is an elimination
2892 that will be done (tested above), this insn is really
2893 adjusting the frame pointer downward to compensate for
2894 the adjustment done before a nonlocal goto. */
2895 if (ep->from == FRAME_POINTER_REGNUM
2896 && ep->to == HARD_FRAME_POINTER_REGNUM)
2898 rtx base = SET_SRC (old_set);
2899 rtx base_insn = insn;
2900 HOST_WIDE_INT offset = 0;
2902 while (base != ep->to_rtx)
2904 rtx prev_insn, prev_set;
2906 if (GET_CODE (base) == PLUS
2907 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2909 offset += INTVAL (XEXP (base, 1));
2910 base = XEXP (base, 0);
2912 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2913 && (prev_set = single_set (prev_insn)) != 0
2914 && rtx_equal_p (SET_DEST (prev_set), base))
2916 base = SET_SRC (prev_set);
2917 base_insn = prev_insn;
2923 if (base == ep->to_rtx)
2926 = plus_constant (ep->to_rtx, offset - ep->offset);
2928 new_body = old_body;
2931 new_body = copy_insn (old_body);
2932 if (REG_NOTES (insn))
2933 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2935 PATTERN (insn) = new_body;
2936 old_set = single_set (insn);
2938 /* First see if this insn remains valid when we
2939 make the change. If not, keep the INSN_CODE
2940 the same and let reload fit it up. */
2941 validate_change (insn, &SET_SRC (old_set), src, 1);
2942 validate_change (insn, &SET_DEST (old_set),
2944 if (! apply_change_group ())
2946 SET_SRC (old_set) = src;
2947 SET_DEST (old_set) = ep->to_rtx;
2956 /* In this case this insn isn't serving a useful purpose. We
2957 will delete it in reload_as_needed once we know that this
2958 elimination is, in fact, being done.
2960 If REPLACE isn't set, we can't delete this insn, but needn't
2961 process it since it won't be used unless something changes. */
2964 delete_dead_insn (insn);
2972 /* We allow one special case which happens to work on all machines we
2973 currently support: a single set with the source being a PLUS of an
2974 eliminable register and a constant. */
2976 && GET_CODE (SET_DEST (old_set)) == REG
2977 && GET_CODE (SET_SRC (old_set)) == PLUS
2978 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
2979 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
2980 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
2982 rtx reg = XEXP (SET_SRC (old_set), 0);
2983 HOST_WIDE_INT offset = INTVAL (XEXP (SET_SRC (old_set), 1));
2985 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2986 if (ep->from_rtx == reg && ep->can_eliminate)
2988 offset += ep->offset;
2993 /* We assume here that if we need a PARALLEL with
2994 CLOBBERs for this assignment, we can do with the
2995 MATCH_SCRATCHes that add_clobbers allocates.
2996 There's not much we can do if that doesn't work. */
2997 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3001 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3004 rtvec vec = rtvec_alloc (num_clobbers + 1);
3006 vec->elem[0] = PATTERN (insn);
3007 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3008 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3010 if (INSN_CODE (insn) < 0)
3015 new_body = old_body;
3018 new_body = copy_insn (old_body);
3019 if (REG_NOTES (insn))
3020 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3022 PATTERN (insn) = new_body;
3023 old_set = single_set (insn);
3025 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3026 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3029 /* This can't have an effect on elimination offsets, so skip right
3035 /* Determine the effects of this insn on elimination offsets. */
3036 elimination_effects (old_body, 0);
3038 /* Eliminate all eliminable registers occurring in operands that
3039 can be handled by reload. */
3040 extract_insn (insn);
3041 for (i = 0; i < recog_data.n_operands; i++)
3043 orig_operand[i] = recog_data.operand[i];
3044 substed_operand[i] = recog_data.operand[i];
3046 /* For an asm statement, every operand is eliminable. */
3047 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3049 /* Check for setting a register that we know about. */
3050 if (recog_data.operand_type[i] != OP_IN
3051 && GET_CODE (orig_operand[i]) == REG)
3053 /* If we are assigning to a register that can be eliminated, it
3054 must be as part of a PARALLEL, since the code above handles
3055 single SETs. We must indicate that we can no longer
3056 eliminate this reg. */
3057 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3059 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3060 ep->can_eliminate = 0;
3063 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3064 replace ? insn : NULL_RTX);
3065 if (substed_operand[i] != orig_operand[i])
3067 /* Terminate the search in check_eliminable_occurrences at
3069 *recog_data.operand_loc[i] = 0;
3071 /* If an output operand changed from a REG to a MEM and INSN is an
3072 insn, write a CLOBBER insn. */
3073 if (recog_data.operand_type[i] != OP_IN
3074 && GET_CODE (orig_operand[i]) == REG
3075 && GET_CODE (substed_operand[i]) == MEM
3077 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3082 for (i = 0; i < recog_data.n_dups; i++)
3083 *recog_data.dup_loc[i]
3084 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3086 /* If any eliminable remain, they aren't eliminable anymore. */
3087 check_eliminable_occurrences (old_body);
3089 /* Substitute the operands; the new values are in the substed_operand
3091 for (i = 0; i < recog_data.n_operands; i++)
3092 *recog_data.operand_loc[i] = substed_operand[i];
3093 for (i = 0; i < recog_data.n_dups; i++)
3094 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3096 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3097 re-recognize the insn. We do this in case we had a simple addition
3098 but now can do this as a load-address. This saves an insn in this
3100 If re-recognition fails, the old insn code number will still be used,
3101 and some register operands may have changed into PLUS expressions.
3102 These will be handled by find_reloads by loading them into a register
3107 /* If we aren't replacing things permanently and we changed something,
3108 make another copy to ensure that all the RTL is new. Otherwise
3109 things can go wrong if find_reload swaps commutative operands
3110 and one is inside RTL that has been copied while the other is not. */
3111 new_body = old_body;
3114 new_body = copy_insn (old_body);
3115 if (REG_NOTES (insn))
3116 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3118 PATTERN (insn) = new_body;
3120 /* If we had a move insn but now we don't, rerecognize it. This will
3121 cause spurious re-recognition if the old move had a PARALLEL since
3122 the new one still will, but we can't call single_set without
3123 having put NEW_BODY into the insn and the re-recognition won't
3124 hurt in this rare case. */
3125 /* ??? Why this huge if statement - why don't we just rerecognize the
3129 && ((GET_CODE (SET_SRC (old_set)) == REG
3130 && (GET_CODE (new_body) != SET
3131 || GET_CODE (SET_SRC (new_body)) != REG))
3132 /* If this was a load from or store to memory, compare
3133 the MEM in recog_data.operand to the one in the insn.
3134 If they are not equal, then rerecognize the insn. */
3136 && ((GET_CODE (SET_SRC (old_set)) == MEM
3137 && SET_SRC (old_set) != recog_data.operand[1])
3138 || (GET_CODE (SET_DEST (old_set)) == MEM
3139 && SET_DEST (old_set) != recog_data.operand[0])))
3140 /* If this was an add insn before, rerecognize. */
3141 || GET_CODE (SET_SRC (old_set)) == PLUS))
3143 int new_icode = recog (PATTERN (insn), insn, 0);
3145 INSN_CODE (insn) = icode;
3149 /* Restore the old body. If there were any changes to it, we made a copy
3150 of it while the changes were still in place, so we'll correctly return
3151 a modified insn below. */
3154 /* Restore the old body. */
3155 for (i = 0; i < recog_data.n_operands; i++)
3156 *recog_data.operand_loc[i] = orig_operand[i];
3157 for (i = 0; i < recog_data.n_dups; i++)
3158 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3161 /* Update all elimination pairs to reflect the status after the current
3162 insn. The changes we make were determined by the earlier call to
3163 elimination_effects.
3165 We also detect cases where register elimination cannot be done,
3166 namely, if a register would be both changed and referenced outside a MEM
3167 in the resulting insn since such an insn is often undefined and, even if
3168 not, we cannot know what meaning will be given to it. Note that it is
3169 valid to have a register used in an address in an insn that changes it
3170 (presumably with a pre- or post-increment or decrement).
3172 If anything changes, return nonzero. */
3174 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3176 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3177 ep->can_eliminate = 0;
3179 ep->ref_outside_mem = 0;
3181 if (ep->previous_offset != ep->offset)
3186 /* If we changed something, perform elimination in REG_NOTES. This is
3187 needed even when REPLACE is zero because a REG_DEAD note might refer
3188 to a register that we eliminate and could cause a different number
3189 of spill registers to be needed in the final reload pass than in
3191 if (val && REG_NOTES (insn) != 0)
3192 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3197 /* Loop through all elimination pairs.
3198 Recalculate the number not at initial offset.
3200 Compute the maximum offset (minimum offset if the stack does not
3201 grow downward) for each elimination pair. */
3204 update_eliminable_offsets (void)
3206 struct elim_table *ep;
3208 num_not_at_initial_offset = 0;
3209 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3211 ep->previous_offset = ep->offset;
3212 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3213 num_not_at_initial_offset++;
3217 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3218 replacement we currently believe is valid, mark it as not eliminable if X
3219 modifies DEST in any way other than by adding a constant integer to it.
3221 If DEST is the frame pointer, we do nothing because we assume that
3222 all assignments to the hard frame pointer are nonlocal gotos and are being
3223 done at a time when they are valid and do not disturb anything else.
3224 Some machines want to eliminate a fake argument pointer with either the
3225 frame or stack pointer. Assignments to the hard frame pointer must not
3226 prevent this elimination.
3228 Called via note_stores from reload before starting its passes to scan
3229 the insns of the function. */
3232 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3236 /* A SUBREG of a hard register here is just changing its mode. We should
3237 not see a SUBREG of an eliminable hard register, but check just in
3239 if (GET_CODE (dest) == SUBREG)
3240 dest = SUBREG_REG (dest);
3242 if (dest == hard_frame_pointer_rtx)
3245 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3246 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3247 && (GET_CODE (x) != SET
3248 || GET_CODE (SET_SRC (x)) != PLUS
3249 || XEXP (SET_SRC (x), 0) != dest
3250 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3252 reg_eliminate[i].can_eliminate_previous
3253 = reg_eliminate[i].can_eliminate = 0;
3258 /* Verify that the initial elimination offsets did not change since the
3259 last call to set_initial_elim_offsets. This is used to catch cases
3260 where something illegal happened during reload_as_needed that could
3261 cause incorrect code to be generated if we did not check for it. */
3264 verify_initial_elim_offsets (void)
3268 #ifdef ELIMINABLE_REGS
3269 struct elim_table *ep;
3271 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3273 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3274 if (t != ep->initial_offset)
3278 INITIAL_FRAME_POINTER_OFFSET (t);
3279 if (t != reg_eliminate[0].initial_offset)
3284 /* Reset all offsets on eliminable registers to their initial values. */
3287 set_initial_elim_offsets (void)
3289 struct elim_table *ep = reg_eliminate;
3291 #ifdef ELIMINABLE_REGS
3292 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3294 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3295 ep->previous_offset = ep->offset = ep->initial_offset;
3298 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3299 ep->previous_offset = ep->offset = ep->initial_offset;
3302 num_not_at_initial_offset = 0;
3305 /* Initialize the known label offsets.
3306 Set a known offset for each forced label to be at the initial offset
3307 of each elimination. We do this because we assume that all
3308 computed jumps occur from a location where each elimination is
3309 at its initial offset.
3310 For all other labels, show that we don't know the offsets. */
3313 set_initial_label_offsets (void)
3316 memset (offsets_known_at, 0, num_labels);
3318 for (x = forced_labels; x; x = XEXP (x, 1))
3320 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3323 /* Set all elimination offsets to the known values for the code label given
3327 set_offsets_for_label (rtx insn)
3330 int label_nr = CODE_LABEL_NUMBER (insn);
3331 struct elim_table *ep;
3333 num_not_at_initial_offset = 0;
3334 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3336 ep->offset = ep->previous_offset
3337 = offsets_at[label_nr - first_label_num][i];
3338 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3339 num_not_at_initial_offset++;
3343 /* See if anything that happened changes which eliminations are valid.
3344 For example, on the SPARC, whether or not the frame pointer can
3345 be eliminated can depend on what registers have been used. We need
3346 not check some conditions again (such as flag_omit_frame_pointer)
3347 since they can't have changed. */
3350 update_eliminables (HARD_REG_SET *pset)
3352 int previous_frame_pointer_needed = frame_pointer_needed;
3353 struct elim_table *ep;
3355 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3356 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3357 #ifdef ELIMINABLE_REGS
3358 || ! CAN_ELIMINATE (ep->from, ep->to)
3361 ep->can_eliminate = 0;
3363 /* Look for the case where we have discovered that we can't replace
3364 register A with register B and that means that we will now be
3365 trying to replace register A with register C. This means we can
3366 no longer replace register C with register B and we need to disable
3367 such an elimination, if it exists. This occurs often with A == ap,
3368 B == sp, and C == fp. */
3370 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3372 struct elim_table *op;
3375 if (! ep->can_eliminate && ep->can_eliminate_previous)
3377 /* Find the current elimination for ep->from, if there is a
3379 for (op = reg_eliminate;
3380 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3381 if (op->from == ep->from && op->can_eliminate)
3387 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3389 for (op = reg_eliminate;
3390 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3391 if (op->from == new_to && op->to == ep->to)
3392 op->can_eliminate = 0;
3396 /* See if any registers that we thought we could eliminate the previous
3397 time are no longer eliminable. If so, something has changed and we
3398 must spill the register. Also, recompute the number of eliminable
3399 registers and see if the frame pointer is needed; it is if there is
3400 no elimination of the frame pointer that we can perform. */
3402 frame_pointer_needed = 1;
3403 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3405 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3406 && ep->to != HARD_FRAME_POINTER_REGNUM)
3407 frame_pointer_needed = 0;
3409 if (! ep->can_eliminate && ep->can_eliminate_previous)
3411 ep->can_eliminate_previous = 0;
3412 SET_HARD_REG_BIT (*pset, ep->from);
3417 /* If we didn't need a frame pointer last time, but we do now, spill
3418 the hard frame pointer. */
3419 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3420 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3423 /* Initialize the table of registers to eliminate. */
3426 init_elim_table (void)
3428 struct elim_table *ep;
3429 #ifdef ELIMINABLE_REGS
3430 const struct elim_table_1 *ep1;
3434 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3436 /* Does this function require a frame pointer? */
3438 frame_pointer_needed = (! flag_omit_frame_pointer
3439 #ifdef EXIT_IGNORE_STACK
3440 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3441 and restore sp for alloca. So we can't eliminate
3442 the frame pointer in that case. At some point,
3443 we should improve this by emitting the
3444 sp-adjusting insns for this case. */
3445 || (current_function_calls_alloca
3446 && EXIT_IGNORE_STACK)
3448 || FRAME_POINTER_REQUIRED);
3452 #ifdef ELIMINABLE_REGS
3453 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3454 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3456 ep->from = ep1->from;
3458 ep->can_eliminate = ep->can_eliminate_previous
3459 = (CAN_ELIMINATE (ep->from, ep->to)
3460 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3463 reg_eliminate[0].from = reg_eliminate_1[0].from;
3464 reg_eliminate[0].to = reg_eliminate_1[0].to;
3465 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3466 = ! frame_pointer_needed;
3469 /* Count the number of eliminable registers and build the FROM and TO
3470 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3471 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3472 We depend on this. */
3473 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3475 num_eliminable += ep->can_eliminate;
3476 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3477 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3481 /* Kick all pseudos out of hard register REGNO.
3483 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3484 because we found we can't eliminate some register. In the case, no pseudos
3485 are allowed to be in the register, even if they are only in a block that
3486 doesn't require spill registers, unlike the case when we are spilling this
3487 hard reg to produce another spill register.
3489 Return nonzero if any pseudos needed to be kicked out. */
3492 spill_hard_reg (unsigned int regno, int cant_eliminate)
3498 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3499 regs_ever_live[regno] = 1;
3502 /* Spill every pseudo reg that was allocated to this reg
3503 or to something that overlaps this reg. */
3505 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3506 if (reg_renumber[i] >= 0
3507 && (unsigned int) reg_renumber[i] <= regno
3508 && ((unsigned int) reg_renumber[i]
3509 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3510 PSEUDO_REGNO_MODE (i))
3512 SET_REGNO_REG_SET (&spilled_pseudos, i);
3515 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3516 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3519 ior_hard_reg_set (HARD_REG_SET *set1, HARD_REG_SET *set2)
3521 IOR_HARD_REG_SET (*set1, *set2);
3524 /* After find_reload_regs has been run for all insn that need reloads,
3525 and/or spill_hard_regs was called, this function is used to actually
3526 spill pseudo registers and try to reallocate them. It also sets up the
3527 spill_regs array for use by choose_reload_regs. */
3530 finish_spills (int global)
3532 struct insn_chain *chain;
3533 int something_changed = 0;
3536 /* Build the spill_regs array for the function. */
3537 /* If there are some registers still to eliminate and one of the spill regs
3538 wasn't ever used before, additional stack space may have to be
3539 allocated to store this register. Thus, we may have changed the offset
3540 between the stack and frame pointers, so mark that something has changed.
3542 One might think that we need only set VAL to 1 if this is a call-used
3543 register. However, the set of registers that must be saved by the
3544 prologue is not identical to the call-used set. For example, the
3545 register used by the call insn for the return PC is a call-used register,
3546 but must be saved by the prologue. */
3549 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3550 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3552 spill_reg_order[i] = n_spills;
3553 spill_regs[n_spills++] = i;
3554 if (num_eliminable && ! regs_ever_live[i])
3555 something_changed = 1;
3556 regs_ever_live[i] = 1;
3559 spill_reg_order[i] = -1;
3561 EXECUTE_IF_SET_IN_REG_SET
3562 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3564 /* Record the current hard register the pseudo is allocated to in
3565 pseudo_previous_regs so we avoid reallocating it to the same
3566 hard reg in a later pass. */
3567 if (reg_renumber[i] < 0)
3570 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3571 /* Mark it as no longer having a hard register home. */
3572 reg_renumber[i] = -1;
3573 /* We will need to scan everything again. */
3574 something_changed = 1;
3577 /* Retry global register allocation if possible. */
3580 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3581 /* For every insn that needs reloads, set the registers used as spill
3582 regs in pseudo_forbidden_regs for every pseudo live across the
3584 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3586 EXECUTE_IF_SET_IN_REG_SET
3587 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3589 ior_hard_reg_set (pseudo_forbidden_regs + i,
3590 &chain->used_spill_regs);
3592 EXECUTE_IF_SET_IN_REG_SET
3593 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3595 ior_hard_reg_set (pseudo_forbidden_regs + i,
3596 &chain->used_spill_regs);
3600 /* Retry allocating the spilled pseudos. For each reg, merge the
3601 various reg sets that indicate which hard regs can't be used,
3602 and call retry_global_alloc.
3603 We change spill_pseudos here to only contain pseudos that did not
3604 get a new hard register. */
3605 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3606 if (reg_old_renumber[i] != reg_renumber[i])
3608 HARD_REG_SET forbidden;
3609 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3610 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3611 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3612 retry_global_alloc (i, forbidden);
3613 if (reg_renumber[i] >= 0)
3614 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3618 /* Fix up the register information in the insn chain.
3619 This involves deleting those of the spilled pseudos which did not get
3620 a new hard register home from the live_{before,after} sets. */
3621 for (chain = reload_insn_chain; chain; chain = chain->next)
3623 HARD_REG_SET used_by_pseudos;
3624 HARD_REG_SET used_by_pseudos2;
3626 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3627 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3629 /* Mark any unallocated hard regs as available for spills. That
3630 makes inheritance work somewhat better. */
3631 if (chain->need_reload)
3633 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3634 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3635 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3637 /* Save the old value for the sanity test below. */
3638 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3640 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3641 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3642 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3643 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3645 /* Make sure we only enlarge the set. */
3646 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3652 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3653 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3655 int regno = reg_renumber[i];
3656 if (reg_old_renumber[i] == regno)
3659 alter_reg (i, reg_old_renumber[i]);
3660 reg_old_renumber[i] = regno;
3664 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3666 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3667 i, reg_renumber[i]);
3671 return something_changed;
3674 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3675 Also mark any hard registers used to store user variables as
3676 forbidden from being used for spill registers. */
3679 scan_paradoxical_subregs (rtx x)
3683 enum rtx_code code = GET_CODE (x);
3689 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3690 && REG_USERVAR_P (x))
3691 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3700 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3708 if (GET_CODE (SUBREG_REG (x)) == REG
3709 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3710 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3711 = GET_MODE_SIZE (GET_MODE (x));
3718 fmt = GET_RTX_FORMAT (code);
3719 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3722 scan_paradoxical_subregs (XEXP (x, i));
3723 else if (fmt[i] == 'E')
3726 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3727 scan_paradoxical_subregs (XVECEXP (x, i, j));
3732 /* Reload pseudo-registers into hard regs around each insn as needed.
3733 Additional register load insns are output before the insn that needs it
3734 and perhaps store insns after insns that modify the reloaded pseudo reg.
3736 reg_last_reload_reg and reg_reloaded_contents keep track of
3737 which registers are already available in reload registers.
3738 We update these for the reloads that we perform,
3739 as the insns are scanned. */
3742 reload_as_needed (int live_known)
3744 struct insn_chain *chain;
3745 #if defined (AUTO_INC_DEC)
3750 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3751 memset (spill_reg_store, 0, sizeof spill_reg_store);
3752 reg_last_reload_reg = xcalloc (max_regno, sizeof (rtx));
3753 reg_has_output_reload = xmalloc (max_regno);
3754 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3756 set_initial_elim_offsets ();
3758 for (chain = reload_insn_chain; chain; chain = chain->next)
3761 rtx insn = chain->insn;
3762 rtx old_next = NEXT_INSN (insn);
3764 /* If we pass a label, copy the offsets from the label information
3765 into the current offsets of each elimination. */
3766 if (GET_CODE (insn) == CODE_LABEL)
3767 set_offsets_for_label (insn);
3769 else if (INSN_P (insn))
3771 rtx oldpat = copy_rtx (PATTERN (insn));
3773 /* If this is a USE and CLOBBER of a MEM, ensure that any
3774 references to eliminable registers have been removed. */
3776 if ((GET_CODE (PATTERN (insn)) == USE
3777 || GET_CODE (PATTERN (insn)) == CLOBBER)
3778 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3779 XEXP (XEXP (PATTERN (insn), 0), 0)
3780 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3781 GET_MODE (XEXP (PATTERN (insn), 0)),
3784 /* If we need to do register elimination processing, do so.
3785 This might delete the insn, in which case we are done. */
3786 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3788 eliminate_regs_in_insn (insn, 1);
3789 if (GET_CODE (insn) == NOTE)
3791 update_eliminable_offsets ();
3796 /* If need_elim is nonzero but need_reload is zero, one might think
3797 that we could simply set n_reloads to 0. However, find_reloads
3798 could have done some manipulation of the insn (such as swapping
3799 commutative operands), and these manipulations are lost during
3800 the first pass for every insn that needs register elimination.
3801 So the actions of find_reloads must be redone here. */
3803 if (! chain->need_elim && ! chain->need_reload
3804 && ! chain->need_operand_change)
3806 /* First find the pseudo regs that must be reloaded for this insn.
3807 This info is returned in the tables reload_... (see reload.h).
3808 Also modify the body of INSN by substituting RELOAD
3809 rtx's for those pseudo regs. */
3812 memset (reg_has_output_reload, 0, max_regno);
3813 CLEAR_HARD_REG_SET (reg_is_output_reload);
3815 find_reloads (insn, 1, spill_indirect_levels, live_known,
3821 rtx next = NEXT_INSN (insn);
3824 prev = PREV_INSN (insn);
3826 /* Now compute which reload regs to reload them into. Perhaps
3827 reusing reload regs from previous insns, or else output
3828 load insns to reload them. Maybe output store insns too.
3829 Record the choices of reload reg in reload_reg_rtx. */
3830 choose_reload_regs (chain);
3832 /* Merge any reloads that we didn't combine for fear of
3833 increasing the number of spill registers needed but now
3834 discover can be safely merged. */
3835 if (SMALL_REGISTER_CLASSES)
3836 merge_assigned_reloads (insn);
3838 /* Generate the insns to reload operands into or out of
3839 their reload regs. */
3840 emit_reload_insns (chain);
3842 /* Substitute the chosen reload regs from reload_reg_rtx
3843 into the insn's body (or perhaps into the bodies of other
3844 load and store insn that we just made for reloading
3845 and that we moved the structure into). */
3846 subst_reloads (insn);
3848 /* If this was an ASM, make sure that all the reload insns
3849 we have generated are valid. If not, give an error
3852 if (asm_noperands (PATTERN (insn)) >= 0)
3853 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3854 if (p != insn && INSN_P (p)
3855 && GET_CODE (PATTERN (p)) != USE
3856 && (recog_memoized (p) < 0
3857 || (extract_insn (p), ! constrain_operands (1))))
3859 error_for_asm (insn,
3860 "`asm' operand requires impossible reload");
3865 if (num_eliminable && chain->need_elim)
3866 update_eliminable_offsets ();
3868 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3869 is no longer validly lying around to save a future reload.
3870 Note that this does not detect pseudos that were reloaded
3871 for this insn in order to be stored in
3872 (obeying register constraints). That is correct; such reload
3873 registers ARE still valid. */
3874 note_stores (oldpat, forget_old_reloads_1, NULL);
3876 /* There may have been CLOBBER insns placed after INSN. So scan
3877 between INSN and NEXT and use them to forget old reloads. */
3878 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3879 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3880 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3883 /* Likewise for regs altered by auto-increment in this insn.
3884 REG_INC notes have been changed by reloading:
3885 find_reloads_address_1 records substitutions for them,
3886 which have been performed by subst_reloads above. */
3887 for (i = n_reloads - 1; i >= 0; i--)
3889 rtx in_reg = rld[i].in_reg;
3892 enum rtx_code code = GET_CODE (in_reg);
3893 /* PRE_INC / PRE_DEC will have the reload register ending up
3894 with the same value as the stack slot, but that doesn't
3895 hold true for POST_INC / POST_DEC. Either we have to
3896 convert the memory access to a true POST_INC / POST_DEC,
3897 or we can't use the reload register for inheritance. */
3898 if ((code == POST_INC || code == POST_DEC)
3899 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3900 REGNO (rld[i].reg_rtx))
3901 /* Make sure it is the inc/dec pseudo, and not
3902 some other (e.g. output operand) pseudo. */
3903 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3904 == REGNO (XEXP (in_reg, 0))))
3907 rtx reload_reg = rld[i].reg_rtx;
3908 enum machine_mode mode = GET_MODE (reload_reg);
3912 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3914 /* We really want to ignore REG_INC notes here, so
3915 use PATTERN (p) as argument to reg_set_p . */
3916 if (reg_set_p (reload_reg, PATTERN (p)))
3918 n = count_occurrences (PATTERN (p), reload_reg, 0);
3923 n = validate_replace_rtx (reload_reg,
3924 gen_rtx (code, mode,
3928 /* We must also verify that the constraints
3929 are met after the replacement. */
3932 n = constrain_operands (1);
3936 /* If the constraints were not met, then
3937 undo the replacement. */
3940 validate_replace_rtx (gen_rtx (code, mode,
3952 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3954 /* Mark this as having an output reload so that the
3955 REG_INC processing code below won't invalidate
3956 the reload for inheritance. */
3957 SET_HARD_REG_BIT (reg_is_output_reload,
3958 REGNO (reload_reg));
3959 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3962 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3965 else if ((code == PRE_INC || code == PRE_DEC)
3966 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3967 REGNO (rld[i].reg_rtx))
3968 /* Make sure it is the inc/dec pseudo, and not
3969 some other (e.g. output operand) pseudo. */
3970 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3971 == REGNO (XEXP (in_reg, 0))))
3973 SET_HARD_REG_BIT (reg_is_output_reload,
3974 REGNO (rld[i].reg_rtx));
3975 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3979 /* If a pseudo that got a hard register is auto-incremented,
3980 we must purge records of copying it into pseudos without
3982 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3983 if (REG_NOTE_KIND (x) == REG_INC)
3985 /* See if this pseudo reg was reloaded in this insn.
3986 If so, its last-reload info is still valid
3987 because it is based on this insn's reload. */
3988 for (i = 0; i < n_reloads; i++)
3989 if (rld[i].out == XEXP (x, 0))
3993 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
3997 /* A reload reg's contents are unknown after a label. */
3998 if (GET_CODE (insn) == CODE_LABEL)
3999 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4001 /* Don't assume a reload reg is still good after a call insn
4002 if it is a call-used reg. */
4003 else if (GET_CODE (insn) == CALL_INSN)
4004 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4008 free (reg_last_reload_reg);
4009 free (reg_has_output_reload);
4012 /* Discard all record of any value reloaded from X,
4013 or reloaded in X from someplace else;
4014 unless X is an output reload reg of the current insn.
4016 X may be a hard reg (the reload reg)
4017 or it may be a pseudo reg that was reloaded from. */
4020 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4021 void *data ATTRIBUTE_UNUSED)
4026 /* note_stores does give us subregs of hard regs,
4027 subreg_regno_offset will abort if it is not a hard reg. */
4028 while (GET_CODE (x) == SUBREG)
4030 /* We ignore the subreg offset when calculating the regno,
4031 because we are using the entire underlying hard register
4036 if (GET_CODE (x) != REG)
4041 if (regno >= FIRST_PSEUDO_REGISTER)
4047 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4048 /* Storing into a spilled-reg invalidates its contents.
4049 This can happen if a block-local pseudo is allocated to that reg
4050 and it wasn't spilled because this block's total need is 0.
4051 Then some insn might have an optional reload and use this reg. */
4052 for (i = 0; i < nr; i++)
4053 /* But don't do this if the reg actually serves as an output
4054 reload reg in the current instruction. */
4056 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4058 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4059 spill_reg_store[regno + i] = 0;
4063 /* Since value of X has changed,
4064 forget any value previously copied from it. */
4067 /* But don't forget a copy if this is the output reload
4068 that establishes the copy's validity. */
4069 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4070 reg_last_reload_reg[regno + nr] = 0;
4073 /* The following HARD_REG_SETs indicate when each hard register is
4074 used for a reload of various parts of the current insn. */
4076 /* If reg is unavailable for all reloads. */
4077 static HARD_REG_SET reload_reg_unavailable;
4078 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4079 static HARD_REG_SET reload_reg_used;
4080 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4081 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4082 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4083 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4084 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4085 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4086 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4087 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4088 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4089 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4090 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4091 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4092 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4093 static HARD_REG_SET reload_reg_used_in_op_addr;
4094 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4095 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4096 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4097 static HARD_REG_SET reload_reg_used_in_insn;
4098 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4099 static HARD_REG_SET reload_reg_used_in_other_addr;
4101 /* If reg is in use as a reload reg for any sort of reload. */
4102 static HARD_REG_SET reload_reg_used_at_all;
4104 /* If reg is use as an inherited reload. We just mark the first register
4106 static HARD_REG_SET reload_reg_used_for_inherit;
4108 /* Records which hard regs are used in any way, either as explicit use or
4109 by being allocated to a pseudo during any point of the current insn. */
4110 static HARD_REG_SET reg_used_in_insn;
4112 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4113 TYPE. MODE is used to indicate how many consecutive regs are
4117 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4118 enum machine_mode mode)
4120 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4123 for (i = regno; i < nregs + regno; i++)
4128 SET_HARD_REG_BIT (reload_reg_used, i);
4131 case RELOAD_FOR_INPUT_ADDRESS:
4132 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4135 case RELOAD_FOR_INPADDR_ADDRESS:
4136 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4139 case RELOAD_FOR_OUTPUT_ADDRESS:
4140 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4143 case RELOAD_FOR_OUTADDR_ADDRESS:
4144 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4147 case RELOAD_FOR_OPERAND_ADDRESS:
4148 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4151 case RELOAD_FOR_OPADDR_ADDR:
4152 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4155 case RELOAD_FOR_OTHER_ADDRESS:
4156 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4159 case RELOAD_FOR_INPUT:
4160 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4163 case RELOAD_FOR_OUTPUT:
4164 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4167 case RELOAD_FOR_INSN:
4168 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4172 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4176 /* Similarly, but show REGNO is no longer in use for a reload. */
4179 clear_reload_reg_in_use (unsigned int regno, int opnum,
4180 enum reload_type type, enum machine_mode mode)
4182 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4183 unsigned int start_regno, end_regno, r;
4185 /* A complication is that for some reload types, inheritance might
4186 allow multiple reloads of the same types to share a reload register.
4187 We set check_opnum if we have to check only reloads with the same
4188 operand number, and check_any if we have to check all reloads. */
4189 int check_opnum = 0;
4191 HARD_REG_SET *used_in_set;
4196 used_in_set = &reload_reg_used;
4199 case RELOAD_FOR_INPUT_ADDRESS:
4200 used_in_set = &reload_reg_used_in_input_addr[opnum];
4203 case RELOAD_FOR_INPADDR_ADDRESS:
4205 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4208 case RELOAD_FOR_OUTPUT_ADDRESS:
4209 used_in_set = &reload_reg_used_in_output_addr[opnum];
4212 case RELOAD_FOR_OUTADDR_ADDRESS:
4214 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4217 case RELOAD_FOR_OPERAND_ADDRESS:
4218 used_in_set = &reload_reg_used_in_op_addr;
4221 case RELOAD_FOR_OPADDR_ADDR:
4223 used_in_set = &reload_reg_used_in_op_addr_reload;
4226 case RELOAD_FOR_OTHER_ADDRESS:
4227 used_in_set = &reload_reg_used_in_other_addr;
4231 case RELOAD_FOR_INPUT:
4232 used_in_set = &reload_reg_used_in_input[opnum];
4235 case RELOAD_FOR_OUTPUT:
4236 used_in_set = &reload_reg_used_in_output[opnum];
4239 case RELOAD_FOR_INSN:
4240 used_in_set = &reload_reg_used_in_insn;
4245 /* We resolve conflicts with remaining reloads of the same type by
4246 excluding the intervals of reload registers by them from the
4247 interval of freed reload registers. Since we only keep track of
4248 one set of interval bounds, we might have to exclude somewhat
4249 more than what would be necessary if we used a HARD_REG_SET here.
4250 But this should only happen very infrequently, so there should
4251 be no reason to worry about it. */
4253 start_regno = regno;
4254 end_regno = regno + nregs;
4255 if (check_opnum || check_any)
4257 for (i = n_reloads - 1; i >= 0; i--)
4259 if (rld[i].when_needed == type
4260 && (check_any || rld[i].opnum == opnum)
4263 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4264 unsigned int conflict_end
4266 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4268 /* If there is an overlap with the first to-be-freed register,
4269 adjust the interval start. */
4270 if (conflict_start <= start_regno && conflict_end > start_regno)
4271 start_regno = conflict_end;
4272 /* Otherwise, if there is a conflict with one of the other
4273 to-be-freed registers, adjust the interval end. */
4274 if (conflict_start > start_regno && conflict_start < end_regno)
4275 end_regno = conflict_start;
4280 for (r = start_regno; r < end_regno; r++)
4281 CLEAR_HARD_REG_BIT (*used_in_set, r);
4284 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4285 specified by OPNUM and TYPE. */
4288 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4292 /* In use for a RELOAD_OTHER means it's not available for anything. */
4293 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4294 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4300 /* In use for anything means we can't use it for RELOAD_OTHER. */
4301 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4302 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4303 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4306 for (i = 0; i < reload_n_operands; i++)
4307 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4308 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4309 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4310 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4311 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4312 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4317 case RELOAD_FOR_INPUT:
4318 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4319 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4322 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4325 /* If it is used for some other input, can't use it. */
4326 for (i = 0; i < reload_n_operands; i++)
4327 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4330 /* If it is used in a later operand's address, can't use it. */
4331 for (i = opnum + 1; i < reload_n_operands; i++)
4332 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4333 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4338 case RELOAD_FOR_INPUT_ADDRESS:
4339 /* Can't use a register if it is used for an input address for this
4340 operand or used as an input in an earlier one. */
4341 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4342 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4345 for (i = 0; i < opnum; i++)
4346 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4351 case RELOAD_FOR_INPADDR_ADDRESS:
4352 /* Can't use a register if it is used for an input address
4353 for this operand or used as an input in an earlier
4355 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4358 for (i = 0; i < opnum; i++)
4359 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4364 case RELOAD_FOR_OUTPUT_ADDRESS:
4365 /* Can't use a register if it is used for an output address for this
4366 operand or used as an output in this or a later operand. Note
4367 that multiple output operands are emitted in reverse order, so
4368 the conflicting ones are those with lower indices. */
4369 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4372 for (i = 0; i <= opnum; i++)
4373 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4378 case RELOAD_FOR_OUTADDR_ADDRESS:
4379 /* Can't use a register if it is used for an output address
4380 for this operand or used as an output in this or a
4381 later operand. Note that multiple output operands are
4382 emitted in reverse order, so the conflicting ones are
4383 those with lower indices. */
4384 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4387 for (i = 0; i <= opnum; i++)
4388 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4393 case RELOAD_FOR_OPERAND_ADDRESS:
4394 for (i = 0; i < reload_n_operands; i++)
4395 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4398 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4399 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4401 case RELOAD_FOR_OPADDR_ADDR:
4402 for (i = 0; i < reload_n_operands; i++)
4403 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4406 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4408 case RELOAD_FOR_OUTPUT:
4409 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4410 outputs, or an operand address for this or an earlier output.
4411 Note that multiple output operands are emitted in reverse order,
4412 so the conflicting ones are those with higher indices. */
4413 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4416 for (i = 0; i < reload_n_operands; i++)
4417 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4420 for (i = opnum; i < reload_n_operands; i++)
4421 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4422 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4427 case RELOAD_FOR_INSN:
4428 for (i = 0; i < reload_n_operands; i++)
4429 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4430 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4433 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4434 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4436 case RELOAD_FOR_OTHER_ADDRESS:
4437 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4442 /* Return 1 if the value in reload reg REGNO, as used by a reload
4443 needed for the part of the insn specified by OPNUM and TYPE,
4444 is still available in REGNO at the end of the insn.
4446 We can assume that the reload reg was already tested for availability
4447 at the time it is needed, and we should not check this again,
4448 in case the reg has already been marked in use. */
4451 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4458 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4459 its value must reach the end. */
4462 /* If this use is for part of the insn,
4463 its value reaches if no subsequent part uses the same register.
4464 Just like the above function, don't try to do this with lots
4467 case RELOAD_FOR_OTHER_ADDRESS:
4468 /* Here we check for everything else, since these don't conflict
4469 with anything else and everything comes later. */
4471 for (i = 0; i < reload_n_operands; i++)
4472 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4473 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4474 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4475 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4476 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4477 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4480 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4481 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4482 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4484 case RELOAD_FOR_INPUT_ADDRESS:
4485 case RELOAD_FOR_INPADDR_ADDRESS:
4486 /* Similar, except that we check only for this and subsequent inputs
4487 and the address of only subsequent inputs and we do not need
4488 to check for RELOAD_OTHER objects since they are known not to
4491 for (i = opnum; i < reload_n_operands; i++)
4492 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4495 for (i = opnum + 1; i < reload_n_operands; i++)
4496 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4497 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4500 for (i = 0; i < reload_n_operands; i++)
4501 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4502 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4503 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4506 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4509 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4510 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4511 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4513 case RELOAD_FOR_INPUT:
4514 /* Similar to input address, except we start at the next operand for
4515 both input and input address and we do not check for
4516 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4519 for (i = opnum + 1; i < reload_n_operands; i++)
4520 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4521 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4522 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4525 /* ... fall through ... */
4527 case RELOAD_FOR_OPERAND_ADDRESS:
4528 /* Check outputs and their addresses. */
4530 for (i = 0; i < reload_n_operands; i++)
4531 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4532 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4533 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4536 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4538 case RELOAD_FOR_OPADDR_ADDR:
4539 for (i = 0; i < reload_n_operands; i++)
4540 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4541 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4542 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4545 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4546 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4547 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4549 case RELOAD_FOR_INSN:
4550 /* These conflict with other outputs with RELOAD_OTHER. So
4551 we need only check for output addresses. */
4553 opnum = reload_n_operands;
4555 /* ... fall through ... */
4557 case RELOAD_FOR_OUTPUT:
4558 case RELOAD_FOR_OUTPUT_ADDRESS:
4559 case RELOAD_FOR_OUTADDR_ADDRESS:
4560 /* We already know these can't conflict with a later output. So the
4561 only thing to check are later output addresses.
4562 Note that multiple output operands are emitted in reverse order,
4563 so the conflicting ones are those with lower indices. */
4564 for (i = 0; i < opnum; i++)
4565 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4566 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4575 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4578 This function uses the same algorithm as reload_reg_free_p above. */
4581 reloads_conflict (int r1, int r2)
4583 enum reload_type r1_type = rld[r1].when_needed;
4584 enum reload_type r2_type = rld[r2].when_needed;
4585 int r1_opnum = rld[r1].opnum;
4586 int r2_opnum = rld[r2].opnum;
4588 /* RELOAD_OTHER conflicts with everything. */
4589 if (r2_type == RELOAD_OTHER)
4592 /* Otherwise, check conflicts differently for each type. */
4596 case RELOAD_FOR_INPUT:
4597 return (r2_type == RELOAD_FOR_INSN
4598 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4599 || r2_type == RELOAD_FOR_OPADDR_ADDR
4600 || r2_type == RELOAD_FOR_INPUT
4601 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4602 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4603 && r2_opnum > r1_opnum));
4605 case RELOAD_FOR_INPUT_ADDRESS:
4606 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4607 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4609 case RELOAD_FOR_INPADDR_ADDRESS:
4610 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4611 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4613 case RELOAD_FOR_OUTPUT_ADDRESS:
4614 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4615 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4617 case RELOAD_FOR_OUTADDR_ADDRESS:
4618 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4619 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4621 case RELOAD_FOR_OPERAND_ADDRESS:
4622 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4623 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4625 case RELOAD_FOR_OPADDR_ADDR:
4626 return (r2_type == RELOAD_FOR_INPUT
4627 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4629 case RELOAD_FOR_OUTPUT:
4630 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4631 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4632 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4633 && r2_opnum >= r1_opnum));
4635 case RELOAD_FOR_INSN:
4636 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4637 || r2_type == RELOAD_FOR_INSN
4638 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4640 case RELOAD_FOR_OTHER_ADDRESS:
4641 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4651 /* Indexed by reload number, 1 if incoming value
4652 inherited from previous insns. */
4653 char reload_inherited[MAX_RELOADS];
4655 /* For an inherited reload, this is the insn the reload was inherited from,
4656 if we know it. Otherwise, this is 0. */
4657 rtx reload_inheritance_insn[MAX_RELOADS];
4659 /* If nonzero, this is a place to get the value of the reload,
4660 rather than using reload_in. */
4661 rtx reload_override_in[MAX_RELOADS];
4663 /* For each reload, the hard register number of the register used,
4664 or -1 if we did not need a register for this reload. */
4665 int reload_spill_index[MAX_RELOADS];
4667 /* Subroutine of free_for_value_p, used to check a single register.
4668 START_REGNO is the starting regno of the full reload register
4669 (possibly comprising multiple hard registers) that we are considering. */
4672 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4673 enum reload_type type, rtx value, rtx out,
4674 int reloadnum, int ignore_address_reloads)
4677 /* Set if we see an input reload that must not share its reload register
4678 with any new earlyclobber, but might otherwise share the reload
4679 register with an output or input-output reload. */
4680 int check_earlyclobber = 0;
4684 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4687 if (out == const0_rtx)
4693 /* We use some pseudo 'time' value to check if the lifetimes of the
4694 new register use would overlap with the one of a previous reload
4695 that is not read-only or uses a different value.
4696 The 'time' used doesn't have to be linear in any shape or form, just
4698 Some reload types use different 'buckets' for each operand.
4699 So there are MAX_RECOG_OPERANDS different time values for each
4701 We compute TIME1 as the time when the register for the prospective
4702 new reload ceases to be live, and TIME2 for each existing
4703 reload as the time when that the reload register of that reload
4705 Where there is little to be gained by exact lifetime calculations,
4706 we just make conservative assumptions, i.e. a longer lifetime;
4707 this is done in the 'default:' cases. */
4710 case RELOAD_FOR_OTHER_ADDRESS:
4711 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4712 time1 = copy ? 0 : 1;
4715 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4717 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4718 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4719 respectively, to the time values for these, we get distinct time
4720 values. To get distinct time values for each operand, we have to
4721 multiply opnum by at least three. We round that up to four because
4722 multiply by four is often cheaper. */
4723 case RELOAD_FOR_INPADDR_ADDRESS:
4724 time1 = opnum * 4 + 2;
4726 case RELOAD_FOR_INPUT_ADDRESS:
4727 time1 = opnum * 4 + 3;
4729 case RELOAD_FOR_INPUT:
4730 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4731 executes (inclusive). */
4732 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4734 case RELOAD_FOR_OPADDR_ADDR:
4736 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4737 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4739 case RELOAD_FOR_OPERAND_ADDRESS:
4740 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4742 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4744 case RELOAD_FOR_OUTADDR_ADDRESS:
4745 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4747 case RELOAD_FOR_OUTPUT_ADDRESS:
4748 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4751 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4754 for (i = 0; i < n_reloads; i++)
4756 rtx reg = rld[i].reg_rtx;
4757 if (reg && GET_CODE (reg) == REG
4758 && ((unsigned) regno - true_regnum (reg)
4759 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned) 1)
4762 rtx other_input = rld[i].in;
4764 /* If the other reload loads the same input value, that
4765 will not cause a conflict only if it's loading it into
4766 the same register. */
4767 if (true_regnum (reg) != start_regno)
4768 other_input = NULL_RTX;
4769 if (! other_input || ! rtx_equal_p (other_input, value)
4770 || rld[i].out || out)
4773 switch (rld[i].when_needed)
4775 case RELOAD_FOR_OTHER_ADDRESS:
4778 case RELOAD_FOR_INPADDR_ADDRESS:
4779 /* find_reloads makes sure that a
4780 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4781 by at most one - the first -
4782 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4783 address reload is inherited, the address address reload
4784 goes away, so we can ignore this conflict. */
4785 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4786 && ignore_address_reloads
4787 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4788 Then the address address is still needed to store
4789 back the new address. */
4790 && ! rld[reloadnum].out)
4792 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4793 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4795 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4796 && ignore_address_reloads
4797 /* Unless we are reloading an auto_inc expression. */
4798 && ! rld[reloadnum].out)
4800 time2 = rld[i].opnum * 4 + 2;
4802 case RELOAD_FOR_INPUT_ADDRESS:
4803 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4804 && ignore_address_reloads
4805 && ! rld[reloadnum].out)
4807 time2 = rld[i].opnum * 4 + 3;
4809 case RELOAD_FOR_INPUT:
4810 time2 = rld[i].opnum * 4 + 4;
4811 check_earlyclobber = 1;
4813 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4814 == MAX_RECOG_OPERAND * 4 */
4815 case RELOAD_FOR_OPADDR_ADDR:
4816 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4817 && ignore_address_reloads
4818 && ! rld[reloadnum].out)
4820 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4822 case RELOAD_FOR_OPERAND_ADDRESS:
4823 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4824 check_earlyclobber = 1;
4826 case RELOAD_FOR_INSN:
4827 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4829 case RELOAD_FOR_OUTPUT:
4830 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4831 instruction is executed. */
4832 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4834 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4835 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4837 case RELOAD_FOR_OUTADDR_ADDRESS:
4838 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4839 && ignore_address_reloads
4840 && ! rld[reloadnum].out)
4842 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4844 case RELOAD_FOR_OUTPUT_ADDRESS:
4845 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4848 /* If there is no conflict in the input part, handle this
4849 like an output reload. */
4850 if (! rld[i].in || rtx_equal_p (other_input, value))
4852 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4853 /* Earlyclobbered outputs must conflict with inputs. */
4854 if (earlyclobber_operand_p (rld[i].out))
4855 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4860 /* RELOAD_OTHER might be live beyond instruction execution,
4861 but this is not obvious when we set time2 = 1. So check
4862 here if there might be a problem with the new reload
4863 clobbering the register used by the RELOAD_OTHER. */
4871 && (! rld[i].in || rld[i].out
4872 || ! rtx_equal_p (other_input, value)))
4873 || (out && rld[reloadnum].out_reg
4874 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4880 /* Earlyclobbered outputs must conflict with inputs. */
4881 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4887 /* Return 1 if the value in reload reg REGNO, as used by a reload
4888 needed for the part of the insn specified by OPNUM and TYPE,
4889 may be used to load VALUE into it.
4891 MODE is the mode in which the register is used, this is needed to
4892 determine how many hard regs to test.
4894 Other read-only reloads with the same value do not conflict
4895 unless OUT is nonzero and these other reloads have to live while
4896 output reloads live.
4897 If OUT is CONST0_RTX, this is a special case: it means that the
4898 test should not be for using register REGNO as reload register, but
4899 for copying from register REGNO into the reload register.
4901 RELOADNUM is the number of the reload we want to load this value for;
4902 a reload does not conflict with itself.
4904 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4905 reloads that load an address for the very reload we are considering.
4907 The caller has to make sure that there is no conflict with the return
4911 free_for_value_p (int regno, enum machine_mode mode, int opnum,
4912 enum reload_type type, rtx value, rtx out, int reloadnum,
4913 int ignore_address_reloads)
4915 int nregs = HARD_REGNO_NREGS (regno, mode);
4917 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4918 value, out, reloadnum,
4919 ignore_address_reloads))
4924 /* Determine whether the reload reg X overlaps any rtx'es used for
4925 overriding inheritance. Return nonzero if so. */
4928 conflicts_with_override (rtx x)
4931 for (i = 0; i < n_reloads; i++)
4932 if (reload_override_in[i]
4933 && reg_overlap_mentioned_p (x, reload_override_in[i]))
4938 /* Give an error message saying we failed to find a reload for INSN,
4939 and clear out reload R. */
4941 failed_reload (rtx insn, int r)
4943 if (asm_noperands (PATTERN (insn)) < 0)
4944 /* It's the compiler's fault. */
4945 fatal_insn ("could not find a spill register", insn);
4947 /* It's the user's fault; the operand's mode and constraint
4948 don't match. Disable this reload so we don't crash in final. */
4949 error_for_asm (insn,
4950 "`asm' operand constraint incompatible with operand size");
4954 rld[r].optional = 1;
4955 rld[r].secondary_p = 1;
4958 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
4959 for reload R. If it's valid, get an rtx for it. Return nonzero if
4962 set_reload_reg (int i, int r)
4965 rtx reg = spill_reg_rtx[i];
4967 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
4968 spill_reg_rtx[i] = reg
4969 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
4971 regno = true_regnum (reg);
4973 /* Detect when the reload reg can't hold the reload mode.
4974 This used to be one `if', but Sequent compiler can't handle that. */
4975 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
4977 enum machine_mode test_mode = VOIDmode;
4979 test_mode = GET_MODE (rld[r].in);
4980 /* If rld[r].in has VOIDmode, it means we will load it
4981 in whatever mode the reload reg has: to wit, rld[r].mode.
4982 We have already tested that for validity. */
4983 /* Aside from that, we need to test that the expressions
4984 to reload from or into have modes which are valid for this
4985 reload register. Otherwise the reload insns would be invalid. */
4986 if (! (rld[r].in != 0 && test_mode != VOIDmode
4987 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
4988 if (! (rld[r].out != 0
4989 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
4991 /* The reg is OK. */
4994 /* Mark as in use for this insn the reload regs we use
4996 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
4997 rld[r].when_needed, rld[r].mode);
4999 rld[r].reg_rtx = reg;
5000 reload_spill_index[r] = spill_regs[i];
5007 /* Find a spill register to use as a reload register for reload R.
5008 LAST_RELOAD is nonzero if this is the last reload for the insn being
5011 Set rld[R].reg_rtx to the register allocated.
5013 We return 1 if successful, or 0 if we couldn't find a spill reg and
5014 we didn't change anything. */
5017 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5022 /* If we put this reload ahead, thinking it is a group,
5023 then insist on finding a group. Otherwise we can grab a
5024 reg that some other reload needs.
5025 (That can happen when we have a 68000 DATA_OR_FP_REG
5026 which is a group of data regs or one fp reg.)
5027 We need not be so restrictive if there are no more reloads
5030 ??? Really it would be nicer to have smarter handling
5031 for that kind of reg class, where a problem like this is normal.
5032 Perhaps those classes should be avoided for reloading
5033 by use of more alternatives. */
5035 int force_group = rld[r].nregs > 1 && ! last_reload;
5037 /* If we want a single register and haven't yet found one,
5038 take any reg in the right class and not in use.
5039 If we want a consecutive group, here is where we look for it.
5041 We use two passes so we can first look for reload regs to
5042 reuse, which are already in use for other reloads in this insn,
5043 and only then use additional registers.
5044 I think that maximizing reuse is needed to make sure we don't
5045 run out of reload regs. Suppose we have three reloads, and
5046 reloads A and B can share regs. These need two regs.
5047 Suppose A and B are given different regs.
5048 That leaves none for C. */
5049 for (pass = 0; pass < 2; pass++)
5051 /* I is the index in spill_regs.
5052 We advance it round-robin between insns to use all spill regs
5053 equally, so that inherited reloads have a chance
5054 of leapfrogging each other. */
5058 for (count = 0; count < n_spills; count++)
5060 int class = (int) rld[r].class;
5066 regnum = spill_regs[i];
5068 if ((reload_reg_free_p (regnum, rld[r].opnum,
5071 /* We check reload_reg_used to make sure we
5072 don't clobber the return register. */
5073 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5074 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5075 rld[r].when_needed, rld[r].in,
5077 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5078 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5079 /* Look first for regs to share, then for unshared. But
5080 don't share regs used for inherited reloads; they are
5081 the ones we want to preserve. */
5083 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5085 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5088 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5089 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5090 (on 68000) got us two FP regs. If NR is 1,
5091 we would reject both of them. */
5094 /* If we need only one reg, we have already won. */
5097 /* But reject a single reg if we demand a group. */
5102 /* Otherwise check that as many consecutive regs as we need
5103 are available here. */
5106 int regno = regnum + nr - 1;
5107 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5108 && spill_reg_order[regno] >= 0
5109 && reload_reg_free_p (regno, rld[r].opnum,
5110 rld[r].when_needed)))
5119 /* If we found something on pass 1, omit pass 2. */
5120 if (count < n_spills)
5124 /* We should have found a spill register by now. */
5125 if (count >= n_spills)
5128 /* I is the index in SPILL_REG_RTX of the reload register we are to
5129 allocate. Get an rtx for it and find its register number. */
5131 return set_reload_reg (i, r);
5134 /* Initialize all the tables needed to allocate reload registers.
5135 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5136 is the array we use to restore the reg_rtx field for every reload. */
5139 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5143 for (i = 0; i < n_reloads; i++)
5144 rld[i].reg_rtx = save_reload_reg_rtx[i];
5146 memset (reload_inherited, 0, MAX_RELOADS);
5147 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5148 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5150 CLEAR_HARD_REG_SET (reload_reg_used);
5151 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5152 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5153 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5154 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5155 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5157 CLEAR_HARD_REG_SET (reg_used_in_insn);
5160 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5161 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5162 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5163 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5164 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5165 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5168 for (i = 0; i < reload_n_operands; i++)
5170 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5171 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5172 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5173 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5174 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5175 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5178 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5180 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5182 for (i = 0; i < n_reloads; i++)
5183 /* If we have already decided to use a certain register,
5184 don't use it in another way. */
5186 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5187 rld[i].when_needed, rld[i].mode);
5190 /* Assign hard reg targets for the pseudo-registers we must reload
5191 into hard regs for this insn.
5192 Also output the instructions to copy them in and out of the hard regs.
5194 For machines with register classes, we are responsible for
5195 finding a reload reg in the proper class. */
5198 choose_reload_regs (struct insn_chain *chain)
5200 rtx insn = chain->insn;
5202 unsigned int max_group_size = 1;
5203 enum reg_class group_class = NO_REGS;
5204 int pass, win, inheritance;
5206 rtx save_reload_reg_rtx[MAX_RELOADS];
5208 /* In order to be certain of getting the registers we need,
5209 we must sort the reloads into order of increasing register class.
5210 Then our grabbing of reload registers will parallel the process
5211 that provided the reload registers.
5213 Also note whether any of the reloads wants a consecutive group of regs.
5214 If so, record the maximum size of the group desired and what
5215 register class contains all the groups needed by this insn. */
5217 for (j = 0; j < n_reloads; j++)
5219 reload_order[j] = j;
5220 reload_spill_index[j] = -1;
5222 if (rld[j].nregs > 1)
5224 max_group_size = MAX (rld[j].nregs, max_group_size);
5226 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5229 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5233 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5235 /* If -O, try first with inheritance, then turning it off.
5236 If not -O, don't do inheritance.
5237 Using inheritance when not optimizing leads to paradoxes
5238 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5239 because one side of the comparison might be inherited. */
5241 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5243 choose_reload_regs_init (chain, save_reload_reg_rtx);
5245 /* Process the reloads in order of preference just found.
5246 Beyond this point, subregs can be found in reload_reg_rtx.
5248 This used to look for an existing reloaded home for all of the
5249 reloads, and only then perform any new reloads. But that could lose
5250 if the reloads were done out of reg-class order because a later
5251 reload with a looser constraint might have an old home in a register
5252 needed by an earlier reload with a tighter constraint.
5254 To solve this, we make two passes over the reloads, in the order
5255 described above. In the first pass we try to inherit a reload
5256 from a previous insn. If there is a later reload that needs a
5257 class that is a proper subset of the class being processed, we must
5258 also allocate a spill register during the first pass.
5260 Then make a second pass over the reloads to allocate any reloads
5261 that haven't been given registers yet. */
5263 for (j = 0; j < n_reloads; j++)
5265 int r = reload_order[j];
5266 rtx search_equiv = NULL_RTX;
5268 /* Ignore reloads that got marked inoperative. */
5269 if (rld[r].out == 0 && rld[r].in == 0
5270 && ! rld[r].secondary_p)
5273 /* If find_reloads chose to use reload_in or reload_out as a reload
5274 register, we don't need to chose one. Otherwise, try even if it
5275 found one since we might save an insn if we find the value lying
5277 Try also when reload_in is a pseudo without a hard reg. */
5278 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5279 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5280 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5281 && GET_CODE (rld[r].in) != MEM
5282 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5285 #if 0 /* No longer needed for correct operation.
5286 It might give better code, or might not; worth an experiment? */
5287 /* If this is an optional reload, we can't inherit from earlier insns
5288 until we are sure that any non-optional reloads have been allocated.
5289 The following code takes advantage of the fact that optional reloads
5290 are at the end of reload_order. */
5291 if (rld[r].optional != 0)
5292 for (i = 0; i < j; i++)
5293 if ((rld[reload_order[i]].out != 0
5294 || rld[reload_order[i]].in != 0
5295 || rld[reload_order[i]].secondary_p)
5296 && ! rld[reload_order[i]].optional
5297 && rld[reload_order[i]].reg_rtx == 0)
5298 allocate_reload_reg (chain, reload_order[i], 0);
5301 /* First see if this pseudo is already available as reloaded
5302 for a previous insn. We cannot try to inherit for reloads
5303 that are smaller than the maximum number of registers needed
5304 for groups unless the register we would allocate cannot be used
5307 We could check here to see if this is a secondary reload for
5308 an object that is already in a register of the desired class.
5309 This would avoid the need for the secondary reload register.
5310 But this is complex because we can't easily determine what
5311 objects might want to be loaded via this reload. So let a
5312 register be allocated here. In `emit_reload_insns' we suppress
5313 one of the loads in the case described above. */
5319 enum machine_mode mode = VOIDmode;
5323 else if (GET_CODE (rld[r].in) == REG)
5325 regno = REGNO (rld[r].in);
5326 mode = GET_MODE (rld[r].in);
5328 else if (GET_CODE (rld[r].in_reg) == REG)
5330 regno = REGNO (rld[r].in_reg);
5331 mode = GET_MODE (rld[r].in_reg);
5333 else if (GET_CODE (rld[r].in_reg) == SUBREG
5334 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5336 byte = SUBREG_BYTE (rld[r].in_reg);
5337 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5338 if (regno < FIRST_PSEUDO_REGISTER)
5339 regno = subreg_regno (rld[r].in_reg);
5340 mode = GET_MODE (rld[r].in_reg);
5343 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5344 || GET_CODE (rld[r].in_reg) == PRE_DEC
5345 || GET_CODE (rld[r].in_reg) == POST_INC
5346 || GET_CODE (rld[r].in_reg) == POST_DEC)
5347 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5349 regno = REGNO (XEXP (rld[r].in_reg, 0));
5350 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5351 rld[r].out = rld[r].in;
5355 /* This won't work, since REGNO can be a pseudo reg number.
5356 Also, it takes much more hair to keep track of all the things
5357 that can invalidate an inherited reload of part of a pseudoreg. */
5358 else if (GET_CODE (rld[r].in) == SUBREG
5359 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5360 regno = subreg_regno (rld[r].in);
5363 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5365 enum reg_class class = rld[r].class, last_class;
5366 rtx last_reg = reg_last_reload_reg[regno];
5367 enum machine_mode need_mode;
5369 i = REGNO (last_reg);
5370 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5371 last_class = REGNO_REG_CLASS (i);
5377 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5378 GET_MODE_CLASS (mode));
5381 #ifdef CANNOT_CHANGE_MODE_CLASS
5382 (!REG_CANNOT_CHANGE_MODE_P (i, GET_MODE (last_reg),
5386 (GET_MODE_SIZE (GET_MODE (last_reg))
5387 >= GET_MODE_SIZE (need_mode))
5388 #ifdef CANNOT_CHANGE_MODE_CLASS
5391 && reg_reloaded_contents[i] == regno
5392 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5393 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5394 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5395 /* Even if we can't use this register as a reload
5396 register, we might use it for reload_override_in,
5397 if copying it to the desired class is cheap
5399 || ((REGISTER_MOVE_COST (mode, last_class, class)
5400 < MEMORY_MOVE_COST (mode, class, 1))
5401 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5402 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5406 #ifdef SECONDARY_MEMORY_NEEDED
5407 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5412 && (rld[r].nregs == max_group_size
5413 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5415 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5416 rld[r].when_needed, rld[r].in,
5419 /* If a group is needed, verify that all the subsequent
5420 registers still have their values intact. */
5421 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5424 for (k = 1; k < nr; k++)
5425 if (reg_reloaded_contents[i + k] != regno
5426 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5434 last_reg = (GET_MODE (last_reg) == mode
5435 ? last_reg : gen_rtx_REG (mode, i));
5438 for (k = 0; k < nr; k++)
5439 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5442 /* We found a register that contains the
5443 value we need. If this register is the
5444 same as an `earlyclobber' operand of the
5445 current insn, just mark it as a place to
5446 reload from since we can't use it as the
5447 reload register itself. */
5449 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5450 if (reg_overlap_mentioned_for_reload_p
5451 (reg_last_reload_reg[regno],
5452 reload_earlyclobbers[i1]))
5455 if (i1 != n_earlyclobbers
5456 || ! (free_for_value_p (i, rld[r].mode,
5458 rld[r].when_needed, rld[r].in,
5460 /* Don't use it if we'd clobber a pseudo reg. */
5461 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5463 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5464 /* Don't clobber the frame pointer. */
5465 || (i == HARD_FRAME_POINTER_REGNUM
5466 && frame_pointer_needed
5468 /* Don't really use the inherited spill reg
5469 if we need it wider than we've got it. */
5470 || (GET_MODE_SIZE (rld[r].mode)
5471 > GET_MODE_SIZE (mode))
5474 /* If find_reloads chose reload_out as reload
5475 register, stay with it - that leaves the
5476 inherited register for subsequent reloads. */
5477 || (rld[r].out && rld[r].reg_rtx
5478 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5480 if (! rld[r].optional)
5482 reload_override_in[r] = last_reg;
5483 reload_inheritance_insn[r]
5484 = reg_reloaded_insn[i];
5490 /* We can use this as a reload reg. */
5491 /* Mark the register as in use for this part of
5493 mark_reload_reg_in_use (i,
5497 rld[r].reg_rtx = last_reg;
5498 reload_inherited[r] = 1;
5499 reload_inheritance_insn[r]
5500 = reg_reloaded_insn[i];
5501 reload_spill_index[r] = i;
5502 for (k = 0; k < nr; k++)
5503 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5511 /* Here's another way to see if the value is already lying around. */
5514 && ! reload_inherited[r]
5516 && (CONSTANT_P (rld[r].in)
5517 || GET_CODE (rld[r].in) == PLUS
5518 || GET_CODE (rld[r].in) == REG
5519 || GET_CODE (rld[r].in) == MEM)
5520 && (rld[r].nregs == max_group_size
5521 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5522 search_equiv = rld[r].in;
5523 /* If this is an output reload from a simple move insn, look
5524 if an equivalence for the input is available. */
5525 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5527 rtx set = single_set (insn);
5530 && rtx_equal_p (rld[r].out, SET_DEST (set))
5531 && CONSTANT_P (SET_SRC (set)))
5532 search_equiv = SET_SRC (set);
5538 = find_equiv_reg (search_equiv, insn, rld[r].class,
5539 -1, NULL, 0, rld[r].mode);
5544 if (GET_CODE (equiv) == REG)
5545 regno = REGNO (equiv);
5546 else if (GET_CODE (equiv) == SUBREG)
5548 /* This must be a SUBREG of a hard register.
5549 Make a new REG since this might be used in an
5550 address and not all machines support SUBREGs
5552 regno = subreg_regno (equiv);
5553 equiv = gen_rtx_REG (rld[r].mode, regno);
5559 /* If we found a spill reg, reject it unless it is free
5560 and of the desired class. */
5564 int bad_for_class = 0;
5565 int max_regno = regno + rld[r].nregs;
5567 for (i = regno; i < max_regno; i++)
5569 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5571 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5576 && ! free_for_value_p (regno, rld[r].mode,
5577 rld[r].opnum, rld[r].when_needed,
5578 rld[r].in, rld[r].out, r, 1))
5583 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5586 /* We found a register that contains the value we need.
5587 If this register is the same as an `earlyclobber' operand
5588 of the current insn, just mark it as a place to reload from
5589 since we can't use it as the reload register itself. */
5592 for (i = 0; i < n_earlyclobbers; i++)
5593 if (reg_overlap_mentioned_for_reload_p (equiv,
5594 reload_earlyclobbers[i]))
5596 if (! rld[r].optional)
5597 reload_override_in[r] = equiv;
5602 /* If the equiv register we have found is explicitly clobbered
5603 in the current insn, it depends on the reload type if we
5604 can use it, use it for reload_override_in, or not at all.
5605 In particular, we then can't use EQUIV for a
5606 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5610 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5611 switch (rld[r].when_needed)
5613 case RELOAD_FOR_OTHER_ADDRESS:
5614 case RELOAD_FOR_INPADDR_ADDRESS:
5615 case RELOAD_FOR_INPUT_ADDRESS:
5616 case RELOAD_FOR_OPADDR_ADDR:
5619 case RELOAD_FOR_INPUT:
5620 case RELOAD_FOR_OPERAND_ADDRESS:
5621 if (! rld[r].optional)
5622 reload_override_in[r] = equiv;
5628 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5629 switch (rld[r].when_needed)
5631 case RELOAD_FOR_OTHER_ADDRESS:
5632 case RELOAD_FOR_INPADDR_ADDRESS:
5633 case RELOAD_FOR_INPUT_ADDRESS:
5634 case RELOAD_FOR_OPADDR_ADDR:
5635 case RELOAD_FOR_OPERAND_ADDRESS:
5636 case RELOAD_FOR_INPUT:
5639 if (! rld[r].optional)
5640 reload_override_in[r] = equiv;
5648 /* If we found an equivalent reg, say no code need be generated
5649 to load it, and use it as our reload reg. */
5651 && (regno != HARD_FRAME_POINTER_REGNUM
5652 || !frame_pointer_needed))
5654 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5656 rld[r].reg_rtx = equiv;
5657 reload_inherited[r] = 1;
5659 /* If reg_reloaded_valid is not set for this register,
5660 there might be a stale spill_reg_store lying around.
5661 We must clear it, since otherwise emit_reload_insns
5662 might delete the store. */
5663 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5664 spill_reg_store[regno] = NULL_RTX;
5665 /* If any of the hard registers in EQUIV are spill
5666 registers, mark them as in use for this insn. */
5667 for (k = 0; k < nr; k++)
5669 i = spill_reg_order[regno + k];
5672 mark_reload_reg_in_use (regno, rld[r].opnum,
5675 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5682 /* If we found a register to use already, or if this is an optional
5683 reload, we are done. */
5684 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5688 /* No longer needed for correct operation. Might or might
5689 not give better code on the average. Want to experiment? */
5691 /* See if there is a later reload that has a class different from our
5692 class that intersects our class or that requires less register
5693 than our reload. If so, we must allocate a register to this
5694 reload now, since that reload might inherit a previous reload
5695 and take the only available register in our class. Don't do this
5696 for optional reloads since they will force all previous reloads
5697 to be allocated. Also don't do this for reloads that have been
5700 for (i = j + 1; i < n_reloads; i++)
5702 int s = reload_order[i];
5704 if ((rld[s].in == 0 && rld[s].out == 0
5705 && ! rld[s].secondary_p)
5709 if ((rld[s].class != rld[r].class
5710 && reg_classes_intersect_p (rld[r].class,
5712 || rld[s].nregs < rld[r].nregs)
5719 allocate_reload_reg (chain, r, j == n_reloads - 1);
5723 /* Now allocate reload registers for anything non-optional that
5724 didn't get one yet. */
5725 for (j = 0; j < n_reloads; j++)
5727 int r = reload_order[j];
5729 /* Ignore reloads that got marked inoperative. */
5730 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5733 /* Skip reloads that already have a register allocated or are
5735 if (rld[r].reg_rtx != 0 || rld[r].optional)
5738 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5742 /* If that loop got all the way, we have won. */
5749 /* Loop around and try without any inheritance. */
5754 /* First undo everything done by the failed attempt
5755 to allocate with inheritance. */
5756 choose_reload_regs_init (chain, save_reload_reg_rtx);
5758 /* Some sanity tests to verify that the reloads found in the first
5759 pass are identical to the ones we have now. */
5760 if (chain->n_reloads != n_reloads)
5763 for (i = 0; i < n_reloads; i++)
5765 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5767 if (chain->rld[i].when_needed != rld[i].when_needed)
5769 for (j = 0; j < n_spills; j++)
5770 if (spill_regs[j] == chain->rld[i].regno)
5771 if (! set_reload_reg (j, i))
5772 failed_reload (chain->insn, i);
5776 /* If we thought we could inherit a reload, because it seemed that
5777 nothing else wanted the same reload register earlier in the insn,
5778 verify that assumption, now that all reloads have been assigned.
5779 Likewise for reloads where reload_override_in has been set. */
5781 /* If doing expensive optimizations, do one preliminary pass that doesn't
5782 cancel any inheritance, but removes reloads that have been needed only
5783 for reloads that we know can be inherited. */
5784 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5786 for (j = 0; j < n_reloads; j++)
5788 int r = reload_order[j];
5790 if (reload_inherited[r] && rld[r].reg_rtx)
5791 check_reg = rld[r].reg_rtx;
5792 else if (reload_override_in[r]
5793 && (GET_CODE (reload_override_in[r]) == REG
5794 || GET_CODE (reload_override_in[r]) == SUBREG))
5795 check_reg = reload_override_in[r];
5798 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5799 rld[r].opnum, rld[r].when_needed, rld[r].in,
5800 (reload_inherited[r]
5801 ? rld[r].out : const0_rtx),
5806 reload_inherited[r] = 0;
5807 reload_override_in[r] = 0;
5809 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5810 reload_override_in, then we do not need its related
5811 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5812 likewise for other reload types.
5813 We handle this by removing a reload when its only replacement
5814 is mentioned in reload_in of the reload we are going to inherit.
5815 A special case are auto_inc expressions; even if the input is
5816 inherited, we still need the address for the output. We can
5817 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5818 If we succeeded removing some reload and we are doing a preliminary
5819 pass just to remove such reloads, make another pass, since the
5820 removal of one reload might allow us to inherit another one. */
5822 && rld[r].out != rld[r].in
5823 && remove_address_replacements (rld[r].in) && pass)
5828 /* Now that reload_override_in is known valid,
5829 actually override reload_in. */
5830 for (j = 0; j < n_reloads; j++)
5831 if (reload_override_in[j])
5832 rld[j].in = reload_override_in[j];
5834 /* If this reload won't be done because it has been canceled or is
5835 optional and not inherited, clear reload_reg_rtx so other
5836 routines (such as subst_reloads) don't get confused. */
5837 for (j = 0; j < n_reloads; j++)
5838 if (rld[j].reg_rtx != 0
5839 && ((rld[j].optional && ! reload_inherited[j])
5840 || (rld[j].in == 0 && rld[j].out == 0
5841 && ! rld[j].secondary_p)))
5843 int regno = true_regnum (rld[j].reg_rtx);
5845 if (spill_reg_order[regno] >= 0)
5846 clear_reload_reg_in_use (regno, rld[j].opnum,
5847 rld[j].when_needed, rld[j].mode);
5849 reload_spill_index[j] = -1;
5852 /* Record which pseudos and which spill regs have output reloads. */
5853 for (j = 0; j < n_reloads; j++)
5855 int r = reload_order[j];
5857 i = reload_spill_index[r];
5859 /* I is nonneg if this reload uses a register.
5860 If rld[r].reg_rtx is 0, this is an optional reload
5861 that we opted to ignore. */
5862 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5863 && rld[r].reg_rtx != 0)
5865 int nregno = REGNO (rld[r].out_reg);
5868 if (nregno < FIRST_PSEUDO_REGISTER)
5869 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5872 reg_has_output_reload[nregno + nr] = 1;
5876 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5878 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5881 if (rld[r].when_needed != RELOAD_OTHER
5882 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5883 && rld[r].when_needed != RELOAD_FOR_INSN)
5889 /* Deallocate the reload register for reload R. This is called from
5890 remove_address_replacements. */
5893 deallocate_reload_reg (int r)
5897 if (! rld[r].reg_rtx)
5899 regno = true_regnum (rld[r].reg_rtx);
5901 if (spill_reg_order[regno] >= 0)
5902 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5904 reload_spill_index[r] = -1;
5907 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
5908 reloads of the same item for fear that we might not have enough reload
5909 registers. However, normally they will get the same reload register
5910 and hence actually need not be loaded twice.
5912 Here we check for the most common case of this phenomenon: when we have
5913 a number of reloads for the same object, each of which were allocated
5914 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5915 reload, and is not modified in the insn itself. If we find such,
5916 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5917 This will not increase the number of spill registers needed and will
5918 prevent redundant code. */
5921 merge_assigned_reloads (rtx insn)
5925 /* Scan all the reloads looking for ones that only load values and
5926 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5927 assigned and not modified by INSN. */
5929 for (i = 0; i < n_reloads; i++)
5931 int conflicting_input = 0;
5932 int max_input_address_opnum = -1;
5933 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5935 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5936 || rld[i].out != 0 || rld[i].reg_rtx == 0
5937 || reg_set_p (rld[i].reg_rtx, insn))
5940 /* Look at all other reloads. Ensure that the only use of this
5941 reload_reg_rtx is in a reload that just loads the same value
5942 as we do. Note that any secondary reloads must be of the identical
5943 class since the values, modes, and result registers are the
5944 same, so we need not do anything with any secondary reloads. */
5946 for (j = 0; j < n_reloads; j++)
5948 if (i == j || rld[j].reg_rtx == 0
5949 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
5953 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5954 && rld[j].opnum > max_input_address_opnum)
5955 max_input_address_opnum = rld[j].opnum;
5957 /* If the reload regs aren't exactly the same (e.g, different modes)
5958 or if the values are different, we can't merge this reload.
5959 But if it is an input reload, we might still merge
5960 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
5962 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5963 || rld[j].out != 0 || rld[j].in == 0
5964 || ! rtx_equal_p (rld[i].in, rld[j].in))
5966 if (rld[j].when_needed != RELOAD_FOR_INPUT
5967 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
5968 || rld[i].opnum > rld[j].opnum)
5969 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
5971 conflicting_input = 1;
5972 if (min_conflicting_input_opnum > rld[j].opnum)
5973 min_conflicting_input_opnum = rld[j].opnum;
5977 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5978 we, in fact, found any matching reloads. */
5981 && max_input_address_opnum <= min_conflicting_input_opnum)
5983 for (j = 0; j < n_reloads; j++)
5984 if (i != j && rld[j].reg_rtx != 0
5985 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5986 && (! conflicting_input
5987 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5988 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
5990 rld[i].when_needed = RELOAD_OTHER;
5992 reload_spill_index[j] = -1;
5993 transfer_replacements (i, j);
5996 /* If this is now RELOAD_OTHER, look for any reloads that load
5997 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5998 if they were for inputs, RELOAD_OTHER for outputs. Note that
5999 this test is equivalent to looking for reloads for this operand
6001 /* We must take special care when there are two or more reloads to
6002 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6003 same value or a part of it; we must not change its type if there
6004 is a conflicting input. */
6006 if (rld[i].when_needed == RELOAD_OTHER)
6007 for (j = 0; j < n_reloads; j++)
6009 && rld[j].when_needed != RELOAD_OTHER
6010 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6011 && (! conflicting_input
6012 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6013 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6014 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6020 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6021 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6022 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6024 /* Check to see if we accidentally converted two reloads
6025 that use the same reload register with different inputs
6026 to the same type. If so, the resulting code won't work,
6029 for (k = 0; k < j; k++)
6030 if (rld[k].in != 0 && rld[k].reg_rtx != 0
6031 && rld[k].when_needed == rld[j].when_needed
6032 && rtx_equal_p (rld[k].reg_rtx, rld[j].reg_rtx)
6033 && ! rtx_equal_p (rld[k].in, rld[j].in))
6040 /* These arrays are filled by emit_reload_insns and its subroutines. */
6041 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6042 static rtx other_input_address_reload_insns = 0;
6043 static rtx other_input_reload_insns = 0;
6044 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6045 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6046 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6047 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6048 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6049 static rtx operand_reload_insns = 0;
6050 static rtx other_operand_reload_insns = 0;
6051 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6053 /* Values to be put in spill_reg_store are put here first. */
6054 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6055 static HARD_REG_SET reg_reloaded_died;
6057 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6058 has the number J. OLD contains the value to be used as input. */
6061 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6064 rtx insn = chain->insn;
6065 rtx reloadreg = rl->reg_rtx;
6066 rtx oldequiv_reg = 0;
6069 enum machine_mode mode;
6072 /* Determine the mode to reload in.
6073 This is very tricky because we have three to choose from.
6074 There is the mode the insn operand wants (rl->inmode).
6075 There is the mode of the reload register RELOADREG.
6076 There is the intrinsic mode of the operand, which we could find
6077 by stripping some SUBREGs.
6078 It turns out that RELOADREG's mode is irrelevant:
6079 we can change that arbitrarily.
6081 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6082 then the reload reg may not support QImode moves, so use SImode.
6083 If foo is in memory due to spilling a pseudo reg, this is safe,
6084 because the QImode value is in the least significant part of a
6085 slot big enough for a SImode. If foo is some other sort of
6086 memory reference, then it is impossible to reload this case,
6087 so previous passes had better make sure this never happens.
6089 Then consider a one-word union which has SImode and one of its
6090 members is a float, being fetched as (SUBREG:SF union:SI).
6091 We must fetch that as SFmode because we could be loading into
6092 a float-only register. In this case OLD's mode is correct.
6094 Consider an immediate integer: it has VOIDmode. Here we need
6095 to get a mode from something else.
6097 In some cases, there is a fourth mode, the operand's
6098 containing mode. If the insn specifies a containing mode for
6099 this operand, it overrides all others.
6101 I am not sure whether the algorithm here is always right,
6102 but it does the right things in those cases. */
6104 mode = GET_MODE (old);
6105 if (mode == VOIDmode)
6108 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6109 /* If we need a secondary register for this operation, see if
6110 the value is already in a register in that class. Don't
6111 do this if the secondary register will be used as a scratch
6114 if (rl->secondary_in_reload >= 0
6115 && rl->secondary_in_icode == CODE_FOR_nothing
6118 = find_equiv_reg (old, insn,
6119 rld[rl->secondary_in_reload].class,
6123 /* If reloading from memory, see if there is a register
6124 that already holds the same value. If so, reload from there.
6125 We can pass 0 as the reload_reg_p argument because
6126 any other reload has either already been emitted,
6127 in which case find_equiv_reg will see the reload-insn,
6128 or has yet to be emitted, in which case it doesn't matter
6129 because we will use this equiv reg right away. */
6131 if (oldequiv == 0 && optimize
6132 && (GET_CODE (old) == MEM
6133 || (GET_CODE (old) == REG
6134 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6135 && reg_renumber[REGNO (old)] < 0)))
6136 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6140 unsigned int regno = true_regnum (oldequiv);
6142 /* Don't use OLDEQUIV if any other reload changes it at an
6143 earlier stage of this insn or at this stage. */
6144 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6145 rl->in, const0_rtx, j, 0))
6148 /* If it is no cheaper to copy from OLDEQUIV into the
6149 reload register than it would be to move from memory,
6150 don't use it. Likewise, if we need a secondary register
6154 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6155 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6157 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6158 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6159 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6163 #ifdef SECONDARY_MEMORY_NEEDED
6164 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6172 /* delete_output_reload is only invoked properly if old contains
6173 the original pseudo register. Since this is replaced with a
6174 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6175 find the pseudo in RELOAD_IN_REG. */
6177 && reload_override_in[j]
6178 && GET_CODE (rl->in_reg) == REG)
6185 else if (GET_CODE (oldequiv) == REG)
6186 oldequiv_reg = oldequiv;
6187 else if (GET_CODE (oldequiv) == SUBREG)
6188 oldequiv_reg = SUBREG_REG (oldequiv);
6190 /* If we are reloading from a register that was recently stored in
6191 with an output-reload, see if we can prove there was
6192 actually no need to store the old value in it. */
6194 if (optimize && GET_CODE (oldequiv) == REG
6195 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6196 && spill_reg_store[REGNO (oldequiv)]
6197 && GET_CODE (old) == REG
6198 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6199 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6201 delete_output_reload (insn, j, REGNO (oldequiv));
6203 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6204 then load RELOADREG from OLDEQUIV. Note that we cannot use
6205 gen_lowpart_common since it can do the wrong thing when
6206 RELOADREG has a multi-word mode. Note that RELOADREG
6207 must always be a REG here. */
6209 if (GET_MODE (reloadreg) != mode)
6210 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6211 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6212 oldequiv = SUBREG_REG (oldequiv);
6213 if (GET_MODE (oldequiv) != VOIDmode
6214 && mode != GET_MODE (oldequiv))
6215 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6217 /* Switch to the right place to emit the reload insns. */
6218 switch (rl->when_needed)
6221 where = &other_input_reload_insns;
6223 case RELOAD_FOR_INPUT:
6224 where = &input_reload_insns[rl->opnum];
6226 case RELOAD_FOR_INPUT_ADDRESS:
6227 where = &input_address_reload_insns[rl->opnum];
6229 case RELOAD_FOR_INPADDR_ADDRESS:
6230 where = &inpaddr_address_reload_insns[rl->opnum];
6232 case RELOAD_FOR_OUTPUT_ADDRESS:
6233 where = &output_address_reload_insns[rl->opnum];
6235 case RELOAD_FOR_OUTADDR_ADDRESS:
6236 where = &outaddr_address_reload_insns[rl->opnum];
6238 case RELOAD_FOR_OPERAND_ADDRESS:
6239 where = &operand_reload_insns;
6241 case RELOAD_FOR_OPADDR_ADDR:
6242 where = &other_operand_reload_insns;
6244 case RELOAD_FOR_OTHER_ADDRESS:
6245 where = &other_input_address_reload_insns;
6251 push_to_sequence (*where);
6253 /* Auto-increment addresses must be reloaded in a special way. */
6254 if (rl->out && ! rl->out_reg)
6256 /* We are not going to bother supporting the case where a
6257 incremented register can't be copied directly from
6258 OLDEQUIV since this seems highly unlikely. */
6259 if (rl->secondary_in_reload >= 0)
6262 if (reload_inherited[j])
6263 oldequiv = reloadreg;
6265 old = XEXP (rl->in_reg, 0);
6267 if (optimize && GET_CODE (oldequiv) == REG
6268 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6269 && spill_reg_store[REGNO (oldequiv)]
6270 && GET_CODE (old) == REG
6271 && (dead_or_set_p (insn,
6272 spill_reg_stored_to[REGNO (oldequiv)])
6273 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6275 delete_output_reload (insn, j, REGNO (oldequiv));
6277 /* Prevent normal processing of this reload. */
6279 /* Output a special code sequence for this case. */
6280 new_spill_reg_store[REGNO (reloadreg)]
6281 = inc_for_reload (reloadreg, oldequiv, rl->out,
6285 /* If we are reloading a pseudo-register that was set by the previous
6286 insn, see if we can get rid of that pseudo-register entirely
6287 by redirecting the previous insn into our reload register. */
6289 else if (optimize && GET_CODE (old) == REG
6290 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6291 && dead_or_set_p (insn, old)
6292 /* This is unsafe if some other reload
6293 uses the same reg first. */
6294 && ! conflicts_with_override (reloadreg)
6295 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6296 rl->when_needed, old, rl->out, j, 0))
6298 rtx temp = PREV_INSN (insn);
6299 while (temp && GET_CODE (temp) == NOTE)
6300 temp = PREV_INSN (temp);
6302 && GET_CODE (temp) == INSN
6303 && GET_CODE (PATTERN (temp)) == SET
6304 && SET_DEST (PATTERN (temp)) == old
6305 /* Make sure we can access insn_operand_constraint. */
6306 && asm_noperands (PATTERN (temp)) < 0
6307 /* This is unsafe if operand occurs more than once in current
6308 insn. Perhaps some occurrences aren't reloaded. */
6309 && count_occurrences (PATTERN (insn), old, 0) == 1)
6311 rtx old = SET_DEST (PATTERN (temp));
6312 /* Store into the reload register instead of the pseudo. */
6313 SET_DEST (PATTERN (temp)) = reloadreg;
6315 /* Verify that resulting insn is valid. */
6316 extract_insn (temp);
6317 if (constrain_operands (1))
6319 /* If the previous insn is an output reload, the source is
6320 a reload register, and its spill_reg_store entry will
6321 contain the previous destination. This is now
6323 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6324 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6326 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6327 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6330 /* If these are the only uses of the pseudo reg,
6331 pretend for GDB it lives in the reload reg we used. */
6332 if (REG_N_DEATHS (REGNO (old)) == 1
6333 && REG_N_SETS (REGNO (old)) == 1)
6335 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6336 alter_reg (REGNO (old), -1);
6342 SET_DEST (PATTERN (temp)) = old;
6347 /* We can't do that, so output an insn to load RELOADREG. */
6349 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6350 /* If we have a secondary reload, pick up the secondary register
6351 and icode, if any. If OLDEQUIV and OLD are different or
6352 if this is an in-out reload, recompute whether or not we
6353 still need a secondary register and what the icode should
6354 be. If we still need a secondary register and the class or
6355 icode is different, go back to reloading from OLD if using
6356 OLDEQUIV means that we got the wrong type of register. We
6357 cannot have different class or icode due to an in-out reload
6358 because we don't make such reloads when both the input and
6359 output need secondary reload registers. */
6361 if (! special && rl->secondary_in_reload >= 0)
6363 rtx second_reload_reg = 0;
6364 int secondary_reload = rl->secondary_in_reload;
6365 rtx real_oldequiv = oldequiv;
6368 enum insn_code icode;
6370 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6371 and similarly for OLD.
6372 See comments in get_secondary_reload in reload.c. */
6373 /* If it is a pseudo that cannot be replaced with its
6374 equivalent MEM, we must fall back to reload_in, which
6375 will have all the necessary substitutions registered.
6376 Likewise for a pseudo that can't be replaced with its
6377 equivalent constant.
6379 Take extra care for subregs of such pseudos. Note that
6380 we cannot use reg_equiv_mem in this case because it is
6381 not in the right mode. */
6384 if (GET_CODE (tmp) == SUBREG)
6385 tmp = SUBREG_REG (tmp);
6386 if (GET_CODE (tmp) == REG
6387 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6388 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6389 || reg_equiv_constant[REGNO (tmp)] != 0))
6391 if (! reg_equiv_mem[REGNO (tmp)]
6392 || num_not_at_initial_offset
6393 || GET_CODE (oldequiv) == SUBREG)
6394 real_oldequiv = rl->in;
6396 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6400 if (GET_CODE (tmp) == SUBREG)
6401 tmp = SUBREG_REG (tmp);
6402 if (GET_CODE (tmp) == REG
6403 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6404 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6405 || reg_equiv_constant[REGNO (tmp)] != 0))
6407 if (! reg_equiv_mem[REGNO (tmp)]
6408 || num_not_at_initial_offset
6409 || GET_CODE (old) == SUBREG)
6412 real_old = reg_equiv_mem[REGNO (tmp)];
6415 second_reload_reg = rld[secondary_reload].reg_rtx;
6416 icode = rl->secondary_in_icode;
6418 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6419 || (rl->in != 0 && rl->out != 0))
6421 enum reg_class new_class
6422 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6423 mode, real_oldequiv);
6425 if (new_class == NO_REGS)
6426 second_reload_reg = 0;
6429 enum insn_code new_icode;
6430 enum machine_mode new_mode;
6432 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6433 REGNO (second_reload_reg)))
6434 oldequiv = old, real_oldequiv = real_old;
6437 new_icode = reload_in_optab[(int) mode];
6438 if (new_icode != CODE_FOR_nothing
6439 && ((insn_data[(int) new_icode].operand[0].predicate
6440 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6442 || (insn_data[(int) new_icode].operand[1].predicate
6443 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6444 (real_oldequiv, mode)))))
6445 new_icode = CODE_FOR_nothing;
6447 if (new_icode == CODE_FOR_nothing)
6450 new_mode = insn_data[(int) new_icode].operand[2].mode;
6452 if (GET_MODE (second_reload_reg) != new_mode)
6454 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6456 oldequiv = old, real_oldequiv = real_old;
6459 = reload_adjust_reg_for_mode (second_reload_reg,
6466 /* If we still need a secondary reload register, check
6467 to see if it is being used as a scratch or intermediate
6468 register and generate code appropriately. If we need
6469 a scratch register, use REAL_OLDEQUIV since the form of
6470 the insn may depend on the actual address if it is
6473 if (second_reload_reg)
6475 if (icode != CODE_FOR_nothing)
6477 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6478 second_reload_reg));
6483 /* See if we need a scratch register to load the
6484 intermediate register (a tertiary reload). */
6485 enum insn_code tertiary_icode
6486 = rld[secondary_reload].secondary_in_icode;
6488 if (tertiary_icode != CODE_FOR_nothing)
6490 rtx third_reload_reg
6491 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6493 emit_insn ((GEN_FCN (tertiary_icode)
6494 (second_reload_reg, real_oldequiv,
6495 third_reload_reg)));
6498 gen_reload (second_reload_reg, real_oldequiv,
6502 oldequiv = second_reload_reg;
6508 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6510 rtx real_oldequiv = oldequiv;
6512 if ((GET_CODE (oldequiv) == REG
6513 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6514 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6515 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6516 || (GET_CODE (oldequiv) == SUBREG
6517 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6518 && (REGNO (SUBREG_REG (oldequiv))
6519 >= FIRST_PSEUDO_REGISTER)
6520 && ((reg_equiv_memory_loc
6521 [REGNO (SUBREG_REG (oldequiv))] != 0)
6522 || (reg_equiv_constant
6523 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6524 || (CONSTANT_P (oldequiv)
6525 && (PREFERRED_RELOAD_CLASS (oldequiv,
6526 REGNO_REG_CLASS (REGNO (reloadreg)))
6528 real_oldequiv = rl->in;
6529 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6533 if (flag_non_call_exceptions)
6534 copy_eh_notes (insn, get_insns ());
6536 /* End this sequence. */
6537 *where = get_insns ();
6540 /* Update reload_override_in so that delete_address_reloads_1
6541 can see the actual register usage. */
6543 reload_override_in[j] = oldequiv;
6546 /* Generate insns to for the output reload RL, which is for the insn described
6547 by CHAIN and has the number J. */
6549 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6552 rtx reloadreg = rl->reg_rtx;
6553 rtx insn = chain->insn;
6556 enum machine_mode mode = GET_MODE (old);
6559 if (rl->when_needed == RELOAD_OTHER)
6562 push_to_sequence (output_reload_insns[rl->opnum]);
6564 /* Determine the mode to reload in.
6565 See comments above (for input reloading). */
6567 if (mode == VOIDmode)
6569 /* VOIDmode should never happen for an output. */
6570 if (asm_noperands (PATTERN (insn)) < 0)
6571 /* It's the compiler's fault. */
6572 fatal_insn ("VOIDmode on an output", insn);
6573 error_for_asm (insn, "output operand is constant in `asm'");
6574 /* Prevent crash--use something we know is valid. */
6576 old = gen_rtx_REG (mode, REGNO (reloadreg));
6579 if (GET_MODE (reloadreg) != mode)
6580 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6582 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6584 /* If we need two reload regs, set RELOADREG to the intermediate
6585 one, since it will be stored into OLD. We might need a secondary
6586 register only for an input reload, so check again here. */
6588 if (rl->secondary_out_reload >= 0)
6592 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6593 && reg_equiv_mem[REGNO (old)] != 0)
6594 real_old = reg_equiv_mem[REGNO (old)];
6596 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6600 rtx second_reloadreg = reloadreg;
6601 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6603 /* See if RELOADREG is to be used as a scratch register
6604 or as an intermediate register. */
6605 if (rl->secondary_out_icode != CODE_FOR_nothing)
6607 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6608 (real_old, second_reloadreg, reloadreg)));
6613 /* See if we need both a scratch and intermediate reload
6616 int secondary_reload = rl->secondary_out_reload;
6617 enum insn_code tertiary_icode
6618 = rld[secondary_reload].secondary_out_icode;
6620 if (GET_MODE (reloadreg) != mode)
6621 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6623 if (tertiary_icode != CODE_FOR_nothing)
6626 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6629 /* Copy primary reload reg to secondary reload reg.
6630 (Note that these have been swapped above, then
6631 secondary reload reg to OLD using our insn.) */
6633 /* If REAL_OLD is a paradoxical SUBREG, remove it
6634 and try to put the opposite SUBREG on
6636 if (GET_CODE (real_old) == SUBREG
6637 && (GET_MODE_SIZE (GET_MODE (real_old))
6638 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6639 && 0 != (tem = gen_lowpart_common
6640 (GET_MODE (SUBREG_REG (real_old)),
6642 real_old = SUBREG_REG (real_old), reloadreg = tem;
6644 gen_reload (reloadreg, second_reloadreg,
6645 rl->opnum, rl->when_needed);
6646 emit_insn ((GEN_FCN (tertiary_icode)
6647 (real_old, reloadreg, third_reloadreg)));
6652 /* Copy between the reload regs here and then to
6655 gen_reload (reloadreg, second_reloadreg,
6656 rl->opnum, rl->when_needed);
6662 /* Output the last reload insn. */
6667 /* Don't output the last reload if OLD is not the dest of
6668 INSN and is in the src and is clobbered by INSN. */
6669 if (! flag_expensive_optimizations
6670 || GET_CODE (old) != REG
6671 || !(set = single_set (insn))
6672 || rtx_equal_p (old, SET_DEST (set))
6673 || !reg_mentioned_p (old, SET_SRC (set))
6674 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6675 gen_reload (old, reloadreg, rl->opnum,
6679 /* Look at all insns we emitted, just to be safe. */
6680 for (p = get_insns (); p; p = NEXT_INSN (p))
6683 rtx pat = PATTERN (p);
6685 /* If this output reload doesn't come from a spill reg,
6686 clear any memory of reloaded copies of the pseudo reg.
6687 If this output reload comes from a spill reg,
6688 reg_has_output_reload will make this do nothing. */
6689 note_stores (pat, forget_old_reloads_1, NULL);
6691 if (reg_mentioned_p (rl->reg_rtx, pat))
6693 rtx set = single_set (insn);
6694 if (reload_spill_index[j] < 0
6696 && SET_SRC (set) == rl->reg_rtx)
6698 int src = REGNO (SET_SRC (set));
6700 reload_spill_index[j] = src;
6701 SET_HARD_REG_BIT (reg_is_output_reload, src);
6702 if (find_regno_note (insn, REG_DEAD, src))
6703 SET_HARD_REG_BIT (reg_reloaded_died, src);
6705 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6707 int s = rl->secondary_out_reload;
6708 set = single_set (p);
6709 /* If this reload copies only to the secondary reload
6710 register, the secondary reload does the actual
6712 if (s >= 0 && set == NULL_RTX)
6713 /* We can't tell what function the secondary reload
6714 has and where the actual store to the pseudo is
6715 made; leave new_spill_reg_store alone. */
6718 && SET_SRC (set) == rl->reg_rtx
6719 && SET_DEST (set) == rld[s].reg_rtx)
6721 /* Usually the next instruction will be the
6722 secondary reload insn; if we can confirm
6723 that it is, setting new_spill_reg_store to
6724 that insn will allow an extra optimization. */
6725 rtx s_reg = rld[s].reg_rtx;
6726 rtx next = NEXT_INSN (p);
6727 rld[s].out = rl->out;
6728 rld[s].out_reg = rl->out_reg;
6729 set = single_set (next);
6730 if (set && SET_SRC (set) == s_reg
6731 && ! new_spill_reg_store[REGNO (s_reg)])
6733 SET_HARD_REG_BIT (reg_is_output_reload,
6735 new_spill_reg_store[REGNO (s_reg)] = next;
6739 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6744 if (rl->when_needed == RELOAD_OTHER)
6746 emit_insn (other_output_reload_insns[rl->opnum]);
6747 other_output_reload_insns[rl->opnum] = get_insns ();
6750 output_reload_insns[rl->opnum] = get_insns ();
6752 if (flag_non_call_exceptions)
6753 copy_eh_notes (insn, get_insns ());
6758 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6759 and has the number J. */
6761 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
6763 rtx insn = chain->insn;
6764 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6765 ? rl->in_reg : rl->in);
6768 /* AUTO_INC reloads need to be handled even if inherited. We got an
6769 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6770 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6771 && ! rtx_equal_p (rl->reg_rtx, old)
6772 && rl->reg_rtx != 0)
6773 emit_input_reload_insns (chain, rld + j, old, j);
6775 /* When inheriting a wider reload, we have a MEM in rl->in,
6776 e.g. inheriting a SImode output reload for
6777 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6778 if (optimize && reload_inherited[j] && rl->in
6779 && GET_CODE (rl->in) == MEM
6780 && GET_CODE (rl->in_reg) == MEM
6781 && reload_spill_index[j] >= 0
6782 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6783 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6785 /* If we are reloading a register that was recently stored in with an
6786 output-reload, see if we can prove there was
6787 actually no need to store the old value in it. */
6790 && (reload_inherited[j] || reload_override_in[j])
6792 && GET_CODE (rl->reg_rtx) == REG
6793 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6795 /* There doesn't seem to be any reason to restrict this to pseudos
6796 and doing so loses in the case where we are copying from a
6797 register of the wrong class. */
6798 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6799 >= FIRST_PSEUDO_REGISTER)
6801 /* The insn might have already some references to stackslots
6802 replaced by MEMs, while reload_out_reg still names the
6804 && (dead_or_set_p (insn,
6805 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6806 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6808 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6811 /* Do output reloading for reload RL, which is for the insn described by
6812 CHAIN and has the number J.
6813 ??? At some point we need to support handling output reloads of
6814 JUMP_INSNs or insns that set cc0. */
6816 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
6819 rtx insn = chain->insn;
6820 /* If this is an output reload that stores something that is
6821 not loaded in this same reload, see if we can eliminate a previous
6823 rtx pseudo = rl->out_reg;
6827 && GET_CODE (pseudo) == REG
6828 && ! rtx_equal_p (rl->in_reg, pseudo)
6829 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6830 && reg_last_reload_reg[REGNO (pseudo)])
6832 int pseudo_no = REGNO (pseudo);
6833 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6835 /* We don't need to test full validity of last_regno for
6836 inherit here; we only want to know if the store actually
6837 matches the pseudo. */
6838 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6839 && reg_reloaded_contents[last_regno] == pseudo_no
6840 && spill_reg_store[last_regno]
6841 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6842 delete_output_reload (insn, j, last_regno);
6847 || rl->reg_rtx == old
6848 || rl->reg_rtx == 0)
6851 /* An output operand that dies right away does need a reload,
6852 but need not be copied from it. Show the new location in the
6854 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6855 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6857 XEXP (note, 0) = rl->reg_rtx;
6860 /* Likewise for a SUBREG of an operand that dies. */
6861 else if (GET_CODE (old) == SUBREG
6862 && GET_CODE (SUBREG_REG (old)) == REG
6863 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6866 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6870 else if (GET_CODE (old) == SCRATCH)
6871 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6872 but we don't want to make an output reload. */
6875 /* If is a JUMP_INSN, we can't support output reloads yet. */
6876 if (GET_CODE (insn) == JUMP_INSN)
6879 emit_output_reload_insns (chain, rld + j, j);
6882 /* Output insns to reload values in and out of the chosen reload regs. */
6885 emit_reload_insns (struct insn_chain *chain)
6887 rtx insn = chain->insn;
6891 CLEAR_HARD_REG_SET (reg_reloaded_died);
6893 for (j = 0; j < reload_n_operands; j++)
6894 input_reload_insns[j] = input_address_reload_insns[j]
6895 = inpaddr_address_reload_insns[j]
6896 = output_reload_insns[j] = output_address_reload_insns[j]
6897 = outaddr_address_reload_insns[j]
6898 = other_output_reload_insns[j] = 0;
6899 other_input_address_reload_insns = 0;
6900 other_input_reload_insns = 0;
6901 operand_reload_insns = 0;
6902 other_operand_reload_insns = 0;
6904 /* Dump reloads into the dump file. */
6907 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6908 debug_reload_to_stream (rtl_dump_file);
6911 /* Now output the instructions to copy the data into and out of the
6912 reload registers. Do these in the order that the reloads were reported,
6913 since reloads of base and index registers precede reloads of operands
6914 and the operands may need the base and index registers reloaded. */
6916 for (j = 0; j < n_reloads; j++)
6919 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6920 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6922 do_input_reload (chain, rld + j, j);
6923 do_output_reload (chain, rld + j, j);
6926 /* Now write all the insns we made for reloads in the order expected by
6927 the allocation functions. Prior to the insn being reloaded, we write
6928 the following reloads:
6930 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6932 RELOAD_OTHER reloads.
6934 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6935 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6936 RELOAD_FOR_INPUT reload for the operand.
6938 RELOAD_FOR_OPADDR_ADDRS reloads.
6940 RELOAD_FOR_OPERAND_ADDRESS reloads.
6942 After the insn being reloaded, we write the following:
6944 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6945 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6946 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6947 reloads for the operand. The RELOAD_OTHER output reloads are
6948 output in descending order by reload number. */
6950 emit_insn_before (other_input_address_reload_insns, insn);
6951 emit_insn_before (other_input_reload_insns, insn);
6953 for (j = 0; j < reload_n_operands; j++)
6955 emit_insn_before (inpaddr_address_reload_insns[j], insn);
6956 emit_insn_before (input_address_reload_insns[j], insn);
6957 emit_insn_before (input_reload_insns[j], insn);
6960 emit_insn_before (other_operand_reload_insns, insn);
6961 emit_insn_before (operand_reload_insns, insn);
6963 for (j = 0; j < reload_n_operands; j++)
6965 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
6966 x = emit_insn_after (output_address_reload_insns[j], x);
6967 x = emit_insn_after (output_reload_insns[j], x);
6968 emit_insn_after (other_output_reload_insns[j], x);
6971 /* For all the spill regs newly reloaded in this instruction,
6972 record what they were reloaded from, so subsequent instructions
6973 can inherit the reloads.
6975 Update spill_reg_store for the reloads of this insn.
6976 Copy the elements that were updated in the loop above. */
6978 for (j = 0; j < n_reloads; j++)
6980 int r = reload_order[j];
6981 int i = reload_spill_index[r];
6983 /* If this is a non-inherited input reload from a pseudo, we must
6984 clear any memory of a previous store to the same pseudo. Only do
6985 something if there will not be an output reload for the pseudo
6987 if (rld[r].in_reg != 0
6988 && ! (reload_inherited[r] || reload_override_in[r]))
6990 rtx reg = rld[r].in_reg;
6992 if (GET_CODE (reg) == SUBREG)
6993 reg = SUBREG_REG (reg);
6995 if (GET_CODE (reg) == REG
6996 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
6997 && ! reg_has_output_reload[REGNO (reg)])
6999 int nregno = REGNO (reg);
7001 if (reg_last_reload_reg[nregno])
7003 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7005 if (reg_reloaded_contents[last_regno] == nregno)
7006 spill_reg_store[last_regno] = 0;
7011 /* I is nonneg if this reload used a register.
7012 If rld[r].reg_rtx is 0, this is an optional reload
7013 that we opted to ignore. */
7015 if (i >= 0 && rld[r].reg_rtx != 0)
7017 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7019 int part_reaches_end = 0;
7020 int all_reaches_end = 1;
7022 /* For a multi register reload, we need to check if all or part
7023 of the value lives to the end. */
7024 for (k = 0; k < nr; k++)
7026 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7027 rld[r].when_needed))
7028 part_reaches_end = 1;
7030 all_reaches_end = 0;
7033 /* Ignore reloads that don't reach the end of the insn in
7035 if (all_reaches_end)
7037 /* First, clear out memory of what used to be in this spill reg.
7038 If consecutive registers are used, clear them all. */
7040 for (k = 0; k < nr; k++)
7041 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7043 /* Maybe the spill reg contains a copy of reload_out. */
7045 && (GET_CODE (rld[r].out) == REG
7049 || GET_CODE (rld[r].out_reg) == REG))
7051 rtx out = (GET_CODE (rld[r].out) == REG
7055 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7056 int nregno = REGNO (out);
7057 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7058 : HARD_REGNO_NREGS (nregno,
7059 GET_MODE (rld[r].reg_rtx)));
7061 spill_reg_store[i] = new_spill_reg_store[i];
7062 spill_reg_stored_to[i] = out;
7063 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7065 /* If NREGNO is a hard register, it may occupy more than
7066 one register. If it does, say what is in the
7067 rest of the registers assuming that both registers
7068 agree on how many words the object takes. If not,
7069 invalidate the subsequent registers. */
7071 if (nregno < FIRST_PSEUDO_REGISTER)
7072 for (k = 1; k < nnr; k++)
7073 reg_last_reload_reg[nregno + k]
7075 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7078 /* Now do the inverse operation. */
7079 for (k = 0; k < nr; k++)
7081 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7082 reg_reloaded_contents[i + k]
7083 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7086 reg_reloaded_insn[i + k] = insn;
7087 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7091 /* Maybe the spill reg contains a copy of reload_in. Only do
7092 something if there will not be an output reload for
7093 the register being reloaded. */
7094 else if (rld[r].out_reg == 0
7096 && ((GET_CODE (rld[r].in) == REG
7097 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7098 && ! reg_has_output_reload[REGNO (rld[r].in)])
7099 || (GET_CODE (rld[r].in_reg) == REG
7100 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7101 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7106 if (GET_CODE (rld[r].in) == REG
7107 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7108 nregno = REGNO (rld[r].in);
7109 else if (GET_CODE (rld[r].in_reg) == REG)
7110 nregno = REGNO (rld[r].in_reg);
7112 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7114 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7115 : HARD_REGNO_NREGS (nregno,
7116 GET_MODE (rld[r].reg_rtx)));
7118 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7120 if (nregno < FIRST_PSEUDO_REGISTER)
7121 for (k = 1; k < nnr; k++)
7122 reg_last_reload_reg[nregno + k]
7124 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7127 /* Unless we inherited this reload, show we haven't
7128 recently done a store.
7129 Previous stores of inherited auto_inc expressions
7130 also have to be discarded. */
7131 if (! reload_inherited[r]
7132 || (rld[r].out && ! rld[r].out_reg))
7133 spill_reg_store[i] = 0;
7135 for (k = 0; k < nr; k++)
7137 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7138 reg_reloaded_contents[i + k]
7139 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7142 reg_reloaded_insn[i + k] = insn;
7143 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7148 /* However, if part of the reload reaches the end, then we must
7149 invalidate the old info for the part that survives to the end. */
7150 else if (part_reaches_end)
7152 for (k = 0; k < nr; k++)
7153 if (reload_reg_reaches_end_p (i + k,
7155 rld[r].when_needed))
7156 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7160 /* The following if-statement was #if 0'd in 1.34 (or before...).
7161 It's reenabled in 1.35 because supposedly nothing else
7162 deals with this problem. */
7164 /* If a register gets output-reloaded from a non-spill register,
7165 that invalidates any previous reloaded copy of it.
7166 But forget_old_reloads_1 won't get to see it, because
7167 it thinks only about the original insn. So invalidate it here. */
7168 if (i < 0 && rld[r].out != 0
7169 && (GET_CODE (rld[r].out) == REG
7170 || (GET_CODE (rld[r].out) == MEM
7171 && GET_CODE (rld[r].out_reg) == REG)))
7173 rtx out = (GET_CODE (rld[r].out) == REG
7174 ? rld[r].out : rld[r].out_reg);
7175 int nregno = REGNO (out);
7176 if (nregno >= FIRST_PSEUDO_REGISTER)
7178 rtx src_reg, store_insn = NULL_RTX;
7180 reg_last_reload_reg[nregno] = 0;
7182 /* If we can find a hard register that is stored, record
7183 the storing insn so that we may delete this insn with
7184 delete_output_reload. */
7185 src_reg = rld[r].reg_rtx;
7187 /* If this is an optional reload, try to find the source reg
7188 from an input reload. */
7191 rtx set = single_set (insn);
7192 if (set && SET_DEST (set) == rld[r].out)
7196 src_reg = SET_SRC (set);
7198 for (k = 0; k < n_reloads; k++)
7200 if (rld[k].in == src_reg)
7202 src_reg = rld[k].reg_rtx;
7209 store_insn = new_spill_reg_store[REGNO (src_reg)];
7210 if (src_reg && GET_CODE (src_reg) == REG
7211 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7213 int src_regno = REGNO (src_reg);
7214 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7215 /* The place where to find a death note varies with
7216 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7217 necessarily checked exactly in the code that moves
7218 notes, so just check both locations. */
7219 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7220 if (! note && store_insn)
7221 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7224 spill_reg_store[src_regno + nr] = store_insn;
7225 spill_reg_stored_to[src_regno + nr] = out;
7226 reg_reloaded_contents[src_regno + nr] = nregno;
7227 reg_reloaded_insn[src_regno + nr] = store_insn;
7228 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7229 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7230 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7232 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7234 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7236 reg_last_reload_reg[nregno] = src_reg;
7241 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7243 while (num_regs-- > 0)
7244 reg_last_reload_reg[nregno + num_regs] = 0;
7248 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7251 /* Emit code to perform a reload from IN (which may be a reload register) to
7252 OUT (which may also be a reload register). IN or OUT is from operand
7253 OPNUM with reload type TYPE.
7255 Returns first insn emitted. */
7258 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7260 rtx last = get_last_insn ();
7263 /* If IN is a paradoxical SUBREG, remove it and try to put the
7264 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7265 if (GET_CODE (in) == SUBREG
7266 && (GET_MODE_SIZE (GET_MODE (in))
7267 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7268 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7269 in = SUBREG_REG (in), out = tem;
7270 else if (GET_CODE (out) == SUBREG
7271 && (GET_MODE_SIZE (GET_MODE (out))
7272 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7273 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7274 out = SUBREG_REG (out), in = tem;
7276 /* How to do this reload can get quite tricky. Normally, we are being
7277 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7278 register that didn't get a hard register. In that case we can just
7279 call emit_move_insn.
7281 We can also be asked to reload a PLUS that adds a register or a MEM to
7282 another register, constant or MEM. This can occur during frame pointer
7283 elimination and while reloading addresses. This case is handled by
7284 trying to emit a single insn to perform the add. If it is not valid,
7285 we use a two insn sequence.
7287 Finally, we could be called to handle an 'o' constraint by putting
7288 an address into a register. In that case, we first try to do this
7289 with a named pattern of "reload_load_address". If no such pattern
7290 exists, we just emit a SET insn and hope for the best (it will normally
7291 be valid on machines that use 'o').
7293 This entire process is made complex because reload will never
7294 process the insns we generate here and so we must ensure that
7295 they will fit their constraints and also by the fact that parts of
7296 IN might be being reloaded separately and replaced with spill registers.
7297 Because of this, we are, in some sense, just guessing the right approach
7298 here. The one listed above seems to work.
7300 ??? At some point, this whole thing needs to be rethought. */
7302 if (GET_CODE (in) == PLUS
7303 && (GET_CODE (XEXP (in, 0)) == REG
7304 || GET_CODE (XEXP (in, 0)) == SUBREG
7305 || GET_CODE (XEXP (in, 0)) == MEM)
7306 && (GET_CODE (XEXP (in, 1)) == REG
7307 || GET_CODE (XEXP (in, 1)) == SUBREG
7308 || CONSTANT_P (XEXP (in, 1))
7309 || GET_CODE (XEXP (in, 1)) == MEM))
7311 /* We need to compute the sum of a register or a MEM and another
7312 register, constant, or MEM, and put it into the reload
7313 register. The best possible way of doing this is if the machine
7314 has a three-operand ADD insn that accepts the required operands.
7316 The simplest approach is to try to generate such an insn and see if it
7317 is recognized and matches its constraints. If so, it can be used.
7319 It might be better not to actually emit the insn unless it is valid,
7320 but we need to pass the insn as an operand to `recog' and
7321 `extract_insn' and it is simpler to emit and then delete the insn if
7322 not valid than to dummy things up. */
7324 rtx op0, op1, tem, insn;
7327 op0 = find_replacement (&XEXP (in, 0));
7328 op1 = find_replacement (&XEXP (in, 1));
7330 /* Since constraint checking is strict, commutativity won't be
7331 checked, so we need to do that here to avoid spurious failure
7332 if the add instruction is two-address and the second operand
7333 of the add is the same as the reload reg, which is frequently
7334 the case. If the insn would be A = B + A, rearrange it so
7335 it will be A = A + B as constrain_operands expects. */
7337 if (GET_CODE (XEXP (in, 1)) == REG
7338 && REGNO (out) == REGNO (XEXP (in, 1)))
7339 tem = op0, op0 = op1, op1 = tem;
7341 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7342 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7344 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7345 code = recog_memoized (insn);
7349 extract_insn (insn);
7350 /* We want constrain operands to treat this insn strictly in
7351 its validity determination, i.e., the way it would after reload
7353 if (constrain_operands (1))
7357 delete_insns_since (last);
7359 /* If that failed, we must use a conservative two-insn sequence.
7361 Use a move to copy one operand into the reload register. Prefer
7362 to reload a constant, MEM or pseudo since the move patterns can
7363 handle an arbitrary operand. If OP1 is not a constant, MEM or
7364 pseudo and OP1 is not a valid operand for an add instruction, then
7367 After reloading one of the operands into the reload register, add
7368 the reload register to the output register.
7370 If there is another way to do this for a specific machine, a
7371 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7374 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7376 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7377 || (GET_CODE (op1) == REG
7378 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7379 || (code != CODE_FOR_nothing
7380 && ! ((*insn_data[code].operand[2].predicate)
7381 (op1, insn_data[code].operand[2].mode))))
7382 tem = op0, op0 = op1, op1 = tem;
7384 gen_reload (out, op0, opnum, type);
7386 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7387 This fixes a problem on the 32K where the stack pointer cannot
7388 be used as an operand of an add insn. */
7390 if (rtx_equal_p (op0, op1))
7393 insn = emit_insn (gen_add2_insn (out, op1));
7395 /* If that failed, copy the address register to the reload register.
7396 Then add the constant to the reload register. */
7398 code = recog_memoized (insn);
7402 extract_insn (insn);
7403 /* We want constrain operands to treat this insn strictly in
7404 its validity determination, i.e., the way it would after reload
7406 if (constrain_operands (1))
7408 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7410 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7415 delete_insns_since (last);
7417 gen_reload (out, op1, opnum, type);
7418 insn = emit_insn (gen_add2_insn (out, op0));
7419 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7422 #ifdef SECONDARY_MEMORY_NEEDED
7423 /* If we need a memory location to do the move, do it that way. */
7424 else if ((GET_CODE (in) == REG || GET_CODE (in) == SUBREG)
7425 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7426 && (GET_CODE (out) == REG || GET_CODE (out) == SUBREG)
7427 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7428 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7429 REGNO_REG_CLASS (reg_or_subregno (out)),
7432 /* Get the memory to use and rewrite both registers to its mode. */
7433 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7435 if (GET_MODE (loc) != GET_MODE (out))
7436 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7438 if (GET_MODE (loc) != GET_MODE (in))
7439 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7441 gen_reload (loc, in, opnum, type);
7442 gen_reload (out, loc, opnum, type);
7446 /* If IN is a simple operand, use gen_move_insn. */
7447 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7448 emit_insn (gen_move_insn (out, in));
7450 #ifdef HAVE_reload_load_address
7451 else if (HAVE_reload_load_address)
7452 emit_insn (gen_reload_load_address (out, in));
7455 /* Otherwise, just write (set OUT IN) and hope for the best. */
7457 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7459 /* Return the first insn emitted.
7460 We can not just return get_last_insn, because there may have
7461 been multiple instructions emitted. Also note that gen_move_insn may
7462 emit more than one insn itself, so we can not assume that there is one
7463 insn emitted per emit_insn_before call. */
7465 return last ? NEXT_INSN (last) : get_insns ();
7468 /* Delete a previously made output-reload whose result we now believe
7469 is not needed. First we double-check.
7471 INSN is the insn now being processed.
7472 LAST_RELOAD_REG is the hard register number for which we want to delete
7473 the last output reload.
7474 J is the reload-number that originally used REG. The caller has made
7475 certain that reload J doesn't use REG any longer for input. */
7478 delete_output_reload (rtx insn, int j, int last_reload_reg)
7480 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7481 rtx reg = spill_reg_stored_to[last_reload_reg];
7484 int n_inherited = 0;
7488 /* It is possible that this reload has been only used to set another reload
7489 we eliminated earlier and thus deleted this instruction too. */
7490 if (INSN_DELETED_P (output_reload_insn))
7493 /* Get the raw pseudo-register referred to. */
7495 while (GET_CODE (reg) == SUBREG)
7496 reg = SUBREG_REG (reg);
7497 substed = reg_equiv_memory_loc[REGNO (reg)];
7499 /* This is unsafe if the operand occurs more often in the current
7500 insn than it is inherited. */
7501 for (k = n_reloads - 1; k >= 0; k--)
7503 rtx reg2 = rld[k].in;
7506 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7507 reg2 = rld[k].in_reg;
7509 if (rld[k].out && ! rld[k].out_reg)
7510 reg2 = XEXP (rld[k].in_reg, 0);
7512 while (GET_CODE (reg2) == SUBREG)
7513 reg2 = SUBREG_REG (reg2);
7514 if (rtx_equal_p (reg2, reg))
7516 if (reload_inherited[k] || reload_override_in[k] || k == j)
7519 reg2 = rld[k].out_reg;
7522 while (GET_CODE (reg2) == SUBREG)
7523 reg2 = XEXP (reg2, 0);
7524 if (rtx_equal_p (reg2, reg))
7531 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7533 n_occurrences += count_occurrences (PATTERN (insn),
7534 eliminate_regs (substed, 0,
7536 if (n_occurrences > n_inherited)
7539 /* If the pseudo-reg we are reloading is no longer referenced
7540 anywhere between the store into it and here,
7541 and no jumps or labels intervene, then the value can get
7542 here through the reload reg alone.
7543 Otherwise, give up--return. */
7544 for (i1 = NEXT_INSN (output_reload_insn);
7545 i1 != insn; i1 = NEXT_INSN (i1))
7547 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7549 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7550 && reg_mentioned_p (reg, PATTERN (i1)))
7552 /* If this is USE in front of INSN, we only have to check that
7553 there are no more references than accounted for by inheritance. */
7554 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7556 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7557 i1 = NEXT_INSN (i1);
7559 if (n_occurrences <= n_inherited && i1 == insn)
7565 /* We will be deleting the insn. Remove the spill reg information. */
7566 for (k = HARD_REGNO_NREGS (last_reload_reg, GET_MODE (reg)); k-- > 0; )
7568 spill_reg_store[last_reload_reg + k] = 0;
7569 spill_reg_stored_to[last_reload_reg + k] = 0;
7572 /* The caller has already checked that REG dies or is set in INSN.
7573 It has also checked that we are optimizing, and thus some
7574 inaccuracies in the debugging information are acceptable.
7575 So we could just delete output_reload_insn. But in some cases
7576 we can improve the debugging information without sacrificing
7577 optimization - maybe even improving the code: See if the pseudo
7578 reg has been completely replaced with reload regs. If so, delete
7579 the store insn and forget we had a stack slot for the pseudo. */
7580 if (rld[j].out != rld[j].in
7581 && REG_N_DEATHS (REGNO (reg)) == 1
7582 && REG_N_SETS (REGNO (reg)) == 1
7583 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7584 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7588 /* We know that it was used only between here and the beginning of
7589 the current basic block. (We also know that the last use before
7590 INSN was the output reload we are thinking of deleting, but never
7591 mind that.) Search that range; see if any ref remains. */
7592 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7594 rtx set = single_set (i2);
7596 /* Uses which just store in the pseudo don't count,
7597 since if they are the only uses, they are dead. */
7598 if (set != 0 && SET_DEST (set) == reg)
7600 if (GET_CODE (i2) == CODE_LABEL
7601 || GET_CODE (i2) == JUMP_INSN)
7603 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7604 && reg_mentioned_p (reg, PATTERN (i2)))
7606 /* Some other ref remains; just delete the output reload we
7608 delete_address_reloads (output_reload_insn, insn);
7609 delete_insn (output_reload_insn);
7614 /* Delete the now-dead stores into this pseudo. Note that this
7615 loop also takes care of deleting output_reload_insn. */
7616 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7618 rtx set = single_set (i2);
7620 if (set != 0 && SET_DEST (set) == reg)
7622 delete_address_reloads (i2, insn);
7625 if (GET_CODE (i2) == CODE_LABEL
7626 || GET_CODE (i2) == JUMP_INSN)
7630 /* For the debugging info, say the pseudo lives in this reload reg. */
7631 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7632 alter_reg (REGNO (reg), -1);
7636 delete_address_reloads (output_reload_insn, insn);
7637 delete_insn (output_reload_insn);
7641 /* We are going to delete DEAD_INSN. Recursively delete loads of
7642 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7643 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7645 delete_address_reloads (rtx dead_insn, rtx current_insn)
7647 rtx set = single_set (dead_insn);
7648 rtx set2, dst, prev, next;
7651 rtx dst = SET_DEST (set);
7652 if (GET_CODE (dst) == MEM)
7653 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7655 /* If we deleted the store from a reloaded post_{in,de}c expression,
7656 we can delete the matching adds. */
7657 prev = PREV_INSN (dead_insn);
7658 next = NEXT_INSN (dead_insn);
7659 if (! prev || ! next)
7661 set = single_set (next);
7662 set2 = single_set (prev);
7664 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7665 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7666 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7668 dst = SET_DEST (set);
7669 if (! rtx_equal_p (dst, SET_DEST (set2))
7670 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7671 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7672 || (INTVAL (XEXP (SET_SRC (set), 1))
7673 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7675 delete_related_insns (prev);
7676 delete_related_insns (next);
7679 /* Subfunction of delete_address_reloads: process registers found in X. */
7681 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
7683 rtx prev, set, dst, i2;
7685 enum rtx_code code = GET_CODE (x);
7689 const char *fmt = GET_RTX_FORMAT (code);
7690 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7693 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7694 else if (fmt[i] == 'E')
7696 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7697 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7704 if (spill_reg_order[REGNO (x)] < 0)
7707 /* Scan backwards for the insn that sets x. This might be a way back due
7709 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7711 code = GET_CODE (prev);
7712 if (code == CODE_LABEL || code == JUMP_INSN)
7714 if (GET_RTX_CLASS (code) != 'i')
7716 if (reg_set_p (x, PATTERN (prev)))
7718 if (reg_referenced_p (x, PATTERN (prev)))
7721 if (! prev || INSN_UID (prev) < reload_first_uid)
7723 /* Check that PREV only sets the reload register. */
7724 set = single_set (prev);
7727 dst = SET_DEST (set);
7728 if (GET_CODE (dst) != REG
7729 || ! rtx_equal_p (dst, x))
7731 if (! reg_set_p (dst, PATTERN (dead_insn)))
7733 /* Check if DST was used in a later insn -
7734 it might have been inherited. */
7735 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7737 if (GET_CODE (i2) == CODE_LABEL)
7741 if (reg_referenced_p (dst, PATTERN (i2)))
7743 /* If there is a reference to the register in the current insn,
7744 it might be loaded in a non-inherited reload. If no other
7745 reload uses it, that means the register is set before
7747 if (i2 == current_insn)
7749 for (j = n_reloads - 1; j >= 0; j--)
7750 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7751 || reload_override_in[j] == dst)
7753 for (j = n_reloads - 1; j >= 0; j--)
7754 if (rld[j].in && rld[j].reg_rtx == dst)
7761 if (GET_CODE (i2) == JUMP_INSN)
7763 /* If DST is still live at CURRENT_INSN, check if it is used for
7764 any reload. Note that even if CURRENT_INSN sets DST, we still
7765 have to check the reloads. */
7766 if (i2 == current_insn)
7768 for (j = n_reloads - 1; j >= 0; j--)
7769 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7770 || reload_override_in[j] == dst)
7772 /* ??? We can't finish the loop here, because dst might be
7773 allocated to a pseudo in this block if no reload in this
7774 block needs any of the classes containing DST - see
7775 spill_hard_reg. There is no easy way to tell this, so we
7776 have to scan till the end of the basic block. */
7778 if (reg_set_p (dst, PATTERN (i2)))
7782 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7783 reg_reloaded_contents[REGNO (dst)] = -1;
7787 /* Output reload-insns to reload VALUE into RELOADREG.
7788 VALUE is an autoincrement or autodecrement RTX whose operand
7789 is a register or memory location;
7790 so reloading involves incrementing that location.
7791 IN is either identical to VALUE, or some cheaper place to reload from.
7793 INC_AMOUNT is the number to increment or decrement by (always positive).
7794 This cannot be deduced from VALUE.
7796 Return the instruction that stores into RELOADREG. */
7799 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
7801 /* REG or MEM to be copied and incremented. */
7802 rtx incloc = XEXP (value, 0);
7803 /* Nonzero if increment after copying. */
7804 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7810 rtx real_in = in == value ? XEXP (in, 0) : in;
7812 /* No hard register is equivalent to this register after
7813 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7814 we could inc/dec that register as well (maybe even using it for
7815 the source), but I'm not sure it's worth worrying about. */
7816 if (GET_CODE (incloc) == REG)
7817 reg_last_reload_reg[REGNO (incloc)] = 0;
7819 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7820 inc_amount = -inc_amount;
7822 inc = GEN_INT (inc_amount);
7824 /* If this is post-increment, first copy the location to the reload reg. */
7825 if (post && real_in != reloadreg)
7826 emit_insn (gen_move_insn (reloadreg, real_in));
7830 /* See if we can directly increment INCLOC. Use a method similar to
7831 that in gen_reload. */
7833 last = get_last_insn ();
7834 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7835 gen_rtx_PLUS (GET_MODE (incloc),
7838 code = recog_memoized (add_insn);
7841 extract_insn (add_insn);
7842 if (constrain_operands (1))
7844 /* If this is a pre-increment and we have incremented the value
7845 where it lives, copy the incremented value to RELOADREG to
7846 be used as an address. */
7849 emit_insn (gen_move_insn (reloadreg, incloc));
7854 delete_insns_since (last);
7857 /* If couldn't do the increment directly, must increment in RELOADREG.
7858 The way we do this depends on whether this is pre- or post-increment.
7859 For pre-increment, copy INCLOC to the reload register, increment it
7860 there, then save back. */
7864 if (in != reloadreg)
7865 emit_insn (gen_move_insn (reloadreg, real_in));
7866 emit_insn (gen_add2_insn (reloadreg, inc));
7867 store = emit_insn (gen_move_insn (incloc, reloadreg));
7872 Because this might be a jump insn or a compare, and because RELOADREG
7873 may not be available after the insn in an input reload, we must do
7874 the incrementation before the insn being reloaded for.
7876 We have already copied IN to RELOADREG. Increment the copy in
7877 RELOADREG, save that back, then decrement RELOADREG so it has
7878 the original value. */
7880 emit_insn (gen_add2_insn (reloadreg, inc));
7881 store = emit_insn (gen_move_insn (incloc, reloadreg));
7882 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7890 add_auto_inc_notes (rtx insn, rtx x)
7892 enum rtx_code code = GET_CODE (x);
7896 if (code == MEM && auto_inc_p (XEXP (x, 0)))
7899 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
7903 /* Scan all the operand sub-expressions. */
7904 fmt = GET_RTX_FORMAT (code);
7905 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7908 add_auto_inc_notes (insn, XEXP (x, i));
7909 else if (fmt[i] == 'E')
7910 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7911 add_auto_inc_notes (insn, XVECEXP (x, i, j));
7916 /* Copy EH notes from an insn to its reloads. */
7918 copy_eh_notes (rtx insn, rtx x)
7920 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
7923 for (; x != 0; x = NEXT_INSN (x))
7925 if (may_trap_p (PATTERN (x)))
7927 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
7933 /* This is used by reload pass, that does emit some instructions after
7934 abnormal calls moving basic block end, but in fact it wants to emit
7935 them on the edge. Looks for abnormal call edges, find backward the
7936 proper call and fix the damage.
7938 Similar handle instructions throwing exceptions internally. */
7940 fixup_abnormal_edges (void)
7942 bool inserted = false;
7949 /* Look for cases we are interested in - calls or instructions causing
7951 for (e = bb->succ; e; e = e->succ_next)
7953 if (e->flags & EDGE_ABNORMAL_CALL)
7955 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
7956 == (EDGE_ABNORMAL | EDGE_EH))
7959 if (e && GET_CODE (bb->end) != CALL_INSN && !can_throw_internal (bb->end))
7961 rtx insn = bb->end, stop = NEXT_INSN (bb->end);
7963 for (e = bb->succ; e; e = e->succ_next)
7964 if (e->flags & EDGE_FALLTHRU)
7966 /* Get past the new insns generated. Allow notes, as the insns may
7967 be already deleted. */
7968 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE)
7969 && !can_throw_internal (insn)
7970 && insn != bb->head)
7971 insn = PREV_INSN (insn);
7972 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn))
7976 insn = NEXT_INSN (insn);
7977 while (insn && insn != stop)
7979 next = NEXT_INSN (insn);
7984 /* Sometimes there's still the return value USE.
7985 If it's placed after a trapping call (i.e. that
7986 call is the last insn anyway), we have no fallthru
7987 edge. Simply delete this use and don't try to insert
7988 on the non-existent edge. */
7989 if (GET_CODE (PATTERN (insn)) != USE)
7991 /* We're not deleting it, we're moving it. */
7992 INSN_DELETED_P (insn) = 0;
7993 PREV_INSN (insn) = NULL_RTX;
7994 NEXT_INSN (insn) = NULL_RTX;
7996 insert_insn_on_edge (insn, e);
8003 /* We've possibly turned single trapping insn into multiple ones. */
8004 if (flag_non_call_exceptions)
8007 blocks = sbitmap_alloc (last_basic_block);
8008 sbitmap_ones (blocks);
8009 find_many_sub_basic_blocks (blocks);
8012 commit_edge_insertions ();
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