1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "insn-flags.h"
32 #include "insn-codes.h"
37 #include "basic-block.h"
45 #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY
46 #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
49 /* This file contains the reload pass of the compiler, which is
50 run after register allocation has been done. It checks that
51 each insn is valid (operands required to be in registers really
52 are in registers of the proper class) and fixes up invalid ones
53 by copying values temporarily into registers for the insns
56 The results of register allocation are described by the vector
57 reg_renumber; the insns still contain pseudo regs, but reg_renumber
58 can be used to find which hard reg, if any, a pseudo reg is in.
60 The technique we always use is to free up a few hard regs that are
61 called ``reload regs'', and for each place where a pseudo reg
62 must be in a hard reg, copy it temporarily into one of the reload regs.
64 Reload regs are allocated locally for every instruction that needs
65 reloads. When there are pseudos which are allocated to a register that
66 has been chosen as a reload reg, such pseudos must be ``spilled''.
67 This means that they go to other hard regs, or to stack slots if no other
68 available hard regs can be found. Spilling can invalidate more
69 insns, requiring additional need for reloads, so we must keep checking
70 until the process stabilizes.
72 For machines with different classes of registers, we must keep track
73 of the register class needed for each reload, and make sure that
74 we allocate enough reload registers of each class.
76 The file reload.c contains the code that checks one insn for
77 validity and reports the reloads that it needs. This file
78 is in charge of scanning the entire rtl code, accumulating the
79 reload needs, spilling, assigning reload registers to use for
80 fixing up each insn, and generating the new insns to copy values
81 into the reload registers. */
83 #ifndef REGISTER_MOVE_COST
84 #define REGISTER_MOVE_COST(x, y) 2
88 #define LOCAL_REGNO(REGNO) 0
91 /* During reload_as_needed, element N contains a REG rtx for the hard reg
92 into which reg N has been reloaded (perhaps for a previous insn). */
93 static rtx *reg_last_reload_reg;
95 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
96 for an output reload that stores into reg N. */
97 static char *reg_has_output_reload;
99 /* Indicates which hard regs are reload-registers for an output reload
100 in the current insn. */
101 static HARD_REG_SET reg_is_output_reload;
103 /* Element N is the constant value to which pseudo reg N is equivalent,
104 or zero if pseudo reg N is not equivalent to a constant.
105 find_reloads looks at this in order to replace pseudo reg N
106 with the constant it stands for. */
107 rtx *reg_equiv_constant;
109 /* Element N is a memory location to which pseudo reg N is equivalent,
110 prior to any register elimination (such as frame pointer to stack
111 pointer). Depending on whether or not it is a valid address, this value
112 is transferred to either reg_equiv_address or reg_equiv_mem. */
113 rtx *reg_equiv_memory_loc;
115 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
116 This is used when the address is not valid as a memory address
117 (because its displacement is too big for the machine.) */
118 rtx *reg_equiv_address;
120 /* Element N is the memory slot to which pseudo reg N is equivalent,
121 or zero if pseudo reg N is not equivalent to a memory slot. */
124 /* Widest width in which each pseudo reg is referred to (via subreg). */
125 static unsigned int *reg_max_ref_width;
127 /* Element N is the list of insns that initialized reg N from its equivalent
128 constant or memory slot. */
129 static rtx *reg_equiv_init;
131 /* Vector to remember old contents of reg_renumber before spilling. */
132 static short *reg_old_renumber;
134 /* During reload_as_needed, element N contains the last pseudo regno reloaded
135 into hard register N. If that pseudo reg occupied more than one register,
136 reg_reloaded_contents points to that pseudo for each spill register in
137 use; all of these must remain set for an inheritance to occur. */
138 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
140 /* During reload_as_needed, element N contains the insn for which
141 hard register N was last used. Its contents are significant only
142 when reg_reloaded_valid is set for this register. */
143 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
145 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
146 static HARD_REG_SET reg_reloaded_valid;
147 /* Indicate if the register was dead at the end of the reload.
148 This is only valid if reg_reloaded_contents is set and valid. */
149 static HARD_REG_SET reg_reloaded_dead;
151 /* Number of spill-regs so far; number of valid elements of spill_regs. */
154 /* In parallel with spill_regs, contains REG rtx's for those regs.
155 Holds the last rtx used for any given reg, or 0 if it has never
156 been used for spilling yet. This rtx is reused, provided it has
158 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
160 /* In parallel with spill_regs, contains nonzero for a spill reg
161 that was stored after the last time it was used.
162 The precise value is the insn generated to do the store. */
163 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
165 /* This is the register that was stored with spill_reg_store. This is a
166 copy of reload_out / reload_out_reg when the value was stored; if
167 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
168 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
170 /* This table is the inverse mapping of spill_regs:
171 indexed by hard reg number,
172 it contains the position of that reg in spill_regs,
173 or -1 for something that is not in spill_regs.
175 ?!? This is no longer accurate. */
176 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
178 /* This reg set indicates registers that can't be used as spill registers for
179 the currently processed insn. These are the hard registers which are live
180 during the insn, but not allocated to pseudos, as well as fixed
182 static HARD_REG_SET bad_spill_regs;
184 /* These are the hard registers that can't be used as spill register for any
185 insn. This includes registers used for user variables and registers that
186 we can't eliminate. A register that appears in this set also can't be used
187 to retry register allocation. */
188 static HARD_REG_SET bad_spill_regs_global;
190 /* Describes order of use of registers for reloading
191 of spilled pseudo-registers. `n_spills' is the number of
192 elements that are actually valid; new ones are added at the end.
194 Both spill_regs and spill_reg_order are used on two occasions:
195 once during find_reload_regs, where they keep track of the spill registers
196 for a single insn, but also during reload_as_needed where they show all
197 the registers ever used by reload. For the latter case, the information
198 is calculated during finish_spills. */
199 static short spill_regs[FIRST_PSEUDO_REGISTER];
201 /* This vector of reg sets indicates, for each pseudo, which hard registers
202 may not be used for retrying global allocation because the register was
203 formerly spilled from one of them. If we allowed reallocating a pseudo to
204 a register that it was already allocated to, reload might not
206 static HARD_REG_SET *pseudo_previous_regs;
208 /* This vector of reg sets indicates, for each pseudo, which hard
209 registers may not be used for retrying global allocation because they
210 are used as spill registers during one of the insns in which the
212 static HARD_REG_SET *pseudo_forbidden_regs;
214 /* All hard regs that have been used as spill registers for any insn are
215 marked in this set. */
216 static HARD_REG_SET used_spill_regs;
218 /* Index of last register assigned as a spill register. We allocate in
219 a round-robin fashion. */
220 static int last_spill_reg;
222 /* Nonzero if indirect addressing is supported on the machine; this means
223 that spilling (REG n) does not require reloading it into a register in
224 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
225 value indicates the level of indirect addressing supported, e.g., two
226 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
228 static char spill_indirect_levels;
230 /* Nonzero if indirect addressing is supported when the innermost MEM is
231 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
232 which these are valid is the same as spill_indirect_levels, above. */
233 char indirect_symref_ok;
235 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
236 char double_reg_address_ok;
238 /* Record the stack slot for each spilled hard register. */
239 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
241 /* Width allocated so far for that stack slot. */
242 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
244 /* Record which pseudos needed to be spilled. */
245 static regset_head spilled_pseudos;
247 /* Used for communication between order_regs_for_reload and count_pseudo.
248 Used to avoid counting one pseudo twice. */
249 static regset_head pseudos_counted;
251 /* First uid used by insns created by reload in this function.
252 Used in find_equiv_reg. */
253 int reload_first_uid;
255 /* Flag set by local-alloc or global-alloc if anything is live in
256 a call-clobbered reg across calls. */
257 int caller_save_needed;
259 /* Set to 1 while reload_as_needed is operating.
260 Required by some machines to handle any generated moves differently. */
261 int reload_in_progress = 0;
263 /* These arrays record the insn_code of insns that may be needed to
264 perform input and output reloads of special objects. They provide a
265 place to pass a scratch register. */
266 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
267 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
269 /* This obstack is used for allocation of rtl during register elimination.
270 The allocated storage can be freed once find_reloads has processed the
272 struct obstack reload_obstack;
274 /* Points to the beginning of the reload_obstack. All insn_chain structures
275 are allocated first. */
276 char *reload_startobj;
278 /* The point after all insn_chain structures. Used to quickly deallocate
279 memory allocated in copy_reloads during calculate_needs_all_insns. */
280 char *reload_firstobj;
282 /* This points before all local rtl generated by register elimination.
283 Used to quickly free all memory after processing one insn. */
284 static char *reload_insn_firstobj;
286 #define obstack_chunk_alloc xmalloc
287 #define obstack_chunk_free free
289 /* List of insn_chain instructions, one for every insn that reload needs to
291 struct insn_chain *reload_insn_chain;
294 extern tree current_function_decl;
296 extern union tree_node *current_function_decl;
299 /* List of all insns needing reloads. */
300 static struct insn_chain *insns_need_reload;
302 /* This structure is used to record information about register eliminations.
303 Each array entry describes one possible way of eliminating a register
304 in favor of another. If there is more than one way of eliminating a
305 particular register, the most preferred should be specified first. */
309 int from; /* Register number to be eliminated. */
310 int to; /* Register number used as replacement. */
311 int initial_offset; /* Initial difference between values. */
312 int can_eliminate; /* Non-zero if this elimination can be done. */
313 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
314 insns made by reload. */
315 int offset; /* Current offset between the two regs. */
316 int previous_offset; /* Offset at end of previous insn. */
317 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
318 rtx from_rtx; /* REG rtx for the register to be eliminated.
319 We cannot simply compare the number since
320 we might then spuriously replace a hard
321 register corresponding to a pseudo
322 assigned to the reg to be eliminated. */
323 rtx to_rtx; /* REG rtx for the replacement. */
326 static struct elim_table *reg_eliminate = 0;
328 /* This is an intermediate structure to initialize the table. It has
329 exactly the members provided by ELIMINABLE_REGS. */
330 static struct elim_table_1
334 } reg_eliminate_1[] =
336 /* If a set of eliminable registers was specified, define the table from it.
337 Otherwise, default to the normal case of the frame pointer being
338 replaced by the stack pointer. */
340 #ifdef ELIMINABLE_REGS
343 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
346 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
348 /* Record the number of pending eliminations that have an offset not equal
349 to their initial offset. If non-zero, we use a new copy of each
350 replacement result in any insns encountered. */
351 int num_not_at_initial_offset;
353 /* Count the number of registers that we may be able to eliminate. */
354 static int num_eliminable;
355 /* And the number of registers that are equivalent to a constant that
356 can be eliminated to frame_pointer / arg_pointer + constant. */
357 static int num_eliminable_invariants;
359 /* For each label, we record the offset of each elimination. If we reach
360 a label by more than one path and an offset differs, we cannot do the
361 elimination. This information is indexed by the number of the label.
362 The first table is an array of flags that records whether we have yet
363 encountered a label and the second table is an array of arrays, one
364 entry in the latter array for each elimination. */
366 static char *offsets_known_at;
367 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
369 /* Number of labels in the current function. */
371 static int num_labels;
373 static void maybe_fix_stack_asms PARAMS ((void));
374 static void copy_reloads PARAMS ((struct insn_chain *));
375 static void calculate_needs_all_insns PARAMS ((int));
376 static int find_reg PARAMS ((struct insn_chain *, int));
377 static void find_reload_regs PARAMS ((struct insn_chain *));
378 static void select_reload_regs PARAMS ((void));
379 static void delete_caller_save_insns PARAMS ((void));
381 static void spill_failure PARAMS ((rtx, enum reg_class));
382 static void count_spilled_pseudo PARAMS ((int, int, int));
383 static void delete_dead_insn PARAMS ((rtx));
384 static void alter_reg PARAMS ((int, int));
385 static void set_label_offsets PARAMS ((rtx, rtx, int));
386 static void check_eliminable_occurrences PARAMS ((rtx));
387 static void elimination_effects PARAMS ((rtx, enum machine_mode));
388 static int eliminate_regs_in_insn PARAMS ((rtx, int));
389 static void update_eliminable_offsets PARAMS ((void));
390 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
391 static void set_initial_elim_offsets PARAMS ((void));
392 static void verify_initial_elim_offsets PARAMS ((void));
393 static void set_initial_label_offsets PARAMS ((void));
394 static void set_offsets_for_label PARAMS ((rtx));
395 static void init_elim_table PARAMS ((void));
396 static void update_eliminables PARAMS ((HARD_REG_SET *));
397 static void spill_hard_reg PARAMS ((unsigned int, int));
398 static int finish_spills PARAMS ((int));
399 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
400 static void scan_paradoxical_subregs PARAMS ((rtx));
401 static void count_pseudo PARAMS ((int));
402 static void order_regs_for_reload PARAMS ((struct insn_chain *));
403 static void reload_as_needed PARAMS ((int));
404 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
405 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
406 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
409 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
412 static int reload_reg_free_p PARAMS ((unsigned int, int,
414 static int reload_reg_free_for_value_p PARAMS ((int, int, enum reload_type,
415 rtx, rtx, int, int));
416 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
418 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
420 static void failed_reload PARAMS ((rtx, int));
421 static int set_reload_reg PARAMS ((int, int));
422 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
423 static void choose_reload_regs PARAMS ((struct insn_chain *));
424 static void merge_assigned_reloads PARAMS ((rtx));
425 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
426 struct reload *, rtx, int));
427 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
428 struct reload *, int));
429 static void do_input_reload PARAMS ((struct insn_chain *,
430 struct reload *, int));
431 static void do_output_reload PARAMS ((struct insn_chain *,
432 struct reload *, int));
433 static void emit_reload_insns PARAMS ((struct insn_chain *));
434 static void delete_output_reload PARAMS ((rtx, int, int));
435 static void delete_address_reloads PARAMS ((rtx, rtx));
436 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
437 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
438 static int constraint_accepts_reg_p PARAMS ((const char *, rtx));
439 static void reload_cse_regs_1 PARAMS ((rtx));
440 static int reload_cse_noop_set_p PARAMS ((rtx));
441 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
442 static int reload_cse_simplify_operands PARAMS ((rtx));
443 static void reload_combine PARAMS ((void));
444 static void reload_combine_note_use PARAMS ((rtx *, rtx));
445 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
446 static void reload_cse_move2add PARAMS ((rtx));
447 static void move2add_note_store PARAMS ((rtx, rtx, void *));
449 static void add_auto_inc_notes PARAMS ((rtx, rtx));
451 static rtx gen_mode_int PARAMS ((enum machine_mode,
453 static void failed_reload PARAMS ((rtx, int));
454 static int set_reload_reg PARAMS ((int, int));
455 static void reload_cse_delete_noop_set PARAMS ((rtx, rtx));
456 static void reload_cse_simplify PARAMS ((rtx));
457 extern void dump_needs PARAMS ((struct insn_chain *));
459 /* Initialize the reload pass once per compilation. */
466 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
467 Set spill_indirect_levels to the number of levels such addressing is
468 permitted, zero if it is not permitted at all. */
471 = gen_rtx_MEM (Pmode,
474 LAST_VIRTUAL_REGISTER + 1),
476 spill_indirect_levels = 0;
478 while (memory_address_p (QImode, tem))
480 spill_indirect_levels++;
481 tem = gen_rtx_MEM (Pmode, tem);
484 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
486 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
487 indirect_symref_ok = memory_address_p (QImode, tem);
489 /* See if reg+reg is a valid (and offsettable) address. */
491 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
493 tem = gen_rtx_PLUS (Pmode,
494 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
495 gen_rtx_REG (Pmode, i));
497 /* This way, we make sure that reg+reg is an offsettable address. */
498 tem = plus_constant (tem, 4);
500 if (memory_address_p (QImode, tem))
502 double_reg_address_ok = 1;
507 /* Initialize obstack for our rtl allocation. */
508 gcc_obstack_init (&reload_obstack);
509 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
511 INIT_REG_SET (&spilled_pseudos);
512 INIT_REG_SET (&pseudos_counted);
515 /* List of insn chains that are currently unused. */
516 static struct insn_chain *unused_insn_chains = 0;
518 /* Allocate an empty insn_chain structure. */
522 struct insn_chain *c;
524 if (unused_insn_chains == 0)
526 c = (struct insn_chain *)
527 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
528 INIT_REG_SET (&c->live_throughout);
529 INIT_REG_SET (&c->dead_or_set);
533 c = unused_insn_chains;
534 unused_insn_chains = c->next;
536 c->is_caller_save_insn = 0;
537 c->need_operand_change = 0;
543 /* Small utility function to set all regs in hard reg set TO which are
544 allocated to pseudos in regset FROM. */
547 compute_use_by_pseudos (to, from)
553 EXECUTE_IF_SET_IN_REG_SET
554 (from, FIRST_PSEUDO_REGISTER, regno,
556 int r = reg_renumber[regno];
561 /* reload_combine uses the information from
562 BASIC_BLOCK->global_live_at_start, which might still
563 contain registers that have not actually been allocated
564 since they have an equivalence. */
565 if (! reload_completed)
570 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
572 SET_HARD_REG_BIT (*to, r + nregs);
577 /* Global variables used by reload and its subroutines. */
579 /* Set during calculate_needs if an insn needs register elimination. */
580 static int something_needs_elimination;
581 /* Set during calculate_needs if an insn needs an operand changed. */
582 int something_needs_operands_changed;
584 /* Nonzero means we couldn't get enough spill regs. */
587 /* Main entry point for the reload pass.
589 FIRST is the first insn of the function being compiled.
591 GLOBAL nonzero means we were called from global_alloc
592 and should attempt to reallocate any pseudoregs that we
593 displace from hard regs we will use for reloads.
594 If GLOBAL is zero, we do not have enough information to do that,
595 so any pseudo reg that is spilled must go to the stack.
597 Return value is nonzero if reload failed
598 and we must not do any more for this function. */
601 reload (first, global)
607 register struct elim_table *ep;
609 /* The two pointers used to track the true location of the memory used
610 for label offsets. */
611 char *real_known_ptr = NULL_PTR;
612 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
614 /* Make sure even insns with volatile mem refs are recognizable. */
619 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
621 /* Make sure that the last insn in the chain
622 is not something that needs reloading. */
623 emit_note (NULL_PTR, NOTE_INSN_DELETED);
625 /* Enable find_equiv_reg to distinguish insns made by reload. */
626 reload_first_uid = get_max_uid ();
628 #ifdef SECONDARY_MEMORY_NEEDED
629 /* Initialize the secondary memory table. */
630 clear_secondary_mem ();
633 /* We don't have a stack slot for any spill reg yet. */
634 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
635 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
637 /* Initialize the save area information for caller-save, in case some
641 /* Compute which hard registers are now in use
642 as homes for pseudo registers.
643 This is done here rather than (eg) in global_alloc
644 because this point is reached even if not optimizing. */
645 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
648 /* A function that receives a nonlocal goto must save all call-saved
650 if (current_function_has_nonlocal_label)
651 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
652 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
653 regs_ever_live[i] = 1;
655 /* Find all the pseudo registers that didn't get hard regs
656 but do have known equivalent constants or memory slots.
657 These include parameters (known equivalent to parameter slots)
658 and cse'd or loop-moved constant memory addresses.
660 Record constant equivalents in reg_equiv_constant
661 so they will be substituted by find_reloads.
662 Record memory equivalents in reg_mem_equiv so they can
663 be substituted eventually by altering the REG-rtx's. */
665 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
666 reg_equiv_memory_loc = (rtx *) xcalloc (max_regno, sizeof (rtx));
667 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
668 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
669 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
670 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
671 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
672 bcopy ((PTR) reg_renumber, (PTR) reg_old_renumber, max_regno * sizeof (short));
673 pseudo_forbidden_regs
674 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
676 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
678 CLEAR_HARD_REG_SET (bad_spill_regs_global);
680 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
681 Also find all paradoxical subregs and find largest such for each pseudo.
682 On machines with small register classes, record hard registers that
683 are used for user variables. These can never be used for spills.
684 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
685 caller-saved registers must be marked live. */
687 num_eliminable_invariants = 0;
688 for (insn = first; insn; insn = NEXT_INSN (insn))
690 rtx set = single_set (insn);
692 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
693 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
694 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
695 if (! call_used_regs[i])
696 regs_ever_live[i] = 1;
698 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
700 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
702 #ifdef LEGITIMATE_PIC_OPERAND_P
703 && (! function_invariant_p (XEXP (note, 0))
705 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
709 rtx x = XEXP (note, 0);
710 i = REGNO (SET_DEST (set));
711 if (i > LAST_VIRTUAL_REGISTER)
713 if (GET_CODE (x) == MEM)
715 /* If the operand is a PLUS, the MEM may be shared,
716 so make sure we have an unshared copy here. */
717 if (GET_CODE (XEXP (x, 0)) == PLUS)
720 reg_equiv_memory_loc[i] = x;
722 else if (function_invariant_p (x))
724 if (GET_CODE (x) == PLUS)
726 /* This is PLUS of frame pointer and a constant,
727 and might be shared. Unshare it. */
728 reg_equiv_constant[i] = copy_rtx (x);
729 num_eliminable_invariants++;
731 else if (x == frame_pointer_rtx
732 || x == arg_pointer_rtx)
734 reg_equiv_constant[i] = x;
735 num_eliminable_invariants++;
737 else if (LEGITIMATE_CONSTANT_P (x))
738 reg_equiv_constant[i] = x;
740 reg_equiv_memory_loc[i]
741 = force_const_mem (GET_MODE (SET_DEST (set)), x);
746 /* If this register is being made equivalent to a MEM
747 and the MEM is not SET_SRC, the equivalencing insn
748 is one with the MEM as a SET_DEST and it occurs later.
749 So don't mark this insn now. */
750 if (GET_CODE (x) != MEM
751 || rtx_equal_p (SET_SRC (set), x))
753 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
758 /* If this insn is setting a MEM from a register equivalent to it,
759 this is the equivalencing insn. */
760 else if (set && GET_CODE (SET_DEST (set)) == MEM
761 && GET_CODE (SET_SRC (set)) == REG
762 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
763 && rtx_equal_p (SET_DEST (set),
764 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
765 reg_equiv_init[REGNO (SET_SRC (set))]
766 = gen_rtx_INSN_LIST (VOIDmode, insn,
767 reg_equiv_init[REGNO (SET_SRC (set))]);
770 scan_paradoxical_subregs (PATTERN (insn));
775 num_labels = max_label_num () - get_first_label_num ();
777 /* Allocate the tables used to store offset information at labels. */
778 /* We used to use alloca here, but the size of what it would try to
779 allocate would occasionally cause it to exceed the stack limit and
780 cause a core dump. */
781 real_known_ptr = xmalloc (num_labels);
783 = (int (*)[NUM_ELIMINABLE_REGS])
784 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
786 offsets_known_at = real_known_ptr - get_first_label_num ();
788 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
790 /* Alter each pseudo-reg rtx to contain its hard reg number.
791 Assign stack slots to the pseudos that lack hard regs or equivalents.
792 Do not touch virtual registers. */
794 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
797 /* If we have some registers we think can be eliminated, scan all insns to
798 see if there is an insn that sets one of these registers to something
799 other than itself plus a constant. If so, the register cannot be
800 eliminated. Doing this scan here eliminates an extra pass through the
801 main reload loop in the most common case where register elimination
803 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
804 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
805 || GET_CODE (insn) == CALL_INSN)
806 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
808 maybe_fix_stack_asms ();
810 insns_need_reload = 0;
811 something_needs_elimination = 0;
813 /* Initialize to -1, which means take the first spill register. */
816 /* Spill any hard regs that we know we can't eliminate. */
817 CLEAR_HARD_REG_SET (used_spill_regs);
818 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
819 if (! ep->can_eliminate)
820 spill_hard_reg (ep->from, 1);
822 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
823 if (frame_pointer_needed)
824 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
826 finish_spills (global);
828 /* From now on, we may need to generate moves differently. We may also
829 allow modifications of insns which cause them to not be recognized.
830 Any such modifications will be cleaned up during reload itself. */
831 reload_in_progress = 1;
833 /* This loop scans the entire function each go-round
834 and repeats until one repetition spills no additional hard regs. */
837 int something_changed;
840 HOST_WIDE_INT starting_frame_size;
842 /* Round size of stack frame to stack_alignment_needed. This must be done
843 here because the stack size may be a part of the offset computation
844 for register elimination, and there might have been new stack slots
845 created in the last iteration of this loop. */
846 if (cfun->stack_alignment_needed)
847 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
849 starting_frame_size = get_frame_size ();
851 set_initial_elim_offsets ();
852 set_initial_label_offsets ();
854 /* For each pseudo register that has an equivalent location defined,
855 try to eliminate any eliminable registers (such as the frame pointer)
856 assuming initial offsets for the replacement register, which
859 If the resulting location is directly addressable, substitute
860 the MEM we just got directly for the old REG.
862 If it is not addressable but is a constant or the sum of a hard reg
863 and constant, it is probably not addressable because the constant is
864 out of range, in that case record the address; we will generate
865 hairy code to compute the address in a register each time it is
866 needed. Similarly if it is a hard register, but one that is not
867 valid as an address register.
869 If the location is not addressable, but does not have one of the
870 above forms, assign a stack slot. We have to do this to avoid the
871 potential of producing lots of reloads if, e.g., a location involves
872 a pseudo that didn't get a hard register and has an equivalent memory
873 location that also involves a pseudo that didn't get a hard register.
875 Perhaps at some point we will improve reload_when_needed handling
876 so this problem goes away. But that's very hairy. */
878 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
879 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
881 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
883 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
885 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
886 else if (CONSTANT_P (XEXP (x, 0))
887 || (GET_CODE (XEXP (x, 0)) == REG
888 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
889 || (GET_CODE (XEXP (x, 0)) == PLUS
890 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
891 && (REGNO (XEXP (XEXP (x, 0), 0))
892 < FIRST_PSEUDO_REGISTER)
893 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
894 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
897 /* Make a new stack slot. Then indicate that something
898 changed so we go back and recompute offsets for
899 eliminable registers because the allocation of memory
900 below might change some offset. reg_equiv_{mem,address}
901 will be set up for this pseudo on the next pass around
903 reg_equiv_memory_loc[i] = 0;
904 reg_equiv_init[i] = 0;
909 if (caller_save_needed)
912 /* If we allocated another stack slot, redo elimination bookkeeping. */
913 if (starting_frame_size != get_frame_size ())
916 if (caller_save_needed)
918 save_call_clobbered_regs ();
919 /* That might have allocated new insn_chain structures. */
920 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
923 calculate_needs_all_insns (global);
925 CLEAR_REG_SET (&spilled_pseudos);
928 something_changed = 0;
930 /* If we allocated any new memory locations, make another pass
931 since it might have changed elimination offsets. */
932 if (starting_frame_size != get_frame_size ())
933 something_changed = 1;
936 HARD_REG_SET to_spill;
937 CLEAR_HARD_REG_SET (to_spill);
938 update_eliminables (&to_spill);
939 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
940 if (TEST_HARD_REG_BIT (to_spill, i))
942 spill_hard_reg (i, 1);
945 /* Regardless of the state of spills, if we previously had
946 a register that we thought we could eliminate, but no can
947 not eliminate, we must run another pass.
949 Consider pseudos which have an entry in reg_equiv_* which
950 reference an eliminable register. We must make another pass
951 to update reg_equiv_* so that we do not substitute in the
952 old value from when we thought the elimination could be
954 something_changed = 1;
958 select_reload_regs ();
962 if (insns_need_reload != 0 || did_spill)
963 something_changed |= finish_spills (global);
965 if (! something_changed)
968 if (caller_save_needed)
969 delete_caller_save_insns ();
971 obstack_free (&reload_obstack, reload_firstobj);
974 /* If global-alloc was run, notify it of any register eliminations we have
977 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
978 if (ep->can_eliminate)
979 mark_elimination (ep->from, ep->to);
981 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
982 If that insn didn't set the register (i.e., it copied the register to
983 memory), just delete that insn instead of the equivalencing insn plus
984 anything now dead. If we call delete_dead_insn on that insn, we may
985 delete the insn that actually sets the register if the register dies
986 there and that is incorrect. */
988 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
990 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
993 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
995 rtx equiv_insn = XEXP (list, 0);
996 if (GET_CODE (equiv_insn) == NOTE)
998 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
999 delete_dead_insn (equiv_insn);
1002 PUT_CODE (equiv_insn, NOTE);
1003 NOTE_SOURCE_FILE (equiv_insn) = 0;
1004 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1010 /* Use the reload registers where necessary
1011 by generating move instructions to move the must-be-register
1012 values into or out of the reload registers. */
1014 if (insns_need_reload != 0 || something_needs_elimination
1015 || something_needs_operands_changed)
1017 int old_frame_size = get_frame_size ();
1019 reload_as_needed (global);
1021 if (old_frame_size != get_frame_size ())
1025 verify_initial_elim_offsets ();
1028 /* If we were able to eliminate the frame pointer, show that it is no
1029 longer live at the start of any basic block. If it ls live by
1030 virtue of being in a pseudo, that pseudo will be marked live
1031 and hence the frame pointer will be known to be live via that
1034 if (! frame_pointer_needed)
1035 for (i = 0; i < n_basic_blocks; i++)
1036 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1037 HARD_FRAME_POINTER_REGNUM);
1039 /* Come here (with failure set nonzero) if we can't get enough spill regs
1040 and we decide not to abort about it. */
1043 CLEAR_REG_SET (&spilled_pseudos);
1044 reload_in_progress = 0;
1046 /* Now eliminate all pseudo regs by modifying them into
1047 their equivalent memory references.
1048 The REG-rtx's for the pseudos are modified in place,
1049 so all insns that used to refer to them now refer to memory.
1051 For a reg that has a reg_equiv_address, all those insns
1052 were changed by reloading so that no insns refer to it any longer;
1053 but the DECL_RTL of a variable decl may refer to it,
1054 and if so this causes the debugging info to mention the variable. */
1056 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1061 int is_readonly = 0;
1063 if (reg_equiv_memory_loc[i])
1065 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1066 is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]);
1067 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1070 if (reg_equiv_mem[i])
1071 addr = XEXP (reg_equiv_mem[i], 0);
1073 if (reg_equiv_address[i])
1074 addr = reg_equiv_address[i];
1078 if (reg_renumber[i] < 0)
1080 rtx reg = regno_reg_rtx[i];
1081 PUT_CODE (reg, MEM);
1082 XEXP (reg, 0) = addr;
1083 REG_USERVAR_P (reg) = 0;
1084 RTX_UNCHANGING_P (reg) = is_readonly;
1085 MEM_IN_STRUCT_P (reg) = in_struct;
1086 MEM_SCALAR_P (reg) = is_scalar;
1087 /* We have no alias information about this newly created
1089 MEM_ALIAS_SET (reg) = 0;
1091 else if (reg_equiv_mem[i])
1092 XEXP (reg_equiv_mem[i], 0) = addr;
1096 /* We must set reload_completed now since the cleanup_subreg_operands call
1097 below will re-recognize each insn and reload may have generated insns
1098 which are only valid during and after reload. */
1099 reload_completed = 1;
1101 /* Make a pass over all the insns and delete all USEs which we inserted
1102 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1103 notes. Delete all CLOBBER insns that don't refer to the return value
1104 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1105 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1106 and regenerate REG_INC notes that may have been moved around. */
1108 for (insn = first; insn; insn = NEXT_INSN (insn))
1113 if ((GET_CODE (PATTERN (insn)) == USE
1114 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1115 || (GET_CODE (PATTERN (insn)) == CLOBBER
1116 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1117 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1119 PUT_CODE (insn, NOTE);
1120 NOTE_SOURCE_FILE (insn) = 0;
1121 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1125 pnote = ®_NOTES (insn);
1128 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1129 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1130 || REG_NOTE_KIND (*pnote) == REG_INC
1131 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1132 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1133 *pnote = XEXP (*pnote, 1);
1135 pnote = &XEXP (*pnote, 1);
1139 add_auto_inc_notes (insn, PATTERN (insn));
1142 /* And simplify (subreg (reg)) if it appears as an operand. */
1143 cleanup_subreg_operands (insn);
1146 /* If we are doing stack checking, give a warning if this function's
1147 frame size is larger than we expect. */
1148 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1150 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1151 static int verbose_warned = 0;
1153 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1154 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1155 size += UNITS_PER_WORD;
1157 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1159 warning ("frame size too large for reliable stack checking");
1160 if (! verbose_warned)
1162 warning ("try reducing the number of local variables");
1168 /* Indicate that we no longer have known memory locations or constants. */
1169 if (reg_equiv_constant)
1170 free (reg_equiv_constant);
1171 reg_equiv_constant = 0;
1172 if (reg_equiv_memory_loc)
1173 free (reg_equiv_memory_loc);
1174 reg_equiv_memory_loc = 0;
1177 free (real_known_ptr);
1181 free (reg_equiv_mem);
1182 free (reg_equiv_init);
1183 free (reg_equiv_address);
1184 free (reg_max_ref_width);
1185 free (reg_old_renumber);
1186 free (pseudo_previous_regs);
1187 free (pseudo_forbidden_regs);
1189 CLEAR_HARD_REG_SET (used_spill_regs);
1190 for (i = 0; i < n_spills; i++)
1191 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1193 /* Free all the insn_chain structures at once. */
1194 obstack_free (&reload_obstack, reload_startobj);
1195 unused_insn_chains = 0;
1200 /* Yet another special case. Unfortunately, reg-stack forces people to
1201 write incorrect clobbers in asm statements. These clobbers must not
1202 cause the register to appear in bad_spill_regs, otherwise we'll call
1203 fatal_insn later. We clear the corresponding regnos in the live
1204 register sets to avoid this.
1205 The whole thing is rather sick, I'm afraid. */
1208 maybe_fix_stack_asms ()
1211 const char *constraints[MAX_RECOG_OPERANDS];
1212 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1213 struct insn_chain *chain;
1215 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1218 HARD_REG_SET clobbered, allowed;
1221 if (! INSN_P (chain->insn)
1222 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1224 pat = PATTERN (chain->insn);
1225 if (GET_CODE (pat) != PARALLEL)
1228 CLEAR_HARD_REG_SET (clobbered);
1229 CLEAR_HARD_REG_SET (allowed);
1231 /* First, make a mask of all stack regs that are clobbered. */
1232 for (i = 0; i < XVECLEN (pat, 0); i++)
1234 rtx t = XVECEXP (pat, 0, i);
1235 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1236 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1239 /* Get the operand values and constraints out of the insn. */
1240 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1241 constraints, operand_mode);
1243 /* For every operand, see what registers are allowed. */
1244 for (i = 0; i < noperands; i++)
1246 const char *p = constraints[i];
1247 /* For every alternative, we compute the class of registers allowed
1248 for reloading in CLS, and merge its contents into the reg set
1250 int cls = (int) NO_REGS;
1256 if (c == '\0' || c == ',' || c == '#')
1258 /* End of one alternative - mark the regs in the current
1259 class, and reset the class. */
1260 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1265 } while (c != '\0' && c != ',');
1273 case '=': case '+': case '*': case '%': case '?': case '!':
1274 case '0': case '1': case '2': case '3': case '4': case 'm':
1275 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1276 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1277 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1282 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1287 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1291 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1296 /* Those of the registers which are clobbered, but allowed by the
1297 constraints, must be usable as reload registers. So clear them
1298 out of the life information. */
1299 AND_HARD_REG_SET (allowed, clobbered);
1300 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1301 if (TEST_HARD_REG_BIT (allowed, i))
1303 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1304 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1311 /* Copy the global variables n_reloads and rld into the corresponding elts
1314 copy_reloads (chain)
1315 struct insn_chain *chain;
1317 chain->n_reloads = n_reloads;
1319 = (struct reload *) obstack_alloc (&reload_obstack,
1320 n_reloads * sizeof (struct reload));
1321 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1322 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1325 /* Walk the chain of insns, and determine for each whether it needs reloads
1326 and/or eliminations. Build the corresponding insns_need_reload list, and
1327 set something_needs_elimination as appropriate. */
1329 calculate_needs_all_insns (global)
1332 struct insn_chain **pprev_reload = &insns_need_reload;
1333 struct insn_chain *chain;
1335 something_needs_elimination = 0;
1337 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1338 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1340 rtx insn = chain->insn;
1342 /* Clear out the shortcuts. */
1343 chain->n_reloads = 0;
1344 chain->need_elim = 0;
1345 chain->need_reload = 0;
1346 chain->need_operand_change = 0;
1348 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1349 include REG_LABEL), we need to see what effects this has on the
1350 known offsets at labels. */
1352 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1353 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1354 set_label_offsets (insn, insn, 0);
1358 rtx old_body = PATTERN (insn);
1359 int old_code = INSN_CODE (insn);
1360 rtx old_notes = REG_NOTES (insn);
1361 int did_elimination = 0;
1362 int operands_changed = 0;
1363 rtx set = single_set (insn);
1365 /* Skip insns that only set an equivalence. */
1366 if (set && GET_CODE (SET_DEST (set)) == REG
1367 && reg_renumber[REGNO (SET_DEST (set))] < 0
1368 && reg_equiv_constant[REGNO (SET_DEST (set))])
1371 /* If needed, eliminate any eliminable registers. */
1372 if (num_eliminable || num_eliminable_invariants)
1373 did_elimination = eliminate_regs_in_insn (insn, 0);
1375 /* Analyze the instruction. */
1376 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1377 global, spill_reg_order);
1379 /* If a no-op set needs more than one reload, this is likely
1380 to be something that needs input address reloads. We
1381 can't get rid of this cleanly later, and it is of no use
1382 anyway, so discard it now.
1383 We only do this when expensive_optimizations is enabled,
1384 since this complements reload inheritance / output
1385 reload deletion, and it can make debugging harder. */
1386 if (flag_expensive_optimizations && n_reloads > 1)
1388 rtx set = single_set (insn);
1390 && SET_SRC (set) == SET_DEST (set)
1391 && GET_CODE (SET_SRC (set)) == REG
1392 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1394 PUT_CODE (insn, NOTE);
1395 NOTE_SOURCE_FILE (insn) = 0;
1396 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1401 update_eliminable_offsets ();
1403 /* Remember for later shortcuts which insns had any reloads or
1404 register eliminations. */
1405 chain->need_elim = did_elimination;
1406 chain->need_reload = n_reloads > 0;
1407 chain->need_operand_change = operands_changed;
1409 /* Discard any register replacements done. */
1410 if (did_elimination)
1412 obstack_free (&reload_obstack, reload_insn_firstobj);
1413 PATTERN (insn) = old_body;
1414 INSN_CODE (insn) = old_code;
1415 REG_NOTES (insn) = old_notes;
1416 something_needs_elimination = 1;
1419 something_needs_operands_changed |= operands_changed;
1423 copy_reloads (chain);
1424 *pprev_reload = chain;
1425 pprev_reload = &chain->next_need_reload;
1432 /* Comparison function for qsort to decide which of two reloads
1433 should be handled first. *P1 and *P2 are the reload numbers. */
1436 reload_reg_class_lower (r1p, r2p)
1440 register int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1443 /* Consider required reloads before optional ones. */
1444 t = rld[r1].optional - rld[r2].optional;
1448 /* Count all solitary classes before non-solitary ones. */
1449 t = ((reg_class_size[(int) rld[r2].class] == 1)
1450 - (reg_class_size[(int) rld[r1].class] == 1));
1454 /* Aside from solitaires, consider all multi-reg groups first. */
1455 t = rld[r2].nregs - rld[r1].nregs;
1459 /* Consider reloads in order of increasing reg-class number. */
1460 t = (int) rld[r1].class - (int) rld[r2].class;
1464 /* If reloads are equally urgent, sort by reload number,
1465 so that the results of qsort leave nothing to chance. */
1469 /* The cost of spilling each hard reg. */
1470 static int spill_cost[FIRST_PSEUDO_REGISTER];
1472 /* When spilling multiple hard registers, we use SPILL_COST for the first
1473 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1474 only the first hard reg for a multi-reg pseudo. */
1475 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1477 /* Update the spill cost arrays, considering that pseudo REG is live. */
1483 int n_refs = REG_N_REFS (reg);
1484 int r = reg_renumber[reg];
1487 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1488 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1491 SET_REGNO_REG_SET (&pseudos_counted, reg);
1496 spill_add_cost[r] += n_refs;
1498 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1500 spill_cost[r + nregs] += n_refs;
1503 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1504 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1507 order_regs_for_reload (chain)
1508 struct insn_chain *chain;
1511 HARD_REG_SET used_by_pseudos;
1512 HARD_REG_SET used_by_pseudos2;
1514 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1516 memset (spill_cost, 0, sizeof spill_cost);
1517 memset (spill_add_cost, 0, sizeof spill_add_cost);
1519 /* Count number of uses of each hard reg by pseudo regs allocated to it
1520 and then order them by decreasing use. First exclude hard registers
1521 that are live in or across this insn. */
1523 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1524 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1525 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1526 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1528 /* Now find out which pseudos are allocated to it, and update
1530 CLEAR_REG_SET (&pseudos_counted);
1532 EXECUTE_IF_SET_IN_REG_SET
1533 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1537 EXECUTE_IF_SET_IN_REG_SET
1538 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1542 CLEAR_REG_SET (&pseudos_counted);
1545 /* Vector of reload-numbers showing the order in which the reloads should
1547 static short reload_order[MAX_RELOADS];
1549 /* This is used to keep track of the spill regs used in one insn. */
1550 static HARD_REG_SET used_spill_regs_local;
1552 /* We decided to spill hard register SPILLED, which has a size of
1553 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1554 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1555 update SPILL_COST/SPILL_ADD_COST. */
1558 count_spilled_pseudo (spilled, spilled_nregs, reg)
1559 int spilled, spilled_nregs, reg;
1561 int r = reg_renumber[reg];
1562 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1564 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1565 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1568 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1570 spill_add_cost[r] -= REG_N_REFS (reg);
1572 spill_cost[r + nregs] -= REG_N_REFS (reg);
1575 /* Find reload register to use for reload number ORDER. */
1578 find_reg (chain, order)
1579 struct insn_chain *chain;
1582 int rnum = reload_order[order];
1583 struct reload *rl = rld + rnum;
1584 int best_cost = INT_MAX;
1588 HARD_REG_SET not_usable;
1589 HARD_REG_SET used_by_other_reload;
1591 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1592 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1593 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1595 CLEAR_HARD_REG_SET (used_by_other_reload);
1596 for (k = 0; k < order; k++)
1598 int other = reload_order[k];
1600 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1601 for (j = 0; j < rld[other].nregs; j++)
1602 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1605 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1607 unsigned int regno = i;
1609 if (! TEST_HARD_REG_BIT (not_usable, regno)
1610 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1611 && HARD_REGNO_MODE_OK (regno, rl->mode))
1613 int this_cost = spill_cost[regno];
1615 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1617 for (j = 1; j < this_nregs; j++)
1619 this_cost += spill_add_cost[regno + j];
1620 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1621 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1626 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1628 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1630 if (this_cost < best_cost
1631 /* Among registers with equal cost, prefer caller-saved ones, or
1632 use REG_ALLOC_ORDER if it is defined. */
1633 || (this_cost == best_cost
1634 #ifdef REG_ALLOC_ORDER
1635 && (inv_reg_alloc_order[regno]
1636 < inv_reg_alloc_order[best_reg])
1638 && call_used_regs[regno]
1639 && ! call_used_regs[best_reg]
1644 best_cost = this_cost;
1652 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1654 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1655 rl->regno = best_reg;
1657 EXECUTE_IF_SET_IN_REG_SET
1658 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1660 count_spilled_pseudo (best_reg, rl->nregs, j);
1663 EXECUTE_IF_SET_IN_REG_SET
1664 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1666 count_spilled_pseudo (best_reg, rl->nregs, j);
1669 for (i = 0; i < rl->nregs; i++)
1671 if (spill_cost[best_reg + i] != 0
1672 || spill_add_cost[best_reg + i] != 0)
1674 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1679 /* Find more reload regs to satisfy the remaining need of an insn, which
1681 Do it by ascending class number, since otherwise a reg
1682 might be spilled for a big class and might fail to count
1683 for a smaller class even though it belongs to that class. */
1686 find_reload_regs (chain)
1687 struct insn_chain *chain;
1691 /* In order to be certain of getting the registers we need,
1692 we must sort the reloads into order of increasing register class.
1693 Then our grabbing of reload registers will parallel the process
1694 that provided the reload registers. */
1695 for (i = 0; i < chain->n_reloads; i++)
1697 /* Show whether this reload already has a hard reg. */
1698 if (chain->rld[i].reg_rtx)
1700 int regno = REGNO (chain->rld[i].reg_rtx);
1701 chain->rld[i].regno = regno;
1703 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1706 chain->rld[i].regno = -1;
1707 reload_order[i] = i;
1710 n_reloads = chain->n_reloads;
1711 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1713 CLEAR_HARD_REG_SET (used_spill_regs_local);
1716 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1718 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1720 /* Compute the order of preference for hard registers to spill. */
1722 order_regs_for_reload (chain);
1724 for (i = 0; i < n_reloads; i++)
1726 int r = reload_order[i];
1728 /* Ignore reloads that got marked inoperative. */
1729 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1730 && ! rld[r].optional
1731 && rld[r].regno == -1)
1732 if (! find_reg (chain, i))
1734 spill_failure (chain->insn, rld[r].class);
1740 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1741 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1743 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1747 select_reload_regs ()
1749 struct insn_chain *chain;
1751 /* Try to satisfy the needs for each insn. */
1752 for (chain = insns_need_reload; chain != 0;
1753 chain = chain->next_need_reload)
1754 find_reload_regs (chain);
1757 /* Delete all insns that were inserted by emit_caller_save_insns during
1760 delete_caller_save_insns ()
1762 struct insn_chain *c = reload_insn_chain;
1766 while (c != 0 && c->is_caller_save_insn)
1768 struct insn_chain *next = c->next;
1771 if (insn == BLOCK_HEAD (c->block))
1772 BLOCK_HEAD (c->block) = NEXT_INSN (insn);
1773 if (insn == BLOCK_END (c->block))
1774 BLOCK_END (c->block) = PREV_INSN (insn);
1775 if (c == reload_insn_chain)
1776 reload_insn_chain = next;
1778 if (NEXT_INSN (insn) != 0)
1779 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
1780 if (PREV_INSN (insn) != 0)
1781 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
1784 next->prev = c->prev;
1786 c->prev->next = next;
1787 c->next = unused_insn_chains;
1788 unused_insn_chains = c;
1796 /* Handle the failure to find a register to spill.
1797 INSN should be one of the insns which needed this particular spill reg. */
1800 spill_failure (insn, class)
1802 enum reg_class class;
1804 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1805 if (asm_noperands (PATTERN (insn)) >= 0)
1806 error_for_asm (insn, "Can't find a register in class `%s' while reloading `asm'.",
1807 reg_class_names[class]);
1810 error ("Unable to find a register to spill in class `%s'.",
1811 reg_class_names[class]);
1812 fatal_insn ("This is the insn:", insn);
1816 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1817 data that is dead in INSN. */
1820 delete_dead_insn (insn)
1823 rtx prev = prev_real_insn (insn);
1826 /* If the previous insn sets a register that dies in our insn, delete it
1828 if (prev && GET_CODE (PATTERN (prev)) == SET
1829 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1830 && reg_mentioned_p (prev_dest, PATTERN (insn))
1831 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1832 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1833 delete_dead_insn (prev);
1835 PUT_CODE (insn, NOTE);
1836 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1837 NOTE_SOURCE_FILE (insn) = 0;
1840 /* Modify the home of pseudo-reg I.
1841 The new home is present in reg_renumber[I].
1843 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1844 or it may be -1, meaning there is none or it is not relevant.
1845 This is used so that all pseudos spilled from a given hard reg
1846 can share one stack slot. */
1849 alter_reg (i, from_reg)
1853 /* When outputting an inline function, this can happen
1854 for a reg that isn't actually used. */
1855 if (regno_reg_rtx[i] == 0)
1858 /* If the reg got changed to a MEM at rtl-generation time,
1860 if (GET_CODE (regno_reg_rtx[i]) != REG)
1863 /* Modify the reg-rtx to contain the new hard reg
1864 number or else to contain its pseudo reg number. */
1865 REGNO (regno_reg_rtx[i])
1866 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1868 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1869 allocate a stack slot for it. */
1871 if (reg_renumber[i] < 0
1872 && REG_N_REFS (i) > 0
1873 && reg_equiv_constant[i] == 0
1874 && reg_equiv_memory_loc[i] == 0)
1877 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1878 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1881 /* Each pseudo reg has an inherent size which comes from its own mode,
1882 and a total size which provides room for paradoxical subregs
1883 which refer to the pseudo reg in wider modes.
1885 We can use a slot already allocated if it provides both
1886 enough inherent space and enough total space.
1887 Otherwise, we allocate a new slot, making sure that it has no less
1888 inherent space, and no less total space, then the previous slot. */
1891 /* No known place to spill from => no slot to reuse. */
1892 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1893 inherent_size == total_size ? 0 : -1);
1894 if (BYTES_BIG_ENDIAN)
1895 /* Cancel the big-endian correction done in assign_stack_local.
1896 Get the address of the beginning of the slot.
1897 This is so we can do a big-endian correction unconditionally
1899 adjust = inherent_size - total_size;
1901 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1903 /* Nothing can alias this slot except this pseudo. */
1904 MEM_ALIAS_SET (x) = new_alias_set ();
1907 /* Reuse a stack slot if possible. */
1908 else if (spill_stack_slot[from_reg] != 0
1909 && spill_stack_slot_width[from_reg] >= total_size
1910 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1912 x = spill_stack_slot[from_reg];
1914 /* Allocate a bigger slot. */
1917 /* Compute maximum size needed, both for inherent size
1918 and for total size. */
1919 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1922 if (spill_stack_slot[from_reg])
1924 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1926 mode = GET_MODE (spill_stack_slot[from_reg]);
1927 if (spill_stack_slot_width[from_reg] > total_size)
1928 total_size = spill_stack_slot_width[from_reg];
1931 /* Make a slot with that size. */
1932 x = assign_stack_local (mode, total_size,
1933 inherent_size == total_size ? 0 : -1);
1936 /* All pseudos mapped to this slot can alias each other. */
1937 if (spill_stack_slot[from_reg])
1938 MEM_ALIAS_SET (x) = MEM_ALIAS_SET (spill_stack_slot[from_reg]);
1940 MEM_ALIAS_SET (x) = new_alias_set ();
1942 if (BYTES_BIG_ENDIAN)
1944 /* Cancel the big-endian correction done in assign_stack_local.
1945 Get the address of the beginning of the slot.
1946 This is so we can do a big-endian correction unconditionally
1948 adjust = GET_MODE_SIZE (mode) - total_size;
1950 stack_slot = gen_rtx_MEM (mode_for_size (total_size
1953 plus_constant (XEXP (x, 0), adjust));
1956 spill_stack_slot[from_reg] = stack_slot;
1957 spill_stack_slot_width[from_reg] = total_size;
1960 /* On a big endian machine, the "address" of the slot
1961 is the address of the low part that fits its inherent mode. */
1962 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
1963 adjust += (total_size - inherent_size);
1965 /* If we have any adjustment to make, or if the stack slot is the
1966 wrong mode, make a new stack slot. */
1967 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
1969 rtx new = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
1970 plus_constant (XEXP (x, 0), adjust));
1972 MEM_COPY_ATTRIBUTES (new, x);
1976 /* Save the stack slot for later. */
1977 reg_equiv_memory_loc[i] = x;
1981 /* Mark the slots in regs_ever_live for the hard regs
1982 used by pseudo-reg number REGNO. */
1985 mark_home_live (regno)
1988 register int i, lim;
1990 i = reg_renumber[regno];
1993 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
1995 regs_ever_live[i++] = 1;
1998 /* This function handles the tracking of elimination offsets around branches.
2000 X is a piece of RTL being scanned.
2002 INSN is the insn that it came from, if any.
2004 INITIAL_P is non-zero if we are to set the offset to be the initial
2005 offset and zero if we are setting the offset of the label to be the
2009 set_label_offsets (x, insn, initial_p)
2014 enum rtx_code code = GET_CODE (x);
2017 struct elim_table *p;
2022 if (LABEL_REF_NONLOCAL_P (x))
2027 /* ... fall through ... */
2030 /* If we know nothing about this label, set the desired offsets. Note
2031 that this sets the offset at a label to be the offset before a label
2032 if we don't know anything about the label. This is not correct for
2033 the label after a BARRIER, but is the best guess we can make. If
2034 we guessed wrong, we will suppress an elimination that might have
2035 been possible had we been able to guess correctly. */
2037 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2039 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2040 offsets_at[CODE_LABEL_NUMBER (x)][i]
2041 = (initial_p ? reg_eliminate[i].initial_offset
2042 : reg_eliminate[i].offset);
2043 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2046 /* Otherwise, if this is the definition of a label and it is
2047 preceded by a BARRIER, set our offsets to the known offset of
2051 && (tem = prev_nonnote_insn (insn)) != 0
2052 && GET_CODE (tem) == BARRIER)
2053 set_offsets_for_label (insn);
2055 /* If neither of the above cases is true, compare each offset
2056 with those previously recorded and suppress any eliminations
2057 where the offsets disagree. */
2059 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2060 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2061 != (initial_p ? reg_eliminate[i].initial_offset
2062 : reg_eliminate[i].offset))
2063 reg_eliminate[i].can_eliminate = 0;
2068 set_label_offsets (PATTERN (insn), insn, initial_p);
2070 /* ... fall through ... */
2074 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2075 and hence must have all eliminations at their initial offsets. */
2076 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2077 if (REG_NOTE_KIND (tem) == REG_LABEL)
2078 set_label_offsets (XEXP (tem, 0), insn, 1);
2083 /* Each of the labels in the address vector must be at their initial
2084 offsets. We want the first field for ADDR_VEC and the second
2085 field for ADDR_DIFF_VEC. */
2087 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2088 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2093 /* We only care about setting PC. If the source is not RETURN,
2094 IF_THEN_ELSE, or a label, disable any eliminations not at
2095 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2096 isn't one of those possibilities. For branches to a label,
2097 call ourselves recursively.
2099 Note that this can disable elimination unnecessarily when we have
2100 a non-local goto since it will look like a non-constant jump to
2101 someplace in the current function. This isn't a significant
2102 problem since such jumps will normally be when all elimination
2103 pairs are back to their initial offsets. */
2105 if (SET_DEST (x) != pc_rtx)
2108 switch (GET_CODE (SET_SRC (x)))
2115 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2119 tem = XEXP (SET_SRC (x), 1);
2120 if (GET_CODE (tem) == LABEL_REF)
2121 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2122 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2125 tem = XEXP (SET_SRC (x), 2);
2126 if (GET_CODE (tem) == LABEL_REF)
2127 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2128 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2136 /* If we reach here, all eliminations must be at their initial
2137 offset because we are doing a jump to a variable address. */
2138 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2139 if (p->offset != p->initial_offset)
2140 p->can_eliminate = 0;
2148 /* Scan X and replace any eliminable registers (such as fp) with a
2149 replacement (such as sp), plus an offset.
2151 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2152 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2153 MEM, we are allowed to replace a sum of a register and the constant zero
2154 with the register, which we cannot do outside a MEM. In addition, we need
2155 to record the fact that a register is referenced outside a MEM.
2157 If INSN is an insn, it is the insn containing X. If we replace a REG
2158 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2159 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2160 the REG is being modified.
2162 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2163 That's used when we eliminate in expressions stored in notes.
2164 This means, do not set ref_outside_mem even if the reference
2167 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2168 replacements done assuming all offsets are at their initial values. If
2169 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2170 encounter, return the actual location so that find_reloads will do
2171 the proper thing. */
2174 eliminate_regs (x, mem_mode, insn)
2176 enum machine_mode mem_mode;
2179 enum rtx_code code = GET_CODE (x);
2180 struct elim_table *ep;
2187 if (! current_function_decl)
2206 /* This is only for the benefit of the debugging backends, which call
2207 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2208 removed after CSE. */
2209 new = eliminate_regs (XEXP (x, 0), 0, insn);
2210 if (GET_CODE (new) == MEM)
2211 return XEXP (new, 0);
2217 /* First handle the case where we encounter a bare register that
2218 is eliminable. Replace it with a PLUS. */
2219 if (regno < FIRST_PSEUDO_REGISTER)
2221 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2223 if (ep->from_rtx == x && ep->can_eliminate)
2224 return plus_constant (ep->to_rtx, ep->previous_offset);
2227 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2228 && reg_equiv_constant[regno]
2229 && ! CONSTANT_P (reg_equiv_constant[regno]))
2230 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2234 /* You might think handling MINUS in a manner similar to PLUS is a
2235 good idea. It is not. It has been tried multiple times and every
2236 time the change has had to have been reverted.
2238 Other parts of reload know a PLUS is special (gen_reload for example)
2239 and require special code to handle code a reloaded PLUS operand.
2241 Also consider backends where the flags register is clobbered by a
2242 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2243 lea instruction comes to mind). If we try to reload a MINUS, we
2244 may kill the flags register that was holding a useful value.
2246 So, please before trying to handle MINUS, consider reload as a
2247 whole instead of this little section as well as the backend issues. */
2249 /* If this is the sum of an eliminable register and a constant, rework
2251 if (GET_CODE (XEXP (x, 0)) == REG
2252 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2253 && CONSTANT_P (XEXP (x, 1)))
2255 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2257 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2259 /* The only time we want to replace a PLUS with a REG (this
2260 occurs when the constant operand of the PLUS is the negative
2261 of the offset) is when we are inside a MEM. We won't want
2262 to do so at other times because that would change the
2263 structure of the insn in a way that reload can't handle.
2264 We special-case the commonest situation in
2265 eliminate_regs_in_insn, so just replace a PLUS with a
2266 PLUS here, unless inside a MEM. */
2267 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2268 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2271 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2272 plus_constant (XEXP (x, 1),
2273 ep->previous_offset));
2276 /* If the register is not eliminable, we are done since the other
2277 operand is a constant. */
2281 /* If this is part of an address, we want to bring any constant to the
2282 outermost PLUS. We will do this by doing register replacement in
2283 our operands and seeing if a constant shows up in one of them.
2285 Note that there is no risk of modifying the structure of the insn,
2286 since we only get called for its operands, thus we are either
2287 modifying the address inside a MEM, or something like an address
2288 operand of a load-address insn. */
2291 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2292 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2294 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2296 /* If one side is a PLUS and the other side is a pseudo that
2297 didn't get a hard register but has a reg_equiv_constant,
2298 we must replace the constant here since it may no longer
2299 be in the position of any operand. */
2300 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2301 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2302 && reg_renumber[REGNO (new1)] < 0
2303 && reg_equiv_constant != 0
2304 && reg_equiv_constant[REGNO (new1)] != 0)
2305 new1 = reg_equiv_constant[REGNO (new1)];
2306 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2307 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2308 && reg_renumber[REGNO (new0)] < 0
2309 && reg_equiv_constant[REGNO (new0)] != 0)
2310 new0 = reg_equiv_constant[REGNO (new0)];
2312 new = form_sum (new0, new1);
2314 /* As above, if we are not inside a MEM we do not want to
2315 turn a PLUS into something else. We might try to do so here
2316 for an addition of 0 if we aren't optimizing. */
2317 if (! mem_mode && GET_CODE (new) != PLUS)
2318 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2326 /* If this is the product of an eliminable register and a
2327 constant, apply the distribute law and move the constant out
2328 so that we have (plus (mult ..) ..). This is needed in order
2329 to keep load-address insns valid. This case is pathological.
2330 We ignore the possibility of overflow here. */
2331 if (GET_CODE (XEXP (x, 0)) == REG
2332 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2333 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2334 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2336 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2339 /* Refs inside notes don't count for this purpose. */
2340 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2341 || GET_CODE (insn) == INSN_LIST)))
2342 ep->ref_outside_mem = 1;
2345 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2346 ep->previous_offset * INTVAL (XEXP (x, 1)));
2349 /* ... fall through ... */
2353 /* See comments before PLUS about handling MINUS. */
2355 case DIV: case UDIV:
2356 case MOD: case UMOD:
2357 case AND: case IOR: case XOR:
2358 case ROTATERT: case ROTATE:
2359 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2361 case GE: case GT: case GEU: case GTU:
2362 case LE: case LT: case LEU: case LTU:
2364 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2366 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2368 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2369 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2374 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2377 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2378 if (new != XEXP (x, 0))
2380 /* If this is a REG_DEAD note, it is not valid anymore.
2381 Using the eliminated version could result in creating a
2382 REG_DEAD note for the stack or frame pointer. */
2383 if (GET_MODE (x) == REG_DEAD)
2385 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2388 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2392 /* ... fall through ... */
2395 /* Now do eliminations in the rest of the chain. If this was
2396 an EXPR_LIST, this might result in allocating more memory than is
2397 strictly needed, but it simplifies the code. */
2400 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2401 if (new != XEXP (x, 1))
2402 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2410 case STRICT_LOW_PART:
2412 case SIGN_EXTEND: case ZERO_EXTEND:
2413 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2414 case FLOAT: case FIX:
2415 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2419 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2420 if (new != XEXP (x, 0))
2421 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2425 /* Similar to above processing, but preserve SUBREG_WORD.
2426 Convert (subreg (mem)) to (mem) if not paradoxical.
2427 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2428 pseudo didn't get a hard reg, we must replace this with the
2429 eliminated version of the memory location because push_reloads
2430 may do the replacement in certain circumstances. */
2431 if (GET_CODE (SUBREG_REG (x)) == REG
2432 && (GET_MODE_SIZE (GET_MODE (x))
2433 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2434 && reg_equiv_memory_loc != 0
2435 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2437 new = SUBREG_REG (x);
2440 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2442 if (new != XEXP (x, 0))
2444 int x_size = GET_MODE_SIZE (GET_MODE (x));
2445 int new_size = GET_MODE_SIZE (GET_MODE (new));
2447 if (GET_CODE (new) == MEM
2448 && ((x_size < new_size
2449 #ifdef WORD_REGISTER_OPERATIONS
2450 /* On these machines, combine can create rtl of the form
2451 (set (subreg:m1 (reg:m2 R) 0) ...)
2452 where m1 < m2, and expects something interesting to
2453 happen to the entire word. Moreover, it will use the
2454 (reg:m2 R) later, expecting all bits to be preserved.
2455 So if the number of words is the same, preserve the
2456 subreg so that push_reloads can see it. */
2457 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
2460 || (x_size == new_size))
2463 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2464 enum machine_mode mode = GET_MODE (x);
2466 if (BYTES_BIG_ENDIAN)
2467 offset += (MIN (UNITS_PER_WORD,
2468 GET_MODE_SIZE (GET_MODE (new)))
2469 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2471 PUT_MODE (new, mode);
2472 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2476 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
2482 /* This is only for the benefit of the debugging backends, which call
2483 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2484 removed after CSE. */
2485 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2486 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2488 /* Our only special processing is to pass the mode of the MEM to our
2489 recursive call and copy the flags. While we are here, handle this
2490 case more efficiently. */
2491 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
2492 if (new != XEXP (x, 0))
2494 new = gen_rtx_MEM (GET_MODE (x), new);
2495 MEM_COPY_ATTRIBUTES (new, x);
2511 /* Process each of our operands recursively. If any have changed, make a
2513 fmt = GET_RTX_FORMAT (code);
2514 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2518 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2519 if (new != XEXP (x, i) && ! copied)
2521 rtx new_x = rtx_alloc (code);
2522 bcopy ((char *) x, (char *) new_x,
2523 (sizeof (*new_x) - sizeof (new_x->fld)
2524 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2530 else if (*fmt == 'E')
2533 for (j = 0; j < XVECLEN (x, i); j++)
2535 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2536 if (new != XVECEXP (x, i, j) && ! copied_vec)
2538 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2542 rtx new_x = rtx_alloc (code);
2543 bcopy ((char *) x, (char *) new_x,
2544 (sizeof (*new_x) - sizeof (new_x->fld)
2545 + (sizeof (new_x->fld[0])
2546 * GET_RTX_LENGTH (code))));
2550 XVEC (x, i) = new_v;
2553 XVECEXP (x, i, j) = new;
2561 /* Scan rtx X for modifications of elimination target registers. Update
2562 the table of eliminables to reflect the changed state. MEM_MODE is
2563 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2566 elimination_effects (x, mem_mode)
2568 enum machine_mode mem_mode;
2571 enum rtx_code code = GET_CODE (x);
2572 struct elim_table *ep;
2598 /* First handle the case where we encounter a bare register that
2599 is eliminable. Replace it with a PLUS. */
2600 if (regno < FIRST_PSEUDO_REGISTER)
2602 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2604 if (ep->from_rtx == x && ep->can_eliminate)
2607 ep->ref_outside_mem = 1;
2612 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2613 && reg_equiv_constant[regno]
2614 && ! CONSTANT_P (reg_equiv_constant[regno]))
2615 elimination_effects (reg_equiv_constant[regno], mem_mode);
2624 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2625 if (ep->to_rtx == XEXP (x, 0))
2627 int size = GET_MODE_SIZE (mem_mode);
2629 /* If more bytes than MEM_MODE are pushed, account for them. */
2630 #ifdef PUSH_ROUNDING
2631 if (ep->to_rtx == stack_pointer_rtx)
2632 size = PUSH_ROUNDING (size);
2634 if (code == PRE_DEC || code == POST_DEC)
2636 else if (code == PRE_INC || code == POST_INC)
2638 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2639 && GET_CODE (XEXP (x, 1)) == PLUS
2640 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2641 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2642 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2645 /* These two aren't unary operators. */
2646 if (code == POST_MODIFY || code == PRE_MODIFY)
2649 /* Fall through to generic unary operation case. */
2650 case STRICT_LOW_PART:
2652 case SIGN_EXTEND: case ZERO_EXTEND:
2653 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2654 case FLOAT: case FIX:
2655 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2659 elimination_effects (XEXP (x, 0), mem_mode);
2663 if (GET_CODE (SUBREG_REG (x)) == REG
2664 && (GET_MODE_SIZE (GET_MODE (x))
2665 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2666 && reg_equiv_memory_loc != 0
2667 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2670 elimination_effects (SUBREG_REG (x), mem_mode);
2674 /* If using a register that is the source of an eliminate we still
2675 think can be performed, note it cannot be performed since we don't
2676 know how this register is used. */
2677 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2678 if (ep->from_rtx == XEXP (x, 0))
2679 ep->can_eliminate = 0;
2681 elimination_effects (XEXP (x, 0), mem_mode);
2685 /* If clobbering a register that is the replacement register for an
2686 elimination we still think can be performed, note that it cannot
2687 be performed. Otherwise, we need not be concerned about it. */
2688 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2689 if (ep->to_rtx == XEXP (x, 0))
2690 ep->can_eliminate = 0;
2692 elimination_effects (XEXP (x, 0), mem_mode);
2696 /* Check for setting a register that we know about. */
2697 if (GET_CODE (SET_DEST (x)) == REG)
2699 /* See if this is setting the replacement register for an
2702 If DEST is the hard frame pointer, we do nothing because we
2703 assume that all assignments to the frame pointer are for
2704 non-local gotos and are being done at a time when they are valid
2705 and do not disturb anything else. Some machines want to
2706 eliminate a fake argument pointer (or even a fake frame pointer)
2707 with either the real frame or the stack pointer. Assignments to
2708 the hard frame pointer must not prevent this elimination. */
2710 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2712 if (ep->to_rtx == SET_DEST (x)
2713 && SET_DEST (x) != hard_frame_pointer_rtx)
2715 /* If it is being incremented, adjust the offset. Otherwise,
2716 this elimination can't be done. */
2717 rtx src = SET_SRC (x);
2719 if (GET_CODE (src) == PLUS
2720 && XEXP (src, 0) == SET_DEST (x)
2721 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2722 ep->offset -= INTVAL (XEXP (src, 1));
2724 ep->can_eliminate = 0;
2728 elimination_effects (SET_DEST (x), 0);
2729 elimination_effects (SET_SRC (x), 0);
2733 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2736 /* Our only special processing is to pass the mode of the MEM to our
2738 elimination_effects (XEXP (x, 0), GET_MODE (x));
2745 fmt = GET_RTX_FORMAT (code);
2746 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2749 elimination_effects (XEXP (x, i), mem_mode);
2750 else if (*fmt == 'E')
2751 for (j = 0; j < XVECLEN (x, i); j++)
2752 elimination_effects (XVECEXP (x, i, j), mem_mode);
2756 /* Descend through rtx X and verify that no references to eliminable registers
2757 remain. If any do remain, mark the involved register as not
2761 check_eliminable_occurrences (x)
2771 code = GET_CODE (x);
2773 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2775 struct elim_table *ep;
2777 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2778 if (ep->from_rtx == x && ep->can_eliminate)
2779 ep->can_eliminate = 0;
2783 fmt = GET_RTX_FORMAT (code);
2784 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2787 check_eliminable_occurrences (XEXP (x, i));
2788 else if (*fmt == 'E')
2791 for (j = 0; j < XVECLEN (x, i); j++)
2792 check_eliminable_occurrences (XVECEXP (x, i, j));
2797 /* Scan INSN and eliminate all eliminable registers in it.
2799 If REPLACE is nonzero, do the replacement destructively. Also
2800 delete the insn as dead it if it is setting an eliminable register.
2802 If REPLACE is zero, do all our allocations in reload_obstack.
2804 If no eliminations were done and this insn doesn't require any elimination
2805 processing (these are not identical conditions: it might be updating sp,
2806 but not referencing fp; this needs to be seen during reload_as_needed so
2807 that the offset between fp and sp can be taken into consideration), zero
2808 is returned. Otherwise, 1 is returned. */
2811 eliminate_regs_in_insn (insn, replace)
2815 int icode = recog_memoized (insn);
2816 rtx old_body = PATTERN (insn);
2817 int insn_is_asm = asm_noperands (old_body) >= 0;
2818 rtx old_set = single_set (insn);
2822 rtx substed_operand[MAX_RECOG_OPERANDS];
2823 rtx orig_operand[MAX_RECOG_OPERANDS];
2824 struct elim_table *ep;
2826 if (! insn_is_asm && icode < 0)
2828 if (GET_CODE (PATTERN (insn)) == USE
2829 || GET_CODE (PATTERN (insn)) == CLOBBER
2830 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2831 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2832 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2838 push_obstacks (&reload_obstack, &reload_obstack);
2840 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2841 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2843 /* Check for setting an eliminable register. */
2844 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2845 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2847 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2848 /* If this is setting the frame pointer register to the
2849 hardware frame pointer register and this is an elimination
2850 that will be done (tested above), this insn is really
2851 adjusting the frame pointer downward to compensate for
2852 the adjustment done before a nonlocal goto. */
2853 if (ep->from == FRAME_POINTER_REGNUM
2854 && ep->to == HARD_FRAME_POINTER_REGNUM)
2856 rtx src = SET_SRC (old_set);
2857 int offset = 0, ok = 0;
2858 rtx prev_insn, prev_set;
2860 if (src == ep->to_rtx)
2862 else if (GET_CODE (src) == PLUS
2863 && GET_CODE (XEXP (src, 0)) == CONST_INT
2864 && XEXP (src, 1) == ep->to_rtx)
2865 offset = INTVAL (XEXP (src, 0)), ok = 1;
2866 else if (GET_CODE (src) == PLUS
2867 && GET_CODE (XEXP (src, 1)) == CONST_INT
2868 && XEXP (src, 0) == ep->to_rtx)
2869 offset = INTVAL (XEXP (src, 1)), ok = 1;
2870 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
2871 && (prev_set = single_set (prev_insn)) != 0
2872 && rtx_equal_p (SET_DEST (prev_set), src))
2874 src = SET_SRC (prev_set);
2875 if (src == ep->to_rtx)
2877 else if (GET_CODE (src) == PLUS
2878 && GET_CODE (XEXP (src, 0)) == CONST_INT
2879 && XEXP (src, 1) == ep->to_rtx)
2880 offset = INTVAL (XEXP (src, 0)), ok = 1;
2881 else if (GET_CODE (src) == PLUS
2882 && GET_CODE (XEXP (src, 1)) == CONST_INT
2883 && XEXP (src, 0) == ep->to_rtx)
2884 offset = INTVAL (XEXP (src, 1)), ok = 1;
2892 = plus_constant (ep->to_rtx, offset - ep->offset);
2894 /* First see if this insn remains valid when we
2895 make the change. If not, keep the INSN_CODE
2896 the same and let reload fit it up. */
2897 validate_change (insn, &SET_SRC (old_set), src, 1);
2898 validate_change (insn, &SET_DEST (old_set),
2900 if (! apply_change_group ())
2902 SET_SRC (old_set) = src;
2903 SET_DEST (old_set) = ep->to_rtx;
2913 /* In this case this insn isn't serving a useful purpose. We
2914 will delete it in reload_as_needed once we know that this
2915 elimination is, in fact, being done.
2917 If REPLACE isn't set, we can't delete this insn, but needn't
2918 process it since it won't be used unless something changes. */
2921 delete_dead_insn (insn);
2929 /* We allow one special case which happens to work on all machines we
2930 currently support: a single set with the source being a PLUS of an
2931 eliminable register and a constant. */
2933 && GET_CODE (SET_SRC (old_set)) == PLUS
2934 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
2935 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
2936 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
2938 rtx reg = XEXP (SET_SRC (old_set), 0);
2939 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
2941 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2942 if (ep->from_rtx == reg && ep->can_eliminate)
2944 offset += ep->offset;
2948 /* We assume here that we don't need a PARALLEL of
2949 any CLOBBERs for this assignment. There's not
2950 much we can do if we do need it. */
2951 PATTERN (insn) = gen_rtx_SET (VOIDmode,
2954 INSN_CODE (insn) = recog (PATTERN (insn), insn, 0);
2955 if (INSN_CODE (insn) < 0)
2960 new_body = old_body;
2963 new_body = copy_insn (old_body);
2964 if (REG_NOTES (insn))
2965 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2967 PATTERN (insn) = new_body;
2968 old_set = single_set (insn);
2970 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
2971 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
2974 /* This can't have an effect on elimination offsets, so skip right
2980 /* Determine the effects of this insn on elimination offsets. */
2981 elimination_effects (old_body, 0);
2983 /* Eliminate all eliminable registers occurring in operands that
2984 can be handled by reload. */
2985 extract_insn (insn);
2987 for (i = 0; i < recog_data.n_operands; i++)
2989 orig_operand[i] = recog_data.operand[i];
2990 substed_operand[i] = recog_data.operand[i];
2992 /* For an asm statement, every operand is eliminable. */
2993 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
2995 /* Check for setting a register that we know about. */
2996 if (recog_data.operand_type[i] != OP_IN
2997 && GET_CODE (orig_operand[i]) == REG)
2999 /* If we are assigning to a register that can be eliminated, it
3000 must be as part of a PARALLEL, since the code above handles
3001 single SETs. We must indicate that we can no longer
3002 eliminate this reg. */
3003 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3005 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3006 ep->can_eliminate = 0;
3009 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3010 replace ? insn : NULL_RTX);
3011 if (substed_operand[i] != orig_operand[i])
3012 val = any_changes = 1;
3013 /* Terminate the search in check_eliminable_occurrences at
3015 *recog_data.operand_loc[i] = 0;
3017 /* If an output operand changed from a REG to a MEM and INSN is an
3018 insn, write a CLOBBER insn. */
3019 if (recog_data.operand_type[i] != OP_IN
3020 && GET_CODE (orig_operand[i]) == REG
3021 && GET_CODE (substed_operand[i]) == MEM
3023 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3028 for (i = 0; i < recog_data.n_dups; i++)
3029 *recog_data.dup_loc[i]
3030 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3032 /* If any eliminable remain, they aren't eliminable anymore. */
3033 check_eliminable_occurrences (old_body);
3035 /* Substitute the operands; the new values are in the substed_operand
3037 for (i = 0; i < recog_data.n_operands; i++)
3038 *recog_data.operand_loc[i] = substed_operand[i];
3039 for (i = 0; i < recog_data.n_dups; i++)
3040 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3042 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3043 re-recognize the insn. We do this in case we had a simple addition
3044 but now can do this as a load-address. This saves an insn in this
3046 If re-recognition fails, the old insn code number will still be used,
3047 and some register operands may have changed into PLUS expressions.
3048 These will be handled by find_reloads by loading them into a register
3053 /* If we aren't replacing things permanently and we changed something,
3054 make another copy to ensure that all the RTL is new. Otherwise
3055 things can go wrong if find_reload swaps commutative operands
3056 and one is inside RTL that has been copied while the other is not. */
3057 new_body = old_body;
3060 new_body = copy_insn (old_body);
3061 if (REG_NOTES (insn))
3062 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3064 PATTERN (insn) = new_body;
3066 /* If we had a move insn but now we don't, rerecognize it. This will
3067 cause spurious re-recognition if the old move had a PARALLEL since
3068 the new one still will, but we can't call single_set without
3069 having put NEW_BODY into the insn and the re-recognition won't
3070 hurt in this rare case. */
3071 /* ??? Why this huge if statement - why don't we just rerecognize the
3075 && ((GET_CODE (SET_SRC (old_set)) == REG
3076 && (GET_CODE (new_body) != SET
3077 || GET_CODE (SET_SRC (new_body)) != REG))
3078 /* If this was a load from or store to memory, compare
3079 the MEM in recog_data.operand to the one in the insn.
3080 If they are not equal, then rerecognize the insn. */
3082 && ((GET_CODE (SET_SRC (old_set)) == MEM
3083 && SET_SRC (old_set) != recog_data.operand[1])
3084 || (GET_CODE (SET_DEST (old_set)) == MEM
3085 && SET_DEST (old_set) != recog_data.operand[0])))
3086 /* If this was an add insn before, rerecognize. */
3087 || GET_CODE (SET_SRC (old_set)) == PLUS))
3089 int new_icode = recog (PATTERN (insn), insn, 0);
3091 INSN_CODE (insn) = icode;
3095 /* Restore the old body. If there were any changes to it, we made a copy
3096 of it while the changes were still in place, so we'll correctly return
3097 a modified insn below. */
3100 /* Restore the old body. */
3101 for (i = 0; i < recog_data.n_operands; i++)
3102 *recog_data.operand_loc[i] = orig_operand[i];
3103 for (i = 0; i < recog_data.n_dups; i++)
3104 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3107 /* Update all elimination pairs to reflect the status after the current
3108 insn. The changes we make were determined by the earlier call to
3109 elimination_effects.
3111 We also detect a cases where register elimination cannot be done,
3112 namely, if a register would be both changed and referenced outside a MEM
3113 in the resulting insn since such an insn is often undefined and, even if
3114 not, we cannot know what meaning will be given to it. Note that it is
3115 valid to have a register used in an address in an insn that changes it
3116 (presumably with a pre- or post-increment or decrement).
3118 If anything changes, return nonzero. */
3120 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3122 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3123 ep->can_eliminate = 0;
3125 ep->ref_outside_mem = 0;
3127 if (ep->previous_offset != ep->offset)
3132 /* If we changed something, perform elimination in REG_NOTES. This is
3133 needed even when REPLACE is zero because a REG_DEAD note might refer
3134 to a register that we eliminate and could cause a different number
3135 of spill registers to be needed in the final reload pass than in
3137 if (val && REG_NOTES (insn) != 0)
3138 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3146 /* Loop through all elimination pairs.
3147 Recalculate the number not at initial offset.
3149 Compute the maximum offset (minimum offset if the stack does not
3150 grow downward) for each elimination pair. */
3153 update_eliminable_offsets ()
3155 struct elim_table *ep;
3157 num_not_at_initial_offset = 0;
3158 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3160 ep->previous_offset = ep->offset;
3161 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3162 num_not_at_initial_offset++;
3166 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3167 replacement we currently believe is valid, mark it as not eliminable if X
3168 modifies DEST in any way other than by adding a constant integer to it.
3170 If DEST is the frame pointer, we do nothing because we assume that
3171 all assignments to the hard frame pointer are nonlocal gotos and are being
3172 done at a time when they are valid and do not disturb anything else.
3173 Some machines want to eliminate a fake argument pointer with either the
3174 frame or stack pointer. Assignments to the hard frame pointer must not
3175 prevent this elimination.
3177 Called via note_stores from reload before starting its passes to scan
3178 the insns of the function. */
3181 mark_not_eliminable (dest, x, data)
3184 void *data ATTRIBUTE_UNUSED;
3186 register unsigned int i;
3188 /* A SUBREG of a hard register here is just changing its mode. We should
3189 not see a SUBREG of an eliminable hard register, but check just in
3191 if (GET_CODE (dest) == SUBREG)
3192 dest = SUBREG_REG (dest);
3194 if (dest == hard_frame_pointer_rtx)
3197 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3198 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3199 && (GET_CODE (x) != SET
3200 || GET_CODE (SET_SRC (x)) != PLUS
3201 || XEXP (SET_SRC (x), 0) != dest
3202 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3204 reg_eliminate[i].can_eliminate_previous
3205 = reg_eliminate[i].can_eliminate = 0;
3210 /* Verify that the initial elimination offsets did not change since the
3211 last call to set_initial_elim_offsets. This is used to catch cases
3212 where something illegal happened during reload_as_needed that could
3213 cause incorrect code to be generated if we did not check for it. */
3216 verify_initial_elim_offsets ()
3220 #ifdef ELIMINABLE_REGS
3221 struct elim_table *ep;
3223 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3225 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3226 if (t != ep->initial_offset)
3230 INITIAL_FRAME_POINTER_OFFSET (t);
3231 if (t != reg_eliminate[0].initial_offset)
3236 /* Reset all offsets on eliminable registers to their initial values. */
3239 set_initial_elim_offsets ()
3241 struct elim_table *ep = reg_eliminate;
3243 #ifdef ELIMINABLE_REGS
3244 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3246 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3247 ep->previous_offset = ep->offset = ep->initial_offset;
3250 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3251 ep->previous_offset = ep->offset = ep->initial_offset;
3254 num_not_at_initial_offset = 0;
3257 /* Initialize the known label offsets.
3258 Set a known offset for each forced label to be at the initial offset
3259 of each elimination. We do this because we assume that all
3260 computed jumps occur from a location where each elimination is
3261 at its initial offset.
3262 For all other labels, show that we don't know the offsets. */
3265 set_initial_label_offsets ()
3268 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
3270 for (x = forced_labels; x; x = XEXP (x, 1))
3272 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3275 /* Set all elimination offsets to the known values for the code label given
3279 set_offsets_for_label (insn)
3283 int label_nr = CODE_LABEL_NUMBER (insn);
3284 struct elim_table *ep;
3286 num_not_at_initial_offset = 0;
3287 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3289 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3290 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3291 num_not_at_initial_offset++;
3295 /* See if anything that happened changes which eliminations are valid.
3296 For example, on the Sparc, whether or not the frame pointer can
3297 be eliminated can depend on what registers have been used. We need
3298 not check some conditions again (such as flag_omit_frame_pointer)
3299 since they can't have changed. */
3302 update_eliminables (pset)
3305 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3306 int previous_frame_pointer_needed = frame_pointer_needed;
3308 struct elim_table *ep;
3310 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3311 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3312 #ifdef ELIMINABLE_REGS
3313 || ! CAN_ELIMINATE (ep->from, ep->to)
3316 ep->can_eliminate = 0;
3318 /* Look for the case where we have discovered that we can't replace
3319 register A with register B and that means that we will now be
3320 trying to replace register A with register C. This means we can
3321 no longer replace register C with register B and we need to disable
3322 such an elimination, if it exists. This occurs often with A == ap,
3323 B == sp, and C == fp. */
3325 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3327 struct elim_table *op;
3328 register int new_to = -1;
3330 if (! ep->can_eliminate && ep->can_eliminate_previous)
3332 /* Find the current elimination for ep->from, if there is a
3334 for (op = reg_eliminate;
3335 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3336 if (op->from == ep->from && op->can_eliminate)
3342 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3344 for (op = reg_eliminate;
3345 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3346 if (op->from == new_to && op->to == ep->to)
3347 op->can_eliminate = 0;
3351 /* See if any registers that we thought we could eliminate the previous
3352 time are no longer eliminable. If so, something has changed and we
3353 must spill the register. Also, recompute the number of eliminable
3354 registers and see if the frame pointer is needed; it is if there is
3355 no elimination of the frame pointer that we can perform. */
3357 frame_pointer_needed = 1;
3358 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3360 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3361 && ep->to != HARD_FRAME_POINTER_REGNUM)
3362 frame_pointer_needed = 0;
3364 if (! ep->can_eliminate && ep->can_eliminate_previous)
3366 ep->can_eliminate_previous = 0;
3367 SET_HARD_REG_BIT (*pset, ep->from);
3372 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3373 /* If we didn't need a frame pointer last time, but we do now, spill
3374 the hard frame pointer. */
3375 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3376 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3380 /* Initialize the table of registers to eliminate. */
3385 struct elim_table *ep;
3386 #ifdef ELIMINABLE_REGS
3387 struct elim_table_1 *ep1;
3391 reg_eliminate = (struct elim_table *)
3392 xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3394 /* Does this function require a frame pointer? */
3396 frame_pointer_needed = (! flag_omit_frame_pointer
3397 #ifdef EXIT_IGNORE_STACK
3398 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3399 and restore sp for alloca. So we can't eliminate
3400 the frame pointer in that case. At some point,
3401 we should improve this by emitting the
3402 sp-adjusting insns for this case. */
3403 || (current_function_calls_alloca
3404 && EXIT_IGNORE_STACK)
3406 || FRAME_POINTER_REQUIRED);
3410 #ifdef ELIMINABLE_REGS
3411 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3412 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3414 ep->from = ep1->from;
3416 ep->can_eliminate = ep->can_eliminate_previous
3417 = (CAN_ELIMINATE (ep->from, ep->to)
3418 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3421 reg_eliminate[0].from = reg_eliminate_1[0].from;
3422 reg_eliminate[0].to = reg_eliminate_1[0].to;
3423 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3424 = ! frame_pointer_needed;
3427 /* Count the number of eliminable registers and build the FROM and TO
3428 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3429 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3430 We depend on this. */
3431 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3433 num_eliminable += ep->can_eliminate;
3434 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3435 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3439 /* Kick all pseudos out of hard register REGNO.
3441 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3442 because we found we can't eliminate some register. In the case, no pseudos
3443 are allowed to be in the register, even if they are only in a block that
3444 doesn't require spill registers, unlike the case when we are spilling this
3445 hard reg to produce another spill register.
3447 Return nonzero if any pseudos needed to be kicked out. */
3450 spill_hard_reg (regno, cant_eliminate)
3458 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3459 regs_ever_live[regno] = 1;
3462 /* Spill every pseudo reg that was allocated to this reg
3463 or to something that overlaps this reg. */
3465 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3466 if (reg_renumber[i] >= 0
3467 && (unsigned int) reg_renumber[i] <= regno
3468 && ((unsigned int) reg_renumber[i]
3469 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3470 PSEUDO_REGNO_MODE (i))
3472 SET_REGNO_REG_SET (&spilled_pseudos, i);
3475 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3476 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3479 ior_hard_reg_set (set1, set2)
3480 HARD_REG_SET *set1, *set2;
3482 IOR_HARD_REG_SET (*set1, *set2);
3485 /* After find_reload_regs has been run for all insn that need reloads,
3486 and/or spill_hard_regs was called, this function is used to actually
3487 spill pseudo registers and try to reallocate them. It also sets up the
3488 spill_regs array for use by choose_reload_regs. */
3491 finish_spills (global)
3494 struct insn_chain *chain;
3495 int something_changed = 0;
3498 /* Build the spill_regs array for the function. */
3499 /* If there are some registers still to eliminate and one of the spill regs
3500 wasn't ever used before, additional stack space may have to be
3501 allocated to store this register. Thus, we may have changed the offset
3502 between the stack and frame pointers, so mark that something has changed.
3504 One might think that we need only set VAL to 1 if this is a call-used
3505 register. However, the set of registers that must be saved by the
3506 prologue is not identical to the call-used set. For example, the
3507 register used by the call insn for the return PC is a call-used register,
3508 but must be saved by the prologue. */
3511 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3512 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3514 spill_reg_order[i] = n_spills;
3515 spill_regs[n_spills++] = i;
3516 if (num_eliminable && ! regs_ever_live[i])
3517 something_changed = 1;
3518 regs_ever_live[i] = 1;
3521 spill_reg_order[i] = -1;
3523 EXECUTE_IF_SET_IN_REG_SET
3524 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3526 /* Record the current hard register the pseudo is allocated to in
3527 pseudo_previous_regs so we avoid reallocating it to the same
3528 hard reg in a later pass. */
3529 if (reg_renumber[i] < 0)
3532 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3533 /* Mark it as no longer having a hard register home. */
3534 reg_renumber[i] = -1;
3535 /* We will need to scan everything again. */
3536 something_changed = 1;
3539 /* Retry global register allocation if possible. */
3542 bzero ((char *) pseudo_forbidden_regs, max_regno * sizeof (HARD_REG_SET));
3543 /* For every insn that needs reloads, set the registers used as spill
3544 regs in pseudo_forbidden_regs for every pseudo live across the
3546 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3548 EXECUTE_IF_SET_IN_REG_SET
3549 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3551 ior_hard_reg_set (pseudo_forbidden_regs + i,
3552 &chain->used_spill_regs);
3554 EXECUTE_IF_SET_IN_REG_SET
3555 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3557 ior_hard_reg_set (pseudo_forbidden_regs + i,
3558 &chain->used_spill_regs);
3562 /* Retry allocating the spilled pseudos. For each reg, merge the
3563 various reg sets that indicate which hard regs can't be used,
3564 and call retry_global_alloc.
3565 We change spill_pseudos here to only contain pseudos that did not
3566 get a new hard register. */
3567 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3568 if (reg_old_renumber[i] != reg_renumber[i])
3570 HARD_REG_SET forbidden;
3571 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3572 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3573 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3574 retry_global_alloc (i, forbidden);
3575 if (reg_renumber[i] >= 0)
3576 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3580 /* Fix up the register information in the insn chain.
3581 This involves deleting those of the spilled pseudos which did not get
3582 a new hard register home from the live_{before,after} sets. */
3583 for (chain = reload_insn_chain; chain; chain = chain->next)
3585 HARD_REG_SET used_by_pseudos;
3586 HARD_REG_SET used_by_pseudos2;
3588 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3589 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3591 /* Mark any unallocated hard regs as available for spills. That
3592 makes inheritance work somewhat better. */
3593 if (chain->need_reload)
3595 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3596 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3597 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3599 /* Save the old value for the sanity test below. */
3600 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3602 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3603 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3604 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3605 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3607 /* Make sure we only enlarge the set. */
3608 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3614 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3615 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3617 int regno = reg_renumber[i];
3618 if (reg_old_renumber[i] == regno)
3621 alter_reg (i, reg_old_renumber[i]);
3622 reg_old_renumber[i] = regno;
3626 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3628 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3629 i, reg_renumber[i]);
3633 return something_changed;
3636 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3637 Also mark any hard registers used to store user variables as
3638 forbidden from being used for spill registers. */
3641 scan_paradoxical_subregs (x)
3645 register const char *fmt;
3646 register enum rtx_code code = GET_CODE (x);
3652 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3653 && REG_USERVAR_P (x))
3654 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3670 if (GET_CODE (SUBREG_REG (x)) == REG
3671 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3672 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3673 = GET_MODE_SIZE (GET_MODE (x));
3680 fmt = GET_RTX_FORMAT (code);
3681 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3684 scan_paradoxical_subregs (XEXP (x, i));
3685 else if (fmt[i] == 'E')
3688 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3689 scan_paradoxical_subregs (XVECEXP (x, i, j));
3694 /* Reload pseudo-registers into hard regs around each insn as needed.
3695 Additional register load insns are output before the insn that needs it
3696 and perhaps store insns after insns that modify the reloaded pseudo reg.
3698 reg_last_reload_reg and reg_reloaded_contents keep track of
3699 which registers are already available in reload registers.
3700 We update these for the reloads that we perform,
3701 as the insns are scanned. */
3704 reload_as_needed (live_known)
3707 struct insn_chain *chain;
3708 #if defined (AUTO_INC_DEC)
3713 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
3714 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
3715 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3716 reg_has_output_reload = (char *) xmalloc (max_regno);
3717 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3719 set_initial_elim_offsets ();
3721 for (chain = reload_insn_chain; chain; chain = chain->next)
3724 rtx insn = chain->insn;
3725 rtx old_next = NEXT_INSN (insn);
3727 /* If we pass a label, copy the offsets from the label information
3728 into the current offsets of each elimination. */
3729 if (GET_CODE (insn) == CODE_LABEL)
3730 set_offsets_for_label (insn);
3732 else if (INSN_P (insn))
3734 rtx oldpat = PATTERN (insn);
3736 /* If this is a USE and CLOBBER of a MEM, ensure that any
3737 references to eliminable registers have been removed. */
3739 if ((GET_CODE (PATTERN (insn)) == USE
3740 || GET_CODE (PATTERN (insn)) == CLOBBER)
3741 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3742 XEXP (XEXP (PATTERN (insn), 0), 0)
3743 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3744 GET_MODE (XEXP (PATTERN (insn), 0)),
3747 /* If we need to do register elimination processing, do so.
3748 This might delete the insn, in which case we are done. */
3749 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3751 eliminate_regs_in_insn (insn, 1);
3752 if (GET_CODE (insn) == NOTE)
3754 update_eliminable_offsets ();
3759 /* If need_elim is nonzero but need_reload is zero, one might think
3760 that we could simply set n_reloads to 0. However, find_reloads
3761 could have done some manipulation of the insn (such as swapping
3762 commutative operands), and these manipulations are lost during
3763 the first pass for every insn that needs register elimination.
3764 So the actions of find_reloads must be redone here. */
3766 if (! chain->need_elim && ! chain->need_reload
3767 && ! chain->need_operand_change)
3769 /* First find the pseudo regs that must be reloaded for this insn.
3770 This info is returned in the tables reload_... (see reload.h).
3771 Also modify the body of INSN by substituting RELOAD
3772 rtx's for those pseudo regs. */
3775 bzero (reg_has_output_reload, max_regno);
3776 CLEAR_HARD_REG_SET (reg_is_output_reload);
3778 find_reloads (insn, 1, spill_indirect_levels, live_known,
3782 if (num_eliminable && chain->need_elim)
3783 update_eliminable_offsets ();
3787 rtx next = NEXT_INSN (insn);
3790 prev = PREV_INSN (insn);
3792 /* Now compute which reload regs to reload them into. Perhaps
3793 reusing reload regs from previous insns, or else output
3794 load insns to reload them. Maybe output store insns too.
3795 Record the choices of reload reg in reload_reg_rtx. */
3796 choose_reload_regs (chain);
3798 /* Merge any reloads that we didn't combine for fear of
3799 increasing the number of spill registers needed but now
3800 discover can be safely merged. */
3801 if (SMALL_REGISTER_CLASSES)
3802 merge_assigned_reloads (insn);
3804 /* Generate the insns to reload operands into or out of
3805 their reload regs. */
3806 emit_reload_insns (chain);
3808 /* Substitute the chosen reload regs from reload_reg_rtx
3809 into the insn's body (or perhaps into the bodies of other
3810 load and store insn that we just made for reloading
3811 and that we moved the structure into). */
3814 /* If this was an ASM, make sure that all the reload insns
3815 we have generated are valid. If not, give an error
3818 if (asm_noperands (PATTERN (insn)) >= 0)
3819 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3820 if (p != insn && INSN_P (p)
3821 && (recog_memoized (p) < 0
3822 || (extract_insn (p), ! constrain_operands (1))))
3824 error_for_asm (insn,
3825 "`asm' operand requires impossible reload");
3827 NOTE_SOURCE_FILE (p) = 0;
3828 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3831 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3832 is no longer validly lying around to save a future reload.
3833 Note that this does not detect pseudos that were reloaded
3834 for this insn in order to be stored in
3835 (obeying register constraints). That is correct; such reload
3836 registers ARE still valid. */
3837 note_stores (oldpat, forget_old_reloads_1, NULL);
3839 /* There may have been CLOBBER insns placed after INSN. So scan
3840 between INSN and NEXT and use them to forget old reloads. */
3841 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3842 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3843 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3846 /* Likewise for regs altered by auto-increment in this insn.
3847 REG_INC notes have been changed by reloading:
3848 find_reloads_address_1 records substitutions for them,
3849 which have been performed by subst_reloads above. */
3850 for (i = n_reloads - 1; i >= 0; i--)
3852 rtx in_reg = rld[i].in_reg;
3855 enum rtx_code code = GET_CODE (in_reg);
3856 /* PRE_INC / PRE_DEC will have the reload register ending up
3857 with the same value as the stack slot, but that doesn't
3858 hold true for POST_INC / POST_DEC. Either we have to
3859 convert the memory access to a true POST_INC / POST_DEC,
3860 or we can't use the reload register for inheritance. */
3861 if ((code == POST_INC || code == POST_DEC)
3862 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3863 REGNO (rld[i].reg_rtx))
3864 /* Make sure it is the inc/dec pseudo, and not
3865 some other (e.g. output operand) pseudo. */
3866 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3867 == REGNO (XEXP (in_reg, 0))))
3870 rtx reload_reg = rld[i].reg_rtx;
3871 enum machine_mode mode = GET_MODE (reload_reg);
3875 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3877 /* We really want to ignore REG_INC notes here, so
3878 use PATTERN (p) as argument to reg_set_p . */
3879 if (reg_set_p (reload_reg, PATTERN (p)))
3881 n = count_occurrences (PATTERN (p), reload_reg, 0);
3886 n = validate_replace_rtx (reload_reg,
3887 gen_rtx (code, mode,
3891 /* We must also verify that the constraints
3892 are met after the replacement. */
3895 n = constrain_operands (1);
3899 /* If the constraints were not met, then
3900 undo the replacement. */
3903 validate_replace_rtx (gen_rtx (code, mode,
3915 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3917 /* Mark this as having an output reload so that the
3918 REG_INC processing code below won't invalidate
3919 the reload for inheritance. */
3920 SET_HARD_REG_BIT (reg_is_output_reload,
3921 REGNO (reload_reg));
3922 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3925 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3928 else if ((code == PRE_INC || code == PRE_DEC)
3929 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3930 REGNO (rld[i].reg_rtx))
3931 /* Make sure it is the inc/dec pseudo, and not
3932 some other (e.g. output operand) pseudo. */
3933 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3934 == REGNO (XEXP (in_reg, 0))))
3936 SET_HARD_REG_BIT (reg_is_output_reload,
3937 REGNO (rld[i].reg_rtx));
3938 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3942 /* If a pseudo that got a hard register is auto-incremented,
3943 we must purge records of copying it into pseudos without
3945 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3946 if (REG_NOTE_KIND (x) == REG_INC)
3948 /* See if this pseudo reg was reloaded in this insn.
3949 If so, its last-reload info is still valid
3950 because it is based on this insn's reload. */
3951 for (i = 0; i < n_reloads; i++)
3952 if (rld[i].out == XEXP (x, 0))
3956 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
3960 /* A reload reg's contents are unknown after a label. */
3961 if (GET_CODE (insn) == CODE_LABEL)
3962 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3964 /* Don't assume a reload reg is still good after a call insn
3965 if it is a call-used reg. */
3966 else if (GET_CODE (insn) == CALL_INSN)
3967 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
3971 free (reg_last_reload_reg);
3972 free (reg_has_output_reload);
3975 /* Discard all record of any value reloaded from X,
3976 or reloaded in X from someplace else;
3977 unless X is an output reload reg of the current insn.
3979 X may be a hard reg (the reload reg)
3980 or it may be a pseudo reg that was reloaded from. */
3983 forget_old_reloads_1 (x, ignored, data)
3985 rtx ignored ATTRIBUTE_UNUSED;
3986 void *data ATTRIBUTE_UNUSED;
3992 /* note_stores does give us subregs of hard regs. */
3993 while (GET_CODE (x) == SUBREG)
3995 offset += SUBREG_WORD (x);
3999 if (GET_CODE (x) != REG)
4002 regno = REGNO (x) + offset;
4004 if (regno >= FIRST_PSEUDO_REGISTER)
4010 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4011 /* Storing into a spilled-reg invalidates its contents.
4012 This can happen if a block-local pseudo is allocated to that reg
4013 and it wasn't spilled because this block's total need is 0.
4014 Then some insn might have an optional reload and use this reg. */
4015 for (i = 0; i < nr; i++)
4016 /* But don't do this if the reg actually serves as an output
4017 reload reg in the current instruction. */
4019 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4020 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4023 /* Since value of X has changed,
4024 forget any value previously copied from it. */
4027 /* But don't forget a copy if this is the output reload
4028 that establishes the copy's validity. */
4029 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4030 reg_last_reload_reg[regno + nr] = 0;
4033 /* The following HARD_REG_SETs indicate when each hard register is
4034 used for a reload of various parts of the current insn. */
4036 /* If reg is unavailable for all reloads. */
4037 static HARD_REG_SET reload_reg_unavailable;
4038 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4039 static HARD_REG_SET reload_reg_used;
4040 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4041 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4042 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4043 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4044 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4045 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4046 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4047 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4048 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4049 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4050 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4051 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4052 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4053 static HARD_REG_SET reload_reg_used_in_op_addr;
4054 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4055 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4056 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4057 static HARD_REG_SET reload_reg_used_in_insn;
4058 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4059 static HARD_REG_SET reload_reg_used_in_other_addr;
4061 /* If reg is in use as a reload reg for any sort of reload. */
4062 static HARD_REG_SET reload_reg_used_at_all;
4064 /* If reg is use as an inherited reload. We just mark the first register
4066 static HARD_REG_SET reload_reg_used_for_inherit;
4068 /* Records which hard regs are used in any way, either as explicit use or
4069 by being allocated to a pseudo during any point of the current insn. */
4070 static HARD_REG_SET reg_used_in_insn;
4072 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4073 TYPE. MODE is used to indicate how many consecutive regs are
4077 mark_reload_reg_in_use (regno, opnum, type, mode)
4080 enum reload_type type;
4081 enum machine_mode mode;
4083 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4086 for (i = regno; i < nregs + regno; i++)
4091 SET_HARD_REG_BIT (reload_reg_used, i);
4094 case RELOAD_FOR_INPUT_ADDRESS:
4095 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4098 case RELOAD_FOR_INPADDR_ADDRESS:
4099 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4102 case RELOAD_FOR_OUTPUT_ADDRESS:
4103 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4106 case RELOAD_FOR_OUTADDR_ADDRESS:
4107 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4110 case RELOAD_FOR_OPERAND_ADDRESS:
4111 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4114 case RELOAD_FOR_OPADDR_ADDR:
4115 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4118 case RELOAD_FOR_OTHER_ADDRESS:
4119 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4122 case RELOAD_FOR_INPUT:
4123 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4126 case RELOAD_FOR_OUTPUT:
4127 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4130 case RELOAD_FOR_INSN:
4131 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4135 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4139 /* Similarly, but show REGNO is no longer in use for a reload. */
4142 clear_reload_reg_in_use (regno, opnum, type, mode)
4145 enum reload_type type;
4146 enum machine_mode mode;
4148 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4149 unsigned int start_regno, end_regno, r;
4151 /* A complication is that for some reload types, inheritance might
4152 allow multiple reloads of the same types to share a reload register.
4153 We set check_opnum if we have to check only reloads with the same
4154 operand number, and check_any if we have to check all reloads. */
4155 int check_opnum = 0;
4157 HARD_REG_SET *used_in_set;
4162 used_in_set = &reload_reg_used;
4165 case RELOAD_FOR_INPUT_ADDRESS:
4166 used_in_set = &reload_reg_used_in_input_addr[opnum];
4169 case RELOAD_FOR_INPADDR_ADDRESS:
4171 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4174 case RELOAD_FOR_OUTPUT_ADDRESS:
4175 used_in_set = &reload_reg_used_in_output_addr[opnum];
4178 case RELOAD_FOR_OUTADDR_ADDRESS:
4180 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4183 case RELOAD_FOR_OPERAND_ADDRESS:
4184 used_in_set = &reload_reg_used_in_op_addr;
4187 case RELOAD_FOR_OPADDR_ADDR:
4189 used_in_set = &reload_reg_used_in_op_addr_reload;
4192 case RELOAD_FOR_OTHER_ADDRESS:
4193 used_in_set = &reload_reg_used_in_other_addr;
4197 case RELOAD_FOR_INPUT:
4198 used_in_set = &reload_reg_used_in_input[opnum];
4201 case RELOAD_FOR_OUTPUT:
4202 used_in_set = &reload_reg_used_in_output[opnum];
4205 case RELOAD_FOR_INSN:
4206 used_in_set = &reload_reg_used_in_insn;
4211 /* We resolve conflicts with remaining reloads of the same type by
4212 excluding the intervals of of reload registers by them from the
4213 interval of freed reload registers. Since we only keep track of
4214 one set of interval bounds, we might have to exclude somewhat
4215 more then what would be necessary if we used a HARD_REG_SET here.
4216 But this should only happen very infrequently, so there should
4217 be no reason to worry about it. */
4219 start_regno = regno;
4220 end_regno = regno + nregs;
4221 if (check_opnum || check_any)
4223 for (i = n_reloads - 1; i >= 0; i--)
4225 if (rld[i].when_needed == type
4226 && (check_any || rld[i].opnum == opnum)
4229 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4230 unsigned int conflict_end
4232 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4234 /* If there is an overlap with the first to-be-freed register,
4235 adjust the interval start. */
4236 if (conflict_start <= start_regno && conflict_end > start_regno)
4237 start_regno = conflict_end;
4238 /* Otherwise, if there is a conflict with one of the other
4239 to-be-freed registers, adjust the interval end. */
4240 if (conflict_start > start_regno && conflict_start < end_regno)
4241 end_regno = conflict_start;
4246 for (r = start_regno; r < end_regno; r++)
4247 CLEAR_HARD_REG_BIT (*used_in_set, r);
4250 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4251 specified by OPNUM and TYPE. */
4254 reload_reg_free_p (regno, opnum, type)
4257 enum reload_type type;
4261 /* In use for a RELOAD_OTHER means it's not available for anything. */
4262 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4263 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4269 /* In use for anything means we can't use it for RELOAD_OTHER. */
4270 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4271 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4272 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4275 for (i = 0; i < reload_n_operands; i++)
4276 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4277 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4278 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4279 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4280 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4281 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4286 case RELOAD_FOR_INPUT:
4287 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4288 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4291 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4294 /* If it is used for some other input, can't use it. */
4295 for (i = 0; i < reload_n_operands; i++)
4296 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4299 /* If it is used in a later operand's address, can't use it. */
4300 for (i = opnum + 1; i < reload_n_operands; i++)
4301 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4302 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4307 case RELOAD_FOR_INPUT_ADDRESS:
4308 /* Can't use a register if it is used for an input address for this
4309 operand or used as an input in an earlier one. */
4310 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4311 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4314 for (i = 0; i < opnum; i++)
4315 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4320 case RELOAD_FOR_INPADDR_ADDRESS:
4321 /* Can't use a register if it is used for an input address
4322 for this operand or used as an input in an earlier
4324 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4327 for (i = 0; i < opnum; i++)
4328 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4333 case RELOAD_FOR_OUTPUT_ADDRESS:
4334 /* Can't use a register if it is used for an output address for this
4335 operand or used as an output in this or a later operand. */
4336 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4339 for (i = opnum; i < reload_n_operands; i++)
4340 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4345 case RELOAD_FOR_OUTADDR_ADDRESS:
4346 /* Can't use a register if it is used for an output address
4347 for this operand or used as an output in this or a
4349 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4352 for (i = opnum; i < reload_n_operands; i++)
4353 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4358 case RELOAD_FOR_OPERAND_ADDRESS:
4359 for (i = 0; i < reload_n_operands; i++)
4360 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4363 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4364 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4366 case RELOAD_FOR_OPADDR_ADDR:
4367 for (i = 0; i < reload_n_operands; i++)
4368 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4371 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4373 case RELOAD_FOR_OUTPUT:
4374 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4375 outputs, or an operand address for this or an earlier output. */
4376 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4379 for (i = 0; i < reload_n_operands; i++)
4380 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4383 for (i = 0; i <= opnum; i++)
4384 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4385 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4390 case RELOAD_FOR_INSN:
4391 for (i = 0; i < reload_n_operands; i++)
4392 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4393 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4396 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4397 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4399 case RELOAD_FOR_OTHER_ADDRESS:
4400 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4405 /* Return 1 if the value in reload reg REGNO, as used by a reload
4406 needed for the part of the insn specified by OPNUM and TYPE,
4407 is still available in REGNO at the end of the insn.
4409 We can assume that the reload reg was already tested for availability
4410 at the time it is needed, and we should not check this again,
4411 in case the reg has already been marked in use. */
4414 reload_reg_reaches_end_p (regno, opnum, type)
4417 enum reload_type type;
4424 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4425 its value must reach the end. */
4428 /* If this use is for part of the insn,
4429 its value reaches if no subsequent part uses the same register.
4430 Just like the above function, don't try to do this with lots
4433 case RELOAD_FOR_OTHER_ADDRESS:
4434 /* Here we check for everything else, since these don't conflict
4435 with anything else and everything comes later. */
4437 for (i = 0; i < reload_n_operands; i++)
4438 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4439 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4440 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4441 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4442 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4443 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4446 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4447 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4448 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4450 case RELOAD_FOR_INPUT_ADDRESS:
4451 case RELOAD_FOR_INPADDR_ADDRESS:
4452 /* Similar, except that we check only for this and subsequent inputs
4453 and the address of only subsequent inputs and we do not need
4454 to check for RELOAD_OTHER objects since they are known not to
4457 for (i = opnum; i < reload_n_operands; i++)
4458 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4461 for (i = opnum + 1; i < reload_n_operands; i++)
4462 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4463 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4466 for (i = 0; i < reload_n_operands; i++)
4467 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4468 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4469 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4472 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4475 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4476 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4478 case RELOAD_FOR_INPUT:
4479 /* Similar to input address, except we start at the next operand for
4480 both input and input address and we do not check for
4481 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4484 for (i = opnum + 1; i < reload_n_operands; i++)
4485 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4486 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4487 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4490 /* ... fall through ... */
4492 case RELOAD_FOR_OPERAND_ADDRESS:
4493 /* Check outputs and their addresses. */
4495 for (i = 0; i < reload_n_operands; i++)
4496 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4497 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4498 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4503 case RELOAD_FOR_OPADDR_ADDR:
4504 for (i = 0; i < reload_n_operands; i++)
4505 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4506 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4507 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4510 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4511 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4513 case RELOAD_FOR_INSN:
4514 /* These conflict with other outputs with RELOAD_OTHER. So
4515 we need only check for output addresses. */
4519 /* ... fall through ... */
4521 case RELOAD_FOR_OUTPUT:
4522 case RELOAD_FOR_OUTPUT_ADDRESS:
4523 case RELOAD_FOR_OUTADDR_ADDRESS:
4524 /* We already know these can't conflict with a later output. So the
4525 only thing to check are later output addresses. */
4526 for (i = opnum + 1; i < reload_n_operands; i++)
4527 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4528 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4537 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4540 This function uses the same algorithm as reload_reg_free_p above. */
4543 reloads_conflict (r1, r2)
4546 enum reload_type r1_type = rld[r1].when_needed;
4547 enum reload_type r2_type = rld[r2].when_needed;
4548 int r1_opnum = rld[r1].opnum;
4549 int r2_opnum = rld[r2].opnum;
4551 /* RELOAD_OTHER conflicts with everything. */
4552 if (r2_type == RELOAD_OTHER)
4555 /* Otherwise, check conflicts differently for each type. */
4559 case RELOAD_FOR_INPUT:
4560 return (r2_type == RELOAD_FOR_INSN
4561 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4562 || r2_type == RELOAD_FOR_OPADDR_ADDR
4563 || r2_type == RELOAD_FOR_INPUT
4564 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4565 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4566 && r2_opnum > r1_opnum));
4568 case RELOAD_FOR_INPUT_ADDRESS:
4569 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4570 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4572 case RELOAD_FOR_INPADDR_ADDRESS:
4573 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4574 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4576 case RELOAD_FOR_OUTPUT_ADDRESS:
4577 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4578 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4580 case RELOAD_FOR_OUTADDR_ADDRESS:
4581 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4582 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4584 case RELOAD_FOR_OPERAND_ADDRESS:
4585 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4586 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4588 case RELOAD_FOR_OPADDR_ADDR:
4589 return (r2_type == RELOAD_FOR_INPUT
4590 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4592 case RELOAD_FOR_OUTPUT:
4593 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4594 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4595 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4596 && r2_opnum <= r1_opnum));
4598 case RELOAD_FOR_INSN:
4599 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4600 || r2_type == RELOAD_FOR_INSN
4601 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4603 case RELOAD_FOR_OTHER_ADDRESS:
4604 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4614 /* Indexed by reload number, 1 if incoming value
4615 inherited from previous insns. */
4616 char reload_inherited[MAX_RELOADS];
4618 /* For an inherited reload, this is the insn the reload was inherited from,
4619 if we know it. Otherwise, this is 0. */
4620 rtx reload_inheritance_insn[MAX_RELOADS];
4622 /* If non-zero, this is a place to get the value of the reload,
4623 rather than using reload_in. */
4624 rtx reload_override_in[MAX_RELOADS];
4626 /* For each reload, the hard register number of the register used,
4627 or -1 if we did not need a register for this reload. */
4628 int reload_spill_index[MAX_RELOADS];
4630 /* Return 1 if the value in reload reg REGNO, as used by a reload
4631 needed for the part of the insn specified by OPNUM and TYPE,
4632 may be used to load VALUE into it.
4634 Other read-only reloads with the same value do not conflict
4635 unless OUT is non-zero and these other reloads have to live while
4636 output reloads live.
4637 If OUT is CONST0_RTX, this is a special case: it means that the
4638 test should not be for using register REGNO as reload register, but
4639 for copying from register REGNO into the reload register.
4641 RELOADNUM is the number of the reload we want to load this value for;
4642 a reload does not conflict with itself.
4644 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4645 reloads that load an address for the very reload we are considering.
4647 The caller has to make sure that there is no conflict with the return
4650 reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum,
4651 ignore_address_reloads)
4654 enum reload_type type;
4657 int ignore_address_reloads;
4660 /* Set if we see an input reload that must not share its reload register
4661 with any new earlyclobber, but might otherwise share the reload
4662 register with an output or input-output reload. */
4663 int check_earlyclobber = 0;
4667 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4670 if (out == const0_rtx)
4676 /* We use some pseudo 'time' value to check if the lifetimes of the
4677 new register use would overlap with the one of a previous reload
4678 that is not read-only or uses a different value.
4679 The 'time' used doesn't have to be linear in any shape or form, just
4681 Some reload types use different 'buckets' for each operand.
4682 So there are MAX_RECOG_OPERANDS different time values for each
4684 We compute TIME1 as the time when the register for the prospective
4685 new reload ceases to be live, and TIME2 for each existing
4686 reload as the time when that the reload register of that reload
4688 Where there is little to be gained by exact lifetime calculations,
4689 we just make conservative assumptions, i.e. a longer lifetime;
4690 this is done in the 'default:' cases. */
4693 case RELOAD_FOR_OTHER_ADDRESS:
4694 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4695 time1 = copy ? 0 : 1;
4698 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4700 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4701 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4702 respectively, to the time values for these, we get distinct time
4703 values. To get distinct time values for each operand, we have to
4704 multiply opnum by at least three. We round that up to four because
4705 multiply by four is often cheaper. */
4706 case RELOAD_FOR_INPADDR_ADDRESS:
4707 time1 = opnum * 4 + 2;
4709 case RELOAD_FOR_INPUT_ADDRESS:
4710 time1 = opnum * 4 + 3;
4712 case RELOAD_FOR_INPUT:
4713 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4714 executes (inclusive). */
4715 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4717 case RELOAD_FOR_OPADDR_ADDR:
4719 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4720 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4722 case RELOAD_FOR_OPERAND_ADDRESS:
4723 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4725 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4727 case RELOAD_FOR_OUTADDR_ADDRESS:
4728 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4730 case RELOAD_FOR_OUTPUT_ADDRESS:
4731 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4734 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4737 for (i = 0; i < n_reloads; i++)
4739 rtx reg = rld[i].reg_rtx;
4740 if (reg && GET_CODE (reg) == REG
4741 && ((unsigned) regno - true_regnum (reg)
4742 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
4745 if (! rld[i].in || ! rtx_equal_p (rld[i].in, value)
4746 || rld[i].out || out)
4749 switch (rld[i].when_needed)
4751 case RELOAD_FOR_OTHER_ADDRESS:
4754 case RELOAD_FOR_INPADDR_ADDRESS:
4755 /* find_reloads makes sure that a
4756 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4757 by at most one - the first -
4758 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4759 address reload is inherited, the address address reload
4760 goes away, so we can ignore this conflict. */
4761 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4762 && ignore_address_reloads
4763 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4764 Then the address address is still needed to store
4765 back the new address. */
4766 && ! rld[reloadnum].out)
4768 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4769 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4771 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4772 && ignore_address_reloads
4773 /* Unless we are reloading an auto_inc expression. */
4774 && ! rld[reloadnum].out)
4776 time2 = rld[i].opnum * 4 + 2;
4778 case RELOAD_FOR_INPUT_ADDRESS:
4779 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4780 && ignore_address_reloads
4781 && ! rld[reloadnum].out)
4783 time2 = rld[i].opnum * 4 + 3;
4785 case RELOAD_FOR_INPUT:
4786 time2 = rld[i].opnum * 4 + 4;
4787 check_earlyclobber = 1;
4789 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4790 == MAX_RECOG_OPERAND * 4 */
4791 case RELOAD_FOR_OPADDR_ADDR:
4792 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4793 && ignore_address_reloads
4794 && ! rld[reloadnum].out)
4796 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4798 case RELOAD_FOR_OPERAND_ADDRESS:
4799 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4800 check_earlyclobber = 1;
4802 case RELOAD_FOR_INSN:
4803 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4805 case RELOAD_FOR_OUTPUT:
4806 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4807 instruction is executed. */
4808 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4810 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4811 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4813 case RELOAD_FOR_OUTADDR_ADDRESS:
4814 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4815 && ignore_address_reloads
4816 && ! rld[reloadnum].out)
4818 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4820 case RELOAD_FOR_OUTPUT_ADDRESS:
4821 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4824 /* If there is no conflict in the input part, handle this
4825 like an output reload. */
4826 if (! rld[i].in || rtx_equal_p (rld[i].in, value))
4828 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4829 /* Earlyclobbered outputs must conflict with inputs. */
4830 if (earlyclobber_operand_p (rld[i].out))
4831 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4836 /* RELOAD_OTHER might be live beyond instruction execution,
4837 but this is not obvious when we set time2 = 1. So check
4838 here if there might be a problem with the new reload
4839 clobbering the register used by the RELOAD_OTHER. */
4847 && (! rld[i].in || rld[i].out
4848 || ! rtx_equal_p (rld[i].in, value)))
4849 || (out && rld[reloadnum].out_reg
4850 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4856 /* Earlyclobbered outputs must conflict with inputs. */
4857 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4863 /* Give an error message saying we failed to find a reload for INSN,
4864 and clear out reload R. */
4866 failed_reload (insn, r)
4870 if (asm_noperands (PATTERN (insn)) < 0)
4871 /* It's the compiler's fault. */
4872 fatal_insn ("Could not find a spill register", insn);
4874 /* It's the user's fault; the operand's mode and constraint
4875 don't match. Disable this reload so we don't crash in final. */
4876 error_for_asm (insn,
4877 "`asm' operand constraint incompatible with operand size");
4881 rld[r].optional = 1;
4882 rld[r].secondary_p = 1;
4885 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
4886 for reload R. If it's valid, get an rtx for it. Return nonzero if
4889 set_reload_reg (i, r)
4893 rtx reg = spill_reg_rtx[i];
4895 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
4896 spill_reg_rtx[i] = reg
4897 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
4899 regno = true_regnum (reg);
4901 /* Detect when the reload reg can't hold the reload mode.
4902 This used to be one `if', but Sequent compiler can't handle that. */
4903 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
4905 enum machine_mode test_mode = VOIDmode;
4907 test_mode = GET_MODE (rld[r].in);
4908 /* If rld[r].in has VOIDmode, it means we will load it
4909 in whatever mode the reload reg has: to wit, rld[r].mode.
4910 We have already tested that for validity. */
4911 /* Aside from that, we need to test that the expressions
4912 to reload from or into have modes which are valid for this
4913 reload register. Otherwise the reload insns would be invalid. */
4914 if (! (rld[r].in != 0 && test_mode != VOIDmode
4915 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
4916 if (! (rld[r].out != 0
4917 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
4919 /* The reg is OK. */
4922 /* Mark as in use for this insn the reload regs we use
4924 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
4925 rld[r].when_needed, rld[r].mode);
4927 rld[r].reg_rtx = reg;
4928 reload_spill_index[r] = spill_regs[i];
4935 /* Find a spill register to use as a reload register for reload R.
4936 LAST_RELOAD is non-zero if this is the last reload for the insn being
4939 Set rld[R].reg_rtx to the register allocated.
4941 We return 1 if successful, or 0 if we couldn't find a spill reg and
4942 we didn't change anything. */
4945 allocate_reload_reg (chain, r, last_reload)
4946 struct insn_chain *chain ATTRIBUTE_UNUSED;
4952 /* If we put this reload ahead, thinking it is a group,
4953 then insist on finding a group. Otherwise we can grab a
4954 reg that some other reload needs.
4955 (That can happen when we have a 68000 DATA_OR_FP_REG
4956 which is a group of data regs or one fp reg.)
4957 We need not be so restrictive if there are no more reloads
4960 ??? Really it would be nicer to have smarter handling
4961 for that kind of reg class, where a problem like this is normal.
4962 Perhaps those classes should be avoided for reloading
4963 by use of more alternatives. */
4965 int force_group = rld[r].nregs > 1 && ! last_reload;
4967 /* If we want a single register and haven't yet found one,
4968 take any reg in the right class and not in use.
4969 If we want a consecutive group, here is where we look for it.
4971 We use two passes so we can first look for reload regs to
4972 reuse, which are already in use for other reloads in this insn,
4973 and only then use additional registers.
4974 I think that maximizing reuse is needed to make sure we don't
4975 run out of reload regs. Suppose we have three reloads, and
4976 reloads A and B can share regs. These need two regs.
4977 Suppose A and B are given different regs.
4978 That leaves none for C. */
4979 for (pass = 0; pass < 2; pass++)
4981 /* I is the index in spill_regs.
4982 We advance it round-robin between insns to use all spill regs
4983 equally, so that inherited reloads have a chance
4984 of leapfrogging each other. */
4988 for (count = 0; count < n_spills; count++)
4990 int class = (int) rld[r].class;
4996 regnum = spill_regs[i];
4998 if ((reload_reg_free_p (regnum, rld[r].opnum,
5001 /* We check reload_reg_used to make sure we
5002 don't clobber the return register. */
5003 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5004 && reload_reg_free_for_value_p (regnum,
5009 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5010 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5011 /* Look first for regs to share, then for unshared. But
5012 don't share regs used for inherited reloads; they are
5013 the ones we want to preserve. */
5015 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5017 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5020 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5021 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5022 (on 68000) got us two FP regs. If NR is 1,
5023 we would reject both of them. */
5026 /* If we need only one reg, we have already won. */
5029 /* But reject a single reg if we demand a group. */
5034 /* Otherwise check that as many consecutive regs as we need
5035 are available here. */
5038 int regno = regnum + nr - 1;
5039 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5040 && spill_reg_order[regno] >= 0
5041 && reload_reg_free_p (regno, rld[r].opnum,
5042 rld[r].when_needed)))
5051 /* If we found something on pass 1, omit pass 2. */
5052 if (count < n_spills)
5056 /* We should have found a spill register by now. */
5057 if (count >= n_spills)
5060 /* I is the index in SPILL_REG_RTX of the reload register we are to
5061 allocate. Get an rtx for it and find its register number. */
5063 return set_reload_reg (i, r);
5066 /* Initialize all the tables needed to allocate reload registers.
5067 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5068 is the array we use to restore the reg_rtx field for every reload. */
5071 choose_reload_regs_init (chain, save_reload_reg_rtx)
5072 struct insn_chain *chain;
5073 rtx *save_reload_reg_rtx;
5077 for (i = 0; i < n_reloads; i++)
5078 rld[i].reg_rtx = save_reload_reg_rtx[i];
5080 bzero (reload_inherited, MAX_RELOADS);
5081 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5082 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5084 CLEAR_HARD_REG_SET (reload_reg_used);
5085 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5086 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5087 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5088 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5089 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5091 CLEAR_HARD_REG_SET (reg_used_in_insn);
5094 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5095 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5096 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5097 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5098 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5099 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5102 for (i = 0; i < reload_n_operands; i++)
5104 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5105 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5106 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5107 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5108 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5109 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5112 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5114 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5116 for (i = 0; i < n_reloads; i++)
5117 /* If we have already decided to use a certain register,
5118 don't use it in another way. */
5120 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5121 rld[i].when_needed, rld[i].mode);
5124 /* Assign hard reg targets for the pseudo-registers we must reload
5125 into hard regs for this insn.
5126 Also output the instructions to copy them in and out of the hard regs.
5128 For machines with register classes, we are responsible for
5129 finding a reload reg in the proper class. */
5132 choose_reload_regs (chain)
5133 struct insn_chain *chain;
5135 rtx insn = chain->insn;
5137 unsigned int max_group_size = 1;
5138 enum reg_class group_class = NO_REGS;
5139 int pass, win, inheritance;
5141 rtx save_reload_reg_rtx[MAX_RELOADS];
5143 /* In order to be certain of getting the registers we need,
5144 we must sort the reloads into order of increasing register class.
5145 Then our grabbing of reload registers will parallel the process
5146 that provided the reload registers.
5148 Also note whether any of the reloads wants a consecutive group of regs.
5149 If so, record the maximum size of the group desired and what
5150 register class contains all the groups needed by this insn. */
5152 for (j = 0; j < n_reloads; j++)
5154 reload_order[j] = j;
5155 reload_spill_index[j] = -1;
5157 if (rld[j].nregs > 1)
5159 max_group_size = MAX (rld[j].nregs, max_group_size);
5161 = reg_class_superunion[(int) rld[j].class][(int)group_class];
5164 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5168 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5170 /* If -O, try first with inheritance, then turning it off.
5171 If not -O, don't do inheritance.
5172 Using inheritance when not optimizing leads to paradoxes
5173 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5174 because one side of the comparison might be inherited. */
5176 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5178 choose_reload_regs_init (chain, save_reload_reg_rtx);
5180 /* Process the reloads in order of preference just found.
5181 Beyond this point, subregs can be found in reload_reg_rtx.
5183 This used to look for an existing reloaded home for all of the
5184 reloads, and only then perform any new reloads. But that could lose
5185 if the reloads were done out of reg-class order because a later
5186 reload with a looser constraint might have an old home in a register
5187 needed by an earlier reload with a tighter constraint.
5189 To solve this, we make two passes over the reloads, in the order
5190 described above. In the first pass we try to inherit a reload
5191 from a previous insn. If there is a later reload that needs a
5192 class that is a proper subset of the class being processed, we must
5193 also allocate a spill register during the first pass.
5195 Then make a second pass over the reloads to allocate any reloads
5196 that haven't been given registers yet. */
5198 for (j = 0; j < n_reloads; j++)
5200 register int r = reload_order[j];
5201 rtx search_equiv = NULL_RTX;
5203 /* Ignore reloads that got marked inoperative. */
5204 if (rld[r].out == 0 && rld[r].in == 0
5205 && ! rld[r].secondary_p)
5208 /* If find_reloads chose to use reload_in or reload_out as a reload
5209 register, we don't need to chose one. Otherwise, try even if it
5210 found one since we might save an insn if we find the value lying
5212 Try also when reload_in is a pseudo without a hard reg. */
5213 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5214 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5215 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5216 && GET_CODE (rld[r].in) != MEM
5217 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5220 #if 0 /* No longer needed for correct operation.
5221 It might give better code, or might not; worth an experiment? */
5222 /* If this is an optional reload, we can't inherit from earlier insns
5223 until we are sure that any non-optional reloads have been allocated.
5224 The following code takes advantage of the fact that optional reloads
5225 are at the end of reload_order. */
5226 if (rld[r].optional != 0)
5227 for (i = 0; i < j; i++)
5228 if ((rld[reload_order[i]].out != 0
5229 || rld[reload_order[i]].in != 0
5230 || rld[reload_order[i]].secondary_p)
5231 && ! rld[reload_order[i]].optional
5232 && rld[reload_order[i]].reg_rtx == 0)
5233 allocate_reload_reg (chain, reload_order[i], 0);
5236 /* First see if this pseudo is already available as reloaded
5237 for a previous insn. We cannot try to inherit for reloads
5238 that are smaller than the maximum number of registers needed
5239 for groups unless the register we would allocate cannot be used
5242 We could check here to see if this is a secondary reload for
5243 an object that is already in a register of the desired class.
5244 This would avoid the need for the secondary reload register.
5245 But this is complex because we can't easily determine what
5246 objects might want to be loaded via this reload. So let a
5247 register be allocated here. In `emit_reload_insns' we suppress
5248 one of the loads in the case described above. */
5253 register int regno = -1;
5254 enum machine_mode mode = VOIDmode;
5258 else if (GET_CODE (rld[r].in) == REG)
5260 regno = REGNO (rld[r].in);
5261 mode = GET_MODE (rld[r].in);
5263 else if (GET_CODE (rld[r].in_reg) == REG)
5265 regno = REGNO (rld[r].in_reg);
5266 mode = GET_MODE (rld[r].in_reg);
5268 else if (GET_CODE (rld[r].in_reg) == SUBREG
5269 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5271 word = SUBREG_WORD (rld[r].in_reg);
5272 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5273 if (regno < FIRST_PSEUDO_REGISTER)
5275 mode = GET_MODE (rld[r].in_reg);
5278 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5279 || GET_CODE (rld[r].in_reg) == PRE_DEC
5280 || GET_CODE (rld[r].in_reg) == POST_INC
5281 || GET_CODE (rld[r].in_reg) == POST_DEC)
5282 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5284 regno = REGNO (XEXP (rld[r].in_reg, 0));
5285 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5286 rld[r].out = rld[r].in;
5290 /* This won't work, since REGNO can be a pseudo reg number.
5291 Also, it takes much more hair to keep track of all the things
5292 that can invalidate an inherited reload of part of a pseudoreg. */
5293 else if (GET_CODE (rld[r].in) == SUBREG
5294 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5295 regno = REGNO (SUBREG_REG (rld[r].in)) + SUBREG_WORD (rld[r].in);
5298 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5300 enum reg_class class = rld[r].class, last_class;
5301 rtx last_reg = reg_last_reload_reg[regno];
5302 enum machine_mode need_mode;
5304 i = REGNO (last_reg) + word;
5305 last_class = REGNO_REG_CLASS (i);
5307 need_mode = smallest_mode_for_size ((word+1) * UNITS_PER_WORD,
5308 GET_MODE_CLASS (mode));
5311 #ifdef CLASS_CANNOT_CHANGE_MODE
5313 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], i)
5314 ? ! CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (last_reg),
5316 : (GET_MODE_SIZE (GET_MODE (last_reg))
5317 >= GET_MODE_SIZE (need_mode)))
5319 (GET_MODE_SIZE (GET_MODE (last_reg))
5320 >= GET_MODE_SIZE (need_mode))
5322 && reg_reloaded_contents[i] == regno
5323 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5324 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5325 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5326 /* Even if we can't use this register as a reload
5327 register, we might use it for reload_override_in,
5328 if copying it to the desired class is cheap
5330 || ((REGISTER_MOVE_COST (last_class, class)
5331 < MEMORY_MOVE_COST (mode, class, 1))
5332 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5333 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5337 #ifdef SECONDARY_MEMORY_NEEDED
5338 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5343 && (rld[r].nregs == max_group_size
5344 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5346 && reload_reg_free_for_value_p (i, rld[r].opnum,
5351 /* If a group is needed, verify that all the subsequent
5352 registers still have their values intact. */
5353 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5356 for (k = 1; k < nr; k++)
5357 if (reg_reloaded_contents[i + k] != regno
5358 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5365 last_reg = (GET_MODE (last_reg) == mode
5366 ? last_reg : gen_rtx_REG (mode, i));
5368 /* We found a register that contains the
5369 value we need. If this register is the
5370 same as an `earlyclobber' operand of the
5371 current insn, just mark it as a place to
5372 reload from since we can't use it as the
5373 reload register itself. */
5375 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5376 if (reg_overlap_mentioned_for_reload_p
5377 (reg_last_reload_reg[regno],
5378 reload_earlyclobbers[i1]))
5381 if (i1 != n_earlyclobbers
5382 || ! (reload_reg_free_for_value_p
5383 (i, rld[r].opnum, rld[r].when_needed,
5384 rld[r].in, rld[r].out, r, 1))
5385 /* Don't use it if we'd clobber a pseudo reg. */
5386 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5388 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5389 /* Don't clobber the frame pointer. */
5390 || (i == HARD_FRAME_POINTER_REGNUM
5392 /* Don't really use the inherited spill reg
5393 if we need it wider than we've got it. */
5394 || (GET_MODE_SIZE (rld[r].mode)
5395 > GET_MODE_SIZE (mode))
5396 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5399 /* If find_reloads chose reload_out as reload
5400 register, stay with it - that leaves the
5401 inherited register for subsequent reloads. */
5402 || (rld[r].out && rld[r].reg_rtx
5403 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5405 reload_override_in[r] = last_reg;
5406 reload_inheritance_insn[r]
5407 = reg_reloaded_insn[i];
5412 /* We can use this as a reload reg. */
5413 /* Mark the register as in use for this part of
5415 mark_reload_reg_in_use (i,
5419 rld[r].reg_rtx = last_reg;
5420 reload_inherited[r] = 1;
5421 reload_inheritance_insn[r]
5422 = reg_reloaded_insn[i];
5423 reload_spill_index[r] = i;
5424 for (k = 0; k < nr; k++)
5425 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5433 /* Here's another way to see if the value is already lying around. */
5436 && ! reload_inherited[r]
5438 && (CONSTANT_P (rld[r].in)
5439 || GET_CODE (rld[r].in) == PLUS
5440 || GET_CODE (rld[r].in) == REG
5441 || GET_CODE (rld[r].in) == MEM)
5442 && (rld[r].nregs == max_group_size
5443 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5444 search_equiv = rld[r].in;
5445 /* If this is an output reload from a simple move insn, look
5446 if an equivalence for the input is available. */
5447 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5449 rtx set = single_set (insn);
5452 && rtx_equal_p (rld[r].out, SET_DEST (set))
5453 && CONSTANT_P (SET_SRC (set)))
5454 search_equiv = SET_SRC (set);
5460 = find_equiv_reg (search_equiv, insn, rld[r].class,
5461 -1, NULL_PTR, 0, rld[r].mode);
5466 if (GET_CODE (equiv) == REG)
5467 regno = REGNO (equiv);
5468 else if (GET_CODE (equiv) == SUBREG)
5470 /* This must be a SUBREG of a hard register.
5471 Make a new REG since this might be used in an
5472 address and not all machines support SUBREGs
5474 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5475 equiv = gen_rtx_REG (rld[r].mode, regno);
5481 /* If we found a spill reg, reject it unless it is free
5482 and of the desired class. */
5484 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5485 && ! reload_reg_free_for_value_p (regno, rld[r].opnum,
5489 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5493 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5496 /* We found a register that contains the value we need.
5497 If this register is the same as an `earlyclobber' operand
5498 of the current insn, just mark it as a place to reload from
5499 since we can't use it as the reload register itself. */
5502 for (i = 0; i < n_earlyclobbers; i++)
5503 if (reg_overlap_mentioned_for_reload_p (equiv,
5504 reload_earlyclobbers[i]))
5506 reload_override_in[r] = equiv;
5511 /* If the equiv register we have found is explicitly clobbered
5512 in the current insn, it depends on the reload type if we
5513 can use it, use it for reload_override_in, or not at all.
5514 In particular, we then can't use EQUIV for a
5515 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5517 if (equiv != 0 && regno_clobbered_p (regno, insn, rld[r].mode))
5519 switch (rld[r].when_needed)
5521 case RELOAD_FOR_OTHER_ADDRESS:
5522 case RELOAD_FOR_INPADDR_ADDRESS:
5523 case RELOAD_FOR_INPUT_ADDRESS:
5524 case RELOAD_FOR_OPADDR_ADDR:
5527 case RELOAD_FOR_INPUT:
5528 case RELOAD_FOR_OPERAND_ADDRESS:
5529 reload_override_in[r] = equiv;
5537 /* If we found an equivalent reg, say no code need be generated
5538 to load it, and use it as our reload reg. */
5539 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5541 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5543 rld[r].reg_rtx = equiv;
5544 reload_inherited[r] = 1;
5546 /* If reg_reloaded_valid is not set for this register,
5547 there might be a stale spill_reg_store lying around.
5548 We must clear it, since otherwise emit_reload_insns
5549 might delete the store. */
5550 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5551 spill_reg_store[regno] = NULL_RTX;
5552 /* If any of the hard registers in EQUIV are spill
5553 registers, mark them as in use for this insn. */
5554 for (k = 0; k < nr; k++)
5556 i = spill_reg_order[regno + k];
5559 mark_reload_reg_in_use (regno, rld[r].opnum,
5562 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5569 /* If we found a register to use already, or if this is an optional
5570 reload, we are done. */
5571 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5575 /* No longer needed for correct operation. Might or might
5576 not give better code on the average. Want to experiment? */
5578 /* See if there is a later reload that has a class different from our
5579 class that intersects our class or that requires less register
5580 than our reload. If so, we must allocate a register to this
5581 reload now, since that reload might inherit a previous reload
5582 and take the only available register in our class. Don't do this
5583 for optional reloads since they will force all previous reloads
5584 to be allocated. Also don't do this for reloads that have been
5587 for (i = j + 1; i < n_reloads; i++)
5589 int s = reload_order[i];
5591 if ((rld[s].in == 0 && rld[s].out == 0
5592 && ! rld[s].secondary_p)
5596 if ((rld[s].class != rld[r].class
5597 && reg_classes_intersect_p (rld[r].class,
5599 || rld[s].nregs < rld[r].nregs)
5606 allocate_reload_reg (chain, r, j == n_reloads - 1);
5610 /* Now allocate reload registers for anything non-optional that
5611 didn't get one yet. */
5612 for (j = 0; j < n_reloads; j++)
5614 register int r = reload_order[j];
5616 /* Ignore reloads that got marked inoperative. */
5617 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5620 /* Skip reloads that already have a register allocated or are
5622 if (rld[r].reg_rtx != 0 || rld[r].optional)
5625 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5629 /* If that loop got all the way, we have won. */
5636 /* Loop around and try without any inheritance. */
5641 /* First undo everything done by the failed attempt
5642 to allocate with inheritance. */
5643 choose_reload_regs_init (chain, save_reload_reg_rtx);
5645 /* Some sanity tests to verify that the reloads found in the first
5646 pass are identical to the ones we have now. */
5647 if (chain->n_reloads != n_reloads)
5650 for (i = 0; i < n_reloads; i++)
5652 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5654 if (chain->rld[i].when_needed != rld[i].when_needed)
5656 for (j = 0; j < n_spills; j++)
5657 if (spill_regs[j] == chain->rld[i].regno)
5658 if (! set_reload_reg (j, i))
5659 failed_reload (chain->insn, i);
5663 /* If we thought we could inherit a reload, because it seemed that
5664 nothing else wanted the same reload register earlier in the insn,
5665 verify that assumption, now that all reloads have been assigned.
5666 Likewise for reloads where reload_override_in has been set. */
5668 /* If doing expensive optimizations, do one preliminary pass that doesn't
5669 cancel any inheritance, but removes reloads that have been needed only
5670 for reloads that we know can be inherited. */
5671 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5673 for (j = 0; j < n_reloads; j++)
5675 register int r = reload_order[j];
5677 if (reload_inherited[r] && rld[r].reg_rtx)
5678 check_reg = rld[r].reg_rtx;
5679 else if (reload_override_in[r]
5680 && (GET_CODE (reload_override_in[r]) == REG
5681 || GET_CODE (reload_override_in[r]) == SUBREG))
5682 check_reg = reload_override_in[r];
5685 if (! reload_reg_free_for_value_p (true_regnum (check_reg),
5689 (reload_inherited[r]
5690 ? rld[r].out : const0_rtx),
5695 reload_inherited[r] = 0;
5696 reload_override_in[r] = 0;
5698 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5699 reload_override_in, then we do not need its related
5700 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5701 likewise for other reload types.
5702 We handle this by removing a reload when its only replacement
5703 is mentioned in reload_in of the reload we are going to inherit.
5704 A special case are auto_inc expressions; even if the input is
5705 inherited, we still need the address for the output. We can
5706 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5707 If we suceeded removing some reload and we are doing a preliminary
5708 pass just to remove such reloads, make another pass, since the
5709 removal of one reload might allow us to inherit another one. */
5711 && rld[r].out != rld[r].in
5712 && remove_address_replacements (rld[r].in) && pass)
5717 /* Now that reload_override_in is known valid,
5718 actually override reload_in. */
5719 for (j = 0; j < n_reloads; j++)
5720 if (reload_override_in[j])
5721 rld[j].in = reload_override_in[j];
5723 /* If this reload won't be done because it has been cancelled or is
5724 optional and not inherited, clear reload_reg_rtx so other
5725 routines (such as subst_reloads) don't get confused. */
5726 for (j = 0; j < n_reloads; j++)
5727 if (rld[j].reg_rtx != 0
5728 && ((rld[j].optional && ! reload_inherited[j])
5729 || (rld[j].in == 0 && rld[j].out == 0
5730 && ! rld[j].secondary_p)))
5732 int regno = true_regnum (rld[j].reg_rtx);
5734 if (spill_reg_order[regno] >= 0)
5735 clear_reload_reg_in_use (regno, rld[j].opnum,
5736 rld[j].when_needed, rld[j].mode);
5738 reload_spill_index[j] = -1;
5741 /* Record which pseudos and which spill regs have output reloads. */
5742 for (j = 0; j < n_reloads; j++)
5744 register int r = reload_order[j];
5746 i = reload_spill_index[r];
5748 /* I is nonneg if this reload uses a register.
5749 If rld[r].reg_rtx is 0, this is an optional reload
5750 that we opted to ignore. */
5751 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5752 && rld[r].reg_rtx != 0)
5754 register int nregno = REGNO (rld[r].out_reg);
5757 if (nregno < FIRST_PSEUDO_REGISTER)
5758 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5761 reg_has_output_reload[nregno + nr] = 1;
5765 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5767 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5770 if (rld[r].when_needed != RELOAD_OTHER
5771 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5772 && rld[r].when_needed != RELOAD_FOR_INSN)
5778 /* Deallocate the reload register for reload R. This is called from
5779 remove_address_replacements. */
5782 deallocate_reload_reg (r)
5787 if (! rld[r].reg_rtx)
5789 regno = true_regnum (rld[r].reg_rtx);
5791 if (spill_reg_order[regno] >= 0)
5792 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5794 reload_spill_index[r] = -1;
5797 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5798 reloads of the same item for fear that we might not have enough reload
5799 registers. However, normally they will get the same reload register
5800 and hence actually need not be loaded twice.
5802 Here we check for the most common case of this phenomenon: when we have
5803 a number of reloads for the same object, each of which were allocated
5804 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5805 reload, and is not modified in the insn itself. If we find such,
5806 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5807 This will not increase the number of spill registers needed and will
5808 prevent redundant code. */
5811 merge_assigned_reloads (insn)
5816 /* Scan all the reloads looking for ones that only load values and
5817 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5818 assigned and not modified by INSN. */
5820 for (i = 0; i < n_reloads; i++)
5822 int conflicting_input = 0;
5823 int max_input_address_opnum = -1;
5824 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5826 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5827 || rld[i].out != 0 || rld[i].reg_rtx == 0
5828 || reg_set_p (rld[i].reg_rtx, insn))
5831 /* Look at all other reloads. Ensure that the only use of this
5832 reload_reg_rtx is in a reload that just loads the same value
5833 as we do. Note that any secondary reloads must be of the identical
5834 class since the values, modes, and result registers are the
5835 same, so we need not do anything with any secondary reloads. */
5837 for (j = 0; j < n_reloads; j++)
5839 if (i == j || rld[j].reg_rtx == 0
5840 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
5844 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5845 && rld[j].opnum > max_input_address_opnum)
5846 max_input_address_opnum = rld[j].opnum;
5848 /* If the reload regs aren't exactly the same (e.g, different modes)
5849 or if the values are different, we can't merge this reload.
5850 But if it is an input reload, we might still merge
5851 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
5853 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5854 || rld[j].out != 0 || rld[j].in == 0
5855 || ! rtx_equal_p (rld[i].in, rld[j].in))
5857 if (rld[j].when_needed != RELOAD_FOR_INPUT
5858 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
5859 || rld[i].opnum > rld[j].opnum)
5860 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
5862 conflicting_input = 1;
5863 if (min_conflicting_input_opnum > rld[j].opnum)
5864 min_conflicting_input_opnum = rld[j].opnum;
5868 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5869 we, in fact, found any matching reloads. */
5872 && max_input_address_opnum <= min_conflicting_input_opnum)
5874 for (j = 0; j < n_reloads; j++)
5875 if (i != j && rld[j].reg_rtx != 0
5876 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5877 && (! conflicting_input
5878 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5879 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
5881 rld[i].when_needed = RELOAD_OTHER;
5883 reload_spill_index[j] = -1;
5884 transfer_replacements (i, j);
5887 /* If this is now RELOAD_OTHER, look for any reloads that load
5888 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5889 if they were for inputs, RELOAD_OTHER for outputs. Note that
5890 this test is equivalent to looking for reloads for this operand
5893 if (rld[i].when_needed == RELOAD_OTHER)
5894 for (j = 0; j < n_reloads; j++)
5896 && rld[i].when_needed != RELOAD_OTHER
5897 && reg_overlap_mentioned_for_reload_p (rld[j].in,
5900 = ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
5901 || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
5902 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
5907 /* These arrays are filled by emit_reload_insns and its subroutines. */
5908 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
5909 static rtx other_input_address_reload_insns = 0;
5910 static rtx other_input_reload_insns = 0;
5911 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
5912 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5913 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
5914 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
5915 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5916 static rtx operand_reload_insns = 0;
5917 static rtx other_operand_reload_insns = 0;
5918 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
5920 /* Values to be put in spill_reg_store are put here first. */
5921 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
5922 static HARD_REG_SET reg_reloaded_died;
5924 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
5925 has the number J. OLD contains the value to be used as input. */
5928 emit_input_reload_insns (chain, rl, old, j)
5929 struct insn_chain *chain;
5934 rtx insn = chain->insn;
5935 register rtx reloadreg = rl->reg_rtx;
5936 rtx oldequiv_reg = 0;
5939 enum machine_mode mode;
5942 /* Determine the mode to reload in.
5943 This is very tricky because we have three to choose from.
5944 There is the mode the insn operand wants (rl->inmode).
5945 There is the mode of the reload register RELOADREG.
5946 There is the intrinsic mode of the operand, which we could find
5947 by stripping some SUBREGs.
5948 It turns out that RELOADREG's mode is irrelevant:
5949 we can change that arbitrarily.
5951 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
5952 then the reload reg may not support QImode moves, so use SImode.
5953 If foo is in memory due to spilling a pseudo reg, this is safe,
5954 because the QImode value is in the least significant part of a
5955 slot big enough for a SImode. If foo is some other sort of
5956 memory reference, then it is impossible to reload this case,
5957 so previous passes had better make sure this never happens.
5959 Then consider a one-word union which has SImode and one of its
5960 members is a float, being fetched as (SUBREG:SF union:SI).
5961 We must fetch that as SFmode because we could be loading into
5962 a float-only register. In this case OLD's mode is correct.
5964 Consider an immediate integer: it has VOIDmode. Here we need
5965 to get a mode from something else.
5967 In some cases, there is a fourth mode, the operand's
5968 containing mode. If the insn specifies a containing mode for
5969 this operand, it overrides all others.
5971 I am not sure whether the algorithm here is always right,
5972 but it does the right things in those cases. */
5974 mode = GET_MODE (old);
5975 if (mode == VOIDmode)
5978 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5979 /* If we need a secondary register for this operation, see if
5980 the value is already in a register in that class. Don't
5981 do this if the secondary register will be used as a scratch
5984 if (rl->secondary_in_reload >= 0
5985 && rl->secondary_in_icode == CODE_FOR_nothing
5988 = find_equiv_reg (old, insn,
5989 rld[rl->secondary_in_reload].class,
5990 -1, NULL_PTR, 0, mode);
5993 /* If reloading from memory, see if there is a register
5994 that already holds the same value. If so, reload from there.
5995 We can pass 0 as the reload_reg_p argument because
5996 any other reload has either already been emitted,
5997 in which case find_equiv_reg will see the reload-insn,
5998 or has yet to be emitted, in which case it doesn't matter
5999 because we will use this equiv reg right away. */
6001 if (oldequiv == 0 && optimize
6002 && (GET_CODE (old) == MEM
6003 || (GET_CODE (old) == REG
6004 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6005 && reg_renumber[REGNO (old)] < 0)))
6006 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6007 -1, NULL_PTR, 0, mode);
6011 unsigned int regno = true_regnum (oldequiv);
6013 /* Don't use OLDEQUIV if any other reload changes it at an
6014 earlier stage of this insn or at this stage. */
6015 if (! reload_reg_free_for_value_p (regno, rl->opnum,
6017 rl->in, const0_rtx, j,
6021 /* If it is no cheaper to copy from OLDEQUIV into the
6022 reload register than it would be to move from memory,
6023 don't use it. Likewise, if we need a secondary register
6027 && ((REGNO_REG_CLASS (regno) != rl->class
6028 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
6030 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6031 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6032 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6036 #ifdef SECONDARY_MEMORY_NEEDED
6037 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6045 /* delete_output_reload is only invoked properly if old contains
6046 the original pseudo register. Since this is replaced with a
6047 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6048 find the pseudo in RELOAD_IN_REG. */
6050 && reload_override_in[j]
6051 && GET_CODE (rl->in_reg) == REG)
6058 else if (GET_CODE (oldequiv) == REG)
6059 oldequiv_reg = oldequiv;
6060 else if (GET_CODE (oldequiv) == SUBREG)
6061 oldequiv_reg = SUBREG_REG (oldequiv);
6063 /* If we are reloading from a register that was recently stored in
6064 with an output-reload, see if we can prove there was
6065 actually no need to store the old value in it. */
6067 if (optimize && GET_CODE (oldequiv) == REG
6068 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6069 && spill_reg_store[REGNO (oldequiv)]
6070 && GET_CODE (old) == REG
6071 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6072 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6074 delete_output_reload (insn, j, REGNO (oldequiv));
6076 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6077 then load RELOADREG from OLDEQUIV. Note that we cannot use
6078 gen_lowpart_common since it can do the wrong thing when
6079 RELOADREG has a multi-word mode. Note that RELOADREG
6080 must always be a REG here. */
6082 if (GET_MODE (reloadreg) != mode)
6083 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6084 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6085 oldequiv = SUBREG_REG (oldequiv);
6086 if (GET_MODE (oldequiv) != VOIDmode
6087 && mode != GET_MODE (oldequiv))
6088 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6090 /* Switch to the right place to emit the reload insns. */
6091 switch (rl->when_needed)
6094 where = &other_input_reload_insns;
6096 case RELOAD_FOR_INPUT:
6097 where = &input_reload_insns[rl->opnum];
6099 case RELOAD_FOR_INPUT_ADDRESS:
6100 where = &input_address_reload_insns[rl->opnum];
6102 case RELOAD_FOR_INPADDR_ADDRESS:
6103 where = &inpaddr_address_reload_insns[rl->opnum];
6105 case RELOAD_FOR_OUTPUT_ADDRESS:
6106 where = &output_address_reload_insns[rl->opnum];
6108 case RELOAD_FOR_OUTADDR_ADDRESS:
6109 where = &outaddr_address_reload_insns[rl->opnum];
6111 case RELOAD_FOR_OPERAND_ADDRESS:
6112 where = &operand_reload_insns;
6114 case RELOAD_FOR_OPADDR_ADDR:
6115 where = &other_operand_reload_insns;
6117 case RELOAD_FOR_OTHER_ADDRESS:
6118 where = &other_input_address_reload_insns;
6124 push_to_sequence (*where);
6126 /* Auto-increment addresses must be reloaded in a special way. */
6127 if (rl->out && ! rl->out_reg)
6129 /* We are not going to bother supporting the case where a
6130 incremented register can't be copied directly from
6131 OLDEQUIV since this seems highly unlikely. */
6132 if (rl->secondary_in_reload >= 0)
6135 if (reload_inherited[j])
6136 oldequiv = reloadreg;
6138 old = XEXP (rl->in_reg, 0);
6140 if (optimize && GET_CODE (oldequiv) == REG
6141 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6142 && spill_reg_store[REGNO (oldequiv)]
6143 && GET_CODE (old) == REG
6144 && (dead_or_set_p (insn,
6145 spill_reg_stored_to[REGNO (oldequiv)])
6146 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6148 delete_output_reload (insn, j, REGNO (oldequiv));
6150 /* Prevent normal processing of this reload. */
6152 /* Output a special code sequence for this case. */
6153 new_spill_reg_store[REGNO (reloadreg)]
6154 = inc_for_reload (reloadreg, oldequiv, rl->out,
6158 /* If we are reloading a pseudo-register that was set by the previous
6159 insn, see if we can get rid of that pseudo-register entirely
6160 by redirecting the previous insn into our reload register. */
6162 else if (optimize && GET_CODE (old) == REG
6163 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6164 && dead_or_set_p (insn, old)
6165 /* This is unsafe if some other reload
6166 uses the same reg first. */
6167 && reload_reg_free_for_value_p (REGNO (reloadreg),
6173 rtx temp = PREV_INSN (insn);
6174 while (temp && GET_CODE (temp) == NOTE)
6175 temp = PREV_INSN (temp);
6177 && GET_CODE (temp) == INSN
6178 && GET_CODE (PATTERN (temp)) == SET
6179 && SET_DEST (PATTERN (temp)) == old
6180 /* Make sure we can access insn_operand_constraint. */
6181 && asm_noperands (PATTERN (temp)) < 0
6182 /* This is unsafe if prev insn rejects our reload reg. */
6183 && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint,
6185 /* This is unsafe if operand occurs more than once in current
6186 insn. Perhaps some occurrences aren't reloaded. */
6187 && count_occurrences (PATTERN (insn), old, 0) == 1
6188 /* Don't risk splitting a matching pair of operands. */
6189 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6191 /* Store into the reload register instead of the pseudo. */
6192 SET_DEST (PATTERN (temp)) = reloadreg;
6194 /* If the previous insn is an output reload, the source is
6195 a reload register, and its spill_reg_store entry will
6196 contain the previous destination. This is now
6198 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6199 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6201 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6202 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6205 /* If these are the only uses of the pseudo reg,
6206 pretend for GDB it lives in the reload reg we used. */
6207 if (REG_N_DEATHS (REGNO (old)) == 1
6208 && REG_N_SETS (REGNO (old)) == 1)
6210 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6211 alter_reg (REGNO (old), -1);
6217 /* We can't do that, so output an insn to load RELOADREG. */
6219 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6220 /* If we have a secondary reload, pick up the secondary register
6221 and icode, if any. If OLDEQUIV and OLD are different or
6222 if this is an in-out reload, recompute whether or not we
6223 still need a secondary register and what the icode should
6224 be. If we still need a secondary register and the class or
6225 icode is different, go back to reloading from OLD if using
6226 OLDEQUIV means that we got the wrong type of register. We
6227 cannot have different class or icode due to an in-out reload
6228 because we don't make such reloads when both the input and
6229 output need secondary reload registers. */
6231 if (! special && rl->secondary_in_reload >= 0)
6233 rtx second_reload_reg = 0;
6234 int secondary_reload = rl->secondary_in_reload;
6235 rtx real_oldequiv = oldequiv;
6238 enum insn_code icode;
6240 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6241 and similarly for OLD.
6242 See comments in get_secondary_reload in reload.c. */
6243 /* If it is a pseudo that cannot be replaced with its
6244 equivalent MEM, we must fall back to reload_in, which
6245 will have all the necessary substitutions registered.
6246 Likewise for a pseudo that can't be replaced with its
6247 equivalent constant.
6249 Take extra care for subregs of such pseudos. Note that
6250 we cannot use reg_equiv_mem in this case because it is
6251 not in the right mode. */
6254 if (GET_CODE (tmp) == SUBREG)
6255 tmp = SUBREG_REG (tmp);
6256 if (GET_CODE (tmp) == REG
6257 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6258 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6259 || reg_equiv_constant[REGNO (tmp)] != 0))
6261 if (! reg_equiv_mem[REGNO (tmp)]
6262 || num_not_at_initial_offset
6263 || GET_CODE (oldequiv) == SUBREG)
6264 real_oldequiv = rl->in;
6266 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6270 if (GET_CODE (tmp) == SUBREG)
6271 tmp = SUBREG_REG (tmp);
6272 if (GET_CODE (tmp) == REG
6273 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6274 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6275 || reg_equiv_constant[REGNO (tmp)] != 0))
6277 if (! reg_equiv_mem[REGNO (tmp)]
6278 || num_not_at_initial_offset
6279 || GET_CODE (old) == SUBREG)
6282 real_old = reg_equiv_mem[REGNO (tmp)];
6285 second_reload_reg = rld[secondary_reload].reg_rtx;
6286 icode = rl->secondary_in_icode;
6288 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6289 || (rl->in != 0 && rl->out != 0))
6291 enum reg_class new_class
6292 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6293 mode, real_oldequiv);
6295 if (new_class == NO_REGS)
6296 second_reload_reg = 0;
6299 enum insn_code new_icode;
6300 enum machine_mode new_mode;
6302 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6303 REGNO (second_reload_reg)))
6304 oldequiv = old, real_oldequiv = real_old;
6307 new_icode = reload_in_optab[(int) mode];
6308 if (new_icode != CODE_FOR_nothing
6309 && ((insn_data[(int) new_icode].operand[0].predicate
6310 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6312 || (insn_data[(int) new_icode].operand[1].predicate
6313 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6314 (real_oldequiv, mode)))))
6315 new_icode = CODE_FOR_nothing;
6317 if (new_icode == CODE_FOR_nothing)
6320 new_mode = insn_data[(int) new_icode].operand[2].mode;
6322 if (GET_MODE (second_reload_reg) != new_mode)
6324 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6326 oldequiv = old, real_oldequiv = real_old;
6329 = gen_rtx_REG (new_mode,
6330 REGNO (second_reload_reg));
6336 /* If we still need a secondary reload register, check
6337 to see if it is being used as a scratch or intermediate
6338 register and generate code appropriately. If we need
6339 a scratch register, use REAL_OLDEQUIV since the form of
6340 the insn may depend on the actual address if it is
6343 if (second_reload_reg)
6345 if (icode != CODE_FOR_nothing)
6347 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6348 second_reload_reg));
6353 /* See if we need a scratch register to load the
6354 intermediate register (a tertiary reload). */
6355 enum insn_code tertiary_icode
6356 = rld[secondary_reload].secondary_in_icode;
6358 if (tertiary_icode != CODE_FOR_nothing)
6360 rtx third_reload_reg
6361 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6363 emit_insn ((GEN_FCN (tertiary_icode)
6364 (second_reload_reg, real_oldequiv,
6365 third_reload_reg)));
6368 gen_reload (second_reload_reg, real_oldequiv,
6372 oldequiv = second_reload_reg;
6378 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6380 rtx real_oldequiv = oldequiv;
6382 if ((GET_CODE (oldequiv) == REG
6383 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6384 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6385 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6386 || (GET_CODE (oldequiv) == SUBREG
6387 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6388 && (REGNO (SUBREG_REG (oldequiv))
6389 >= FIRST_PSEUDO_REGISTER)
6390 && ((reg_equiv_memory_loc
6391 [REGNO (SUBREG_REG (oldequiv))] != 0)
6392 || (reg_equiv_constant
6393 [REGNO (SUBREG_REG (oldequiv))] != 0))))
6394 real_oldequiv = rl->in;
6395 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6399 /* End this sequence. */
6400 *where = get_insns ();
6403 /* Update reload_override_in so that delete_address_reloads_1
6404 can see the actual register usage. */
6406 reload_override_in[j] = oldequiv;
6409 /* Generate insns to for the output reload RL, which is for the insn described
6410 by CHAIN and has the number J. */
6412 emit_output_reload_insns (chain, rl, j)
6413 struct insn_chain *chain;
6417 rtx reloadreg = rl->reg_rtx;
6418 rtx insn = chain->insn;
6421 enum machine_mode mode = GET_MODE (old);
6424 if (rl->when_needed == RELOAD_OTHER)
6427 push_to_sequence (output_reload_insns[rl->opnum]);
6429 /* Determine the mode to reload in.
6430 See comments above (for input reloading). */
6432 if (mode == VOIDmode)
6434 /* VOIDmode should never happen for an output. */
6435 if (asm_noperands (PATTERN (insn)) < 0)
6436 /* It's the compiler's fault. */
6437 fatal_insn ("VOIDmode on an output", insn);
6438 error_for_asm (insn, "output operand is constant in `asm'");
6439 /* Prevent crash--use something we know is valid. */
6441 old = gen_rtx_REG (mode, REGNO (reloadreg));
6444 if (GET_MODE (reloadreg) != mode)
6445 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6447 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6449 /* If we need two reload regs, set RELOADREG to the intermediate
6450 one, since it will be stored into OLD. We might need a secondary
6451 register only for an input reload, so check again here. */
6453 if (rl->secondary_out_reload >= 0)
6457 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6458 && reg_equiv_mem[REGNO (old)] != 0)
6459 real_old = reg_equiv_mem[REGNO (old)];
6461 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6465 rtx second_reloadreg = reloadreg;
6466 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6468 /* See if RELOADREG is to be used as a scratch register
6469 or as an intermediate register. */
6470 if (rl->secondary_out_icode != CODE_FOR_nothing)
6472 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6473 (real_old, second_reloadreg, reloadreg)));
6478 /* See if we need both a scratch and intermediate reload
6481 int secondary_reload = rl->secondary_out_reload;
6482 enum insn_code tertiary_icode
6483 = rld[secondary_reload].secondary_out_icode;
6485 if (GET_MODE (reloadreg) != mode)
6486 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6488 if (tertiary_icode != CODE_FOR_nothing)
6491 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6494 /* Copy primary reload reg to secondary reload reg.
6495 (Note that these have been swapped above, then
6496 secondary reload reg to OLD using our insn. */
6498 /* If REAL_OLD is a paradoxical SUBREG, remove it
6499 and try to put the opposite SUBREG on
6501 if (GET_CODE (real_old) == SUBREG
6502 && (GET_MODE_SIZE (GET_MODE (real_old))
6503 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6504 && 0 != (tem = gen_lowpart_common
6505 (GET_MODE (SUBREG_REG (real_old)),
6507 real_old = SUBREG_REG (real_old), reloadreg = tem;
6509 gen_reload (reloadreg, second_reloadreg,
6510 rl->opnum, rl->when_needed);
6511 emit_insn ((GEN_FCN (tertiary_icode)
6512 (real_old, reloadreg, third_reloadreg)));
6517 /* Copy between the reload regs here and then to
6520 gen_reload (reloadreg, second_reloadreg,
6521 rl->opnum, rl->when_needed);
6527 /* Output the last reload insn. */
6532 /* Don't output the last reload if OLD is not the dest of
6533 INSN and is in the src and is clobbered by INSN. */
6534 if (! flag_expensive_optimizations
6535 || GET_CODE (old) != REG
6536 || !(set = single_set (insn))
6537 || rtx_equal_p (old, SET_DEST (set))
6538 || !reg_mentioned_p (old, SET_SRC (set))
6539 || !regno_clobbered_p (REGNO (old), insn, rl->mode))
6540 gen_reload (old, reloadreg, rl->opnum,
6544 /* Look at all insns we emitted, just to be safe. */
6545 for (p = get_insns (); p; p = NEXT_INSN (p))
6548 rtx pat = PATTERN (p);
6550 /* If this output reload doesn't come from a spill reg,
6551 clear any memory of reloaded copies of the pseudo reg.
6552 If this output reload comes from a spill reg,
6553 reg_has_output_reload will make this do nothing. */
6554 note_stores (pat, forget_old_reloads_1, NULL);
6556 if (reg_mentioned_p (rl->reg_rtx, pat))
6558 rtx set = single_set (insn);
6559 if (reload_spill_index[j] < 0
6561 && SET_SRC (set) == rl->reg_rtx)
6563 int src = REGNO (SET_SRC (set));
6565 reload_spill_index[j] = src;
6566 SET_HARD_REG_BIT (reg_is_output_reload, src);
6567 if (find_regno_note (insn, REG_DEAD, src))
6568 SET_HARD_REG_BIT (reg_reloaded_died, src);
6570 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6572 int s = rl->secondary_out_reload;
6573 set = single_set (p);
6574 /* If this reload copies only to the secondary reload
6575 register, the secondary reload does the actual
6577 if (s >= 0 && set == NULL_RTX)
6578 /* We can't tell what function the secondary reload
6579 has and where the actual store to the pseudo is
6580 made; leave new_spill_reg_store alone. */
6583 && SET_SRC (set) == rl->reg_rtx
6584 && SET_DEST (set) == rld[s].reg_rtx)
6586 /* Usually the next instruction will be the
6587 secondary reload insn; if we can confirm
6588 that it is, setting new_spill_reg_store to
6589 that insn will allow an extra optimization. */
6590 rtx s_reg = rld[s].reg_rtx;
6591 rtx next = NEXT_INSN (p);
6592 rld[s].out = rl->out;
6593 rld[s].out_reg = rl->out_reg;
6594 set = single_set (next);
6595 if (set && SET_SRC (set) == s_reg
6596 && ! new_spill_reg_store[REGNO (s_reg)])
6598 SET_HARD_REG_BIT (reg_is_output_reload,
6600 new_spill_reg_store[REGNO (s_reg)] = next;
6604 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6609 if (rl->when_needed == RELOAD_OTHER)
6611 emit_insns (other_output_reload_insns[rl->opnum]);
6612 other_output_reload_insns[rl->opnum] = get_insns ();
6615 output_reload_insns[rl->opnum] = get_insns ();
6620 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6621 and has the number J. */
6623 do_input_reload (chain, rl, j)
6624 struct insn_chain *chain;
6628 int expect_occurrences = 1;
6629 rtx insn = chain->insn;
6630 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6631 ? rl->in_reg : rl->in);
6634 /* AUTO_INC reloads need to be handled even if inherited. We got an
6635 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6636 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6637 && ! rtx_equal_p (rl->reg_rtx, old)
6638 && rl->reg_rtx != 0)
6639 emit_input_reload_insns (chain, rld + j, old, j);
6641 /* When inheriting a wider reload, we have a MEM in rl->in,
6642 e.g. inheriting a SImode output reload for
6643 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6644 if (optimize && reload_inherited[j] && rl->in
6645 && GET_CODE (rl->in) == MEM
6646 && GET_CODE (rl->in_reg) == MEM
6647 && reload_spill_index[j] >= 0
6648 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6651 = count_occurrences (PATTERN (insn), rl->in, 0) == 1 ? 0 : -1;
6652 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6655 /* If we are reloading a register that was recently stored in with an
6656 output-reload, see if we can prove there was
6657 actually no need to store the old value in it. */
6660 && (reload_inherited[j] || reload_override_in[j])
6662 && GET_CODE (rl->reg_rtx) == REG
6663 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6665 /* There doesn't seem to be any reason to restrict this to pseudos
6666 and doing so loses in the case where we are copying from a
6667 register of the wrong class. */
6668 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6669 >= FIRST_PSEUDO_REGISTER)
6671 /* The insn might have already some references to stackslots
6672 replaced by MEMs, while reload_out_reg still names the
6674 && (dead_or_set_p (insn,
6675 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6676 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6678 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6681 /* Do output reloading for reload RL, which is for the insn described by
6682 CHAIN and has the number J.
6683 ??? At some point we need to support handling output reloads of
6684 JUMP_INSNs or insns that set cc0. */
6686 do_output_reload (chain, rl, j)
6687 struct insn_chain *chain;
6692 rtx insn = chain->insn;
6693 /* If this is an output reload that stores something that is
6694 not loaded in this same reload, see if we can eliminate a previous
6696 rtx pseudo = rl->out_reg;
6699 && GET_CODE (pseudo) == REG
6700 && ! rtx_equal_p (rl->in_reg, pseudo)
6701 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6702 && reg_last_reload_reg[REGNO (pseudo)])
6704 int pseudo_no = REGNO (pseudo);
6705 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6707 /* We don't need to test full validity of last_regno for
6708 inherit here; we only want to know if the store actually
6709 matches the pseudo. */
6710 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6711 && reg_reloaded_contents[last_regno] == pseudo_no
6712 && spill_reg_store[last_regno]
6713 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6714 delete_output_reload (insn, j, last_regno);
6719 || rl->reg_rtx == old
6720 || rl->reg_rtx == 0)
6723 /* An output operand that dies right away does need a reload,
6724 but need not be copied from it. Show the new location in the
6726 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6727 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6729 XEXP (note, 0) = rl->reg_rtx;
6732 /* Likewise for a SUBREG of an operand that dies. */
6733 else if (GET_CODE (old) == SUBREG
6734 && GET_CODE (SUBREG_REG (old)) == REG
6735 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6738 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6742 else if (GET_CODE (old) == SCRATCH)
6743 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6744 but we don't want to make an output reload. */
6747 /* If is a JUMP_INSN, we can't support output reloads yet. */
6748 if (GET_CODE (insn) == JUMP_INSN)
6751 emit_output_reload_insns (chain, rld + j, j);
6754 /* Output insns to reload values in and out of the chosen reload regs. */
6757 emit_reload_insns (chain)
6758 struct insn_chain *chain;
6760 rtx insn = chain->insn;
6763 rtx following_insn = NEXT_INSN (insn);
6764 rtx before_insn = PREV_INSN (insn);
6766 CLEAR_HARD_REG_SET (reg_reloaded_died);
6768 for (j = 0; j < reload_n_operands; j++)
6769 input_reload_insns[j] = input_address_reload_insns[j]
6770 = inpaddr_address_reload_insns[j]
6771 = output_reload_insns[j] = output_address_reload_insns[j]
6772 = outaddr_address_reload_insns[j]
6773 = other_output_reload_insns[j] = 0;
6774 other_input_address_reload_insns = 0;
6775 other_input_reload_insns = 0;
6776 operand_reload_insns = 0;
6777 other_operand_reload_insns = 0;
6779 /* Dump reloads into the dump file. */
6782 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6783 debug_reload_to_stream (rtl_dump_file);
6786 /* Now output the instructions to copy the data into and out of the
6787 reload registers. Do these in the order that the reloads were reported,
6788 since reloads of base and index registers precede reloads of operands
6789 and the operands may need the base and index registers reloaded. */
6791 for (j = 0; j < n_reloads; j++)
6794 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6795 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6797 do_input_reload (chain, rld + j, j);
6798 do_output_reload (chain, rld + j, j);
6801 /* Now write all the insns we made for reloads in the order expected by
6802 the allocation functions. Prior to the insn being reloaded, we write
6803 the following reloads:
6805 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6807 RELOAD_OTHER reloads.
6809 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6810 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6811 RELOAD_FOR_INPUT reload for the operand.
6813 RELOAD_FOR_OPADDR_ADDRS reloads.
6815 RELOAD_FOR_OPERAND_ADDRESS reloads.
6817 After the insn being reloaded, we write the following:
6819 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6820 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6821 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6822 reloads for the operand. The RELOAD_OTHER output reloads are
6823 output in descending order by reload number. */
6825 emit_insns_before (other_input_address_reload_insns, insn);
6826 emit_insns_before (other_input_reload_insns, insn);
6828 for (j = 0; j < reload_n_operands; j++)
6830 emit_insns_before (inpaddr_address_reload_insns[j], insn);
6831 emit_insns_before (input_address_reload_insns[j], insn);
6832 emit_insns_before (input_reload_insns[j], insn);
6835 emit_insns_before (other_operand_reload_insns, insn);
6836 emit_insns_before (operand_reload_insns, insn);
6838 for (j = 0; j < reload_n_operands; j++)
6840 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
6841 emit_insns_before (output_address_reload_insns[j], following_insn);
6842 emit_insns_before (output_reload_insns[j], following_insn);
6843 emit_insns_before (other_output_reload_insns[j], following_insn);
6846 /* Keep basic block info up to date. */
6849 if (BLOCK_HEAD (chain->block) == insn)
6850 BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
6851 if (BLOCK_END (chain->block) == insn)
6852 BLOCK_END (chain->block) = PREV_INSN (following_insn);
6855 /* For all the spill regs newly reloaded in this instruction,
6856 record what they were reloaded from, so subsequent instructions
6857 can inherit the reloads.
6859 Update spill_reg_store for the reloads of this insn.
6860 Copy the elements that were updated in the loop above. */
6862 for (j = 0; j < n_reloads; j++)
6864 register int r = reload_order[j];
6865 register int i = reload_spill_index[r];
6867 /* If this is a non-inherited input reload from a pseudo, we must
6868 clear any memory of a previous store to the same pseudo. Only do
6869 something if there will not be an output reload for the pseudo
6871 if (rld[r].in_reg != 0
6872 && ! (reload_inherited[r] || reload_override_in[r]))
6874 rtx reg = rld[r].in_reg;
6876 if (GET_CODE (reg) == SUBREG)
6877 reg = SUBREG_REG (reg);
6879 if (GET_CODE (reg) == REG
6880 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
6881 && ! reg_has_output_reload[REGNO (reg)])
6883 int nregno = REGNO (reg);
6885 if (reg_last_reload_reg[nregno])
6887 int last_regno = REGNO (reg_last_reload_reg[nregno]);
6889 if (reg_reloaded_contents[last_regno] == nregno)
6890 spill_reg_store[last_regno] = 0;
6895 /* I is nonneg if this reload used a register.
6896 If rld[r].reg_rtx is 0, this is an optional reload
6897 that we opted to ignore. */
6899 if (i >= 0 && rld[r].reg_rtx != 0)
6901 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
6903 int part_reaches_end = 0;
6904 int all_reaches_end = 1;
6906 /* For a multi register reload, we need to check if all or part
6907 of the value lives to the end. */
6908 for (k = 0; k < nr; k++)
6910 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
6911 rld[r].when_needed))
6912 part_reaches_end = 1;
6914 all_reaches_end = 0;
6917 /* Ignore reloads that don't reach the end of the insn in
6919 if (all_reaches_end)
6921 /* First, clear out memory of what used to be in this spill reg.
6922 If consecutive registers are used, clear them all. */
6924 for (k = 0; k < nr; k++)
6925 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
6927 /* Maybe the spill reg contains a copy of reload_out. */
6929 && (GET_CODE (rld[r].out) == REG
6933 || GET_CODE (rld[r].out_reg) == REG))
6935 rtx out = (GET_CODE (rld[r].out) == REG
6939 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
6940 register int nregno = REGNO (out);
6941 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6942 : HARD_REGNO_NREGS (nregno,
6943 GET_MODE (rld[r].reg_rtx)));
6945 spill_reg_store[i] = new_spill_reg_store[i];
6946 spill_reg_stored_to[i] = out;
6947 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
6949 /* If NREGNO is a hard register, it may occupy more than
6950 one register. If it does, say what is in the
6951 rest of the registers assuming that both registers
6952 agree on how many words the object takes. If not,
6953 invalidate the subsequent registers. */
6955 if (nregno < FIRST_PSEUDO_REGISTER)
6956 for (k = 1; k < nnr; k++)
6957 reg_last_reload_reg[nregno + k]
6959 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
6960 REGNO (rld[r].reg_rtx) + k)
6963 /* Now do the inverse operation. */
6964 for (k = 0; k < nr; k++)
6966 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
6967 reg_reloaded_contents[i + k]
6968 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
6971 reg_reloaded_insn[i + k] = insn;
6972 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
6976 /* Maybe the spill reg contains a copy of reload_in. Only do
6977 something if there will not be an output reload for
6978 the register being reloaded. */
6979 else if (rld[r].out_reg == 0
6981 && ((GET_CODE (rld[r].in) == REG
6982 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
6983 && ! reg_has_output_reload[REGNO (rld[r].in)])
6984 || (GET_CODE (rld[r].in_reg) == REG
6985 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
6986 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
6988 register int nregno;
6991 if (GET_CODE (rld[r].in) == REG
6992 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
6993 nregno = REGNO (rld[r].in);
6994 else if (GET_CODE (rld[r].in_reg) == REG)
6995 nregno = REGNO (rld[r].in_reg);
6997 nregno = REGNO (XEXP (rld[r].in_reg, 0));
6999 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7000 : HARD_REGNO_NREGS (nregno,
7001 GET_MODE (rld[r].reg_rtx)));
7003 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7005 if (nregno < FIRST_PSEUDO_REGISTER)
7006 for (k = 1; k < nnr; k++)
7007 reg_last_reload_reg[nregno + k]
7009 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7010 REGNO (rld[r].reg_rtx) + k)
7013 /* Unless we inherited this reload, show we haven't
7014 recently done a store.
7015 Previous stores of inherited auto_inc expressions
7016 also have to be discarded. */
7017 if (! reload_inherited[r]
7018 || (rld[r].out && ! rld[r].out_reg))
7019 spill_reg_store[i] = 0;
7021 for (k = 0; k < nr; k++)
7023 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7024 reg_reloaded_contents[i + k]
7025 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7028 reg_reloaded_insn[i + k] = insn;
7029 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7034 /* However, if part of the reload reaches the end, then we must
7035 invalidate the old info for the part that survives to the end. */
7036 else if (part_reaches_end)
7038 for (k = 0; k < nr; k++)
7039 if (reload_reg_reaches_end_p (i + k,
7041 rld[r].when_needed))
7042 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7046 /* The following if-statement was #if 0'd in 1.34 (or before...).
7047 It's reenabled in 1.35 because supposedly nothing else
7048 deals with this problem. */
7050 /* If a register gets output-reloaded from a non-spill register,
7051 that invalidates any previous reloaded copy of it.
7052 But forget_old_reloads_1 won't get to see it, because
7053 it thinks only about the original insn. So invalidate it here. */
7054 if (i < 0 && rld[r].out != 0
7055 && (GET_CODE (rld[r].out) == REG
7056 || (GET_CODE (rld[r].out) == MEM
7057 && GET_CODE (rld[r].out_reg) == REG)))
7059 rtx out = (GET_CODE (rld[r].out) == REG
7060 ? rld[r].out : rld[r].out_reg);
7061 register int nregno = REGNO (out);
7062 if (nregno >= FIRST_PSEUDO_REGISTER)
7064 rtx src_reg, store_insn = NULL_RTX;
7066 reg_last_reload_reg[nregno] = 0;
7068 /* If we can find a hard register that is stored, record
7069 the storing insn so that we may delete this insn with
7070 delete_output_reload. */
7071 src_reg = rld[r].reg_rtx;
7073 /* If this is an optional reload, try to find the source reg
7074 from an input reload. */
7077 rtx set = single_set (insn);
7078 if (set && SET_DEST (set) == rld[r].out)
7082 src_reg = SET_SRC (set);
7084 for (k = 0; k < n_reloads; k++)
7086 if (rld[k].in == src_reg)
7088 src_reg = rld[k].reg_rtx;
7095 store_insn = new_spill_reg_store[REGNO (src_reg)];
7096 if (src_reg && GET_CODE (src_reg) == REG
7097 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7099 int src_regno = REGNO (src_reg);
7100 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7101 /* The place where to find a death note varies with
7102 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7103 necessarily checked exactly in the code that moves
7104 notes, so just check both locations. */
7105 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7107 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7110 spill_reg_store[src_regno + nr] = store_insn;
7111 spill_reg_stored_to[src_regno + nr] = out;
7112 reg_reloaded_contents[src_regno + nr] = nregno;
7113 reg_reloaded_insn[src_regno + nr] = store_insn;
7114 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7115 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7116 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7118 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7120 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7122 reg_last_reload_reg[nregno] = src_reg;
7127 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7129 while (num_regs-- > 0)
7130 reg_last_reload_reg[nregno + num_regs] = 0;
7134 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7137 /* Emit code to perform a reload from IN (which may be a reload register) to
7138 OUT (which may also be a reload register). IN or OUT is from operand
7139 OPNUM with reload type TYPE.
7141 Returns first insn emitted. */
7144 gen_reload (out, in, opnum, type)
7148 enum reload_type type;
7150 rtx last = get_last_insn ();
7153 /* If IN is a paradoxical SUBREG, remove it and try to put the
7154 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7155 if (GET_CODE (in) == SUBREG
7156 && (GET_MODE_SIZE (GET_MODE (in))
7157 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7158 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7159 in = SUBREG_REG (in), out = tem;
7160 else if (GET_CODE (out) == SUBREG
7161 && (GET_MODE_SIZE (GET_MODE (out))
7162 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7163 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7164 out = SUBREG_REG (out), in = tem;
7166 /* How to do this reload can get quite tricky. Normally, we are being
7167 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7168 register that didn't get a hard register. In that case we can just
7169 call emit_move_insn.
7171 We can also be asked to reload a PLUS that adds a register or a MEM to
7172 another register, constant or MEM. This can occur during frame pointer
7173 elimination and while reloading addresses. This case is handled by
7174 trying to emit a single insn to perform the add. If it is not valid,
7175 we use a two insn sequence.
7177 Finally, we could be called to handle an 'o' constraint by putting
7178 an address into a register. In that case, we first try to do this
7179 with a named pattern of "reload_load_address". If no such pattern
7180 exists, we just emit a SET insn and hope for the best (it will normally
7181 be valid on machines that use 'o').
7183 This entire process is made complex because reload will never
7184 process the insns we generate here and so we must ensure that
7185 they will fit their constraints and also by the fact that parts of
7186 IN might be being reloaded separately and replaced with spill registers.
7187 Because of this, we are, in some sense, just guessing the right approach
7188 here. The one listed above seems to work.
7190 ??? At some point, this whole thing needs to be rethought. */
7192 if (GET_CODE (in) == PLUS
7193 && (GET_CODE (XEXP (in, 0)) == REG
7194 || GET_CODE (XEXP (in, 0)) == SUBREG
7195 || GET_CODE (XEXP (in, 0)) == MEM)
7196 && (GET_CODE (XEXP (in, 1)) == REG
7197 || GET_CODE (XEXP (in, 1)) == SUBREG
7198 || CONSTANT_P (XEXP (in, 1))
7199 || GET_CODE (XEXP (in, 1)) == MEM))
7201 /* We need to compute the sum of a register or a MEM and another
7202 register, constant, or MEM, and put it into the reload
7203 register. The best possible way of doing this is if the machine
7204 has a three-operand ADD insn that accepts the required operands.
7206 The simplest approach is to try to generate such an insn and see if it
7207 is recognized and matches its constraints. If so, it can be used.
7209 It might be better not to actually emit the insn unless it is valid,
7210 but we need to pass the insn as an operand to `recog' and
7211 `extract_insn' and it is simpler to emit and then delete the insn if
7212 not valid than to dummy things up. */
7214 rtx op0, op1, tem, insn;
7217 op0 = find_replacement (&XEXP (in, 0));
7218 op1 = find_replacement (&XEXP (in, 1));
7220 /* Since constraint checking is strict, commutativity won't be
7221 checked, so we need to do that here to avoid spurious failure
7222 if the add instruction is two-address and the second operand
7223 of the add is the same as the reload reg, which is frequently
7224 the case. If the insn would be A = B + A, rearrange it so
7225 it will be A = A + B as constrain_operands expects. */
7227 if (GET_CODE (XEXP (in, 1)) == REG
7228 && REGNO (out) == REGNO (XEXP (in, 1)))
7229 tem = op0, op0 = op1, op1 = tem;
7231 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7232 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7234 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7235 code = recog_memoized (insn);
7239 extract_insn (insn);
7240 /* We want constrain operands to treat this insn strictly in
7241 its validity determination, i.e., the way it would after reload
7243 if (constrain_operands (1))
7247 delete_insns_since (last);
7249 /* If that failed, we must use a conservative two-insn sequence.
7251 Use a move to copy one operand into the reload register. Prefer
7252 to reload a constant, MEM or pseudo since the move patterns can
7253 handle an arbitrary operand. If OP1 is not a constant, MEM or
7254 pseudo and OP1 is not a valid operand for an add instruction, then
7257 After reloading one of the operands into the reload register, add
7258 the reload register to the output register.
7260 If there is another way to do this for a specific machine, a
7261 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7264 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7266 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7267 || (GET_CODE (op1) == REG
7268 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7269 || (code != CODE_FOR_nothing
7270 && ! ((*insn_data[code].operand[2].predicate)
7271 (op1, insn_data[code].operand[2].mode))))
7272 tem = op0, op0 = op1, op1 = tem;
7274 gen_reload (out, op0, opnum, type);
7276 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7277 This fixes a problem on the 32K where the stack pointer cannot
7278 be used as an operand of an add insn. */
7280 if (rtx_equal_p (op0, op1))
7283 insn = emit_insn (gen_add2_insn (out, op1));
7285 /* If that failed, copy the address register to the reload register.
7286 Then add the constant to the reload register. */
7288 code = recog_memoized (insn);
7292 extract_insn (insn);
7293 /* We want constrain operands to treat this insn strictly in
7294 its validity determination, i.e., the way it would after reload
7296 if (constrain_operands (1))
7298 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7300 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7305 delete_insns_since (last);
7307 gen_reload (out, op1, opnum, type);
7308 insn = emit_insn (gen_add2_insn (out, op0));
7309 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7312 #ifdef SECONDARY_MEMORY_NEEDED
7313 /* If we need a memory location to do the move, do it that way. */
7314 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7315 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7316 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7317 REGNO_REG_CLASS (REGNO (out)),
7320 /* Get the memory to use and rewrite both registers to its mode. */
7321 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7323 if (GET_MODE (loc) != GET_MODE (out))
7324 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7326 if (GET_MODE (loc) != GET_MODE (in))
7327 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7329 gen_reload (loc, in, opnum, type);
7330 gen_reload (out, loc, opnum, type);
7334 /* If IN is a simple operand, use gen_move_insn. */
7335 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7336 emit_insn (gen_move_insn (out, in));
7338 #ifdef HAVE_reload_load_address
7339 else if (HAVE_reload_load_address)
7340 emit_insn (gen_reload_load_address (out, in));
7343 /* Otherwise, just write (set OUT IN) and hope for the best. */
7345 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7347 /* Return the first insn emitted.
7348 We can not just return get_last_insn, because there may have
7349 been multiple instructions emitted. Also note that gen_move_insn may
7350 emit more than one insn itself, so we can not assume that there is one
7351 insn emitted per emit_insn_before call. */
7353 return last ? NEXT_INSN (last) : get_insns ();
7356 /* Delete a previously made output-reload
7357 whose result we now believe is not needed.
7358 First we double-check.
7360 INSN is the insn now being processed.
7361 LAST_RELOAD_REG is the hard register number for which we want to delete
7362 the last output reload.
7363 J is the reload-number that originally used REG. The caller has made
7364 certain that reload J doesn't use REG any longer for input. */
7367 delete_output_reload (insn, j, last_reload_reg)
7370 int last_reload_reg;
7372 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7373 rtx reg = spill_reg_stored_to[last_reload_reg];
7376 int n_inherited = 0;
7380 /* Get the raw pseudo-register referred to. */
7382 while (GET_CODE (reg) == SUBREG)
7383 reg = SUBREG_REG (reg);
7384 substed = reg_equiv_memory_loc[REGNO (reg)];
7386 /* This is unsafe if the operand occurs more often in the current
7387 insn than it is inherited. */
7388 for (k = n_reloads - 1; k >= 0; k--)
7390 rtx reg2 = rld[k].in;
7393 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7394 reg2 = rld[k].in_reg;
7396 if (rld[k].out && ! rld[k].out_reg)
7397 reg2 = XEXP (rld[k].in_reg, 0);
7399 while (GET_CODE (reg2) == SUBREG)
7400 reg2 = SUBREG_REG (reg2);
7401 if (rtx_equal_p (reg2, reg))
7403 if (reload_inherited[k] || reload_override_in[k] || k == j)
7406 reg2 = rld[k].out_reg;
7409 while (GET_CODE (reg2) == SUBREG)
7410 reg2 = XEXP (reg2, 0);
7411 if (rtx_equal_p (reg2, reg))
7418 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7420 n_occurrences += count_occurrences (PATTERN (insn), substed, 0);
7421 if (n_occurrences > n_inherited)
7424 /* If the pseudo-reg we are reloading is no longer referenced
7425 anywhere between the store into it and here,
7426 and no jumps or labels intervene, then the value can get
7427 here through the reload reg alone.
7428 Otherwise, give up--return. */
7429 for (i1 = NEXT_INSN (output_reload_insn);
7430 i1 != insn; i1 = NEXT_INSN (i1))
7432 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7434 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7435 && reg_mentioned_p (reg, PATTERN (i1)))
7437 /* If this is USE in front of INSN, we only have to check that
7438 there are no more references than accounted for by inheritance. */
7439 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7441 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7442 i1 = NEXT_INSN (i1);
7444 if (n_occurrences <= n_inherited && i1 == insn)
7450 /* The caller has already checked that REG dies or is set in INSN.
7451 It has also checked that we are optimizing, and thus some inaccurancies
7452 in the debugging information are acceptable.
7453 So we could just delete output_reload_insn.
7454 But in some cases we can improve the debugging information without
7455 sacrificing optimization - maybe even improving the code:
7456 See if the pseudo reg has been completely replaced
7457 with reload regs. If so, delete the store insn
7458 and forget we had a stack slot for the pseudo. */
7459 if (rld[j].out != rld[j].in
7460 && REG_N_DEATHS (REGNO (reg)) == 1
7461 && REG_N_SETS (REGNO (reg)) == 1
7462 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7463 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7467 /* We know that it was used only between here
7468 and the beginning of the current basic block.
7469 (We also know that the last use before INSN was
7470 the output reload we are thinking of deleting, but never mind that.)
7471 Search that range; see if any ref remains. */
7472 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7474 rtx set = single_set (i2);
7476 /* Uses which just store in the pseudo don't count,
7477 since if they are the only uses, they are dead. */
7478 if (set != 0 && SET_DEST (set) == reg)
7480 if (GET_CODE (i2) == CODE_LABEL
7481 || GET_CODE (i2) == JUMP_INSN)
7483 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7484 && reg_mentioned_p (reg, PATTERN (i2)))
7486 /* Some other ref remains; just delete the output reload we
7488 delete_address_reloads (output_reload_insn, insn);
7489 PUT_CODE (output_reload_insn, NOTE);
7490 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7491 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7496 /* Delete the now-dead stores into this pseudo. */
7497 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7499 rtx set = single_set (i2);
7501 if (set != 0 && SET_DEST (set) == reg)
7503 delete_address_reloads (i2, insn);
7504 /* This might be a basic block head,
7505 thus don't use delete_insn. */
7506 PUT_CODE (i2, NOTE);
7507 NOTE_SOURCE_FILE (i2) = 0;
7508 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7510 if (GET_CODE (i2) == CODE_LABEL
7511 || GET_CODE (i2) == JUMP_INSN)
7515 /* For the debugging info,
7516 say the pseudo lives in this reload reg. */
7517 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7518 alter_reg (REGNO (reg), -1);
7520 delete_address_reloads (output_reload_insn, insn);
7521 PUT_CODE (output_reload_insn, NOTE);
7522 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7523 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7527 /* We are going to delete DEAD_INSN. Recursively delete loads of
7528 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7529 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7531 delete_address_reloads (dead_insn, current_insn)
7532 rtx dead_insn, current_insn;
7534 rtx set = single_set (dead_insn);
7535 rtx set2, dst, prev, next;
7538 rtx dst = SET_DEST (set);
7539 if (GET_CODE (dst) == MEM)
7540 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7542 /* If we deleted the store from a reloaded post_{in,de}c expression,
7543 we can delete the matching adds. */
7544 prev = PREV_INSN (dead_insn);
7545 next = NEXT_INSN (dead_insn);
7546 if (! prev || ! next)
7548 set = single_set (next);
7549 set2 = single_set (prev);
7551 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7552 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7553 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7555 dst = SET_DEST (set);
7556 if (! rtx_equal_p (dst, SET_DEST (set2))
7557 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7558 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7559 || (INTVAL (XEXP (SET_SRC (set), 1))
7560 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7566 /* Subfunction of delete_address_reloads: process registers found in X. */
7568 delete_address_reloads_1 (dead_insn, x, current_insn)
7569 rtx dead_insn, x, current_insn;
7571 rtx prev, set, dst, i2;
7573 enum rtx_code code = GET_CODE (x);
7577 const char *fmt = GET_RTX_FORMAT (code);
7578 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7581 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7582 else if (fmt[i] == 'E')
7584 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7585 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7592 if (spill_reg_order[REGNO (x)] < 0)
7595 /* Scan backwards for the insn that sets x. This might be a way back due
7597 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7599 code = GET_CODE (prev);
7600 if (code == CODE_LABEL || code == JUMP_INSN)
7602 if (GET_RTX_CLASS (code) != 'i')
7604 if (reg_set_p (x, PATTERN (prev)))
7606 if (reg_referenced_p (x, PATTERN (prev)))
7609 if (! prev || INSN_UID (prev) < reload_first_uid)
7611 /* Check that PREV only sets the reload register. */
7612 set = single_set (prev);
7615 dst = SET_DEST (set);
7616 if (GET_CODE (dst) != REG
7617 || ! rtx_equal_p (dst, x))
7619 if (! reg_set_p (dst, PATTERN (dead_insn)))
7621 /* Check if DST was used in a later insn -
7622 it might have been inherited. */
7623 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7625 if (GET_CODE (i2) == CODE_LABEL)
7629 if (reg_referenced_p (dst, PATTERN (i2)))
7631 /* If there is a reference to the register in the current insn,
7632 it might be loaded in a non-inherited reload. If no other
7633 reload uses it, that means the register is set before
7635 if (i2 == current_insn)
7637 for (j = n_reloads - 1; j >= 0; j--)
7638 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7639 || reload_override_in[j] == dst)
7641 for (j = n_reloads - 1; j >= 0; j--)
7642 if (rld[j].in && rld[j].reg_rtx == dst)
7649 if (GET_CODE (i2) == JUMP_INSN)
7651 /* If DST is still live at CURRENT_INSN, check if it is used for
7652 any reload. Note that even if CURRENT_INSN sets DST, we still
7653 have to check the reloads. */
7654 if (i2 == current_insn)
7656 for (j = n_reloads - 1; j >= 0; j--)
7657 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7658 || reload_override_in[j] == dst)
7660 /* ??? We can't finish the loop here, because dst might be
7661 allocated to a pseudo in this block if no reload in this
7662 block needs any of the clsses containing DST - see
7663 spill_hard_reg. There is no easy way to tell this, so we
7664 have to scan till the end of the basic block. */
7666 if (reg_set_p (dst, PATTERN (i2)))
7670 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7671 reg_reloaded_contents[REGNO (dst)] = -1;
7672 /* Can't use delete_insn here because PREV might be a basic block head. */
7673 PUT_CODE (prev, NOTE);
7674 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
7675 NOTE_SOURCE_FILE (prev) = 0;
7678 /* Output reload-insns to reload VALUE into RELOADREG.
7679 VALUE is an autoincrement or autodecrement RTX whose operand
7680 is a register or memory location;
7681 so reloading involves incrementing that location.
7682 IN is either identical to VALUE, or some cheaper place to reload from.
7684 INC_AMOUNT is the number to increment or decrement by (always positive).
7685 This cannot be deduced from VALUE.
7687 Return the instruction that stores into RELOADREG. */
7690 inc_for_reload (reloadreg, in, value, inc_amount)
7695 /* REG or MEM to be copied and incremented. */
7696 rtx incloc = XEXP (value, 0);
7697 /* Nonzero if increment after copying. */
7698 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7704 rtx real_in = in == value ? XEXP (in, 0) : in;
7706 /* No hard register is equivalent to this register after
7707 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7708 we could inc/dec that register as well (maybe even using it for
7709 the source), but I'm not sure it's worth worrying about. */
7710 if (GET_CODE (incloc) == REG)
7711 reg_last_reload_reg[REGNO (incloc)] = 0;
7713 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7714 inc_amount = -inc_amount;
7716 inc = GEN_INT (inc_amount);
7718 /* If this is post-increment, first copy the location to the reload reg. */
7719 if (post && real_in != reloadreg)
7720 emit_insn (gen_move_insn (reloadreg, real_in));
7724 /* See if we can directly increment INCLOC. Use a method similar to
7725 that in gen_reload. */
7727 last = get_last_insn ();
7728 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7729 gen_rtx_PLUS (GET_MODE (incloc),
7732 code = recog_memoized (add_insn);
7735 extract_insn (add_insn);
7736 if (constrain_operands (1))
7738 /* If this is a pre-increment and we have incremented the value
7739 where it lives, copy the incremented value to RELOADREG to
7740 be used as an address. */
7743 emit_insn (gen_move_insn (reloadreg, incloc));
7748 delete_insns_since (last);
7751 /* If couldn't do the increment directly, must increment in RELOADREG.
7752 The way we do this depends on whether this is pre- or post-increment.
7753 For pre-increment, copy INCLOC to the reload register, increment it
7754 there, then save back. */
7758 if (in != reloadreg)
7759 emit_insn (gen_move_insn (reloadreg, real_in));
7760 emit_insn (gen_add2_insn (reloadreg, inc));
7761 store = emit_insn (gen_move_insn (incloc, reloadreg));
7766 Because this might be a jump insn or a compare, and because RELOADREG
7767 may not be available after the insn in an input reload, we must do
7768 the incrementation before the insn being reloaded for.
7770 We have already copied IN to RELOADREG. Increment the copy in
7771 RELOADREG, save that back, then decrement RELOADREG so it has
7772 the original value. */
7774 emit_insn (gen_add2_insn (reloadreg, inc));
7775 store = emit_insn (gen_move_insn (incloc, reloadreg));
7776 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7782 /* Return 1 if we are certain that the constraint-string STRING allows
7783 the hard register REG. Return 0 if we can't be sure of this. */
7786 constraint_accepts_reg_p (string, reg)
7791 int regno = true_regnum (reg);
7794 /* Initialize for first alternative. */
7796 /* Check that each alternative contains `g' or `r'. */
7798 switch (c = *string++)
7801 /* If an alternative lacks `g' or `r', we lose. */
7804 /* If an alternative lacks `g' or `r', we lose. */
7807 /* Initialize for next alternative. */
7812 /* Any general reg wins for this alternative. */
7813 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7817 /* Any reg in specified class wins for this alternative. */
7819 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7821 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
7827 /* INSN is a no-op; delete it.
7828 If this sets the return value of the function, we must keep a USE around,
7829 in case this is in a different basic block than the final USE. Otherwise,
7830 we could loose important register lifeness information on
7831 SMALL_REGISTER_CLASSES machines, where return registers might be used as
7832 spills: subsequent passes assume that spill registers are dead at the end
7834 VALUE must be the return value in such a case, NULL otherwise. */
7836 reload_cse_delete_noop_set (insn, value)
7841 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
7842 INSN_CODE (insn) = -1;
7843 REG_NOTES (insn) = NULL_RTX;
7847 PUT_CODE (insn, NOTE);
7848 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
7849 NOTE_SOURCE_FILE (insn) = 0;
7853 /* See whether a single set SET is a noop. */
7855 reload_cse_noop_set_p (set)
7858 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
7861 /* Try to simplify INSN. */
7863 reload_cse_simplify (insn)
7866 rtx body = PATTERN (insn);
7868 if (GET_CODE (body) == SET)
7871 if (reload_cse_noop_set_p (body))
7873 rtx value = SET_DEST (body);
7874 if (! REG_FUNCTION_VALUE_P (SET_DEST (body)))
7876 reload_cse_delete_noop_set (insn, value);
7880 /* It's not a no-op, but we can try to simplify it. */
7881 count += reload_cse_simplify_set (body, insn);
7884 apply_change_group ();
7886 reload_cse_simplify_operands (insn);
7888 else if (GET_CODE (body) == PARALLEL)
7892 rtx value = NULL_RTX;
7894 /* If every action in a PARALLEL is a noop, we can delete
7895 the entire PARALLEL. */
7896 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
7898 rtx part = XVECEXP (body, 0, i);
7899 if (GET_CODE (part) == SET)
7901 if (! reload_cse_noop_set_p (part))
7903 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
7907 value = SET_DEST (part);
7910 else if (GET_CODE (part) != CLOBBER)
7916 reload_cse_delete_noop_set (insn, value);
7917 /* We're done with this insn. */
7921 /* It's not a no-op, but we can try to simplify it. */
7922 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
7923 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
7924 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
7927 apply_change_group ();
7929 reload_cse_simplify_operands (insn);
7933 /* Do a very simple CSE pass over the hard registers.
7935 This function detects no-op moves where we happened to assign two
7936 different pseudo-registers to the same hard register, and then
7937 copied one to the other. Reload will generate a useless
7938 instruction copying a register to itself.
7940 This function also detects cases where we load a value from memory
7941 into two different registers, and (if memory is more expensive than
7942 registers) changes it to simply copy the first register into the
7945 Another optimization is performed that scans the operands of each
7946 instruction to see whether the value is already available in a
7947 hard register. It then replaces the operand with the hard register
7948 if possible, much like an optional reload would. */
7951 reload_cse_regs_1 (first)
7957 init_alias_analysis ();
7959 for (insn = first; insn; insn = NEXT_INSN (insn))
7962 reload_cse_simplify (insn);
7964 cselib_process_insn (insn);
7968 end_alias_analysis ();
7972 /* Call cse / combine like post-reload optimization phases.
7973 FIRST is the first instruction. */
7975 reload_cse_regs (first)
7978 reload_cse_regs_1 (first);
7980 reload_cse_move2add (first);
7981 if (flag_expensive_optimizations)
7982 reload_cse_regs_1 (first);
7985 /* Try to simplify a single SET instruction. SET is the set pattern.
7986 INSN is the instruction it came from.
7987 This function only handles one case: if we set a register to a value
7988 which is not a register, we try to find that value in some other register
7989 and change the set into a register copy. */
7992 reload_cse_simplify_set (set, insn)
7999 enum reg_class dclass;
8002 struct elt_loc_list *l;
8004 dreg = true_regnum (SET_DEST (set));
8008 src = SET_SRC (set);
8009 if (side_effects_p (src) || true_regnum (src) >= 0)
8012 dclass = REGNO_REG_CLASS (dreg);
8014 /* If memory loads are cheaper than register copies, don't change them. */
8015 if (GET_CODE (src) == MEM)
8016 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8017 else if (CONSTANT_P (src))
8018 old_cost = rtx_cost (src, SET);
8019 else if (GET_CODE (src) == REG)
8020 old_cost = REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (src)), dclass);
8023 old_cost = rtx_cost (src, SET);
8025 val = cselib_lookup (src, VOIDmode, 0);
8028 for (l = val->locs; l; l = l->next)
8031 if (CONSTANT_P (l->loc) && ! references_value_p (l->loc, 0))
8032 this_cost = rtx_cost (l->loc, SET);
8033 else if (GET_CODE (l->loc) == REG)
8034 this_cost = REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (l->loc)),
8038 /* If equal costs, prefer registers over anything else. That tends to
8039 lead to smaller instructions on some machines. */
8040 if ((this_cost < old_cost
8041 || (this_cost == old_cost
8042 && GET_CODE (l->loc) == REG
8043 && GET_CODE (SET_SRC (set)) != REG))
8044 && validate_change (insn, &SET_SRC (set), copy_rtx (l->loc), 1))
8045 old_cost = this_cost, did_change = 1;
8051 /* Try to replace operands in INSN with equivalent values that are already
8052 in registers. This can be viewed as optional reloading.
8054 For each non-register operand in the insn, see if any hard regs are
8055 known to be equivalent to that operand. Record the alternatives which
8056 can accept these hard registers. Among all alternatives, select the
8057 ones which are better or equal to the one currently matching, where
8058 "better" is in terms of '?' and '!' constraints. Among the remaining
8059 alternatives, select the one which replaces most operands with
8063 reload_cse_simplify_operands (insn)
8068 /* For each operand, all registers that are equivalent to it. */
8069 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8071 const char *constraints[MAX_RECOG_OPERANDS];
8073 /* Vector recording how bad an alternative is. */
8074 int *alternative_reject;
8075 /* Vector recording how many registers can be introduced by choosing
8076 this alternative. */
8077 int *alternative_nregs;
8078 /* Array of vectors recording, for each operand and each alternative,
8079 which hard register to substitute, or -1 if the operand should be
8081 int *op_alt_regno[MAX_RECOG_OPERANDS];
8082 /* Array of alternatives, sorted in order of decreasing desirability. */
8083 int *alternative_order;
8084 rtx reg = gen_rtx_REG (VOIDmode, -1);
8086 extract_insn (insn);
8088 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8091 /* Figure out which alternative currently matches. */
8092 if (! constrain_operands (1))
8093 fatal_insn_not_found (insn);
8095 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8096 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8097 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8098 bzero ((char *)alternative_reject, recog_data.n_alternatives * sizeof (int));
8099 bzero ((char *)alternative_nregs, recog_data.n_alternatives * sizeof (int));
8101 /* For each operand, find out which regs are equivalent. */
8102 for (i = 0; i < recog_data.n_operands; i++)
8105 struct elt_loc_list *l;
8107 CLEAR_HARD_REG_SET (equiv_regs[i]);
8109 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8110 right, so avoid the problem here. */
8111 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL)
8114 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8118 for (l = v->locs; l; l = l->next)
8119 if (GET_CODE (l->loc) == REG)
8120 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8123 for (i = 0; i < recog_data.n_operands; i++)
8125 enum machine_mode mode;
8129 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8130 for (j = 0; j < recog_data.n_alternatives; j++)
8131 op_alt_regno[i][j] = -1;
8133 p = constraints[i] = recog_data.constraints[i];
8134 mode = recog_data.operand_mode[i];
8136 /* Add the reject values for each alternative given by the constraints
8137 for this operand. */
8145 alternative_reject[j] += 3;
8147 alternative_reject[j] += 300;
8150 /* We won't change operands which are already registers. We
8151 also don't want to modify output operands. */
8152 regno = true_regnum (recog_data.operand[i]);
8154 || constraints[i][0] == '='
8155 || constraints[i][0] == '+')
8158 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8160 int class = (int) NO_REGS;
8162 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8165 REGNO (reg) = regno;
8166 PUT_MODE (reg, mode);
8168 /* We found a register equal to this operand. Now look for all
8169 alternatives that can accept this register and have not been
8170 assigned a register they can use yet. */
8179 case '=': case '+': case '?':
8180 case '#': case '&': case '!':
8182 case '0': case '1': case '2': case '3': case '4':
8183 case '5': case '6': case '7': case '8': case '9':
8184 case 'm': case '<': case '>': case 'V': case 'o':
8185 case 'E': case 'F': case 'G': case 'H':
8186 case 's': case 'i': case 'n':
8187 case 'I': case 'J': case 'K': case 'L':
8188 case 'M': case 'N': case 'O': case 'P':
8190 /* These don't say anything we care about. */
8194 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8199 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
8202 case ',': case '\0':
8203 /* See if REGNO fits this alternative, and set it up as the
8204 replacement register if we don't have one for this
8205 alternative yet and the operand being replaced is not
8206 a cheap CONST_INT. */
8207 if (op_alt_regno[i][j] == -1
8208 && reg_fits_class_p (reg, class, 0, mode)
8209 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8210 || (rtx_cost (recog_data.operand[i], SET)
8211 > rtx_cost (reg, SET))))
8213 alternative_nregs[j]++;
8214 op_alt_regno[i][j] = regno;
8226 /* Record all alternatives which are better or equal to the currently
8227 matching one in the alternative_order array. */
8228 for (i = j = 0; i < recog_data.n_alternatives; i++)
8229 if (alternative_reject[i] <= alternative_reject[which_alternative])
8230 alternative_order[j++] = i;
8231 recog_data.n_alternatives = j;
8233 /* Sort it. Given a small number of alternatives, a dumb algorithm
8234 won't hurt too much. */
8235 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8238 int best_reject = alternative_reject[alternative_order[i]];
8239 int best_nregs = alternative_nregs[alternative_order[i]];
8242 for (j = i + 1; j < recog_data.n_alternatives; j++)
8244 int this_reject = alternative_reject[alternative_order[j]];
8245 int this_nregs = alternative_nregs[alternative_order[j]];
8247 if (this_reject < best_reject
8248 || (this_reject == best_reject && this_nregs < best_nregs))
8251 best_reject = this_reject;
8252 best_nregs = this_nregs;
8256 tmp = alternative_order[best];
8257 alternative_order[best] = alternative_order[i];
8258 alternative_order[i] = tmp;
8261 /* Substitute the operands as determined by op_alt_regno for the best
8263 j = alternative_order[0];
8265 for (i = 0; i < recog_data.n_operands; i++)
8267 enum machine_mode mode = recog_data.operand_mode[i];
8268 if (op_alt_regno[i][j] == -1)
8271 validate_change (insn, recog_data.operand_loc[i],
8272 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8275 for (i = recog_data.n_dups - 1; i >= 0; i--)
8277 int op = recog_data.dup_num[i];
8278 enum machine_mode mode = recog_data.operand_mode[op];
8280 if (op_alt_regno[op][j] == -1)
8283 validate_change (insn, recog_data.dup_loc[i],
8284 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8287 return apply_change_group ();
8290 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8292 This code might also be useful when reload gave up on reg+reg addresssing
8293 because of clashes between the return register and INDEX_REG_CLASS. */
8295 /* The maximum number of uses of a register we can keep track of to
8296 replace them with reg+reg addressing. */
8297 #define RELOAD_COMBINE_MAX_USES 6
8299 /* INSN is the insn where a register has ben used, and USEP points to the
8300 location of the register within the rtl. */
8301 struct reg_use { rtx insn, *usep; };
8303 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8304 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8305 indicates where it becomes live again.
8306 Otherwise, USE_INDEX is the index of the last encountered use of the
8307 register (which is first among these we have seen since we scan backwards),
8308 OFFSET contains the constant offset that is added to the register in
8309 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8310 last, of these uses.
8311 STORE_RUID is always meaningful if we only want to use a value in a
8312 register in a different place: it denotes the next insn in the insn
8313 stream (i.e. the last ecountered) that sets or clobbers the register. */
8316 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8321 } reg_state[FIRST_PSEUDO_REGISTER];
8323 /* Reverse linear uid. This is increased in reload_combine while scanning
8324 the instructions from last to first. It is used to set last_label_ruid
8325 and the store_ruid / use_ruid fields in reg_state. */
8326 static int reload_combine_ruid;
8328 #define LABEL_LIVE(LABEL) \
8329 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8335 int first_index_reg = 1, last_index_reg = 0;
8338 int last_label_ruid;
8339 int min_labelno, n_labels;
8340 HARD_REG_SET ever_live_at_start, *label_live;
8342 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
8343 reload has already used it where appropriate, so there is no use in
8344 trying to generate it now. */
8345 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8348 /* To avoid wasting too much time later searching for an index register,
8349 determine the minimum and maximum index register numbers. */
8350 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8351 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
8353 if (! first_index_reg)
8354 first_index_reg = r;
8359 /* If no index register is available, we can quit now. */
8360 if (first_index_reg > last_index_reg)
8363 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8364 information is a bit fuzzy immediately after reload, but it's
8365 still good enough to determine which registers are live at a jump
8367 min_labelno = get_first_label_num ();
8368 n_labels = max_label_num () - min_labelno;
8369 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8370 CLEAR_HARD_REG_SET (ever_live_at_start);
8372 for (i = n_basic_blocks - 1; i >= 0; i--)
8374 insn = BLOCK_HEAD (i);
8375 if (GET_CODE (insn) == CODE_LABEL)
8379 REG_SET_TO_HARD_REG_SET (live,
8380 BASIC_BLOCK (i)->global_live_at_start);
8381 compute_use_by_pseudos (&live,
8382 BASIC_BLOCK (i)->global_live_at_start);
8383 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8384 IOR_HARD_REG_SET (ever_live_at_start, live);
8388 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8389 last_label_ruid = reload_combine_ruid = 0;
8390 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8392 reg_state[r].store_ruid = reload_combine_ruid;
8394 reg_state[r].use_index = -1;
8396 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8399 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8403 /* We cannot do our optimization across labels. Invalidating all the use
8404 information we have would be costly, so we just note where the label
8405 is and then later disable any optimization that would cross it. */
8406 if (GET_CODE (insn) == CODE_LABEL)
8407 last_label_ruid = reload_combine_ruid;
8408 else if (GET_CODE (insn) == BARRIER)
8409 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8410 if (! fixed_regs[r])
8411 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8413 if (! INSN_P (insn))
8416 reload_combine_ruid++;
8418 /* Look for (set (REGX) (CONST_INT))
8419 (set (REGX) (PLUS (REGX) (REGY)))
8421 ... (MEM (REGX)) ...
8423 (set (REGZ) (CONST_INT))
8425 ... (MEM (PLUS (REGZ) (REGY)))... .
8427 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8428 and that we know all uses of REGX before it dies. */
8429 set = single_set (insn);
8431 && GET_CODE (SET_DEST (set)) == REG
8432 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8433 GET_MODE (SET_DEST (set)))
8435 && GET_CODE (SET_SRC (set)) == PLUS
8436 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8437 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8438 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8440 rtx reg = SET_DEST (set);
8441 rtx plus = SET_SRC (set);
8442 rtx base = XEXP (plus, 1);
8443 rtx prev = prev_nonnote_insn (insn);
8444 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8445 unsigned int regno = REGNO (reg);
8446 rtx const_reg = NULL_RTX;
8447 rtx reg_sum = NULL_RTX;
8449 /* Now, we need an index register.
8450 We'll set index_reg to this index register, const_reg to the
8451 register that is to be loaded with the constant
8452 (denoted as REGZ in the substitution illustration above),
8453 and reg_sum to the register-register that we want to use to
8454 substitute uses of REG (typically in MEMs) with.
8455 First check REG and BASE for being index registers;
8456 we can use them even if they are not dead. */
8457 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8458 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8466 /* Otherwise, look for a free index register. Since we have
8467 checked above that neiter REG nor BASE are index registers,
8468 if we find anything at all, it will be different from these
8470 for (i = first_index_reg; i <= last_index_reg; i++)
8472 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8474 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8475 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8476 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8478 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8480 const_reg = index_reg;
8481 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8487 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8488 (REGY), i.e. BASE, is not clobbered before the last use we'll
8491 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8492 && rtx_equal_p (SET_DEST (prev_set), reg)
8493 && reg_state[regno].use_index >= 0
8494 && (reg_state[REGNO (base)].store_ruid
8495 <= reg_state[regno].use_ruid)
8500 /* Change destination register and, if necessary, the
8501 constant value in PREV, the constant loading instruction. */
8502 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8503 if (reg_state[regno].offset != const0_rtx)
8504 validate_change (prev,
8505 &SET_SRC (prev_set),
8506 GEN_INT (INTVAL (SET_SRC (prev_set))
8507 + INTVAL (reg_state[regno].offset)),
8510 /* Now for every use of REG that we have recorded, replace REG
8512 for (i = reg_state[regno].use_index;
8513 i < RELOAD_COMBINE_MAX_USES; i++)
8514 validate_change (reg_state[regno].reg_use[i].insn,
8515 reg_state[regno].reg_use[i].usep,
8518 if (apply_change_group ())
8522 /* Delete the reg-reg addition. */
8523 PUT_CODE (insn, NOTE);
8524 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8525 NOTE_SOURCE_FILE (insn) = 0;
8527 if (reg_state[regno].offset != const0_rtx)
8528 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8530 for (np = ®_NOTES (prev); *np;)
8532 if (REG_NOTE_KIND (*np) == REG_EQUAL
8533 || REG_NOTE_KIND (*np) == REG_EQUIV)
8534 *np = XEXP (*np, 1);
8536 np = &XEXP (*np, 1);
8539 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8540 reg_state[REGNO (const_reg)].store_ruid
8541 = reload_combine_ruid;
8547 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8549 if (GET_CODE (insn) == CALL_INSN)
8553 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8554 if (call_used_regs[r])
8556 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8557 reg_state[r].store_ruid = reload_combine_ruid;
8560 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8561 link = XEXP (link, 1))
8562 if (GET_CODE (XEXP (XEXP (link, 0), 0)) == REG)
8564 unsigned int regno = REGNO (XEXP (XEXP (link, 0), 0));
8566 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
8568 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8569 reg_state[regno].store_ruid = reload_combine_ruid;
8572 reg_state[regno].use_index = -1;
8576 else if (GET_CODE (insn) == JUMP_INSN
8577 && GET_CODE (PATTERN (insn)) != RETURN)
8579 /* Non-spill registers might be used at the call destination in
8580 some unknown fashion, so we have to mark the unknown use. */
8583 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8584 && JUMP_LABEL (insn))
8585 live = &LABEL_LIVE (JUMP_LABEL (insn));
8587 live = &ever_live_at_start;
8589 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8590 if (TEST_HARD_REG_BIT (*live, i))
8591 reg_state[i].use_index = -1;
8594 reload_combine_note_use (&PATTERN (insn), insn);
8595 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8597 if (REG_NOTE_KIND (note) == REG_INC
8598 && GET_CODE (XEXP (note, 0)) == REG)
8600 int regno = REGNO (XEXP (note, 0));
8602 reg_state[regno].store_ruid = reload_combine_ruid;
8603 reg_state[regno].use_index = -1;
8611 /* Check if DST is a register or a subreg of a register; if it is,
8612 update reg_state[regno].store_ruid and reg_state[regno].use_index
8613 accordingly. Called via note_stores from reload_combine. */
8616 reload_combine_note_store (dst, set, data)
8618 void *data ATTRIBUTE_UNUSED;
8622 enum machine_mode mode = GET_MODE (dst);
8624 if (GET_CODE (dst) == SUBREG)
8626 regno = SUBREG_WORD (dst);
8627 dst = SUBREG_REG (dst);
8629 if (GET_CODE (dst) != REG)
8631 regno += REGNO (dst);
8633 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8634 careful with registers / register parts that are not full words.
8636 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8637 if (GET_CODE (set) != SET
8638 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8639 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8640 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8642 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8644 reg_state[i].use_index = -1;
8645 reg_state[i].store_ruid = reload_combine_ruid;
8650 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8652 reg_state[i].store_ruid = reload_combine_ruid;
8653 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8658 /* XP points to a piece of rtl that has to be checked for any uses of
8660 *XP is the pattern of INSN, or a part of it.
8661 Called from reload_combine, and recursively by itself. */
8663 reload_combine_note_use (xp, insn)
8667 enum rtx_code code = x->code;
8670 rtx offset = const0_rtx; /* For the REG case below. */
8675 if (GET_CODE (SET_DEST (x)) == REG)
8677 reload_combine_note_use (&SET_SRC (x), insn);
8683 /* If this is the USE of a return value, we can't change it. */
8684 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8686 /* Mark the return register as used in an unknown fashion. */
8687 rtx reg = XEXP (x, 0);
8688 int regno = REGNO (reg);
8689 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8691 while (--nregs >= 0)
8692 reg_state[regno + nregs].use_index = -1;
8698 if (GET_CODE (SET_DEST (x)) == REG)
8703 /* We are interested in (plus (reg) (const_int)) . */
8704 if (GET_CODE (XEXP (x, 0)) != REG
8705 || GET_CODE (XEXP (x, 1)) != CONST_INT)
8707 offset = XEXP (x, 1);
8712 int regno = REGNO (x);
8716 /* Some spurious USEs of pseudo registers might remain.
8717 Just ignore them. */
8718 if (regno >= FIRST_PSEUDO_REGISTER)
8721 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
8723 /* We can't substitute into multi-hard-reg uses. */
8726 while (--nregs >= 0)
8727 reg_state[regno + nregs].use_index = -1;
8731 /* If this register is already used in some unknown fashion, we
8733 If we decrement the index from zero to -1, we can't store more
8734 uses, so this register becomes used in an unknown fashion. */
8735 use_index = --reg_state[regno].use_index;
8739 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
8741 /* We have found another use for a register that is already
8742 used later. Check if the offsets match; if not, mark the
8743 register as used in an unknown fashion. */
8744 if (! rtx_equal_p (offset, reg_state[regno].offset))
8746 reg_state[regno].use_index = -1;
8752 /* This is the first use of this register we have seen since we
8753 marked it as dead. */
8754 reg_state[regno].offset = offset;
8755 reg_state[regno].use_ruid = reload_combine_ruid;
8757 reg_state[regno].reg_use[use_index].insn = insn;
8758 reg_state[regno].reg_use[use_index].usep = xp;
8766 /* Recursively process the components of X. */
8767 fmt = GET_RTX_FORMAT (code);
8768 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8771 reload_combine_note_use (&XEXP (x, i), insn);
8772 else if (fmt[i] == 'E')
8774 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8775 reload_combine_note_use (&XVECEXP (x, i, j), insn);
8780 /* See if we can reduce the cost of a constant by replacing a move with
8782 /* We cannot do our optimization across labels. Invalidating all the
8783 information about register contents we have would be costly, so we
8784 use last_label_luid (local variable of reload_cse_move2add) to note
8785 where the label is and then later disable any optimization that would
8787 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
8788 reg_set_luid[n] is larger than last_label_luid[n] . */
8789 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
8791 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
8792 reg_mode[n] to be valid.
8793 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
8794 has been set to reg_offset[n] in mode reg_mode[n] .
8795 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
8796 register n has been set to the sum of reg_offset[n] and register
8797 reg_base_reg[n], calculated in mode reg_mode[n] . */
8798 static rtx reg_offset[FIRST_PSEUDO_REGISTER];
8799 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
8800 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
8802 /* move2add_luid is linearily increased while scanning the instructions
8803 from first to last. It is used to set reg_set_luid in
8804 reload_cse_move2add and move2add_note_store. */
8805 static int move2add_luid;
8807 /* Generate a CONST_INT and force it in the range of MODE. */
8810 gen_mode_int (mode, value)
8811 enum machine_mode mode;
8812 HOST_WIDE_INT value;
8814 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
8815 int width = GET_MODE_BITSIZE (mode);
8817 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
8819 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
8820 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
8821 cval |= (HOST_WIDE_INT) -1 << width;
8823 return GEN_INT (cval);
8827 reload_cse_move2add (first)
8832 int last_label_luid;
8834 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
8835 reg_set_luid[i] = 0;
8837 last_label_luid = 0;
8839 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
8843 if (GET_CODE (insn) == CODE_LABEL)
8844 last_label_luid = move2add_luid;
8845 if (! INSN_P (insn))
8847 pat = PATTERN (insn);
8848 /* For simplicity, we only perform this optimization on
8849 straightforward SETs. */
8850 if (GET_CODE (pat) == SET
8851 && GET_CODE (SET_DEST (pat)) == REG)
8853 rtx reg = SET_DEST (pat);
8854 int regno = REGNO (reg);
8855 rtx src = SET_SRC (pat);
8857 /* Check if we have valid information on the contents of this
8858 register in the mode of REG. */
8859 /* ??? We don't know how zero / sign extension is handled, hence
8860 we can't go from a narrower to a wider mode. */
8861 if (reg_set_luid[regno] > last_label_luid
8862 && ((GET_MODE_SIZE (GET_MODE (reg))
8863 == GET_MODE_SIZE (reg_mode[regno]))
8864 || ((GET_MODE_SIZE (GET_MODE (reg))
8865 <= GET_MODE_SIZE (reg_mode[regno]))
8866 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (reg)),
8867 GET_MODE_BITSIZE (reg_mode[regno]))))
8868 && GET_CODE (reg_offset[regno]) == CONST_INT)
8870 /* Try to transform (set (REGX) (CONST_INT A))
8872 (set (REGX) (CONST_INT B))
8874 (set (REGX) (CONST_INT A))
8876 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
8878 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
8882 = gen_mode_int (GET_MODE (reg),
8883 INTVAL (src) - INTVAL (reg_offset[regno]));
8884 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
8885 use (set (reg) (reg)) instead.
8886 We don't delete this insn, nor do we convert it into a
8887 note, to avoid losing register notes or the return
8888 value flag. jump2 already knowns how to get rid of
8890 if (new_src == const0_rtx)
8891 success = validate_change (insn, &SET_SRC (pat), reg, 0);
8892 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
8893 && have_add2_insn (GET_MODE (reg)))
8894 success = validate_change (insn, &PATTERN (insn),
8895 gen_add2_insn (reg, new_src), 0);
8896 reg_set_luid[regno] = move2add_luid;
8897 reg_mode[regno] = GET_MODE (reg);
8898 reg_offset[regno] = src;
8902 /* Try to transform (set (REGX) (REGY))
8903 (set (REGX) (PLUS (REGX) (CONST_INT A)))
8906 (set (REGX) (PLUS (REGX) (CONST_INT B)))
8909 (set (REGX) (PLUS (REGX) (CONST_INT A)))
8911 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
8912 else if (GET_CODE (src) == REG
8913 && reg_base_reg[regno] == (int) REGNO (src)
8914 && reg_set_luid[regno] > reg_set_luid[REGNO (src)])
8916 rtx next = next_nonnote_insn (insn);
8919 set = single_set (next);
8922 && SET_DEST (set) == reg
8923 && GET_CODE (SET_SRC (set)) == PLUS
8924 && XEXP (SET_SRC (set), 0) == reg
8925 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
8927 rtx src3 = XEXP (SET_SRC (set), 1);
8929 = gen_mode_int (GET_MODE (reg),
8931 - INTVAL (reg_offset[regno]));
8934 if (new_src == const0_rtx)
8935 /* See above why we create (set (reg) (reg)) here. */
8937 = validate_change (next, &SET_SRC (set), reg, 0);
8938 else if ((rtx_cost (new_src, PLUS)
8939 < 2 + rtx_cost (src3, SET))
8940 && have_add2_insn (GET_MODE (reg)))
8942 = validate_change (next, &PATTERN (next),
8943 gen_add2_insn (reg, new_src), 0);
8946 /* INSN might be the first insn in a basic block
8947 if the preceding insn is a conditional jump
8948 or a possible-throwing call. */
8949 PUT_CODE (insn, NOTE);
8950 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8951 NOTE_SOURCE_FILE (insn) = 0;
8954 reg_set_luid[regno] = move2add_luid;
8955 reg_mode[regno] = GET_MODE (reg);
8956 reg_offset[regno] = src3;
8963 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8965 if (REG_NOTE_KIND (note) == REG_INC
8966 && GET_CODE (XEXP (note, 0)) == REG)
8968 /* Indicate that this register has been recently written to,
8969 but the exact contents are not available. */
8970 int regno = REGNO (XEXP (note, 0));
8971 if (regno < FIRST_PSEUDO_REGISTER)
8973 reg_set_luid[regno] = move2add_luid;
8974 reg_offset[regno] = note;
8978 note_stores (PATTERN (insn), move2add_note_store, NULL);
8979 /* If this is a CALL_INSN, all call used registers are stored with
8981 if (GET_CODE (insn) == CALL_INSN)
8983 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
8985 if (call_used_regs[i])
8987 reg_set_luid[i] = move2add_luid;
8988 reg_offset[i] = insn; /* Invalidate contents. */
8995 /* SET is a SET or CLOBBER that sets DST.
8996 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
8997 Called from reload_cse_move2add via note_stores. */
9000 move2add_note_store (dst, set, data)
9002 void *data ATTRIBUTE_UNUSED;
9004 unsigned int regno = 0;
9006 enum machine_mode mode = GET_MODE (dst);
9008 if (GET_CODE (dst) == SUBREG)
9010 regno = SUBREG_WORD (dst);
9011 dst = SUBREG_REG (dst);
9014 if (GET_CODE (dst) != REG)
9017 regno += REGNO (dst);
9019 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9020 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9021 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9022 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9024 rtx src = SET_SRC (set);
9026 reg_mode[regno] = mode;
9027 switch (GET_CODE (src))
9031 rtx src0 = XEXP (src, 0);
9033 if (GET_CODE (src0) == REG)
9035 if (REGNO (src0) != regno
9036 || reg_offset[regno] != const0_rtx)
9038 reg_base_reg[regno] = REGNO (src0);
9039 reg_set_luid[regno] = move2add_luid;
9042 reg_offset[regno] = XEXP (src, 1);
9046 reg_set_luid[regno] = move2add_luid;
9047 reg_offset[regno] = set; /* Invalidate contents. */
9052 reg_base_reg[regno] = REGNO (SET_SRC (set));
9053 reg_offset[regno] = const0_rtx;
9054 reg_set_luid[regno] = move2add_luid;
9058 reg_base_reg[regno] = -1;
9059 reg_offset[regno] = SET_SRC (set);
9060 reg_set_luid[regno] = move2add_luid;
9066 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9068 for (i = regno; i < endregno; i++)
9070 /* Indicate that this register has been recently written to,
9071 but the exact contents are not available. */
9072 reg_set_luid[i] = move2add_luid;
9073 reg_offset[i] = dst;
9080 add_auto_inc_notes (insn, x)
9084 enum rtx_code code = GET_CODE (x);
9088 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9091 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9095 /* Scan all the operand sub-expressions. */
9096 fmt = GET_RTX_FORMAT (code);
9097 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9100 add_auto_inc_notes (insn, XEXP (x, i));
9101 else if (fmt[i] == 'E')
9102 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9103 add_auto_inc_notes (insn, XVECEXP (x, i, j));
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