1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
82 #define LOCAL_REGNO(REGNO) 0
85 /* During reload_as_needed, element N contains a REG rtx for the hard reg
86 into which reg N has been reloaded (perhaps for a previous insn). */
87 static rtx *reg_last_reload_reg;
89 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
90 for an output reload that stores into reg N. */
91 static char *reg_has_output_reload;
93 /* Indicates which hard regs are reload-registers for an output reload
94 in the current insn. */
95 static HARD_REG_SET reg_is_output_reload;
97 /* Element N is the constant value to which pseudo reg N is equivalent,
98 or zero if pseudo reg N is not equivalent to a constant.
99 find_reloads looks at this in order to replace pseudo reg N
100 with the constant it stands for. */
101 rtx *reg_equiv_constant;
103 /* Element N is a memory location to which pseudo reg N is equivalent,
104 prior to any register elimination (such as frame pointer to stack
105 pointer). Depending on whether or not it is a valid address, this value
106 is transferred to either reg_equiv_address or reg_equiv_mem. */
107 rtx *reg_equiv_memory_loc;
109 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
110 This is used when the address is not valid as a memory address
111 (because its displacement is too big for the machine.) */
112 rtx *reg_equiv_address;
114 /* Element N is the memory slot to which pseudo reg N is equivalent,
115 or zero if pseudo reg N is not equivalent to a memory slot. */
118 /* Widest width in which each pseudo reg is referred to (via subreg). */
119 static unsigned int *reg_max_ref_width;
121 /* Element N is the list of insns that initialized reg N from its equivalent
122 constant or memory slot. */
123 static rtx *reg_equiv_init;
125 /* Vector to remember old contents of reg_renumber before spilling. */
126 static short *reg_old_renumber;
128 /* During reload_as_needed, element N contains the last pseudo regno reloaded
129 into hard register N. If that pseudo reg occupied more than one register,
130 reg_reloaded_contents points to that pseudo for each spill register in
131 use; all of these must remain set for an inheritance to occur. */
132 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
134 /* During reload_as_needed, element N contains the insn for which
135 hard register N was last used. Its contents are significant only
136 when reg_reloaded_valid is set for this register. */
137 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
139 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
140 static HARD_REG_SET reg_reloaded_valid;
141 /* Indicate if the register was dead at the end of the reload.
142 This is only valid if reg_reloaded_contents is set and valid. */
143 static HARD_REG_SET reg_reloaded_dead;
145 /* Number of spill-regs so far; number of valid elements of spill_regs. */
148 /* In parallel with spill_regs, contains REG rtx's for those regs.
149 Holds the last rtx used for any given reg, or 0 if it has never
150 been used for spilling yet. This rtx is reused, provided it has
152 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
154 /* In parallel with spill_regs, contains nonzero for a spill reg
155 that was stored after the last time it was used.
156 The precise value is the insn generated to do the store. */
157 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
159 /* This is the register that was stored with spill_reg_store. This is a
160 copy of reload_out / reload_out_reg when the value was stored; if
161 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
162 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
164 /* This table is the inverse mapping of spill_regs:
165 indexed by hard reg number,
166 it contains the position of that reg in spill_regs,
167 or -1 for something that is not in spill_regs.
169 ?!? This is no longer accurate. */
170 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
172 /* This reg set indicates registers that can't be used as spill registers for
173 the currently processed insn. These are the hard registers which are live
174 during the insn, but not allocated to pseudos, as well as fixed
176 static HARD_REG_SET bad_spill_regs;
178 /* These are the hard registers that can't be used as spill register for any
179 insn. This includes registers used for user variables and registers that
180 we can't eliminate. A register that appears in this set also can't be used
181 to retry register allocation. */
182 static HARD_REG_SET bad_spill_regs_global;
184 /* Describes order of use of registers for reloading
185 of spilled pseudo-registers. `n_spills' is the number of
186 elements that are actually valid; new ones are added at the end.
188 Both spill_regs and spill_reg_order are used on two occasions:
189 once during find_reload_regs, where they keep track of the spill registers
190 for a single insn, but also during reload_as_needed where they show all
191 the registers ever used by reload. For the latter case, the information
192 is calculated during finish_spills. */
193 static short spill_regs[FIRST_PSEUDO_REGISTER];
195 /* This vector of reg sets indicates, for each pseudo, which hard registers
196 may not be used for retrying global allocation because the register was
197 formerly spilled from one of them. If we allowed reallocating a pseudo to
198 a register that it was already allocated to, reload might not
200 static HARD_REG_SET *pseudo_previous_regs;
202 /* This vector of reg sets indicates, for each pseudo, which hard
203 registers may not be used for retrying global allocation because they
204 are used as spill registers during one of the insns in which the
206 static HARD_REG_SET *pseudo_forbidden_regs;
208 /* All hard regs that have been used as spill registers for any insn are
209 marked in this set. */
210 static HARD_REG_SET used_spill_regs;
212 /* Index of last register assigned as a spill register. We allocate in
213 a round-robin fashion. */
214 static int last_spill_reg;
216 /* Nonzero if indirect addressing is supported on the machine; this means
217 that spilling (REG n) does not require reloading it into a register in
218 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
219 value indicates the level of indirect addressing supported, e.g., two
220 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
222 static char spill_indirect_levels;
224 /* Nonzero if indirect addressing is supported when the innermost MEM is
225 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
226 which these are valid is the same as spill_indirect_levels, above. */
227 char indirect_symref_ok;
229 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
230 char double_reg_address_ok;
232 /* Record the stack slot for each spilled hard register. */
233 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
235 /* Width allocated so far for that stack slot. */
236 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
238 /* Record which pseudos needed to be spilled. */
239 static regset_head spilled_pseudos;
241 /* Used for communication between order_regs_for_reload and count_pseudo.
242 Used to avoid counting one pseudo twice. */
243 static regset_head pseudos_counted;
245 /* First uid used by insns created by reload in this function.
246 Used in find_equiv_reg. */
247 int reload_first_uid;
249 /* Flag set by local-alloc or global-alloc if anything is live in
250 a call-clobbered reg across calls. */
251 int caller_save_needed;
253 /* Set to 1 while reload_as_needed is operating.
254 Required by some machines to handle any generated moves differently. */
255 int reload_in_progress = 0;
257 /* These arrays record the insn_code of insns that may be needed to
258 perform input and output reloads of special objects. They provide a
259 place to pass a scratch register. */
260 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
261 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
263 /* This obstack is used for allocation of rtl during register elimination.
264 The allocated storage can be freed once find_reloads has processed the
266 struct obstack reload_obstack;
268 /* Points to the beginning of the reload_obstack. All insn_chain structures
269 are allocated first. */
270 char *reload_startobj;
272 /* The point after all insn_chain structures. Used to quickly deallocate
273 memory allocated in copy_reloads during calculate_needs_all_insns. */
274 char *reload_firstobj;
276 /* This points before all local rtl generated by register elimination.
277 Used to quickly free all memory after processing one insn. */
278 static char *reload_insn_firstobj;
280 /* List of insn_chain instructions, one for every insn that reload needs to
282 struct insn_chain *reload_insn_chain;
284 /* List of all insns needing reloads. */
285 static struct insn_chain *insns_need_reload;
287 /* This structure is used to record information about register eliminations.
288 Each array entry describes one possible way of eliminating a register
289 in favor of another. If there is more than one way of eliminating a
290 particular register, the most preferred should be specified first. */
294 int from; /* Register number to be eliminated. */
295 int to; /* Register number used as replacement. */
296 int initial_offset; /* Initial difference between values. */
297 int can_eliminate; /* Nonzero if this elimination can be done. */
298 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
299 insns made by reload. */
300 int offset; /* Current offset between the two regs. */
301 int previous_offset; /* Offset at end of previous insn. */
302 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
303 rtx from_rtx; /* REG rtx for the register to be eliminated.
304 We cannot simply compare the number since
305 we might then spuriously replace a hard
306 register corresponding to a pseudo
307 assigned to the reg to be eliminated. */
308 rtx to_rtx; /* REG rtx for the replacement. */
311 static struct elim_table *reg_eliminate = 0;
313 /* This is an intermediate structure to initialize the table. It has
314 exactly the members provided by ELIMINABLE_REGS. */
315 static const struct elim_table_1
319 } reg_eliminate_1[] =
321 /* If a set of eliminable registers was specified, define the table from it.
322 Otherwise, default to the normal case of the frame pointer being
323 replaced by the stack pointer. */
325 #ifdef ELIMINABLE_REGS
328 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
331 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
333 /* Record the number of pending eliminations that have an offset not equal
334 to their initial offset. If nonzero, we use a new copy of each
335 replacement result in any insns encountered. */
336 int num_not_at_initial_offset;
338 /* Count the number of registers that we may be able to eliminate. */
339 static int num_eliminable;
340 /* And the number of registers that are equivalent to a constant that
341 can be eliminated to frame_pointer / arg_pointer + constant. */
342 static int num_eliminable_invariants;
344 /* For each label, we record the offset of each elimination. If we reach
345 a label by more than one path and an offset differs, we cannot do the
346 elimination. This information is indexed by the difference of the
347 number of the label and the first label number. We can't offset the
348 pointer itself as this can cause problems on machines with segmented
349 memory. The first table is an array of flags that records whether we
350 have yet encountered a label and the second table is an array of arrays,
351 one entry in the latter array for each elimination. */
353 static int first_label_num;
354 static char *offsets_known_at;
355 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
357 /* Number of labels in the current function. */
359 static int num_labels;
361 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
362 static void maybe_fix_stack_asms (void);
363 static void copy_reloads (struct insn_chain *);
364 static void calculate_needs_all_insns (int);
365 static int find_reg (struct insn_chain *, int);
366 static void find_reload_regs (struct insn_chain *);
367 static void select_reload_regs (void);
368 static void delete_caller_save_insns (void);
370 static void spill_failure (rtx, enum reg_class);
371 static void count_spilled_pseudo (int, int, int);
372 static void delete_dead_insn (rtx);
373 static void alter_reg (int, int);
374 static void set_label_offsets (rtx, rtx, int);
375 static void check_eliminable_occurrences (rtx);
376 static void elimination_effects (rtx, enum machine_mode);
377 static int eliminate_regs_in_insn (rtx, int);
378 static void update_eliminable_offsets (void);
379 static void mark_not_eliminable (rtx, rtx, void *);
380 static void set_initial_elim_offsets (void);
381 static void verify_initial_elim_offsets (void);
382 static void set_initial_label_offsets (void);
383 static void set_offsets_for_label (rtx);
384 static void init_elim_table (void);
385 static void update_eliminables (HARD_REG_SET *);
386 static void spill_hard_reg (unsigned int, int);
387 static int finish_spills (int);
388 static void ior_hard_reg_set (HARD_REG_SET *, HARD_REG_SET *);
389 static void scan_paradoxical_subregs (rtx);
390 static void count_pseudo (int);
391 static void order_regs_for_reload (struct insn_chain *);
392 static void reload_as_needed (int);
393 static void forget_old_reloads_1 (rtx, rtx, void *);
394 static int reload_reg_class_lower (const void *, const void *);
395 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
397 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
399 static int reload_reg_free_p (unsigned int, int, enum reload_type);
400 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
402 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
404 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
405 static int allocate_reload_reg (struct insn_chain *, int, int);
406 static int conflicts_with_override (rtx);
407 static void failed_reload (rtx, int);
408 static int set_reload_reg (int, int);
409 static void choose_reload_regs_init (struct insn_chain *, rtx *);
410 static void choose_reload_regs (struct insn_chain *);
411 static void merge_assigned_reloads (rtx);
412 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
414 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
416 static void do_input_reload (struct insn_chain *, struct reload *, int);
417 static void do_output_reload (struct insn_chain *, struct reload *, int);
418 static void emit_reload_insns (struct insn_chain *);
419 static void delete_output_reload (rtx, int, int);
420 static void delete_address_reloads (rtx, rtx);
421 static void delete_address_reloads_1 (rtx, rtx, rtx);
422 static rtx inc_for_reload (rtx, rtx, rtx, int);
424 static void add_auto_inc_notes (rtx, rtx);
426 static void copy_eh_notes (rtx, rtx);
428 /* Initialize the reload pass once per compilation. */
435 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
436 Set spill_indirect_levels to the number of levels such addressing is
437 permitted, zero if it is not permitted at all. */
440 = gen_rtx_MEM (Pmode,
443 LAST_VIRTUAL_REGISTER + 1),
445 spill_indirect_levels = 0;
447 while (memory_address_p (QImode, tem))
449 spill_indirect_levels++;
450 tem = gen_rtx_MEM (Pmode, tem);
453 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
455 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
456 indirect_symref_ok = memory_address_p (QImode, tem);
458 /* See if reg+reg is a valid (and offsettable) address. */
460 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
462 tem = gen_rtx_PLUS (Pmode,
463 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
464 gen_rtx_REG (Pmode, i));
466 /* This way, we make sure that reg+reg is an offsettable address. */
467 tem = plus_constant (tem, 4);
469 if (memory_address_p (QImode, tem))
471 double_reg_address_ok = 1;
476 /* Initialize obstack for our rtl allocation. */
477 gcc_obstack_init (&reload_obstack);
478 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
480 INIT_REG_SET (&spilled_pseudos);
481 INIT_REG_SET (&pseudos_counted);
484 /* List of insn chains that are currently unused. */
485 static struct insn_chain *unused_insn_chains = 0;
487 /* Allocate an empty insn_chain structure. */
489 new_insn_chain (void)
491 struct insn_chain *c;
493 if (unused_insn_chains == 0)
495 c = (struct insn_chain *)
496 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
497 INIT_REG_SET (&c->live_throughout);
498 INIT_REG_SET (&c->dead_or_set);
502 c = unused_insn_chains;
503 unused_insn_chains = c->next;
505 c->is_caller_save_insn = 0;
506 c->need_operand_change = 0;
512 /* Small utility function to set all regs in hard reg set TO which are
513 allocated to pseudos in regset FROM. */
516 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
520 EXECUTE_IF_SET_IN_REG_SET
521 (from, FIRST_PSEUDO_REGISTER, regno,
523 int r = reg_renumber[regno];
528 /* reload_combine uses the information from
529 BASIC_BLOCK->global_live_at_start, which might still
530 contain registers that have not actually been allocated
531 since they have an equivalence. */
532 if (! reload_completed)
537 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
539 SET_HARD_REG_BIT (*to, r + nregs);
544 /* Replace all pseudos found in LOC with their corresponding
548 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
561 unsigned int regno = REGNO (x);
563 if (regno < FIRST_PSEUDO_REGISTER)
566 x = eliminate_regs (x, mem_mode, usage);
570 replace_pseudos_in (loc, mem_mode, usage);
574 if (reg_equiv_constant[regno])
575 *loc = reg_equiv_constant[regno];
576 else if (reg_equiv_mem[regno])
577 *loc = reg_equiv_mem[regno];
578 else if (reg_equiv_address[regno])
579 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
580 else if (GET_CODE (regno_reg_rtx[regno]) != REG
581 || REGNO (regno_reg_rtx[regno]) != regno)
582 *loc = regno_reg_rtx[regno];
588 else if (code == MEM)
590 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
594 /* Process each of our operands recursively. */
595 fmt = GET_RTX_FORMAT (code);
596 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
598 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
599 else if (*fmt == 'E')
600 for (j = 0; j < XVECLEN (x, i); j++)
601 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
605 /* Global variables used by reload and its subroutines. */
607 /* Set during calculate_needs if an insn needs register elimination. */
608 static int something_needs_elimination;
609 /* Set during calculate_needs if an insn needs an operand changed. */
610 int something_needs_operands_changed;
612 /* Nonzero means we couldn't get enough spill regs. */
615 /* Main entry point for the reload pass.
617 FIRST is the first insn of the function being compiled.
619 GLOBAL nonzero means we were called from global_alloc
620 and should attempt to reallocate any pseudoregs that we
621 displace from hard regs we will use for reloads.
622 If GLOBAL is zero, we do not have enough information to do that,
623 so any pseudo reg that is spilled must go to the stack.
625 Return value is nonzero if reload failed
626 and we must not do any more for this function. */
629 reload (rtx first, int global)
633 struct elim_table *ep;
636 /* Make sure even insns with volatile mem refs are recognizable. */
641 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
643 /* Make sure that the last insn in the chain
644 is not something that needs reloading. */
645 emit_note (NOTE_INSN_DELETED);
647 /* Enable find_equiv_reg to distinguish insns made by reload. */
648 reload_first_uid = get_max_uid ();
650 #ifdef SECONDARY_MEMORY_NEEDED
651 /* Initialize the secondary memory table. */
652 clear_secondary_mem ();
655 /* We don't have a stack slot for any spill reg yet. */
656 memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot);
657 memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
659 /* Initialize the save area information for caller-save, in case some
663 /* Compute which hard registers are now in use
664 as homes for pseudo registers.
665 This is done here rather than (eg) in global_alloc
666 because this point is reached even if not optimizing. */
667 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
670 /* A function that receives a nonlocal goto must save all call-saved
672 if (current_function_has_nonlocal_label)
673 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
674 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
675 regs_ever_live[i] = 1;
677 /* Find all the pseudo registers that didn't get hard regs
678 but do have known equivalent constants or memory slots.
679 These include parameters (known equivalent to parameter slots)
680 and cse'd or loop-moved constant memory addresses.
682 Record constant equivalents in reg_equiv_constant
683 so they will be substituted by find_reloads.
684 Record memory equivalents in reg_mem_equiv so they can
685 be substituted eventually by altering the REG-rtx's. */
687 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
688 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
689 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
690 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
691 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
692 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
693 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
694 pseudo_forbidden_regs
695 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
697 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
699 CLEAR_HARD_REG_SET (bad_spill_regs_global);
701 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
702 Also find all paradoxical subregs and find largest such for each pseudo.
703 On machines with small register classes, record hard registers that
704 are used for user variables. These can never be used for spills.
705 Also look for a "constant" REG_SETJMP. This means that all
706 caller-saved registers must be marked live. */
708 num_eliminable_invariants = 0;
709 for (insn = first; insn; insn = NEXT_INSN (insn))
711 rtx set = single_set (insn);
713 /* We may introduce USEs that we want to remove at the end, so
714 we'll mark them with QImode. Make sure there are no
715 previously-marked insns left by say regmove. */
716 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
717 && GET_MODE (insn) != VOIDmode)
718 PUT_MODE (insn, VOIDmode);
720 if (GET_CODE (insn) == CALL_INSN
721 && find_reg_note (insn, REG_SETJMP, NULL))
722 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
723 if (! call_used_regs[i])
724 regs_ever_live[i] = 1;
726 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
728 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
730 #ifdef LEGITIMATE_PIC_OPERAND_P
731 && (! function_invariant_p (XEXP (note, 0))
733 /* A function invariant is often CONSTANT_P but may
734 include a register. We promise to only pass
735 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
736 || (CONSTANT_P (XEXP (note, 0))
737 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))))
741 rtx x = XEXP (note, 0);
742 i = REGNO (SET_DEST (set));
743 if (i > LAST_VIRTUAL_REGISTER)
745 /* It can happen that a REG_EQUIV note contains a MEM
746 that is not a legitimate memory operand. As later
747 stages of reload assume that all addresses found
748 in the reg_equiv_* arrays were originally legitimate,
749 we ignore such REG_EQUIV notes. */
750 if (memory_operand (x, VOIDmode))
752 /* Always unshare the equivalence, so we can
753 substitute into this insn without touching the
755 reg_equiv_memory_loc[i] = copy_rtx (x);
757 else if (function_invariant_p (x))
759 if (GET_CODE (x) == PLUS)
761 /* This is PLUS of frame pointer and a constant,
762 and might be shared. Unshare it. */
763 reg_equiv_constant[i] = copy_rtx (x);
764 num_eliminable_invariants++;
766 else if (x == frame_pointer_rtx
767 || x == arg_pointer_rtx)
769 reg_equiv_constant[i] = x;
770 num_eliminable_invariants++;
772 else if (LEGITIMATE_CONSTANT_P (x))
773 reg_equiv_constant[i] = x;
776 reg_equiv_memory_loc[i]
777 = force_const_mem (GET_MODE (SET_DEST (set)), x);
778 if (!reg_equiv_memory_loc[i])
785 /* If this register is being made equivalent to a MEM
786 and the MEM is not SET_SRC, the equivalencing insn
787 is one with the MEM as a SET_DEST and it occurs later.
788 So don't mark this insn now. */
789 if (GET_CODE (x) != MEM
790 || rtx_equal_p (SET_SRC (set), x))
792 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
797 /* If this insn is setting a MEM from a register equivalent to it,
798 this is the equivalencing insn. */
799 else if (set && GET_CODE (SET_DEST (set)) == MEM
800 && GET_CODE (SET_SRC (set)) == REG
801 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
802 && rtx_equal_p (SET_DEST (set),
803 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
804 reg_equiv_init[REGNO (SET_SRC (set))]
805 = gen_rtx_INSN_LIST (VOIDmode, insn,
806 reg_equiv_init[REGNO (SET_SRC (set))]);
809 scan_paradoxical_subregs (PATTERN (insn));
814 first_label_num = get_first_label_num ();
815 num_labels = max_label_num () - first_label_num;
817 /* Allocate the tables used to store offset information at labels. */
818 /* We used to use alloca here, but the size of what it would try to
819 allocate would occasionally cause it to exceed the stack limit and
820 cause a core dump. */
821 offsets_known_at = xmalloc (num_labels);
823 = (int (*)[NUM_ELIMINABLE_REGS])
824 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
826 /* Alter each pseudo-reg rtx to contain its hard reg number.
827 Assign stack slots to the pseudos that lack hard regs or equivalents.
828 Do not touch virtual registers. */
830 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
833 /* If we have some registers we think can be eliminated, scan all insns to
834 see if there is an insn that sets one of these registers to something
835 other than itself plus a constant. If so, the register cannot be
836 eliminated. Doing this scan here eliminates an extra pass through the
837 main reload loop in the most common case where register elimination
839 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
840 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
841 || GET_CODE (insn) == CALL_INSN)
842 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
844 maybe_fix_stack_asms ();
846 insns_need_reload = 0;
847 something_needs_elimination = 0;
849 /* Initialize to -1, which means take the first spill register. */
852 /* Spill any hard regs that we know we can't eliminate. */
853 CLEAR_HARD_REG_SET (used_spill_regs);
854 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
855 if (! ep->can_eliminate)
856 spill_hard_reg (ep->from, 1);
858 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
859 if (frame_pointer_needed)
860 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
862 finish_spills (global);
864 /* From now on, we may need to generate moves differently. We may also
865 allow modifications of insns which cause them to not be recognized.
866 Any such modifications will be cleaned up during reload itself. */
867 reload_in_progress = 1;
869 /* This loop scans the entire function each go-round
870 and repeats until one repetition spills no additional hard regs. */
873 int something_changed;
876 HOST_WIDE_INT starting_frame_size;
878 /* Round size of stack frame to stack_alignment_needed. This must be done
879 here because the stack size may be a part of the offset computation
880 for register elimination, and there might have been new stack slots
881 created in the last iteration of this loop. */
882 if (cfun->stack_alignment_needed)
883 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
885 starting_frame_size = get_frame_size ();
887 set_initial_elim_offsets ();
888 set_initial_label_offsets ();
890 /* For each pseudo register that has an equivalent location defined,
891 try to eliminate any eliminable registers (such as the frame pointer)
892 assuming initial offsets for the replacement register, which
895 If the resulting location is directly addressable, substitute
896 the MEM we just got directly for the old REG.
898 If it is not addressable but is a constant or the sum of a hard reg
899 and constant, it is probably not addressable because the constant is
900 out of range, in that case record the address; we will generate
901 hairy code to compute the address in a register each time it is
902 needed. Similarly if it is a hard register, but one that is not
903 valid as an address register.
905 If the location is not addressable, but does not have one of the
906 above forms, assign a stack slot. We have to do this to avoid the
907 potential of producing lots of reloads if, e.g., a location involves
908 a pseudo that didn't get a hard register and has an equivalent memory
909 location that also involves a pseudo that didn't get a hard register.
911 Perhaps at some point we will improve reload_when_needed handling
912 so this problem goes away. But that's very hairy. */
914 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
915 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
917 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
919 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
921 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
922 else if (CONSTANT_P (XEXP (x, 0))
923 || (GET_CODE (XEXP (x, 0)) == REG
924 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
925 || (GET_CODE (XEXP (x, 0)) == PLUS
926 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
927 && (REGNO (XEXP (XEXP (x, 0), 0))
928 < FIRST_PSEUDO_REGISTER)
929 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
930 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
933 /* Make a new stack slot. Then indicate that something
934 changed so we go back and recompute offsets for
935 eliminable registers because the allocation of memory
936 below might change some offset. reg_equiv_{mem,address}
937 will be set up for this pseudo on the next pass around
939 reg_equiv_memory_loc[i] = 0;
940 reg_equiv_init[i] = 0;
945 if (caller_save_needed)
948 /* If we allocated another stack slot, redo elimination bookkeeping. */
949 if (starting_frame_size != get_frame_size ())
952 if (caller_save_needed)
954 save_call_clobbered_regs ();
955 /* That might have allocated new insn_chain structures. */
956 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
959 calculate_needs_all_insns (global);
961 CLEAR_REG_SET (&spilled_pseudos);
964 something_changed = 0;
966 /* If we allocated any new memory locations, make another pass
967 since it might have changed elimination offsets. */
968 if (starting_frame_size != get_frame_size ())
969 something_changed = 1;
972 HARD_REG_SET to_spill;
973 CLEAR_HARD_REG_SET (to_spill);
974 update_eliminables (&to_spill);
975 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
976 if (TEST_HARD_REG_BIT (to_spill, i))
978 spill_hard_reg (i, 1);
981 /* Regardless of the state of spills, if we previously had
982 a register that we thought we could eliminate, but now can
983 not eliminate, we must run another pass.
985 Consider pseudos which have an entry in reg_equiv_* which
986 reference an eliminable register. We must make another pass
987 to update reg_equiv_* so that we do not substitute in the
988 old value from when we thought the elimination could be
990 something_changed = 1;
994 select_reload_regs ();
998 if (insns_need_reload != 0 || did_spill)
999 something_changed |= finish_spills (global);
1001 if (! something_changed)
1004 if (caller_save_needed)
1005 delete_caller_save_insns ();
1007 obstack_free (&reload_obstack, reload_firstobj);
1010 /* If global-alloc was run, notify it of any register eliminations we have
1013 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1014 if (ep->can_eliminate)
1015 mark_elimination (ep->from, ep->to);
1017 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1018 If that insn didn't set the register (i.e., it copied the register to
1019 memory), just delete that insn instead of the equivalencing insn plus
1020 anything now dead. If we call delete_dead_insn on that insn, we may
1021 delete the insn that actually sets the register if the register dies
1022 there and that is incorrect. */
1024 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1026 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1029 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1031 rtx equiv_insn = XEXP (list, 0);
1033 /* If we already deleted the insn or if it may trap, we can't
1034 delete it. The latter case shouldn't happen, but can
1035 if an insn has a variable address, gets a REG_EH_REGION
1036 note added to it, and then gets converted into an load
1037 from a constant address. */
1038 if (GET_CODE (equiv_insn) == NOTE
1039 || can_throw_internal (equiv_insn))
1041 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1042 delete_dead_insn (equiv_insn);
1045 PUT_CODE (equiv_insn, NOTE);
1046 NOTE_SOURCE_FILE (equiv_insn) = 0;
1047 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1053 /* Use the reload registers where necessary
1054 by generating move instructions to move the must-be-register
1055 values into or out of the reload registers. */
1057 if (insns_need_reload != 0 || something_needs_elimination
1058 || something_needs_operands_changed)
1060 HOST_WIDE_INT old_frame_size = get_frame_size ();
1062 reload_as_needed (global);
1064 if (old_frame_size != get_frame_size ())
1068 verify_initial_elim_offsets ();
1071 /* If we were able to eliminate the frame pointer, show that it is no
1072 longer live at the start of any basic block. If it ls live by
1073 virtue of being in a pseudo, that pseudo will be marked live
1074 and hence the frame pointer will be known to be live via that
1077 if (! frame_pointer_needed)
1079 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1080 HARD_FRAME_POINTER_REGNUM);
1082 /* Come here (with failure set nonzero) if we can't get enough spill regs
1083 and we decide not to abort about it. */
1086 CLEAR_REG_SET (&spilled_pseudos);
1087 reload_in_progress = 0;
1089 /* Now eliminate all pseudo regs by modifying them into
1090 their equivalent memory references.
1091 The REG-rtx's for the pseudos are modified in place,
1092 so all insns that used to refer to them now refer to memory.
1094 For a reg that has a reg_equiv_address, all those insns
1095 were changed by reloading so that no insns refer to it any longer;
1096 but the DECL_RTL of a variable decl may refer to it,
1097 and if so this causes the debugging info to mention the variable. */
1099 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1103 if (reg_equiv_mem[i])
1104 addr = XEXP (reg_equiv_mem[i], 0);
1106 if (reg_equiv_address[i])
1107 addr = reg_equiv_address[i];
1111 if (reg_renumber[i] < 0)
1113 rtx reg = regno_reg_rtx[i];
1115 REG_USERVAR_P (reg) = 0;
1116 PUT_CODE (reg, MEM);
1117 XEXP (reg, 0) = addr;
1118 if (reg_equiv_memory_loc[i])
1119 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1122 RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg)
1123 = MEM_SCALAR_P (reg) = 0;
1124 MEM_ATTRS (reg) = 0;
1127 else if (reg_equiv_mem[i])
1128 XEXP (reg_equiv_mem[i], 0) = addr;
1132 /* We must set reload_completed now since the cleanup_subreg_operands call
1133 below will re-recognize each insn and reload may have generated insns
1134 which are only valid during and after reload. */
1135 reload_completed = 1;
1137 /* Make a pass over all the insns and delete all USEs which we inserted
1138 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1139 notes. Delete all CLOBBER insns, except those that refer to the return
1140 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1141 from misarranging variable-array code, and simplify (subreg (reg))
1142 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1143 are no longer useful or accurate. Strip and regenerate REG_INC notes
1144 that may have been moved around. */
1146 for (insn = first; insn; insn = NEXT_INSN (insn))
1151 if (GET_CODE (insn) == CALL_INSN)
1152 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1153 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1155 if ((GET_CODE (PATTERN (insn)) == USE
1156 /* We mark with QImode USEs introduced by reload itself. */
1157 && (GET_MODE (insn) == QImode
1158 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1159 || (GET_CODE (PATTERN (insn)) == CLOBBER
1160 && (GET_CODE (XEXP (PATTERN (insn), 0)) != MEM
1161 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1162 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1163 && XEXP (XEXP (PATTERN (insn), 0), 0)
1164 != stack_pointer_rtx))
1165 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1166 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1172 /* Some CLOBBERs may survive until here and still reference unassigned
1173 pseudos with const equivalent, which may in turn cause ICE in later
1174 passes if the reference remains in place. */
1175 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1176 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1177 VOIDmode, PATTERN (insn));
1179 pnote = ®_NOTES (insn);
1182 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1183 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1184 || REG_NOTE_KIND (*pnote) == REG_INC
1185 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1186 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1187 *pnote = XEXP (*pnote, 1);
1189 pnote = &XEXP (*pnote, 1);
1193 add_auto_inc_notes (insn, PATTERN (insn));
1196 /* And simplify (subreg (reg)) if it appears as an operand. */
1197 cleanup_subreg_operands (insn);
1200 /* If we are doing stack checking, give a warning if this function's
1201 frame size is larger than we expect. */
1202 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1204 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1205 static int verbose_warned = 0;
1207 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1208 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1209 size += UNITS_PER_WORD;
1211 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1213 warning ("frame size too large for reliable stack checking");
1214 if (! verbose_warned)
1216 warning ("try reducing the number of local variables");
1222 /* Indicate that we no longer have known memory locations or constants. */
1223 if (reg_equiv_constant)
1224 free (reg_equiv_constant);
1225 reg_equiv_constant = 0;
1226 if (reg_equiv_memory_loc)
1227 free (reg_equiv_memory_loc);
1228 reg_equiv_memory_loc = 0;
1230 if (offsets_known_at)
1231 free (offsets_known_at);
1235 free (reg_equiv_mem);
1236 free (reg_equiv_init);
1237 free (reg_equiv_address);
1238 free (reg_max_ref_width);
1239 free (reg_old_renumber);
1240 free (pseudo_previous_regs);
1241 free (pseudo_forbidden_regs);
1243 CLEAR_HARD_REG_SET (used_spill_regs);
1244 for (i = 0; i < n_spills; i++)
1245 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1247 /* Free all the insn_chain structures at once. */
1248 obstack_free (&reload_obstack, reload_startobj);
1249 unused_insn_chains = 0;
1250 fixup_abnormal_edges ();
1252 /* Replacing pseudos with their memory equivalents might have
1253 created shared rtx. Subsequent passes would get confused
1254 by this, so unshare everything here. */
1255 unshare_all_rtl_again (first);
1260 /* Yet another special case. Unfortunately, reg-stack forces people to
1261 write incorrect clobbers in asm statements. These clobbers must not
1262 cause the register to appear in bad_spill_regs, otherwise we'll call
1263 fatal_insn later. We clear the corresponding regnos in the live
1264 register sets to avoid this.
1265 The whole thing is rather sick, I'm afraid. */
1268 maybe_fix_stack_asms (void)
1271 const char *constraints[MAX_RECOG_OPERANDS];
1272 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1273 struct insn_chain *chain;
1275 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1278 HARD_REG_SET clobbered, allowed;
1281 if (! INSN_P (chain->insn)
1282 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1284 pat = PATTERN (chain->insn);
1285 if (GET_CODE (pat) != PARALLEL)
1288 CLEAR_HARD_REG_SET (clobbered);
1289 CLEAR_HARD_REG_SET (allowed);
1291 /* First, make a mask of all stack regs that are clobbered. */
1292 for (i = 0; i < XVECLEN (pat, 0); i++)
1294 rtx t = XVECEXP (pat, 0, i);
1295 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1296 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1299 /* Get the operand values and constraints out of the insn. */
1300 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1301 constraints, operand_mode);
1303 /* For every operand, see what registers are allowed. */
1304 for (i = 0; i < noperands; i++)
1306 const char *p = constraints[i];
1307 /* For every alternative, we compute the class of registers allowed
1308 for reloading in CLS, and merge its contents into the reg set
1310 int cls = (int) NO_REGS;
1316 if (c == '\0' || c == ',' || c == '#')
1318 /* End of one alternative - mark the regs in the current
1319 class, and reset the class. */
1320 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1326 } while (c != '\0' && c != ',');
1334 case '=': case '+': case '*': case '%': case '?': case '!':
1335 case '0': case '1': case '2': case '3': case '4': case 'm':
1336 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1337 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1338 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1343 cls = (int) reg_class_subunion[cls]
1344 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1349 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1353 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1354 cls = (int) reg_class_subunion[cls]
1355 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1357 cls = (int) reg_class_subunion[cls]
1358 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1360 p += CONSTRAINT_LEN (c, p);
1363 /* Those of the registers which are clobbered, but allowed by the
1364 constraints, must be usable as reload registers. So clear them
1365 out of the life information. */
1366 AND_HARD_REG_SET (allowed, clobbered);
1367 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1368 if (TEST_HARD_REG_BIT (allowed, i))
1370 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1371 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1378 /* Copy the global variables n_reloads and rld into the corresponding elts
1381 copy_reloads (struct insn_chain *chain)
1383 chain->n_reloads = n_reloads;
1385 = (struct reload *) obstack_alloc (&reload_obstack,
1386 n_reloads * sizeof (struct reload));
1387 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1388 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1391 /* Walk the chain of insns, and determine for each whether it needs reloads
1392 and/or eliminations. Build the corresponding insns_need_reload list, and
1393 set something_needs_elimination as appropriate. */
1395 calculate_needs_all_insns (int global)
1397 struct insn_chain **pprev_reload = &insns_need_reload;
1398 struct insn_chain *chain, *next = 0;
1400 something_needs_elimination = 0;
1402 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1403 for (chain = reload_insn_chain; chain != 0; chain = next)
1405 rtx insn = chain->insn;
1409 /* Clear out the shortcuts. */
1410 chain->n_reloads = 0;
1411 chain->need_elim = 0;
1412 chain->need_reload = 0;
1413 chain->need_operand_change = 0;
1415 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1416 include REG_LABEL), we need to see what effects this has on the
1417 known offsets at labels. */
1419 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1420 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1421 set_label_offsets (insn, insn, 0);
1425 rtx old_body = PATTERN (insn);
1426 int old_code = INSN_CODE (insn);
1427 rtx old_notes = REG_NOTES (insn);
1428 int did_elimination = 0;
1429 int operands_changed = 0;
1430 rtx set = single_set (insn);
1432 /* Skip insns that only set an equivalence. */
1433 if (set && GET_CODE (SET_DEST (set)) == REG
1434 && reg_renumber[REGNO (SET_DEST (set))] < 0
1435 && reg_equiv_constant[REGNO (SET_DEST (set))])
1438 /* If needed, eliminate any eliminable registers. */
1439 if (num_eliminable || num_eliminable_invariants)
1440 did_elimination = eliminate_regs_in_insn (insn, 0);
1442 /* Analyze the instruction. */
1443 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1444 global, spill_reg_order);
1446 /* If a no-op set needs more than one reload, this is likely
1447 to be something that needs input address reloads. We
1448 can't get rid of this cleanly later, and it is of no use
1449 anyway, so discard it now.
1450 We only do this when expensive_optimizations is enabled,
1451 since this complements reload inheritance / output
1452 reload deletion, and it can make debugging harder. */
1453 if (flag_expensive_optimizations && n_reloads > 1)
1455 rtx set = single_set (insn);
1457 && SET_SRC (set) == SET_DEST (set)
1458 && GET_CODE (SET_SRC (set)) == REG
1459 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1462 /* Delete it from the reload chain. */
1464 chain->prev->next = next;
1466 reload_insn_chain = next;
1468 next->prev = chain->prev;
1469 chain->next = unused_insn_chains;
1470 unused_insn_chains = chain;
1475 update_eliminable_offsets ();
1477 /* Remember for later shortcuts which insns had any reloads or
1478 register eliminations. */
1479 chain->need_elim = did_elimination;
1480 chain->need_reload = n_reloads > 0;
1481 chain->need_operand_change = operands_changed;
1483 /* Discard any register replacements done. */
1484 if (did_elimination)
1486 obstack_free (&reload_obstack, reload_insn_firstobj);
1487 PATTERN (insn) = old_body;
1488 INSN_CODE (insn) = old_code;
1489 REG_NOTES (insn) = old_notes;
1490 something_needs_elimination = 1;
1493 something_needs_operands_changed |= operands_changed;
1497 copy_reloads (chain);
1498 *pprev_reload = chain;
1499 pprev_reload = &chain->next_need_reload;
1506 /* Comparison function for qsort to decide which of two reloads
1507 should be handled first. *P1 and *P2 are the reload numbers. */
1510 reload_reg_class_lower (const void *r1p, const void *r2p)
1512 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1515 /* Consider required reloads before optional ones. */
1516 t = rld[r1].optional - rld[r2].optional;
1520 /* Count all solitary classes before non-solitary ones. */
1521 t = ((reg_class_size[(int) rld[r2].class] == 1)
1522 - (reg_class_size[(int) rld[r1].class] == 1));
1526 /* Aside from solitaires, consider all multi-reg groups first. */
1527 t = rld[r2].nregs - rld[r1].nregs;
1531 /* Consider reloads in order of increasing reg-class number. */
1532 t = (int) rld[r1].class - (int) rld[r2].class;
1536 /* If reloads are equally urgent, sort by reload number,
1537 so that the results of qsort leave nothing to chance. */
1541 /* The cost of spilling each hard reg. */
1542 static int spill_cost[FIRST_PSEUDO_REGISTER];
1544 /* When spilling multiple hard registers, we use SPILL_COST for the first
1545 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1546 only the first hard reg for a multi-reg pseudo. */
1547 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1549 /* Update the spill cost arrays, considering that pseudo REG is live. */
1552 count_pseudo (int reg)
1554 int freq = REG_FREQ (reg);
1555 int r = reg_renumber[reg];
1558 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1559 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1562 SET_REGNO_REG_SET (&pseudos_counted, reg);
1567 spill_add_cost[r] += freq;
1569 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1571 spill_cost[r + nregs] += freq;
1574 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1575 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1578 order_regs_for_reload (struct insn_chain *chain)
1581 HARD_REG_SET used_by_pseudos;
1582 HARD_REG_SET used_by_pseudos2;
1584 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1586 memset (spill_cost, 0, sizeof spill_cost);
1587 memset (spill_add_cost, 0, sizeof spill_add_cost);
1589 /* Count number of uses of each hard reg by pseudo regs allocated to it
1590 and then order them by decreasing use. First exclude hard registers
1591 that are live in or across this insn. */
1593 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1594 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1595 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1596 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1598 /* Now find out which pseudos are allocated to it, and update
1600 CLEAR_REG_SET (&pseudos_counted);
1602 EXECUTE_IF_SET_IN_REG_SET
1603 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1607 EXECUTE_IF_SET_IN_REG_SET
1608 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1612 CLEAR_REG_SET (&pseudos_counted);
1615 /* Vector of reload-numbers showing the order in which the reloads should
1617 static short reload_order[MAX_RELOADS];
1619 /* This is used to keep track of the spill regs used in one insn. */
1620 static HARD_REG_SET used_spill_regs_local;
1622 /* We decided to spill hard register SPILLED, which has a size of
1623 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1624 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1625 update SPILL_COST/SPILL_ADD_COST. */
1628 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1630 int r = reg_renumber[reg];
1631 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1633 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1634 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1637 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1639 spill_add_cost[r] -= REG_FREQ (reg);
1641 spill_cost[r + nregs] -= REG_FREQ (reg);
1644 /* Find reload register to use for reload number ORDER. */
1647 find_reg (struct insn_chain *chain, int order)
1649 int rnum = reload_order[order];
1650 struct reload *rl = rld + rnum;
1651 int best_cost = INT_MAX;
1655 HARD_REG_SET not_usable;
1656 HARD_REG_SET used_by_other_reload;
1658 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1659 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1660 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1662 CLEAR_HARD_REG_SET (used_by_other_reload);
1663 for (k = 0; k < order; k++)
1665 int other = reload_order[k];
1667 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1668 for (j = 0; j < rld[other].nregs; j++)
1669 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1672 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1674 unsigned int regno = i;
1676 if (! TEST_HARD_REG_BIT (not_usable, regno)
1677 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1678 && HARD_REGNO_MODE_OK (regno, rl->mode))
1680 int this_cost = spill_cost[regno];
1682 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1684 for (j = 1; j < this_nregs; j++)
1686 this_cost += spill_add_cost[regno + j];
1687 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1688 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1693 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1695 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1697 if (this_cost < best_cost
1698 /* Among registers with equal cost, prefer caller-saved ones, or
1699 use REG_ALLOC_ORDER if it is defined. */
1700 || (this_cost == best_cost
1701 #ifdef REG_ALLOC_ORDER
1702 && (inv_reg_alloc_order[regno]
1703 < inv_reg_alloc_order[best_reg])
1705 && call_used_regs[regno]
1706 && ! call_used_regs[best_reg]
1711 best_cost = this_cost;
1719 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1721 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1722 rl->regno = best_reg;
1724 EXECUTE_IF_SET_IN_REG_SET
1725 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1727 count_spilled_pseudo (best_reg, rl->nregs, j);
1730 EXECUTE_IF_SET_IN_REG_SET
1731 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1733 count_spilled_pseudo (best_reg, rl->nregs, j);
1736 for (i = 0; i < rl->nregs; i++)
1738 if (spill_cost[best_reg + i] != 0
1739 || spill_add_cost[best_reg + i] != 0)
1741 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1746 /* Find more reload regs to satisfy the remaining need of an insn, which
1748 Do it by ascending class number, since otherwise a reg
1749 might be spilled for a big class and might fail to count
1750 for a smaller class even though it belongs to that class. */
1753 find_reload_regs (struct insn_chain *chain)
1757 /* In order to be certain of getting the registers we need,
1758 we must sort the reloads into order of increasing register class.
1759 Then our grabbing of reload registers will parallel the process
1760 that provided the reload registers. */
1761 for (i = 0; i < chain->n_reloads; i++)
1763 /* Show whether this reload already has a hard reg. */
1764 if (chain->rld[i].reg_rtx)
1766 int regno = REGNO (chain->rld[i].reg_rtx);
1767 chain->rld[i].regno = regno;
1769 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1772 chain->rld[i].regno = -1;
1773 reload_order[i] = i;
1776 n_reloads = chain->n_reloads;
1777 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1779 CLEAR_HARD_REG_SET (used_spill_regs_local);
1782 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1784 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1786 /* Compute the order of preference for hard registers to spill. */
1788 order_regs_for_reload (chain);
1790 for (i = 0; i < n_reloads; i++)
1792 int r = reload_order[i];
1794 /* Ignore reloads that got marked inoperative. */
1795 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1796 && ! rld[r].optional
1797 && rld[r].regno == -1)
1798 if (! find_reg (chain, i))
1800 spill_failure (chain->insn, rld[r].class);
1806 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1807 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1809 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1813 select_reload_regs (void)
1815 struct insn_chain *chain;
1817 /* Try to satisfy the needs for each insn. */
1818 for (chain = insns_need_reload; chain != 0;
1819 chain = chain->next_need_reload)
1820 find_reload_regs (chain);
1823 /* Delete all insns that were inserted by emit_caller_save_insns during
1826 delete_caller_save_insns (void)
1828 struct insn_chain *c = reload_insn_chain;
1832 while (c != 0 && c->is_caller_save_insn)
1834 struct insn_chain *next = c->next;
1837 if (c == reload_insn_chain)
1838 reload_insn_chain = next;
1842 next->prev = c->prev;
1844 c->prev->next = next;
1845 c->next = unused_insn_chains;
1846 unused_insn_chains = c;
1854 /* Handle the failure to find a register to spill.
1855 INSN should be one of the insns which needed this particular spill reg. */
1858 spill_failure (rtx insn, enum reg_class class)
1860 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1861 if (asm_noperands (PATTERN (insn)) >= 0)
1862 error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'",
1863 reg_class_names[class]);
1866 error ("unable to find a register to spill in class `%s'",
1867 reg_class_names[class]);
1868 fatal_insn ("this is the insn:", insn);
1872 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1873 data that is dead in INSN. */
1876 delete_dead_insn (rtx insn)
1878 rtx prev = prev_real_insn (insn);
1881 /* If the previous insn sets a register that dies in our insn, delete it
1883 if (prev && GET_CODE (PATTERN (prev)) == SET
1884 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1885 && reg_mentioned_p (prev_dest, PATTERN (insn))
1886 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1887 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1888 delete_dead_insn (prev);
1890 PUT_CODE (insn, NOTE);
1891 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1892 NOTE_SOURCE_FILE (insn) = 0;
1895 /* Modify the home of pseudo-reg I.
1896 The new home is present in reg_renumber[I].
1898 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1899 or it may be -1, meaning there is none or it is not relevant.
1900 This is used so that all pseudos spilled from a given hard reg
1901 can share one stack slot. */
1904 alter_reg (int i, int from_reg)
1906 /* When outputting an inline function, this can happen
1907 for a reg that isn't actually used. */
1908 if (regno_reg_rtx[i] == 0)
1911 /* If the reg got changed to a MEM at rtl-generation time,
1913 if (GET_CODE (regno_reg_rtx[i]) != REG)
1916 /* Modify the reg-rtx to contain the new hard reg
1917 number or else to contain its pseudo reg number. */
1918 REGNO (regno_reg_rtx[i])
1919 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1921 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1922 allocate a stack slot for it. */
1924 if (reg_renumber[i] < 0
1925 && REG_N_REFS (i) > 0
1926 && reg_equiv_constant[i] == 0
1927 && reg_equiv_memory_loc[i] == 0)
1930 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1931 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1934 /* Each pseudo reg has an inherent size which comes from its own mode,
1935 and a total size which provides room for paradoxical subregs
1936 which refer to the pseudo reg in wider modes.
1938 We can use a slot already allocated if it provides both
1939 enough inherent space and enough total space.
1940 Otherwise, we allocate a new slot, making sure that it has no less
1941 inherent space, and no less total space, then the previous slot. */
1944 /* No known place to spill from => no slot to reuse. */
1945 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1946 inherent_size == total_size ? 0 : -1);
1947 if (BYTES_BIG_ENDIAN)
1948 /* Cancel the big-endian correction done in assign_stack_local.
1949 Get the address of the beginning of the slot.
1950 This is so we can do a big-endian correction unconditionally
1952 adjust = inherent_size - total_size;
1954 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1956 /* Nothing can alias this slot except this pseudo. */
1957 set_mem_alias_set (x, new_alias_set ());
1960 /* Reuse a stack slot if possible. */
1961 else if (spill_stack_slot[from_reg] != 0
1962 && spill_stack_slot_width[from_reg] >= total_size
1963 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1965 x = spill_stack_slot[from_reg];
1967 /* Allocate a bigger slot. */
1970 /* Compute maximum size needed, both for inherent size
1971 and for total size. */
1972 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1975 if (spill_stack_slot[from_reg])
1977 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1979 mode = GET_MODE (spill_stack_slot[from_reg]);
1980 if (spill_stack_slot_width[from_reg] > total_size)
1981 total_size = spill_stack_slot_width[from_reg];
1984 /* Make a slot with that size. */
1985 x = assign_stack_local (mode, total_size,
1986 inherent_size == total_size ? 0 : -1);
1989 /* All pseudos mapped to this slot can alias each other. */
1990 if (spill_stack_slot[from_reg])
1991 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
1993 set_mem_alias_set (x, new_alias_set ());
1995 if (BYTES_BIG_ENDIAN)
1997 /* Cancel the big-endian correction done in assign_stack_local.
1998 Get the address of the beginning of the slot.
1999 This is so we can do a big-endian correction unconditionally
2001 adjust = GET_MODE_SIZE (mode) - total_size;
2004 = adjust_address_nv (x, mode_for_size (total_size
2010 spill_stack_slot[from_reg] = stack_slot;
2011 spill_stack_slot_width[from_reg] = total_size;
2014 /* On a big endian machine, the "address" of the slot
2015 is the address of the low part that fits its inherent mode. */
2016 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2017 adjust += (total_size - inherent_size);
2019 /* If we have any adjustment to make, or if the stack slot is the
2020 wrong mode, make a new stack slot. */
2021 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2023 /* If we have a decl for the original register, set it for the
2024 memory. If this is a shared MEM, make a copy. */
2025 if (REG_EXPR (regno_reg_rtx[i])
2026 && TREE_CODE_CLASS (TREE_CODE (REG_EXPR (regno_reg_rtx[i]))) == 'd')
2028 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2030 /* We can do this only for the DECLs home pseudo, not for
2031 any copies of it, since otherwise when the stack slot
2032 is reused, nonoverlapping_memrefs_p might think they
2034 if (decl && GET_CODE (decl) == REG && REGNO (decl) == (unsigned) i)
2036 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2039 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2043 /* Save the stack slot for later. */
2044 reg_equiv_memory_loc[i] = x;
2048 /* Mark the slots in regs_ever_live for the hard regs
2049 used by pseudo-reg number REGNO. */
2052 mark_home_live (int regno)
2056 i = reg_renumber[regno];
2059 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2061 regs_ever_live[i++] = 1;
2064 /* This function handles the tracking of elimination offsets around branches.
2066 X is a piece of RTL being scanned.
2068 INSN is the insn that it came from, if any.
2070 INITIAL_P is nonzero if we are to set the offset to be the initial
2071 offset and zero if we are setting the offset of the label to be the
2075 set_label_offsets (rtx x, rtx insn, int initial_p)
2077 enum rtx_code code = GET_CODE (x);
2080 struct elim_table *p;
2085 if (LABEL_REF_NONLOCAL_P (x))
2090 /* ... fall through ... */
2093 /* If we know nothing about this label, set the desired offsets. Note
2094 that this sets the offset at a label to be the offset before a label
2095 if we don't know anything about the label. This is not correct for
2096 the label after a BARRIER, but is the best guess we can make. If
2097 we guessed wrong, we will suppress an elimination that might have
2098 been possible had we been able to guess correctly. */
2100 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2102 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2103 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2104 = (initial_p ? reg_eliminate[i].initial_offset
2105 : reg_eliminate[i].offset);
2106 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2109 /* Otherwise, if this is the definition of a label and it is
2110 preceded by a BARRIER, set our offsets to the known offset of
2114 && (tem = prev_nonnote_insn (insn)) != 0
2115 && GET_CODE (tem) == BARRIER)
2116 set_offsets_for_label (insn);
2118 /* If neither of the above cases is true, compare each offset
2119 with those previously recorded and suppress any eliminations
2120 where the offsets disagree. */
2122 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2123 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2124 != (initial_p ? reg_eliminate[i].initial_offset
2125 : reg_eliminate[i].offset))
2126 reg_eliminate[i].can_eliminate = 0;
2131 set_label_offsets (PATTERN (insn), insn, initial_p);
2133 /* ... fall through ... */
2137 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2138 and hence must have all eliminations at their initial offsets. */
2139 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2140 if (REG_NOTE_KIND (tem) == REG_LABEL)
2141 set_label_offsets (XEXP (tem, 0), insn, 1);
2147 /* Each of the labels in the parallel or address vector must be
2148 at their initial offsets. We want the first field for PARALLEL
2149 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2151 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2152 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2157 /* We only care about setting PC. If the source is not RETURN,
2158 IF_THEN_ELSE, or a label, disable any eliminations not at
2159 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2160 isn't one of those possibilities. For branches to a label,
2161 call ourselves recursively.
2163 Note that this can disable elimination unnecessarily when we have
2164 a non-local goto since it will look like a non-constant jump to
2165 someplace in the current function. This isn't a significant
2166 problem since such jumps will normally be when all elimination
2167 pairs are back to their initial offsets. */
2169 if (SET_DEST (x) != pc_rtx)
2172 switch (GET_CODE (SET_SRC (x)))
2179 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2183 tem = XEXP (SET_SRC (x), 1);
2184 if (GET_CODE (tem) == LABEL_REF)
2185 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2186 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2189 tem = XEXP (SET_SRC (x), 2);
2190 if (GET_CODE (tem) == LABEL_REF)
2191 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2192 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2200 /* If we reach here, all eliminations must be at their initial
2201 offset because we are doing a jump to a variable address. */
2202 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2203 if (p->offset != p->initial_offset)
2204 p->can_eliminate = 0;
2212 /* Scan X and replace any eliminable registers (such as fp) with a
2213 replacement (such as sp), plus an offset.
2215 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2216 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2217 MEM, we are allowed to replace a sum of a register and the constant zero
2218 with the register, which we cannot do outside a MEM. In addition, we need
2219 to record the fact that a register is referenced outside a MEM.
2221 If INSN is an insn, it is the insn containing X. If we replace a REG
2222 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2223 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2224 the REG is being modified.
2226 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2227 That's used when we eliminate in expressions stored in notes.
2228 This means, do not set ref_outside_mem even if the reference
2231 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2232 replacements done assuming all offsets are at their initial values. If
2233 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2234 encounter, return the actual location so that find_reloads will do
2235 the proper thing. */
2238 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2240 enum rtx_code code = GET_CODE (x);
2241 struct elim_table *ep;
2248 if (! current_function_decl)
2268 /* This is only for the benefit of the debugging backends, which call
2269 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2270 removed after CSE. */
2271 new = eliminate_regs (XEXP (x, 0), 0, insn);
2272 if (GET_CODE (new) == MEM)
2273 return XEXP (new, 0);
2279 /* First handle the case where we encounter a bare register that
2280 is eliminable. Replace it with a PLUS. */
2281 if (regno < FIRST_PSEUDO_REGISTER)
2283 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2285 if (ep->from_rtx == x && ep->can_eliminate)
2286 return plus_constant (ep->to_rtx, ep->previous_offset);
2289 else if (reg_renumber && reg_renumber[regno] < 0
2290 && reg_equiv_constant && reg_equiv_constant[regno]
2291 && ! CONSTANT_P (reg_equiv_constant[regno]))
2292 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2296 /* You might think handling MINUS in a manner similar to PLUS is a
2297 good idea. It is not. It has been tried multiple times and every
2298 time the change has had to have been reverted.
2300 Other parts of reload know a PLUS is special (gen_reload for example)
2301 and require special code to handle code a reloaded PLUS operand.
2303 Also consider backends where the flags register is clobbered by a
2304 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2305 lea instruction comes to mind). If we try to reload a MINUS, we
2306 may kill the flags register that was holding a useful value.
2308 So, please before trying to handle MINUS, consider reload as a
2309 whole instead of this little section as well as the backend issues. */
2311 /* If this is the sum of an eliminable register and a constant, rework
2313 if (GET_CODE (XEXP (x, 0)) == REG
2314 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2315 && CONSTANT_P (XEXP (x, 1)))
2317 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2319 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2321 /* The only time we want to replace a PLUS with a REG (this
2322 occurs when the constant operand of the PLUS is the negative
2323 of the offset) is when we are inside a MEM. We won't want
2324 to do so at other times because that would change the
2325 structure of the insn in a way that reload can't handle.
2326 We special-case the commonest situation in
2327 eliminate_regs_in_insn, so just replace a PLUS with a
2328 PLUS here, unless inside a MEM. */
2329 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2330 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2333 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2334 plus_constant (XEXP (x, 1),
2335 ep->previous_offset));
2338 /* If the register is not eliminable, we are done since the other
2339 operand is a constant. */
2343 /* If this is part of an address, we want to bring any constant to the
2344 outermost PLUS. We will do this by doing register replacement in
2345 our operands and seeing if a constant shows up in one of them.
2347 Note that there is no risk of modifying the structure of the insn,
2348 since we only get called for its operands, thus we are either
2349 modifying the address inside a MEM, or something like an address
2350 operand of a load-address insn. */
2353 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2354 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2356 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2358 /* If one side is a PLUS and the other side is a pseudo that
2359 didn't get a hard register but has a reg_equiv_constant,
2360 we must replace the constant here since it may no longer
2361 be in the position of any operand. */
2362 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2363 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2364 && reg_renumber[REGNO (new1)] < 0
2365 && reg_equiv_constant != 0
2366 && reg_equiv_constant[REGNO (new1)] != 0)
2367 new1 = reg_equiv_constant[REGNO (new1)];
2368 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2369 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2370 && reg_renumber[REGNO (new0)] < 0
2371 && reg_equiv_constant[REGNO (new0)] != 0)
2372 new0 = reg_equiv_constant[REGNO (new0)];
2374 new = form_sum (new0, new1);
2376 /* As above, if we are not inside a MEM we do not want to
2377 turn a PLUS into something else. We might try to do so here
2378 for an addition of 0 if we aren't optimizing. */
2379 if (! mem_mode && GET_CODE (new) != PLUS)
2380 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2388 /* If this is the product of an eliminable register and a
2389 constant, apply the distribute law and move the constant out
2390 so that we have (plus (mult ..) ..). This is needed in order
2391 to keep load-address insns valid. This case is pathological.
2392 We ignore the possibility of overflow here. */
2393 if (GET_CODE (XEXP (x, 0)) == REG
2394 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2395 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2396 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2398 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2401 /* Refs inside notes don't count for this purpose. */
2402 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2403 || GET_CODE (insn) == INSN_LIST)))
2404 ep->ref_outside_mem = 1;
2407 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2408 ep->previous_offset * INTVAL (XEXP (x, 1)));
2411 /* ... fall through ... */
2415 /* See comments before PLUS about handling MINUS. */
2417 case DIV: case UDIV:
2418 case MOD: case UMOD:
2419 case AND: case IOR: case XOR:
2420 case ROTATERT: case ROTATE:
2421 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2423 case GE: case GT: case GEU: case GTU:
2424 case LE: case LT: case LEU: case LTU:
2426 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2428 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2430 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2431 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2436 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2439 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2440 if (new != XEXP (x, 0))
2442 /* If this is a REG_DEAD note, it is not valid anymore.
2443 Using the eliminated version could result in creating a
2444 REG_DEAD note for the stack or frame pointer. */
2445 if (GET_MODE (x) == REG_DEAD)
2447 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2450 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2454 /* ... fall through ... */
2457 /* Now do eliminations in the rest of the chain. If this was
2458 an EXPR_LIST, this might result in allocating more memory than is
2459 strictly needed, but it simplifies the code. */
2462 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2463 if (new != XEXP (x, 1))
2465 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2473 case STRICT_LOW_PART:
2475 case SIGN_EXTEND: case ZERO_EXTEND:
2476 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2477 case FLOAT: case FIX:
2478 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2486 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2487 if (new != XEXP (x, 0))
2488 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2492 /* Similar to above processing, but preserve SUBREG_BYTE.
2493 Convert (subreg (mem)) to (mem) if not paradoxical.
2494 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2495 pseudo didn't get a hard reg, we must replace this with the
2496 eliminated version of the memory location because push_reload
2497 may do the replacement in certain circumstances. */
2498 if (GET_CODE (SUBREG_REG (x)) == REG
2499 && (GET_MODE_SIZE (GET_MODE (x))
2500 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2501 && reg_equiv_memory_loc != 0
2502 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2504 new = SUBREG_REG (x);
2507 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2509 if (new != SUBREG_REG (x))
2511 int x_size = GET_MODE_SIZE (GET_MODE (x));
2512 int new_size = GET_MODE_SIZE (GET_MODE (new));
2514 if (GET_CODE (new) == MEM
2515 && ((x_size < new_size
2516 #ifdef WORD_REGISTER_OPERATIONS
2517 /* On these machines, combine can create rtl of the form
2518 (set (subreg:m1 (reg:m2 R) 0) ...)
2519 where m1 < m2, and expects something interesting to
2520 happen to the entire word. Moreover, it will use the
2521 (reg:m2 R) later, expecting all bits to be preserved.
2522 So if the number of words is the same, preserve the
2523 subreg so that push_reload can see it. */
2524 && ! ((x_size - 1) / UNITS_PER_WORD
2525 == (new_size -1 ) / UNITS_PER_WORD)
2528 || x_size == new_size)
2530 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2532 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2538 /* This is only for the benefit of the debugging backends, which call
2539 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2540 removed after CSE. */
2541 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2542 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2544 /* Our only special processing is to pass the mode of the MEM to our
2545 recursive call and copy the flags. While we are here, handle this
2546 case more efficiently. */
2548 replace_equiv_address_nv (x,
2549 eliminate_regs (XEXP (x, 0),
2550 GET_MODE (x), insn));
2553 /* Handle insn_list USE that a call to a pure function may generate. */
2554 new = eliminate_regs (XEXP (x, 0), 0, insn);
2555 if (new != XEXP (x, 0))
2556 return gen_rtx_USE (GET_MODE (x), new);
2568 /* Process each of our operands recursively. If any have changed, make a
2570 fmt = GET_RTX_FORMAT (code);
2571 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2575 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2576 if (new != XEXP (x, i) && ! copied)
2578 rtx new_x = rtx_alloc (code);
2580 (sizeof (*new_x) - sizeof (new_x->fld)
2581 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2587 else if (*fmt == 'E')
2590 for (j = 0; j < XVECLEN (x, i); j++)
2592 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2593 if (new != XVECEXP (x, i, j) && ! copied_vec)
2595 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2599 rtx new_x = rtx_alloc (code);
2601 (sizeof (*new_x) - sizeof (new_x->fld)
2602 + (sizeof (new_x->fld[0])
2603 * GET_RTX_LENGTH (code))));
2607 XVEC (x, i) = new_v;
2610 XVECEXP (x, i, j) = new;
2618 /* Scan rtx X for modifications of elimination target registers. Update
2619 the table of eliminables to reflect the changed state. MEM_MODE is
2620 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2623 elimination_effects (rtx x, enum machine_mode mem_mode)
2625 enum rtx_code code = GET_CODE (x);
2626 struct elim_table *ep;
2653 /* First handle the case where we encounter a bare register that
2654 is eliminable. Replace it with a PLUS. */
2655 if (regno < FIRST_PSEUDO_REGISTER)
2657 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2659 if (ep->from_rtx == x && ep->can_eliminate)
2662 ep->ref_outside_mem = 1;
2667 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2668 && reg_equiv_constant[regno]
2669 && ! function_invariant_p (reg_equiv_constant[regno]))
2670 elimination_effects (reg_equiv_constant[regno], mem_mode);
2679 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2680 if (ep->to_rtx == XEXP (x, 0))
2682 int size = GET_MODE_SIZE (mem_mode);
2684 /* If more bytes than MEM_MODE are pushed, account for them. */
2685 #ifdef PUSH_ROUNDING
2686 if (ep->to_rtx == stack_pointer_rtx)
2687 size = PUSH_ROUNDING (size);
2689 if (code == PRE_DEC || code == POST_DEC)
2691 else if (code == PRE_INC || code == POST_INC)
2693 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2694 && GET_CODE (XEXP (x, 1)) == PLUS
2695 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2696 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2697 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2700 /* These two aren't unary operators. */
2701 if (code == POST_MODIFY || code == PRE_MODIFY)
2704 /* Fall through to generic unary operation case. */
2705 case STRICT_LOW_PART:
2707 case SIGN_EXTEND: case ZERO_EXTEND:
2708 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2709 case FLOAT: case FIX:
2710 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2718 elimination_effects (XEXP (x, 0), mem_mode);
2722 if (GET_CODE (SUBREG_REG (x)) == REG
2723 && (GET_MODE_SIZE (GET_MODE (x))
2724 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2725 && reg_equiv_memory_loc != 0
2726 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2729 elimination_effects (SUBREG_REG (x), mem_mode);
2733 /* If using a register that is the source of an eliminate we still
2734 think can be performed, note it cannot be performed since we don't
2735 know how this register is used. */
2736 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2737 if (ep->from_rtx == XEXP (x, 0))
2738 ep->can_eliminate = 0;
2740 elimination_effects (XEXP (x, 0), mem_mode);
2744 /* If clobbering a register that is the replacement register for an
2745 elimination we still think can be performed, note that it cannot
2746 be performed. Otherwise, we need not be concerned about it. */
2747 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2748 if (ep->to_rtx == XEXP (x, 0))
2749 ep->can_eliminate = 0;
2751 elimination_effects (XEXP (x, 0), mem_mode);
2755 /* Check for setting a register that we know about. */
2756 if (GET_CODE (SET_DEST (x)) == REG)
2758 /* See if this is setting the replacement register for an
2761 If DEST is the hard frame pointer, we do nothing because we
2762 assume that all assignments to the frame pointer are for
2763 non-local gotos and are being done at a time when they are valid
2764 and do not disturb anything else. Some machines want to
2765 eliminate a fake argument pointer (or even a fake frame pointer)
2766 with either the real frame or the stack pointer. Assignments to
2767 the hard frame pointer must not prevent this elimination. */
2769 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2771 if (ep->to_rtx == SET_DEST (x)
2772 && SET_DEST (x) != hard_frame_pointer_rtx)
2774 /* If it is being incremented, adjust the offset. Otherwise,
2775 this elimination can't be done. */
2776 rtx src = SET_SRC (x);
2778 if (GET_CODE (src) == PLUS
2779 && XEXP (src, 0) == SET_DEST (x)
2780 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2781 ep->offset -= INTVAL (XEXP (src, 1));
2783 ep->can_eliminate = 0;
2787 elimination_effects (SET_DEST (x), 0);
2788 elimination_effects (SET_SRC (x), 0);
2792 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2795 /* Our only special processing is to pass the mode of the MEM to our
2797 elimination_effects (XEXP (x, 0), GET_MODE (x));
2804 fmt = GET_RTX_FORMAT (code);
2805 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2808 elimination_effects (XEXP (x, i), mem_mode);
2809 else if (*fmt == 'E')
2810 for (j = 0; j < XVECLEN (x, i); j++)
2811 elimination_effects (XVECEXP (x, i, j), mem_mode);
2815 /* Descend through rtx X and verify that no references to eliminable registers
2816 remain. If any do remain, mark the involved register as not
2820 check_eliminable_occurrences (rtx x)
2829 code = GET_CODE (x);
2831 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2833 struct elim_table *ep;
2835 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2836 if (ep->from_rtx == x && ep->can_eliminate)
2837 ep->can_eliminate = 0;
2841 fmt = GET_RTX_FORMAT (code);
2842 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2845 check_eliminable_occurrences (XEXP (x, i));
2846 else if (*fmt == 'E')
2849 for (j = 0; j < XVECLEN (x, i); j++)
2850 check_eliminable_occurrences (XVECEXP (x, i, j));
2855 /* Scan INSN and eliminate all eliminable registers in it.
2857 If REPLACE is nonzero, do the replacement destructively. Also
2858 delete the insn as dead it if it is setting an eliminable register.
2860 If REPLACE is zero, do all our allocations in reload_obstack.
2862 If no eliminations were done and this insn doesn't require any elimination
2863 processing (these are not identical conditions: it might be updating sp,
2864 but not referencing fp; this needs to be seen during reload_as_needed so
2865 that the offset between fp and sp can be taken into consideration), zero
2866 is returned. Otherwise, 1 is returned. */
2869 eliminate_regs_in_insn (rtx insn, int replace)
2871 int icode = recog_memoized (insn);
2872 rtx old_body = PATTERN (insn);
2873 int insn_is_asm = asm_noperands (old_body) >= 0;
2874 rtx old_set = single_set (insn);
2878 rtx substed_operand[MAX_RECOG_OPERANDS];
2879 rtx orig_operand[MAX_RECOG_OPERANDS];
2880 struct elim_table *ep;
2882 if (! insn_is_asm && icode < 0)
2884 if (GET_CODE (PATTERN (insn)) == USE
2885 || GET_CODE (PATTERN (insn)) == CLOBBER
2886 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2887 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2888 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2893 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2894 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2896 /* Check for setting an eliminable register. */
2897 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2898 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2900 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2901 /* If this is setting the frame pointer register to the
2902 hardware frame pointer register and this is an elimination
2903 that will be done (tested above), this insn is really
2904 adjusting the frame pointer downward to compensate for
2905 the adjustment done before a nonlocal goto. */
2906 if (ep->from == FRAME_POINTER_REGNUM
2907 && ep->to == HARD_FRAME_POINTER_REGNUM)
2909 rtx base = SET_SRC (old_set);
2910 rtx base_insn = insn;
2913 while (base != ep->to_rtx)
2915 rtx prev_insn, prev_set;
2917 if (GET_CODE (base) == PLUS
2918 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2920 offset += INTVAL (XEXP (base, 1));
2921 base = XEXP (base, 0);
2923 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2924 && (prev_set = single_set (prev_insn)) != 0
2925 && rtx_equal_p (SET_DEST (prev_set), base))
2927 base = SET_SRC (prev_set);
2928 base_insn = prev_insn;
2934 if (base == ep->to_rtx)
2937 = plus_constant (ep->to_rtx, offset - ep->offset);
2939 new_body = old_body;
2942 new_body = copy_insn (old_body);
2943 if (REG_NOTES (insn))
2944 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2946 PATTERN (insn) = new_body;
2947 old_set = single_set (insn);
2949 /* First see if this insn remains valid when we
2950 make the change. If not, keep the INSN_CODE
2951 the same and let reload fit it up. */
2952 validate_change (insn, &SET_SRC (old_set), src, 1);
2953 validate_change (insn, &SET_DEST (old_set),
2955 if (! apply_change_group ())
2957 SET_SRC (old_set) = src;
2958 SET_DEST (old_set) = ep->to_rtx;
2967 /* In this case this insn isn't serving a useful purpose. We
2968 will delete it in reload_as_needed once we know that this
2969 elimination is, in fact, being done.
2971 If REPLACE isn't set, we can't delete this insn, but needn't
2972 process it since it won't be used unless something changes. */
2975 delete_dead_insn (insn);
2983 /* We allow one special case which happens to work on all machines we
2984 currently support: a single set with the source being a PLUS of an
2985 eliminable register and a constant. */
2987 && GET_CODE (SET_DEST (old_set)) == REG
2988 && GET_CODE (SET_SRC (old_set)) == PLUS
2989 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
2990 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
2991 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
2993 rtx reg = XEXP (SET_SRC (old_set), 0);
2994 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
2996 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2997 if (ep->from_rtx == reg && ep->can_eliminate)
2999 offset += ep->offset;
3004 /* We assume here that if we need a PARALLEL with
3005 CLOBBERs for this assignment, we can do with the
3006 MATCH_SCRATCHes that add_clobbers allocates.
3007 There's not much we can do if that doesn't work. */
3008 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3012 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3015 rtvec vec = rtvec_alloc (num_clobbers + 1);
3017 vec->elem[0] = PATTERN (insn);
3018 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3019 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3021 if (INSN_CODE (insn) < 0)
3026 new_body = old_body;
3029 new_body = copy_insn (old_body);
3030 if (REG_NOTES (insn))
3031 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3033 PATTERN (insn) = new_body;
3034 old_set = single_set (insn);
3036 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3037 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3040 /* This can't have an effect on elimination offsets, so skip right
3046 /* Determine the effects of this insn on elimination offsets. */
3047 elimination_effects (old_body, 0);
3049 /* Eliminate all eliminable registers occurring in operands that
3050 can be handled by reload. */
3051 extract_insn (insn);
3052 for (i = 0; i < recog_data.n_operands; i++)
3054 orig_operand[i] = recog_data.operand[i];
3055 substed_operand[i] = recog_data.operand[i];
3057 /* For an asm statement, every operand is eliminable. */
3058 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3060 /* Check for setting a register that we know about. */
3061 if (recog_data.operand_type[i] != OP_IN
3062 && GET_CODE (orig_operand[i]) == REG)
3064 /* If we are assigning to a register that can be eliminated, it
3065 must be as part of a PARALLEL, since the code above handles
3066 single SETs. We must indicate that we can no longer
3067 eliminate this reg. */
3068 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3070 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3071 ep->can_eliminate = 0;
3074 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3075 replace ? insn : NULL_RTX);
3076 if (substed_operand[i] != orig_operand[i])
3078 /* Terminate the search in check_eliminable_occurrences at
3080 *recog_data.operand_loc[i] = 0;
3082 /* If an output operand changed from a REG to a MEM and INSN is an
3083 insn, write a CLOBBER insn. */
3084 if (recog_data.operand_type[i] != OP_IN
3085 && GET_CODE (orig_operand[i]) == REG
3086 && GET_CODE (substed_operand[i]) == MEM
3088 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3093 for (i = 0; i < recog_data.n_dups; i++)
3094 *recog_data.dup_loc[i]
3095 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3097 /* If any eliminable remain, they aren't eliminable anymore. */
3098 check_eliminable_occurrences (old_body);
3100 /* Substitute the operands; the new values are in the substed_operand
3102 for (i = 0; i < recog_data.n_operands; i++)
3103 *recog_data.operand_loc[i] = substed_operand[i];
3104 for (i = 0; i < recog_data.n_dups; i++)
3105 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3107 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3108 re-recognize the insn. We do this in case we had a simple addition
3109 but now can do this as a load-address. This saves an insn in this
3111 If re-recognition fails, the old insn code number will still be used,
3112 and some register operands may have changed into PLUS expressions.
3113 These will be handled by find_reloads by loading them into a register
3118 /* If we aren't replacing things permanently and we changed something,
3119 make another copy to ensure that all the RTL is new. Otherwise
3120 things can go wrong if find_reload swaps commutative operands
3121 and one is inside RTL that has been copied while the other is not. */
3122 new_body = old_body;
3125 new_body = copy_insn (old_body);
3126 if (REG_NOTES (insn))
3127 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3129 PATTERN (insn) = new_body;
3131 /* If we had a move insn but now we don't, rerecognize it. This will
3132 cause spurious re-recognition if the old move had a PARALLEL since
3133 the new one still will, but we can't call single_set without
3134 having put NEW_BODY into the insn and the re-recognition won't
3135 hurt in this rare case. */
3136 /* ??? Why this huge if statement - why don't we just rerecognize the
3140 && ((GET_CODE (SET_SRC (old_set)) == REG
3141 && (GET_CODE (new_body) != SET
3142 || GET_CODE (SET_SRC (new_body)) != REG))
3143 /* If this was a load from or store to memory, compare
3144 the MEM in recog_data.operand to the one in the insn.
3145 If they are not equal, then rerecognize the insn. */
3147 && ((GET_CODE (SET_SRC (old_set)) == MEM
3148 && SET_SRC (old_set) != recog_data.operand[1])
3149 || (GET_CODE (SET_DEST (old_set)) == MEM
3150 && SET_DEST (old_set) != recog_data.operand[0])))
3151 /* If this was an add insn before, rerecognize. */
3152 || GET_CODE (SET_SRC (old_set)) == PLUS))
3154 int new_icode = recog (PATTERN (insn), insn, 0);
3156 INSN_CODE (insn) = icode;
3160 /* Restore the old body. If there were any changes to it, we made a copy
3161 of it while the changes were still in place, so we'll correctly return
3162 a modified insn below. */
3165 /* Restore the old body. */
3166 for (i = 0; i < recog_data.n_operands; i++)
3167 *recog_data.operand_loc[i] = orig_operand[i];
3168 for (i = 0; i < recog_data.n_dups; i++)
3169 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3172 /* Update all elimination pairs to reflect the status after the current
3173 insn. The changes we make were determined by the earlier call to
3174 elimination_effects.
3176 We also detect cases where register elimination cannot be done,
3177 namely, if a register would be both changed and referenced outside a MEM
3178 in the resulting insn since such an insn is often undefined and, even if
3179 not, we cannot know what meaning will be given to it. Note that it is
3180 valid to have a register used in an address in an insn that changes it
3181 (presumably with a pre- or post-increment or decrement).
3183 If anything changes, return nonzero. */
3185 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3187 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3188 ep->can_eliminate = 0;
3190 ep->ref_outside_mem = 0;
3192 if (ep->previous_offset != ep->offset)
3197 /* If we changed something, perform elimination in REG_NOTES. This is
3198 needed even when REPLACE is zero because a REG_DEAD note might refer
3199 to a register that we eliminate and could cause a different number
3200 of spill registers to be needed in the final reload pass than in
3202 if (val && REG_NOTES (insn) != 0)
3203 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3208 /* Loop through all elimination pairs.
3209 Recalculate the number not at initial offset.
3211 Compute the maximum offset (minimum offset if the stack does not
3212 grow downward) for each elimination pair. */
3215 update_eliminable_offsets (void)
3217 struct elim_table *ep;
3219 num_not_at_initial_offset = 0;
3220 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3222 ep->previous_offset = ep->offset;
3223 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3224 num_not_at_initial_offset++;
3228 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3229 replacement we currently believe is valid, mark it as not eliminable if X
3230 modifies DEST in any way other than by adding a constant integer to it.
3232 If DEST is the frame pointer, we do nothing because we assume that
3233 all assignments to the hard frame pointer are nonlocal gotos and are being
3234 done at a time when they are valid and do not disturb anything else.
3235 Some machines want to eliminate a fake argument pointer with either the
3236 frame or stack pointer. Assignments to the hard frame pointer must not
3237 prevent this elimination.
3239 Called via note_stores from reload before starting its passes to scan
3240 the insns of the function. */
3243 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3247 /* A SUBREG of a hard register here is just changing its mode. We should
3248 not see a SUBREG of an eliminable hard register, but check just in
3250 if (GET_CODE (dest) == SUBREG)
3251 dest = SUBREG_REG (dest);
3253 if (dest == hard_frame_pointer_rtx)
3256 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3257 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3258 && (GET_CODE (x) != SET
3259 || GET_CODE (SET_SRC (x)) != PLUS
3260 || XEXP (SET_SRC (x), 0) != dest
3261 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3263 reg_eliminate[i].can_eliminate_previous
3264 = reg_eliminate[i].can_eliminate = 0;
3269 /* Verify that the initial elimination offsets did not change since the
3270 last call to set_initial_elim_offsets. This is used to catch cases
3271 where something illegal happened during reload_as_needed that could
3272 cause incorrect code to be generated if we did not check for it. */
3275 verify_initial_elim_offsets (void)
3279 #ifdef ELIMINABLE_REGS
3280 struct elim_table *ep;
3282 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3284 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3285 if (t != ep->initial_offset)
3289 INITIAL_FRAME_POINTER_OFFSET (t);
3290 if (t != reg_eliminate[0].initial_offset)
3295 /* Reset all offsets on eliminable registers to their initial values. */
3298 set_initial_elim_offsets (void)
3300 struct elim_table *ep = reg_eliminate;
3302 #ifdef ELIMINABLE_REGS
3303 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3305 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3306 ep->previous_offset = ep->offset = ep->initial_offset;
3309 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3310 ep->previous_offset = ep->offset = ep->initial_offset;
3313 num_not_at_initial_offset = 0;
3316 /* Initialize the known label offsets.
3317 Set a known offset for each forced label to be at the initial offset
3318 of each elimination. We do this because we assume that all
3319 computed jumps occur from a location where each elimination is
3320 at its initial offset.
3321 For all other labels, show that we don't know the offsets. */
3324 set_initial_label_offsets (void)
3327 memset (offsets_known_at, 0, num_labels);
3329 for (x = forced_labels; x; x = XEXP (x, 1))
3331 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3334 /* Set all elimination offsets to the known values for the code label given
3338 set_offsets_for_label (rtx insn)
3341 int label_nr = CODE_LABEL_NUMBER (insn);
3342 struct elim_table *ep;
3344 num_not_at_initial_offset = 0;
3345 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3347 ep->offset = ep->previous_offset
3348 = offsets_at[label_nr - first_label_num][i];
3349 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3350 num_not_at_initial_offset++;
3354 /* See if anything that happened changes which eliminations are valid.
3355 For example, on the SPARC, whether or not the frame pointer can
3356 be eliminated can depend on what registers have been used. We need
3357 not check some conditions again (such as flag_omit_frame_pointer)
3358 since they can't have changed. */
3361 update_eliminables (HARD_REG_SET *pset)
3363 int previous_frame_pointer_needed = frame_pointer_needed;
3364 struct elim_table *ep;
3366 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3367 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3368 #ifdef ELIMINABLE_REGS
3369 || ! CAN_ELIMINATE (ep->from, ep->to)
3372 ep->can_eliminate = 0;
3374 /* Look for the case where we have discovered that we can't replace
3375 register A with register B and that means that we will now be
3376 trying to replace register A with register C. This means we can
3377 no longer replace register C with register B and we need to disable
3378 such an elimination, if it exists. This occurs often with A == ap,
3379 B == sp, and C == fp. */
3381 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3383 struct elim_table *op;
3386 if (! ep->can_eliminate && ep->can_eliminate_previous)
3388 /* Find the current elimination for ep->from, if there is a
3390 for (op = reg_eliminate;
3391 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3392 if (op->from == ep->from && op->can_eliminate)
3398 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3400 for (op = reg_eliminate;
3401 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3402 if (op->from == new_to && op->to == ep->to)
3403 op->can_eliminate = 0;
3407 /* See if any registers that we thought we could eliminate the previous
3408 time are no longer eliminable. If so, something has changed and we
3409 must spill the register. Also, recompute the number of eliminable
3410 registers and see if the frame pointer is needed; it is if there is
3411 no elimination of the frame pointer that we can perform. */
3413 frame_pointer_needed = 1;
3414 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3416 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3417 && ep->to != HARD_FRAME_POINTER_REGNUM)
3418 frame_pointer_needed = 0;
3420 if (! ep->can_eliminate && ep->can_eliminate_previous)
3422 ep->can_eliminate_previous = 0;
3423 SET_HARD_REG_BIT (*pset, ep->from);
3428 /* If we didn't need a frame pointer last time, but we do now, spill
3429 the hard frame pointer. */
3430 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3431 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3434 /* Initialize the table of registers to eliminate. */
3437 init_elim_table (void)
3439 struct elim_table *ep;
3440 #ifdef ELIMINABLE_REGS
3441 const struct elim_table_1 *ep1;
3445 reg_eliminate = (struct elim_table *)
3446 xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3448 /* Does this function require a frame pointer? */
3450 frame_pointer_needed = (! flag_omit_frame_pointer
3451 #ifdef EXIT_IGNORE_STACK
3452 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3453 and restore sp for alloca. So we can't eliminate
3454 the frame pointer in that case. At some point,
3455 we should improve this by emitting the
3456 sp-adjusting insns for this case. */
3457 || (current_function_calls_alloca
3458 && EXIT_IGNORE_STACK)
3460 || FRAME_POINTER_REQUIRED);
3464 #ifdef ELIMINABLE_REGS
3465 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3466 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3468 ep->from = ep1->from;
3470 ep->can_eliminate = ep->can_eliminate_previous
3471 = (CAN_ELIMINATE (ep->from, ep->to)
3472 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3475 reg_eliminate[0].from = reg_eliminate_1[0].from;
3476 reg_eliminate[0].to = reg_eliminate_1[0].to;
3477 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3478 = ! frame_pointer_needed;
3481 /* Count the number of eliminable registers and build the FROM and TO
3482 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3483 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3484 We depend on this. */
3485 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3487 num_eliminable += ep->can_eliminate;
3488 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3489 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3493 /* Kick all pseudos out of hard register REGNO.
3495 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3496 because we found we can't eliminate some register. In the case, no pseudos
3497 are allowed to be in the register, even if they are only in a block that
3498 doesn't require spill registers, unlike the case when we are spilling this
3499 hard reg to produce another spill register.
3501 Return nonzero if any pseudos needed to be kicked out. */
3504 spill_hard_reg (unsigned int regno, int cant_eliminate)
3510 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3511 regs_ever_live[regno] = 1;
3514 /* Spill every pseudo reg that was allocated to this reg
3515 or to something that overlaps this reg. */
3517 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3518 if (reg_renumber[i] >= 0
3519 && (unsigned int) reg_renumber[i] <= regno
3520 && ((unsigned int) reg_renumber[i]
3521 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3522 PSEUDO_REGNO_MODE (i))
3524 SET_REGNO_REG_SET (&spilled_pseudos, i);
3527 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3528 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3531 ior_hard_reg_set (HARD_REG_SET *set1, HARD_REG_SET *set2)
3533 IOR_HARD_REG_SET (*set1, *set2);
3536 /* After find_reload_regs has been run for all insn that need reloads,
3537 and/or spill_hard_regs was called, this function is used to actually
3538 spill pseudo registers and try to reallocate them. It also sets up the
3539 spill_regs array for use by choose_reload_regs. */
3542 finish_spills (int global)
3544 struct insn_chain *chain;
3545 int something_changed = 0;
3548 /* Build the spill_regs array for the function. */
3549 /* If there are some registers still to eliminate and one of the spill regs
3550 wasn't ever used before, additional stack space may have to be
3551 allocated to store this register. Thus, we may have changed the offset
3552 between the stack and frame pointers, so mark that something has changed.
3554 One might think that we need only set VAL to 1 if this is a call-used
3555 register. However, the set of registers that must be saved by the
3556 prologue is not identical to the call-used set. For example, the
3557 register used by the call insn for the return PC is a call-used register,
3558 but must be saved by the prologue. */
3561 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3562 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3564 spill_reg_order[i] = n_spills;
3565 spill_regs[n_spills++] = i;
3566 if (num_eliminable && ! regs_ever_live[i])
3567 something_changed = 1;
3568 regs_ever_live[i] = 1;
3571 spill_reg_order[i] = -1;
3573 EXECUTE_IF_SET_IN_REG_SET
3574 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3576 /* Record the current hard register the pseudo is allocated to in
3577 pseudo_previous_regs so we avoid reallocating it to the same
3578 hard reg in a later pass. */
3579 if (reg_renumber[i] < 0)
3582 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3583 /* Mark it as no longer having a hard register home. */
3584 reg_renumber[i] = -1;
3585 /* We will need to scan everything again. */
3586 something_changed = 1;
3589 /* Retry global register allocation if possible. */
3592 memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3593 /* For every insn that needs reloads, set the registers used as spill
3594 regs in pseudo_forbidden_regs for every pseudo live across the
3596 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3598 EXECUTE_IF_SET_IN_REG_SET
3599 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3601 ior_hard_reg_set (pseudo_forbidden_regs + i,
3602 &chain->used_spill_regs);
3604 EXECUTE_IF_SET_IN_REG_SET
3605 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3607 ior_hard_reg_set (pseudo_forbidden_regs + i,
3608 &chain->used_spill_regs);
3612 /* Retry allocating the spilled pseudos. For each reg, merge the
3613 various reg sets that indicate which hard regs can't be used,
3614 and call retry_global_alloc.
3615 We change spill_pseudos here to only contain pseudos that did not
3616 get a new hard register. */
3617 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3618 if (reg_old_renumber[i] != reg_renumber[i])
3620 HARD_REG_SET forbidden;
3621 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3622 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3623 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3624 retry_global_alloc (i, forbidden);
3625 if (reg_renumber[i] >= 0)
3626 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3630 /* Fix up the register information in the insn chain.
3631 This involves deleting those of the spilled pseudos which did not get
3632 a new hard register home from the live_{before,after} sets. */
3633 for (chain = reload_insn_chain; chain; chain = chain->next)
3635 HARD_REG_SET used_by_pseudos;
3636 HARD_REG_SET used_by_pseudos2;
3638 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3639 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3641 /* Mark any unallocated hard regs as available for spills. That
3642 makes inheritance work somewhat better. */
3643 if (chain->need_reload)
3645 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3646 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3647 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3649 /* Save the old value for the sanity test below. */
3650 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3652 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3653 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3654 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3655 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3657 /* Make sure we only enlarge the set. */
3658 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3664 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3665 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3667 int regno = reg_renumber[i];
3668 if (reg_old_renumber[i] == regno)
3671 alter_reg (i, reg_old_renumber[i]);
3672 reg_old_renumber[i] = regno;
3676 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3678 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3679 i, reg_renumber[i]);
3683 return something_changed;
3686 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3687 Also mark any hard registers used to store user variables as
3688 forbidden from being used for spill registers. */
3691 scan_paradoxical_subregs (rtx x)
3695 enum rtx_code code = GET_CODE (x);
3701 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3702 && REG_USERVAR_P (x))
3703 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3712 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3720 if (GET_CODE (SUBREG_REG (x)) == REG
3721 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3722 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3723 = GET_MODE_SIZE (GET_MODE (x));
3730 fmt = GET_RTX_FORMAT (code);
3731 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3734 scan_paradoxical_subregs (XEXP (x, i));
3735 else if (fmt[i] == 'E')
3738 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3739 scan_paradoxical_subregs (XVECEXP (x, i, j));
3744 /* Reload pseudo-registers into hard regs around each insn as needed.
3745 Additional register load insns are output before the insn that needs it
3746 and perhaps store insns after insns that modify the reloaded pseudo reg.
3748 reg_last_reload_reg and reg_reloaded_contents keep track of
3749 which registers are already available in reload registers.
3750 We update these for the reloads that we perform,
3751 as the insns are scanned. */
3754 reload_as_needed (int live_known)
3756 struct insn_chain *chain;
3757 #if defined (AUTO_INC_DEC)
3762 memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx);
3763 memset ((char *) spill_reg_store, 0, sizeof spill_reg_store);
3764 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3765 reg_has_output_reload = (char *) xmalloc (max_regno);
3766 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3768 set_initial_elim_offsets ();
3770 for (chain = reload_insn_chain; chain; chain = chain->next)
3773 rtx insn = chain->insn;
3774 rtx old_next = NEXT_INSN (insn);
3776 /* If we pass a label, copy the offsets from the label information
3777 into the current offsets of each elimination. */
3778 if (GET_CODE (insn) == CODE_LABEL)
3779 set_offsets_for_label (insn);
3781 else if (INSN_P (insn))
3783 rtx oldpat = copy_rtx (PATTERN (insn));
3785 /* If this is a USE and CLOBBER of a MEM, ensure that any
3786 references to eliminable registers have been removed. */
3788 if ((GET_CODE (PATTERN (insn)) == USE
3789 || GET_CODE (PATTERN (insn)) == CLOBBER)
3790 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3791 XEXP (XEXP (PATTERN (insn), 0), 0)
3792 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3793 GET_MODE (XEXP (PATTERN (insn), 0)),
3796 /* If we need to do register elimination processing, do so.
3797 This might delete the insn, in which case we are done. */
3798 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3800 eliminate_regs_in_insn (insn, 1);
3801 if (GET_CODE (insn) == NOTE)
3803 update_eliminable_offsets ();
3808 /* If need_elim is nonzero but need_reload is zero, one might think
3809 that we could simply set n_reloads to 0. However, find_reloads
3810 could have done some manipulation of the insn (such as swapping
3811 commutative operands), and these manipulations are lost during
3812 the first pass for every insn that needs register elimination.
3813 So the actions of find_reloads must be redone here. */
3815 if (! chain->need_elim && ! chain->need_reload
3816 && ! chain->need_operand_change)
3818 /* First find the pseudo regs that must be reloaded for this insn.
3819 This info is returned in the tables reload_... (see reload.h).
3820 Also modify the body of INSN by substituting RELOAD
3821 rtx's for those pseudo regs. */
3824 memset (reg_has_output_reload, 0, max_regno);
3825 CLEAR_HARD_REG_SET (reg_is_output_reload);
3827 find_reloads (insn, 1, spill_indirect_levels, live_known,
3833 rtx next = NEXT_INSN (insn);
3836 prev = PREV_INSN (insn);
3838 /* Now compute which reload regs to reload them into. Perhaps
3839 reusing reload regs from previous insns, or else output
3840 load insns to reload them. Maybe output store insns too.
3841 Record the choices of reload reg in reload_reg_rtx. */
3842 choose_reload_regs (chain);
3844 /* Merge any reloads that we didn't combine for fear of
3845 increasing the number of spill registers needed but now
3846 discover can be safely merged. */
3847 if (SMALL_REGISTER_CLASSES)
3848 merge_assigned_reloads (insn);
3850 /* Generate the insns to reload operands into or out of
3851 their reload regs. */
3852 emit_reload_insns (chain);
3854 /* Substitute the chosen reload regs from reload_reg_rtx
3855 into the insn's body (or perhaps into the bodies of other
3856 load and store insn that we just made for reloading
3857 and that we moved the structure into). */
3858 subst_reloads (insn);
3860 /* If this was an ASM, make sure that all the reload insns
3861 we have generated are valid. If not, give an error
3864 if (asm_noperands (PATTERN (insn)) >= 0)
3865 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3866 if (p != insn && INSN_P (p)
3867 && GET_CODE (PATTERN (p)) != USE
3868 && (recog_memoized (p) < 0
3869 || (extract_insn (p), ! constrain_operands (1))))
3871 error_for_asm (insn,
3872 "`asm' operand requires impossible reload");
3877 if (num_eliminable && chain->need_elim)
3878 update_eliminable_offsets ();
3880 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3881 is no longer validly lying around to save a future reload.
3882 Note that this does not detect pseudos that were reloaded
3883 for this insn in order to be stored in
3884 (obeying register constraints). That is correct; such reload
3885 registers ARE still valid. */
3886 note_stores (oldpat, forget_old_reloads_1, NULL);
3888 /* There may have been CLOBBER insns placed after INSN. So scan
3889 between INSN and NEXT and use them to forget old reloads. */
3890 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3891 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3892 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3895 /* Likewise for regs altered by auto-increment in this insn.
3896 REG_INC notes have been changed by reloading:
3897 find_reloads_address_1 records substitutions for them,
3898 which have been performed by subst_reloads above. */
3899 for (i = n_reloads - 1; i >= 0; i--)
3901 rtx in_reg = rld[i].in_reg;
3904 enum rtx_code code = GET_CODE (in_reg);
3905 /* PRE_INC / PRE_DEC will have the reload register ending up
3906 with the same value as the stack slot, but that doesn't
3907 hold true for POST_INC / POST_DEC. Either we have to
3908 convert the memory access to a true POST_INC / POST_DEC,
3909 or we can't use the reload register for inheritance. */
3910 if ((code == POST_INC || code == POST_DEC)
3911 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3912 REGNO (rld[i].reg_rtx))
3913 /* Make sure it is the inc/dec pseudo, and not
3914 some other (e.g. output operand) pseudo. */
3915 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3916 == REGNO (XEXP (in_reg, 0))))
3919 rtx reload_reg = rld[i].reg_rtx;
3920 enum machine_mode mode = GET_MODE (reload_reg);
3924 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3926 /* We really want to ignore REG_INC notes here, so
3927 use PATTERN (p) as argument to reg_set_p . */
3928 if (reg_set_p (reload_reg, PATTERN (p)))
3930 n = count_occurrences (PATTERN (p), reload_reg, 0);
3935 n = validate_replace_rtx (reload_reg,
3936 gen_rtx (code, mode,
3940 /* We must also verify that the constraints
3941 are met after the replacement. */
3944 n = constrain_operands (1);
3948 /* If the constraints were not met, then
3949 undo the replacement. */
3952 validate_replace_rtx (gen_rtx (code, mode,
3964 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3966 /* Mark this as having an output reload so that the
3967 REG_INC processing code below won't invalidate
3968 the reload for inheritance. */
3969 SET_HARD_REG_BIT (reg_is_output_reload,
3970 REGNO (reload_reg));
3971 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3974 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3977 else if ((code == PRE_INC || code == PRE_DEC)
3978 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3979 REGNO (rld[i].reg_rtx))
3980 /* Make sure it is the inc/dec pseudo, and not
3981 some other (e.g. output operand) pseudo. */
3982 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3983 == REGNO (XEXP (in_reg, 0))))
3985 SET_HARD_REG_BIT (reg_is_output_reload,
3986 REGNO (rld[i].reg_rtx));
3987 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3991 /* If a pseudo that got a hard register is auto-incremented,
3992 we must purge records of copying it into pseudos without
3994 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3995 if (REG_NOTE_KIND (x) == REG_INC)
3997 /* See if this pseudo reg was reloaded in this insn.
3998 If so, its last-reload info is still valid
3999 because it is based on this insn's reload. */
4000 for (i = 0; i < n_reloads; i++)
4001 if (rld[i].out == XEXP (x, 0))
4005 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4009 /* A reload reg's contents are unknown after a label. */
4010 if (GET_CODE (insn) == CODE_LABEL)
4011 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4013 /* Don't assume a reload reg is still good after a call insn
4014 if it is a call-used reg. */
4015 else if (GET_CODE (insn) == CALL_INSN)
4016 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4020 free (reg_last_reload_reg);
4021 free (reg_has_output_reload);
4024 /* Discard all record of any value reloaded from X,
4025 or reloaded in X from someplace else;
4026 unless X is an output reload reg of the current insn.
4028 X may be a hard reg (the reload reg)
4029 or it may be a pseudo reg that was reloaded from. */
4032 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4033 void *data ATTRIBUTE_UNUSED)
4038 /* note_stores does give us subregs of hard regs,
4039 subreg_regno_offset will abort if it is not a hard reg. */
4040 while (GET_CODE (x) == SUBREG)
4042 /* We ignore the subreg offset when calculating the regno,
4043 because we are using the entire underlying hard register
4048 if (GET_CODE (x) != REG)
4053 if (regno >= FIRST_PSEUDO_REGISTER)
4059 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4060 /* Storing into a spilled-reg invalidates its contents.
4061 This can happen if a block-local pseudo is allocated to that reg
4062 and it wasn't spilled because this block's total need is 0.
4063 Then some insn might have an optional reload and use this reg. */
4064 for (i = 0; i < nr; i++)
4065 /* But don't do this if the reg actually serves as an output
4066 reload reg in the current instruction. */
4068 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4070 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4071 spill_reg_store[regno + i] = 0;
4075 /* Since value of X has changed,
4076 forget any value previously copied from it. */
4079 /* But don't forget a copy if this is the output reload
4080 that establishes the copy's validity. */
4081 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4082 reg_last_reload_reg[regno + nr] = 0;
4085 /* The following HARD_REG_SETs indicate when each hard register is
4086 used for a reload of various parts of the current insn. */
4088 /* If reg is unavailable for all reloads. */
4089 static HARD_REG_SET reload_reg_unavailable;
4090 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4091 static HARD_REG_SET reload_reg_used;
4092 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4093 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4094 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4095 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4096 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4097 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4098 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4099 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4100 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4101 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4102 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4103 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4104 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4105 static HARD_REG_SET reload_reg_used_in_op_addr;
4106 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4107 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4108 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4109 static HARD_REG_SET reload_reg_used_in_insn;
4110 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4111 static HARD_REG_SET reload_reg_used_in_other_addr;
4113 /* If reg is in use as a reload reg for any sort of reload. */
4114 static HARD_REG_SET reload_reg_used_at_all;
4116 /* If reg is use as an inherited reload. We just mark the first register
4118 static HARD_REG_SET reload_reg_used_for_inherit;
4120 /* Records which hard regs are used in any way, either as explicit use or
4121 by being allocated to a pseudo during any point of the current insn. */
4122 static HARD_REG_SET reg_used_in_insn;
4124 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4125 TYPE. MODE is used to indicate how many consecutive regs are
4129 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4130 enum machine_mode mode)
4132 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4135 for (i = regno; i < nregs + regno; i++)
4140 SET_HARD_REG_BIT (reload_reg_used, i);
4143 case RELOAD_FOR_INPUT_ADDRESS:
4144 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4147 case RELOAD_FOR_INPADDR_ADDRESS:
4148 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4151 case RELOAD_FOR_OUTPUT_ADDRESS:
4152 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4155 case RELOAD_FOR_OUTADDR_ADDRESS:
4156 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4159 case RELOAD_FOR_OPERAND_ADDRESS:
4160 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4163 case RELOAD_FOR_OPADDR_ADDR:
4164 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4167 case RELOAD_FOR_OTHER_ADDRESS:
4168 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4171 case RELOAD_FOR_INPUT:
4172 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4175 case RELOAD_FOR_OUTPUT:
4176 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4179 case RELOAD_FOR_INSN:
4180 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4184 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4188 /* Similarly, but show REGNO is no longer in use for a reload. */
4191 clear_reload_reg_in_use (unsigned int regno, int opnum,
4192 enum reload_type type, enum machine_mode mode)
4194 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4195 unsigned int start_regno, end_regno, r;
4197 /* A complication is that for some reload types, inheritance might
4198 allow multiple reloads of the same types to share a reload register.
4199 We set check_opnum if we have to check only reloads with the same
4200 operand number, and check_any if we have to check all reloads. */
4201 int check_opnum = 0;
4203 HARD_REG_SET *used_in_set;
4208 used_in_set = &reload_reg_used;
4211 case RELOAD_FOR_INPUT_ADDRESS:
4212 used_in_set = &reload_reg_used_in_input_addr[opnum];
4215 case RELOAD_FOR_INPADDR_ADDRESS:
4217 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4220 case RELOAD_FOR_OUTPUT_ADDRESS:
4221 used_in_set = &reload_reg_used_in_output_addr[opnum];
4224 case RELOAD_FOR_OUTADDR_ADDRESS:
4226 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4229 case RELOAD_FOR_OPERAND_ADDRESS:
4230 used_in_set = &reload_reg_used_in_op_addr;
4233 case RELOAD_FOR_OPADDR_ADDR:
4235 used_in_set = &reload_reg_used_in_op_addr_reload;
4238 case RELOAD_FOR_OTHER_ADDRESS:
4239 used_in_set = &reload_reg_used_in_other_addr;
4243 case RELOAD_FOR_INPUT:
4244 used_in_set = &reload_reg_used_in_input[opnum];
4247 case RELOAD_FOR_OUTPUT:
4248 used_in_set = &reload_reg_used_in_output[opnum];
4251 case RELOAD_FOR_INSN:
4252 used_in_set = &reload_reg_used_in_insn;
4257 /* We resolve conflicts with remaining reloads of the same type by
4258 excluding the intervals of reload registers by them from the
4259 interval of freed reload registers. Since we only keep track of
4260 one set of interval bounds, we might have to exclude somewhat
4261 more than what would be necessary if we used a HARD_REG_SET here.
4262 But this should only happen very infrequently, so there should
4263 be no reason to worry about it. */
4265 start_regno = regno;
4266 end_regno = regno + nregs;
4267 if (check_opnum || check_any)
4269 for (i = n_reloads - 1; i >= 0; i--)
4271 if (rld[i].when_needed == type
4272 && (check_any || rld[i].opnum == opnum)
4275 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4276 unsigned int conflict_end
4278 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4280 /* If there is an overlap with the first to-be-freed register,
4281 adjust the interval start. */
4282 if (conflict_start <= start_regno && conflict_end > start_regno)
4283 start_regno = conflict_end;
4284 /* Otherwise, if there is a conflict with one of the other
4285 to-be-freed registers, adjust the interval end. */
4286 if (conflict_start > start_regno && conflict_start < end_regno)
4287 end_regno = conflict_start;
4292 for (r = start_regno; r < end_regno; r++)
4293 CLEAR_HARD_REG_BIT (*used_in_set, r);
4296 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4297 specified by OPNUM and TYPE. */
4300 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4304 /* In use for a RELOAD_OTHER means it's not available for anything. */
4305 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4306 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4312 /* In use for anything means we can't use it for RELOAD_OTHER. */
4313 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4314 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4315 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4318 for (i = 0; i < reload_n_operands; i++)
4319 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4320 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4321 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4322 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4323 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4324 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4329 case RELOAD_FOR_INPUT:
4330 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4331 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4334 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4337 /* If it is used for some other input, can't use it. */
4338 for (i = 0; i < reload_n_operands; i++)
4339 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4342 /* If it is used in a later operand's address, can't use it. */
4343 for (i = opnum + 1; i < reload_n_operands; i++)
4344 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4345 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4350 case RELOAD_FOR_INPUT_ADDRESS:
4351 /* Can't use a register if it is used for an input address for this
4352 operand or used as an input in an earlier one. */
4353 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4354 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4357 for (i = 0; i < opnum; i++)
4358 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4363 case RELOAD_FOR_INPADDR_ADDRESS:
4364 /* Can't use a register if it is used for an input address
4365 for this operand or used as an input in an earlier
4367 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4370 for (i = 0; i < opnum; i++)
4371 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4376 case RELOAD_FOR_OUTPUT_ADDRESS:
4377 /* Can't use a register if it is used for an output address for this
4378 operand or used as an output in this or a later operand. Note
4379 that multiple output operands are emitted in reverse order, so
4380 the conflicting ones are those with lower indices. */
4381 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4384 for (i = 0; i <= opnum; i++)
4385 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4390 case RELOAD_FOR_OUTADDR_ADDRESS:
4391 /* Can't use a register if it is used for an output address
4392 for this operand or used as an output in this or a
4393 later operand. Note that multiple output operands are
4394 emitted in reverse order, so the conflicting ones are
4395 those with lower indices. */
4396 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4399 for (i = 0; i <= opnum; i++)
4400 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4405 case RELOAD_FOR_OPERAND_ADDRESS:
4406 for (i = 0; i < reload_n_operands; i++)
4407 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4410 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4411 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4413 case RELOAD_FOR_OPADDR_ADDR:
4414 for (i = 0; i < reload_n_operands; i++)
4415 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4418 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4420 case RELOAD_FOR_OUTPUT:
4421 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4422 outputs, or an operand address for this or an earlier output.
4423 Note that multiple output operands are emitted in reverse order,
4424 so the conflicting ones are those with higher indices. */
4425 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4428 for (i = 0; i < reload_n_operands; i++)
4429 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4432 for (i = opnum; i < reload_n_operands; i++)
4433 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4434 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4439 case RELOAD_FOR_INSN:
4440 for (i = 0; i < reload_n_operands; i++)
4441 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4442 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4445 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4446 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4448 case RELOAD_FOR_OTHER_ADDRESS:
4449 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4454 /* Return 1 if the value in reload reg REGNO, as used by a reload
4455 needed for the part of the insn specified by OPNUM and TYPE,
4456 is still available in REGNO at the end of the insn.
4458 We can assume that the reload reg was already tested for availability
4459 at the time it is needed, and we should not check this again,
4460 in case the reg has already been marked in use. */
4463 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4470 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4471 its value must reach the end. */
4474 /* If this use is for part of the insn,
4475 its value reaches if no subsequent part uses the same register.
4476 Just like the above function, don't try to do this with lots
4479 case RELOAD_FOR_OTHER_ADDRESS:
4480 /* Here we check for everything else, since these don't conflict
4481 with anything else and everything comes later. */
4483 for (i = 0; i < reload_n_operands; i++)
4484 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4485 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4486 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4487 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4488 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4489 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4492 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4493 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4494 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4496 case RELOAD_FOR_INPUT_ADDRESS:
4497 case RELOAD_FOR_INPADDR_ADDRESS:
4498 /* Similar, except that we check only for this and subsequent inputs
4499 and the address of only subsequent inputs and we do not need
4500 to check for RELOAD_OTHER objects since they are known not to
4503 for (i = opnum; i < reload_n_operands; i++)
4504 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4507 for (i = opnum + 1; i < reload_n_operands; i++)
4508 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4509 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4512 for (i = 0; i < reload_n_operands; i++)
4513 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4514 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4515 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4518 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4521 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4522 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4523 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4525 case RELOAD_FOR_INPUT:
4526 /* Similar to input address, except we start at the next operand for
4527 both input and input address and we do not check for
4528 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4531 for (i = opnum + 1; i < reload_n_operands; i++)
4532 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4533 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4534 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4537 /* ... fall through ... */
4539 case RELOAD_FOR_OPERAND_ADDRESS:
4540 /* Check outputs and their addresses. */
4542 for (i = 0; i < reload_n_operands; i++)
4543 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4544 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4545 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4548 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4550 case RELOAD_FOR_OPADDR_ADDR:
4551 for (i = 0; i < reload_n_operands; i++)
4552 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4553 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4554 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4557 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4558 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4559 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4561 case RELOAD_FOR_INSN:
4562 /* These conflict with other outputs with RELOAD_OTHER. So
4563 we need only check for output addresses. */
4565 opnum = reload_n_operands;
4567 /* ... fall through ... */
4569 case RELOAD_FOR_OUTPUT:
4570 case RELOAD_FOR_OUTPUT_ADDRESS:
4571 case RELOAD_FOR_OUTADDR_ADDRESS:
4572 /* We already know these can't conflict with a later output. So the
4573 only thing to check are later output addresses.
4574 Note that multiple output operands are emitted in reverse order,
4575 so the conflicting ones are those with lower indices. */
4576 for (i = 0; i < opnum; i++)
4577 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4578 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4587 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4590 This function uses the same algorithm as reload_reg_free_p above. */
4593 reloads_conflict (int r1, int r2)
4595 enum reload_type r1_type = rld[r1].when_needed;
4596 enum reload_type r2_type = rld[r2].when_needed;
4597 int r1_opnum = rld[r1].opnum;
4598 int r2_opnum = rld[r2].opnum;
4600 /* RELOAD_OTHER conflicts with everything. */
4601 if (r2_type == RELOAD_OTHER)
4604 /* Otherwise, check conflicts differently for each type. */
4608 case RELOAD_FOR_INPUT:
4609 return (r2_type == RELOAD_FOR_INSN
4610 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4611 || r2_type == RELOAD_FOR_OPADDR_ADDR
4612 || r2_type == RELOAD_FOR_INPUT
4613 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4614 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4615 && r2_opnum > r1_opnum));
4617 case RELOAD_FOR_INPUT_ADDRESS:
4618 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4619 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4621 case RELOAD_FOR_INPADDR_ADDRESS:
4622 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4623 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4625 case RELOAD_FOR_OUTPUT_ADDRESS:
4626 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4627 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4629 case RELOAD_FOR_OUTADDR_ADDRESS:
4630 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4631 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4633 case RELOAD_FOR_OPERAND_ADDRESS:
4634 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4635 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4637 case RELOAD_FOR_OPADDR_ADDR:
4638 return (r2_type == RELOAD_FOR_INPUT
4639 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4641 case RELOAD_FOR_OUTPUT:
4642 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4643 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4644 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4645 && r2_opnum >= r1_opnum));
4647 case RELOAD_FOR_INSN:
4648 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4649 || r2_type == RELOAD_FOR_INSN
4650 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4652 case RELOAD_FOR_OTHER_ADDRESS:
4653 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4663 /* Indexed by reload number, 1 if incoming value
4664 inherited from previous insns. */
4665 char reload_inherited[MAX_RELOADS];
4667 /* For an inherited reload, this is the insn the reload was inherited from,
4668 if we know it. Otherwise, this is 0. */
4669 rtx reload_inheritance_insn[MAX_RELOADS];
4671 /* If nonzero, this is a place to get the value of the reload,
4672 rather than using reload_in. */
4673 rtx reload_override_in[MAX_RELOADS];
4675 /* For each reload, the hard register number of the register used,
4676 or -1 if we did not need a register for this reload. */
4677 int reload_spill_index[MAX_RELOADS];
4679 /* Subroutine of free_for_value_p, used to check a single register.
4680 START_REGNO is the starting regno of the full reload register
4681 (possibly comprising multiple hard registers) that we are considering. */
4684 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4685 enum reload_type type, rtx value, rtx out,
4686 int reloadnum, int ignore_address_reloads)
4689 /* Set if we see an input reload that must not share its reload register
4690 with any new earlyclobber, but might otherwise share the reload
4691 register with an output or input-output reload. */
4692 int check_earlyclobber = 0;
4696 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4699 if (out == const0_rtx)
4705 /* We use some pseudo 'time' value to check if the lifetimes of the
4706 new register use would overlap with the one of a previous reload
4707 that is not read-only or uses a different value.
4708 The 'time' used doesn't have to be linear in any shape or form, just
4710 Some reload types use different 'buckets' for each operand.
4711 So there are MAX_RECOG_OPERANDS different time values for each
4713 We compute TIME1 as the time when the register for the prospective
4714 new reload ceases to be live, and TIME2 for each existing
4715 reload as the time when that the reload register of that reload
4717 Where there is little to be gained by exact lifetime calculations,
4718 we just make conservative assumptions, i.e. a longer lifetime;
4719 this is done in the 'default:' cases. */
4722 case RELOAD_FOR_OTHER_ADDRESS:
4723 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4724 time1 = copy ? 0 : 1;
4727 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4729 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4730 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4731 respectively, to the time values for these, we get distinct time
4732 values. To get distinct time values for each operand, we have to
4733 multiply opnum by at least three. We round that up to four because
4734 multiply by four is often cheaper. */
4735 case RELOAD_FOR_INPADDR_ADDRESS:
4736 time1 = opnum * 4 + 2;
4738 case RELOAD_FOR_INPUT_ADDRESS:
4739 time1 = opnum * 4 + 3;
4741 case RELOAD_FOR_INPUT:
4742 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4743 executes (inclusive). */
4744 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4746 case RELOAD_FOR_OPADDR_ADDR:
4748 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4749 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4751 case RELOAD_FOR_OPERAND_ADDRESS:
4752 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4754 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4756 case RELOAD_FOR_OUTADDR_ADDRESS:
4757 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4759 case RELOAD_FOR_OUTPUT_ADDRESS:
4760 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4763 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4766 for (i = 0; i < n_reloads; i++)
4768 rtx reg = rld[i].reg_rtx;
4769 if (reg && GET_CODE (reg) == REG
4770 && ((unsigned) regno - true_regnum (reg)
4771 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned) 1)
4774 rtx other_input = rld[i].in;
4776 /* If the other reload loads the same input value, that
4777 will not cause a conflict only if it's loading it into
4778 the same register. */
4779 if (true_regnum (reg) != start_regno)
4780 other_input = NULL_RTX;
4781 if (! other_input || ! rtx_equal_p (other_input, value)
4782 || rld[i].out || out)
4785 switch (rld[i].when_needed)
4787 case RELOAD_FOR_OTHER_ADDRESS:
4790 case RELOAD_FOR_INPADDR_ADDRESS:
4791 /* find_reloads makes sure that a
4792 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4793 by at most one - the first -
4794 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4795 address reload is inherited, the address address reload
4796 goes away, so we can ignore this conflict. */
4797 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4798 && ignore_address_reloads
4799 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4800 Then the address address is still needed to store
4801 back the new address. */
4802 && ! rld[reloadnum].out)
4804 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4805 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4807 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4808 && ignore_address_reloads
4809 /* Unless we are reloading an auto_inc expression. */
4810 && ! rld[reloadnum].out)
4812 time2 = rld[i].opnum * 4 + 2;
4814 case RELOAD_FOR_INPUT_ADDRESS:
4815 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4816 && ignore_address_reloads
4817 && ! rld[reloadnum].out)
4819 time2 = rld[i].opnum * 4 + 3;
4821 case RELOAD_FOR_INPUT:
4822 time2 = rld[i].opnum * 4 + 4;
4823 check_earlyclobber = 1;
4825 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4826 == MAX_RECOG_OPERAND * 4 */
4827 case RELOAD_FOR_OPADDR_ADDR:
4828 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4829 && ignore_address_reloads
4830 && ! rld[reloadnum].out)
4832 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4834 case RELOAD_FOR_OPERAND_ADDRESS:
4835 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4836 check_earlyclobber = 1;
4838 case RELOAD_FOR_INSN:
4839 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4841 case RELOAD_FOR_OUTPUT:
4842 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4843 instruction is executed. */
4844 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4846 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4847 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4849 case RELOAD_FOR_OUTADDR_ADDRESS:
4850 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4851 && ignore_address_reloads
4852 && ! rld[reloadnum].out)
4854 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4856 case RELOAD_FOR_OUTPUT_ADDRESS:
4857 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4860 /* If there is no conflict in the input part, handle this
4861 like an output reload. */
4862 if (! rld[i].in || rtx_equal_p (other_input, value))
4864 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4865 /* Earlyclobbered outputs must conflict with inputs. */
4866 if (earlyclobber_operand_p (rld[i].out))
4867 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4872 /* RELOAD_OTHER might be live beyond instruction execution,
4873 but this is not obvious when we set time2 = 1. So check
4874 here if there might be a problem with the new reload
4875 clobbering the register used by the RELOAD_OTHER. */
4883 && (! rld[i].in || rld[i].out
4884 || ! rtx_equal_p (other_input, value)))
4885 || (out && rld[reloadnum].out_reg
4886 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4892 /* Earlyclobbered outputs must conflict with inputs. */
4893 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4899 /* Return 1 if the value in reload reg REGNO, as used by a reload
4900 needed for the part of the insn specified by OPNUM and TYPE,
4901 may be used to load VALUE into it.
4903 MODE is the mode in which the register is used, this is needed to
4904 determine how many hard regs to test.
4906 Other read-only reloads with the same value do not conflict
4907 unless OUT is nonzero and these other reloads have to live while
4908 output reloads live.
4909 If OUT is CONST0_RTX, this is a special case: it means that the
4910 test should not be for using register REGNO as reload register, but
4911 for copying from register REGNO into the reload register.
4913 RELOADNUM is the number of the reload we want to load this value for;
4914 a reload does not conflict with itself.
4916 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4917 reloads that load an address for the very reload we are considering.
4919 The caller has to make sure that there is no conflict with the return
4923 free_for_value_p (int regno, enum machine_mode mode, int opnum,
4924 enum reload_type type, rtx value, rtx out, int reloadnum,
4925 int ignore_address_reloads)
4927 int nregs = HARD_REGNO_NREGS (regno, mode);
4929 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4930 value, out, reloadnum,
4931 ignore_address_reloads))
4936 /* Determine whether the reload reg X overlaps any rtx'es used for
4937 overriding inheritance. Return nonzero if so. */
4940 conflicts_with_override (rtx x)
4943 for (i = 0; i < n_reloads; i++)
4944 if (reload_override_in[i]
4945 && reg_overlap_mentioned_p (x, reload_override_in[i]))
4950 /* Give an error message saying we failed to find a reload for INSN,
4951 and clear out reload R. */
4953 failed_reload (rtx insn, int r)
4955 if (asm_noperands (PATTERN (insn)) < 0)
4956 /* It's the compiler's fault. */
4957 fatal_insn ("could not find a spill register", insn);
4959 /* It's the user's fault; the operand's mode and constraint
4960 don't match. Disable this reload so we don't crash in final. */
4961 error_for_asm (insn,
4962 "`asm' operand constraint incompatible with operand size");
4966 rld[r].optional = 1;
4967 rld[r].secondary_p = 1;
4970 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
4971 for reload R. If it's valid, get an rtx for it. Return nonzero if
4974 set_reload_reg (int i, int r)
4977 rtx reg = spill_reg_rtx[i];
4979 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
4980 spill_reg_rtx[i] = reg
4981 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
4983 regno = true_regnum (reg);
4985 /* Detect when the reload reg can't hold the reload mode.
4986 This used to be one `if', but Sequent compiler can't handle that. */
4987 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
4989 enum machine_mode test_mode = VOIDmode;
4991 test_mode = GET_MODE (rld[r].in);
4992 /* If rld[r].in has VOIDmode, it means we will load it
4993 in whatever mode the reload reg has: to wit, rld[r].mode.
4994 We have already tested that for validity. */
4995 /* Aside from that, we need to test that the expressions
4996 to reload from or into have modes which are valid for this
4997 reload register. Otherwise the reload insns would be invalid. */
4998 if (! (rld[r].in != 0 && test_mode != VOIDmode
4999 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5000 if (! (rld[r].out != 0
5001 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5003 /* The reg is OK. */
5006 /* Mark as in use for this insn the reload regs we use
5008 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5009 rld[r].when_needed, rld[r].mode);
5011 rld[r].reg_rtx = reg;
5012 reload_spill_index[r] = spill_regs[i];
5019 /* Find a spill register to use as a reload register for reload R.
5020 LAST_RELOAD is nonzero if this is the last reload for the insn being
5023 Set rld[R].reg_rtx to the register allocated.
5025 We return 1 if successful, or 0 if we couldn't find a spill reg and
5026 we didn't change anything. */
5029 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5034 /* If we put this reload ahead, thinking it is a group,
5035 then insist on finding a group. Otherwise we can grab a
5036 reg that some other reload needs.
5037 (That can happen when we have a 68000 DATA_OR_FP_REG
5038 which is a group of data regs or one fp reg.)
5039 We need not be so restrictive if there are no more reloads
5042 ??? Really it would be nicer to have smarter handling
5043 for that kind of reg class, where a problem like this is normal.
5044 Perhaps those classes should be avoided for reloading
5045 by use of more alternatives. */
5047 int force_group = rld[r].nregs > 1 && ! last_reload;
5049 /* If we want a single register and haven't yet found one,
5050 take any reg in the right class and not in use.
5051 If we want a consecutive group, here is where we look for it.
5053 We use two passes so we can first look for reload regs to
5054 reuse, which are already in use for other reloads in this insn,
5055 and only then use additional registers.
5056 I think that maximizing reuse is needed to make sure we don't
5057 run out of reload regs. Suppose we have three reloads, and
5058 reloads A and B can share regs. These need two regs.
5059 Suppose A and B are given different regs.
5060 That leaves none for C. */
5061 for (pass = 0; pass < 2; pass++)
5063 /* I is the index in spill_regs.
5064 We advance it round-robin between insns to use all spill regs
5065 equally, so that inherited reloads have a chance
5066 of leapfrogging each other. */
5070 for (count = 0; count < n_spills; count++)
5072 int class = (int) rld[r].class;
5078 regnum = spill_regs[i];
5080 if ((reload_reg_free_p (regnum, rld[r].opnum,
5083 /* We check reload_reg_used to make sure we
5084 don't clobber the return register. */
5085 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5086 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5087 rld[r].when_needed, rld[r].in,
5089 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5090 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5091 /* Look first for regs to share, then for unshared. But
5092 don't share regs used for inherited reloads; they are
5093 the ones we want to preserve. */
5095 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5097 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5100 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5101 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5102 (on 68000) got us two FP regs. If NR is 1,
5103 we would reject both of them. */
5106 /* If we need only one reg, we have already won. */
5109 /* But reject a single reg if we demand a group. */
5114 /* Otherwise check that as many consecutive regs as we need
5115 are available here. */
5118 int regno = regnum + nr - 1;
5119 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5120 && spill_reg_order[regno] >= 0
5121 && reload_reg_free_p (regno, rld[r].opnum,
5122 rld[r].when_needed)))
5131 /* If we found something on pass 1, omit pass 2. */
5132 if (count < n_spills)
5136 /* We should have found a spill register by now. */
5137 if (count >= n_spills)
5140 /* I is the index in SPILL_REG_RTX of the reload register we are to
5141 allocate. Get an rtx for it and find its register number. */
5143 return set_reload_reg (i, r);
5146 /* Initialize all the tables needed to allocate reload registers.
5147 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5148 is the array we use to restore the reg_rtx field for every reload. */
5151 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5155 for (i = 0; i < n_reloads; i++)
5156 rld[i].reg_rtx = save_reload_reg_rtx[i];
5158 memset (reload_inherited, 0, MAX_RELOADS);
5159 memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5160 memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5162 CLEAR_HARD_REG_SET (reload_reg_used);
5163 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5164 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5165 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5166 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5167 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5169 CLEAR_HARD_REG_SET (reg_used_in_insn);
5172 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5173 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5174 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5175 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5176 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5177 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5180 for (i = 0; i < reload_n_operands; i++)
5182 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5183 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5184 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5185 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5186 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5187 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5190 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5192 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5194 for (i = 0; i < n_reloads; i++)
5195 /* If we have already decided to use a certain register,
5196 don't use it in another way. */
5198 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5199 rld[i].when_needed, rld[i].mode);
5202 /* Assign hard reg targets for the pseudo-registers we must reload
5203 into hard regs for this insn.
5204 Also output the instructions to copy them in and out of the hard regs.
5206 For machines with register classes, we are responsible for
5207 finding a reload reg in the proper class. */
5210 choose_reload_regs (struct insn_chain *chain)
5212 rtx insn = chain->insn;
5214 unsigned int max_group_size = 1;
5215 enum reg_class group_class = NO_REGS;
5216 int pass, win, inheritance;
5218 rtx save_reload_reg_rtx[MAX_RELOADS];
5220 /* In order to be certain of getting the registers we need,
5221 we must sort the reloads into order of increasing register class.
5222 Then our grabbing of reload registers will parallel the process
5223 that provided the reload registers.
5225 Also note whether any of the reloads wants a consecutive group of regs.
5226 If so, record the maximum size of the group desired and what
5227 register class contains all the groups needed by this insn. */
5229 for (j = 0; j < n_reloads; j++)
5231 reload_order[j] = j;
5232 reload_spill_index[j] = -1;
5234 if (rld[j].nregs > 1)
5236 max_group_size = MAX (rld[j].nregs, max_group_size);
5238 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5241 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5245 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5247 /* If -O, try first with inheritance, then turning it off.
5248 If not -O, don't do inheritance.
5249 Using inheritance when not optimizing leads to paradoxes
5250 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5251 because one side of the comparison might be inherited. */
5253 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5255 choose_reload_regs_init (chain, save_reload_reg_rtx);
5257 /* Process the reloads in order of preference just found.
5258 Beyond this point, subregs can be found in reload_reg_rtx.
5260 This used to look for an existing reloaded home for all of the
5261 reloads, and only then perform any new reloads. But that could lose
5262 if the reloads were done out of reg-class order because a later
5263 reload with a looser constraint might have an old home in a register
5264 needed by an earlier reload with a tighter constraint.
5266 To solve this, we make two passes over the reloads, in the order
5267 described above. In the first pass we try to inherit a reload
5268 from a previous insn. If there is a later reload that needs a
5269 class that is a proper subset of the class being processed, we must
5270 also allocate a spill register during the first pass.
5272 Then make a second pass over the reloads to allocate any reloads
5273 that haven't been given registers yet. */
5275 for (j = 0; j < n_reloads; j++)
5277 int r = reload_order[j];
5278 rtx search_equiv = NULL_RTX;
5280 /* Ignore reloads that got marked inoperative. */
5281 if (rld[r].out == 0 && rld[r].in == 0
5282 && ! rld[r].secondary_p)
5285 /* If find_reloads chose to use reload_in or reload_out as a reload
5286 register, we don't need to chose one. Otherwise, try even if it
5287 found one since we might save an insn if we find the value lying
5289 Try also when reload_in is a pseudo without a hard reg. */
5290 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5291 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5292 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5293 && GET_CODE (rld[r].in) != MEM
5294 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5297 #if 0 /* No longer needed for correct operation.
5298 It might give better code, or might not; worth an experiment? */
5299 /* If this is an optional reload, we can't inherit from earlier insns
5300 until we are sure that any non-optional reloads have been allocated.
5301 The following code takes advantage of the fact that optional reloads
5302 are at the end of reload_order. */
5303 if (rld[r].optional != 0)
5304 for (i = 0; i < j; i++)
5305 if ((rld[reload_order[i]].out != 0
5306 || rld[reload_order[i]].in != 0
5307 || rld[reload_order[i]].secondary_p)
5308 && ! rld[reload_order[i]].optional
5309 && rld[reload_order[i]].reg_rtx == 0)
5310 allocate_reload_reg (chain, reload_order[i], 0);
5313 /* First see if this pseudo is already available as reloaded
5314 for a previous insn. We cannot try to inherit for reloads
5315 that are smaller than the maximum number of registers needed
5316 for groups unless the register we would allocate cannot be used
5319 We could check here to see if this is a secondary reload for
5320 an object that is already in a register of the desired class.
5321 This would avoid the need for the secondary reload register.
5322 But this is complex because we can't easily determine what
5323 objects might want to be loaded via this reload. So let a
5324 register be allocated here. In `emit_reload_insns' we suppress
5325 one of the loads in the case described above. */
5331 enum machine_mode mode = VOIDmode;
5335 else if (GET_CODE (rld[r].in) == REG)
5337 regno = REGNO (rld[r].in);
5338 mode = GET_MODE (rld[r].in);
5340 else if (GET_CODE (rld[r].in_reg) == REG)
5342 regno = REGNO (rld[r].in_reg);
5343 mode = GET_MODE (rld[r].in_reg);
5345 else if (GET_CODE (rld[r].in_reg) == SUBREG
5346 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5348 byte = SUBREG_BYTE (rld[r].in_reg);
5349 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5350 if (regno < FIRST_PSEUDO_REGISTER)
5351 regno = subreg_regno (rld[r].in_reg);
5352 mode = GET_MODE (rld[r].in_reg);
5355 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5356 || GET_CODE (rld[r].in_reg) == PRE_DEC
5357 || GET_CODE (rld[r].in_reg) == POST_INC
5358 || GET_CODE (rld[r].in_reg) == POST_DEC)
5359 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5361 regno = REGNO (XEXP (rld[r].in_reg, 0));
5362 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5363 rld[r].out = rld[r].in;
5367 /* This won't work, since REGNO can be a pseudo reg number.
5368 Also, it takes much more hair to keep track of all the things
5369 that can invalidate an inherited reload of part of a pseudoreg. */
5370 else if (GET_CODE (rld[r].in) == SUBREG
5371 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5372 regno = subreg_regno (rld[r].in);
5375 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5377 enum reg_class class = rld[r].class, last_class;
5378 rtx last_reg = reg_last_reload_reg[regno];
5379 enum machine_mode need_mode;
5381 i = REGNO (last_reg);
5382 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5383 last_class = REGNO_REG_CLASS (i);
5389 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5390 GET_MODE_CLASS (mode));
5393 #ifdef CANNOT_CHANGE_MODE_CLASS
5394 (!REG_CANNOT_CHANGE_MODE_P (i, GET_MODE (last_reg),
5398 (GET_MODE_SIZE (GET_MODE (last_reg))
5399 >= GET_MODE_SIZE (need_mode))
5400 #ifdef CANNOT_CHANGE_MODE_CLASS
5403 && reg_reloaded_contents[i] == regno
5404 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5405 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5406 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5407 /* Even if we can't use this register as a reload
5408 register, we might use it for reload_override_in,
5409 if copying it to the desired class is cheap
5411 || ((REGISTER_MOVE_COST (mode, last_class, class)
5412 < MEMORY_MOVE_COST (mode, class, 1))
5413 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5414 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5418 #ifdef SECONDARY_MEMORY_NEEDED
5419 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5424 && (rld[r].nregs == max_group_size
5425 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5427 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5428 rld[r].when_needed, rld[r].in,
5431 /* If a group is needed, verify that all the subsequent
5432 registers still have their values intact. */
5433 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5436 for (k = 1; k < nr; k++)
5437 if (reg_reloaded_contents[i + k] != regno
5438 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5446 last_reg = (GET_MODE (last_reg) == mode
5447 ? last_reg : gen_rtx_REG (mode, i));
5450 for (k = 0; k < nr; k++)
5451 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5454 /* We found a register that contains the
5455 value we need. If this register is the
5456 same as an `earlyclobber' operand of the
5457 current insn, just mark it as a place to
5458 reload from since we can't use it as the
5459 reload register itself. */
5461 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5462 if (reg_overlap_mentioned_for_reload_p
5463 (reg_last_reload_reg[regno],
5464 reload_earlyclobbers[i1]))
5467 if (i1 != n_earlyclobbers
5468 || ! (free_for_value_p (i, rld[r].mode,
5470 rld[r].when_needed, rld[r].in,
5472 /* Don't use it if we'd clobber a pseudo reg. */
5473 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5475 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5476 /* Don't clobber the frame pointer. */
5477 || (i == HARD_FRAME_POINTER_REGNUM
5478 && frame_pointer_needed
5480 /* Don't really use the inherited spill reg
5481 if we need it wider than we've got it. */
5482 || (GET_MODE_SIZE (rld[r].mode)
5483 > GET_MODE_SIZE (mode))
5486 /* If find_reloads chose reload_out as reload
5487 register, stay with it - that leaves the
5488 inherited register for subsequent reloads. */
5489 || (rld[r].out && rld[r].reg_rtx
5490 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5492 if (! rld[r].optional)
5494 reload_override_in[r] = last_reg;
5495 reload_inheritance_insn[r]
5496 = reg_reloaded_insn[i];
5502 /* We can use this as a reload reg. */
5503 /* Mark the register as in use for this part of
5505 mark_reload_reg_in_use (i,
5509 rld[r].reg_rtx = last_reg;
5510 reload_inherited[r] = 1;
5511 reload_inheritance_insn[r]
5512 = reg_reloaded_insn[i];
5513 reload_spill_index[r] = i;
5514 for (k = 0; k < nr; k++)
5515 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5523 /* Here's another way to see if the value is already lying around. */
5526 && ! reload_inherited[r]
5528 && (CONSTANT_P (rld[r].in)
5529 || GET_CODE (rld[r].in) == PLUS
5530 || GET_CODE (rld[r].in) == REG
5531 || GET_CODE (rld[r].in) == MEM)
5532 && (rld[r].nregs == max_group_size
5533 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5534 search_equiv = rld[r].in;
5535 /* If this is an output reload from a simple move insn, look
5536 if an equivalence for the input is available. */
5537 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5539 rtx set = single_set (insn);
5542 && rtx_equal_p (rld[r].out, SET_DEST (set))
5543 && CONSTANT_P (SET_SRC (set)))
5544 search_equiv = SET_SRC (set);
5550 = find_equiv_reg (search_equiv, insn, rld[r].class,
5551 -1, NULL, 0, rld[r].mode);
5556 if (GET_CODE (equiv) == REG)
5557 regno = REGNO (equiv);
5558 else if (GET_CODE (equiv) == SUBREG)
5560 /* This must be a SUBREG of a hard register.
5561 Make a new REG since this might be used in an
5562 address and not all machines support SUBREGs
5564 regno = subreg_regno (equiv);
5565 equiv = gen_rtx_REG (rld[r].mode, regno);
5571 /* If we found a spill reg, reject it unless it is free
5572 and of the desired class. */
5576 int bad_for_class = 0;
5577 int max_regno = regno + rld[r].nregs;
5579 for (i = regno; i < max_regno; i++)
5581 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5583 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5588 && ! free_for_value_p (regno, rld[r].mode,
5589 rld[r].opnum, rld[r].when_needed,
5590 rld[r].in, rld[r].out, r, 1))
5595 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5598 /* We found a register that contains the value we need.
5599 If this register is the same as an `earlyclobber' operand
5600 of the current insn, just mark it as a place to reload from
5601 since we can't use it as the reload register itself. */
5604 for (i = 0; i < n_earlyclobbers; i++)
5605 if (reg_overlap_mentioned_for_reload_p (equiv,
5606 reload_earlyclobbers[i]))
5608 if (! rld[r].optional)
5609 reload_override_in[r] = equiv;
5614 /* If the equiv register we have found is explicitly clobbered
5615 in the current insn, it depends on the reload type if we
5616 can use it, use it for reload_override_in, or not at all.
5617 In particular, we then can't use EQUIV for a
5618 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5622 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5623 switch (rld[r].when_needed)
5625 case RELOAD_FOR_OTHER_ADDRESS:
5626 case RELOAD_FOR_INPADDR_ADDRESS:
5627 case RELOAD_FOR_INPUT_ADDRESS:
5628 case RELOAD_FOR_OPADDR_ADDR:
5631 case RELOAD_FOR_INPUT:
5632 case RELOAD_FOR_OPERAND_ADDRESS:
5633 if (! rld[r].optional)
5634 reload_override_in[r] = equiv;
5640 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5641 switch (rld[r].when_needed)
5643 case RELOAD_FOR_OTHER_ADDRESS:
5644 case RELOAD_FOR_INPADDR_ADDRESS:
5645 case RELOAD_FOR_INPUT_ADDRESS:
5646 case RELOAD_FOR_OPADDR_ADDR:
5647 case RELOAD_FOR_OPERAND_ADDRESS:
5648 case RELOAD_FOR_INPUT:
5651 if (! rld[r].optional)
5652 reload_override_in[r] = equiv;
5660 /* If we found an equivalent reg, say no code need be generated
5661 to load it, and use it as our reload reg. */
5663 && (regno != HARD_FRAME_POINTER_REGNUM
5664 || !frame_pointer_needed))
5666 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5668 rld[r].reg_rtx = equiv;
5669 reload_inherited[r] = 1;
5671 /* If reg_reloaded_valid is not set for this register,
5672 there might be a stale spill_reg_store lying around.
5673 We must clear it, since otherwise emit_reload_insns
5674 might delete the store. */
5675 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5676 spill_reg_store[regno] = NULL_RTX;
5677 /* If any of the hard registers in EQUIV are spill
5678 registers, mark them as in use for this insn. */
5679 for (k = 0; k < nr; k++)
5681 i = spill_reg_order[regno + k];
5684 mark_reload_reg_in_use (regno, rld[r].opnum,
5687 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5694 /* If we found a register to use already, or if this is an optional
5695 reload, we are done. */
5696 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5700 /* No longer needed for correct operation. Might or might
5701 not give better code on the average. Want to experiment? */
5703 /* See if there is a later reload that has a class different from our
5704 class that intersects our class or that requires less register
5705 than our reload. If so, we must allocate a register to this
5706 reload now, since that reload might inherit a previous reload
5707 and take the only available register in our class. Don't do this
5708 for optional reloads since they will force all previous reloads
5709 to be allocated. Also don't do this for reloads that have been
5712 for (i = j + 1; i < n_reloads; i++)
5714 int s = reload_order[i];
5716 if ((rld[s].in == 0 && rld[s].out == 0
5717 && ! rld[s].secondary_p)
5721 if ((rld[s].class != rld[r].class
5722 && reg_classes_intersect_p (rld[r].class,
5724 || rld[s].nregs < rld[r].nregs)
5731 allocate_reload_reg (chain, r, j == n_reloads - 1);
5735 /* Now allocate reload registers for anything non-optional that
5736 didn't get one yet. */
5737 for (j = 0; j < n_reloads; j++)
5739 int r = reload_order[j];
5741 /* Ignore reloads that got marked inoperative. */
5742 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5745 /* Skip reloads that already have a register allocated or are
5747 if (rld[r].reg_rtx != 0 || rld[r].optional)
5750 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5754 /* If that loop got all the way, we have won. */
5761 /* Loop around and try without any inheritance. */
5766 /* First undo everything done by the failed attempt
5767 to allocate with inheritance. */
5768 choose_reload_regs_init (chain, save_reload_reg_rtx);
5770 /* Some sanity tests to verify that the reloads found in the first
5771 pass are identical to the ones we have now. */
5772 if (chain->n_reloads != n_reloads)
5775 for (i = 0; i < n_reloads; i++)
5777 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5779 if (chain->rld[i].when_needed != rld[i].when_needed)
5781 for (j = 0; j < n_spills; j++)
5782 if (spill_regs[j] == chain->rld[i].regno)
5783 if (! set_reload_reg (j, i))
5784 failed_reload (chain->insn, i);
5788 /* If we thought we could inherit a reload, because it seemed that
5789 nothing else wanted the same reload register earlier in the insn,
5790 verify that assumption, now that all reloads have been assigned.
5791 Likewise for reloads where reload_override_in has been set. */
5793 /* If doing expensive optimizations, do one preliminary pass that doesn't
5794 cancel any inheritance, but removes reloads that have been needed only
5795 for reloads that we know can be inherited. */
5796 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5798 for (j = 0; j < n_reloads; j++)
5800 int r = reload_order[j];
5802 if (reload_inherited[r] && rld[r].reg_rtx)
5803 check_reg = rld[r].reg_rtx;
5804 else if (reload_override_in[r]
5805 && (GET_CODE (reload_override_in[r]) == REG
5806 || GET_CODE (reload_override_in[r]) == SUBREG))
5807 check_reg = reload_override_in[r];
5810 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5811 rld[r].opnum, rld[r].when_needed, rld[r].in,
5812 (reload_inherited[r]
5813 ? rld[r].out : const0_rtx),
5818 reload_inherited[r] = 0;
5819 reload_override_in[r] = 0;
5821 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5822 reload_override_in, then we do not need its related
5823 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5824 likewise for other reload types.
5825 We handle this by removing a reload when its only replacement
5826 is mentioned in reload_in of the reload we are going to inherit.
5827 A special case are auto_inc expressions; even if the input is
5828 inherited, we still need the address for the output. We can
5829 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5830 If we succeeded removing some reload and we are doing a preliminary
5831 pass just to remove such reloads, make another pass, since the
5832 removal of one reload might allow us to inherit another one. */
5834 && rld[r].out != rld[r].in
5835 && remove_address_replacements (rld[r].in) && pass)
5840 /* Now that reload_override_in is known valid,
5841 actually override reload_in. */
5842 for (j = 0; j < n_reloads; j++)
5843 if (reload_override_in[j])
5844 rld[j].in = reload_override_in[j];
5846 /* If this reload won't be done because it has been canceled or is
5847 optional and not inherited, clear reload_reg_rtx so other
5848 routines (such as subst_reloads) don't get confused. */
5849 for (j = 0; j < n_reloads; j++)
5850 if (rld[j].reg_rtx != 0
5851 && ((rld[j].optional && ! reload_inherited[j])
5852 || (rld[j].in == 0 && rld[j].out == 0
5853 && ! rld[j].secondary_p)))
5855 int regno = true_regnum (rld[j].reg_rtx);
5857 if (spill_reg_order[regno] >= 0)
5858 clear_reload_reg_in_use (regno, rld[j].opnum,
5859 rld[j].when_needed, rld[j].mode);
5861 reload_spill_index[j] = -1;
5864 /* Record which pseudos and which spill regs have output reloads. */
5865 for (j = 0; j < n_reloads; j++)
5867 int r = reload_order[j];
5869 i = reload_spill_index[r];
5871 /* I is nonneg if this reload uses a register.
5872 If rld[r].reg_rtx is 0, this is an optional reload
5873 that we opted to ignore. */
5874 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5875 && rld[r].reg_rtx != 0)
5877 int nregno = REGNO (rld[r].out_reg);
5880 if (nregno < FIRST_PSEUDO_REGISTER)
5881 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5884 reg_has_output_reload[nregno + nr] = 1;
5888 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5890 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5893 if (rld[r].when_needed != RELOAD_OTHER
5894 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5895 && rld[r].when_needed != RELOAD_FOR_INSN)
5901 /* Deallocate the reload register for reload R. This is called from
5902 remove_address_replacements. */
5905 deallocate_reload_reg (int r)
5909 if (! rld[r].reg_rtx)
5911 regno = true_regnum (rld[r].reg_rtx);
5913 if (spill_reg_order[regno] >= 0)
5914 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5916 reload_spill_index[r] = -1;
5919 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
5920 reloads of the same item for fear that we might not have enough reload
5921 registers. However, normally they will get the same reload register
5922 and hence actually need not be loaded twice.
5924 Here we check for the most common case of this phenomenon: when we have
5925 a number of reloads for the same object, each of which were allocated
5926 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5927 reload, and is not modified in the insn itself. If we find such,
5928 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5929 This will not increase the number of spill registers needed and will
5930 prevent redundant code. */
5933 merge_assigned_reloads (rtx insn)
5937 /* Scan all the reloads looking for ones that only load values and
5938 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5939 assigned and not modified by INSN. */
5941 for (i = 0; i < n_reloads; i++)
5943 int conflicting_input = 0;
5944 int max_input_address_opnum = -1;
5945 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5947 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5948 || rld[i].out != 0 || rld[i].reg_rtx == 0
5949 || reg_set_p (rld[i].reg_rtx, insn))
5952 /* Look at all other reloads. Ensure that the only use of this
5953 reload_reg_rtx is in a reload that just loads the same value
5954 as we do. Note that any secondary reloads must be of the identical
5955 class since the values, modes, and result registers are the
5956 same, so we need not do anything with any secondary reloads. */
5958 for (j = 0; j < n_reloads; j++)
5960 if (i == j || rld[j].reg_rtx == 0
5961 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
5965 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5966 && rld[j].opnum > max_input_address_opnum)
5967 max_input_address_opnum = rld[j].opnum;
5969 /* If the reload regs aren't exactly the same (e.g, different modes)
5970 or if the values are different, we can't merge this reload.
5971 But if it is an input reload, we might still merge
5972 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
5974 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5975 || rld[j].out != 0 || rld[j].in == 0
5976 || ! rtx_equal_p (rld[i].in, rld[j].in))
5978 if (rld[j].when_needed != RELOAD_FOR_INPUT
5979 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
5980 || rld[i].opnum > rld[j].opnum)
5981 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
5983 conflicting_input = 1;
5984 if (min_conflicting_input_opnum > rld[j].opnum)
5985 min_conflicting_input_opnum = rld[j].opnum;
5989 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5990 we, in fact, found any matching reloads. */
5993 && max_input_address_opnum <= min_conflicting_input_opnum)
5995 for (j = 0; j < n_reloads; j++)
5996 if (i != j && rld[j].reg_rtx != 0
5997 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5998 && (! conflicting_input
5999 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6000 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6002 rld[i].when_needed = RELOAD_OTHER;
6004 reload_spill_index[j] = -1;
6005 transfer_replacements (i, j);
6008 /* If this is now RELOAD_OTHER, look for any reloads that load
6009 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6010 if they were for inputs, RELOAD_OTHER for outputs. Note that
6011 this test is equivalent to looking for reloads for this operand
6013 /* We must take special care when there are two or more reloads to
6014 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6015 same value or a part of it; we must not change its type if there
6016 is a conflicting input. */
6018 if (rld[i].when_needed == RELOAD_OTHER)
6019 for (j = 0; j < n_reloads; j++)
6021 && rld[j].when_needed != RELOAD_OTHER
6022 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6023 && (! conflicting_input
6024 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6025 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6026 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6032 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6033 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6034 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6036 /* Check to see if we accidentally converted two reloads
6037 that use the same reload register with different inputs
6038 to the same type. If so, the resulting code won't work,
6041 for (k = 0; k < j; k++)
6042 if (rld[k].in != 0 && rld[k].reg_rtx != 0
6043 && rld[k].when_needed == rld[j].when_needed
6044 && rtx_equal_p (rld[k].reg_rtx, rld[j].reg_rtx)
6045 && ! rtx_equal_p (rld[k].in, rld[j].in))
6052 /* These arrays are filled by emit_reload_insns and its subroutines. */
6053 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6054 static rtx other_input_address_reload_insns = 0;
6055 static rtx other_input_reload_insns = 0;
6056 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6057 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6058 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6059 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6060 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6061 static rtx operand_reload_insns = 0;
6062 static rtx other_operand_reload_insns = 0;
6063 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6065 /* Values to be put in spill_reg_store are put here first. */
6066 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6067 static HARD_REG_SET reg_reloaded_died;
6069 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6070 has the number J. OLD contains the value to be used as input. */
6073 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6076 rtx insn = chain->insn;
6077 rtx reloadreg = rl->reg_rtx;
6078 rtx oldequiv_reg = 0;
6081 enum machine_mode mode;
6084 /* Determine the mode to reload in.
6085 This is very tricky because we have three to choose from.
6086 There is the mode the insn operand wants (rl->inmode).
6087 There is the mode of the reload register RELOADREG.
6088 There is the intrinsic mode of the operand, which we could find
6089 by stripping some SUBREGs.
6090 It turns out that RELOADREG's mode is irrelevant:
6091 we can change that arbitrarily.
6093 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6094 then the reload reg may not support QImode moves, so use SImode.
6095 If foo is in memory due to spilling a pseudo reg, this is safe,
6096 because the QImode value is in the least significant part of a
6097 slot big enough for a SImode. If foo is some other sort of
6098 memory reference, then it is impossible to reload this case,
6099 so previous passes had better make sure this never happens.
6101 Then consider a one-word union which has SImode and one of its
6102 members is a float, being fetched as (SUBREG:SF union:SI).
6103 We must fetch that as SFmode because we could be loading into
6104 a float-only register. In this case OLD's mode is correct.
6106 Consider an immediate integer: it has VOIDmode. Here we need
6107 to get a mode from something else.
6109 In some cases, there is a fourth mode, the operand's
6110 containing mode. If the insn specifies a containing mode for
6111 this operand, it overrides all others.
6113 I am not sure whether the algorithm here is always right,
6114 but it does the right things in those cases. */
6116 mode = GET_MODE (old);
6117 if (mode == VOIDmode)
6120 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6121 /* If we need a secondary register for this operation, see if
6122 the value is already in a register in that class. Don't
6123 do this if the secondary register will be used as a scratch
6126 if (rl->secondary_in_reload >= 0
6127 && rl->secondary_in_icode == CODE_FOR_nothing
6130 = find_equiv_reg (old, insn,
6131 rld[rl->secondary_in_reload].class,
6135 /* If reloading from memory, see if there is a register
6136 that already holds the same value. If so, reload from there.
6137 We can pass 0 as the reload_reg_p argument because
6138 any other reload has either already been emitted,
6139 in which case find_equiv_reg will see the reload-insn,
6140 or has yet to be emitted, in which case it doesn't matter
6141 because we will use this equiv reg right away. */
6143 if (oldequiv == 0 && optimize
6144 && (GET_CODE (old) == MEM
6145 || (GET_CODE (old) == REG
6146 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6147 && reg_renumber[REGNO (old)] < 0)))
6148 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6152 unsigned int regno = true_regnum (oldequiv);
6154 /* Don't use OLDEQUIV if any other reload changes it at an
6155 earlier stage of this insn or at this stage. */
6156 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6157 rl->in, const0_rtx, j, 0))
6160 /* If it is no cheaper to copy from OLDEQUIV into the
6161 reload register than it would be to move from memory,
6162 don't use it. Likewise, if we need a secondary register
6166 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6167 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6169 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6170 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6171 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6175 #ifdef SECONDARY_MEMORY_NEEDED
6176 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6184 /* delete_output_reload is only invoked properly if old contains
6185 the original pseudo register. Since this is replaced with a
6186 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6187 find the pseudo in RELOAD_IN_REG. */
6189 && reload_override_in[j]
6190 && GET_CODE (rl->in_reg) == REG)
6197 else if (GET_CODE (oldequiv) == REG)
6198 oldequiv_reg = oldequiv;
6199 else if (GET_CODE (oldequiv) == SUBREG)
6200 oldequiv_reg = SUBREG_REG (oldequiv);
6202 /* If we are reloading from a register that was recently stored in
6203 with an output-reload, see if we can prove there was
6204 actually no need to store the old value in it. */
6206 if (optimize && GET_CODE (oldequiv) == REG
6207 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6208 && spill_reg_store[REGNO (oldequiv)]
6209 && GET_CODE (old) == REG
6210 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6211 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6213 delete_output_reload (insn, j, REGNO (oldequiv));
6215 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6216 then load RELOADREG from OLDEQUIV. Note that we cannot use
6217 gen_lowpart_common since it can do the wrong thing when
6218 RELOADREG has a multi-word mode. Note that RELOADREG
6219 must always be a REG here. */
6221 if (GET_MODE (reloadreg) != mode)
6222 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6223 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6224 oldequiv = SUBREG_REG (oldequiv);
6225 if (GET_MODE (oldequiv) != VOIDmode
6226 && mode != GET_MODE (oldequiv))
6227 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6229 /* Switch to the right place to emit the reload insns. */
6230 switch (rl->when_needed)
6233 where = &other_input_reload_insns;
6235 case RELOAD_FOR_INPUT:
6236 where = &input_reload_insns[rl->opnum];
6238 case RELOAD_FOR_INPUT_ADDRESS:
6239 where = &input_address_reload_insns[rl->opnum];
6241 case RELOAD_FOR_INPADDR_ADDRESS:
6242 where = &inpaddr_address_reload_insns[rl->opnum];
6244 case RELOAD_FOR_OUTPUT_ADDRESS:
6245 where = &output_address_reload_insns[rl->opnum];
6247 case RELOAD_FOR_OUTADDR_ADDRESS:
6248 where = &outaddr_address_reload_insns[rl->opnum];
6250 case RELOAD_FOR_OPERAND_ADDRESS:
6251 where = &operand_reload_insns;
6253 case RELOAD_FOR_OPADDR_ADDR:
6254 where = &other_operand_reload_insns;
6256 case RELOAD_FOR_OTHER_ADDRESS:
6257 where = &other_input_address_reload_insns;
6263 push_to_sequence (*where);
6265 /* Auto-increment addresses must be reloaded in a special way. */
6266 if (rl->out && ! rl->out_reg)
6268 /* We are not going to bother supporting the case where a
6269 incremented register can't be copied directly from
6270 OLDEQUIV since this seems highly unlikely. */
6271 if (rl->secondary_in_reload >= 0)
6274 if (reload_inherited[j])
6275 oldequiv = reloadreg;
6277 old = XEXP (rl->in_reg, 0);
6279 if (optimize && GET_CODE (oldequiv) == REG
6280 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6281 && spill_reg_store[REGNO (oldequiv)]
6282 && GET_CODE (old) == REG
6283 && (dead_or_set_p (insn,
6284 spill_reg_stored_to[REGNO (oldequiv)])
6285 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6287 delete_output_reload (insn, j, REGNO (oldequiv));
6289 /* Prevent normal processing of this reload. */
6291 /* Output a special code sequence for this case. */
6292 new_spill_reg_store[REGNO (reloadreg)]
6293 = inc_for_reload (reloadreg, oldequiv, rl->out,
6297 /* If we are reloading a pseudo-register that was set by the previous
6298 insn, see if we can get rid of that pseudo-register entirely
6299 by redirecting the previous insn into our reload register. */
6301 else if (optimize && GET_CODE (old) == REG
6302 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6303 && dead_or_set_p (insn, old)
6304 /* This is unsafe if some other reload
6305 uses the same reg first. */
6306 && ! conflicts_with_override (reloadreg)
6307 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6308 rl->when_needed, old, rl->out, j, 0))
6310 rtx temp = PREV_INSN (insn);
6311 while (temp && GET_CODE (temp) == NOTE)
6312 temp = PREV_INSN (temp);
6314 && GET_CODE (temp) == INSN
6315 && GET_CODE (PATTERN (temp)) == SET
6316 && SET_DEST (PATTERN (temp)) == old
6317 /* Make sure we can access insn_operand_constraint. */
6318 && asm_noperands (PATTERN (temp)) < 0
6319 /* This is unsafe if operand occurs more than once in current
6320 insn. Perhaps some occurrences aren't reloaded. */
6321 && count_occurrences (PATTERN (insn), old, 0) == 1)
6323 rtx old = SET_DEST (PATTERN (temp));
6324 /* Store into the reload register instead of the pseudo. */
6325 SET_DEST (PATTERN (temp)) = reloadreg;
6327 /* Verify that resulting insn is valid. */
6328 extract_insn (temp);
6329 if (constrain_operands (1))
6331 /* If the previous insn is an output reload, the source is
6332 a reload register, and its spill_reg_store entry will
6333 contain the previous destination. This is now
6335 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6336 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6338 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6339 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6342 /* If these are the only uses of the pseudo reg,
6343 pretend for GDB it lives in the reload reg we used. */
6344 if (REG_N_DEATHS (REGNO (old)) == 1
6345 && REG_N_SETS (REGNO (old)) == 1)
6347 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6348 alter_reg (REGNO (old), -1);
6354 SET_DEST (PATTERN (temp)) = old;
6359 /* We can't do that, so output an insn to load RELOADREG. */
6361 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6362 /* If we have a secondary reload, pick up the secondary register
6363 and icode, if any. If OLDEQUIV and OLD are different or
6364 if this is an in-out reload, recompute whether or not we
6365 still need a secondary register and what the icode should
6366 be. If we still need a secondary register and the class or
6367 icode is different, go back to reloading from OLD if using
6368 OLDEQUIV means that we got the wrong type of register. We
6369 cannot have different class or icode due to an in-out reload
6370 because we don't make such reloads when both the input and
6371 output need secondary reload registers. */
6373 if (! special && rl->secondary_in_reload >= 0)
6375 rtx second_reload_reg = 0;
6376 int secondary_reload = rl->secondary_in_reload;
6377 rtx real_oldequiv = oldequiv;
6380 enum insn_code icode;
6382 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6383 and similarly for OLD.
6384 See comments in get_secondary_reload in reload.c. */
6385 /* If it is a pseudo that cannot be replaced with its
6386 equivalent MEM, we must fall back to reload_in, which
6387 will have all the necessary substitutions registered.
6388 Likewise for a pseudo that can't be replaced with its
6389 equivalent constant.
6391 Take extra care for subregs of such pseudos. Note that
6392 we cannot use reg_equiv_mem in this case because it is
6393 not in the right mode. */
6396 if (GET_CODE (tmp) == SUBREG)
6397 tmp = SUBREG_REG (tmp);
6398 if (GET_CODE (tmp) == REG
6399 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6400 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6401 || reg_equiv_constant[REGNO (tmp)] != 0))
6403 if (! reg_equiv_mem[REGNO (tmp)]
6404 || num_not_at_initial_offset
6405 || GET_CODE (oldequiv) == SUBREG)
6406 real_oldequiv = rl->in;
6408 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6412 if (GET_CODE (tmp) == SUBREG)
6413 tmp = SUBREG_REG (tmp);
6414 if (GET_CODE (tmp) == REG
6415 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6416 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6417 || reg_equiv_constant[REGNO (tmp)] != 0))
6419 if (! reg_equiv_mem[REGNO (tmp)]
6420 || num_not_at_initial_offset
6421 || GET_CODE (old) == SUBREG)
6424 real_old = reg_equiv_mem[REGNO (tmp)];
6427 second_reload_reg = rld[secondary_reload].reg_rtx;
6428 icode = rl->secondary_in_icode;
6430 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6431 || (rl->in != 0 && rl->out != 0))
6433 enum reg_class new_class
6434 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6435 mode, real_oldequiv);
6437 if (new_class == NO_REGS)
6438 second_reload_reg = 0;
6441 enum insn_code new_icode;
6442 enum machine_mode new_mode;
6444 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6445 REGNO (second_reload_reg)))
6446 oldequiv = old, real_oldequiv = real_old;
6449 new_icode = reload_in_optab[(int) mode];
6450 if (new_icode != CODE_FOR_nothing
6451 && ((insn_data[(int) new_icode].operand[0].predicate
6452 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6454 || (insn_data[(int) new_icode].operand[1].predicate
6455 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6456 (real_oldequiv, mode)))))
6457 new_icode = CODE_FOR_nothing;
6459 if (new_icode == CODE_FOR_nothing)
6462 new_mode = insn_data[(int) new_icode].operand[2].mode;
6464 if (GET_MODE (second_reload_reg) != new_mode)
6466 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6468 oldequiv = old, real_oldequiv = real_old;
6471 = reload_adjust_reg_for_mode (second_reload_reg,
6478 /* If we still need a secondary reload register, check
6479 to see if it is being used as a scratch or intermediate
6480 register and generate code appropriately. If we need
6481 a scratch register, use REAL_OLDEQUIV since the form of
6482 the insn may depend on the actual address if it is
6485 if (second_reload_reg)
6487 if (icode != CODE_FOR_nothing)
6489 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6490 second_reload_reg));
6495 /* See if we need a scratch register to load the
6496 intermediate register (a tertiary reload). */
6497 enum insn_code tertiary_icode
6498 = rld[secondary_reload].secondary_in_icode;
6500 if (tertiary_icode != CODE_FOR_nothing)
6502 rtx third_reload_reg
6503 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6505 emit_insn ((GEN_FCN (tertiary_icode)
6506 (second_reload_reg, real_oldequiv,
6507 third_reload_reg)));
6510 gen_reload (second_reload_reg, real_oldequiv,
6514 oldequiv = second_reload_reg;
6520 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6522 rtx real_oldequiv = oldequiv;
6524 if ((GET_CODE (oldequiv) == REG
6525 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6526 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6527 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6528 || (GET_CODE (oldequiv) == SUBREG
6529 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6530 && (REGNO (SUBREG_REG (oldequiv))
6531 >= FIRST_PSEUDO_REGISTER)
6532 && ((reg_equiv_memory_loc
6533 [REGNO (SUBREG_REG (oldequiv))] != 0)
6534 || (reg_equiv_constant
6535 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6536 || (CONSTANT_P (oldequiv)
6537 && (PREFERRED_RELOAD_CLASS (oldequiv,
6538 REGNO_REG_CLASS (REGNO (reloadreg)))
6540 real_oldequiv = rl->in;
6541 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6545 if (flag_non_call_exceptions)
6546 copy_eh_notes (insn, get_insns ());
6548 /* End this sequence. */
6549 *where = get_insns ();
6552 /* Update reload_override_in so that delete_address_reloads_1
6553 can see the actual register usage. */
6555 reload_override_in[j] = oldequiv;
6558 /* Generate insns to for the output reload RL, which is for the insn described
6559 by CHAIN and has the number J. */
6561 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6564 rtx reloadreg = rl->reg_rtx;
6565 rtx insn = chain->insn;
6568 enum machine_mode mode = GET_MODE (old);
6571 if (rl->when_needed == RELOAD_OTHER)
6574 push_to_sequence (output_reload_insns[rl->opnum]);
6576 /* Determine the mode to reload in.
6577 See comments above (for input reloading). */
6579 if (mode == VOIDmode)
6581 /* VOIDmode should never happen for an output. */
6582 if (asm_noperands (PATTERN (insn)) < 0)
6583 /* It's the compiler's fault. */
6584 fatal_insn ("VOIDmode on an output", insn);
6585 error_for_asm (insn, "output operand is constant in `asm'");
6586 /* Prevent crash--use something we know is valid. */
6588 old = gen_rtx_REG (mode, REGNO (reloadreg));
6591 if (GET_MODE (reloadreg) != mode)
6592 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6594 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6596 /* If we need two reload regs, set RELOADREG to the intermediate
6597 one, since it will be stored into OLD. We might need a secondary
6598 register only for an input reload, so check again here. */
6600 if (rl->secondary_out_reload >= 0)
6604 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6605 && reg_equiv_mem[REGNO (old)] != 0)
6606 real_old = reg_equiv_mem[REGNO (old)];
6608 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6612 rtx second_reloadreg = reloadreg;
6613 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6615 /* See if RELOADREG is to be used as a scratch register
6616 or as an intermediate register. */
6617 if (rl->secondary_out_icode != CODE_FOR_nothing)
6619 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6620 (real_old, second_reloadreg, reloadreg)));
6625 /* See if we need both a scratch and intermediate reload
6628 int secondary_reload = rl->secondary_out_reload;
6629 enum insn_code tertiary_icode
6630 = rld[secondary_reload].secondary_out_icode;
6632 if (GET_MODE (reloadreg) != mode)
6633 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6635 if (tertiary_icode != CODE_FOR_nothing)
6638 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6641 /* Copy primary reload reg to secondary reload reg.
6642 (Note that these have been swapped above, then
6643 secondary reload reg to OLD using our insn.) */
6645 /* If REAL_OLD is a paradoxical SUBREG, remove it
6646 and try to put the opposite SUBREG on
6648 if (GET_CODE (real_old) == SUBREG
6649 && (GET_MODE_SIZE (GET_MODE (real_old))
6650 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6651 && 0 != (tem = gen_lowpart_common
6652 (GET_MODE (SUBREG_REG (real_old)),
6654 real_old = SUBREG_REG (real_old), reloadreg = tem;
6656 gen_reload (reloadreg, second_reloadreg,
6657 rl->opnum, rl->when_needed);
6658 emit_insn ((GEN_FCN (tertiary_icode)
6659 (real_old, reloadreg, third_reloadreg)));
6664 /* Copy between the reload regs here and then to
6667 gen_reload (reloadreg, second_reloadreg,
6668 rl->opnum, rl->when_needed);
6674 /* Output the last reload insn. */
6679 /* Don't output the last reload if OLD is not the dest of
6680 INSN and is in the src and is clobbered by INSN. */
6681 if (! flag_expensive_optimizations
6682 || GET_CODE (old) != REG
6683 || !(set = single_set (insn))
6684 || rtx_equal_p (old, SET_DEST (set))
6685 || !reg_mentioned_p (old, SET_SRC (set))
6686 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6687 gen_reload (old, reloadreg, rl->opnum,
6691 /* Look at all insns we emitted, just to be safe. */
6692 for (p = get_insns (); p; p = NEXT_INSN (p))
6695 rtx pat = PATTERN (p);
6697 /* If this output reload doesn't come from a spill reg,
6698 clear any memory of reloaded copies of the pseudo reg.
6699 If this output reload comes from a spill reg,
6700 reg_has_output_reload will make this do nothing. */
6701 note_stores (pat, forget_old_reloads_1, NULL);
6703 if (reg_mentioned_p (rl->reg_rtx, pat))
6705 rtx set = single_set (insn);
6706 if (reload_spill_index[j] < 0
6708 && SET_SRC (set) == rl->reg_rtx)
6710 int src = REGNO (SET_SRC (set));
6712 reload_spill_index[j] = src;
6713 SET_HARD_REG_BIT (reg_is_output_reload, src);
6714 if (find_regno_note (insn, REG_DEAD, src))
6715 SET_HARD_REG_BIT (reg_reloaded_died, src);
6717 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6719 int s = rl->secondary_out_reload;
6720 set = single_set (p);
6721 /* If this reload copies only to the secondary reload
6722 register, the secondary reload does the actual
6724 if (s >= 0 && set == NULL_RTX)
6725 /* We can't tell what function the secondary reload
6726 has and where the actual store to the pseudo is
6727 made; leave new_spill_reg_store alone. */
6730 && SET_SRC (set) == rl->reg_rtx
6731 && SET_DEST (set) == rld[s].reg_rtx)
6733 /* Usually the next instruction will be the
6734 secondary reload insn; if we can confirm
6735 that it is, setting new_spill_reg_store to
6736 that insn will allow an extra optimization. */
6737 rtx s_reg = rld[s].reg_rtx;
6738 rtx next = NEXT_INSN (p);
6739 rld[s].out = rl->out;
6740 rld[s].out_reg = rl->out_reg;
6741 set = single_set (next);
6742 if (set && SET_SRC (set) == s_reg
6743 && ! new_spill_reg_store[REGNO (s_reg)])
6745 SET_HARD_REG_BIT (reg_is_output_reload,
6747 new_spill_reg_store[REGNO (s_reg)] = next;
6751 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6756 if (rl->when_needed == RELOAD_OTHER)
6758 emit_insn (other_output_reload_insns[rl->opnum]);
6759 other_output_reload_insns[rl->opnum] = get_insns ();
6762 output_reload_insns[rl->opnum] = get_insns ();
6764 if (flag_non_call_exceptions)
6765 copy_eh_notes (insn, get_insns ());
6770 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6771 and has the number J. */
6773 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
6775 rtx insn = chain->insn;
6776 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6777 ? rl->in_reg : rl->in);
6780 /* AUTO_INC reloads need to be handled even if inherited. We got an
6781 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6782 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6783 && ! rtx_equal_p (rl->reg_rtx, old)
6784 && rl->reg_rtx != 0)
6785 emit_input_reload_insns (chain, rld + j, old, j);
6787 /* When inheriting a wider reload, we have a MEM in rl->in,
6788 e.g. inheriting a SImode output reload for
6789 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6790 if (optimize && reload_inherited[j] && rl->in
6791 && GET_CODE (rl->in) == MEM
6792 && GET_CODE (rl->in_reg) == MEM
6793 && reload_spill_index[j] >= 0
6794 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6795 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6797 /* If we are reloading a register that was recently stored in with an
6798 output-reload, see if we can prove there was
6799 actually no need to store the old value in it. */
6802 && (reload_inherited[j] || reload_override_in[j])
6804 && GET_CODE (rl->reg_rtx) == REG
6805 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6807 /* There doesn't seem to be any reason to restrict this to pseudos
6808 and doing so loses in the case where we are copying from a
6809 register of the wrong class. */
6810 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6811 >= FIRST_PSEUDO_REGISTER)
6813 /* The insn might have already some references to stackslots
6814 replaced by MEMs, while reload_out_reg still names the
6816 && (dead_or_set_p (insn,
6817 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6818 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6820 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6823 /* Do output reloading for reload RL, which is for the insn described by
6824 CHAIN and has the number J.
6825 ??? At some point we need to support handling output reloads of
6826 JUMP_INSNs or insns that set cc0. */
6828 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
6831 rtx insn = chain->insn;
6832 /* If this is an output reload that stores something that is
6833 not loaded in this same reload, see if we can eliminate a previous
6835 rtx pseudo = rl->out_reg;
6839 && GET_CODE (pseudo) == REG
6840 && ! rtx_equal_p (rl->in_reg, pseudo)
6841 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6842 && reg_last_reload_reg[REGNO (pseudo)])
6844 int pseudo_no = REGNO (pseudo);
6845 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6847 /* We don't need to test full validity of last_regno for
6848 inherit here; we only want to know if the store actually
6849 matches the pseudo. */
6850 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6851 && reg_reloaded_contents[last_regno] == pseudo_no
6852 && spill_reg_store[last_regno]
6853 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6854 delete_output_reload (insn, j, last_regno);
6859 || rl->reg_rtx == old
6860 || rl->reg_rtx == 0)
6863 /* An output operand that dies right away does need a reload,
6864 but need not be copied from it. Show the new location in the
6866 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6867 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6869 XEXP (note, 0) = rl->reg_rtx;
6872 /* Likewise for a SUBREG of an operand that dies. */
6873 else if (GET_CODE (old) == SUBREG
6874 && GET_CODE (SUBREG_REG (old)) == REG
6875 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6878 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6882 else if (GET_CODE (old) == SCRATCH)
6883 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6884 but we don't want to make an output reload. */
6887 /* If is a JUMP_INSN, we can't support output reloads yet. */
6888 if (GET_CODE (insn) == JUMP_INSN)
6891 emit_output_reload_insns (chain, rld + j, j);
6894 /* Output insns to reload values in and out of the chosen reload regs. */
6897 emit_reload_insns (struct insn_chain *chain)
6899 rtx insn = chain->insn;
6903 CLEAR_HARD_REG_SET (reg_reloaded_died);
6905 for (j = 0; j < reload_n_operands; j++)
6906 input_reload_insns[j] = input_address_reload_insns[j]
6907 = inpaddr_address_reload_insns[j]
6908 = output_reload_insns[j] = output_address_reload_insns[j]
6909 = outaddr_address_reload_insns[j]
6910 = other_output_reload_insns[j] = 0;
6911 other_input_address_reload_insns = 0;
6912 other_input_reload_insns = 0;
6913 operand_reload_insns = 0;
6914 other_operand_reload_insns = 0;
6916 /* Dump reloads into the dump file. */
6919 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6920 debug_reload_to_stream (rtl_dump_file);
6923 /* Now output the instructions to copy the data into and out of the
6924 reload registers. Do these in the order that the reloads were reported,
6925 since reloads of base and index registers precede reloads of operands
6926 and the operands may need the base and index registers reloaded. */
6928 for (j = 0; j < n_reloads; j++)
6931 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6932 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6934 do_input_reload (chain, rld + j, j);
6935 do_output_reload (chain, rld + j, j);
6938 /* Now write all the insns we made for reloads in the order expected by
6939 the allocation functions. Prior to the insn being reloaded, we write
6940 the following reloads:
6942 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6944 RELOAD_OTHER reloads.
6946 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6947 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6948 RELOAD_FOR_INPUT reload for the operand.
6950 RELOAD_FOR_OPADDR_ADDRS reloads.
6952 RELOAD_FOR_OPERAND_ADDRESS reloads.
6954 After the insn being reloaded, we write the following:
6956 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6957 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6958 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6959 reloads for the operand. The RELOAD_OTHER output reloads are
6960 output in descending order by reload number. */
6962 emit_insn_before (other_input_address_reload_insns, insn);
6963 emit_insn_before (other_input_reload_insns, insn);
6965 for (j = 0; j < reload_n_operands; j++)
6967 emit_insn_before (inpaddr_address_reload_insns[j], insn);
6968 emit_insn_before (input_address_reload_insns[j], insn);
6969 emit_insn_before (input_reload_insns[j], insn);
6972 emit_insn_before (other_operand_reload_insns, insn);
6973 emit_insn_before (operand_reload_insns, insn);
6975 for (j = 0; j < reload_n_operands; j++)
6977 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
6978 x = emit_insn_after (output_address_reload_insns[j], x);
6979 x = emit_insn_after (output_reload_insns[j], x);
6980 emit_insn_after (other_output_reload_insns[j], x);
6983 /* For all the spill regs newly reloaded in this instruction,
6984 record what they were reloaded from, so subsequent instructions
6985 can inherit the reloads.
6987 Update spill_reg_store for the reloads of this insn.
6988 Copy the elements that were updated in the loop above. */
6990 for (j = 0; j < n_reloads; j++)
6992 int r = reload_order[j];
6993 int i = reload_spill_index[r];
6995 /* If this is a non-inherited input reload from a pseudo, we must
6996 clear any memory of a previous store to the same pseudo. Only do
6997 something if there will not be an output reload for the pseudo
6999 if (rld[r].in_reg != 0
7000 && ! (reload_inherited[r] || reload_override_in[r]))
7002 rtx reg = rld[r].in_reg;
7004 if (GET_CODE (reg) == SUBREG)
7005 reg = SUBREG_REG (reg);
7007 if (GET_CODE (reg) == REG
7008 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7009 && ! reg_has_output_reload[REGNO (reg)])
7011 int nregno = REGNO (reg);
7013 if (reg_last_reload_reg[nregno])
7015 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7017 if (reg_reloaded_contents[last_regno] == nregno)
7018 spill_reg_store[last_regno] = 0;
7023 /* I is nonneg if this reload used a register.
7024 If rld[r].reg_rtx is 0, this is an optional reload
7025 that we opted to ignore. */
7027 if (i >= 0 && rld[r].reg_rtx != 0)
7029 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7031 int part_reaches_end = 0;
7032 int all_reaches_end = 1;
7034 /* For a multi register reload, we need to check if all or part
7035 of the value lives to the end. */
7036 for (k = 0; k < nr; k++)
7038 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7039 rld[r].when_needed))
7040 part_reaches_end = 1;
7042 all_reaches_end = 0;
7045 /* Ignore reloads that don't reach the end of the insn in
7047 if (all_reaches_end)
7049 /* First, clear out memory of what used to be in this spill reg.
7050 If consecutive registers are used, clear them all. */
7052 for (k = 0; k < nr; k++)
7053 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7055 /* Maybe the spill reg contains a copy of reload_out. */
7057 && (GET_CODE (rld[r].out) == REG
7061 || GET_CODE (rld[r].out_reg) == REG))
7063 rtx out = (GET_CODE (rld[r].out) == REG
7067 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7068 int nregno = REGNO (out);
7069 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7070 : HARD_REGNO_NREGS (nregno,
7071 GET_MODE (rld[r].reg_rtx)));
7073 spill_reg_store[i] = new_spill_reg_store[i];
7074 spill_reg_stored_to[i] = out;
7075 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7077 /* If NREGNO is a hard register, it may occupy more than
7078 one register. If it does, say what is in the
7079 rest of the registers assuming that both registers
7080 agree on how many words the object takes. If not,
7081 invalidate the subsequent registers. */
7083 if (nregno < FIRST_PSEUDO_REGISTER)
7084 for (k = 1; k < nnr; k++)
7085 reg_last_reload_reg[nregno + k]
7087 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7090 /* Now do the inverse operation. */
7091 for (k = 0; k < nr; k++)
7093 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7094 reg_reloaded_contents[i + k]
7095 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7098 reg_reloaded_insn[i + k] = insn;
7099 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7103 /* Maybe the spill reg contains a copy of reload_in. Only do
7104 something if there will not be an output reload for
7105 the register being reloaded. */
7106 else if (rld[r].out_reg == 0
7108 && ((GET_CODE (rld[r].in) == REG
7109 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7110 && ! reg_has_output_reload[REGNO (rld[r].in)])
7111 || (GET_CODE (rld[r].in_reg) == REG
7112 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7113 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7118 if (GET_CODE (rld[r].in) == REG
7119 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7120 nregno = REGNO (rld[r].in);
7121 else if (GET_CODE (rld[r].in_reg) == REG)
7122 nregno = REGNO (rld[r].in_reg);
7124 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7126 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7127 : HARD_REGNO_NREGS (nregno,
7128 GET_MODE (rld[r].reg_rtx)));
7130 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7132 if (nregno < FIRST_PSEUDO_REGISTER)
7133 for (k = 1; k < nnr; k++)
7134 reg_last_reload_reg[nregno + k]
7136 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7139 /* Unless we inherited this reload, show we haven't
7140 recently done a store.
7141 Previous stores of inherited auto_inc expressions
7142 also have to be discarded. */
7143 if (! reload_inherited[r]
7144 || (rld[r].out && ! rld[r].out_reg))
7145 spill_reg_store[i] = 0;
7147 for (k = 0; k < nr; k++)
7149 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7150 reg_reloaded_contents[i + k]
7151 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7154 reg_reloaded_insn[i + k] = insn;
7155 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7160 /* However, if part of the reload reaches the end, then we must
7161 invalidate the old info for the part that survives to the end. */
7162 else if (part_reaches_end)
7164 for (k = 0; k < nr; k++)
7165 if (reload_reg_reaches_end_p (i + k,
7167 rld[r].when_needed))
7168 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7172 /* The following if-statement was #if 0'd in 1.34 (or before...).
7173 It's reenabled in 1.35 because supposedly nothing else
7174 deals with this problem. */
7176 /* If a register gets output-reloaded from a non-spill register,
7177 that invalidates any previous reloaded copy of it.
7178 But forget_old_reloads_1 won't get to see it, because
7179 it thinks only about the original insn. So invalidate it here. */
7180 if (i < 0 && rld[r].out != 0
7181 && (GET_CODE (rld[r].out) == REG
7182 || (GET_CODE (rld[r].out) == MEM
7183 && GET_CODE (rld[r].out_reg) == REG)))
7185 rtx out = (GET_CODE (rld[r].out) == REG
7186 ? rld[r].out : rld[r].out_reg);
7187 int nregno = REGNO (out);
7188 if (nregno >= FIRST_PSEUDO_REGISTER)
7190 rtx src_reg, store_insn = NULL_RTX;
7192 reg_last_reload_reg[nregno] = 0;
7194 /* If we can find a hard register that is stored, record
7195 the storing insn so that we may delete this insn with
7196 delete_output_reload. */
7197 src_reg = rld[r].reg_rtx;
7199 /* If this is an optional reload, try to find the source reg
7200 from an input reload. */
7203 rtx set = single_set (insn);
7204 if (set && SET_DEST (set) == rld[r].out)
7208 src_reg = SET_SRC (set);
7210 for (k = 0; k < n_reloads; k++)
7212 if (rld[k].in == src_reg)
7214 src_reg = rld[k].reg_rtx;
7221 store_insn = new_spill_reg_store[REGNO (src_reg)];
7222 if (src_reg && GET_CODE (src_reg) == REG
7223 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7225 int src_regno = REGNO (src_reg);
7226 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7227 /* The place where to find a death note varies with
7228 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7229 necessarily checked exactly in the code that moves
7230 notes, so just check both locations. */
7231 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7232 if (! note && store_insn)
7233 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7236 spill_reg_store[src_regno + nr] = store_insn;
7237 spill_reg_stored_to[src_regno + nr] = out;
7238 reg_reloaded_contents[src_regno + nr] = nregno;
7239 reg_reloaded_insn[src_regno + nr] = store_insn;
7240 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7241 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7242 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7244 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7246 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7248 reg_last_reload_reg[nregno] = src_reg;
7253 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7255 while (num_regs-- > 0)
7256 reg_last_reload_reg[nregno + num_regs] = 0;
7260 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7263 /* Emit code to perform a reload from IN (which may be a reload register) to
7264 OUT (which may also be a reload register). IN or OUT is from operand
7265 OPNUM with reload type TYPE.
7267 Returns first insn emitted. */
7270 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7272 rtx last = get_last_insn ();
7275 /* If IN is a paradoxical SUBREG, remove it and try to put the
7276 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7277 if (GET_CODE (in) == SUBREG
7278 && (GET_MODE_SIZE (GET_MODE (in))
7279 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7280 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7281 in = SUBREG_REG (in), out = tem;
7282 else if (GET_CODE (out) == SUBREG
7283 && (GET_MODE_SIZE (GET_MODE (out))
7284 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7285 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7286 out = SUBREG_REG (out), in = tem;
7288 /* How to do this reload can get quite tricky. Normally, we are being
7289 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7290 register that didn't get a hard register. In that case we can just
7291 call emit_move_insn.
7293 We can also be asked to reload a PLUS that adds a register or a MEM to
7294 another register, constant or MEM. This can occur during frame pointer
7295 elimination and while reloading addresses. This case is handled by
7296 trying to emit a single insn to perform the add. If it is not valid,
7297 we use a two insn sequence.
7299 Finally, we could be called to handle an 'o' constraint by putting
7300 an address into a register. In that case, we first try to do this
7301 with a named pattern of "reload_load_address". If no such pattern
7302 exists, we just emit a SET insn and hope for the best (it will normally
7303 be valid on machines that use 'o').
7305 This entire process is made complex because reload will never
7306 process the insns we generate here and so we must ensure that
7307 they will fit their constraints and also by the fact that parts of
7308 IN might be being reloaded separately and replaced with spill registers.
7309 Because of this, we are, in some sense, just guessing the right approach
7310 here. The one listed above seems to work.
7312 ??? At some point, this whole thing needs to be rethought. */
7314 if (GET_CODE (in) == PLUS
7315 && (GET_CODE (XEXP (in, 0)) == REG
7316 || GET_CODE (XEXP (in, 0)) == SUBREG
7317 || GET_CODE (XEXP (in, 0)) == MEM)
7318 && (GET_CODE (XEXP (in, 1)) == REG
7319 || GET_CODE (XEXP (in, 1)) == SUBREG
7320 || CONSTANT_P (XEXP (in, 1))
7321 || GET_CODE (XEXP (in, 1)) == MEM))
7323 /* We need to compute the sum of a register or a MEM and another
7324 register, constant, or MEM, and put it into the reload
7325 register. The best possible way of doing this is if the machine
7326 has a three-operand ADD insn that accepts the required operands.
7328 The simplest approach is to try to generate such an insn and see if it
7329 is recognized and matches its constraints. If so, it can be used.
7331 It might be better not to actually emit the insn unless it is valid,
7332 but we need to pass the insn as an operand to `recog' and
7333 `extract_insn' and it is simpler to emit and then delete the insn if
7334 not valid than to dummy things up. */
7336 rtx op0, op1, tem, insn;
7339 op0 = find_replacement (&XEXP (in, 0));
7340 op1 = find_replacement (&XEXP (in, 1));
7342 /* Since constraint checking is strict, commutativity won't be
7343 checked, so we need to do that here to avoid spurious failure
7344 if the add instruction is two-address and the second operand
7345 of the add is the same as the reload reg, which is frequently
7346 the case. If the insn would be A = B + A, rearrange it so
7347 it will be A = A + B as constrain_operands expects. */
7349 if (GET_CODE (XEXP (in, 1)) == REG
7350 && REGNO (out) == REGNO (XEXP (in, 1)))
7351 tem = op0, op0 = op1, op1 = tem;
7353 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7354 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7356 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7357 code = recog_memoized (insn);
7361 extract_insn (insn);
7362 /* We want constrain operands to treat this insn strictly in
7363 its validity determination, i.e., the way it would after reload
7365 if (constrain_operands (1))
7369 delete_insns_since (last);
7371 /* If that failed, we must use a conservative two-insn sequence.
7373 Use a move to copy one operand into the reload register. Prefer
7374 to reload a constant, MEM or pseudo since the move patterns can
7375 handle an arbitrary operand. If OP1 is not a constant, MEM or
7376 pseudo and OP1 is not a valid operand for an add instruction, then
7379 After reloading one of the operands into the reload register, add
7380 the reload register to the output register.
7382 If there is another way to do this for a specific machine, a
7383 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7386 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7388 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7389 || (GET_CODE (op1) == REG
7390 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7391 || (code != CODE_FOR_nothing
7392 && ! ((*insn_data[code].operand[2].predicate)
7393 (op1, insn_data[code].operand[2].mode))))
7394 tem = op0, op0 = op1, op1 = tem;
7396 gen_reload (out, op0, opnum, type);
7398 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7399 This fixes a problem on the 32K where the stack pointer cannot
7400 be used as an operand of an add insn. */
7402 if (rtx_equal_p (op0, op1))
7405 insn = emit_insn (gen_add2_insn (out, op1));
7407 /* If that failed, copy the address register to the reload register.
7408 Then add the constant to the reload register. */
7410 code = recog_memoized (insn);
7414 extract_insn (insn);
7415 /* We want constrain operands to treat this insn strictly in
7416 its validity determination, i.e., the way it would after reload
7418 if (constrain_operands (1))
7420 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7422 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7427 delete_insns_since (last);
7429 gen_reload (out, op1, opnum, type);
7430 insn = emit_insn (gen_add2_insn (out, op0));
7431 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7434 #ifdef SECONDARY_MEMORY_NEEDED
7435 /* If we need a memory location to do the move, do it that way. */
7436 else if ((GET_CODE (in) == REG || GET_CODE (in) == SUBREG)
7437 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7438 && (GET_CODE (out) == REG || GET_CODE (out) == SUBREG)
7439 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7440 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7441 REGNO_REG_CLASS (reg_or_subregno (out)),
7444 /* Get the memory to use and rewrite both registers to its mode. */
7445 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7447 if (GET_MODE (loc) != GET_MODE (out))
7448 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7450 if (GET_MODE (loc) != GET_MODE (in))
7451 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7453 gen_reload (loc, in, opnum, type);
7454 gen_reload (out, loc, opnum, type);
7458 /* If IN is a simple operand, use gen_move_insn. */
7459 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7460 emit_insn (gen_move_insn (out, in));
7462 #ifdef HAVE_reload_load_address
7463 else if (HAVE_reload_load_address)
7464 emit_insn (gen_reload_load_address (out, in));
7467 /* Otherwise, just write (set OUT IN) and hope for the best. */
7469 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7471 /* Return the first insn emitted.
7472 We can not just return get_last_insn, because there may have
7473 been multiple instructions emitted. Also note that gen_move_insn may
7474 emit more than one insn itself, so we can not assume that there is one
7475 insn emitted per emit_insn_before call. */
7477 return last ? NEXT_INSN (last) : get_insns ();
7480 /* Delete a previously made output-reload whose result we now believe
7481 is not needed. First we double-check.
7483 INSN is the insn now being processed.
7484 LAST_RELOAD_REG is the hard register number for which we want to delete
7485 the last output reload.
7486 J is the reload-number that originally used REG. The caller has made
7487 certain that reload J doesn't use REG any longer for input. */
7490 delete_output_reload (rtx insn, int j, int last_reload_reg)
7492 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7493 rtx reg = spill_reg_stored_to[last_reload_reg];
7496 int n_inherited = 0;
7500 /* It is possible that this reload has been only used to set another reload
7501 we eliminated earlier and thus deleted this instruction too. */
7502 if (INSN_DELETED_P (output_reload_insn))
7505 /* Get the raw pseudo-register referred to. */
7507 while (GET_CODE (reg) == SUBREG)
7508 reg = SUBREG_REG (reg);
7509 substed = reg_equiv_memory_loc[REGNO (reg)];
7511 /* This is unsafe if the operand occurs more often in the current
7512 insn than it is inherited. */
7513 for (k = n_reloads - 1; k >= 0; k--)
7515 rtx reg2 = rld[k].in;
7518 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7519 reg2 = rld[k].in_reg;
7521 if (rld[k].out && ! rld[k].out_reg)
7522 reg2 = XEXP (rld[k].in_reg, 0);
7524 while (GET_CODE (reg2) == SUBREG)
7525 reg2 = SUBREG_REG (reg2);
7526 if (rtx_equal_p (reg2, reg))
7528 if (reload_inherited[k] || reload_override_in[k] || k == j)
7531 reg2 = rld[k].out_reg;
7534 while (GET_CODE (reg2) == SUBREG)
7535 reg2 = XEXP (reg2, 0);
7536 if (rtx_equal_p (reg2, reg))
7543 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7545 n_occurrences += count_occurrences (PATTERN (insn),
7546 eliminate_regs (substed, 0,
7548 if (n_occurrences > n_inherited)
7551 /* If the pseudo-reg we are reloading is no longer referenced
7552 anywhere between the store into it and here,
7553 and no jumps or labels intervene, then the value can get
7554 here through the reload reg alone.
7555 Otherwise, give up--return. */
7556 for (i1 = NEXT_INSN (output_reload_insn);
7557 i1 != insn; i1 = NEXT_INSN (i1))
7559 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7561 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7562 && reg_mentioned_p (reg, PATTERN (i1)))
7564 /* If this is USE in front of INSN, we only have to check that
7565 there are no more references than accounted for by inheritance. */
7566 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7568 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7569 i1 = NEXT_INSN (i1);
7571 if (n_occurrences <= n_inherited && i1 == insn)
7577 /* We will be deleting the insn. Remove the spill reg information. */
7578 for (k = HARD_REGNO_NREGS (last_reload_reg, GET_MODE (reg)); k-- > 0; )
7580 spill_reg_store[last_reload_reg + k] = 0;
7581 spill_reg_stored_to[last_reload_reg + k] = 0;
7584 /* The caller has already checked that REG dies or is set in INSN.
7585 It has also checked that we are optimizing, and thus some
7586 inaccuracies in the debugging information are acceptable.
7587 So we could just delete output_reload_insn. But in some cases
7588 we can improve the debugging information without sacrificing
7589 optimization - maybe even improving the code: See if the pseudo
7590 reg has been completely replaced with reload regs. If so, delete
7591 the store insn and forget we had a stack slot for the pseudo. */
7592 if (rld[j].out != rld[j].in
7593 && REG_N_DEATHS (REGNO (reg)) == 1
7594 && REG_N_SETS (REGNO (reg)) == 1
7595 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7596 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7600 /* We know that it was used only between here and the beginning of
7601 the current basic block. (We also know that the last use before
7602 INSN was the output reload we are thinking of deleting, but never
7603 mind that.) Search that range; see if any ref remains. */
7604 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7606 rtx set = single_set (i2);
7608 /* Uses which just store in the pseudo don't count,
7609 since if they are the only uses, they are dead. */
7610 if (set != 0 && SET_DEST (set) == reg)
7612 if (GET_CODE (i2) == CODE_LABEL
7613 || GET_CODE (i2) == JUMP_INSN)
7615 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7616 && reg_mentioned_p (reg, PATTERN (i2)))
7618 /* Some other ref remains; just delete the output reload we
7620 delete_address_reloads (output_reload_insn, insn);
7621 delete_insn (output_reload_insn);
7626 /* Delete the now-dead stores into this pseudo. Note that this
7627 loop also takes care of deleting output_reload_insn. */
7628 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7630 rtx set = single_set (i2);
7632 if (set != 0 && SET_DEST (set) == reg)
7634 delete_address_reloads (i2, insn);
7637 if (GET_CODE (i2) == CODE_LABEL
7638 || GET_CODE (i2) == JUMP_INSN)
7642 /* For the debugging info, say the pseudo lives in this reload reg. */
7643 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7644 alter_reg (REGNO (reg), -1);
7648 delete_address_reloads (output_reload_insn, insn);
7649 delete_insn (output_reload_insn);
7653 /* We are going to delete DEAD_INSN. Recursively delete loads of
7654 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7655 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7657 delete_address_reloads (rtx dead_insn, rtx current_insn)
7659 rtx set = single_set (dead_insn);
7660 rtx set2, dst, prev, next;
7663 rtx dst = SET_DEST (set);
7664 if (GET_CODE (dst) == MEM)
7665 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7667 /* If we deleted the store from a reloaded post_{in,de}c expression,
7668 we can delete the matching adds. */
7669 prev = PREV_INSN (dead_insn);
7670 next = NEXT_INSN (dead_insn);
7671 if (! prev || ! next)
7673 set = single_set (next);
7674 set2 = single_set (prev);
7676 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7677 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7678 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7680 dst = SET_DEST (set);
7681 if (! rtx_equal_p (dst, SET_DEST (set2))
7682 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7683 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7684 || (INTVAL (XEXP (SET_SRC (set), 1))
7685 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7687 delete_related_insns (prev);
7688 delete_related_insns (next);
7691 /* Subfunction of delete_address_reloads: process registers found in X. */
7693 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
7695 rtx prev, set, dst, i2;
7697 enum rtx_code code = GET_CODE (x);
7701 const char *fmt = GET_RTX_FORMAT (code);
7702 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7705 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7706 else if (fmt[i] == 'E')
7708 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7709 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7716 if (spill_reg_order[REGNO (x)] < 0)
7719 /* Scan backwards for the insn that sets x. This might be a way back due
7721 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7723 code = GET_CODE (prev);
7724 if (code == CODE_LABEL || code == JUMP_INSN)
7726 if (GET_RTX_CLASS (code) != 'i')
7728 if (reg_set_p (x, PATTERN (prev)))
7730 if (reg_referenced_p (x, PATTERN (prev)))
7733 if (! prev || INSN_UID (prev) < reload_first_uid)
7735 /* Check that PREV only sets the reload register. */
7736 set = single_set (prev);
7739 dst = SET_DEST (set);
7740 if (GET_CODE (dst) != REG
7741 || ! rtx_equal_p (dst, x))
7743 if (! reg_set_p (dst, PATTERN (dead_insn)))
7745 /* Check if DST was used in a later insn -
7746 it might have been inherited. */
7747 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7749 if (GET_CODE (i2) == CODE_LABEL)
7753 if (reg_referenced_p (dst, PATTERN (i2)))
7755 /* If there is a reference to the register in the current insn,
7756 it might be loaded in a non-inherited reload. If no other
7757 reload uses it, that means the register is set before
7759 if (i2 == current_insn)
7761 for (j = n_reloads - 1; j >= 0; j--)
7762 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7763 || reload_override_in[j] == dst)
7765 for (j = n_reloads - 1; j >= 0; j--)
7766 if (rld[j].in && rld[j].reg_rtx == dst)
7773 if (GET_CODE (i2) == JUMP_INSN)
7775 /* If DST is still live at CURRENT_INSN, check if it is used for
7776 any reload. Note that even if CURRENT_INSN sets DST, we still
7777 have to check the reloads. */
7778 if (i2 == current_insn)
7780 for (j = n_reloads - 1; j >= 0; j--)
7781 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7782 || reload_override_in[j] == dst)
7784 /* ??? We can't finish the loop here, because dst might be
7785 allocated to a pseudo in this block if no reload in this
7786 block needs any of the classes containing DST - see
7787 spill_hard_reg. There is no easy way to tell this, so we
7788 have to scan till the end of the basic block. */
7790 if (reg_set_p (dst, PATTERN (i2)))
7794 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7795 reg_reloaded_contents[REGNO (dst)] = -1;
7799 /* Output reload-insns to reload VALUE into RELOADREG.
7800 VALUE is an autoincrement or autodecrement RTX whose operand
7801 is a register or memory location;
7802 so reloading involves incrementing that location.
7803 IN is either identical to VALUE, or some cheaper place to reload from.
7805 INC_AMOUNT is the number to increment or decrement by (always positive).
7806 This cannot be deduced from VALUE.
7808 Return the instruction that stores into RELOADREG. */
7811 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
7813 /* REG or MEM to be copied and incremented. */
7814 rtx incloc = XEXP (value, 0);
7815 /* Nonzero if increment after copying. */
7816 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7822 rtx real_in = in == value ? XEXP (in, 0) : in;
7824 /* No hard register is equivalent to this register after
7825 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7826 we could inc/dec that register as well (maybe even using it for
7827 the source), but I'm not sure it's worth worrying about. */
7828 if (GET_CODE (incloc) == REG)
7829 reg_last_reload_reg[REGNO (incloc)] = 0;
7831 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7832 inc_amount = -inc_amount;
7834 inc = GEN_INT (inc_amount);
7836 /* If this is post-increment, first copy the location to the reload reg. */
7837 if (post && real_in != reloadreg)
7838 emit_insn (gen_move_insn (reloadreg, real_in));
7842 /* See if we can directly increment INCLOC. Use a method similar to
7843 that in gen_reload. */
7845 last = get_last_insn ();
7846 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7847 gen_rtx_PLUS (GET_MODE (incloc),
7850 code = recog_memoized (add_insn);
7853 extract_insn (add_insn);
7854 if (constrain_operands (1))
7856 /* If this is a pre-increment and we have incremented the value
7857 where it lives, copy the incremented value to RELOADREG to
7858 be used as an address. */
7861 emit_insn (gen_move_insn (reloadreg, incloc));
7866 delete_insns_since (last);
7869 /* If couldn't do the increment directly, must increment in RELOADREG.
7870 The way we do this depends on whether this is pre- or post-increment.
7871 For pre-increment, copy INCLOC to the reload register, increment it
7872 there, then save back. */
7876 if (in != reloadreg)
7877 emit_insn (gen_move_insn (reloadreg, real_in));
7878 emit_insn (gen_add2_insn (reloadreg, inc));
7879 store = emit_insn (gen_move_insn (incloc, reloadreg));
7884 Because this might be a jump insn or a compare, and because RELOADREG
7885 may not be available after the insn in an input reload, we must do
7886 the incrementation before the insn being reloaded for.
7888 We have already copied IN to RELOADREG. Increment the copy in
7889 RELOADREG, save that back, then decrement RELOADREG so it has
7890 the original value. */
7892 emit_insn (gen_add2_insn (reloadreg, inc));
7893 store = emit_insn (gen_move_insn (incloc, reloadreg));
7894 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7902 add_auto_inc_notes (rtx insn, rtx x)
7904 enum rtx_code code = GET_CODE (x);
7908 if (code == MEM && auto_inc_p (XEXP (x, 0)))
7911 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
7915 /* Scan all the operand sub-expressions. */
7916 fmt = GET_RTX_FORMAT (code);
7917 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7920 add_auto_inc_notes (insn, XEXP (x, i));
7921 else if (fmt[i] == 'E')
7922 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7923 add_auto_inc_notes (insn, XVECEXP (x, i, j));
7928 /* Copy EH notes from an insn to its reloads. */
7930 copy_eh_notes (rtx insn, rtx x)
7932 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
7935 for (; x != 0; x = NEXT_INSN (x))
7937 if (may_trap_p (PATTERN (x)))
7939 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
7945 /* This is used by reload pass, that does emit some instructions after
7946 abnormal calls moving basic block end, but in fact it wants to emit
7947 them on the edge. Looks for abnormal call edges, find backward the
7948 proper call and fix the damage.
7950 Similar handle instructions throwing exceptions internally. */
7952 fixup_abnormal_edges (void)
7954 bool inserted = false;
7961 /* Look for cases we are interested in - calls or instructions causing
7963 for (e = bb->succ; e; e = e->succ_next)
7965 if (e->flags & EDGE_ABNORMAL_CALL)
7967 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
7968 == (EDGE_ABNORMAL | EDGE_EH))
7971 if (e && GET_CODE (bb->end) != CALL_INSN && !can_throw_internal (bb->end))
7973 rtx insn = bb->end, stop = NEXT_INSN (bb->end);
7975 for (e = bb->succ; e; e = e->succ_next)
7976 if (e->flags & EDGE_FALLTHRU)
7978 /* Get past the new insns generated. Allow notes, as the insns may
7979 be already deleted. */
7980 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE)
7981 && !can_throw_internal (insn)
7982 && insn != bb->head)
7983 insn = PREV_INSN (insn);
7984 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn))
7988 insn = NEXT_INSN (insn);
7989 while (insn && insn != stop)
7991 next = NEXT_INSN (insn);
7996 /* Sometimes there's still the return value USE.
7997 If it's placed after a trapping call (i.e. that
7998 call is the last insn anyway), we have no fallthru
7999 edge. Simply delete this use and don't try to insert
8000 on the non-existent edge. */
8001 if (GET_CODE (PATTERN (insn)) != USE)
8003 /* We're not deleting it, we're moving it. */
8004 INSN_DELETED_P (insn) = 0;
8005 PREV_INSN (insn) = NULL_RTX;
8006 NEXT_INSN (insn) = NULL_RTX;
8008 insert_insn_on_edge (insn, e);
8015 /* We've possibly turned single trapping insn into multiple ones. */
8016 if (flag_non_call_exceptions)
8019 blocks = sbitmap_alloc (last_basic_block);
8020 sbitmap_ones (blocks);
8021 find_many_sub_basic_blocks (blocks);
8024 commit_edge_insertions ();
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