1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 88, 89, 92-97, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "insn-flags.h"
31 #include "insn-codes.h"
35 #include "basic-block.h"
42 /* This file contains the reload pass of the compiler, which is
43 run after register allocation has been done. It checks that
44 each insn is valid (operands required to be in registers really
45 are in registers of the proper class) and fixes up invalid ones
46 by copying values temporarily into registers for the insns
49 The results of register allocation are described by the vector
50 reg_renumber; the insns still contain pseudo regs, but reg_renumber
51 can be used to find which hard reg, if any, a pseudo reg is in.
53 The technique we always use is to free up a few hard regs that are
54 called ``reload regs'', and for each place where a pseudo reg
55 must be in a hard reg, copy it temporarily into one of the reload regs.
57 All the pseudos that were formerly allocated to the hard regs that
58 are now in use as reload regs must be ``spilled''. This means
59 that they go to other hard regs, or to stack slots if no other
60 available hard regs can be found. Spilling can invalidate more
61 insns, requiring additional need for reloads, so we must keep checking
62 until the process stabilizes.
64 For machines with different classes of registers, we must keep track
65 of the register class needed for each reload, and make sure that
66 we allocate enough reload registers of each class.
68 The file reload.c contains the code that checks one insn for
69 validity and reports the reloads that it needs. This file
70 is in charge of scanning the entire rtl code, accumulating the
71 reload needs, spilling, assigning reload registers to use for
72 fixing up each insn, and generating the new insns to copy values
73 into the reload registers. */
76 #ifndef REGISTER_MOVE_COST
77 #define REGISTER_MOVE_COST(x, y) 2
80 /* During reload_as_needed, element N contains a REG rtx for the hard reg
81 into which reg N has been reloaded (perhaps for a previous insn). */
82 static rtx *reg_last_reload_reg;
84 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
85 for an output reload that stores into reg N. */
86 static char *reg_has_output_reload;
88 /* Indicates which hard regs are reload-registers for an output reload
89 in the current insn. */
90 static HARD_REG_SET reg_is_output_reload;
92 /* Element N is the constant value to which pseudo reg N is equivalent,
93 or zero if pseudo reg N is not equivalent to a constant.
94 find_reloads looks at this in order to replace pseudo reg N
95 with the constant it stands for. */
96 rtx *reg_equiv_constant;
98 /* Element N is a memory location to which pseudo reg N is equivalent,
99 prior to any register elimination (such as frame pointer to stack
100 pointer). Depending on whether or not it is a valid address, this value
101 is transferred to either reg_equiv_address or reg_equiv_mem. */
102 rtx *reg_equiv_memory_loc;
104 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
105 This is used when the address is not valid as a memory address
106 (because its displacement is too big for the machine.) */
107 rtx *reg_equiv_address;
109 /* Element N is the memory slot to which pseudo reg N is equivalent,
110 or zero if pseudo reg N is not equivalent to a memory slot. */
113 /* Widest width in which each pseudo reg is referred to (via subreg). */
114 static int *reg_max_ref_width;
116 /* Element N is the insn that initialized reg N from its equivalent
117 constant or memory slot. */
118 static rtx *reg_equiv_init;
120 /* During reload_as_needed, element N contains the last pseudo regno reloaded
121 into hard register N. If that pseudo reg occupied more than one register,
122 reg_reloaded_contents points to that pseudo for each spill register in
123 use; all of these must remain set for an inheritance to occur. */
124 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
126 /* During reload_as_needed, element N contains the insn for which
127 hard register N was last used. Its contents are significant only
128 when reg_reloaded_valid is set for this register. */
129 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
131 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
132 static HARD_REG_SET reg_reloaded_valid;
133 /* Indicate if the register was dead at the end of the reload.
134 This is only valid if reg_reloaded_contents is set and valid. */
135 static HARD_REG_SET reg_reloaded_dead;
137 /* Number of spill-regs so far; number of valid elements of spill_regs. */
140 /* In parallel with spill_regs, contains REG rtx's for those regs.
141 Holds the last rtx used for any given reg, or 0 if it has never
142 been used for spilling yet. This rtx is reused, provided it has
144 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
146 /* In parallel with spill_regs, contains nonzero for a spill reg
147 that was stored after the last time it was used.
148 The precise value is the insn generated to do the store. */
149 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
151 /* This table is the inverse mapping of spill_regs:
152 indexed by hard reg number,
153 it contains the position of that reg in spill_regs,
154 or -1 for something that is not in spill_regs. */
155 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
157 /* This reg set indicates registers that may not be used for retrying global
158 allocation. The registers that may not be used include all spill registers
159 and the frame pointer (if we are using one). */
160 HARD_REG_SET forbidden_regs;
162 /* This reg set indicates registers that are not good for spill registers.
163 They will not be used to complete groups of spill registers. This includes
164 all fixed registers, registers that may be eliminated, and, if
165 SMALL_REGISTER_CLASSES is zero, registers explicitly used in the rtl.
167 (spill_reg_order prevents these registers from being used to start a
169 static HARD_REG_SET bad_spill_regs;
171 /* Describes order of use of registers for reloading
172 of spilled pseudo-registers. `spills' is the number of
173 elements that are actually valid; new ones are added at the end. */
174 static short spill_regs[FIRST_PSEUDO_REGISTER];
176 /* This reg set indicates those registers that have been used a spill
177 registers. This information is used in reorg.c, to help figure out
178 what registers are live at any point. It is assumed that all spill_regs
179 are dead at every CODE_LABEL. */
181 HARD_REG_SET used_spill_regs;
183 /* Index of last register assigned as a spill register. We allocate in
184 a round-robin fashion. */
186 static int last_spill_reg;
188 /* Describes order of preference for putting regs into spill_regs.
189 Contains the numbers of all the hard regs, in order most preferred first.
190 This order is different for each function.
191 It is set up by order_regs_for_reload.
192 Empty elements at the end contain -1. */
193 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
195 /* 1 for a hard register that appears explicitly in the rtl
196 (for example, function value registers, special registers
197 used by insns, structure value pointer registers). */
198 static char regs_explicitly_used[FIRST_PSEUDO_REGISTER];
200 /* Indicates if a register was counted against the need for
201 groups. 0 means it can count against max_nongroup instead. */
202 static HARD_REG_SET counted_for_groups;
204 /* Indicates if a register was counted against the need for
205 non-groups. 0 means it can become part of a new group.
206 During choose_reload_regs, 1 here means don't use this reg
207 as part of a group, even if it seems to be otherwise ok. */
208 static HARD_REG_SET counted_for_nongroups;
210 /* Nonzero if indirect addressing is supported on the machine; this means
211 that spilling (REG n) does not require reloading it into a register in
212 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
213 value indicates the level of indirect addressing supported, e.g., two
214 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
217 static char spill_indirect_levels;
219 /* Nonzero if indirect addressing is supported when the innermost MEM is
220 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
221 which these are valid is the same as spill_indirect_levels, above. */
223 char indirect_symref_ok;
225 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
227 char double_reg_address_ok;
229 /* Record the stack slot for each spilled hard register. */
231 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
233 /* Width allocated so far for that stack slot. */
235 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
237 /* Indexed by register class and basic block number, nonzero if there is
238 any need for a spill register of that class in that basic block.
239 The pointer is 0 if we did stupid allocation and don't know
240 the structure of basic blocks. */
242 char *basic_block_needs[N_REG_CLASSES];
244 /* First uid used by insns created by reload in this function.
245 Used in find_equiv_reg. */
246 int reload_first_uid;
248 /* Flag set by local-alloc or global-alloc if anything is live in
249 a call-clobbered reg across calls. */
251 int caller_save_needed;
253 /* The register class to use for a base register when reloading an
254 address. This is normally BASE_REG_CLASS, but it may be different
255 when using SMALL_REGISTER_CLASSES and passing parameters in
257 enum reg_class reload_address_base_reg_class;
259 /* The register class to use for an index register when reloading an
260 address. This is normally INDEX_REG_CLASS, but it may be different
261 when using SMALL_REGISTER_CLASSES and passing parameters in
263 enum reg_class reload_address_index_reg_class;
265 /* Set to 1 while reload_as_needed is operating.
266 Required by some machines to handle any generated moves differently. */
268 int reload_in_progress = 0;
270 /* These arrays record the insn_code of insns that may be needed to
271 perform input and output reloads of special objects. They provide a
272 place to pass a scratch register. */
274 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
275 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
277 /* This obstack is used for allocation of rtl during register elimination.
278 The allocated storage can be freed once find_reloads has processed the
281 struct obstack reload_obstack;
283 /* Points to the beginning of the reload_obstack. All insn_chain structures
284 are allocated first. */
285 char *reload_startobj;
287 /* The point after all insn_chain structures. Used to quickly deallocate
288 memory used while processing one insn. */
289 char *reload_firstobj;
291 #define obstack_chunk_alloc xmalloc
292 #define obstack_chunk_free free
294 /* List of labels that must never be deleted. */
295 extern rtx forced_labels;
297 /* List of insn_chain instructions, one for every insn that reload needs to
299 struct insn_chain *reload_insn_chain;
301 /* This structure is used to record information about register eliminations.
302 Each array entry describes one possible way of eliminating a register
303 in favor of another. If there is more than one way of eliminating a
304 particular register, the most preferred should be specified first. */
306 static struct elim_table
308 int from; /* Register number to be eliminated. */
309 int to; /* Register number used as replacement. */
310 int initial_offset; /* Initial difference between values. */
311 int can_eliminate; /* Non-zero if this elimination can be done. */
312 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
313 insns made by reload. */
314 int offset; /* Current offset between the two regs. */
315 int max_offset; /* Maximum offset between the two regs. */
316 int previous_offset; /* Offset at end of previous insn. */
317 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
318 rtx from_rtx; /* REG rtx for the register to be eliminated.
319 We cannot simply compare the number since
320 we might then spuriously replace a hard
321 register corresponding to a pseudo
322 assigned to the reg to be eliminated. */
323 rtx to_rtx; /* REG rtx for the replacement. */
326 /* If a set of eliminable registers was specified, define the table from it.
327 Otherwise, default to the normal case of the frame pointer being
328 replaced by the stack pointer. */
330 #ifdef ELIMINABLE_REGS
333 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
336 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0])
338 /* Record the number of pending eliminations that have an offset not equal
339 to their initial offset. If non-zero, we use a new copy of each
340 replacement result in any insns encountered. */
341 static int num_not_at_initial_offset;
343 /* Count the number of registers that we may be able to eliminate. */
344 static int num_eliminable;
346 /* For each label, we record the offset of each elimination. If we reach
347 a label by more than one path and an offset differs, we cannot do the
348 elimination. This information is indexed by the number of the label.
349 The first table is an array of flags that records whether we have yet
350 encountered a label and the second table is an array of arrays, one
351 entry in the latter array for each elimination. */
353 static char *offsets_known_at;
354 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
356 /* Number of labels in the current function. */
358 static int num_labels;
360 struct hard_reg_n_uses { int regno; int uses; };
362 static void dump_needs PROTO((FILE *));
363 static int calculate_needs_all_insns PROTO((rtx, int));
364 static int calculate_needs PROTO((int, rtx, rtx, int));
365 static int find_reload_regs PROTO((int, FILE *));
366 static int find_tworeg_group PROTO((int, int, FILE *));
367 static int find_group PROTO((int, int, FILE *));
368 static int possible_group_p PROTO((int, int *));
369 static void count_possible_groups PROTO((int *, enum machine_mode *,
371 static int modes_equiv_for_class_p PROTO((enum machine_mode,
374 static void delete_caller_save_insns PROTO((rtx));
375 static void spill_failure PROTO((rtx));
376 static int new_spill_reg PROTO((int, int, int *, int *, int,
378 static void delete_dead_insn PROTO((rtx));
379 static void alter_reg PROTO((int, int));
380 static void set_label_offsets PROTO((rtx, rtx, int));
381 static int eliminate_regs_in_insn PROTO((rtx, int));
382 static void mark_not_eliminable PROTO((rtx, rtx));
383 static void set_initial_elim_offsets PROTO((void));
384 static void init_elim_table PROTO((void));
385 static void update_eliminables PROTO((HARD_REG_SET *));
386 static int spill_hard_reg PROTO((int, int, FILE *, int));
387 static void scan_paradoxical_subregs PROTO((rtx));
388 static int hard_reg_use_compare PROTO((const GENERIC_PTR, const GENERIC_PTR));
389 static void order_regs_for_reload PROTO((void));
390 static int compare_spill_regs PROTO((const GENERIC_PTR, const GENERIC_PTR));
391 static void reload_as_needed PROTO((rtx, int));
392 static void forget_old_reloads_1 PROTO((rtx, rtx));
393 static int reload_reg_class_lower PROTO((const GENERIC_PTR, const GENERIC_PTR));
394 static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
396 static void clear_reload_reg_in_use PROTO((int, int, enum reload_type,
398 static int reload_reg_free_p PROTO((int, int, enum reload_type));
399 static int reload_reg_free_before_p PROTO((int, int, enum reload_type, int));
400 static int reload_reg_free_for_value_p PROTO((int, int, enum reload_type, rtx, rtx, int));
401 static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
402 static int allocate_reload_reg PROTO((int, rtx, int, int));
403 static void choose_reload_regs PROTO((rtx, rtx));
404 static void merge_assigned_reloads PROTO((rtx));
405 static void emit_reload_insns PROTO((rtx, int));
406 static void delete_output_reload PROTO((rtx, int, rtx));
407 static void inc_for_reload PROTO((rtx, rtx, int));
408 static int constraint_accepts_reg_p PROTO((char *, rtx));
409 static void reload_cse_regs_1 PROTO((rtx));
410 static void reload_cse_invalidate_regno PROTO((int, enum machine_mode, int));
411 static int reload_cse_mem_conflict_p PROTO((rtx, rtx));
412 static void reload_cse_invalidate_mem PROTO((rtx));
413 static void reload_cse_invalidate_rtx PROTO((rtx, rtx));
414 static int reload_cse_regno_equal_p PROTO((int, rtx, enum machine_mode));
415 static int reload_cse_noop_set_p PROTO((rtx, rtx));
416 static int reload_cse_simplify_set PROTO((rtx, rtx));
417 static int reload_cse_simplify_operands PROTO((rtx));
418 static void reload_cse_check_clobber PROTO((rtx, rtx));
419 static void reload_cse_record_set PROTO((rtx, rtx));
420 static void reload_cse_delete_death_notes PROTO((rtx));
421 static void reload_cse_no_longer_dead PROTO((int, enum machine_mode));
422 static void reload_combine PROTO((void));
423 static void reload_combine_note_use PROTO((rtx *, rtx));
424 static void reload_combine_note_store PROTO((rtx, rtx));
425 static void reload_cse_move2add PROTO((rtx));
426 static void move2add_note_store PROTO((rtx, rtx));
428 /* Initialize the reload pass once per compilation. */
435 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
436 Set spill_indirect_levels to the number of levels such addressing is
437 permitted, zero if it is not permitted at all. */
440 = gen_rtx_MEM (Pmode,
442 gen_rtx_REG (Pmode, LAST_VIRTUAL_REGISTER + 1),
444 spill_indirect_levels = 0;
446 while (memory_address_p (QImode, tem))
448 spill_indirect_levels++;
449 tem = gen_rtx_MEM (Pmode, tem);
452 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
454 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
455 indirect_symref_ok = memory_address_p (QImode, tem);
457 /* See if reg+reg is a valid (and offsettable) address. */
459 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
461 tem = gen_rtx_PLUS (Pmode,
462 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
463 gen_rtx_REG (Pmode, i));
464 /* This way, we make sure that reg+reg is an offsettable address. */
465 tem = plus_constant (tem, 4);
467 if (memory_address_p (QImode, tem))
469 double_reg_address_ok = 1;
474 /* Initialize obstack for our rtl allocation. */
475 gcc_obstack_init (&reload_obstack);
476 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
478 /* Decide which register class should be used when reloading
479 addresses. If we are using SMALL_REGISTER_CLASSES, and any
480 parameters are passed in registers, then we do not want to use
481 those registers when reloading an address. Otherwise, if a
482 function argument needs a reload, we may wind up clobbering
483 another argument to the function which was already computed. If
484 we find a subset class which simply avoids those registers, we
485 use it instead. ??? It would be better to only use the
486 restricted class when we actually are loading function arguments,
487 but that is hard to determine. */
488 reload_address_base_reg_class = BASE_REG_CLASS;
489 reload_address_index_reg_class = INDEX_REG_CLASS;
490 if (SMALL_REGISTER_CLASSES)
493 HARD_REG_SET base, index;
496 COPY_HARD_REG_SET (base, reg_class_contents[BASE_REG_CLASS]);
497 COPY_HARD_REG_SET (index, reg_class_contents[INDEX_REG_CLASS]);
498 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
500 if (FUNCTION_ARG_REGNO_P (regno))
502 CLEAR_HARD_REG_BIT (base, regno);
503 CLEAR_HARD_REG_BIT (index, regno);
507 GO_IF_HARD_REG_EQUAL (base, reg_class_contents[BASE_REG_CLASS],
509 for (p = reg_class_subclasses[BASE_REG_CLASS];
510 *p != LIM_REG_CLASSES;
513 GO_IF_HARD_REG_EQUAL (base, reg_class_contents[*p], usebase);
516 reload_address_base_reg_class = *p;
521 GO_IF_HARD_REG_EQUAL (index, reg_class_contents[INDEX_REG_CLASS],
523 for (p = reg_class_subclasses[INDEX_REG_CLASS];
524 *p != LIM_REG_CLASSES;
527 GO_IF_HARD_REG_EQUAL (index, reg_class_contents[*p], useindex);
530 reload_address_index_reg_class = *p;
537 /* List of insn chains that are currently unused. */
538 static struct insn_chain *unused_insn_chains = 0;
540 /* Allocate an empty insn_chain structure. */
544 struct insn_chain *c;
546 if (unused_insn_chains == 0)
548 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
549 c->live_before = OBSTACK_ALLOC_REG_SET (&reload_obstack);
550 c->live_after = OBSTACK_ALLOC_REG_SET (&reload_obstack);
554 c = unused_insn_chains;
555 unused_insn_chains = c->next;
557 c->is_caller_save_insn = 0;
563 /* Global variables used by reload and its subroutines. */
565 /* Set during calculate_needs if an insn needs reloading. */
566 static int something_needs_reloads;
567 /* Set during calculate_needs if an insn needs register elimination. */
568 static int something_needs_elimination;
570 /* For each class, number of reload regs needed in that class.
571 This is the maximum over all insns of the needs in that class
572 of the individual insn. */
573 static int max_needs[N_REG_CLASSES];
575 /* For each class, size of group of consecutive regs
576 that is needed for the reloads of this class. */
577 static int group_size[N_REG_CLASSES];
579 /* For each class, max number of consecutive groups needed.
580 (Each group contains group_size[CLASS] consecutive registers.) */
581 static int max_groups[N_REG_CLASSES];
583 /* For each class, max number needed of regs that don't belong
584 to any of the groups. */
585 static int max_nongroups[N_REG_CLASSES];
587 /* For each class, the machine mode which requires consecutive
588 groups of regs of that class.
589 If two different modes ever require groups of one class,
590 they must be the same size and equally restrictive for that class,
591 otherwise we can't handle the complexity. */
592 static enum machine_mode group_mode[N_REG_CLASSES];
594 /* Record the insn where each maximum need is first found. */
595 static rtx max_needs_insn[N_REG_CLASSES];
596 static rtx max_groups_insn[N_REG_CLASSES];
597 static rtx max_nongroups_insn[N_REG_CLASSES];
599 /* Nonzero means we couldn't get enough spill regs. */
602 /* Main entry point for the reload pass.
604 FIRST is the first insn of the function being compiled.
606 GLOBAL nonzero means we were called from global_alloc
607 and should attempt to reallocate any pseudoregs that we
608 displace from hard regs we will use for reloads.
609 If GLOBAL is zero, we do not have enough information to do that,
610 so any pseudo reg that is spilled must go to the stack.
612 DUMPFILE is the global-reg debugging dump file stream, or 0.
613 If it is nonzero, messages are written to it to describe
614 which registers are seized as reload regs, which pseudo regs
615 are spilled from them, and where the pseudo regs are reallocated to.
617 Return value is nonzero if reload failed
618 and we must not do any more for this function. */
621 reload (first, global, dumpfile)
628 register struct elim_table *ep;
630 /* The two pointers used to track the true location of the memory used
631 for label offsets. */
632 char *real_known_ptr = NULL_PTR;
633 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
635 int something_changed;
637 /* Make sure even insns with volatile mem refs are recognizable. */
642 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
644 /* Make sure that the last insn in the chain
645 is not something that needs reloading. */
646 emit_note (NULL_PTR, NOTE_INSN_DELETED);
648 /* Enable find_equiv_reg to distinguish insns made by reload. */
649 reload_first_uid = get_max_uid ();
651 for (i = 0; i < N_REG_CLASSES; i++)
652 basic_block_needs[i] = 0;
654 #ifdef SECONDARY_MEMORY_NEEDED
655 /* Initialize the secondary memory table. */
656 clear_secondary_mem ();
659 /* Remember which hard regs appear explicitly
660 before we merge into `regs_ever_live' the ones in which
661 pseudo regs have been allocated. */
662 bcopy (regs_ever_live, regs_explicitly_used, sizeof regs_ever_live);
664 /* We don't have a stack slot for any spill reg yet. */
665 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
666 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
668 /* Initialize the save area information for caller-save, in case some
672 /* Compute which hard registers are now in use
673 as homes for pseudo registers.
674 This is done here rather than (eg) in global_alloc
675 because this point is reached even if not optimizing. */
676 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
679 /* A function that receives a nonlocal goto must save all call-saved
681 if (current_function_has_nonlocal_label)
682 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
684 if (! call_used_regs[i] && ! fixed_regs[i])
685 regs_ever_live[i] = 1;
688 /* Find all the pseudo registers that didn't get hard regs
689 but do have known equivalent constants or memory slots.
690 These include parameters (known equivalent to parameter slots)
691 and cse'd or loop-moved constant memory addresses.
693 Record constant equivalents in reg_equiv_constant
694 so they will be substituted by find_reloads.
695 Record memory equivalents in reg_mem_equiv so they can
696 be substituted eventually by altering the REG-rtx's. */
698 reg_equiv_constant = (rtx *) xmalloc (max_regno * sizeof (rtx));
699 bzero ((char *) reg_equiv_constant, max_regno * sizeof (rtx));
700 reg_equiv_memory_loc = (rtx *) xmalloc (max_regno * sizeof (rtx));
701 bzero ((char *) reg_equiv_memory_loc, max_regno * sizeof (rtx));
702 reg_equiv_mem = (rtx *) xmalloc (max_regno * sizeof (rtx));
703 bzero ((char *) reg_equiv_mem, max_regno * sizeof (rtx));
704 reg_equiv_init = (rtx *) xmalloc (max_regno * sizeof (rtx));
705 bzero ((char *) reg_equiv_init, max_regno * sizeof (rtx));
706 reg_equiv_address = (rtx *) xmalloc (max_regno * sizeof (rtx));
707 bzero ((char *) reg_equiv_address, max_regno * sizeof (rtx));
708 reg_max_ref_width = (int *) xmalloc (max_regno * sizeof (int));
709 bzero ((char *) reg_max_ref_width, max_regno * sizeof (int));
711 if (SMALL_REGISTER_CLASSES)
712 CLEAR_HARD_REG_SET (forbidden_regs);
714 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
715 Also find all paradoxical subregs and find largest such for each pseudo.
716 On machines with small register classes, record hard registers that
717 are used for user variables. These can never be used for spills.
718 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
719 caller-saved registers must be marked live. */
721 for (insn = first; insn; insn = NEXT_INSN (insn))
723 rtx set = single_set (insn);
725 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
726 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
727 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
728 if (! call_used_regs[i])
729 regs_ever_live[i] = 1;
731 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
733 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
735 #ifdef LEGITIMATE_PIC_OPERAND_P
736 && (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic
737 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
741 rtx x = XEXP (note, 0);
742 i = REGNO (SET_DEST (set));
743 if (i > LAST_VIRTUAL_REGISTER)
745 if (GET_CODE (x) == MEM)
747 /* If the operand is a PLUS, the MEM may be shared,
748 so make sure we have an unshared copy here. */
749 if (GET_CODE (XEXP (x, 0)) == PLUS)
752 reg_equiv_memory_loc[i] = x;
754 else if (CONSTANT_P (x))
756 if (LEGITIMATE_CONSTANT_P (x))
757 reg_equiv_constant[i] = x;
759 reg_equiv_memory_loc[i]
760 = force_const_mem (GET_MODE (SET_DEST (set)), x);
765 /* If this register is being made equivalent to a MEM
766 and the MEM is not SET_SRC, the equivalencing insn
767 is one with the MEM as a SET_DEST and it occurs later.
768 So don't mark this insn now. */
769 if (GET_CODE (x) != MEM
770 || rtx_equal_p (SET_SRC (set), x))
771 reg_equiv_init[i] = insn;
776 /* If this insn is setting a MEM from a register equivalent to it,
777 this is the equivalencing insn. */
778 else if (set && GET_CODE (SET_DEST (set)) == MEM
779 && GET_CODE (SET_SRC (set)) == REG
780 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
781 && rtx_equal_p (SET_DEST (set),
782 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
783 reg_equiv_init[REGNO (SET_SRC (set))] = insn;
785 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
786 scan_paradoxical_subregs (PATTERN (insn));
791 num_labels = max_label_num () - get_first_label_num ();
793 /* Allocate the tables used to store offset information at labels. */
794 /* We used to use alloca here, but the size of what it would try to
795 allocate would occasionally cause it to exceed the stack limit and
796 cause a core dump. */
797 real_known_ptr = xmalloc (num_labels);
799 = (int (*)[NUM_ELIMINABLE_REGS])
800 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
802 offsets_known_at = real_known_ptr - get_first_label_num ();
804 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
806 /* Alter each pseudo-reg rtx to contain its hard reg number.
807 Assign stack slots to the pseudos that lack hard regs or equivalents.
808 Do not touch virtual registers. */
810 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
813 /* If we have some registers we think can be eliminated, scan all insns to
814 see if there is an insn that sets one of these registers to something
815 other than itself plus a constant. If so, the register cannot be
816 eliminated. Doing this scan here eliminates an extra pass through the
817 main reload loop in the most common case where register elimination
819 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
820 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
821 || GET_CODE (insn) == CALL_INSN)
822 note_stores (PATTERN (insn), mark_not_eliminable);
824 #ifndef REGISTER_CONSTRAINTS
825 /* If all the pseudo regs have hard regs,
826 except for those that are never referenced,
827 we know that no reloads are needed. */
828 /* But that is not true if there are register constraints, since
829 in that case some pseudos might be in the wrong kind of hard reg. */
831 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
832 if (reg_renumber[i] == -1 && REG_N_REFS (i) != 0)
835 if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
837 free (real_known_ptr);
839 free (reg_equiv_constant);
840 free (reg_equiv_memory_loc);
841 free (reg_equiv_mem);
842 free (reg_equiv_init);
843 free (reg_equiv_address);
844 free (reg_max_ref_width);
849 /* Compute the order of preference for hard registers to spill.
850 Store them by decreasing preference in potential_reload_regs. */
852 order_regs_for_reload ();
854 /* So far, no hard regs have been spilled. */
856 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
857 spill_reg_order[i] = -1;
859 /* Initialize to -1, which means take the first spill register. */
862 /* On most machines, we can't use any register explicitly used in the
863 rtl as a spill register. But on some, we have to. Those will have
864 taken care to keep the life of hard regs as short as possible. */
866 if (! SMALL_REGISTER_CLASSES)
867 COPY_HARD_REG_SET (forbidden_regs, bad_spill_regs);
869 /* Spill any hard regs that we know we can't eliminate. */
870 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
871 if (! ep->can_eliminate)
872 spill_hard_reg (ep->from, global, dumpfile, 1);
874 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
875 if (frame_pointer_needed)
876 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, global, dumpfile, 1);
880 for (i = 0; i < N_REG_CLASSES; i++)
882 basic_block_needs[i] = (char *) alloca (n_basic_blocks);
883 bzero (basic_block_needs[i], n_basic_blocks);
886 /* From now on, we need to emit any moves without making new pseudos. */
887 reload_in_progress = 1;
889 /* This loop scans the entire function each go-round
890 and repeats until one repetition spills no additional hard regs. */
892 /* This flag is set when a pseudo reg is spilled,
893 to require another pass. Note that getting an additional reload
894 reg does not necessarily imply any pseudo reg was spilled;
895 sometimes we find a reload reg that no pseudo reg was allocated in. */
896 something_changed = 1;
897 /* This flag is set if there are any insns that require reloading. */
898 something_needs_reloads = 0;
899 /* This flag is set if there are any insns that require register
901 something_needs_elimination = 0;
902 while (something_changed)
904 HOST_WIDE_INT starting_frame_size;
906 something_changed = 0;
907 bzero ((char *) max_needs, sizeof max_needs);
908 bzero ((char *) max_groups, sizeof max_groups);
909 bzero ((char *) max_nongroups, sizeof max_nongroups);
910 bzero ((char *) max_needs_insn, sizeof max_needs_insn);
911 bzero ((char *) max_groups_insn, sizeof max_groups_insn);
912 bzero ((char *) max_nongroups_insn, sizeof max_nongroups_insn);
913 bzero ((char *) group_size, sizeof group_size);
914 for (i = 0; i < N_REG_CLASSES; i++)
915 group_mode[i] = VOIDmode;
917 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done
918 here because the stack size may be a part of the offset computation
919 for register elimination, and there might have been new stack slots
920 created in the last iteration of this loop. */
921 assign_stack_local (BLKmode, 0, 0);
923 starting_frame_size = get_frame_size ();
925 set_initial_elim_offsets ();
927 /* For each pseudo register that has an equivalent location defined,
928 try to eliminate any eliminable registers (such as the frame pointer)
929 assuming initial offsets for the replacement register, which
932 If the resulting location is directly addressable, substitute
933 the MEM we just got directly for the old REG.
935 If it is not addressable but is a constant or the sum of a hard reg
936 and constant, it is probably not addressable because the constant is
937 out of range, in that case record the address; we will generate
938 hairy code to compute the address in a register each time it is
939 needed. Similarly if it is a hard register, but one that is not
940 valid as an address register.
942 If the location is not addressable, but does not have one of the
943 above forms, assign a stack slot. We have to do this to avoid the
944 potential of producing lots of reloads if, e.g., a location involves
945 a pseudo that didn't get a hard register and has an equivalent memory
946 location that also involves a pseudo that didn't get a hard register.
948 Perhaps at some point we will improve reload_when_needed handling
949 so this problem goes away. But that's very hairy. */
951 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
952 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
954 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
956 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
958 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
959 else if (CONSTANT_P (XEXP (x, 0))
960 || (GET_CODE (XEXP (x, 0)) == REG
961 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
962 || (GET_CODE (XEXP (x, 0)) == PLUS
963 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
964 && (REGNO (XEXP (XEXP (x, 0), 0))
965 < FIRST_PSEUDO_REGISTER)
966 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
967 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
970 /* Make a new stack slot. Then indicate that something
971 changed so we go back and recompute offsets for
972 eliminable registers because the allocation of memory
973 below might change some offset. reg_equiv_{mem,address}
974 will be set up for this pseudo on the next pass around
976 reg_equiv_memory_loc[i] = 0;
977 reg_equiv_init[i] = 0;
979 something_changed = 1;
983 /* Insert code to save and restore call-clobbered hard regs
984 around calls. Tell if what mode to use so that we will process
985 those insns in reload_as_needed if we have to. */
987 if (caller_save_needed)
990 if (starting_frame_size != get_frame_size ())
991 something_changed = 1;
993 /* If we allocated another pseudo to the stack, redo elimination
995 if (something_changed)
998 if (caller_save_needed)
1000 save_call_clobbered_regs ();
1001 /* That might have allocated new insn_chain structures. */
1002 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1005 something_changed |= calculate_needs_all_insns (first, global);
1007 /* If we allocated any new memory locations, make another pass
1008 since it might have changed elimination offsets. */
1009 if (starting_frame_size != get_frame_size ())
1010 something_changed = 1;
1013 dump_needs (dumpfile);
1016 HARD_REG_SET to_spill;
1017 CLEAR_HARD_REG_SET (to_spill);
1018 update_eliminables (&to_spill);
1019 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1020 if (TEST_HARD_REG_BIT (to_spill, i))
1022 spill_hard_reg (i, global, dumpfile, 1);
1023 something_changed = 1;
1027 /* If all needs are met, we win. */
1029 for (i = 0; i < N_REG_CLASSES; i++)
1030 if (max_needs[i] > 0 || max_groups[i] > 0 || max_nongroups[i] > 0)
1032 if (i == N_REG_CLASSES && ! something_changed)
1035 /* Not all needs are met; must spill some hard regs. */
1037 /* Put all registers spilled so far back in potential_reload_regs, but
1038 put them at the front, since we've already spilled most of the
1039 pseudos in them (we might have left some pseudos unspilled if they
1040 were in a block that didn't need any spill registers of a conflicting
1041 class. We used to try to mark off the need for those registers,
1042 but doing so properly is very complex and reallocating them is the
1043 simpler approach. First, "pack" potential_reload_regs by pushing
1044 any nonnegative entries towards the end. That will leave room
1045 for the registers we already spilled.
1047 Also, undo the marking of the spill registers from the last time
1048 around in FORBIDDEN_REGS since we will be probably be allocating
1051 ??? It is theoretically possible that we might end up not using one
1052 of our previously-spilled registers in this allocation, even though
1053 they are at the head of the list. It's not clear what to do about
1054 this, but it was no better before, when we marked off the needs met
1055 by the previously-spilled registers. With the current code, globals
1056 can be allocated into these registers, but locals cannot. */
1060 for (i = j = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
1061 if (potential_reload_regs[i] != -1)
1062 potential_reload_regs[j--] = potential_reload_regs[i];
1064 for (i = 0; i < n_spills; i++)
1066 potential_reload_regs[i] = spill_regs[i];
1067 spill_reg_order[spill_regs[i]] = -1;
1068 CLEAR_HARD_REG_BIT (forbidden_regs, spill_regs[i]);
1074 something_changed |= find_reload_regs (global, dumpfile);
1078 if (something_changed)
1079 delete_caller_save_insns (first);
1082 /* If global-alloc was run, notify it of any register eliminations we have
1085 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1086 if (ep->can_eliminate)
1087 mark_elimination (ep->from, ep->to);
1089 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1090 If that insn didn't set the register (i.e., it copied the register to
1091 memory), just delete that insn instead of the equivalencing insn plus
1092 anything now dead. If we call delete_dead_insn on that insn, we may
1093 delete the insn that actually sets the register if the register die
1094 there and that is incorrect. */
1096 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1097 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0
1098 && GET_CODE (reg_equiv_init[i]) != NOTE)
1100 if (reg_set_p (regno_reg_rtx[i], PATTERN (reg_equiv_init[i])))
1101 delete_dead_insn (reg_equiv_init[i]);
1104 PUT_CODE (reg_equiv_init[i], NOTE);
1105 NOTE_SOURCE_FILE (reg_equiv_init[i]) = 0;
1106 NOTE_LINE_NUMBER (reg_equiv_init[i]) = NOTE_INSN_DELETED;
1110 /* Use the reload registers where necessary
1111 by generating move instructions to move the must-be-register
1112 values into or out of the reload registers. */
1114 if (something_needs_reloads || something_needs_elimination)
1115 reload_as_needed (first, global);
1117 /* If we were able to eliminate the frame pointer, show that it is no
1118 longer live at the start of any basic block. If it ls live by
1119 virtue of being in a pseudo, that pseudo will be marked live
1120 and hence the frame pointer will be known to be live via that
1123 if (! frame_pointer_needed)
1124 for (i = 0; i < n_basic_blocks; i++)
1125 CLEAR_REGNO_REG_SET (basic_block_live_at_start[i],
1126 HARD_FRAME_POINTER_REGNUM);
1128 /* Come here (with failure set nonzero) if we can't get enough spill regs
1129 and we decide not to abort about it. */
1132 reload_in_progress = 0;
1134 /* Now eliminate all pseudo regs by modifying them into
1135 their equivalent memory references.
1136 The REG-rtx's for the pseudos are modified in place,
1137 so all insns that used to refer to them now refer to memory.
1139 For a reg that has a reg_equiv_address, all those insns
1140 were changed by reloading so that no insns refer to it any longer;
1141 but the DECL_RTL of a variable decl may refer to it,
1142 and if so this causes the debugging info to mention the variable. */
1144 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1148 int is_readonly = 0;
1150 if (reg_equiv_memory_loc[i])
1152 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1153 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1156 if (reg_equiv_mem[i])
1157 addr = XEXP (reg_equiv_mem[i], 0);
1159 if (reg_equiv_address[i])
1160 addr = reg_equiv_address[i];
1164 if (reg_renumber[i] < 0)
1166 rtx reg = regno_reg_rtx[i];
1167 XEXP (reg, 0) = addr;
1168 REG_USERVAR_P (reg) = 0;
1169 RTX_UNCHANGING_P (reg) = is_readonly;
1170 MEM_IN_STRUCT_P (reg) = in_struct;
1171 /* We have no alias information about this newly created
1173 MEM_ALIAS_SET (reg) = 0;
1174 PUT_CODE (reg, MEM);
1176 else if (reg_equiv_mem[i])
1177 XEXP (reg_equiv_mem[i], 0) = addr;
1181 /* Make a pass over all the insns and delete all USEs which we inserted
1182 only to tag a REG_EQUAL note on them; if PRESERVE_DEATH_INFO_REGNO_P
1183 is defined, also remove death notes for things that are no longer
1184 registers or no longer die in the insn (e.g., an input and output
1185 pseudo being tied). */
1187 for (insn = first; insn; insn = NEXT_INSN (insn))
1188 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1190 #ifdef PRESERVE_DEATH_INFO_REGNO_P
1194 if (GET_CODE (PATTERN (insn)) == USE
1195 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1197 PUT_CODE (insn, NOTE);
1198 NOTE_SOURCE_FILE (insn) = 0;
1199 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1202 #ifdef PRESERVE_DEATH_INFO_REGNO_P
1203 for (note = REG_NOTES (insn); note; note = next)
1205 next = XEXP (note, 1);
1206 if (REG_NOTE_KIND (note) == REG_DEAD
1207 && (GET_CODE (XEXP (note, 0)) != REG
1208 || reg_set_p (XEXP (note, 0), PATTERN (insn))))
1209 remove_note (insn, note);
1214 /* If we are doing stack checking, give a warning if this function's
1215 frame size is larger than we expect. */
1216 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1218 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1220 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1221 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1222 size += UNITS_PER_WORD;
1224 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1225 warning ("frame size too large for reliable stack checking");
1228 obstack_free (&reload_obstack, reload_startobj);
1230 /* Indicate that we no longer have known memory locations or constants. */
1231 if (reg_equiv_constant)
1232 free (reg_equiv_constant);
1233 reg_equiv_constant = 0;
1234 if (reg_equiv_memory_loc)
1235 free (reg_equiv_memory_loc);
1236 reg_equiv_memory_loc = 0;
1239 free (real_known_ptr);
1243 free (reg_equiv_mem);
1244 free (reg_equiv_init);
1245 free (reg_equiv_address);
1246 free (reg_max_ref_width);
1248 CLEAR_HARD_REG_SET (used_spill_regs);
1249 for (i = 0; i < n_spills; i++)
1250 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1255 /* Walk the insns of the current function, starting with FIRST, and collect
1256 information about the need to do register elimination and the need to
1259 calculate_needs_all_insns (first, global)
1264 int something_changed = 0;
1266 /* Keep track of which basic blocks are needing the reloads. */
1269 /* Compute the most additional registers needed by any instruction.
1270 Collect information separately for each class of regs. */
1272 for (insn = first; insn; insn = NEXT_INSN (insn))
1274 if (global && this_block + 1 < n_basic_blocks
1275 && insn == basic_block_head[this_block+1])
1278 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which
1279 might include REG_LABEL), we need to see what effects this
1280 has on the known offsets at labels. */
1282 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1283 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1284 && REG_NOTES (insn) != 0))
1285 set_label_offsets (insn, insn, 0);
1287 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1289 rtx old_body = PATTERN (insn);
1290 int old_code = INSN_CODE (insn);
1291 rtx old_notes = REG_NOTES (insn);
1292 int did_elimination = 0;
1294 /* Nonzero means don't use a reload reg that overlaps
1295 the place where a function value can be returned. */
1296 rtx avoid_return_reg = 0;
1298 /* Set avoid_return_reg if this is an insn
1299 that might use the value of a function call. */
1300 if (SMALL_REGISTER_CLASSES && GET_CODE (insn) == CALL_INSN)
1302 if (GET_CODE (PATTERN (insn)) == SET)
1303 after_call = SET_DEST (PATTERN (insn));
1304 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1305 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1306 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
1310 else if (SMALL_REGISTER_CLASSES && after_call != 0
1311 && !(GET_CODE (PATTERN (insn)) == SET
1312 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx)
1313 && GET_CODE (PATTERN (insn)) != USE)
1315 if (reg_referenced_p (after_call, PATTERN (insn)))
1316 avoid_return_reg = after_call;
1320 /* If needed, eliminate any eliminable registers. */
1322 did_elimination = eliminate_regs_in_insn (insn, 0);
1324 /* Analyze the instruction. */
1325 find_reloads (insn, 0, spill_indirect_levels, global,
1328 /* Remember for later shortcuts which insns had any reloads or
1329 register eliminations.
1331 One might think that it would be worthwhile to mark insns
1332 that need register replacements but not reloads, but this is
1333 not safe because find_reloads may do some manipulation of
1334 the insn (such as swapping commutative operands), which would
1335 be lost when we restore the old pattern after register
1336 replacement. So the actions of find_reloads must be redone in
1337 subsequent passes or in reload_as_needed.
1339 However, it is safe to mark insns that need reloads
1340 but not register replacement. */
1342 PUT_MODE (insn, (did_elimination ? QImode
1343 : n_reloads ? HImode
1344 : GET_MODE (insn) == DImode ? DImode
1347 /* Discard any register replacements done. */
1348 if (did_elimination)
1350 obstack_free (&reload_obstack, reload_firstobj);
1351 PATTERN (insn) = old_body;
1352 INSN_CODE (insn) = old_code;
1353 REG_NOTES (insn) = old_notes;
1354 something_needs_elimination = 1;
1358 something_changed |= calculate_needs (this_block, insn,
1359 avoid_return_reg, global);
1362 /* Note that there is a continue statement above. */
1364 return something_changed;
1367 /* To compute the number of reload registers of each class
1368 needed for an insn, we must simulate what choose_reload_regs
1369 can do. We do this by splitting an insn into an "input" and
1370 an "output" part. RELOAD_OTHER reloads are used in both.
1371 The input part uses those reloads, RELOAD_FOR_INPUT reloads,
1372 which must be live over the entire input section of reloads,
1373 and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
1374 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the
1377 The registers needed for output are RELOAD_OTHER and
1378 RELOAD_FOR_OUTPUT, which are live for the entire output
1379 portion, and the maximum of all the RELOAD_FOR_OUTPUT_ADDRESS
1380 reloads for each operand.
1382 The total number of registers needed is the maximum of the
1383 inputs and outputs. */
1386 calculate_needs (this_block, insn, avoid_return_reg, global)
1388 rtx insn, avoid_return_reg;
1391 int something_changed = 0;
1396 /* [0] is normal, [1] is nongroup. */
1397 int regs[2][N_REG_CLASSES];
1398 int groups[N_REG_CLASSES];
1401 /* Each `struct needs' corresponds to one RELOAD_... type. */
1405 struct needs output;
1407 struct needs other_addr;
1408 struct needs op_addr;
1409 struct needs op_addr_reload;
1410 struct needs in_addr[MAX_RECOG_OPERANDS];
1411 struct needs in_addr_addr[MAX_RECOG_OPERANDS];
1412 struct needs out_addr[MAX_RECOG_OPERANDS];
1413 struct needs out_addr_addr[MAX_RECOG_OPERANDS];
1416 something_needs_reloads = 1;
1417 bzero ((char *) &insn_needs, sizeof insn_needs);
1419 /* Count each reload once in every class
1420 containing the reload's own class. */
1422 for (i = 0; i < n_reloads; i++)
1424 register enum reg_class *p;
1425 enum reg_class class = reload_reg_class[i];
1427 enum machine_mode mode;
1428 struct needs *this_needs;
1430 /* Don't count the dummy reloads, for which one of the
1431 regs mentioned in the insn can be used for reloading.
1432 Don't count optional reloads.
1433 Don't count reloads that got combined with others. */
1434 if (reload_reg_rtx[i] != 0
1435 || reload_optional[i] != 0
1436 || (reload_out[i] == 0 && reload_in[i] == 0
1437 && ! reload_secondary_p[i]))
1440 /* Show that a reload register of this class is needed
1441 in this basic block. We do not use insn_needs and
1442 insn_groups because they are overly conservative for
1444 if (global && ! basic_block_needs[(int) class][this_block])
1446 basic_block_needs[(int) class][this_block] = 1;
1447 something_changed = 1;
1450 mode = reload_inmode[i];
1451 if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1452 mode = reload_outmode[i];
1453 size = CLASS_MAX_NREGS (class, mode);
1455 /* Decide which time-of-use to count this reload for. */
1456 switch (reload_when_needed[i])
1459 this_needs = &insn_needs.other;
1461 case RELOAD_FOR_INPUT:
1462 this_needs = &insn_needs.input;
1464 case RELOAD_FOR_OUTPUT:
1465 this_needs = &insn_needs.output;
1467 case RELOAD_FOR_INSN:
1468 this_needs = &insn_needs.insn;
1470 case RELOAD_FOR_OTHER_ADDRESS:
1471 this_needs = &insn_needs.other_addr;
1473 case RELOAD_FOR_INPUT_ADDRESS:
1474 this_needs = &insn_needs.in_addr[reload_opnum[i]];
1476 case RELOAD_FOR_INPADDR_ADDRESS:
1477 this_needs = &insn_needs.in_addr_addr[reload_opnum[i]];
1479 case RELOAD_FOR_OUTPUT_ADDRESS:
1480 this_needs = &insn_needs.out_addr[reload_opnum[i]];
1482 case RELOAD_FOR_OUTADDR_ADDRESS:
1483 this_needs = &insn_needs.out_addr_addr[reload_opnum[i]];
1485 case RELOAD_FOR_OPERAND_ADDRESS:
1486 this_needs = &insn_needs.op_addr;
1488 case RELOAD_FOR_OPADDR_ADDR:
1489 this_needs = &insn_needs.op_addr_reload;
1495 enum machine_mode other_mode, allocate_mode;
1497 /* Count number of groups needed separately from
1498 number of individual regs needed. */
1499 this_needs->groups[(int) class]++;
1500 p = reg_class_superclasses[(int) class];
1501 while (*p != LIM_REG_CLASSES)
1502 this_needs->groups[(int) *p++]++;
1504 /* Record size and mode of a group of this class. */
1505 /* If more than one size group is needed,
1506 make all groups the largest needed size. */
1507 if (group_size[(int) class] < size)
1509 other_mode = group_mode[(int) class];
1510 allocate_mode = mode;
1512 group_size[(int) class] = size;
1513 group_mode[(int) class] = mode;
1518 allocate_mode = group_mode[(int) class];
1521 /* Crash if two dissimilar machine modes both need
1522 groups of consecutive regs of the same class. */
1524 if (other_mode != VOIDmode && other_mode != allocate_mode
1525 && ! modes_equiv_for_class_p (allocate_mode,
1527 fatal_insn ("Two dissimilar machine modes both need groups of consecutive regs of the same class",
1532 this_needs->regs[reload_nongroup[i]][(int) class] += 1;
1533 p = reg_class_superclasses[(int) class];
1534 while (*p != LIM_REG_CLASSES)
1535 this_needs->regs[reload_nongroup[i]][(int) *p++] += 1;
1541 /* All reloads have been counted for this insn;
1542 now merge the various times of use.
1543 This sets insn_needs, etc., to the maximum total number
1544 of registers needed at any point in this insn. */
1546 for (i = 0; i < N_REG_CLASSES; i++)
1548 int j, in_max, out_max;
1550 /* Compute normal and nongroup needs. */
1551 for (j = 0; j <= 1; j++)
1554 for (in_max = 0, out_max = 0, k = 0; k < reload_n_operands; k++)
1556 in_max = MAX (in_max,
1557 (insn_needs.in_addr[k].regs[j][i]
1558 + insn_needs.in_addr_addr[k].regs[j][i]));
1559 out_max = MAX (out_max, insn_needs.out_addr[k].regs[j][i]);
1560 out_max = MAX (out_max,
1561 insn_needs.out_addr_addr[k].regs[j][i]);
1564 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1565 and operand addresses but not things used to reload
1566 them. Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads
1567 don't conflict with things needed to reload inputs or
1570 in_max = MAX (MAX (insn_needs.op_addr.regs[j][i],
1571 insn_needs.op_addr_reload.regs[j][i]),
1574 out_max = MAX (out_max, insn_needs.insn.regs[j][i]);
1576 insn_needs.input.regs[j][i]
1577 = MAX (insn_needs.input.regs[j][i]
1578 + insn_needs.op_addr.regs[j][i]
1579 + insn_needs.insn.regs[j][i],
1580 in_max + insn_needs.input.regs[j][i]);
1582 insn_needs.output.regs[j][i] += out_max;
1583 insn_needs.other.regs[j][i]
1584 += MAX (MAX (insn_needs.input.regs[j][i],
1585 insn_needs.output.regs[j][i]),
1586 insn_needs.other_addr.regs[j][i]);
1590 /* Now compute group needs. */
1591 for (in_max = 0, out_max = 0, j = 0; j < reload_n_operands; j++)
1593 in_max = MAX (in_max, insn_needs.in_addr[j].groups[i]);
1594 in_max = MAX (in_max, insn_needs.in_addr_addr[j].groups[i]);
1595 out_max = MAX (out_max, insn_needs.out_addr[j].groups[i]);
1596 out_max = MAX (out_max, insn_needs.out_addr_addr[j].groups[i]);
1599 in_max = MAX (MAX (insn_needs.op_addr.groups[i],
1600 insn_needs.op_addr_reload.groups[i]),
1602 out_max = MAX (out_max, insn_needs.insn.groups[i]);
1604 insn_needs.input.groups[i]
1605 = MAX (insn_needs.input.groups[i]
1606 + insn_needs.op_addr.groups[i]
1607 + insn_needs.insn.groups[i],
1608 in_max + insn_needs.input.groups[i]);
1610 insn_needs.output.groups[i] += out_max;
1611 insn_needs.other.groups[i]
1612 += MAX (MAX (insn_needs.input.groups[i],
1613 insn_needs.output.groups[i]),
1614 insn_needs.other_addr.groups[i]);
1617 /* If this insn stores the value of a function call,
1618 and that value is in a register that has been spilled,
1619 and if the insn needs a reload in a class
1620 that might use that register as the reload register,
1621 then add an extra need in that class.
1622 This makes sure we have a register available that does
1623 not overlap the return value. */
1625 if (SMALL_REGISTER_CLASSES && avoid_return_reg)
1627 int regno = REGNO (avoid_return_reg);
1629 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
1631 int basic_needs[N_REG_CLASSES], basic_groups[N_REG_CLASSES];
1633 /* First compute the "basic needs", which counts a
1634 need only in the smallest class in which it
1637 bcopy ((char *) insn_needs.other.regs[0],
1638 (char *) basic_needs, sizeof basic_needs);
1639 bcopy ((char *) insn_needs.other.groups,
1640 (char *) basic_groups, sizeof basic_groups);
1642 for (i = 0; i < N_REG_CLASSES; i++)
1646 if (basic_needs[i] >= 0)
1647 for (p = reg_class_superclasses[i];
1648 *p != LIM_REG_CLASSES; p++)
1649 basic_needs[(int) *p] -= basic_needs[i];
1651 if (basic_groups[i] >= 0)
1652 for (p = reg_class_superclasses[i];
1653 *p != LIM_REG_CLASSES; p++)
1654 basic_groups[(int) *p] -= basic_groups[i];
1657 /* Now count extra regs if there might be a conflict with
1658 the return value register. */
1660 for (r = regno; r < regno + nregs; r++)
1661 if (spill_reg_order[r] >= 0)
1662 for (i = 0; i < N_REG_CLASSES; i++)
1663 if (TEST_HARD_REG_BIT (reg_class_contents[i], r))
1665 if (basic_needs[i] > 0)
1669 insn_needs.other.regs[0][i]++;
1670 p = reg_class_superclasses[i];
1671 while (*p != LIM_REG_CLASSES)
1672 insn_needs.other.regs[0][(int) *p++]++;
1674 if (basic_groups[i] > 0)
1678 insn_needs.other.groups[i]++;
1679 p = reg_class_superclasses[i];
1680 while (*p != LIM_REG_CLASSES)
1681 insn_needs.other.groups[(int) *p++]++;
1686 /* For each class, collect maximum need of any insn. */
1688 for (i = 0; i < N_REG_CLASSES; i++)
1690 if (max_needs[i] < insn_needs.other.regs[0][i])
1692 max_needs[i] = insn_needs.other.regs[0][i];
1693 max_needs_insn[i] = insn;
1695 if (max_groups[i] < insn_needs.other.groups[i])
1697 max_groups[i] = insn_needs.other.groups[i];
1698 max_groups_insn[i] = insn;
1700 if (max_nongroups[i] < insn_needs.other.regs[1][i])
1702 max_nongroups[i] = insn_needs.other.regs[1][i];
1703 max_nongroups_insn[i] = insn;
1706 return something_changed;
1709 /* Find a group of exactly 2 registers.
1711 First try to fill out the group by spilling a single register which
1712 would allow completion of the group.
1714 Then try to create a new group from a pair of registers, neither of
1715 which are explicitly used.
1717 Then try to create a group from any pair of registers. */
1719 find_tworeg_group (global, class, dumpfile)
1725 /* First, look for a register that will complete a group. */
1726 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1730 j = potential_reload_regs[i];
1731 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1732 && ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1733 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1734 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1735 && HARD_REGNO_MODE_OK (other, group_mode[class])
1736 && ! TEST_HARD_REG_BIT (counted_for_nongroups, other)
1737 /* We don't want one part of another group.
1738 We could get "two groups" that overlap! */
1739 && ! TEST_HARD_REG_BIT (counted_for_groups, other))
1740 || (j < FIRST_PSEUDO_REGISTER - 1
1741 && (other = j + 1, spill_reg_order[other] >= 0)
1742 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1743 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1744 && HARD_REGNO_MODE_OK (j, group_mode[class])
1745 && ! TEST_HARD_REG_BIT (counted_for_nongroups, other)
1746 && ! TEST_HARD_REG_BIT (counted_for_groups, other))))
1748 register enum reg_class *p;
1750 /* We have found one that will complete a group,
1751 so count off one group as provided. */
1752 max_groups[class]--;
1753 p = reg_class_superclasses[class];
1754 while (*p != LIM_REG_CLASSES)
1756 if (group_size [(int) *p] <= group_size [class])
1757 max_groups[(int) *p]--;
1761 /* Indicate both these regs are part of a group. */
1762 SET_HARD_REG_BIT (counted_for_groups, j);
1763 SET_HARD_REG_BIT (counted_for_groups, other);
1767 /* We can't complete a group, so start one. */
1768 /* Look for a pair neither of which is explicitly used. */
1769 if (SMALL_REGISTER_CLASSES && i == FIRST_PSEUDO_REGISTER)
1770 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1773 j = potential_reload_regs[i];
1774 /* Verify that J+1 is a potential reload reg. */
1775 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1776 if (potential_reload_regs[k] == j + 1)
1778 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1779 && k < FIRST_PSEUDO_REGISTER
1780 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1781 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1782 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1783 && HARD_REGNO_MODE_OK (j, group_mode[class])
1784 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1786 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1)
1787 /* Reject J at this stage
1788 if J+1 was explicitly used. */
1789 && ! regs_explicitly_used[j + 1])
1792 /* Now try any group at all
1793 whose registers are not in bad_spill_regs. */
1794 if (i == FIRST_PSEUDO_REGISTER)
1795 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1798 j = potential_reload_regs[i];
1799 /* Verify that J+1 is a potential reload reg. */
1800 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1801 if (potential_reload_regs[k] == j + 1)
1803 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1804 && k < FIRST_PSEUDO_REGISTER
1805 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1806 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1807 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1808 && HARD_REGNO_MODE_OK (j, group_mode[class])
1809 && ! TEST_HARD_REG_BIT (counted_for_nongroups, j + 1)
1810 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1))
1814 /* I should be the index in potential_reload_regs
1815 of the new reload reg we have found. */
1817 if (i < FIRST_PSEUDO_REGISTER)
1818 return new_spill_reg (i, class, max_needs, NULL_PTR,
1821 /* There are no groups left to spill. */
1822 spill_failure (max_groups_insn[class]);
1827 /* Find a group of more than 2 registers.
1828 Look for a sufficient sequence of unspilled registers, and spill them all
1831 find_group (global, class, dumpfile)
1836 int something_changed = 0;
1839 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1843 j = potential_reload_regs[i];
1845 && j + group_size[class] <= FIRST_PSEUDO_REGISTER
1846 && HARD_REGNO_MODE_OK (j, group_mode[class]))
1848 /* Check each reg in the sequence. */
1849 for (k = 0; k < group_size[class]; k++)
1850 if (! (spill_reg_order[j + k] < 0
1851 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1852 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1854 /* We got a full sequence, so spill them all. */
1855 if (k == group_size[class])
1857 register enum reg_class *p;
1858 for (k = 0; k < group_size[class]; k++)
1861 SET_HARD_REG_BIT (counted_for_groups, j + k);
1862 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1863 if (potential_reload_regs[idx] == j + k)
1865 something_changed |= new_spill_reg (idx, class, max_needs,
1870 /* We have found one that will complete a group,
1871 so count off one group as provided. */
1872 max_groups[class]--;
1873 p = reg_class_superclasses[class];
1874 while (*p != LIM_REG_CLASSES)
1876 if (group_size [(int) *p]
1877 <= group_size [class])
1878 max_groups[(int) *p]--;
1881 return something_changed;
1885 /* There are no groups left. */
1886 spill_failure (max_groups_insn[class]);
1891 /* Find more reload regs to satisfy the remaining need.
1892 Do it by ascending class number, since otherwise a reg
1893 might be spilled for a big class and might fail to count
1894 for a smaller class even though it belongs to that class.
1896 Count spilled regs in `spills', and add entries to
1897 `spill_regs' and `spill_reg_order'.
1899 ??? Note there is a problem here.
1900 When there is a need for a group in a high-numbered class,
1901 and also need for non-group regs that come from a lower class,
1902 the non-group regs are chosen first. If there aren't many regs,
1903 they might leave no room for a group.
1905 This was happening on the 386. To fix it, we added the code
1906 that calls possible_group_p, so that the lower class won't
1907 break up the last possible group.
1909 Really fixing the problem would require changes above
1910 in counting the regs already spilled, and in choose_reload_regs.
1911 It might be hard to avoid introducing bugs there. */
1914 find_reload_regs (global, dumpfile)
1919 int something_changed = 0;
1921 CLEAR_HARD_REG_SET (counted_for_groups);
1922 CLEAR_HARD_REG_SET (counted_for_nongroups);
1924 for (class = 0; class < N_REG_CLASSES; class++)
1926 /* First get the groups of registers.
1927 If we got single registers first, we might fragment
1929 while (max_groups[class] > 0)
1931 /* If any single spilled regs happen to form groups,
1932 count them now. Maybe we don't really need
1933 to spill another group. */
1934 count_possible_groups (group_size, group_mode, max_groups, class);
1936 if (max_groups[class] <= 0)
1939 /* Groups of size 2 (the only groups used on most machines)
1940 are treated specially. */
1941 if (group_size[class] == 2)
1942 something_changed |= find_tworeg_group (global, class, dumpfile);
1944 something_changed |= find_group (global, class, dumpfile);
1950 /* Now similarly satisfy all need for single registers. */
1952 while (max_needs[class] > 0 || max_nongroups[class] > 0)
1955 /* If we spilled enough regs, but they weren't counted
1956 against the non-group need, see if we can count them now.
1957 If so, we can avoid some actual spilling. */
1958 if (max_needs[class] <= 0 && max_nongroups[class] > 0)
1959 for (i = 0; i < n_spills; i++)
1961 int regno = spill_regs[i];
1962 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1963 && !TEST_HARD_REG_BIT (counted_for_groups, regno)
1964 && !TEST_HARD_REG_BIT (counted_for_nongroups, regno)
1965 && max_nongroups[class] > 0)
1967 register enum reg_class *p;
1969 SET_HARD_REG_BIT (counted_for_nongroups, regno);
1970 max_nongroups[class]--;
1971 p = reg_class_superclasses[class];
1972 while (*p != LIM_REG_CLASSES)
1973 max_nongroups[(int) *p++]--;
1976 if (max_needs[class] <= 0 && max_nongroups[class] <= 0)
1979 /* Consider the potential reload regs that aren't
1980 yet in use as reload regs, in order of preference.
1981 Find the most preferred one that's in this class. */
1983 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1985 int regno = potential_reload_regs[i];
1987 && TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1988 /* If this reg will not be available for groups,
1989 pick one that does not foreclose possible groups.
1990 This is a kludge, and not very general,
1991 but it should be sufficient to make the 386 work,
1992 and the problem should not occur on machines with
1994 && (max_nongroups[class] == 0
1995 || possible_group_p (regno, max_groups)))
1999 /* If we couldn't get a register, try to get one even if we
2000 might foreclose possible groups. This may cause problems
2001 later, but that's better than aborting now, since it is
2002 possible that we will, in fact, be able to form the needed
2003 group even with this allocation. */
2005 if (i >= FIRST_PSEUDO_REGISTER
2006 && (asm_noperands (max_needs[class] > 0
2007 ? max_needs_insn[class]
2008 : max_nongroups_insn[class])
2010 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2011 if (potential_reload_regs[i] >= 0
2012 && TEST_HARD_REG_BIT (reg_class_contents[class],
2013 potential_reload_regs[i]))
2016 /* I should be the index in potential_reload_regs
2017 of the new reload reg we have found. */
2019 if (i >= FIRST_PSEUDO_REGISTER)
2021 /* There are no possible registers left to spill. */
2022 spill_failure (max_needs[class] > 0 ? max_needs_insn[class]
2023 : max_nongroups_insn[class]);
2028 something_changed |= new_spill_reg (i, class, max_needs,
2029 max_nongroups, global,
2033 return something_changed;
2037 dump_needs (dumpfile)
2040 static char *reg_class_names[] = REG_CLASS_NAMES;
2043 for (i = 0; i < N_REG_CLASSES; i++)
2045 if (max_needs[i] > 0)
2047 ";; Need %d reg%s of class %s (for insn %d).\n",
2048 max_needs[i], max_needs[i] == 1 ? "" : "s",
2049 reg_class_names[i], INSN_UID (max_needs_insn[i]));
2050 if (max_nongroups[i] > 0)
2052 ";; Need %d nongroup reg%s of class %s (for insn %d).\n",
2053 max_nongroups[i], max_nongroups[i] == 1 ? "" : "s",
2054 reg_class_names[i], INSN_UID (max_nongroups_insn[i]));
2055 if (max_groups[i] > 0)
2057 ";; Need %d group%s (%smode) of class %s (for insn %d).\n",
2058 max_groups[i], max_groups[i] == 1 ? "" : "s",
2059 mode_name[(int) group_mode[i]],
2060 reg_class_names[i], INSN_UID (max_groups_insn[i]));
2064 /* Delete all insns that were inserted by emit_caller_save_insns during
2067 delete_caller_save_insns (first)
2075 if (b + 1 != n_basic_blocks
2076 && basic_block_head[b + 1] == insn)
2079 while (insn != 0 && INSN_UID (insn) >= reload_first_uid)
2081 rtx next = NEXT_INSN (insn);
2082 rtx prev = PREV_INSN (insn);
2084 if (insn == basic_block_head[b])
2085 basic_block_head[b] = next;
2086 if (insn == basic_block_end[b])
2087 basic_block_end[b] = prev;
2090 PREV_INSN (next) = prev;
2092 NEXT_INSN (prev) = next;
2096 if (b + 1 != n_basic_blocks
2097 && basic_block_head[b + 1] == insn)
2101 insn = NEXT_INSN (insn);
2105 /* Nonzero if, after spilling reg REGNO for non-groups,
2106 it will still be possible to find a group if we still need one. */
2109 possible_group_p (regno, max_groups)
2114 int class = (int) NO_REGS;
2116 for (i = 0; i < (int) N_REG_CLASSES; i++)
2117 if (max_groups[i] > 0)
2123 if (class == (int) NO_REGS)
2126 /* Consider each pair of consecutive registers. */
2127 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
2129 /* Ignore pairs that include reg REGNO. */
2130 if (i == regno || i + 1 == regno)
2133 /* Ignore pairs that are outside the class that needs the group.
2134 ??? Here we fail to handle the case where two different classes
2135 independently need groups. But this never happens with our
2136 current machine descriptions. */
2137 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
2138 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
2141 /* A pair of consecutive regs we can still spill does the trick. */
2142 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
2143 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2144 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
2147 /* A pair of one already spilled and one we can spill does it
2148 provided the one already spilled is not otherwise reserved. */
2149 if (spill_reg_order[i] < 0
2150 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2151 && spill_reg_order[i + 1] >= 0
2152 && ! TEST_HARD_REG_BIT (counted_for_groups, i + 1)
2153 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i + 1))
2155 if (spill_reg_order[i + 1] < 0
2156 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
2157 && spill_reg_order[i] >= 0
2158 && ! TEST_HARD_REG_BIT (counted_for_groups, i)
2159 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i))
2166 /* Count any groups of CLASS that can be formed from the registers recently
2170 count_possible_groups (group_size, group_mode, max_groups, class)
2172 enum machine_mode *group_mode;
2179 /* Now find all consecutive groups of spilled registers
2180 and mark each group off against the need for such groups.
2181 But don't count them against ordinary need, yet. */
2183 if (group_size[class] == 0)
2186 CLEAR_HARD_REG_SET (new);
2188 /* Make a mask of all the regs that are spill regs in class I. */
2189 for (i = 0; i < n_spills; i++)
2190 if (TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
2191 && ! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[i])
2192 && ! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
2193 SET_HARD_REG_BIT (new, spill_regs[i]);
2195 /* Find each consecutive group of them. */
2196 for (i = 0; i < FIRST_PSEUDO_REGISTER && max_groups[class] > 0; i++)
2197 if (TEST_HARD_REG_BIT (new, i)
2198 && i + group_size[class] <= FIRST_PSEUDO_REGISTER
2199 && HARD_REGNO_MODE_OK (i, group_mode[class]))
2201 for (j = 1; j < group_size[class]; j++)
2202 if (! TEST_HARD_REG_BIT (new, i + j))
2205 if (j == group_size[class])
2207 /* We found a group. Mark it off against this class's need for
2208 groups, and against each superclass too. */
2209 register enum reg_class *p;
2211 max_groups[class]--;
2212 p = reg_class_superclasses[class];
2213 while (*p != LIM_REG_CLASSES)
2215 if (group_size [(int) *p] <= group_size [class])
2216 max_groups[(int) *p]--;
2220 /* Don't count these registers again. */
2221 for (j = 0; j < group_size[class]; j++)
2222 SET_HARD_REG_BIT (counted_for_groups, i + j);
2225 /* Skip to the last reg in this group. When i is incremented above,
2226 it will then point to the first reg of the next possible group. */
2231 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2232 another mode that needs to be reloaded for the same register class CLASS.
2233 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2234 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2236 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2237 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2238 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2239 causes unnecessary failures on machines requiring alignment of register
2240 groups when the two modes are different sizes, because the larger mode has
2241 more strict alignment rules than the smaller mode. */
2244 modes_equiv_for_class_p (allocate_mode, other_mode, class)
2245 enum machine_mode allocate_mode, other_mode;
2246 enum reg_class class;
2249 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2251 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
2252 && HARD_REGNO_MODE_OK (regno, allocate_mode)
2253 && ! HARD_REGNO_MODE_OK (regno, other_mode))
2259 /* Handle the failure to find a register to spill.
2260 INSN should be one of the insns which needed this particular spill reg. */
2263 spill_failure (insn)
2266 if (asm_noperands (PATTERN (insn)) >= 0)
2267 error_for_asm (insn, "`asm' needs too many reloads");
2269 fatal_insn ("Unable to find a register to spill.", insn);
2272 /* Add a new register to the tables of available spill-registers
2273 (as well as spilling all pseudos allocated to the register).
2274 I is the index of this register in potential_reload_regs.
2275 CLASS is the regclass whose need is being satisfied.
2276 MAX_NEEDS and MAX_NONGROUPS are the vectors of needs,
2277 so that this register can count off against them.
2278 MAX_NONGROUPS is 0 if this register is part of a group.
2279 GLOBAL and DUMPFILE are the same as the args that `reload' got. */
2282 new_spill_reg (i, class, max_needs, max_nongroups, global, dumpfile)
2290 register enum reg_class *p;
2292 int regno = potential_reload_regs[i];
2294 if (i >= FIRST_PSEUDO_REGISTER)
2295 abort (); /* Caller failed to find any register. */
2297 if (fixed_regs[regno] || TEST_HARD_REG_BIT (forbidden_regs, regno))
2299 static char *reg_class_names[] = REG_CLASS_NAMES;
2300 fatal ("fixed or forbidden register %d (%s) was spilled for class %s.\n\
2301 This may be due to a compiler bug or to impossible asm\n\
2302 statements or clauses.", regno, reg_names[regno], reg_class_names[class]);
2305 /* Make reg REGNO an additional reload reg. */
2307 potential_reload_regs[i] = -1;
2308 spill_regs[n_spills] = regno;
2309 spill_reg_order[regno] = n_spills;
2311 fprintf (dumpfile, "Spilling reg %d.\n", spill_regs[n_spills]);
2313 /* Clear off the needs we just satisfied. */
2316 p = reg_class_superclasses[class];
2317 while (*p != LIM_REG_CLASSES)
2318 max_needs[(int) *p++]--;
2320 if (max_nongroups && max_nongroups[class] > 0)
2322 SET_HARD_REG_BIT (counted_for_nongroups, regno);
2323 max_nongroups[class]--;
2324 p = reg_class_superclasses[class];
2325 while (*p != LIM_REG_CLASSES)
2326 max_nongroups[(int) *p++]--;
2329 /* Spill every pseudo reg that was allocated to this reg
2330 or to something that overlaps this reg. */
2332 val = spill_hard_reg (spill_regs[n_spills], global, dumpfile, 0);
2334 /* If there are some registers still to eliminate and this register
2335 wasn't ever used before, additional stack space may have to be
2336 allocated to store this register. Thus, we may have changed the offset
2337 between the stack and frame pointers, so mark that something has changed.
2338 (If new pseudos were spilled, thus requiring more space, VAL would have
2339 been set non-zero by the call to spill_hard_reg above since additional
2340 reloads may be needed in that case.
2342 One might think that we need only set VAL to 1 if this is a call-used
2343 register. However, the set of registers that must be saved by the
2344 prologue is not identical to the call-used set. For example, the
2345 register used by the call insn for the return PC is a call-used register,
2346 but must be saved by the prologue. */
2347 if (num_eliminable && ! regs_ever_live[spill_regs[n_spills]])
2350 regs_ever_live[spill_regs[n_spills]] = 1;
2356 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2357 data that is dead in INSN. */
2360 delete_dead_insn (insn)
2363 rtx prev = prev_real_insn (insn);
2366 /* If the previous insn sets a register that dies in our insn, delete it
2368 if (prev && GET_CODE (PATTERN (prev)) == SET
2369 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2370 && reg_mentioned_p (prev_dest, PATTERN (insn))
2371 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2372 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2373 delete_dead_insn (prev);
2375 PUT_CODE (insn, NOTE);
2376 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2377 NOTE_SOURCE_FILE (insn) = 0;
2380 /* Modify the home of pseudo-reg I.
2381 The new home is present in reg_renumber[I].
2383 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2384 or it may be -1, meaning there is none or it is not relevant.
2385 This is used so that all pseudos spilled from a given hard reg
2386 can share one stack slot. */
2389 alter_reg (i, from_reg)
2393 /* When outputting an inline function, this can happen
2394 for a reg that isn't actually used. */
2395 if (regno_reg_rtx[i] == 0)
2398 /* If the reg got changed to a MEM at rtl-generation time,
2400 if (GET_CODE (regno_reg_rtx[i]) != REG)
2403 /* Modify the reg-rtx to contain the new hard reg
2404 number or else to contain its pseudo reg number. */
2405 REGNO (regno_reg_rtx[i])
2406 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2408 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2409 allocate a stack slot for it. */
2411 if (reg_renumber[i] < 0
2412 && REG_N_REFS (i) > 0
2413 && reg_equiv_constant[i] == 0
2414 && reg_equiv_memory_loc[i] == 0)
2417 int inherent_size = PSEUDO_REGNO_BYTES (i);
2418 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2421 /* Each pseudo reg has an inherent size which comes from its own mode,
2422 and a total size which provides room for paradoxical subregs
2423 which refer to the pseudo reg in wider modes.
2425 We can use a slot already allocated if it provides both
2426 enough inherent space and enough total space.
2427 Otherwise, we allocate a new slot, making sure that it has no less
2428 inherent space, and no less total space, then the previous slot. */
2431 /* No known place to spill from => no slot to reuse. */
2432 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
2433 inherent_size == total_size ? 0 : -1);
2434 if (BYTES_BIG_ENDIAN)
2435 /* Cancel the big-endian correction done in assign_stack_local.
2436 Get the address of the beginning of the slot.
2437 This is so we can do a big-endian correction unconditionally
2439 adjust = inherent_size - total_size;
2441 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2443 /* Reuse a stack slot if possible. */
2444 else if (spill_stack_slot[from_reg] != 0
2445 && spill_stack_slot_width[from_reg] >= total_size
2446 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2448 x = spill_stack_slot[from_reg];
2449 /* Allocate a bigger slot. */
2452 /* Compute maximum size needed, both for inherent size
2453 and for total size. */
2454 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2456 if (spill_stack_slot[from_reg])
2458 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2460 mode = GET_MODE (spill_stack_slot[from_reg]);
2461 if (spill_stack_slot_width[from_reg] > total_size)
2462 total_size = spill_stack_slot_width[from_reg];
2464 /* Make a slot with that size. */
2465 x = assign_stack_local (mode, total_size,
2466 inherent_size == total_size ? 0 : -1);
2468 if (BYTES_BIG_ENDIAN)
2470 /* Cancel the big-endian correction done in assign_stack_local.
2471 Get the address of the beginning of the slot.
2472 This is so we can do a big-endian correction unconditionally
2474 adjust = GET_MODE_SIZE (mode) - total_size;
2476 stack_slot = gen_rtx_MEM (mode_for_size (total_size
2479 plus_constant (XEXP (x, 0), adjust));
2481 spill_stack_slot[from_reg] = stack_slot;
2482 spill_stack_slot_width[from_reg] = total_size;
2485 /* On a big endian machine, the "address" of the slot
2486 is the address of the low part that fits its inherent mode. */
2487 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2488 adjust += (total_size - inherent_size);
2490 /* If we have any adjustment to make, or if the stack slot is the
2491 wrong mode, make a new stack slot. */
2492 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2494 x = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
2495 plus_constant (XEXP (x, 0), adjust));
2497 /* If this was shared among registers, must ensure we never
2498 set it readonly since that can cause scheduling
2499 problems. Note we would only have in this adjustment
2500 case in any event, since the code above doesn't set it. */
2503 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2506 /* Save the stack slot for later. */
2507 reg_equiv_memory_loc[i] = x;
2511 /* Mark the slots in regs_ever_live for the hard regs
2512 used by pseudo-reg number REGNO. */
2515 mark_home_live (regno)
2518 register int i, lim;
2519 i = reg_renumber[regno];
2522 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2524 regs_ever_live[i++] = 1;
2527 /* This function handles the tracking of elimination offsets around branches.
2529 X is a piece of RTL being scanned.
2531 INSN is the insn that it came from, if any.
2533 INITIAL_P is non-zero if we are to set the offset to be the initial
2534 offset and zero if we are setting the offset of the label to be the
2538 set_label_offsets (x, insn, initial_p)
2543 enum rtx_code code = GET_CODE (x);
2546 struct elim_table *p;
2551 if (LABEL_REF_NONLOCAL_P (x))
2556 /* ... fall through ... */
2559 /* If we know nothing about this label, set the desired offsets. Note
2560 that this sets the offset at a label to be the offset before a label
2561 if we don't know anything about the label. This is not correct for
2562 the label after a BARRIER, but is the best guess we can make. If
2563 we guessed wrong, we will suppress an elimination that might have
2564 been possible had we been able to guess correctly. */
2566 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2568 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2569 offsets_at[CODE_LABEL_NUMBER (x)][i]
2570 = (initial_p ? reg_eliminate[i].initial_offset
2571 : reg_eliminate[i].offset);
2572 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2575 /* Otherwise, if this is the definition of a label and it is
2576 preceded by a BARRIER, set our offsets to the known offset of
2580 && (tem = prev_nonnote_insn (insn)) != 0
2581 && GET_CODE (tem) == BARRIER)
2583 num_not_at_initial_offset = 0;
2584 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2586 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
2587 = offsets_at[CODE_LABEL_NUMBER (x)][i];
2588 if (reg_eliminate[i].can_eliminate
2589 && (reg_eliminate[i].offset
2590 != reg_eliminate[i].initial_offset))
2591 num_not_at_initial_offset++;
2596 /* If neither of the above cases is true, compare each offset
2597 with those previously recorded and suppress any eliminations
2598 where the offsets disagree. */
2600 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2601 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2602 != (initial_p ? reg_eliminate[i].initial_offset
2603 : reg_eliminate[i].offset))
2604 reg_eliminate[i].can_eliminate = 0;
2609 set_label_offsets (PATTERN (insn), insn, initial_p);
2611 /* ... fall through ... */
2615 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2616 and hence must have all eliminations at their initial offsets. */
2617 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2618 if (REG_NOTE_KIND (tem) == REG_LABEL)
2619 set_label_offsets (XEXP (tem, 0), insn, 1);
2624 /* Each of the labels in the address vector must be at their initial
2625 offsets. We want the first field for ADDR_VEC and the second
2626 field for ADDR_DIFF_VEC. */
2628 for (i = 0; i < XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2629 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2634 /* We only care about setting PC. If the source is not RETURN,
2635 IF_THEN_ELSE, or a label, disable any eliminations not at
2636 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2637 isn't one of those possibilities. For branches to a label,
2638 call ourselves recursively.
2640 Note that this can disable elimination unnecessarily when we have
2641 a non-local goto since it will look like a non-constant jump to
2642 someplace in the current function. This isn't a significant
2643 problem since such jumps will normally be when all elimination
2644 pairs are back to their initial offsets. */
2646 if (SET_DEST (x) != pc_rtx)
2649 switch (GET_CODE (SET_SRC (x)))
2656 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2660 tem = XEXP (SET_SRC (x), 1);
2661 if (GET_CODE (tem) == LABEL_REF)
2662 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2663 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2666 tem = XEXP (SET_SRC (x), 2);
2667 if (GET_CODE (tem) == LABEL_REF)
2668 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2669 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2677 /* If we reach here, all eliminations must be at their initial
2678 offset because we are doing a jump to a variable address. */
2679 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2680 if (p->offset != p->initial_offset)
2681 p->can_eliminate = 0;
2689 /* Used for communication between the next two function to properly share
2690 the vector for an ASM_OPERANDS. */
2692 static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2694 /* Scan X and replace any eliminable registers (such as fp) with a
2695 replacement (such as sp), plus an offset.
2697 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2698 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2699 MEM, we are allowed to replace a sum of a register and the constant zero
2700 with the register, which we cannot do outside a MEM. In addition, we need
2701 to record the fact that a register is referenced outside a MEM.
2703 If INSN is an insn, it is the insn containing X. If we replace a REG
2704 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2705 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2706 the REG is being modified.
2708 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2709 That's used when we eliminate in expressions stored in notes.
2710 This means, do not set ref_outside_mem even if the reference
2713 If we see a modification to a register we know about, take the
2714 appropriate action (see case SET, below).
2716 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2717 replacements done assuming all offsets are at their initial values. If
2718 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2719 encounter, return the actual location so that find_reloads will do
2720 the proper thing. */
2723 eliminate_regs (x, mem_mode, insn)
2725 enum machine_mode mem_mode;
2728 enum rtx_code code = GET_CODE (x);
2729 struct elim_table *ep;
2752 /* This is only for the benefit of the debugging backends, which call
2753 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2754 removed after CSE. */
2755 new = eliminate_regs (XEXP (x, 0), 0, insn);
2756 if (GET_CODE (new) == MEM)
2757 return XEXP (new, 0);
2763 /* First handle the case where we encounter a bare register that
2764 is eliminable. Replace it with a PLUS. */
2765 if (regno < FIRST_PSEUDO_REGISTER)
2767 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2769 if (ep->from_rtx == x && ep->can_eliminate)
2772 /* Refs inside notes don't count for this purpose. */
2773 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2774 || GET_CODE (insn) == INSN_LIST)))
2775 ep->ref_outside_mem = 1;
2776 return plus_constant (ep->to_rtx, ep->previous_offset);
2780 else if (reg_equiv_memory_loc && reg_equiv_memory_loc[regno]
2781 && (reg_equiv_address[regno] || num_not_at_initial_offset))
2783 /* In this case, find_reloads would attempt to either use an
2784 incorrect address (if something is not at its initial offset)
2785 or substitute an replaced address into an insn (which loses
2786 if the offset is changed by some later action). So we simply
2787 return the replaced stack slot (assuming it is changed by
2788 elimination) and ignore the fact that this is actually a
2789 reference to the pseudo. Ensure we make a copy of the
2790 address in case it is shared. */
2791 new = eliminate_regs (reg_equiv_memory_loc[regno], mem_mode, insn);
2792 if (new != reg_equiv_memory_loc[regno])
2794 if (insn != 0 && GET_CODE (insn) != EXPR_LIST
2795 && GET_CODE (insn) != INSN_LIST)
2796 REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode, x), insn))
2797 = gen_rtx_EXPR_LIST (REG_EQUAL, new, NULL_RTX);
2798 return copy_rtx (new);
2804 /* If this is the sum of an eliminable register and a constant, rework
2806 if (GET_CODE (XEXP (x, 0)) == REG
2807 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2808 && CONSTANT_P (XEXP (x, 1)))
2810 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2812 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2815 /* Refs inside notes don't count for this purpose. */
2816 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2817 || GET_CODE (insn) == INSN_LIST)))
2818 ep->ref_outside_mem = 1;
2820 /* The only time we want to replace a PLUS with a REG (this
2821 occurs when the constant operand of the PLUS is the negative
2822 of the offset) is when we are inside a MEM. We won't want
2823 to do so at other times because that would change the
2824 structure of the insn in a way that reload can't handle.
2825 We special-case the commonest situation in
2826 eliminate_regs_in_insn, so just replace a PLUS with a
2827 PLUS here, unless inside a MEM. */
2828 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2829 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2832 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2833 plus_constant (XEXP (x, 1),
2834 ep->previous_offset));
2837 /* If the register is not eliminable, we are done since the other
2838 operand is a constant. */
2842 /* If this is part of an address, we want to bring any constant to the
2843 outermost PLUS. We will do this by doing register replacement in
2844 our operands and seeing if a constant shows up in one of them.
2846 We assume here this is part of an address (or a "load address" insn)
2847 since an eliminable register is not likely to appear in any other
2850 If we have (plus (eliminable) (reg)), we want to produce
2851 (plus (plus (replacement) (reg) (const))). If this was part of a
2852 normal add insn, (plus (replacement) (reg)) will be pushed as a
2853 reload. This is the desired action. */
2856 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2857 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2859 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2861 /* If one side is a PLUS and the other side is a pseudo that
2862 didn't get a hard register but has a reg_equiv_constant,
2863 we must replace the constant here since it may no longer
2864 be in the position of any operand. */
2865 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2866 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2867 && reg_renumber[REGNO (new1)] < 0
2868 && reg_equiv_constant != 0
2869 && reg_equiv_constant[REGNO (new1)] != 0)
2870 new1 = reg_equiv_constant[REGNO (new1)];
2871 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2872 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2873 && reg_renumber[REGNO (new0)] < 0
2874 && reg_equiv_constant[REGNO (new0)] != 0)
2875 new0 = reg_equiv_constant[REGNO (new0)];
2877 new = form_sum (new0, new1);
2879 /* As above, if we are not inside a MEM we do not want to
2880 turn a PLUS into something else. We might try to do so here
2881 for an addition of 0 if we aren't optimizing. */
2882 if (! mem_mode && GET_CODE (new) != PLUS)
2883 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2891 /* If this is the product of an eliminable register and a
2892 constant, apply the distribute law and move the constant out
2893 so that we have (plus (mult ..) ..). This is needed in order
2894 to keep load-address insns valid. This case is pathological.
2895 We ignore the possibility of overflow here. */
2896 if (GET_CODE (XEXP (x, 0)) == REG
2897 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2898 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2899 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2901 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2904 /* Refs inside notes don't count for this purpose. */
2905 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2906 || GET_CODE (insn) == INSN_LIST)))
2907 ep->ref_outside_mem = 1;
2910 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2911 ep->previous_offset * INTVAL (XEXP (x, 1)));
2914 /* ... fall through ... */
2919 case DIV: case UDIV:
2920 case MOD: case UMOD:
2921 case AND: case IOR: case XOR:
2922 case ROTATERT: case ROTATE:
2923 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2925 case GE: case GT: case GEU: case GTU:
2926 case LE: case LT: case LEU: case LTU:
2928 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2930 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2932 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2933 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2938 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2941 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2942 if (new != XEXP (x, 0))
2943 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2946 /* ... fall through ... */
2949 /* Now do eliminations in the rest of the chain. If this was
2950 an EXPR_LIST, this might result in allocating more memory than is
2951 strictly needed, but it simplifies the code. */
2954 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2955 if (new != XEXP (x, 1))
2956 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2964 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2965 if (ep->to_rtx == XEXP (x, 0))
2967 int size = GET_MODE_SIZE (mem_mode);
2969 /* If more bytes than MEM_MODE are pushed, account for them. */
2970 #ifdef PUSH_ROUNDING
2971 if (ep->to_rtx == stack_pointer_rtx)
2972 size = PUSH_ROUNDING (size);
2974 if (code == PRE_DEC || code == POST_DEC)
2980 /* Fall through to generic unary operation case. */
2981 case STRICT_LOW_PART:
2983 case SIGN_EXTEND: case ZERO_EXTEND:
2984 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2985 case FLOAT: case FIX:
2986 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2990 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2991 if (new != XEXP (x, 0))
2992 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2996 /* Similar to above processing, but preserve SUBREG_WORD.
2997 Convert (subreg (mem)) to (mem) if not paradoxical.
2998 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2999 pseudo didn't get a hard reg, we must replace this with the
3000 eliminated version of the memory location because push_reloads
3001 may do the replacement in certain circumstances. */
3002 if (GET_CODE (SUBREG_REG (x)) == REG
3003 && (GET_MODE_SIZE (GET_MODE (x))
3004 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3005 && reg_equiv_memory_loc != 0
3006 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
3008 new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
3011 /* If we didn't change anything, we must retain the pseudo. */
3012 if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
3013 new = SUBREG_REG (x);
3016 /* In this case, we must show that the pseudo is used in this
3017 insn so that delete_output_reload will do the right thing. */
3018 if (insn != 0 && GET_CODE (insn) != EXPR_LIST
3019 && GET_CODE (insn) != INSN_LIST)
3020 REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode,
3023 = gen_rtx_EXPR_LIST (REG_EQUAL, new, NULL_RTX);
3025 /* Ensure NEW isn't shared in case we have to reload it. */
3026 new = copy_rtx (new);
3030 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
3032 if (new != XEXP (x, 0))
3034 int x_size = GET_MODE_SIZE (GET_MODE (x));
3035 int new_size = GET_MODE_SIZE (GET_MODE (new));
3037 if (GET_CODE (new) == MEM
3038 && ((x_size < new_size
3039 #ifdef WORD_REGISTER_OPERATIONS
3040 /* On these machines, combine can create rtl of the form
3041 (set (subreg:m1 (reg:m2 R) 0) ...)
3042 where m1 < m2, and expects something interesting to
3043 happen to the entire word. Moreover, it will use the
3044 (reg:m2 R) later, expecting all bits to be preserved.
3045 So if the number of words is the same, preserve the
3046 subreg so that push_reloads can see it. */
3047 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
3050 || (x_size == new_size))
3053 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
3054 enum machine_mode mode = GET_MODE (x);
3056 if (BYTES_BIG_ENDIAN)
3057 offset += (MIN (UNITS_PER_WORD,
3058 GET_MODE_SIZE (GET_MODE (new)))
3059 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
3061 PUT_MODE (new, mode);
3062 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
3066 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
3072 /* If using a register that is the source of an eliminate we still
3073 think can be performed, note it cannot be performed since we don't
3074 know how this register is used. */
3075 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3076 if (ep->from_rtx == XEXP (x, 0))
3077 ep->can_eliminate = 0;
3079 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3080 if (new != XEXP (x, 0))
3081 return gen_rtx_fmt_e (code, GET_MODE (x), new);
3085 /* If clobbering a register that is the replacement register for an
3086 elimination we still think can be performed, note that it cannot
3087 be performed. Otherwise, we need not be concerned about it. */
3088 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3089 if (ep->to_rtx == XEXP (x, 0))
3090 ep->can_eliminate = 0;
3092 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3093 if (new != XEXP (x, 0))
3094 return gen_rtx_fmt_e (code, GET_MODE (x), new);
3100 /* Properly handle sharing input and constraint vectors. */
3101 if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
3103 /* When we come to a new vector not seen before,
3104 scan all its elements; keep the old vector if none
3105 of them changes; otherwise, make a copy. */
3106 old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
3107 temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
3108 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3109 temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
3112 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3113 if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
3116 if (i == ASM_OPERANDS_INPUT_LENGTH (x))
3117 new_asm_operands_vec = old_asm_operands_vec;
3119 new_asm_operands_vec
3120 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
3123 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
3124 if (new_asm_operands_vec == old_asm_operands_vec)
3127 new = gen_rtx_ASM_OPERANDS (VOIDmode, ASM_OPERANDS_TEMPLATE (x),
3128 ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
3129 ASM_OPERANDS_OUTPUT_IDX (x),
3130 new_asm_operands_vec,
3131 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
3132 ASM_OPERANDS_SOURCE_FILE (x),
3133 ASM_OPERANDS_SOURCE_LINE (x));
3134 new->volatil = x->volatil;
3139 /* Check for setting a register that we know about. */
3140 if (GET_CODE (SET_DEST (x)) == REG)
3142 /* See if this is setting the replacement register for an
3145 If DEST is the hard frame pointer, we do nothing because we
3146 assume that all assignments to the frame pointer are for
3147 non-local gotos and are being done at a time when they are valid
3148 and do not disturb anything else. Some machines want to
3149 eliminate a fake argument pointer (or even a fake frame pointer)
3150 with either the real frame or the stack pointer. Assignments to
3151 the hard frame pointer must not prevent this elimination. */
3153 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3155 if (ep->to_rtx == SET_DEST (x)
3156 && SET_DEST (x) != hard_frame_pointer_rtx)
3158 /* If it is being incremented, adjust the offset. Otherwise,
3159 this elimination can't be done. */
3160 rtx src = SET_SRC (x);
3162 if (GET_CODE (src) == PLUS
3163 && XEXP (src, 0) == SET_DEST (x)
3164 && GET_CODE (XEXP (src, 1)) == CONST_INT)
3165 ep->offset -= INTVAL (XEXP (src, 1));
3167 ep->can_eliminate = 0;
3170 /* Now check to see we are assigning to a register that can be
3171 eliminated. If so, it must be as part of a PARALLEL, since we
3172 will not have been called if this is a single SET. So indicate
3173 that we can no longer eliminate this reg. */
3174 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3176 if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
3177 ep->can_eliminate = 0;
3180 /* Now avoid the loop below in this common case. */
3182 rtx new0 = eliminate_regs (SET_DEST (x), 0, insn);
3183 rtx new1 = eliminate_regs (SET_SRC (x), 0, insn);
3185 /* If SET_DEST changed from a REG to a MEM and INSN is an insn,
3186 write a CLOBBER insn. */
3187 if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
3188 && insn != 0 && GET_CODE (insn) != EXPR_LIST
3189 && GET_CODE (insn) != INSN_LIST)
3190 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, SET_DEST (x)), insn);
3192 if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
3193 return gen_rtx_SET (VOIDmode, new0, new1);
3199 /* This is only for the benefit of the debugging backends, which call
3200 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
3201 removed after CSE. */
3202 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
3203 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
3205 /* Our only special processing is to pass the mode of the MEM to our
3206 recursive call and copy the flags. While we are here, handle this
3207 case more efficiently. */
3208 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
3209 if (new != XEXP (x, 0))
3211 new = gen_rtx_MEM (GET_MODE (x), new);
3212 new->volatil = x->volatil;
3213 new->unchanging = x->unchanging;
3214 new->in_struct = x->in_struct;
3224 /* Process each of our operands recursively. If any have changed, make a
3226 fmt = GET_RTX_FORMAT (code);
3227 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3231 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
3232 if (new != XEXP (x, i) && ! copied)
3234 rtx new_x = rtx_alloc (code);
3235 bcopy ((char *) x, (char *) new_x,
3236 (sizeof (*new_x) - sizeof (new_x->fld)
3237 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
3243 else if (*fmt == 'E')
3246 for (j = 0; j < XVECLEN (x, i); j++)
3248 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
3249 if (new != XVECEXP (x, i, j) && ! copied_vec)
3251 rtvec new_v = gen_rtvec_vv (XVECLEN (x, i),
3255 rtx new_x = rtx_alloc (code);
3256 bcopy ((char *) x, (char *) new_x,
3257 (sizeof (*new_x) - sizeof (new_x->fld)
3258 + (sizeof (new_x->fld[0])
3259 * GET_RTX_LENGTH (code))));
3263 XVEC (x, i) = new_v;
3266 XVECEXP (x, i, j) = new;
3274 /* Scan INSN and eliminate all eliminable registers in it.
3276 If REPLACE is nonzero, do the replacement destructively. Also
3277 delete the insn as dead it if it is setting an eliminable register.
3279 If REPLACE is zero, do all our allocations in reload_obstack.
3281 If no eliminations were done and this insn doesn't require any elimination
3282 processing (these are not identical conditions: it might be updating sp,
3283 but not referencing fp; this needs to be seen during reload_as_needed so
3284 that the offset between fp and sp can be taken into consideration), zero
3285 is returned. Otherwise, 1 is returned. */
3288 eliminate_regs_in_insn (insn, replace)
3292 rtx old_body = PATTERN (insn);
3293 rtx old_set = single_set (insn);
3296 struct elim_table *ep;
3299 push_obstacks (&reload_obstack, &reload_obstack);
3301 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
3302 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3304 /* Check for setting an eliminable register. */
3305 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3306 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3308 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3309 /* If this is setting the frame pointer register to the
3310 hardware frame pointer register and this is an elimination
3311 that will be done (tested above), this insn is really
3312 adjusting the frame pointer downward to compensate for
3313 the adjustment done before a nonlocal goto. */
3314 if (ep->from == FRAME_POINTER_REGNUM
3315 && ep->to == HARD_FRAME_POINTER_REGNUM)
3317 rtx src = SET_SRC (old_set);
3319 rtx prev_insn, prev_set;
3321 if (src == ep->to_rtx)
3323 else if (GET_CODE (src) == PLUS
3324 && GET_CODE (XEXP (src, 0)) == CONST_INT
3325 && XEXP (src, 1) == ep->to_rtx)
3326 offset = INTVAL (XEXP (src, 0)), ok = 1;
3327 else if (GET_CODE (src) == PLUS
3328 && GET_CODE (XEXP (src, 1)) == CONST_INT
3329 && XEXP (src, 0) == ep->to_rtx)
3330 offset = INTVAL (XEXP (src, 1)), ok = 1;
3331 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
3332 && (prev_set = single_set (prev_insn)) != 0
3333 && rtx_equal_p (SET_DEST (prev_set), src))
3335 src = SET_SRC (prev_set);
3336 if (src == ep->to_rtx)
3338 else if (GET_CODE (src) == PLUS
3339 && GET_CODE (XEXP (src, 0)) == CONST_INT
3340 && XEXP (src, 1) == ep->to_rtx)
3341 offset = INTVAL (XEXP (src, 0)), ok = 1;
3342 else if (GET_CODE (src) == PLUS
3343 && GET_CODE (XEXP (src, 1)) == CONST_INT
3344 && XEXP (src, 0) == ep->to_rtx)
3345 offset = INTVAL (XEXP (src, 1)), ok = 1;
3353 = plus_constant (ep->to_rtx, offset - ep->offset);
3355 /* First see if this insn remains valid when we
3356 make the change. If not, keep the INSN_CODE
3357 the same and let reload fit it up. */
3358 validate_change (insn, &SET_SRC (old_set), src, 1);
3359 validate_change (insn, &SET_DEST (old_set),
3361 if (! apply_change_group ())
3363 SET_SRC (old_set) = src;
3364 SET_DEST (old_set) = ep->to_rtx;
3374 /* In this case this insn isn't serving a useful purpose. We
3375 will delete it in reload_as_needed once we know that this
3376 elimination is, in fact, being done.
3378 If REPLACE isn't set, we can't delete this insn, but needn't
3379 process it since it won't be used unless something changes. */
3381 delete_dead_insn (insn);
3386 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3387 in the insn is the negative of the offset in FROM. Substitute
3388 (set (reg) (reg to)) for the insn and change its code.
3390 We have to do this here, rather than in eliminate_regs, do that we can
3391 change the insn code. */
3393 if (GET_CODE (SET_SRC (old_set)) == PLUS
3394 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3395 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT)
3396 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3398 if (ep->from_rtx == XEXP (SET_SRC (old_set), 0)
3399 && ep->can_eliminate)
3401 /* We must stop at the first elimination that will be used.
3402 If this one would replace the PLUS with a REG, do it
3403 now. Otherwise, quit the loop and let eliminate_regs
3404 do its normal replacement. */
3405 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_set), 1)))
3407 /* We assume here that we don't need a PARALLEL of
3408 any CLOBBERs for this assignment. There's not
3409 much we can do if we do need it. */
3410 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3413 INSN_CODE (insn) = -1;
3422 old_asm_operands_vec = 0;
3424 /* Replace the body of this insn with a substituted form. If we changed
3425 something, return non-zero.
3427 If we are replacing a body that was a (set X (plus Y Z)), try to
3428 re-recognize the insn. We do this in case we had a simple addition
3429 but now can do this as a load-address. This saves an insn in this
3432 new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX);
3433 if (new_body != old_body)
3435 /* If we aren't replacing things permanently and we changed something,
3436 make another copy to ensure that all the RTL is new. Otherwise
3437 things can go wrong if find_reload swaps commutative operands
3438 and one is inside RTL that has been copied while the other is not. */
3440 /* Don't copy an asm_operands because (1) there's no need and (2)
3441 copy_rtx can't do it properly when there are multiple outputs. */
3442 if (! replace && asm_noperands (old_body) < 0)
3443 new_body = copy_rtx (new_body);
3445 /* If we had a move insn but now we don't, rerecognize it. This will
3446 cause spurious re-recognition if the old move had a PARALLEL since
3447 the new one still will, but we can't call single_set without
3448 having put NEW_BODY into the insn and the re-recognition won't
3449 hurt in this rare case. */
3451 && ((GET_CODE (SET_SRC (old_set)) == REG
3452 && (GET_CODE (new_body) != SET
3453 || GET_CODE (SET_SRC (new_body)) != REG))
3454 /* If this was a load from or store to memory, compare
3455 the MEM in recog_operand to the one in the insn. If they
3456 are not equal, then rerecognize the insn. */
3458 && ((GET_CODE (SET_SRC (old_set)) == MEM
3459 && SET_SRC (old_set) != recog_operand[1])
3460 || (GET_CODE (SET_DEST (old_set)) == MEM
3461 && SET_DEST (old_set) != recog_operand[0])))
3462 /* If this was an add insn before, rerecognize. */
3463 || GET_CODE (SET_SRC (old_set)) == PLUS))
3465 if (! validate_change (insn, &PATTERN (insn), new_body, 0))
3466 /* If recognition fails, store the new body anyway.
3467 It's normal to have recognition failures here
3468 due to bizarre memory addresses; reloading will fix them. */
3469 PATTERN (insn) = new_body;
3472 PATTERN (insn) = new_body;
3477 /* Loop through all elimination pairs. See if any have changed and
3478 recalculate the number not at initial offset.
3480 Compute the maximum offset (minimum offset if the stack does not
3481 grow downward) for each elimination pair.
3483 We also detect a cases where register elimination cannot be done,
3484 namely, if a register would be both changed and referenced outside a MEM
3485 in the resulting insn since such an insn is often undefined and, even if
3486 not, we cannot know what meaning will be given to it. Note that it is
3487 valid to have a register used in an address in an insn that changes it
3488 (presumably with a pre- or post-increment or decrement).
3490 If anything changes, return nonzero. */
3492 num_not_at_initial_offset = 0;
3493 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3495 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3496 ep->can_eliminate = 0;
3498 ep->ref_outside_mem = 0;
3500 if (ep->previous_offset != ep->offset)
3503 ep->previous_offset = ep->offset;
3504 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3505 num_not_at_initial_offset++;
3507 #ifdef STACK_GROWS_DOWNWARD
3508 ep->max_offset = MAX (ep->max_offset, ep->offset);
3510 ep->max_offset = MIN (ep->max_offset, ep->offset);
3515 /* If we changed something, perform elimination in REG_NOTES. This is
3516 needed even when REPLACE is zero because a REG_DEAD note might refer
3517 to a register that we eliminate and could cause a different number
3518 of spill registers to be needed in the final reload pass than in
3520 if (val && REG_NOTES (insn) != 0)
3521 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3529 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3530 replacement we currently believe is valid, mark it as not eliminable if X
3531 modifies DEST in any way other than by adding a constant integer to it.
3533 If DEST is the frame pointer, we do nothing because we assume that
3534 all assignments to the hard frame pointer are nonlocal gotos and are being
3535 done at a time when they are valid and do not disturb anything else.
3536 Some machines want to eliminate a fake argument pointer with either the
3537 frame or stack pointer. Assignments to the hard frame pointer must not
3538 prevent this elimination.
3540 Called via note_stores from reload before starting its passes to scan
3541 the insns of the function. */
3544 mark_not_eliminable (dest, x)
3550 /* A SUBREG of a hard register here is just changing its mode. We should
3551 not see a SUBREG of an eliminable hard register, but check just in
3553 if (GET_CODE (dest) == SUBREG)
3554 dest = SUBREG_REG (dest);
3556 if (dest == hard_frame_pointer_rtx)
3559 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3560 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3561 && (GET_CODE (x) != SET
3562 || GET_CODE (SET_SRC (x)) != PLUS
3563 || XEXP (SET_SRC (x), 0) != dest
3564 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3566 reg_eliminate[i].can_eliminate_previous
3567 = reg_eliminate[i].can_eliminate = 0;
3572 /* Reset all offsets on eliminable registers to their initial values. */
3574 set_initial_elim_offsets ()
3578 #ifdef ELIMINABLE_REGS
3579 struct elim_table *ep;
3581 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3583 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3584 ep->previous_offset = ep->offset
3585 = ep->max_offset = ep->initial_offset;
3588 #ifdef INITIAL_FRAME_POINTER_OFFSET
3589 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
3591 if (!FRAME_POINTER_REQUIRED)
3593 reg_eliminate[0].initial_offset = 0;
3595 reg_eliminate[0].previous_offset = reg_eliminate[0].max_offset
3596 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
3599 num_not_at_initial_offset = 0;
3601 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
3603 /* Set a known offset for each forced label to be at the initial offset
3604 of each elimination. We do this because we assume that all
3605 computed jumps occur from a location where each elimination is
3606 at its initial offset. */
3608 for (x = forced_labels; x; x = XEXP (x, 1))
3610 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3613 /* See if anything that happened changes which eliminations are valid.
3614 For example, on the Sparc, whether or not the frame pointer can
3615 be eliminated can depend on what registers have been used. We need
3616 not check some conditions again (such as flag_omit_frame_pointer)
3617 since they can't have changed. */
3620 update_eliminables (pset)
3623 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3624 int previous_frame_pointer_needed = frame_pointer_needed;
3626 struct elim_table *ep;
3628 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3629 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3630 #ifdef ELIMINABLE_REGS
3631 || ! CAN_ELIMINATE (ep->from, ep->to)
3634 ep->can_eliminate = 0;
3636 /* Look for the case where we have discovered that we can't replace
3637 register A with register B and that means that we will now be
3638 trying to replace register A with register C. This means we can
3639 no longer replace register C with register B and we need to disable
3640 such an elimination, if it exists. This occurs often with A == ap,
3641 B == sp, and C == fp. */
3643 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3645 struct elim_table *op;
3646 register int new_to = -1;
3648 if (! ep->can_eliminate && ep->can_eliminate_previous)
3650 /* Find the current elimination for ep->from, if there is a
3652 for (op = reg_eliminate;
3653 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3654 if (op->from == ep->from && op->can_eliminate)
3660 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3662 for (op = reg_eliminate;
3663 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3664 if (op->from == new_to && op->to == ep->to)
3665 op->can_eliminate = 0;
3669 /* See if any registers that we thought we could eliminate the previous
3670 time are no longer eliminable. If so, something has changed and we
3671 must spill the register. Also, recompute the number of eliminable
3672 registers and see if the frame pointer is needed; it is if there is
3673 no elimination of the frame pointer that we can perform. */
3675 frame_pointer_needed = 1;
3676 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3678 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3679 && ep->to != HARD_FRAME_POINTER_REGNUM)
3680 frame_pointer_needed = 0;
3682 if (! ep->can_eliminate && ep->can_eliminate_previous)
3684 ep->can_eliminate_previous = 0;
3685 SET_HARD_REG_BIT (*pset, ep->from);
3690 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3691 /* If we didn't need a frame pointer last time, but we do now, spill
3692 the hard frame pointer. */
3693 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3694 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3698 /* Initialize the table of registers to eliminate. */
3702 struct elim_table *ep;
3704 /* Does this function require a frame pointer? */
3706 frame_pointer_needed = (! flag_omit_frame_pointer
3707 #ifdef EXIT_IGNORE_STACK
3708 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3709 and restore sp for alloca. So we can't eliminate
3710 the frame pointer in that case. At some point,
3711 we should improve this by emitting the
3712 sp-adjusting insns for this case. */
3713 || (current_function_calls_alloca
3714 && EXIT_IGNORE_STACK)
3716 || FRAME_POINTER_REQUIRED);
3720 #ifdef ELIMINABLE_REGS
3721 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3723 ep->can_eliminate = ep->can_eliminate_previous
3724 = (CAN_ELIMINATE (ep->from, ep->to)
3725 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3728 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3729 = ! frame_pointer_needed;
3732 /* Count the number of eliminable registers and build the FROM and TO
3733 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3734 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3735 We depend on this. */
3736 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3738 num_eliminable += ep->can_eliminate;
3739 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3740 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3744 /* Kick all pseudos out of hard register REGNO.
3745 If GLOBAL is nonzero, try to find someplace else to put them.
3746 If DUMPFILE is nonzero, log actions taken on that file.
3748 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3749 because we found we can't eliminate some register. In the case, no pseudos
3750 are allowed to be in the register, even if they are only in a block that
3751 doesn't require spill registers, unlike the case when we are spilling this
3752 hard reg to produce another spill register.
3754 Return nonzero if any pseudos needed to be kicked out. */
3757 spill_hard_reg (regno, global, dumpfile, cant_eliminate)
3763 enum reg_class class = REGNO_REG_CLASS (regno);
3764 int something_changed = 0;
3767 SET_HARD_REG_BIT (forbidden_regs, regno);
3770 regs_ever_live[regno] = 1;
3772 /* Spill every pseudo reg that was allocated to this reg
3773 or to something that overlaps this reg. */
3775 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3776 if (reg_renumber[i] >= 0
3777 && reg_renumber[i] <= regno
3779 + HARD_REGNO_NREGS (reg_renumber[i],
3780 PSEUDO_REGNO_MODE (i))
3783 /* If this register belongs solely to a basic block which needed no
3784 spilling of any class that this register is contained in,
3785 leave it be, unless we are spilling this register because
3786 it was a hard register that can't be eliminated. */
3788 if (! cant_eliminate
3789 && basic_block_needs[0]
3790 && REG_BASIC_BLOCK (i) >= 0
3791 && basic_block_needs[(int) class][REG_BASIC_BLOCK (i)] == 0)
3795 for (p = reg_class_superclasses[(int) class];
3796 *p != LIM_REG_CLASSES; p++)
3797 if (basic_block_needs[(int) *p][REG_BASIC_BLOCK (i)] > 0)
3800 if (*p == LIM_REG_CLASSES)
3804 /* Mark it as no longer having a hard register home. */
3805 reg_renumber[i] = -1;
3806 /* We will need to scan everything again. */
3807 something_changed = 1;
3809 retry_global_alloc (i, forbidden_regs);
3811 alter_reg (i, regno);
3814 if (reg_renumber[i] == -1)
3815 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3817 fprintf (dumpfile, " Register %d now in %d.\n\n",
3818 i, reg_renumber[i]);
3822 return something_changed;
3825 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3826 Also mark any hard registers used to store user variables as
3827 forbidden from being used for spill registers. */
3830 scan_paradoxical_subregs (x)
3835 register enum rtx_code code = GET_CODE (x);
3840 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3841 && REG_USERVAR_P (x))
3842 SET_HARD_REG_BIT (forbidden_regs, REGNO (x));
3857 if (GET_CODE (SUBREG_REG (x)) == REG
3858 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3859 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3860 = GET_MODE_SIZE (GET_MODE (x));
3867 fmt = GET_RTX_FORMAT (code);
3868 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3871 scan_paradoxical_subregs (XEXP (x, i));
3872 else if (fmt[i] == 'E')
3875 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3876 scan_paradoxical_subregs (XVECEXP (x, i, j));
3882 hard_reg_use_compare (p1p, p2p)
3883 const GENERIC_PTR p1p;
3884 const GENERIC_PTR p2p;
3886 struct hard_reg_n_uses *p1 = (struct hard_reg_n_uses *)p1p,
3887 *p2 = (struct hard_reg_n_uses *)p2p;
3888 int tem = p1->uses - p2->uses;
3889 if (tem != 0) return tem;
3890 /* If regs are equally good, sort by regno,
3891 so that the results of qsort leave nothing to chance. */
3892 return p1->regno - p2->regno;
3895 /* Choose the order to consider regs for use as reload registers
3896 based on how much trouble would be caused by spilling one.
3897 Store them in order of decreasing preference in potential_reload_regs. */
3900 order_regs_for_reload ()
3906 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
3908 CLEAR_HARD_REG_SET (bad_spill_regs);
3910 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3911 potential_reload_regs[i] = -1;
3913 /* Count number of uses of each hard reg by pseudo regs allocated to it
3914 and then order them by decreasing use. */
3916 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3918 hard_reg_n_uses[i].uses = 0;
3919 hard_reg_n_uses[i].regno = i;
3922 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3924 int regno = reg_renumber[i];
3927 int lim = regno + HARD_REGNO_NREGS (regno, PSEUDO_REGNO_MODE (i));
3929 hard_reg_n_uses[regno++].uses += REG_N_REFS (i);
3931 large += REG_N_REFS (i);
3934 /* Now fixed registers (which cannot safely be used for reloading)
3935 get a very high use count so they will be considered least desirable.
3936 Registers used explicitly in the rtl code are almost as bad. */
3938 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3942 hard_reg_n_uses[i].uses += 2 * large + 2;
3943 SET_HARD_REG_BIT (bad_spill_regs, i);
3945 else if (regs_explicitly_used[i])
3947 hard_reg_n_uses[i].uses += large + 1;
3948 if (! SMALL_REGISTER_CLASSES)
3949 /* ??? We are doing this here because of the potential
3950 that bad code may be generated if a register explicitly
3951 used in an insn was used as a spill register for that
3952 insn. But not using these are spill registers may lose
3953 on some machine. We'll have to see how this works out. */
3954 SET_HARD_REG_BIT (bad_spill_regs, i);
3957 hard_reg_n_uses[HARD_FRAME_POINTER_REGNUM].uses += 2 * large + 2;
3958 SET_HARD_REG_BIT (bad_spill_regs, HARD_FRAME_POINTER_REGNUM);
3960 #ifdef ELIMINABLE_REGS
3961 /* If registers other than the frame pointer are eliminable, mark them as
3963 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3965 hard_reg_n_uses[reg_eliminate[i].from].uses += 2 * large + 2;
3966 SET_HARD_REG_BIT (bad_spill_regs, reg_eliminate[i].from);
3970 /* Prefer registers not so far used, for use in temporary loading.
3971 Among them, if REG_ALLOC_ORDER is defined, use that order.
3972 Otherwise, prefer registers not preserved by calls. */
3974 #ifdef REG_ALLOC_ORDER
3975 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3977 int regno = reg_alloc_order[i];
3979 if (hard_reg_n_uses[regno].uses == 0)
3980 potential_reload_regs[o++] = regno;
3983 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3985 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i])
3986 potential_reload_regs[o++] = i;
3988 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3990 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i])
3991 potential_reload_regs[o++] = i;
3995 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
3996 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
3998 /* Now add the regs that are already used,
3999 preferring those used less often. The fixed and otherwise forbidden
4000 registers will be at the end of this list. */
4002 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4003 if (hard_reg_n_uses[i].uses != 0)
4004 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
4007 /* Used in reload_as_needed to sort the spilled regs. */
4010 compare_spill_regs (r1p, r2p)
4011 const GENERIC_PTR r1p;
4012 const GENERIC_PTR r2p;
4014 short r1 = *(short *)r1p, r2 = *(short *)r2p;
4018 /* Reload pseudo-registers into hard regs around each insn as needed.
4019 Additional register load insns are output before the insn that needs it
4020 and perhaps store insns after insns that modify the reloaded pseudo reg.
4022 reg_last_reload_reg and reg_reloaded_contents keep track of
4023 which registers are already available in reload registers.
4024 We update these for the reloads that we perform,
4025 as the insns are scanned. */
4028 reload_as_needed (first, live_known)
4038 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
4039 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
4040 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
4041 bzero ((char *) reg_last_reload_reg, max_regno * sizeof (rtx));
4042 reg_has_output_reload = (char *) alloca (max_regno);
4043 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4045 /* Reset all offsets on eliminable registers to their initial values. */
4046 #ifdef ELIMINABLE_REGS
4047 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
4049 INITIAL_ELIMINATION_OFFSET (reg_eliminate[i].from, reg_eliminate[i].to,
4050 reg_eliminate[i].initial_offset);
4051 reg_eliminate[i].previous_offset
4052 = reg_eliminate[i].offset = reg_eliminate[i].initial_offset;
4055 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
4056 reg_eliminate[0].previous_offset
4057 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
4060 num_not_at_initial_offset = 0;
4062 /* Order the spilled regs, so that allocate_reload_regs can guarantee to
4063 pack registers with group needs. */
4066 qsort (spill_regs, n_spills, sizeof (short), compare_spill_regs);
4067 for (i = 0; i < n_spills; i++)
4068 spill_reg_order[spill_regs[i]] = i;
4071 for (insn = first; insn;)
4073 register rtx next = NEXT_INSN (insn);
4075 /* Notice when we move to a new basic block. */
4076 if (live_known && this_block + 1 < n_basic_blocks
4077 && insn == basic_block_head[this_block+1])
4080 /* If we pass a label, copy the offsets from the label information
4081 into the current offsets of each elimination. */
4082 if (GET_CODE (insn) == CODE_LABEL)
4084 num_not_at_initial_offset = 0;
4085 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
4087 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
4088 = offsets_at[CODE_LABEL_NUMBER (insn)][i];
4089 if (reg_eliminate[i].can_eliminate
4090 && (reg_eliminate[i].offset
4091 != reg_eliminate[i].initial_offset))
4092 num_not_at_initial_offset++;
4096 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
4098 rtx avoid_return_reg = 0;
4099 rtx oldpat = PATTERN (insn);
4101 /* Set avoid_return_reg if this is an insn
4102 that might use the value of a function call. */
4103 if (SMALL_REGISTER_CLASSES && GET_CODE (insn) == CALL_INSN)
4105 if (GET_CODE (PATTERN (insn)) == SET)
4106 after_call = SET_DEST (PATTERN (insn));
4107 else if (GET_CODE (PATTERN (insn)) == PARALLEL
4108 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
4109 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
4113 else if (SMALL_REGISTER_CLASSES && after_call != 0
4114 && !(GET_CODE (PATTERN (insn)) == SET
4115 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx)
4116 && GET_CODE (PATTERN (insn)) != USE)
4118 if (reg_referenced_p (after_call, PATTERN (insn)))
4119 avoid_return_reg = after_call;
4123 /* If this is a USE and CLOBBER of a MEM, ensure that any
4124 references to eliminable registers have been removed. */
4126 if ((GET_CODE (PATTERN (insn)) == USE
4127 || GET_CODE (PATTERN (insn)) == CLOBBER)
4128 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
4129 XEXP (XEXP (PATTERN (insn), 0), 0)
4130 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4131 GET_MODE (XEXP (PATTERN (insn), 0)),
4134 /* If we need to do register elimination processing, do so.
4135 This might delete the insn, in which case we are done. */
4136 if (num_eliminable && GET_MODE (insn) == QImode)
4138 eliminate_regs_in_insn (insn, 1);
4139 if (GET_CODE (insn) == NOTE)
4146 if (GET_MODE (insn) == VOIDmode)
4148 /* First find the pseudo regs that must be reloaded for this insn.
4149 This info is returned in the tables reload_... (see reload.h).
4150 Also modify the body of INSN by substituting RELOAD
4151 rtx's for those pseudo regs. */
4154 bzero (reg_has_output_reload, max_regno);
4155 CLEAR_HARD_REG_SET (reg_is_output_reload);
4157 find_reloads (insn, 1, spill_indirect_levels, live_known,
4163 rtx prev = PREV_INSN (insn), next = NEXT_INSN (insn);
4167 /* If this block has not had spilling done for a
4168 particular clas and we have any non-optionals that need a
4169 spill reg in that class, abort. */
4171 for (class = 0; class < N_REG_CLASSES; class++)
4172 if (basic_block_needs[class] != 0
4173 && basic_block_needs[class][this_block] == 0)
4174 for (i = 0; i < n_reloads; i++)
4175 if (class == (int) reload_reg_class[i]
4176 && reload_reg_rtx[i] == 0
4177 && ! reload_optional[i]
4178 && (reload_in[i] != 0 || reload_out[i] != 0
4179 || reload_secondary_p[i] != 0))
4180 fatal_insn ("Non-optional registers need a spill register", insn);
4182 /* Now compute which reload regs to reload them into. Perhaps
4183 reusing reload regs from previous insns, or else output
4184 load insns to reload them. Maybe output store insns too.
4185 Record the choices of reload reg in reload_reg_rtx. */
4186 choose_reload_regs (insn, avoid_return_reg);
4188 /* Merge any reloads that we didn't combine for fear of
4189 increasing the number of spill registers needed but now
4190 discover can be safely merged. */
4191 if (SMALL_REGISTER_CLASSES)
4192 merge_assigned_reloads (insn);
4194 /* Generate the insns to reload operands into or out of
4195 their reload regs. */
4196 emit_reload_insns (insn, this_block);
4198 /* Substitute the chosen reload regs from reload_reg_rtx
4199 into the insn's body (or perhaps into the bodies of other
4200 load and store insn that we just made for reloading
4201 and that we moved the structure into). */
4204 /* If this was an ASM, make sure that all the reload insns
4205 we have generated are valid. If not, give an error
4208 if (asm_noperands (PATTERN (insn)) >= 0)
4209 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4210 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
4211 && (recog_memoized (p) < 0
4212 || (insn_extract (p),
4213 ! constrain_operands (INSN_CODE (p), 1))))
4215 error_for_asm (insn,
4216 "`asm' operand requires impossible reload");
4218 NOTE_SOURCE_FILE (p) = 0;
4219 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
4222 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4223 is no longer validly lying around to save a future reload.
4224 Note that this does not detect pseudos that were reloaded
4225 for this insn in order to be stored in
4226 (obeying register constraints). That is correct; such reload
4227 registers ARE still valid. */
4228 note_stores (oldpat, forget_old_reloads_1);
4230 /* There may have been CLOBBER insns placed after INSN. So scan
4231 between INSN and NEXT and use them to forget old reloads. */
4232 for (x = NEXT_INSN (insn); x != next; x = NEXT_INSN (x))
4233 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
4234 note_stores (PATTERN (x), forget_old_reloads_1);
4237 /* Likewise for regs altered by auto-increment in this insn.
4238 But note that the reg-notes are not changed by reloading:
4239 they still contain the pseudo-regs, not the spill regs. */
4240 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4241 if (REG_NOTE_KIND (x) == REG_INC)
4243 /* See if this pseudo reg was reloaded in this insn.
4244 If so, its last-reload info is still valid
4245 because it is based on this insn's reload. */
4246 for (i = 0; i < n_reloads; i++)
4247 if (reload_out[i] == XEXP (x, 0))
4251 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX);
4255 /* A reload reg's contents are unknown after a label. */
4256 if (GET_CODE (insn) == CODE_LABEL)
4257 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4259 /* Don't assume a reload reg is still good after a call insn
4260 if it is a call-used reg. */
4261 else if (GET_CODE (insn) == CALL_INSN)
4262 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
4264 /* In case registers overlap, allow certain insns to invalidate
4265 particular hard registers. */
4267 #ifdef INSN_CLOBBERS_REGNO_P
4268 for (i = 0 ; i < FIRST_PSEUDO_REGISTER; i++)
4269 if (TEST_HARD_REG_BIT (reg_reloaded_valid, i)
4270 && INSN_CLOBBERS_REGNO_P (insn, i))
4271 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i);
4282 /* Discard all record of any value reloaded from X,
4283 or reloaded in X from someplace else;
4284 unless X is an output reload reg of the current insn.
4286 X may be a hard reg (the reload reg)
4287 or it may be a pseudo reg that was reloaded from. */
4290 forget_old_reloads_1 (x, ignored)
4292 rtx ignored ATTRIBUTE_UNUSED;
4298 /* note_stores does give us subregs of hard regs. */
4299 while (GET_CODE (x) == SUBREG)
4301 offset += SUBREG_WORD (x);
4305 if (GET_CODE (x) != REG)
4308 regno = REGNO (x) + offset;
4310 if (regno >= FIRST_PSEUDO_REGISTER)
4315 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4316 /* Storing into a spilled-reg invalidates its contents.
4317 This can happen if a block-local pseudo is allocated to that reg
4318 and it wasn't spilled because this block's total need is 0.
4319 Then some insn might have an optional reload and use this reg. */
4320 for (i = 0; i < nr; i++)
4321 /* But don't do this if the reg actually serves as an output
4322 reload reg in the current instruction. */
4324 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4325 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4328 /* Since value of X has changed,
4329 forget any value previously copied from it. */
4332 /* But don't forget a copy if this is the output reload
4333 that establishes the copy's validity. */
4334 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4335 reg_last_reload_reg[regno + nr] = 0;
4338 /* For each reload, the mode of the reload register. */
4339 static enum machine_mode reload_mode[MAX_RELOADS];
4341 /* For each reload, the largest number of registers it will require. */
4342 static int reload_nregs[MAX_RELOADS];
4344 /* Comparison function for qsort to decide which of two reloads
4345 should be handled first. *P1 and *P2 are the reload numbers. */
4348 reload_reg_class_lower (r1p, r2p)
4349 const GENERIC_PTR r1p;
4350 const GENERIC_PTR r2p;
4352 register int r1 = *(short *)r1p, r2 = *(short *)r2p;
4355 /* Consider required reloads before optional ones. */
4356 t = reload_optional[r1] - reload_optional[r2];
4360 /* Count all solitary classes before non-solitary ones. */
4361 t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
4362 - (reg_class_size[(int) reload_reg_class[r1]] == 1));
4366 /* Aside from solitaires, consider all multi-reg groups first. */
4367 t = reload_nregs[r2] - reload_nregs[r1];
4371 /* Consider reloads in order of increasing reg-class number. */
4372 t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
4376 /* If reloads are equally urgent, sort by reload number,
4377 so that the results of qsort leave nothing to chance. */
4381 /* The following HARD_REG_SETs indicate when each hard register is
4382 used for a reload of various parts of the current insn. */
4384 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4385 static HARD_REG_SET reload_reg_used;
4386 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4387 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4388 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4389 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4390 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4391 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4392 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4393 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4394 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4395 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4396 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4397 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4398 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4399 static HARD_REG_SET reload_reg_used_in_op_addr;
4400 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4401 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4402 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4403 static HARD_REG_SET reload_reg_used_in_insn;
4404 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4405 static HARD_REG_SET reload_reg_used_in_other_addr;
4407 /* If reg is in use as a reload reg for any sort of reload. */
4408 static HARD_REG_SET reload_reg_used_at_all;
4410 /* If reg is use as an inherited reload. We just mark the first register
4412 static HARD_REG_SET reload_reg_used_for_inherit;
4414 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4415 TYPE. MODE is used to indicate how many consecutive regs are
4419 mark_reload_reg_in_use (regno, opnum, type, mode)
4422 enum reload_type type;
4423 enum machine_mode mode;
4425 int nregs = HARD_REGNO_NREGS (regno, mode);
4428 for (i = regno; i < nregs + regno; i++)
4433 SET_HARD_REG_BIT (reload_reg_used, i);
4436 case RELOAD_FOR_INPUT_ADDRESS:
4437 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4440 case RELOAD_FOR_INPADDR_ADDRESS:
4441 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4444 case RELOAD_FOR_OUTPUT_ADDRESS:
4445 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4448 case RELOAD_FOR_OUTADDR_ADDRESS:
4449 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4452 case RELOAD_FOR_OPERAND_ADDRESS:
4453 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4456 case RELOAD_FOR_OPADDR_ADDR:
4457 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4460 case RELOAD_FOR_OTHER_ADDRESS:
4461 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4464 case RELOAD_FOR_INPUT:
4465 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4468 case RELOAD_FOR_OUTPUT:
4469 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4472 case RELOAD_FOR_INSN:
4473 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4477 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4481 /* Similarly, but show REGNO is no longer in use for a reload. */
4484 clear_reload_reg_in_use (regno, opnum, type, mode)
4487 enum reload_type type;
4488 enum machine_mode mode;
4490 int nregs = HARD_REGNO_NREGS (regno, mode);
4493 for (i = regno; i < nregs + regno; i++)
4498 CLEAR_HARD_REG_BIT (reload_reg_used, i);
4501 case RELOAD_FOR_INPUT_ADDRESS:
4502 CLEAR_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4505 case RELOAD_FOR_INPADDR_ADDRESS:
4506 CLEAR_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4509 case RELOAD_FOR_OUTPUT_ADDRESS:
4510 CLEAR_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4513 case RELOAD_FOR_OUTADDR_ADDRESS:
4514 CLEAR_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4517 case RELOAD_FOR_OPERAND_ADDRESS:
4518 CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4521 case RELOAD_FOR_OPADDR_ADDR:
4522 CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4525 case RELOAD_FOR_OTHER_ADDRESS:
4526 CLEAR_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4529 case RELOAD_FOR_INPUT:
4530 CLEAR_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4533 case RELOAD_FOR_OUTPUT:
4534 CLEAR_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4537 case RELOAD_FOR_INSN:
4538 CLEAR_HARD_REG_BIT (reload_reg_used_in_insn, i);
4544 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4545 specified by OPNUM and TYPE. */
4548 reload_reg_free_p (regno, opnum, type)
4551 enum reload_type type;
4555 /* In use for a RELOAD_OTHER means it's not available for anything. */
4556 if (TEST_HARD_REG_BIT (reload_reg_used, regno))
4562 /* In use for anything means we can't use it for RELOAD_OTHER. */
4563 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4564 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4565 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4568 for (i = 0; i < reload_n_operands; i++)
4569 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4570 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4571 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4572 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4573 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4574 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4579 case RELOAD_FOR_INPUT:
4580 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4581 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4584 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4587 /* If it is used for some other input, can't use it. */
4588 for (i = 0; i < reload_n_operands; i++)
4589 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4592 /* If it is used in a later operand's address, can't use it. */
4593 for (i = opnum + 1; i < reload_n_operands; i++)
4594 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4595 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4600 case RELOAD_FOR_INPUT_ADDRESS:
4601 /* Can't use a register if it is used for an input address for this
4602 operand or used as an input in an earlier one. */
4603 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4604 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4607 for (i = 0; i < opnum; i++)
4608 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4613 case RELOAD_FOR_INPADDR_ADDRESS:
4614 /* Can't use a register if it is used for an input address
4615 for this operand or used as an input in an earlier
4617 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4620 for (i = 0; i < opnum; i++)
4621 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4626 case RELOAD_FOR_OUTPUT_ADDRESS:
4627 /* Can't use a register if it is used for an output address for this
4628 operand or used as an output in this or a later operand. */
4629 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4632 for (i = opnum; i < reload_n_operands; i++)
4633 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4638 case RELOAD_FOR_OUTADDR_ADDRESS:
4639 /* Can't use a register if it is used for an output address
4640 for this operand or used as an output in this or a
4642 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4645 for (i = opnum; i < reload_n_operands; i++)
4646 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4651 case RELOAD_FOR_OPERAND_ADDRESS:
4652 for (i = 0; i < reload_n_operands; i++)
4653 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4656 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4657 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4659 case RELOAD_FOR_OPADDR_ADDR:
4660 for (i = 0; i < reload_n_operands; i++)
4661 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4664 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4666 case RELOAD_FOR_OUTPUT:
4667 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4668 outputs, or an operand address for this or an earlier output. */
4669 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4672 for (i = 0; i < reload_n_operands; i++)
4673 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4676 for (i = 0; i <= opnum; i++)
4677 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4678 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4683 case RELOAD_FOR_INSN:
4684 for (i = 0; i < reload_n_operands; i++)
4685 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4686 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4689 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4690 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4692 case RELOAD_FOR_OTHER_ADDRESS:
4693 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4698 /* Return 1 if the value in reload reg REGNO, as used by a reload
4699 needed for the part of the insn specified by OPNUM and TYPE,
4700 is not in use for a reload in any prior part of the insn.
4702 We can assume that the reload reg was already tested for availability
4703 at the time it is needed, and we should not check this again,
4704 in case the reg has already been marked in use.
4706 However, if EQUIV is set, we are checking the availability of a register
4707 holding an equivalence to the value to be loaded into the reload register,
4708 not the availability of the reload register itself.
4710 This is still less stringent than what reload_reg_free_p checks; for
4711 example, compare the checks for RELOAD_OTHER. */
4714 reload_reg_free_before_p (regno, opnum, type, equiv)
4717 enum reload_type type;
4724 case RELOAD_FOR_OTHER_ADDRESS:
4725 /* These always come first. */
4726 if (equiv && TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno))
4731 if (equiv && TEST_HARD_REG_BIT (reload_reg_used, regno))
4733 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4735 /* If this use is for part of the insn,
4736 check the reg is not in use for any prior part. It is tempting
4737 to try to do this by falling through from objecs that occur
4738 later in the insn to ones that occur earlier, but that will not
4739 correctly take into account the fact that here we MUST ignore
4740 things that would prevent the register from being allocated in
4741 the first place, since we know that it was allocated. */
4743 case RELOAD_FOR_OUTPUT_ADDRESS:
4745 && TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4747 /* Earlier reloads include RELOAD_FOR_OUTADDR_ADDRESS reloads. */
4748 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4750 /* ... fall through ... */
4751 case RELOAD_FOR_OUTADDR_ADDRESS:
4753 && (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno)
4754 || TEST_HARD_REG_BIT (reload_reg_used, regno)))
4756 /* Earlier reloads are for earlier outputs or their addresses,
4757 any RELOAD_FOR_INSN reloads, any inputs or their addresses, or any
4758 RELOAD_FOR_OTHER_ADDRESS reloads (we know it can't conflict with
4760 for (i = 0; i < opnum; i++)
4761 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4762 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4765 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4768 for (i = 0; i < reload_n_operands; i++)
4769 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4770 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4771 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4772 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4775 return (! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4776 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4777 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4778 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4780 case RELOAD_FOR_OUTPUT:
4781 case RELOAD_FOR_INSN:
4782 /* There is no reason to call this function for output reloads, thus
4783 anything we'd put here wouldn't be tested. So just abort. */
4786 case RELOAD_FOR_OPERAND_ADDRESS:
4787 if (equiv && TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4790 /* Earlier reloads include RELOAD_FOR_OPADDR_ADDR reloads. */
4791 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4794 /* ... fall through ... */
4796 case RELOAD_FOR_OPADDR_ADDR:
4799 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4800 || TEST_HARD_REG_BIT (reload_reg_used, regno))
4802 for (i = 0; i < reload_n_operands; i++)
4803 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4806 /* These can't conflict with inputs, or each other, so all we have to
4807 test is input addresses and the addresses of OTHER items. */
4809 for (i = 0; i < reload_n_operands; i++)
4810 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4811 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4814 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4816 case RELOAD_FOR_INPUT:
4817 if (equiv && TEST_HARD_REG_BIT (reload_reg_used, regno))
4820 /* The only things earlier are the address for this and
4821 earlier inputs, other inputs (which we know we don't conflict
4822 with), and addresses of RELOAD_OTHER objects. */
4824 for (i = 0; i <= opnum; i++)
4825 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4826 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4829 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4831 case RELOAD_FOR_INPUT_ADDRESS:
4832 /* Earlier reloads include RELOAD_FOR_INPADDR_ADDRESS reloads. */
4833 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4835 /* ... fall through ... */
4836 case RELOAD_FOR_INPADDR_ADDRESS:
4837 if (equiv && TEST_HARD_REG_BIT (reload_reg_used, regno))
4840 /* Similarly, all we have to check is for use in earlier inputs'
4842 for (i = 0; i < opnum; i++)
4843 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4844 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4847 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4852 /* Return 1 if the value in reload reg REGNO, as used by a reload
4853 needed for the part of the insn specified by OPNUM and TYPE,
4854 is still available in REGNO at the end of the insn.
4856 We can assume that the reload reg was already tested for availability
4857 at the time it is needed, and we should not check this again,
4858 in case the reg has already been marked in use. */
4861 reload_reg_reaches_end_p (regno, opnum, type)
4864 enum reload_type type;
4871 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4872 its value must reach the end. */
4875 /* If this use is for part of the insn,
4876 its value reaches if no subsequent part uses the same register.
4877 Just like the above function, don't try to do this with lots
4880 case RELOAD_FOR_OTHER_ADDRESS:
4881 /* Here we check for everything else, since these don't conflict
4882 with anything else and everything comes later. */
4884 for (i = 0; i < reload_n_operands; i++)
4885 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4886 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4887 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4888 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4889 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4890 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4893 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4894 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4895 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4897 case RELOAD_FOR_INPUT_ADDRESS:
4898 case RELOAD_FOR_INPADDR_ADDRESS:
4899 /* Similar, except that we check only for this and subsequent inputs
4900 and the address of only subsequent inputs and we do not need
4901 to check for RELOAD_OTHER objects since they are known not to
4904 for (i = opnum; i < reload_n_operands; i++)
4905 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4908 for (i = opnum + 1; i < reload_n_operands; i++)
4909 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4910 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4913 for (i = 0; i < reload_n_operands; i++)
4914 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4915 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4916 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4919 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4922 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4923 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4925 case RELOAD_FOR_INPUT:
4926 /* Similar to input address, except we start at the next operand for
4927 both input and input address and we do not check for
4928 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4931 for (i = opnum + 1; i < reload_n_operands; i++)
4932 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4933 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4934 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4937 /* ... fall through ... */
4939 case RELOAD_FOR_OPERAND_ADDRESS:
4940 /* Check outputs and their addresses. */
4942 for (i = 0; i < reload_n_operands; i++)
4943 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4944 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4945 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4950 case RELOAD_FOR_OPADDR_ADDR:
4951 for (i = 0; i < reload_n_operands; i++)
4952 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4953 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4954 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4957 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4958 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4960 case RELOAD_FOR_INSN:
4961 /* These conflict with other outputs with RELOAD_OTHER. So
4962 we need only check for output addresses. */
4966 /* ... fall through ... */
4968 case RELOAD_FOR_OUTPUT:
4969 case RELOAD_FOR_OUTPUT_ADDRESS:
4970 case RELOAD_FOR_OUTADDR_ADDRESS:
4971 /* We already know these can't conflict with a later output. So the
4972 only thing to check are later output addresses. */
4973 for (i = opnum + 1; i < reload_n_operands; i++)
4974 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4975 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4984 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4987 This function uses the same algorithm as reload_reg_free_p above. */
4990 reloads_conflict (r1, r2)
4993 enum reload_type r1_type = reload_when_needed[r1];
4994 enum reload_type r2_type = reload_when_needed[r2];
4995 int r1_opnum = reload_opnum[r1];
4996 int r2_opnum = reload_opnum[r2];
4998 /* RELOAD_OTHER conflicts with everything. */
4999 if (r2_type == RELOAD_OTHER)
5002 /* Otherwise, check conflicts differently for each type. */
5006 case RELOAD_FOR_INPUT:
5007 return (r2_type == RELOAD_FOR_INSN
5008 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5009 || r2_type == RELOAD_FOR_OPADDR_ADDR
5010 || r2_type == RELOAD_FOR_INPUT
5011 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5012 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5013 && r2_opnum > r1_opnum));
5015 case RELOAD_FOR_INPUT_ADDRESS:
5016 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5017 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5019 case RELOAD_FOR_INPADDR_ADDRESS:
5020 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5021 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5023 case RELOAD_FOR_OUTPUT_ADDRESS:
5024 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5025 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
5027 case RELOAD_FOR_OUTADDR_ADDRESS:
5028 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5029 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
5031 case RELOAD_FOR_OPERAND_ADDRESS:
5032 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5033 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5035 case RELOAD_FOR_OPADDR_ADDR:
5036 return (r2_type == RELOAD_FOR_INPUT
5037 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5039 case RELOAD_FOR_OUTPUT:
5040 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5041 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5042 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5043 && r2_opnum >= r1_opnum));
5045 case RELOAD_FOR_INSN:
5046 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5047 || r2_type == RELOAD_FOR_INSN
5048 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5050 case RELOAD_FOR_OTHER_ADDRESS:
5051 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5061 /* Vector of reload-numbers showing the order in which the reloads should
5063 short reload_order[MAX_RELOADS];
5065 /* Indexed by reload number, 1 if incoming value
5066 inherited from previous insns. */
5067 char reload_inherited[MAX_RELOADS];
5069 /* For an inherited reload, this is the insn the reload was inherited from,
5070 if we know it. Otherwise, this is 0. */
5071 rtx reload_inheritance_insn[MAX_RELOADS];
5073 /* If non-zero, this is a place to get the value of the reload,
5074 rather than using reload_in. */
5075 rtx reload_override_in[MAX_RELOADS];
5077 /* For each reload, the hard register number of the register used,
5078 or -1 if we did not need a register for this reload. */
5079 int reload_spill_index[MAX_RELOADS];
5081 /* Return 1 if the value in reload reg REGNO, as used by a reload
5082 needed for the part of the insn specified by OPNUM and TYPE,
5083 may be used to load VALUE into it.
5085 Other read-only reloads with the same value do not conflict
5086 unless OUT is non-zero and these other reloads have to live while
5087 output reloads live.
5089 RELOADNUM is the number of the reload we want to load this value for;
5090 a reload does not conflict with itself.
5092 The caller has to make sure that there is no conflict with the return
5095 reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum)
5098 enum reload_type type;
5105 /* We use some pseudo 'time' value to check if the lifetimes of the
5106 new register use would overlap with the one of a previous reload
5107 that is not read-only or uses a different value.
5108 The 'time' used doesn't have to be linear in any shape or form, just
5110 Some reload types use different 'buckets' for each operand.
5111 So there are MAX_RECOG_OPERANDS different time values for each
5113 We compute TIME1 as the time when the register for the prospective
5114 new reload ceases to be live, and TIME2 for each existing
5115 reload as the time when that the reload register of that reload
5117 Where there is little to be gained by exact lifetime calculations,
5118 we just make conservative assumptions, i.e. a longer lifetime;
5119 this is done in the 'default:' cases. */
5122 case RELOAD_FOR_OTHER_ADDRESS:
5125 /* For each input, we might have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5126 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5127 respectively, to the time values for these, we get distinct time
5128 values. To get distinct time values for each operand, we have to
5129 multiply opnum by at least three. We round that up to four because
5130 multiply by four is often cheaper. */
5131 case RELOAD_FOR_INPADDR_ADDRESS:
5132 time1 = opnum * 4 + 1;
5134 case RELOAD_FOR_INPUT_ADDRESS:
5135 time1 = opnum * 4 + 2;
5137 case RELOAD_FOR_INPUT:
5138 /* All RELOAD_FOR_INPUT reloads remain live till just before the
5139 instruction is executed. */
5140 time1 = (MAX_RECOG_OPERANDS - 1) * 4 + 3;
5142 /* opnum * 4 + 3 < opnum * 4 + 4
5143 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5144 case RELOAD_FOR_OUTPUT_ADDRESS:
5145 time1 = MAX_RECOG_OPERANDS * 4 + opnum;
5148 time1 = MAX_RECOG_OPERANDS * 5;
5151 for (i = 0; i < n_reloads; i++)
5153 rtx reg = reload_reg_rtx[i];
5154 if (reg && GET_CODE (reg) == REG
5155 && ((unsigned) regno - true_regnum (reg)
5156 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
5160 && reload_when_needed[i] != RELOAD_FOR_INPUT
5161 && reload_when_needed[i] != RELOAD_FOR_INPUT_ADDRESS
5162 && reload_when_needed[i] != RELOAD_FOR_INPADDR_ADDRESS)
5164 if (! reload_in[i] || ! rtx_equal_p (reload_in[i], value)
5168 switch (reload_when_needed[i])
5170 case RELOAD_FOR_OTHER_ADDRESS:
5173 case RELOAD_FOR_INPADDR_ADDRESS:
5174 time2 = reload_opnum[i] * 4 + 1;
5176 case RELOAD_FOR_INPUT_ADDRESS:
5177 time2 = reload_opnum[i] * 4 + 2;
5179 case RELOAD_FOR_INPUT:
5180 time2 = reload_opnum[i] * 4 + 3;
5182 case RELOAD_FOR_OUTPUT:
5183 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5184 instruction is executed. */
5185 time2 = MAX_RECOG_OPERANDS * 4;
5187 /* The first RELOAD_FOR_OUTPUT_ADDRESS reload conflicts with the
5188 RELOAD_FOR_OUTPUT reloads, so assign it the same time value. */
5189 case RELOAD_FOR_OUTPUT_ADDRESS:
5190 time2 = MAX_RECOG_OPERANDS * 4 + reload_opnum[i];
5193 if (! reload_in[i] || rtx_equal_p (reload_in[i], value))
5195 time2 = MAX_RECOG_OPERANDS * 4;
5209 /* Find a spill register to use as a reload register for reload R.
5210 LAST_RELOAD is non-zero if this is the last reload for the insn being
5213 Set reload_reg_rtx[R] to the register allocated.
5215 If NOERROR is nonzero, we return 1 if successful,
5216 or 0 if we couldn't find a spill reg and we didn't change anything. */
5219 allocate_reload_reg (r, insn, last_reload, noerror)
5231 /* If we put this reload ahead, thinking it is a group,
5232 then insist on finding a group. Otherwise we can grab a
5233 reg that some other reload needs.
5234 (That can happen when we have a 68000 DATA_OR_FP_REG
5235 which is a group of data regs or one fp reg.)
5236 We need not be so restrictive if there are no more reloads
5239 ??? Really it would be nicer to have smarter handling
5240 for that kind of reg class, where a problem like this is normal.
5241 Perhaps those classes should be avoided for reloading
5242 by use of more alternatives. */
5244 int force_group = reload_nregs[r] > 1 && ! last_reload;
5246 /* If we want a single register and haven't yet found one,
5247 take any reg in the right class and not in use.
5248 If we want a consecutive group, here is where we look for it.
5250 We use two passes so we can first look for reload regs to
5251 reuse, which are already in use for other reloads in this insn,
5252 and only then use additional registers.
5253 I think that maximizing reuse is needed to make sure we don't
5254 run out of reload regs. Suppose we have three reloads, and
5255 reloads A and B can share regs. These need two regs.
5256 Suppose A and B are given different regs.
5257 That leaves none for C. */
5258 for (pass = 0; pass < 2; pass++)
5260 /* I is the index in spill_regs.
5261 We advance it round-robin between insns to use all spill regs
5262 equally, so that inherited reloads have a chance
5263 of leapfrogging each other. Don't do this, however, when we have
5264 group needs and failure would be fatal; if we only have a relatively
5265 small number of spill registers, and more than one of them has
5266 group needs, then by starting in the middle, we may end up
5267 allocating the first one in such a way that we are not left with
5268 sufficient groups to handle the rest. */
5270 if (noerror || ! force_group)
5275 for (count = 0; count < n_spills; count++)
5277 int class = (int) reload_reg_class[r];
5279 i = (i + 1) % n_spills;
5281 if ((reload_reg_free_p (spill_regs[i], reload_opnum[r],
5282 reload_when_needed[r])
5284 /* We check reload_reg_used to make sure we
5285 don't clobber the return register. */
5286 && ! TEST_HARD_REG_BIT (reload_reg_used, spill_regs[i])
5287 && reload_reg_free_for_value_p (spill_regs[i],
5289 reload_when_needed[r],
5292 && TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
5293 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
5294 /* Look first for regs to share, then for unshared. But
5295 don't share regs used for inherited reloads; they are
5296 the ones we want to preserve. */
5298 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5300 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5303 int nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
5304 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5305 (on 68000) got us two FP regs. If NR is 1,
5306 we would reject both of them. */
5308 nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
5309 /* If we need only one reg, we have already won. */
5312 /* But reject a single reg if we demand a group. */
5317 /* Otherwise check that as many consecutive regs as we need
5319 Also, don't use for a group registers that are
5320 needed for nongroups. */
5321 if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
5324 regno = spill_regs[i] + nr - 1;
5325 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5326 && spill_reg_order[regno] >= 0
5327 && reload_reg_free_p (regno, reload_opnum[r],
5328 reload_when_needed[r])
5329 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
5339 /* If we found something on pass 1, omit pass 2. */
5340 if (count < n_spills)
5344 /* We should have found a spill register by now. */
5345 if (count == n_spills)
5352 /* I is the index in SPILL_REG_RTX of the reload register we are to
5353 allocate. Get an rtx for it and find its register number. */
5355 new = spill_reg_rtx[i];
5357 if (new == 0 || GET_MODE (new) != reload_mode[r])
5358 spill_reg_rtx[i] = new
5359 = gen_rtx_REG (reload_mode[r], spill_regs[i]);
5361 regno = true_regnum (new);
5363 /* Detect when the reload reg can't hold the reload mode.
5364 This used to be one `if', but Sequent compiler can't handle that. */
5365 if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5367 enum machine_mode test_mode = VOIDmode;
5369 test_mode = GET_MODE (reload_in[r]);
5370 /* If reload_in[r] has VOIDmode, it means we will load it
5371 in whatever mode the reload reg has: to wit, reload_mode[r].
5372 We have already tested that for validity. */
5373 /* Aside from that, we need to test that the expressions
5374 to reload from or into have modes which are valid for this
5375 reload register. Otherwise the reload insns would be invalid. */
5376 if (! (reload_in[r] != 0 && test_mode != VOIDmode
5377 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5378 if (! (reload_out[r] != 0
5379 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
5381 /* The reg is OK. */
5384 /* Mark as in use for this insn the reload regs we use
5386 mark_reload_reg_in_use (spill_regs[i], reload_opnum[r],
5387 reload_when_needed[r], reload_mode[r]);
5389 reload_reg_rtx[r] = new;
5390 reload_spill_index[r] = spill_regs[i];
5395 /* The reg is not OK. */
5400 if (asm_noperands (PATTERN (insn)) < 0)
5401 /* It's the compiler's fault. */
5402 fatal_insn ("Could not find a spill register", insn);
5404 /* It's the user's fault; the operand's mode and constraint
5405 don't match. Disable this reload so we don't crash in final. */
5406 error_for_asm (insn,
5407 "`asm' operand constraint incompatible with operand size");
5410 reload_reg_rtx[r] = 0;
5411 reload_optional[r] = 1;
5412 reload_secondary_p[r] = 1;
5417 /* Assign hard reg targets for the pseudo-registers we must reload
5418 into hard regs for this insn.
5419 Also output the instructions to copy them in and out of the hard regs.
5421 For machines with register classes, we are responsible for
5422 finding a reload reg in the proper class. */
5425 choose_reload_regs (insn, avoid_return_reg)
5427 rtx avoid_return_reg;
5430 int max_group_size = 1;
5431 enum reg_class group_class = NO_REGS;
5434 rtx save_reload_reg_rtx[MAX_RELOADS];
5435 char save_reload_inherited[MAX_RELOADS];
5436 rtx save_reload_inheritance_insn[MAX_RELOADS];
5437 rtx save_reload_override_in[MAX_RELOADS];
5438 int save_reload_spill_index[MAX_RELOADS];
5439 HARD_REG_SET save_reload_reg_used;
5440 HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
5441 HARD_REG_SET save_reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
5442 HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
5443 HARD_REG_SET save_reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
5444 HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS];
5445 HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS];
5446 HARD_REG_SET save_reload_reg_used_in_op_addr;
5447 HARD_REG_SET save_reload_reg_used_in_op_addr_reload;
5448 HARD_REG_SET save_reload_reg_used_in_insn;
5449 HARD_REG_SET save_reload_reg_used_in_other_addr;
5450 HARD_REG_SET save_reload_reg_used_at_all;
5452 bzero (reload_inherited, MAX_RELOADS);
5453 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5454 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5456 CLEAR_HARD_REG_SET (reload_reg_used);
5457 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5458 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5459 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5460 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5461 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5463 for (i = 0; i < reload_n_operands; i++)
5465 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5466 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5467 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5468 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5469 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5470 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5473 /* Don't bother with avoiding the return reg
5474 if we have no mandatory reload that could use it. */
5475 if (SMALL_REGISTER_CLASSES && avoid_return_reg)
5478 int regno = REGNO (avoid_return_reg);
5480 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
5483 for (r = regno; r < regno + nregs; r++)
5484 if (spill_reg_order[r] >= 0)
5485 for (j = 0; j < n_reloads; j++)
5486 if (!reload_optional[j] && reload_reg_rtx[j] == 0
5487 && (reload_in[j] != 0 || reload_out[j] != 0
5488 || reload_secondary_p[j])
5490 TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[j]], r))
5493 avoid_return_reg = 0;
5496 #if 0 /* Not needed, now that we can always retry without inheritance. */
5497 /* See if we have more mandatory reloads than spill regs.
5498 If so, then we cannot risk optimizations that could prevent
5499 reloads from sharing one spill register.
5501 Since we will try finding a better register than reload_reg_rtx
5502 unless it is equal to reload_in or reload_out, count such reloads. */
5505 int tem = SMALL_REGISTER_CLASSES? (avoid_return_reg != 0): 0;
5506 for (j = 0; j < n_reloads; j++)
5507 if (! reload_optional[j]
5508 && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
5509 && (reload_reg_rtx[j] == 0
5510 || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
5511 && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
5518 /* Don't use the subroutine call return reg for a reload
5519 if we are supposed to avoid it. */
5520 if (SMALL_REGISTER_CLASSES && avoid_return_reg)
5522 int regno = REGNO (avoid_return_reg);
5524 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
5527 for (r = regno; r < regno + nregs; r++)
5528 if (spill_reg_order[r] >= 0)
5529 SET_HARD_REG_BIT (reload_reg_used, r);
5532 /* In order to be certain of getting the registers we need,
5533 we must sort the reloads into order of increasing register class.
5534 Then our grabbing of reload registers will parallel the process
5535 that provided the reload registers.
5537 Also note whether any of the reloads wants a consecutive group of regs.
5538 If so, record the maximum size of the group desired and what
5539 register class contains all the groups needed by this insn. */
5541 for (j = 0; j < n_reloads; j++)
5543 reload_order[j] = j;
5544 reload_spill_index[j] = -1;
5547 = (reload_inmode[j] == VOIDmode
5548 || (GET_MODE_SIZE (reload_outmode[j])
5549 > GET_MODE_SIZE (reload_inmode[j])))
5550 ? reload_outmode[j] : reload_inmode[j];
5552 reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
5554 if (reload_nregs[j] > 1)
5556 max_group_size = MAX (reload_nregs[j], max_group_size);
5557 group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
5560 /* If we have already decided to use a certain register,
5561 don't use it in another way. */
5562 if (reload_reg_rtx[j])
5563 mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j],
5564 reload_when_needed[j], reload_mode[j]);
5568 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5570 bcopy ((char *) reload_reg_rtx, (char *) save_reload_reg_rtx,
5571 sizeof reload_reg_rtx);
5572 bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
5573 bcopy ((char *) reload_inheritance_insn,
5574 (char *) save_reload_inheritance_insn,
5575 sizeof reload_inheritance_insn);
5576 bcopy ((char *) reload_override_in, (char *) save_reload_override_in,
5577 sizeof reload_override_in);
5578 bcopy ((char *) reload_spill_index, (char *) save_reload_spill_index,
5579 sizeof reload_spill_index);
5580 COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
5581 COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
5582 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
5583 reload_reg_used_in_op_addr);
5585 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr_reload,
5586 reload_reg_used_in_op_addr_reload);
5588 COPY_HARD_REG_SET (save_reload_reg_used_in_insn,
5589 reload_reg_used_in_insn);
5590 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr,
5591 reload_reg_used_in_other_addr);
5593 for (i = 0; i < reload_n_operands; i++)
5595 COPY_HARD_REG_SET (save_reload_reg_used_in_output[i],
5596 reload_reg_used_in_output[i]);
5597 COPY_HARD_REG_SET (save_reload_reg_used_in_input[i],
5598 reload_reg_used_in_input[i]);
5599 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i],
5600 reload_reg_used_in_input_addr[i]);
5601 COPY_HARD_REG_SET (save_reload_reg_used_in_inpaddr_addr[i],
5602 reload_reg_used_in_inpaddr_addr[i]);
5603 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i],
5604 reload_reg_used_in_output_addr[i]);
5605 COPY_HARD_REG_SET (save_reload_reg_used_in_outaddr_addr[i],
5606 reload_reg_used_in_outaddr_addr[i]);
5609 /* If -O, try first with inheritance, then turning it off.
5610 If not -O, don't do inheritance.
5611 Using inheritance when not optimizing leads to paradoxes
5612 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5613 because one side of the comparison might be inherited. */
5615 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5617 /* Process the reloads in order of preference just found.
5618 Beyond this point, subregs can be found in reload_reg_rtx.
5620 This used to look for an existing reloaded home for all
5621 of the reloads, and only then perform any new reloads.
5622 But that could lose if the reloads were done out of reg-class order
5623 because a later reload with a looser constraint might have an old
5624 home in a register needed by an earlier reload with a tighter constraint.
5626 To solve this, we make two passes over the reloads, in the order
5627 described above. In the first pass we try to inherit a reload
5628 from a previous insn. If there is a later reload that needs a
5629 class that is a proper subset of the class being processed, we must
5630 also allocate a spill register during the first pass.
5632 Then make a second pass over the reloads to allocate any reloads
5633 that haven't been given registers yet. */
5635 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5637 for (j = 0; j < n_reloads; j++)
5639 register int r = reload_order[j];
5641 /* Ignore reloads that got marked inoperative. */
5642 if (reload_out[r] == 0 && reload_in[r] == 0
5643 && ! reload_secondary_p[r])
5646 /* If find_reloads chose to use reload_in or reload_out as a reload
5647 register, we don't need to chose one. Otherwise, try even if it
5648 found one since we might save an insn if we find the value lying
5650 Try also when reload_in is a pseudo without a hard reg. */
5651 if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
5652 && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
5653 || (rtx_equal_p (reload_out[r], reload_reg_rtx[r])
5654 && GET_CODE (reload_in[r]) != MEM
5655 && true_regnum (reload_in[r]) < FIRST_PSEUDO_REGISTER)))
5658 #if 0 /* No longer needed for correct operation.
5659 It might give better code, or might not; worth an experiment? */
5660 /* If this is an optional reload, we can't inherit from earlier insns
5661 until we are sure that any non-optional reloads have been allocated.
5662 The following code takes advantage of the fact that optional reloads
5663 are at the end of reload_order. */
5664 if (reload_optional[r] != 0)
5665 for (i = 0; i < j; i++)
5666 if ((reload_out[reload_order[i]] != 0
5667 || reload_in[reload_order[i]] != 0
5668 || reload_secondary_p[reload_order[i]])
5669 && ! reload_optional[reload_order[i]]
5670 && reload_reg_rtx[reload_order[i]] == 0)
5671 allocate_reload_reg (reload_order[i], insn, 0, inheritance);
5674 /* First see if this pseudo is already available as reloaded
5675 for a previous insn. We cannot try to inherit for reloads
5676 that are smaller than the maximum number of registers needed
5677 for groups unless the register we would allocate cannot be used
5680 We could check here to see if this is a secondary reload for
5681 an object that is already in a register of the desired class.
5682 This would avoid the need for the secondary reload register.
5683 But this is complex because we can't easily determine what
5684 objects might want to be loaded via this reload. So let a
5685 register be allocated here. In `emit_reload_insns' we suppress
5686 one of the loads in the case described above. */
5690 register int regno = -1;
5691 enum machine_mode mode;
5693 if (reload_in[r] == 0)
5695 else if (GET_CODE (reload_in[r]) == REG)
5697 regno = REGNO (reload_in[r]);
5698 mode = GET_MODE (reload_in[r]);
5700 else if (GET_CODE (reload_in_reg[r]) == REG)
5702 regno = REGNO (reload_in_reg[r]);
5703 mode = GET_MODE (reload_in_reg[r]);
5705 else if (GET_CODE (reload_in[r]) == MEM)
5707 rtx prev = prev_nonnote_insn (insn), note;
5709 if (prev && GET_CODE (prev) == INSN
5710 && GET_CODE (PATTERN (prev)) == USE
5711 && GET_CODE (XEXP (PATTERN (prev), 0)) == REG
5712 && (REGNO (XEXP (PATTERN (prev), 0))
5713 >= FIRST_PSEUDO_REGISTER)
5714 && (note = find_reg_note (prev, REG_EQUAL, NULL_RTX))
5715 && GET_CODE (XEXP (note, 0)) == MEM)
5717 rtx addr = XEXP (XEXP (note, 0), 0);
5719 = (GET_MODE_SIZE (GET_MODE (addr))
5720 - GET_MODE_SIZE (GET_MODE (reload_in[r])));
5722 && rtx_equal_p ((BYTES_BIG_ENDIAN
5723 ? plus_constant (addr, size_diff)
5725 XEXP (reload_in[r], 0)))
5727 regno = REGNO (XEXP (PATTERN (prev), 0));
5728 mode = GET_MODE (reload_in[r]);
5733 /* This won't work, since REGNO can be a pseudo reg number.
5734 Also, it takes much more hair to keep track of all the things
5735 that can invalidate an inherited reload of part of a pseudoreg. */
5736 else if (GET_CODE (reload_in[r]) == SUBREG
5737 && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
5738 regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
5741 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5743 i = REGNO (reg_last_reload_reg[regno]);
5745 if (reg_reloaded_contents[i] == regno
5746 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5747 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
5748 >= GET_MODE_SIZE (mode))
5749 && HARD_REGNO_MODE_OK (i, reload_mode[r])
5750 && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5752 && (reload_nregs[r] == max_group_size
5753 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5755 && ((reload_reg_free_p (i, reload_opnum[r],
5756 reload_when_needed[r])
5757 && reload_reg_free_before_p (i, reload_opnum[r],
5758 reload_when_needed[r],
5760 || reload_reg_free_for_value_p (i, reload_opnum[r],
5761 reload_when_needed[r],
5765 /* If a group is needed, verify that all the subsequent
5766 registers still have their values intact. */
5768 = HARD_REGNO_NREGS (i, reload_mode[r]);
5771 for (k = 1; k < nr; k++)
5772 if (reg_reloaded_contents[i + k] != regno
5773 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5780 /* We found a register that contains the
5781 value we need. If this register is the
5782 same as an `earlyclobber' operand of the
5783 current insn, just mark it as a place to
5784 reload from since we can't use it as the
5785 reload register itself. */
5787 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5788 if (reg_overlap_mentioned_for_reload_p
5789 (reg_last_reload_reg[regno],
5790 reload_earlyclobbers[i1]))
5793 if (i1 != n_earlyclobbers
5794 /* Don't use it if we'd clobber a pseudo reg. */
5795 || (spill_reg_order[i] < 0
5797 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5798 /* Don't really use the inherited spill reg
5799 if we need it wider than we've got it. */
5800 || (GET_MODE_SIZE (reload_mode[r])
5801 > GET_MODE_SIZE (mode))
5802 /* If find_reloads chose reload_out as reload
5803 register, stay with it - that leaves the
5804 inherited register for subsequent reloads. */
5805 || (reload_out[r] && reload_reg_rtx
5806 && rtx_equal_p (reload_out[r],
5807 reload_reg_rtx[r])))
5808 reload_override_in[r] = reg_last_reload_reg[regno];
5812 /* We can use this as a reload reg. */
5813 /* Mark the register as in use for this part of
5815 mark_reload_reg_in_use (i,
5817 reload_when_needed[r],
5819 reload_reg_rtx[r] = reg_last_reload_reg[regno];
5820 reload_inherited[r] = 1;
5821 reload_inheritance_insn[r]
5822 = reg_reloaded_insn[i];
5823 reload_spill_index[r] = i;
5824 for (k = 0; k < nr; k++)
5825 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5833 /* Here's another way to see if the value is already lying around. */
5835 && reload_in[r] != 0
5836 && ! reload_inherited[r]
5837 && reload_out[r] == 0
5838 && (CONSTANT_P (reload_in[r])
5839 || GET_CODE (reload_in[r]) == PLUS
5840 || GET_CODE (reload_in[r]) == REG
5841 || GET_CODE (reload_in[r]) == MEM)
5842 && (reload_nregs[r] == max_group_size
5843 || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
5846 = find_equiv_reg (reload_in[r], insn, reload_reg_class[r],
5847 -1, NULL_PTR, 0, reload_mode[r]);
5852 if (GET_CODE (equiv) == REG)
5853 regno = REGNO (equiv);
5854 else if (GET_CODE (equiv) == SUBREG)
5856 /* This must be a SUBREG of a hard register.
5857 Make a new REG since this might be used in an
5858 address and not all machines support SUBREGs
5860 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5861 equiv = gen_rtx_REG (reload_mode[r], regno);
5867 /* If we found a spill reg, reject it unless it is free
5868 and of the desired class. */
5870 && ((spill_reg_order[regno] >= 0
5871 && ! (reload_reg_free_before_p (regno, reload_opnum[r],
5872 reload_when_needed[r], 1)
5873 || reload_reg_free_for_value_p (regno,
5875 reload_when_needed[r],
5878 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5882 if (equiv != 0 && TEST_HARD_REG_BIT (reload_reg_used_at_all, regno))
5885 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5888 /* We found a register that contains the value we need.
5889 If this register is the same as an `earlyclobber' operand
5890 of the current insn, just mark it as a place to reload from
5891 since we can't use it as the reload register itself. */
5894 for (i = 0; i < n_earlyclobbers; i++)
5895 if (reg_overlap_mentioned_for_reload_p (equiv,
5896 reload_earlyclobbers[i]))
5898 reload_override_in[r] = equiv;
5903 /* If the equiv register we have found is explicitly clobbered
5904 in the current insn, it depends on the reload type if we
5905 can use it, use it for reload_override_in, or not at all.
5906 In particular, we then can't use EQUIV for a
5907 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5909 if (equiv != 0 && regno_clobbered_p (regno, insn))
5911 switch (reload_when_needed[r])
5913 case RELOAD_FOR_OTHER_ADDRESS:
5914 case RELOAD_FOR_INPADDR_ADDRESS:
5915 case RELOAD_FOR_INPUT_ADDRESS:
5916 case RELOAD_FOR_OPADDR_ADDR:
5919 case RELOAD_FOR_INPUT:
5920 case RELOAD_FOR_OPERAND_ADDRESS:
5921 reload_override_in[r] = equiv;
5929 /* If we found an equivalent reg, say no code need be generated
5930 to load it, and use it as our reload reg. */
5931 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5933 int nr = HARD_REGNO_NREGS (regno, reload_mode[r]);
5935 reload_reg_rtx[r] = equiv;
5936 reload_inherited[r] = 1;
5938 /* If reg_reloaded_valid is not set for this register,
5939 there might be a stale spill_reg_store lying around.
5940 We must clear it, since otherwise emit_reload_insns
5941 might delete the store. */
5942 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5943 spill_reg_store[regno] = NULL_RTX;
5944 /* If any of the hard registers in EQUIV are spill
5945 registers, mark them as in use for this insn. */
5946 for (k = 0; k < nr; k++)
5948 i = spill_reg_order[regno + k];
5951 mark_reload_reg_in_use (regno, reload_opnum[r],
5952 reload_when_needed[r],
5954 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5961 /* If we found a register to use already, or if this is an optional
5962 reload, we are done. */
5963 if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
5966 #if 0 /* No longer needed for correct operation. Might or might not
5967 give better code on the average. Want to experiment? */
5969 /* See if there is a later reload that has a class different from our
5970 class that intersects our class or that requires less register
5971 than our reload. If so, we must allocate a register to this
5972 reload now, since that reload might inherit a previous reload
5973 and take the only available register in our class. Don't do this
5974 for optional reloads since they will force all previous reloads
5975 to be allocated. Also don't do this for reloads that have been
5978 for (i = j + 1; i < n_reloads; i++)
5980 int s = reload_order[i];
5982 if ((reload_in[s] == 0 && reload_out[s] == 0
5983 && ! reload_secondary_p[s])
5984 || reload_optional[s])
5987 if ((reload_reg_class[s] != reload_reg_class[r]
5988 && reg_classes_intersect_p (reload_reg_class[r],
5989 reload_reg_class[s]))
5990 || reload_nregs[s] < reload_nregs[r])
5997 allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance);
6001 /* Now allocate reload registers for anything non-optional that
6002 didn't get one yet. */
6003 for (j = 0; j < n_reloads; j++)
6005 register int r = reload_order[j];
6007 /* Ignore reloads that got marked inoperative. */
6008 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
6011 /* Skip reloads that already have a register allocated or are
6013 if (reload_reg_rtx[r] != 0 || reload_optional[r])
6016 if (! allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance))
6020 /* If that loop got all the way, we have won. */
6025 /* Loop around and try without any inheritance. */
6026 /* First undo everything done by the failed attempt
6027 to allocate with inheritance. */
6028 bcopy ((char *) save_reload_reg_rtx, (char *) reload_reg_rtx,
6029 sizeof reload_reg_rtx);
6030 bcopy ((char *) save_reload_inherited, (char *) reload_inherited,
6031 sizeof reload_inherited);
6032 bcopy ((char *) save_reload_inheritance_insn,
6033 (char *) reload_inheritance_insn,
6034 sizeof reload_inheritance_insn);
6035 bcopy ((char *) save_reload_override_in, (char *) reload_override_in,
6036 sizeof reload_override_in);
6037 bcopy ((char *) save_reload_spill_index, (char *) reload_spill_index,
6038 sizeof reload_spill_index);
6039 COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
6040 COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
6041 COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
6042 save_reload_reg_used_in_op_addr);
6043 COPY_HARD_REG_SET (reload_reg_used_in_op_addr_reload,
6044 save_reload_reg_used_in_op_addr_reload);
6045 COPY_HARD_REG_SET (reload_reg_used_in_insn,
6046 save_reload_reg_used_in_insn);
6047 COPY_HARD_REG_SET (reload_reg_used_in_other_addr,
6048 save_reload_reg_used_in_other_addr);
6050 for (i = 0; i < reload_n_operands; i++)
6052 COPY_HARD_REG_SET (reload_reg_used_in_input[i],
6053 save_reload_reg_used_in_input[i]);
6054 COPY_HARD_REG_SET (reload_reg_used_in_output[i],
6055 save_reload_reg_used_in_output[i]);
6056 COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i],
6057 save_reload_reg_used_in_input_addr[i]);
6058 COPY_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i],
6059 save_reload_reg_used_in_inpaddr_addr[i]);
6060 COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i],
6061 save_reload_reg_used_in_output_addr[i]);
6062 COPY_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i],
6063 save_reload_reg_used_in_outaddr_addr[i]);
6067 /* If we thought we could inherit a reload, because it seemed that
6068 nothing else wanted the same reload register earlier in the insn,
6069 verify that assumption, now that all reloads have been assigned. */
6071 for (j = 0; j < n_reloads; j++)
6073 register int r = reload_order[j];
6075 if (reload_inherited[r] && reload_reg_rtx[r] != 0
6076 && ! (reload_reg_free_before_p (true_regnum (reload_reg_rtx[r]),
6078 reload_when_needed[r], 0)
6079 || reload_reg_free_for_value_p (true_regnum (reload_reg_rtx[r]),
6081 reload_when_needed[r],
6084 reload_inherited[r] = 0;
6085 /* If we can inherit a RELOAD_FOR_INPUT, then we do not need its related
6086 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads.
6087 ??? This could be extended to other reload types, but these are
6088 more tricky to handle:
6089 RELOAD_FOR_OTHER_ADDRESS reloads might have been merged, so we
6090 can't eliminate them without a check that *all* references are
6091 now unused due to inheritance.
6092 While RELOAD_FOR_INPADDR_ADDRESS and RELOAD_FOR_OUTADDR_ADDRESS are
6093 not merged, we can't be sure that we have eliminated the use of
6094 that particular reload if we have seen just one
6095 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_OUTPUT_ADDRESS being inherited,
6096 since there might be multiple of the latter two reloads for a single
6098 RELOAD_FOR_OPADDR_ADDR reloads for different operands are not
6099 merged, but might share the same register by courtesy of
6100 reload_reg_free_for_value_p. reload_reg_used_in_op_addr_reload
6101 does not differentiate by opnum, thus calling clear_reload_reg_in_use
6102 for one of these reloads would mark the register as free even though
6103 another RELOAD_FOR_OPADDR_ADDR reload might still use it. */
6104 else if (reload_inherited[r] && reload_when_needed[r] == RELOAD_FOR_INPUT)
6106 for (i = 0; i < n_reloads; i++)
6108 if ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
6109 || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS)
6110 && reload_opnum[i] == reload_opnum[r]
6111 && reload_in[i] && reload_reg_rtx[i])
6113 int regno = true_regnum (reload_reg_rtx[i]);
6116 if (spill_reg_order[regno] >= 0)
6117 clear_reload_reg_in_use (regno, reload_opnum[i],
6118 reload_when_needed[i],
6120 reload_reg_rtx[i] = 0;
6121 reload_spill_index[i] = -1;
6122 remove_replacements (i);
6127 /* If we found a better place to reload from,
6128 validate it in the same fashion, if it is a reload reg. */
6129 if (reload_override_in[r]
6130 && (GET_CODE (reload_override_in[r]) == REG
6131 || GET_CODE (reload_override_in[r]) == SUBREG))
6133 int regno = true_regnum (reload_override_in[r]);
6134 if (spill_reg_order[regno] >= 0
6135 && ! reload_reg_free_before_p (regno, reload_opnum[r],
6136 reload_when_needed[r], 1))
6137 reload_override_in[r] = 0;
6141 /* Now that reload_override_in is known valid,
6142 actually override reload_in. */
6143 for (j = 0; j < n_reloads; j++)
6144 if (reload_override_in[j])
6145 reload_in[j] = reload_override_in[j];
6147 /* If this reload won't be done because it has been cancelled or is
6148 optional and not inherited, clear reload_reg_rtx so other
6149 routines (such as subst_reloads) don't get confused. */
6150 for (j = 0; j < n_reloads; j++)
6151 if (reload_reg_rtx[j] != 0
6152 && ((reload_optional[j] && ! reload_inherited[j])
6153 || (reload_in[j] == 0 && reload_out[j] == 0
6154 && ! reload_secondary_p[j])))
6156 int regno = true_regnum (reload_reg_rtx[j]);
6158 if (spill_reg_order[regno] >= 0)
6159 clear_reload_reg_in_use (regno, reload_opnum[j],
6160 reload_when_needed[j], reload_mode[j]);
6161 reload_reg_rtx[j] = 0;
6164 /* Record which pseudos and which spill regs have output reloads. */
6165 for (j = 0; j < n_reloads; j++)
6167 register int r = reload_order[j];
6169 i = reload_spill_index[r];
6171 /* I is nonneg if this reload uses a register.
6172 If reload_reg_rtx[r] is 0, this is an optional reload
6173 that we opted to ignore. */
6174 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG
6175 && reload_reg_rtx[r] != 0)
6177 register int nregno = REGNO (reload_out[r]);
6180 if (nregno < FIRST_PSEUDO_REGISTER)
6181 nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
6184 reg_has_output_reload[nregno + nr] = 1;
6188 nr = HARD_REGNO_NREGS (i, reload_mode[r]);
6190 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6193 if (reload_when_needed[r] != RELOAD_OTHER
6194 && reload_when_needed[r] != RELOAD_FOR_OUTPUT
6195 && reload_when_needed[r] != RELOAD_FOR_INSN)
6201 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
6202 reloads of the same item for fear that we might not have enough reload
6203 registers. However, normally they will get the same reload register
6204 and hence actually need not be loaded twice.
6206 Here we check for the most common case of this phenomenon: when we have
6207 a number of reloads for the same object, each of which were allocated
6208 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6209 reload, and is not modified in the insn itself. If we find such,
6210 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6211 This will not increase the number of spill registers needed and will
6212 prevent redundant code. */
6215 merge_assigned_reloads (insn)
6220 /* Scan all the reloads looking for ones that only load values and
6221 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6222 assigned and not modified by INSN. */
6224 for (i = 0; i < n_reloads; i++)
6226 int conflicting_input = 0;
6227 int max_input_address_opnum = -1;
6228 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6230 if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER
6231 || reload_out[i] != 0 || reload_reg_rtx[i] == 0
6232 || reg_set_p (reload_reg_rtx[i], insn))
6235 /* Look at all other reloads. Ensure that the only use of this
6236 reload_reg_rtx is in a reload that just loads the same value
6237 as we do. Note that any secondary reloads must be of the identical
6238 class since the values, modes, and result registers are the
6239 same, so we need not do anything with any secondary reloads. */
6241 for (j = 0; j < n_reloads; j++)
6243 if (i == j || reload_reg_rtx[j] == 0
6244 || ! reg_overlap_mentioned_p (reload_reg_rtx[j],
6248 if (reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS
6249 && reload_opnum[j] > max_input_address_opnum)
6250 max_input_address_opnum = reload_opnum[j];
6252 /* If the reload regs aren't exactly the same (e.g, different modes)
6253 or if the values are different, we can't merge this reload.
6254 But if it is an input reload, we might still merge
6255 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6257 if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
6258 || reload_out[j] != 0 || reload_in[j] == 0
6259 || ! rtx_equal_p (reload_in[i], reload_in[j]))
6261 if (reload_when_needed[j] != RELOAD_FOR_INPUT
6262 || ((reload_when_needed[i] != RELOAD_FOR_INPUT_ADDRESS
6263 || reload_opnum[i] > reload_opnum[j])
6264 && reload_when_needed[i] != RELOAD_FOR_OTHER_ADDRESS))
6266 conflicting_input = 1;
6267 if (min_conflicting_input_opnum > reload_opnum[j])
6268 min_conflicting_input_opnum = reload_opnum[j];
6272 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6273 we, in fact, found any matching reloads. */
6276 && max_input_address_opnum <= min_conflicting_input_opnum)
6278 for (j = 0; j < n_reloads; j++)
6279 if (i != j && reload_reg_rtx[j] != 0
6280 && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
6281 && (! conflicting_input
6282 || reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS
6283 || reload_when_needed[j] == RELOAD_FOR_OTHER_ADDRESS))
6285 reload_when_needed[i] = RELOAD_OTHER;
6287 reload_spill_index[j] = -1;
6288 transfer_replacements (i, j);
6291 /* If this is now RELOAD_OTHER, look for any reloads that load
6292 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6293 if they were for inputs, RELOAD_OTHER for outputs. Note that
6294 this test is equivalent to looking for reloads for this operand
6297 if (reload_when_needed[i] == RELOAD_OTHER)
6298 for (j = 0; j < n_reloads; j++)
6299 if (reload_in[j] != 0
6300 && reload_when_needed[i] != RELOAD_OTHER
6301 && reg_overlap_mentioned_for_reload_p (reload_in[j],
6303 reload_when_needed[j]
6304 = ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
6305 || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS)
6306 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6312 /* Output insns to reload values in and out of the chosen reload regs. */
6315 emit_reload_insns (insn, bb)
6320 rtx input_reload_insns[MAX_RECOG_OPERANDS];
6321 rtx other_input_address_reload_insns = 0;
6322 rtx other_input_reload_insns = 0;
6323 rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6324 rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6325 rtx output_reload_insns[MAX_RECOG_OPERANDS];
6326 rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6327 rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6328 rtx operand_reload_insns = 0;
6329 rtx other_operand_reload_insns = 0;
6330 rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6331 rtx following_insn = NEXT_INSN (insn);
6332 rtx before_insn = PREV_INSN (insn);
6334 /* Values to be put in spill_reg_store are put here first. */
6335 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6336 HARD_REG_SET reg_reloaded_died;
6338 CLEAR_HARD_REG_SET (reg_reloaded_died);
6340 for (j = 0; j < reload_n_operands; j++)
6341 input_reload_insns[j] = input_address_reload_insns[j]
6342 = inpaddr_address_reload_insns[j]
6343 = output_reload_insns[j] = output_address_reload_insns[j]
6344 = outaddr_address_reload_insns[j]
6345 = other_output_reload_insns[j] = 0;
6347 /* Now output the instructions to copy the data into and out of the
6348 reload registers. Do these in the order that the reloads were reported,
6349 since reloads of base and index registers precede reloads of operands
6350 and the operands may need the base and index registers reloaded. */
6352 for (j = 0; j < n_reloads; j++)
6355 rtx oldequiv_reg = 0;
6356 rtx this_reload_insn = 0;
6357 int expect_occurrences = 1;
6359 if (reload_spill_index[j] >= 0)
6360 new_spill_reg_store[reload_spill_index[j]] = 0;
6363 if (old != 0 && ! reload_inherited[j]
6364 && ! rtx_equal_p (reload_reg_rtx[j], old)
6365 && reload_reg_rtx[j] != 0)
6367 register rtx reloadreg = reload_reg_rtx[j];
6369 enum machine_mode mode;
6372 /* Determine the mode to reload in.
6373 This is very tricky because we have three to choose from.
6374 There is the mode the insn operand wants (reload_inmode[J]).
6375 There is the mode of the reload register RELOADREG.
6376 There is the intrinsic mode of the operand, which we could find
6377 by stripping some SUBREGs.
6378 It turns out that RELOADREG's mode is irrelevant:
6379 we can change that arbitrarily.
6381 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6382 then the reload reg may not support QImode moves, so use SImode.
6383 If foo is in memory due to spilling a pseudo reg, this is safe,
6384 because the QImode value is in the least significant part of a
6385 slot big enough for a SImode. If foo is some other sort of
6386 memory reference, then it is impossible to reload this case,
6387 so previous passes had better make sure this never happens.
6389 Then consider a one-word union which has SImode and one of its
6390 members is a float, being fetched as (SUBREG:SF union:SI).
6391 We must fetch that as SFmode because we could be loading into
6392 a float-only register. In this case OLD's mode is correct.
6394 Consider an immediate integer: it has VOIDmode. Here we need
6395 to get a mode from something else.
6397 In some cases, there is a fourth mode, the operand's
6398 containing mode. If the insn specifies a containing mode for
6399 this operand, it overrides all others.
6401 I am not sure whether the algorithm here is always right,
6402 but it does the right things in those cases. */
6404 mode = GET_MODE (old);
6405 if (mode == VOIDmode)
6406 mode = reload_inmode[j];
6408 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6409 /* If we need a secondary register for this operation, see if
6410 the value is already in a register in that class. Don't
6411 do this if the secondary register will be used as a scratch
6414 if (reload_secondary_in_reload[j] >= 0
6415 && reload_secondary_in_icode[j] == CODE_FOR_nothing
6418 = find_equiv_reg (old, insn,
6419 reload_reg_class[reload_secondary_in_reload[j]],
6420 -1, NULL_PTR, 0, mode);
6423 /* If reloading from memory, see if there is a register
6424 that already holds the same value. If so, reload from there.
6425 We can pass 0 as the reload_reg_p argument because
6426 any other reload has either already been emitted,
6427 in which case find_equiv_reg will see the reload-insn,
6428 or has yet to be emitted, in which case it doesn't matter
6429 because we will use this equiv reg right away. */
6431 if (oldequiv == 0 && optimize
6432 && (GET_CODE (old) == MEM
6433 || (GET_CODE (old) == REG
6434 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6435 && reg_renumber[REGNO (old)] < 0)))
6436 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6437 -1, NULL_PTR, 0, mode);
6441 int regno = true_regnum (oldequiv);
6443 /* If OLDEQUIV is a spill register, don't use it for this
6444 if any other reload needs it at an earlier stage of this insn
6445 or at this stage. */
6446 if (spill_reg_order[regno] >= 0
6447 && (! reload_reg_free_p (regno, reload_opnum[j],
6448 reload_when_needed[j])
6449 || ! reload_reg_free_before_p (regno, reload_opnum[j],
6450 reload_when_needed[j], 1)))
6453 /* If OLDEQUIV is not a spill register,
6454 don't use it if any other reload wants it. */
6455 if (spill_reg_order[regno] < 0)
6458 for (k = 0; k < n_reloads; k++)
6459 if (reload_reg_rtx[k] != 0 && k != j
6460 && reg_overlap_mentioned_for_reload_p (reload_reg_rtx[k],
6468 /* If it is no cheaper to copy from OLDEQUIV into the
6469 reload register than it would be to move from memory,
6470 don't use it. Likewise, if we need a secondary register
6474 && ((REGNO_REG_CLASS (regno) != reload_reg_class[j]
6475 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
6476 reload_reg_class[j])
6477 >= MEMORY_MOVE_COST (mode, reload_reg_class[j], 1)))
6478 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6479 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6483 #ifdef SECONDARY_MEMORY_NEEDED
6484 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6485 reload_reg_class[j],
6494 else if (GET_CODE (oldequiv) == REG)
6495 oldequiv_reg = oldequiv;
6496 else if (GET_CODE (oldequiv) == SUBREG)
6497 oldequiv_reg = SUBREG_REG (oldequiv);
6499 /* If we are reloading from a register that was recently stored in
6500 with an output-reload, see if we can prove there was
6501 actually no need to store the old value in it. */
6503 if (optimize && GET_CODE (oldequiv) == REG
6504 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6505 && spill_reg_store[REGNO (oldequiv)]
6506 && GET_CODE (old) == REG && dead_or_set_p (insn, old)
6507 /* This is unsafe if operand occurs more than once in current
6508 insn. Perhaps some occurrences weren't reloaded. */
6509 && count_occurrences (PATTERN (insn), old) == 1)
6510 delete_output_reload (insn, j, spill_reg_store[REGNO (oldequiv)]);
6512 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6513 then load RELOADREG from OLDEQUIV. Note that we cannot use
6514 gen_lowpart_common since it can do the wrong thing when
6515 RELOADREG has a multi-word mode. Note that RELOADREG
6516 must always be a REG here. */
6518 if (GET_MODE (reloadreg) != mode)
6519 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6520 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6521 oldequiv = SUBREG_REG (oldequiv);
6522 if (GET_MODE (oldequiv) != VOIDmode
6523 && mode != GET_MODE (oldequiv))
6524 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6526 /* Switch to the right place to emit the reload insns. */
6527 switch (reload_when_needed[j])
6530 where = &other_input_reload_insns;
6532 case RELOAD_FOR_INPUT:
6533 where = &input_reload_insns[reload_opnum[j]];
6535 case RELOAD_FOR_INPUT_ADDRESS:
6536 where = &input_address_reload_insns[reload_opnum[j]];
6538 case RELOAD_FOR_INPADDR_ADDRESS:
6539 where = &inpaddr_address_reload_insns[reload_opnum[j]];
6541 case RELOAD_FOR_OUTPUT_ADDRESS:
6542 where = &output_address_reload_insns[reload_opnum[j]];
6544 case RELOAD_FOR_OUTADDR_ADDRESS:
6545 where = &outaddr_address_reload_insns[reload_opnum[j]];
6547 case RELOAD_FOR_OPERAND_ADDRESS:
6548 where = &operand_reload_insns;
6550 case RELOAD_FOR_OPADDR_ADDR:
6551 where = &other_operand_reload_insns;
6553 case RELOAD_FOR_OTHER_ADDRESS:
6554 where = &other_input_address_reload_insns;
6560 push_to_sequence (*where);
6563 /* Auto-increment addresses must be reloaded in a special way. */
6564 if (GET_CODE (oldequiv) == POST_INC
6565 || GET_CODE (oldequiv) == POST_DEC
6566 || GET_CODE (oldequiv) == PRE_INC
6567 || GET_CODE (oldequiv) == PRE_DEC)
6569 /* We are not going to bother supporting the case where a
6570 incremented register can't be copied directly from
6571 OLDEQUIV since this seems highly unlikely. */
6572 if (reload_secondary_in_reload[j] >= 0)
6574 /* Prevent normal processing of this reload. */
6576 /* Output a special code sequence for this case. */
6577 inc_for_reload (reloadreg, oldequiv, reload_inc[j]);
6580 /* If we are reloading a pseudo-register that was set by the previous
6581 insn, see if we can get rid of that pseudo-register entirely
6582 by redirecting the previous insn into our reload register. */
6584 else if (optimize && GET_CODE (old) == REG
6585 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6586 && dead_or_set_p (insn, old)
6587 /* This is unsafe if some other reload
6588 uses the same reg first. */
6589 && reload_reg_free_before_p (REGNO (reloadreg),
6591 reload_when_needed[j], 0))
6593 rtx temp = PREV_INSN (insn);
6594 while (temp && GET_CODE (temp) == NOTE)
6595 temp = PREV_INSN (temp);
6597 && GET_CODE (temp) == INSN
6598 && GET_CODE (PATTERN (temp)) == SET
6599 && SET_DEST (PATTERN (temp)) == old
6600 /* Make sure we can access insn_operand_constraint. */
6601 && asm_noperands (PATTERN (temp)) < 0
6602 /* This is unsafe if prev insn rejects our reload reg. */
6603 && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
6605 /* This is unsafe if operand occurs more than once in current
6606 insn. Perhaps some occurrences aren't reloaded. */
6607 && count_occurrences (PATTERN (insn), old) == 1
6608 /* Don't risk splitting a matching pair of operands. */
6609 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6611 /* Store into the reload register instead of the pseudo. */
6612 SET_DEST (PATTERN (temp)) = reloadreg;
6613 /* If these are the only uses of the pseudo reg,
6614 pretend for GDB it lives in the reload reg we used. */
6615 if (REG_N_DEATHS (REGNO (old)) == 1
6616 && REG_N_SETS (REGNO (old)) == 1)
6618 reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
6619 alter_reg (REGNO (old), -1);
6625 /* We can't do that, so output an insn to load RELOADREG. */
6629 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6630 rtx second_reload_reg = 0;
6631 enum insn_code icode;
6633 /* If we have a secondary reload, pick up the secondary register
6634 and icode, if any. If OLDEQUIV and OLD are different or
6635 if this is an in-out reload, recompute whether or not we
6636 still need a secondary register and what the icode should
6637 be. If we still need a secondary register and the class or
6638 icode is different, go back to reloading from OLD if using
6639 OLDEQUIV means that we got the wrong type of register. We
6640 cannot have different class or icode due to an in-out reload
6641 because we don't make such reloads when both the input and
6642 output need secondary reload registers. */
6644 if (reload_secondary_in_reload[j] >= 0)
6646 int secondary_reload = reload_secondary_in_reload[j];
6647 rtx real_oldequiv = oldequiv;
6650 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6651 and similarly for OLD.
6652 See comments in get_secondary_reload in reload.c. */
6653 if (GET_CODE (oldequiv) == REG
6654 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6655 && reg_equiv_mem[REGNO (oldequiv)] != 0)
6656 real_oldequiv = reg_equiv_mem[REGNO (oldequiv)];
6658 if (GET_CODE (old) == REG
6659 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6660 && reg_equiv_mem[REGNO (old)] != 0)
6661 real_old = reg_equiv_mem[REGNO (old)];
6663 second_reload_reg = reload_reg_rtx[secondary_reload];
6664 icode = reload_secondary_in_icode[j];
6666 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6667 || (reload_in[j] != 0 && reload_out[j] != 0))
6669 enum reg_class new_class
6670 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6671 mode, real_oldequiv);
6673 if (new_class == NO_REGS)
6674 second_reload_reg = 0;
6677 enum insn_code new_icode;
6678 enum machine_mode new_mode;
6680 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6681 REGNO (second_reload_reg)))
6682 oldequiv = old, real_oldequiv = real_old;
6685 new_icode = reload_in_optab[(int) mode];
6686 if (new_icode != CODE_FOR_nothing
6687 && ((insn_operand_predicate[(int) new_icode][0]
6688 && ! ((*insn_operand_predicate[(int) new_icode][0])
6690 || (insn_operand_predicate[(int) new_icode][1]
6691 && ! ((*insn_operand_predicate[(int) new_icode][1])
6692 (real_oldequiv, mode)))))
6693 new_icode = CODE_FOR_nothing;
6695 if (new_icode == CODE_FOR_nothing)
6698 new_mode = insn_operand_mode[(int) new_icode][2];
6700 if (GET_MODE (second_reload_reg) != new_mode)
6702 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6704 oldequiv = old, real_oldequiv = real_old;
6707 = gen_rtx_REG (new_mode,
6708 REGNO (second_reload_reg));
6714 /* If we still need a secondary reload register, check
6715 to see if it is being used as a scratch or intermediate
6716 register and generate code appropriately. If we need
6717 a scratch register, use REAL_OLDEQUIV since the form of
6718 the insn may depend on the actual address if it is
6721 if (second_reload_reg)
6723 if (icode != CODE_FOR_nothing)
6725 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6726 second_reload_reg));
6731 /* See if we need a scratch register to load the
6732 intermediate register (a tertiary reload). */
6733 enum insn_code tertiary_icode
6734 = reload_secondary_in_icode[secondary_reload];
6736 if (tertiary_icode != CODE_FOR_nothing)
6738 rtx third_reload_reg
6739 = reload_reg_rtx[reload_secondary_in_reload[secondary_reload]];
6741 emit_insn ((GEN_FCN (tertiary_icode)
6742 (second_reload_reg, real_oldequiv,
6743 third_reload_reg)));
6746 gen_reload (second_reload_reg, oldequiv,
6748 reload_when_needed[j]);
6750 oldequiv = second_reload_reg;
6756 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6757 gen_reload (reloadreg, oldequiv, reload_opnum[j],
6758 reload_when_needed[j]);
6760 #if defined(SECONDARY_INPUT_RELOAD_CLASS) && defined(PRESERVE_DEATH_INFO_REGNO_P)
6761 /* We may have to make a REG_DEAD note for the secondary reload
6762 register in the insns we just made. Find the last insn that
6763 mentioned the register. */
6764 if (! special && second_reload_reg
6765 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reload_reg)))
6769 for (prev = get_last_insn (); prev;
6770 prev = PREV_INSN (prev))
6771 if (GET_RTX_CLASS (GET_CODE (prev) == 'i')
6772 && reg_overlap_mentioned_for_reload_p (second_reload_reg,
6775 REG_NOTES (prev) = gen_rtx_EXPR_LIST (REG_DEAD,
6784 this_reload_insn = get_last_insn ();
6785 /* End this sequence. */
6786 *where = get_insns ();
6790 /* When inheriting a wider reload, we have a MEM in reload_in[j],
6791 e.g. inheriting a SImode output reload for
6792 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6793 if (optimize && reload_inherited[j] && reload_in[j]
6794 && GET_CODE (reload_in[j]) == MEM
6795 && reload_spill_index[j] >= 0
6796 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6799 = count_occurrences (PATTERN (insn), reload_in[j]) == 1 ? 0 : -1;
6801 = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6803 /* Add a note saying the input reload reg
6804 dies in this insn, if anyone cares. */
6805 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6807 && reload_reg_rtx[j] != old
6808 && reload_reg_rtx[j] != 0
6809 && reload_out[j] == 0
6810 && ! reload_inherited[j]
6811 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j])))
6813 register rtx reloadreg = reload_reg_rtx[j];
6816 /* We can't abort here because we need to support this for sched.c.
6817 It's not terrible to miss a REG_DEAD note, but we should try
6818 to figure out how to do this correctly. */
6819 /* The code below is incorrect for address-only reloads. */
6820 if (reload_when_needed[j] != RELOAD_OTHER
6821 && reload_when_needed[j] != RELOAD_FOR_INPUT)
6825 /* Add a death note to this insn, for an input reload. */
6827 if ((reload_when_needed[j] == RELOAD_OTHER
6828 || reload_when_needed[j] == RELOAD_FOR_INPUT)
6829 && ! dead_or_set_p (insn, reloadreg))
6831 = gen_rtx_EXPR_LIST (REG_DEAD,
6832 reloadreg, REG_NOTES (insn));
6835 /* When we inherit a reload, the last marked death of the reload reg
6836 may no longer really be a death. */
6837 if (reload_reg_rtx[j] != 0
6838 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j]))
6839 && reload_inherited[j])
6841 /* Handle inheriting an output reload.
6842 Remove the death note from the output reload insn. */
6843 if (reload_spill_index[j] >= 0
6844 && GET_CODE (reload_in[j]) == REG
6845 && spill_reg_store[reload_spill_index[j]] != 0
6846 && find_regno_note (spill_reg_store[reload_spill_index[j]],
6847 REG_DEAD, REGNO (reload_reg_rtx[j])))
6848 remove_death (REGNO (reload_reg_rtx[j]),
6849 spill_reg_store[reload_spill_index[j]]);
6850 /* Likewise for input reloads that were inherited. */
6851 else if (reload_spill_index[j] >= 0
6852 && GET_CODE (reload_in[j]) == REG
6853 && spill_reg_store[reload_spill_index[j]] == 0
6854 && reload_inheritance_insn[j] != 0
6855 && find_regno_note (reload_inheritance_insn[j], REG_DEAD,
6856 REGNO (reload_reg_rtx[j])))
6857 remove_death (REGNO (reload_reg_rtx[j]),
6858 reload_inheritance_insn[j]);
6863 /* We got this register from find_equiv_reg.
6864 Search back for its last death note and get rid of it.
6865 But don't search back too far.
6866 Don't go past a place where this reg is set,
6867 since a death note before that remains valid. */
6868 for (prev = PREV_INSN (insn);
6869 prev && GET_CODE (prev) != CODE_LABEL;
6870 prev = PREV_INSN (prev))
6871 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
6872 && dead_or_set_p (prev, reload_reg_rtx[j]))
6874 if (find_regno_note (prev, REG_DEAD,
6875 REGNO (reload_reg_rtx[j])))
6876 remove_death (REGNO (reload_reg_rtx[j]), prev);
6882 /* We might have used find_equiv_reg above to choose an alternate
6883 place from which to reload. If so, and it died, we need to remove
6884 that death and move it to one of the insns we just made. */
6886 if (oldequiv_reg != 0
6887 && PRESERVE_DEATH_INFO_REGNO_P (true_regnum (oldequiv_reg)))
6891 for (prev = PREV_INSN (insn); prev && GET_CODE (prev) != CODE_LABEL;
6892 prev = PREV_INSN (prev))
6893 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
6894 && dead_or_set_p (prev, oldequiv_reg))
6896 if (find_regno_note (prev, REG_DEAD, REGNO (oldequiv_reg)))
6898 for (prev1 = this_reload_insn;
6899 prev1; prev1 = PREV_INSN (prev1))
6900 if (GET_RTX_CLASS (GET_CODE (prev1) == 'i')
6901 && reg_overlap_mentioned_for_reload_p (oldequiv_reg,
6904 REG_NOTES (prev1) = gen_rtx_EXPR_LIST (REG_DEAD,
6909 remove_death (REGNO (oldequiv_reg), prev);
6916 /* If we are reloading a register that was recently stored in with an
6917 output-reload, see if we can prove there was
6918 actually no need to store the old value in it. */
6920 if (optimize && reload_inherited[j] && reload_spill_index[j] >= 0
6921 && reload_in[j] != 0
6922 && GET_CODE (reload_in[j]) == REG
6924 /* There doesn't seem to be any reason to restrict this to pseudos
6925 and doing so loses in the case where we are copying from a
6926 register of the wrong class. */
6927 && REGNO (reload_in[j]) >= FIRST_PSEUDO_REGISTER
6929 && spill_reg_store[reload_spill_index[j]] != 0
6930 /* This is unsafe if some other reload uses the same reg first. */
6931 && reload_reg_free_before_p (reload_spill_index[j],
6932 reload_opnum[j], reload_when_needed[j],
6934 && dead_or_set_p (insn, reload_in[j])
6935 /* This is unsafe if operand occurs more than once in current
6936 insn. Perhaps some occurrences weren't reloaded. */
6937 && (count_occurrences (PATTERN (insn), reload_in[j])
6938 == expect_occurrences))
6939 delete_output_reload (insn, j,
6940 spill_reg_store[reload_spill_index[j]]);
6942 /* Input-reloading is done. Now do output-reloading,
6943 storing the value from the reload-register after the main insn
6944 if reload_out[j] is nonzero.
6946 ??? At some point we need to support handling output reloads of
6947 JUMP_INSNs or insns that set cc0. */
6948 old = reload_out[j];
6950 && reload_reg_rtx[j] != old
6951 && reload_reg_rtx[j] != 0)
6953 register rtx reloadreg = reload_reg_rtx[j];
6954 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6955 register rtx second_reloadreg = 0;
6958 enum machine_mode mode;
6961 /* An output operand that dies right away does need a reload,
6962 but need not be copied from it. Show the new location in the
6964 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6965 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6967 XEXP (note, 0) = reload_reg_rtx[j];
6970 /* Likewise for a SUBREG of an operand that dies. */
6971 else if (GET_CODE (old) == SUBREG
6972 && GET_CODE (SUBREG_REG (old)) == REG
6973 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6976 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6980 else if (GET_CODE (old) == SCRATCH)
6981 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6982 but we don't want to make an output reload. */
6986 /* Strip off of OLD any size-increasing SUBREGs such as
6987 (SUBREG:SI foo:QI 0). */
6989 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
6990 && (GET_MODE_SIZE (GET_MODE (old))
6991 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
6992 old = SUBREG_REG (old);
6995 /* If is a JUMP_INSN, we can't support output reloads yet. */
6996 if (GET_CODE (insn) == JUMP_INSN)
6999 if (reload_when_needed[j] == RELOAD_OTHER)
7002 push_to_sequence (output_reload_insns[reload_opnum[j]]);
7004 /* Determine the mode to reload in.
7005 See comments above (for input reloading). */
7007 mode = GET_MODE (old);
7008 if (mode == VOIDmode)
7010 /* VOIDmode should never happen for an output. */
7011 if (asm_noperands (PATTERN (insn)) < 0)
7012 /* It's the compiler's fault. */
7013 fatal_insn ("VOIDmode on an output", insn);
7014 error_for_asm (insn, "output operand is constant in `asm'");
7015 /* Prevent crash--use something we know is valid. */
7017 old = gen_rtx_REG (mode, REGNO (reloadreg));
7020 if (GET_MODE (reloadreg) != mode)
7021 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
7023 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7025 /* If we need two reload regs, set RELOADREG to the intermediate
7026 one, since it will be stored into OLD. We might need a secondary
7027 register only for an input reload, so check again here. */
7029 if (reload_secondary_out_reload[j] >= 0)
7033 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
7034 && reg_equiv_mem[REGNO (old)] != 0)
7035 real_old = reg_equiv_mem[REGNO (old)];
7037 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
7041 second_reloadreg = reloadreg;
7042 reloadreg = reload_reg_rtx[reload_secondary_out_reload[j]];
7044 /* See if RELOADREG is to be used as a scratch register
7045 or as an intermediate register. */
7046 if (reload_secondary_out_icode[j] != CODE_FOR_nothing)
7048 emit_insn ((GEN_FCN (reload_secondary_out_icode[j])
7049 (real_old, second_reloadreg, reloadreg)));
7054 /* See if we need both a scratch and intermediate reload
7057 int secondary_reload = reload_secondary_out_reload[j];
7058 enum insn_code tertiary_icode
7059 = reload_secondary_out_icode[secondary_reload];
7061 if (GET_MODE (reloadreg) != mode)
7062 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
7064 if (tertiary_icode != CODE_FOR_nothing)
7067 = reload_reg_rtx[reload_secondary_out_reload[secondary_reload]];
7070 /* Copy primary reload reg to secondary reload reg.
7071 (Note that these have been swapped above, then
7072 secondary reload reg to OLD using our insn. */
7074 /* If REAL_OLD is a paradoxical SUBREG, remove it
7075 and try to put the opposite SUBREG on
7077 if (GET_CODE (real_old) == SUBREG
7078 && (GET_MODE_SIZE (GET_MODE (real_old))
7079 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7080 && 0 != (tem = gen_lowpart_common
7081 (GET_MODE (SUBREG_REG (real_old)),
7083 real_old = SUBREG_REG (real_old), reloadreg = tem;
7085 gen_reload (reloadreg, second_reloadreg,
7086 reload_opnum[j], reload_when_needed[j]);
7087 emit_insn ((GEN_FCN (tertiary_icode)
7088 (real_old, reloadreg, third_reloadreg)));
7093 /* Copy between the reload regs here and then to
7096 gen_reload (reloadreg, second_reloadreg,
7097 reload_opnum[j], reload_when_needed[j]);
7103 /* Output the last reload insn. */
7108 /* Don't output the last reload if OLD is not the dest of
7109 INSN and is in the src and is clobbered by INSN. */
7110 if (! flag_expensive_optimizations
7111 || GET_CODE (old) != REG
7112 || !(set = single_set (insn))
7113 || rtx_equal_p (old, SET_DEST (set))
7114 || !reg_mentioned_p (old, SET_SRC (set))
7115 || !regno_clobbered_p (REGNO (old), insn))
7116 gen_reload (old, reloadreg, reload_opnum[j],
7117 reload_when_needed[j]);
7120 #ifdef PRESERVE_DEATH_INFO_REGNO_P
7121 /* If final will look at death notes for this reg,
7122 put one on the last output-reload insn to use it. Similarly
7123 for any secondary register. */
7124 if (PRESERVE_DEATH_INFO_REGNO_P (REGNO (reloadreg)))
7125 for (p = get_last_insn (); p; p = PREV_INSN (p))
7126 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
7127 && reg_overlap_mentioned_for_reload_p (reloadreg,
7129 REG_NOTES (p) = gen_rtx_EXPR_LIST (REG_DEAD,
7130 reloadreg, REG_NOTES (p));
7132 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7133 if (! special && second_reloadreg
7134 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reloadreg)))
7135 for (p = get_last_insn (); p; p = PREV_INSN (p))
7136 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
7137 && reg_overlap_mentioned_for_reload_p (second_reloadreg,
7139 REG_NOTES (p) = gen_rtx_EXPR_LIST (REG_DEAD,
7144 /* Look at all insns we emitted, just to be safe. */
7145 for (p = get_insns (); p; p = NEXT_INSN (p))
7146 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
7148 rtx pat = PATTERN (p);
7150 /* If this output reload doesn't come from a spill reg,
7151 clear any memory of reloaded copies of the pseudo reg.
7152 If this output reload comes from a spill reg,
7153 reg_has_output_reload will make this do nothing. */
7154 note_stores (pat, forget_old_reloads_1);
7156 if (reg_mentioned_p (reload_reg_rtx[j], pat))
7158 if (reload_spill_index[j] < 0
7159 && GET_CODE (pat) == SET
7160 && SET_SRC (pat) == reload_reg_rtx[j])
7162 int src = REGNO (SET_SRC (pat));
7164 reload_spill_index[j] = src;
7165 SET_HARD_REG_BIT (reg_is_output_reload, src);
7166 if (find_regno_note (insn, REG_DEAD, src))
7167 SET_HARD_REG_BIT (reg_reloaded_died, src);
7169 if (reload_spill_index[j] >= 0)
7171 int s = reload_secondary_out_reload[j];
7172 rtx set = single_set (p);
7173 /* If this reload copies only to the secondary reload
7174 register, the secondary reload does the actual
7176 if (s >= 0 && set == NULL_RTX)
7177 ; /* We can't tell what function the secondary reload
7178 has and where the actual store to the pseudo is
7179 made; leave new_spill_reg_store alone. */
7181 && SET_SRC (set) == reload_reg_rtx[j]
7182 && SET_DEST (set) == reload_reg_rtx[s])
7184 /* Usually the next instruction will be the
7185 secondary reload insn; if we can confirm
7186 that it is, setting new_spill_reg_store to
7187 that insn will allow an extra optimization. */
7188 rtx s_reg = reload_reg_rtx[s];
7189 rtx next = NEXT_INSN (p);
7190 reload_out[s] = reload_out[j];
7191 set = single_set (next);
7192 if (set && SET_SRC (set) == s_reg
7193 && ! new_spill_reg_store[REGNO (s_reg)])
7194 new_spill_reg_store[REGNO (s_reg)] = next;
7197 new_spill_reg_store[reload_spill_index[j]] = p;
7202 if (reload_when_needed[j] == RELOAD_OTHER)
7204 emit_insns (other_output_reload_insns[reload_opnum[j]]);
7205 other_output_reload_insns[reload_opnum[j]] = get_insns ();
7208 output_reload_insns[reload_opnum[j]] = get_insns ();
7214 /* Now write all the insns we made for reloads in the order expected by
7215 the allocation functions. Prior to the insn being reloaded, we write
7216 the following reloads:
7218 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7220 RELOAD_OTHER reloads.
7222 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7223 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7224 RELOAD_FOR_INPUT reload for the operand.
7226 RELOAD_FOR_OPADDR_ADDRS reloads.
7228 RELOAD_FOR_OPERAND_ADDRESS reloads.
7230 After the insn being reloaded, we write the following:
7232 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7233 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7234 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7235 reloads for the operand. The RELOAD_OTHER output reloads are
7236 output in descending order by reload number. */
7238 emit_insns_before (other_input_address_reload_insns, insn);
7239 emit_insns_before (other_input_reload_insns, insn);
7241 for (j = 0; j < reload_n_operands; j++)
7243 emit_insns_before (inpaddr_address_reload_insns[j], insn);
7244 emit_insns_before (input_address_reload_insns[j], insn);
7245 emit_insns_before (input_reload_insns[j], insn);
7248 emit_insns_before (other_operand_reload_insns, insn);
7249 emit_insns_before (operand_reload_insns, insn);
7251 for (j = 0; j < reload_n_operands; j++)
7253 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
7254 emit_insns_before (output_address_reload_insns[j], following_insn);
7255 emit_insns_before (output_reload_insns[j], following_insn);
7256 emit_insns_before (other_output_reload_insns[j], following_insn);
7259 /* Keep basic block info up to date. */
7262 if (basic_block_head[bb] == insn)
7263 basic_block_head[bb] = NEXT_INSN (before_insn);
7264 if (basic_block_end[bb] == insn)
7265 basic_block_end[bb] = PREV_INSN (following_insn);
7268 /* Move death notes from INSN
7269 to output-operand-address and output reload insns. */
7270 #ifdef PRESERVE_DEATH_INFO_REGNO_P
7273 /* Loop over those insns, last ones first. */
7274 for (insn1 = PREV_INSN (following_insn); insn1 != insn;
7275 insn1 = PREV_INSN (insn1))
7276 if (GET_CODE (insn1) == INSN && GET_CODE (PATTERN (insn1)) == SET)
7278 rtx source = SET_SRC (PATTERN (insn1));
7279 rtx dest = SET_DEST (PATTERN (insn1));
7281 /* The note we will examine next. */
7282 rtx reg_notes = REG_NOTES (insn);
7283 /* The place that pointed to this note. */
7284 rtx *prev_reg_note = ®_NOTES (insn);
7286 /* If the note is for something used in the source of this
7287 reload insn, or in the output address, move the note. */
7290 rtx next_reg_notes = XEXP (reg_notes, 1);
7291 if (REG_NOTE_KIND (reg_notes) == REG_DEAD
7292 && GET_CODE (XEXP (reg_notes, 0)) == REG
7293 && ((GET_CODE (dest) != REG
7294 && reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
7296 || reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
7299 *prev_reg_note = next_reg_notes;
7300 XEXP (reg_notes, 1) = REG_NOTES (insn1);
7301 REG_NOTES (insn1) = reg_notes;
7304 prev_reg_note = &XEXP (reg_notes, 1);
7306 reg_notes = next_reg_notes;
7312 /* For all the spill regs newly reloaded in this instruction,
7313 record what they were reloaded from, so subsequent instructions
7314 can inherit the reloads.
7316 Update spill_reg_store for the reloads of this insn.
7317 Copy the elements that were updated in the loop above. */
7319 for (j = 0; j < n_reloads; j++)
7321 register int r = reload_order[j];
7322 register int i = reload_spill_index[r];
7324 /* I is nonneg if this reload used a register.
7325 If reload_reg_rtx[r] is 0, this is an optional reload
7326 that we opted to ignore. */
7328 if (i >= 0 && reload_reg_rtx[r] != 0)
7331 = HARD_REGNO_NREGS (i, GET_MODE (reload_reg_rtx[r]));
7333 int part_reaches_end = 0;
7334 int all_reaches_end = 1;
7336 /* For a multi register reload, we need to check if all or part
7337 of the value lives to the end. */
7338 for (k = 0; k < nr; k++)
7340 if (reload_reg_reaches_end_p (i + k, reload_opnum[r],
7341 reload_when_needed[r]))
7342 part_reaches_end = 1;
7344 all_reaches_end = 0;
7347 /* Ignore reloads that don't reach the end of the insn in
7349 if (all_reaches_end)
7351 /* First, clear out memory of what used to be in this spill reg.
7352 If consecutive registers are used, clear them all. */
7354 for (k = 0; k < nr; k++)
7355 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7357 /* Maybe the spill reg contains a copy of reload_out. */
7358 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
7360 register int nregno = REGNO (reload_out[r]);
7361 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7362 : HARD_REGNO_NREGS (nregno,
7363 GET_MODE (reload_reg_rtx[r])));
7365 spill_reg_store[i] = new_spill_reg_store[i];
7366 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
7368 /* If NREGNO is a hard register, it may occupy more than
7369 one register. If it does, say what is in the
7370 rest of the registers assuming that both registers
7371 agree on how many words the object takes. If not,
7372 invalidate the subsequent registers. */
7374 if (nregno < FIRST_PSEUDO_REGISTER)
7375 for (k = 1; k < nnr; k++)
7376 reg_last_reload_reg[nregno + k]
7378 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
7379 REGNO (reload_reg_rtx[r]) + k)
7382 /* Now do the inverse operation. */
7383 for (k = 0; k < nr; k++)
7385 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7386 reg_reloaded_contents[i + k]
7387 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7390 reg_reloaded_insn[i + k] = insn;
7391 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7395 /* Maybe the spill reg contains a copy of reload_in. Only do
7396 something if there will not be an output reload for
7397 the register being reloaded. */
7398 else if (reload_out[r] == 0
7399 && reload_in[r] != 0
7400 && spill_reg_order[i] >= 0
7401 && ((GET_CODE (reload_in[r]) == REG
7402 && ! reg_has_output_reload[REGNO (reload_in[r])])
7403 || (GET_CODE (reload_in_reg[r]) == REG
7404 && ! reg_has_output_reload[REGNO (reload_in_reg[r])])))
7406 register int nregno;
7409 if (GET_CODE (reload_in[r]) == REG)
7410 nregno = REGNO (reload_in[r]);
7412 nregno = REGNO (reload_in_reg[r]);
7414 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7415 : HARD_REGNO_NREGS (nregno,
7416 GET_MODE (reload_reg_rtx[r])));
7418 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
7420 if (nregno < FIRST_PSEUDO_REGISTER)
7421 for (k = 1; k < nnr; k++)
7422 reg_last_reload_reg[nregno + k]
7424 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
7425 REGNO (reload_reg_rtx[r]) + k)
7428 /* Unless we inherited this reload, show we haven't
7429 recently done a store. */
7430 if (! reload_inherited[r])
7431 spill_reg_store[i] = 0;
7433 for (k = 0; k < nr; k++)
7435 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7436 reg_reloaded_contents[i + k]
7437 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7440 reg_reloaded_insn[i + k] = insn;
7441 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7446 /* However, if part of the reload reaches the end, then we must
7447 invalidate the old info for the part that survives to the end. */
7448 else if (part_reaches_end)
7450 for (k = 0; k < nr; k++)
7451 if (reload_reg_reaches_end_p (i + k,
7453 reload_when_needed[r]))
7454 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7458 /* The following if-statement was #if 0'd in 1.34 (or before...).
7459 It's reenabled in 1.35 because supposedly nothing else
7460 deals with this problem. */
7462 /* If a register gets output-reloaded from a non-spill register,
7463 that invalidates any previous reloaded copy of it.
7464 But forget_old_reloads_1 won't get to see it, because
7465 it thinks only about the original insn. So invalidate it here. */
7466 if (i < 0 && reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
7468 register int nregno = REGNO (reload_out[r]);
7469 if (nregno >= FIRST_PSEUDO_REGISTER)
7470 reg_last_reload_reg[nregno] = 0;
7473 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (reload_out[r]));
7475 while (num_regs-- > 0)
7476 reg_last_reload_reg[nregno + num_regs] = 0;
7480 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7483 /* Emit code to perform a reload from IN (which may be a reload register) to
7484 OUT (which may also be a reload register). IN or OUT is from operand
7485 OPNUM with reload type TYPE.
7487 Returns first insn emitted. */
7490 gen_reload (out, in, opnum, type)
7494 enum reload_type type;
7496 rtx last = get_last_insn ();
7499 /* If IN is a paradoxical SUBREG, remove it and try to put the
7500 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7501 if (GET_CODE (in) == SUBREG
7502 && (GET_MODE_SIZE (GET_MODE (in))
7503 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7504 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7505 in = SUBREG_REG (in), out = tem;
7506 else if (GET_CODE (out) == SUBREG
7507 && (GET_MODE_SIZE (GET_MODE (out))
7508 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7509 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7510 out = SUBREG_REG (out), in = tem;
7512 /* How to do this reload can get quite tricky. Normally, we are being
7513 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7514 register that didn't get a hard register. In that case we can just
7515 call emit_move_insn.
7517 We can also be asked to reload a PLUS that adds a register or a MEM to
7518 another register, constant or MEM. This can occur during frame pointer
7519 elimination and while reloading addresses. This case is handled by
7520 trying to emit a single insn to perform the add. If it is not valid,
7521 we use a two insn sequence.
7523 Finally, we could be called to handle an 'o' constraint by putting
7524 an address into a register. In that case, we first try to do this
7525 with a named pattern of "reload_load_address". If no such pattern
7526 exists, we just emit a SET insn and hope for the best (it will normally
7527 be valid on machines that use 'o').
7529 This entire process is made complex because reload will never
7530 process the insns we generate here and so we must ensure that
7531 they will fit their constraints and also by the fact that parts of
7532 IN might be being reloaded separately and replaced with spill registers.
7533 Because of this, we are, in some sense, just guessing the right approach
7534 here. The one listed above seems to work.
7536 ??? At some point, this whole thing needs to be rethought. */
7538 if (GET_CODE (in) == PLUS
7539 && (GET_CODE (XEXP (in, 0)) == REG
7540 || GET_CODE (XEXP (in, 0)) == SUBREG
7541 || GET_CODE (XEXP (in, 0)) == MEM)
7542 && (GET_CODE (XEXP (in, 1)) == REG
7543 || GET_CODE (XEXP (in, 1)) == SUBREG
7544 || CONSTANT_P (XEXP (in, 1))
7545 || GET_CODE (XEXP (in, 1)) == MEM))
7547 /* We need to compute the sum of a register or a MEM and another
7548 register, constant, or MEM, and put it into the reload
7549 register. The best possible way of doing this is if the machine
7550 has a three-operand ADD insn that accepts the required operands.
7552 The simplest approach is to try to generate such an insn and see if it
7553 is recognized and matches its constraints. If so, it can be used.
7555 It might be better not to actually emit the insn unless it is valid,
7556 but we need to pass the insn as an operand to `recog' and
7557 `insn_extract' and it is simpler to emit and then delete the insn if
7558 not valid than to dummy things up. */
7560 rtx op0, op1, tem, insn;
7563 op0 = find_replacement (&XEXP (in, 0));
7564 op1 = find_replacement (&XEXP (in, 1));
7566 /* Since constraint checking is strict, commutativity won't be
7567 checked, so we need to do that here to avoid spurious failure
7568 if the add instruction is two-address and the second operand
7569 of the add is the same as the reload reg, which is frequently
7570 the case. If the insn would be A = B + A, rearrange it so
7571 it will be A = A + B as constrain_operands expects. */
7573 if (GET_CODE (XEXP (in, 1)) == REG
7574 && REGNO (out) == REGNO (XEXP (in, 1)))
7575 tem = op0, op0 = op1, op1 = tem;
7577 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7578 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7580 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7581 code = recog_memoized (insn);
7585 insn_extract (insn);
7586 /* We want constrain operands to treat this insn strictly in
7587 its validity determination, i.e., the way it would after reload
7589 if (constrain_operands (code, 1))
7593 delete_insns_since (last);
7595 /* If that failed, we must use a conservative two-insn sequence.
7596 use move to copy constant, MEM, or pseudo register to the reload
7597 register since "move" will be able to handle an arbitrary operand,
7598 unlike add which can't, in general. Then add the registers.
7600 If there is another way to do this for a specific machine, a
7601 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7604 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7605 || (GET_CODE (op1) == REG
7606 && REGNO (op1) >= FIRST_PSEUDO_REGISTER))
7607 tem = op0, op0 = op1, op1 = tem;
7609 gen_reload (out, op0, opnum, type);
7611 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7612 This fixes a problem on the 32K where the stack pointer cannot
7613 be used as an operand of an add insn. */
7615 if (rtx_equal_p (op0, op1))
7618 insn = emit_insn (gen_add2_insn (out, op1));
7620 /* If that failed, copy the address register to the reload register.
7621 Then add the constant to the reload register. */
7623 code = recog_memoized (insn);
7627 insn_extract (insn);
7628 /* We want constrain operands to treat this insn strictly in
7629 its validity determination, i.e., the way it would after reload
7631 if (constrain_operands (code, 1))
7633 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7635 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7640 delete_insns_since (last);
7642 gen_reload (out, op1, opnum, type);
7643 insn = emit_insn (gen_add2_insn (out, op0));
7644 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7647 #ifdef SECONDARY_MEMORY_NEEDED
7648 /* If we need a memory location to do the move, do it that way. */
7649 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7650 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7651 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7652 REGNO_REG_CLASS (REGNO (out)),
7655 /* Get the memory to use and rewrite both registers to its mode. */
7656 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7658 if (GET_MODE (loc) != GET_MODE (out))
7659 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7661 if (GET_MODE (loc) != GET_MODE (in))
7662 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7664 gen_reload (loc, in, opnum, type);
7665 gen_reload (out, loc, opnum, type);
7669 /* If IN is a simple operand, use gen_move_insn. */
7670 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7671 emit_insn (gen_move_insn (out, in));
7673 #ifdef HAVE_reload_load_address
7674 else if (HAVE_reload_load_address)
7675 emit_insn (gen_reload_load_address (out, in));
7678 /* Otherwise, just write (set OUT IN) and hope for the best. */
7680 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7682 /* Return the first insn emitted.
7683 We can not just return get_last_insn, because there may have
7684 been multiple instructions emitted. Also note that gen_move_insn may
7685 emit more than one insn itself, so we can not assume that there is one
7686 insn emitted per emit_insn_before call. */
7688 return last ? NEXT_INSN (last) : get_insns ();
7691 /* Delete a previously made output-reload
7692 whose result we now believe is not needed.
7693 First we double-check.
7695 INSN is the insn now being processed.
7696 OUTPUT_RELOAD_INSN is the insn of the output reload.
7697 J is the reload-number for this insn. */
7700 delete_output_reload (insn, j, output_reload_insn)
7703 rtx output_reload_insn;
7707 /* Get the raw pseudo-register referred to. */
7709 rtx reg = reload_in[j];
7710 while (GET_CODE (reg) == SUBREG)
7711 reg = SUBREG_REG (reg);
7713 /* If the pseudo-reg we are reloading is no longer referenced
7714 anywhere between the store into it and here,
7715 and no jumps or labels intervene, then the value can get
7716 here through the reload reg alone.
7717 Otherwise, give up--return. */
7718 for (i1 = NEXT_INSN (output_reload_insn);
7719 i1 != insn; i1 = NEXT_INSN (i1))
7721 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7723 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7724 && reg_mentioned_p (reg, PATTERN (i1)))
7726 /* If this is just a single USE with an REG_EQUAL note in front
7727 of INSN, this is no problem, because this mentions just the
7728 address that we are using here.
7729 But if there is more than one such USE, the insn might use
7730 the operand directly, or another reload might do that.
7731 This is analogous to the count_occurences check in the callers. */
7732 int num_occurences = 0;
7734 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE
7735 && find_reg_note (i1, REG_EQUAL, NULL_RTX))
7737 num_occurences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7738 i1 = NEXT_INSN (i1);
7740 if (num_occurences == 1 && i1 == insn)
7746 /* The caller has already checked that REG dies or is set in INSN.
7747 It has also checked that we are optimizing, and thus some inaccurancies
7748 in the debugging information are acceptable.
7749 So we could just delete output_reload_insn.
7750 But in some cases we can improve the debugging information without
7751 sacrificing optimization - maybe even improving the code:
7752 See if the pseudo reg has been completely replaced
7753 with reload regs. If so, delete the store insn
7754 and forget we had a stack slot for the pseudo. */
7755 if (reload_out[j] != reload_in[j]
7756 && REG_N_DEATHS (REGNO (reg)) == 1
7757 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7758 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7762 /* We know that it was used only between here
7763 and the beginning of the current basic block.
7764 (We also know that the last use before INSN was
7765 the output reload we are thinking of deleting, but never mind that.)
7766 Search that range; see if any ref remains. */
7767 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7769 rtx set = single_set (i2);
7771 /* Uses which just store in the pseudo don't count,
7772 since if they are the only uses, they are dead. */
7773 if (set != 0 && SET_DEST (set) == reg)
7775 if (GET_CODE (i2) == CODE_LABEL
7776 || GET_CODE (i2) == JUMP_INSN)
7778 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7779 && reg_mentioned_p (reg, PATTERN (i2)))
7781 /* Some other ref remains; just delete the output reload we
7783 delete_insn (output_reload_insn);
7788 /* Delete the now-dead stores into this pseudo. */
7789 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7791 rtx set = single_set (i2);
7793 if (set != 0 && SET_DEST (set) == reg)
7795 /* This might be a basic block head,
7796 thus don't use delete_insn. */
7797 PUT_CODE (i2, NOTE);
7798 NOTE_SOURCE_FILE (i2) = 0;
7799 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7801 if (GET_CODE (i2) == CODE_LABEL
7802 || GET_CODE (i2) == JUMP_INSN)
7806 /* For the debugging info,
7807 say the pseudo lives in this reload reg. */
7808 reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
7809 alter_reg (REGNO (reg), -1);
7811 delete_insn (output_reload_insn);
7815 /* Output reload-insns to reload VALUE into RELOADREG.
7816 VALUE is an autoincrement or autodecrement RTX whose operand
7817 is a register or memory location;
7818 so reloading involves incrementing that location.
7820 INC_AMOUNT is the number to increment or decrement by (always positive).
7821 This cannot be deduced from VALUE. */
7824 inc_for_reload (reloadreg, value, inc_amount)
7829 /* REG or MEM to be copied and incremented. */
7830 rtx incloc = XEXP (value, 0);
7831 /* Nonzero if increment after copying. */
7832 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7838 /* No hard register is equivalent to this register after
7839 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7840 we could inc/dec that register as well (maybe even using it for
7841 the source), but I'm not sure it's worth worrying about. */
7842 if (GET_CODE (incloc) == REG)
7843 reg_last_reload_reg[REGNO (incloc)] = 0;
7845 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7846 inc_amount = - inc_amount;
7848 inc = GEN_INT (inc_amount);
7850 /* If this is post-increment, first copy the location to the reload reg. */
7852 emit_insn (gen_move_insn (reloadreg, incloc));
7854 /* See if we can directly increment INCLOC. Use a method similar to that
7857 last = get_last_insn ();
7858 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7859 gen_rtx_PLUS (GET_MODE (incloc),
7862 code = recog_memoized (add_insn);
7865 insn_extract (add_insn);
7866 if (constrain_operands (code, 1))
7868 /* If this is a pre-increment and we have incremented the value
7869 where it lives, copy the incremented value to RELOADREG to
7870 be used as an address. */
7873 emit_insn (gen_move_insn (reloadreg, incloc));
7879 delete_insns_since (last);
7881 /* If couldn't do the increment directly, must increment in RELOADREG.
7882 The way we do this depends on whether this is pre- or post-increment.
7883 For pre-increment, copy INCLOC to the reload register, increment it
7884 there, then save back. */
7888 emit_insn (gen_move_insn (reloadreg, incloc));
7889 emit_insn (gen_add2_insn (reloadreg, inc));
7890 emit_insn (gen_move_insn (incloc, reloadreg));
7895 Because this might be a jump insn or a compare, and because RELOADREG
7896 may not be available after the insn in an input reload, we must do
7897 the incrementation before the insn being reloaded for.
7899 We have already copied INCLOC to RELOADREG. Increment the copy in
7900 RELOADREG, save that back, then decrement RELOADREG so it has
7901 the original value. */
7903 emit_insn (gen_add2_insn (reloadreg, inc));
7904 emit_insn (gen_move_insn (incloc, reloadreg));
7905 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7911 /* Return 1 if we are certain that the constraint-string STRING allows
7912 the hard register REG. Return 0 if we can't be sure of this. */
7915 constraint_accepts_reg_p (string, reg)
7920 int regno = true_regnum (reg);
7923 /* Initialize for first alternative. */
7925 /* Check that each alternative contains `g' or `r'. */
7927 switch (c = *string++)
7930 /* If an alternative lacks `g' or `r', we lose. */
7933 /* If an alternative lacks `g' or `r', we lose. */
7936 /* Initialize for next alternative. */
7941 /* Any general reg wins for this alternative. */
7942 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7946 /* Any reg in specified class wins for this alternative. */
7948 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7950 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
7956 /* Return the number of places FIND appears within X, but don't count
7957 an occurrence if some SET_DEST is FIND. */
7960 count_occurrences (x, find)
7961 register rtx x, find;
7964 register enum rtx_code code;
7965 register char *format_ptr;
7973 code = GET_CODE (x);
7988 if (SET_DEST (x) == find)
7989 return count_occurrences (SET_SRC (x), find);
7996 format_ptr = GET_RTX_FORMAT (code);
7999 for (i = 0; i < GET_RTX_LENGTH (code); i++)
8001 switch (*format_ptr++)
8004 count += count_occurrences (XEXP (x, i), find);
8008 if (XVEC (x, i) != NULL)
8010 for (j = 0; j < XVECLEN (x, i); j++)
8011 count += count_occurrences (XVECEXP (x, i, j), find);
8019 /* This array holds values which are equivalent to a hard register
8020 during reload_cse_regs. Each array element is an EXPR_LIST of
8021 values. Each time a hard register is set, we set the corresponding
8022 array element to the value. Each time a hard register is copied
8023 into memory, we add the memory location to the corresponding array
8024 element. We don't store values or memory addresses with side
8025 effects in this array.
8027 If the value is a CONST_INT, then the mode of the containing
8028 EXPR_LIST is the mode in which that CONST_INT was referenced.
8030 We sometimes clobber a specific entry in a list. In that case, we
8031 just set XEXP (list-entry, 0) to 0. */
8033 static rtx *reg_values;
8035 /* This is a preallocated REG rtx which we use as a temporary in
8036 reload_cse_invalidate_regno, so that we don't need to allocate a
8037 new one each time through a loop in that function. */
8039 static rtx invalidate_regno_rtx;
8041 /* This is a set of registers for which we must remove REG_DEAD notes in
8042 previous insns, because our modifications made them invalid. That can
8043 happen if we introduced the register into the current insn, or we deleted
8044 the current insn which used to set the register. */
8046 static HARD_REG_SET no_longer_dead_regs;
8048 /* Invalidate any entries in reg_values which depend on REGNO,
8049 including those for REGNO itself. This is called if REGNO is
8050 changing. If CLOBBER is true, then always forget anything we
8051 currently know about REGNO. MODE is the mode of the assignment to
8052 REGNO, which is used to determine how many hard registers are being
8053 changed. If MODE is VOIDmode, then only REGNO is being changed;
8054 this is used when invalidating call clobbered registers across a
8058 reload_cse_invalidate_regno (regno, mode, clobber)
8060 enum machine_mode mode;
8066 /* Our callers don't always go through true_regnum; we may see a
8067 pseudo-register here from a CLOBBER or the like. We probably
8068 won't ever see a pseudo-register that has a real register number,
8069 for we check anyhow for safety. */
8070 if (regno >= FIRST_PSEUDO_REGISTER)
8071 regno = reg_renumber[regno];
8075 if (mode == VOIDmode)
8076 endregno = regno + 1;
8078 endregno = regno + HARD_REGNO_NREGS (regno, mode);
8081 for (i = regno; i < endregno; i++)
8084 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8088 for (x = reg_values[i]; x; x = XEXP (x, 1))
8090 if (XEXP (x, 0) != 0
8091 && refers_to_regno_p (regno, endregno, XEXP (x, 0), NULL_PTR))
8093 /* If this is the only entry on the list, clear
8094 reg_values[i]. Otherwise, just clear this entry on
8096 if (XEXP (x, 1) == 0 && x == reg_values[i])
8106 /* We must look at earlier registers, in case REGNO is part of a
8107 multi word value but is not the first register. If an earlier
8108 register has a value in a mode which overlaps REGNO, then we must
8109 invalidate that earlier register. Note that we do not need to
8110 check REGNO or later registers (we must not check REGNO itself,
8111 because we would incorrectly conclude that there was a conflict). */
8113 for (i = 0; i < regno; i++)
8117 for (x = reg_values[i]; x; x = XEXP (x, 1))
8119 if (XEXP (x, 0) != 0)
8121 PUT_MODE (invalidate_regno_rtx, GET_MODE (x));
8122 REGNO (invalidate_regno_rtx) = i;
8123 if (refers_to_regno_p (regno, endregno, invalidate_regno_rtx,
8126 reload_cse_invalidate_regno (i, VOIDmode, 1);
8134 /* The memory at address MEM_BASE is being changed.
8135 Return whether this change will invalidate VAL. */
8138 reload_cse_mem_conflict_p (mem_base, val)
8146 code = GET_CODE (val);
8149 /* Get rid of a few simple cases quickly. */
8162 if (GET_MODE (mem_base) == BLKmode
8163 || GET_MODE (val) == BLKmode)
8165 if (anti_dependence (val, mem_base))
8167 /* The address may contain nested MEMs. */
8174 fmt = GET_RTX_FORMAT (code);
8176 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8180 if (reload_cse_mem_conflict_p (mem_base, XEXP (val, i)))
8183 else if (fmt[i] == 'E')
8187 for (j = 0; j < XVECLEN (val, i); j++)
8188 if (reload_cse_mem_conflict_p (mem_base, XVECEXP (val, i, j)))
8196 /* Invalidate any entries in reg_values which are changed because of a
8197 store to MEM_RTX. If this is called because of a non-const call
8198 instruction, MEM_RTX is (mem:BLK const0_rtx). */
8201 reload_cse_invalidate_mem (mem_rtx)
8206 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8210 for (x = reg_values[i]; x; x = XEXP (x, 1))
8212 if (XEXP (x, 0) != 0
8213 && reload_cse_mem_conflict_p (mem_rtx, XEXP (x, 0)))
8215 /* If this is the only entry on the list, clear
8216 reg_values[i]. Otherwise, just clear this entry on
8218 if (XEXP (x, 1) == 0 && x == reg_values[i])
8229 /* Invalidate DEST, which is being assigned to or clobbered. The
8230 second parameter exists so that this function can be passed to
8231 note_stores; it is ignored. */
8234 reload_cse_invalidate_rtx (dest, ignore)
8236 rtx ignore ATTRIBUTE_UNUSED;
8238 while (GET_CODE (dest) == STRICT_LOW_PART
8239 || GET_CODE (dest) == SIGN_EXTRACT
8240 || GET_CODE (dest) == ZERO_EXTRACT
8241 || GET_CODE (dest) == SUBREG)
8242 dest = XEXP (dest, 0);
8244 if (GET_CODE (dest) == REG)
8245 reload_cse_invalidate_regno (REGNO (dest), GET_MODE (dest), 1);
8246 else if (GET_CODE (dest) == MEM)
8247 reload_cse_invalidate_mem (dest);
8250 /* Possibly delete death notes on the insns before INSN if modifying INSN
8251 extended the lifespan of the registers. */
8254 reload_cse_delete_death_notes (insn)
8259 for (dreg = 0; dreg < FIRST_PSEUDO_REGISTER; dreg++)
8263 if (! TEST_HARD_REG_BIT (no_longer_dead_regs, dreg))
8266 for (trial = prev_nonnote_insn (insn);
8268 && GET_CODE (trial) != CODE_LABEL
8269 && GET_CODE (trial) != BARRIER);
8270 trial = prev_nonnote_insn (trial))
8272 if (find_regno_note (trial, REG_DEAD, dreg))
8274 remove_death (dreg, trial);
8281 /* Record that the current insn uses hard reg REGNO in mode MODE. This
8282 will be used in reload_cse_delete_death_notes to delete prior REG_DEAD
8283 notes for this register. */
8286 reload_cse_no_longer_dead (regno, mode)
8288 enum machine_mode mode;
8290 int nregs = HARD_REGNO_NREGS (regno, mode);
8293 SET_HARD_REG_BIT (no_longer_dead_regs, regno);
8299 /* Do a very simple CSE pass over the hard registers.
8301 This function detects no-op moves where we happened to assign two
8302 different pseudo-registers to the same hard register, and then
8303 copied one to the other. Reload will generate a useless
8304 instruction copying a register to itself.
8306 This function also detects cases where we load a value from memory
8307 into two different registers, and (if memory is more expensive than
8308 registers) changes it to simply copy the first register into the
8311 Another optimization is performed that scans the operands of each
8312 instruction to see whether the value is already available in a
8313 hard register. It then replaces the operand with the hard register
8314 if possible, much like an optional reload would. */
8317 reload_cse_regs_1 (first)
8325 init_alias_analysis ();
8327 reg_values = (rtx *) alloca (FIRST_PSEUDO_REGISTER * sizeof (rtx));
8328 bzero ((char *)reg_values, FIRST_PSEUDO_REGISTER * sizeof (rtx));
8330 /* Create our EXPR_LIST structures on reload_obstack, so that we can
8331 free them when we are done. */
8332 push_obstacks (&reload_obstack, &reload_obstack);
8333 firstobj = (char *) obstack_alloc (&reload_obstack, 0);
8335 /* We pass this to reload_cse_invalidate_mem to invalidate all of
8336 memory for a non-const call instruction. */
8337 callmem = gen_rtx_MEM (BLKmode, const0_rtx);
8339 /* This is used in reload_cse_invalidate_regno to avoid consing a
8340 new REG in a loop in that function. */
8341 invalidate_regno_rtx = gen_rtx_REG (VOIDmode, 0);
8343 for (insn = first; insn; insn = NEXT_INSN (insn))
8347 if (GET_CODE (insn) == CODE_LABEL)
8349 /* Forget all the register values at a code label. We don't
8350 try to do anything clever around jumps. */
8351 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8357 #ifdef NON_SAVING_SETJMP
8358 if (NON_SAVING_SETJMP && GET_CODE (insn) == NOTE
8359 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
8361 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8368 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8371 CLEAR_HARD_REG_SET (no_longer_dead_regs);
8373 /* If this is a call instruction, forget anything stored in a
8374 call clobbered register, or, if this is not a const call, in
8376 if (GET_CODE (insn) == CALL_INSN)
8378 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8379 if (call_used_regs[i])
8380 reload_cse_invalidate_regno (i, VOIDmode, 1);
8382 if (! CONST_CALL_P (insn))
8383 reload_cse_invalidate_mem (callmem);
8386 body = PATTERN (insn);
8387 if (GET_CODE (body) == SET)
8390 if (reload_cse_noop_set_p (body, insn))
8392 /* If this sets the return value of the function, we must keep
8393 a USE around, in case this is in a different basic block
8394 than the final USE. Otherwise, we could loose important
8395 register lifeness information on SMALL_REGISTER_CLASSES
8396 machines, where return registers might be used as spills:
8397 subsequent passes assume that spill registers are dead at
8398 the end of a basic block. */
8399 if (REG_FUNCTION_VALUE_P (SET_DEST (body)))
8402 PATTERN (insn) = gen_rtx_USE (VOIDmode, SET_DEST (body));
8403 INSN_CODE (insn) = -1;
8404 REG_NOTES (insn) = NULL_RTX;
8405 push_obstacks (&reload_obstack, &reload_obstack);
8409 PUT_CODE (insn, NOTE);
8410 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8411 NOTE_SOURCE_FILE (insn) = 0;
8413 reload_cse_delete_death_notes (insn);
8415 /* We're done with this insn. */
8419 /* It's not a no-op, but we can try to simplify it. */
8420 CLEAR_HARD_REG_SET (no_longer_dead_regs);
8421 count += reload_cse_simplify_set (body, insn);
8423 if (count > 0 && apply_change_group ())
8424 reload_cse_delete_death_notes (insn);
8425 else if (reload_cse_simplify_operands (insn))
8426 reload_cse_delete_death_notes (insn);
8428 reload_cse_record_set (body, body);
8430 else if (GET_CODE (body) == PARALLEL)
8433 rtx value = NULL_RTX;
8435 /* If every action in a PARALLEL is a noop, we can delete
8436 the entire PARALLEL. */
8437 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8439 rtx part = XVECEXP (body, 0, i);
8440 if (GET_CODE (part) == SET)
8442 if (! reload_cse_noop_set_p (part, insn))
8444 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8448 value = SET_DEST (part);
8451 else if (GET_CODE (part) != CLOBBER)
8459 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
8460 INSN_CODE (insn) = -1;
8461 REG_NOTES (insn) = NULL_RTX;
8462 push_obstacks (&reload_obstack, &reload_obstack);
8466 PUT_CODE (insn, NOTE);
8467 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8468 NOTE_SOURCE_FILE (insn) = 0;
8470 reload_cse_delete_death_notes (insn);
8472 /* We're done with this insn. */
8476 /* It's not a no-op, but we can try to simplify it. */
8477 CLEAR_HARD_REG_SET (no_longer_dead_regs);
8478 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8479 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8480 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8482 if (count > 0 && apply_change_group ())
8483 reload_cse_delete_death_notes (insn);
8484 else if (reload_cse_simplify_operands (insn))
8485 reload_cse_delete_death_notes (insn);
8487 /* Look through the PARALLEL and record the values being
8488 set, if possible. Also handle any CLOBBERs. */
8489 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8491 rtx x = XVECEXP (body, 0, i);
8493 if (GET_CODE (x) == SET)
8494 reload_cse_record_set (x, body);
8496 note_stores (x, reload_cse_invalidate_rtx);
8500 note_stores (body, reload_cse_invalidate_rtx);
8503 /* Clobber any registers which appear in REG_INC notes. We
8504 could keep track of the changes to their values, but it is
8505 unlikely to help. */
8509 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
8510 if (REG_NOTE_KIND (x) == REG_INC)
8511 reload_cse_invalidate_rtx (XEXP (x, 0), NULL_RTX);
8515 /* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only
8516 after we have processed the insn. */
8517 if (GET_CODE (insn) == CALL_INSN)
8521 for (x = CALL_INSN_FUNCTION_USAGE (insn); x; x = XEXP (x, 1))
8522 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
8523 reload_cse_invalidate_rtx (XEXP (XEXP (x, 0), 0), NULL_RTX);
8527 /* Free all the temporary structures we created, and go back to the
8528 regular obstacks. */
8529 obstack_free (&reload_obstack, firstobj);
8533 /* Call cse / combine like post-reload optimization phases.
8534 FIRST is the first instruction. */
8536 reload_cse_regs (first)
8539 reload_cse_regs_1 (first);
8541 reload_cse_move2add (first);
8542 if (flag_expensive_optimizations)
8543 reload_cse_regs_1 (first);
8546 /* Return whether the values known for REGNO are equal to VAL. MODE
8547 is the mode of the object that VAL is being copied to; this matters
8548 if VAL is a CONST_INT. */
8551 reload_cse_regno_equal_p (regno, val, mode)
8554 enum machine_mode mode;
8561 for (x = reg_values[regno]; x; x = XEXP (x, 1))
8562 if (XEXP (x, 0) != 0
8563 && rtx_equal_p (XEXP (x, 0), val)
8564 && (! flag_float_store || GET_CODE (XEXP (x, 0)) != MEM
8565 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
8566 && (GET_CODE (val) != CONST_INT
8567 || mode == GET_MODE (x)
8568 || (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8569 /* On a big endian machine if the value spans more than
8570 one register then this register holds the high part of
8571 it and we can't use it.
8573 ??? We should also compare with the high part of the
8575 && !(WORDS_BIG_ENDIAN
8576 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
8577 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
8578 GET_MODE_BITSIZE (GET_MODE (x))))))
8584 /* See whether a single set is a noop. SET is the set instruction we
8585 are should check, and INSN is the instruction from which it came. */
8588 reload_cse_noop_set_p (set, insn)
8593 enum machine_mode dest_mode;
8597 src = SET_SRC (set);
8598 dest = SET_DEST (set);
8599 dest_mode = GET_MODE (dest);
8601 if (side_effects_p (src))
8604 dreg = true_regnum (dest);
8605 sreg = true_regnum (src);
8607 /* Check for setting a register to itself. In this case, we don't
8608 have to worry about REG_DEAD notes. */
8609 if (dreg >= 0 && dreg == sreg)
8615 /* Check for setting a register to itself. */
8619 /* Check for setting a register to a value which we already know
8620 is in the register. */
8621 else if (reload_cse_regno_equal_p (dreg, src, dest_mode))
8624 /* Check for setting a register DREG to another register SREG
8625 where SREG is equal to a value which is already in DREG. */
8630 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
8634 if (XEXP (x, 0) == 0)
8637 if (dest_mode == GET_MODE (x))
8639 else if (GET_MODE_BITSIZE (dest_mode)
8640 < GET_MODE_BITSIZE (GET_MODE (x)))
8641 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
8646 && reload_cse_regno_equal_p (dreg, tmp, dest_mode))
8654 else if (GET_CODE (dest) == MEM)
8656 /* Check for storing a register to memory when we know that the
8657 register is equivalent to the memory location. */
8659 && reload_cse_regno_equal_p (sreg, dest, dest_mode)
8660 && ! side_effects_p (dest))
8664 /* If we can delete this SET, then we need to look for an earlier
8665 REG_DEAD note on DREG, and remove it if it exists. */
8666 if (ret && dreg >= 0)
8668 if (! find_regno_note (insn, REG_UNUSED, dreg))
8669 reload_cse_no_longer_dead (dreg, dest_mode);
8675 /* Try to simplify a single SET instruction. SET is the set pattern.
8676 INSN is the instruction it came from.
8677 This function only handles one case: if we set a register to a value
8678 which is not a register, we try to find that value in some other register
8679 and change the set into a register copy. */
8682 reload_cse_simplify_set (set, insn)
8688 enum machine_mode dest_mode;
8689 enum reg_class dclass;
8692 dreg = true_regnum (SET_DEST (set));
8696 src = SET_SRC (set);
8697 if (side_effects_p (src) || true_regnum (src) >= 0)
8700 dclass = REGNO_REG_CLASS (dreg);
8702 /* If memory loads are cheaper than register copies, don't change them. */
8703 if (GET_CODE (src) == MEM
8704 && MEMORY_MOVE_COST (GET_MODE (src), dclass, 1) < 2)
8707 /* If the constant is cheaper than a register, don't change it. */
8708 if (CONSTANT_P (src)
8709 && rtx_cost (src, SET) < 2)
8712 dest_mode = GET_MODE (SET_DEST (set));
8713 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8716 && REGISTER_MOVE_COST (REGNO_REG_CLASS (i), dclass) == 2
8717 && reload_cse_regno_equal_p (i, src, dest_mode))
8721 /* Pop back to the real obstacks while changing the insn. */
8724 validated = validate_change (insn, &SET_SRC (set),
8725 gen_rtx_REG (dest_mode, i), 1);
8727 /* Go back to the obstack we are using for temporary
8729 push_obstacks (&reload_obstack, &reload_obstack);
8731 if (validated && ! find_regno_note (insn, REG_UNUSED, i))
8733 reload_cse_no_longer_dead (i, dest_mode);
8741 /* Try to replace operands in INSN with equivalent values that are already
8742 in registers. This can be viewed as optional reloading.
8744 For each non-register operand in the insn, see if any hard regs are
8745 known to be equivalent to that operand. Record the alternatives which
8746 can accept these hard registers. Among all alternatives, select the
8747 ones which are better or equal to the one currently matching, where
8748 "better" is in terms of '?' and '!' constraints. Among the remaining
8749 alternatives, select the one which replaces most operands with
8753 reload_cse_simplify_operands (insn)
8756 #ifdef REGISTER_CONSTRAINTS
8757 int insn_code_number, n_operands, n_alternatives;
8760 char *constraints[MAX_RECOG_OPERANDS];
8762 /* Vector recording how bad an alternative is. */
8763 int *alternative_reject;
8764 /* Vector recording how many registers can be introduced by choosing
8765 this alternative. */
8766 int *alternative_nregs;
8767 /* Array of vectors recording, for each operand and each alternative,
8768 which hard register to substitute, or -1 if the operand should be
8770 int *op_alt_regno[MAX_RECOG_OPERANDS];
8771 /* Array of alternatives, sorted in order of decreasing desirability. */
8772 int *alternative_order;
8773 rtx reg = gen_rtx_REG (VOIDmode, -1);
8775 /* Find out some information about this insn. */
8776 insn_code_number = recog_memoized (insn);
8777 /* We don't modify asm instructions. */
8778 if (insn_code_number < 0)
8781 n_operands = insn_n_operands[insn_code_number];
8782 n_alternatives = insn_n_alternatives[insn_code_number];
8784 if (n_alternatives == 0 || n_operands == 0)
8786 insn_extract (insn);
8788 /* Figure out which alternative currently matches. */
8789 if (! constrain_operands (insn_code_number, 1))
8790 fatal_insn_not_found (insn);
8792 alternative_reject = (int *) alloca (n_alternatives * sizeof (int));
8793 alternative_nregs = (int *) alloca (n_alternatives * sizeof (int));
8794 alternative_order = (int *) alloca (n_alternatives * sizeof (int));
8795 bzero ((char *)alternative_reject, n_alternatives * sizeof (int));
8796 bzero ((char *)alternative_nregs, n_alternatives * sizeof (int));
8798 for (i = 0; i < n_operands; i++)
8800 enum machine_mode mode;
8804 op_alt_regno[i] = (int *) alloca (n_alternatives * sizeof (int));
8805 for (j = 0; j < n_alternatives; j++)
8806 op_alt_regno[i][j] = -1;
8808 p = constraints[i] = insn_operand_constraint[insn_code_number][i];
8809 mode = insn_operand_mode[insn_code_number][i];
8811 /* Add the reject values for each alternative given by the constraints
8812 for this operand. */
8820 alternative_reject[j] += 3;
8822 alternative_reject[j] += 300;
8825 /* We won't change operands which are already registers. We
8826 also don't want to modify output operands. */
8827 regno = true_regnum (recog_operand[i]);
8829 || constraints[i][0] == '='
8830 || constraints[i][0] == '+')
8833 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8835 int class = (int) NO_REGS;
8837 if (! reload_cse_regno_equal_p (regno, recog_operand[i], mode))
8840 REGNO (reg) = regno;
8841 PUT_MODE (reg, mode);
8843 /* We found a register equal to this operand. Now look for all
8844 alternatives that can accept this register and have not been
8845 assigned a register they can use yet. */
8854 case '=': case '+': case '?':
8855 case '#': case '&': case '!':
8857 case '0': case '1': case '2': case '3': case '4':
8858 case 'm': case '<': case '>': case 'V': case 'o':
8859 case 'E': case 'F': case 'G': case 'H':
8860 case 's': case 'i': case 'n':
8861 case 'I': case 'J': case 'K': case 'L':
8862 case 'M': case 'N': case 'O': case 'P':
8863 #ifdef EXTRA_CONSTRAINT
8864 case 'Q': case 'R': case 'S': case 'T': case 'U':
8867 /* These don't say anything we care about. */
8871 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8876 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER (c)];
8879 case ',': case '\0':
8880 /* See if REGNO fits this alternative, and set it up as the
8881 replacement register if we don't have one for this
8882 alternative yet and the operand being replaced is not
8883 a cheap CONST_INT. */
8884 if (op_alt_regno[i][j] == -1
8885 && reg_fits_class_p (reg, class, 0, mode)
8886 && (GET_CODE (recog_operand[i]) != CONST_INT
8887 || rtx_cost (recog_operand[i], SET) > rtx_cost (reg, SET)))
8889 alternative_nregs[j]++;
8890 op_alt_regno[i][j] = regno;
8902 /* Record all alternatives which are better or equal to the currently
8903 matching one in the alternative_order array. */
8904 for (i = j = 0; i < n_alternatives; i++)
8905 if (alternative_reject[i] <= alternative_reject[which_alternative])
8906 alternative_order[j++] = i;
8909 /* Sort it. Given a small number of alternatives, a dumb algorithm
8910 won't hurt too much. */
8911 for (i = 0; i < n_alternatives - 1; i++)
8914 int best_reject = alternative_reject[alternative_order[i]];
8915 int best_nregs = alternative_nregs[alternative_order[i]];
8918 for (j = i + 1; j < n_alternatives; j++)
8920 int this_reject = alternative_reject[alternative_order[j]];
8921 int this_nregs = alternative_nregs[alternative_order[j]];
8923 if (this_reject < best_reject
8924 || (this_reject == best_reject && this_nregs < best_nregs))
8927 best_reject = this_reject;
8928 best_nregs = this_nregs;
8932 tmp = alternative_order[best];
8933 alternative_order[best] = alternative_order[i];
8934 alternative_order[i] = tmp;
8937 /* Substitute the operands as determined by op_alt_regno for the best
8939 j = alternative_order[0];
8940 CLEAR_HARD_REG_SET (no_longer_dead_regs);
8942 /* Pop back to the real obstacks while changing the insn. */
8945 for (i = 0; i < n_operands; i++)
8947 enum machine_mode mode = insn_operand_mode[insn_code_number][i];
8948 if (op_alt_regno[i][j] == -1)
8951 reload_cse_no_longer_dead (op_alt_regno[i][j], mode);
8952 validate_change (insn, recog_operand_loc[i],
8953 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8956 for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--)
8958 int op = recog_dup_num[i];
8959 enum machine_mode mode = insn_operand_mode[insn_code_number][op];
8961 if (op_alt_regno[op][j] == -1)
8964 reload_cse_no_longer_dead (op_alt_regno[op][j], mode);
8965 validate_change (insn, recog_dup_loc[i],
8966 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8969 /* Go back to the obstack we are using for temporary
8971 push_obstacks (&reload_obstack, &reload_obstack);
8973 return apply_change_group ();
8979 /* These two variables are used to pass information from
8980 reload_cse_record_set to reload_cse_check_clobber. */
8982 static int reload_cse_check_clobbered;
8983 static rtx reload_cse_check_src;
8985 /* See if DEST overlaps with RELOAD_CSE_CHECK_SRC. If it does, set
8986 RELOAD_CSE_CHECK_CLOBBERED. This is called via note_stores. The
8987 second argument, which is passed by note_stores, is ignored. */
8990 reload_cse_check_clobber (dest, ignore)
8992 rtx ignore ATTRIBUTE_UNUSED;
8994 if (reg_overlap_mentioned_p (dest, reload_cse_check_src))
8995 reload_cse_check_clobbered = 1;
8998 /* Record the result of a SET instruction. SET is the set pattern.
8999 BODY is the pattern of the insn that it came from. */
9002 reload_cse_record_set (set, body)
9008 enum machine_mode dest_mode;
9010 dest = SET_DEST (set);
9011 src = SET_SRC (set);
9012 dreg = true_regnum (dest);
9013 sreg = true_regnum (src);
9014 dest_mode = GET_MODE (dest);
9016 /* Some machines don't define AUTO_INC_DEC, but they still use push
9017 instructions. We need to catch that case here in order to
9018 invalidate the stack pointer correctly. Note that invalidating
9019 the stack pointer is different from invalidating DEST. */
9021 while (GET_CODE (x) == SUBREG
9022 || GET_CODE (x) == ZERO_EXTRACT
9023 || GET_CODE (x) == SIGN_EXTRACT
9024 || GET_CODE (x) == STRICT_LOW_PART)
9026 if (push_operand (x, GET_MODE (x)))
9028 reload_cse_invalidate_rtx (stack_pointer_rtx, NULL_RTX);
9029 reload_cse_invalidate_rtx (dest, NULL_RTX);
9033 /* We can only handle an assignment to a register, or a store of a
9034 register to a memory location. For other cases, we just clobber
9035 the destination. We also have to just clobber if there are side
9036 effects in SRC or DEST. */
9037 if ((dreg < 0 && GET_CODE (dest) != MEM)
9038 || side_effects_p (src)
9039 || side_effects_p (dest))
9041 reload_cse_invalidate_rtx (dest, NULL_RTX);
9046 /* We don't try to handle values involving CC, because it's a pain
9047 to keep track of when they have to be invalidated. */
9048 if (reg_mentioned_p (cc0_rtx, src)
9049 || reg_mentioned_p (cc0_rtx, dest))
9051 reload_cse_invalidate_rtx (dest, NULL_RTX);
9056 /* If BODY is a PARALLEL, then we need to see whether the source of
9057 SET is clobbered by some other instruction in the PARALLEL. */
9058 if (GET_CODE (body) == PARALLEL)
9062 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
9066 x = XVECEXP (body, 0, i);
9070 reload_cse_check_clobbered = 0;
9071 reload_cse_check_src = src;
9072 note_stores (x, reload_cse_check_clobber);
9073 if (reload_cse_check_clobbered)
9075 reload_cse_invalidate_rtx (dest, NULL_RTX);
9085 /* This is an assignment to a register. Update the value we
9086 have stored for the register. */
9091 /* This is a copy from one register to another. Any values
9092 which were valid for SREG are now valid for DREG. If the
9093 mode changes, we use gen_lowpart_common to extract only
9094 the part of the value that is copied. */
9095 reg_values[dreg] = 0;
9096 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
9100 if (XEXP (x, 0) == 0)
9102 if (dest_mode == GET_MODE (XEXP (x, 0)))
9104 else if (GET_MODE_BITSIZE (dest_mode)
9105 > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
9108 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
9110 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, tmp,
9115 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, src, NULL_RTX);
9117 /* We've changed DREG, so invalidate any values held by other
9118 registers that depend upon it. */
9119 reload_cse_invalidate_regno (dreg, dest_mode, 0);
9121 /* If this assignment changes more than one hard register,
9122 forget anything we know about the others. */
9123 for (i = 1; i < HARD_REGNO_NREGS (dreg, dest_mode); i++)
9124 reg_values[dreg + i] = 0;
9126 else if (GET_CODE (dest) == MEM)
9128 /* Invalidate conflicting memory locations. */
9129 reload_cse_invalidate_mem (dest);
9131 /* If we're storing a register to memory, add DEST to the list
9133 if (sreg >= 0 && ! side_effects_p (dest))
9134 reg_values[sreg] = gen_rtx_EXPR_LIST (dest_mode, dest,
9139 /* We should have bailed out earlier. */
9144 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
9146 This code might also be useful when reload gave up on reg+reg addresssing
9147 because of clashes between the return register and INDEX_REG_CLASS. */
9149 /* The maximum number of uses of a register we can keep track of to
9150 replace them with reg+reg addressing. */
9151 #define RELOAD_COMBINE_MAX_USES 6
9153 /* INSN is the insn where a register has ben used, and USEP points to the
9154 location of the register within the rtl. */
9155 struct reg_use { rtx insn, *usep; };
9157 /* If the register is used in some unknown fashion, USE_INDEX is negative.
9158 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
9159 indicates where it becomes live again.
9160 Otherwise, USE_INDEX is the index of the last encountered use of the
9161 register (which is first among these we have seen since we scan backwards),
9162 OFFSET contains the constant offset that is added to the register in
9163 all encountered uses, and USE_RUID indicates the first encountered, i.e.
9164 last, of these uses. */
9167 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
9172 } reg_state[FIRST_PSEUDO_REGISTER];
9174 /* Reverse linear uid. This is increased in reload_combine while scanning
9175 the instructions from last to first. It is used to set last_label_ruid
9176 and the store_ruid / use_ruid fields in reg_state. */
9177 static int reload_combine_ruid;
9183 int first_index_reg = 1, last_index_reg = 0;
9185 int last_label_ruid;
9187 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
9188 reload has already used it where appropriate, so there is no use in
9189 trying to generate it now. */
9190 if (double_reg_address_ok && reload_address_index_reg_class != NO_REGS)
9193 /* To avoid wasting too much time later searching for an index register,
9194 determine the minimum and maximum index register numbers. */
9195 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9197 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i))
9199 if (! last_index_reg)
9201 first_index_reg = i;
9204 /* If no index register is available, we can quit now. */
9205 if (first_index_reg > last_index_reg)
9208 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
9209 last_label_ruid = reload_combine_ruid = 0;
9210 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9213 reg_state[i].use_index = -1;
9216 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9217 reg_state[i].store_ruid = reload_combine_ruid;
9221 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
9225 /* We cannot do our optimization across labels. Invalidating all the use
9226 information we have would be costly, so we just note where the label
9227 is and then later disable any optimization that would cross it. */
9228 if (GET_CODE (insn) == CODE_LABEL)
9229 last_label_ruid = reload_combine_ruid;
9230 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
9232 reload_combine_ruid++;
9234 /* Look for (set (REGX) (CONST_INT))
9235 (set (REGX) (PLUS (REGX) (REGY)))
9237 ... (MEM (REGX)) ...
9239 (set (REGZ) (CONST_INT))
9241 ... (MEM (PLUS (REGZ) (REGY)))... .
9243 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
9244 and that we know all uses of REGX before it dies. */
9245 set = single_set (insn);
9247 && GET_CODE (SET_DEST (set)) == REG
9248 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
9249 GET_MODE (SET_DEST (set)))
9251 && GET_CODE (SET_SRC (set)) == PLUS
9252 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
9253 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
9254 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
9256 rtx reg = SET_DEST (set);
9257 rtx plus = SET_SRC (set);
9258 rtx base = XEXP (plus, 1);
9259 rtx prev = prev_nonnote_insn (insn);
9260 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
9261 int regno = REGNO (reg);
9263 rtx reg_sum = NULL_RTX;
9265 /* Now, we need an index register.
9266 We'll set index_reg to this index register, const_reg to the
9267 register that is to be loaded with the constant
9268 (denoted as REGZ in the substitution illustration above),
9269 and reg_sum to the register-register that we want to use to
9270 substitute uses of REG (typically in MEMs) with.
9271 First check REG and BASE for being index registers;
9272 we can use them even if they are not dead. */
9273 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
9274 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
9282 /* Otherwise, look for a free index register. Since we have
9283 checked above that neiter REG nor BASE are index registers,
9284 if we find anything at all, it will be different from these
9286 for (i = first_index_reg; i <= last_index_reg; i++)
9288 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
9289 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
9290 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
9291 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
9293 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
9294 const_reg = index_reg;
9295 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
9301 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
9302 && rtx_equal_p (SET_DEST (prev_set), reg)
9303 && reg_state[regno].use_index >= 0
9308 /* Change destination register and - if necessary - the
9309 constant value in PREV, the constant loading instruction. */
9310 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
9311 if (reg_state[regno].offset != const0_rtx)
9312 validate_change (prev,
9313 &SET_SRC (prev_set),
9314 GEN_INT (INTVAL (SET_SRC (prev_set))
9315 + INTVAL (reg_state[regno].offset)),
9317 /* Now for every use of REG that we have recorded, replace REG
9319 for (i = reg_state[regno].use_index;
9320 i < RELOAD_COMBINE_MAX_USES; i++)
9321 validate_change (reg_state[regno].reg_use[i].insn,
9322 reg_state[regno].reg_use[i].usep,
9325 if (apply_change_group ())
9329 /* Delete the reg-reg addition. */
9330 PUT_CODE (insn, NOTE);
9331 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9332 NOTE_SOURCE_FILE (insn) = 0;
9334 if (reg_state[regno].offset != const0_rtx)
9336 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
9338 for (np = ®_NOTES (prev); *np; )
9340 if (REG_NOTE_KIND (*np) == REG_EQUAL
9341 || REG_NOTE_KIND (*np) == REG_EQUIV)
9342 *np = XEXP (*np, 1);
9344 np = &XEXP (*np, 1);
9347 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9348 reg_state[REGNO (const_reg)].store_ruid = reload_combine_ruid;
9353 note_stores (PATTERN (insn), reload_combine_note_store);
9354 if (GET_CODE (insn) == CALL_INSN)
9358 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9360 if (call_used_regs[i])
9362 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9363 reg_state[i].store_ruid = reload_combine_ruid;
9366 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
9367 link = XEXP (link, 1))
9369 rtx use = XEXP (link, 0);
9370 int regno = REGNO (XEXP (use, 0));
9371 if (GET_CODE (use) == CLOBBER)
9373 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9374 reg_state[regno].store_ruid = reload_combine_ruid;
9377 reg_state[regno].use_index = -1;
9380 if (GET_CODE (insn) == JUMP_INSN)
9382 /* Non-spill registers might be used at the call destination in
9383 some unknown fashion, so we have to mark the unknown use. */
9384 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9386 if (! TEST_HARD_REG_BIT (used_spill_regs, i))
9387 reg_state[i].use_index = -1;
9390 reload_combine_note_use (&PATTERN (insn), insn);
9391 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9393 if (REG_NOTE_KIND (note) == REG_INC
9394 && GET_CODE (XEXP (note, 0)) == REG)
9395 reg_state[REGNO (XEXP (note, 0))].use_index = -1;
9400 /* Check if DST is a register or a subreg of a register; if it is,
9401 update reg_state[regno].store_ruid and reg_state[regno].use_index
9402 accordingly. Called via note_stores from reload_combine.
9403 The second argument, SET, is ignored. */
9405 reload_combine_note_store (dst, set)
9410 unsigned size = GET_MODE_SIZE (GET_MODE (dst));
9412 if (GET_CODE (dst) == SUBREG)
9414 regno = SUBREG_WORD (dst);
9415 dst = SUBREG_REG (dst);
9417 if (GET_CODE (dst) != REG)
9419 regno += REGNO (dst);
9420 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
9421 careful with registers / register parts that are not full words. */
9422 if (size < UNITS_PER_WORD)
9423 reg_state[regno].use_index = -1;
9426 for (i = size / UNITS_PER_WORD - 1 + regno; i >= regno; i--)
9428 reg_state[i].store_ruid = reload_combine_ruid;
9429 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9434 /* XP points to a piece of rtl that has to be checked for any uses of
9436 *XP is the pattern of INSN, or a part of it.
9437 Called from reload_combine, and recursively by itself. */
9439 reload_combine_note_use (xp, insn)
9443 enum rtx_code code = x->code;
9446 rtx offset = const0_rtx; /* For the REG case below. */
9451 if (GET_CODE (SET_DEST (x)) == REG)
9453 reload_combine_note_use (&SET_SRC (x), insn);
9459 if (GET_CODE (SET_DEST (x)) == REG)
9464 /* We are interested in (plus (reg) (const_int)) . */
9465 if (GET_CODE (XEXP (x, 0)) != REG || GET_CODE (XEXP (x, 1)) != CONST_INT)
9467 offset = XEXP (x, 1);
9472 int regno = REGNO (x);
9475 /* Some spurious USEs of pseudo registers might remain.
9476 Just ignore them. */
9477 if (regno >= FIRST_PSEUDO_REGISTER)
9480 /* If this register is already used in some unknown fashion, we
9482 If we decrement the index from zero to -1, we can't store more
9483 uses, so this register becomes used in an unknown fashion. */
9484 use_index = --reg_state[regno].use_index;
9488 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
9490 /* We have found another use for a register that is already
9491 used later. Check if the offsets match; if not, mark the
9492 register as used in an unknown fashion. */
9493 if (! rtx_equal_p (offset, reg_state[regno].offset))
9495 reg_state[regno].use_index = -1;
9501 /* This is the first use of this register we have seen since we
9502 marked it as dead. */
9503 reg_state[regno].offset = offset;
9504 reg_state[regno].use_ruid = reload_combine_ruid;
9506 reg_state[regno].reg_use[use_index].insn = insn;
9507 reg_state[regno].reg_use[use_index].usep = xp;
9515 /* Recursively process the components of X. */
9516 fmt = GET_RTX_FORMAT (code);
9517 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9520 reload_combine_note_use (&XEXP (x, i), insn);
9521 else if (fmt[i] == 'E')
9523 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9524 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9529 /* See if we can reduce the cost of a constant by replacing a move with
9531 /* We cannot do our optimization across labels. Invalidating all the
9532 information about register contents we have would be costly, so we
9533 use last_label_luid (local variable of reload_cse_move2add) to note
9534 where the label is and then later disable any optimization that would
9536 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9537 reg_set_luid[n] is larger than last_label_luid[n] . */
9538 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9539 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
9540 reg_mode[n] to be valid.
9541 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
9542 has been set to reg_offset[n] in mode reg_mode[n] .
9543 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
9544 register n has been set to the sum of reg_offset[n] and register
9545 reg_base_reg[n], calculated in mode reg_mode[n] . */
9546 static rtx reg_offset[FIRST_PSEUDO_REGISTER];
9547 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9548 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9549 /* move2add_luid is linearily increased while scanning the instructions
9550 from first to last. It is used to set reg_set_luid in
9551 reload_cse_move2add and move2add_note_store, and to set reg_death_luid
9552 (local variable of reload_cse_move2add) . */
9553 static int move2add_luid;
9556 reload_cse_move2add (first)
9561 int last_label_luid;
9562 /* reg_death and reg_death_luid are solely used to remove stale REG_DEAD
9564 int reg_death_luid[FIRST_PSEUDO_REGISTER];
9565 rtx reg_death[FIRST_PSEUDO_REGISTER];
9567 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
9569 reg_set_luid[i] = 0;
9570 reg_death_luid[i] = 0;
9572 last_label_luid = 0;
9574 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9578 if (GET_CODE (insn) == CODE_LABEL)
9579 last_label_luid = move2add_luid;
9580 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
9582 pat = PATTERN (insn);
9583 /* For simplicity, we only perform this optimization on
9584 straightforward SETs. */
9585 if (GET_CODE (pat) == SET
9586 && GET_CODE (SET_DEST (pat)) == REG)
9588 rtx reg = SET_DEST (pat);
9589 int regno = REGNO (reg);
9590 rtx src = SET_SRC (pat);
9592 /* Check if we have valid information on the contents of this
9593 register in the mode of REG. */
9594 /* ??? We don't know how zero / sign extension is handled, hence
9595 we can't go from a narrower to a wider mode. */
9596 if (reg_set_luid[regno] > last_label_luid
9597 && (GET_MODE_SIZE (GET_MODE (reg))
9598 <= GET_MODE_SIZE (reg_mode[regno]))
9599 && GET_CODE (reg_offset[regno]) == CONST_INT)
9601 /* Try to transform (set (REGX) (CONST_INT A))
9603 (set (REGX) (CONST_INT B))
9605 (set (REGX) (CONST_INT A))
9607 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9609 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9612 rtx new_src = GEN_INT (INTVAL (src)
9613 - INTVAL (reg_offset[regno]));
9614 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9615 use (set (reg) (reg)) instead.
9616 We don't delete this insn, nor do we convert it into a
9617 note, to avoid losing register notes or the return
9618 value flag. jump2 already knowns how to get rid of
9620 if (new_src == const0_rtx)
9621 success = validate_change (insn, &SET_SRC (pat), reg, 0);
9622 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9623 && have_add2_insn (GET_MODE (reg)))
9624 success = validate_change (insn, &PATTERN (insn),
9625 gen_add2_insn (reg, new_src), 0);
9626 if (success && reg_death_luid[regno] > reg_set_luid[regno])
9627 remove_death (regno, reg_death[regno]);
9628 reg_set_luid[regno] = move2add_luid;
9629 reg_mode[regno] = GET_MODE (reg);
9630 reg_offset[regno] = src;
9634 /* Try to transform (set (REGX) (REGY))
9635 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9638 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9641 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9643 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9644 else if (GET_CODE (src) == REG
9645 && reg_base_reg[regno] == REGNO (src)
9646 && reg_set_luid[regno] > reg_set_luid[REGNO (src)])
9648 rtx next = next_nonnote_insn (insn);
9651 set = single_set (next);
9654 && SET_DEST (set) == reg
9655 && GET_CODE (SET_SRC (set)) == PLUS
9656 && XEXP (SET_SRC (set), 0) == reg
9657 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9659 rtx src2 = SET_SRC (set);
9660 rtx src3 = XEXP (SET_SRC (set), 1);
9661 rtx new_src = GEN_INT (INTVAL (src3)
9662 - INTVAL (reg_offset[regno]));
9665 if (new_src == const0_rtx)
9666 /* See above why we create (set (reg) (reg)) here. */
9668 = validate_change (next, &SET_SRC (set), reg, 0);
9669 else if ((rtx_cost (new_src, PLUS)
9670 < 2 + rtx_cost (src3, SET))
9671 && have_add2_insn (GET_MODE (reg)))
9673 = validate_change (next, &PATTERN (next),
9674 gen_add2_insn (reg, new_src), 0);
9677 if (reg_death_luid[regno] > reg_set_luid[regno])
9678 remove_death (regno, reg_death[regno]);
9679 /* INSN might be the first insn in a basic block
9680 if the preceding insn is a conditional jump
9681 or a possible-throwing call. */
9682 PUT_CODE (insn, NOTE);
9683 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9684 NOTE_SOURCE_FILE (insn) = 0;
9687 reg_set_luid[regno] = move2add_luid;
9688 reg_mode[regno] = GET_MODE (reg);
9689 reg_offset[regno] = src3;
9696 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9698 if (REG_NOTE_KIND (note) == REG_INC
9699 && GET_CODE (XEXP (note, 0)) == REG)
9701 /* Indicate that this register has been recently written to,
9702 but the exact contents are not available. */
9703 int regno = REGNO (XEXP (note, 0));
9704 if (regno < FIRST_PSEUDO_REGISTER)
9706 reg_set_luid[regno] = move2add_luid;
9707 reg_offset[regno] = note;
9710 /* Remember any REG_DEAD notes so that we can remove them
9711 later if necessary. */
9712 else if (REG_NOTE_KIND (note) == REG_DEAD
9713 && GET_CODE (XEXP (note, 0)) == REG)
9715 int regno = REGNO (XEXP (note, 0));
9716 if (regno < FIRST_PSEUDO_REGISTER)
9718 reg_death[regno] = insn;
9719 reg_death_luid[regno] = move2add_luid;
9723 note_stores (PATTERN (insn), move2add_note_store);
9724 /* If this is a CALL_INSN, all call used registers are stored with
9726 if (GET_CODE (insn) == CALL_INSN)
9728 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
9730 if (call_used_regs[i])
9732 reg_set_luid[i] = move2add_luid;
9733 reg_offset[i] = insn; /* Invalidate contents. */
9740 /* SET is a SET or CLOBBER that sets DST.
9741 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9742 Called from reload_cse_move2add via note_stores. */
9744 move2add_note_store (dst, set)
9750 enum machine_mode mode = GET_MODE (dst);
9751 if (GET_CODE (dst) == SUBREG)
9753 regno = SUBREG_WORD (dst);
9754 dst = SUBREG_REG (dst);
9756 if (GET_CODE (dst) != REG)
9759 regno += REGNO (dst);
9761 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET)
9763 rtx src = SET_SRC (set);
9765 reg_mode[regno] = mode;
9766 switch (GET_CODE (src))
9770 rtx src0 = XEXP (src, 0);
9771 if (GET_CODE (src0) == REG)
9773 if (REGNO (src0) != regno
9774 || reg_offset[regno] != const0_rtx)
9776 reg_base_reg[regno] = REGNO (src0);
9777 reg_set_luid[regno] = move2add_luid;
9779 reg_offset[regno] = XEXP (src, 1);
9782 reg_set_luid[regno] = move2add_luid;
9783 reg_offset[regno] = set; /* Invalidate contents. */
9788 reg_base_reg[regno] = REGNO (SET_SRC (set));
9789 reg_offset[regno] = const0_rtx;
9790 reg_set_luid[regno] = move2add_luid;
9794 reg_base_reg[regno] = -1;
9795 reg_offset[regno] = SET_SRC (set);
9796 reg_set_luid[regno] = move2add_luid;
9802 for (i = regno + HARD_REGNO_NREGS (regno, mode) - 1; i >= regno; i--)
9804 /* Indicate that this register has been recently written to,
9805 but the exact contents are not available. */
9806 reg_set_luid[i] = move2add_luid;
9807 reg_offset[i] = dst;
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