1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation,
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
33 #include "insn-config.h"
39 #include "addresses.h"
40 #include "basic-block.h"
50 /* This file contains the reload pass of the compiler, which is
51 run after register allocation has been done. It checks that
52 each insn is valid (operands required to be in registers really
53 are in registers of the proper class) and fixes up invalid ones
54 by copying values temporarily into registers for the insns
57 The results of register allocation are described by the vector
58 reg_renumber; the insns still contain pseudo regs, but reg_renumber
59 can be used to find which hard reg, if any, a pseudo reg is in.
61 The technique we always use is to free up a few hard regs that are
62 called ``reload regs'', and for each place where a pseudo reg
63 must be in a hard reg, copy it temporarily into one of the reload regs.
65 Reload regs are allocated locally for every instruction that needs
66 reloads. When there are pseudos which are allocated to a register that
67 has been chosen as a reload reg, such pseudos must be ``spilled''.
68 This means that they go to other hard regs, or to stack slots if no other
69 available hard regs can be found. Spilling can invalidate more
70 insns, requiring additional need for reloads, so we must keep checking
71 until the process stabilizes.
73 For machines with different classes of registers, we must keep track
74 of the register class needed for each reload, and make sure that
75 we allocate enough reload registers of each class.
77 The file reload.c contains the code that checks one insn for
78 validity and reports the reloads that it needs. This file
79 is in charge of scanning the entire rtl code, accumulating the
80 reload needs, spilling, assigning reload registers to use for
81 fixing up each insn, and generating the new insns to copy values
82 into the reload registers. */
84 /* During reload_as_needed, element N contains a REG rtx for the hard reg
85 into which reg N has been reloaded (perhaps for a previous insn). */
86 static rtx *reg_last_reload_reg;
88 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
89 for an output reload that stores into reg N. */
90 static regset_head reg_has_output_reload;
92 /* Indicates which hard regs are reload-registers for an output reload
93 in the current insn. */
94 static HARD_REG_SET reg_is_output_reload;
96 /* Element N is the constant value to which pseudo reg N is equivalent,
97 or zero if pseudo reg N is not equivalent to a constant.
98 find_reloads looks at this in order to replace pseudo reg N
99 with the constant it stands for. */
100 rtx *reg_equiv_constant;
102 /* Element N is an invariant value to which pseudo reg N is equivalent.
103 eliminate_regs_in_insn uses this to replace pseudos in particular
105 rtx *reg_equiv_invariant;
107 /* Element N is a memory location to which pseudo reg N is equivalent,
108 prior to any register elimination (such as frame pointer to stack
109 pointer). Depending on whether or not it is a valid address, this value
110 is transferred to either reg_equiv_address or reg_equiv_mem. */
111 rtx *reg_equiv_memory_loc;
113 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
114 collector can keep track of what is inside. */
115 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
117 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
118 This is used when the address is not valid as a memory address
119 (because its displacement is too big for the machine.) */
120 rtx *reg_equiv_address;
122 /* Element N is the memory slot to which pseudo reg N is equivalent,
123 or zero if pseudo reg N is not equivalent to a memory slot. */
126 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
127 alternate representations of the location of pseudo reg N. */
128 rtx *reg_equiv_alt_mem_list;
130 /* Widest width in which each pseudo reg is referred to (via subreg). */
131 static unsigned int *reg_max_ref_width;
133 /* Element N is the list of insns that initialized reg N from its equivalent
134 constant or memory slot. */
136 int reg_equiv_init_size;
138 /* Vector to remember old contents of reg_renumber before spilling. */
139 static short *reg_old_renumber;
141 /* During reload_as_needed, element N contains the last pseudo regno reloaded
142 into hard register N. If that pseudo reg occupied more than one register,
143 reg_reloaded_contents points to that pseudo for each spill register in
144 use; all of these must remain set for an inheritance to occur. */
145 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
147 /* During reload_as_needed, element N contains the insn for which
148 hard register N was last used. Its contents are significant only
149 when reg_reloaded_valid is set for this register. */
150 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
152 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
153 static HARD_REG_SET reg_reloaded_valid;
154 /* Indicate if the register was dead at the end of the reload.
155 This is only valid if reg_reloaded_contents is set and valid. */
156 static HARD_REG_SET reg_reloaded_dead;
158 /* Indicate whether the register's current value is one that is not
159 safe to retain across a call, even for registers that are normally
161 static HARD_REG_SET reg_reloaded_call_part_clobbered;
163 /* Number of spill-regs so far; number of valid elements of spill_regs. */
166 /* In parallel with spill_regs, contains REG rtx's for those regs.
167 Holds the last rtx used for any given reg, or 0 if it has never
168 been used for spilling yet. This rtx is reused, provided it has
170 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
172 /* In parallel with spill_regs, contains nonzero for a spill reg
173 that was stored after the last time it was used.
174 The precise value is the insn generated to do the store. */
175 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
177 /* This is the register that was stored with spill_reg_store. This is a
178 copy of reload_out / reload_out_reg when the value was stored; if
179 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
180 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
182 /* This table is the inverse mapping of spill_regs:
183 indexed by hard reg number,
184 it contains the position of that reg in spill_regs,
185 or -1 for something that is not in spill_regs.
187 ?!? This is no longer accurate. */
188 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
190 /* This reg set indicates registers that can't be used as spill registers for
191 the currently processed insn. These are the hard registers which are live
192 during the insn, but not allocated to pseudos, as well as fixed
194 static HARD_REG_SET bad_spill_regs;
196 /* These are the hard registers that can't be used as spill register for any
197 insn. This includes registers used for user variables and registers that
198 we can't eliminate. A register that appears in this set also can't be used
199 to retry register allocation. */
200 static HARD_REG_SET bad_spill_regs_global;
202 /* Describes order of use of registers for reloading
203 of spilled pseudo-registers. `n_spills' is the number of
204 elements that are actually valid; new ones are added at the end.
206 Both spill_regs and spill_reg_order are used on two occasions:
207 once during find_reload_regs, where they keep track of the spill registers
208 for a single insn, but also during reload_as_needed where they show all
209 the registers ever used by reload. For the latter case, the information
210 is calculated during finish_spills. */
211 static short spill_regs[FIRST_PSEUDO_REGISTER];
213 /* This vector of reg sets indicates, for each pseudo, which hard registers
214 may not be used for retrying global allocation because the register was
215 formerly spilled from one of them. If we allowed reallocating a pseudo to
216 a register that it was already allocated to, reload might not
218 static HARD_REG_SET *pseudo_previous_regs;
220 /* This vector of reg sets indicates, for each pseudo, which hard
221 registers may not be used for retrying global allocation because they
222 are used as spill registers during one of the insns in which the
224 static HARD_REG_SET *pseudo_forbidden_regs;
226 /* All hard regs that have been used as spill registers for any insn are
227 marked in this set. */
228 static HARD_REG_SET used_spill_regs;
230 /* Index of last register assigned as a spill register. We allocate in
231 a round-robin fashion. */
232 static int last_spill_reg;
234 /* Nonzero if indirect addressing is supported on the machine; this means
235 that spilling (REG n) does not require reloading it into a register in
236 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
237 value indicates the level of indirect addressing supported, e.g., two
238 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
240 static char spill_indirect_levels;
242 /* Nonzero if indirect addressing is supported when the innermost MEM is
243 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
244 which these are valid is the same as spill_indirect_levels, above. */
245 char indirect_symref_ok;
247 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
248 char double_reg_address_ok;
250 /* Record the stack slot for each spilled hard register. */
251 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
253 /* Width allocated so far for that stack slot. */
254 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
256 /* Record which pseudos needed to be spilled. */
257 static regset_head spilled_pseudos;
259 /* Used for communication between order_regs_for_reload and count_pseudo.
260 Used to avoid counting one pseudo twice. */
261 static regset_head pseudos_counted;
263 /* First uid used by insns created by reload in this function.
264 Used in find_equiv_reg. */
265 int reload_first_uid;
267 /* Flag set by local-alloc or global-alloc if anything is live in
268 a call-clobbered reg across calls. */
269 int caller_save_needed;
271 /* Set to 1 while reload_as_needed is operating.
272 Required by some machines to handle any generated moves differently. */
273 int reload_in_progress = 0;
275 /* These arrays record the insn_code of insns that may be needed to
276 perform input and output reloads of special objects. They provide a
277 place to pass a scratch register. */
278 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
279 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
281 /* This obstack is used for allocation of rtl during register elimination.
282 The allocated storage can be freed once find_reloads has processed the
284 static struct obstack reload_obstack;
286 /* Points to the beginning of the reload_obstack. All insn_chain structures
287 are allocated first. */
288 static char *reload_startobj;
290 /* The point after all insn_chain structures. Used to quickly deallocate
291 memory allocated in copy_reloads during calculate_needs_all_insns. */
292 static char *reload_firstobj;
294 /* This points before all local rtl generated by register elimination.
295 Used to quickly free all memory after processing one insn. */
296 static char *reload_insn_firstobj;
298 /* List of insn_chain instructions, one for every insn that reload needs to
300 struct insn_chain *reload_insn_chain;
302 /* List of all insns needing reloads. */
303 static struct insn_chain *insns_need_reload;
305 /* This structure is used to record information about register eliminations.
306 Each array entry describes one possible way of eliminating a register
307 in favor of another. If there is more than one way of eliminating a
308 particular register, the most preferred should be specified first. */
312 int from; /* Register number to be eliminated. */
313 int to; /* Register number used as replacement. */
314 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
315 int can_eliminate; /* Nonzero if this elimination can be done. */
316 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
317 insns made by reload. */
318 HOST_WIDE_INT offset; /* Current offset between the two regs. */
319 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
320 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
321 rtx from_rtx; /* REG rtx for the register to be eliminated.
322 We cannot simply compare the number since
323 we might then spuriously replace a hard
324 register corresponding to a pseudo
325 assigned to the reg to be eliminated. */
326 rtx to_rtx; /* REG rtx for the replacement. */
329 static struct elim_table *reg_eliminate = 0;
331 /* This is an intermediate structure to initialize the table. It has
332 exactly the members provided by ELIMINABLE_REGS. */
333 static const struct elim_table_1
337 } reg_eliminate_1[] =
339 /* If a set of eliminable registers was specified, define the table from it.
340 Otherwise, default to the normal case of the frame pointer being
341 replaced by the stack pointer. */
343 #ifdef ELIMINABLE_REGS
346 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
349 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
351 /* Record the number of pending eliminations that have an offset not equal
352 to their initial offset. If nonzero, we use a new copy of each
353 replacement result in any insns encountered. */
354 int num_not_at_initial_offset;
356 /* Count the number of registers that we may be able to eliminate. */
357 static int num_eliminable;
358 /* And the number of registers that are equivalent to a constant that
359 can be eliminated to frame_pointer / arg_pointer + constant. */
360 static int num_eliminable_invariants;
362 /* For each label, we record the offset of each elimination. If we reach
363 a label by more than one path and an offset differs, we cannot do the
364 elimination. This information is indexed by the difference of the
365 number of the label and the first label number. We can't offset the
366 pointer itself as this can cause problems on machines with segmented
367 memory. The first table is an array of flags that records whether we
368 have yet encountered a label and the second table is an array of arrays,
369 one entry in the latter array for each elimination. */
371 static int first_label_num;
372 static char *offsets_known_at;
373 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
375 /* Number of labels in the current function. */
377 static int num_labels;
379 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
380 static void maybe_fix_stack_asms (void);
381 static void copy_reloads (struct insn_chain *);
382 static void calculate_needs_all_insns (int);
383 static int find_reg (struct insn_chain *, int);
384 static void find_reload_regs (struct insn_chain *);
385 static void select_reload_regs (void);
386 static void delete_caller_save_insns (void);
388 static void spill_failure (rtx, enum reg_class);
389 static void count_spilled_pseudo (int, int, int);
390 static void delete_dead_insn (rtx);
391 static void alter_reg (int, int);
392 static void set_label_offsets (rtx, rtx, int);
393 static void check_eliminable_occurrences (rtx);
394 static void elimination_effects (rtx, enum machine_mode);
395 static int eliminate_regs_in_insn (rtx, int);
396 static void update_eliminable_offsets (void);
397 static void mark_not_eliminable (rtx, rtx, void *);
398 static void set_initial_elim_offsets (void);
399 static bool verify_initial_elim_offsets (void);
400 static void set_initial_label_offsets (void);
401 static void set_offsets_for_label (rtx);
402 static void init_elim_table (void);
403 static void update_eliminables (HARD_REG_SET *);
404 static void spill_hard_reg (unsigned int, int);
405 static int finish_spills (int);
406 static void scan_paradoxical_subregs (rtx);
407 static void count_pseudo (int);
408 static void order_regs_for_reload (struct insn_chain *);
409 static void reload_as_needed (int);
410 static void forget_old_reloads_1 (rtx, rtx, void *);
411 static void forget_marked_reloads (regset);
412 static int reload_reg_class_lower (const void *, const void *);
413 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
415 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
417 static int reload_reg_free_p (unsigned int, int, enum reload_type);
418 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
420 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
422 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
423 static int allocate_reload_reg (struct insn_chain *, int, int);
424 static int conflicts_with_override (rtx);
425 static void failed_reload (rtx, int);
426 static int set_reload_reg (int, int);
427 static void choose_reload_regs_init (struct insn_chain *, rtx *);
428 static void choose_reload_regs (struct insn_chain *);
429 static void merge_assigned_reloads (rtx);
430 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
432 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
434 static void do_input_reload (struct insn_chain *, struct reload *, int);
435 static void do_output_reload (struct insn_chain *, struct reload *, int);
436 static bool inherit_piecemeal_p (int, int);
437 static void emit_reload_insns (struct insn_chain *);
438 static void delete_output_reload (rtx, int, int);
439 static void delete_address_reloads (rtx, rtx);
440 static void delete_address_reloads_1 (rtx, rtx, rtx);
441 static rtx inc_for_reload (rtx, rtx, rtx, int);
443 static void add_auto_inc_notes (rtx, rtx);
445 static void copy_eh_notes (rtx, rtx);
446 static int reloads_conflict (int, int);
447 static rtx gen_reload (rtx, rtx, int, enum reload_type);
448 static rtx emit_insn_if_valid_for_reload (rtx);
450 /* Initialize the reload pass once per compilation. */
457 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
458 Set spill_indirect_levels to the number of levels such addressing is
459 permitted, zero if it is not permitted at all. */
462 = gen_rtx_MEM (Pmode,
465 LAST_VIRTUAL_REGISTER + 1),
467 spill_indirect_levels = 0;
469 while (memory_address_p (QImode, tem))
471 spill_indirect_levels++;
472 tem = gen_rtx_MEM (Pmode, tem);
475 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
477 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
478 indirect_symref_ok = memory_address_p (QImode, tem);
480 /* See if reg+reg is a valid (and offsettable) address. */
482 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
484 tem = gen_rtx_PLUS (Pmode,
485 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
486 gen_rtx_REG (Pmode, i));
488 /* This way, we make sure that reg+reg is an offsettable address. */
489 tem = plus_constant (tem, 4);
491 if (memory_address_p (QImode, tem))
493 double_reg_address_ok = 1;
498 /* Initialize obstack for our rtl allocation. */
499 gcc_obstack_init (&reload_obstack);
500 reload_startobj = obstack_alloc (&reload_obstack, 0);
502 INIT_REG_SET (&spilled_pseudos);
503 INIT_REG_SET (&pseudos_counted);
506 /* List of insn chains that are currently unused. */
507 static struct insn_chain *unused_insn_chains = 0;
509 /* Allocate an empty insn_chain structure. */
511 new_insn_chain (void)
513 struct insn_chain *c;
515 if (unused_insn_chains == 0)
517 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
518 INIT_REG_SET (&c->live_throughout);
519 INIT_REG_SET (&c->dead_or_set);
523 c = unused_insn_chains;
524 unused_insn_chains = c->next;
526 c->is_caller_save_insn = 0;
527 c->need_operand_change = 0;
533 /* Small utility function to set all regs in hard reg set TO which are
534 allocated to pseudos in regset FROM. */
537 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
540 reg_set_iterator rsi;
542 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
544 int r = reg_renumber[regno];
549 /* reload_combine uses the information from
550 BASIC_BLOCK->global_live_at_start, which might still
551 contain registers that have not actually been allocated
552 since they have an equivalence. */
553 gcc_assert (reload_completed);
557 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
559 SET_HARD_REG_BIT (*to, r + nregs);
564 /* Replace all pseudos found in LOC with their corresponding
568 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
581 unsigned int regno = REGNO (x);
583 if (regno < FIRST_PSEUDO_REGISTER)
586 x = eliminate_regs (x, mem_mode, usage);
590 replace_pseudos_in (loc, mem_mode, usage);
594 if (reg_equiv_constant[regno])
595 *loc = reg_equiv_constant[regno];
596 else if (reg_equiv_mem[regno])
597 *loc = reg_equiv_mem[regno];
598 else if (reg_equiv_address[regno])
599 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
602 gcc_assert (!REG_P (regno_reg_rtx[regno])
603 || REGNO (regno_reg_rtx[regno]) != regno);
604 *loc = regno_reg_rtx[regno];
609 else if (code == MEM)
611 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
615 /* Process each of our operands recursively. */
616 fmt = GET_RTX_FORMAT (code);
617 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
619 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
620 else if (*fmt == 'E')
621 for (j = 0; j < XVECLEN (x, i); j++)
622 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
626 /* Global variables used by reload and its subroutines. */
628 /* Set during calculate_needs if an insn needs register elimination. */
629 static int something_needs_elimination;
630 /* Set during calculate_needs if an insn needs an operand changed. */
631 static int something_needs_operands_changed;
633 /* Nonzero means we couldn't get enough spill regs. */
636 /* Main entry point for the reload pass.
638 FIRST is the first insn of the function being compiled.
640 GLOBAL nonzero means we were called from global_alloc
641 and should attempt to reallocate any pseudoregs that we
642 displace from hard regs we will use for reloads.
643 If GLOBAL is zero, we do not have enough information to do that,
644 so any pseudo reg that is spilled must go to the stack.
646 Return value is nonzero if reload failed
647 and we must not do any more for this function. */
650 reload (rtx first, int global)
654 struct elim_table *ep;
657 /* Make sure even insns with volatile mem refs are recognizable. */
662 reload_firstobj = obstack_alloc (&reload_obstack, 0);
664 /* Make sure that the last insn in the chain
665 is not something that needs reloading. */
666 emit_note (NOTE_INSN_DELETED);
668 /* Enable find_equiv_reg to distinguish insns made by reload. */
669 reload_first_uid = get_max_uid ();
671 #ifdef SECONDARY_MEMORY_NEEDED
672 /* Initialize the secondary memory table. */
673 clear_secondary_mem ();
676 /* We don't have a stack slot for any spill reg yet. */
677 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
678 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
680 /* Initialize the save area information for caller-save, in case some
684 /* Compute which hard registers are now in use
685 as homes for pseudo registers.
686 This is done here rather than (eg) in global_alloc
687 because this point is reached even if not optimizing. */
688 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
691 /* A function that receives a nonlocal goto must save all call-saved
693 if (current_function_has_nonlocal_label)
694 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
695 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
696 regs_ever_live[i] = 1;
698 /* Find all the pseudo registers that didn't get hard regs
699 but do have known equivalent constants or memory slots.
700 These include parameters (known equivalent to parameter slots)
701 and cse'd or loop-moved constant memory addresses.
703 Record constant equivalents in reg_equiv_constant
704 so they will be substituted by find_reloads.
705 Record memory equivalents in reg_mem_equiv so they can
706 be substituted eventually by altering the REG-rtx's. */
708 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
709 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
710 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
711 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
712 reg_equiv_address = XCNEWVEC (rtx, max_regno);
713 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
714 reg_old_renumber = XCNEWVEC (short, max_regno);
715 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
716 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
717 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
719 CLEAR_HARD_REG_SET (bad_spill_regs_global);
721 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
722 to. Also find all paradoxical subregs and find largest such for
725 num_eliminable_invariants = 0;
726 for (insn = first; insn; insn = NEXT_INSN (insn))
728 rtx set = single_set (insn);
730 /* We may introduce USEs that we want to remove at the end, so
731 we'll mark them with QImode. Make sure there are no
732 previously-marked insns left by say regmove. */
733 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
734 && GET_MODE (insn) != VOIDmode)
735 PUT_MODE (insn, VOIDmode);
738 scan_paradoxical_subregs (PATTERN (insn));
740 if (set != 0 && REG_P (SET_DEST (set)))
742 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
748 i = REGNO (SET_DEST (set));
751 if (i <= LAST_VIRTUAL_REGISTER)
754 if (! function_invariant_p (x)
756 /* A function invariant is often CONSTANT_P but may
757 include a register. We promise to only pass
758 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
760 && LEGITIMATE_PIC_OPERAND_P (x)))
762 /* It can happen that a REG_EQUIV note contains a MEM
763 that is not a legitimate memory operand. As later
764 stages of reload assume that all addresses found
765 in the reg_equiv_* arrays were originally legitimate,
766 we ignore such REG_EQUIV notes. */
767 if (memory_operand (x, VOIDmode))
769 /* Always unshare the equivalence, so we can
770 substitute into this insn without touching the
772 reg_equiv_memory_loc[i] = copy_rtx (x);
774 else if (function_invariant_p (x))
776 if (GET_CODE (x) == PLUS)
778 /* This is PLUS of frame pointer and a constant,
779 and might be shared. Unshare it. */
780 reg_equiv_invariant[i] = copy_rtx (x);
781 num_eliminable_invariants++;
783 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
785 reg_equiv_invariant[i] = x;
786 num_eliminable_invariants++;
788 else if (LEGITIMATE_CONSTANT_P (x))
789 reg_equiv_constant[i] = x;
792 reg_equiv_memory_loc[i]
793 = force_const_mem (GET_MODE (SET_DEST (set)), x);
794 if (! reg_equiv_memory_loc[i])
795 reg_equiv_init[i] = NULL_RTX;
800 reg_equiv_init[i] = NULL_RTX;
805 reg_equiv_init[i] = NULL_RTX;
810 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
811 if (reg_equiv_init[i])
813 fprintf (dump_file, "init_insns for %u: ", i);
814 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
815 fprintf (dump_file, "\n");
820 first_label_num = get_first_label_num ();
821 num_labels = max_label_num () - first_label_num;
823 /* Allocate the tables used to store offset information at labels. */
824 /* We used to use alloca here, but the size of what it would try to
825 allocate would occasionally cause it to exceed the stack limit and
826 cause a core dump. */
827 offsets_known_at = XNEWVEC (char, num_labels);
828 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
830 /* Alter each pseudo-reg rtx to contain its hard reg number.
831 Assign stack slots to the pseudos that lack hard regs or equivalents.
832 Do not touch virtual registers. */
834 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
837 /* If we have some registers we think can be eliminated, scan all insns to
838 see if there is an insn that sets one of these registers to something
839 other than itself plus a constant. If so, the register cannot be
840 eliminated. Doing this scan here eliminates an extra pass through the
841 main reload loop in the most common case where register elimination
843 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
845 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
847 maybe_fix_stack_asms ();
849 insns_need_reload = 0;
850 something_needs_elimination = 0;
852 /* Initialize to -1, which means take the first spill register. */
855 /* Spill any hard regs that we know we can't eliminate. */
856 CLEAR_HARD_REG_SET (used_spill_regs);
857 /* There can be multiple ways to eliminate a register;
858 they should be listed adjacently.
859 Elimination for any register fails only if all possible ways fail. */
860 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
863 int can_eliminate = 0;
866 can_eliminate |= ep->can_eliminate;
869 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
871 spill_hard_reg (from, 1);
874 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
875 if (frame_pointer_needed)
876 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
878 finish_spills (global);
880 /* From now on, we may need to generate moves differently. We may also
881 allow modifications of insns which cause them to not be recognized.
882 Any such modifications will be cleaned up during reload itself. */
883 reload_in_progress = 1;
885 /* This loop scans the entire function each go-round
886 and repeats until one repetition spills no additional hard regs. */
889 int something_changed;
891 HOST_WIDE_INT starting_frame_size;
893 starting_frame_size = get_frame_size ();
895 set_initial_elim_offsets ();
896 set_initial_label_offsets ();
898 /* For each pseudo register that has an equivalent location defined,
899 try to eliminate any eliminable registers (such as the frame pointer)
900 assuming initial offsets for the replacement register, which
903 If the resulting location is directly addressable, substitute
904 the MEM we just got directly for the old REG.
906 If it is not addressable but is a constant or the sum of a hard reg
907 and constant, it is probably not addressable because the constant is
908 out of range, in that case record the address; we will generate
909 hairy code to compute the address in a register each time it is
910 needed. Similarly if it is a hard register, but one that is not
911 valid as an address register.
913 If the location is not addressable, but does not have one of the
914 above forms, assign a stack slot. We have to do this to avoid the
915 potential of producing lots of reloads if, e.g., a location involves
916 a pseudo that didn't get a hard register and has an equivalent memory
917 location that also involves a pseudo that didn't get a hard register.
919 Perhaps at some point we will improve reload_when_needed handling
920 so this problem goes away. But that's very hairy. */
922 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
923 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
925 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
927 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
929 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
930 else if (CONSTANT_P (XEXP (x, 0))
931 || (REG_P (XEXP (x, 0))
932 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
933 || (GET_CODE (XEXP (x, 0)) == PLUS
934 && REG_P (XEXP (XEXP (x, 0), 0))
935 && (REGNO (XEXP (XEXP (x, 0), 0))
936 < FIRST_PSEUDO_REGISTER)
937 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
938 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
941 /* Make a new stack slot. Then indicate that something
942 changed so we go back and recompute offsets for
943 eliminable registers because the allocation of memory
944 below might change some offset. reg_equiv_{mem,address}
945 will be set up for this pseudo on the next pass around
947 reg_equiv_memory_loc[i] = 0;
948 reg_equiv_init[i] = 0;
953 if (caller_save_needed)
956 /* If we allocated another stack slot, redo elimination bookkeeping. */
957 if (starting_frame_size != get_frame_size ())
959 if (starting_frame_size && cfun->stack_alignment_needed)
961 /* If we have a stack frame, we must align it now. The
962 stack size may be a part of the offset computation for
963 register elimination. So if this changes the stack size,
964 then repeat the elimination bookkeeping. We don't
965 realign when there is no stack, as that will cause a
966 stack frame when none is needed should
967 STARTING_FRAME_OFFSET not be already aligned to
969 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
970 if (starting_frame_size != get_frame_size ())
974 if (caller_save_needed)
976 save_call_clobbered_regs ();
977 /* That might have allocated new insn_chain structures. */
978 reload_firstobj = obstack_alloc (&reload_obstack, 0);
981 calculate_needs_all_insns (global);
983 CLEAR_REG_SET (&spilled_pseudos);
986 something_changed = 0;
988 /* If we allocated any new memory locations, make another pass
989 since it might have changed elimination offsets. */
990 if (starting_frame_size != get_frame_size ())
991 something_changed = 1;
993 /* Even if the frame size remained the same, we might still have
994 changed elimination offsets, e.g. if find_reloads called
995 force_const_mem requiring the back end to allocate a constant
996 pool base register that needs to be saved on the stack. */
997 else if (!verify_initial_elim_offsets ())
998 something_changed = 1;
1001 HARD_REG_SET to_spill;
1002 CLEAR_HARD_REG_SET (to_spill);
1003 update_eliminables (&to_spill);
1004 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
1006 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1007 if (TEST_HARD_REG_BIT (to_spill, i))
1009 spill_hard_reg (i, 1);
1012 /* Regardless of the state of spills, if we previously had
1013 a register that we thought we could eliminate, but now can
1014 not eliminate, we must run another pass.
1016 Consider pseudos which have an entry in reg_equiv_* which
1017 reference an eliminable register. We must make another pass
1018 to update reg_equiv_* so that we do not substitute in the
1019 old value from when we thought the elimination could be
1021 something_changed = 1;
1025 select_reload_regs ();
1029 if (insns_need_reload != 0 || did_spill)
1030 something_changed |= finish_spills (global);
1032 if (! something_changed)
1035 if (caller_save_needed)
1036 delete_caller_save_insns ();
1038 obstack_free (&reload_obstack, reload_firstobj);
1041 /* If global-alloc was run, notify it of any register eliminations we have
1044 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1045 if (ep->can_eliminate)
1046 mark_elimination (ep->from, ep->to);
1048 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1049 If that insn didn't set the register (i.e., it copied the register to
1050 memory), just delete that insn instead of the equivalencing insn plus
1051 anything now dead. If we call delete_dead_insn on that insn, we may
1052 delete the insn that actually sets the register if the register dies
1053 there and that is incorrect. */
1055 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1057 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1060 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1062 rtx equiv_insn = XEXP (list, 0);
1064 /* If we already deleted the insn or if it may trap, we can't
1065 delete it. The latter case shouldn't happen, but can
1066 if an insn has a variable address, gets a REG_EH_REGION
1067 note added to it, and then gets converted into a load
1068 from a constant address. */
1069 if (NOTE_P (equiv_insn)
1070 || can_throw_internal (equiv_insn))
1072 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1073 delete_dead_insn (equiv_insn);
1075 SET_INSN_DELETED (equiv_insn);
1080 /* Use the reload registers where necessary
1081 by generating move instructions to move the must-be-register
1082 values into or out of the reload registers. */
1084 if (insns_need_reload != 0 || something_needs_elimination
1085 || something_needs_operands_changed)
1087 HOST_WIDE_INT old_frame_size = get_frame_size ();
1089 reload_as_needed (global);
1091 gcc_assert (old_frame_size == get_frame_size ());
1093 gcc_assert (verify_initial_elim_offsets ());
1096 /* If we were able to eliminate the frame pointer, show that it is no
1097 longer live at the start of any basic block. If it ls live by
1098 virtue of being in a pseudo, that pseudo will be marked live
1099 and hence the frame pointer will be known to be live via that
1102 if (! frame_pointer_needed)
1104 CLEAR_REGNO_REG_SET (bb->il.rtl->global_live_at_start,
1105 HARD_FRAME_POINTER_REGNUM);
1107 /* Come here (with failure set nonzero) if we can't get enough spill
1111 CLEAR_REG_SET (&spilled_pseudos);
1112 reload_in_progress = 0;
1114 /* Now eliminate all pseudo regs by modifying them into
1115 their equivalent memory references.
1116 The REG-rtx's for the pseudos are modified in place,
1117 so all insns that used to refer to them now refer to memory.
1119 For a reg that has a reg_equiv_address, all those insns
1120 were changed by reloading so that no insns refer to it any longer;
1121 but the DECL_RTL of a variable decl may refer to it,
1122 and if so this causes the debugging info to mention the variable. */
1124 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1128 if (reg_equiv_mem[i])
1129 addr = XEXP (reg_equiv_mem[i], 0);
1131 if (reg_equiv_address[i])
1132 addr = reg_equiv_address[i];
1136 if (reg_renumber[i] < 0)
1138 rtx reg = regno_reg_rtx[i];
1140 REG_USERVAR_P (reg) = 0;
1141 PUT_CODE (reg, MEM);
1142 XEXP (reg, 0) = addr;
1143 if (reg_equiv_memory_loc[i])
1144 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1147 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1148 MEM_ATTRS (reg) = 0;
1150 MEM_NOTRAP_P (reg) = 1;
1152 else if (reg_equiv_mem[i])
1153 XEXP (reg_equiv_mem[i], 0) = addr;
1157 /* We must set reload_completed now since the cleanup_subreg_operands call
1158 below will re-recognize each insn and reload may have generated insns
1159 which are only valid during and after reload. */
1160 reload_completed = 1;
1162 /* Make a pass over all the insns and delete all USEs which we inserted
1163 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1164 notes. Delete all CLOBBER insns, except those that refer to the return
1165 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1166 from misarranging variable-array code, and simplify (subreg (reg))
1167 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1168 are no longer useful or accurate. Strip and regenerate REG_INC notes
1169 that may have been moved around. */
1171 for (insn = first; insn; insn = NEXT_INSN (insn))
1176 /* Clean up invalid ASMs so that they don't confuse later passes.
1178 if (asm_noperands (PATTERN (insn)) >= 0)
1180 extract_insn (insn);
1181 if (!constrain_operands (1))
1183 error_for_asm (insn,
1184 "%<asm%> operand has impossible constraints");
1191 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1192 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1194 if ((GET_CODE (PATTERN (insn)) == USE
1195 /* We mark with QImode USEs introduced by reload itself. */
1196 && (GET_MODE (insn) == QImode
1197 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1198 || (GET_CODE (PATTERN (insn)) == CLOBBER
1199 && (!MEM_P (XEXP (PATTERN (insn), 0))
1200 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1201 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1202 && XEXP (XEXP (PATTERN (insn), 0), 0)
1203 != stack_pointer_rtx))
1204 && (!REG_P (XEXP (PATTERN (insn), 0))
1205 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1211 /* Some CLOBBERs may survive until here and still reference unassigned
1212 pseudos with const equivalent, which may in turn cause ICE in later
1213 passes if the reference remains in place. */
1214 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1215 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1216 VOIDmode, PATTERN (insn));
1218 /* Discard obvious no-ops, even without -O. This optimization
1219 is fast and doesn't interfere with debugging. */
1220 if (NONJUMP_INSN_P (insn)
1221 && GET_CODE (PATTERN (insn)) == SET
1222 && REG_P (SET_SRC (PATTERN (insn)))
1223 && REG_P (SET_DEST (PATTERN (insn)))
1224 && (REGNO (SET_SRC (PATTERN (insn)))
1225 == REGNO (SET_DEST (PATTERN (insn)))))
1231 pnote = ®_NOTES (insn);
1234 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1235 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1236 || REG_NOTE_KIND (*pnote) == REG_INC
1237 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1238 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1239 *pnote = XEXP (*pnote, 1);
1241 pnote = &XEXP (*pnote, 1);
1245 add_auto_inc_notes (insn, PATTERN (insn));
1248 /* And simplify (subreg (reg)) if it appears as an operand. */
1249 cleanup_subreg_operands (insn);
1252 /* If we are doing stack checking, give a warning if this function's
1253 frame size is larger than we expect. */
1254 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1256 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1257 static int verbose_warned = 0;
1259 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1260 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1261 size += UNITS_PER_WORD;
1263 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1265 warning (0, "frame size too large for reliable stack checking");
1266 if (! verbose_warned)
1268 warning (0, "try reducing the number of local variables");
1274 /* Indicate that we no longer have known memory locations or constants. */
1275 if (reg_equiv_constant)
1276 free (reg_equiv_constant);
1277 if (reg_equiv_invariant)
1278 free (reg_equiv_invariant);
1279 reg_equiv_constant = 0;
1280 reg_equiv_invariant = 0;
1281 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1282 reg_equiv_memory_loc = 0;
1284 if (offsets_known_at)
1285 free (offsets_known_at);
1289 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1290 if (reg_equiv_alt_mem_list[i])
1291 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1292 free (reg_equiv_alt_mem_list);
1294 free (reg_equiv_mem);
1296 free (reg_equiv_address);
1297 free (reg_max_ref_width);
1298 free (reg_old_renumber);
1299 free (pseudo_previous_regs);
1300 free (pseudo_forbidden_regs);
1302 CLEAR_HARD_REG_SET (used_spill_regs);
1303 for (i = 0; i < n_spills; i++)
1304 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1306 /* Free all the insn_chain structures at once. */
1307 obstack_free (&reload_obstack, reload_startobj);
1308 unused_insn_chains = 0;
1309 fixup_abnormal_edges ();
1311 /* Replacing pseudos with their memory equivalents might have
1312 created shared rtx. Subsequent passes would get confused
1313 by this, so unshare everything here. */
1314 unshare_all_rtl_again (first);
1316 #ifdef STACK_BOUNDARY
1317 /* init_emit has set the alignment of the hard frame pointer
1318 to STACK_BOUNDARY. It is very likely no longer valid if
1319 the hard frame pointer was used for register allocation. */
1320 if (!frame_pointer_needed)
1321 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1327 /* Yet another special case. Unfortunately, reg-stack forces people to
1328 write incorrect clobbers in asm statements. These clobbers must not
1329 cause the register to appear in bad_spill_regs, otherwise we'll call
1330 fatal_insn later. We clear the corresponding regnos in the live
1331 register sets to avoid this.
1332 The whole thing is rather sick, I'm afraid. */
1335 maybe_fix_stack_asms (void)
1338 const char *constraints[MAX_RECOG_OPERANDS];
1339 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1340 struct insn_chain *chain;
1342 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1345 HARD_REG_SET clobbered, allowed;
1348 if (! INSN_P (chain->insn)
1349 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1351 pat = PATTERN (chain->insn);
1352 if (GET_CODE (pat) != PARALLEL)
1355 CLEAR_HARD_REG_SET (clobbered);
1356 CLEAR_HARD_REG_SET (allowed);
1358 /* First, make a mask of all stack regs that are clobbered. */
1359 for (i = 0; i < XVECLEN (pat, 0); i++)
1361 rtx t = XVECEXP (pat, 0, i);
1362 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1363 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1366 /* Get the operand values and constraints out of the insn. */
1367 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1368 constraints, operand_mode);
1370 /* For every operand, see what registers are allowed. */
1371 for (i = 0; i < noperands; i++)
1373 const char *p = constraints[i];
1374 /* For every alternative, we compute the class of registers allowed
1375 for reloading in CLS, and merge its contents into the reg set
1377 int cls = (int) NO_REGS;
1383 if (c == '\0' || c == ',' || c == '#')
1385 /* End of one alternative - mark the regs in the current
1386 class, and reset the class. */
1387 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1393 } while (c != '\0' && c != ',');
1401 case '=': case '+': case '*': case '%': case '?': case '!':
1402 case '0': case '1': case '2': case '3': case '4': case 'm':
1403 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1404 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1405 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1410 cls = (int) reg_class_subunion[cls]
1411 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1416 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1420 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1421 cls = (int) reg_class_subunion[cls]
1422 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1424 cls = (int) reg_class_subunion[cls]
1425 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1427 p += CONSTRAINT_LEN (c, p);
1430 /* Those of the registers which are clobbered, but allowed by the
1431 constraints, must be usable as reload registers. So clear them
1432 out of the life information. */
1433 AND_HARD_REG_SET (allowed, clobbered);
1434 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1435 if (TEST_HARD_REG_BIT (allowed, i))
1437 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1438 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1445 /* Copy the global variables n_reloads and rld into the corresponding elts
1448 copy_reloads (struct insn_chain *chain)
1450 chain->n_reloads = n_reloads;
1451 chain->rld = obstack_alloc (&reload_obstack,
1452 n_reloads * sizeof (struct reload));
1453 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1454 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1457 /* Walk the chain of insns, and determine for each whether it needs reloads
1458 and/or eliminations. Build the corresponding insns_need_reload list, and
1459 set something_needs_elimination as appropriate. */
1461 calculate_needs_all_insns (int global)
1463 struct insn_chain **pprev_reload = &insns_need_reload;
1464 struct insn_chain *chain, *next = 0;
1466 something_needs_elimination = 0;
1468 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1469 for (chain = reload_insn_chain; chain != 0; chain = next)
1471 rtx insn = chain->insn;
1475 /* Clear out the shortcuts. */
1476 chain->n_reloads = 0;
1477 chain->need_elim = 0;
1478 chain->need_reload = 0;
1479 chain->need_operand_change = 0;
1481 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1482 include REG_LABEL), we need to see what effects this has on the
1483 known offsets at labels. */
1485 if (LABEL_P (insn) || JUMP_P (insn)
1486 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1487 set_label_offsets (insn, insn, 0);
1491 rtx old_body = PATTERN (insn);
1492 int old_code = INSN_CODE (insn);
1493 rtx old_notes = REG_NOTES (insn);
1494 int did_elimination = 0;
1495 int operands_changed = 0;
1496 rtx set = single_set (insn);
1498 /* Skip insns that only set an equivalence. */
1499 if (set && REG_P (SET_DEST (set))
1500 && reg_renumber[REGNO (SET_DEST (set))] < 0
1501 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1502 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1503 && reg_equiv_init[REGNO (SET_DEST (set))])
1506 /* If needed, eliminate any eliminable registers. */
1507 if (num_eliminable || num_eliminable_invariants)
1508 did_elimination = eliminate_regs_in_insn (insn, 0);
1510 /* Analyze the instruction. */
1511 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1512 global, spill_reg_order);
1514 /* If a no-op set needs more than one reload, this is likely
1515 to be something that needs input address reloads. We
1516 can't get rid of this cleanly later, and it is of no use
1517 anyway, so discard it now.
1518 We only do this when expensive_optimizations is enabled,
1519 since this complements reload inheritance / output
1520 reload deletion, and it can make debugging harder. */
1521 if (flag_expensive_optimizations && n_reloads > 1)
1523 rtx set = single_set (insn);
1525 && SET_SRC (set) == SET_DEST (set)
1526 && REG_P (SET_SRC (set))
1527 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1530 /* Delete it from the reload chain. */
1532 chain->prev->next = next;
1534 reload_insn_chain = next;
1536 next->prev = chain->prev;
1537 chain->next = unused_insn_chains;
1538 unused_insn_chains = chain;
1543 update_eliminable_offsets ();
1545 /* Remember for later shortcuts which insns had any reloads or
1546 register eliminations. */
1547 chain->need_elim = did_elimination;
1548 chain->need_reload = n_reloads > 0;
1549 chain->need_operand_change = operands_changed;
1551 /* Discard any register replacements done. */
1552 if (did_elimination)
1554 obstack_free (&reload_obstack, reload_insn_firstobj);
1555 PATTERN (insn) = old_body;
1556 INSN_CODE (insn) = old_code;
1557 REG_NOTES (insn) = old_notes;
1558 something_needs_elimination = 1;
1561 something_needs_operands_changed |= operands_changed;
1565 copy_reloads (chain);
1566 *pprev_reload = chain;
1567 pprev_reload = &chain->next_need_reload;
1574 /* Comparison function for qsort to decide which of two reloads
1575 should be handled first. *P1 and *P2 are the reload numbers. */
1578 reload_reg_class_lower (const void *r1p, const void *r2p)
1580 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1583 /* Consider required reloads before optional ones. */
1584 t = rld[r1].optional - rld[r2].optional;
1588 /* Count all solitary classes before non-solitary ones. */
1589 t = ((reg_class_size[(int) rld[r2].class] == 1)
1590 - (reg_class_size[(int) rld[r1].class] == 1));
1594 /* Aside from solitaires, consider all multi-reg groups first. */
1595 t = rld[r2].nregs - rld[r1].nregs;
1599 /* Consider reloads in order of increasing reg-class number. */
1600 t = (int) rld[r1].class - (int) rld[r2].class;
1604 /* If reloads are equally urgent, sort by reload number,
1605 so that the results of qsort leave nothing to chance. */
1609 /* The cost of spilling each hard reg. */
1610 static int spill_cost[FIRST_PSEUDO_REGISTER];
1612 /* When spilling multiple hard registers, we use SPILL_COST for the first
1613 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1614 only the first hard reg for a multi-reg pseudo. */
1615 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1617 /* Update the spill cost arrays, considering that pseudo REG is live. */
1620 count_pseudo (int reg)
1622 int freq = REG_FREQ (reg);
1623 int r = reg_renumber[reg];
1626 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1627 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1630 SET_REGNO_REG_SET (&pseudos_counted, reg);
1632 gcc_assert (r >= 0);
1634 spill_add_cost[r] += freq;
1636 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1638 spill_cost[r + nregs] += freq;
1641 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1642 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1645 order_regs_for_reload (struct insn_chain *chain)
1648 HARD_REG_SET used_by_pseudos;
1649 HARD_REG_SET used_by_pseudos2;
1650 reg_set_iterator rsi;
1652 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1654 memset (spill_cost, 0, sizeof spill_cost);
1655 memset (spill_add_cost, 0, sizeof spill_add_cost);
1657 /* Count number of uses of each hard reg by pseudo regs allocated to it
1658 and then order them by decreasing use. First exclude hard registers
1659 that are live in or across this insn. */
1661 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1662 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1663 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1664 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1666 /* Now find out which pseudos are allocated to it, and update
1668 CLEAR_REG_SET (&pseudos_counted);
1670 EXECUTE_IF_SET_IN_REG_SET
1671 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1675 EXECUTE_IF_SET_IN_REG_SET
1676 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1680 CLEAR_REG_SET (&pseudos_counted);
1683 /* Vector of reload-numbers showing the order in which the reloads should
1685 static short reload_order[MAX_RELOADS];
1687 /* This is used to keep track of the spill regs used in one insn. */
1688 static HARD_REG_SET used_spill_regs_local;
1690 /* We decided to spill hard register SPILLED, which has a size of
1691 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1692 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1693 update SPILL_COST/SPILL_ADD_COST. */
1696 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1698 int r = reg_renumber[reg];
1699 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1701 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1702 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1705 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1707 spill_add_cost[r] -= REG_FREQ (reg);
1709 spill_cost[r + nregs] -= REG_FREQ (reg);
1712 /* Find reload register to use for reload number ORDER. */
1715 find_reg (struct insn_chain *chain, int order)
1717 int rnum = reload_order[order];
1718 struct reload *rl = rld + rnum;
1719 int best_cost = INT_MAX;
1723 HARD_REG_SET not_usable;
1724 HARD_REG_SET used_by_other_reload;
1725 reg_set_iterator rsi;
1727 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1728 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1729 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1731 CLEAR_HARD_REG_SET (used_by_other_reload);
1732 for (k = 0; k < order; k++)
1734 int other = reload_order[k];
1736 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1737 for (j = 0; j < rld[other].nregs; j++)
1738 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1741 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1743 unsigned int regno = i;
1745 if (! TEST_HARD_REG_BIT (not_usable, regno)
1746 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1747 && HARD_REGNO_MODE_OK (regno, rl->mode))
1749 int this_cost = spill_cost[regno];
1751 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1753 for (j = 1; j < this_nregs; j++)
1755 this_cost += spill_add_cost[regno + j];
1756 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1757 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1762 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1764 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1766 if (this_cost < best_cost
1767 /* Among registers with equal cost, prefer caller-saved ones, or
1768 use REG_ALLOC_ORDER if it is defined. */
1769 || (this_cost == best_cost
1770 #ifdef REG_ALLOC_ORDER
1771 && (inv_reg_alloc_order[regno]
1772 < inv_reg_alloc_order[best_reg])
1774 && call_used_regs[regno]
1775 && ! call_used_regs[best_reg]
1780 best_cost = this_cost;
1788 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1790 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1791 rl->regno = best_reg;
1793 EXECUTE_IF_SET_IN_REG_SET
1794 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1796 count_spilled_pseudo (best_reg, rl->nregs, j);
1799 EXECUTE_IF_SET_IN_REG_SET
1800 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1802 count_spilled_pseudo (best_reg, rl->nregs, j);
1805 for (i = 0; i < rl->nregs; i++)
1807 gcc_assert (spill_cost[best_reg + i] == 0);
1808 gcc_assert (spill_add_cost[best_reg + i] == 0);
1809 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1814 /* Find more reload regs to satisfy the remaining need of an insn, which
1816 Do it by ascending class number, since otherwise a reg
1817 might be spilled for a big class and might fail to count
1818 for a smaller class even though it belongs to that class. */
1821 find_reload_regs (struct insn_chain *chain)
1825 /* In order to be certain of getting the registers we need,
1826 we must sort the reloads into order of increasing register class.
1827 Then our grabbing of reload registers will parallel the process
1828 that provided the reload registers. */
1829 for (i = 0; i < chain->n_reloads; i++)
1831 /* Show whether this reload already has a hard reg. */
1832 if (chain->rld[i].reg_rtx)
1834 int regno = REGNO (chain->rld[i].reg_rtx);
1835 chain->rld[i].regno = regno;
1837 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1840 chain->rld[i].regno = -1;
1841 reload_order[i] = i;
1844 n_reloads = chain->n_reloads;
1845 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1847 CLEAR_HARD_REG_SET (used_spill_regs_local);
1850 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1852 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1854 /* Compute the order of preference for hard registers to spill. */
1856 order_regs_for_reload (chain);
1858 for (i = 0; i < n_reloads; i++)
1860 int r = reload_order[i];
1862 /* Ignore reloads that got marked inoperative. */
1863 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1864 && ! rld[r].optional
1865 && rld[r].regno == -1)
1866 if (! find_reg (chain, i))
1869 fprintf (dump_file, "reload failure for reload %d\n", r);
1870 spill_failure (chain->insn, rld[r].class);
1876 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1877 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1879 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1883 select_reload_regs (void)
1885 struct insn_chain *chain;
1887 /* Try to satisfy the needs for each insn. */
1888 for (chain = insns_need_reload; chain != 0;
1889 chain = chain->next_need_reload)
1890 find_reload_regs (chain);
1893 /* Delete all insns that were inserted by emit_caller_save_insns during
1896 delete_caller_save_insns (void)
1898 struct insn_chain *c = reload_insn_chain;
1902 while (c != 0 && c->is_caller_save_insn)
1904 struct insn_chain *next = c->next;
1907 if (c == reload_insn_chain)
1908 reload_insn_chain = next;
1912 next->prev = c->prev;
1914 c->prev->next = next;
1915 c->next = unused_insn_chains;
1916 unused_insn_chains = c;
1924 /* Handle the failure to find a register to spill.
1925 INSN should be one of the insns which needed this particular spill reg. */
1928 spill_failure (rtx insn, enum reg_class class)
1930 if (asm_noperands (PATTERN (insn)) >= 0)
1931 error_for_asm (insn, "can't find a register in class %qs while "
1932 "reloading %<asm%>",
1933 reg_class_names[class]);
1936 error ("unable to find a register to spill in class %qs",
1937 reg_class_names[class]);
1941 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
1942 debug_reload_to_stream (dump_file);
1944 fatal_insn ("this is the insn:", insn);
1948 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1949 data that is dead in INSN. */
1952 delete_dead_insn (rtx insn)
1954 rtx prev = prev_real_insn (insn);
1957 /* If the previous insn sets a register that dies in our insn, delete it
1959 if (prev && GET_CODE (PATTERN (prev)) == SET
1960 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
1961 && reg_mentioned_p (prev_dest, PATTERN (insn))
1962 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1963 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1964 delete_dead_insn (prev);
1966 SET_INSN_DELETED (insn);
1969 /* Modify the home of pseudo-reg I.
1970 The new home is present in reg_renumber[I].
1972 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1973 or it may be -1, meaning there is none or it is not relevant.
1974 This is used so that all pseudos spilled from a given hard reg
1975 can share one stack slot. */
1978 alter_reg (int i, int from_reg)
1980 /* When outputting an inline function, this can happen
1981 for a reg that isn't actually used. */
1982 if (regno_reg_rtx[i] == 0)
1985 /* If the reg got changed to a MEM at rtl-generation time,
1987 if (!REG_P (regno_reg_rtx[i]))
1990 /* Modify the reg-rtx to contain the new hard reg
1991 number or else to contain its pseudo reg number. */
1992 REGNO (regno_reg_rtx[i])
1993 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1995 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1996 allocate a stack slot for it. */
1998 if (reg_renumber[i] < 0
1999 && REG_N_REFS (i) > 0
2000 && reg_equiv_constant[i] == 0
2001 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
2002 && reg_equiv_memory_loc[i] == 0)
2005 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2006 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2007 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2008 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2009 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2012 /* Each pseudo reg has an inherent size which comes from its own mode,
2013 and a total size which provides room for paradoxical subregs
2014 which refer to the pseudo reg in wider modes.
2016 We can use a slot already allocated if it provides both
2017 enough inherent space and enough total space.
2018 Otherwise, we allocate a new slot, making sure that it has no less
2019 inherent space, and no less total space, then the previous slot. */
2022 /* No known place to spill from => no slot to reuse. */
2023 x = assign_stack_local (mode, total_size,
2024 min_align > inherent_align
2025 || total_size > inherent_size ? -1 : 0);
2026 if (BYTES_BIG_ENDIAN)
2027 /* Cancel the big-endian correction done in assign_stack_local.
2028 Get the address of the beginning of the slot.
2029 This is so we can do a big-endian correction unconditionally
2031 adjust = inherent_size - total_size;
2033 /* Nothing can alias this slot except this pseudo. */
2034 set_mem_alias_set (x, new_alias_set ());
2037 /* Reuse a stack slot if possible. */
2038 else if (spill_stack_slot[from_reg] != 0
2039 && spill_stack_slot_width[from_reg] >= total_size
2040 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2042 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2043 x = spill_stack_slot[from_reg];
2045 /* Allocate a bigger slot. */
2048 /* Compute maximum size needed, both for inherent size
2049 and for total size. */
2052 if (spill_stack_slot[from_reg])
2054 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2056 mode = GET_MODE (spill_stack_slot[from_reg]);
2057 if (spill_stack_slot_width[from_reg] > total_size)
2058 total_size = spill_stack_slot_width[from_reg];
2059 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2060 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2063 /* Make a slot with that size. */
2064 x = assign_stack_local (mode, total_size,
2065 min_align > inherent_align
2066 || total_size > inherent_size ? -1 : 0);
2069 /* All pseudos mapped to this slot can alias each other. */
2070 if (spill_stack_slot[from_reg])
2071 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2073 set_mem_alias_set (x, new_alias_set ());
2075 if (BYTES_BIG_ENDIAN)
2077 /* Cancel the big-endian correction done in assign_stack_local.
2078 Get the address of the beginning of the slot.
2079 This is so we can do a big-endian correction unconditionally
2081 adjust = GET_MODE_SIZE (mode) - total_size;
2084 = adjust_address_nv (x, mode_for_size (total_size
2090 spill_stack_slot[from_reg] = stack_slot;
2091 spill_stack_slot_width[from_reg] = total_size;
2094 /* On a big endian machine, the "address" of the slot
2095 is the address of the low part that fits its inherent mode. */
2096 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2097 adjust += (total_size - inherent_size);
2099 /* If we have any adjustment to make, or if the stack slot is the
2100 wrong mode, make a new stack slot. */
2101 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2103 /* If we have a decl for the original register, set it for the
2104 memory. If this is a shared MEM, make a copy. */
2105 if (REG_EXPR (regno_reg_rtx[i])
2106 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2108 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2110 /* We can do this only for the DECLs home pseudo, not for
2111 any copies of it, since otherwise when the stack slot
2112 is reused, nonoverlapping_memrefs_p might think they
2114 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2116 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2119 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2123 /* Save the stack slot for later. */
2124 reg_equiv_memory_loc[i] = x;
2128 /* Mark the slots in regs_ever_live for the hard regs
2129 used by pseudo-reg number REGNO. */
2132 mark_home_live (int regno)
2136 i = reg_renumber[regno];
2139 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2141 regs_ever_live[i++] = 1;
2144 /* This function handles the tracking of elimination offsets around branches.
2146 X is a piece of RTL being scanned.
2148 INSN is the insn that it came from, if any.
2150 INITIAL_P is nonzero if we are to set the offset to be the initial
2151 offset and zero if we are setting the offset of the label to be the
2155 set_label_offsets (rtx x, rtx insn, int initial_p)
2157 enum rtx_code code = GET_CODE (x);
2160 struct elim_table *p;
2165 if (LABEL_REF_NONLOCAL_P (x))
2170 /* ... fall through ... */
2173 /* If we know nothing about this label, set the desired offsets. Note
2174 that this sets the offset at a label to be the offset before a label
2175 if we don't know anything about the label. This is not correct for
2176 the label after a BARRIER, but is the best guess we can make. If
2177 we guessed wrong, we will suppress an elimination that might have
2178 been possible had we been able to guess correctly. */
2180 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2182 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2183 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2184 = (initial_p ? reg_eliminate[i].initial_offset
2185 : reg_eliminate[i].offset);
2186 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2189 /* Otherwise, if this is the definition of a label and it is
2190 preceded by a BARRIER, set our offsets to the known offset of
2194 && (tem = prev_nonnote_insn (insn)) != 0
2196 set_offsets_for_label (insn);
2198 /* If neither of the above cases is true, compare each offset
2199 with those previously recorded and suppress any eliminations
2200 where the offsets disagree. */
2202 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2203 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2204 != (initial_p ? reg_eliminate[i].initial_offset
2205 : reg_eliminate[i].offset))
2206 reg_eliminate[i].can_eliminate = 0;
2211 set_label_offsets (PATTERN (insn), insn, initial_p);
2213 /* ... fall through ... */
2217 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2218 and hence must have all eliminations at their initial offsets. */
2219 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2220 if (REG_NOTE_KIND (tem) == REG_LABEL)
2221 set_label_offsets (XEXP (tem, 0), insn, 1);
2227 /* Each of the labels in the parallel or address vector must be
2228 at their initial offsets. We want the first field for PARALLEL
2229 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2231 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2232 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2237 /* We only care about setting PC. If the source is not RETURN,
2238 IF_THEN_ELSE, or a label, disable any eliminations not at
2239 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2240 isn't one of those possibilities. For branches to a label,
2241 call ourselves recursively.
2243 Note that this can disable elimination unnecessarily when we have
2244 a non-local goto since it will look like a non-constant jump to
2245 someplace in the current function. This isn't a significant
2246 problem since such jumps will normally be when all elimination
2247 pairs are back to their initial offsets. */
2249 if (SET_DEST (x) != pc_rtx)
2252 switch (GET_CODE (SET_SRC (x)))
2259 set_label_offsets (SET_SRC (x), insn, initial_p);
2263 tem = XEXP (SET_SRC (x), 1);
2264 if (GET_CODE (tem) == LABEL_REF)
2265 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2266 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2269 tem = XEXP (SET_SRC (x), 2);
2270 if (GET_CODE (tem) == LABEL_REF)
2271 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2272 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2280 /* If we reach here, all eliminations must be at their initial
2281 offset because we are doing a jump to a variable address. */
2282 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2283 if (p->offset != p->initial_offset)
2284 p->can_eliminate = 0;
2292 /* Scan X and replace any eliminable registers (such as fp) with a
2293 replacement (such as sp), plus an offset.
2295 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2296 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2297 MEM, we are allowed to replace a sum of a register and the constant zero
2298 with the register, which we cannot do outside a MEM. In addition, we need
2299 to record the fact that a register is referenced outside a MEM.
2301 If INSN is an insn, it is the insn containing X. If we replace a REG
2302 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2303 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2304 the REG is being modified.
2306 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2307 That's used when we eliminate in expressions stored in notes.
2308 This means, do not set ref_outside_mem even if the reference
2311 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2312 replacements done assuming all offsets are at their initial values. If
2313 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2314 encounter, return the actual location so that find_reloads will do
2315 the proper thing. */
2318 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2319 bool may_use_invariant)
2321 enum rtx_code code = GET_CODE (x);
2322 struct elim_table *ep;
2329 if (! current_function_decl)
2351 /* First handle the case where we encounter a bare register that
2352 is eliminable. Replace it with a PLUS. */
2353 if (regno < FIRST_PSEUDO_REGISTER)
2355 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2357 if (ep->from_rtx == x && ep->can_eliminate)
2358 return plus_constant (ep->to_rtx, ep->previous_offset);
2361 else if (reg_renumber && reg_renumber[regno] < 0
2362 && reg_equiv_invariant && reg_equiv_invariant[regno])
2364 if (may_use_invariant)
2365 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2366 mem_mode, insn, true);
2367 /* There exists at least one use of REGNO that cannot be
2368 eliminated. Prevent the defining insn from being deleted. */
2369 reg_equiv_init[regno] = NULL_RTX;
2370 alter_reg (regno, -1);
2374 /* You might think handling MINUS in a manner similar to PLUS is a
2375 good idea. It is not. It has been tried multiple times and every
2376 time the change has had to have been reverted.
2378 Other parts of reload know a PLUS is special (gen_reload for example)
2379 and require special code to handle code a reloaded PLUS operand.
2381 Also consider backends where the flags register is clobbered by a
2382 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2383 lea instruction comes to mind). If we try to reload a MINUS, we
2384 may kill the flags register that was holding a useful value.
2386 So, please before trying to handle MINUS, consider reload as a
2387 whole instead of this little section as well as the backend issues. */
2389 /* If this is the sum of an eliminable register and a constant, rework
2391 if (REG_P (XEXP (x, 0))
2392 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2393 && CONSTANT_P (XEXP (x, 1)))
2395 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2397 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2399 /* The only time we want to replace a PLUS with a REG (this
2400 occurs when the constant operand of the PLUS is the negative
2401 of the offset) is when we are inside a MEM. We won't want
2402 to do so at other times because that would change the
2403 structure of the insn in a way that reload can't handle.
2404 We special-case the commonest situation in
2405 eliminate_regs_in_insn, so just replace a PLUS with a
2406 PLUS here, unless inside a MEM. */
2407 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2408 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2411 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2412 plus_constant (XEXP (x, 1),
2413 ep->previous_offset));
2416 /* If the register is not eliminable, we are done since the other
2417 operand is a constant. */
2421 /* If this is part of an address, we want to bring any constant to the
2422 outermost PLUS. We will do this by doing register replacement in
2423 our operands and seeing if a constant shows up in one of them.
2425 Note that there is no risk of modifying the structure of the insn,
2426 since we only get called for its operands, thus we are either
2427 modifying the address inside a MEM, or something like an address
2428 operand of a load-address insn. */
2431 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2432 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2434 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2436 /* If one side is a PLUS and the other side is a pseudo that
2437 didn't get a hard register but has a reg_equiv_constant,
2438 we must replace the constant here since it may no longer
2439 be in the position of any operand. */
2440 if (GET_CODE (new0) == PLUS && REG_P (new1)
2441 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2442 && reg_renumber[REGNO (new1)] < 0
2443 && reg_equiv_constant != 0
2444 && reg_equiv_constant[REGNO (new1)] != 0)
2445 new1 = reg_equiv_constant[REGNO (new1)];
2446 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2447 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2448 && reg_renumber[REGNO (new0)] < 0
2449 && reg_equiv_constant[REGNO (new0)] != 0)
2450 new0 = reg_equiv_constant[REGNO (new0)];
2452 new = form_sum (new0, new1);
2454 /* As above, if we are not inside a MEM we do not want to
2455 turn a PLUS into something else. We might try to do so here
2456 for an addition of 0 if we aren't optimizing. */
2457 if (! mem_mode && GET_CODE (new) != PLUS)
2458 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2466 /* If this is the product of an eliminable register and a
2467 constant, apply the distribute law and move the constant out
2468 so that we have (plus (mult ..) ..). This is needed in order
2469 to keep load-address insns valid. This case is pathological.
2470 We ignore the possibility of overflow here. */
2471 if (REG_P (XEXP (x, 0))
2472 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2473 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2474 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2476 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2479 /* Refs inside notes don't count for this purpose. */
2480 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2481 || GET_CODE (insn) == INSN_LIST)))
2482 ep->ref_outside_mem = 1;
2485 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2486 ep->previous_offset * INTVAL (XEXP (x, 1)));
2489 /* ... fall through ... */
2493 /* See comments before PLUS about handling MINUS. */
2495 case DIV: case UDIV:
2496 case MOD: case UMOD:
2497 case AND: case IOR: case XOR:
2498 case ROTATERT: case ROTATE:
2499 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2501 case GE: case GT: case GEU: case GTU:
2502 case LE: case LT: case LEU: case LTU:
2504 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2505 rtx new1 = XEXP (x, 1)
2506 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2508 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2509 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2514 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2517 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2518 if (new != XEXP (x, 0))
2520 /* If this is a REG_DEAD note, it is not valid anymore.
2521 Using the eliminated version could result in creating a
2522 REG_DEAD note for the stack or frame pointer. */
2523 if (GET_MODE (x) == REG_DEAD)
2525 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2528 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2532 /* ... fall through ... */
2535 /* Now do eliminations in the rest of the chain. If this was
2536 an EXPR_LIST, this might result in allocating more memory than is
2537 strictly needed, but it simplifies the code. */
2540 new = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2541 if (new != XEXP (x, 1))
2543 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2551 case STRICT_LOW_PART:
2553 case SIGN_EXTEND: case ZERO_EXTEND:
2554 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2555 case FLOAT: case FIX:
2556 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2565 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2566 if (new != XEXP (x, 0))
2567 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2571 /* Similar to above processing, but preserve SUBREG_BYTE.
2572 Convert (subreg (mem)) to (mem) if not paradoxical.
2573 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2574 pseudo didn't get a hard reg, we must replace this with the
2575 eliminated version of the memory location because push_reload
2576 may do the replacement in certain circumstances. */
2577 if (REG_P (SUBREG_REG (x))
2578 && (GET_MODE_SIZE (GET_MODE (x))
2579 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2580 && reg_equiv_memory_loc != 0
2581 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2583 new = SUBREG_REG (x);
2586 new = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2588 if (new != SUBREG_REG (x))
2590 int x_size = GET_MODE_SIZE (GET_MODE (x));
2591 int new_size = GET_MODE_SIZE (GET_MODE (new));
2594 && ((x_size < new_size
2595 #ifdef WORD_REGISTER_OPERATIONS
2596 /* On these machines, combine can create rtl of the form
2597 (set (subreg:m1 (reg:m2 R) 0) ...)
2598 where m1 < m2, and expects something interesting to
2599 happen to the entire word. Moreover, it will use the
2600 (reg:m2 R) later, expecting all bits to be preserved.
2601 So if the number of words is the same, preserve the
2602 subreg so that push_reload can see it. */
2603 && ! ((x_size - 1) / UNITS_PER_WORD
2604 == (new_size -1 ) / UNITS_PER_WORD)
2607 || x_size == new_size)
2609 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2611 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2617 /* Our only special processing is to pass the mode of the MEM to our
2618 recursive call and copy the flags. While we are here, handle this
2619 case more efficiently. */
2621 replace_equiv_address_nv (x,
2622 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2626 /* Handle insn_list USE that a call to a pure function may generate. */
2627 new = eliminate_regs_1 (XEXP (x, 0), 0, insn, false);
2628 if (new != XEXP (x, 0))
2629 return gen_rtx_USE (GET_MODE (x), new);
2641 /* Process each of our operands recursively. If any have changed, make a
2643 fmt = GET_RTX_FORMAT (code);
2644 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2648 new = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2649 if (new != XEXP (x, i) && ! copied)
2651 x = shallow_copy_rtx (x);
2656 else if (*fmt == 'E')
2659 for (j = 0; j < XVECLEN (x, i); j++)
2661 new = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2662 if (new != XVECEXP (x, i, j) && ! copied_vec)
2664 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2668 x = shallow_copy_rtx (x);
2671 XVEC (x, i) = new_v;
2674 XVECEXP (x, i, j) = new;
2683 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2685 return eliminate_regs_1 (x, mem_mode, insn, false);
2688 /* Scan rtx X for modifications of elimination target registers. Update
2689 the table of eliminables to reflect the changed state. MEM_MODE is
2690 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2693 elimination_effects (rtx x, enum machine_mode mem_mode)
2695 enum rtx_code code = GET_CODE (x);
2696 struct elim_table *ep;
2720 /* First handle the case where we encounter a bare register that
2721 is eliminable. Replace it with a PLUS. */
2722 if (regno < FIRST_PSEUDO_REGISTER)
2724 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2726 if (ep->from_rtx == x && ep->can_eliminate)
2729 ep->ref_outside_mem = 1;
2734 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2735 && reg_equiv_constant[regno]
2736 && ! function_invariant_p (reg_equiv_constant[regno]))
2737 elimination_effects (reg_equiv_constant[regno], mem_mode);
2746 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2747 if (ep->to_rtx == XEXP (x, 0))
2749 int size = GET_MODE_SIZE (mem_mode);
2751 /* If more bytes than MEM_MODE are pushed, account for them. */
2752 #ifdef PUSH_ROUNDING
2753 if (ep->to_rtx == stack_pointer_rtx)
2754 size = PUSH_ROUNDING (size);
2756 if (code == PRE_DEC || code == POST_DEC)
2758 else if (code == PRE_INC || code == POST_INC)
2760 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2761 && GET_CODE (XEXP (x, 1)) == PLUS
2762 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2763 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2764 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2767 /* These two aren't unary operators. */
2768 if (code == POST_MODIFY || code == PRE_MODIFY)
2771 /* Fall through to generic unary operation case. */
2772 case STRICT_LOW_PART:
2774 case SIGN_EXTEND: case ZERO_EXTEND:
2775 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2776 case FLOAT: case FIX:
2777 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2786 elimination_effects (XEXP (x, 0), mem_mode);
2790 if (REG_P (SUBREG_REG (x))
2791 && (GET_MODE_SIZE (GET_MODE (x))
2792 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2793 && reg_equiv_memory_loc != 0
2794 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2797 elimination_effects (SUBREG_REG (x), mem_mode);
2801 /* If using a register that is the source of an eliminate we still
2802 think can be performed, note it cannot be performed since we don't
2803 know how this register is used. */
2804 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2805 if (ep->from_rtx == XEXP (x, 0))
2806 ep->can_eliminate = 0;
2808 elimination_effects (XEXP (x, 0), mem_mode);
2812 /* If clobbering a register that is the replacement register for an
2813 elimination we still think can be performed, note that it cannot
2814 be performed. Otherwise, we need not be concerned about it. */
2815 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2816 if (ep->to_rtx == XEXP (x, 0))
2817 ep->can_eliminate = 0;
2819 elimination_effects (XEXP (x, 0), mem_mode);
2823 /* Check for setting a register that we know about. */
2824 if (REG_P (SET_DEST (x)))
2826 /* See if this is setting the replacement register for an
2829 If DEST is the hard frame pointer, we do nothing because we
2830 assume that all assignments to the frame pointer are for
2831 non-local gotos and are being done at a time when they are valid
2832 and do not disturb anything else. Some machines want to
2833 eliminate a fake argument pointer (or even a fake frame pointer)
2834 with either the real frame or the stack pointer. Assignments to
2835 the hard frame pointer must not prevent this elimination. */
2837 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2839 if (ep->to_rtx == SET_DEST (x)
2840 && SET_DEST (x) != hard_frame_pointer_rtx)
2842 /* If it is being incremented, adjust the offset. Otherwise,
2843 this elimination can't be done. */
2844 rtx src = SET_SRC (x);
2846 if (GET_CODE (src) == PLUS
2847 && XEXP (src, 0) == SET_DEST (x)
2848 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2849 ep->offset -= INTVAL (XEXP (src, 1));
2851 ep->can_eliminate = 0;
2855 elimination_effects (SET_DEST (x), 0);
2856 elimination_effects (SET_SRC (x), 0);
2860 /* Our only special processing is to pass the mode of the MEM to our
2862 elimination_effects (XEXP (x, 0), GET_MODE (x));
2869 fmt = GET_RTX_FORMAT (code);
2870 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2873 elimination_effects (XEXP (x, i), mem_mode);
2874 else if (*fmt == 'E')
2875 for (j = 0; j < XVECLEN (x, i); j++)
2876 elimination_effects (XVECEXP (x, i, j), mem_mode);
2880 /* Descend through rtx X and verify that no references to eliminable registers
2881 remain. If any do remain, mark the involved register as not
2885 check_eliminable_occurrences (rtx x)
2894 code = GET_CODE (x);
2896 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2898 struct elim_table *ep;
2900 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2901 if (ep->from_rtx == x)
2902 ep->can_eliminate = 0;
2906 fmt = GET_RTX_FORMAT (code);
2907 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2910 check_eliminable_occurrences (XEXP (x, i));
2911 else if (*fmt == 'E')
2914 for (j = 0; j < XVECLEN (x, i); j++)
2915 check_eliminable_occurrences (XVECEXP (x, i, j));
2920 /* Scan INSN and eliminate all eliminable registers in it.
2922 If REPLACE is nonzero, do the replacement destructively. Also
2923 delete the insn as dead it if it is setting an eliminable register.
2925 If REPLACE is zero, do all our allocations in reload_obstack.
2927 If no eliminations were done and this insn doesn't require any elimination
2928 processing (these are not identical conditions: it might be updating sp,
2929 but not referencing fp; this needs to be seen during reload_as_needed so
2930 that the offset between fp and sp can be taken into consideration), zero
2931 is returned. Otherwise, 1 is returned. */
2934 eliminate_regs_in_insn (rtx insn, int replace)
2936 int icode = recog_memoized (insn);
2937 rtx old_body = PATTERN (insn);
2938 int insn_is_asm = asm_noperands (old_body) >= 0;
2939 rtx old_set = single_set (insn);
2943 rtx substed_operand[MAX_RECOG_OPERANDS];
2944 rtx orig_operand[MAX_RECOG_OPERANDS];
2945 struct elim_table *ep;
2946 rtx plus_src, plus_cst_src;
2948 if (! insn_is_asm && icode < 0)
2950 gcc_assert (GET_CODE (PATTERN (insn)) == USE
2951 || GET_CODE (PATTERN (insn)) == CLOBBER
2952 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2953 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2954 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
2958 if (old_set != 0 && REG_P (SET_DEST (old_set))
2959 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2961 /* Check for setting an eliminable register. */
2962 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2963 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2965 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2966 /* If this is setting the frame pointer register to the
2967 hardware frame pointer register and this is an elimination
2968 that will be done (tested above), this insn is really
2969 adjusting the frame pointer downward to compensate for
2970 the adjustment done before a nonlocal goto. */
2971 if (ep->from == FRAME_POINTER_REGNUM
2972 && ep->to == HARD_FRAME_POINTER_REGNUM)
2974 rtx base = SET_SRC (old_set);
2975 rtx base_insn = insn;
2976 HOST_WIDE_INT offset = 0;
2978 while (base != ep->to_rtx)
2980 rtx prev_insn, prev_set;
2982 if (GET_CODE (base) == PLUS
2983 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2985 offset += INTVAL (XEXP (base, 1));
2986 base = XEXP (base, 0);
2988 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2989 && (prev_set = single_set (prev_insn)) != 0
2990 && rtx_equal_p (SET_DEST (prev_set), base))
2992 base = SET_SRC (prev_set);
2993 base_insn = prev_insn;
2999 if (base == ep->to_rtx)
3002 = plus_constant (ep->to_rtx, offset - ep->offset);
3004 new_body = old_body;
3007 new_body = copy_insn (old_body);
3008 if (REG_NOTES (insn))
3009 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3011 PATTERN (insn) = new_body;
3012 old_set = single_set (insn);
3014 /* First see if this insn remains valid when we
3015 make the change. If not, keep the INSN_CODE
3016 the same and let reload fit it up. */
3017 validate_change (insn, &SET_SRC (old_set), src, 1);
3018 validate_change (insn, &SET_DEST (old_set),
3020 if (! apply_change_group ())
3022 SET_SRC (old_set) = src;
3023 SET_DEST (old_set) = ep->to_rtx;
3032 /* In this case this insn isn't serving a useful purpose. We
3033 will delete it in reload_as_needed once we know that this
3034 elimination is, in fact, being done.
3036 If REPLACE isn't set, we can't delete this insn, but needn't
3037 process it since it won't be used unless something changes. */
3040 delete_dead_insn (insn);
3048 /* We allow one special case which happens to work on all machines we
3049 currently support: a single set with the source or a REG_EQUAL
3050 note being a PLUS of an eliminable register and a constant. */
3051 plus_src = plus_cst_src = 0;
3052 if (old_set && REG_P (SET_DEST (old_set)))
3054 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3055 plus_src = SET_SRC (old_set);
3056 /* First see if the source is of the form (plus (...) CST). */
3058 && GET_CODE (XEXP (plus_src, 1)) == CONST_INT)
3059 plus_cst_src = plus_src;
3060 else if (REG_P (SET_SRC (old_set))
3063 /* Otherwise, see if we have a REG_EQUAL note of the form
3064 (plus (...) CST). */
3066 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3068 if (REG_NOTE_KIND (links) == REG_EQUAL
3069 && GET_CODE (XEXP (links, 0)) == PLUS
3070 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT)
3072 plus_cst_src = XEXP (links, 0);
3078 /* Check that the first operand of the PLUS is a hard reg or
3079 the lowpart subreg of one. */
3082 rtx reg = XEXP (plus_cst_src, 0);
3083 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3084 reg = SUBREG_REG (reg);
3086 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3092 rtx reg = XEXP (plus_cst_src, 0);
3093 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3095 if (GET_CODE (reg) == SUBREG)
3096 reg = SUBREG_REG (reg);
3098 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3099 if (ep->from_rtx == reg && ep->can_eliminate)
3101 rtx to_rtx = ep->to_rtx;
3102 offset += ep->offset;
3104 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3105 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3110 /* We assume here that if we need a PARALLEL with
3111 CLOBBERs for this assignment, we can do with the
3112 MATCH_SCRATCHes that add_clobbers allocates.
3113 There's not much we can do if that doesn't work. */
3114 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3118 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3121 rtvec vec = rtvec_alloc (num_clobbers + 1);
3123 vec->elem[0] = PATTERN (insn);
3124 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3125 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3127 gcc_assert (INSN_CODE (insn) >= 0);
3129 /* If we have a nonzero offset, and the source is already
3130 a simple REG, the following transformation would
3131 increase the cost of the insn by replacing a simple REG
3132 with (plus (reg sp) CST). So try only when we already
3133 had a PLUS before. */
3136 new_body = old_body;
3139 new_body = copy_insn (old_body);
3140 if (REG_NOTES (insn))
3141 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3143 PATTERN (insn) = new_body;
3144 old_set = single_set (insn);
3146 XEXP (SET_SRC (old_set), 0) = to_rtx;
3147 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3153 /* This can't have an effect on elimination offsets, so skip right
3159 /* Determine the effects of this insn on elimination offsets. */
3160 elimination_effects (old_body, 0);
3162 /* Eliminate all eliminable registers occurring in operands that
3163 can be handled by reload. */
3164 extract_insn (insn);
3165 for (i = 0; i < recog_data.n_operands; i++)
3167 orig_operand[i] = recog_data.operand[i];
3168 substed_operand[i] = recog_data.operand[i];
3170 /* For an asm statement, every operand is eliminable. */
3171 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3173 bool is_set_src, in_plus;
3175 /* Check for setting a register that we know about. */
3176 if (recog_data.operand_type[i] != OP_IN
3177 && REG_P (orig_operand[i]))
3179 /* If we are assigning to a register that can be eliminated, it
3180 must be as part of a PARALLEL, since the code above handles
3181 single SETs. We must indicate that we can no longer
3182 eliminate this reg. */
3183 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3185 if (ep->from_rtx == orig_operand[i])
3186 ep->can_eliminate = 0;
3189 /* Companion to the above plus substitution, we can allow
3190 invariants as the source of a plain move. */
3192 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3196 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3197 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3201 = eliminate_regs_1 (recog_data.operand[i], 0,
3202 replace ? insn : NULL_RTX,
3203 is_set_src || in_plus);
3204 if (substed_operand[i] != orig_operand[i])
3206 /* Terminate the search in check_eliminable_occurrences at
3208 *recog_data.operand_loc[i] = 0;
3210 /* If an output operand changed from a REG to a MEM and INSN is an
3211 insn, write a CLOBBER insn. */
3212 if (recog_data.operand_type[i] != OP_IN
3213 && REG_P (orig_operand[i])
3214 && MEM_P (substed_operand[i])
3216 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3221 for (i = 0; i < recog_data.n_dups; i++)
3222 *recog_data.dup_loc[i]
3223 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3225 /* If any eliminable remain, they aren't eliminable anymore. */
3226 check_eliminable_occurrences (old_body);
3228 /* Substitute the operands; the new values are in the substed_operand
3230 for (i = 0; i < recog_data.n_operands; i++)
3231 *recog_data.operand_loc[i] = substed_operand[i];
3232 for (i = 0; i < recog_data.n_dups; i++)
3233 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3235 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3236 re-recognize the insn. We do this in case we had a simple addition
3237 but now can do this as a load-address. This saves an insn in this
3239 If re-recognition fails, the old insn code number will still be used,
3240 and some register operands may have changed into PLUS expressions.
3241 These will be handled by find_reloads by loading them into a register
3246 /* If we aren't replacing things permanently and we changed something,
3247 make another copy to ensure that all the RTL is new. Otherwise
3248 things can go wrong if find_reload swaps commutative operands
3249 and one is inside RTL that has been copied while the other is not. */
3250 new_body = old_body;
3253 new_body = copy_insn (old_body);
3254 if (REG_NOTES (insn))
3255 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3257 PATTERN (insn) = new_body;
3259 /* If we had a move insn but now we don't, rerecognize it. This will
3260 cause spurious re-recognition if the old move had a PARALLEL since
3261 the new one still will, but we can't call single_set without
3262 having put NEW_BODY into the insn and the re-recognition won't
3263 hurt in this rare case. */
3264 /* ??? Why this huge if statement - why don't we just rerecognize the
3268 && ((REG_P (SET_SRC (old_set))
3269 && (GET_CODE (new_body) != SET
3270 || !REG_P (SET_SRC (new_body))))
3271 /* If this was a load from or store to memory, compare
3272 the MEM in recog_data.operand to the one in the insn.
3273 If they are not equal, then rerecognize the insn. */
3275 && ((MEM_P (SET_SRC (old_set))
3276 && SET_SRC (old_set) != recog_data.operand[1])
3277 || (MEM_P (SET_DEST (old_set))
3278 && SET_DEST (old_set) != recog_data.operand[0])))
3279 /* If this was an add insn before, rerecognize. */
3280 || GET_CODE (SET_SRC (old_set)) == PLUS))
3282 int new_icode = recog (PATTERN (insn), insn, 0);
3284 INSN_CODE (insn) = new_icode;
3288 /* Restore the old body. If there were any changes to it, we made a copy
3289 of it while the changes were still in place, so we'll correctly return
3290 a modified insn below. */
3293 /* Restore the old body. */
3294 for (i = 0; i < recog_data.n_operands; i++)
3295 *recog_data.operand_loc[i] = orig_operand[i];
3296 for (i = 0; i < recog_data.n_dups; i++)
3297 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3300 /* Update all elimination pairs to reflect the status after the current
3301 insn. The changes we make were determined by the earlier call to
3302 elimination_effects.
3304 We also detect cases where register elimination cannot be done,
3305 namely, if a register would be both changed and referenced outside a MEM
3306 in the resulting insn since such an insn is often undefined and, even if
3307 not, we cannot know what meaning will be given to it. Note that it is
3308 valid to have a register used in an address in an insn that changes it
3309 (presumably with a pre- or post-increment or decrement).
3311 If anything changes, return nonzero. */
3313 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3315 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3316 ep->can_eliminate = 0;
3318 ep->ref_outside_mem = 0;
3320 if (ep->previous_offset != ep->offset)
3325 /* If we changed something, perform elimination in REG_NOTES. This is
3326 needed even when REPLACE is zero because a REG_DEAD note might refer
3327 to a register that we eliminate and could cause a different number
3328 of spill registers to be needed in the final reload pass than in
3330 if (val && REG_NOTES (insn) != 0)
3332 = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true);
3337 /* Loop through all elimination pairs.
3338 Recalculate the number not at initial offset.
3340 Compute the maximum offset (minimum offset if the stack does not
3341 grow downward) for each elimination pair. */
3344 update_eliminable_offsets (void)
3346 struct elim_table *ep;
3348 num_not_at_initial_offset = 0;
3349 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3351 ep->previous_offset = ep->offset;
3352 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3353 num_not_at_initial_offset++;
3357 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3358 replacement we currently believe is valid, mark it as not eliminable if X
3359 modifies DEST in any way other than by adding a constant integer to it.
3361 If DEST is the frame pointer, we do nothing because we assume that
3362 all assignments to the hard frame pointer are nonlocal gotos and are being
3363 done at a time when they are valid and do not disturb anything else.
3364 Some machines want to eliminate a fake argument pointer with either the
3365 frame or stack pointer. Assignments to the hard frame pointer must not
3366 prevent this elimination.
3368 Called via note_stores from reload before starting its passes to scan
3369 the insns of the function. */
3372 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3376 /* A SUBREG of a hard register here is just changing its mode. We should
3377 not see a SUBREG of an eliminable hard register, but check just in
3379 if (GET_CODE (dest) == SUBREG)
3380 dest = SUBREG_REG (dest);
3382 if (dest == hard_frame_pointer_rtx)
3385 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3386 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3387 && (GET_CODE (x) != SET
3388 || GET_CODE (SET_SRC (x)) != PLUS
3389 || XEXP (SET_SRC (x), 0) != dest
3390 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3392 reg_eliminate[i].can_eliminate_previous
3393 = reg_eliminate[i].can_eliminate = 0;
3398 /* Verify that the initial elimination offsets did not change since the
3399 last call to set_initial_elim_offsets. This is used to catch cases
3400 where something illegal happened during reload_as_needed that could
3401 cause incorrect code to be generated if we did not check for it. */
3404 verify_initial_elim_offsets (void)
3408 if (!num_eliminable)
3411 #ifdef ELIMINABLE_REGS
3413 struct elim_table *ep;
3415 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3417 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3418 if (t != ep->initial_offset)
3423 INITIAL_FRAME_POINTER_OFFSET (t);
3424 if (t != reg_eliminate[0].initial_offset)
3431 /* Reset all offsets on eliminable registers to their initial values. */
3434 set_initial_elim_offsets (void)
3436 struct elim_table *ep = reg_eliminate;
3438 #ifdef ELIMINABLE_REGS
3439 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3441 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3442 ep->previous_offset = ep->offset = ep->initial_offset;
3445 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3446 ep->previous_offset = ep->offset = ep->initial_offset;
3449 num_not_at_initial_offset = 0;
3452 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3455 set_initial_eh_label_offset (rtx label)
3457 set_label_offsets (label, NULL_RTX, 1);
3460 /* Initialize the known label offsets.
3461 Set a known offset for each forced label to be at the initial offset
3462 of each elimination. We do this because we assume that all
3463 computed jumps occur from a location where each elimination is
3464 at its initial offset.
3465 For all other labels, show that we don't know the offsets. */
3468 set_initial_label_offsets (void)
3471 memset (offsets_known_at, 0, num_labels);
3473 for (x = forced_labels; x; x = XEXP (x, 1))
3475 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3477 for_each_eh_label (set_initial_eh_label_offset);
3480 /* Set all elimination offsets to the known values for the code label given
3484 set_offsets_for_label (rtx insn)
3487 int label_nr = CODE_LABEL_NUMBER (insn);
3488 struct elim_table *ep;
3490 num_not_at_initial_offset = 0;
3491 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3493 ep->offset = ep->previous_offset
3494 = offsets_at[label_nr - first_label_num][i];
3495 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3496 num_not_at_initial_offset++;
3500 /* See if anything that happened changes which eliminations are valid.
3501 For example, on the SPARC, whether or not the frame pointer can
3502 be eliminated can depend on what registers have been used. We need
3503 not check some conditions again (such as flag_omit_frame_pointer)
3504 since they can't have changed. */
3507 update_eliminables (HARD_REG_SET *pset)
3509 int previous_frame_pointer_needed = frame_pointer_needed;
3510 struct elim_table *ep;
3512 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3513 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3514 #ifdef ELIMINABLE_REGS
3515 || ! CAN_ELIMINATE (ep->from, ep->to)
3518 ep->can_eliminate = 0;
3520 /* Look for the case where we have discovered that we can't replace
3521 register A with register B and that means that we will now be
3522 trying to replace register A with register C. This means we can
3523 no longer replace register C with register B and we need to disable
3524 such an elimination, if it exists. This occurs often with A == ap,
3525 B == sp, and C == fp. */
3527 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3529 struct elim_table *op;
3532 if (! ep->can_eliminate && ep->can_eliminate_previous)
3534 /* Find the current elimination for ep->from, if there is a
3536 for (op = reg_eliminate;
3537 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3538 if (op->from == ep->from && op->can_eliminate)
3544 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3546 for (op = reg_eliminate;
3547 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3548 if (op->from == new_to && op->to == ep->to)
3549 op->can_eliminate = 0;
3553 /* See if any registers that we thought we could eliminate the previous
3554 time are no longer eliminable. If so, something has changed and we
3555 must spill the register. Also, recompute the number of eliminable
3556 registers and see if the frame pointer is needed; it is if there is
3557 no elimination of the frame pointer that we can perform. */
3559 frame_pointer_needed = 1;
3560 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3562 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3563 && ep->to != HARD_FRAME_POINTER_REGNUM)
3564 frame_pointer_needed = 0;
3566 if (! ep->can_eliminate && ep->can_eliminate_previous)
3568 ep->can_eliminate_previous = 0;
3569 SET_HARD_REG_BIT (*pset, ep->from);
3574 /* If we didn't need a frame pointer last time, but we do now, spill
3575 the hard frame pointer. */
3576 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3577 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3580 /* Initialize the table of registers to eliminate. */
3583 init_elim_table (void)
3585 struct elim_table *ep;
3586 #ifdef ELIMINABLE_REGS
3587 const struct elim_table_1 *ep1;
3591 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3593 /* Does this function require a frame pointer? */
3595 frame_pointer_needed = (! flag_omit_frame_pointer
3596 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3597 and restore sp for alloca. So we can't eliminate
3598 the frame pointer in that case. At some point,
3599 we should improve this by emitting the
3600 sp-adjusting insns for this case. */
3601 || (current_function_calls_alloca
3602 && EXIT_IGNORE_STACK)
3603 || current_function_accesses_prior_frames
3604 || FRAME_POINTER_REQUIRED);
3608 #ifdef ELIMINABLE_REGS
3609 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3610 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3612 ep->from = ep1->from;
3614 ep->can_eliminate = ep->can_eliminate_previous
3615 = (CAN_ELIMINATE (ep->from, ep->to)
3616 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3619 reg_eliminate[0].from = reg_eliminate_1[0].from;
3620 reg_eliminate[0].to = reg_eliminate_1[0].to;
3621 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3622 = ! frame_pointer_needed;
3625 /* Count the number of eliminable registers and build the FROM and TO
3626 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3627 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3628 We depend on this. */
3629 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3631 num_eliminable += ep->can_eliminate;
3632 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3633 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3637 /* Kick all pseudos out of hard register REGNO.
3639 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3640 because we found we can't eliminate some register. In the case, no pseudos
3641 are allowed to be in the register, even if they are only in a block that
3642 doesn't require spill registers, unlike the case when we are spilling this
3643 hard reg to produce another spill register.
3645 Return nonzero if any pseudos needed to be kicked out. */
3648 spill_hard_reg (unsigned int regno, int cant_eliminate)
3654 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3655 regs_ever_live[regno] = 1;
3658 /* Spill every pseudo reg that was allocated to this reg
3659 or to something that overlaps this reg. */
3661 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3662 if (reg_renumber[i] >= 0
3663 && (unsigned int) reg_renumber[i] <= regno
3664 && ((unsigned int) reg_renumber[i]
3665 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3666 [PSEUDO_REGNO_MODE (i)]
3668 SET_REGNO_REG_SET (&spilled_pseudos, i);
3671 /* After find_reload_regs has been run for all insn that need reloads,
3672 and/or spill_hard_regs was called, this function is used to actually
3673 spill pseudo registers and try to reallocate them. It also sets up the
3674 spill_regs array for use by choose_reload_regs. */
3677 finish_spills (int global)
3679 struct insn_chain *chain;
3680 int something_changed = 0;
3682 reg_set_iterator rsi;
3684 /* Build the spill_regs array for the function. */
3685 /* If there are some registers still to eliminate and one of the spill regs
3686 wasn't ever used before, additional stack space may have to be
3687 allocated to store this register. Thus, we may have changed the offset
3688 between the stack and frame pointers, so mark that something has changed.
3690 One might think that we need only set VAL to 1 if this is a call-used
3691 register. However, the set of registers that must be saved by the
3692 prologue is not identical to the call-used set. For example, the
3693 register used by the call insn for the return PC is a call-used register,
3694 but must be saved by the prologue. */
3697 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3698 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3700 spill_reg_order[i] = n_spills;
3701 spill_regs[n_spills++] = i;
3702 if (num_eliminable && ! regs_ever_live[i])
3703 something_changed = 1;
3704 regs_ever_live[i] = 1;
3707 spill_reg_order[i] = -1;
3709 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3711 /* Record the current hard register the pseudo is allocated to in
3712 pseudo_previous_regs so we avoid reallocating it to the same
3713 hard reg in a later pass. */
3714 gcc_assert (reg_renumber[i] >= 0);
3716 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3717 /* Mark it as no longer having a hard register home. */
3718 reg_renumber[i] = -1;
3719 /* We will need to scan everything again. */
3720 something_changed = 1;
3723 /* Retry global register allocation if possible. */
3726 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3727 /* For every insn that needs reloads, set the registers used as spill
3728 regs in pseudo_forbidden_regs for every pseudo live across the
3730 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3732 EXECUTE_IF_SET_IN_REG_SET
3733 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3735 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3736 chain->used_spill_regs);
3738 EXECUTE_IF_SET_IN_REG_SET
3739 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3741 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3742 chain->used_spill_regs);
3746 /* Retry allocating the spilled pseudos. For each reg, merge the
3747 various reg sets that indicate which hard regs can't be used,
3748 and call retry_global_alloc.
3749 We change spill_pseudos here to only contain pseudos that did not
3750 get a new hard register. */
3751 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3752 if (reg_old_renumber[i] != reg_renumber[i])
3754 HARD_REG_SET forbidden;
3755 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3756 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3757 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3758 retry_global_alloc (i, forbidden);
3759 if (reg_renumber[i] >= 0)
3760 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3764 /* Fix up the register information in the insn chain.
3765 This involves deleting those of the spilled pseudos which did not get
3766 a new hard register home from the live_{before,after} sets. */
3767 for (chain = reload_insn_chain; chain; chain = chain->next)
3769 HARD_REG_SET used_by_pseudos;
3770 HARD_REG_SET used_by_pseudos2;
3772 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3773 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3775 /* Mark any unallocated hard regs as available for spills. That
3776 makes inheritance work somewhat better. */
3777 if (chain->need_reload)
3779 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3780 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3781 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3783 /* Save the old value for the sanity test below. */
3784 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3786 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3787 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3788 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3789 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3791 /* Make sure we only enlarge the set. */
3792 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3798 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3799 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3801 int regno = reg_renumber[i];
3802 if (reg_old_renumber[i] == regno)
3805 alter_reg (i, reg_old_renumber[i]);
3806 reg_old_renumber[i] = regno;
3810 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3812 fprintf (dump_file, " Register %d now in %d.\n\n",
3813 i, reg_renumber[i]);
3817 return something_changed;
3820 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3823 scan_paradoxical_subregs (rtx x)
3827 enum rtx_code code = GET_CODE (x);
3837 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3845 if (REG_P (SUBREG_REG (x))
3846 && (GET_MODE_SIZE (GET_MODE (x))
3847 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
3848 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3849 = GET_MODE_SIZE (GET_MODE (x));
3856 fmt = GET_RTX_FORMAT (code);
3857 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3860 scan_paradoxical_subregs (XEXP (x, i));
3861 else if (fmt[i] == 'E')
3864 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3865 scan_paradoxical_subregs (XVECEXP (x, i, j));
3870 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
3871 examine all of the reload insns between PREV and NEXT exclusive, and
3872 annotate all that may trap. */
3875 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
3877 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
3878 unsigned int trap_count;
3884 if (may_trap_p (PATTERN (insn)))
3888 remove_note (insn, note);
3892 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
3893 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
3897 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0), REG_NOTES (i));
3901 /* Reload pseudo-registers into hard regs around each insn as needed.
3902 Additional register load insns are output before the insn that needs it
3903 and perhaps store insns after insns that modify the reloaded pseudo reg.
3905 reg_last_reload_reg and reg_reloaded_contents keep track of
3906 which registers are already available in reload registers.
3907 We update these for the reloads that we perform,
3908 as the insns are scanned. */
3911 reload_as_needed (int live_known)
3913 struct insn_chain *chain;
3914 #if defined (AUTO_INC_DEC)
3919 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3920 memset (spill_reg_store, 0, sizeof spill_reg_store);
3921 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
3922 INIT_REG_SET (®_has_output_reload);
3923 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3924 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3926 set_initial_elim_offsets ();
3928 for (chain = reload_insn_chain; chain; chain = chain->next)
3931 rtx insn = chain->insn;
3932 rtx old_next = NEXT_INSN (insn);
3934 /* If we pass a label, copy the offsets from the label information
3935 into the current offsets of each elimination. */
3937 set_offsets_for_label (insn);
3939 else if (INSN_P (insn))
3941 regset_head regs_to_forget;
3942 INIT_REG_SET (®s_to_forget);
3943 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
3945 /* If this is a USE and CLOBBER of a MEM, ensure that any
3946 references to eliminable registers have been removed. */
3948 if ((GET_CODE (PATTERN (insn)) == USE
3949 || GET_CODE (PATTERN (insn)) == CLOBBER)
3950 && MEM_P (XEXP (PATTERN (insn), 0)))
3951 XEXP (XEXP (PATTERN (insn), 0), 0)
3952 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3953 GET_MODE (XEXP (PATTERN (insn), 0)),
3956 /* If we need to do register elimination processing, do so.
3957 This might delete the insn, in which case we are done. */
3958 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3960 eliminate_regs_in_insn (insn, 1);
3963 update_eliminable_offsets ();
3964 CLEAR_REG_SET (®s_to_forget);
3969 /* If need_elim is nonzero but need_reload is zero, one might think
3970 that we could simply set n_reloads to 0. However, find_reloads
3971 could have done some manipulation of the insn (such as swapping
3972 commutative operands), and these manipulations are lost during
3973 the first pass for every insn that needs register elimination.
3974 So the actions of find_reloads must be redone here. */
3976 if (! chain->need_elim && ! chain->need_reload
3977 && ! chain->need_operand_change)
3979 /* First find the pseudo regs that must be reloaded for this insn.
3980 This info is returned in the tables reload_... (see reload.h).
3981 Also modify the body of INSN by substituting RELOAD
3982 rtx's for those pseudo regs. */
3985 CLEAR_REG_SET (®_has_output_reload);
3986 CLEAR_HARD_REG_SET (reg_is_output_reload);
3988 find_reloads (insn, 1, spill_indirect_levels, live_known,
3994 rtx next = NEXT_INSN (insn);
3997 prev = PREV_INSN (insn);
3999 /* Now compute which reload regs to reload them into. Perhaps
4000 reusing reload regs from previous insns, or else output
4001 load insns to reload them. Maybe output store insns too.
4002 Record the choices of reload reg in reload_reg_rtx. */
4003 choose_reload_regs (chain);
4005 /* Merge any reloads that we didn't combine for fear of
4006 increasing the number of spill registers needed but now
4007 discover can be safely merged. */
4008 if (SMALL_REGISTER_CLASSES)
4009 merge_assigned_reloads (insn);
4011 /* Generate the insns to reload operands into or out of
4012 their reload regs. */
4013 emit_reload_insns (chain);
4015 /* Substitute the chosen reload regs from reload_reg_rtx
4016 into the insn's body (or perhaps into the bodies of other
4017 load and store insn that we just made for reloading
4018 and that we moved the structure into). */
4019 subst_reloads (insn);
4021 /* Adjust the exception region notes for loads and stores. */
4022 if (flag_non_call_exceptions && !CALL_P (insn))
4023 fixup_eh_region_note (insn, prev, next);
4025 /* If this was an ASM, make sure that all the reload insns
4026 we have generated are valid. If not, give an error
4028 if (asm_noperands (PATTERN (insn)) >= 0)
4029 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4030 if (p != insn && INSN_P (p)
4031 && GET_CODE (PATTERN (p)) != USE
4032 && (recog_memoized (p) < 0
4033 || (extract_insn (p), ! constrain_operands (1))))
4035 error_for_asm (insn,
4036 "%<asm%> operand requires "
4037 "impossible reload");
4042 if (num_eliminable && chain->need_elim)
4043 update_eliminable_offsets ();
4045 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4046 is no longer validly lying around to save a future reload.
4047 Note that this does not detect pseudos that were reloaded
4048 for this insn in order to be stored in
4049 (obeying register constraints). That is correct; such reload
4050 registers ARE still valid. */
4051 forget_marked_reloads (®s_to_forget);
4052 CLEAR_REG_SET (®s_to_forget);
4054 /* There may have been CLOBBER insns placed after INSN. So scan
4055 between INSN and NEXT and use them to forget old reloads. */
4056 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4057 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4058 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4061 /* Likewise for regs altered by auto-increment in this insn.
4062 REG_INC notes have been changed by reloading:
4063 find_reloads_address_1 records substitutions for them,
4064 which have been performed by subst_reloads above. */
4065 for (i = n_reloads - 1; i >= 0; i--)
4067 rtx in_reg = rld[i].in_reg;
4070 enum rtx_code code = GET_CODE (in_reg);
4071 /* PRE_INC / PRE_DEC will have the reload register ending up
4072 with the same value as the stack slot, but that doesn't
4073 hold true for POST_INC / POST_DEC. Either we have to
4074 convert the memory access to a true POST_INC / POST_DEC,
4075 or we can't use the reload register for inheritance. */
4076 if ((code == POST_INC || code == POST_DEC)
4077 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4078 REGNO (rld[i].reg_rtx))
4079 /* Make sure it is the inc/dec pseudo, and not
4080 some other (e.g. output operand) pseudo. */
4081 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4082 == REGNO (XEXP (in_reg, 0))))
4085 rtx reload_reg = rld[i].reg_rtx;
4086 enum machine_mode mode = GET_MODE (reload_reg);
4090 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4092 /* We really want to ignore REG_INC notes here, so
4093 use PATTERN (p) as argument to reg_set_p . */
4094 if (reg_set_p (reload_reg, PATTERN (p)))
4096 n = count_occurrences (PATTERN (p), reload_reg, 0);
4101 n = validate_replace_rtx (reload_reg,
4102 gen_rtx_fmt_e (code,
4107 /* We must also verify that the constraints
4108 are met after the replacement. */
4111 n = constrain_operands (1);
4115 /* If the constraints were not met, then
4116 undo the replacement. */
4119 validate_replace_rtx (gen_rtx_fmt_e (code,
4132 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4134 /* Mark this as having an output reload so that the
4135 REG_INC processing code below won't invalidate
4136 the reload for inheritance. */
4137 SET_HARD_REG_BIT (reg_is_output_reload,
4138 REGNO (reload_reg));
4139 SET_REGNO_REG_SET (®_has_output_reload,
4140 REGNO (XEXP (in_reg, 0)));
4143 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4146 else if ((code == PRE_INC || code == PRE_DEC)
4147 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4148 REGNO (rld[i].reg_rtx))
4149 /* Make sure it is the inc/dec pseudo, and not
4150 some other (e.g. output operand) pseudo. */
4151 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4152 == REGNO (XEXP (in_reg, 0))))
4154 SET_HARD_REG_BIT (reg_is_output_reload,
4155 REGNO (rld[i].reg_rtx));
4156 SET_REGNO_REG_SET (®_has_output_reload,
4157 REGNO (XEXP (in_reg, 0)));
4161 /* If a pseudo that got a hard register is auto-incremented,
4162 we must purge records of copying it into pseudos without
4164 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4165 if (REG_NOTE_KIND (x) == REG_INC)
4167 /* See if this pseudo reg was reloaded in this insn.
4168 If so, its last-reload info is still valid
4169 because it is based on this insn's reload. */
4170 for (i = 0; i < n_reloads; i++)
4171 if (rld[i].out == XEXP (x, 0))
4175 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4179 /* A reload reg's contents are unknown after a label. */
4181 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4183 /* Don't assume a reload reg is still good after a call insn
4184 if it is a call-used reg, or if it contains a value that will
4185 be partially clobbered by the call. */
4186 else if (CALL_P (insn))
4188 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4189 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4194 free (reg_last_reload_reg);
4195 CLEAR_REG_SET (®_has_output_reload);
4198 /* Discard all record of any value reloaded from X,
4199 or reloaded in X from someplace else;
4200 unless X is an output reload reg of the current insn.
4202 X may be a hard reg (the reload reg)
4203 or it may be a pseudo reg that was reloaded from.
4205 When DATA is non-NULL just mark the registers in regset
4206 to be forgotten later. */
4209 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4214 regset regs = (regset) data;
4216 /* note_stores does give us subregs of hard regs,
4217 subreg_regno_offset requires a hard reg. */
4218 while (GET_CODE (x) == SUBREG)
4220 /* We ignore the subreg offset when calculating the regno,
4221 because we are using the entire underlying hard register
4231 if (regno >= FIRST_PSEUDO_REGISTER)
4237 nr = hard_regno_nregs[regno][GET_MODE (x)];
4238 /* Storing into a spilled-reg invalidates its contents.
4239 This can happen if a block-local pseudo is allocated to that reg
4240 and it wasn't spilled because this block's total need is 0.
4241 Then some insn might have an optional reload and use this reg. */
4243 for (i = 0; i < nr; i++)
4244 /* But don't do this if the reg actually serves as an output
4245 reload reg in the current instruction. */
4247 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4249 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4250 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4251 spill_reg_store[regno + i] = 0;
4257 SET_REGNO_REG_SET (regs, regno + nr);
4260 /* Since value of X has changed,
4261 forget any value previously copied from it. */
4264 /* But don't forget a copy if this is the output reload
4265 that establishes the copy's validity. */
4267 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4268 reg_last_reload_reg[regno + nr] = 0;
4272 /* Forget the reloads marked in regset by previous function. */
4274 forget_marked_reloads (regset regs)
4277 reg_set_iterator rsi;
4278 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4280 if (reg < FIRST_PSEUDO_REGISTER
4281 /* But don't do this if the reg actually serves as an output
4282 reload reg in the current instruction. */
4284 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4286 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4287 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, reg);
4288 spill_reg_store[reg] = 0;
4291 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4292 reg_last_reload_reg[reg] = 0;
4296 /* The following HARD_REG_SETs indicate when each hard register is
4297 used for a reload of various parts of the current insn. */
4299 /* If reg is unavailable for all reloads. */
4300 static HARD_REG_SET reload_reg_unavailable;
4301 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4302 static HARD_REG_SET reload_reg_used;
4303 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4304 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4305 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4306 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4307 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4308 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4309 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4310 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4311 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4312 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4313 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4314 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4315 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4316 static HARD_REG_SET reload_reg_used_in_op_addr;
4317 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4318 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4319 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4320 static HARD_REG_SET reload_reg_used_in_insn;
4321 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4322 static HARD_REG_SET reload_reg_used_in_other_addr;
4324 /* If reg is in use as a reload reg for any sort of reload. */
4325 static HARD_REG_SET reload_reg_used_at_all;
4327 /* If reg is use as an inherited reload. We just mark the first register
4329 static HARD_REG_SET reload_reg_used_for_inherit;
4331 /* Records which hard regs are used in any way, either as explicit use or
4332 by being allocated to a pseudo during any point of the current insn. */
4333 static HARD_REG_SET reg_used_in_insn;
4335 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4336 TYPE. MODE is used to indicate how many consecutive regs are
4340 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4341 enum machine_mode mode)
4343 unsigned int nregs = hard_regno_nregs[regno][mode];
4346 for (i = regno; i < nregs + regno; i++)
4351 SET_HARD_REG_BIT (reload_reg_used, i);
4354 case RELOAD_FOR_INPUT_ADDRESS:
4355 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4358 case RELOAD_FOR_INPADDR_ADDRESS:
4359 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4362 case RELOAD_FOR_OUTPUT_ADDRESS:
4363 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4366 case RELOAD_FOR_OUTADDR_ADDRESS:
4367 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4370 case RELOAD_FOR_OPERAND_ADDRESS:
4371 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4374 case RELOAD_FOR_OPADDR_ADDR:
4375 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4378 case RELOAD_FOR_OTHER_ADDRESS:
4379 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4382 case RELOAD_FOR_INPUT:
4383 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4386 case RELOAD_FOR_OUTPUT:
4387 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4390 case RELOAD_FOR_INSN:
4391 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4395 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4399 /* Similarly, but show REGNO is no longer in use for a reload. */
4402 clear_reload_reg_in_use (unsigned int regno, int opnum,
4403 enum reload_type type, enum machine_mode mode)
4405 unsigned int nregs = hard_regno_nregs[regno][mode];
4406 unsigned int start_regno, end_regno, r;
4408 /* A complication is that for some reload types, inheritance might
4409 allow multiple reloads of the same types to share a reload register.
4410 We set check_opnum if we have to check only reloads with the same
4411 operand number, and check_any if we have to check all reloads. */
4412 int check_opnum = 0;
4414 HARD_REG_SET *used_in_set;
4419 used_in_set = &reload_reg_used;
4422 case RELOAD_FOR_INPUT_ADDRESS:
4423 used_in_set = &reload_reg_used_in_input_addr[opnum];
4426 case RELOAD_FOR_INPADDR_ADDRESS:
4428 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4431 case RELOAD_FOR_OUTPUT_ADDRESS:
4432 used_in_set = &reload_reg_used_in_output_addr[opnum];
4435 case RELOAD_FOR_OUTADDR_ADDRESS:
4437 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4440 case RELOAD_FOR_OPERAND_ADDRESS:
4441 used_in_set = &reload_reg_used_in_op_addr;
4444 case RELOAD_FOR_OPADDR_ADDR:
4446 used_in_set = &reload_reg_used_in_op_addr_reload;
4449 case RELOAD_FOR_OTHER_ADDRESS:
4450 used_in_set = &reload_reg_used_in_other_addr;
4454 case RELOAD_FOR_INPUT:
4455 used_in_set = &reload_reg_used_in_input[opnum];
4458 case RELOAD_FOR_OUTPUT:
4459 used_in_set = &reload_reg_used_in_output[opnum];
4462 case RELOAD_FOR_INSN:
4463 used_in_set = &reload_reg_used_in_insn;
4468 /* We resolve conflicts with remaining reloads of the same type by
4469 excluding the intervals of reload registers by them from the
4470 interval of freed reload registers. Since we only keep track of
4471 one set of interval bounds, we might have to exclude somewhat
4472 more than what would be necessary if we used a HARD_REG_SET here.
4473 But this should only happen very infrequently, so there should
4474 be no reason to worry about it. */
4476 start_regno = regno;
4477 end_regno = regno + nregs;
4478 if (check_opnum || check_any)
4480 for (i = n_reloads - 1; i >= 0; i--)
4482 if (rld[i].when_needed == type
4483 && (check_any || rld[i].opnum == opnum)
4486 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4487 unsigned int conflict_end
4489 + hard_regno_nregs[conflict_start][rld[i].mode]);
4491 /* If there is an overlap with the first to-be-freed register,
4492 adjust the interval start. */
4493 if (conflict_start <= start_regno && conflict_end > start_regno)
4494 start_regno = conflict_end;
4495 /* Otherwise, if there is a conflict with one of the other
4496 to-be-freed registers, adjust the interval end. */
4497 if (conflict_start > start_regno && conflict_start < end_regno)
4498 end_regno = conflict_start;
4503 for (r = start_regno; r < end_regno; r++)
4504 CLEAR_HARD_REG_BIT (*used_in_set, r);
4507 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4508 specified by OPNUM and TYPE. */
4511 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4515 /* In use for a RELOAD_OTHER means it's not available for anything. */
4516 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4517 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4523 /* In use for anything means we can't use it for RELOAD_OTHER. */
4524 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4525 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4526 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4527 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4530 for (i = 0; i < reload_n_operands; i++)
4531 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4532 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4533 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4534 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4535 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4536 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4541 case RELOAD_FOR_INPUT:
4542 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4543 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4546 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4549 /* If it is used for some other input, can't use it. */
4550 for (i = 0; i < reload_n_operands; i++)
4551 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4554 /* If it is used in a later operand's address, can't use it. */
4555 for (i = opnum + 1; i < reload_n_operands; i++)
4556 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4557 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4562 case RELOAD_FOR_INPUT_ADDRESS:
4563 /* Can't use a register if it is used for an input address for this
4564 operand or used as an input in an earlier one. */
4565 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4566 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4569 for (i = 0; i < opnum; i++)
4570 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4575 case RELOAD_FOR_INPADDR_ADDRESS:
4576 /* Can't use a register if it is used for an input address
4577 for this operand or used as an input in an earlier
4579 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4582 for (i = 0; i < opnum; i++)
4583 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4588 case RELOAD_FOR_OUTPUT_ADDRESS:
4589 /* Can't use a register if it is used for an output address for this
4590 operand or used as an output in this or a later operand. Note
4591 that multiple output operands are emitted in reverse order, so
4592 the conflicting ones are those with lower indices. */
4593 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4596 for (i = 0; i <= opnum; i++)
4597 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4602 case RELOAD_FOR_OUTADDR_ADDRESS:
4603 /* Can't use a register if it is used for an output address
4604 for this operand or used as an output in this or a
4605 later operand. Note that multiple output operands are
4606 emitted in reverse order, so the conflicting ones are
4607 those with lower indices. */
4608 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4611 for (i = 0; i <= opnum; i++)
4612 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4617 case RELOAD_FOR_OPERAND_ADDRESS:
4618 for (i = 0; i < reload_n_operands; i++)
4619 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4622 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4623 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4625 case RELOAD_FOR_OPADDR_ADDR:
4626 for (i = 0; i < reload_n_operands; i++)
4627 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4630 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4632 case RELOAD_FOR_OUTPUT:
4633 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4634 outputs, or an operand address for this or an earlier output.
4635 Note that multiple output operands are emitted in reverse order,
4636 so the conflicting ones are those with higher indices. */
4637 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4640 for (i = 0; i < reload_n_operands; i++)
4641 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4644 for (i = opnum; i < reload_n_operands; i++)
4645 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4646 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4651 case RELOAD_FOR_INSN:
4652 for (i = 0; i < reload_n_operands; i++)
4653 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4654 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4657 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4658 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4660 case RELOAD_FOR_OTHER_ADDRESS:
4661 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4668 /* Return 1 if the value in reload reg REGNO, as used by a reload
4669 needed for the part of the insn specified by OPNUM and TYPE,
4670 is still available in REGNO at the end of the insn.
4672 We can assume that the reload reg was already tested for availability
4673 at the time it is needed, and we should not check this again,
4674 in case the reg has already been marked in use. */
4677 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4684 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4685 its value must reach the end. */
4688 /* If this use is for part of the insn,
4689 its value reaches if no subsequent part uses the same register.
4690 Just like the above function, don't try to do this with lots
4693 case RELOAD_FOR_OTHER_ADDRESS:
4694 /* Here we check for everything else, since these don't conflict
4695 with anything else and everything comes later. */
4697 for (i = 0; i < reload_n_operands; i++)
4698 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4699 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4700 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4701 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4702 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4703 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4706 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4707 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4708 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4709 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4711 case RELOAD_FOR_INPUT_ADDRESS:
4712 case RELOAD_FOR_INPADDR_ADDRESS:
4713 /* Similar, except that we check only for this and subsequent inputs
4714 and the address of only subsequent inputs and we do not need
4715 to check for RELOAD_OTHER objects since they are known not to
4718 for (i = opnum; i < reload_n_operands; i++)
4719 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4722 for (i = opnum + 1; i < reload_n_operands; i++)
4723 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4724 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4727 for (i = 0; i < reload_n_operands; i++)
4728 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4729 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4730 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4733 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4736 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4737 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4738 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4740 case RELOAD_FOR_INPUT:
4741 /* Similar to input address, except we start at the next operand for
4742 both input and input address and we do not check for
4743 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4746 for (i = opnum + 1; i < reload_n_operands; i++)
4747 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4748 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4749 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4752 /* ... fall through ... */
4754 case RELOAD_FOR_OPERAND_ADDRESS:
4755 /* Check outputs and their addresses. */
4757 for (i = 0; i < reload_n_operands; i++)
4758 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4759 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4760 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4763 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4765 case RELOAD_FOR_OPADDR_ADDR:
4766 for (i = 0; i < reload_n_operands; i++)
4767 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4768 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4769 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4772 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4773 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4774 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4776 case RELOAD_FOR_INSN:
4777 /* These conflict with other outputs with RELOAD_OTHER. So
4778 we need only check for output addresses. */
4780 opnum = reload_n_operands;
4782 /* ... fall through ... */
4784 case RELOAD_FOR_OUTPUT:
4785 case RELOAD_FOR_OUTPUT_ADDRESS:
4786 case RELOAD_FOR_OUTADDR_ADDRESS:
4787 /* We already know these can't conflict with a later output. So the
4788 only thing to check are later output addresses.
4789 Note that multiple output operands are emitted in reverse order,
4790 so the conflicting ones are those with lower indices. */
4791 for (i = 0; i < opnum; i++)
4792 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4793 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4804 /* Returns whether R1 and R2 are uniquely chained: the value of one
4805 is used by the other, and that value is not used by any other
4806 reload for this insn. This is used to partially undo the decision
4807 made in find_reloads when in the case of multiple
4808 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
4809 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
4810 reloads. This code tries to avoid the conflict created by that
4811 change. It might be cleaner to explicitly keep track of which
4812 RELOAD_FOR_OPADDR_ADDR reload is associated with which
4813 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
4814 this after the fact. */
4816 reloads_unique_chain_p (int r1, int r2)
4820 /* We only check input reloads. */
4821 if (! rld[r1].in || ! rld[r2].in)
4824 /* Avoid anything with output reloads. */
4825 if (rld[r1].out || rld[r2].out)
4828 /* "chained" means one reload is a component of the other reload,
4829 not the same as the other reload. */
4830 if (rld[r1].opnum != rld[r2].opnum
4831 || rtx_equal_p (rld[r1].in, rld[r2].in)
4832 || rld[r1].optional || rld[r2].optional
4833 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
4834 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
4837 for (i = 0; i < n_reloads; i ++)
4838 /* Look for input reloads that aren't our two */
4839 if (i != r1 && i != r2 && rld[i].in)
4841 /* If our reload is mentioned at all, it isn't a simple chain. */
4842 if (reg_mentioned_p (rld[r1].in, rld[i].in))
4848 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4851 This function uses the same algorithm as reload_reg_free_p above. */
4854 reloads_conflict (int r1, int r2)
4856 enum reload_type r1_type = rld[r1].when_needed;
4857 enum reload_type r2_type = rld[r2].when_needed;
4858 int r1_opnum = rld[r1].opnum;
4859 int r2_opnum = rld[r2].opnum;
4861 /* RELOAD_OTHER conflicts with everything. */
4862 if (r2_type == RELOAD_OTHER)
4865 /* Otherwise, check conflicts differently for each type. */
4869 case RELOAD_FOR_INPUT:
4870 return (r2_type == RELOAD_FOR_INSN
4871 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4872 || r2_type == RELOAD_FOR_OPADDR_ADDR
4873 || r2_type == RELOAD_FOR_INPUT
4874 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4875 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4876 && r2_opnum > r1_opnum));
4878 case RELOAD_FOR_INPUT_ADDRESS:
4879 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4880 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4882 case RELOAD_FOR_INPADDR_ADDRESS:
4883 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4884 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4886 case RELOAD_FOR_OUTPUT_ADDRESS:
4887 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4888 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4890 case RELOAD_FOR_OUTADDR_ADDRESS:
4891 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4892 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4894 case RELOAD_FOR_OPERAND_ADDRESS:
4895 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4896 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
4897 && !reloads_unique_chain_p (r1, r2)));
4899 case RELOAD_FOR_OPADDR_ADDR:
4900 return (r2_type == RELOAD_FOR_INPUT
4901 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4903 case RELOAD_FOR_OUTPUT:
4904 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4905 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4906 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4907 && r2_opnum >= r1_opnum));
4909 case RELOAD_FOR_INSN:
4910 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4911 || r2_type == RELOAD_FOR_INSN
4912 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4914 case RELOAD_FOR_OTHER_ADDRESS:
4915 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4925 /* Indexed by reload number, 1 if incoming value
4926 inherited from previous insns. */
4927 static char reload_inherited[MAX_RELOADS];
4929 /* For an inherited reload, this is the insn the reload was inherited from,
4930 if we know it. Otherwise, this is 0. */
4931 static rtx reload_inheritance_insn[MAX_RELOADS];
4933 /* If nonzero, this is a place to get the value of the reload,
4934 rather than using reload_in. */
4935 static rtx reload_override_in[MAX_RELOADS];
4937 /* For each reload, the hard register number of the register used,
4938 or -1 if we did not need a register for this reload. */
4939 static int reload_spill_index[MAX_RELOADS];
4941 /* Subroutine of free_for_value_p, used to check a single register.
4942 START_REGNO is the starting regno of the full reload register
4943 (possibly comprising multiple hard registers) that we are considering. */
4946 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4947 enum reload_type type, rtx value, rtx out,
4948 int reloadnum, int ignore_address_reloads)
4951 /* Set if we see an input reload that must not share its reload register
4952 with any new earlyclobber, but might otherwise share the reload
4953 register with an output or input-output reload. */
4954 int check_earlyclobber = 0;
4958 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4961 if (out == const0_rtx)
4967 /* We use some pseudo 'time' value to check if the lifetimes of the
4968 new register use would overlap with the one of a previous reload
4969 that is not read-only or uses a different value.
4970 The 'time' used doesn't have to be linear in any shape or form, just
4972 Some reload types use different 'buckets' for each operand.
4973 So there are MAX_RECOG_OPERANDS different time values for each
4975 We compute TIME1 as the time when the register for the prospective
4976 new reload ceases to be live, and TIME2 for each existing
4977 reload as the time when that the reload register of that reload
4979 Where there is little to be gained by exact lifetime calculations,
4980 we just make conservative assumptions, i.e. a longer lifetime;
4981 this is done in the 'default:' cases. */
4984 case RELOAD_FOR_OTHER_ADDRESS:
4985 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4986 time1 = copy ? 0 : 1;
4989 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4991 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4992 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4993 respectively, to the time values for these, we get distinct time
4994 values. To get distinct time values for each operand, we have to
4995 multiply opnum by at least three. We round that up to four because
4996 multiply by four is often cheaper. */
4997 case RELOAD_FOR_INPADDR_ADDRESS:
4998 time1 = opnum * 4 + 2;
5000 case RELOAD_FOR_INPUT_ADDRESS:
5001 time1 = opnum * 4 + 3;
5003 case RELOAD_FOR_INPUT:
5004 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5005 executes (inclusive). */
5006 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5008 case RELOAD_FOR_OPADDR_ADDR:
5010 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5011 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5013 case RELOAD_FOR_OPERAND_ADDRESS:
5014 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5016 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5018 case RELOAD_FOR_OUTADDR_ADDRESS:
5019 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5021 case RELOAD_FOR_OUTPUT_ADDRESS:
5022 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5025 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5028 for (i = 0; i < n_reloads; i++)
5030 rtx reg = rld[i].reg_rtx;
5031 if (reg && REG_P (reg)
5032 && ((unsigned) regno - true_regnum (reg)
5033 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5036 rtx other_input = rld[i].in;
5038 /* If the other reload loads the same input value, that
5039 will not cause a conflict only if it's loading it into
5040 the same register. */
5041 if (true_regnum (reg) != start_regno)
5042 other_input = NULL_RTX;
5043 if (! other_input || ! rtx_equal_p (other_input, value)
5044 || rld[i].out || out)
5047 switch (rld[i].when_needed)
5049 case RELOAD_FOR_OTHER_ADDRESS:
5052 case RELOAD_FOR_INPADDR_ADDRESS:
5053 /* find_reloads makes sure that a
5054 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5055 by at most one - the first -
5056 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5057 address reload is inherited, the address address reload
5058 goes away, so we can ignore this conflict. */
5059 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5060 && ignore_address_reloads
5061 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5062 Then the address address is still needed to store
5063 back the new address. */
5064 && ! rld[reloadnum].out)
5066 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5067 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5069 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5070 && ignore_address_reloads
5071 /* Unless we are reloading an auto_inc expression. */
5072 && ! rld[reloadnum].out)
5074 time2 = rld[i].opnum * 4 + 2;
5076 case RELOAD_FOR_INPUT_ADDRESS:
5077 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5078 && ignore_address_reloads
5079 && ! rld[reloadnum].out)
5081 time2 = rld[i].opnum * 4 + 3;
5083 case RELOAD_FOR_INPUT:
5084 time2 = rld[i].opnum * 4 + 4;
5085 check_earlyclobber = 1;
5087 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5088 == MAX_RECOG_OPERAND * 4 */
5089 case RELOAD_FOR_OPADDR_ADDR:
5090 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5091 && ignore_address_reloads
5092 && ! rld[reloadnum].out)
5094 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5096 case RELOAD_FOR_OPERAND_ADDRESS:
5097 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5098 check_earlyclobber = 1;
5100 case RELOAD_FOR_INSN:
5101 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5103 case RELOAD_FOR_OUTPUT:
5104 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5105 instruction is executed. */
5106 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5108 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5109 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5111 case RELOAD_FOR_OUTADDR_ADDRESS:
5112 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5113 && ignore_address_reloads
5114 && ! rld[reloadnum].out)
5116 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5118 case RELOAD_FOR_OUTPUT_ADDRESS:
5119 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5122 /* If there is no conflict in the input part, handle this
5123 like an output reload. */
5124 if (! rld[i].in || rtx_equal_p (other_input, value))
5126 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5127 /* Earlyclobbered outputs must conflict with inputs. */
5128 if (earlyclobber_operand_p (rld[i].out))
5129 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5134 /* RELOAD_OTHER might be live beyond instruction execution,
5135 but this is not obvious when we set time2 = 1. So check
5136 here if there might be a problem with the new reload
5137 clobbering the register used by the RELOAD_OTHER. */
5145 && (! rld[i].in || rld[i].out
5146 || ! rtx_equal_p (other_input, value)))
5147 || (out && rld[reloadnum].out_reg
5148 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5154 /* Earlyclobbered outputs must conflict with inputs. */
5155 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5161 /* Return 1 if the value in reload reg REGNO, as used by a reload
5162 needed for the part of the insn specified by OPNUM and TYPE,
5163 may be used to load VALUE into it.
5165 MODE is the mode in which the register is used, this is needed to
5166 determine how many hard regs to test.
5168 Other read-only reloads with the same value do not conflict
5169 unless OUT is nonzero and these other reloads have to live while
5170 output reloads live.
5171 If OUT is CONST0_RTX, this is a special case: it means that the
5172 test should not be for using register REGNO as reload register, but
5173 for copying from register REGNO into the reload register.
5175 RELOADNUM is the number of the reload we want to load this value for;
5176 a reload does not conflict with itself.
5178 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5179 reloads that load an address for the very reload we are considering.
5181 The caller has to make sure that there is no conflict with the return
5185 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5186 enum reload_type type, rtx value, rtx out, int reloadnum,
5187 int ignore_address_reloads)
5189 int nregs = hard_regno_nregs[regno][mode];
5191 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5192 value, out, reloadnum,
5193 ignore_address_reloads))
5198 /* Return nonzero if the rtx X is invariant over the current function. */
5199 /* ??? Actually, the places where we use this expect exactly what is
5200 tested here, and not everything that is function invariant. In
5201 particular, the frame pointer and arg pointer are special cased;
5202 pic_offset_table_rtx is not, and we must not spill these things to
5206 function_invariant_p (rtx x)
5210 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5212 if (GET_CODE (x) == PLUS
5213 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5214 && CONSTANT_P (XEXP (x, 1)))
5219 /* Determine whether the reload reg X overlaps any rtx'es used for
5220 overriding inheritance. Return nonzero if so. */
5223 conflicts_with_override (rtx x)
5226 for (i = 0; i < n_reloads; i++)
5227 if (reload_override_in[i]
5228 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5233 /* Give an error message saying we failed to find a reload for INSN,
5234 and clear out reload R. */
5236 failed_reload (rtx insn, int r)
5238 if (asm_noperands (PATTERN (insn)) < 0)
5239 /* It's the compiler's fault. */
5240 fatal_insn ("could not find a spill register", insn);
5242 /* It's the user's fault; the operand's mode and constraint
5243 don't match. Disable this reload so we don't crash in final. */
5244 error_for_asm (insn,
5245 "%<asm%> operand constraint incompatible with operand size");
5249 rld[r].optional = 1;
5250 rld[r].secondary_p = 1;
5253 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5254 for reload R. If it's valid, get an rtx for it. Return nonzero if
5257 set_reload_reg (int i, int r)
5260 rtx reg = spill_reg_rtx[i];
5262 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5263 spill_reg_rtx[i] = reg
5264 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5266 regno = true_regnum (reg);
5268 /* Detect when the reload reg can't hold the reload mode.
5269 This used to be one `if', but Sequent compiler can't handle that. */
5270 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5272 enum machine_mode test_mode = VOIDmode;
5274 test_mode = GET_MODE (rld[r].in);
5275 /* If rld[r].in has VOIDmode, it means we will load it
5276 in whatever mode the reload reg has: to wit, rld[r].mode.
5277 We have already tested that for validity. */
5278 /* Aside from that, we need to test that the expressions
5279 to reload from or into have modes which are valid for this
5280 reload register. Otherwise the reload insns would be invalid. */
5281 if (! (rld[r].in != 0 && test_mode != VOIDmode
5282 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5283 if (! (rld[r].out != 0
5284 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5286 /* The reg is OK. */
5289 /* Mark as in use for this insn the reload regs we use
5291 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5292 rld[r].when_needed, rld[r].mode);
5294 rld[r].reg_rtx = reg;
5295 reload_spill_index[r] = spill_regs[i];
5302 /* Find a spill register to use as a reload register for reload R.
5303 LAST_RELOAD is nonzero if this is the last reload for the insn being
5306 Set rld[R].reg_rtx to the register allocated.
5308 We return 1 if successful, or 0 if we couldn't find a spill reg and
5309 we didn't change anything. */
5312 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5317 /* If we put this reload ahead, thinking it is a group,
5318 then insist on finding a group. Otherwise we can grab a
5319 reg that some other reload needs.
5320 (That can happen when we have a 68000 DATA_OR_FP_REG
5321 which is a group of data regs or one fp reg.)
5322 We need not be so restrictive if there are no more reloads
5325 ??? Really it would be nicer to have smarter handling
5326 for that kind of reg class, where a problem like this is normal.
5327 Perhaps those classes should be avoided for reloading
5328 by use of more alternatives. */
5330 int force_group = rld[r].nregs > 1 && ! last_reload;
5332 /* If we want a single register and haven't yet found one,
5333 take any reg in the right class and not in use.
5334 If we want a consecutive group, here is where we look for it.
5336 We use two passes so we can first look for reload regs to
5337 reuse, which are already in use for other reloads in this insn,
5338 and only then use additional registers.
5339 I think that maximizing reuse is needed to make sure we don't
5340 run out of reload regs. Suppose we have three reloads, and
5341 reloads A and B can share regs. These need two regs.
5342 Suppose A and B are given different regs.
5343 That leaves none for C. */
5344 for (pass = 0; pass < 2; pass++)
5346 /* I is the index in spill_regs.
5347 We advance it round-robin between insns to use all spill regs
5348 equally, so that inherited reloads have a chance
5349 of leapfrogging each other. */
5353 for (count = 0; count < n_spills; count++)
5355 int class = (int) rld[r].class;
5361 regnum = spill_regs[i];
5363 if ((reload_reg_free_p (regnum, rld[r].opnum,
5366 /* We check reload_reg_used to make sure we
5367 don't clobber the return register. */
5368 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5369 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5370 rld[r].when_needed, rld[r].in,
5372 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5373 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5374 /* Look first for regs to share, then for unshared. But
5375 don't share regs used for inherited reloads; they are
5376 the ones we want to preserve. */
5378 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5380 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5383 int nr = hard_regno_nregs[regnum][rld[r].mode];
5384 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5385 (on 68000) got us two FP regs. If NR is 1,
5386 we would reject both of them. */
5389 /* If we need only one reg, we have already won. */
5392 /* But reject a single reg if we demand a group. */
5397 /* Otherwise check that as many consecutive regs as we need
5398 are available here. */
5401 int regno = regnum + nr - 1;
5402 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5403 && spill_reg_order[regno] >= 0
5404 && reload_reg_free_p (regno, rld[r].opnum,
5405 rld[r].when_needed)))
5414 /* If we found something on pass 1, omit pass 2. */
5415 if (count < n_spills)
5419 /* We should have found a spill register by now. */
5420 if (count >= n_spills)
5423 /* I is the index in SPILL_REG_RTX of the reload register we are to
5424 allocate. Get an rtx for it and find its register number. */
5426 return set_reload_reg (i, r);
5429 /* Initialize all the tables needed to allocate reload registers.
5430 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5431 is the array we use to restore the reg_rtx field for every reload. */
5434 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5438 for (i = 0; i < n_reloads; i++)
5439 rld[i].reg_rtx = save_reload_reg_rtx[i];
5441 memset (reload_inherited, 0, MAX_RELOADS);
5442 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5443 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5445 CLEAR_HARD_REG_SET (reload_reg_used);
5446 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5447 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5448 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5449 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5450 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5452 CLEAR_HARD_REG_SET (reg_used_in_insn);
5455 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5456 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5457 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5458 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5459 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5460 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5463 for (i = 0; i < reload_n_operands; i++)
5465 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5466 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5467 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5468 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5469 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5470 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5473 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5475 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5477 for (i = 0; i < n_reloads; i++)
5478 /* If we have already decided to use a certain register,
5479 don't use it in another way. */
5481 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5482 rld[i].when_needed, rld[i].mode);
5485 /* Assign hard reg targets for the pseudo-registers we must reload
5486 into hard regs for this insn.
5487 Also output the instructions to copy them in and out of the hard regs.
5489 For machines with register classes, we are responsible for
5490 finding a reload reg in the proper class. */
5493 choose_reload_regs (struct insn_chain *chain)
5495 rtx insn = chain->insn;
5497 unsigned int max_group_size = 1;
5498 enum reg_class group_class = NO_REGS;
5499 int pass, win, inheritance;
5501 rtx save_reload_reg_rtx[MAX_RELOADS];
5503 /* In order to be certain of getting the registers we need,
5504 we must sort the reloads into order of increasing register class.
5505 Then our grabbing of reload registers will parallel the process
5506 that provided the reload registers.
5508 Also note whether any of the reloads wants a consecutive group of regs.
5509 If so, record the maximum size of the group desired and what
5510 register class contains all the groups needed by this insn. */
5512 for (j = 0; j < n_reloads; j++)
5514 reload_order[j] = j;
5515 reload_spill_index[j] = -1;
5517 if (rld[j].nregs > 1)
5519 max_group_size = MAX (rld[j].nregs, max_group_size);
5521 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5524 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5528 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5530 /* If -O, try first with inheritance, then turning it off.
5531 If not -O, don't do inheritance.
5532 Using inheritance when not optimizing leads to paradoxes
5533 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5534 because one side of the comparison might be inherited. */
5536 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5538 choose_reload_regs_init (chain, save_reload_reg_rtx);
5540 /* Process the reloads in order of preference just found.
5541 Beyond this point, subregs can be found in reload_reg_rtx.
5543 This used to look for an existing reloaded home for all of the
5544 reloads, and only then perform any new reloads. But that could lose
5545 if the reloads were done out of reg-class order because a later
5546 reload with a looser constraint might have an old home in a register
5547 needed by an earlier reload with a tighter constraint.
5549 To solve this, we make two passes over the reloads, in the order
5550 described above. In the first pass we try to inherit a reload
5551 from a previous insn. If there is a later reload that needs a
5552 class that is a proper subset of the class being processed, we must
5553 also allocate a spill register during the first pass.
5555 Then make a second pass over the reloads to allocate any reloads
5556 that haven't been given registers yet. */
5558 for (j = 0; j < n_reloads; j++)
5560 int r = reload_order[j];
5561 rtx search_equiv = NULL_RTX;
5563 /* Ignore reloads that got marked inoperative. */
5564 if (rld[r].out == 0 && rld[r].in == 0
5565 && ! rld[r].secondary_p)
5568 /* If find_reloads chose to use reload_in or reload_out as a reload
5569 register, we don't need to chose one. Otherwise, try even if it
5570 found one since we might save an insn if we find the value lying
5572 Try also when reload_in is a pseudo without a hard reg. */
5573 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5574 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5575 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5576 && !MEM_P (rld[r].in)
5577 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5580 #if 0 /* No longer needed for correct operation.
5581 It might give better code, or might not; worth an experiment? */
5582 /* If this is an optional reload, we can't inherit from earlier insns
5583 until we are sure that any non-optional reloads have been allocated.
5584 The following code takes advantage of the fact that optional reloads
5585 are at the end of reload_order. */
5586 if (rld[r].optional != 0)
5587 for (i = 0; i < j; i++)
5588 if ((rld[reload_order[i]].out != 0
5589 || rld[reload_order[i]].in != 0
5590 || rld[reload_order[i]].secondary_p)
5591 && ! rld[reload_order[i]].optional
5592 && rld[reload_order[i]].reg_rtx == 0)
5593 allocate_reload_reg (chain, reload_order[i], 0);
5596 /* First see if this pseudo is already available as reloaded
5597 for a previous insn. We cannot try to inherit for reloads
5598 that are smaller than the maximum number of registers needed
5599 for groups unless the register we would allocate cannot be used
5602 We could check here to see if this is a secondary reload for
5603 an object that is already in a register of the desired class.
5604 This would avoid the need for the secondary reload register.
5605 But this is complex because we can't easily determine what
5606 objects might want to be loaded via this reload. So let a
5607 register be allocated here. In `emit_reload_insns' we suppress
5608 one of the loads in the case described above. */
5614 enum machine_mode mode = VOIDmode;
5618 else if (REG_P (rld[r].in))
5620 regno = REGNO (rld[r].in);
5621 mode = GET_MODE (rld[r].in);
5623 else if (REG_P (rld[r].in_reg))
5625 regno = REGNO (rld[r].in_reg);
5626 mode = GET_MODE (rld[r].in_reg);
5628 else if (GET_CODE (rld[r].in_reg) == SUBREG
5629 && REG_P (SUBREG_REG (rld[r].in_reg)))
5631 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5632 if (regno < FIRST_PSEUDO_REGISTER)
5633 regno = subreg_regno (rld[r].in_reg);
5635 byte = SUBREG_BYTE (rld[r].in_reg);
5636 mode = GET_MODE (rld[r].in_reg);
5639 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
5640 && REG_P (XEXP (rld[r].in_reg, 0)))
5642 regno = REGNO (XEXP (rld[r].in_reg, 0));
5643 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5644 rld[r].out = rld[r].in;
5648 /* This won't work, since REGNO can be a pseudo reg number.
5649 Also, it takes much more hair to keep track of all the things
5650 that can invalidate an inherited reload of part of a pseudoreg. */
5651 else if (GET_CODE (rld[r].in) == SUBREG
5652 && REG_P (SUBREG_REG (rld[r].in)))
5653 regno = subreg_regno (rld[r].in);
5656 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5658 enum reg_class class = rld[r].class, last_class;
5659 rtx last_reg = reg_last_reload_reg[regno];
5660 enum machine_mode need_mode;
5662 i = REGNO (last_reg);
5663 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5664 last_class = REGNO_REG_CLASS (i);
5670 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5671 + byte * BITS_PER_UNIT,
5672 GET_MODE_CLASS (mode));
5674 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5675 >= GET_MODE_SIZE (need_mode))
5676 #ifdef CANNOT_CHANGE_MODE_CLASS
5677 /* Verify that the register in "i" can be obtained
5679 && !REG_CANNOT_CHANGE_MODE_P (REGNO (last_reg),
5680 GET_MODE (last_reg),
5683 && reg_reloaded_contents[i] == regno
5684 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5685 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5686 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5687 /* Even if we can't use this register as a reload
5688 register, we might use it for reload_override_in,
5689 if copying it to the desired class is cheap
5691 || ((REGISTER_MOVE_COST (mode, last_class, class)
5692 < MEMORY_MOVE_COST (mode, class, 1))
5693 && (secondary_reload_class (1, class, mode,
5696 #ifdef SECONDARY_MEMORY_NEEDED
5697 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5702 && (rld[r].nregs == max_group_size
5703 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5705 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5706 rld[r].when_needed, rld[r].in,
5709 /* If a group is needed, verify that all the subsequent
5710 registers still have their values intact. */
5711 int nr = hard_regno_nregs[i][rld[r].mode];
5714 for (k = 1; k < nr; k++)
5715 if (reg_reloaded_contents[i + k] != regno
5716 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5724 last_reg = (GET_MODE (last_reg) == mode
5725 ? last_reg : gen_rtx_REG (mode, i));
5728 for (k = 0; k < nr; k++)
5729 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5732 /* We found a register that contains the
5733 value we need. If this register is the
5734 same as an `earlyclobber' operand of the
5735 current insn, just mark it as a place to
5736 reload from since we can't use it as the
5737 reload register itself. */
5739 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5740 if (reg_overlap_mentioned_for_reload_p
5741 (reg_last_reload_reg[regno],
5742 reload_earlyclobbers[i1]))
5745 if (i1 != n_earlyclobbers
5746 || ! (free_for_value_p (i, rld[r].mode,
5748 rld[r].when_needed, rld[r].in,
5750 /* Don't use it if we'd clobber a pseudo reg. */
5751 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5753 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5754 /* Don't clobber the frame pointer. */
5755 || (i == HARD_FRAME_POINTER_REGNUM
5756 && frame_pointer_needed
5758 /* Don't really use the inherited spill reg
5759 if we need it wider than we've got it. */
5760 || (GET_MODE_SIZE (rld[r].mode)
5761 > GET_MODE_SIZE (mode))
5764 /* If find_reloads chose reload_out as reload
5765 register, stay with it - that leaves the
5766 inherited register for subsequent reloads. */
5767 || (rld[r].out && rld[r].reg_rtx
5768 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5770 if (! rld[r].optional)
5772 reload_override_in[r] = last_reg;
5773 reload_inheritance_insn[r]
5774 = reg_reloaded_insn[i];
5780 /* We can use this as a reload reg. */
5781 /* Mark the register as in use for this part of
5783 mark_reload_reg_in_use (i,
5787 rld[r].reg_rtx = last_reg;
5788 reload_inherited[r] = 1;
5789 reload_inheritance_insn[r]
5790 = reg_reloaded_insn[i];
5791 reload_spill_index[r] = i;
5792 for (k = 0; k < nr; k++)
5793 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5801 /* Here's another way to see if the value is already lying around. */
5804 && ! reload_inherited[r]
5806 && (CONSTANT_P (rld[r].in)
5807 || GET_CODE (rld[r].in) == PLUS
5808 || REG_P (rld[r].in)
5809 || MEM_P (rld[r].in))
5810 && (rld[r].nregs == max_group_size
5811 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5812 search_equiv = rld[r].in;
5813 /* If this is an output reload from a simple move insn, look
5814 if an equivalence for the input is available. */
5815 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5817 rtx set = single_set (insn);
5820 && rtx_equal_p (rld[r].out, SET_DEST (set))
5821 && CONSTANT_P (SET_SRC (set)))
5822 search_equiv = SET_SRC (set);
5828 = find_equiv_reg (search_equiv, insn, rld[r].class,
5829 -1, NULL, 0, rld[r].mode);
5835 regno = REGNO (equiv);
5838 /* This must be a SUBREG of a hard register.
5839 Make a new REG since this might be used in an
5840 address and not all machines support SUBREGs
5842 gcc_assert (GET_CODE (equiv) == SUBREG);
5843 regno = subreg_regno (equiv);
5844 equiv = gen_rtx_REG (rld[r].mode, regno);
5845 /* If we choose EQUIV as the reload register, but the
5846 loop below decides to cancel the inheritance, we'll
5847 end up reloading EQUIV in rld[r].mode, not the mode
5848 it had originally. That isn't safe when EQUIV isn't
5849 available as a spill register since its value might
5850 still be live at this point. */
5851 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5852 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
5857 /* If we found a spill reg, reject it unless it is free
5858 and of the desired class. */
5862 int bad_for_class = 0;
5863 int max_regno = regno + rld[r].nregs;
5865 for (i = regno; i < max_regno; i++)
5867 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5869 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5874 && ! free_for_value_p (regno, rld[r].mode,
5875 rld[r].opnum, rld[r].when_needed,
5876 rld[r].in, rld[r].out, r, 1))
5881 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5884 /* We found a register that contains the value we need.
5885 If this register is the same as an `earlyclobber' operand
5886 of the current insn, just mark it as a place to reload from
5887 since we can't use it as the reload register itself. */
5890 for (i = 0; i < n_earlyclobbers; i++)
5891 if (reg_overlap_mentioned_for_reload_p (equiv,
5892 reload_earlyclobbers[i]))
5894 if (! rld[r].optional)
5895 reload_override_in[r] = equiv;
5900 /* If the equiv register we have found is explicitly clobbered
5901 in the current insn, it depends on the reload type if we
5902 can use it, use it for reload_override_in, or not at all.
5903 In particular, we then can't use EQUIV for a
5904 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5908 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
5909 switch (rld[r].when_needed)
5911 case RELOAD_FOR_OTHER_ADDRESS:
5912 case RELOAD_FOR_INPADDR_ADDRESS:
5913 case RELOAD_FOR_INPUT_ADDRESS:
5914 case RELOAD_FOR_OPADDR_ADDR:
5917 case RELOAD_FOR_INPUT:
5918 case RELOAD_FOR_OPERAND_ADDRESS:
5919 if (! rld[r].optional)
5920 reload_override_in[r] = equiv;
5926 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5927 switch (rld[r].when_needed)
5929 case RELOAD_FOR_OTHER_ADDRESS:
5930 case RELOAD_FOR_INPADDR_ADDRESS:
5931 case RELOAD_FOR_INPUT_ADDRESS:
5932 case RELOAD_FOR_OPADDR_ADDR:
5933 case RELOAD_FOR_OPERAND_ADDRESS:
5934 case RELOAD_FOR_INPUT:
5937 if (! rld[r].optional)
5938 reload_override_in[r] = equiv;
5946 /* If we found an equivalent reg, say no code need be generated
5947 to load it, and use it as our reload reg. */
5949 && (regno != HARD_FRAME_POINTER_REGNUM
5950 || !frame_pointer_needed))
5952 int nr = hard_regno_nregs[regno][rld[r].mode];
5954 rld[r].reg_rtx = equiv;
5955 reload_inherited[r] = 1;
5957 /* If reg_reloaded_valid is not set for this register,
5958 there might be a stale spill_reg_store lying around.
5959 We must clear it, since otherwise emit_reload_insns
5960 might delete the store. */
5961 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5962 spill_reg_store[regno] = NULL_RTX;
5963 /* If any of the hard registers in EQUIV are spill
5964 registers, mark them as in use for this insn. */
5965 for (k = 0; k < nr; k++)
5967 i = spill_reg_order[regno + k];
5970 mark_reload_reg_in_use (regno, rld[r].opnum,
5973 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5980 /* If we found a register to use already, or if this is an optional
5981 reload, we are done. */
5982 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5986 /* No longer needed for correct operation. Might or might
5987 not give better code on the average. Want to experiment? */
5989 /* See if there is a later reload that has a class different from our
5990 class that intersects our class or that requires less register
5991 than our reload. If so, we must allocate a register to this
5992 reload now, since that reload might inherit a previous reload
5993 and take the only available register in our class. Don't do this
5994 for optional reloads since they will force all previous reloads
5995 to be allocated. Also don't do this for reloads that have been
5998 for (i = j + 1; i < n_reloads; i++)
6000 int s = reload_order[i];
6002 if ((rld[s].in == 0 && rld[s].out == 0
6003 && ! rld[s].secondary_p)
6007 if ((rld[s].class != rld[r].class
6008 && reg_classes_intersect_p (rld[r].class,
6010 || rld[s].nregs < rld[r].nregs)
6017 allocate_reload_reg (chain, r, j == n_reloads - 1);
6021 /* Now allocate reload registers for anything non-optional that
6022 didn't get one yet. */
6023 for (j = 0; j < n_reloads; j++)
6025 int r = reload_order[j];
6027 /* Ignore reloads that got marked inoperative. */
6028 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6031 /* Skip reloads that already have a register allocated or are
6033 if (rld[r].reg_rtx != 0 || rld[r].optional)
6036 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6040 /* If that loop got all the way, we have won. */
6047 /* Loop around and try without any inheritance. */
6052 /* First undo everything done by the failed attempt
6053 to allocate with inheritance. */
6054 choose_reload_regs_init (chain, save_reload_reg_rtx);
6056 /* Some sanity tests to verify that the reloads found in the first
6057 pass are identical to the ones we have now. */
6058 gcc_assert (chain->n_reloads == n_reloads);
6060 for (i = 0; i < n_reloads; i++)
6062 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6064 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6065 for (j = 0; j < n_spills; j++)
6066 if (spill_regs[j] == chain->rld[i].regno)
6067 if (! set_reload_reg (j, i))
6068 failed_reload (chain->insn, i);
6072 /* If we thought we could inherit a reload, because it seemed that
6073 nothing else wanted the same reload register earlier in the insn,
6074 verify that assumption, now that all reloads have been assigned.
6075 Likewise for reloads where reload_override_in has been set. */
6077 /* If doing expensive optimizations, do one preliminary pass that doesn't
6078 cancel any inheritance, but removes reloads that have been needed only
6079 for reloads that we know can be inherited. */
6080 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6082 for (j = 0; j < n_reloads; j++)
6084 int r = reload_order[j];
6086 if (reload_inherited[r] && rld[r].reg_rtx)
6087 check_reg = rld[r].reg_rtx;
6088 else if (reload_override_in[r]
6089 && (REG_P (reload_override_in[r])
6090 || GET_CODE (reload_override_in[r]) == SUBREG))
6091 check_reg = reload_override_in[r];
6094 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6095 rld[r].opnum, rld[r].when_needed, rld[r].in,
6096 (reload_inherited[r]
6097 ? rld[r].out : const0_rtx),
6102 reload_inherited[r] = 0;
6103 reload_override_in[r] = 0;
6105 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6106 reload_override_in, then we do not need its related
6107 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6108 likewise for other reload types.
6109 We handle this by removing a reload when its only replacement
6110 is mentioned in reload_in of the reload we are going to inherit.
6111 A special case are auto_inc expressions; even if the input is
6112 inherited, we still need the address for the output. We can
6113 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6114 If we succeeded removing some reload and we are doing a preliminary
6115 pass just to remove such reloads, make another pass, since the
6116 removal of one reload might allow us to inherit another one. */
6118 && rld[r].out != rld[r].in
6119 && remove_address_replacements (rld[r].in) && pass)
6124 /* Now that reload_override_in is known valid,
6125 actually override reload_in. */
6126 for (j = 0; j < n_reloads; j++)
6127 if (reload_override_in[j])
6128 rld[j].in = reload_override_in[j];
6130 /* If this reload won't be done because it has been canceled or is
6131 optional and not inherited, clear reload_reg_rtx so other
6132 routines (such as subst_reloads) don't get confused. */
6133 for (j = 0; j < n_reloads; j++)
6134 if (rld[j].reg_rtx != 0
6135 && ((rld[j].optional && ! reload_inherited[j])
6136 || (rld[j].in == 0 && rld[j].out == 0
6137 && ! rld[j].secondary_p)))
6139 int regno = true_regnum (rld[j].reg_rtx);
6141 if (spill_reg_order[regno] >= 0)
6142 clear_reload_reg_in_use (regno, rld[j].opnum,
6143 rld[j].when_needed, rld[j].mode);
6145 reload_spill_index[j] = -1;
6148 /* Record which pseudos and which spill regs have output reloads. */
6149 for (j = 0; j < n_reloads; j++)
6151 int r = reload_order[j];
6153 i = reload_spill_index[r];
6155 /* I is nonneg if this reload uses a register.
6156 If rld[r].reg_rtx is 0, this is an optional reload
6157 that we opted to ignore. */
6158 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6159 && rld[r].reg_rtx != 0)
6161 int nregno = REGNO (rld[r].out_reg);
6164 if (nregno < FIRST_PSEUDO_REGISTER)
6165 nr = hard_regno_nregs[nregno][rld[r].mode];
6168 SET_REGNO_REG_SET (®_has_output_reload,
6173 nr = hard_regno_nregs[i][rld[r].mode];
6175 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6178 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6179 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6180 || rld[r].when_needed == RELOAD_FOR_INSN);
6185 /* Deallocate the reload register for reload R. This is called from
6186 remove_address_replacements. */
6189 deallocate_reload_reg (int r)
6193 if (! rld[r].reg_rtx)
6195 regno = true_regnum (rld[r].reg_rtx);
6197 if (spill_reg_order[regno] >= 0)
6198 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6200 reload_spill_index[r] = -1;
6203 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6204 reloads of the same item for fear that we might not have enough reload
6205 registers. However, normally they will get the same reload register
6206 and hence actually need not be loaded twice.
6208 Here we check for the most common case of this phenomenon: when we have
6209 a number of reloads for the same object, each of which were allocated
6210 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6211 reload, and is not modified in the insn itself. If we find such,
6212 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6213 This will not increase the number of spill registers needed and will
6214 prevent redundant code. */
6217 merge_assigned_reloads (rtx insn)
6221 /* Scan all the reloads looking for ones that only load values and
6222 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6223 assigned and not modified by INSN. */
6225 for (i = 0; i < n_reloads; i++)
6227 int conflicting_input = 0;
6228 int max_input_address_opnum = -1;
6229 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6231 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6232 || rld[i].out != 0 || rld[i].reg_rtx == 0
6233 || reg_set_p (rld[i].reg_rtx, insn))
6236 /* Look at all other reloads. Ensure that the only use of this
6237 reload_reg_rtx is in a reload that just loads the same value
6238 as we do. Note that any secondary reloads must be of the identical
6239 class since the values, modes, and result registers are the
6240 same, so we need not do anything with any secondary reloads. */
6242 for (j = 0; j < n_reloads; j++)
6244 if (i == j || rld[j].reg_rtx == 0
6245 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6249 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6250 && rld[j].opnum > max_input_address_opnum)
6251 max_input_address_opnum = rld[j].opnum;
6253 /* If the reload regs aren't exactly the same (e.g, different modes)
6254 or if the values are different, we can't merge this reload.
6255 But if it is an input reload, we might still merge
6256 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6258 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6259 || rld[j].out != 0 || rld[j].in == 0
6260 || ! rtx_equal_p (rld[i].in, rld[j].in))
6262 if (rld[j].when_needed != RELOAD_FOR_INPUT
6263 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6264 || rld[i].opnum > rld[j].opnum)
6265 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6267 conflicting_input = 1;
6268 if (min_conflicting_input_opnum > rld[j].opnum)
6269 min_conflicting_input_opnum = rld[j].opnum;
6273 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6274 we, in fact, found any matching reloads. */
6277 && max_input_address_opnum <= min_conflicting_input_opnum)
6279 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6281 for (j = 0; j < n_reloads; j++)
6282 if (i != j && rld[j].reg_rtx != 0
6283 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6284 && (! conflicting_input
6285 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6286 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6288 rld[i].when_needed = RELOAD_OTHER;
6290 reload_spill_index[j] = -1;
6291 transfer_replacements (i, j);
6294 /* If this is now RELOAD_OTHER, look for any reloads that load
6295 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6296 if they were for inputs, RELOAD_OTHER for outputs. Note that
6297 this test is equivalent to looking for reloads for this operand
6299 /* We must take special care with RELOAD_FOR_OUTPUT_ADDRESS; it may
6300 share registers with a RELOAD_FOR_INPUT, so we can not change it
6301 to RELOAD_FOR_OTHER_ADDRESS. We should never need to, since we
6302 do not modify RELOAD_FOR_OUTPUT. */
6304 if (rld[i].when_needed == RELOAD_OTHER)
6305 for (j = 0; j < n_reloads; j++)
6307 && rld[j].when_needed != RELOAD_OTHER
6308 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6309 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6310 && (! conflicting_input
6311 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6312 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6313 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6319 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6320 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6321 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6323 /* Check to see if we accidentally converted two
6324 reloads that use the same reload register with
6325 different inputs to the same type. If so, the
6326 resulting code won't work. */
6328 for (k = 0; k < j; k++)
6329 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6330 || rld[k].when_needed != rld[j].when_needed
6331 || !rtx_equal_p (rld[k].reg_rtx,
6333 || rtx_equal_p (rld[k].in,
6340 /* These arrays are filled by emit_reload_insns and its subroutines. */
6341 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6342 static rtx other_input_address_reload_insns = 0;
6343 static rtx other_input_reload_insns = 0;
6344 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6345 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6346 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6347 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6348 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6349 static rtx operand_reload_insns = 0;
6350 static rtx other_operand_reload_insns = 0;
6351 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6353 /* Values to be put in spill_reg_store are put here first. */
6354 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6355 static HARD_REG_SET reg_reloaded_died;
6357 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6358 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6359 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6360 adjusted register, and return true. Otherwise, return false. */
6362 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6363 enum reg_class new_class,
6364 enum machine_mode new_mode)
6369 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6371 unsigned regno = REGNO (reg);
6373 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6375 if (GET_MODE (reg) != new_mode)
6377 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6379 if (hard_regno_nregs[regno][new_mode]
6380 > hard_regno_nregs[regno][GET_MODE (reg)])
6382 reg = reload_adjust_reg_for_mode (reg, new_mode);
6390 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6391 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6392 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6393 adjusted register, and return true. Otherwise, return false. */
6395 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6396 enum insn_code icode)
6399 enum reg_class new_class = scratch_reload_class (icode);
6400 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6402 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6403 new_class, new_mode);
6406 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6407 has the number J. OLD contains the value to be used as input. */
6410 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6413 rtx insn = chain->insn;
6414 rtx reloadreg = rl->reg_rtx;
6415 rtx oldequiv_reg = 0;
6418 enum machine_mode mode;
6421 /* Determine the mode to reload in.
6422 This is very tricky because we have three to choose from.
6423 There is the mode the insn operand wants (rl->inmode).
6424 There is the mode of the reload register RELOADREG.
6425 There is the intrinsic mode of the operand, which we could find
6426 by stripping some SUBREGs.
6427 It turns out that RELOADREG's mode is irrelevant:
6428 we can change that arbitrarily.
6430 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6431 then the reload reg may not support QImode moves, so use SImode.
6432 If foo is in memory due to spilling a pseudo reg, this is safe,
6433 because the QImode value is in the least significant part of a
6434 slot big enough for a SImode. If foo is some other sort of
6435 memory reference, then it is impossible to reload this case,
6436 so previous passes had better make sure this never happens.
6438 Then consider a one-word union which has SImode and one of its
6439 members is a float, being fetched as (SUBREG:SF union:SI).
6440 We must fetch that as SFmode because we could be loading into
6441 a float-only register. In this case OLD's mode is correct.
6443 Consider an immediate integer: it has VOIDmode. Here we need
6444 to get a mode from something else.
6446 In some cases, there is a fourth mode, the operand's
6447 containing mode. If the insn specifies a containing mode for
6448 this operand, it overrides all others.
6450 I am not sure whether the algorithm here is always right,
6451 but it does the right things in those cases. */
6453 mode = GET_MODE (old);
6454 if (mode == VOIDmode)
6457 /* delete_output_reload is only invoked properly if old contains
6458 the original pseudo register. Since this is replaced with a
6459 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6460 find the pseudo in RELOAD_IN_REG. */
6461 if (reload_override_in[j]
6462 && REG_P (rl->in_reg))
6469 else if (REG_P (oldequiv))
6470 oldequiv_reg = oldequiv;
6471 else if (GET_CODE (oldequiv) == SUBREG)
6472 oldequiv_reg = SUBREG_REG (oldequiv);
6474 /* If we are reloading from a register that was recently stored in
6475 with an output-reload, see if we can prove there was
6476 actually no need to store the old value in it. */
6478 if (optimize && REG_P (oldequiv)
6479 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6480 && spill_reg_store[REGNO (oldequiv)]
6482 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6483 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6485 delete_output_reload (insn, j, REGNO (oldequiv));
6487 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6488 then load RELOADREG from OLDEQUIV. Note that we cannot use
6489 gen_lowpart_common since it can do the wrong thing when
6490 RELOADREG has a multi-word mode. Note that RELOADREG
6491 must always be a REG here. */
6493 if (GET_MODE (reloadreg) != mode)
6494 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6495 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6496 oldequiv = SUBREG_REG (oldequiv);
6497 if (GET_MODE (oldequiv) != VOIDmode
6498 && mode != GET_MODE (oldequiv))
6499 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6501 /* Switch to the right place to emit the reload insns. */
6502 switch (rl->when_needed)
6505 where = &other_input_reload_insns;
6507 case RELOAD_FOR_INPUT:
6508 where = &input_reload_insns[rl->opnum];
6510 case RELOAD_FOR_INPUT_ADDRESS:
6511 where = &input_address_reload_insns[rl->opnum];
6513 case RELOAD_FOR_INPADDR_ADDRESS:
6514 where = &inpaddr_address_reload_insns[rl->opnum];
6516 case RELOAD_FOR_OUTPUT_ADDRESS:
6517 where = &output_address_reload_insns[rl->opnum];
6519 case RELOAD_FOR_OUTADDR_ADDRESS:
6520 where = &outaddr_address_reload_insns[rl->opnum];
6522 case RELOAD_FOR_OPERAND_ADDRESS:
6523 where = &operand_reload_insns;
6525 case RELOAD_FOR_OPADDR_ADDR:
6526 where = &other_operand_reload_insns;
6528 case RELOAD_FOR_OTHER_ADDRESS:
6529 where = &other_input_address_reload_insns;
6535 push_to_sequence (*where);
6537 /* Auto-increment addresses must be reloaded in a special way. */
6538 if (rl->out && ! rl->out_reg)
6540 /* We are not going to bother supporting the case where a
6541 incremented register can't be copied directly from
6542 OLDEQUIV since this seems highly unlikely. */
6543 gcc_assert (rl->secondary_in_reload < 0);
6545 if (reload_inherited[j])
6546 oldequiv = reloadreg;
6548 old = XEXP (rl->in_reg, 0);
6550 if (optimize && REG_P (oldequiv)
6551 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6552 && spill_reg_store[REGNO (oldequiv)]
6554 && (dead_or_set_p (insn,
6555 spill_reg_stored_to[REGNO (oldequiv)])
6556 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6558 delete_output_reload (insn, j, REGNO (oldequiv));
6560 /* Prevent normal processing of this reload. */
6562 /* Output a special code sequence for this case. */
6563 new_spill_reg_store[REGNO (reloadreg)]
6564 = inc_for_reload (reloadreg, oldequiv, rl->out,
6568 /* If we are reloading a pseudo-register that was set by the previous
6569 insn, see if we can get rid of that pseudo-register entirely
6570 by redirecting the previous insn into our reload register. */
6572 else if (optimize && REG_P (old)
6573 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6574 && dead_or_set_p (insn, old)
6575 /* This is unsafe if some other reload
6576 uses the same reg first. */
6577 && ! conflicts_with_override (reloadreg)
6578 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6579 rl->when_needed, old, rl->out, j, 0))
6581 rtx temp = PREV_INSN (insn);
6582 while (temp && NOTE_P (temp))
6583 temp = PREV_INSN (temp);
6585 && NONJUMP_INSN_P (temp)
6586 && GET_CODE (PATTERN (temp)) == SET
6587 && SET_DEST (PATTERN (temp)) == old
6588 /* Make sure we can access insn_operand_constraint. */
6589 && asm_noperands (PATTERN (temp)) < 0
6590 /* This is unsafe if operand occurs more than once in current
6591 insn. Perhaps some occurrences aren't reloaded. */
6592 && count_occurrences (PATTERN (insn), old, 0) == 1)
6594 rtx old = SET_DEST (PATTERN (temp));
6595 /* Store into the reload register instead of the pseudo. */
6596 SET_DEST (PATTERN (temp)) = reloadreg;
6598 /* Verify that resulting insn is valid. */
6599 extract_insn (temp);
6600 if (constrain_operands (1))
6602 /* If the previous insn is an output reload, the source is
6603 a reload register, and its spill_reg_store entry will
6604 contain the previous destination. This is now
6606 if (REG_P (SET_SRC (PATTERN (temp)))
6607 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6609 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6610 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6613 /* If these are the only uses of the pseudo reg,
6614 pretend for GDB it lives in the reload reg we used. */
6615 if (REG_N_DEATHS (REGNO (old)) == 1
6616 && REG_N_SETS (REGNO (old)) == 1)
6618 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6619 alter_reg (REGNO (old), -1);
6625 SET_DEST (PATTERN (temp)) = old;
6630 /* We can't do that, so output an insn to load RELOADREG. */
6632 /* If we have a secondary reload, pick up the secondary register
6633 and icode, if any. If OLDEQUIV and OLD are different or
6634 if this is an in-out reload, recompute whether or not we
6635 still need a secondary register and what the icode should
6636 be. If we still need a secondary register and the class or
6637 icode is different, go back to reloading from OLD if using
6638 OLDEQUIV means that we got the wrong type of register. We
6639 cannot have different class or icode due to an in-out reload
6640 because we don't make such reloads when both the input and
6641 output need secondary reload registers. */
6643 if (! special && rl->secondary_in_reload >= 0)
6645 rtx second_reload_reg = 0;
6646 rtx third_reload_reg = 0;
6647 int secondary_reload = rl->secondary_in_reload;
6648 rtx real_oldequiv = oldequiv;
6651 enum insn_code icode;
6652 enum insn_code tertiary_icode = CODE_FOR_nothing;
6654 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6655 and similarly for OLD.
6656 See comments in get_secondary_reload in reload.c. */
6657 /* If it is a pseudo that cannot be replaced with its
6658 equivalent MEM, we must fall back to reload_in, which
6659 will have all the necessary substitutions registered.
6660 Likewise for a pseudo that can't be replaced with its
6661 equivalent constant.
6663 Take extra care for subregs of such pseudos. Note that
6664 we cannot use reg_equiv_mem in this case because it is
6665 not in the right mode. */
6668 if (GET_CODE (tmp) == SUBREG)
6669 tmp = SUBREG_REG (tmp);
6671 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6672 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6673 || reg_equiv_constant[REGNO (tmp)] != 0))
6675 if (! reg_equiv_mem[REGNO (tmp)]
6676 || num_not_at_initial_offset
6677 || GET_CODE (oldequiv) == SUBREG)
6678 real_oldequiv = rl->in;
6680 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6684 if (GET_CODE (tmp) == SUBREG)
6685 tmp = SUBREG_REG (tmp);
6687 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6688 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6689 || reg_equiv_constant[REGNO (tmp)] != 0))
6691 if (! reg_equiv_mem[REGNO (tmp)]
6692 || num_not_at_initial_offset
6693 || GET_CODE (old) == SUBREG)
6696 real_old = reg_equiv_mem[REGNO (tmp)];
6699 second_reload_reg = rld[secondary_reload].reg_rtx;
6700 if (rld[secondary_reload].secondary_in_reload >= 0)
6702 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
6704 third_reload_reg = rld[tertiary_reload].reg_rtx;
6705 tertiary_icode = rld[secondary_reload].secondary_in_icode;
6706 /* We'd have to add more code for quartary reloads. */
6707 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
6709 icode = rl->secondary_in_icode;
6711 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6712 || (rl->in != 0 && rl->out != 0))
6714 secondary_reload_info sri, sri2;
6715 enum reg_class new_class, new_t_class;
6717 sri.icode = CODE_FOR_nothing;
6718 sri.prev_sri = NULL;
6719 new_class = targetm.secondary_reload (1, real_oldequiv, rl->class,
6722 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
6723 second_reload_reg = 0;
6724 else if (new_class == NO_REGS)
6726 if (reload_adjust_reg_for_icode (&second_reload_reg,
6727 third_reload_reg, sri.icode))
6728 icode = sri.icode, third_reload_reg = 0;
6730 oldequiv = old, real_oldequiv = real_old;
6732 else if (sri.icode != CODE_FOR_nothing)
6733 /* We currently lack a way to express this in reloads. */
6737 sri2.icode = CODE_FOR_nothing;
6738 sri2.prev_sri = &sri;
6739 new_t_class = targetm.secondary_reload (1, real_oldequiv,
6740 new_class, mode, &sri);
6741 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
6743 if (reload_adjust_reg_for_temp (&second_reload_reg,
6746 third_reload_reg = 0, tertiary_icode = sri2.icode;
6748 oldequiv = old, real_oldequiv = real_old;
6750 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
6752 rtx intermediate = second_reload_reg;
6754 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6756 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
6759 second_reload_reg = intermediate;
6760 tertiary_icode = sri2.icode;
6763 oldequiv = old, real_oldequiv = real_old;
6765 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
6767 rtx intermediate = second_reload_reg;
6769 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6771 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
6774 second_reload_reg = intermediate;
6775 tertiary_icode = sri2.icode;
6778 oldequiv = old, real_oldequiv = real_old;
6781 /* This could be handled more intelligently too. */
6782 oldequiv = old, real_oldequiv = real_old;
6786 /* If we still need a secondary reload register, check
6787 to see if it is being used as a scratch or intermediate
6788 register and generate code appropriately. If we need
6789 a scratch register, use REAL_OLDEQUIV since the form of
6790 the insn may depend on the actual address if it is
6793 if (second_reload_reg)
6795 if (icode != CODE_FOR_nothing)
6797 /* We'd have to add extra code to handle this case. */
6798 gcc_assert (!third_reload_reg);
6800 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6801 second_reload_reg));
6806 /* See if we need a scratch register to load the
6807 intermediate register (a tertiary reload). */
6808 if (tertiary_icode != CODE_FOR_nothing)
6810 emit_insn ((GEN_FCN (tertiary_icode)
6811 (second_reload_reg, real_oldequiv,
6812 third_reload_reg)));
6814 else if (third_reload_reg)
6816 gen_reload (third_reload_reg, real_oldequiv,
6819 gen_reload (second_reload_reg, third_reload_reg,
6824 gen_reload (second_reload_reg, real_oldequiv,
6828 oldequiv = second_reload_reg;
6833 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6835 rtx real_oldequiv = oldequiv;
6837 if ((REG_P (oldequiv)
6838 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6839 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6840 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6841 || (GET_CODE (oldequiv) == SUBREG
6842 && REG_P (SUBREG_REG (oldequiv))
6843 && (REGNO (SUBREG_REG (oldequiv))
6844 >= FIRST_PSEUDO_REGISTER)
6845 && ((reg_equiv_memory_loc
6846 [REGNO (SUBREG_REG (oldequiv))] != 0)
6847 || (reg_equiv_constant
6848 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6849 || (CONSTANT_P (oldequiv)
6850 && (PREFERRED_RELOAD_CLASS (oldequiv,
6851 REGNO_REG_CLASS (REGNO (reloadreg)))
6853 real_oldequiv = rl->in;
6854 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6858 if (flag_non_call_exceptions)
6859 copy_eh_notes (insn, get_insns ());
6861 /* End this sequence. */
6862 *where = get_insns ();
6865 /* Update reload_override_in so that delete_address_reloads_1
6866 can see the actual register usage. */
6868 reload_override_in[j] = oldequiv;
6871 /* Generate insns to for the output reload RL, which is for the insn described
6872 by CHAIN and has the number J. */
6874 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6877 rtx reloadreg = rl->reg_rtx;
6878 rtx insn = chain->insn;
6881 enum machine_mode mode = GET_MODE (old);
6884 if (rl->when_needed == RELOAD_OTHER)
6887 push_to_sequence (output_reload_insns[rl->opnum]);
6889 /* Determine the mode to reload in.
6890 See comments above (for input reloading). */
6892 if (mode == VOIDmode)
6894 /* VOIDmode should never happen for an output. */
6895 if (asm_noperands (PATTERN (insn)) < 0)
6896 /* It's the compiler's fault. */
6897 fatal_insn ("VOIDmode on an output", insn);
6898 error_for_asm (insn, "output operand is constant in %<asm%>");
6899 /* Prevent crash--use something we know is valid. */
6901 old = gen_rtx_REG (mode, REGNO (reloadreg));
6904 if (GET_MODE (reloadreg) != mode)
6905 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6907 /* If we need two reload regs, set RELOADREG to the intermediate
6908 one, since it will be stored into OLD. We might need a secondary
6909 register only for an input reload, so check again here. */
6911 if (rl->secondary_out_reload >= 0)
6914 int secondary_reload = rl->secondary_out_reload;
6915 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
6917 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
6918 && reg_equiv_mem[REGNO (old)] != 0)
6919 real_old = reg_equiv_mem[REGNO (old)];
6921 if (secondary_reload_class (0, rl->class, mode, real_old) != NO_REGS)
6923 rtx second_reloadreg = reloadreg;
6924 reloadreg = rld[secondary_reload].reg_rtx;
6926 /* See if RELOADREG is to be used as a scratch register
6927 or as an intermediate register. */
6928 if (rl->secondary_out_icode != CODE_FOR_nothing)
6930 /* We'd have to add extra code to handle this case. */
6931 gcc_assert (tertiary_reload < 0);
6933 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6934 (real_old, second_reloadreg, reloadreg)));
6939 /* See if we need both a scratch and intermediate reload
6942 enum insn_code tertiary_icode
6943 = rld[secondary_reload].secondary_out_icode;
6945 /* We'd have to add more code for quartary reloads. */
6946 gcc_assert (tertiary_reload < 0
6947 || rld[tertiary_reload].secondary_out_reload < 0);
6949 if (GET_MODE (reloadreg) != mode)
6950 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6952 if (tertiary_icode != CODE_FOR_nothing)
6954 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
6957 /* Copy primary reload reg to secondary reload reg.
6958 (Note that these have been swapped above, then
6959 secondary reload reg to OLD using our insn.) */
6961 /* If REAL_OLD is a paradoxical SUBREG, remove it
6962 and try to put the opposite SUBREG on
6964 if (GET_CODE (real_old) == SUBREG
6965 && (GET_MODE_SIZE (GET_MODE (real_old))
6966 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6967 && 0 != (tem = gen_lowpart_common
6968 (GET_MODE (SUBREG_REG (real_old)),
6970 real_old = SUBREG_REG (real_old), reloadreg = tem;
6972 gen_reload (reloadreg, second_reloadreg,
6973 rl->opnum, rl->when_needed);
6974 emit_insn ((GEN_FCN (tertiary_icode)
6975 (real_old, reloadreg, third_reloadreg)));
6981 /* Copy between the reload regs here and then to
6984 gen_reload (reloadreg, second_reloadreg,
6985 rl->opnum, rl->when_needed);
6986 if (tertiary_reload >= 0)
6988 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
6990 gen_reload (third_reloadreg, reloadreg,
6991 rl->opnum, rl->when_needed);
6992 reloadreg = third_reloadreg;
6999 /* Output the last reload insn. */
7004 /* Don't output the last reload if OLD is not the dest of
7005 INSN and is in the src and is clobbered by INSN. */
7006 if (! flag_expensive_optimizations
7008 || !(set = single_set (insn))
7009 || rtx_equal_p (old, SET_DEST (set))
7010 || !reg_mentioned_p (old, SET_SRC (set))
7011 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7012 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7013 gen_reload (old, reloadreg, rl->opnum,
7017 /* Look at all insns we emitted, just to be safe. */
7018 for (p = get_insns (); p; p = NEXT_INSN (p))
7021 rtx pat = PATTERN (p);
7023 /* If this output reload doesn't come from a spill reg,
7024 clear any memory of reloaded copies of the pseudo reg.
7025 If this output reload comes from a spill reg,
7026 reg_has_output_reload will make this do nothing. */
7027 note_stores (pat, forget_old_reloads_1, NULL);
7029 if (reg_mentioned_p (rl->reg_rtx, pat))
7031 rtx set = single_set (insn);
7032 if (reload_spill_index[j] < 0
7034 && SET_SRC (set) == rl->reg_rtx)
7036 int src = REGNO (SET_SRC (set));
7038 reload_spill_index[j] = src;
7039 SET_HARD_REG_BIT (reg_is_output_reload, src);
7040 if (find_regno_note (insn, REG_DEAD, src))
7041 SET_HARD_REG_BIT (reg_reloaded_died, src);
7043 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
7045 int s = rl->secondary_out_reload;
7046 set = single_set (p);
7047 /* If this reload copies only to the secondary reload
7048 register, the secondary reload does the actual
7050 if (s >= 0 && set == NULL_RTX)
7051 /* We can't tell what function the secondary reload
7052 has and where the actual store to the pseudo is
7053 made; leave new_spill_reg_store alone. */
7056 && SET_SRC (set) == rl->reg_rtx
7057 && SET_DEST (set) == rld[s].reg_rtx)
7059 /* Usually the next instruction will be the
7060 secondary reload insn; if we can confirm
7061 that it is, setting new_spill_reg_store to
7062 that insn will allow an extra optimization. */
7063 rtx s_reg = rld[s].reg_rtx;
7064 rtx next = NEXT_INSN (p);
7065 rld[s].out = rl->out;
7066 rld[s].out_reg = rl->out_reg;
7067 set = single_set (next);
7068 if (set && SET_SRC (set) == s_reg
7069 && ! new_spill_reg_store[REGNO (s_reg)])
7071 SET_HARD_REG_BIT (reg_is_output_reload,
7073 new_spill_reg_store[REGNO (s_reg)] = next;
7077 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
7082 if (rl->when_needed == RELOAD_OTHER)
7084 emit_insn (other_output_reload_insns[rl->opnum]);
7085 other_output_reload_insns[rl->opnum] = get_insns ();
7088 output_reload_insns[rl->opnum] = get_insns ();
7090 if (flag_non_call_exceptions)
7091 copy_eh_notes (insn, get_insns ());
7096 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7097 and has the number J. */
7099 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7101 rtx insn = chain->insn;
7102 rtx old = (rl->in && MEM_P (rl->in)
7103 ? rl->in_reg : rl->in);
7106 /* AUTO_INC reloads need to be handled even if inherited. We got an
7107 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7108 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7109 && ! rtx_equal_p (rl->reg_rtx, old)
7110 && rl->reg_rtx != 0)
7111 emit_input_reload_insns (chain, rld + j, old, j);
7113 /* When inheriting a wider reload, we have a MEM in rl->in,
7114 e.g. inheriting a SImode output reload for
7115 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7116 if (optimize && reload_inherited[j] && rl->in
7118 && MEM_P (rl->in_reg)
7119 && reload_spill_index[j] >= 0
7120 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7121 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7123 /* If we are reloading a register that was recently stored in with an
7124 output-reload, see if we can prove there was
7125 actually no need to store the old value in it. */
7128 /* Only attempt this for input reloads; for RELOAD_OTHER we miss
7129 that there may be multiple uses of the previous output reload.
7130 Restricting to RELOAD_FOR_INPUT is mostly paranoia. */
7131 && rl->when_needed == RELOAD_FOR_INPUT
7132 && (reload_inherited[j] || reload_override_in[j])
7134 && REG_P (rl->reg_rtx)
7135 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
7137 /* There doesn't seem to be any reason to restrict this to pseudos
7138 and doing so loses in the case where we are copying from a
7139 register of the wrong class. */
7140 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
7141 >= FIRST_PSEUDO_REGISTER)
7143 /* The insn might have already some references to stackslots
7144 replaced by MEMs, while reload_out_reg still names the
7146 && (dead_or_set_p (insn,
7147 spill_reg_stored_to[REGNO (rl->reg_rtx)])
7148 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
7150 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
7153 /* Do output reloading for reload RL, which is for the insn described by
7154 CHAIN and has the number J.
7155 ??? At some point we need to support handling output reloads of
7156 JUMP_INSNs or insns that set cc0. */
7158 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7161 rtx insn = chain->insn;
7162 /* If this is an output reload that stores something that is
7163 not loaded in this same reload, see if we can eliminate a previous
7165 rtx pseudo = rl->out_reg;
7170 && ! rtx_equal_p (rl->in_reg, pseudo)
7171 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7172 && reg_last_reload_reg[REGNO (pseudo)])
7174 int pseudo_no = REGNO (pseudo);
7175 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7177 /* We don't need to test full validity of last_regno for
7178 inherit here; we only want to know if the store actually
7179 matches the pseudo. */
7180 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7181 && reg_reloaded_contents[last_regno] == pseudo_no
7182 && spill_reg_store[last_regno]
7183 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7184 delete_output_reload (insn, j, last_regno);
7189 || rl->reg_rtx == old
7190 || rl->reg_rtx == 0)
7193 /* An output operand that dies right away does need a reload,
7194 but need not be copied from it. Show the new location in the
7196 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7197 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7199 XEXP (note, 0) = rl->reg_rtx;
7202 /* Likewise for a SUBREG of an operand that dies. */
7203 else if (GET_CODE (old) == SUBREG
7204 && REG_P (SUBREG_REG (old))
7205 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7208 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7212 else if (GET_CODE (old) == SCRATCH)
7213 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7214 but we don't want to make an output reload. */
7217 /* If is a JUMP_INSN, we can't support output reloads yet. */
7218 gcc_assert (NONJUMP_INSN_P (insn));
7220 emit_output_reload_insns (chain, rld + j, j);
7223 /* Reload number R reloads from or to a group of hard registers starting at
7224 register REGNO. Return true if it can be treated for inheritance purposes
7225 like a group of reloads, each one reloading a single hard register.
7226 The caller has already checked that the spill register and REGNO use
7227 the same number of registers to store the reload value. */
7230 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
7232 #ifdef CANNOT_CHANGE_MODE_CLASS
7233 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
7234 GET_MODE (rld[r].reg_rtx),
7235 reg_raw_mode[reload_spill_index[r]])
7236 && !REG_CANNOT_CHANGE_MODE_P (regno,
7237 GET_MODE (rld[r].reg_rtx),
7238 reg_raw_mode[regno]));
7244 /* Output insns to reload values in and out of the chosen reload regs. */
7247 emit_reload_insns (struct insn_chain *chain)
7249 rtx insn = chain->insn;
7253 CLEAR_HARD_REG_SET (reg_reloaded_died);
7255 for (j = 0; j < reload_n_operands; j++)
7256 input_reload_insns[j] = input_address_reload_insns[j]
7257 = inpaddr_address_reload_insns[j]
7258 = output_reload_insns[j] = output_address_reload_insns[j]
7259 = outaddr_address_reload_insns[j]
7260 = other_output_reload_insns[j] = 0;
7261 other_input_address_reload_insns = 0;
7262 other_input_reload_insns = 0;
7263 operand_reload_insns = 0;
7264 other_operand_reload_insns = 0;
7266 /* Dump reloads into the dump file. */
7269 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7270 debug_reload_to_stream (dump_file);
7273 /* Now output the instructions to copy the data into and out of the
7274 reload registers. Do these in the order that the reloads were reported,
7275 since reloads of base and index registers precede reloads of operands
7276 and the operands may need the base and index registers reloaded. */
7278 for (j = 0; j < n_reloads; j++)
7281 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7282 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7284 do_input_reload (chain, rld + j, j);
7285 do_output_reload (chain, rld + j, j);
7288 /* Now write all the insns we made for reloads in the order expected by
7289 the allocation functions. Prior to the insn being reloaded, we write
7290 the following reloads:
7292 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7294 RELOAD_OTHER reloads.
7296 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7297 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7298 RELOAD_FOR_INPUT reload for the operand.
7300 RELOAD_FOR_OPADDR_ADDRS reloads.
7302 RELOAD_FOR_OPERAND_ADDRESS reloads.
7304 After the insn being reloaded, we write the following:
7306 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7307 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7308 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7309 reloads for the operand. The RELOAD_OTHER output reloads are
7310 output in descending order by reload number. */
7312 emit_insn_before (other_input_address_reload_insns, insn);
7313 emit_insn_before (other_input_reload_insns, insn);
7315 for (j = 0; j < reload_n_operands; j++)
7317 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7318 emit_insn_before (input_address_reload_insns[j], insn);
7319 emit_insn_before (input_reload_insns[j], insn);
7322 emit_insn_before (other_operand_reload_insns, insn);
7323 emit_insn_before (operand_reload_insns, insn);
7325 for (j = 0; j < reload_n_operands; j++)
7327 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7328 x = emit_insn_after (output_address_reload_insns[j], x);
7329 x = emit_insn_after (output_reload_insns[j], x);
7330 emit_insn_after (other_output_reload_insns[j], x);
7333 /* For all the spill regs newly reloaded in this instruction,
7334 record what they were reloaded from, so subsequent instructions
7335 can inherit the reloads.
7337 Update spill_reg_store for the reloads of this insn.
7338 Copy the elements that were updated in the loop above. */
7340 for (j = 0; j < n_reloads; j++)
7342 int r = reload_order[j];
7343 int i = reload_spill_index[r];
7345 /* If this is a non-inherited input reload from a pseudo, we must
7346 clear any memory of a previous store to the same pseudo. Only do
7347 something if there will not be an output reload for the pseudo
7349 if (rld[r].in_reg != 0
7350 && ! (reload_inherited[r] || reload_override_in[r]))
7352 rtx reg = rld[r].in_reg;
7354 if (GET_CODE (reg) == SUBREG)
7355 reg = SUBREG_REG (reg);
7358 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7359 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7361 int nregno = REGNO (reg);
7363 if (reg_last_reload_reg[nregno])
7365 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7367 if (reg_reloaded_contents[last_regno] == nregno)
7368 spill_reg_store[last_regno] = 0;
7373 /* I is nonneg if this reload used a register.
7374 If rld[r].reg_rtx is 0, this is an optional reload
7375 that we opted to ignore. */
7377 if (i >= 0 && rld[r].reg_rtx != 0)
7379 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7381 int part_reaches_end = 0;
7382 int all_reaches_end = 1;
7384 /* For a multi register reload, we need to check if all or part
7385 of the value lives to the end. */
7386 for (k = 0; k < nr; k++)
7388 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7389 rld[r].when_needed))
7390 part_reaches_end = 1;
7392 all_reaches_end = 0;
7395 /* Ignore reloads that don't reach the end of the insn in
7397 if (all_reaches_end)
7399 /* First, clear out memory of what used to be in this spill reg.
7400 If consecutive registers are used, clear them all. */
7402 for (k = 0; k < nr; k++)
7404 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7405 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7408 /* Maybe the spill reg contains a copy of reload_out. */
7410 && (REG_P (rld[r].out)
7414 || REG_P (rld[r].out_reg)))
7416 rtx out = (REG_P (rld[r].out)
7420 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7421 int nregno = REGNO (out);
7422 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7423 : hard_regno_nregs[nregno]
7424 [GET_MODE (rld[r].reg_rtx)]);
7427 spill_reg_store[i] = new_spill_reg_store[i];
7428 spill_reg_stored_to[i] = out;
7429 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7431 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7433 && inherit_piecemeal_p (r, nregno));
7435 /* If NREGNO is a hard register, it may occupy more than
7436 one register. If it does, say what is in the
7437 rest of the registers assuming that both registers
7438 agree on how many words the object takes. If not,
7439 invalidate the subsequent registers. */
7441 if (nregno < FIRST_PSEUDO_REGISTER)
7442 for (k = 1; k < nnr; k++)
7443 reg_last_reload_reg[nregno + k]
7445 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7448 /* Now do the inverse operation. */
7449 for (k = 0; k < nr; k++)
7451 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7452 reg_reloaded_contents[i + k]
7453 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7456 reg_reloaded_insn[i + k] = insn;
7457 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7458 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7459 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7463 /* Maybe the spill reg contains a copy of reload_in. Only do
7464 something if there will not be an output reload for
7465 the register being reloaded. */
7466 else if (rld[r].out_reg == 0
7468 && ((REG_P (rld[r].in)
7469 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7470 && !REGNO_REG_SET_P (®_has_output_reload,
7472 || (REG_P (rld[r].in_reg)
7473 && !REGNO_REG_SET_P (®_has_output_reload,
7474 REGNO (rld[r].in_reg))))
7475 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7482 if (REG_P (rld[r].in)
7483 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7485 else if (REG_P (rld[r].in_reg))
7488 in = XEXP (rld[r].in_reg, 0);
7489 nregno = REGNO (in);
7491 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7492 : hard_regno_nregs[nregno]
7493 [GET_MODE (rld[r].reg_rtx)]);
7495 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7497 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7499 && inherit_piecemeal_p (r, nregno));
7501 if (nregno < FIRST_PSEUDO_REGISTER)
7502 for (k = 1; k < nnr; k++)
7503 reg_last_reload_reg[nregno + k]
7505 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7508 /* Unless we inherited this reload, show we haven't
7509 recently done a store.
7510 Previous stores of inherited auto_inc expressions
7511 also have to be discarded. */
7512 if (! reload_inherited[r]
7513 || (rld[r].out && ! rld[r].out_reg))
7514 spill_reg_store[i] = 0;
7516 for (k = 0; k < nr; k++)
7518 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7519 reg_reloaded_contents[i + k]
7520 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7523 reg_reloaded_insn[i + k] = insn;
7524 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7525 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7526 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7531 /* However, if part of the reload reaches the end, then we must
7532 invalidate the old info for the part that survives to the end. */
7533 else if (part_reaches_end)
7535 for (k = 0; k < nr; k++)
7536 if (reload_reg_reaches_end_p (i + k,
7538 rld[r].when_needed))
7539 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7543 /* The following if-statement was #if 0'd in 1.34 (or before...).
7544 It's reenabled in 1.35 because supposedly nothing else
7545 deals with this problem. */
7547 /* If a register gets output-reloaded from a non-spill register,
7548 that invalidates any previous reloaded copy of it.
7549 But forget_old_reloads_1 won't get to see it, because
7550 it thinks only about the original insn. So invalidate it here.
7551 Also do the same thing for RELOAD_OTHER constraints where the
7552 output is discarded. */
7554 && ((rld[r].out != 0
7555 && (REG_P (rld[r].out)
7556 || (MEM_P (rld[r].out)
7557 && REG_P (rld[r].out_reg))))
7558 || (rld[r].out == 0 && rld[r].out_reg
7559 && REG_P (rld[r].out_reg))))
7561 rtx out = ((rld[r].out && REG_P (rld[r].out))
7562 ? rld[r].out : rld[r].out_reg);
7563 int nregno = REGNO (out);
7564 if (nregno >= FIRST_PSEUDO_REGISTER)
7566 rtx src_reg, store_insn = NULL_RTX;
7568 reg_last_reload_reg[nregno] = 0;
7570 /* If we can find a hard register that is stored, record
7571 the storing insn so that we may delete this insn with
7572 delete_output_reload. */
7573 src_reg = rld[r].reg_rtx;
7575 /* If this is an optional reload, try to find the source reg
7576 from an input reload. */
7579 rtx set = single_set (insn);
7580 if (set && SET_DEST (set) == rld[r].out)
7584 src_reg = SET_SRC (set);
7586 for (k = 0; k < n_reloads; k++)
7588 if (rld[k].in == src_reg)
7590 src_reg = rld[k].reg_rtx;
7597 store_insn = new_spill_reg_store[REGNO (src_reg)];
7598 if (src_reg && REG_P (src_reg)
7599 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7601 int src_regno = REGNO (src_reg);
7602 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7603 /* The place where to find a death note varies with
7604 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7605 necessarily checked exactly in the code that moves
7606 notes, so just check both locations. */
7607 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7608 if (! note && store_insn)
7609 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7612 spill_reg_store[src_regno + nr] = store_insn;
7613 spill_reg_stored_to[src_regno + nr] = out;
7614 reg_reloaded_contents[src_regno + nr] = nregno;
7615 reg_reloaded_insn[src_regno + nr] = store_insn;
7616 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7617 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7618 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7619 GET_MODE (src_reg)))
7620 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7622 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7624 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7626 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7628 reg_last_reload_reg[nregno] = src_reg;
7629 /* We have to set reg_has_output_reload here, or else
7630 forget_old_reloads_1 will clear reg_last_reload_reg
7632 SET_REGNO_REG_SET (®_has_output_reload,
7638 int num_regs = hard_regno_nregs[nregno][GET_MODE (out)];
7640 while (num_regs-- > 0)
7641 reg_last_reload_reg[nregno + num_regs] = 0;
7645 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7648 /* Go through the motions to emit INSN and test if it is strictly valid.
7649 Return the emitted insn if valid, else return NULL. */
7652 emit_insn_if_valid_for_reload (rtx insn)
7654 rtx last = get_last_insn ();
7657 insn = emit_insn (insn);
7658 code = recog_memoized (insn);
7662 extract_insn (insn);
7663 /* We want constrain operands to treat this insn strictly in its
7664 validity determination, i.e., the way it would after reload has
7666 if (constrain_operands (1))
7670 delete_insns_since (last);
7674 /* Emit code to perform a reload from IN (which may be a reload register) to
7675 OUT (which may also be a reload register). IN or OUT is from operand
7676 OPNUM with reload type TYPE.
7678 Returns first insn emitted. */
7681 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7683 rtx last = get_last_insn ();
7686 /* If IN is a paradoxical SUBREG, remove it and try to put the
7687 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7688 if (GET_CODE (in) == SUBREG
7689 && (GET_MODE_SIZE (GET_MODE (in))
7690 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7691 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7692 in = SUBREG_REG (in), out = tem;
7693 else if (GET_CODE (out) == SUBREG
7694 && (GET_MODE_SIZE (GET_MODE (out))
7695 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7696 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7697 out = SUBREG_REG (out), in = tem;
7699 /* How to do this reload can get quite tricky. Normally, we are being
7700 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7701 register that didn't get a hard register. In that case we can just
7702 call emit_move_insn.
7704 We can also be asked to reload a PLUS that adds a register or a MEM to
7705 another register, constant or MEM. This can occur during frame pointer
7706 elimination and while reloading addresses. This case is handled by
7707 trying to emit a single insn to perform the add. If it is not valid,
7708 we use a two insn sequence.
7710 Or we can be asked to reload an unary operand that was a fragment of
7711 an addressing mode, into a register. If it isn't recognized as-is,
7712 we try making the unop operand and the reload-register the same:
7713 (set reg:X (unop:X expr:Y))
7714 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
7716 Finally, we could be called to handle an 'o' constraint by putting
7717 an address into a register. In that case, we first try to do this
7718 with a named pattern of "reload_load_address". If no such pattern
7719 exists, we just emit a SET insn and hope for the best (it will normally
7720 be valid on machines that use 'o').
7722 This entire process is made complex because reload will never
7723 process the insns we generate here and so we must ensure that
7724 they will fit their constraints and also by the fact that parts of
7725 IN might be being reloaded separately and replaced with spill registers.
7726 Because of this, we are, in some sense, just guessing the right approach
7727 here. The one listed above seems to work.
7729 ??? At some point, this whole thing needs to be rethought. */
7731 if (GET_CODE (in) == PLUS
7732 && (REG_P (XEXP (in, 0))
7733 || GET_CODE (XEXP (in, 0)) == SUBREG
7734 || MEM_P (XEXP (in, 0)))
7735 && (REG_P (XEXP (in, 1))
7736 || GET_CODE (XEXP (in, 1)) == SUBREG
7737 || CONSTANT_P (XEXP (in, 1))
7738 || MEM_P (XEXP (in, 1))))
7740 /* We need to compute the sum of a register or a MEM and another
7741 register, constant, or MEM, and put it into the reload
7742 register. The best possible way of doing this is if the machine
7743 has a three-operand ADD insn that accepts the required operands.
7745 The simplest approach is to try to generate such an insn and see if it
7746 is recognized and matches its constraints. If so, it can be used.
7748 It might be better not to actually emit the insn unless it is valid,
7749 but we need to pass the insn as an operand to `recog' and
7750 `extract_insn' and it is simpler to emit and then delete the insn if
7751 not valid than to dummy things up. */
7753 rtx op0, op1, tem, insn;
7756 op0 = find_replacement (&XEXP (in, 0));
7757 op1 = find_replacement (&XEXP (in, 1));
7759 /* Since constraint checking is strict, commutativity won't be
7760 checked, so we need to do that here to avoid spurious failure
7761 if the add instruction is two-address and the second operand
7762 of the add is the same as the reload reg, which is frequently
7763 the case. If the insn would be A = B + A, rearrange it so
7764 it will be A = A + B as constrain_operands expects. */
7766 if (REG_P (XEXP (in, 1))
7767 && REGNO (out) == REGNO (XEXP (in, 1)))
7768 tem = op0, op0 = op1, op1 = tem;
7770 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7771 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7773 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7777 /* If that failed, we must use a conservative two-insn sequence.
7779 Use a move to copy one operand into the reload register. Prefer
7780 to reload a constant, MEM or pseudo since the move patterns can
7781 handle an arbitrary operand. If OP1 is not a constant, MEM or
7782 pseudo and OP1 is not a valid operand for an add instruction, then
7785 After reloading one of the operands into the reload register, add
7786 the reload register to the output register.
7788 If there is another way to do this for a specific machine, a
7789 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7792 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7794 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7796 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7797 || (code != CODE_FOR_nothing
7798 && ! ((*insn_data[code].operand[2].predicate)
7799 (op1, insn_data[code].operand[2].mode))))
7800 tem = op0, op0 = op1, op1 = tem;
7802 gen_reload (out, op0, opnum, type);
7804 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7805 This fixes a problem on the 32K where the stack pointer cannot
7806 be used as an operand of an add insn. */
7808 if (rtx_equal_p (op0, op1))
7811 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
7814 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7816 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7820 /* If that failed, copy the address register to the reload register.
7821 Then add the constant to the reload register. */
7823 gen_reload (out, op1, opnum, type);
7824 insn = emit_insn (gen_add2_insn (out, op0));
7825 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7828 #ifdef SECONDARY_MEMORY_NEEDED
7829 /* If we need a memory location to do the move, do it that way. */
7830 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7831 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7832 && (REG_P (out) || GET_CODE (out) == SUBREG)
7833 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7834 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7835 REGNO_REG_CLASS (reg_or_subregno (out)),
7838 /* Get the memory to use and rewrite both registers to its mode. */
7839 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7841 if (GET_MODE (loc) != GET_MODE (out))
7842 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7844 if (GET_MODE (loc) != GET_MODE (in))
7845 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7847 gen_reload (loc, in, opnum, type);
7848 gen_reload (out, loc, opnum, type);
7851 else if (REG_P (out) && UNARY_P (in))
7858 op1 = find_replacement (&XEXP (in, 0));
7859 if (op1 != XEXP (in, 0))
7860 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
7862 /* First, try a plain SET. */
7863 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7867 /* If that failed, move the inner operand to the reload
7868 register, and try the same unop with the inner expression
7869 replaced with the reload register. */
7871 if (GET_MODE (op1) != GET_MODE (out))
7872 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
7876 gen_reload (out_moded, op1, opnum, type);
7879 = gen_rtx_SET (VOIDmode, out,
7880 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
7882 insn = emit_insn_if_valid_for_reload (insn);
7886 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7890 fatal_insn ("Failure trying to reload:", set);
7892 /* If IN is a simple operand, use gen_move_insn. */
7893 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
7895 tem = emit_insn (gen_move_insn (out, in));
7896 /* IN may contain a LABEL_REF, if so add a REG_LABEL note. */
7897 mark_jump_label (in, tem, 0);
7900 #ifdef HAVE_reload_load_address
7901 else if (HAVE_reload_load_address)
7902 emit_insn (gen_reload_load_address (out, in));
7905 /* Otherwise, just write (set OUT IN) and hope for the best. */
7907 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7909 /* Return the first insn emitted.
7910 We can not just return get_last_insn, because there may have
7911 been multiple instructions emitted. Also note that gen_move_insn may
7912 emit more than one insn itself, so we can not assume that there is one
7913 insn emitted per emit_insn_before call. */
7915 return last ? NEXT_INSN (last) : get_insns ();
7918 /* Delete a previously made output-reload whose result we now believe
7919 is not needed. First we double-check.
7921 INSN is the insn now being processed.
7922 LAST_RELOAD_REG is the hard register number for which we want to delete
7923 the last output reload.
7924 J is the reload-number that originally used REG. The caller has made
7925 certain that reload J doesn't use REG any longer for input. */
7928 delete_output_reload (rtx insn, int j, int last_reload_reg)
7930 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7931 rtx reg = spill_reg_stored_to[last_reload_reg];
7934 int n_inherited = 0;
7938 /* It is possible that this reload has been only used to set another reload
7939 we eliminated earlier and thus deleted this instruction too. */
7940 if (INSN_DELETED_P (output_reload_insn))
7943 /* Get the raw pseudo-register referred to. */
7945 while (GET_CODE (reg) == SUBREG)
7946 reg = SUBREG_REG (reg);
7947 substed = reg_equiv_memory_loc[REGNO (reg)];
7949 /* This is unsafe if the operand occurs more often in the current
7950 insn than it is inherited. */
7951 for (k = n_reloads - 1; k >= 0; k--)
7953 rtx reg2 = rld[k].in;
7956 if (MEM_P (reg2) || reload_override_in[k])
7957 reg2 = rld[k].in_reg;
7959 if (rld[k].out && ! rld[k].out_reg)
7960 reg2 = XEXP (rld[k].in_reg, 0);
7962 while (GET_CODE (reg2) == SUBREG)
7963 reg2 = SUBREG_REG (reg2);
7964 if (rtx_equal_p (reg2, reg))
7966 if (reload_inherited[k] || reload_override_in[k] || k == j)
7969 reg2 = rld[k].out_reg;
7972 while (GET_CODE (reg2) == SUBREG)
7973 reg2 = XEXP (reg2, 0);
7974 if (rtx_equal_p (reg2, reg))
7981 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7982 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
7983 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
7986 n_occurrences += count_occurrences (PATTERN (insn),
7987 eliminate_regs (substed, 0,
7989 for (i1 = reg_equiv_alt_mem_list [REGNO (reg)]; i1; i1 = XEXP (i1, 1))
7991 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
7992 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
7994 if (n_occurrences > n_inherited)
7997 /* If the pseudo-reg we are reloading is no longer referenced
7998 anywhere between the store into it and here,
7999 and we're within the same basic block, then the value can only
8000 pass through the reload reg and end up here.
8001 Otherwise, give up--return. */
8002 for (i1 = NEXT_INSN (output_reload_insn);
8003 i1 != insn; i1 = NEXT_INSN (i1))
8005 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8007 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8008 && reg_mentioned_p (reg, PATTERN (i1)))
8010 /* If this is USE in front of INSN, we only have to check that
8011 there are no more references than accounted for by inheritance. */
8012 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8014 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8015 i1 = NEXT_INSN (i1);
8017 if (n_occurrences <= n_inherited && i1 == insn)
8023 /* We will be deleting the insn. Remove the spill reg information. */
8024 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8026 spill_reg_store[last_reload_reg + k] = 0;
8027 spill_reg_stored_to[last_reload_reg + k] = 0;
8030 /* The caller has already checked that REG dies or is set in INSN.
8031 It has also checked that we are optimizing, and thus some
8032 inaccuracies in the debugging information are acceptable.
8033 So we could just delete output_reload_insn. But in some cases
8034 we can improve the debugging information without sacrificing
8035 optimization - maybe even improving the code: See if the pseudo
8036 reg has been completely replaced with reload regs. If so, delete
8037 the store insn and forget we had a stack slot for the pseudo. */
8038 if (rld[j].out != rld[j].in
8039 && REG_N_DEATHS (REGNO (reg)) == 1
8040 && REG_N_SETS (REGNO (reg)) == 1
8041 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
8042 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8046 /* We know that it was used only between here and the beginning of
8047 the current basic block. (We also know that the last use before
8048 INSN was the output reload we are thinking of deleting, but never
8049 mind that.) Search that range; see if any ref remains. */
8050 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8052 rtx set = single_set (i2);
8054 /* Uses which just store in the pseudo don't count,
8055 since if they are the only uses, they are dead. */
8056 if (set != 0 && SET_DEST (set) == reg)
8061 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8062 && reg_mentioned_p (reg, PATTERN (i2)))
8064 /* Some other ref remains; just delete the output reload we
8066 delete_address_reloads (output_reload_insn, insn);
8067 delete_insn (output_reload_insn);
8072 /* Delete the now-dead stores into this pseudo. Note that this
8073 loop also takes care of deleting output_reload_insn. */
8074 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8076 rtx set = single_set (i2);
8078 if (set != 0 && SET_DEST (set) == reg)
8080 delete_address_reloads (i2, insn);
8088 /* For the debugging info, say the pseudo lives in this reload reg. */
8089 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
8090 alter_reg (REGNO (reg), -1);
8094 delete_address_reloads (output_reload_insn, insn);
8095 delete_insn (output_reload_insn);
8099 /* We are going to delete DEAD_INSN. Recursively delete loads of
8100 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8101 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8103 delete_address_reloads (rtx dead_insn, rtx current_insn)
8105 rtx set = single_set (dead_insn);
8106 rtx set2, dst, prev, next;
8109 rtx dst = SET_DEST (set);
8111 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8113 /* If we deleted the store from a reloaded post_{in,de}c expression,
8114 we can delete the matching adds. */
8115 prev = PREV_INSN (dead_insn);
8116 next = NEXT_INSN (dead_insn);
8117 if (! prev || ! next)
8119 set = single_set (next);
8120 set2 = single_set (prev);
8122 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8123 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8124 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8126 dst = SET_DEST (set);
8127 if (! rtx_equal_p (dst, SET_DEST (set2))
8128 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8129 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8130 || (INTVAL (XEXP (SET_SRC (set), 1))
8131 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8133 delete_related_insns (prev);
8134 delete_related_insns (next);
8137 /* Subfunction of delete_address_reloads: process registers found in X. */
8139 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8141 rtx prev, set, dst, i2;
8143 enum rtx_code code = GET_CODE (x);
8147 const char *fmt = GET_RTX_FORMAT (code);
8148 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8151 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8152 else if (fmt[i] == 'E')
8154 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8155 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8162 if (spill_reg_order[REGNO (x)] < 0)
8165 /* Scan backwards for the insn that sets x. This might be a way back due
8167 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8169 code = GET_CODE (prev);
8170 if (code == CODE_LABEL || code == JUMP_INSN)
8174 if (reg_set_p (x, PATTERN (prev)))
8176 if (reg_referenced_p (x, PATTERN (prev)))
8179 if (! prev || INSN_UID (prev) < reload_first_uid)
8181 /* Check that PREV only sets the reload register. */
8182 set = single_set (prev);
8185 dst = SET_DEST (set);
8187 || ! rtx_equal_p (dst, x))
8189 if (! reg_set_p (dst, PATTERN (dead_insn)))
8191 /* Check if DST was used in a later insn -
8192 it might have been inherited. */
8193 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8199 if (reg_referenced_p (dst, PATTERN (i2)))
8201 /* If there is a reference to the register in the current insn,
8202 it might be loaded in a non-inherited reload. If no other
8203 reload uses it, that means the register is set before
8205 if (i2 == current_insn)
8207 for (j = n_reloads - 1; j >= 0; j--)
8208 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8209 || reload_override_in[j] == dst)
8211 for (j = n_reloads - 1; j >= 0; j--)
8212 if (rld[j].in && rld[j].reg_rtx == dst)
8221 /* If DST is still live at CURRENT_INSN, check if it is used for
8222 any reload. Note that even if CURRENT_INSN sets DST, we still
8223 have to check the reloads. */
8224 if (i2 == current_insn)
8226 for (j = n_reloads - 1; j >= 0; j--)
8227 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8228 || reload_override_in[j] == dst)
8230 /* ??? We can't finish the loop here, because dst might be
8231 allocated to a pseudo in this block if no reload in this
8232 block needs any of the classes containing DST - see
8233 spill_hard_reg. There is no easy way to tell this, so we
8234 have to scan till the end of the basic block. */
8236 if (reg_set_p (dst, PATTERN (i2)))
8240 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8241 reg_reloaded_contents[REGNO (dst)] = -1;
8245 /* Output reload-insns to reload VALUE into RELOADREG.
8246 VALUE is an autoincrement or autodecrement RTX whose operand
8247 is a register or memory location;
8248 so reloading involves incrementing that location.
8249 IN is either identical to VALUE, or some cheaper place to reload from.
8251 INC_AMOUNT is the number to increment or decrement by (always positive).
8252 This cannot be deduced from VALUE.
8254 Return the instruction that stores into RELOADREG. */
8257 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8259 /* REG or MEM to be copied and incremented. */
8260 rtx incloc = find_replacement (&XEXP (value, 0));
8261 /* Nonzero if increment after copying. */
8262 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8263 || GET_CODE (value) == POST_MODIFY);
8269 rtx real_in = in == value ? incloc : in;
8271 /* No hard register is equivalent to this register after
8272 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8273 we could inc/dec that register as well (maybe even using it for
8274 the source), but I'm not sure it's worth worrying about. */
8276 reg_last_reload_reg[REGNO (incloc)] = 0;
8278 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8280 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8281 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8285 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8286 inc_amount = -inc_amount;
8288 inc = GEN_INT (inc_amount);
8291 /* If this is post-increment, first copy the location to the reload reg. */
8292 if (post && real_in != reloadreg)
8293 emit_insn (gen_move_insn (reloadreg, real_in));
8297 /* See if we can directly increment INCLOC. Use a method similar to
8298 that in gen_reload. */
8300 last = get_last_insn ();
8301 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8302 gen_rtx_PLUS (GET_MODE (incloc),
8305 code = recog_memoized (add_insn);
8308 extract_insn (add_insn);
8309 if (constrain_operands (1))
8311 /* If this is a pre-increment and we have incremented the value
8312 where it lives, copy the incremented value to RELOADREG to
8313 be used as an address. */
8316 emit_insn (gen_move_insn (reloadreg, incloc));
8321 delete_insns_since (last);
8324 /* If couldn't do the increment directly, must increment in RELOADREG.
8325 The way we do this depends on whether this is pre- or post-increment.
8326 For pre-increment, copy INCLOC to the reload register, increment it
8327 there, then save back. */
8331 if (in != reloadreg)
8332 emit_insn (gen_move_insn (reloadreg, real_in));
8333 emit_insn (gen_add2_insn (reloadreg, inc));
8334 store = emit_insn (gen_move_insn (incloc, reloadreg));
8339 Because this might be a jump insn or a compare, and because RELOADREG
8340 may not be available after the insn in an input reload, we must do
8341 the incrementation before the insn being reloaded for.
8343 We have already copied IN to RELOADREG. Increment the copy in
8344 RELOADREG, save that back, then decrement RELOADREG so it has
8345 the original value. */
8347 emit_insn (gen_add2_insn (reloadreg, inc));
8348 store = emit_insn (gen_move_insn (incloc, reloadreg));
8349 if (GET_CODE (inc) == CONST_INT)
8350 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
8352 emit_insn (gen_sub2_insn (reloadreg, inc));
8360 add_auto_inc_notes (rtx insn, rtx x)
8362 enum rtx_code code = GET_CODE (x);
8366 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8369 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8373 /* Scan all the operand sub-expressions. */
8374 fmt = GET_RTX_FORMAT (code);
8375 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8378 add_auto_inc_notes (insn, XEXP (x, i));
8379 else if (fmt[i] == 'E')
8380 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8381 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8386 /* Copy EH notes from an insn to its reloads. */
8388 copy_eh_notes (rtx insn, rtx x)
8390 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8393 for (; x != 0; x = NEXT_INSN (x))
8395 if (may_trap_p (PATTERN (x)))
8397 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8403 /* This is used by reload pass, that does emit some instructions after
8404 abnormal calls moving basic block end, but in fact it wants to emit
8405 them on the edge. Looks for abnormal call edges, find backward the
8406 proper call and fix the damage.
8408 Similar handle instructions throwing exceptions internally. */
8410 fixup_abnormal_edges (void)
8412 bool inserted = false;
8420 /* Look for cases we are interested in - calls or instructions causing
8422 FOR_EACH_EDGE (e, ei, bb->succs)
8424 if (e->flags & EDGE_ABNORMAL_CALL)
8426 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8427 == (EDGE_ABNORMAL | EDGE_EH))
8430 if (e && !CALL_P (BB_END (bb))
8431 && !can_throw_internal (BB_END (bb)))
8435 /* Get past the new insns generated. Allow notes, as the insns
8436 may be already deleted. */
8438 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8439 && !can_throw_internal (insn)
8440 && insn != BB_HEAD (bb))
8441 insn = PREV_INSN (insn);
8443 if (CALL_P (insn) || can_throw_internal (insn))
8447 stop = NEXT_INSN (BB_END (bb));
8449 insn = NEXT_INSN (insn);
8451 FOR_EACH_EDGE (e, ei, bb->succs)
8452 if (e->flags & EDGE_FALLTHRU)
8455 while (insn && insn != stop)
8457 next = NEXT_INSN (insn);
8462 /* Sometimes there's still the return value USE.
8463 If it's placed after a trapping call (i.e. that
8464 call is the last insn anyway), we have no fallthru
8465 edge. Simply delete this use and don't try to insert
8466 on the non-existent edge. */
8467 if (GET_CODE (PATTERN (insn)) != USE)
8469 /* We're not deleting it, we're moving it. */
8470 INSN_DELETED_P (insn) = 0;
8471 PREV_INSN (insn) = NULL_RTX;
8472 NEXT_INSN (insn) = NULL_RTX;
8474 insert_insn_on_edge (insn, e);
8482 /* It may be that we don't find any such trapping insn. In this
8483 case we discovered quite late that the insn that had been
8484 marked as can_throw_internal in fact couldn't trap at all.
8485 So we should in fact delete the EH edges out of the block. */
8487 purge_dead_edges (bb);
8491 /* We've possibly turned single trapping insn into multiple ones. */
8492 if (flag_non_call_exceptions)
8495 blocks = sbitmap_alloc (last_basic_block);
8496 sbitmap_ones (blocks);
8497 find_many_sub_basic_blocks (blocks);
8501 commit_edge_insertions ();
8503 #ifdef ENABLE_CHECKING
8504 /* Verify that we didn't turn one trapping insn into many, and that
8505 we found and corrected all of the problems wrt fixups on the
8507 verify_flow_info ();
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