1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 88, 89, 92-97, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "insn-flags.h"
31 #include "insn-codes.h"
35 #include "basic-block.h"
42 /* This file contains the reload pass of the compiler, which is
43 run after register allocation has been done. It checks that
44 each insn is valid (operands required to be in registers really
45 are in registers of the proper class) and fixes up invalid ones
46 by copying values temporarily into registers for the insns
49 The results of register allocation are described by the vector
50 reg_renumber; the insns still contain pseudo regs, but reg_renumber
51 can be used to find which hard reg, if any, a pseudo reg is in.
53 The technique we always use is to free up a few hard regs that are
54 called ``reload regs'', and for each place where a pseudo reg
55 must be in a hard reg, copy it temporarily into one of the reload regs.
57 Reload regs are allocated locally for every instruction that needs
58 reloads. When there are pseudos which are allocated to a register that
59 has been chosen as a reload reg, such pseudos must be ``spilled''.
60 This means that they go to other hard regs, or to stack slots if no other
61 available hard regs can be found. Spilling can invalidate more
62 insns, requiring additional need for reloads, so we must keep checking
63 until the process stabilizes.
65 For machines with different classes of registers, we must keep track
66 of the register class needed for each reload, and make sure that
67 we allocate enough reload registers of each class.
69 The file reload.c contains the code that checks one insn for
70 validity and reports the reloads that it needs. This file
71 is in charge of scanning the entire rtl code, accumulating the
72 reload needs, spilling, assigning reload registers to use for
73 fixing up each insn, and generating the new insns to copy values
74 into the reload registers. */
77 #ifndef REGISTER_MOVE_COST
78 #define REGISTER_MOVE_COST(x, y) 2
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
106 This is used when the address is not valid as a memory address
107 (because its displacement is too big for the machine.) */
108 rtx *reg_equiv_address;
110 /* Element N is the memory slot to which pseudo reg N is equivalent,
111 or zero if pseudo reg N is not equivalent to a memory slot. */
114 /* Widest width in which each pseudo reg is referred to (via subreg). */
115 static int *reg_max_ref_width;
117 /* Element N is the list of insns that initialized reg N from its equivalent
118 constant or memory slot. */
119 static rtx *reg_equiv_init;
121 /* Vector to remember old contents of reg_renumber before spilling. */
122 static short *reg_old_renumber;
124 /* During reload_as_needed, element N contains the last pseudo regno reloaded
125 into hard register N. If that pseudo reg occupied more than one register,
126 reg_reloaded_contents points to that pseudo for each spill register in
127 use; all of these must remain set for an inheritance to occur. */
128 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
130 /* During reload_as_needed, element N contains the insn for which
131 hard register N was last used. Its contents are significant only
132 when reg_reloaded_valid is set for this register. */
133 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
135 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
136 static HARD_REG_SET reg_reloaded_valid;
137 /* Indicate if the register was dead at the end of the reload.
138 This is only valid if reg_reloaded_contents is set and valid. */
139 static HARD_REG_SET reg_reloaded_dead;
141 /* Number of spill-regs so far; number of valid elements of spill_regs. */
144 /* In parallel with spill_regs, contains REG rtx's for those regs.
145 Holds the last rtx used for any given reg, or 0 if it has never
146 been used for spilling yet. This rtx is reused, provided it has
148 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
150 /* In parallel with spill_regs, contains nonzero for a spill reg
151 that was stored after the last time it was used.
152 The precise value is the insn generated to do the store. */
153 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
155 /* This is the register that was stored with spill_reg_store. This is a
156 copy of reload_out / reload_out_reg when the value was stored; if
157 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
158 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
160 /* This table is the inverse mapping of spill_regs:
161 indexed by hard reg number,
162 it contains the position of that reg in spill_regs,
163 or -1 for something that is not in spill_regs.
165 ?!? This is no longer accurate. */
166 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
168 /* This reg set indicates registers that can't be used as spill registers for
169 the currently processed insn. These are the hard registers which are live
170 during the insn, but not allocated to pseudos, as well as fixed
172 static HARD_REG_SET bad_spill_regs;
174 /* These are the hard registers that can't be used as spill register for any
175 insn. This includes registers used for user variables and registers that
176 we can't eliminate. A register that appears in this set also can't be used
177 to retry register allocation. */
178 static HARD_REG_SET bad_spill_regs_global;
180 /* Describes order of use of registers for reloading
181 of spilled pseudo-registers. `n_spills' is the number of
182 elements that are actually valid; new ones are added at the end.
184 Both spill_regs and spill_reg_order are used on two occasions:
185 once during find_reload_regs, where they keep track of the spill registers
186 for a single insn, but also during reload_as_needed where they show all
187 the registers ever used by reload. For the latter case, the information
188 is calculated during finish_spills. */
189 static short spill_regs[FIRST_PSEUDO_REGISTER];
191 /* This vector of reg sets indicates, for each pseudo, which hard registers
192 may not be used for retrying global allocation because the register was
193 formerly spilled from one of them. If we allowed reallocating a pseudo to
194 a register that it was already allocated to, reload might not
196 static HARD_REG_SET *pseudo_previous_regs;
198 /* This vector of reg sets indicates, for each pseudo, which hard
199 registers may not be used for retrying global allocation because they
200 are used as spill registers during one of the insns in which the
202 static HARD_REG_SET *pseudo_forbidden_regs;
204 /* All hard regs that have been used as spill registers for any insn are
205 marked in this set. */
206 static HARD_REG_SET used_spill_regs;
208 /* Index of last register assigned as a spill register. We allocate in
209 a round-robin fashion. */
210 static int last_spill_reg;
212 /* Describes order of preference for putting regs into spill_regs.
213 Contains the numbers of all the hard regs, in order most preferred first.
214 This order is different for each function.
215 It is set up by order_regs_for_reload.
216 Empty elements at the end contain -1. */
217 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
219 /* Nonzero if indirect addressing is supported on the machine; this means
220 that spilling (REG n) does not require reloading it into a register in
221 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
222 value indicates the level of indirect addressing supported, e.g., two
223 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
225 static char spill_indirect_levels;
227 /* Nonzero if indirect addressing is supported when the innermost MEM is
228 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
229 which these are valid is the same as spill_indirect_levels, above. */
230 char indirect_symref_ok;
232 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
233 char double_reg_address_ok;
235 /* Record the stack slot for each spilled hard register. */
236 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
238 /* Width allocated so far for that stack slot. */
239 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
241 /* Record which pseudos needed to be spilled. */
242 static regset spilled_pseudos;
244 /* First uid used by insns created by reload in this function.
245 Used in find_equiv_reg. */
246 int reload_first_uid;
248 /* Flag set by local-alloc or global-alloc if anything is live in
249 a call-clobbered reg across calls. */
250 int caller_save_needed;
252 /* Set to 1 while reload_as_needed is operating.
253 Required by some machines to handle any generated moves differently. */
254 int reload_in_progress = 0;
256 /* These arrays record the insn_code of insns that may be needed to
257 perform input and output reloads of special objects. They provide a
258 place to pass a scratch register. */
259 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
260 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
262 /* This obstack is used for allocation of rtl during register elimination.
263 The allocated storage can be freed once find_reloads has processed the
265 struct obstack reload_obstack;
267 /* Points to the beginning of the reload_obstack. All insn_chain structures
268 are allocated first. */
269 char *reload_startobj;
271 /* The point after all insn_chain structures. Used to quickly deallocate
272 memory used while processing one insn. */
273 char *reload_firstobj;
275 #define obstack_chunk_alloc xmalloc
276 #define obstack_chunk_free free
278 /* List of labels that must never be deleted. */
279 extern rtx forced_labels;
281 /* List of insn_chain instructions, one for every insn that reload needs to
283 struct insn_chain *reload_insn_chain;
285 /* List of all insns needing reloads. */
286 static struct insn_chain *insns_need_reload;
288 /* This structure is used to record information about register eliminations.
289 Each array entry describes one possible way of eliminating a register
290 in favor of another. If there is more than one way of eliminating a
291 particular register, the most preferred should be specified first. */
295 int from; /* Register number to be eliminated. */
296 int to; /* Register number used as replacement. */
297 int initial_offset; /* Initial difference between values. */
298 int can_eliminate; /* Non-zero if this elimination can be done. */
299 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
300 insns made by reload. */
301 int offset; /* Current offset between the two regs. */
302 int previous_offset; /* Offset at end of previous insn. */
303 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
304 rtx from_rtx; /* REG rtx for the register to be eliminated.
305 We cannot simply compare the number since
306 we might then spuriously replace a hard
307 register corresponding to a pseudo
308 assigned to the reg to be eliminated. */
309 rtx to_rtx; /* REG rtx for the replacement. */
312 static struct elim_table * reg_eliminate = 0;
314 /* This is an intermediate structure to initialize the table. It has
315 exactly the members provided by ELIMINABLE_REGS. */
316 static struct elim_table_1
320 } reg_eliminate_1[] =
322 /* If a set of eliminable registers was specified, define the table from it.
323 Otherwise, default to the normal case of the frame pointer being
324 replaced by the stack pointer. */
326 #ifdef ELIMINABLE_REGS
329 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
332 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate_1/sizeof reg_eliminate_1[0])
334 /* Record the number of pending eliminations that have an offset not equal
335 to their initial offset. If non-zero, we use a new copy of each
336 replacement result in any insns encountered. */
337 int num_not_at_initial_offset;
339 /* Count the number of registers that we may be able to eliminate. */
340 static int num_eliminable;
342 /* For each label, we record the offset of each elimination. If we reach
343 a label by more than one path and an offset differs, we cannot do the
344 elimination. This information is indexed by the number of the label.
345 The first table is an array of flags that records whether we have yet
346 encountered a label and the second table is an array of arrays, one
347 entry in the latter array for each elimination. */
349 static char *offsets_known_at;
350 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
352 /* Number of labels in the current function. */
354 static int num_labels;
356 struct hard_reg_n_uses
362 static void maybe_fix_stack_asms PROTO((void));
363 static void calculate_needs_all_insns PROTO((int));
364 static void calculate_needs PROTO((struct insn_chain *));
365 static void find_reload_regs PROTO((struct insn_chain *chain,
367 static void find_tworeg_group PROTO((struct insn_chain *, int,
369 static void find_group PROTO((struct insn_chain *, int,
371 static int possible_group_p PROTO((struct insn_chain *, int));
372 static void count_possible_groups PROTO((struct insn_chain *, int));
373 static int modes_equiv_for_class_p PROTO((enum machine_mode,
376 static void delete_caller_save_insns PROTO((void));
378 static void spill_failure PROTO((rtx));
379 static void new_spill_reg PROTO((struct insn_chain *, int, int,
381 static void maybe_mark_pseudo_spilled PROTO((int));
382 static void delete_dead_insn PROTO((rtx));
383 static void alter_reg PROTO((int, int));
384 static void set_label_offsets PROTO((rtx, rtx, int));
385 static int eliminate_regs_in_insn PROTO((rtx, int));
386 static void update_eliminable_offsets PROTO((void));
387 static void mark_not_eliminable PROTO((rtx, rtx));
388 static void set_initial_elim_offsets PROTO((void));
389 static void verify_initial_elim_offsets PROTO((void));
390 static void set_initial_label_offsets PROTO((void));
391 static void set_offsets_for_label PROTO((rtx));
392 static void init_elim_table PROTO((void));
393 static void update_eliminables PROTO((HARD_REG_SET *));
394 static void spill_hard_reg PROTO((int, FILE *, int));
395 static int finish_spills PROTO((int, FILE *));
396 static void ior_hard_reg_set PROTO((HARD_REG_SET *, HARD_REG_SET *));
397 static void scan_paradoxical_subregs PROTO((rtx));
398 static int hard_reg_use_compare PROTO((const GENERIC_PTR, const GENERIC_PTR));
399 static void count_pseudo PROTO((struct hard_reg_n_uses *, int));
400 static void order_regs_for_reload PROTO((struct insn_chain *));
401 static void reload_as_needed PROTO((int));
402 static void forget_old_reloads_1 PROTO((rtx, rtx));
403 static int reload_reg_class_lower PROTO((const GENERIC_PTR, const GENERIC_PTR));
404 static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
406 static void clear_reload_reg_in_use PROTO((int, int, enum reload_type,
408 static int reload_reg_free_p PROTO((int, int, enum reload_type));
409 static int reload_reg_free_for_value_p PROTO((int, int, enum reload_type, rtx, rtx, int, int));
410 static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
411 static int allocate_reload_reg PROTO((struct insn_chain *, int, int,
413 static void choose_reload_regs PROTO((struct insn_chain *));
414 static void merge_assigned_reloads PROTO((rtx));
415 static void emit_reload_insns PROTO((struct insn_chain *));
416 static void delete_output_reload PROTO((rtx, int, int));
417 static void delete_address_reloads PROTO((rtx, rtx));
418 static void delete_address_reloads_1 PROTO((rtx, rtx, rtx));
419 static rtx inc_for_reload PROTO((rtx, rtx, rtx, int));
420 static int constraint_accepts_reg_p PROTO((char *, rtx));
421 static void reload_cse_regs_1 PROTO((rtx));
422 static void reload_cse_invalidate_regno PROTO((int, enum machine_mode, int));
423 static int reload_cse_mem_conflict_p PROTO((rtx, rtx));
424 static void reload_cse_invalidate_mem PROTO((rtx));
425 static void reload_cse_invalidate_rtx PROTO((rtx, rtx));
426 static int reload_cse_regno_equal_p PROTO((int, rtx, enum machine_mode));
427 static int reload_cse_noop_set_p PROTO((rtx, rtx));
428 static int reload_cse_simplify_set PROTO((rtx, rtx));
429 static int reload_cse_simplify_operands PROTO((rtx));
430 static void reload_cse_check_clobber PROTO((rtx, rtx));
431 static void reload_cse_record_set PROTO((rtx, rtx));
432 static void reload_combine PROTO((void));
433 static void reload_combine_note_use PROTO((rtx *, rtx));
434 static void reload_combine_note_store PROTO((rtx, rtx));
435 static void reload_cse_move2add PROTO((rtx));
436 static void move2add_note_store PROTO((rtx, rtx));
438 /* Initialize the reload pass once per compilation. */
445 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
446 Set spill_indirect_levels to the number of levels such addressing is
447 permitted, zero if it is not permitted at all. */
450 = gen_rtx_MEM (Pmode,
452 gen_rtx_REG (Pmode, LAST_VIRTUAL_REGISTER + 1),
454 spill_indirect_levels = 0;
456 while (memory_address_p (QImode, tem))
458 spill_indirect_levels++;
459 tem = gen_rtx_MEM (Pmode, tem);
462 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
464 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
465 indirect_symref_ok = memory_address_p (QImode, tem);
467 /* See if reg+reg is a valid (and offsettable) address. */
469 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
471 tem = gen_rtx_PLUS (Pmode,
472 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
473 gen_rtx_REG (Pmode, i));
474 /* This way, we make sure that reg+reg is an offsettable address. */
475 tem = plus_constant (tem, 4);
477 if (memory_address_p (QImode, tem))
479 double_reg_address_ok = 1;
484 /* Initialize obstack for our rtl allocation. */
485 gcc_obstack_init (&reload_obstack);
486 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
489 /* List of insn chains that are currently unused. */
490 static struct insn_chain *unused_insn_chains = 0;
492 /* Allocate an empty insn_chain structure. */
496 struct insn_chain *c;
498 if (unused_insn_chains == 0)
500 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
501 c->live_before = OBSTACK_ALLOC_REG_SET (&reload_obstack);
502 c->live_after = OBSTACK_ALLOC_REG_SET (&reload_obstack);
506 c = unused_insn_chains;
507 unused_insn_chains = c->next;
509 c->is_caller_save_insn = 0;
510 c->need_operand_change = 0;
516 /* Small utility function to set all regs in hard reg set TO which are
517 allocated to pseudos in regset FROM. */
519 compute_use_by_pseudos (to, from)
524 EXECUTE_IF_SET_IN_REG_SET
525 (from, FIRST_PSEUDO_REGISTER, regno,
527 int r = reg_renumber[regno];
531 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
533 SET_HARD_REG_BIT (*to, r + nregs);
537 /* Global variables used by reload and its subroutines. */
539 /* Set during calculate_needs if an insn needs register elimination. */
540 static int something_needs_elimination;
541 /* Set during calculate_needs if an insn needs an operand changed. */
542 int something_needs_operands_changed;
544 /* Nonzero means we couldn't get enough spill regs. */
547 /* Main entry point for the reload pass.
549 FIRST is the first insn of the function being compiled.
551 GLOBAL nonzero means we were called from global_alloc
552 and should attempt to reallocate any pseudoregs that we
553 displace from hard regs we will use for reloads.
554 If GLOBAL is zero, we do not have enough information to do that,
555 so any pseudo reg that is spilled must go to the stack.
557 DUMPFILE is the global-reg debugging dump file stream, or 0.
558 If it is nonzero, messages are written to it to describe
559 which registers are seized as reload regs, which pseudo regs
560 are spilled from them, and where the pseudo regs are reallocated to.
562 Return value is nonzero if reload failed
563 and we must not do any more for this function. */
566 reload (first, global, dumpfile)
573 register struct elim_table *ep;
575 /* The two pointers used to track the true location of the memory used
576 for label offsets. */
577 char *real_known_ptr = NULL_PTR;
578 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
580 /* Make sure even insns with volatile mem refs are recognizable. */
585 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
587 /* Make sure that the last insn in the chain
588 is not something that needs reloading. */
589 emit_note (NULL_PTR, NOTE_INSN_DELETED);
591 /* Enable find_equiv_reg to distinguish insns made by reload. */
592 reload_first_uid = get_max_uid ();
594 #ifdef SECONDARY_MEMORY_NEEDED
595 /* Initialize the secondary memory table. */
596 clear_secondary_mem ();
599 /* We don't have a stack slot for any spill reg yet. */
600 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
601 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
603 /* Initialize the save area information for caller-save, in case some
607 /* Compute which hard registers are now in use
608 as homes for pseudo registers.
609 This is done here rather than (eg) in global_alloc
610 because this point is reached even if not optimizing. */
611 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
614 /* A function that receives a nonlocal goto must save all call-saved
616 if (current_function_has_nonlocal_label)
617 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
619 if (! call_used_regs[i] && ! fixed_regs[i])
620 regs_ever_live[i] = 1;
623 /* Find all the pseudo registers that didn't get hard regs
624 but do have known equivalent constants or memory slots.
625 These include parameters (known equivalent to parameter slots)
626 and cse'd or loop-moved constant memory addresses.
628 Record constant equivalents in reg_equiv_constant
629 so they will be substituted by find_reloads.
630 Record memory equivalents in reg_mem_equiv so they can
631 be substituted eventually by altering the REG-rtx's. */
633 reg_equiv_constant = (rtx *) xmalloc (max_regno * sizeof (rtx));
634 bzero ((char *) reg_equiv_constant, max_regno * sizeof (rtx));
635 reg_equiv_memory_loc = (rtx *) xmalloc (max_regno * sizeof (rtx));
636 bzero ((char *) reg_equiv_memory_loc, max_regno * sizeof (rtx));
637 reg_equiv_mem = (rtx *) xmalloc (max_regno * sizeof (rtx));
638 bzero ((char *) reg_equiv_mem, max_regno * sizeof (rtx));
639 reg_equiv_init = (rtx *) xmalloc (max_regno * sizeof (rtx));
640 bzero ((char *) reg_equiv_init, max_regno * sizeof (rtx));
641 reg_equiv_address = (rtx *) xmalloc (max_regno * sizeof (rtx));
642 bzero ((char *) reg_equiv_address, max_regno * sizeof (rtx));
643 reg_max_ref_width = (int *) xmalloc (max_regno * sizeof (int));
644 bzero ((char *) reg_max_ref_width, max_regno * sizeof (int));
645 reg_old_renumber = (short *) xmalloc (max_regno * sizeof (short));
646 bcopy (reg_renumber, reg_old_renumber, max_regno * sizeof (short));
647 pseudo_forbidden_regs
648 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
650 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
652 CLEAR_HARD_REG_SET (bad_spill_regs_global);
653 bzero ((char *) pseudo_previous_regs, max_regno * sizeof (HARD_REG_SET));
655 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
656 Also find all paradoxical subregs and find largest such for each pseudo.
657 On machines with small register classes, record hard registers that
658 are used for user variables. These can never be used for spills.
659 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
660 caller-saved registers must be marked live. */
662 for (insn = first; insn; insn = NEXT_INSN (insn))
664 rtx set = single_set (insn);
666 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
667 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
668 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
669 if (! call_used_regs[i])
670 regs_ever_live[i] = 1;
672 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
674 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
676 #ifdef LEGITIMATE_PIC_OPERAND_P
677 && (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic
678 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
682 rtx x = XEXP (note, 0);
683 i = REGNO (SET_DEST (set));
684 if (i > LAST_VIRTUAL_REGISTER)
686 if (GET_CODE (x) == MEM)
688 /* If the operand is a PLUS, the MEM may be shared,
689 so make sure we have an unshared copy here. */
690 if (GET_CODE (XEXP (x, 0)) == PLUS)
693 reg_equiv_memory_loc[i] = x;
695 else if (CONSTANT_P (x))
697 if (LEGITIMATE_CONSTANT_P (x))
698 reg_equiv_constant[i] = x;
700 reg_equiv_memory_loc[i]
701 = force_const_mem (GET_MODE (SET_DEST (set)), x);
706 /* If this register is being made equivalent to a MEM
707 and the MEM is not SET_SRC, the equivalencing insn
708 is one with the MEM as a SET_DEST and it occurs later.
709 So don't mark this insn now. */
710 if (GET_CODE (x) != MEM
711 || rtx_equal_p (SET_SRC (set), x))
713 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
718 /* If this insn is setting a MEM from a register equivalent to it,
719 this is the equivalencing insn. */
720 else if (set && GET_CODE (SET_DEST (set)) == MEM
721 && GET_CODE (SET_SRC (set)) == REG
722 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
723 && rtx_equal_p (SET_DEST (set),
724 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
725 reg_equiv_init[REGNO (SET_SRC (set))]
726 = gen_rtx_INSN_LIST (VOIDmode, insn,
727 reg_equiv_init[REGNO (SET_SRC (set))]);
729 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
730 scan_paradoxical_subregs (PATTERN (insn));
735 num_labels = max_label_num () - get_first_label_num ();
737 /* Allocate the tables used to store offset information at labels. */
738 /* We used to use alloca here, but the size of what it would try to
739 allocate would occasionally cause it to exceed the stack limit and
740 cause a core dump. */
741 real_known_ptr = xmalloc (num_labels);
743 = (int (*)[NUM_ELIMINABLE_REGS])
744 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
746 offsets_known_at = real_known_ptr - get_first_label_num ();
748 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
750 /* Alter each pseudo-reg rtx to contain its hard reg number.
751 Assign stack slots to the pseudos that lack hard regs or equivalents.
752 Do not touch virtual registers. */
754 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
757 /* If we have some registers we think can be eliminated, scan all insns to
758 see if there is an insn that sets one of these registers to something
759 other than itself plus a constant. If so, the register cannot be
760 eliminated. Doing this scan here eliminates an extra pass through the
761 main reload loop in the most common case where register elimination
763 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
764 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
765 || GET_CODE (insn) == CALL_INSN)
766 note_stores (PATTERN (insn), mark_not_eliminable);
768 #ifndef REGISTER_CONSTRAINTS
769 /* If all the pseudo regs have hard regs,
770 except for those that are never referenced,
771 we know that no reloads are needed. */
772 /* But that is not true if there are register constraints, since
773 in that case some pseudos might be in the wrong kind of hard reg. */
775 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
776 if (reg_renumber[i] == -1 && REG_N_REFS (i) != 0)
779 if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
781 free (real_known_ptr);
783 free (reg_equiv_constant);
784 free (reg_equiv_memory_loc);
785 free (reg_equiv_mem);
786 free (reg_equiv_init);
787 free (reg_equiv_address);
788 free (reg_max_ref_width);
789 free (reg_old_renumber);
790 free (pseudo_previous_regs);
791 free (pseudo_forbidden_regs);
796 maybe_fix_stack_asms ();
798 insns_need_reload = 0;
799 something_needs_elimination = 0;
801 /* Initialize to -1, which means take the first spill register. */
804 spilled_pseudos = ALLOCA_REG_SET ();
806 /* Spill any hard regs that we know we can't eliminate. */
807 CLEAR_HARD_REG_SET (used_spill_regs);
808 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
809 if (! ep->can_eliminate)
810 spill_hard_reg (ep->from, dumpfile, 1);
812 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
813 if (frame_pointer_needed)
814 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, dumpfile, 1);
816 finish_spills (global, dumpfile);
818 /* From now on, we may need to generate moves differently. We may also
819 allow modifications of insns which cause them to not be recognized.
820 Any such modifications will be cleaned up during reload itself. */
821 reload_in_progress = 1;
823 /* This loop scans the entire function each go-round
824 and repeats until one repetition spills no additional hard regs. */
827 int something_changed;
829 struct insn_chain *chain;
831 HOST_WIDE_INT starting_frame_size;
833 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done
834 here because the stack size may be a part of the offset computation
835 for register elimination, and there might have been new stack slots
836 created in the last iteration of this loop. */
837 assign_stack_local (BLKmode, 0, 0);
839 starting_frame_size = get_frame_size ();
841 set_initial_elim_offsets ();
842 set_initial_label_offsets ();
844 /* For each pseudo register that has an equivalent location defined,
845 try to eliminate any eliminable registers (such as the frame pointer)
846 assuming initial offsets for the replacement register, which
849 If the resulting location is directly addressable, substitute
850 the MEM we just got directly for the old REG.
852 If it is not addressable but is a constant or the sum of a hard reg
853 and constant, it is probably not addressable because the constant is
854 out of range, in that case record the address; we will generate
855 hairy code to compute the address in a register each time it is
856 needed. Similarly if it is a hard register, but one that is not
857 valid as an address register.
859 If the location is not addressable, but does not have one of the
860 above forms, assign a stack slot. We have to do this to avoid the
861 potential of producing lots of reloads if, e.g., a location involves
862 a pseudo that didn't get a hard register and has an equivalent memory
863 location that also involves a pseudo that didn't get a hard register.
865 Perhaps at some point we will improve reload_when_needed handling
866 so this problem goes away. But that's very hairy. */
868 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
869 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
871 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
873 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
875 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
876 else if (CONSTANT_P (XEXP (x, 0))
877 || (GET_CODE (XEXP (x, 0)) == REG
878 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
879 || (GET_CODE (XEXP (x, 0)) == PLUS
880 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
881 && (REGNO (XEXP (XEXP (x, 0), 0))
882 < FIRST_PSEUDO_REGISTER)
883 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
884 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
887 /* Make a new stack slot. Then indicate that something
888 changed so we go back and recompute offsets for
889 eliminable registers because the allocation of memory
890 below might change some offset. reg_equiv_{mem,address}
891 will be set up for this pseudo on the next pass around
893 reg_equiv_memory_loc[i] = 0;
894 reg_equiv_init[i] = 0;
899 if (caller_save_needed)
902 /* If we allocated another stack slot, redo elimination bookkeeping. */
903 if (starting_frame_size != get_frame_size ())
906 if (caller_save_needed)
908 save_call_clobbered_regs ();
909 /* That might have allocated new insn_chain structures. */
910 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
913 calculate_needs_all_insns (global);
915 CLEAR_REG_SET (spilled_pseudos);
918 something_changed = 0;
920 /* If we allocated any new memory locations, make another pass
921 since it might have changed elimination offsets. */
922 if (starting_frame_size != get_frame_size ())
923 something_changed = 1;
926 HARD_REG_SET to_spill;
927 CLEAR_HARD_REG_SET (to_spill);
928 update_eliminables (&to_spill);
929 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
930 if (TEST_HARD_REG_BIT (to_spill, i))
932 spill_hard_reg (i, dumpfile, 1);
935 /* Regardless of the state of spills, if we previously had
936 a register that we thought we could eliminate, but no can
937 not eliminate, we must run another pass.
939 Consider pseudos which have an entry in reg_equiv_* which
940 reference an eliminable register. We must make another pass
941 to update reg_equiv_* so that we do not substitute in the
942 old value from when we thought the elimination could be
944 something_changed = 1;
948 CLEAR_HARD_REG_SET (used_spill_regs);
949 /* Try to satisfy the needs for each insn. */
950 for (chain = insns_need_reload; chain != 0;
951 chain = chain->next_need_reload)
952 find_reload_regs (chain, dumpfile);
957 if (insns_need_reload != 0 || did_spill)
958 something_changed |= finish_spills (global, dumpfile);
960 if (! something_changed)
963 if (caller_save_needed)
964 delete_caller_save_insns ();
967 /* If global-alloc was run, notify it of any register eliminations we have
970 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
971 if (ep->can_eliminate)
972 mark_elimination (ep->from, ep->to);
974 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
975 If that insn didn't set the register (i.e., it copied the register to
976 memory), just delete that insn instead of the equivalencing insn plus
977 anything now dead. If we call delete_dead_insn on that insn, we may
978 delete the insn that actually sets the register if the register dies
979 there and that is incorrect. */
981 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
983 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
986 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
988 rtx equiv_insn = XEXP (list, 0);
989 if (GET_CODE (equiv_insn) == NOTE)
991 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
992 delete_dead_insn (equiv_insn);
995 PUT_CODE (equiv_insn, NOTE);
996 NOTE_SOURCE_FILE (equiv_insn) = 0;
997 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1003 /* Use the reload registers where necessary
1004 by generating move instructions to move the must-be-register
1005 values into or out of the reload registers. */
1007 if (insns_need_reload != 0 || something_needs_elimination
1008 || something_needs_operands_changed)
1010 int old_frame_size = get_frame_size ();
1012 reload_as_needed (global);
1014 if (old_frame_size != get_frame_size ())
1018 verify_initial_elim_offsets ();
1021 /* If we were able to eliminate the frame pointer, show that it is no
1022 longer live at the start of any basic block. If it ls live by
1023 virtue of being in a pseudo, that pseudo will be marked live
1024 and hence the frame pointer will be known to be live via that
1027 if (! frame_pointer_needed)
1028 for (i = 0; i < n_basic_blocks; i++)
1029 CLEAR_REGNO_REG_SET (basic_block_live_at_start[i],
1030 HARD_FRAME_POINTER_REGNUM);
1032 /* Come here (with failure set nonzero) if we can't get enough spill regs
1033 and we decide not to abort about it. */
1036 reload_in_progress = 0;
1038 /* Now eliminate all pseudo regs by modifying them into
1039 their equivalent memory references.
1040 The REG-rtx's for the pseudos are modified in place,
1041 so all insns that used to refer to them now refer to memory.
1043 For a reg that has a reg_equiv_address, all those insns
1044 were changed by reloading so that no insns refer to it any longer;
1045 but the DECL_RTL of a variable decl may refer to it,
1046 and if so this causes the debugging info to mention the variable. */
1048 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1052 int is_readonly = 0;
1054 if (reg_equiv_memory_loc[i])
1056 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1057 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1060 if (reg_equiv_mem[i])
1061 addr = XEXP (reg_equiv_mem[i], 0);
1063 if (reg_equiv_address[i])
1064 addr = reg_equiv_address[i];
1068 if (reg_renumber[i] < 0)
1070 rtx reg = regno_reg_rtx[i];
1071 XEXP (reg, 0) = addr;
1072 REG_USERVAR_P (reg) = 0;
1073 RTX_UNCHANGING_P (reg) = is_readonly;
1074 MEM_IN_STRUCT_P (reg) = in_struct;
1075 /* We have no alias information about this newly created
1077 MEM_ALIAS_SET (reg) = 0;
1078 PUT_CODE (reg, MEM);
1080 else if (reg_equiv_mem[i])
1081 XEXP (reg_equiv_mem[i], 0) = addr;
1085 /* We've finished reloading. This reload_completed must be set before we
1086 perform instruction splitting below. */
1087 reload_completed = 1;
1089 /* Make a pass over all the insns and delete all USEs which we inserted
1090 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1091 notes. Delete all CLOBBER insns and simplify (subreg (reg)) operands. */
1093 for (insn = first; insn; insn = NEXT_INSN (insn))
1094 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1098 if ((GET_CODE (PATTERN (insn)) == USE
1099 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1100 || GET_CODE (PATTERN (insn)) == CLOBBER)
1102 PUT_CODE (insn, NOTE);
1103 NOTE_SOURCE_FILE (insn) = 0;
1104 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1108 pnote = ®_NOTES (insn);
1111 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1112 || REG_NOTE_KIND (*pnote) == REG_UNUSED)
1113 *pnote = XEXP (*pnote, 1);
1115 pnote = &XEXP (*pnote, 1);
1118 /* And simplify (subreg (reg)) if it appears as an operand. */
1119 cleanup_subreg_operands (insn);
1121 /* If optimizing and we are performing instruction scheduling after
1122 reload, then go ahead and split insns now since we are about to
1123 recompute flow information anyway. */
1124 if (optimize && flag_schedule_insns_after_reload)
1128 last = try_split (PATTERN (insn), insn, 1);
1132 PUT_CODE (insn, NOTE);
1133 NOTE_SOURCE_FILE (insn) = 0;
1134 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1140 /* If we are doing stack checking, give a warning if this function's
1141 frame size is larger than we expect. */
1142 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1144 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1146 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1147 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1148 size += UNITS_PER_WORD;
1150 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1151 warning ("frame size too large for reliable stack checking");
1154 /* Indicate that we no longer have known memory locations or constants. */
1155 if (reg_equiv_constant)
1156 free (reg_equiv_constant);
1157 reg_equiv_constant = 0;
1158 if (reg_equiv_memory_loc)
1159 free (reg_equiv_memory_loc);
1160 reg_equiv_memory_loc = 0;
1163 free (real_known_ptr);
1167 free (reg_equiv_mem);
1168 free (reg_equiv_init);
1169 free (reg_equiv_address);
1170 free (reg_max_ref_width);
1171 free (reg_old_renumber);
1172 free (pseudo_previous_regs);
1173 free (pseudo_forbidden_regs);
1175 FREE_REG_SET (spilled_pseudos);
1177 CLEAR_HARD_REG_SET (used_spill_regs);
1178 for (i = 0; i < n_spills; i++)
1179 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1181 /* Free all the insn_chain structures at once. */
1182 obstack_free (&reload_obstack, reload_startobj);
1183 unused_insn_chains = 0;
1188 /* Yet another special case. Unfortunately, reg-stack forces people to
1189 write incorrect clobbers in asm statements. These clobbers must not
1190 cause the register to appear in bad_spill_regs, otherwise we'll call
1191 fatal_insn later. We clear the corresponding regnos in the live
1192 register sets to avoid this.
1193 The whole thing is rather sick, I'm afraid. */
1195 maybe_fix_stack_asms ()
1198 char *constraints[MAX_RECOG_OPERANDS];
1199 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1200 struct insn_chain *chain;
1202 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1205 HARD_REG_SET clobbered, allowed;
1208 if (GET_RTX_CLASS (GET_CODE (chain->insn)) != 'i'
1209 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1211 pat = PATTERN (chain->insn);
1212 if (GET_CODE (pat) != PARALLEL)
1215 CLEAR_HARD_REG_SET (clobbered);
1216 CLEAR_HARD_REG_SET (allowed);
1218 /* First, make a mask of all stack regs that are clobbered. */
1219 for (i = 0; i < XVECLEN (pat, 0); i++)
1221 rtx t = XVECEXP (pat, 0, i);
1222 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1223 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1226 /* Get the operand values and constraints out of the insn. */
1227 decode_asm_operands (pat, recog_operand, recog_operand_loc,
1228 constraints, operand_mode);
1230 /* For every operand, see what registers are allowed. */
1231 for (i = 0; i < noperands; i++)
1233 char *p = constraints[i];
1234 /* For every alternative, we compute the class of registers allowed
1235 for reloading in CLS, and merge its contents into the reg set
1237 int cls = (int) NO_REGS;
1243 if (c == '\0' || c == ',' || c == '#')
1245 /* End of one alternative - mark the regs in the current
1246 class, and reset the class. */
1247 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1252 } while (c != '\0' && c != ',');
1260 case '=': case '+': case '*': case '%': case '?': case '!':
1261 case '0': case '1': case '2': case '3': case '4': case 'm':
1262 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1263 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1264 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1266 #ifdef EXTRA_CONSTRAINT
1267 case 'Q': case 'R': case 'S': case 'T': case 'U':
1272 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1277 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1281 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1286 /* Those of the registers which are clobbered, but allowed by the
1287 constraints, must be usable as reload registers. So clear them
1288 out of the life information. */
1289 AND_HARD_REG_SET (allowed, clobbered);
1290 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1291 if (TEST_HARD_REG_BIT (allowed, i))
1293 CLEAR_REGNO_REG_SET (chain->live_before, i);
1294 CLEAR_REGNO_REG_SET (chain->live_after, i);
1302 /* Walk the chain of insns, and determine for each whether it needs reloads
1303 and/or eliminations. Build the corresponding insns_need_reload list, and
1304 set something_needs_elimination as appropriate. */
1306 calculate_needs_all_insns (global)
1309 struct insn_chain **pprev_reload = &insns_need_reload;
1310 struct insn_chain **pchain;
1312 something_needs_elimination = 0;
1314 for (pchain = &reload_insn_chain; *pchain != 0; pchain = &(*pchain)->next)
1317 struct insn_chain *chain;
1322 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1323 include REG_LABEL), we need to see what effects this has on the
1324 known offsets at labels. */
1326 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1327 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1328 && REG_NOTES (insn) != 0))
1329 set_label_offsets (insn, insn, 0);
1331 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1333 rtx old_body = PATTERN (insn);
1334 int old_code = INSN_CODE (insn);
1335 rtx old_notes = REG_NOTES (insn);
1336 int did_elimination = 0;
1337 int operands_changed = 0;
1339 /* If needed, eliminate any eliminable registers. */
1341 did_elimination = eliminate_regs_in_insn (insn, 0);
1343 /* Analyze the instruction. */
1344 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1345 global, spill_reg_order);
1347 /* If a no-op set needs more than one reload, this is likely
1348 to be something that needs input address reloads. We
1349 can't get rid of this cleanly later, and it is of no use
1350 anyway, so discard it now.
1351 We only do this when expensive_optimizations is enabled,
1352 since this complements reload inheritance / output
1353 reload deletion, and it can make debugging harder. */
1354 if (flag_expensive_optimizations && n_reloads > 1)
1356 rtx set = single_set (insn);
1358 && SET_SRC (set) == SET_DEST (set)
1359 && GET_CODE (SET_SRC (set)) == REG
1360 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1362 PUT_CODE (insn, NOTE);
1363 NOTE_SOURCE_FILE (insn) = 0;
1364 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1369 update_eliminable_offsets ();
1371 /* Remember for later shortcuts which insns had any reloads or
1372 register eliminations. */
1373 chain->need_elim = did_elimination;
1374 chain->need_reload = n_reloads > 0;
1375 chain->need_operand_change = operands_changed;
1377 /* Discard any register replacements done. */
1378 if (did_elimination)
1380 obstack_free (&reload_obstack, reload_firstobj);
1381 PATTERN (insn) = old_body;
1382 INSN_CODE (insn) = old_code;
1383 REG_NOTES (insn) = old_notes;
1384 something_needs_elimination = 1;
1387 something_needs_operands_changed |= operands_changed;
1391 *pprev_reload = chain;
1392 pprev_reload = &chain->next_need_reload;
1394 calculate_needs (chain);
1401 /* Compute the most additional registers needed by one instruction,
1402 given by CHAIN. Collect information separately for each class of regs.
1404 To compute the number of reload registers of each class needed for an
1405 insn, we must simulate what choose_reload_regs can do. We do this by
1406 splitting an insn into an "input" and an "output" part. RELOAD_OTHER
1407 reloads are used in both. The input part uses those reloads,
1408 RELOAD_FOR_INPUT reloads, which must be live over the entire input section
1409 of reloads, and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
1410 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the inputs.
1412 The registers needed for output are RELOAD_OTHER and RELOAD_FOR_OUTPUT,
1413 which are live for the entire output portion, and the maximum of all the
1414 RELOAD_FOR_OUTPUT_ADDRESS reloads for each operand.
1416 The total number of registers needed is the maximum of the
1417 inputs and outputs. */
1420 calculate_needs (chain)
1421 struct insn_chain *chain;
1425 /* Each `struct needs' corresponds to one RELOAD_... type. */
1429 struct needs output;
1431 struct needs other_addr;
1432 struct needs op_addr;
1433 struct needs op_addr_reload;
1434 struct needs in_addr[MAX_RECOG_OPERANDS];
1435 struct needs in_addr_addr[MAX_RECOG_OPERANDS];
1436 struct needs out_addr[MAX_RECOG_OPERANDS];
1437 struct needs out_addr_addr[MAX_RECOG_OPERANDS];
1440 bzero ((char *) chain->group_size, sizeof chain->group_size);
1441 for (i = 0; i < N_REG_CLASSES; i++)
1442 chain->group_mode[i] = VOIDmode;
1443 bzero ((char *) &insn_needs, sizeof insn_needs);
1445 /* Count each reload once in every class
1446 containing the reload's own class. */
1448 for (i = 0; i < n_reloads; i++)
1450 register enum reg_class *p;
1451 enum reg_class class = reload_reg_class[i];
1453 enum machine_mode mode;
1454 struct needs *this_needs;
1456 /* Don't count the dummy reloads, for which one of the
1457 regs mentioned in the insn can be used for reloading.
1458 Don't count optional reloads.
1459 Don't count reloads that got combined with others. */
1460 if (reload_reg_rtx[i] != 0
1461 || reload_optional[i] != 0
1462 || (reload_out[i] == 0 && reload_in[i] == 0
1463 && ! reload_secondary_p[i]))
1466 mode = reload_inmode[i];
1467 if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1468 mode = reload_outmode[i];
1469 size = CLASS_MAX_NREGS (class, mode);
1471 /* Decide which time-of-use to count this reload for. */
1472 switch (reload_when_needed[i])
1475 this_needs = &insn_needs.other;
1477 case RELOAD_FOR_INPUT:
1478 this_needs = &insn_needs.input;
1480 case RELOAD_FOR_OUTPUT:
1481 this_needs = &insn_needs.output;
1483 case RELOAD_FOR_INSN:
1484 this_needs = &insn_needs.insn;
1486 case RELOAD_FOR_OTHER_ADDRESS:
1487 this_needs = &insn_needs.other_addr;
1489 case RELOAD_FOR_INPUT_ADDRESS:
1490 this_needs = &insn_needs.in_addr[reload_opnum[i]];
1492 case RELOAD_FOR_INPADDR_ADDRESS:
1493 this_needs = &insn_needs.in_addr_addr[reload_opnum[i]];
1495 case RELOAD_FOR_OUTPUT_ADDRESS:
1496 this_needs = &insn_needs.out_addr[reload_opnum[i]];
1498 case RELOAD_FOR_OUTADDR_ADDRESS:
1499 this_needs = &insn_needs.out_addr_addr[reload_opnum[i]];
1501 case RELOAD_FOR_OPERAND_ADDRESS:
1502 this_needs = &insn_needs.op_addr;
1504 case RELOAD_FOR_OPADDR_ADDR:
1505 this_needs = &insn_needs.op_addr_reload;
1511 enum machine_mode other_mode, allocate_mode;
1513 /* Count number of groups needed separately from
1514 number of individual regs needed. */
1515 this_needs->groups[(int) class]++;
1516 p = reg_class_superclasses[(int) class];
1517 while (*p != LIM_REG_CLASSES)
1518 this_needs->groups[(int) *p++]++;
1520 /* Record size and mode of a group of this class. */
1521 /* If more than one size group is needed,
1522 make all groups the largest needed size. */
1523 if (chain->group_size[(int) class] < size)
1525 other_mode = chain->group_mode[(int) class];
1526 allocate_mode = mode;
1528 chain->group_size[(int) class] = size;
1529 chain->group_mode[(int) class] = mode;
1534 allocate_mode = chain->group_mode[(int) class];
1537 /* Crash if two dissimilar machine modes both need
1538 groups of consecutive regs of the same class. */
1540 if (other_mode != VOIDmode && other_mode != allocate_mode
1541 && ! modes_equiv_for_class_p (allocate_mode,
1543 fatal_insn ("Two dissimilar machine modes both need groups of consecutive regs of the same class",
1548 this_needs->regs[(unsigned char)reload_nongroup[i]][(int) class] += 1;
1549 p = reg_class_superclasses[(int) class];
1550 while (*p != LIM_REG_CLASSES)
1551 this_needs->regs[(unsigned char)reload_nongroup[i]][(int) *p++] += 1;
1557 /* All reloads have been counted for this insn;
1558 now merge the various times of use.
1559 This sets insn_needs, etc., to the maximum total number
1560 of registers needed at any point in this insn. */
1562 for (i = 0; i < N_REG_CLASSES; i++)
1564 int j, in_max, out_max;
1566 /* Compute normal and nongroup needs. */
1567 for (j = 0; j <= 1; j++)
1570 for (in_max = 0, out_max = 0, k = 0; k < reload_n_operands; k++)
1572 in_max = MAX (in_max,
1573 (insn_needs.in_addr[k].regs[j][i]
1574 + insn_needs.in_addr_addr[k].regs[j][i]));
1575 out_max = MAX (out_max, insn_needs.out_addr[k].regs[j][i]);
1576 out_max = MAX (out_max,
1577 insn_needs.out_addr_addr[k].regs[j][i]);
1580 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1581 and operand addresses but not things used to reload
1582 them. Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads
1583 don't conflict with things needed to reload inputs or
1586 in_max = MAX (MAX (insn_needs.op_addr.regs[j][i],
1587 insn_needs.op_addr_reload.regs[j][i]),
1590 out_max = MAX (out_max, insn_needs.insn.regs[j][i]);
1592 insn_needs.input.regs[j][i]
1593 = MAX (insn_needs.input.regs[j][i]
1594 + insn_needs.op_addr.regs[j][i]
1595 + insn_needs.insn.regs[j][i],
1596 in_max + insn_needs.input.regs[j][i]);
1598 insn_needs.output.regs[j][i] += out_max;
1599 insn_needs.other.regs[j][i]
1600 += MAX (MAX (insn_needs.input.regs[j][i],
1601 insn_needs.output.regs[j][i]),
1602 insn_needs.other_addr.regs[j][i]);
1606 /* Now compute group needs. */
1607 for (in_max = 0, out_max = 0, j = 0; j < reload_n_operands; j++)
1609 in_max = MAX (in_max, insn_needs.in_addr[j].groups[i]);
1610 in_max = MAX (in_max, insn_needs.in_addr_addr[j].groups[i]);
1611 out_max = MAX (out_max, insn_needs.out_addr[j].groups[i]);
1612 out_max = MAX (out_max, insn_needs.out_addr_addr[j].groups[i]);
1615 in_max = MAX (MAX (insn_needs.op_addr.groups[i],
1616 insn_needs.op_addr_reload.groups[i]),
1618 out_max = MAX (out_max, insn_needs.insn.groups[i]);
1620 insn_needs.input.groups[i]
1621 = MAX (insn_needs.input.groups[i]
1622 + insn_needs.op_addr.groups[i]
1623 + insn_needs.insn.groups[i],
1624 in_max + insn_needs.input.groups[i]);
1626 insn_needs.output.groups[i] += out_max;
1627 insn_needs.other.groups[i]
1628 += MAX (MAX (insn_needs.input.groups[i],
1629 insn_needs.output.groups[i]),
1630 insn_needs.other_addr.groups[i]);
1633 /* Record the needs for later. */
1634 chain->need = insn_needs.other;
1637 /* Find a group of exactly 2 registers.
1639 First try to fill out the group by spilling a single register which
1640 would allow completion of the group.
1642 Then try to create a new group from a pair of registers, neither of
1643 which are explicitly used.
1645 Then try to create a group from any pair of registers. */
1648 find_tworeg_group (chain, class, dumpfile)
1649 struct insn_chain *chain;
1654 /* First, look for a register that will complete a group. */
1655 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1659 j = potential_reload_regs[i];
1660 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1661 && ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1662 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1663 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1664 && HARD_REGNO_MODE_OK (other, chain->group_mode[class])
1665 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, other)
1666 /* We don't want one part of another group.
1667 We could get "two groups" that overlap! */
1668 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, other))
1669 || (j < FIRST_PSEUDO_REGISTER - 1
1670 && (other = j + 1, spill_reg_order[other] >= 0)
1671 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1672 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1673 && HARD_REGNO_MODE_OK (j, chain->group_mode[class])
1674 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, other)
1675 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, other))))
1677 register enum reg_class *p;
1679 /* We have found one that will complete a group,
1680 so count off one group as provided. */
1681 chain->need.groups[class]--;
1682 p = reg_class_superclasses[class];
1683 while (*p != LIM_REG_CLASSES)
1685 if (chain->group_size [(int) *p] <= chain->group_size [class])
1686 chain->need.groups[(int) *p]--;
1690 /* Indicate both these regs are part of a group. */
1691 SET_HARD_REG_BIT (chain->counted_for_groups, j);
1692 SET_HARD_REG_BIT (chain->counted_for_groups, other);
1696 /* We can't complete a group, so start one. */
1697 if (i == FIRST_PSEUDO_REGISTER)
1698 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1701 j = potential_reload_regs[i];
1702 /* Verify that J+1 is a potential reload reg. */
1703 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1704 if (potential_reload_regs[k] == j + 1)
1706 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1707 && k < FIRST_PSEUDO_REGISTER
1708 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1709 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1710 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1711 && HARD_REGNO_MODE_OK (j, chain->group_mode[class])
1712 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, j + 1)
1713 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1))
1717 /* I should be the index in potential_reload_regs
1718 of the new reload reg we have found. */
1720 new_spill_reg (chain, i, class, 0, dumpfile);
1723 /* Find a group of more than 2 registers.
1724 Look for a sufficient sequence of unspilled registers, and spill them all
1728 find_group (chain, class, dumpfile)
1729 struct insn_chain *chain;
1735 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1737 int j = potential_reload_regs[i];
1740 && j + chain->group_size[class] <= FIRST_PSEUDO_REGISTER
1741 && HARD_REGNO_MODE_OK (j, chain->group_mode[class]))
1744 /* Check each reg in the sequence. */
1745 for (k = 0; k < chain->group_size[class]; k++)
1746 if (! (spill_reg_order[j + k] < 0
1747 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1748 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1750 /* We got a full sequence, so spill them all. */
1751 if (k == chain->group_size[class])
1753 register enum reg_class *p;
1754 for (k = 0; k < chain->group_size[class]; k++)
1757 SET_HARD_REG_BIT (chain->counted_for_groups, j + k);
1758 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1759 if (potential_reload_regs[idx] == j + k)
1761 new_spill_reg (chain, idx, class, 0, dumpfile);
1764 /* We have found one that will complete a group,
1765 so count off one group as provided. */
1766 chain->need.groups[class]--;
1767 p = reg_class_superclasses[class];
1768 while (*p != LIM_REG_CLASSES)
1770 if (chain->group_size [(int) *p]
1771 <= chain->group_size [class])
1772 chain->need.groups[(int) *p]--;
1779 /* There are no groups left. */
1780 spill_failure (chain->insn);
1784 /* If pseudo REG conflicts with one of our reload registers, mark it as
1787 maybe_mark_pseudo_spilled (reg)
1791 int r = reg_renumber[reg];
1796 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1797 for (i = 0; i < n_spills; i++)
1798 if (r <= spill_regs[i] && r + nregs > spill_regs[i])
1800 SET_REGNO_REG_SET (spilled_pseudos, reg);
1805 /* Find more reload regs to satisfy the remaining need of an insn, which
1807 Do it by ascending class number, since otherwise a reg
1808 might be spilled for a big class and might fail to count
1809 for a smaller class even though it belongs to that class.
1811 Count spilled regs in `spills', and add entries to
1812 `spill_regs' and `spill_reg_order'.
1814 ??? Note there is a problem here.
1815 When there is a need for a group in a high-numbered class,
1816 and also need for non-group regs that come from a lower class,
1817 the non-group regs are chosen first. If there aren't many regs,
1818 they might leave no room for a group.
1820 This was happening on the 386. To fix it, we added the code
1821 that calls possible_group_p, so that the lower class won't
1822 break up the last possible group.
1824 Really fixing the problem would require changes above
1825 in counting the regs already spilled, and in choose_reload_regs.
1826 It might be hard to avoid introducing bugs there. */
1829 find_reload_regs (chain, dumpfile)
1830 struct insn_chain *chain;
1834 short *group_needs = chain->need.groups;
1835 short *simple_needs = chain->need.regs[0];
1836 short *nongroup_needs = chain->need.regs[1];
1839 fprintf (dumpfile, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1841 /* Compute the order of preference for hard registers to spill.
1842 Store them by decreasing preference in potential_reload_regs. */
1844 order_regs_for_reload (chain);
1846 /* So far, no hard regs have been spilled. */
1848 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1849 spill_reg_order[i] = -1;
1851 CLEAR_HARD_REG_SET (chain->used_spill_regs);
1852 CLEAR_HARD_REG_SET (chain->counted_for_groups);
1853 CLEAR_HARD_REG_SET (chain->counted_for_nongroups);
1855 for (class = 0; class < N_REG_CLASSES; class++)
1857 /* First get the groups of registers.
1858 If we got single registers first, we might fragment
1860 while (group_needs[class] > 0)
1862 /* If any single spilled regs happen to form groups,
1863 count them now. Maybe we don't really need
1864 to spill another group. */
1865 count_possible_groups (chain, class);
1867 if (group_needs[class] <= 0)
1870 /* Groups of size 2, the only groups used on most machines,
1871 are treated specially. */
1872 if (chain->group_size[class] == 2)
1873 find_tworeg_group (chain, class, dumpfile);
1875 find_group (chain, class, dumpfile);
1880 /* Now similarly satisfy all need for single registers. */
1882 while (simple_needs[class] > 0 || nongroup_needs[class] > 0)
1884 /* If we spilled enough regs, but they weren't counted
1885 against the non-group need, see if we can count them now.
1886 If so, we can avoid some actual spilling. */
1887 if (simple_needs[class] <= 0 && nongroup_needs[class] > 0)
1888 for (i = 0; i < n_spills; i++)
1890 int regno = spill_regs[i];
1891 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1892 && !TEST_HARD_REG_BIT (chain->counted_for_groups, regno)
1893 && !TEST_HARD_REG_BIT (chain->counted_for_nongroups, regno)
1894 && nongroup_needs[class] > 0)
1896 register enum reg_class *p;
1898 SET_HARD_REG_BIT (chain->counted_for_nongroups, regno);
1899 nongroup_needs[class]--;
1900 p = reg_class_superclasses[class];
1901 while (*p != LIM_REG_CLASSES)
1902 nongroup_needs[(int) *p++]--;
1906 if (simple_needs[class] <= 0 && nongroup_needs[class] <= 0)
1909 /* Consider the potential reload regs that aren't
1910 yet in use as reload regs, in order of preference.
1911 Find the most preferred one that's in this class. */
1913 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1915 int regno = potential_reload_regs[i];
1917 && TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1918 /* If this reg will not be available for groups,
1919 pick one that does not foreclose possible groups.
1920 This is a kludge, and not very general,
1921 but it should be sufficient to make the 386 work,
1922 and the problem should not occur on machines with
1924 && (nongroup_needs[class] == 0
1925 || possible_group_p (chain, regno)))
1929 /* If we couldn't get a register, try to get one even if we
1930 might foreclose possible groups. This may cause problems
1931 later, but that's better than aborting now, since it is
1932 possible that we will, in fact, be able to form the needed
1933 group even with this allocation. */
1935 if (i >= FIRST_PSEUDO_REGISTER
1936 && asm_noperands (chain->insn) < 0)
1937 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1938 if (potential_reload_regs[i] >= 0
1939 && TEST_HARD_REG_BIT (reg_class_contents[class],
1940 potential_reload_regs[i]))
1943 /* I should be the index in potential_reload_regs
1944 of the new reload reg we have found. */
1946 new_spill_reg (chain, i, class, 1, dumpfile);
1952 /* We know which hard regs to use, now mark the pseudos that live in them
1953 as needing to be kicked out. */
1954 EXECUTE_IF_SET_IN_REG_SET
1955 (chain->live_before, FIRST_PSEUDO_REGISTER, i,
1957 maybe_mark_pseudo_spilled (i);
1959 EXECUTE_IF_SET_IN_REG_SET
1960 (chain->live_after, FIRST_PSEUDO_REGISTER, i,
1962 maybe_mark_pseudo_spilled (i);
1965 IOR_HARD_REG_SET (used_spill_regs, chain->used_spill_regs);
1969 dump_needs (chain, dumpfile)
1970 struct insn_chain *chain;
1973 static char *reg_class_names[] = REG_CLASS_NAMES;
1975 struct needs *n = &chain->need;
1977 for (i = 0; i < N_REG_CLASSES; i++)
1979 if (n->regs[i][0] > 0)
1981 ";; Need %d reg%s of class %s.\n",
1982 n->regs[i][0], n->regs[i][0] == 1 ? "" : "s",
1983 reg_class_names[i]);
1984 if (n->regs[i][1] > 0)
1986 ";; Need %d nongroup reg%s of class %s.\n",
1987 n->regs[i][1], n->regs[i][1] == 1 ? "" : "s",
1988 reg_class_names[i]);
1989 if (n->groups[i] > 0)
1991 ";; Need %d group%s (%smode) of class %s.\n",
1992 n->groups[i], n->groups[i] == 1 ? "" : "s",
1993 mode_name[(int) chain->group_mode[i]],
1994 reg_class_names[i]);
1998 /* Delete all insns that were inserted by emit_caller_save_insns during
2001 delete_caller_save_insns ()
2003 struct insn_chain *c = reload_insn_chain;
2007 while (c != 0 && c->is_caller_save_insn)
2009 struct insn_chain *next = c->next;
2012 if (insn == basic_block_head[c->block])
2013 basic_block_head[c->block] = NEXT_INSN (insn);
2014 if (insn == basic_block_end[c->block])
2015 basic_block_end[c->block] = PREV_INSN (insn);
2016 if (c == reload_insn_chain)
2017 reload_insn_chain = next;
2019 if (NEXT_INSN (insn) != 0)
2020 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2021 if (PREV_INSN (insn) != 0)
2022 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2025 next->prev = c->prev;
2027 c->prev->next = next;
2028 c->next = unused_insn_chains;
2029 unused_insn_chains = c;
2037 /* Nonzero if, after spilling reg REGNO for non-groups,
2038 it will still be possible to find a group if we still need one. */
2041 possible_group_p (chain, regno)
2042 struct insn_chain *chain;
2046 int class = (int) NO_REGS;
2048 for (i = 0; i < (int) N_REG_CLASSES; i++)
2049 if (chain->need.groups[i] > 0)
2055 if (class == (int) NO_REGS)
2058 /* Consider each pair of consecutive registers. */
2059 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
2061 /* Ignore pairs that include reg REGNO. */
2062 if (i == regno || i + 1 == regno)
2065 /* Ignore pairs that are outside the class that needs the group.
2066 ??? Here we fail to handle the case where two different classes
2067 independently need groups. But this never happens with our
2068 current machine descriptions. */
2069 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
2070 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
2073 /* A pair of consecutive regs we can still spill does the trick. */
2074 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
2075 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2076 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
2079 /* A pair of one already spilled and one we can spill does it
2080 provided the one already spilled is not otherwise reserved. */
2081 if (spill_reg_order[i] < 0
2082 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2083 && spill_reg_order[i + 1] >= 0
2084 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, i + 1)
2085 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, i + 1))
2087 if (spill_reg_order[i + 1] < 0
2088 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
2089 && spill_reg_order[i] >= 0
2090 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, i)
2091 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, i))
2098 /* Count any groups of CLASS that can be formed from the registers recently
2102 count_possible_groups (chain, class)
2103 struct insn_chain *chain;
2109 /* Now find all consecutive groups of spilled registers
2110 and mark each group off against the need for such groups.
2111 But don't count them against ordinary need, yet. */
2113 if (chain->group_size[class] == 0)
2116 CLEAR_HARD_REG_SET (new);
2118 /* Make a mask of all the regs that are spill regs in class I. */
2119 for (i = 0; i < n_spills; i++)
2121 int regno = spill_regs[i];
2123 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
2124 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, regno)
2125 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, regno))
2126 SET_HARD_REG_BIT (new, regno);
2129 /* Find each consecutive group of them. */
2130 for (i = 0; i < FIRST_PSEUDO_REGISTER && chain->need.groups[class] > 0; i++)
2131 if (TEST_HARD_REG_BIT (new, i)
2132 && i + chain->group_size[class] <= FIRST_PSEUDO_REGISTER
2133 && HARD_REGNO_MODE_OK (i, chain->group_mode[class]))
2135 for (j = 1; j < chain->group_size[class]; j++)
2136 if (! TEST_HARD_REG_BIT (new, i + j))
2139 if (j == chain->group_size[class])
2141 /* We found a group. Mark it off against this class's need for
2142 groups, and against each superclass too. */
2143 register enum reg_class *p;
2145 chain->need.groups[class]--;
2146 p = reg_class_superclasses[class];
2147 while (*p != LIM_REG_CLASSES)
2149 if (chain->group_size [(int) *p] <= chain->group_size [class])
2150 chain->need.groups[(int) *p]--;
2154 /* Don't count these registers again. */
2155 for (j = 0; j < chain->group_size[class]; j++)
2156 SET_HARD_REG_BIT (chain->counted_for_groups, i + j);
2159 /* Skip to the last reg in this group. When i is incremented above,
2160 it will then point to the first reg of the next possible group. */
2165 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2166 another mode that needs to be reloaded for the same register class CLASS.
2167 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2168 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2170 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2171 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2172 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2173 causes unnecessary failures on machines requiring alignment of register
2174 groups when the two modes are different sizes, because the larger mode has
2175 more strict alignment rules than the smaller mode. */
2178 modes_equiv_for_class_p (allocate_mode, other_mode, class)
2179 enum machine_mode allocate_mode, other_mode;
2180 enum reg_class class;
2183 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2185 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
2186 && HARD_REGNO_MODE_OK (regno, allocate_mode)
2187 && ! HARD_REGNO_MODE_OK (regno, other_mode))
2193 /* Handle the failure to find a register to spill.
2194 INSN should be one of the insns which needed this particular spill reg. */
2197 spill_failure (insn)
2200 if (asm_noperands (PATTERN (insn)) >= 0)
2201 error_for_asm (insn, "`asm' needs too many reloads");
2203 fatal_insn ("Unable to find a register to spill.", insn);
2206 /* Add a new register to the tables of available spill-registers.
2207 CHAIN is the insn for which the register will be used; we decrease the
2209 I is the index of this register in potential_reload_regs.
2210 CLASS is the regclass whose need is being satisfied.
2211 NONGROUP is 0 if this register is part of a group.
2212 DUMPFILE is the same as the one that `reload' got. */
2215 new_spill_reg (chain, i, class, nongroup, dumpfile)
2216 struct insn_chain *chain;
2222 register enum reg_class *p;
2223 int regno = potential_reload_regs[i];
2225 if (i >= FIRST_PSEUDO_REGISTER)
2227 spill_failure (chain->insn);
2232 if (TEST_HARD_REG_BIT (bad_spill_regs, regno))
2234 static char *reg_class_names[] = REG_CLASS_NAMES;
2236 if (asm_noperands (PATTERN (chain->insn)) < 0)
2238 /* The error message is still correct - we know only that it wasn't
2239 an asm statement that caused the problem, but one of the global
2240 registers declared by the users might have screwed us. */
2241 error ("fixed or forbidden register %d (%s) was spilled for class %s.",
2242 regno, reg_names[regno], reg_class_names[class]);
2243 error ("This may be due to a compiler bug or to impossible asm");
2244 error ("statements or clauses.");
2245 fatal_insn ("This is the instruction:", chain->insn);
2247 error_for_asm (chain->insn, "Invalid `asm' statement:");
2248 error_for_asm (chain->insn,
2249 "fixed or forbidden register %d (%s) was spilled for class %s.",
2250 regno, reg_names[regno], reg_class_names[class]);
2255 /* Make reg REGNO an additional reload reg. */
2257 potential_reload_regs[i] = -1;
2258 spill_regs[n_spills] = regno;
2259 spill_reg_order[regno] = n_spills;
2261 fprintf (dumpfile, "Spilling reg %d.\n", regno);
2262 SET_HARD_REG_BIT (chain->used_spill_regs, regno);
2264 /* Clear off the needs we just satisfied. */
2266 chain->need.regs[0][class]--;
2267 p = reg_class_superclasses[class];
2268 while (*p != LIM_REG_CLASSES)
2269 chain->need.regs[0][(int) *p++]--;
2271 if (nongroup && chain->need.regs[1][class] > 0)
2273 SET_HARD_REG_BIT (chain->counted_for_nongroups, regno);
2274 chain->need.regs[1][class]--;
2275 p = reg_class_superclasses[class];
2276 while (*p != LIM_REG_CLASSES)
2277 chain->need.regs[1][(int) *p++]--;
2283 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2284 data that is dead in INSN. */
2287 delete_dead_insn (insn)
2290 rtx prev = prev_real_insn (insn);
2293 /* If the previous insn sets a register that dies in our insn, delete it
2295 if (prev && GET_CODE (PATTERN (prev)) == SET
2296 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2297 && reg_mentioned_p (prev_dest, PATTERN (insn))
2298 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2299 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2300 delete_dead_insn (prev);
2302 PUT_CODE (insn, NOTE);
2303 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2304 NOTE_SOURCE_FILE (insn) = 0;
2307 /* Modify the home of pseudo-reg I.
2308 The new home is present in reg_renumber[I].
2310 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2311 or it may be -1, meaning there is none or it is not relevant.
2312 This is used so that all pseudos spilled from a given hard reg
2313 can share one stack slot. */
2316 alter_reg (i, from_reg)
2320 /* When outputting an inline function, this can happen
2321 for a reg that isn't actually used. */
2322 if (regno_reg_rtx[i] == 0)
2325 /* If the reg got changed to a MEM at rtl-generation time,
2327 if (GET_CODE (regno_reg_rtx[i]) != REG)
2330 /* Modify the reg-rtx to contain the new hard reg
2331 number or else to contain its pseudo reg number. */
2332 REGNO (regno_reg_rtx[i])
2333 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2335 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2336 allocate a stack slot for it. */
2338 if (reg_renumber[i] < 0
2339 && REG_N_REFS (i) > 0
2340 && reg_equiv_constant[i] == 0
2341 && reg_equiv_memory_loc[i] == 0)
2344 int inherent_size = PSEUDO_REGNO_BYTES (i);
2345 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2348 /* Each pseudo reg has an inherent size which comes from its own mode,
2349 and a total size which provides room for paradoxical subregs
2350 which refer to the pseudo reg in wider modes.
2352 We can use a slot already allocated if it provides both
2353 enough inherent space and enough total space.
2354 Otherwise, we allocate a new slot, making sure that it has no less
2355 inherent space, and no less total space, then the previous slot. */
2358 /* No known place to spill from => no slot to reuse. */
2359 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
2360 inherent_size == total_size ? 0 : -1);
2361 if (BYTES_BIG_ENDIAN)
2362 /* Cancel the big-endian correction done in assign_stack_local.
2363 Get the address of the beginning of the slot.
2364 This is so we can do a big-endian correction unconditionally
2366 adjust = inherent_size - total_size;
2368 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2370 /* Reuse a stack slot if possible. */
2371 else if (spill_stack_slot[from_reg] != 0
2372 && spill_stack_slot_width[from_reg] >= total_size
2373 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2375 x = spill_stack_slot[from_reg];
2376 /* Allocate a bigger slot. */
2379 /* Compute maximum size needed, both for inherent size
2380 and for total size. */
2381 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2383 if (spill_stack_slot[from_reg])
2385 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2387 mode = GET_MODE (spill_stack_slot[from_reg]);
2388 if (spill_stack_slot_width[from_reg] > total_size)
2389 total_size = spill_stack_slot_width[from_reg];
2391 /* Make a slot with that size. */
2392 x = assign_stack_local (mode, total_size,
2393 inherent_size == total_size ? 0 : -1);
2395 if (BYTES_BIG_ENDIAN)
2397 /* Cancel the big-endian correction done in assign_stack_local.
2398 Get the address of the beginning of the slot.
2399 This is so we can do a big-endian correction unconditionally
2401 adjust = GET_MODE_SIZE (mode) - total_size;
2403 stack_slot = gen_rtx_MEM (mode_for_size (total_size
2406 plus_constant (XEXP (x, 0), adjust));
2408 spill_stack_slot[from_reg] = stack_slot;
2409 spill_stack_slot_width[from_reg] = total_size;
2412 /* On a big endian machine, the "address" of the slot
2413 is the address of the low part that fits its inherent mode. */
2414 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2415 adjust += (total_size - inherent_size);
2417 /* If we have any adjustment to make, or if the stack slot is the
2418 wrong mode, make a new stack slot. */
2419 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2421 x = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
2422 plus_constant (XEXP (x, 0), adjust));
2424 /* If this was shared among registers, must ensure we never
2425 set it readonly since that can cause scheduling
2426 problems. Note we would only have in this adjustment
2427 case in any event, since the code above doesn't set it. */
2430 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2433 /* Save the stack slot for later. */
2434 reg_equiv_memory_loc[i] = x;
2438 /* Mark the slots in regs_ever_live for the hard regs
2439 used by pseudo-reg number REGNO. */
2442 mark_home_live (regno)
2445 register int i, lim;
2446 i = reg_renumber[regno];
2449 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2451 regs_ever_live[i++] = 1;
2454 /* This function handles the tracking of elimination offsets around branches.
2456 X is a piece of RTL being scanned.
2458 INSN is the insn that it came from, if any.
2460 INITIAL_P is non-zero if we are to set the offset to be the initial
2461 offset and zero if we are setting the offset of the label to be the
2465 set_label_offsets (x, insn, initial_p)
2470 enum rtx_code code = GET_CODE (x);
2473 struct elim_table *p;
2478 if (LABEL_REF_NONLOCAL_P (x))
2483 /* ... fall through ... */
2486 /* If we know nothing about this label, set the desired offsets. Note
2487 that this sets the offset at a label to be the offset before a label
2488 if we don't know anything about the label. This is not correct for
2489 the label after a BARRIER, but is the best guess we can make. If
2490 we guessed wrong, we will suppress an elimination that might have
2491 been possible had we been able to guess correctly. */
2493 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2495 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2496 offsets_at[CODE_LABEL_NUMBER (x)][i]
2497 = (initial_p ? reg_eliminate[i].initial_offset
2498 : reg_eliminate[i].offset);
2499 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2502 /* Otherwise, if this is the definition of a label and it is
2503 preceded by a BARRIER, set our offsets to the known offset of
2507 && (tem = prev_nonnote_insn (insn)) != 0
2508 && GET_CODE (tem) == BARRIER)
2509 set_offsets_for_label (insn);
2511 /* If neither of the above cases is true, compare each offset
2512 with those previously recorded and suppress any eliminations
2513 where the offsets disagree. */
2515 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2516 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2517 != (initial_p ? reg_eliminate[i].initial_offset
2518 : reg_eliminate[i].offset))
2519 reg_eliminate[i].can_eliminate = 0;
2524 set_label_offsets (PATTERN (insn), insn, initial_p);
2526 /* ... fall through ... */
2530 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2531 and hence must have all eliminations at their initial offsets. */
2532 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2533 if (REG_NOTE_KIND (tem) == REG_LABEL)
2534 set_label_offsets (XEXP (tem, 0), insn, 1);
2539 /* Each of the labels in the address vector must be at their initial
2540 offsets. We want the first field for ADDR_VEC and the second
2541 field for ADDR_DIFF_VEC. */
2543 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2544 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2549 /* We only care about setting PC. If the source is not RETURN,
2550 IF_THEN_ELSE, or a label, disable any eliminations not at
2551 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2552 isn't one of those possibilities. For branches to a label,
2553 call ourselves recursively.
2555 Note that this can disable elimination unnecessarily when we have
2556 a non-local goto since it will look like a non-constant jump to
2557 someplace in the current function. This isn't a significant
2558 problem since such jumps will normally be when all elimination
2559 pairs are back to their initial offsets. */
2561 if (SET_DEST (x) != pc_rtx)
2564 switch (GET_CODE (SET_SRC (x)))
2571 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2575 tem = XEXP (SET_SRC (x), 1);
2576 if (GET_CODE (tem) == LABEL_REF)
2577 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2578 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2581 tem = XEXP (SET_SRC (x), 2);
2582 if (GET_CODE (tem) == LABEL_REF)
2583 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2584 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2592 /* If we reach here, all eliminations must be at their initial
2593 offset because we are doing a jump to a variable address. */
2594 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2595 if (p->offset != p->initial_offset)
2596 p->can_eliminate = 0;
2604 /* Used for communication between the next two function to properly share
2605 the vector for an ASM_OPERANDS. */
2607 static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2609 /* Scan X and replace any eliminable registers (such as fp) with a
2610 replacement (such as sp), plus an offset.
2612 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2613 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2614 MEM, we are allowed to replace a sum of a register and the constant zero
2615 with the register, which we cannot do outside a MEM. In addition, we need
2616 to record the fact that a register is referenced outside a MEM.
2618 If INSN is an insn, it is the insn containing X. If we replace a REG
2619 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2620 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2621 the REG is being modified.
2623 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2624 That's used when we eliminate in expressions stored in notes.
2625 This means, do not set ref_outside_mem even if the reference
2628 If we see a modification to a register we know about, take the
2629 appropriate action (see case SET, below).
2631 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2632 replacements done assuming all offsets are at their initial values. If
2633 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2634 encounter, return the actual location so that find_reloads will do
2635 the proper thing. */
2638 eliminate_regs (x, mem_mode, insn)
2640 enum machine_mode mem_mode;
2643 enum rtx_code code = GET_CODE (x);
2644 struct elim_table *ep;
2651 /* We can reach here without reload being run if we have an variable
2652 definition in a file with no functions (for exmaple). Ensure we
2653 have a valid elimination table in such cases. */
2654 if (reg_eliminate == NULL)
2673 /* This is only for the benefit of the debugging backends, which call
2674 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2675 removed after CSE. */
2676 new = eliminate_regs (XEXP (x, 0), 0, insn);
2677 if (GET_CODE (new) == MEM)
2678 return XEXP (new, 0);
2684 /* First handle the case where we encounter a bare register that
2685 is eliminable. Replace it with a PLUS. */
2686 if (regno < FIRST_PSEUDO_REGISTER)
2688 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2690 if (ep->from_rtx == x && ep->can_eliminate)
2693 /* Refs inside notes don't count for this purpose. */
2694 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2695 || GET_CODE (insn) == INSN_LIST)))
2696 ep->ref_outside_mem = 1;
2697 return plus_constant (ep->to_rtx, ep->previous_offset);
2704 /* If this is the sum of an eliminable register and a constant, rework
2706 if (GET_CODE (XEXP (x, 0)) == REG
2707 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2708 && CONSTANT_P (XEXP (x, 1)))
2710 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2712 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2715 /* Refs inside notes don't count for this purpose. */
2716 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2717 || GET_CODE (insn) == INSN_LIST)))
2718 ep->ref_outside_mem = 1;
2720 /* The only time we want to replace a PLUS with a REG (this
2721 occurs when the constant operand of the PLUS is the negative
2722 of the offset) is when we are inside a MEM. We won't want
2723 to do so at other times because that would change the
2724 structure of the insn in a way that reload can't handle.
2725 We special-case the commonest situation in
2726 eliminate_regs_in_insn, so just replace a PLUS with a
2727 PLUS here, unless inside a MEM. */
2728 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2729 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2732 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2733 plus_constant (XEXP (x, 1),
2734 ep->previous_offset));
2737 /* If the register is not eliminable, we are done since the other
2738 operand is a constant. */
2742 /* If this is part of an address, we want to bring any constant to the
2743 outermost PLUS. We will do this by doing register replacement in
2744 our operands and seeing if a constant shows up in one of them.
2746 We assume here this is part of an address (or a "load address" insn)
2747 since an eliminable register is not likely to appear in any other
2750 If we have (plus (eliminable) (reg)), we want to produce
2751 (plus (plus (replacement) (reg) (const))). If this was part of a
2752 normal add insn, (plus (replacement) (reg)) will be pushed as a
2753 reload. This is the desired action. */
2756 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2757 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2759 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2761 /* If one side is a PLUS and the other side is a pseudo that
2762 didn't get a hard register but has a reg_equiv_constant,
2763 we must replace the constant here since it may no longer
2764 be in the position of any operand. */
2765 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2766 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2767 && reg_renumber[REGNO (new1)] < 0
2768 && reg_equiv_constant != 0
2769 && reg_equiv_constant[REGNO (new1)] != 0)
2770 new1 = reg_equiv_constant[REGNO (new1)];
2771 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2772 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2773 && reg_renumber[REGNO (new0)] < 0
2774 && reg_equiv_constant[REGNO (new0)] != 0)
2775 new0 = reg_equiv_constant[REGNO (new0)];
2777 new = form_sum (new0, new1);
2779 /* As above, if we are not inside a MEM we do not want to
2780 turn a PLUS into something else. We might try to do so here
2781 for an addition of 0 if we aren't optimizing. */
2782 if (! mem_mode && GET_CODE (new) != PLUS)
2783 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2791 /* If this is the product of an eliminable register and a
2792 constant, apply the distribute law and move the constant out
2793 so that we have (plus (mult ..) ..). This is needed in order
2794 to keep load-address insns valid. This case is pathological.
2795 We ignore the possibility of overflow here. */
2796 if (GET_CODE (XEXP (x, 0)) == REG
2797 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2798 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2799 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2801 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2804 /* Refs inside notes don't count for this purpose. */
2805 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2806 || GET_CODE (insn) == INSN_LIST)))
2807 ep->ref_outside_mem = 1;
2810 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2811 ep->previous_offset * INTVAL (XEXP (x, 1)));
2814 /* ... fall through ... */
2819 case DIV: case UDIV:
2820 case MOD: case UMOD:
2821 case AND: case IOR: case XOR:
2822 case ROTATERT: case ROTATE:
2823 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2825 case GE: case GT: case GEU: case GTU:
2826 case LE: case LT: case LEU: case LTU:
2828 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2830 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2832 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2833 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2838 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2841 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2842 if (new != XEXP (x, 0))
2843 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2846 /* ... fall through ... */
2849 /* Now do eliminations in the rest of the chain. If this was
2850 an EXPR_LIST, this might result in allocating more memory than is
2851 strictly needed, but it simplifies the code. */
2854 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2855 if (new != XEXP (x, 1))
2856 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2864 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2865 if (ep->to_rtx == XEXP (x, 0))
2867 int size = GET_MODE_SIZE (mem_mode);
2869 /* If more bytes than MEM_MODE are pushed, account for them. */
2870 #ifdef PUSH_ROUNDING
2871 if (ep->to_rtx == stack_pointer_rtx)
2872 size = PUSH_ROUNDING (size);
2874 if (code == PRE_DEC || code == POST_DEC)
2880 /* Fall through to generic unary operation case. */
2881 case STRICT_LOW_PART:
2883 case SIGN_EXTEND: case ZERO_EXTEND:
2884 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2885 case FLOAT: case FIX:
2886 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2890 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2891 if (new != XEXP (x, 0))
2892 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2896 /* Similar to above processing, but preserve SUBREG_WORD.
2897 Convert (subreg (mem)) to (mem) if not paradoxical.
2898 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2899 pseudo didn't get a hard reg, we must replace this with the
2900 eliminated version of the memory location because push_reloads
2901 may do the replacement in certain circumstances. */
2902 if (GET_CODE (SUBREG_REG (x)) == REG
2903 && (GET_MODE_SIZE (GET_MODE (x))
2904 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2905 && reg_equiv_memory_loc != 0
2906 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2909 new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
2912 /* If we didn't change anything, we must retain the pseudo. */
2913 if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
2914 new = SUBREG_REG (x);
2917 /* In this case, we must show that the pseudo is used in this
2918 insn so that delete_output_reload will do the right thing. */
2919 if (insn != 0 && GET_CODE (insn) != EXPR_LIST
2920 && GET_CODE (insn) != INSN_LIST)
2921 REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode,
2924 = gen_rtx_EXPR_LIST (REG_EQUAL, new, NULL_RTX);
2926 /* Ensure NEW isn't shared in case we have to reload it. */
2927 new = copy_rtx (new);
2930 new = SUBREG_REG (x);
2934 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2936 if (new != XEXP (x, 0))
2938 int x_size = GET_MODE_SIZE (GET_MODE (x));
2939 int new_size = GET_MODE_SIZE (GET_MODE (new));
2941 if (GET_CODE (new) == MEM
2942 && ((x_size < new_size
2943 #ifdef WORD_REGISTER_OPERATIONS
2944 /* On these machines, combine can create rtl of the form
2945 (set (subreg:m1 (reg:m2 R) 0) ...)
2946 where m1 < m2, and expects something interesting to
2947 happen to the entire word. Moreover, it will use the
2948 (reg:m2 R) later, expecting all bits to be preserved.
2949 So if the number of words is the same, preserve the
2950 subreg so that push_reloads can see it. */
2951 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
2954 || (x_size == new_size))
2957 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2958 enum machine_mode mode = GET_MODE (x);
2960 if (BYTES_BIG_ENDIAN)
2961 offset += (MIN (UNITS_PER_WORD,
2962 GET_MODE_SIZE (GET_MODE (new)))
2963 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2965 PUT_MODE (new, mode);
2966 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2970 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
2976 /* If using a register that is the source of an eliminate we still
2977 think can be performed, note it cannot be performed since we don't
2978 know how this register is used. */
2979 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2980 if (ep->from_rtx == XEXP (x, 0))
2981 ep->can_eliminate = 0;
2983 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2984 if (new != XEXP (x, 0))
2985 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2989 /* If clobbering a register that is the replacement register for an
2990 elimination we still think can be performed, note that it cannot
2991 be performed. Otherwise, we need not be concerned about it. */
2992 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2993 if (ep->to_rtx == XEXP (x, 0))
2994 ep->can_eliminate = 0;
2996 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2997 if (new != XEXP (x, 0))
2998 return gen_rtx_fmt_e (code, GET_MODE (x), new);
3004 /* Properly handle sharing input and constraint vectors. */
3005 if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
3007 /* When we come to a new vector not seen before,
3008 scan all its elements; keep the old vector if none
3009 of them changes; otherwise, make a copy. */
3010 old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
3011 temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
3012 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3013 temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
3016 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3017 if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
3020 if (i == ASM_OPERANDS_INPUT_LENGTH (x))
3021 new_asm_operands_vec = old_asm_operands_vec;
3023 new_asm_operands_vec
3024 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
3027 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
3028 if (new_asm_operands_vec == old_asm_operands_vec)
3031 new = gen_rtx_ASM_OPERANDS (VOIDmode, ASM_OPERANDS_TEMPLATE (x),
3032 ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
3033 ASM_OPERANDS_OUTPUT_IDX (x),
3034 new_asm_operands_vec,
3035 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
3036 ASM_OPERANDS_SOURCE_FILE (x),
3037 ASM_OPERANDS_SOURCE_LINE (x));
3038 new->volatil = x->volatil;
3043 /* Check for setting a register that we know about. */
3044 if (GET_CODE (SET_DEST (x)) == REG)
3046 /* See if this is setting the replacement register for an
3049 If DEST is the hard frame pointer, we do nothing because we
3050 assume that all assignments to the frame pointer are for
3051 non-local gotos and are being done at a time when they are valid
3052 and do not disturb anything else. Some machines want to
3053 eliminate a fake argument pointer (or even a fake frame pointer)
3054 with either the real frame or the stack pointer. Assignments to
3055 the hard frame pointer must not prevent this elimination. */
3057 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3059 if (ep->to_rtx == SET_DEST (x)
3060 && SET_DEST (x) != hard_frame_pointer_rtx)
3062 /* If it is being incremented, adjust the offset. Otherwise,
3063 this elimination can't be done. */
3064 rtx src = SET_SRC (x);
3066 if (GET_CODE (src) == PLUS
3067 && XEXP (src, 0) == SET_DEST (x)
3068 && GET_CODE (XEXP (src, 1)) == CONST_INT)
3069 ep->offset -= INTVAL (XEXP (src, 1));
3071 ep->can_eliminate = 0;
3074 /* Now check to see we are assigning to a register that can be
3075 eliminated. If so, it must be as part of a PARALLEL, since we
3076 will not have been called if this is a single SET. So indicate
3077 that we can no longer eliminate this reg. */
3078 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3080 if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
3081 ep->can_eliminate = 0;
3084 /* Now avoid the loop below in this common case. */
3086 rtx new0 = eliminate_regs (SET_DEST (x), 0, insn);
3087 rtx new1 = eliminate_regs (SET_SRC (x), 0, insn);
3089 /* If SET_DEST changed from a REG to a MEM and INSN is an insn,
3090 write a CLOBBER insn. */
3091 if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
3092 && insn != 0 && GET_CODE (insn) != EXPR_LIST
3093 && GET_CODE (insn) != INSN_LIST)
3094 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, SET_DEST (x)), insn);
3096 if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
3097 return gen_rtx_SET (VOIDmode, new0, new1);
3103 /* This is only for the benefit of the debugging backends, which call
3104 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
3105 removed after CSE. */
3106 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
3107 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
3109 /* Our only special processing is to pass the mode of the MEM to our
3110 recursive call and copy the flags. While we are here, handle this
3111 case more efficiently. */
3112 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
3113 if (new != XEXP (x, 0))
3115 new = gen_rtx_MEM (GET_MODE (x), new);
3116 new->volatil = x->volatil;
3117 new->unchanging = x->unchanging;
3118 new->in_struct = x->in_struct;
3128 /* Process each of our operands recursively. If any have changed, make a
3130 fmt = GET_RTX_FORMAT (code);
3131 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3135 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
3136 if (new != XEXP (x, i) && ! copied)
3138 rtx new_x = rtx_alloc (code);
3139 bcopy ((char *) x, (char *) new_x,
3140 (sizeof (*new_x) - sizeof (new_x->fld)
3141 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
3147 else if (*fmt == 'E')
3150 for (j = 0; j < XVECLEN (x, i); j++)
3152 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
3153 if (new != XVECEXP (x, i, j) && ! copied_vec)
3155 rtvec new_v = gen_rtvec_vv (XVECLEN (x, i),
3159 rtx new_x = rtx_alloc (code);
3160 bcopy ((char *) x, (char *) new_x,
3161 (sizeof (*new_x) - sizeof (new_x->fld)
3162 + (sizeof (new_x->fld[0])
3163 * GET_RTX_LENGTH (code))));
3167 XVEC (x, i) = new_v;
3170 XVECEXP (x, i, j) = new;
3178 /* Scan INSN and eliminate all eliminable registers in it.
3180 If REPLACE is nonzero, do the replacement destructively. Also
3181 delete the insn as dead it if it is setting an eliminable register.
3183 If REPLACE is zero, do all our allocations in reload_obstack.
3185 If no eliminations were done and this insn doesn't require any elimination
3186 processing (these are not identical conditions: it might be updating sp,
3187 but not referencing fp; this needs to be seen during reload_as_needed so
3188 that the offset between fp and sp can be taken into consideration), zero
3189 is returned. Otherwise, 1 is returned. */
3192 eliminate_regs_in_insn (insn, replace)
3196 rtx old_body = PATTERN (insn);
3197 rtx old_set = single_set (insn);
3200 struct elim_table *ep;
3203 push_obstacks (&reload_obstack, &reload_obstack);
3205 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
3206 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3208 /* Check for setting an eliminable register. */
3209 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3210 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3212 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3213 /* If this is setting the frame pointer register to the
3214 hardware frame pointer register and this is an elimination
3215 that will be done (tested above), this insn is really
3216 adjusting the frame pointer downward to compensate for
3217 the adjustment done before a nonlocal goto. */
3218 if (ep->from == FRAME_POINTER_REGNUM
3219 && ep->to == HARD_FRAME_POINTER_REGNUM)
3221 rtx src = SET_SRC (old_set);
3223 rtx prev_insn, prev_set;
3225 if (src == ep->to_rtx)
3227 else if (GET_CODE (src) == PLUS
3228 && GET_CODE (XEXP (src, 0)) == CONST_INT
3229 && XEXP (src, 1) == ep->to_rtx)
3230 offset = INTVAL (XEXP (src, 0)), ok = 1;
3231 else if (GET_CODE (src) == PLUS
3232 && GET_CODE (XEXP (src, 1)) == CONST_INT
3233 && XEXP (src, 0) == ep->to_rtx)
3234 offset = INTVAL (XEXP (src, 1)), ok = 1;
3235 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
3236 && (prev_set = single_set (prev_insn)) != 0
3237 && rtx_equal_p (SET_DEST (prev_set), src))
3239 src = SET_SRC (prev_set);
3240 if (src == ep->to_rtx)
3242 else if (GET_CODE (src) == PLUS
3243 && GET_CODE (XEXP (src, 0)) == CONST_INT
3244 && XEXP (src, 1) == ep->to_rtx)
3245 offset = INTVAL (XEXP (src, 0)), ok = 1;
3246 else if (GET_CODE (src) == PLUS
3247 && GET_CODE (XEXP (src, 1)) == CONST_INT
3248 && XEXP (src, 0) == ep->to_rtx)
3249 offset = INTVAL (XEXP (src, 1)), ok = 1;
3257 = plus_constant (ep->to_rtx, offset - ep->offset);
3259 /* First see if this insn remains valid when we
3260 make the change. If not, keep the INSN_CODE
3261 the same and let reload fit it up. */
3262 validate_change (insn, &SET_SRC (old_set), src, 1);
3263 validate_change (insn, &SET_DEST (old_set),
3265 if (! apply_change_group ())
3267 SET_SRC (old_set) = src;
3268 SET_DEST (old_set) = ep->to_rtx;
3278 /* In this case this insn isn't serving a useful purpose. We
3279 will delete it in reload_as_needed once we know that this
3280 elimination is, in fact, being done.
3282 If REPLACE isn't set, we can't delete this insn, but needn't
3283 process it since it won't be used unless something changes. */
3285 delete_dead_insn (insn);
3290 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3291 in the insn is the negative of the offset in FROM. Substitute
3292 (set (reg) (reg to)) for the insn and change its code.
3294 We have to do this here, rather than in eliminate_regs, so that we can
3295 change the insn code. */
3297 if (GET_CODE (SET_SRC (old_set)) == PLUS
3298 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3299 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT)
3300 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3302 if (ep->from_rtx == XEXP (SET_SRC (old_set), 0)
3303 && ep->can_eliminate)
3305 /* We must stop at the first elimination that will be used.
3306 If this one would replace the PLUS with a REG, do it
3307 now. Otherwise, quit the loop and let eliminate_regs
3308 do its normal replacement. */
3309 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_set), 1)))
3311 /* We assume here that we don't need a PARALLEL of
3312 any CLOBBERs for this assignment. There's not
3313 much we can do if we do need it. */
3314 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3317 INSN_CODE (insn) = -1;
3326 old_asm_operands_vec = 0;
3328 /* Replace the body of this insn with a substituted form. If we changed
3329 something, return non-zero.
3331 If we are replacing a body that was a (set X (plus Y Z)), try to
3332 re-recognize the insn. We do this in case we had a simple addition
3333 but now can do this as a load-address. This saves an insn in this
3336 new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX);
3337 if (new_body != old_body)
3339 /* If we aren't replacing things permanently and we changed something,
3340 make another copy to ensure that all the RTL is new. Otherwise
3341 things can go wrong if find_reload swaps commutative operands
3342 and one is inside RTL that has been copied while the other is not. */
3344 /* Don't copy an asm_operands because (1) there's no need and (2)
3345 copy_rtx can't do it properly when there are multiple outputs. */
3346 if (! replace && asm_noperands (old_body) < 0)
3347 new_body = copy_rtx (new_body);
3349 /* If we had a move insn but now we don't, rerecognize it. This will
3350 cause spurious re-recognition if the old move had a PARALLEL since
3351 the new one still will, but we can't call single_set without
3352 having put NEW_BODY into the insn and the re-recognition won't
3353 hurt in this rare case. */
3355 && ((GET_CODE (SET_SRC (old_set)) == REG
3356 && (GET_CODE (new_body) != SET
3357 || GET_CODE (SET_SRC (new_body)) != REG))
3358 /* If this was a load from or store to memory, compare
3359 the MEM in recog_operand to the one in the insn. If they
3360 are not equal, then rerecognize the insn. */
3362 && ((GET_CODE (SET_SRC (old_set)) == MEM
3363 && SET_SRC (old_set) != recog_operand[1])
3364 || (GET_CODE (SET_DEST (old_set)) == MEM
3365 && SET_DEST (old_set) != recog_operand[0])))
3366 /* If this was an add insn before, rerecognize. */
3367 || GET_CODE (SET_SRC (old_set)) == PLUS))
3369 if (! validate_change (insn, &PATTERN (insn), new_body, 0))
3370 /* If recognition fails, store the new body anyway.
3371 It's normal to have recognition failures here
3372 due to bizarre memory addresses; reloading will fix them. */
3373 PATTERN (insn) = new_body;
3376 PATTERN (insn) = new_body;
3381 /* Loop through all elimination pairs. See if any have changed.
3383 We also detect a cases where register elimination cannot be done,
3384 namely, if a register would be both changed and referenced outside a MEM
3385 in the resulting insn since such an insn is often undefined and, even if
3386 not, we cannot know what meaning will be given to it. Note that it is
3387 valid to have a register used in an address in an insn that changes it
3388 (presumably with a pre- or post-increment or decrement).
3390 If anything changes, return nonzero. */
3392 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3394 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3395 ep->can_eliminate = 0;
3397 ep->ref_outside_mem = 0;
3399 if (ep->previous_offset != ep->offset)
3404 /* If we changed something, perform elimination in REG_NOTES. This is
3405 needed even when REPLACE is zero because a REG_DEAD note might refer
3406 to a register that we eliminate and could cause a different number
3407 of spill registers to be needed in the final reload pass than in
3409 if (val && REG_NOTES (insn) != 0)
3410 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3418 /* Loop through all elimination pairs.
3419 Recalculate the number not at initial offset.
3421 Compute the maximum offset (minimum offset if the stack does not
3422 grow downward) for each elimination pair. */
3425 update_eliminable_offsets ()
3427 struct elim_table *ep;
3429 num_not_at_initial_offset = 0;
3430 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3432 ep->previous_offset = ep->offset;
3433 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3434 num_not_at_initial_offset++;
3438 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3439 replacement we currently believe is valid, mark it as not eliminable if X
3440 modifies DEST in any way other than by adding a constant integer to it.
3442 If DEST is the frame pointer, we do nothing because we assume that
3443 all assignments to the hard frame pointer are nonlocal gotos and are being
3444 done at a time when they are valid and do not disturb anything else.
3445 Some machines want to eliminate a fake argument pointer with either the
3446 frame or stack pointer. Assignments to the hard frame pointer must not
3447 prevent this elimination.
3449 Called via note_stores from reload before starting its passes to scan
3450 the insns of the function. */
3453 mark_not_eliminable (dest, x)
3457 register unsigned int i;
3459 /* A SUBREG of a hard register here is just changing its mode. We should
3460 not see a SUBREG of an eliminable hard register, but check just in
3462 if (GET_CODE (dest) == SUBREG)
3463 dest = SUBREG_REG (dest);
3465 if (dest == hard_frame_pointer_rtx)
3468 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3469 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3470 && (GET_CODE (x) != SET
3471 || GET_CODE (SET_SRC (x)) != PLUS
3472 || XEXP (SET_SRC (x), 0) != dest
3473 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3475 reg_eliminate[i].can_eliminate_previous
3476 = reg_eliminate[i].can_eliminate = 0;
3481 /* Verify that the initial elimination offsets did not change since the
3482 last call to set_initial_elim_offsets. This is used to catch cases
3483 where something illegal happened during reload_as_needed that could
3484 cause incorrect code to be generated if we did not check for it. */
3486 verify_initial_elim_offsets ()
3490 #ifdef ELIMINABLE_REGS
3491 struct elim_table *ep;
3493 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3495 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3496 if (t != ep->initial_offset)
3500 INITIAL_FRAME_POINTER_OFFSET (t);
3501 if (t != reg_eliminate[0].initial_offset)
3506 /* Reset all offsets on eliminable registers to their initial values. */
3508 set_initial_elim_offsets ()
3510 struct elim_table *ep = reg_eliminate;
3512 #ifdef ELIMINABLE_REGS
3513 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3515 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3516 ep->previous_offset = ep->offset = ep->initial_offset;
3519 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3520 ep->previous_offset = ep->offset = ep->initial_offset;
3523 num_not_at_initial_offset = 0;
3526 /* Initialize the known label offsets.
3527 Set a known offset for each forced label to be at the initial offset
3528 of each elimination. We do this because we assume that all
3529 computed jumps occur from a location where each elimination is
3530 at its initial offset.
3531 For all other labels, show that we don't know the offsets. */
3534 set_initial_label_offsets ()
3537 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
3539 for (x = forced_labels; x; x = XEXP (x, 1))
3541 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3544 /* Set all elimination offsets to the known values for the code label given
3547 set_offsets_for_label (insn)
3551 int label_nr = CODE_LABEL_NUMBER (insn);
3552 struct elim_table *ep;
3554 num_not_at_initial_offset = 0;
3555 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3557 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3558 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3559 num_not_at_initial_offset++;
3563 /* See if anything that happened changes which eliminations are valid.
3564 For example, on the Sparc, whether or not the frame pointer can
3565 be eliminated can depend on what registers have been used. We need
3566 not check some conditions again (such as flag_omit_frame_pointer)
3567 since they can't have changed. */
3570 update_eliminables (pset)
3573 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3574 int previous_frame_pointer_needed = frame_pointer_needed;
3576 struct elim_table *ep;
3578 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3579 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3580 #ifdef ELIMINABLE_REGS
3581 || ! CAN_ELIMINATE (ep->from, ep->to)
3584 ep->can_eliminate = 0;
3586 /* Look for the case where we have discovered that we can't replace
3587 register A with register B and that means that we will now be
3588 trying to replace register A with register C. This means we can
3589 no longer replace register C with register B and we need to disable
3590 such an elimination, if it exists. This occurs often with A == ap,
3591 B == sp, and C == fp. */
3593 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3595 struct elim_table *op;
3596 register int new_to = -1;
3598 if (! ep->can_eliminate && ep->can_eliminate_previous)
3600 /* Find the current elimination for ep->from, if there is a
3602 for (op = reg_eliminate;
3603 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3604 if (op->from == ep->from && op->can_eliminate)
3610 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3612 for (op = reg_eliminate;
3613 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3614 if (op->from == new_to && op->to == ep->to)
3615 op->can_eliminate = 0;
3619 /* See if any registers that we thought we could eliminate the previous
3620 time are no longer eliminable. If so, something has changed and we
3621 must spill the register. Also, recompute the number of eliminable
3622 registers and see if the frame pointer is needed; it is if there is
3623 no elimination of the frame pointer that we can perform. */
3625 frame_pointer_needed = 1;
3626 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3628 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3629 && ep->to != HARD_FRAME_POINTER_REGNUM)
3630 frame_pointer_needed = 0;
3632 if (! ep->can_eliminate && ep->can_eliminate_previous)
3634 ep->can_eliminate_previous = 0;
3635 SET_HARD_REG_BIT (*pset, ep->from);
3640 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3641 /* If we didn't need a frame pointer last time, but we do now, spill
3642 the hard frame pointer. */
3643 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3644 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3648 /* Initialize the table of registers to eliminate. */
3652 struct elim_table *ep;
3653 #ifdef ELIMINABLE_REGS
3654 struct elim_table_1 *ep1;
3659 reg_eliminate = (struct elim_table *)
3660 xmalloc(sizeof(struct elim_table) * NUM_ELIMINABLE_REGS);
3661 bzero ((PTR) reg_eliminate,
3662 sizeof(struct elim_table) * NUM_ELIMINABLE_REGS);
3665 /* Does this function require a frame pointer? */
3667 frame_pointer_needed = (! flag_omit_frame_pointer
3668 #ifdef EXIT_IGNORE_STACK
3669 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3670 and restore sp for alloca. So we can't eliminate
3671 the frame pointer in that case. At some point,
3672 we should improve this by emitting the
3673 sp-adjusting insns for this case. */
3674 || (current_function_calls_alloca
3675 && EXIT_IGNORE_STACK)
3677 || FRAME_POINTER_REQUIRED);
3681 #ifdef ELIMINABLE_REGS
3682 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3683 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3685 ep->from = ep1->from;
3687 ep->can_eliminate = ep->can_eliminate_previous
3688 = (CAN_ELIMINATE (ep->from, ep->to)
3689 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3692 reg_eliminate[0].from = reg_eliminate_1[0].from;
3693 reg_eliminate[0].to = reg_eliminate_1[0].to;
3694 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3695 = ! frame_pointer_needed;
3698 /* Count the number of eliminable registers and build the FROM and TO
3699 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3700 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3701 We depend on this. */
3702 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3704 num_eliminable += ep->can_eliminate;
3705 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3706 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3710 /* Kick all pseudos out of hard register REGNO.
3711 If DUMPFILE is nonzero, log actions taken on that file.
3713 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3714 because we found we can't eliminate some register. In the case, no pseudos
3715 are allowed to be in the register, even if they are only in a block that
3716 doesn't require spill registers, unlike the case when we are spilling this
3717 hard reg to produce another spill register.
3719 Return nonzero if any pseudos needed to be kicked out. */
3722 spill_hard_reg (regno, dumpfile, cant_eliminate)
3731 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3732 regs_ever_live[regno] = 1;
3735 /* Spill every pseudo reg that was allocated to this reg
3736 or to something that overlaps this reg. */
3738 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3739 if (reg_renumber[i] >= 0
3740 && reg_renumber[i] <= regno
3742 + HARD_REGNO_NREGS (reg_renumber[i],
3743 PSEUDO_REGNO_MODE (i))
3745 SET_REGNO_REG_SET (spilled_pseudos, i);
3748 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3749 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3751 ior_hard_reg_set (set1, set2)
3752 HARD_REG_SET *set1, *set2;
3754 IOR_HARD_REG_SET (*set1, *set2);
3757 /* After find_reload_regs has been run for all insn that need reloads,
3758 and/or spill_hard_regs was called, this function is used to actually
3759 spill pseudo registers and try to reallocate them. It also sets up the
3760 spill_regs array for use by choose_reload_regs. */
3763 finish_spills (global, dumpfile)
3767 struct insn_chain *chain;
3768 int something_changed = 0;
3771 /* Build the spill_regs array for the function. */
3772 /* If there are some registers still to eliminate and one of the spill regs
3773 wasn't ever used before, additional stack space may have to be
3774 allocated to store this register. Thus, we may have changed the offset
3775 between the stack and frame pointers, so mark that something has changed.
3777 One might think that we need only set VAL to 1 if this is a call-used
3778 register. However, the set of registers that must be saved by the
3779 prologue is not identical to the call-used set. For example, the
3780 register used by the call insn for the return PC is a call-used register,
3781 but must be saved by the prologue. */
3784 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3785 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3787 spill_reg_order[i] = n_spills;
3788 spill_regs[n_spills++] = i;
3789 if (num_eliminable && ! regs_ever_live[i])
3790 something_changed = 1;
3791 regs_ever_live[i] = 1;
3794 spill_reg_order[i] = -1;
3796 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3797 if (REGNO_REG_SET_P (spilled_pseudos, i))
3799 /* Record the current hard register the pseudo is allocated to in
3800 pseudo_previous_regs so we avoid reallocating it to the same
3801 hard reg in a later pass. */
3802 if (reg_renumber[i] < 0)
3804 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3805 /* Mark it as no longer having a hard register home. */
3806 reg_renumber[i] = -1;
3807 /* We will need to scan everything again. */
3808 something_changed = 1;
3811 /* Retry global register allocation if possible. */
3814 bzero ((char *) pseudo_forbidden_regs, max_regno * sizeof (HARD_REG_SET));
3815 /* For every insn that needs reloads, set the registers used as spill
3816 regs in pseudo_forbidden_regs for every pseudo live across the
3818 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3820 EXECUTE_IF_SET_IN_REG_SET
3821 (chain->live_before, FIRST_PSEUDO_REGISTER, i,
3823 ior_hard_reg_set (pseudo_forbidden_regs + i,
3824 &chain->used_spill_regs);
3826 EXECUTE_IF_SET_IN_REG_SET
3827 (chain->live_after, FIRST_PSEUDO_REGISTER, i,
3829 ior_hard_reg_set (pseudo_forbidden_regs + i,
3830 &chain->used_spill_regs);
3834 /* Retry allocating the spilled pseudos. For each reg, merge the
3835 various reg sets that indicate which hard regs can't be used,
3836 and call retry_global_alloc.
3837 We change spill_pseudos here to only contain pseudos that did not
3838 get a new hard register. */
3839 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3840 if (reg_old_renumber[i] != reg_renumber[i])
3842 HARD_REG_SET forbidden;
3843 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3844 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3845 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3846 retry_global_alloc (i, forbidden);
3847 if (reg_renumber[i] >= 0)
3848 CLEAR_REGNO_REG_SET (spilled_pseudos, i);
3852 /* Fix up the register information in the insn chain.
3853 This involves deleting those of the spilled pseudos which did not get
3854 a new hard register home from the live_{before,after} sets. */
3855 for (chain = reload_insn_chain; chain; chain = chain->next)
3857 HARD_REG_SET used_by_pseudos;
3858 HARD_REG_SET used_by_pseudos2;
3860 AND_COMPL_REG_SET (chain->live_before, spilled_pseudos);
3861 AND_COMPL_REG_SET (chain->live_after, spilled_pseudos);
3863 /* Mark any unallocated hard regs as available for spills. That
3864 makes inheritance work somewhat better. */
3865 if (chain->need_reload)
3867 REG_SET_TO_HARD_REG_SET (used_by_pseudos, chain->live_before);
3868 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, chain->live_after);
3869 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3871 /* Save the old value for the sanity test below. */
3872 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3874 compute_use_by_pseudos (&used_by_pseudos, chain->live_before);
3875 compute_use_by_pseudos (&used_by_pseudos, chain->live_after);
3876 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3877 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3879 /* Make sure we only enlarge the set. */
3880 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3886 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3887 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3889 int regno = reg_renumber[i];
3890 if (reg_old_renumber[i] == regno)
3893 alter_reg (i, reg_old_renumber[i]);
3894 reg_old_renumber[i] = regno;
3898 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3900 fprintf (dumpfile, " Register %d now in %d.\n\n",
3901 i, reg_renumber[i]);
3905 return something_changed;
3908 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3909 Also mark any hard registers used to store user variables as
3910 forbidden from being used for spill registers. */
3913 scan_paradoxical_subregs (x)
3918 register enum rtx_code code = GET_CODE (x);
3924 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3925 && REG_USERVAR_P (x))
3926 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3942 if (GET_CODE (SUBREG_REG (x)) == REG
3943 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3944 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3945 = GET_MODE_SIZE (GET_MODE (x));
3952 fmt = GET_RTX_FORMAT (code);
3953 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3956 scan_paradoxical_subregs (XEXP (x, i));
3957 else if (fmt[i] == 'E')
3960 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3961 scan_paradoxical_subregs (XVECEXP (x, i, j));
3967 hard_reg_use_compare (p1p, p2p)
3968 const GENERIC_PTR p1p;
3969 const GENERIC_PTR p2p;
3971 struct hard_reg_n_uses *p1 = (struct hard_reg_n_uses *)p1p;
3972 struct hard_reg_n_uses *p2 = (struct hard_reg_n_uses *)p2p;
3973 int bad1 = TEST_HARD_REG_BIT (bad_spill_regs, p1->regno);
3974 int bad2 = TEST_HARD_REG_BIT (bad_spill_regs, p2->regno);
3976 return p1->regno - p2->regno;
3981 if (p1->uses > p2->uses)
3983 if (p1->uses < p2->uses)
3985 /* If regs are equally good, sort by regno,
3986 so that the results of qsort leave nothing to chance. */
3987 return p1->regno - p2->regno;
3990 /* Used for communication between order_regs_for_reload and count_pseudo.
3991 Used to avoid counting one pseudo twice. */
3992 static regset pseudos_counted;
3994 /* Update the costs in N_USES, considering that pseudo REG is live. */
3996 count_pseudo (n_uses, reg)
3997 struct hard_reg_n_uses *n_uses;
4000 int r = reg_renumber[reg];
4003 if (REGNO_REG_SET_P (pseudos_counted, reg))
4005 SET_REGNO_REG_SET (pseudos_counted, reg);
4010 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
4012 n_uses[r++].uses += REG_N_REFS (reg);
4014 /* Choose the order to consider regs for use as reload registers
4015 based on how much trouble would be caused by spilling one.
4016 Store them in order of decreasing preference in potential_reload_regs. */
4019 order_regs_for_reload (chain)
4020 struct insn_chain *chain;
4024 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
4026 pseudos_counted = ALLOCA_REG_SET ();
4028 COPY_HARD_REG_SET (bad_spill_regs, bad_spill_regs_global);
4030 /* Count number of uses of each hard reg by pseudo regs allocated to it
4031 and then order them by decreasing use. */
4033 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4037 hard_reg_n_uses[i].regno = i;
4038 hard_reg_n_uses[i].uses = 0;
4040 /* Test the various reasons why we can't use a register for
4041 spilling in this insn. */
4043 || REGNO_REG_SET_P (chain->live_before, i)
4044 || REGNO_REG_SET_P (chain->live_after, i))
4046 SET_HARD_REG_BIT (bad_spill_regs, i);
4050 /* Now find out which pseudos are allocated to it, and update
4052 CLEAR_REG_SET (pseudos_counted);
4054 EXECUTE_IF_SET_IN_REG_SET
4055 (chain->live_before, FIRST_PSEUDO_REGISTER, j,
4057 count_pseudo (hard_reg_n_uses, j);
4059 EXECUTE_IF_SET_IN_REG_SET
4060 (chain->live_after, FIRST_PSEUDO_REGISTER, j,
4062 count_pseudo (hard_reg_n_uses, j);
4066 FREE_REG_SET (pseudos_counted);
4068 /* Prefer registers not so far used, for use in temporary loading.
4069 Among them, if REG_ALLOC_ORDER is defined, use that order.
4070 Otherwise, prefer registers not preserved by calls. */
4072 #ifdef REG_ALLOC_ORDER
4073 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4075 int regno = reg_alloc_order[i];
4077 if (hard_reg_n_uses[regno].uses == 0
4078 && ! TEST_HARD_REG_BIT (bad_spill_regs, regno))
4079 potential_reload_regs[o++] = regno;
4082 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4084 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i]
4085 && ! TEST_HARD_REG_BIT (bad_spill_regs, i))
4086 potential_reload_regs[o++] = i;
4088 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4090 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i]
4091 && ! TEST_HARD_REG_BIT (bad_spill_regs, i))
4092 potential_reload_regs[o++] = i;
4096 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
4097 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
4099 /* Now add the regs that are already used,
4100 preferring those used less often. The fixed and otherwise forbidden
4101 registers will be at the end of this list. */
4103 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4104 if (hard_reg_n_uses[i].uses != 0
4105 && ! TEST_HARD_REG_BIT (bad_spill_regs, hard_reg_n_uses[i].regno))
4106 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
4107 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4108 if (TEST_HARD_REG_BIT (bad_spill_regs, hard_reg_n_uses[i].regno))
4109 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
4112 /* Reload pseudo-registers into hard regs around each insn as needed.
4113 Additional register load insns are output before the insn that needs it
4114 and perhaps store insns after insns that modify the reloaded pseudo reg.
4116 reg_last_reload_reg and reg_reloaded_contents keep track of
4117 which registers are already available in reload registers.
4118 We update these for the reloads that we perform,
4119 as the insns are scanned. */
4122 reload_as_needed (live_known)
4125 struct insn_chain *chain;
4129 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
4130 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
4131 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
4132 bzero ((char *) reg_last_reload_reg, max_regno * sizeof (rtx));
4133 reg_has_output_reload = (char *) alloca (max_regno);
4134 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4136 set_initial_elim_offsets ();
4138 for (chain = reload_insn_chain; chain; chain = chain->next)
4141 rtx insn = chain->insn;
4142 rtx old_next = NEXT_INSN (insn);
4144 /* If we pass a label, copy the offsets from the label information
4145 into the current offsets of each elimination. */
4146 if (GET_CODE (insn) == CODE_LABEL)
4147 set_offsets_for_label (insn);
4149 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
4151 rtx oldpat = PATTERN (insn);
4153 /* If this is a USE and CLOBBER of a MEM, ensure that any
4154 references to eliminable registers have been removed. */
4156 if ((GET_CODE (PATTERN (insn)) == USE
4157 || GET_CODE (PATTERN (insn)) == CLOBBER)
4158 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
4159 XEXP (XEXP (PATTERN (insn), 0), 0)
4160 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4161 GET_MODE (XEXP (PATTERN (insn), 0)),
4164 /* If we need to do register elimination processing, do so.
4165 This might delete the insn, in which case we are done. */
4166 if (num_eliminable && chain->need_elim)
4168 eliminate_regs_in_insn (insn, 1);
4169 if (GET_CODE (insn) == NOTE)
4171 update_eliminable_offsets ();
4176 /* If need_elim is nonzero but need_reload is zero, one might think
4177 that we could simply set n_reloads to 0. However, find_reloads
4178 could have done some manipulation of the insn (such as swapping
4179 commutative operands), and these manipulations are lost during
4180 the first pass for every insn that needs register elimination.
4181 So the actions of find_reloads must be redone here. */
4183 if (! chain->need_elim && ! chain->need_reload
4184 && ! chain->need_operand_change)
4186 /* First find the pseudo regs that must be reloaded for this insn.
4187 This info is returned in the tables reload_... (see reload.h).
4188 Also modify the body of INSN by substituting RELOAD
4189 rtx's for those pseudo regs. */
4192 bzero (reg_has_output_reload, max_regno);
4193 CLEAR_HARD_REG_SET (reg_is_output_reload);
4195 find_reloads (insn, 1, spill_indirect_levels, live_known,
4199 if (num_eliminable && chain->need_elim)
4200 update_eliminable_offsets ();
4204 rtx next = NEXT_INSN (insn);
4207 prev = PREV_INSN (insn);
4209 /* Now compute which reload regs to reload them into. Perhaps
4210 reusing reload regs from previous insns, or else output
4211 load insns to reload them. Maybe output store insns too.
4212 Record the choices of reload reg in reload_reg_rtx. */
4213 choose_reload_regs (chain);
4215 /* Merge any reloads that we didn't combine for fear of
4216 increasing the number of spill registers needed but now
4217 discover can be safely merged. */
4218 if (SMALL_REGISTER_CLASSES)
4219 merge_assigned_reloads (insn);
4221 /* Generate the insns to reload operands into or out of
4222 their reload regs. */
4223 emit_reload_insns (chain);
4225 /* Substitute the chosen reload regs from reload_reg_rtx
4226 into the insn's body (or perhaps into the bodies of other
4227 load and store insn that we just made for reloading
4228 and that we moved the structure into). */
4231 /* If this was an ASM, make sure that all the reload insns
4232 we have generated are valid. If not, give an error
4235 if (asm_noperands (PATTERN (insn)) >= 0)
4236 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4237 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
4238 && (recog_memoized (p) < 0
4239 || (extract_insn (p), ! constrain_operands (1))))
4241 error_for_asm (insn,
4242 "`asm' operand requires impossible reload");
4244 NOTE_SOURCE_FILE (p) = 0;
4245 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
4248 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4249 is no longer validly lying around to save a future reload.
4250 Note that this does not detect pseudos that were reloaded
4251 for this insn in order to be stored in
4252 (obeying register constraints). That is correct; such reload
4253 registers ARE still valid. */
4254 note_stores (oldpat, forget_old_reloads_1);
4256 /* There may have been CLOBBER insns placed after INSN. So scan
4257 between INSN and NEXT and use them to forget old reloads. */
4258 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4259 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
4260 note_stores (PATTERN (x), forget_old_reloads_1);
4263 /* Likewise for regs altered by auto-increment in this insn.
4264 REG_INC notes have been changed by reloading:
4265 find_reloads_address_1 records substitutions for them,
4266 which have been performed by subst_reloads above. */
4267 for (i = n_reloads - 1; i >= 0; i--)
4269 rtx in_reg = reload_in_reg[i];
4272 enum rtx_code code = GET_CODE (in_reg);
4273 /* PRE_INC / PRE_DEC will have the reload register ending up
4274 with the same value as the stack slot, but that doesn't
4275 hold true for POST_INC / POST_DEC. Either we have to
4276 convert the memory access to a true POST_INC / POST_DEC,
4277 or we can't use the reload register for inheritance. */
4278 if ((code == POST_INC || code == POST_DEC)
4279 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4280 REGNO (reload_reg_rtx[i]))
4281 /* Make sure it is the inc/dec pseudo, and not
4282 some other (e.g. output operand) pseudo. */
4283 && (reg_reloaded_contents[REGNO (reload_reg_rtx[i])]
4284 == REGNO (XEXP (in_reg, 0))))
4287 rtx reload_reg = reload_reg_rtx[i];
4288 enum machine_mode mode = GET_MODE (reload_reg);
4292 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4294 /* We really want to ignore REG_INC notes here, so
4295 use PATTERN (p) as argument to reg_set_p . */
4296 if (reg_set_p (reload_reg, PATTERN (p)))
4298 n = count_occurrences (PATTERN (p), reload_reg);
4302 n = validate_replace_rtx (reload_reg,
4303 gen_rtx (code, mode,
4308 REG_NOTES (p) = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4311 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX);
4315 #if 0 /* ??? Is this code obsolete now? Need to check carefully. */
4316 /* Likewise for regs altered by auto-increment in this insn.
4317 But note that the reg-notes are not changed by reloading:
4318 they still contain the pseudo-regs, not the spill regs. */
4319 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4320 if (REG_NOTE_KIND (x) == REG_INC)
4322 /* See if this pseudo reg was reloaded in this insn.
4323 If so, its last-reload info is still valid
4324 because it is based on this insn's reload. */
4325 for (i = 0; i < n_reloads; i++)
4326 if (reload_out[i] == XEXP (x, 0))
4330 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX);
4335 /* A reload reg's contents are unknown after a label. */
4336 if (GET_CODE (insn) == CODE_LABEL)
4337 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4339 /* Don't assume a reload reg is still good after a call insn
4340 if it is a call-used reg. */
4341 else if (GET_CODE (insn) == CALL_INSN)
4342 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
4344 /* In case registers overlap, allow certain insns to invalidate
4345 particular hard registers. */
4347 #ifdef INSN_CLOBBERS_REGNO_P
4348 for (i = 0 ; i < FIRST_PSEUDO_REGISTER; i++)
4349 if (TEST_HARD_REG_BIT (reg_reloaded_valid, i)
4350 && INSN_CLOBBERS_REGNO_P (insn, i))
4351 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i);
4360 /* Discard all record of any value reloaded from X,
4361 or reloaded in X from someplace else;
4362 unless X is an output reload reg of the current insn.
4364 X may be a hard reg (the reload reg)
4365 or it may be a pseudo reg that was reloaded from. */
4368 forget_old_reloads_1 (x, ignored)
4370 rtx ignored ATTRIBUTE_UNUSED;
4376 /* note_stores does give us subregs of hard regs. */
4377 while (GET_CODE (x) == SUBREG)
4379 offset += SUBREG_WORD (x);
4383 if (GET_CODE (x) != REG)
4386 regno = REGNO (x) + offset;
4388 if (regno >= FIRST_PSEUDO_REGISTER)
4393 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4394 /* Storing into a spilled-reg invalidates its contents.
4395 This can happen if a block-local pseudo is allocated to that reg
4396 and it wasn't spilled because this block's total need is 0.
4397 Then some insn might have an optional reload and use this reg. */
4398 for (i = 0; i < nr; i++)
4399 /* But don't do this if the reg actually serves as an output
4400 reload reg in the current instruction. */
4402 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4403 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4406 /* Since value of X has changed,
4407 forget any value previously copied from it. */
4410 /* But don't forget a copy if this is the output reload
4411 that establishes the copy's validity. */
4412 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4413 reg_last_reload_reg[regno + nr] = 0;
4416 /* For each reload, the mode of the reload register. */
4417 static enum machine_mode reload_mode[MAX_RELOADS];
4419 /* For each reload, the largest number of registers it will require. */
4420 static int reload_nregs[MAX_RELOADS];
4422 /* Comparison function for qsort to decide which of two reloads
4423 should be handled first. *P1 and *P2 are the reload numbers. */
4426 reload_reg_class_lower (r1p, r2p)
4427 const GENERIC_PTR r1p;
4428 const GENERIC_PTR r2p;
4430 register int r1 = *(short *)r1p, r2 = *(short *)r2p;
4433 /* Consider required reloads before optional ones. */
4434 t = reload_optional[r1] - reload_optional[r2];
4438 /* Count all solitary classes before non-solitary ones. */
4439 t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
4440 - (reg_class_size[(int) reload_reg_class[r1]] == 1));
4444 /* Aside from solitaires, consider all multi-reg groups first. */
4445 t = reload_nregs[r2] - reload_nregs[r1];
4449 /* Consider reloads in order of increasing reg-class number. */
4450 t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
4454 /* If reloads are equally urgent, sort by reload number,
4455 so that the results of qsort leave nothing to chance. */
4459 /* The following HARD_REG_SETs indicate when each hard register is
4460 used for a reload of various parts of the current insn. */
4462 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4463 static HARD_REG_SET reload_reg_used;
4464 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4465 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4466 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4467 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4468 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4469 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4470 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4471 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4472 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4473 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4474 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4475 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4476 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4477 static HARD_REG_SET reload_reg_used_in_op_addr;
4478 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4479 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4480 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4481 static HARD_REG_SET reload_reg_used_in_insn;
4482 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4483 static HARD_REG_SET reload_reg_used_in_other_addr;
4485 /* If reg is in use as a reload reg for any sort of reload. */
4486 static HARD_REG_SET reload_reg_used_at_all;
4488 /* If reg is use as an inherited reload. We just mark the first register
4490 static HARD_REG_SET reload_reg_used_for_inherit;
4492 /* Records which hard regs are used in any way, either as explicit use or
4493 by being allocated to a pseudo during any point of the current insn. */
4494 static HARD_REG_SET reg_used_in_insn;
4496 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4497 TYPE. MODE is used to indicate how many consecutive regs are
4501 mark_reload_reg_in_use (regno, opnum, type, mode)
4504 enum reload_type type;
4505 enum machine_mode mode;
4507 int nregs = HARD_REGNO_NREGS (regno, mode);
4510 for (i = regno; i < nregs + regno; i++)
4515 SET_HARD_REG_BIT (reload_reg_used, i);
4518 case RELOAD_FOR_INPUT_ADDRESS:
4519 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4522 case RELOAD_FOR_INPADDR_ADDRESS:
4523 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4526 case RELOAD_FOR_OUTPUT_ADDRESS:
4527 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4530 case RELOAD_FOR_OUTADDR_ADDRESS:
4531 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4534 case RELOAD_FOR_OPERAND_ADDRESS:
4535 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4538 case RELOAD_FOR_OPADDR_ADDR:
4539 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4542 case RELOAD_FOR_OTHER_ADDRESS:
4543 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4546 case RELOAD_FOR_INPUT:
4547 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4550 case RELOAD_FOR_OUTPUT:
4551 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4554 case RELOAD_FOR_INSN:
4555 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4559 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4563 /* Similarly, but show REGNO is no longer in use for a reload. */
4566 clear_reload_reg_in_use (regno, opnum, type, mode)
4569 enum reload_type type;
4570 enum machine_mode mode;
4572 int nregs = HARD_REGNO_NREGS (regno, mode);
4573 int start_regno, end_regno;
4575 /* A complication is that for some reload types, inheritance might
4576 allow multiple reloads of the same types to share a reload register.
4577 We set check_opnum if we have to check only reloads with the same
4578 operand number, and check_any if we have to check all reloads. */
4579 int check_opnum = 0;
4581 HARD_REG_SET *used_in_set;
4586 used_in_set = &reload_reg_used;
4589 case RELOAD_FOR_INPUT_ADDRESS:
4590 used_in_set = &reload_reg_used_in_input_addr[opnum];
4593 case RELOAD_FOR_INPADDR_ADDRESS:
4595 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4598 case RELOAD_FOR_OUTPUT_ADDRESS:
4599 used_in_set = &reload_reg_used_in_output_addr[opnum];
4602 case RELOAD_FOR_OUTADDR_ADDRESS:
4604 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4607 case RELOAD_FOR_OPERAND_ADDRESS:
4608 used_in_set = &reload_reg_used_in_op_addr;
4611 case RELOAD_FOR_OPADDR_ADDR:
4613 used_in_set = &reload_reg_used_in_op_addr_reload;
4616 case RELOAD_FOR_OTHER_ADDRESS:
4617 used_in_set = &reload_reg_used_in_other_addr;
4621 case RELOAD_FOR_INPUT:
4622 used_in_set = &reload_reg_used_in_input[opnum];
4625 case RELOAD_FOR_OUTPUT:
4626 used_in_set = &reload_reg_used_in_output[opnum];
4629 case RELOAD_FOR_INSN:
4630 used_in_set = &reload_reg_used_in_insn;
4635 /* We resolve conflicts with remaining reloads of the same type by
4636 excluding the intervals of of reload registers by them from the
4637 interval of freed reload registers. Since we only keep track of
4638 one set of interval bounds, we might have to exclude somewhat
4639 more then what would be necessary if we used a HARD_REG_SET here.
4640 But this should only happen very infrequently, so there should
4641 be no reason to worry about it. */
4643 start_regno = regno;
4644 end_regno = regno + nregs;
4645 if (check_opnum || check_any)
4647 for (i = n_reloads - 1; i >= 0; i--)
4649 if (reload_when_needed[i] == type
4650 && (check_any || reload_opnum[i] == opnum)
4651 && reload_reg_rtx[i])
4653 int conflict_start = true_regnum (reload_reg_rtx[i]);
4656 + HARD_REGNO_NREGS (conflict_start, reload_mode[i]));
4658 /* If there is an overlap with the first to-be-freed register,
4659 adjust the interval start. */
4660 if (conflict_start <= start_regno && conflict_end > start_regno)
4661 start_regno = conflict_end;
4662 /* Otherwise, if there is a conflict with one of the other
4663 to-be-freed registers, adjust the interval end. */
4664 if (conflict_start > start_regno && conflict_start < end_regno)
4665 end_regno = conflict_start;
4669 for (i = start_regno; i < end_regno; i++)
4670 CLEAR_HARD_REG_BIT (*used_in_set, i);
4673 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4674 specified by OPNUM and TYPE. */
4677 reload_reg_free_p (regno, opnum, type)
4680 enum reload_type type;
4684 /* In use for a RELOAD_OTHER means it's not available for anything. */
4685 if (TEST_HARD_REG_BIT (reload_reg_used, regno))
4691 /* In use for anything means we can't use it for RELOAD_OTHER. */
4692 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4693 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4694 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4697 for (i = 0; i < reload_n_operands; i++)
4698 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4699 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4700 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4701 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4702 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4703 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4708 case RELOAD_FOR_INPUT:
4709 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4710 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4713 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4716 /* If it is used for some other input, can't use it. */
4717 for (i = 0; i < reload_n_operands; i++)
4718 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4721 /* If it is used in a later operand's address, can't use it. */
4722 for (i = opnum + 1; i < reload_n_operands; i++)
4723 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4724 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4729 case RELOAD_FOR_INPUT_ADDRESS:
4730 /* Can't use a register if it is used for an input address for this
4731 operand or used as an input in an earlier one. */
4732 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4733 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4736 for (i = 0; i < opnum; i++)
4737 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4742 case RELOAD_FOR_INPADDR_ADDRESS:
4743 /* Can't use a register if it is used for an input address
4744 for this operand or used as an input in an earlier
4746 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4749 for (i = 0; i < opnum; i++)
4750 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4755 case RELOAD_FOR_OUTPUT_ADDRESS:
4756 /* Can't use a register if it is used for an output address for this
4757 operand or used as an output in this or a later operand. */
4758 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4761 for (i = opnum; i < reload_n_operands; i++)
4762 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4767 case RELOAD_FOR_OUTADDR_ADDRESS:
4768 /* Can't use a register if it is used for an output address
4769 for this operand or used as an output in this or a
4771 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4774 for (i = opnum; i < reload_n_operands; i++)
4775 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4780 case RELOAD_FOR_OPERAND_ADDRESS:
4781 for (i = 0; i < reload_n_operands; i++)
4782 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4785 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4786 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4788 case RELOAD_FOR_OPADDR_ADDR:
4789 for (i = 0; i < reload_n_operands; i++)
4790 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4793 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4795 case RELOAD_FOR_OUTPUT:
4796 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4797 outputs, or an operand address for this or an earlier output. */
4798 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4801 for (i = 0; i < reload_n_operands; i++)
4802 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4805 for (i = 0; i <= opnum; i++)
4806 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4807 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4812 case RELOAD_FOR_INSN:
4813 for (i = 0; i < reload_n_operands; i++)
4814 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4815 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4818 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4819 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4821 case RELOAD_FOR_OTHER_ADDRESS:
4822 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4827 /* Return 1 if the value in reload reg REGNO, as used by a reload
4828 needed for the part of the insn specified by OPNUM and TYPE,
4829 is still available in REGNO at the end of the insn.
4831 We can assume that the reload reg was already tested for availability
4832 at the time it is needed, and we should not check this again,
4833 in case the reg has already been marked in use. */
4836 reload_reg_reaches_end_p (regno, opnum, type)
4839 enum reload_type type;
4846 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4847 its value must reach the end. */
4850 /* If this use is for part of the insn,
4851 its value reaches if no subsequent part uses the same register.
4852 Just like the above function, don't try to do this with lots
4855 case RELOAD_FOR_OTHER_ADDRESS:
4856 /* Here we check for everything else, since these don't conflict
4857 with anything else and everything comes later. */
4859 for (i = 0; i < reload_n_operands; i++)
4860 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4861 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4862 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4863 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4864 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4865 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4868 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4869 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4870 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4872 case RELOAD_FOR_INPUT_ADDRESS:
4873 case RELOAD_FOR_INPADDR_ADDRESS:
4874 /* Similar, except that we check only for this and subsequent inputs
4875 and the address of only subsequent inputs and we do not need
4876 to check for RELOAD_OTHER objects since they are known not to
4879 for (i = opnum; i < reload_n_operands; i++)
4880 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4883 for (i = opnum + 1; i < reload_n_operands; i++)
4884 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4885 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4888 for (i = 0; i < reload_n_operands; i++)
4889 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4890 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4891 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4894 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4897 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4898 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4900 case RELOAD_FOR_INPUT:
4901 /* Similar to input address, except we start at the next operand for
4902 both input and input address and we do not check for
4903 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4906 for (i = opnum + 1; i < reload_n_operands; i++)
4907 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4908 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4909 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4912 /* ... fall through ... */
4914 case RELOAD_FOR_OPERAND_ADDRESS:
4915 /* Check outputs and their addresses. */
4917 for (i = 0; i < reload_n_operands; i++)
4918 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4919 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4920 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4925 case RELOAD_FOR_OPADDR_ADDR:
4926 for (i = 0; i < reload_n_operands; i++)
4927 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4928 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4929 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4932 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4933 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4935 case RELOAD_FOR_INSN:
4936 /* These conflict with other outputs with RELOAD_OTHER. So
4937 we need only check for output addresses. */
4941 /* ... fall through ... */
4943 case RELOAD_FOR_OUTPUT:
4944 case RELOAD_FOR_OUTPUT_ADDRESS:
4945 case RELOAD_FOR_OUTADDR_ADDRESS:
4946 /* We already know these can't conflict with a later output. So the
4947 only thing to check are later output addresses. */
4948 for (i = opnum + 1; i < reload_n_operands; i++)
4949 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4950 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4959 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4962 This function uses the same algorithm as reload_reg_free_p above. */
4965 reloads_conflict (r1, r2)
4968 enum reload_type r1_type = reload_when_needed[r1];
4969 enum reload_type r2_type = reload_when_needed[r2];
4970 int r1_opnum = reload_opnum[r1];
4971 int r2_opnum = reload_opnum[r2];
4973 /* RELOAD_OTHER conflicts with everything. */
4974 if (r2_type == RELOAD_OTHER)
4977 /* Otherwise, check conflicts differently for each type. */
4981 case RELOAD_FOR_INPUT:
4982 return (r2_type == RELOAD_FOR_INSN
4983 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4984 || r2_type == RELOAD_FOR_OPADDR_ADDR
4985 || r2_type == RELOAD_FOR_INPUT
4986 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4987 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4988 && r2_opnum > r1_opnum));
4990 case RELOAD_FOR_INPUT_ADDRESS:
4991 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4992 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4994 case RELOAD_FOR_INPADDR_ADDRESS:
4995 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4996 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4998 case RELOAD_FOR_OUTPUT_ADDRESS:
4999 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5000 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
5002 case RELOAD_FOR_OUTADDR_ADDRESS:
5003 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5004 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
5006 case RELOAD_FOR_OPERAND_ADDRESS:
5007 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5008 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5010 case RELOAD_FOR_OPADDR_ADDR:
5011 return (r2_type == RELOAD_FOR_INPUT
5012 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5014 case RELOAD_FOR_OUTPUT:
5015 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5016 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5017 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5018 && r2_opnum >= r1_opnum));
5020 case RELOAD_FOR_INSN:
5021 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5022 || r2_type == RELOAD_FOR_INSN
5023 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5025 case RELOAD_FOR_OTHER_ADDRESS:
5026 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5036 /* Vector of reload-numbers showing the order in which the reloads should
5038 short reload_order[MAX_RELOADS];
5040 /* Indexed by reload number, 1 if incoming value
5041 inherited from previous insns. */
5042 char reload_inherited[MAX_RELOADS];
5044 /* For an inherited reload, this is the insn the reload was inherited from,
5045 if we know it. Otherwise, this is 0. */
5046 rtx reload_inheritance_insn[MAX_RELOADS];
5048 /* If non-zero, this is a place to get the value of the reload,
5049 rather than using reload_in. */
5050 rtx reload_override_in[MAX_RELOADS];
5052 /* For each reload, the hard register number of the register used,
5053 or -1 if we did not need a register for this reload. */
5054 int reload_spill_index[MAX_RELOADS];
5056 /* Return 1 if the value in reload reg REGNO, as used by a reload
5057 needed for the part of the insn specified by OPNUM and TYPE,
5058 may be used to load VALUE into it.
5060 Other read-only reloads with the same value do not conflict
5061 unless OUT is non-zero and these other reloads have to live while
5062 output reloads live.
5063 If OUT is CONST0_RTX, this is a special case: it means that the
5064 test should not be for using register REGNO as reload register, but
5065 for copying from register REGNO into the reload register.
5067 RELOADNUM is the number of the reload we want to load this value for;
5068 a reload does not conflict with itself.
5070 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5071 reloads that load an address for the very reload we are considering.
5073 The caller has to make sure that there is no conflict with the return
5076 reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum,
5077 ignore_address_reloads)
5080 enum reload_type type;
5083 int ignore_address_reloads;
5089 if (out == const0_rtx)
5095 /* We use some pseudo 'time' value to check if the lifetimes of the
5096 new register use would overlap with the one of a previous reload
5097 that is not read-only or uses a different value.
5098 The 'time' used doesn't have to be linear in any shape or form, just
5100 Some reload types use different 'buckets' for each operand.
5101 So there are MAX_RECOG_OPERANDS different time values for each
5103 We compute TIME1 as the time when the register for the prospective
5104 new reload ceases to be live, and TIME2 for each existing
5105 reload as the time when that the reload register of that reload
5107 Where there is little to be gained by exact lifetime calculations,
5108 we just make conservative assumptions, i.e. a longer lifetime;
5109 this is done in the 'default:' cases. */
5112 case RELOAD_FOR_OTHER_ADDRESS:
5116 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5118 /* For each input, we might have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5119 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5120 respectively, to the time values for these, we get distinct time
5121 values. To get distinct time values for each operand, we have to
5122 multiply opnum by at least three. We round that up to four because
5123 multiply by four is often cheaper. */
5124 case RELOAD_FOR_INPADDR_ADDRESS:
5125 time1 = opnum * 4 + 2;
5127 case RELOAD_FOR_INPUT_ADDRESS:
5128 time1 = opnum * 4 + 3;
5130 case RELOAD_FOR_INPUT:
5131 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5132 executes (inclusive). */
5133 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5135 case RELOAD_FOR_OPADDR_ADDR:
5137 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5138 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5140 case RELOAD_FOR_OPERAND_ADDRESS:
5141 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5143 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5145 case RELOAD_FOR_OUTADDR_ADDRESS:
5146 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5148 case RELOAD_FOR_OUTPUT_ADDRESS:
5149 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5152 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5155 for (i = 0; i < n_reloads; i++)
5157 rtx reg = reload_reg_rtx[i];
5158 if (reg && GET_CODE (reg) == REG
5159 && ((unsigned) regno - true_regnum (reg)
5160 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
5163 if (! reload_in[i] || ! rtx_equal_p (reload_in[i], value)
5164 || reload_out[i] || out)
5167 switch (reload_when_needed[i])
5169 case RELOAD_FOR_OTHER_ADDRESS:
5172 case RELOAD_FOR_INPADDR_ADDRESS:
5173 /* find_reloads makes sure that a
5174 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5175 by at most one - the first -
5176 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5177 address reload is inherited, the address address reload
5178 goes away, so we can ignore this conflict. */
5179 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5180 && ignore_address_reloads
5181 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5182 Then the address address is still needed to store
5183 back the new address. */
5184 && ! reload_out[reloadnum])
5186 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5187 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5189 if (type == RELOAD_FOR_INPUT && opnum == reload_opnum[i]
5190 && ignore_address_reloads
5191 /* Unless we are reloading an auto_inc expression. */
5192 && ! reload_out[reloadnum])
5194 time2 = reload_opnum[i] * 4 + 2;
5196 case RELOAD_FOR_INPUT_ADDRESS:
5197 if (type == RELOAD_FOR_INPUT && opnum == reload_opnum[i]
5198 && ignore_address_reloads
5199 && ! reload_out[reloadnum])
5201 time2 = reload_opnum[i] * 4 + 3;
5203 case RELOAD_FOR_INPUT:
5204 time2 = reload_opnum[i] * 4 + 4;
5206 /* reload_opnum[i] * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5207 == MAX_RECOG_OPERAND * 4 */
5208 case RELOAD_FOR_OPADDR_ADDR:
5209 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5210 && ignore_address_reloads
5211 && ! reload_out[reloadnum])
5213 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5215 case RELOAD_FOR_OPERAND_ADDRESS:
5216 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5218 case RELOAD_FOR_INSN:
5219 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5221 case RELOAD_FOR_OUTPUT:
5222 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5223 instruction is executed. */
5224 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5226 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5227 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5229 case RELOAD_FOR_OUTADDR_ADDRESS:
5230 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5231 && ignore_address_reloads
5232 && ! reload_out[reloadnum])
5234 time2 = MAX_RECOG_OPERANDS * 4 + 4 + reload_opnum[i];
5236 case RELOAD_FOR_OUTPUT_ADDRESS:
5237 time2 = MAX_RECOG_OPERANDS * 4 + 5 + reload_opnum[i];
5240 /* If there is no conflict in the input part, handle this
5241 like an output reload. */
5242 if (! reload_in[i] || rtx_equal_p (reload_in[i], value))
5244 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5248 /* RELOAD_OTHER might be live beyond instruction execution,
5249 but this is not obvious when we set time2 = 1. So check
5250 here if there might be a problem with the new reload
5251 clobbering the register used by the RELOAD_OTHER. */
5259 && (! reload_in[i] || reload_out[i]
5260 || ! rtx_equal_p (reload_in[i], value)))
5261 || (out && reload_out_reg[reloadnum]
5262 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5270 /* Find a spill register to use as a reload register for reload R.
5271 LAST_RELOAD is non-zero if this is the last reload for the insn being
5274 Set reload_reg_rtx[R] to the register allocated.
5276 If NOERROR is nonzero, we return 1 if successful,
5277 or 0 if we couldn't find a spill reg and we didn't change anything. */
5280 allocate_reload_reg (chain, r, last_reload, noerror)
5281 struct insn_chain *chain;
5286 rtx insn = chain->insn;
5287 int i, pass, count, regno;
5290 /* If we put this reload ahead, thinking it is a group,
5291 then insist on finding a group. Otherwise we can grab a
5292 reg that some other reload needs.
5293 (That can happen when we have a 68000 DATA_OR_FP_REG
5294 which is a group of data regs or one fp reg.)
5295 We need not be so restrictive if there are no more reloads
5298 ??? Really it would be nicer to have smarter handling
5299 for that kind of reg class, where a problem like this is normal.
5300 Perhaps those classes should be avoided for reloading
5301 by use of more alternatives. */
5303 int force_group = reload_nregs[r] > 1 && ! last_reload;
5305 /* If we want a single register and haven't yet found one,
5306 take any reg in the right class and not in use.
5307 If we want a consecutive group, here is where we look for it.
5309 We use two passes so we can first look for reload regs to
5310 reuse, which are already in use for other reloads in this insn,
5311 and only then use additional registers.
5312 I think that maximizing reuse is needed to make sure we don't
5313 run out of reload regs. Suppose we have three reloads, and
5314 reloads A and B can share regs. These need two regs.
5315 Suppose A and B are given different regs.
5316 That leaves none for C. */
5317 for (pass = 0; pass < 2; pass++)
5319 /* I is the index in spill_regs.
5320 We advance it round-robin between insns to use all spill regs
5321 equally, so that inherited reloads have a chance
5322 of leapfrogging each other. Don't do this, however, when we have
5323 group needs and failure would be fatal; if we only have a relatively
5324 small number of spill registers, and more than one of them has
5325 group needs, then by starting in the middle, we may end up
5326 allocating the first one in such a way that we are not left with
5327 sufficient groups to handle the rest. */
5329 if (noerror || ! force_group)
5334 for (count = 0; count < n_spills; count++)
5336 int class = (int) reload_reg_class[r];
5342 regnum = spill_regs[i];
5344 if ((reload_reg_free_p (regnum, reload_opnum[r],
5345 reload_when_needed[r])
5347 /* We check reload_reg_used to make sure we
5348 don't clobber the return register. */
5349 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5350 && reload_reg_free_for_value_p (regnum,
5352 reload_when_needed[r],
5354 reload_out[r], r, 1)))
5355 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5356 && HARD_REGNO_MODE_OK (regnum, reload_mode[r])
5357 /* Look first for regs to share, then for unshared. But
5358 don't share regs used for inherited reloads; they are
5359 the ones we want to preserve. */
5361 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5363 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5366 int nr = HARD_REGNO_NREGS (regnum, reload_mode[r]);
5367 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5368 (on 68000) got us two FP regs. If NR is 1,
5369 we would reject both of them. */
5371 nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
5372 /* If we need only one reg, we have already won. */
5375 /* But reject a single reg if we demand a group. */
5380 /* Otherwise check that as many consecutive regs as we need
5382 Also, don't use for a group registers that are
5383 needed for nongroups. */
5384 if (! TEST_HARD_REG_BIT (chain->counted_for_nongroups, regnum))
5387 regno = regnum + nr - 1;
5388 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5389 && spill_reg_order[regno] >= 0
5390 && reload_reg_free_p (regno, reload_opnum[r],
5391 reload_when_needed[r])
5392 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups,
5402 /* If we found something on pass 1, omit pass 2. */
5403 if (count < n_spills)
5407 /* We should have found a spill register by now. */
5408 if (count == n_spills)
5415 /* I is the index in SPILL_REG_RTX of the reload register we are to
5416 allocate. Get an rtx for it and find its register number. */
5418 new = spill_reg_rtx[i];
5420 if (new == 0 || GET_MODE (new) != reload_mode[r])
5421 spill_reg_rtx[i] = new
5422 = gen_rtx_REG (reload_mode[r], spill_regs[i]);
5424 regno = true_regnum (new);
5426 /* Detect when the reload reg can't hold the reload mode.
5427 This used to be one `if', but Sequent compiler can't handle that. */
5428 if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5430 enum machine_mode test_mode = VOIDmode;
5432 test_mode = GET_MODE (reload_in[r]);
5433 /* If reload_in[r] has VOIDmode, it means we will load it
5434 in whatever mode the reload reg has: to wit, reload_mode[r].
5435 We have already tested that for validity. */
5436 /* Aside from that, we need to test that the expressions
5437 to reload from or into have modes which are valid for this
5438 reload register. Otherwise the reload insns would be invalid. */
5439 if (! (reload_in[r] != 0 && test_mode != VOIDmode
5440 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5441 if (! (reload_out[r] != 0
5442 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
5444 /* The reg is OK. */
5447 /* Mark as in use for this insn the reload regs we use
5449 mark_reload_reg_in_use (spill_regs[i], reload_opnum[r],
5450 reload_when_needed[r], reload_mode[r]);
5452 reload_reg_rtx[r] = new;
5453 reload_spill_index[r] = spill_regs[i];
5458 /* The reg is not OK. */
5463 if (asm_noperands (PATTERN (insn)) < 0)
5464 /* It's the compiler's fault. */
5465 fatal_insn ("Could not find a spill register", insn);
5467 /* It's the user's fault; the operand's mode and constraint
5468 don't match. Disable this reload so we don't crash in final. */
5469 error_for_asm (insn,
5470 "`asm' operand constraint incompatible with operand size");
5473 reload_reg_rtx[r] = 0;
5474 reload_optional[r] = 1;
5475 reload_secondary_p[r] = 1;
5480 /* Assign hard reg targets for the pseudo-registers we must reload
5481 into hard regs for this insn.
5482 Also output the instructions to copy them in and out of the hard regs.
5484 For machines with register classes, we are responsible for
5485 finding a reload reg in the proper class. */
5488 choose_reload_regs (chain)
5489 struct insn_chain *chain;
5491 rtx insn = chain->insn;
5493 int max_group_size = 1;
5494 enum reg_class group_class = NO_REGS;
5498 rtx save_reload_reg_rtx[MAX_RELOADS];
5499 char save_reload_inherited[MAX_RELOADS];
5500 rtx save_reload_inheritance_insn[MAX_RELOADS];
5501 rtx save_reload_override_in[MAX_RELOADS];
5502 int save_reload_spill_index[MAX_RELOADS];
5503 HARD_REG_SET save_reload_reg_used;
5504 HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
5505 HARD_REG_SET save_reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
5506 HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
5507 HARD_REG_SET save_reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
5508 HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS];
5509 HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS];
5510 HARD_REG_SET save_reload_reg_used_in_op_addr;
5511 HARD_REG_SET save_reload_reg_used_in_op_addr_reload;
5512 HARD_REG_SET save_reload_reg_used_in_insn;
5513 HARD_REG_SET save_reload_reg_used_in_other_addr;
5514 HARD_REG_SET save_reload_reg_used_at_all;
5516 bzero (reload_inherited, MAX_RELOADS);
5517 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5518 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5520 CLEAR_HARD_REG_SET (reload_reg_used);
5521 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5522 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5523 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5524 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5525 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5527 CLEAR_HARD_REG_SET (reg_used_in_insn);
5530 REG_SET_TO_HARD_REG_SET (tmp, chain->live_before);
5531 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5532 REG_SET_TO_HARD_REG_SET (tmp, chain->live_after);
5533 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5534 compute_use_by_pseudos (®_used_in_insn, chain->live_before);
5535 compute_use_by_pseudos (®_used_in_insn, chain->live_after);
5537 for (i = 0; i < reload_n_operands; i++)
5539 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5540 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5541 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5542 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5543 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5544 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5547 IOR_COMPL_HARD_REG_SET (reload_reg_used, chain->used_spill_regs);
5549 #if 0 /* Not needed, now that we can always retry without inheritance. */
5550 /* See if we have more mandatory reloads than spill regs.
5551 If so, then we cannot risk optimizations that could prevent
5552 reloads from sharing one spill register.
5554 Since we will try finding a better register than reload_reg_rtx
5555 unless it is equal to reload_in or reload_out, count such reloads. */
5559 for (j = 0; j < n_reloads; j++)
5560 if (! reload_optional[j]
5561 && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
5562 && (reload_reg_rtx[j] == 0
5563 || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
5564 && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
5571 /* In order to be certain of getting the registers we need,
5572 we must sort the reloads into order of increasing register class.
5573 Then our grabbing of reload registers will parallel the process
5574 that provided the reload registers.
5576 Also note whether any of the reloads wants a consecutive group of regs.
5577 If so, record the maximum size of the group desired and what
5578 register class contains all the groups needed by this insn. */
5580 for (j = 0; j < n_reloads; j++)
5582 reload_order[j] = j;
5583 reload_spill_index[j] = -1;
5586 = (reload_inmode[j] == VOIDmode
5587 || (GET_MODE_SIZE (reload_outmode[j])
5588 > GET_MODE_SIZE (reload_inmode[j])))
5589 ? reload_outmode[j] : reload_inmode[j];
5591 reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
5593 if (reload_nregs[j] > 1)
5595 max_group_size = MAX (reload_nregs[j], max_group_size);
5596 group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
5599 /* If we have already decided to use a certain register,
5600 don't use it in another way. */
5601 if (reload_reg_rtx[j])
5602 mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j],
5603 reload_when_needed[j], reload_mode[j]);
5607 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5609 bcopy ((char *) reload_reg_rtx, (char *) save_reload_reg_rtx,
5610 sizeof reload_reg_rtx);
5611 bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
5612 bcopy ((char *) reload_inheritance_insn,
5613 (char *) save_reload_inheritance_insn,
5614 sizeof reload_inheritance_insn);
5615 bcopy ((char *) reload_override_in, (char *) save_reload_override_in,
5616 sizeof reload_override_in);
5617 bcopy ((char *) reload_spill_index, (char *) save_reload_spill_index,
5618 sizeof reload_spill_index);
5619 COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
5620 COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
5621 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
5622 reload_reg_used_in_op_addr);
5624 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr_reload,
5625 reload_reg_used_in_op_addr_reload);
5627 COPY_HARD_REG_SET (save_reload_reg_used_in_insn,
5628 reload_reg_used_in_insn);
5629 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr,
5630 reload_reg_used_in_other_addr);
5632 for (i = 0; i < reload_n_operands; i++)
5634 COPY_HARD_REG_SET (save_reload_reg_used_in_output[i],
5635 reload_reg_used_in_output[i]);
5636 COPY_HARD_REG_SET (save_reload_reg_used_in_input[i],
5637 reload_reg_used_in_input[i]);
5638 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i],
5639 reload_reg_used_in_input_addr[i]);
5640 COPY_HARD_REG_SET (save_reload_reg_used_in_inpaddr_addr[i],
5641 reload_reg_used_in_inpaddr_addr[i]);
5642 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i],
5643 reload_reg_used_in_output_addr[i]);
5644 COPY_HARD_REG_SET (save_reload_reg_used_in_outaddr_addr[i],
5645 reload_reg_used_in_outaddr_addr[i]);
5648 /* If -O, try first with inheritance, then turning it off.
5649 If not -O, don't do inheritance.
5650 Using inheritance when not optimizing leads to paradoxes
5651 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5652 because one side of the comparison might be inherited. */
5654 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5656 /* Process the reloads in order of preference just found.
5657 Beyond this point, subregs can be found in reload_reg_rtx.
5659 This used to look for an existing reloaded home for all
5660 of the reloads, and only then perform any new reloads.
5661 But that could lose if the reloads were done out of reg-class order
5662 because a later reload with a looser constraint might have an old
5663 home in a register needed by an earlier reload with a tighter constraint.
5665 To solve this, we make two passes over the reloads, in the order
5666 described above. In the first pass we try to inherit a reload
5667 from a previous insn. If there is a later reload that needs a
5668 class that is a proper subset of the class being processed, we must
5669 also allocate a spill register during the first pass.
5671 Then make a second pass over the reloads to allocate any reloads
5672 that haven't been given registers yet. */
5674 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5676 for (j = 0; j < n_reloads; j++)
5678 register int r = reload_order[j];
5680 /* Ignore reloads that got marked inoperative. */
5681 if (reload_out[r] == 0 && reload_in[r] == 0
5682 && ! reload_secondary_p[r])
5685 /* If find_reloads chose to use reload_in or reload_out as a reload
5686 register, we don't need to chose one. Otherwise, try even if it
5687 found one since we might save an insn if we find the value lying
5689 Try also when reload_in is a pseudo without a hard reg. */
5690 if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
5691 && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
5692 || (rtx_equal_p (reload_out[r], reload_reg_rtx[r])
5693 && GET_CODE (reload_in[r]) != MEM
5694 && true_regnum (reload_in[r]) < FIRST_PSEUDO_REGISTER)))
5697 #if 0 /* No longer needed for correct operation.
5698 It might give better code, or might not; worth an experiment? */
5699 /* If this is an optional reload, we can't inherit from earlier insns
5700 until we are sure that any non-optional reloads have been allocated.
5701 The following code takes advantage of the fact that optional reloads
5702 are at the end of reload_order. */
5703 if (reload_optional[r] != 0)
5704 for (i = 0; i < j; i++)
5705 if ((reload_out[reload_order[i]] != 0
5706 || reload_in[reload_order[i]] != 0
5707 || reload_secondary_p[reload_order[i]])
5708 && ! reload_optional[reload_order[i]]
5709 && reload_reg_rtx[reload_order[i]] == 0)
5710 allocate_reload_reg (chain, reload_order[i], 0, inheritance);
5713 /* First see if this pseudo is already available as reloaded
5714 for a previous insn. We cannot try to inherit for reloads
5715 that are smaller than the maximum number of registers needed
5716 for groups unless the register we would allocate cannot be used
5719 We could check here to see if this is a secondary reload for
5720 an object that is already in a register of the desired class.
5721 This would avoid the need for the secondary reload register.
5722 But this is complex because we can't easily determine what
5723 objects might want to be loaded via this reload. So let a
5724 register be allocated here. In `emit_reload_insns' we suppress
5725 one of the loads in the case described above. */
5730 register int regno = -1;
5731 enum machine_mode mode;
5733 if (reload_in[r] == 0)
5735 else if (GET_CODE (reload_in[r]) == REG)
5737 regno = REGNO (reload_in[r]);
5738 mode = GET_MODE (reload_in[r]);
5740 else if (GET_CODE (reload_in_reg[r]) == REG)
5742 regno = REGNO (reload_in_reg[r]);
5743 mode = GET_MODE (reload_in_reg[r]);
5745 else if (GET_CODE (reload_in_reg[r]) == SUBREG
5746 && GET_CODE (SUBREG_REG (reload_in_reg[r])) == REG)
5748 word = SUBREG_WORD (reload_in_reg[r]);
5749 regno = REGNO (SUBREG_REG (reload_in_reg[r]));
5750 if (regno < FIRST_PSEUDO_REGISTER)
5752 mode = GET_MODE (reload_in_reg[r]);
5755 else if ((GET_CODE (reload_in_reg[r]) == PRE_INC
5756 || GET_CODE (reload_in_reg[r]) == PRE_DEC
5757 || GET_CODE (reload_in_reg[r]) == POST_INC
5758 || GET_CODE (reload_in_reg[r]) == POST_DEC)
5759 && GET_CODE (XEXP (reload_in_reg[r], 0)) == REG)
5761 regno = REGNO (XEXP (reload_in_reg[r], 0));
5762 mode = GET_MODE (XEXP (reload_in_reg[r], 0));
5763 reload_out[r] = reload_in[r];
5767 /* This won't work, since REGNO can be a pseudo reg number.
5768 Also, it takes much more hair to keep track of all the things
5769 that can invalidate an inherited reload of part of a pseudoreg. */
5770 else if (GET_CODE (reload_in[r]) == SUBREG
5771 && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
5772 regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
5775 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5777 enum reg_class class = reload_reg_class[r], last_class;
5778 rtx last_reg = reg_last_reload_reg[regno];
5780 i = REGNO (last_reg) + word;
5781 last_class = REGNO_REG_CLASS (i);
5782 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5783 >= GET_MODE_SIZE (mode) + word * UNITS_PER_WORD)
5784 && reg_reloaded_contents[i] == regno
5785 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5786 && HARD_REGNO_MODE_OK (i, reload_mode[r])
5787 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5788 /* Even if we can't use this register as a reload
5789 register, we might use it for reload_override_in,
5790 if copying it to the desired class is cheap
5792 || ((REGISTER_MOVE_COST (last_class, class)
5793 < MEMORY_MOVE_COST (mode, class, 1))
5794 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5795 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5799 #ifdef SECONDARY_MEMORY_NEEDED
5800 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5805 && (reload_nregs[r] == max_group_size
5806 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5808 && reload_reg_free_for_value_p (i, reload_opnum[r],
5809 reload_when_needed[r],
5813 /* If a group is needed, verify that all the subsequent
5814 registers still have their values intact. */
5816 = HARD_REGNO_NREGS (i, reload_mode[r]);
5819 for (k = 1; k < nr; k++)
5820 if (reg_reloaded_contents[i + k] != regno
5821 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5828 last_reg = (GET_MODE (last_reg) == mode
5829 ? last_reg : gen_rtx_REG (mode, i));
5831 /* We found a register that contains the
5832 value we need. If this register is the
5833 same as an `earlyclobber' operand of the
5834 current insn, just mark it as a place to
5835 reload from since we can't use it as the
5836 reload register itself. */
5838 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5839 if (reg_overlap_mentioned_for_reload_p
5840 (reg_last_reload_reg[regno],
5841 reload_earlyclobbers[i1]))
5844 if (i1 != n_earlyclobbers
5845 || ! (reload_reg_free_for_value_p
5846 (i, reload_opnum[r], reload_when_needed[r],
5847 reload_in[r], reload_out[r], r, 1))
5848 /* Don't use it if we'd clobber a pseudo reg. */
5849 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5851 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5852 /* Don't really use the inherited spill reg
5853 if we need it wider than we've got it. */
5854 || (GET_MODE_SIZE (reload_mode[r])
5855 > GET_MODE_SIZE (mode))
5856 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5859 /* If find_reloads chose reload_out as reload
5860 register, stay with it - that leaves the
5861 inherited register for subsequent reloads. */
5862 || (reload_out[r] && reload_reg_rtx[r]
5863 && rtx_equal_p (reload_out[r],
5864 reload_reg_rtx[r])))
5866 reload_override_in[r] = last_reg;
5867 reload_inheritance_insn[r]
5868 = reg_reloaded_insn[i];
5873 /* We can use this as a reload reg. */
5874 /* Mark the register as in use for this part of
5876 mark_reload_reg_in_use (i,
5878 reload_when_needed[r],
5880 reload_reg_rtx[r] = last_reg;
5881 reload_inherited[r] = 1;
5882 reload_inheritance_insn[r]
5883 = reg_reloaded_insn[i];
5884 reload_spill_index[r] = i;
5885 for (k = 0; k < nr; k++)
5886 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5894 /* Here's another way to see if the value is already lying around. */
5896 && reload_in[r] != 0
5897 && ! reload_inherited[r]
5898 && reload_out[r] == 0
5899 && (CONSTANT_P (reload_in[r])
5900 || GET_CODE (reload_in[r]) == PLUS
5901 || GET_CODE (reload_in[r]) == REG
5902 || GET_CODE (reload_in[r]) == MEM)
5903 && (reload_nregs[r] == max_group_size
5904 || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
5907 = find_equiv_reg (reload_in[r], insn, reload_reg_class[r],
5908 -1, NULL_PTR, 0, reload_mode[r]);
5913 if (GET_CODE (equiv) == REG)
5914 regno = REGNO (equiv);
5915 else if (GET_CODE (equiv) == SUBREG)
5917 /* This must be a SUBREG of a hard register.
5918 Make a new REG since this might be used in an
5919 address and not all machines support SUBREGs
5921 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5922 equiv = gen_rtx_REG (reload_mode[r], regno);
5928 /* If we found a spill reg, reject it unless it is free
5929 and of the desired class. */
5931 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5932 && ! reload_reg_free_for_value_p (regno, reload_opnum[r],
5933 reload_when_needed[r],
5935 reload_out[r], r, 1))
5936 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5940 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5943 /* We found a register that contains the value we need.
5944 If this register is the same as an `earlyclobber' operand
5945 of the current insn, just mark it as a place to reload from
5946 since we can't use it as the reload register itself. */
5949 for (i = 0; i < n_earlyclobbers; i++)
5950 if (reg_overlap_mentioned_for_reload_p (equiv,
5951 reload_earlyclobbers[i]))
5953 reload_override_in[r] = equiv;
5958 /* If the equiv register we have found is explicitly clobbered
5959 in the current insn, it depends on the reload type if we
5960 can use it, use it for reload_override_in, or not at all.
5961 In particular, we then can't use EQUIV for a
5962 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5964 if (equiv != 0 && regno_clobbered_p (regno, insn))
5966 switch (reload_when_needed[r])
5968 case RELOAD_FOR_OTHER_ADDRESS:
5969 case RELOAD_FOR_INPADDR_ADDRESS:
5970 case RELOAD_FOR_INPUT_ADDRESS:
5971 case RELOAD_FOR_OPADDR_ADDR:
5974 case RELOAD_FOR_INPUT:
5975 case RELOAD_FOR_OPERAND_ADDRESS:
5976 reload_override_in[r] = equiv;
5984 /* If we found an equivalent reg, say no code need be generated
5985 to load it, and use it as our reload reg. */
5986 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5988 int nr = HARD_REGNO_NREGS (regno, reload_mode[r]);
5990 reload_reg_rtx[r] = equiv;
5991 reload_inherited[r] = 1;
5993 /* If reg_reloaded_valid is not set for this register,
5994 there might be a stale spill_reg_store lying around.
5995 We must clear it, since otherwise emit_reload_insns
5996 might delete the store. */
5997 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5998 spill_reg_store[regno] = NULL_RTX;
5999 /* If any of the hard registers in EQUIV are spill
6000 registers, mark them as in use for this insn. */
6001 for (k = 0; k < nr; k++)
6003 i = spill_reg_order[regno + k];
6006 mark_reload_reg_in_use (regno, reload_opnum[r],
6007 reload_when_needed[r],
6009 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6016 /* If we found a register to use already, or if this is an optional
6017 reload, we are done. */
6018 if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
6021 #if 0 /* No longer needed for correct operation. Might or might not
6022 give better code on the average. Want to experiment? */
6024 /* See if there is a later reload that has a class different from our
6025 class that intersects our class or that requires less register
6026 than our reload. If so, we must allocate a register to this
6027 reload now, since that reload might inherit a previous reload
6028 and take the only available register in our class. Don't do this
6029 for optional reloads since they will force all previous reloads
6030 to be allocated. Also don't do this for reloads that have been
6033 for (i = j + 1; i < n_reloads; i++)
6035 int s = reload_order[i];
6037 if ((reload_in[s] == 0 && reload_out[s] == 0
6038 && ! reload_secondary_p[s])
6039 || reload_optional[s])
6042 if ((reload_reg_class[s] != reload_reg_class[r]
6043 && reg_classes_intersect_p (reload_reg_class[r],
6044 reload_reg_class[s]))
6045 || reload_nregs[s] < reload_nregs[r])
6052 allocate_reload_reg (chain, r, j == n_reloads - 1, inheritance);
6056 /* Now allocate reload registers for anything non-optional that
6057 didn't get one yet. */
6058 for (j = 0; j < n_reloads; j++)
6060 register int r = reload_order[j];
6062 /* Ignore reloads that got marked inoperative. */
6063 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
6066 /* Skip reloads that already have a register allocated or are
6068 if (reload_reg_rtx[r] != 0 || reload_optional[r])
6071 if (! allocate_reload_reg (chain, r, j == n_reloads - 1, inheritance))
6075 /* If that loop got all the way, we have won. */
6079 /* Loop around and try without any inheritance. */
6080 /* First undo everything done by the failed attempt
6081 to allocate with inheritance. */
6082 bcopy ((char *) save_reload_reg_rtx, (char *) reload_reg_rtx,
6083 sizeof reload_reg_rtx);
6084 bcopy ((char *) save_reload_inherited, (char *) reload_inherited,
6085 sizeof reload_inherited);
6086 bcopy ((char *) save_reload_inheritance_insn,
6087 (char *) reload_inheritance_insn,
6088 sizeof reload_inheritance_insn);
6089 bcopy ((char *) save_reload_override_in, (char *) reload_override_in,
6090 sizeof reload_override_in);
6091 bcopy ((char *) save_reload_spill_index, (char *) reload_spill_index,
6092 sizeof reload_spill_index);
6093 COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
6094 COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
6095 COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
6096 save_reload_reg_used_in_op_addr);
6097 COPY_HARD_REG_SET (reload_reg_used_in_op_addr_reload,
6098 save_reload_reg_used_in_op_addr_reload);
6099 COPY_HARD_REG_SET (reload_reg_used_in_insn,
6100 save_reload_reg_used_in_insn);
6101 COPY_HARD_REG_SET (reload_reg_used_in_other_addr,
6102 save_reload_reg_used_in_other_addr);
6104 for (i = 0; i < reload_n_operands; i++)
6106 COPY_HARD_REG_SET (reload_reg_used_in_input[i],
6107 save_reload_reg_used_in_input[i]);
6108 COPY_HARD_REG_SET (reload_reg_used_in_output[i],
6109 save_reload_reg_used_in_output[i]);
6110 COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i],
6111 save_reload_reg_used_in_input_addr[i]);
6112 COPY_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i],
6113 save_reload_reg_used_in_inpaddr_addr[i]);
6114 COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i],
6115 save_reload_reg_used_in_output_addr[i]);
6116 COPY_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i],
6117 save_reload_reg_used_in_outaddr_addr[i]);
6121 /* If we thought we could inherit a reload, because it seemed that
6122 nothing else wanted the same reload register earlier in the insn,
6123 verify that assumption, now that all reloads have been assigned.
6124 Likewise for reloads where reload_override_in has been set. */
6126 /* If doing expensive optimizations, do one preliminary pass that doesn't
6127 cancel any inheritance, but removes reloads that have been needed only
6128 for reloads that we know can be inherited. */
6129 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6131 for (j = 0; j < n_reloads; j++)
6133 register int r = reload_order[j];
6135 if (reload_inherited[r] && reload_reg_rtx[r])
6136 check_reg = reload_reg_rtx[r];
6137 else if (reload_override_in[r]
6138 && (GET_CODE (reload_override_in[r]) == REG
6139 || GET_CODE (reload_override_in[r]) == SUBREG))
6140 check_reg = reload_override_in[r];
6143 if (! reload_reg_free_for_value_p (true_regnum (check_reg),
6145 reload_when_needed[r],
6147 (reload_inherited[r]
6148 ? reload_out[r] : const0_rtx),
6153 reload_inherited[r] = 0;
6154 reload_override_in[r] = 0;
6156 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6157 reload_override_in, then we do not need its related
6158 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6159 likewise for other reload types.
6160 We handle this by removing a reload when its only replacement
6161 is mentioned in reload_in of the reload we are going to inherit.
6162 A special case are auto_inc expressions; even if the input is
6163 inherited, we still need the address for the output. We can
6164 recognize them because they have RELOAD_OUT set but not
6166 If we suceeded removing some reload and we are doing a preliminary
6167 pass just to remove such reloads, make another pass, since the
6168 removal of one reload might allow us to inherit another one. */
6169 else if ((! reload_out[r] || reload_out_reg[r])
6170 && remove_address_replacements (reload_in[r]) && pass)
6175 /* Now that reload_override_in is known valid,
6176 actually override reload_in. */
6177 for (j = 0; j < n_reloads; j++)
6178 if (reload_override_in[j])
6179 reload_in[j] = reload_override_in[j];
6181 /* If this reload won't be done because it has been cancelled or is
6182 optional and not inherited, clear reload_reg_rtx so other
6183 routines (such as subst_reloads) don't get confused. */
6184 for (j = 0; j < n_reloads; j++)
6185 if (reload_reg_rtx[j] != 0
6186 && ((reload_optional[j] && ! reload_inherited[j])
6187 || (reload_in[j] == 0 && reload_out[j] == 0
6188 && ! reload_secondary_p[j])))
6190 int regno = true_regnum (reload_reg_rtx[j]);
6192 if (spill_reg_order[regno] >= 0)
6193 clear_reload_reg_in_use (regno, reload_opnum[j],
6194 reload_when_needed[j], reload_mode[j]);
6195 reload_reg_rtx[j] = 0;
6198 /* Record which pseudos and which spill regs have output reloads. */
6199 for (j = 0; j < n_reloads; j++)
6201 register int r = reload_order[j];
6203 i = reload_spill_index[r];
6205 /* I is nonneg if this reload uses a register.
6206 If reload_reg_rtx[r] is 0, this is an optional reload
6207 that we opted to ignore. */
6208 if (reload_out_reg[r] != 0 && GET_CODE (reload_out_reg[r]) == REG
6209 && reload_reg_rtx[r] != 0)
6211 register int nregno = REGNO (reload_out_reg[r]);
6214 if (nregno < FIRST_PSEUDO_REGISTER)
6215 nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
6218 reg_has_output_reload[nregno + nr] = 1;
6222 nr = HARD_REGNO_NREGS (i, reload_mode[r]);
6224 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6227 if (reload_when_needed[r] != RELOAD_OTHER
6228 && reload_when_needed[r] != RELOAD_FOR_OUTPUT
6229 && reload_when_needed[r] != RELOAD_FOR_INSN)
6235 /* Deallocate the reload register for reload R. This is called from
6236 remove_address_replacements. */
6238 deallocate_reload_reg (r)
6243 if (! reload_reg_rtx[r])
6245 regno = true_regnum (reload_reg_rtx[r]);
6246 reload_reg_rtx[r] = 0;
6247 if (spill_reg_order[regno] >= 0)
6248 clear_reload_reg_in_use (regno, reload_opnum[r], reload_when_needed[r],
6250 reload_spill_index[r] = -1;
6253 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
6254 reloads of the same item for fear that we might not have enough reload
6255 registers. However, normally they will get the same reload register
6256 and hence actually need not be loaded twice.
6258 Here we check for the most common case of this phenomenon: when we have
6259 a number of reloads for the same object, each of which were allocated
6260 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6261 reload, and is not modified in the insn itself. If we find such,
6262 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6263 This will not increase the number of spill registers needed and will
6264 prevent redundant code. */
6267 merge_assigned_reloads (insn)
6272 /* Scan all the reloads looking for ones that only load values and
6273 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6274 assigned and not modified by INSN. */
6276 for (i = 0; i < n_reloads; i++)
6278 int conflicting_input = 0;
6279 int max_input_address_opnum = -1;
6280 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6282 if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER
6283 || reload_out[i] != 0 || reload_reg_rtx[i] == 0
6284 || reg_set_p (reload_reg_rtx[i], insn))
6287 /* Look at all other reloads. Ensure that the only use of this
6288 reload_reg_rtx is in a reload that just loads the same value
6289 as we do. Note that any secondary reloads must be of the identical
6290 class since the values, modes, and result registers are the
6291 same, so we need not do anything with any secondary reloads. */
6293 for (j = 0; j < n_reloads; j++)
6295 if (i == j || reload_reg_rtx[j] == 0
6296 || ! reg_overlap_mentioned_p (reload_reg_rtx[j],
6300 if (reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS
6301 && reload_opnum[j] > max_input_address_opnum)
6302 max_input_address_opnum = reload_opnum[j];
6304 /* If the reload regs aren't exactly the same (e.g, different modes)
6305 or if the values are different, we can't merge this reload.
6306 But if it is an input reload, we might still merge
6307 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6309 if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
6310 || reload_out[j] != 0 || reload_in[j] == 0
6311 || ! rtx_equal_p (reload_in[i], reload_in[j]))
6313 if (reload_when_needed[j] != RELOAD_FOR_INPUT
6314 || ((reload_when_needed[i] != RELOAD_FOR_INPUT_ADDRESS
6315 || reload_opnum[i] > reload_opnum[j])
6316 && reload_when_needed[i] != RELOAD_FOR_OTHER_ADDRESS))
6318 conflicting_input = 1;
6319 if (min_conflicting_input_opnum > reload_opnum[j])
6320 min_conflicting_input_opnum = reload_opnum[j];
6324 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6325 we, in fact, found any matching reloads. */
6328 && max_input_address_opnum <= min_conflicting_input_opnum)
6330 for (j = 0; j < n_reloads; j++)
6331 if (i != j && reload_reg_rtx[j] != 0
6332 && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
6333 && (! conflicting_input
6334 || reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS
6335 || reload_when_needed[j] == RELOAD_FOR_OTHER_ADDRESS))
6337 reload_when_needed[i] = RELOAD_OTHER;
6339 reload_spill_index[j] = -1;
6340 transfer_replacements (i, j);
6343 /* If this is now RELOAD_OTHER, look for any reloads that load
6344 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6345 if they were for inputs, RELOAD_OTHER for outputs. Note that
6346 this test is equivalent to looking for reloads for this operand
6349 if (reload_when_needed[i] == RELOAD_OTHER)
6350 for (j = 0; j < n_reloads; j++)
6351 if (reload_in[j] != 0
6352 && reload_when_needed[i] != RELOAD_OTHER
6353 && reg_overlap_mentioned_for_reload_p (reload_in[j],
6355 reload_when_needed[j]
6356 = ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
6357 || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS)
6358 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6364 /* Output insns to reload values in and out of the chosen reload regs. */
6367 emit_reload_insns (chain)
6368 struct insn_chain *chain;
6370 rtx insn = chain->insn;
6373 rtx input_reload_insns[MAX_RECOG_OPERANDS];
6374 rtx other_input_address_reload_insns = 0;
6375 rtx other_input_reload_insns = 0;
6376 rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6377 rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6378 rtx output_reload_insns[MAX_RECOG_OPERANDS];
6379 rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6380 rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6381 rtx operand_reload_insns = 0;
6382 rtx other_operand_reload_insns = 0;
6383 rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6384 rtx following_insn = NEXT_INSN (insn);
6385 rtx before_insn = PREV_INSN (insn);
6387 /* Values to be put in spill_reg_store are put here first. */
6388 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6389 HARD_REG_SET reg_reloaded_died;
6391 CLEAR_HARD_REG_SET (reg_reloaded_died);
6393 for (j = 0; j < reload_n_operands; j++)
6394 input_reload_insns[j] = input_address_reload_insns[j]
6395 = inpaddr_address_reload_insns[j]
6396 = output_reload_insns[j] = output_address_reload_insns[j]
6397 = outaddr_address_reload_insns[j]
6398 = other_output_reload_insns[j] = 0;
6400 /* Now output the instructions to copy the data into and out of the
6401 reload registers. Do these in the order that the reloads were reported,
6402 since reloads of base and index registers precede reloads of operands
6403 and the operands may need the base and index registers reloaded. */
6405 for (j = 0; j < n_reloads; j++)
6408 rtx oldequiv_reg = 0;
6409 rtx this_reload_insn = 0;
6410 int expect_occurrences = 1;
6412 if (reload_reg_rtx[j]
6413 && REGNO (reload_reg_rtx[j]) < FIRST_PSEUDO_REGISTER)
6414 new_spill_reg_store[REGNO (reload_reg_rtx[j])] = 0;
6416 old = (reload_in[j] && GET_CODE (reload_in[j]) == MEM
6417 ? reload_in_reg[j] : reload_in[j]);
6420 /* AUTO_INC reloads need to be handled even if inherited. We got an
6421 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6422 && (! reload_inherited[j] || (reload_out[j] && ! reload_out_reg[j]))
6423 && ! rtx_equal_p (reload_reg_rtx[j], old)
6424 && reload_reg_rtx[j] != 0)
6426 register rtx reloadreg = reload_reg_rtx[j];
6428 enum machine_mode mode;
6431 /* Determine the mode to reload in.
6432 This is very tricky because we have three to choose from.
6433 There is the mode the insn operand wants (reload_inmode[J]).
6434 There is the mode of the reload register RELOADREG.
6435 There is the intrinsic mode of the operand, which we could find
6436 by stripping some SUBREGs.
6437 It turns out that RELOADREG's mode is irrelevant:
6438 we can change that arbitrarily.
6440 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6441 then the reload reg may not support QImode moves, so use SImode.
6442 If foo is in memory due to spilling a pseudo reg, this is safe,
6443 because the QImode value is in the least significant part of a
6444 slot big enough for a SImode. If foo is some other sort of
6445 memory reference, then it is impossible to reload this case,
6446 so previous passes had better make sure this never happens.
6448 Then consider a one-word union which has SImode and one of its
6449 members is a float, being fetched as (SUBREG:SF union:SI).
6450 We must fetch that as SFmode because we could be loading into
6451 a float-only register. In this case OLD's mode is correct.
6453 Consider an immediate integer: it has VOIDmode. Here we need
6454 to get a mode from something else.
6456 In some cases, there is a fourth mode, the operand's
6457 containing mode. If the insn specifies a containing mode for
6458 this operand, it overrides all others.
6460 I am not sure whether the algorithm here is always right,
6461 but it does the right things in those cases. */
6463 mode = GET_MODE (old);
6464 if (mode == VOIDmode)
6465 mode = reload_inmode[j];
6467 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6468 /* If we need a secondary register for this operation, see if
6469 the value is already in a register in that class. Don't
6470 do this if the secondary register will be used as a scratch
6473 if (reload_secondary_in_reload[j] >= 0
6474 && reload_secondary_in_icode[j] == CODE_FOR_nothing
6477 = find_equiv_reg (old, insn,
6478 reload_reg_class[reload_secondary_in_reload[j]],
6479 -1, NULL_PTR, 0, mode);
6482 /* If reloading from memory, see if there is a register
6483 that already holds the same value. If so, reload from there.
6484 We can pass 0 as the reload_reg_p argument because
6485 any other reload has either already been emitted,
6486 in which case find_equiv_reg will see the reload-insn,
6487 or has yet to be emitted, in which case it doesn't matter
6488 because we will use this equiv reg right away. */
6490 if (oldequiv == 0 && optimize
6491 && (GET_CODE (old) == MEM
6492 || (GET_CODE (old) == REG
6493 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6494 && reg_renumber[REGNO (old)] < 0)))
6495 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6496 -1, NULL_PTR, 0, mode);
6500 int regno = true_regnum (oldequiv);
6502 /* Don't use OLDEQUIV if any other reload changes it at an
6503 earlier stage of this insn or at this stage. */
6504 if (! reload_reg_free_for_value_p (regno, reload_opnum[j],
6505 reload_when_needed[j],
6506 reload_in[j], const0_rtx, j,
6510 /* If it is no cheaper to copy from OLDEQUIV into the
6511 reload register than it would be to move from memory,
6512 don't use it. Likewise, if we need a secondary register
6516 && ((REGNO_REG_CLASS (regno) != reload_reg_class[j]
6517 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
6518 reload_reg_class[j])
6519 >= MEMORY_MOVE_COST (mode, reload_reg_class[j], 1)))
6520 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6521 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6525 #ifdef SECONDARY_MEMORY_NEEDED
6526 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6527 reload_reg_class[j],
6534 /* delete_output_reload is only invoked properly if old contains
6535 the original pseudo register. Since this is replaced with a
6536 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6537 find the pseudo in RELOAD_IN_REG. */
6539 && reload_override_in[j]
6540 && GET_CODE (reload_in_reg[j]) == REG)
6543 old = reload_in_reg[j];
6547 else if (GET_CODE (oldequiv) == REG)
6548 oldequiv_reg = oldequiv;
6549 else if (GET_CODE (oldequiv) == SUBREG)
6550 oldequiv_reg = SUBREG_REG (oldequiv);
6552 /* If we are reloading from a register that was recently stored in
6553 with an output-reload, see if we can prove there was
6554 actually no need to store the old value in it. */
6556 if (optimize && GET_CODE (oldequiv) == REG
6557 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6558 && spill_reg_store[REGNO (oldequiv)]
6559 && GET_CODE (old) == REG
6560 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6561 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6562 reload_out_reg[j])))
6563 delete_output_reload (insn, j, REGNO (oldequiv));
6565 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6566 then load RELOADREG from OLDEQUIV. Note that we cannot use
6567 gen_lowpart_common since it can do the wrong thing when
6568 RELOADREG has a multi-word mode. Note that RELOADREG
6569 must always be a REG here. */
6571 if (GET_MODE (reloadreg) != mode)
6572 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6573 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6574 oldequiv = SUBREG_REG (oldequiv);
6575 if (GET_MODE (oldequiv) != VOIDmode
6576 && mode != GET_MODE (oldequiv))
6577 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6579 /* Switch to the right place to emit the reload insns. */
6580 switch (reload_when_needed[j])
6583 where = &other_input_reload_insns;
6585 case RELOAD_FOR_INPUT:
6586 where = &input_reload_insns[reload_opnum[j]];
6588 case RELOAD_FOR_INPUT_ADDRESS:
6589 where = &input_address_reload_insns[reload_opnum[j]];
6591 case RELOAD_FOR_INPADDR_ADDRESS:
6592 where = &inpaddr_address_reload_insns[reload_opnum[j]];
6594 case RELOAD_FOR_OUTPUT_ADDRESS:
6595 where = &output_address_reload_insns[reload_opnum[j]];
6597 case RELOAD_FOR_OUTADDR_ADDRESS:
6598 where = &outaddr_address_reload_insns[reload_opnum[j]];
6600 case RELOAD_FOR_OPERAND_ADDRESS:
6601 where = &operand_reload_insns;
6603 case RELOAD_FOR_OPADDR_ADDR:
6604 where = &other_operand_reload_insns;
6606 case RELOAD_FOR_OTHER_ADDRESS:
6607 where = &other_input_address_reload_insns;
6613 push_to_sequence (*where);
6616 /* Auto-increment addresses must be reloaded in a special way. */
6617 if (reload_out[j] && ! reload_out_reg[j])
6619 /* We are not going to bother supporting the case where a
6620 incremented register can't be copied directly from
6621 OLDEQUIV since this seems highly unlikely. */
6622 if (reload_secondary_in_reload[j] >= 0)
6625 if (reload_inherited[j])
6626 oldequiv = reloadreg;
6628 old = XEXP (reload_in_reg[j], 0);
6630 if (optimize && GET_CODE (oldequiv) == REG
6631 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6632 && spill_reg_store[REGNO (oldequiv)]
6633 && GET_CODE (old) == REG
6634 && (dead_or_set_p (insn,
6635 spill_reg_stored_to[REGNO (oldequiv)])
6636 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6638 delete_output_reload (insn, j, REGNO (oldequiv));
6640 /* Prevent normal processing of this reload. */
6642 /* Output a special code sequence for this case. */
6643 new_spill_reg_store[REGNO (reloadreg)]
6644 = inc_for_reload (reloadreg, oldequiv, reload_out[j],
6648 /* If we are reloading a pseudo-register that was set by the previous
6649 insn, see if we can get rid of that pseudo-register entirely
6650 by redirecting the previous insn into our reload register. */
6652 else if (optimize && GET_CODE (old) == REG
6653 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6654 && dead_or_set_p (insn, old)
6655 /* This is unsafe if some other reload
6656 uses the same reg first. */
6657 && reload_reg_free_for_value_p (REGNO (reloadreg),
6659 reload_when_needed[j],
6663 rtx temp = PREV_INSN (insn);
6664 while (temp && GET_CODE (temp) == NOTE)
6665 temp = PREV_INSN (temp);
6667 && GET_CODE (temp) == INSN
6668 && GET_CODE (PATTERN (temp)) == SET
6669 && SET_DEST (PATTERN (temp)) == old
6670 /* Make sure we can access insn_operand_constraint. */
6671 && asm_noperands (PATTERN (temp)) < 0
6672 /* This is unsafe if prev insn rejects our reload reg. */
6673 && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
6675 /* This is unsafe if operand occurs more than once in current
6676 insn. Perhaps some occurrences aren't reloaded. */
6677 && count_occurrences (PATTERN (insn), old) == 1
6678 /* Don't risk splitting a matching pair of operands. */
6679 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6681 /* Store into the reload register instead of the pseudo. */
6682 SET_DEST (PATTERN (temp)) = reloadreg;
6684 /* If the previous insn is an output reload, the source is
6685 a reload register, and its spill_reg_store entry will
6686 contain the previous destination. This is now
6688 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6689 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6691 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6692 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6695 /* If these are the only uses of the pseudo reg,
6696 pretend for GDB it lives in the reload reg we used. */
6697 if (REG_N_DEATHS (REGNO (old)) == 1
6698 && REG_N_SETS (REGNO (old)) == 1)
6700 reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
6701 alter_reg (REGNO (old), -1);
6707 /* We can't do that, so output an insn to load RELOADREG. */
6711 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6712 rtx second_reload_reg = 0;
6713 enum insn_code icode;
6715 /* If we have a secondary reload, pick up the secondary register
6716 and icode, if any. If OLDEQUIV and OLD are different or
6717 if this is an in-out reload, recompute whether or not we
6718 still need a secondary register and what the icode should
6719 be. If we still need a secondary register and the class or
6720 icode is different, go back to reloading from OLD if using
6721 OLDEQUIV means that we got the wrong type of register. We
6722 cannot have different class or icode due to an in-out reload
6723 because we don't make such reloads when both the input and
6724 output need secondary reload registers. */
6726 if (reload_secondary_in_reload[j] >= 0)
6728 int secondary_reload = reload_secondary_in_reload[j];
6729 rtx real_oldequiv = oldequiv;
6732 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6733 and similarly for OLD.
6734 See comments in get_secondary_reload in reload.c. */
6735 /* If it is a pseudo that cannot be replaced with its
6736 equivalent MEM, we must fall back to reload_in, which
6737 will have all the necessary substitutions registered. */
6739 if (GET_CODE (oldequiv) == REG
6740 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6741 && reg_equiv_memory_loc[REGNO (oldequiv)] != 0)
6743 if (reg_equiv_address[REGNO (oldequiv)]
6744 || num_not_at_initial_offset)
6745 real_oldequiv = reload_in[j];
6747 real_oldequiv = reg_equiv_mem[REGNO (oldequiv)];
6750 if (GET_CODE (old) == REG
6751 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6752 && reg_equiv_memory_loc[REGNO (old)] != 0)
6754 if (reg_equiv_address[REGNO (old)]
6755 || num_not_at_initial_offset)
6756 real_old = reload_in[j];
6758 real_old = reg_equiv_mem[REGNO (old)];
6761 second_reload_reg = reload_reg_rtx[secondary_reload];
6762 icode = reload_secondary_in_icode[j];
6764 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6765 || (reload_in[j] != 0 && reload_out[j] != 0))
6767 enum reg_class new_class
6768 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6769 mode, real_oldequiv);
6771 if (new_class == NO_REGS)
6772 second_reload_reg = 0;
6775 enum insn_code new_icode;
6776 enum machine_mode new_mode;
6778 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6779 REGNO (second_reload_reg)))
6780 oldequiv = old, real_oldequiv = real_old;
6783 new_icode = reload_in_optab[(int) mode];
6784 if (new_icode != CODE_FOR_nothing
6785 && ((insn_operand_predicate[(int) new_icode][0]
6786 && ! ((*insn_operand_predicate[(int) new_icode][0])
6788 || (insn_operand_predicate[(int) new_icode][1]
6789 && ! ((*insn_operand_predicate[(int) new_icode][1])
6790 (real_oldequiv, mode)))))
6791 new_icode = CODE_FOR_nothing;
6793 if (new_icode == CODE_FOR_nothing)
6796 new_mode = insn_operand_mode[(int) new_icode][2];
6798 if (GET_MODE (second_reload_reg) != new_mode)
6800 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6802 oldequiv = old, real_oldequiv = real_old;
6805 = gen_rtx_REG (new_mode,
6806 REGNO (second_reload_reg));
6812 /* If we still need a secondary reload register, check
6813 to see if it is being used as a scratch or intermediate
6814 register and generate code appropriately. If we need
6815 a scratch register, use REAL_OLDEQUIV since the form of
6816 the insn may depend on the actual address if it is
6819 if (second_reload_reg)
6821 if (icode != CODE_FOR_nothing)
6823 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6824 second_reload_reg));
6829 /* See if we need a scratch register to load the
6830 intermediate register (a tertiary reload). */
6831 enum insn_code tertiary_icode
6832 = reload_secondary_in_icode[secondary_reload];
6834 if (tertiary_icode != CODE_FOR_nothing)
6836 rtx third_reload_reg
6837 = reload_reg_rtx[reload_secondary_in_reload[secondary_reload]];
6839 emit_insn ((GEN_FCN (tertiary_icode)
6840 (second_reload_reg, real_oldequiv,
6841 third_reload_reg)));
6844 gen_reload (second_reload_reg, real_oldequiv,
6846 reload_when_needed[j]);
6848 oldequiv = second_reload_reg;
6854 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6856 rtx real_oldequiv = oldequiv;
6858 if ((GET_CODE (oldequiv) == REG
6859 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6860 && reg_equiv_memory_loc[REGNO (oldequiv)] != 0)
6861 || (GET_CODE (oldequiv) == SUBREG
6862 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6863 && (REGNO (SUBREG_REG (oldequiv))
6864 >= FIRST_PSEUDO_REGISTER)
6865 && (reg_equiv_memory_loc
6866 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6867 real_oldequiv = reload_in[j];
6868 gen_reload (reloadreg, real_oldequiv, reload_opnum[j],
6869 reload_when_needed[j]);
6874 this_reload_insn = get_last_insn ();
6875 /* End this sequence. */
6876 *where = get_insns ();
6879 /* Update reload_override_in so that delete_address_reloads_1
6880 can see the actual register usage. */
6882 reload_override_in[j] = oldequiv;
6885 /* When inheriting a wider reload, we have a MEM in reload_in[j],
6886 e.g. inheriting a SImode output reload for
6887 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6888 if (optimize && reload_inherited[j] && reload_in[j]
6889 && GET_CODE (reload_in[j]) == MEM
6890 && GET_CODE (reload_in_reg[j]) == MEM
6891 && reload_spill_index[j] >= 0
6892 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6895 = count_occurrences (PATTERN (insn), reload_in[j]) == 1 ? 0 : -1;
6897 = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6900 /* If we are reloading a register that was recently stored in with an
6901 output-reload, see if we can prove there was
6902 actually no need to store the old value in it. */
6905 && (reload_inherited[j] || reload_override_in[j])
6906 && reload_reg_rtx[j]
6907 && GET_CODE (reload_reg_rtx[j]) == REG
6908 && spill_reg_store[REGNO (reload_reg_rtx[j])] != 0
6910 /* There doesn't seem to be any reason to restrict this to pseudos
6911 and doing so loses in the case where we are copying from a
6912 register of the wrong class. */
6913 && REGNO (spill_reg_stored_to[REGNO (reload_reg_rtx[j])])
6914 >= FIRST_PSEUDO_REGISTER
6916 /* The insn might have already some references to stackslots
6917 replaced by MEMs, while reload_out_reg still names the
6919 && (dead_or_set_p (insn,
6920 spill_reg_stored_to[REGNO (reload_reg_rtx[j])])
6921 || rtx_equal_p (spill_reg_stored_to[REGNO (reload_reg_rtx[j])],
6922 reload_out_reg[j])))
6923 delete_output_reload (insn, j, REGNO (reload_reg_rtx[j]));
6925 /* Input-reloading is done. Now do output-reloading,
6926 storing the value from the reload-register after the main insn
6927 if reload_out[j] is nonzero.
6929 ??? At some point we need to support handling output reloads of
6930 JUMP_INSNs or insns that set cc0. */
6932 /* If this is an output reload that stores something that is
6933 not loaded in this same reload, see if we can eliminate a previous
6936 rtx pseudo = reload_out_reg[j];
6939 && GET_CODE (pseudo) == REG
6940 && ! rtx_equal_p (reload_in_reg[j], pseudo)
6941 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6942 && reg_last_reload_reg[REGNO (pseudo)])
6944 int pseudo_no = REGNO (pseudo);
6945 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6947 /* We don't need to test full validity of last_regno for
6948 inherit here; we only want to know if the store actually
6949 matches the pseudo. */
6950 if (reg_reloaded_contents[last_regno] == pseudo_no
6951 && spill_reg_store[last_regno]
6952 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6953 delete_output_reload (insn, j, last_regno);
6957 old = reload_out_reg[j];
6959 && reload_reg_rtx[j] != old
6960 && reload_reg_rtx[j] != 0)
6962 register rtx reloadreg = reload_reg_rtx[j];
6963 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6964 register rtx second_reloadreg = 0;
6967 enum machine_mode mode;
6970 /* An output operand that dies right away does need a reload,
6971 but need not be copied from it. Show the new location in the
6973 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6974 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6976 XEXP (note, 0) = reload_reg_rtx[j];
6979 /* Likewise for a SUBREG of an operand that dies. */
6980 else if (GET_CODE (old) == SUBREG
6981 && GET_CODE (SUBREG_REG (old)) == REG
6982 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6985 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6989 else if (GET_CODE (old) == SCRATCH)
6990 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6991 but we don't want to make an output reload. */
6995 /* Strip off of OLD any size-increasing SUBREGs such as
6996 (SUBREG:SI foo:QI 0). */
6998 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
6999 && (GET_MODE_SIZE (GET_MODE (old))
7000 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
7001 old = SUBREG_REG (old);
7004 /* If is a JUMP_INSN, we can't support output reloads yet. */
7005 if (GET_CODE (insn) == JUMP_INSN)
7008 if (reload_when_needed[j] == RELOAD_OTHER)
7011 push_to_sequence (output_reload_insns[reload_opnum[j]]);
7013 old = reload_out[j];
7015 /* Determine the mode to reload in.
7016 See comments above (for input reloading). */
7018 mode = GET_MODE (old);
7019 if (mode == VOIDmode)
7021 /* VOIDmode should never happen for an output. */
7022 if (asm_noperands (PATTERN (insn)) < 0)
7023 /* It's the compiler's fault. */
7024 fatal_insn ("VOIDmode on an output", insn);
7025 error_for_asm (insn, "output operand is constant in `asm'");
7026 /* Prevent crash--use something we know is valid. */
7028 old = gen_rtx_REG (mode, REGNO (reloadreg));
7031 if (GET_MODE (reloadreg) != mode)
7032 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
7034 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7036 /* If we need two reload regs, set RELOADREG to the intermediate
7037 one, since it will be stored into OLD. We might need a secondary
7038 register only for an input reload, so check again here. */
7040 if (reload_secondary_out_reload[j] >= 0)
7044 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
7045 && reg_equiv_mem[REGNO (old)] != 0)
7046 real_old = reg_equiv_mem[REGNO (old)];
7048 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
7052 second_reloadreg = reloadreg;
7053 reloadreg = reload_reg_rtx[reload_secondary_out_reload[j]];
7055 /* See if RELOADREG is to be used as a scratch register
7056 or as an intermediate register. */
7057 if (reload_secondary_out_icode[j] != CODE_FOR_nothing)
7059 emit_insn ((GEN_FCN (reload_secondary_out_icode[j])
7060 (real_old, second_reloadreg, reloadreg)));
7065 /* See if we need both a scratch and intermediate reload
7068 int secondary_reload = reload_secondary_out_reload[j];
7069 enum insn_code tertiary_icode
7070 = reload_secondary_out_icode[secondary_reload];
7072 if (GET_MODE (reloadreg) != mode)
7073 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
7075 if (tertiary_icode != CODE_FOR_nothing)
7078 = reload_reg_rtx[reload_secondary_out_reload[secondary_reload]];
7081 /* Copy primary reload reg to secondary reload reg.
7082 (Note that these have been swapped above, then
7083 secondary reload reg to OLD using our insn. */
7085 /* If REAL_OLD is a paradoxical SUBREG, remove it
7086 and try to put the opposite SUBREG on
7088 if (GET_CODE (real_old) == SUBREG
7089 && (GET_MODE_SIZE (GET_MODE (real_old))
7090 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7091 && 0 != (tem = gen_lowpart_common
7092 (GET_MODE (SUBREG_REG (real_old)),
7094 real_old = SUBREG_REG (real_old), reloadreg = tem;
7096 gen_reload (reloadreg, second_reloadreg,
7097 reload_opnum[j], reload_when_needed[j]);
7098 emit_insn ((GEN_FCN (tertiary_icode)
7099 (real_old, reloadreg, third_reloadreg)));
7104 /* Copy between the reload regs here and then to
7107 gen_reload (reloadreg, second_reloadreg,
7108 reload_opnum[j], reload_when_needed[j]);
7114 /* Output the last reload insn. */
7119 /* Don't output the last reload if OLD is not the dest of
7120 INSN and is in the src and is clobbered by INSN. */
7121 if (! flag_expensive_optimizations
7122 || GET_CODE (old) != REG
7123 || !(set = single_set (insn))
7124 || rtx_equal_p (old, SET_DEST (set))
7125 || !reg_mentioned_p (old, SET_SRC (set))
7126 || !regno_clobbered_p (REGNO (old), insn))
7127 gen_reload (old, reloadreg, reload_opnum[j],
7128 reload_when_needed[j]);
7131 /* Look at all insns we emitted, just to be safe. */
7132 for (p = get_insns (); p; p = NEXT_INSN (p))
7133 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
7135 rtx pat = PATTERN (p);
7137 /* If this output reload doesn't come from a spill reg,
7138 clear any memory of reloaded copies of the pseudo reg.
7139 If this output reload comes from a spill reg,
7140 reg_has_output_reload will make this do nothing. */
7141 note_stores (pat, forget_old_reloads_1);
7143 if (reg_mentioned_p (reload_reg_rtx[j], pat))
7145 rtx set = single_set (insn);
7146 if (reload_spill_index[j] < 0
7148 && SET_SRC (set) == reload_reg_rtx[j])
7150 int src = REGNO (SET_SRC (set));
7152 reload_spill_index[j] = src;
7153 SET_HARD_REG_BIT (reg_is_output_reload, src);
7154 if (find_regno_note (insn, REG_DEAD, src))
7155 SET_HARD_REG_BIT (reg_reloaded_died, src);
7157 if (REGNO (reload_reg_rtx[j]) < FIRST_PSEUDO_REGISTER)
7159 int s = reload_secondary_out_reload[j];
7160 set = single_set (p);
7161 /* If this reload copies only to the secondary reload
7162 register, the secondary reload does the actual
7164 if (s >= 0 && set == NULL_RTX)
7165 ; /* We can't tell what function the secondary reload
7166 has and where the actual store to the pseudo is
7167 made; leave new_spill_reg_store alone. */
7169 && SET_SRC (set) == reload_reg_rtx[j]
7170 && SET_DEST (set) == reload_reg_rtx[s])
7172 /* Usually the next instruction will be the
7173 secondary reload insn; if we can confirm
7174 that it is, setting new_spill_reg_store to
7175 that insn will allow an extra optimization. */
7176 rtx s_reg = reload_reg_rtx[s];
7177 rtx next = NEXT_INSN (p);
7178 reload_out[s] = reload_out[j];
7179 reload_out_reg[s] = reload_out_reg[j];
7180 set = single_set (next);
7181 if (set && SET_SRC (set) == s_reg
7182 && ! new_spill_reg_store[REGNO (s_reg)])
7184 SET_HARD_REG_BIT (reg_is_output_reload,
7186 new_spill_reg_store[REGNO (s_reg)] = next;
7190 new_spill_reg_store[REGNO (reload_reg_rtx[j])] = p;
7195 if (reload_when_needed[j] == RELOAD_OTHER)
7197 emit_insns (other_output_reload_insns[reload_opnum[j]]);
7198 other_output_reload_insns[reload_opnum[j]] = get_insns ();
7201 output_reload_insns[reload_opnum[j]] = get_insns ();
7207 /* Now write all the insns we made for reloads in the order expected by
7208 the allocation functions. Prior to the insn being reloaded, we write
7209 the following reloads:
7211 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7213 RELOAD_OTHER reloads.
7215 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7216 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7217 RELOAD_FOR_INPUT reload for the operand.
7219 RELOAD_FOR_OPADDR_ADDRS reloads.
7221 RELOAD_FOR_OPERAND_ADDRESS reloads.
7223 After the insn being reloaded, we write the following:
7225 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7226 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7227 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7228 reloads for the operand. The RELOAD_OTHER output reloads are
7229 output in descending order by reload number. */
7231 emit_insns_before (other_input_address_reload_insns, insn);
7232 emit_insns_before (other_input_reload_insns, insn);
7234 for (j = 0; j < reload_n_operands; j++)
7236 emit_insns_before (inpaddr_address_reload_insns[j], insn);
7237 emit_insns_before (input_address_reload_insns[j], insn);
7238 emit_insns_before (input_reload_insns[j], insn);
7241 emit_insns_before (other_operand_reload_insns, insn);
7242 emit_insns_before (operand_reload_insns, insn);
7244 for (j = 0; j < reload_n_operands; j++)
7246 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
7247 emit_insns_before (output_address_reload_insns[j], following_insn);
7248 emit_insns_before (output_reload_insns[j], following_insn);
7249 emit_insns_before (other_output_reload_insns[j], following_insn);
7252 /* Keep basic block info up to date. */
7255 if (basic_block_head[chain->block] == insn)
7256 basic_block_head[chain->block] = NEXT_INSN (before_insn);
7257 if (basic_block_end[chain->block] == insn)
7258 basic_block_end[chain->block] = PREV_INSN (following_insn);
7261 /* For all the spill regs newly reloaded in this instruction,
7262 record what they were reloaded from, so subsequent instructions
7263 can inherit the reloads.
7265 Update spill_reg_store for the reloads of this insn.
7266 Copy the elements that were updated in the loop above. */
7268 for (j = 0; j < n_reloads; j++)
7270 register int r = reload_order[j];
7271 register int i = reload_spill_index[r];
7273 /* I is nonneg if this reload used a register.
7274 If reload_reg_rtx[r] is 0, this is an optional reload
7275 that we opted to ignore. */
7277 if (i >= 0 && reload_reg_rtx[r] != 0)
7280 = HARD_REGNO_NREGS (i, GET_MODE (reload_reg_rtx[r]));
7282 int part_reaches_end = 0;
7283 int all_reaches_end = 1;
7285 /* For a multi register reload, we need to check if all or part
7286 of the value lives to the end. */
7287 for (k = 0; k < nr; k++)
7289 if (reload_reg_reaches_end_p (i + k, reload_opnum[r],
7290 reload_when_needed[r]))
7291 part_reaches_end = 1;
7293 all_reaches_end = 0;
7296 /* Ignore reloads that don't reach the end of the insn in
7298 if (all_reaches_end)
7300 /* First, clear out memory of what used to be in this spill reg.
7301 If consecutive registers are used, clear them all. */
7303 for (k = 0; k < nr; k++)
7304 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7306 /* Maybe the spill reg contains a copy of reload_out. */
7307 if (reload_out[r] != 0
7308 && (GET_CODE (reload_out[r]) == REG
7310 || ! reload_out_reg[r]
7312 || GET_CODE (reload_out_reg[r]) == REG))
7314 rtx out = (GET_CODE (reload_out[r]) == REG
7318 /* AUTO_INC */ : XEXP (reload_in_reg[r], 0));
7319 register int nregno = REGNO (out);
7320 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7321 : HARD_REGNO_NREGS (nregno,
7322 GET_MODE (reload_reg_rtx[r])));
7324 spill_reg_store[i] = new_spill_reg_store[i];
7325 spill_reg_stored_to[i] = out;
7326 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
7328 /* If NREGNO is a hard register, it may occupy more than
7329 one register. If it does, say what is in the
7330 rest of the registers assuming that both registers
7331 agree on how many words the object takes. If not,
7332 invalidate the subsequent registers. */
7334 if (nregno < FIRST_PSEUDO_REGISTER)
7335 for (k = 1; k < nnr; k++)
7336 reg_last_reload_reg[nregno + k]
7338 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
7339 REGNO (reload_reg_rtx[r]) + k)
7342 /* Now do the inverse operation. */
7343 for (k = 0; k < nr; k++)
7345 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7346 reg_reloaded_contents[i + k]
7347 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7350 reg_reloaded_insn[i + k] = insn;
7351 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7355 /* Maybe the spill reg contains a copy of reload_in. Only do
7356 something if there will not be an output reload for
7357 the register being reloaded. */
7358 else if (reload_out_reg[r] == 0
7359 && reload_in[r] != 0
7360 && ((GET_CODE (reload_in[r]) == REG
7361 && REGNO (reload_in[r]) >= FIRST_PSEUDO_REGISTER
7362 && ! reg_has_output_reload[REGNO (reload_in[r])])
7363 || (GET_CODE (reload_in_reg[r]) == REG
7364 && ! reg_has_output_reload[REGNO (reload_in_reg[r])]))
7365 && ! reg_set_p (reload_reg_rtx[r], PATTERN (insn)))
7367 register int nregno;
7370 if (GET_CODE (reload_in[r]) == REG
7371 && REGNO (reload_in[r]) >= FIRST_PSEUDO_REGISTER)
7372 nregno = REGNO (reload_in[r]);
7373 else if (GET_CODE (reload_in_reg[r]) == REG)
7374 nregno = REGNO (reload_in_reg[r]);
7376 nregno = REGNO (XEXP (reload_in_reg[r], 0));
7378 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7379 : HARD_REGNO_NREGS (nregno,
7380 GET_MODE (reload_reg_rtx[r])));
7382 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
7384 if (nregno < FIRST_PSEUDO_REGISTER)
7385 for (k = 1; k < nnr; k++)
7386 reg_last_reload_reg[nregno + k]
7388 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
7389 REGNO (reload_reg_rtx[r]) + k)
7392 /* Unless we inherited this reload, show we haven't
7393 recently done a store.
7394 Previous stores of inherited auto_inc expressions
7395 also have to be discarded. */
7396 if (! reload_inherited[r]
7397 || (reload_out[r] && ! reload_out_reg[r]))
7398 spill_reg_store[i] = 0;
7400 for (k = 0; k < nr; k++)
7402 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7403 reg_reloaded_contents[i + k]
7404 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7407 reg_reloaded_insn[i + k] = insn;
7408 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7413 /* However, if part of the reload reaches the end, then we must
7414 invalidate the old info for the part that survives to the end. */
7415 else if (part_reaches_end)
7417 for (k = 0; k < nr; k++)
7418 if (reload_reg_reaches_end_p (i + k,
7420 reload_when_needed[r]))
7421 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7425 /* The following if-statement was #if 0'd in 1.34 (or before...).
7426 It's reenabled in 1.35 because supposedly nothing else
7427 deals with this problem. */
7429 /* If a register gets output-reloaded from a non-spill register,
7430 that invalidates any previous reloaded copy of it.
7431 But forget_old_reloads_1 won't get to see it, because
7432 it thinks only about the original insn. So invalidate it here. */
7433 if (i < 0 && reload_out[r] != 0
7434 && (GET_CODE (reload_out[r]) == REG
7435 || (GET_CODE (reload_out[r]) == MEM
7436 && GET_CODE (reload_out_reg[r]) == REG)))
7438 rtx out = (GET_CODE (reload_out[r]) == REG
7439 ? reload_out[r] : reload_out_reg[r]);
7440 register int nregno = REGNO (out);
7441 if (nregno >= FIRST_PSEUDO_REGISTER)
7443 rtx src_reg, store_insn;
7445 reg_last_reload_reg[nregno] = 0;
7447 /* If we can find a hard register that is stored, record
7448 the storing insn so that we may delete this insn with
7449 delete_output_reload. */
7450 src_reg = reload_reg_rtx[r];
7452 /* If this is an optional reload, try to find the source reg
7453 from an input reload. */
7456 rtx set = single_set (insn);
7457 if (SET_DEST (set) == reload_out[r])
7461 src_reg = SET_SRC (set);
7463 for (k = 0; k < n_reloads; k++)
7465 if (reload_in[k] == src_reg)
7467 src_reg = reload_reg_rtx[k];
7474 store_insn = new_spill_reg_store[REGNO (src_reg)];
7475 if (src_reg && GET_CODE (src_reg) == REG
7476 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7478 int src_regno = REGNO (src_reg);
7479 int nr = HARD_REGNO_NREGS (src_regno, reload_mode[r]);
7480 /* The place where to find a death note varies with
7481 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7482 necessarily checked exactly in the code that moves
7483 notes, so just check both locations. */
7484 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7486 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7489 spill_reg_store[src_regno + nr] = store_insn;
7490 spill_reg_stored_to[src_regno + nr] = out;
7491 reg_reloaded_contents[src_regno + nr] = nregno;
7492 reg_reloaded_insn[src_regno + nr] = store_insn;
7493 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7494 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7495 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7497 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7499 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7501 reg_last_reload_reg[nregno] = src_reg;
7506 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (reload_out[r]));
7508 while (num_regs-- > 0)
7509 reg_last_reload_reg[nregno + num_regs] = 0;
7513 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7516 /* Emit code to perform a reload from IN (which may be a reload register) to
7517 OUT (which may also be a reload register). IN or OUT is from operand
7518 OPNUM with reload type TYPE.
7520 Returns first insn emitted. */
7523 gen_reload (out, in, opnum, type)
7527 enum reload_type type;
7529 rtx last = get_last_insn ();
7532 /* If IN is a paradoxical SUBREG, remove it and try to put the
7533 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7534 if (GET_CODE (in) == SUBREG
7535 && (GET_MODE_SIZE (GET_MODE (in))
7536 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7537 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7538 in = SUBREG_REG (in), out = tem;
7539 else if (GET_CODE (out) == SUBREG
7540 && (GET_MODE_SIZE (GET_MODE (out))
7541 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7542 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7543 out = SUBREG_REG (out), in = tem;
7545 /* How to do this reload can get quite tricky. Normally, we are being
7546 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7547 register that didn't get a hard register. In that case we can just
7548 call emit_move_insn.
7550 We can also be asked to reload a PLUS that adds a register or a MEM to
7551 another register, constant or MEM. This can occur during frame pointer
7552 elimination and while reloading addresses. This case is handled by
7553 trying to emit a single insn to perform the add. If it is not valid,
7554 we use a two insn sequence.
7556 Finally, we could be called to handle an 'o' constraint by putting
7557 an address into a register. In that case, we first try to do this
7558 with a named pattern of "reload_load_address". If no such pattern
7559 exists, we just emit a SET insn and hope for the best (it will normally
7560 be valid on machines that use 'o').
7562 This entire process is made complex because reload will never
7563 process the insns we generate here and so we must ensure that
7564 they will fit their constraints and also by the fact that parts of
7565 IN might be being reloaded separately and replaced with spill registers.
7566 Because of this, we are, in some sense, just guessing the right approach
7567 here. The one listed above seems to work.
7569 ??? At some point, this whole thing needs to be rethought. */
7571 if (GET_CODE (in) == PLUS
7572 && (GET_CODE (XEXP (in, 0)) == REG
7573 || GET_CODE (XEXP (in, 0)) == SUBREG
7574 || GET_CODE (XEXP (in, 0)) == MEM)
7575 && (GET_CODE (XEXP (in, 1)) == REG
7576 || GET_CODE (XEXP (in, 1)) == SUBREG
7577 || CONSTANT_P (XEXP (in, 1))
7578 || GET_CODE (XEXP (in, 1)) == MEM))
7580 /* We need to compute the sum of a register or a MEM and another
7581 register, constant, or MEM, and put it into the reload
7582 register. The best possible way of doing this is if the machine
7583 has a three-operand ADD insn that accepts the required operands.
7585 The simplest approach is to try to generate such an insn and see if it
7586 is recognized and matches its constraints. If so, it can be used.
7588 It might be better not to actually emit the insn unless it is valid,
7589 but we need to pass the insn as an operand to `recog' and
7590 `extract_insn' and it is simpler to emit and then delete the insn if
7591 not valid than to dummy things up. */
7593 rtx op0, op1, tem, insn;
7596 op0 = find_replacement (&XEXP (in, 0));
7597 op1 = find_replacement (&XEXP (in, 1));
7599 /* Since constraint checking is strict, commutativity won't be
7600 checked, so we need to do that here to avoid spurious failure
7601 if the add instruction is two-address and the second operand
7602 of the add is the same as the reload reg, which is frequently
7603 the case. If the insn would be A = B + A, rearrange it so
7604 it will be A = A + B as constrain_operands expects. */
7606 if (GET_CODE (XEXP (in, 1)) == REG
7607 && REGNO (out) == REGNO (XEXP (in, 1)))
7608 tem = op0, op0 = op1, op1 = tem;
7610 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7611 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7613 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7614 code = recog_memoized (insn);
7618 extract_insn (insn);
7619 /* We want constrain operands to treat this insn strictly in
7620 its validity determination, i.e., the way it would after reload
7622 if (constrain_operands (1))
7626 delete_insns_since (last);
7628 /* If that failed, we must use a conservative two-insn sequence.
7629 use move to copy constant, MEM, or pseudo register to the reload
7630 register since "move" will be able to handle an arbitrary operand,
7631 unlike add which can't, in general. Then add the registers.
7633 If there is another way to do this for a specific machine, a
7634 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7637 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7638 || (GET_CODE (op1) == REG
7639 && REGNO (op1) >= FIRST_PSEUDO_REGISTER))
7640 tem = op0, op0 = op1, op1 = tem;
7642 gen_reload (out, op0, opnum, type);
7644 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7645 This fixes a problem on the 32K where the stack pointer cannot
7646 be used as an operand of an add insn. */
7648 if (rtx_equal_p (op0, op1))
7651 insn = emit_insn (gen_add2_insn (out, op1));
7653 /* If that failed, copy the address register to the reload register.
7654 Then add the constant to the reload register. */
7656 code = recog_memoized (insn);
7660 extract_insn (insn);
7661 /* We want constrain operands to treat this insn strictly in
7662 its validity determination, i.e., the way it would after reload
7664 if (constrain_operands (1))
7666 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7668 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7673 delete_insns_since (last);
7675 gen_reload (out, op1, opnum, type);
7676 insn = emit_insn (gen_add2_insn (out, op0));
7677 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7680 #ifdef SECONDARY_MEMORY_NEEDED
7681 /* If we need a memory location to do the move, do it that way. */
7682 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7683 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7684 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7685 REGNO_REG_CLASS (REGNO (out)),
7688 /* Get the memory to use and rewrite both registers to its mode. */
7689 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7691 if (GET_MODE (loc) != GET_MODE (out))
7692 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7694 if (GET_MODE (loc) != GET_MODE (in))
7695 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7697 gen_reload (loc, in, opnum, type);
7698 gen_reload (out, loc, opnum, type);
7702 /* If IN is a simple operand, use gen_move_insn. */
7703 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7704 emit_insn (gen_move_insn (out, in));
7706 #ifdef HAVE_reload_load_address
7707 else if (HAVE_reload_load_address)
7708 emit_insn (gen_reload_load_address (out, in));
7711 /* Otherwise, just write (set OUT IN) and hope for the best. */
7713 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7715 /* Return the first insn emitted.
7716 We can not just return get_last_insn, because there may have
7717 been multiple instructions emitted. Also note that gen_move_insn may
7718 emit more than one insn itself, so we can not assume that there is one
7719 insn emitted per emit_insn_before call. */
7721 return last ? NEXT_INSN (last) : get_insns ();
7724 /* Delete a previously made output-reload
7725 whose result we now believe is not needed.
7726 First we double-check.
7728 INSN is the insn now being processed.
7729 LAST_RELOAD_REG is the hard register number for which we want to delete
7730 the last output reload.
7731 J is the reload-number that originally used REG. The caller has made
7732 certain that reload J doesn't use REG any longer for input. */
7735 delete_output_reload (insn, j, last_reload_reg)
7738 int last_reload_reg;
7740 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7741 rtx reg = spill_reg_stored_to[last_reload_reg];
7744 int n_inherited = 0;
7748 /* Get the raw pseudo-register referred to. */
7750 while (GET_CODE (reg) == SUBREG)
7751 reg = SUBREG_REG (reg);
7752 substed = reg_equiv_memory_loc[REGNO (reg)];
7754 /* This is unsafe if the operand occurs more often in the current
7755 insn than it is inherited. */
7756 for (k = n_reloads - 1; k >= 0; k--)
7758 rtx reg2 = reload_in[k];
7761 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7762 reg2 = reload_in_reg[k];
7764 if (reload_out[k] && ! reload_out_reg[k])
7765 reg2 = XEXP (reload_in_reg[k], 0);
7767 while (GET_CODE (reg2) == SUBREG)
7768 reg2 = SUBREG_REG (reg2);
7769 if (rtx_equal_p (reg2, reg))
7771 if (reload_inherited[k] || reload_override_in[k] || k == j)
7774 reg2 = reload_out_reg[k];
7777 while (GET_CODE (reg2) == SUBREG)
7778 reg2 = XEXP (reg2, 0);
7779 if (rtx_equal_p (reg2, reg))
7786 n_occurrences = count_occurrences (PATTERN (insn), reg);
7788 n_occurrences += count_occurrences (PATTERN (insn), substed);
7789 if (n_occurrences > n_inherited)
7792 /* If the pseudo-reg we are reloading is no longer referenced
7793 anywhere between the store into it and here,
7794 and no jumps or labels intervene, then the value can get
7795 here through the reload reg alone.
7796 Otherwise, give up--return. */
7797 for (i1 = NEXT_INSN (output_reload_insn);
7798 i1 != insn; i1 = NEXT_INSN (i1))
7800 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7802 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7803 && reg_mentioned_p (reg, PATTERN (i1)))
7805 /* If this is USE in front of INSN, we only have to check that
7806 there are no more references than accounted for by inheritance. */
7807 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7809 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7810 i1 = NEXT_INSN (i1);
7812 if (n_occurrences <= n_inherited && i1 == insn)
7818 /* The caller has already checked that REG dies or is set in INSN.
7819 It has also checked that we are optimizing, and thus some inaccurancies
7820 in the debugging information are acceptable.
7821 So we could just delete output_reload_insn.
7822 But in some cases we can improve the debugging information without
7823 sacrificing optimization - maybe even improving the code:
7824 See if the pseudo reg has been completely replaced
7825 with reload regs. If so, delete the store insn
7826 and forget we had a stack slot for the pseudo. */
7827 if (reload_out[j] != reload_in[j]
7828 && REG_N_DEATHS (REGNO (reg)) == 1
7829 && REG_N_SETS (REGNO (reg)) == 1
7830 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7831 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7835 /* We know that it was used only between here
7836 and the beginning of the current basic block.
7837 (We also know that the last use before INSN was
7838 the output reload we are thinking of deleting, but never mind that.)
7839 Search that range; see if any ref remains. */
7840 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7842 rtx set = single_set (i2);
7844 /* Uses which just store in the pseudo don't count,
7845 since if they are the only uses, they are dead. */
7846 if (set != 0 && SET_DEST (set) == reg)
7848 if (GET_CODE (i2) == CODE_LABEL
7849 || GET_CODE (i2) == JUMP_INSN)
7851 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7852 && reg_mentioned_p (reg, PATTERN (i2)))
7854 /* Some other ref remains; just delete the output reload we
7856 delete_address_reloads (output_reload_insn, insn);
7857 PUT_CODE (output_reload_insn, NOTE);
7858 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7859 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7864 /* Delete the now-dead stores into this pseudo. */
7865 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7867 rtx set = single_set (i2);
7869 if (set != 0 && SET_DEST (set) == reg)
7871 delete_address_reloads (i2, insn);
7872 /* This might be a basic block head,
7873 thus don't use delete_insn. */
7874 PUT_CODE (i2, NOTE);
7875 NOTE_SOURCE_FILE (i2) = 0;
7876 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7878 if (GET_CODE (i2) == CODE_LABEL
7879 || GET_CODE (i2) == JUMP_INSN)
7883 /* For the debugging info,
7884 say the pseudo lives in this reload reg. */
7885 reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
7886 alter_reg (REGNO (reg), -1);
7888 delete_address_reloads (output_reload_insn, insn);
7889 PUT_CODE (output_reload_insn, NOTE);
7890 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7891 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7895 /* We are going to delete DEAD_INSN. Recursively delete loads of
7896 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7897 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7899 delete_address_reloads (dead_insn, current_insn)
7900 rtx dead_insn, current_insn;
7902 rtx set = single_set (dead_insn);
7903 rtx set2, dst, prev, next;
7906 rtx dst = SET_DEST (set);
7907 if (GET_CODE (dst) == MEM)
7908 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7910 /* If we deleted the store from a reloaded post_{in,de}c expression,
7911 we can delete the matching adds. */
7912 prev = PREV_INSN (dead_insn);
7913 next = NEXT_INSN (dead_insn);
7914 if (! prev || ! next)
7916 set = single_set (next);
7917 set2 = single_set (prev);
7919 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7920 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7921 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7923 dst = SET_DEST (set);
7924 if (! rtx_equal_p (dst, SET_DEST (set2))
7925 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7926 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7927 || (INTVAL (XEXP (SET_SRC (set), 1))
7928 != - INTVAL (XEXP (SET_SRC (set2), 1))))
7934 /* Subfunction of delete_address_reloads: process registers found in X. */
7936 delete_address_reloads_1 (dead_insn, x, current_insn)
7937 rtx dead_insn, x, current_insn;
7939 rtx prev, set, dst, i2;
7941 enum rtx_code code = GET_CODE (x);
7945 char *fmt= GET_RTX_FORMAT (code);
7946 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7949 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7950 else if (fmt[i] == 'E')
7952 for (j = XVECLEN (x, i) - 1; j >=0; j--)
7953 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7960 if (spill_reg_order[REGNO (x)] < 0)
7963 /* Scan backwards for the insn that sets x. This might be a way back due
7965 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7967 code = GET_CODE (prev);
7968 if (code == CODE_LABEL || code == JUMP_INSN)
7970 if (GET_RTX_CLASS (code) != 'i')
7972 if (reg_set_p (x, PATTERN (prev)))
7974 if (reg_referenced_p (x, PATTERN (prev)))
7977 if (! prev || INSN_UID (prev) < reload_first_uid)
7979 /* Check that PREV only sets the reload register. */
7980 set = single_set (prev);
7983 dst = SET_DEST (set);
7984 if (GET_CODE (dst) != REG
7985 || ! rtx_equal_p (dst, x))
7987 if (! reg_set_p (dst, PATTERN (dead_insn)))
7989 /* Check if DST was used in a later insn -
7990 it might have been inherited. */
7991 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7993 if (GET_CODE (i2) == CODE_LABEL)
7995 if (GET_RTX_CLASS (GET_CODE (i2)) != 'i')
7997 if (reg_referenced_p (dst, PATTERN (i2)))
7999 /* If there is a reference to the register in the current insn,
8000 it might be loaded in a non-inherited reload. If no other
8001 reload uses it, that means the register is set before
8003 if (i2 == current_insn)
8005 for (j = n_reloads - 1; j >= 0; j--)
8006 if ((reload_reg_rtx[j] == dst && reload_inherited[j])
8007 || reload_override_in[j] == dst)
8009 for (j = n_reloads - 1; j >= 0; j--)
8010 if (reload_in[j] && reload_reg_rtx[j] == dst)
8017 if (GET_CODE (i2) == JUMP_INSN)
8019 if (reg_set_p (dst, PATTERN (i2)))
8021 /* If DST is still live at CURRENT_INSN, check if it is used for
8023 if (i2 == current_insn)
8025 for (j = n_reloads - 1; j >= 0; j--)
8026 if ((reload_reg_rtx[j] == dst && reload_inherited[j])
8027 || reload_override_in[j] == dst)
8029 /* ??? We can't finish the loop here, because dst might be
8030 allocated to a pseudo in this block if no reload in this
8031 block needs any of the clsses containing DST - see
8032 spill_hard_reg. There is no easy way to tell this, so we
8033 have to scan till the end of the basic block. */
8037 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8038 reg_reloaded_contents[REGNO (dst)] = -1;
8039 /* Can't use delete_insn here because PREV might be a basic block head. */
8040 PUT_CODE (prev, NOTE);
8041 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
8042 NOTE_SOURCE_FILE (prev) = 0;
8045 /* Output reload-insns to reload VALUE into RELOADREG.
8046 VALUE is an autoincrement or autodecrement RTX whose operand
8047 is a register or memory location;
8048 so reloading involves incrementing that location.
8049 IN is either identical to VALUE, or some cheaper place to reload from.
8051 INC_AMOUNT is the number to increment or decrement by (always positive).
8052 This cannot be deduced from VALUE.
8054 Return the instruction that stores into RELOADREG. */
8057 inc_for_reload (reloadreg, in, value, inc_amount)
8062 /* REG or MEM to be copied and incremented. */
8063 rtx incloc = XEXP (value, 0);
8064 /* Nonzero if increment after copying. */
8065 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
8071 rtx real_in = in == value ? XEXP (in, 0) : in;
8073 /* No hard register is equivalent to this register after
8074 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
8075 we could inc/dec that register as well (maybe even using it for
8076 the source), but I'm not sure it's worth worrying about. */
8077 if (GET_CODE (incloc) == REG)
8078 reg_last_reload_reg[REGNO (incloc)] = 0;
8080 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8081 inc_amount = - inc_amount;
8083 inc = GEN_INT (inc_amount);
8085 /* If this is post-increment, first copy the location to the reload reg. */
8086 if (post && real_in != reloadreg)
8087 emit_insn (gen_move_insn (reloadreg, real_in));
8091 /* See if we can directly increment INCLOC. Use a method similar to
8092 that in gen_reload. */
8094 last = get_last_insn ();
8095 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8096 gen_rtx_PLUS (GET_MODE (incloc),
8099 code = recog_memoized (add_insn);
8102 extract_insn (add_insn);
8103 if (constrain_operands (1))
8105 /* If this is a pre-increment and we have incremented the value
8106 where it lives, copy the incremented value to RELOADREG to
8107 be used as an address. */
8110 emit_insn (gen_move_insn (reloadreg, incloc));
8115 delete_insns_since (last);
8118 /* If couldn't do the increment directly, must increment in RELOADREG.
8119 The way we do this depends on whether this is pre- or post-increment.
8120 For pre-increment, copy INCLOC to the reload register, increment it
8121 there, then save back. */
8125 if (in != reloadreg)
8126 emit_insn (gen_move_insn (reloadreg, real_in));
8127 emit_insn (gen_add2_insn (reloadreg, inc));
8128 store = emit_insn (gen_move_insn (incloc, reloadreg));
8133 Because this might be a jump insn or a compare, and because RELOADREG
8134 may not be available after the insn in an input reload, we must do
8135 the incrementation before the insn being reloaded for.
8137 We have already copied IN to RELOADREG. Increment the copy in
8138 RELOADREG, save that back, then decrement RELOADREG so it has
8139 the original value. */
8141 emit_insn (gen_add2_insn (reloadreg, inc));
8142 store = emit_insn (gen_move_insn (incloc, reloadreg));
8143 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8149 /* Return 1 if we are certain that the constraint-string STRING allows
8150 the hard register REG. Return 0 if we can't be sure of this. */
8153 constraint_accepts_reg_p (string, reg)
8158 int regno = true_regnum (reg);
8161 /* Initialize for first alternative. */
8163 /* Check that each alternative contains `g' or `r'. */
8165 switch (c = *string++)
8168 /* If an alternative lacks `g' or `r', we lose. */
8171 /* If an alternative lacks `g' or `r', we lose. */
8174 /* Initialize for next alternative. */
8179 /* Any general reg wins for this alternative. */
8180 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
8184 /* Any reg in specified class wins for this alternative. */
8186 enum reg_class class = REG_CLASS_FROM_LETTER (c);
8188 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
8194 /* Return the number of places FIND appears within X, but don't count
8195 an occurrence if some SET_DEST is FIND. */
8198 count_occurrences (x, find)
8199 register rtx x, find;
8202 register enum rtx_code code;
8203 register char *format_ptr;
8211 code = GET_CODE (x);
8226 if (GET_CODE (find) == MEM && rtx_equal_p (x, find))
8230 if (SET_DEST (x) == find)
8231 return count_occurrences (SET_SRC (x), find);
8238 format_ptr = GET_RTX_FORMAT (code);
8241 for (i = 0; i < GET_RTX_LENGTH (code); i++)
8243 switch (*format_ptr++)
8246 count += count_occurrences (XEXP (x, i), find);
8250 if (XVEC (x, i) != NULL)
8252 for (j = 0; j < XVECLEN (x, i); j++)
8253 count += count_occurrences (XVECEXP (x, i, j), find);
8261 /* This array holds values which are equivalent to a hard register
8262 during reload_cse_regs. Each array element is an EXPR_LIST of
8263 values. Each time a hard register is set, we set the corresponding
8264 array element to the value. Each time a hard register is copied
8265 into memory, we add the memory location to the corresponding array
8266 element. We don't store values or memory addresses with side
8267 effects in this array.
8269 If the value is a CONST_INT, then the mode of the containing
8270 EXPR_LIST is the mode in which that CONST_INT was referenced.
8272 We sometimes clobber a specific entry in a list. In that case, we
8273 just set XEXP (list-entry, 0) to 0. */
8275 static rtx *reg_values;
8277 /* This is a preallocated REG rtx which we use as a temporary in
8278 reload_cse_invalidate_regno, so that we don't need to allocate a
8279 new one each time through a loop in that function. */
8281 static rtx invalidate_regno_rtx;
8283 /* Invalidate any entries in reg_values which depend on REGNO,
8284 including those for REGNO itself. This is called if REGNO is
8285 changing. If CLOBBER is true, then always forget anything we
8286 currently know about REGNO. MODE is the mode of the assignment to
8287 REGNO, which is used to determine how many hard registers are being
8288 changed. If MODE is VOIDmode, then only REGNO is being changed;
8289 this is used when invalidating call clobbered registers across a
8293 reload_cse_invalidate_regno (regno, mode, clobber)
8295 enum machine_mode mode;
8301 /* Our callers don't always go through true_regnum; we may see a
8302 pseudo-register here from a CLOBBER or the like. We probably
8303 won't ever see a pseudo-register that has a real register number,
8304 for we check anyhow for safety. */
8305 if (regno >= FIRST_PSEUDO_REGISTER)
8306 regno = reg_renumber[regno];
8310 if (mode == VOIDmode)
8311 endregno = regno + 1;
8313 endregno = regno + HARD_REGNO_NREGS (regno, mode);
8316 for (i = regno; i < endregno; i++)
8319 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8323 for (x = reg_values[i]; x; x = XEXP (x, 1))
8325 if (XEXP (x, 0) != 0
8326 && refers_to_regno_p (regno, endregno, XEXP (x, 0), NULL_PTR))
8328 /* If this is the only entry on the list, clear
8329 reg_values[i]. Otherwise, just clear this entry on
8331 if (XEXP (x, 1) == 0 && x == reg_values[i])
8341 /* We must look at earlier registers, in case REGNO is part of a
8342 multi word value but is not the first register. If an earlier
8343 register has a value in a mode which overlaps REGNO, then we must
8344 invalidate that earlier register. Note that we do not need to
8345 check REGNO or later registers (we must not check REGNO itself,
8346 because we would incorrectly conclude that there was a conflict). */
8348 for (i = 0; i < regno; i++)
8352 for (x = reg_values[i]; x; x = XEXP (x, 1))
8354 if (XEXP (x, 0) != 0)
8356 PUT_MODE (invalidate_regno_rtx, GET_MODE (x));
8357 REGNO (invalidate_regno_rtx) = i;
8358 if (refers_to_regno_p (regno, endregno, invalidate_regno_rtx,
8361 reload_cse_invalidate_regno (i, VOIDmode, 1);
8369 /* The memory at address MEM_BASE is being changed.
8370 Return whether this change will invalidate VAL. */
8373 reload_cse_mem_conflict_p (mem_base, val)
8381 code = GET_CODE (val);
8384 /* Get rid of a few simple cases quickly. */
8397 if (GET_MODE (mem_base) == BLKmode
8398 || GET_MODE (val) == BLKmode)
8400 if (anti_dependence (val, mem_base))
8402 /* The address may contain nested MEMs. */
8409 fmt = GET_RTX_FORMAT (code);
8411 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8415 if (reload_cse_mem_conflict_p (mem_base, XEXP (val, i)))
8418 else if (fmt[i] == 'E')
8422 for (j = 0; j < XVECLEN (val, i); j++)
8423 if (reload_cse_mem_conflict_p (mem_base, XVECEXP (val, i, j)))
8431 /* Invalidate any entries in reg_values which are changed because of a
8432 store to MEM_RTX. If this is called because of a non-const call
8433 instruction, MEM_RTX is (mem:BLK const0_rtx). */
8436 reload_cse_invalidate_mem (mem_rtx)
8441 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8445 for (x = reg_values[i]; x; x = XEXP (x, 1))
8447 if (XEXP (x, 0) != 0
8448 && reload_cse_mem_conflict_p (mem_rtx, XEXP (x, 0)))
8450 /* If this is the only entry on the list, clear
8451 reg_values[i]. Otherwise, just clear this entry on
8453 if (XEXP (x, 1) == 0 && x == reg_values[i])
8464 /* Invalidate DEST, which is being assigned to or clobbered. The
8465 second parameter exists so that this function can be passed to
8466 note_stores; it is ignored. */
8469 reload_cse_invalidate_rtx (dest, ignore)
8471 rtx ignore ATTRIBUTE_UNUSED;
8473 while (GET_CODE (dest) == STRICT_LOW_PART
8474 || GET_CODE (dest) == SIGN_EXTRACT
8475 || GET_CODE (dest) == ZERO_EXTRACT
8476 || GET_CODE (dest) == SUBREG)
8477 dest = XEXP (dest, 0);
8479 if (GET_CODE (dest) == REG)
8480 reload_cse_invalidate_regno (REGNO (dest), GET_MODE (dest), 1);
8481 else if (GET_CODE (dest) == MEM)
8482 reload_cse_invalidate_mem (dest);
8485 /* Do a very simple CSE pass over the hard registers.
8487 This function detects no-op moves where we happened to assign two
8488 different pseudo-registers to the same hard register, and then
8489 copied one to the other. Reload will generate a useless
8490 instruction copying a register to itself.
8492 This function also detects cases where we load a value from memory
8493 into two different registers, and (if memory is more expensive than
8494 registers) changes it to simply copy the first register into the
8497 Another optimization is performed that scans the operands of each
8498 instruction to see whether the value is already available in a
8499 hard register. It then replaces the operand with the hard register
8500 if possible, much like an optional reload would. */
8503 reload_cse_regs_1 (first)
8511 init_alias_analysis ();
8513 reg_values = (rtx *) alloca (FIRST_PSEUDO_REGISTER * sizeof (rtx));
8514 bzero ((char *)reg_values, FIRST_PSEUDO_REGISTER * sizeof (rtx));
8516 /* Create our EXPR_LIST structures on reload_obstack, so that we can
8517 free them when we are done. */
8518 push_obstacks (&reload_obstack, &reload_obstack);
8519 firstobj = (char *) obstack_alloc (&reload_obstack, 0);
8521 /* We pass this to reload_cse_invalidate_mem to invalidate all of
8522 memory for a non-const call instruction. */
8523 callmem = gen_rtx_MEM (BLKmode, const0_rtx);
8525 /* This is used in reload_cse_invalidate_regno to avoid consing a
8526 new REG in a loop in that function. */
8527 invalidate_regno_rtx = gen_rtx_REG (VOIDmode, 0);
8529 for (insn = first; insn; insn = NEXT_INSN (insn))
8533 if (GET_CODE (insn) == CODE_LABEL)
8535 /* Forget all the register values at a code label. We don't
8536 try to do anything clever around jumps. */
8537 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8543 #ifdef NON_SAVING_SETJMP
8544 if (NON_SAVING_SETJMP && GET_CODE (insn) == NOTE
8545 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
8547 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8554 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8557 /* If this is a call instruction, forget anything stored in a
8558 call clobbered register, or, if this is not a const call, in
8560 if (GET_CODE (insn) == CALL_INSN)
8562 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8563 if (call_used_regs[i])
8564 reload_cse_invalidate_regno (i, VOIDmode, 1);
8566 if (! CONST_CALL_P (insn))
8567 reload_cse_invalidate_mem (callmem);
8570 body = PATTERN (insn);
8571 if (GET_CODE (body) == SET)
8574 if (reload_cse_noop_set_p (body, insn))
8576 /* If this sets the return value of the function, we must keep
8577 a USE around, in case this is in a different basic block
8578 than the final USE. Otherwise, we could loose important
8579 register lifeness information on SMALL_REGISTER_CLASSES
8580 machines, where return registers might be used as spills:
8581 subsequent passes assume that spill registers are dead at
8582 the end of a basic block. */
8583 if (REG_FUNCTION_VALUE_P (SET_DEST (body)))
8586 PATTERN (insn) = gen_rtx_USE (VOIDmode, SET_DEST (body));
8587 INSN_CODE (insn) = -1;
8588 REG_NOTES (insn) = NULL_RTX;
8589 push_obstacks (&reload_obstack, &reload_obstack);
8593 PUT_CODE (insn, NOTE);
8594 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8595 NOTE_SOURCE_FILE (insn) = 0;
8598 /* We're done with this insn. */
8602 /* It's not a no-op, but we can try to simplify it. */
8603 count += reload_cse_simplify_set (body, insn);
8606 apply_change_group ();
8608 reload_cse_simplify_operands (insn);
8610 reload_cse_record_set (body, body);
8612 else if (GET_CODE (body) == PARALLEL)
8615 rtx value = NULL_RTX;
8617 /* If every action in a PARALLEL is a noop, we can delete
8618 the entire PARALLEL. */
8619 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8621 rtx part = XVECEXP (body, 0, i);
8622 if (GET_CODE (part) == SET)
8624 if (! reload_cse_noop_set_p (part, insn))
8626 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8630 value = SET_DEST (part);
8633 else if (GET_CODE (part) != CLOBBER)
8641 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
8642 INSN_CODE (insn) = -1;
8643 REG_NOTES (insn) = NULL_RTX;
8644 push_obstacks (&reload_obstack, &reload_obstack);
8648 PUT_CODE (insn, NOTE);
8649 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8650 NOTE_SOURCE_FILE (insn) = 0;
8653 /* We're done with this insn. */
8657 /* It's not a no-op, but we can try to simplify it. */
8658 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8659 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8660 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8663 apply_change_group ();
8665 reload_cse_simplify_operands (insn);
8667 /* Look through the PARALLEL and record the values being
8668 set, if possible. Also handle any CLOBBERs. */
8669 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8671 rtx x = XVECEXP (body, 0, i);
8673 if (GET_CODE (x) == SET)
8674 reload_cse_record_set (x, body);
8676 note_stores (x, reload_cse_invalidate_rtx);
8680 note_stores (body, reload_cse_invalidate_rtx);
8683 /* Clobber any registers which appear in REG_INC notes. We
8684 could keep track of the changes to their values, but it is
8685 unlikely to help. */
8689 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
8690 if (REG_NOTE_KIND (x) == REG_INC)
8691 reload_cse_invalidate_rtx (XEXP (x, 0), NULL_RTX);
8695 /* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only
8696 after we have processed the insn. */
8697 if (GET_CODE (insn) == CALL_INSN)
8701 for (x = CALL_INSN_FUNCTION_USAGE (insn); x; x = XEXP (x, 1))
8702 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
8703 reload_cse_invalidate_rtx (XEXP (XEXP (x, 0), 0), NULL_RTX);
8707 /* Free all the temporary structures we created, and go back to the
8708 regular obstacks. */
8709 obstack_free (&reload_obstack, firstobj);
8713 /* Call cse / combine like post-reload optimization phases.
8714 FIRST is the first instruction. */
8716 reload_cse_regs (first)
8719 reload_cse_regs_1 (first);
8721 reload_cse_move2add (first);
8722 if (flag_expensive_optimizations)
8723 reload_cse_regs_1 (first);
8726 /* Return whether the values known for REGNO are equal to VAL. MODE
8727 is the mode of the object that VAL is being copied to; this matters
8728 if VAL is a CONST_INT. */
8731 reload_cse_regno_equal_p (regno, val, mode)
8734 enum machine_mode mode;
8741 for (x = reg_values[regno]; x; x = XEXP (x, 1))
8742 if (XEXP (x, 0) != 0
8743 && rtx_equal_p (XEXP (x, 0), val)
8744 && (! flag_float_store || GET_CODE (XEXP (x, 0)) != MEM
8745 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
8746 && (GET_CODE (val) != CONST_INT
8747 || mode == GET_MODE (x)
8748 || (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8749 /* On a big endian machine if the value spans more than
8750 one register then this register holds the high part of
8751 it and we can't use it.
8753 ??? We should also compare with the high part of the
8755 && !(WORDS_BIG_ENDIAN
8756 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
8757 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
8758 GET_MODE_BITSIZE (GET_MODE (x))))))
8764 /* See whether a single set is a noop. SET is the set instruction we
8765 are should check, and INSN is the instruction from which it came. */
8768 reload_cse_noop_set_p (set, insn)
8773 enum machine_mode dest_mode;
8777 src = SET_SRC (set);
8778 dest = SET_DEST (set);
8779 dest_mode = GET_MODE (dest);
8781 if (side_effects_p (src))
8784 dreg = true_regnum (dest);
8785 sreg = true_regnum (src);
8787 /* Check for setting a register to itself. In this case, we don't
8788 have to worry about REG_DEAD notes. */
8789 if (dreg >= 0 && dreg == sreg)
8795 /* Check for setting a register to itself. */
8799 /* Check for setting a register to a value which we already know
8800 is in the register. */
8801 else if (reload_cse_regno_equal_p (dreg, src, dest_mode))
8804 /* Check for setting a register DREG to another register SREG
8805 where SREG is equal to a value which is already in DREG. */
8810 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
8814 if (XEXP (x, 0) == 0)
8817 if (dest_mode == GET_MODE (x))
8819 else if (GET_MODE_BITSIZE (dest_mode)
8820 < GET_MODE_BITSIZE (GET_MODE (x)))
8821 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
8826 && reload_cse_regno_equal_p (dreg, tmp, dest_mode))
8834 else if (GET_CODE (dest) == MEM)
8836 /* Check for storing a register to memory when we know that the
8837 register is equivalent to the memory location. */
8839 && reload_cse_regno_equal_p (sreg, dest, dest_mode)
8840 && ! side_effects_p (dest))
8847 /* Try to simplify a single SET instruction. SET is the set pattern.
8848 INSN is the instruction it came from.
8849 This function only handles one case: if we set a register to a value
8850 which is not a register, we try to find that value in some other register
8851 and change the set into a register copy. */
8854 reload_cse_simplify_set (set, insn)
8860 enum machine_mode dest_mode;
8861 enum reg_class dclass;
8864 dreg = true_regnum (SET_DEST (set));
8868 src = SET_SRC (set);
8869 if (side_effects_p (src) || true_regnum (src) >= 0)
8872 dclass = REGNO_REG_CLASS (dreg);
8874 /* If memory loads are cheaper than register copies, don't change them. */
8875 if (GET_CODE (src) == MEM
8876 && MEMORY_MOVE_COST (GET_MODE (src), dclass, 1) < 2)
8879 /* If the constant is cheaper than a register, don't change it. */
8880 if (CONSTANT_P (src)
8881 && rtx_cost (src, SET) < 2)
8884 dest_mode = GET_MODE (SET_DEST (set));
8885 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8888 && REGISTER_MOVE_COST (REGNO_REG_CLASS (i), dclass) == 2
8889 && reload_cse_regno_equal_p (i, src, dest_mode))
8893 /* Pop back to the real obstacks while changing the insn. */
8896 validated = validate_change (insn, &SET_SRC (set),
8897 gen_rtx_REG (dest_mode, i), 1);
8899 /* Go back to the obstack we are using for temporary
8901 push_obstacks (&reload_obstack, &reload_obstack);
8910 /* Try to replace operands in INSN with equivalent values that are already
8911 in registers. This can be viewed as optional reloading.
8913 For each non-register operand in the insn, see if any hard regs are
8914 known to be equivalent to that operand. Record the alternatives which
8915 can accept these hard registers. Among all alternatives, select the
8916 ones which are better or equal to the one currently matching, where
8917 "better" is in terms of '?' and '!' constraints. Among the remaining
8918 alternatives, select the one which replaces most operands with
8922 reload_cse_simplify_operands (insn)
8925 #ifdef REGISTER_CONSTRAINTS
8928 char *constraints[MAX_RECOG_OPERANDS];
8930 /* Vector recording how bad an alternative is. */
8931 int *alternative_reject;
8932 /* Vector recording how many registers can be introduced by choosing
8933 this alternative. */
8934 int *alternative_nregs;
8935 /* Array of vectors recording, for each operand and each alternative,
8936 which hard register to substitute, or -1 if the operand should be
8938 int *op_alt_regno[MAX_RECOG_OPERANDS];
8939 /* Array of alternatives, sorted in order of decreasing desirability. */
8940 int *alternative_order;
8941 rtx reg = gen_rtx_REG (VOIDmode, -1);
8943 extract_insn (insn);
8945 if (recog_n_alternatives == 0 || recog_n_operands == 0)
8948 /* Figure out which alternative currently matches. */
8949 if (! constrain_operands (1))
8950 fatal_insn_not_found (insn);
8952 alternative_reject = (int *) alloca (recog_n_alternatives * sizeof (int));
8953 alternative_nregs = (int *) alloca (recog_n_alternatives * sizeof (int));
8954 alternative_order = (int *) alloca (recog_n_alternatives * sizeof (int));
8955 bzero ((char *)alternative_reject, recog_n_alternatives * sizeof (int));
8956 bzero ((char *)alternative_nregs, recog_n_alternatives * sizeof (int));
8958 for (i = 0; i < recog_n_operands; i++)
8960 enum machine_mode mode;
8964 op_alt_regno[i] = (int *) alloca (recog_n_alternatives * sizeof (int));
8965 for (j = 0; j < recog_n_alternatives; j++)
8966 op_alt_regno[i][j] = -1;
8968 p = constraints[i] = recog_constraints[i];
8969 mode = recog_operand_mode[i];
8971 /* Add the reject values for each alternative given by the constraints
8972 for this operand. */
8980 alternative_reject[j] += 3;
8982 alternative_reject[j] += 300;
8985 /* We won't change operands which are already registers. We
8986 also don't want to modify output operands. */
8987 regno = true_regnum (recog_operand[i]);
8989 || constraints[i][0] == '='
8990 || constraints[i][0] == '+')
8993 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8995 int class = (int) NO_REGS;
8997 if (! reload_cse_regno_equal_p (regno, recog_operand[i], mode))
9000 REGNO (reg) = regno;
9001 PUT_MODE (reg, mode);
9003 /* We found a register equal to this operand. Now look for all
9004 alternatives that can accept this register and have not been
9005 assigned a register they can use yet. */
9014 case '=': case '+': case '?':
9015 case '#': case '&': case '!':
9017 case '0': case '1': case '2': case '3': case '4':
9018 case 'm': case '<': case '>': case 'V': case 'o':
9019 case 'E': case 'F': case 'G': case 'H':
9020 case 's': case 'i': case 'n':
9021 case 'I': case 'J': case 'K': case 'L':
9022 case 'M': case 'N': case 'O': case 'P':
9023 #ifdef EXTRA_CONSTRAINT
9024 case 'Q': case 'R': case 'S': case 'T': case 'U':
9027 /* These don't say anything we care about. */
9031 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
9036 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
9039 case ',': case '\0':
9040 /* See if REGNO fits this alternative, and set it up as the
9041 replacement register if we don't have one for this
9042 alternative yet and the operand being replaced is not
9043 a cheap CONST_INT. */
9044 if (op_alt_regno[i][j] == -1
9045 && reg_fits_class_p (reg, class, 0, mode)
9046 && (GET_CODE (recog_operand[i]) != CONST_INT
9047 || rtx_cost (recog_operand[i], SET) > rtx_cost (reg, SET)))
9049 alternative_nregs[j]++;
9050 op_alt_regno[i][j] = regno;
9062 /* Record all alternatives which are better or equal to the currently
9063 matching one in the alternative_order array. */
9064 for (i = j = 0; i < recog_n_alternatives; i++)
9065 if (alternative_reject[i] <= alternative_reject[which_alternative])
9066 alternative_order[j++] = i;
9067 recog_n_alternatives = j;
9069 /* Sort it. Given a small number of alternatives, a dumb algorithm
9070 won't hurt too much. */
9071 for (i = 0; i < recog_n_alternatives - 1; i++)
9074 int best_reject = alternative_reject[alternative_order[i]];
9075 int best_nregs = alternative_nregs[alternative_order[i]];
9078 for (j = i + 1; j < recog_n_alternatives; j++)
9080 int this_reject = alternative_reject[alternative_order[j]];
9081 int this_nregs = alternative_nregs[alternative_order[j]];
9083 if (this_reject < best_reject
9084 || (this_reject == best_reject && this_nregs < best_nregs))
9087 best_reject = this_reject;
9088 best_nregs = this_nregs;
9092 tmp = alternative_order[best];
9093 alternative_order[best] = alternative_order[i];
9094 alternative_order[i] = tmp;
9097 /* Substitute the operands as determined by op_alt_regno for the best
9099 j = alternative_order[0];
9101 /* Pop back to the real obstacks while changing the insn. */
9104 for (i = 0; i < recog_n_operands; i++)
9106 enum machine_mode mode = recog_operand_mode[i];
9107 if (op_alt_regno[i][j] == -1)
9110 validate_change (insn, recog_operand_loc[i],
9111 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
9114 for (i = recog_n_dups - 1; i >= 0; i--)
9116 int op = recog_dup_num[i];
9117 enum machine_mode mode = recog_operand_mode[op];
9119 if (op_alt_regno[op][j] == -1)
9122 validate_change (insn, recog_dup_loc[i],
9123 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
9126 /* Go back to the obstack we are using for temporary
9128 push_obstacks (&reload_obstack, &reload_obstack);
9130 return apply_change_group ();
9136 /* These two variables are used to pass information from
9137 reload_cse_record_set to reload_cse_check_clobber. */
9139 static int reload_cse_check_clobbered;
9140 static rtx reload_cse_check_src;
9142 /* See if DEST overlaps with RELOAD_CSE_CHECK_SRC. If it does, set
9143 RELOAD_CSE_CHECK_CLOBBERED. This is called via note_stores. The
9144 second argument, which is passed by note_stores, is ignored. */
9147 reload_cse_check_clobber (dest, ignore)
9149 rtx ignore ATTRIBUTE_UNUSED;
9151 if (reg_overlap_mentioned_p (dest, reload_cse_check_src))
9152 reload_cse_check_clobbered = 1;
9155 /* Record the result of a SET instruction. SET is the set pattern.
9156 BODY is the pattern of the insn that it came from. */
9159 reload_cse_record_set (set, body)
9165 enum machine_mode dest_mode;
9167 dest = SET_DEST (set);
9168 src = SET_SRC (set);
9169 dreg = true_regnum (dest);
9170 sreg = true_regnum (src);
9171 dest_mode = GET_MODE (dest);
9173 /* Some machines don't define AUTO_INC_DEC, but they still use push
9174 instructions. We need to catch that case here in order to
9175 invalidate the stack pointer correctly. Note that invalidating
9176 the stack pointer is different from invalidating DEST. */
9178 while (GET_CODE (x) == SUBREG
9179 || GET_CODE (x) == ZERO_EXTRACT
9180 || GET_CODE (x) == SIGN_EXTRACT
9181 || GET_CODE (x) == STRICT_LOW_PART)
9183 if (push_operand (x, GET_MODE (x)))
9185 reload_cse_invalidate_rtx (stack_pointer_rtx, NULL_RTX);
9186 reload_cse_invalidate_rtx (dest, NULL_RTX);
9190 /* We can only handle an assignment to a register, or a store of a
9191 register to a memory location. For other cases, we just clobber
9192 the destination. We also have to just clobber if there are side
9193 effects in SRC or DEST. */
9194 if ((dreg < 0 && GET_CODE (dest) != MEM)
9195 || side_effects_p (src)
9196 || side_effects_p (dest))
9198 reload_cse_invalidate_rtx (dest, NULL_RTX);
9203 /* We don't try to handle values involving CC, because it's a pain
9204 to keep track of when they have to be invalidated. */
9205 if (reg_mentioned_p (cc0_rtx, src)
9206 || reg_mentioned_p (cc0_rtx, dest))
9208 reload_cse_invalidate_rtx (dest, NULL_RTX);
9213 /* If BODY is a PARALLEL, then we need to see whether the source of
9214 SET is clobbered by some other instruction in the PARALLEL. */
9215 if (GET_CODE (body) == PARALLEL)
9219 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
9223 x = XVECEXP (body, 0, i);
9227 reload_cse_check_clobbered = 0;
9228 reload_cse_check_src = src;
9229 note_stores (x, reload_cse_check_clobber);
9230 if (reload_cse_check_clobbered)
9232 reload_cse_invalidate_rtx (dest, NULL_RTX);
9242 /* This is an assignment to a register. Update the value we
9243 have stored for the register. */
9248 /* This is a copy from one register to another. Any values
9249 which were valid for SREG are now valid for DREG. If the
9250 mode changes, we use gen_lowpart_common to extract only
9251 the part of the value that is copied. */
9252 reg_values[dreg] = 0;
9253 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
9257 if (XEXP (x, 0) == 0)
9259 if (dest_mode == GET_MODE (XEXP (x, 0)))
9261 else if (GET_MODE_BITSIZE (dest_mode)
9262 > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
9265 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
9267 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, tmp,
9272 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, src, NULL_RTX);
9274 /* We've changed DREG, so invalidate any values held by other
9275 registers that depend upon it. */
9276 reload_cse_invalidate_regno (dreg, dest_mode, 0);
9278 /* If this assignment changes more than one hard register,
9279 forget anything we know about the others. */
9280 for (i = 1; i < HARD_REGNO_NREGS (dreg, dest_mode); i++)
9281 reg_values[dreg + i] = 0;
9283 else if (GET_CODE (dest) == MEM)
9285 /* Invalidate conflicting memory locations. */
9286 reload_cse_invalidate_mem (dest);
9288 /* If we're storing a register to memory, add DEST to the list
9290 if (sreg >= 0 && ! side_effects_p (dest))
9291 reg_values[sreg] = gen_rtx_EXPR_LIST (dest_mode, dest,
9296 /* We should have bailed out earlier. */
9301 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
9303 This code might also be useful when reload gave up on reg+reg addresssing
9304 because of clashes between the return register and INDEX_REG_CLASS. */
9306 /* The maximum number of uses of a register we can keep track of to
9307 replace them with reg+reg addressing. */
9308 #define RELOAD_COMBINE_MAX_USES 6
9310 /* INSN is the insn where a register has ben used, and USEP points to the
9311 location of the register within the rtl. */
9312 struct reg_use { rtx insn, *usep; };
9314 /* If the register is used in some unknown fashion, USE_INDEX is negative.
9315 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
9316 indicates where it becomes live again.
9317 Otherwise, USE_INDEX is the index of the last encountered use of the
9318 register (which is first among these we have seen since we scan backwards),
9319 OFFSET contains the constant offset that is added to the register in
9320 all encountered uses, and USE_RUID indicates the first encountered, i.e.
9321 last, of these uses. */
9324 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
9329 } reg_state[FIRST_PSEUDO_REGISTER];
9331 /* Reverse linear uid. This is increased in reload_combine while scanning
9332 the instructions from last to first. It is used to set last_label_ruid
9333 and the store_ruid / use_ruid fields in reg_state. */
9334 static int reload_combine_ruid;
9340 int first_index_reg = 1, last_index_reg = 0;
9342 int last_label_ruid;
9344 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
9345 reload has already used it where appropriate, so there is no use in
9346 trying to generate it now. */
9347 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
9350 /* To avoid wasting too much time later searching for an index register,
9351 determine the minimum and maximum index register numbers. */
9352 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9354 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i))
9356 if (! last_index_reg)
9358 first_index_reg = i;
9361 /* If no index register is available, we can quit now. */
9362 if (first_index_reg > last_index_reg)
9365 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
9366 last_label_ruid = reload_combine_ruid = 0;
9367 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9370 reg_state[i].use_index = -1;
9373 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9374 reg_state[i].store_ruid = reload_combine_ruid;
9378 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
9382 /* We cannot do our optimization across labels. Invalidating all the use
9383 information we have would be costly, so we just note where the label
9384 is and then later disable any optimization that would cross it. */
9385 if (GET_CODE (insn) == CODE_LABEL)
9386 last_label_ruid = reload_combine_ruid;
9387 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
9389 reload_combine_ruid++;
9391 /* Look for (set (REGX) (CONST_INT))
9392 (set (REGX) (PLUS (REGX) (REGY)))
9394 ... (MEM (REGX)) ...
9396 (set (REGZ) (CONST_INT))
9398 ... (MEM (PLUS (REGZ) (REGY)))... .
9400 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
9401 and that we know all uses of REGX before it dies. */
9402 set = single_set (insn);
9404 && GET_CODE (SET_DEST (set)) == REG
9405 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
9406 GET_MODE (SET_DEST (set)))
9408 && GET_CODE (SET_SRC (set)) == PLUS
9409 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
9410 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
9411 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
9413 rtx reg = SET_DEST (set);
9414 rtx plus = SET_SRC (set);
9415 rtx base = XEXP (plus, 1);
9416 rtx prev = prev_nonnote_insn (insn);
9417 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
9418 int regno = REGNO (reg);
9420 rtx reg_sum = NULL_RTX;
9422 /* Now, we need an index register.
9423 We'll set index_reg to this index register, const_reg to the
9424 register that is to be loaded with the constant
9425 (denoted as REGZ in the substitution illustration above),
9426 and reg_sum to the register-register that we want to use to
9427 substitute uses of REG (typically in MEMs) with.
9428 First check REG and BASE for being index registers;
9429 we can use them even if they are not dead. */
9430 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
9431 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
9439 /* Otherwise, look for a free index register. Since we have
9440 checked above that neiter REG nor BASE are index registers,
9441 if we find anything at all, it will be different from these
9443 for (i = first_index_reg; i <= last_index_reg; i++)
9445 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
9446 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
9447 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
9448 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
9450 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
9451 const_reg = index_reg;
9452 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
9458 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
9459 && rtx_equal_p (SET_DEST (prev_set), reg)
9460 && reg_state[regno].use_index >= 0
9465 /* Change destination register and - if necessary - the
9466 constant value in PREV, the constant loading instruction. */
9467 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
9468 if (reg_state[regno].offset != const0_rtx)
9469 validate_change (prev,
9470 &SET_SRC (prev_set),
9471 GEN_INT (INTVAL (SET_SRC (prev_set))
9472 + INTVAL (reg_state[regno].offset)),
9474 /* Now for every use of REG that we have recorded, replace REG
9476 for (i = reg_state[regno].use_index;
9477 i < RELOAD_COMBINE_MAX_USES; i++)
9478 validate_change (reg_state[regno].reg_use[i].insn,
9479 reg_state[regno].reg_use[i].usep,
9482 if (apply_change_group ())
9486 /* Delete the reg-reg addition. */
9487 PUT_CODE (insn, NOTE);
9488 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9489 NOTE_SOURCE_FILE (insn) = 0;
9491 if (reg_state[regno].offset != const0_rtx)
9493 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
9495 for (np = ®_NOTES (prev); *np; )
9497 if (REG_NOTE_KIND (*np) == REG_EQUAL
9498 || REG_NOTE_KIND (*np) == REG_EQUIV)
9499 *np = XEXP (*np, 1);
9501 np = &XEXP (*np, 1);
9504 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9505 reg_state[REGNO (const_reg)].store_ruid = reload_combine_ruid;
9510 note_stores (PATTERN (insn), reload_combine_note_store);
9511 if (GET_CODE (insn) == CALL_INSN)
9515 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9517 if (call_used_regs[i])
9519 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9520 reg_state[i].store_ruid = reload_combine_ruid;
9523 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
9524 link = XEXP (link, 1))
9526 rtx use = XEXP (link, 0);
9527 int regno = REGNO (XEXP (use, 0));
9528 if (GET_CODE (use) == CLOBBER)
9530 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
9531 reg_state[regno].store_ruid = reload_combine_ruid;
9534 reg_state[regno].use_index = -1;
9537 if (GET_CODE (insn) == JUMP_INSN)
9539 /* Non-spill registers might be used at the call destination in
9540 some unknown fashion, so we have to mark the unknown use. */
9541 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
9544 reg_state[i].use_index = -1;
9547 reload_combine_note_use (&PATTERN (insn), insn);
9548 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9550 if (REG_NOTE_KIND (note) == REG_INC
9551 && GET_CODE (XEXP (note, 0)) == REG)
9552 reg_state[REGNO (XEXP (note, 0))].use_index = -1;
9557 /* Check if DST is a register or a subreg of a register; if it is,
9558 update reg_state[regno].store_ruid and reg_state[regno].use_index
9559 accordingly. Called via note_stores from reload_combine.
9560 The second argument, SET, is ignored. */
9562 reload_combine_note_store (dst, set)
9563 rtx dst, set ATTRIBUTE_UNUSED;
9567 unsigned size = GET_MODE_SIZE (GET_MODE (dst));
9569 if (GET_CODE (dst) == SUBREG)
9571 regno = SUBREG_WORD (dst);
9572 dst = SUBREG_REG (dst);
9574 if (GET_CODE (dst) != REG)
9576 regno += REGNO (dst);
9577 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
9578 careful with registers / register parts that are not full words. */
9579 if (size < (unsigned) UNITS_PER_WORD)
9580 reg_state[regno].use_index = -1;
9583 for (i = size / UNITS_PER_WORD - 1 + regno; i >= regno; i--)
9585 reg_state[i].store_ruid = reload_combine_ruid;
9586 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
9591 /* XP points to a piece of rtl that has to be checked for any uses of
9593 *XP is the pattern of INSN, or a part of it.
9594 Called from reload_combine, and recursively by itself. */
9596 reload_combine_note_use (xp, insn)
9600 enum rtx_code code = x->code;
9603 rtx offset = const0_rtx; /* For the REG case below. */
9608 if (GET_CODE (SET_DEST (x)) == REG)
9610 reload_combine_note_use (&SET_SRC (x), insn);
9616 if (GET_CODE (SET_DEST (x)) == REG)
9621 /* We are interested in (plus (reg) (const_int)) . */
9622 if (GET_CODE (XEXP (x, 0)) != REG || GET_CODE (XEXP (x, 1)) != CONST_INT)
9624 offset = XEXP (x, 1);
9629 int regno = REGNO (x);
9632 /* Some spurious USEs of pseudo registers might remain.
9633 Just ignore them. */
9634 if (regno >= FIRST_PSEUDO_REGISTER)
9637 /* If this register is already used in some unknown fashion, we
9639 If we decrement the index from zero to -1, we can't store more
9640 uses, so this register becomes used in an unknown fashion. */
9641 use_index = --reg_state[regno].use_index;
9645 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
9647 /* We have found another use for a register that is already
9648 used later. Check if the offsets match; if not, mark the
9649 register as used in an unknown fashion. */
9650 if (! rtx_equal_p (offset, reg_state[regno].offset))
9652 reg_state[regno].use_index = -1;
9658 /* This is the first use of this register we have seen since we
9659 marked it as dead. */
9660 reg_state[regno].offset = offset;
9661 reg_state[regno].use_ruid = reload_combine_ruid;
9663 reg_state[regno].reg_use[use_index].insn = insn;
9664 reg_state[regno].reg_use[use_index].usep = xp;
9672 /* Recursively process the components of X. */
9673 fmt = GET_RTX_FORMAT (code);
9674 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9677 reload_combine_note_use (&XEXP (x, i), insn);
9678 else if (fmt[i] == 'E')
9680 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9681 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9686 /* See if we can reduce the cost of a constant by replacing a move with
9688 /* We cannot do our optimization across labels. Invalidating all the
9689 information about register contents we have would be costly, so we
9690 use last_label_luid (local variable of reload_cse_move2add) to note
9691 where the label is and then later disable any optimization that would
9693 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9694 reg_set_luid[n] is larger than last_label_luid[n] . */
9695 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9696 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
9697 reg_mode[n] to be valid.
9698 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
9699 has been set to reg_offset[n] in mode reg_mode[n] .
9700 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
9701 register n has been set to the sum of reg_offset[n] and register
9702 reg_base_reg[n], calculated in mode reg_mode[n] . */
9703 static rtx reg_offset[FIRST_PSEUDO_REGISTER];
9704 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9705 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9706 /* move2add_luid is linearily increased while scanning the instructions
9707 from first to last. It is used to set reg_set_luid in
9708 reload_cse_move2add and move2add_note_store. */
9709 static int move2add_luid;
9712 reload_cse_move2add (first)
9717 int last_label_luid;
9719 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
9720 reg_set_luid[i] = 0;
9722 last_label_luid = 0;
9724 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9728 if (GET_CODE (insn) == CODE_LABEL)
9729 last_label_luid = move2add_luid;
9730 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
9732 pat = PATTERN (insn);
9733 /* For simplicity, we only perform this optimization on
9734 straightforward SETs. */
9735 if (GET_CODE (pat) == SET
9736 && GET_CODE (SET_DEST (pat)) == REG)
9738 rtx reg = SET_DEST (pat);
9739 int regno = REGNO (reg);
9740 rtx src = SET_SRC (pat);
9742 /* Check if we have valid information on the contents of this
9743 register in the mode of REG. */
9744 /* ??? We don't know how zero / sign extension is handled, hence
9745 we can't go from a narrower to a wider mode. */
9746 if (reg_set_luid[regno] > last_label_luid
9747 && (GET_MODE_SIZE (GET_MODE (reg))
9748 <= GET_MODE_SIZE (reg_mode[regno]))
9749 && GET_CODE (reg_offset[regno]) == CONST_INT)
9751 /* Try to transform (set (REGX) (CONST_INT A))
9753 (set (REGX) (CONST_INT B))
9755 (set (REGX) (CONST_INT A))
9757 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9759 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9762 rtx new_src = GEN_INT (INTVAL (src)
9763 - INTVAL (reg_offset[regno]));
9764 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9765 use (set (reg) (reg)) instead.
9766 We don't delete this insn, nor do we convert it into a
9767 note, to avoid losing register notes or the return
9768 value flag. jump2 already knowns how to get rid of
9770 if (new_src == const0_rtx)
9771 success = validate_change (insn, &SET_SRC (pat), reg, 0);
9772 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9773 && have_add2_insn (GET_MODE (reg)))
9774 success = validate_change (insn, &PATTERN (insn),
9775 gen_add2_insn (reg, new_src), 0);
9776 reg_set_luid[regno] = move2add_luid;
9777 reg_mode[regno] = GET_MODE (reg);
9778 reg_offset[regno] = src;
9782 /* Try to transform (set (REGX) (REGY))
9783 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9786 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9789 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9791 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9792 else if (GET_CODE (src) == REG
9793 && reg_base_reg[regno] == REGNO (src)
9794 && reg_set_luid[regno] > reg_set_luid[REGNO (src)])
9796 rtx next = next_nonnote_insn (insn);
9799 set = single_set (next);
9802 && SET_DEST (set) == reg
9803 && GET_CODE (SET_SRC (set)) == PLUS
9804 && XEXP (SET_SRC (set), 0) == reg
9805 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9807 rtx src3 = XEXP (SET_SRC (set), 1);
9808 rtx new_src = GEN_INT (INTVAL (src3)
9809 - INTVAL (reg_offset[regno]));
9812 if (new_src == const0_rtx)
9813 /* See above why we create (set (reg) (reg)) here. */
9815 = validate_change (next, &SET_SRC (set), reg, 0);
9816 else if ((rtx_cost (new_src, PLUS)
9817 < 2 + rtx_cost (src3, SET))
9818 && have_add2_insn (GET_MODE (reg)))
9820 = validate_change (next, &PATTERN (next),
9821 gen_add2_insn (reg, new_src), 0);
9824 /* INSN might be the first insn in a basic block
9825 if the preceding insn is a conditional jump
9826 or a possible-throwing call. */
9827 PUT_CODE (insn, NOTE);
9828 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9829 NOTE_SOURCE_FILE (insn) = 0;
9832 reg_set_luid[regno] = move2add_luid;
9833 reg_mode[regno] = GET_MODE (reg);
9834 reg_offset[regno] = src3;
9841 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9843 if (REG_NOTE_KIND (note) == REG_INC
9844 && GET_CODE (XEXP (note, 0)) == REG)
9846 /* Indicate that this register has been recently written to,
9847 but the exact contents are not available. */
9848 int regno = REGNO (XEXP (note, 0));
9849 if (regno < FIRST_PSEUDO_REGISTER)
9851 reg_set_luid[regno] = move2add_luid;
9852 reg_offset[regno] = note;
9856 note_stores (PATTERN (insn), move2add_note_store);
9857 /* If this is a CALL_INSN, all call used registers are stored with
9859 if (GET_CODE (insn) == CALL_INSN)
9861 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
9863 if (call_used_regs[i])
9865 reg_set_luid[i] = move2add_luid;
9866 reg_offset[i] = insn; /* Invalidate contents. */
9873 /* SET is a SET or CLOBBER that sets DST.
9874 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9875 Called from reload_cse_move2add via note_stores. */
9877 move2add_note_store (dst, set)
9883 enum machine_mode mode = GET_MODE (dst);
9884 if (GET_CODE (dst) == SUBREG)
9886 regno = SUBREG_WORD (dst);
9887 dst = SUBREG_REG (dst);
9889 if (GET_CODE (dst) != REG)
9892 regno += REGNO (dst);
9894 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET)
9896 rtx src = SET_SRC (set);
9898 reg_mode[regno] = mode;
9899 switch (GET_CODE (src))
9903 rtx src0 = XEXP (src, 0);
9904 if (GET_CODE (src0) == REG)
9906 if (REGNO (src0) != regno
9907 || reg_offset[regno] != const0_rtx)
9909 reg_base_reg[regno] = REGNO (src0);
9910 reg_set_luid[regno] = move2add_luid;
9912 reg_offset[regno] = XEXP (src, 1);
9915 reg_set_luid[regno] = move2add_luid;
9916 reg_offset[regno] = set; /* Invalidate contents. */
9921 reg_base_reg[regno] = REGNO (SET_SRC (set));
9922 reg_offset[regno] = const0_rtx;
9923 reg_set_luid[regno] = move2add_luid;
9927 reg_base_reg[regno] = -1;
9928 reg_offset[regno] = SET_SRC (set);
9929 reg_set_luid[regno] = move2add_luid;
9935 for (i = regno + HARD_REGNO_NREGS (regno, mode) - 1; i >= regno; i--)
9937 /* Indicate that this register has been recently written to,
9938 but the exact contents are not available. */
9939 reg_set_luid[i] = move2add_luid;
9940 reg_offset[i] = dst;