1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
82 #define LOCAL_REGNO(REGNO) 0
85 /* During reload_as_needed, element N contains a REG rtx for the hard reg
86 into which reg N has been reloaded (perhaps for a previous insn). */
87 static rtx *reg_last_reload_reg;
89 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
90 for an output reload that stores into reg N. */
91 static char *reg_has_output_reload;
93 /* Indicates which hard regs are reload-registers for an output reload
94 in the current insn. */
95 static HARD_REG_SET reg_is_output_reload;
97 /* Element N is the constant value to which pseudo reg N is equivalent,
98 or zero if pseudo reg N is not equivalent to a constant.
99 find_reloads looks at this in order to replace pseudo reg N
100 with the constant it stands for. */
101 rtx *reg_equiv_constant;
103 /* Element N is a memory location to which pseudo reg N is equivalent,
104 prior to any register elimination (such as frame pointer to stack
105 pointer). Depending on whether or not it is a valid address, this value
106 is transferred to either reg_equiv_address or reg_equiv_mem. */
107 rtx *reg_equiv_memory_loc;
109 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
110 This is used when the address is not valid as a memory address
111 (because its displacement is too big for the machine.) */
112 rtx *reg_equiv_address;
114 /* Element N is the memory slot to which pseudo reg N is equivalent,
115 or zero if pseudo reg N is not equivalent to a memory slot. */
118 /* Widest width in which each pseudo reg is referred to (via subreg). */
119 static unsigned int *reg_max_ref_width;
121 /* Element N is the list of insns that initialized reg N from its equivalent
122 constant or memory slot. */
123 static rtx *reg_equiv_init;
125 /* Vector to remember old contents of reg_renumber before spilling. */
126 static short *reg_old_renumber;
128 /* During reload_as_needed, element N contains the last pseudo regno reloaded
129 into hard register N. If that pseudo reg occupied more than one register,
130 reg_reloaded_contents points to that pseudo for each spill register in
131 use; all of these must remain set for an inheritance to occur. */
132 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
134 /* During reload_as_needed, element N contains the insn for which
135 hard register N was last used. Its contents are significant only
136 when reg_reloaded_valid is set for this register. */
137 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
139 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
140 static HARD_REG_SET reg_reloaded_valid;
141 /* Indicate if the register was dead at the end of the reload.
142 This is only valid if reg_reloaded_contents is set and valid. */
143 static HARD_REG_SET reg_reloaded_dead;
145 /* Number of spill-regs so far; number of valid elements of spill_regs. */
148 /* In parallel with spill_regs, contains REG rtx's for those regs.
149 Holds the last rtx used for any given reg, or 0 if it has never
150 been used for spilling yet. This rtx is reused, provided it has
152 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
154 /* In parallel with spill_regs, contains nonzero for a spill reg
155 that was stored after the last time it was used.
156 The precise value is the insn generated to do the store. */
157 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
159 /* This is the register that was stored with spill_reg_store. This is a
160 copy of reload_out / reload_out_reg when the value was stored; if
161 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
162 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
164 /* This table is the inverse mapping of spill_regs:
165 indexed by hard reg number,
166 it contains the position of that reg in spill_regs,
167 or -1 for something that is not in spill_regs.
169 ?!? This is no longer accurate. */
170 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
172 /* This reg set indicates registers that can't be used as spill registers for
173 the currently processed insn. These are the hard registers which are live
174 during the insn, but not allocated to pseudos, as well as fixed
176 static HARD_REG_SET bad_spill_regs;
178 /* These are the hard registers that can't be used as spill register for any
179 insn. This includes registers used for user variables and registers that
180 we can't eliminate. A register that appears in this set also can't be used
181 to retry register allocation. */
182 static HARD_REG_SET bad_spill_regs_global;
184 /* Describes order of use of registers for reloading
185 of spilled pseudo-registers. `n_spills' is the number of
186 elements that are actually valid; new ones are added at the end.
188 Both spill_regs and spill_reg_order are used on two occasions:
189 once during find_reload_regs, where they keep track of the spill registers
190 for a single insn, but also during reload_as_needed where they show all
191 the registers ever used by reload. For the latter case, the information
192 is calculated during finish_spills. */
193 static short spill_regs[FIRST_PSEUDO_REGISTER];
195 /* This vector of reg sets indicates, for each pseudo, which hard registers
196 may not be used for retrying global allocation because the register was
197 formerly spilled from one of them. If we allowed reallocating a pseudo to
198 a register that it was already allocated to, reload might not
200 static HARD_REG_SET *pseudo_previous_regs;
202 /* This vector of reg sets indicates, for each pseudo, which hard
203 registers may not be used for retrying global allocation because they
204 are used as spill registers during one of the insns in which the
206 static HARD_REG_SET *pseudo_forbidden_regs;
208 /* All hard regs that have been used as spill registers for any insn are
209 marked in this set. */
210 static HARD_REG_SET used_spill_regs;
212 /* Index of last register assigned as a spill register. We allocate in
213 a round-robin fashion. */
214 static int last_spill_reg;
216 /* Nonzero if indirect addressing is supported on the machine; this means
217 that spilling (REG n) does not require reloading it into a register in
218 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
219 value indicates the level of indirect addressing supported, e.g., two
220 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
222 static char spill_indirect_levels;
224 /* Nonzero if indirect addressing is supported when the innermost MEM is
225 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
226 which these are valid is the same as spill_indirect_levels, above. */
227 char indirect_symref_ok;
229 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
230 char double_reg_address_ok;
232 /* Record the stack slot for each spilled hard register. */
233 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
235 /* Width allocated so far for that stack slot. */
236 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
238 /* Record which pseudos needed to be spilled. */
239 static regset_head spilled_pseudos;
241 /* Used for communication between order_regs_for_reload and count_pseudo.
242 Used to avoid counting one pseudo twice. */
243 static regset_head pseudos_counted;
245 /* First uid used by insns created by reload in this function.
246 Used in find_equiv_reg. */
247 int reload_first_uid;
249 /* Flag set by local-alloc or global-alloc if anything is live in
250 a call-clobbered reg across calls. */
251 int caller_save_needed;
253 /* Set to 1 while reload_as_needed is operating.
254 Required by some machines to handle any generated moves differently. */
255 int reload_in_progress = 0;
257 /* These arrays record the insn_code of insns that may be needed to
258 perform input and output reloads of special objects. They provide a
259 place to pass a scratch register. */
260 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
261 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
263 /* This obstack is used for allocation of rtl during register elimination.
264 The allocated storage can be freed once find_reloads has processed the
266 struct obstack reload_obstack;
268 /* Points to the beginning of the reload_obstack. All insn_chain structures
269 are allocated first. */
270 char *reload_startobj;
272 /* The point after all insn_chain structures. Used to quickly deallocate
273 memory allocated in copy_reloads during calculate_needs_all_insns. */
274 char *reload_firstobj;
276 /* This points before all local rtl generated by register elimination.
277 Used to quickly free all memory after processing one insn. */
278 static char *reload_insn_firstobj;
280 /* List of insn_chain instructions, one for every insn that reload needs to
282 struct insn_chain *reload_insn_chain;
285 extern tree current_function_decl;
287 extern union tree_node *current_function_decl;
290 /* List of all insns needing reloads. */
291 static struct insn_chain *insns_need_reload;
293 /* This structure is used to record information about register eliminations.
294 Each array entry describes one possible way of eliminating a register
295 in favor of another. If there is more than one way of eliminating a
296 particular register, the most preferred should be specified first. */
300 int from; /* Register number to be eliminated. */
301 int to; /* Register number used as replacement. */
302 int initial_offset; /* Initial difference between values. */
303 int can_eliminate; /* Nonzero if this elimination can be done. */
304 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
305 insns made by reload. */
306 int offset; /* Current offset between the two regs. */
307 int previous_offset; /* Offset at end of previous insn. */
308 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
309 rtx from_rtx; /* REG rtx for the register to be eliminated.
310 We cannot simply compare the number since
311 we might then spuriously replace a hard
312 register corresponding to a pseudo
313 assigned to the reg to be eliminated. */
314 rtx to_rtx; /* REG rtx for the replacement. */
317 static struct elim_table *reg_eliminate = 0;
319 /* This is an intermediate structure to initialize the table. It has
320 exactly the members provided by ELIMINABLE_REGS. */
321 static const struct elim_table_1
325 } reg_eliminate_1[] =
327 /* If a set of eliminable registers was specified, define the table from it.
328 Otherwise, default to the normal case of the frame pointer being
329 replaced by the stack pointer. */
331 #ifdef ELIMINABLE_REGS
334 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
337 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
339 /* Record the number of pending eliminations that have an offset not equal
340 to their initial offset. If nonzero, we use a new copy of each
341 replacement result in any insns encountered. */
342 int num_not_at_initial_offset;
344 /* Count the number of registers that we may be able to eliminate. */
345 static int num_eliminable;
346 /* And the number of registers that are equivalent to a constant that
347 can be eliminated to frame_pointer / arg_pointer + constant. */
348 static int num_eliminable_invariants;
350 /* For each label, we record the offset of each elimination. If we reach
351 a label by more than one path and an offset differs, we cannot do the
352 elimination. This information is indexed by the difference of the
353 number of the label and the first label number. We can't offset the
354 pointer itself as this can cause problems on machines with segmented
355 memory. The first table is an array of flags that records whether we
356 have yet encountered a label and the second table is an array of arrays,
357 one entry in the latter array for each elimination. */
359 static int first_label_num;
360 static char *offsets_known_at;
361 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
363 /* Number of labels in the current function. */
365 static int num_labels;
367 static void replace_pseudos_in PARAMS ((rtx *, enum machine_mode, rtx));
368 static void maybe_fix_stack_asms PARAMS ((void));
369 static void copy_reloads PARAMS ((struct insn_chain *));
370 static void calculate_needs_all_insns PARAMS ((int));
371 static int find_reg PARAMS ((struct insn_chain *, int));
372 static void find_reload_regs PARAMS ((struct insn_chain *));
373 static void select_reload_regs PARAMS ((void));
374 static void delete_caller_save_insns PARAMS ((void));
376 static void spill_failure PARAMS ((rtx, enum reg_class));
377 static void count_spilled_pseudo PARAMS ((int, int, int));
378 static void delete_dead_insn PARAMS ((rtx));
379 static void alter_reg PARAMS ((int, int));
380 static void set_label_offsets PARAMS ((rtx, rtx, int));
381 static void check_eliminable_occurrences PARAMS ((rtx));
382 static void elimination_effects PARAMS ((rtx, enum machine_mode));
383 static int eliminate_regs_in_insn PARAMS ((rtx, int));
384 static void update_eliminable_offsets PARAMS ((void));
385 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
386 static void set_initial_elim_offsets PARAMS ((void));
387 static void verify_initial_elim_offsets PARAMS ((void));
388 static void set_initial_label_offsets PARAMS ((void));
389 static void set_offsets_for_label PARAMS ((rtx));
390 static void init_elim_table PARAMS ((void));
391 static void update_eliminables PARAMS ((HARD_REG_SET *));
392 static void spill_hard_reg PARAMS ((unsigned int, int));
393 static int finish_spills PARAMS ((int));
394 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
395 static void scan_paradoxical_subregs PARAMS ((rtx));
396 static void count_pseudo PARAMS ((int));
397 static void order_regs_for_reload PARAMS ((struct insn_chain *));
398 static void reload_as_needed PARAMS ((int));
399 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
400 static int reload_reg_class_lower PARAMS ((const void *, const void *));
401 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
404 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
407 static int reload_reg_free_p PARAMS ((unsigned int, int,
409 static int reload_reg_free_for_value_p PARAMS ((int, int, int,
411 rtx, rtx, int, int));
412 static int free_for_value_p PARAMS ((int, enum machine_mode, int,
413 enum reload_type, rtx, rtx,
415 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
417 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
419 static int conflicts_with_override PARAMS ((rtx));
420 static void failed_reload PARAMS ((rtx, int));
421 static int set_reload_reg PARAMS ((int, int));
422 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
423 static void choose_reload_regs PARAMS ((struct insn_chain *));
424 static void merge_assigned_reloads PARAMS ((rtx));
425 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
426 struct reload *, rtx, int));
427 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
428 struct reload *, int));
429 static void do_input_reload PARAMS ((struct insn_chain *,
430 struct reload *, int));
431 static void do_output_reload PARAMS ((struct insn_chain *,
432 struct reload *, int));
433 static void emit_reload_insns PARAMS ((struct insn_chain *));
434 static void delete_output_reload PARAMS ((rtx, int, int));
435 static void delete_address_reloads PARAMS ((rtx, rtx));
436 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
437 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
439 static void add_auto_inc_notes PARAMS ((rtx, rtx));
441 static void copy_eh_notes PARAMS ((rtx, rtx));
442 extern void dump_needs PARAMS ((struct insn_chain *));
444 /* Initialize the reload pass once per compilation. */
451 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
452 Set spill_indirect_levels to the number of levels such addressing is
453 permitted, zero if it is not permitted at all. */
456 = gen_rtx_MEM (Pmode,
459 LAST_VIRTUAL_REGISTER + 1),
461 spill_indirect_levels = 0;
463 while (memory_address_p (QImode, tem))
465 spill_indirect_levels++;
466 tem = gen_rtx_MEM (Pmode, tem);
469 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
471 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
472 indirect_symref_ok = memory_address_p (QImode, tem);
474 /* See if reg+reg is a valid (and offsettable) address. */
476 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
478 tem = gen_rtx_PLUS (Pmode,
479 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
480 gen_rtx_REG (Pmode, i));
482 /* This way, we make sure that reg+reg is an offsettable address. */
483 tem = plus_constant (tem, 4);
485 if (memory_address_p (QImode, tem))
487 double_reg_address_ok = 1;
492 /* Initialize obstack for our rtl allocation. */
493 gcc_obstack_init (&reload_obstack);
494 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
496 INIT_REG_SET (&spilled_pseudos);
497 INIT_REG_SET (&pseudos_counted);
500 /* List of insn chains that are currently unused. */
501 static struct insn_chain *unused_insn_chains = 0;
503 /* Allocate an empty insn_chain structure. */
507 struct insn_chain *c;
509 if (unused_insn_chains == 0)
511 c = (struct insn_chain *)
512 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
513 INIT_REG_SET (&c->live_throughout);
514 INIT_REG_SET (&c->dead_or_set);
518 c = unused_insn_chains;
519 unused_insn_chains = c->next;
521 c->is_caller_save_insn = 0;
522 c->need_operand_change = 0;
528 /* Small utility function to set all regs in hard reg set TO which are
529 allocated to pseudos in regset FROM. */
532 compute_use_by_pseudos (to, from)
538 EXECUTE_IF_SET_IN_REG_SET
539 (from, FIRST_PSEUDO_REGISTER, regno,
541 int r = reg_renumber[regno];
546 /* reload_combine uses the information from
547 BASIC_BLOCK->global_live_at_start, which might still
548 contain registers that have not actually been allocated
549 since they have an equivalence. */
550 if (! reload_completed)
555 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
557 SET_HARD_REG_BIT (*to, r + nregs);
562 /* Replace all pseudos found in LOC with their corresponding
566 replace_pseudos_in (loc, mem_mode, usage)
568 enum machine_mode mem_mode;
582 unsigned int regno = REGNO (x);
584 if (regno < FIRST_PSEUDO_REGISTER)
587 x = eliminate_regs (x, mem_mode, usage);
591 replace_pseudos_in (loc, mem_mode, usage);
595 if (reg_equiv_constant[regno])
596 *loc = reg_equiv_constant[regno];
597 else if (reg_equiv_mem[regno])
598 *loc = reg_equiv_mem[regno];
599 else if (reg_equiv_address[regno])
600 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
601 else if (GET_CODE (regno_reg_rtx[regno]) != REG
602 || REGNO (regno_reg_rtx[regno]) != regno)
603 *loc = regno_reg_rtx[regno];
609 else if (code == MEM)
611 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
615 /* Process each of our operands recursively. */
616 fmt = GET_RTX_FORMAT (code);
617 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
619 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
620 else if (*fmt == 'E')
621 for (j = 0; j < XVECLEN (x, i); j++)
622 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
626 /* Global variables used by reload and its subroutines. */
628 /* Set during calculate_needs if an insn needs register elimination. */
629 static int something_needs_elimination;
630 /* Set during calculate_needs if an insn needs an operand changed. */
631 int something_needs_operands_changed;
633 /* Nonzero means we couldn't get enough spill regs. */
636 /* Main entry point for the reload pass.
638 FIRST is the first insn of the function being compiled.
640 GLOBAL nonzero means we were called from global_alloc
641 and should attempt to reallocate any pseudoregs that we
642 displace from hard regs we will use for reloads.
643 If GLOBAL is zero, we do not have enough information to do that,
644 so any pseudo reg that is spilled must go to the stack.
646 Return value is nonzero if reload failed
647 and we must not do any more for this function. */
650 reload (first, global)
656 struct elim_table *ep;
659 /* Make sure even insns with volatile mem refs are recognizable. */
664 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
666 /* Make sure that the last insn in the chain
667 is not something that needs reloading. */
668 emit_note (NOTE_INSN_DELETED);
670 /* Enable find_equiv_reg to distinguish insns made by reload. */
671 reload_first_uid = get_max_uid ();
673 #ifdef SECONDARY_MEMORY_NEEDED
674 /* Initialize the secondary memory table. */
675 clear_secondary_mem ();
678 /* We don't have a stack slot for any spill reg yet. */
679 memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot);
680 memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
682 /* Initialize the save area information for caller-save, in case some
686 /* Compute which hard registers are now in use
687 as homes for pseudo registers.
688 This is done here rather than (eg) in global_alloc
689 because this point is reached even if not optimizing. */
690 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
693 /* A function that receives a nonlocal goto must save all call-saved
695 if (current_function_has_nonlocal_label)
696 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
697 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
698 regs_ever_live[i] = 1;
700 /* Find all the pseudo registers that didn't get hard regs
701 but do have known equivalent constants or memory slots.
702 These include parameters (known equivalent to parameter slots)
703 and cse'd or loop-moved constant memory addresses.
705 Record constant equivalents in reg_equiv_constant
706 so they will be substituted by find_reloads.
707 Record memory equivalents in reg_mem_equiv so they can
708 be substituted eventually by altering the REG-rtx's. */
710 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
711 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
712 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
713 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
714 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
715 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
716 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
717 pseudo_forbidden_regs
718 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
720 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
722 CLEAR_HARD_REG_SET (bad_spill_regs_global);
724 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
725 Also find all paradoxical subregs and find largest such for each pseudo.
726 On machines with small register classes, record hard registers that
727 are used for user variables. These can never be used for spills.
728 Also look for a "constant" REG_SETJMP. This means that all
729 caller-saved registers must be marked live. */
731 num_eliminable_invariants = 0;
732 for (insn = first; insn; insn = NEXT_INSN (insn))
734 rtx set = single_set (insn);
736 /* We may introduce USEs that we want to remove at the end, so
737 we'll mark them with QImode. Make sure there are no
738 previously-marked insns left by say regmove. */
739 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
740 && GET_MODE (insn) != VOIDmode)
741 PUT_MODE (insn, VOIDmode);
743 if (GET_CODE (insn) == CALL_INSN
744 && find_reg_note (insn, REG_SETJMP, NULL))
745 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
746 if (! call_used_regs[i])
747 regs_ever_live[i] = 1;
749 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
751 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
753 #ifdef LEGITIMATE_PIC_OPERAND_P
754 && (! function_invariant_p (XEXP (note, 0))
756 /* A function invariant is often CONSTANT_P but may
757 include a register. We promise to only pass
758 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
759 || (CONSTANT_P (XEXP (note, 0))
760 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))))
764 rtx x = XEXP (note, 0);
765 i = REGNO (SET_DEST (set));
766 if (i > LAST_VIRTUAL_REGISTER)
768 /* It can happen that a REG_EQUIV note contains a MEM
769 that is not a legitimate memory operand. As later
770 stages of reload assume that all addresses found
771 in the reg_equiv_* arrays were originally legitimate,
772 we ignore such REG_EQUIV notes. */
773 if (memory_operand (x, VOIDmode))
775 /* Always unshare the equivalence, so we can
776 substitute into this insn without touching the
778 reg_equiv_memory_loc[i] = copy_rtx (x);
780 else if (function_invariant_p (x))
782 if (GET_CODE (x) == PLUS)
784 /* This is PLUS of frame pointer and a constant,
785 and might be shared. Unshare it. */
786 reg_equiv_constant[i] = copy_rtx (x);
787 num_eliminable_invariants++;
789 else if (x == frame_pointer_rtx
790 || x == arg_pointer_rtx)
792 reg_equiv_constant[i] = x;
793 num_eliminable_invariants++;
795 else if (LEGITIMATE_CONSTANT_P (x))
796 reg_equiv_constant[i] = x;
799 reg_equiv_memory_loc[i]
800 = force_const_mem (GET_MODE (SET_DEST (set)), x);
801 if (!reg_equiv_memory_loc[i])
808 /* If this register is being made equivalent to a MEM
809 and the MEM is not SET_SRC, the equivalencing insn
810 is one with the MEM as a SET_DEST and it occurs later.
811 So don't mark this insn now. */
812 if (GET_CODE (x) != MEM
813 || rtx_equal_p (SET_SRC (set), x))
815 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
820 /* If this insn is setting a MEM from a register equivalent to it,
821 this is the equivalencing insn. */
822 else if (set && GET_CODE (SET_DEST (set)) == MEM
823 && GET_CODE (SET_SRC (set)) == REG
824 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
825 && rtx_equal_p (SET_DEST (set),
826 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
827 reg_equiv_init[REGNO (SET_SRC (set))]
828 = gen_rtx_INSN_LIST (VOIDmode, insn,
829 reg_equiv_init[REGNO (SET_SRC (set))]);
832 scan_paradoxical_subregs (PATTERN (insn));
837 first_label_num = get_first_label_num ();
838 num_labels = max_label_num () - first_label_num;
840 /* Allocate the tables used to store offset information at labels. */
841 /* We used to use alloca here, but the size of what it would try to
842 allocate would occasionally cause it to exceed the stack limit and
843 cause a core dump. */
844 offsets_known_at = xmalloc (num_labels);
846 = (int (*)[NUM_ELIMINABLE_REGS])
847 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
849 /* Alter each pseudo-reg rtx to contain its hard reg number.
850 Assign stack slots to the pseudos that lack hard regs or equivalents.
851 Do not touch virtual registers. */
853 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
856 /* If we have some registers we think can be eliminated, scan all insns to
857 see if there is an insn that sets one of these registers to something
858 other than itself plus a constant. If so, the register cannot be
859 eliminated. Doing this scan here eliminates an extra pass through the
860 main reload loop in the most common case where register elimination
862 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
863 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
864 || GET_CODE (insn) == CALL_INSN)
865 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
867 maybe_fix_stack_asms ();
869 insns_need_reload = 0;
870 something_needs_elimination = 0;
872 /* Initialize to -1, which means take the first spill register. */
875 /* Spill any hard regs that we know we can't eliminate. */
876 CLEAR_HARD_REG_SET (used_spill_regs);
877 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
878 if (! ep->can_eliminate)
879 spill_hard_reg (ep->from, 1);
881 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
882 if (frame_pointer_needed)
883 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
885 finish_spills (global);
887 /* From now on, we may need to generate moves differently. We may also
888 allow modifications of insns which cause them to not be recognized.
889 Any such modifications will be cleaned up during reload itself. */
890 reload_in_progress = 1;
892 /* This loop scans the entire function each go-round
893 and repeats until one repetition spills no additional hard regs. */
896 int something_changed;
899 HOST_WIDE_INT starting_frame_size;
901 /* Round size of stack frame to stack_alignment_needed. This must be done
902 here because the stack size may be a part of the offset computation
903 for register elimination, and there might have been new stack slots
904 created in the last iteration of this loop. */
905 if (cfun->stack_alignment_needed)
906 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
908 starting_frame_size = get_frame_size ();
910 set_initial_elim_offsets ();
911 set_initial_label_offsets ();
913 /* For each pseudo register that has an equivalent location defined,
914 try to eliminate any eliminable registers (such as the frame pointer)
915 assuming initial offsets for the replacement register, which
918 If the resulting location is directly addressable, substitute
919 the MEM we just got directly for the old REG.
921 If it is not addressable but is a constant or the sum of a hard reg
922 and constant, it is probably not addressable because the constant is
923 out of range, in that case record the address; we will generate
924 hairy code to compute the address in a register each time it is
925 needed. Similarly if it is a hard register, but one that is not
926 valid as an address register.
928 If the location is not addressable, but does not have one of the
929 above forms, assign a stack slot. We have to do this to avoid the
930 potential of producing lots of reloads if, e.g., a location involves
931 a pseudo that didn't get a hard register and has an equivalent memory
932 location that also involves a pseudo that didn't get a hard register.
934 Perhaps at some point we will improve reload_when_needed handling
935 so this problem goes away. But that's very hairy. */
937 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
938 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
940 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
942 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
944 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
945 else if (CONSTANT_P (XEXP (x, 0))
946 || (GET_CODE (XEXP (x, 0)) == REG
947 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
948 || (GET_CODE (XEXP (x, 0)) == PLUS
949 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
950 && (REGNO (XEXP (XEXP (x, 0), 0))
951 < FIRST_PSEUDO_REGISTER)
952 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
953 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
956 /* Make a new stack slot. Then indicate that something
957 changed so we go back and recompute offsets for
958 eliminable registers because the allocation of memory
959 below might change some offset. reg_equiv_{mem,address}
960 will be set up for this pseudo on the next pass around
962 reg_equiv_memory_loc[i] = 0;
963 reg_equiv_init[i] = 0;
968 if (caller_save_needed)
971 /* If we allocated another stack slot, redo elimination bookkeeping. */
972 if (starting_frame_size != get_frame_size ())
975 if (caller_save_needed)
977 save_call_clobbered_regs ();
978 /* That might have allocated new insn_chain structures. */
979 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
982 calculate_needs_all_insns (global);
984 CLEAR_REG_SET (&spilled_pseudos);
987 something_changed = 0;
989 /* If we allocated any new memory locations, make another pass
990 since it might have changed elimination offsets. */
991 if (starting_frame_size != get_frame_size ())
992 something_changed = 1;
995 HARD_REG_SET to_spill;
996 CLEAR_HARD_REG_SET (to_spill);
997 update_eliminables (&to_spill);
998 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
999 if (TEST_HARD_REG_BIT (to_spill, i))
1001 spill_hard_reg (i, 1);
1004 /* Regardless of the state of spills, if we previously had
1005 a register that we thought we could eliminate, but now can
1006 not eliminate, we must run another pass.
1008 Consider pseudos which have an entry in reg_equiv_* which
1009 reference an eliminable register. We must make another pass
1010 to update reg_equiv_* so that we do not substitute in the
1011 old value from when we thought the elimination could be
1013 something_changed = 1;
1017 select_reload_regs ();
1021 if (insns_need_reload != 0 || did_spill)
1022 something_changed |= finish_spills (global);
1024 if (! something_changed)
1027 if (caller_save_needed)
1028 delete_caller_save_insns ();
1030 obstack_free (&reload_obstack, reload_firstobj);
1033 /* If global-alloc was run, notify it of any register eliminations we have
1036 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1037 if (ep->can_eliminate)
1038 mark_elimination (ep->from, ep->to);
1040 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1041 If that insn didn't set the register (i.e., it copied the register to
1042 memory), just delete that insn instead of the equivalencing insn plus
1043 anything now dead. If we call delete_dead_insn on that insn, we may
1044 delete the insn that actually sets the register if the register dies
1045 there and that is incorrect. */
1047 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1049 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1052 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1054 rtx equiv_insn = XEXP (list, 0);
1056 /* If we already deleted the insn or if it may trap, we can't
1057 delete it. The latter case shouldn't happen, but can
1058 if an insn has a variable address, gets a REG_EH_REGION
1059 note added to it, and then gets converted into an load
1060 from a constant address. */
1061 if (GET_CODE (equiv_insn) == NOTE
1062 || can_throw_internal (equiv_insn))
1064 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1065 delete_dead_insn (equiv_insn);
1068 PUT_CODE (equiv_insn, NOTE);
1069 NOTE_SOURCE_FILE (equiv_insn) = 0;
1070 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1076 /* Use the reload registers where necessary
1077 by generating move instructions to move the must-be-register
1078 values into or out of the reload registers. */
1080 if (insns_need_reload != 0 || something_needs_elimination
1081 || something_needs_operands_changed)
1083 HOST_WIDE_INT old_frame_size = get_frame_size ();
1085 reload_as_needed (global);
1087 if (old_frame_size != get_frame_size ())
1091 verify_initial_elim_offsets ();
1094 /* If we were able to eliminate the frame pointer, show that it is no
1095 longer live at the start of any basic block. If it ls live by
1096 virtue of being in a pseudo, that pseudo will be marked live
1097 and hence the frame pointer will be known to be live via that
1100 if (! frame_pointer_needed)
1102 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1103 HARD_FRAME_POINTER_REGNUM);
1105 /* Come here (with failure set nonzero) if we can't get enough spill regs
1106 and we decide not to abort about it. */
1109 CLEAR_REG_SET (&spilled_pseudos);
1110 reload_in_progress = 0;
1112 /* Now eliminate all pseudo regs by modifying them into
1113 their equivalent memory references.
1114 The REG-rtx's for the pseudos are modified in place,
1115 so all insns that used to refer to them now refer to memory.
1117 For a reg that has a reg_equiv_address, all those insns
1118 were changed by reloading so that no insns refer to it any longer;
1119 but the DECL_RTL of a variable decl may refer to it,
1120 and if so this causes the debugging info to mention the variable. */
1122 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1126 if (reg_equiv_mem[i])
1127 addr = XEXP (reg_equiv_mem[i], 0);
1129 if (reg_equiv_address[i])
1130 addr = reg_equiv_address[i];
1134 if (reg_renumber[i] < 0)
1136 rtx reg = regno_reg_rtx[i];
1138 REG_USERVAR_P (reg) = 0;
1139 PUT_CODE (reg, MEM);
1140 XEXP (reg, 0) = addr;
1141 if (reg_equiv_memory_loc[i])
1142 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1145 RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg)
1146 = MEM_SCALAR_P (reg) = 0;
1147 MEM_ATTRS (reg) = 0;
1150 else if (reg_equiv_mem[i])
1151 XEXP (reg_equiv_mem[i], 0) = addr;
1155 /* We must set reload_completed now since the cleanup_subreg_operands call
1156 below will re-recognize each insn and reload may have generated insns
1157 which are only valid during and after reload. */
1158 reload_completed = 1;
1160 /* Make a pass over all the insns and delete all USEs which we inserted
1161 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1162 notes. Delete all CLOBBER insns, except those that refer to the return
1163 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1164 from misarranging variable-array code, and simplify (subreg (reg))
1165 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1166 are no longer useful or accurate. Strip and regenerate REG_INC notes
1167 that may have been moved around. */
1169 for (insn = first; insn; insn = NEXT_INSN (insn))
1174 if (GET_CODE (insn) == CALL_INSN)
1175 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1176 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1178 if ((GET_CODE (PATTERN (insn)) == USE
1179 /* We mark with QImode USEs introduced by reload itself. */
1180 && (GET_MODE (insn) == QImode
1181 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1182 || (GET_CODE (PATTERN (insn)) == CLOBBER
1183 && (GET_CODE (XEXP (PATTERN (insn), 0)) != MEM
1184 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1185 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1186 && XEXP (XEXP (PATTERN (insn), 0), 0)
1187 != stack_pointer_rtx))
1188 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1189 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1195 /* Some CLOBBERs may survive until here and still reference unassigned
1196 pseudos with const equivalent, which may in turn cause ICE in later
1197 passes if the reference remains in place. */
1198 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1199 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1200 VOIDmode, PATTERN (insn));
1202 pnote = ®_NOTES (insn);
1205 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1206 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1207 || REG_NOTE_KIND (*pnote) == REG_INC
1208 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1209 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1210 *pnote = XEXP (*pnote, 1);
1212 pnote = &XEXP (*pnote, 1);
1216 add_auto_inc_notes (insn, PATTERN (insn));
1219 /* And simplify (subreg (reg)) if it appears as an operand. */
1220 cleanup_subreg_operands (insn);
1223 /* If we are doing stack checking, give a warning if this function's
1224 frame size is larger than we expect. */
1225 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1227 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1228 static int verbose_warned = 0;
1230 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1231 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1232 size += UNITS_PER_WORD;
1234 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1236 warning ("frame size too large for reliable stack checking");
1237 if (! verbose_warned)
1239 warning ("try reducing the number of local variables");
1245 /* Indicate that we no longer have known memory locations or constants. */
1246 if (reg_equiv_constant)
1247 free (reg_equiv_constant);
1248 reg_equiv_constant = 0;
1249 if (reg_equiv_memory_loc)
1250 free (reg_equiv_memory_loc);
1251 reg_equiv_memory_loc = 0;
1253 if (offsets_known_at)
1254 free (offsets_known_at);
1258 free (reg_equiv_mem);
1259 free (reg_equiv_init);
1260 free (reg_equiv_address);
1261 free (reg_max_ref_width);
1262 free (reg_old_renumber);
1263 free (pseudo_previous_regs);
1264 free (pseudo_forbidden_regs);
1266 CLEAR_HARD_REG_SET (used_spill_regs);
1267 for (i = 0; i < n_spills; i++)
1268 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1270 /* Free all the insn_chain structures at once. */
1271 obstack_free (&reload_obstack, reload_startobj);
1272 unused_insn_chains = 0;
1273 fixup_abnormal_edges ();
1275 /* Replacing pseudos with their memory equivalents might have
1276 created shared rtx. Subsequent passes would get confused
1277 by this, so unshare everything here. */
1278 unshare_all_rtl_again (first);
1283 /* Yet another special case. Unfortunately, reg-stack forces people to
1284 write incorrect clobbers in asm statements. These clobbers must not
1285 cause the register to appear in bad_spill_regs, otherwise we'll call
1286 fatal_insn later. We clear the corresponding regnos in the live
1287 register sets to avoid this.
1288 The whole thing is rather sick, I'm afraid. */
1291 maybe_fix_stack_asms ()
1294 const char *constraints[MAX_RECOG_OPERANDS];
1295 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1296 struct insn_chain *chain;
1298 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1301 HARD_REG_SET clobbered, allowed;
1304 if (! INSN_P (chain->insn)
1305 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1307 pat = PATTERN (chain->insn);
1308 if (GET_CODE (pat) != PARALLEL)
1311 CLEAR_HARD_REG_SET (clobbered);
1312 CLEAR_HARD_REG_SET (allowed);
1314 /* First, make a mask of all stack regs that are clobbered. */
1315 for (i = 0; i < XVECLEN (pat, 0); i++)
1317 rtx t = XVECEXP (pat, 0, i);
1318 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1319 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1322 /* Get the operand values and constraints out of the insn. */
1323 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1324 constraints, operand_mode);
1326 /* For every operand, see what registers are allowed. */
1327 for (i = 0; i < noperands; i++)
1329 const char *p = constraints[i];
1330 /* For every alternative, we compute the class of registers allowed
1331 for reloading in CLS, and merge its contents into the reg set
1333 int cls = (int) NO_REGS;
1339 if (c == '\0' || c == ',' || c == '#')
1341 /* End of one alternative - mark the regs in the current
1342 class, and reset the class. */
1343 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1349 } while (c != '\0' && c != ',');
1357 case '=': case '+': case '*': case '%': case '?': case '!':
1358 case '0': case '1': case '2': case '3': case '4': case 'm':
1359 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1360 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1361 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1366 cls = (int) reg_class_subunion[cls]
1367 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1372 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1376 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1377 cls = (int) reg_class_subunion[cls]
1378 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1380 cls = (int) reg_class_subunion[cls]
1381 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1383 p += CONSTRAINT_LEN (c, p);
1386 /* Those of the registers which are clobbered, but allowed by the
1387 constraints, must be usable as reload registers. So clear them
1388 out of the life information. */
1389 AND_HARD_REG_SET (allowed, clobbered);
1390 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1391 if (TEST_HARD_REG_BIT (allowed, i))
1393 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1394 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1401 /* Copy the global variables n_reloads and rld into the corresponding elts
1404 copy_reloads (chain)
1405 struct insn_chain *chain;
1407 chain->n_reloads = n_reloads;
1409 = (struct reload *) obstack_alloc (&reload_obstack,
1410 n_reloads * sizeof (struct reload));
1411 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1412 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1415 /* Walk the chain of insns, and determine for each whether it needs reloads
1416 and/or eliminations. Build the corresponding insns_need_reload list, and
1417 set something_needs_elimination as appropriate. */
1419 calculate_needs_all_insns (global)
1422 struct insn_chain **pprev_reload = &insns_need_reload;
1423 struct insn_chain *chain, *next = 0;
1425 something_needs_elimination = 0;
1427 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1428 for (chain = reload_insn_chain; chain != 0; chain = next)
1430 rtx insn = chain->insn;
1434 /* Clear out the shortcuts. */
1435 chain->n_reloads = 0;
1436 chain->need_elim = 0;
1437 chain->need_reload = 0;
1438 chain->need_operand_change = 0;
1440 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1441 include REG_LABEL), we need to see what effects this has on the
1442 known offsets at labels. */
1444 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1445 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1446 set_label_offsets (insn, insn, 0);
1450 rtx old_body = PATTERN (insn);
1451 int old_code = INSN_CODE (insn);
1452 rtx old_notes = REG_NOTES (insn);
1453 int did_elimination = 0;
1454 int operands_changed = 0;
1455 rtx set = single_set (insn);
1457 /* Skip insns that only set an equivalence. */
1458 if (set && GET_CODE (SET_DEST (set)) == REG
1459 && reg_renumber[REGNO (SET_DEST (set))] < 0
1460 && reg_equiv_constant[REGNO (SET_DEST (set))])
1463 /* If needed, eliminate any eliminable registers. */
1464 if (num_eliminable || num_eliminable_invariants)
1465 did_elimination = eliminate_regs_in_insn (insn, 0);
1467 /* Analyze the instruction. */
1468 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1469 global, spill_reg_order);
1471 /* If a no-op set needs more than one reload, this is likely
1472 to be something that needs input address reloads. We
1473 can't get rid of this cleanly later, and it is of no use
1474 anyway, so discard it now.
1475 We only do this when expensive_optimizations is enabled,
1476 since this complements reload inheritance / output
1477 reload deletion, and it can make debugging harder. */
1478 if (flag_expensive_optimizations && n_reloads > 1)
1480 rtx set = single_set (insn);
1482 && SET_SRC (set) == SET_DEST (set)
1483 && GET_CODE (SET_SRC (set)) == REG
1484 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1487 /* Delete it from the reload chain. */
1489 chain->prev->next = next;
1491 reload_insn_chain = next;
1493 next->prev = chain->prev;
1494 chain->next = unused_insn_chains;
1495 unused_insn_chains = chain;
1500 update_eliminable_offsets ();
1502 /* Remember for later shortcuts which insns had any reloads or
1503 register eliminations. */
1504 chain->need_elim = did_elimination;
1505 chain->need_reload = n_reloads > 0;
1506 chain->need_operand_change = operands_changed;
1508 /* Discard any register replacements done. */
1509 if (did_elimination)
1511 obstack_free (&reload_obstack, reload_insn_firstobj);
1512 PATTERN (insn) = old_body;
1513 INSN_CODE (insn) = old_code;
1514 REG_NOTES (insn) = old_notes;
1515 something_needs_elimination = 1;
1518 something_needs_operands_changed |= operands_changed;
1522 copy_reloads (chain);
1523 *pprev_reload = chain;
1524 pprev_reload = &chain->next_need_reload;
1531 /* Comparison function for qsort to decide which of two reloads
1532 should be handled first. *P1 and *P2 are the reload numbers. */
1535 reload_reg_class_lower (r1p, r2p)
1539 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1542 /* Consider required reloads before optional ones. */
1543 t = rld[r1].optional - rld[r2].optional;
1547 /* Count all solitary classes before non-solitary ones. */
1548 t = ((reg_class_size[(int) rld[r2].class] == 1)
1549 - (reg_class_size[(int) rld[r1].class] == 1));
1553 /* Aside from solitaires, consider all multi-reg groups first. */
1554 t = rld[r2].nregs - rld[r1].nregs;
1558 /* Consider reloads in order of increasing reg-class number. */
1559 t = (int) rld[r1].class - (int) rld[r2].class;
1563 /* If reloads are equally urgent, sort by reload number,
1564 so that the results of qsort leave nothing to chance. */
1568 /* The cost of spilling each hard reg. */
1569 static int spill_cost[FIRST_PSEUDO_REGISTER];
1571 /* When spilling multiple hard registers, we use SPILL_COST for the first
1572 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1573 only the first hard reg for a multi-reg pseudo. */
1574 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1576 /* Update the spill cost arrays, considering that pseudo REG is live. */
1582 int freq = REG_FREQ (reg);
1583 int r = reg_renumber[reg];
1586 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1587 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1590 SET_REGNO_REG_SET (&pseudos_counted, reg);
1595 spill_add_cost[r] += freq;
1597 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1599 spill_cost[r + nregs] += freq;
1602 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1603 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1606 order_regs_for_reload (chain)
1607 struct insn_chain *chain;
1610 HARD_REG_SET used_by_pseudos;
1611 HARD_REG_SET used_by_pseudos2;
1613 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1615 memset (spill_cost, 0, sizeof spill_cost);
1616 memset (spill_add_cost, 0, sizeof spill_add_cost);
1618 /* Count number of uses of each hard reg by pseudo regs allocated to it
1619 and then order them by decreasing use. First exclude hard registers
1620 that are live in or across this insn. */
1622 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1623 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1624 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1625 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1627 /* Now find out which pseudos are allocated to it, and update
1629 CLEAR_REG_SET (&pseudos_counted);
1631 EXECUTE_IF_SET_IN_REG_SET
1632 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1636 EXECUTE_IF_SET_IN_REG_SET
1637 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1641 CLEAR_REG_SET (&pseudos_counted);
1644 /* Vector of reload-numbers showing the order in which the reloads should
1646 static short reload_order[MAX_RELOADS];
1648 /* This is used to keep track of the spill regs used in one insn. */
1649 static HARD_REG_SET used_spill_regs_local;
1651 /* We decided to spill hard register SPILLED, which has a size of
1652 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1653 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1654 update SPILL_COST/SPILL_ADD_COST. */
1657 count_spilled_pseudo (spilled, spilled_nregs, reg)
1658 int spilled, spilled_nregs, reg;
1660 int r = reg_renumber[reg];
1661 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1663 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1664 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1667 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1669 spill_add_cost[r] -= REG_FREQ (reg);
1671 spill_cost[r + nregs] -= REG_FREQ (reg);
1674 /* Find reload register to use for reload number ORDER. */
1677 find_reg (chain, order)
1678 struct insn_chain *chain;
1681 int rnum = reload_order[order];
1682 struct reload *rl = rld + rnum;
1683 int best_cost = INT_MAX;
1687 HARD_REG_SET not_usable;
1688 HARD_REG_SET used_by_other_reload;
1690 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1691 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1692 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1694 CLEAR_HARD_REG_SET (used_by_other_reload);
1695 for (k = 0; k < order; k++)
1697 int other = reload_order[k];
1699 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1700 for (j = 0; j < rld[other].nregs; j++)
1701 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1704 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1706 unsigned int regno = i;
1708 if (! TEST_HARD_REG_BIT (not_usable, regno)
1709 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1710 && HARD_REGNO_MODE_OK (regno, rl->mode))
1712 int this_cost = spill_cost[regno];
1714 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1716 for (j = 1; j < this_nregs; j++)
1718 this_cost += spill_add_cost[regno + j];
1719 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1720 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1725 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1727 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1729 if (this_cost < best_cost
1730 /* Among registers with equal cost, prefer caller-saved ones, or
1731 use REG_ALLOC_ORDER if it is defined. */
1732 || (this_cost == best_cost
1733 #ifdef REG_ALLOC_ORDER
1734 && (inv_reg_alloc_order[regno]
1735 < inv_reg_alloc_order[best_reg])
1737 && call_used_regs[regno]
1738 && ! call_used_regs[best_reg]
1743 best_cost = this_cost;
1751 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1753 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1754 rl->regno = best_reg;
1756 EXECUTE_IF_SET_IN_REG_SET
1757 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1759 count_spilled_pseudo (best_reg, rl->nregs, j);
1762 EXECUTE_IF_SET_IN_REG_SET
1763 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1765 count_spilled_pseudo (best_reg, rl->nregs, j);
1768 for (i = 0; i < rl->nregs; i++)
1770 if (spill_cost[best_reg + i] != 0
1771 || spill_add_cost[best_reg + i] != 0)
1773 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1778 /* Find more reload regs to satisfy the remaining need of an insn, which
1780 Do it by ascending class number, since otherwise a reg
1781 might be spilled for a big class and might fail to count
1782 for a smaller class even though it belongs to that class. */
1785 find_reload_regs (chain)
1786 struct insn_chain *chain;
1790 /* In order to be certain of getting the registers we need,
1791 we must sort the reloads into order of increasing register class.
1792 Then our grabbing of reload registers will parallel the process
1793 that provided the reload registers. */
1794 for (i = 0; i < chain->n_reloads; i++)
1796 /* Show whether this reload already has a hard reg. */
1797 if (chain->rld[i].reg_rtx)
1799 int regno = REGNO (chain->rld[i].reg_rtx);
1800 chain->rld[i].regno = regno;
1802 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1805 chain->rld[i].regno = -1;
1806 reload_order[i] = i;
1809 n_reloads = chain->n_reloads;
1810 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1812 CLEAR_HARD_REG_SET (used_spill_regs_local);
1815 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1817 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1819 /* Compute the order of preference for hard registers to spill. */
1821 order_regs_for_reload (chain);
1823 for (i = 0; i < n_reloads; i++)
1825 int r = reload_order[i];
1827 /* Ignore reloads that got marked inoperative. */
1828 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1829 && ! rld[r].optional
1830 && rld[r].regno == -1)
1831 if (! find_reg (chain, i))
1833 spill_failure (chain->insn, rld[r].class);
1839 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1840 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1842 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1846 select_reload_regs ()
1848 struct insn_chain *chain;
1850 /* Try to satisfy the needs for each insn. */
1851 for (chain = insns_need_reload; chain != 0;
1852 chain = chain->next_need_reload)
1853 find_reload_regs (chain);
1856 /* Delete all insns that were inserted by emit_caller_save_insns during
1859 delete_caller_save_insns ()
1861 struct insn_chain *c = reload_insn_chain;
1865 while (c != 0 && c->is_caller_save_insn)
1867 struct insn_chain *next = c->next;
1870 if (c == reload_insn_chain)
1871 reload_insn_chain = next;
1875 next->prev = c->prev;
1877 c->prev->next = next;
1878 c->next = unused_insn_chains;
1879 unused_insn_chains = c;
1887 /* Handle the failure to find a register to spill.
1888 INSN should be one of the insns which needed this particular spill reg. */
1891 spill_failure (insn, class)
1893 enum reg_class class;
1895 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1896 if (asm_noperands (PATTERN (insn)) >= 0)
1897 error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'",
1898 reg_class_names[class]);
1901 error ("unable to find a register to spill in class `%s'",
1902 reg_class_names[class]);
1903 fatal_insn ("this is the insn:", insn);
1907 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1908 data that is dead in INSN. */
1911 delete_dead_insn (insn)
1914 rtx prev = prev_real_insn (insn);
1917 /* If the previous insn sets a register that dies in our insn, delete it
1919 if (prev && GET_CODE (PATTERN (prev)) == SET
1920 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1921 && reg_mentioned_p (prev_dest, PATTERN (insn))
1922 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1923 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1924 delete_dead_insn (prev);
1926 PUT_CODE (insn, NOTE);
1927 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1928 NOTE_SOURCE_FILE (insn) = 0;
1931 /* Modify the home of pseudo-reg I.
1932 The new home is present in reg_renumber[I].
1934 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1935 or it may be -1, meaning there is none or it is not relevant.
1936 This is used so that all pseudos spilled from a given hard reg
1937 can share one stack slot. */
1940 alter_reg (i, from_reg)
1944 /* When outputting an inline function, this can happen
1945 for a reg that isn't actually used. */
1946 if (regno_reg_rtx[i] == 0)
1949 /* If the reg got changed to a MEM at rtl-generation time,
1951 if (GET_CODE (regno_reg_rtx[i]) != REG)
1954 /* Modify the reg-rtx to contain the new hard reg
1955 number or else to contain its pseudo reg number. */
1956 REGNO (regno_reg_rtx[i])
1957 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1959 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1960 allocate a stack slot for it. */
1962 if (reg_renumber[i] < 0
1963 && REG_N_REFS (i) > 0
1964 && reg_equiv_constant[i] == 0
1965 && reg_equiv_memory_loc[i] == 0)
1968 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1969 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1972 /* Each pseudo reg has an inherent size which comes from its own mode,
1973 and a total size which provides room for paradoxical subregs
1974 which refer to the pseudo reg in wider modes.
1976 We can use a slot already allocated if it provides both
1977 enough inherent space and enough total space.
1978 Otherwise, we allocate a new slot, making sure that it has no less
1979 inherent space, and no less total space, then the previous slot. */
1982 /* No known place to spill from => no slot to reuse. */
1983 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1984 inherent_size == total_size ? 0 : -1);
1985 if (BYTES_BIG_ENDIAN)
1986 /* Cancel the big-endian correction done in assign_stack_local.
1987 Get the address of the beginning of the slot.
1988 This is so we can do a big-endian correction unconditionally
1990 adjust = inherent_size - total_size;
1992 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1994 /* Nothing can alias this slot except this pseudo. */
1995 set_mem_alias_set (x, new_alias_set ());
1998 /* Reuse a stack slot if possible. */
1999 else if (spill_stack_slot[from_reg] != 0
2000 && spill_stack_slot_width[from_reg] >= total_size
2001 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2003 x = spill_stack_slot[from_reg];
2005 /* Allocate a bigger slot. */
2008 /* Compute maximum size needed, both for inherent size
2009 and for total size. */
2010 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2013 if (spill_stack_slot[from_reg])
2015 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2017 mode = GET_MODE (spill_stack_slot[from_reg]);
2018 if (spill_stack_slot_width[from_reg] > total_size)
2019 total_size = spill_stack_slot_width[from_reg];
2022 /* Make a slot with that size. */
2023 x = assign_stack_local (mode, total_size,
2024 inherent_size == total_size ? 0 : -1);
2027 /* All pseudos mapped to this slot can alias each other. */
2028 if (spill_stack_slot[from_reg])
2029 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2031 set_mem_alias_set (x, new_alias_set ());
2033 if (BYTES_BIG_ENDIAN)
2035 /* Cancel the big-endian correction done in assign_stack_local.
2036 Get the address of the beginning of the slot.
2037 This is so we can do a big-endian correction unconditionally
2039 adjust = GET_MODE_SIZE (mode) - total_size;
2042 = adjust_address_nv (x, mode_for_size (total_size
2048 spill_stack_slot[from_reg] = stack_slot;
2049 spill_stack_slot_width[from_reg] = total_size;
2052 /* On a big endian machine, the "address" of the slot
2053 is the address of the low part that fits its inherent mode. */
2054 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2055 adjust += (total_size - inherent_size);
2057 /* If we have any adjustment to make, or if the stack slot is the
2058 wrong mode, make a new stack slot. */
2059 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2061 /* If we have a decl for the original register, set it for the
2062 memory. If this is a shared MEM, make a copy. */
2063 if (REG_EXPR (regno_reg_rtx[i])
2064 && TREE_CODE_CLASS (TREE_CODE (REG_EXPR (regno_reg_rtx[i]))) == 'd')
2066 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2068 /* We can do this only for the DECLs home pseudo, not for
2069 any copies of it, since otherwise when the stack slot
2070 is reused, nonoverlapping_memrefs_p might think they
2072 if (decl && GET_CODE (decl) == REG && REGNO (decl) == (unsigned) i)
2074 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2077 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2081 /* Save the stack slot for later. */
2082 reg_equiv_memory_loc[i] = x;
2086 /* Mark the slots in regs_ever_live for the hard regs
2087 used by pseudo-reg number REGNO. */
2090 mark_home_live (regno)
2095 i = reg_renumber[regno];
2098 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2100 regs_ever_live[i++] = 1;
2103 /* This function handles the tracking of elimination offsets around branches.
2105 X is a piece of RTL being scanned.
2107 INSN is the insn that it came from, if any.
2109 INITIAL_P is nonzero if we are to set the offset to be the initial
2110 offset and zero if we are setting the offset of the label to be the
2114 set_label_offsets (x, insn, initial_p)
2119 enum rtx_code code = GET_CODE (x);
2122 struct elim_table *p;
2127 if (LABEL_REF_NONLOCAL_P (x))
2132 /* ... fall through ... */
2135 /* If we know nothing about this label, set the desired offsets. Note
2136 that this sets the offset at a label to be the offset before a label
2137 if we don't know anything about the label. This is not correct for
2138 the label after a BARRIER, but is the best guess we can make. If
2139 we guessed wrong, we will suppress an elimination that might have
2140 been possible had we been able to guess correctly. */
2142 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2144 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2145 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2146 = (initial_p ? reg_eliminate[i].initial_offset
2147 : reg_eliminate[i].offset);
2148 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2151 /* Otherwise, if this is the definition of a label and it is
2152 preceded by a BARRIER, set our offsets to the known offset of
2156 && (tem = prev_nonnote_insn (insn)) != 0
2157 && GET_CODE (tem) == BARRIER)
2158 set_offsets_for_label (insn);
2160 /* If neither of the above cases is true, compare each offset
2161 with those previously recorded and suppress any eliminations
2162 where the offsets disagree. */
2164 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2165 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2166 != (initial_p ? reg_eliminate[i].initial_offset
2167 : reg_eliminate[i].offset))
2168 reg_eliminate[i].can_eliminate = 0;
2173 set_label_offsets (PATTERN (insn), insn, initial_p);
2175 /* ... fall through ... */
2179 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2180 and hence must have all eliminations at their initial offsets. */
2181 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2182 if (REG_NOTE_KIND (tem) == REG_LABEL)
2183 set_label_offsets (XEXP (tem, 0), insn, 1);
2189 /* Each of the labels in the parallel or address vector must be
2190 at their initial offsets. We want the first field for PARALLEL
2191 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2193 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2194 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2199 /* We only care about setting PC. If the source is not RETURN,
2200 IF_THEN_ELSE, or a label, disable any eliminations not at
2201 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2202 isn't one of those possibilities. For branches to a label,
2203 call ourselves recursively.
2205 Note that this can disable elimination unnecessarily when we have
2206 a non-local goto since it will look like a non-constant jump to
2207 someplace in the current function. This isn't a significant
2208 problem since such jumps will normally be when all elimination
2209 pairs are back to their initial offsets. */
2211 if (SET_DEST (x) != pc_rtx)
2214 switch (GET_CODE (SET_SRC (x)))
2221 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2225 tem = XEXP (SET_SRC (x), 1);
2226 if (GET_CODE (tem) == LABEL_REF)
2227 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2228 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2231 tem = XEXP (SET_SRC (x), 2);
2232 if (GET_CODE (tem) == LABEL_REF)
2233 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2234 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2242 /* If we reach here, all eliminations must be at their initial
2243 offset because we are doing a jump to a variable address. */
2244 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2245 if (p->offset != p->initial_offset)
2246 p->can_eliminate = 0;
2254 /* Scan X and replace any eliminable registers (such as fp) with a
2255 replacement (such as sp), plus an offset.
2257 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2258 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2259 MEM, we are allowed to replace a sum of a register and the constant zero
2260 with the register, which we cannot do outside a MEM. In addition, we need
2261 to record the fact that a register is referenced outside a MEM.
2263 If INSN is an insn, it is the insn containing X. If we replace a REG
2264 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2265 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2266 the REG is being modified.
2268 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2269 That's used when we eliminate in expressions stored in notes.
2270 This means, do not set ref_outside_mem even if the reference
2273 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2274 replacements done assuming all offsets are at their initial values. If
2275 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2276 encounter, return the actual location so that find_reloads will do
2277 the proper thing. */
2280 eliminate_regs (x, mem_mode, insn)
2282 enum machine_mode mem_mode;
2285 enum rtx_code code = GET_CODE (x);
2286 struct elim_table *ep;
2293 if (! current_function_decl)
2313 /* This is only for the benefit of the debugging backends, which call
2314 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2315 removed after CSE. */
2316 new = eliminate_regs (XEXP (x, 0), 0, insn);
2317 if (GET_CODE (new) == MEM)
2318 return XEXP (new, 0);
2324 /* First handle the case where we encounter a bare register that
2325 is eliminable. Replace it with a PLUS. */
2326 if (regno < FIRST_PSEUDO_REGISTER)
2328 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2330 if (ep->from_rtx == x && ep->can_eliminate)
2331 return plus_constant (ep->to_rtx, ep->previous_offset);
2334 else if (reg_renumber && reg_renumber[regno] < 0
2335 && reg_equiv_constant && reg_equiv_constant[regno]
2336 && ! CONSTANT_P (reg_equiv_constant[regno]))
2337 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2341 /* You might think handling MINUS in a manner similar to PLUS is a
2342 good idea. It is not. It has been tried multiple times and every
2343 time the change has had to have been reverted.
2345 Other parts of reload know a PLUS is special (gen_reload for example)
2346 and require special code to handle code a reloaded PLUS operand.
2348 Also consider backends where the flags register is clobbered by a
2349 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2350 lea instruction comes to mind). If we try to reload a MINUS, we
2351 may kill the flags register that was holding a useful value.
2353 So, please before trying to handle MINUS, consider reload as a
2354 whole instead of this little section as well as the backend issues. */
2356 /* If this is the sum of an eliminable register and a constant, rework
2358 if (GET_CODE (XEXP (x, 0)) == REG
2359 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2360 && CONSTANT_P (XEXP (x, 1)))
2362 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2364 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2366 /* The only time we want to replace a PLUS with a REG (this
2367 occurs when the constant operand of the PLUS is the negative
2368 of the offset) is when we are inside a MEM. We won't want
2369 to do so at other times because that would change the
2370 structure of the insn in a way that reload can't handle.
2371 We special-case the commonest situation in
2372 eliminate_regs_in_insn, so just replace a PLUS with a
2373 PLUS here, unless inside a MEM. */
2374 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2375 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2378 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2379 plus_constant (XEXP (x, 1),
2380 ep->previous_offset));
2383 /* If the register is not eliminable, we are done since the other
2384 operand is a constant. */
2388 /* If this is part of an address, we want to bring any constant to the
2389 outermost PLUS. We will do this by doing register replacement in
2390 our operands and seeing if a constant shows up in one of them.
2392 Note that there is no risk of modifying the structure of the insn,
2393 since we only get called for its operands, thus we are either
2394 modifying the address inside a MEM, or something like an address
2395 operand of a load-address insn. */
2398 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2399 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2401 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2403 /* If one side is a PLUS and the other side is a pseudo that
2404 didn't get a hard register but has a reg_equiv_constant,
2405 we must replace the constant here since it may no longer
2406 be in the position of any operand. */
2407 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2408 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2409 && reg_renumber[REGNO (new1)] < 0
2410 && reg_equiv_constant != 0
2411 && reg_equiv_constant[REGNO (new1)] != 0)
2412 new1 = reg_equiv_constant[REGNO (new1)];
2413 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2414 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2415 && reg_renumber[REGNO (new0)] < 0
2416 && reg_equiv_constant[REGNO (new0)] != 0)
2417 new0 = reg_equiv_constant[REGNO (new0)];
2419 new = form_sum (new0, new1);
2421 /* As above, if we are not inside a MEM we do not want to
2422 turn a PLUS into something else. We might try to do so here
2423 for an addition of 0 if we aren't optimizing. */
2424 if (! mem_mode && GET_CODE (new) != PLUS)
2425 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2433 /* If this is the product of an eliminable register and a
2434 constant, apply the distribute law and move the constant out
2435 so that we have (plus (mult ..) ..). This is needed in order
2436 to keep load-address insns valid. This case is pathological.
2437 We ignore the possibility of overflow here. */
2438 if (GET_CODE (XEXP (x, 0)) == REG
2439 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2440 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2441 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2443 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2446 /* Refs inside notes don't count for this purpose. */
2447 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2448 || GET_CODE (insn) == INSN_LIST)))
2449 ep->ref_outside_mem = 1;
2452 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2453 ep->previous_offset * INTVAL (XEXP (x, 1)));
2456 /* ... fall through ... */
2460 /* See comments before PLUS about handling MINUS. */
2462 case DIV: case UDIV:
2463 case MOD: case UMOD:
2464 case AND: case IOR: case XOR:
2465 case ROTATERT: case ROTATE:
2466 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2468 case GE: case GT: case GEU: case GTU:
2469 case LE: case LT: case LEU: case LTU:
2471 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2473 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2475 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2476 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2481 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2484 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2485 if (new != XEXP (x, 0))
2487 /* If this is a REG_DEAD note, it is not valid anymore.
2488 Using the eliminated version could result in creating a
2489 REG_DEAD note for the stack or frame pointer. */
2490 if (GET_MODE (x) == REG_DEAD)
2492 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2495 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2499 /* ... fall through ... */
2502 /* Now do eliminations in the rest of the chain. If this was
2503 an EXPR_LIST, this might result in allocating more memory than is
2504 strictly needed, but it simplifies the code. */
2507 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2508 if (new != XEXP (x, 1))
2510 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2518 case STRICT_LOW_PART:
2520 case SIGN_EXTEND: case ZERO_EXTEND:
2521 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2522 case FLOAT: case FIX:
2523 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2531 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2532 if (new != XEXP (x, 0))
2533 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2537 /* Similar to above processing, but preserve SUBREG_BYTE.
2538 Convert (subreg (mem)) to (mem) if not paradoxical.
2539 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2540 pseudo didn't get a hard reg, we must replace this with the
2541 eliminated version of the memory location because push_reloads
2542 may do the replacement in certain circumstances. */
2543 if (GET_CODE (SUBREG_REG (x)) == REG
2544 && (GET_MODE_SIZE (GET_MODE (x))
2545 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2546 && reg_equiv_memory_loc != 0
2547 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2549 new = SUBREG_REG (x);
2552 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2554 if (new != SUBREG_REG (x))
2556 int x_size = GET_MODE_SIZE (GET_MODE (x));
2557 int new_size = GET_MODE_SIZE (GET_MODE (new));
2559 if (GET_CODE (new) == MEM
2560 && ((x_size < new_size
2561 #ifdef WORD_REGISTER_OPERATIONS
2562 /* On these machines, combine can create rtl of the form
2563 (set (subreg:m1 (reg:m2 R) 0) ...)
2564 where m1 < m2, and expects something interesting to
2565 happen to the entire word. Moreover, it will use the
2566 (reg:m2 R) later, expecting all bits to be preserved.
2567 So if the number of words is the same, preserve the
2568 subreg so that push_reloads can see it. */
2569 && ! ((x_size - 1) / UNITS_PER_WORD
2570 == (new_size -1 ) / UNITS_PER_WORD)
2573 || x_size == new_size)
2575 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2577 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2583 /* This is only for the benefit of the debugging backends, which call
2584 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2585 removed after CSE. */
2586 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2587 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2589 /* Our only special processing is to pass the mode of the MEM to our
2590 recursive call and copy the flags. While we are here, handle this
2591 case more efficiently. */
2593 replace_equiv_address_nv (x,
2594 eliminate_regs (XEXP (x, 0),
2595 GET_MODE (x), insn));
2598 /* Handle insn_list USE that a call to a pure function may generate. */
2599 new = eliminate_regs (XEXP (x, 0), 0, insn);
2600 if (new != XEXP (x, 0))
2601 return gen_rtx_USE (GET_MODE (x), new);
2613 /* Process each of our operands recursively. If any have changed, make a
2615 fmt = GET_RTX_FORMAT (code);
2616 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2620 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2621 if (new != XEXP (x, i) && ! copied)
2623 rtx new_x = rtx_alloc (code);
2625 (sizeof (*new_x) - sizeof (new_x->fld)
2626 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2632 else if (*fmt == 'E')
2635 for (j = 0; j < XVECLEN (x, i); j++)
2637 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2638 if (new != XVECEXP (x, i, j) && ! copied_vec)
2640 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2644 rtx new_x = rtx_alloc (code);
2646 (sizeof (*new_x) - sizeof (new_x->fld)
2647 + (sizeof (new_x->fld[0])
2648 * GET_RTX_LENGTH (code))));
2652 XVEC (x, i) = new_v;
2655 XVECEXP (x, i, j) = new;
2663 /* Scan rtx X for modifications of elimination target registers. Update
2664 the table of eliminables to reflect the changed state. MEM_MODE is
2665 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2668 elimination_effects (x, mem_mode)
2670 enum machine_mode mem_mode;
2673 enum rtx_code code = GET_CODE (x);
2674 struct elim_table *ep;
2701 /* First handle the case where we encounter a bare register that
2702 is eliminable. Replace it with a PLUS. */
2703 if (regno < FIRST_PSEUDO_REGISTER)
2705 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2707 if (ep->from_rtx == x && ep->can_eliminate)
2710 ep->ref_outside_mem = 1;
2715 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2716 && reg_equiv_constant[regno]
2717 && ! function_invariant_p (reg_equiv_constant[regno]))
2718 elimination_effects (reg_equiv_constant[regno], mem_mode);
2727 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2728 if (ep->to_rtx == XEXP (x, 0))
2730 int size = GET_MODE_SIZE (mem_mode);
2732 /* If more bytes than MEM_MODE are pushed, account for them. */
2733 #ifdef PUSH_ROUNDING
2734 if (ep->to_rtx == stack_pointer_rtx)
2735 size = PUSH_ROUNDING (size);
2737 if (code == PRE_DEC || code == POST_DEC)
2739 else if (code == PRE_INC || code == POST_INC)
2741 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2742 && GET_CODE (XEXP (x, 1)) == PLUS
2743 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2744 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2745 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2748 /* These two aren't unary operators. */
2749 if (code == POST_MODIFY || code == PRE_MODIFY)
2752 /* Fall through to generic unary operation case. */
2753 case STRICT_LOW_PART:
2755 case SIGN_EXTEND: case ZERO_EXTEND:
2756 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2757 case FLOAT: case FIX:
2758 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2766 elimination_effects (XEXP (x, 0), mem_mode);
2770 if (GET_CODE (SUBREG_REG (x)) == REG
2771 && (GET_MODE_SIZE (GET_MODE (x))
2772 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2773 && reg_equiv_memory_loc != 0
2774 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2777 elimination_effects (SUBREG_REG (x), mem_mode);
2781 /* If using a register that is the source of an eliminate we still
2782 think can be performed, note it cannot be performed since we don't
2783 know how this register is used. */
2784 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2785 if (ep->from_rtx == XEXP (x, 0))
2786 ep->can_eliminate = 0;
2788 elimination_effects (XEXP (x, 0), mem_mode);
2792 /* If clobbering a register that is the replacement register for an
2793 elimination we still think can be performed, note that it cannot
2794 be performed. Otherwise, we need not be concerned about it. */
2795 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2796 if (ep->to_rtx == XEXP (x, 0))
2797 ep->can_eliminate = 0;
2799 elimination_effects (XEXP (x, 0), mem_mode);
2803 /* Check for setting a register that we know about. */
2804 if (GET_CODE (SET_DEST (x)) == REG)
2806 /* See if this is setting the replacement register for an
2809 If DEST is the hard frame pointer, we do nothing because we
2810 assume that all assignments to the frame pointer are for
2811 non-local gotos and are being done at a time when they are valid
2812 and do not disturb anything else. Some machines want to
2813 eliminate a fake argument pointer (or even a fake frame pointer)
2814 with either the real frame or the stack pointer. Assignments to
2815 the hard frame pointer must not prevent this elimination. */
2817 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2819 if (ep->to_rtx == SET_DEST (x)
2820 && SET_DEST (x) != hard_frame_pointer_rtx)
2822 /* If it is being incremented, adjust the offset. Otherwise,
2823 this elimination can't be done. */
2824 rtx src = SET_SRC (x);
2826 if (GET_CODE (src) == PLUS
2827 && XEXP (src, 0) == SET_DEST (x)
2828 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2829 ep->offset -= INTVAL (XEXP (src, 1));
2831 ep->can_eliminate = 0;
2835 elimination_effects (SET_DEST (x), 0);
2836 elimination_effects (SET_SRC (x), 0);
2840 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2843 /* Our only special processing is to pass the mode of the MEM to our
2845 elimination_effects (XEXP (x, 0), GET_MODE (x));
2852 fmt = GET_RTX_FORMAT (code);
2853 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2856 elimination_effects (XEXP (x, i), mem_mode);
2857 else if (*fmt == 'E')
2858 for (j = 0; j < XVECLEN (x, i); j++)
2859 elimination_effects (XVECEXP (x, i, j), mem_mode);
2863 /* Descend through rtx X and verify that no references to eliminable registers
2864 remain. If any do remain, mark the involved register as not
2868 check_eliminable_occurrences (x)
2878 code = GET_CODE (x);
2880 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2882 struct elim_table *ep;
2884 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2885 if (ep->from_rtx == x && ep->can_eliminate)
2886 ep->can_eliminate = 0;
2890 fmt = GET_RTX_FORMAT (code);
2891 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2894 check_eliminable_occurrences (XEXP (x, i));
2895 else if (*fmt == 'E')
2898 for (j = 0; j < XVECLEN (x, i); j++)
2899 check_eliminable_occurrences (XVECEXP (x, i, j));
2904 /* Scan INSN and eliminate all eliminable registers in it.
2906 If REPLACE is nonzero, do the replacement destructively. Also
2907 delete the insn as dead it if it is setting an eliminable register.
2909 If REPLACE is zero, do all our allocations in reload_obstack.
2911 If no eliminations were done and this insn doesn't require any elimination
2912 processing (these are not identical conditions: it might be updating sp,
2913 but not referencing fp; this needs to be seen during reload_as_needed so
2914 that the offset between fp and sp can be taken into consideration), zero
2915 is returned. Otherwise, 1 is returned. */
2918 eliminate_regs_in_insn (insn, replace)
2922 int icode = recog_memoized (insn);
2923 rtx old_body = PATTERN (insn);
2924 int insn_is_asm = asm_noperands (old_body) >= 0;
2925 rtx old_set = single_set (insn);
2929 rtx substed_operand[MAX_RECOG_OPERANDS];
2930 rtx orig_operand[MAX_RECOG_OPERANDS];
2931 struct elim_table *ep;
2933 if (! insn_is_asm && icode < 0)
2935 if (GET_CODE (PATTERN (insn)) == USE
2936 || GET_CODE (PATTERN (insn)) == CLOBBER
2937 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2938 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2939 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2944 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2945 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2947 /* Check for setting an eliminable register. */
2948 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2949 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2951 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2952 /* If this is setting the frame pointer register to the
2953 hardware frame pointer register and this is an elimination
2954 that will be done (tested above), this insn is really
2955 adjusting the frame pointer downward to compensate for
2956 the adjustment done before a nonlocal goto. */
2957 if (ep->from == FRAME_POINTER_REGNUM
2958 && ep->to == HARD_FRAME_POINTER_REGNUM)
2960 rtx base = SET_SRC (old_set);
2961 rtx base_insn = insn;
2964 while (base != ep->to_rtx)
2966 rtx prev_insn, prev_set;
2968 if (GET_CODE (base) == PLUS
2969 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2971 offset += INTVAL (XEXP (base, 1));
2972 base = XEXP (base, 0);
2974 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2975 && (prev_set = single_set (prev_insn)) != 0
2976 && rtx_equal_p (SET_DEST (prev_set), base))
2978 base = SET_SRC (prev_set);
2979 base_insn = prev_insn;
2985 if (base == ep->to_rtx)
2988 = plus_constant (ep->to_rtx, offset - ep->offset);
2990 new_body = old_body;
2993 new_body = copy_insn (old_body);
2994 if (REG_NOTES (insn))
2995 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2997 PATTERN (insn) = new_body;
2998 old_set = single_set (insn);
3000 /* First see if this insn remains valid when we
3001 make the change. If not, keep the INSN_CODE
3002 the same and let reload fit it up. */
3003 validate_change (insn, &SET_SRC (old_set), src, 1);
3004 validate_change (insn, &SET_DEST (old_set),
3006 if (! apply_change_group ())
3008 SET_SRC (old_set) = src;
3009 SET_DEST (old_set) = ep->to_rtx;
3018 /* In this case this insn isn't serving a useful purpose. We
3019 will delete it in reload_as_needed once we know that this
3020 elimination is, in fact, being done.
3022 If REPLACE isn't set, we can't delete this insn, but needn't
3023 process it since it won't be used unless something changes. */
3026 delete_dead_insn (insn);
3034 /* We allow one special case which happens to work on all machines we
3035 currently support: a single set with the source being a PLUS of an
3036 eliminable register and a constant. */
3038 && GET_CODE (SET_DEST (old_set)) == REG
3039 && GET_CODE (SET_SRC (old_set)) == PLUS
3040 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3041 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
3042 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
3044 rtx reg = XEXP (SET_SRC (old_set), 0);
3045 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
3047 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3048 if (ep->from_rtx == reg && ep->can_eliminate)
3050 offset += ep->offset;
3055 /* We assume here that if we need a PARALLEL with
3056 CLOBBERs for this assignment, we can do with the
3057 MATCH_SCRATCHes that add_clobbers allocates.
3058 There's not much we can do if that doesn't work. */
3059 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3063 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3066 rtvec vec = rtvec_alloc (num_clobbers + 1);
3068 vec->elem[0] = PATTERN (insn);
3069 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3070 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3072 if (INSN_CODE (insn) < 0)
3077 new_body = old_body;
3080 new_body = copy_insn (old_body);
3081 if (REG_NOTES (insn))
3082 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3084 PATTERN (insn) = new_body;
3085 old_set = single_set (insn);
3087 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3088 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3091 /* This can't have an effect on elimination offsets, so skip right
3097 /* Determine the effects of this insn on elimination offsets. */
3098 elimination_effects (old_body, 0);
3100 /* Eliminate all eliminable registers occurring in operands that
3101 can be handled by reload. */
3102 extract_insn (insn);
3103 for (i = 0; i < recog_data.n_operands; i++)
3105 orig_operand[i] = recog_data.operand[i];
3106 substed_operand[i] = recog_data.operand[i];
3108 /* For an asm statement, every operand is eliminable. */
3109 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3111 /* Check for setting a register that we know about. */
3112 if (recog_data.operand_type[i] != OP_IN
3113 && GET_CODE (orig_operand[i]) == REG)
3115 /* If we are assigning to a register that can be eliminated, it
3116 must be as part of a PARALLEL, since the code above handles
3117 single SETs. We must indicate that we can no longer
3118 eliminate this reg. */
3119 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3121 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3122 ep->can_eliminate = 0;
3125 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3126 replace ? insn : NULL_RTX);
3127 if (substed_operand[i] != orig_operand[i])
3129 /* Terminate the search in check_eliminable_occurrences at
3131 *recog_data.operand_loc[i] = 0;
3133 /* If an output operand changed from a REG to a MEM and INSN is an
3134 insn, write a CLOBBER insn. */
3135 if (recog_data.operand_type[i] != OP_IN
3136 && GET_CODE (orig_operand[i]) == REG
3137 && GET_CODE (substed_operand[i]) == MEM
3139 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3144 for (i = 0; i < recog_data.n_dups; i++)
3145 *recog_data.dup_loc[i]
3146 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3148 /* If any eliminable remain, they aren't eliminable anymore. */
3149 check_eliminable_occurrences (old_body);
3151 /* Substitute the operands; the new values are in the substed_operand
3153 for (i = 0; i < recog_data.n_operands; i++)
3154 *recog_data.operand_loc[i] = substed_operand[i];
3155 for (i = 0; i < recog_data.n_dups; i++)
3156 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3158 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3159 re-recognize the insn. We do this in case we had a simple addition
3160 but now can do this as a load-address. This saves an insn in this
3162 If re-recognition fails, the old insn code number will still be used,
3163 and some register operands may have changed into PLUS expressions.
3164 These will be handled by find_reloads by loading them into a register
3169 /* If we aren't replacing things permanently and we changed something,
3170 make another copy to ensure that all the RTL is new. Otherwise
3171 things can go wrong if find_reload swaps commutative operands
3172 and one is inside RTL that has been copied while the other is not. */
3173 new_body = old_body;
3176 new_body = copy_insn (old_body);
3177 if (REG_NOTES (insn))
3178 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3180 PATTERN (insn) = new_body;
3182 /* If we had a move insn but now we don't, rerecognize it. This will
3183 cause spurious re-recognition if the old move had a PARALLEL since
3184 the new one still will, but we can't call single_set without
3185 having put NEW_BODY into the insn and the re-recognition won't
3186 hurt in this rare case. */
3187 /* ??? Why this huge if statement - why don't we just rerecognize the
3191 && ((GET_CODE (SET_SRC (old_set)) == REG
3192 && (GET_CODE (new_body) != SET
3193 || GET_CODE (SET_SRC (new_body)) != REG))
3194 /* If this was a load from or store to memory, compare
3195 the MEM in recog_data.operand to the one in the insn.
3196 If they are not equal, then rerecognize the insn. */
3198 && ((GET_CODE (SET_SRC (old_set)) == MEM
3199 && SET_SRC (old_set) != recog_data.operand[1])
3200 || (GET_CODE (SET_DEST (old_set)) == MEM
3201 && SET_DEST (old_set) != recog_data.operand[0])))
3202 /* If this was an add insn before, rerecognize. */
3203 || GET_CODE (SET_SRC (old_set)) == PLUS))
3205 int new_icode = recog (PATTERN (insn), insn, 0);
3207 INSN_CODE (insn) = icode;
3211 /* Restore the old body. If there were any changes to it, we made a copy
3212 of it while the changes were still in place, so we'll correctly return
3213 a modified insn below. */
3216 /* Restore the old body. */
3217 for (i = 0; i < recog_data.n_operands; i++)
3218 *recog_data.operand_loc[i] = orig_operand[i];
3219 for (i = 0; i < recog_data.n_dups; i++)
3220 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3223 /* Update all elimination pairs to reflect the status after the current
3224 insn. The changes we make were determined by the earlier call to
3225 elimination_effects.
3227 We also detect cases where register elimination cannot be done,
3228 namely, if a register would be both changed and referenced outside a MEM
3229 in the resulting insn since such an insn is often undefined and, even if
3230 not, we cannot know what meaning will be given to it. Note that it is
3231 valid to have a register used in an address in an insn that changes it
3232 (presumably with a pre- or post-increment or decrement).
3234 If anything changes, return nonzero. */
3236 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3238 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3239 ep->can_eliminate = 0;
3241 ep->ref_outside_mem = 0;
3243 if (ep->previous_offset != ep->offset)
3248 /* If we changed something, perform elimination in REG_NOTES. This is
3249 needed even when REPLACE is zero because a REG_DEAD note might refer
3250 to a register that we eliminate and could cause a different number
3251 of spill registers to be needed in the final reload pass than in
3253 if (val && REG_NOTES (insn) != 0)
3254 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3259 /* Loop through all elimination pairs.
3260 Recalculate the number not at initial offset.
3262 Compute the maximum offset (minimum offset if the stack does not
3263 grow downward) for each elimination pair. */
3266 update_eliminable_offsets ()
3268 struct elim_table *ep;
3270 num_not_at_initial_offset = 0;
3271 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3273 ep->previous_offset = ep->offset;
3274 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3275 num_not_at_initial_offset++;
3279 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3280 replacement we currently believe is valid, mark it as not eliminable if X
3281 modifies DEST in any way other than by adding a constant integer to it.
3283 If DEST is the frame pointer, we do nothing because we assume that
3284 all assignments to the hard frame pointer are nonlocal gotos and are being
3285 done at a time when they are valid and do not disturb anything else.
3286 Some machines want to eliminate a fake argument pointer with either the
3287 frame or stack pointer. Assignments to the hard frame pointer must not
3288 prevent this elimination.
3290 Called via note_stores from reload before starting its passes to scan
3291 the insns of the function. */
3294 mark_not_eliminable (dest, x, data)
3297 void *data ATTRIBUTE_UNUSED;
3301 /* A SUBREG of a hard register here is just changing its mode. We should
3302 not see a SUBREG of an eliminable hard register, but check just in
3304 if (GET_CODE (dest) == SUBREG)
3305 dest = SUBREG_REG (dest);
3307 if (dest == hard_frame_pointer_rtx)
3310 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3311 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3312 && (GET_CODE (x) != SET
3313 || GET_CODE (SET_SRC (x)) != PLUS
3314 || XEXP (SET_SRC (x), 0) != dest
3315 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3317 reg_eliminate[i].can_eliminate_previous
3318 = reg_eliminate[i].can_eliminate = 0;
3323 /* Verify that the initial elimination offsets did not change since the
3324 last call to set_initial_elim_offsets. This is used to catch cases
3325 where something illegal happened during reload_as_needed that could
3326 cause incorrect code to be generated if we did not check for it. */
3329 verify_initial_elim_offsets ()
3333 #ifdef ELIMINABLE_REGS
3334 struct elim_table *ep;
3336 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3338 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3339 if (t != ep->initial_offset)
3343 INITIAL_FRAME_POINTER_OFFSET (t);
3344 if (t != reg_eliminate[0].initial_offset)
3349 /* Reset all offsets on eliminable registers to their initial values. */
3352 set_initial_elim_offsets ()
3354 struct elim_table *ep = reg_eliminate;
3356 #ifdef ELIMINABLE_REGS
3357 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3359 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3360 ep->previous_offset = ep->offset = ep->initial_offset;
3363 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3364 ep->previous_offset = ep->offset = ep->initial_offset;
3367 num_not_at_initial_offset = 0;
3370 /* Initialize the known label offsets.
3371 Set a known offset for each forced label to be at the initial offset
3372 of each elimination. We do this because we assume that all
3373 computed jumps occur from a location where each elimination is
3374 at its initial offset.
3375 For all other labels, show that we don't know the offsets. */
3378 set_initial_label_offsets ()
3381 memset (offsets_known_at, 0, num_labels);
3383 for (x = forced_labels; x; x = XEXP (x, 1))
3385 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3388 /* Set all elimination offsets to the known values for the code label given
3392 set_offsets_for_label (insn)
3396 int label_nr = CODE_LABEL_NUMBER (insn);
3397 struct elim_table *ep;
3399 num_not_at_initial_offset = 0;
3400 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3402 ep->offset = ep->previous_offset
3403 = offsets_at[label_nr - first_label_num][i];
3404 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3405 num_not_at_initial_offset++;
3409 /* See if anything that happened changes which eliminations are valid.
3410 For example, on the SPARC, whether or not the frame pointer can
3411 be eliminated can depend on what registers have been used. We need
3412 not check some conditions again (such as flag_omit_frame_pointer)
3413 since they can't have changed. */
3416 update_eliminables (pset)
3419 int previous_frame_pointer_needed = frame_pointer_needed;
3420 struct elim_table *ep;
3422 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3423 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3424 #ifdef ELIMINABLE_REGS
3425 || ! CAN_ELIMINATE (ep->from, ep->to)
3428 ep->can_eliminate = 0;
3430 /* Look for the case where we have discovered that we can't replace
3431 register A with register B and that means that we will now be
3432 trying to replace register A with register C. This means we can
3433 no longer replace register C with register B and we need to disable
3434 such an elimination, if it exists. This occurs often with A == ap,
3435 B == sp, and C == fp. */
3437 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3439 struct elim_table *op;
3442 if (! ep->can_eliminate && ep->can_eliminate_previous)
3444 /* Find the current elimination for ep->from, if there is a
3446 for (op = reg_eliminate;
3447 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3448 if (op->from == ep->from && op->can_eliminate)
3454 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3456 for (op = reg_eliminate;
3457 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3458 if (op->from == new_to && op->to == ep->to)
3459 op->can_eliminate = 0;
3463 /* See if any registers that we thought we could eliminate the previous
3464 time are no longer eliminable. If so, something has changed and we
3465 must spill the register. Also, recompute the number of eliminable
3466 registers and see if the frame pointer is needed; it is if there is
3467 no elimination of the frame pointer that we can perform. */
3469 frame_pointer_needed = 1;
3470 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3472 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3473 && ep->to != HARD_FRAME_POINTER_REGNUM)
3474 frame_pointer_needed = 0;
3476 if (! ep->can_eliminate && ep->can_eliminate_previous)
3478 ep->can_eliminate_previous = 0;
3479 SET_HARD_REG_BIT (*pset, ep->from);
3484 /* If we didn't need a frame pointer last time, but we do now, spill
3485 the hard frame pointer. */
3486 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3487 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3490 /* Initialize the table of registers to eliminate. */
3495 struct elim_table *ep;
3496 #ifdef ELIMINABLE_REGS
3497 const struct elim_table_1 *ep1;
3501 reg_eliminate = (struct elim_table *)
3502 xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3504 /* Does this function require a frame pointer? */
3506 frame_pointer_needed = (! flag_omit_frame_pointer
3507 #ifdef EXIT_IGNORE_STACK
3508 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3509 and restore sp for alloca. So we can't eliminate
3510 the frame pointer in that case. At some point,
3511 we should improve this by emitting the
3512 sp-adjusting insns for this case. */
3513 || (current_function_calls_alloca
3514 && EXIT_IGNORE_STACK)
3516 || FRAME_POINTER_REQUIRED);
3520 #ifdef ELIMINABLE_REGS
3521 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3522 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3524 ep->from = ep1->from;
3526 ep->can_eliminate = ep->can_eliminate_previous
3527 = (CAN_ELIMINATE (ep->from, ep->to)
3528 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3531 reg_eliminate[0].from = reg_eliminate_1[0].from;
3532 reg_eliminate[0].to = reg_eliminate_1[0].to;
3533 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3534 = ! frame_pointer_needed;
3537 /* Count the number of eliminable registers and build the FROM and TO
3538 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3539 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3540 We depend on this. */
3541 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3543 num_eliminable += ep->can_eliminate;
3544 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3545 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3549 /* Kick all pseudos out of hard register REGNO.
3551 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3552 because we found we can't eliminate some register. In the case, no pseudos
3553 are allowed to be in the register, even if they are only in a block that
3554 doesn't require spill registers, unlike the case when we are spilling this
3555 hard reg to produce another spill register.
3557 Return nonzero if any pseudos needed to be kicked out. */
3560 spill_hard_reg (regno, cant_eliminate)
3568 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3569 regs_ever_live[regno] = 1;
3572 /* Spill every pseudo reg that was allocated to this reg
3573 or to something that overlaps this reg. */
3575 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3576 if (reg_renumber[i] >= 0
3577 && (unsigned int) reg_renumber[i] <= regno
3578 && ((unsigned int) reg_renumber[i]
3579 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3580 PSEUDO_REGNO_MODE (i))
3582 SET_REGNO_REG_SET (&spilled_pseudos, i);
3585 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3586 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3589 ior_hard_reg_set (set1, set2)
3590 HARD_REG_SET *set1, *set2;
3592 IOR_HARD_REG_SET (*set1, *set2);
3595 /* After find_reload_regs has been run for all insn that need reloads,
3596 and/or spill_hard_regs was called, this function is used to actually
3597 spill pseudo registers and try to reallocate them. It also sets up the
3598 spill_regs array for use by choose_reload_regs. */
3601 finish_spills (global)
3604 struct insn_chain *chain;
3605 int something_changed = 0;
3608 /* Build the spill_regs array for the function. */
3609 /* If there are some registers still to eliminate and one of the spill regs
3610 wasn't ever used before, additional stack space may have to be
3611 allocated to store this register. Thus, we may have changed the offset
3612 between the stack and frame pointers, so mark that something has changed.
3614 One might think that we need only set VAL to 1 if this is a call-used
3615 register. However, the set of registers that must be saved by the
3616 prologue is not identical to the call-used set. For example, the
3617 register used by the call insn for the return PC is a call-used register,
3618 but must be saved by the prologue. */
3621 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3622 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3624 spill_reg_order[i] = n_spills;
3625 spill_regs[n_spills++] = i;
3626 if (num_eliminable && ! regs_ever_live[i])
3627 something_changed = 1;
3628 regs_ever_live[i] = 1;
3631 spill_reg_order[i] = -1;
3633 EXECUTE_IF_SET_IN_REG_SET
3634 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3636 /* Record the current hard register the pseudo is allocated to in
3637 pseudo_previous_regs so we avoid reallocating it to the same
3638 hard reg in a later pass. */
3639 if (reg_renumber[i] < 0)
3642 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3643 /* Mark it as no longer having a hard register home. */
3644 reg_renumber[i] = -1;
3645 /* We will need to scan everything again. */
3646 something_changed = 1;
3649 /* Retry global register allocation if possible. */
3652 memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3653 /* For every insn that needs reloads, set the registers used as spill
3654 regs in pseudo_forbidden_regs for every pseudo live across the
3656 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3658 EXECUTE_IF_SET_IN_REG_SET
3659 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3661 ior_hard_reg_set (pseudo_forbidden_regs + i,
3662 &chain->used_spill_regs);
3664 EXECUTE_IF_SET_IN_REG_SET
3665 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3667 ior_hard_reg_set (pseudo_forbidden_regs + i,
3668 &chain->used_spill_regs);
3672 /* Retry allocating the spilled pseudos. For each reg, merge the
3673 various reg sets that indicate which hard regs can't be used,
3674 and call retry_global_alloc.
3675 We change spill_pseudos here to only contain pseudos that did not
3676 get a new hard register. */
3677 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3678 if (reg_old_renumber[i] != reg_renumber[i])
3680 HARD_REG_SET forbidden;
3681 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3682 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3683 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3684 retry_global_alloc (i, forbidden);
3685 if (reg_renumber[i] >= 0)
3686 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3690 /* Fix up the register information in the insn chain.
3691 This involves deleting those of the spilled pseudos which did not get
3692 a new hard register home from the live_{before,after} sets. */
3693 for (chain = reload_insn_chain; chain; chain = chain->next)
3695 HARD_REG_SET used_by_pseudos;
3696 HARD_REG_SET used_by_pseudos2;
3698 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3699 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3701 /* Mark any unallocated hard regs as available for spills. That
3702 makes inheritance work somewhat better. */
3703 if (chain->need_reload)
3705 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3706 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3707 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3709 /* Save the old value for the sanity test below. */
3710 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3712 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3713 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3714 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3715 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3717 /* Make sure we only enlarge the set. */
3718 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3724 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3725 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3727 int regno = reg_renumber[i];
3728 if (reg_old_renumber[i] == regno)
3731 alter_reg (i, reg_old_renumber[i]);
3732 reg_old_renumber[i] = regno;
3736 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3738 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3739 i, reg_renumber[i]);
3743 return something_changed;
3746 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3747 Also mark any hard registers used to store user variables as
3748 forbidden from being used for spill registers. */
3751 scan_paradoxical_subregs (x)
3756 enum rtx_code code = GET_CODE (x);
3762 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3763 && REG_USERVAR_P (x))
3764 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3773 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3781 if (GET_CODE (SUBREG_REG (x)) == REG
3782 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3783 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3784 = GET_MODE_SIZE (GET_MODE (x));
3791 fmt = GET_RTX_FORMAT (code);
3792 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3795 scan_paradoxical_subregs (XEXP (x, i));
3796 else if (fmt[i] == 'E')
3799 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3800 scan_paradoxical_subregs (XVECEXP (x, i, j));
3805 /* Reload pseudo-registers into hard regs around each insn as needed.
3806 Additional register load insns are output before the insn that needs it
3807 and perhaps store insns after insns that modify the reloaded pseudo reg.
3809 reg_last_reload_reg and reg_reloaded_contents keep track of
3810 which registers are already available in reload registers.
3811 We update these for the reloads that we perform,
3812 as the insns are scanned. */
3815 reload_as_needed (live_known)
3818 struct insn_chain *chain;
3819 #if defined (AUTO_INC_DEC)
3824 memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx);
3825 memset ((char *) spill_reg_store, 0, sizeof spill_reg_store);
3826 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3827 reg_has_output_reload = (char *) xmalloc (max_regno);
3828 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3830 set_initial_elim_offsets ();
3832 for (chain = reload_insn_chain; chain; chain = chain->next)
3835 rtx insn = chain->insn;
3836 rtx old_next = NEXT_INSN (insn);
3838 /* If we pass a label, copy the offsets from the label information
3839 into the current offsets of each elimination. */
3840 if (GET_CODE (insn) == CODE_LABEL)
3841 set_offsets_for_label (insn);
3843 else if (INSN_P (insn))
3845 rtx oldpat = copy_rtx (PATTERN (insn));
3847 /* If this is a USE and CLOBBER of a MEM, ensure that any
3848 references to eliminable registers have been removed. */
3850 if ((GET_CODE (PATTERN (insn)) == USE
3851 || GET_CODE (PATTERN (insn)) == CLOBBER)
3852 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3853 XEXP (XEXP (PATTERN (insn), 0), 0)
3854 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3855 GET_MODE (XEXP (PATTERN (insn), 0)),
3858 /* If we need to do register elimination processing, do so.
3859 This might delete the insn, in which case we are done. */
3860 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3862 eliminate_regs_in_insn (insn, 1);
3863 if (GET_CODE (insn) == NOTE)
3865 update_eliminable_offsets ();
3870 /* If need_elim is nonzero but need_reload is zero, one might think
3871 that we could simply set n_reloads to 0. However, find_reloads
3872 could have done some manipulation of the insn (such as swapping
3873 commutative operands), and these manipulations are lost during
3874 the first pass for every insn that needs register elimination.
3875 So the actions of find_reloads must be redone here. */
3877 if (! chain->need_elim && ! chain->need_reload
3878 && ! chain->need_operand_change)
3880 /* First find the pseudo regs that must be reloaded for this insn.
3881 This info is returned in the tables reload_... (see reload.h).
3882 Also modify the body of INSN by substituting RELOAD
3883 rtx's for those pseudo regs. */
3886 memset (reg_has_output_reload, 0, max_regno);
3887 CLEAR_HARD_REG_SET (reg_is_output_reload);
3889 find_reloads (insn, 1, spill_indirect_levels, live_known,
3895 rtx next = NEXT_INSN (insn);
3898 prev = PREV_INSN (insn);
3900 /* Now compute which reload regs to reload them into. Perhaps
3901 reusing reload regs from previous insns, or else output
3902 load insns to reload them. Maybe output store insns too.
3903 Record the choices of reload reg in reload_reg_rtx. */
3904 choose_reload_regs (chain);
3906 /* Merge any reloads that we didn't combine for fear of
3907 increasing the number of spill registers needed but now
3908 discover can be safely merged. */
3909 if (SMALL_REGISTER_CLASSES)
3910 merge_assigned_reloads (insn);
3912 /* Generate the insns to reload operands into or out of
3913 their reload regs. */
3914 emit_reload_insns (chain);
3916 /* Substitute the chosen reload regs from reload_reg_rtx
3917 into the insn's body (or perhaps into the bodies of other
3918 load and store insn that we just made for reloading
3919 and that we moved the structure into). */
3920 subst_reloads (insn);
3922 /* If this was an ASM, make sure that all the reload insns
3923 we have generated are valid. If not, give an error
3926 if (asm_noperands (PATTERN (insn)) >= 0)
3927 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3928 if (p != insn && INSN_P (p)
3929 && GET_CODE (PATTERN (p)) != USE
3930 && (recog_memoized (p) < 0
3931 || (extract_insn (p), ! constrain_operands (1))))
3933 error_for_asm (insn,
3934 "`asm' operand requires impossible reload");
3939 if (num_eliminable && chain->need_elim)
3940 update_eliminable_offsets ();
3942 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3943 is no longer validly lying around to save a future reload.
3944 Note that this does not detect pseudos that were reloaded
3945 for this insn in order to be stored in
3946 (obeying register constraints). That is correct; such reload
3947 registers ARE still valid. */
3948 note_stores (oldpat, forget_old_reloads_1, NULL);
3950 /* There may have been CLOBBER insns placed after INSN. So scan
3951 between INSN and NEXT and use them to forget old reloads. */
3952 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3953 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3954 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3957 /* Likewise for regs altered by auto-increment in this insn.
3958 REG_INC notes have been changed by reloading:
3959 find_reloads_address_1 records substitutions for them,
3960 which have been performed by subst_reloads above. */
3961 for (i = n_reloads - 1; i >= 0; i--)
3963 rtx in_reg = rld[i].in_reg;
3966 enum rtx_code code = GET_CODE (in_reg);
3967 /* PRE_INC / PRE_DEC will have the reload register ending up
3968 with the same value as the stack slot, but that doesn't
3969 hold true for POST_INC / POST_DEC. Either we have to
3970 convert the memory access to a true POST_INC / POST_DEC,
3971 or we can't use the reload register for inheritance. */
3972 if ((code == POST_INC || code == POST_DEC)
3973 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3974 REGNO (rld[i].reg_rtx))
3975 /* Make sure it is the inc/dec pseudo, and not
3976 some other (e.g. output operand) pseudo. */
3977 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3978 == REGNO (XEXP (in_reg, 0))))
3981 rtx reload_reg = rld[i].reg_rtx;
3982 enum machine_mode mode = GET_MODE (reload_reg);
3986 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3988 /* We really want to ignore REG_INC notes here, so
3989 use PATTERN (p) as argument to reg_set_p . */
3990 if (reg_set_p (reload_reg, PATTERN (p)))
3992 n = count_occurrences (PATTERN (p), reload_reg, 0);
3997 n = validate_replace_rtx (reload_reg,
3998 gen_rtx (code, mode,
4002 /* We must also verify that the constraints
4003 are met after the replacement. */
4006 n = constrain_operands (1);
4010 /* If the constraints were not met, then
4011 undo the replacement. */
4014 validate_replace_rtx (gen_rtx (code, mode,
4026 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4028 /* Mark this as having an output reload so that the
4029 REG_INC processing code below won't invalidate
4030 the reload for inheritance. */
4031 SET_HARD_REG_BIT (reg_is_output_reload,
4032 REGNO (reload_reg));
4033 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4036 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4039 else if ((code == PRE_INC || code == PRE_DEC)
4040 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4041 REGNO (rld[i].reg_rtx))
4042 /* Make sure it is the inc/dec pseudo, and not
4043 some other (e.g. output operand) pseudo. */
4044 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4045 == REGNO (XEXP (in_reg, 0))))
4047 SET_HARD_REG_BIT (reg_is_output_reload,
4048 REGNO (rld[i].reg_rtx));
4049 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4053 /* If a pseudo that got a hard register is auto-incremented,
4054 we must purge records of copying it into pseudos without
4056 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4057 if (REG_NOTE_KIND (x) == REG_INC)
4059 /* See if this pseudo reg was reloaded in this insn.
4060 If so, its last-reload info is still valid
4061 because it is based on this insn's reload. */
4062 for (i = 0; i < n_reloads; i++)
4063 if (rld[i].out == XEXP (x, 0))
4067 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4071 /* A reload reg's contents are unknown after a label. */
4072 if (GET_CODE (insn) == CODE_LABEL)
4073 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4075 /* Don't assume a reload reg is still good after a call insn
4076 if it is a call-used reg. */
4077 else if (GET_CODE (insn) == CALL_INSN)
4078 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4082 free (reg_last_reload_reg);
4083 free (reg_has_output_reload);
4086 /* Discard all record of any value reloaded from X,
4087 or reloaded in X from someplace else;
4088 unless X is an output reload reg of the current insn.
4090 X may be a hard reg (the reload reg)
4091 or it may be a pseudo reg that was reloaded from. */
4094 forget_old_reloads_1 (x, ignored, data)
4096 rtx ignored ATTRIBUTE_UNUSED;
4097 void *data ATTRIBUTE_UNUSED;
4102 /* note_stores does give us subregs of hard regs,
4103 subreg_regno_offset will abort if it is not a hard reg. */
4104 while (GET_CODE (x) == SUBREG)
4106 /* We ignore the subreg offset when calculating the regno,
4107 because we are using the entire underlying hard register
4112 if (GET_CODE (x) != REG)
4117 if (regno >= FIRST_PSEUDO_REGISTER)
4123 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4124 /* Storing into a spilled-reg invalidates its contents.
4125 This can happen if a block-local pseudo is allocated to that reg
4126 and it wasn't spilled because this block's total need is 0.
4127 Then some insn might have an optional reload and use this reg. */
4128 for (i = 0; i < nr; i++)
4129 /* But don't do this if the reg actually serves as an output
4130 reload reg in the current instruction. */
4132 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4134 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4135 spill_reg_store[regno + i] = 0;
4139 /* Since value of X has changed,
4140 forget any value previously copied from it. */
4143 /* But don't forget a copy if this is the output reload
4144 that establishes the copy's validity. */
4145 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4146 reg_last_reload_reg[regno + nr] = 0;
4149 /* The following HARD_REG_SETs indicate when each hard register is
4150 used for a reload of various parts of the current insn. */
4152 /* If reg is unavailable for all reloads. */
4153 static HARD_REG_SET reload_reg_unavailable;
4154 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4155 static HARD_REG_SET reload_reg_used;
4156 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4157 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4158 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4159 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4160 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4161 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4162 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4163 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4164 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4165 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4166 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4167 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4168 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4169 static HARD_REG_SET reload_reg_used_in_op_addr;
4170 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4171 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4172 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4173 static HARD_REG_SET reload_reg_used_in_insn;
4174 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4175 static HARD_REG_SET reload_reg_used_in_other_addr;
4177 /* If reg is in use as a reload reg for any sort of reload. */
4178 static HARD_REG_SET reload_reg_used_at_all;
4180 /* If reg is use as an inherited reload. We just mark the first register
4182 static HARD_REG_SET reload_reg_used_for_inherit;
4184 /* Records which hard regs are used in any way, either as explicit use or
4185 by being allocated to a pseudo during any point of the current insn. */
4186 static HARD_REG_SET reg_used_in_insn;
4188 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4189 TYPE. MODE is used to indicate how many consecutive regs are
4193 mark_reload_reg_in_use (regno, opnum, type, mode)
4196 enum reload_type type;
4197 enum machine_mode mode;
4199 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4202 for (i = regno; i < nregs + regno; i++)
4207 SET_HARD_REG_BIT (reload_reg_used, i);
4210 case RELOAD_FOR_INPUT_ADDRESS:
4211 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4214 case RELOAD_FOR_INPADDR_ADDRESS:
4215 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4218 case RELOAD_FOR_OUTPUT_ADDRESS:
4219 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4222 case RELOAD_FOR_OUTADDR_ADDRESS:
4223 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4226 case RELOAD_FOR_OPERAND_ADDRESS:
4227 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4230 case RELOAD_FOR_OPADDR_ADDR:
4231 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4234 case RELOAD_FOR_OTHER_ADDRESS:
4235 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4238 case RELOAD_FOR_INPUT:
4239 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4242 case RELOAD_FOR_OUTPUT:
4243 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4246 case RELOAD_FOR_INSN:
4247 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4251 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4255 /* Similarly, but show REGNO is no longer in use for a reload. */
4258 clear_reload_reg_in_use (regno, opnum, type, mode)
4261 enum reload_type type;
4262 enum machine_mode mode;
4264 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4265 unsigned int start_regno, end_regno, r;
4267 /* A complication is that for some reload types, inheritance might
4268 allow multiple reloads of the same types to share a reload register.
4269 We set check_opnum if we have to check only reloads with the same
4270 operand number, and check_any if we have to check all reloads. */
4271 int check_opnum = 0;
4273 HARD_REG_SET *used_in_set;
4278 used_in_set = &reload_reg_used;
4281 case RELOAD_FOR_INPUT_ADDRESS:
4282 used_in_set = &reload_reg_used_in_input_addr[opnum];
4285 case RELOAD_FOR_INPADDR_ADDRESS:
4287 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4290 case RELOAD_FOR_OUTPUT_ADDRESS:
4291 used_in_set = &reload_reg_used_in_output_addr[opnum];
4294 case RELOAD_FOR_OUTADDR_ADDRESS:
4296 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4299 case RELOAD_FOR_OPERAND_ADDRESS:
4300 used_in_set = &reload_reg_used_in_op_addr;
4303 case RELOAD_FOR_OPADDR_ADDR:
4305 used_in_set = &reload_reg_used_in_op_addr_reload;
4308 case RELOAD_FOR_OTHER_ADDRESS:
4309 used_in_set = &reload_reg_used_in_other_addr;
4313 case RELOAD_FOR_INPUT:
4314 used_in_set = &reload_reg_used_in_input[opnum];
4317 case RELOAD_FOR_OUTPUT:
4318 used_in_set = &reload_reg_used_in_output[opnum];
4321 case RELOAD_FOR_INSN:
4322 used_in_set = &reload_reg_used_in_insn;
4327 /* We resolve conflicts with remaining reloads of the same type by
4328 excluding the intervals of reload registers by them from the
4329 interval of freed reload registers. Since we only keep track of
4330 one set of interval bounds, we might have to exclude somewhat
4331 more than what would be necessary if we used a HARD_REG_SET here.
4332 But this should only happen very infrequently, so there should
4333 be no reason to worry about it. */
4335 start_regno = regno;
4336 end_regno = regno + nregs;
4337 if (check_opnum || check_any)
4339 for (i = n_reloads - 1; i >= 0; i--)
4341 if (rld[i].when_needed == type
4342 && (check_any || rld[i].opnum == opnum)
4345 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4346 unsigned int conflict_end
4348 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4350 /* If there is an overlap with the first to-be-freed register,
4351 adjust the interval start. */
4352 if (conflict_start <= start_regno && conflict_end > start_regno)
4353 start_regno = conflict_end;
4354 /* Otherwise, if there is a conflict with one of the other
4355 to-be-freed registers, adjust the interval end. */
4356 if (conflict_start > start_regno && conflict_start < end_regno)
4357 end_regno = conflict_start;
4362 for (r = start_regno; r < end_regno; r++)
4363 CLEAR_HARD_REG_BIT (*used_in_set, r);
4366 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4367 specified by OPNUM and TYPE. */
4370 reload_reg_free_p (regno, opnum, type)
4373 enum reload_type type;
4377 /* In use for a RELOAD_OTHER means it's not available for anything. */
4378 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4379 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4385 /* In use for anything means we can't use it for RELOAD_OTHER. */
4386 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4387 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4388 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4391 for (i = 0; i < reload_n_operands; i++)
4392 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4393 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4394 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4395 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4396 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4397 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4402 case RELOAD_FOR_INPUT:
4403 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4404 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4407 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4410 /* If it is used for some other input, can't use it. */
4411 for (i = 0; i < reload_n_operands; i++)
4412 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4415 /* If it is used in a later operand's address, can't use it. */
4416 for (i = opnum + 1; i < reload_n_operands; i++)
4417 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4418 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4423 case RELOAD_FOR_INPUT_ADDRESS:
4424 /* Can't use a register if it is used for an input address for this
4425 operand or used as an input in an earlier one. */
4426 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4427 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4430 for (i = 0; i < opnum; i++)
4431 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4436 case RELOAD_FOR_INPADDR_ADDRESS:
4437 /* Can't use a register if it is used for an input address
4438 for this operand or used as an input in an earlier
4440 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4443 for (i = 0; i < opnum; i++)
4444 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4449 case RELOAD_FOR_OUTPUT_ADDRESS:
4450 /* Can't use a register if it is used for an output address for this
4451 operand or used as an output in this or a later operand. Note
4452 that multiple output operands are emitted in reverse order, so
4453 the conflicting ones are those with lower indices. */
4454 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4457 for (i = 0; i <= opnum; i++)
4458 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4463 case RELOAD_FOR_OUTADDR_ADDRESS:
4464 /* Can't use a register if it is used for an output address
4465 for this operand or used as an output in this or a
4466 later operand. Note that multiple output operands are
4467 emitted in reverse order, so the conflicting ones are
4468 those with lower indices. */
4469 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4472 for (i = 0; i <= opnum; i++)
4473 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4478 case RELOAD_FOR_OPERAND_ADDRESS:
4479 for (i = 0; i < reload_n_operands; i++)
4480 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4483 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4484 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4486 case RELOAD_FOR_OPADDR_ADDR:
4487 for (i = 0; i < reload_n_operands; i++)
4488 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4491 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4493 case RELOAD_FOR_OUTPUT:
4494 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4495 outputs, or an operand address for this or an earlier output.
4496 Note that multiple output operands are emitted in reverse order,
4497 so the conflicting ones are those with higher indices. */
4498 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4501 for (i = 0; i < reload_n_operands; i++)
4502 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4505 for (i = opnum; i < reload_n_operands; i++)
4506 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4507 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4512 case RELOAD_FOR_INSN:
4513 for (i = 0; i < reload_n_operands; i++)
4514 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4515 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4518 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4519 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4521 case RELOAD_FOR_OTHER_ADDRESS:
4522 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4527 /* Return 1 if the value in reload reg REGNO, as used by a reload
4528 needed for the part of the insn specified by OPNUM and TYPE,
4529 is still available in REGNO at the end of the insn.
4531 We can assume that the reload reg was already tested for availability
4532 at the time it is needed, and we should not check this again,
4533 in case the reg has already been marked in use. */
4536 reload_reg_reaches_end_p (regno, opnum, type)
4539 enum reload_type type;
4546 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4547 its value must reach the end. */
4550 /* If this use is for part of the insn,
4551 its value reaches if no subsequent part uses the same register.
4552 Just like the above function, don't try to do this with lots
4555 case RELOAD_FOR_OTHER_ADDRESS:
4556 /* Here we check for everything else, since these don't conflict
4557 with anything else and everything comes later. */
4559 for (i = 0; i < reload_n_operands; i++)
4560 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4561 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4562 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4563 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4564 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4565 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4568 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4569 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4570 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4572 case RELOAD_FOR_INPUT_ADDRESS:
4573 case RELOAD_FOR_INPADDR_ADDRESS:
4574 /* Similar, except that we check only for this and subsequent inputs
4575 and the address of only subsequent inputs and we do not need
4576 to check for RELOAD_OTHER objects since they are known not to
4579 for (i = opnum; i < reload_n_operands; i++)
4580 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4583 for (i = opnum + 1; i < reload_n_operands; i++)
4584 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4585 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4588 for (i = 0; i < reload_n_operands; i++)
4589 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4590 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4591 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4594 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4597 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4598 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4599 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4601 case RELOAD_FOR_INPUT:
4602 /* Similar to input address, except we start at the next operand for
4603 both input and input address and we do not check for
4604 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4607 for (i = opnum + 1; i < reload_n_operands; i++)
4608 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4609 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4610 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4613 /* ... fall through ... */
4615 case RELOAD_FOR_OPERAND_ADDRESS:
4616 /* Check outputs and their addresses. */
4618 for (i = 0; i < reload_n_operands; i++)
4619 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4620 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4621 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4624 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4626 case RELOAD_FOR_OPADDR_ADDR:
4627 for (i = 0; i < reload_n_operands; i++)
4628 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4629 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4630 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4633 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4634 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4635 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4637 case RELOAD_FOR_INSN:
4638 /* These conflict with other outputs with RELOAD_OTHER. So
4639 we need only check for output addresses. */
4641 opnum = reload_n_operands;
4643 /* ... fall through ... */
4645 case RELOAD_FOR_OUTPUT:
4646 case RELOAD_FOR_OUTPUT_ADDRESS:
4647 case RELOAD_FOR_OUTADDR_ADDRESS:
4648 /* We already know these can't conflict with a later output. So the
4649 only thing to check are later output addresses.
4650 Note that multiple output operands are emitted in reverse order,
4651 so the conflicting ones are those with lower indices. */
4652 for (i = 0; i < opnum; i++)
4653 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4654 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4663 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4666 This function uses the same algorithm as reload_reg_free_p above. */
4669 reloads_conflict (r1, r2)
4672 enum reload_type r1_type = rld[r1].when_needed;
4673 enum reload_type r2_type = rld[r2].when_needed;
4674 int r1_opnum = rld[r1].opnum;
4675 int r2_opnum = rld[r2].opnum;
4677 /* RELOAD_OTHER conflicts with everything. */
4678 if (r2_type == RELOAD_OTHER)
4681 /* Otherwise, check conflicts differently for each type. */
4685 case RELOAD_FOR_INPUT:
4686 return (r2_type == RELOAD_FOR_INSN
4687 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4688 || r2_type == RELOAD_FOR_OPADDR_ADDR
4689 || r2_type == RELOAD_FOR_INPUT
4690 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4691 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4692 && r2_opnum > r1_opnum));
4694 case RELOAD_FOR_INPUT_ADDRESS:
4695 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4696 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4698 case RELOAD_FOR_INPADDR_ADDRESS:
4699 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4700 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4702 case RELOAD_FOR_OUTPUT_ADDRESS:
4703 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4704 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4706 case RELOAD_FOR_OUTADDR_ADDRESS:
4707 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4708 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4710 case RELOAD_FOR_OPERAND_ADDRESS:
4711 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4712 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4714 case RELOAD_FOR_OPADDR_ADDR:
4715 return (r2_type == RELOAD_FOR_INPUT
4716 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4718 case RELOAD_FOR_OUTPUT:
4719 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4720 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4721 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4722 && r2_opnum >= r1_opnum));
4724 case RELOAD_FOR_INSN:
4725 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4726 || r2_type == RELOAD_FOR_INSN
4727 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4729 case RELOAD_FOR_OTHER_ADDRESS:
4730 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4740 /* Indexed by reload number, 1 if incoming value
4741 inherited from previous insns. */
4742 char reload_inherited[MAX_RELOADS];
4744 /* For an inherited reload, this is the insn the reload was inherited from,
4745 if we know it. Otherwise, this is 0. */
4746 rtx reload_inheritance_insn[MAX_RELOADS];
4748 /* If nonzero, this is a place to get the value of the reload,
4749 rather than using reload_in. */
4750 rtx reload_override_in[MAX_RELOADS];
4752 /* For each reload, the hard register number of the register used,
4753 or -1 if we did not need a register for this reload. */
4754 int reload_spill_index[MAX_RELOADS];
4756 /* Subroutine of free_for_value_p, used to check a single register.
4757 START_REGNO is the starting regno of the full reload register
4758 (possibly comprising multiple hard registers) that we are considering. */
4761 reload_reg_free_for_value_p (start_regno, regno, opnum, type, value, out,
4762 reloadnum, ignore_address_reloads)
4763 int start_regno, regno;
4765 enum reload_type type;
4768 int ignore_address_reloads;
4771 /* Set if we see an input reload that must not share its reload register
4772 with any new earlyclobber, but might otherwise share the reload
4773 register with an output or input-output reload. */
4774 int check_earlyclobber = 0;
4778 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4781 if (out == const0_rtx)
4787 /* We use some pseudo 'time' value to check if the lifetimes of the
4788 new register use would overlap with the one of a previous reload
4789 that is not read-only or uses a different value.
4790 The 'time' used doesn't have to be linear in any shape or form, just
4792 Some reload types use different 'buckets' for each operand.
4793 So there are MAX_RECOG_OPERANDS different time values for each
4795 We compute TIME1 as the time when the register for the prospective
4796 new reload ceases to be live, and TIME2 for each existing
4797 reload as the time when that the reload register of that reload
4799 Where there is little to be gained by exact lifetime calculations,
4800 we just make conservative assumptions, i.e. a longer lifetime;
4801 this is done in the 'default:' cases. */
4804 case RELOAD_FOR_OTHER_ADDRESS:
4805 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4806 time1 = copy ? 0 : 1;
4809 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4811 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4812 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4813 respectively, to the time values for these, we get distinct time
4814 values. To get distinct time values for each operand, we have to
4815 multiply opnum by at least three. We round that up to four because
4816 multiply by four is often cheaper. */
4817 case RELOAD_FOR_INPADDR_ADDRESS:
4818 time1 = opnum * 4 + 2;
4820 case RELOAD_FOR_INPUT_ADDRESS:
4821 time1 = opnum * 4 + 3;
4823 case RELOAD_FOR_INPUT:
4824 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4825 executes (inclusive). */
4826 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4828 case RELOAD_FOR_OPADDR_ADDR:
4830 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4831 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4833 case RELOAD_FOR_OPERAND_ADDRESS:
4834 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4836 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4838 case RELOAD_FOR_OUTADDR_ADDRESS:
4839 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4841 case RELOAD_FOR_OUTPUT_ADDRESS:
4842 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4845 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4848 for (i = 0; i < n_reloads; i++)
4850 rtx reg = rld[i].reg_rtx;
4851 if (reg && GET_CODE (reg) == REG
4852 && ((unsigned) regno - true_regnum (reg)
4853 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned) 1)
4856 rtx other_input = rld[i].in;
4858 /* If the other reload loads the same input value, that
4859 will not cause a conflict only if it's loading it into
4860 the same register. */
4861 if (true_regnum (reg) != start_regno)
4862 other_input = NULL_RTX;
4863 if (! other_input || ! rtx_equal_p (other_input, value)
4864 || rld[i].out || out)
4867 switch (rld[i].when_needed)
4869 case RELOAD_FOR_OTHER_ADDRESS:
4872 case RELOAD_FOR_INPADDR_ADDRESS:
4873 /* find_reloads makes sure that a
4874 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4875 by at most one - the first -
4876 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4877 address reload is inherited, the address address reload
4878 goes away, so we can ignore this conflict. */
4879 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4880 && ignore_address_reloads
4881 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4882 Then the address address is still needed to store
4883 back the new address. */
4884 && ! rld[reloadnum].out)
4886 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4887 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4889 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4890 && ignore_address_reloads
4891 /* Unless we are reloading an auto_inc expression. */
4892 && ! rld[reloadnum].out)
4894 time2 = rld[i].opnum * 4 + 2;
4896 case RELOAD_FOR_INPUT_ADDRESS:
4897 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4898 && ignore_address_reloads
4899 && ! rld[reloadnum].out)
4901 time2 = rld[i].opnum * 4 + 3;
4903 case RELOAD_FOR_INPUT:
4904 time2 = rld[i].opnum * 4 + 4;
4905 check_earlyclobber = 1;
4907 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4908 == MAX_RECOG_OPERAND * 4 */
4909 case RELOAD_FOR_OPADDR_ADDR:
4910 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4911 && ignore_address_reloads
4912 && ! rld[reloadnum].out)
4914 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4916 case RELOAD_FOR_OPERAND_ADDRESS:
4917 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4918 check_earlyclobber = 1;
4920 case RELOAD_FOR_INSN:
4921 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4923 case RELOAD_FOR_OUTPUT:
4924 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4925 instruction is executed. */
4926 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4928 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4929 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4931 case RELOAD_FOR_OUTADDR_ADDRESS:
4932 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4933 && ignore_address_reloads
4934 && ! rld[reloadnum].out)
4936 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4938 case RELOAD_FOR_OUTPUT_ADDRESS:
4939 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4942 /* If there is no conflict in the input part, handle this
4943 like an output reload. */
4944 if (! rld[i].in || rtx_equal_p (other_input, value))
4946 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4947 /* Earlyclobbered outputs must conflict with inputs. */
4948 if (earlyclobber_operand_p (rld[i].out))
4949 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4954 /* RELOAD_OTHER might be live beyond instruction execution,
4955 but this is not obvious when we set time2 = 1. So check
4956 here if there might be a problem with the new reload
4957 clobbering the register used by the RELOAD_OTHER. */
4965 && (! rld[i].in || rld[i].out
4966 || ! rtx_equal_p (other_input, value)))
4967 || (out && rld[reloadnum].out_reg
4968 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4974 /* Earlyclobbered outputs must conflict with inputs. */
4975 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4981 /* Return 1 if the value in reload reg REGNO, as used by a reload
4982 needed for the part of the insn specified by OPNUM and TYPE,
4983 may be used to load VALUE into it.
4985 MODE is the mode in which the register is used, this is needed to
4986 determine how many hard regs to test.
4988 Other read-only reloads with the same value do not conflict
4989 unless OUT is nonzero and these other reloads have to live while
4990 output reloads live.
4991 If OUT is CONST0_RTX, this is a special case: it means that the
4992 test should not be for using register REGNO as reload register, but
4993 for copying from register REGNO into the reload register.
4995 RELOADNUM is the number of the reload we want to load this value for;
4996 a reload does not conflict with itself.
4998 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4999 reloads that load an address for the very reload we are considering.
5001 The caller has to make sure that there is no conflict with the return
5005 free_for_value_p (regno, mode, opnum, type, value, out, reloadnum,
5006 ignore_address_reloads)
5008 enum machine_mode mode;
5010 enum reload_type type;
5013 int ignore_address_reloads;
5015 int nregs = HARD_REGNO_NREGS (regno, mode);
5017 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5018 value, out, reloadnum,
5019 ignore_address_reloads))
5024 /* Determine whether the reload reg X overlaps any rtx'es used for
5025 overriding inheritance. Return nonzero if so. */
5028 conflicts_with_override (x)
5032 for (i = 0; i < n_reloads; i++)
5033 if (reload_override_in[i]
5034 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5039 /* Give an error message saying we failed to find a reload for INSN,
5040 and clear out reload R. */
5042 failed_reload (insn, r)
5046 if (asm_noperands (PATTERN (insn)) < 0)
5047 /* It's the compiler's fault. */
5048 fatal_insn ("could not find a spill register", insn);
5050 /* It's the user's fault; the operand's mode and constraint
5051 don't match. Disable this reload so we don't crash in final. */
5052 error_for_asm (insn,
5053 "`asm' operand constraint incompatible with operand size");
5057 rld[r].optional = 1;
5058 rld[r].secondary_p = 1;
5061 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5062 for reload R. If it's valid, get an rtx for it. Return nonzero if
5065 set_reload_reg (i, r)
5069 rtx reg = spill_reg_rtx[i];
5071 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5072 spill_reg_rtx[i] = reg
5073 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5075 regno = true_regnum (reg);
5077 /* Detect when the reload reg can't hold the reload mode.
5078 This used to be one `if', but Sequent compiler can't handle that. */
5079 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5081 enum machine_mode test_mode = VOIDmode;
5083 test_mode = GET_MODE (rld[r].in);
5084 /* If rld[r].in has VOIDmode, it means we will load it
5085 in whatever mode the reload reg has: to wit, rld[r].mode.
5086 We have already tested that for validity. */
5087 /* Aside from that, we need to test that the expressions
5088 to reload from or into have modes which are valid for this
5089 reload register. Otherwise the reload insns would be invalid. */
5090 if (! (rld[r].in != 0 && test_mode != VOIDmode
5091 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5092 if (! (rld[r].out != 0
5093 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5095 /* The reg is OK. */
5098 /* Mark as in use for this insn the reload regs we use
5100 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5101 rld[r].when_needed, rld[r].mode);
5103 rld[r].reg_rtx = reg;
5104 reload_spill_index[r] = spill_regs[i];
5111 /* Find a spill register to use as a reload register for reload R.
5112 LAST_RELOAD is nonzero if this is the last reload for the insn being
5115 Set rld[R].reg_rtx to the register allocated.
5117 We return 1 if successful, or 0 if we couldn't find a spill reg and
5118 we didn't change anything. */
5121 allocate_reload_reg (chain, r, last_reload)
5122 struct insn_chain *chain ATTRIBUTE_UNUSED;
5128 /* If we put this reload ahead, thinking it is a group,
5129 then insist on finding a group. Otherwise we can grab a
5130 reg that some other reload needs.
5131 (That can happen when we have a 68000 DATA_OR_FP_REG
5132 which is a group of data regs or one fp reg.)
5133 We need not be so restrictive if there are no more reloads
5136 ??? Really it would be nicer to have smarter handling
5137 for that kind of reg class, where a problem like this is normal.
5138 Perhaps those classes should be avoided for reloading
5139 by use of more alternatives. */
5141 int force_group = rld[r].nregs > 1 && ! last_reload;
5143 /* If we want a single register and haven't yet found one,
5144 take any reg in the right class and not in use.
5145 If we want a consecutive group, here is where we look for it.
5147 We use two passes so we can first look for reload regs to
5148 reuse, which are already in use for other reloads in this insn,
5149 and only then use additional registers.
5150 I think that maximizing reuse is needed to make sure we don't
5151 run out of reload regs. Suppose we have three reloads, and
5152 reloads A and B can share regs. These need two regs.
5153 Suppose A and B are given different regs.
5154 That leaves none for C. */
5155 for (pass = 0; pass < 2; pass++)
5157 /* I is the index in spill_regs.
5158 We advance it round-robin between insns to use all spill regs
5159 equally, so that inherited reloads have a chance
5160 of leapfrogging each other. */
5164 for (count = 0; count < n_spills; count++)
5166 int class = (int) rld[r].class;
5172 regnum = spill_regs[i];
5174 if ((reload_reg_free_p (regnum, rld[r].opnum,
5177 /* We check reload_reg_used to make sure we
5178 don't clobber the return register. */
5179 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5180 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5181 rld[r].when_needed, rld[r].in,
5183 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5184 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5185 /* Look first for regs to share, then for unshared. But
5186 don't share regs used for inherited reloads; they are
5187 the ones we want to preserve. */
5189 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5191 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5194 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5195 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5196 (on 68000) got us two FP regs. If NR is 1,
5197 we would reject both of them. */
5200 /* If we need only one reg, we have already won. */
5203 /* But reject a single reg if we demand a group. */
5208 /* Otherwise check that as many consecutive regs as we need
5209 are available here. */
5212 int regno = regnum + nr - 1;
5213 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5214 && spill_reg_order[regno] >= 0
5215 && reload_reg_free_p (regno, rld[r].opnum,
5216 rld[r].when_needed)))
5225 /* If we found something on pass 1, omit pass 2. */
5226 if (count < n_spills)
5230 /* We should have found a spill register by now. */
5231 if (count >= n_spills)
5234 /* I is the index in SPILL_REG_RTX of the reload register we are to
5235 allocate. Get an rtx for it and find its register number. */
5237 return set_reload_reg (i, r);
5240 /* Initialize all the tables needed to allocate reload registers.
5241 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5242 is the array we use to restore the reg_rtx field for every reload. */
5245 choose_reload_regs_init (chain, save_reload_reg_rtx)
5246 struct insn_chain *chain;
5247 rtx *save_reload_reg_rtx;
5251 for (i = 0; i < n_reloads; i++)
5252 rld[i].reg_rtx = save_reload_reg_rtx[i];
5254 memset (reload_inherited, 0, MAX_RELOADS);
5255 memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5256 memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5258 CLEAR_HARD_REG_SET (reload_reg_used);
5259 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5260 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5261 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5262 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5263 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5265 CLEAR_HARD_REG_SET (reg_used_in_insn);
5268 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5269 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5270 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5271 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5272 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5273 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5276 for (i = 0; i < reload_n_operands; i++)
5278 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5279 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5280 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5281 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5282 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5283 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5286 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5288 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5290 for (i = 0; i < n_reloads; i++)
5291 /* If we have already decided to use a certain register,
5292 don't use it in another way. */
5294 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5295 rld[i].when_needed, rld[i].mode);
5298 /* Assign hard reg targets for the pseudo-registers we must reload
5299 into hard regs for this insn.
5300 Also output the instructions to copy them in and out of the hard regs.
5302 For machines with register classes, we are responsible for
5303 finding a reload reg in the proper class. */
5306 choose_reload_regs (chain)
5307 struct insn_chain *chain;
5309 rtx insn = chain->insn;
5311 unsigned int max_group_size = 1;
5312 enum reg_class group_class = NO_REGS;
5313 int pass, win, inheritance;
5315 rtx save_reload_reg_rtx[MAX_RELOADS];
5317 /* In order to be certain of getting the registers we need,
5318 we must sort the reloads into order of increasing register class.
5319 Then our grabbing of reload registers will parallel the process
5320 that provided the reload registers.
5322 Also note whether any of the reloads wants a consecutive group of regs.
5323 If so, record the maximum size of the group desired and what
5324 register class contains all the groups needed by this insn. */
5326 for (j = 0; j < n_reloads; j++)
5328 reload_order[j] = j;
5329 reload_spill_index[j] = -1;
5331 if (rld[j].nregs > 1)
5333 max_group_size = MAX (rld[j].nregs, max_group_size);
5335 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5338 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5342 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5344 /* If -O, try first with inheritance, then turning it off.
5345 If not -O, don't do inheritance.
5346 Using inheritance when not optimizing leads to paradoxes
5347 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5348 because one side of the comparison might be inherited. */
5350 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5352 choose_reload_regs_init (chain, save_reload_reg_rtx);
5354 /* Process the reloads in order of preference just found.
5355 Beyond this point, subregs can be found in reload_reg_rtx.
5357 This used to look for an existing reloaded home for all of the
5358 reloads, and only then perform any new reloads. But that could lose
5359 if the reloads were done out of reg-class order because a later
5360 reload with a looser constraint might have an old home in a register
5361 needed by an earlier reload with a tighter constraint.
5363 To solve this, we make two passes over the reloads, in the order
5364 described above. In the first pass we try to inherit a reload
5365 from a previous insn. If there is a later reload that needs a
5366 class that is a proper subset of the class being processed, we must
5367 also allocate a spill register during the first pass.
5369 Then make a second pass over the reloads to allocate any reloads
5370 that haven't been given registers yet. */
5372 for (j = 0; j < n_reloads; j++)
5374 int r = reload_order[j];
5375 rtx search_equiv = NULL_RTX;
5377 /* Ignore reloads that got marked inoperative. */
5378 if (rld[r].out == 0 && rld[r].in == 0
5379 && ! rld[r].secondary_p)
5382 /* If find_reloads chose to use reload_in or reload_out as a reload
5383 register, we don't need to chose one. Otherwise, try even if it
5384 found one since we might save an insn if we find the value lying
5386 Try also when reload_in is a pseudo without a hard reg. */
5387 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5388 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5389 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5390 && GET_CODE (rld[r].in) != MEM
5391 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5394 #if 0 /* No longer needed for correct operation.
5395 It might give better code, or might not; worth an experiment? */
5396 /* If this is an optional reload, we can't inherit from earlier insns
5397 until we are sure that any non-optional reloads have been allocated.
5398 The following code takes advantage of the fact that optional reloads
5399 are at the end of reload_order. */
5400 if (rld[r].optional != 0)
5401 for (i = 0; i < j; i++)
5402 if ((rld[reload_order[i]].out != 0
5403 || rld[reload_order[i]].in != 0
5404 || rld[reload_order[i]].secondary_p)
5405 && ! rld[reload_order[i]].optional
5406 && rld[reload_order[i]].reg_rtx == 0)
5407 allocate_reload_reg (chain, reload_order[i], 0);
5410 /* First see if this pseudo is already available as reloaded
5411 for a previous insn. We cannot try to inherit for reloads
5412 that are smaller than the maximum number of registers needed
5413 for groups unless the register we would allocate cannot be used
5416 We could check here to see if this is a secondary reload for
5417 an object that is already in a register of the desired class.
5418 This would avoid the need for the secondary reload register.
5419 But this is complex because we can't easily determine what
5420 objects might want to be loaded via this reload. So let a
5421 register be allocated here. In `emit_reload_insns' we suppress
5422 one of the loads in the case described above. */
5428 enum machine_mode mode = VOIDmode;
5432 else if (GET_CODE (rld[r].in) == REG)
5434 regno = REGNO (rld[r].in);
5435 mode = GET_MODE (rld[r].in);
5437 else if (GET_CODE (rld[r].in_reg) == REG)
5439 regno = REGNO (rld[r].in_reg);
5440 mode = GET_MODE (rld[r].in_reg);
5442 else if (GET_CODE (rld[r].in_reg) == SUBREG
5443 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5445 byte = SUBREG_BYTE (rld[r].in_reg);
5446 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5447 if (regno < FIRST_PSEUDO_REGISTER)
5448 regno = subreg_regno (rld[r].in_reg);
5449 mode = GET_MODE (rld[r].in_reg);
5452 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5453 || GET_CODE (rld[r].in_reg) == PRE_DEC
5454 || GET_CODE (rld[r].in_reg) == POST_INC
5455 || GET_CODE (rld[r].in_reg) == POST_DEC)
5456 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5458 regno = REGNO (XEXP (rld[r].in_reg, 0));
5459 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5460 rld[r].out = rld[r].in;
5464 /* This won't work, since REGNO can be a pseudo reg number.
5465 Also, it takes much more hair to keep track of all the things
5466 that can invalidate an inherited reload of part of a pseudoreg. */
5467 else if (GET_CODE (rld[r].in) == SUBREG
5468 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5469 regno = subreg_regno (rld[r].in);
5472 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5474 enum reg_class class = rld[r].class, last_class;
5475 rtx last_reg = reg_last_reload_reg[regno];
5476 enum machine_mode need_mode;
5478 i = REGNO (last_reg);
5479 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5480 last_class = REGNO_REG_CLASS (i);
5486 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5487 GET_MODE_CLASS (mode));
5490 #ifdef CANNOT_CHANGE_MODE_CLASS
5491 (!REG_CANNOT_CHANGE_MODE_P (i, GET_MODE (last_reg),
5495 (GET_MODE_SIZE (GET_MODE (last_reg))
5496 >= GET_MODE_SIZE (need_mode))
5497 #ifdef CANNOT_CHANGE_MODE_CLASS
5500 && reg_reloaded_contents[i] == regno
5501 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5502 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5503 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5504 /* Even if we can't use this register as a reload
5505 register, we might use it for reload_override_in,
5506 if copying it to the desired class is cheap
5508 || ((REGISTER_MOVE_COST (mode, last_class, class)
5509 < MEMORY_MOVE_COST (mode, class, 1))
5510 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5511 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5515 #ifdef SECONDARY_MEMORY_NEEDED
5516 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5521 && (rld[r].nregs == max_group_size
5522 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5524 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5525 rld[r].when_needed, rld[r].in,
5528 /* If a group is needed, verify that all the subsequent
5529 registers still have their values intact. */
5530 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5533 for (k = 1; k < nr; k++)
5534 if (reg_reloaded_contents[i + k] != regno
5535 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5543 last_reg = (GET_MODE (last_reg) == mode
5544 ? last_reg : gen_rtx_REG (mode, i));
5547 for (k = 0; k < nr; k++)
5548 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5551 /* We found a register that contains the
5552 value we need. If this register is the
5553 same as an `earlyclobber' operand of the
5554 current insn, just mark it as a place to
5555 reload from since we can't use it as the
5556 reload register itself. */
5558 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5559 if (reg_overlap_mentioned_for_reload_p
5560 (reg_last_reload_reg[regno],
5561 reload_earlyclobbers[i1]))
5564 if (i1 != n_earlyclobbers
5565 || ! (free_for_value_p (i, rld[r].mode,
5567 rld[r].when_needed, rld[r].in,
5569 /* Don't use it if we'd clobber a pseudo reg. */
5570 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5572 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5573 /* Don't clobber the frame pointer. */
5574 || (i == HARD_FRAME_POINTER_REGNUM
5575 && frame_pointer_needed
5577 /* Don't really use the inherited spill reg
5578 if we need it wider than we've got it. */
5579 || (GET_MODE_SIZE (rld[r].mode)
5580 > GET_MODE_SIZE (mode))
5583 /* If find_reloads chose reload_out as reload
5584 register, stay with it - that leaves the
5585 inherited register for subsequent reloads. */
5586 || (rld[r].out && rld[r].reg_rtx
5587 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5589 if (! rld[r].optional)
5591 reload_override_in[r] = last_reg;
5592 reload_inheritance_insn[r]
5593 = reg_reloaded_insn[i];
5599 /* We can use this as a reload reg. */
5600 /* Mark the register as in use for this part of
5602 mark_reload_reg_in_use (i,
5606 rld[r].reg_rtx = last_reg;
5607 reload_inherited[r] = 1;
5608 reload_inheritance_insn[r]
5609 = reg_reloaded_insn[i];
5610 reload_spill_index[r] = i;
5611 for (k = 0; k < nr; k++)
5612 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5620 /* Here's another way to see if the value is already lying around. */
5623 && ! reload_inherited[r]
5625 && (CONSTANT_P (rld[r].in)
5626 || GET_CODE (rld[r].in) == PLUS
5627 || GET_CODE (rld[r].in) == REG
5628 || GET_CODE (rld[r].in) == MEM)
5629 && (rld[r].nregs == max_group_size
5630 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5631 search_equiv = rld[r].in;
5632 /* If this is an output reload from a simple move insn, look
5633 if an equivalence for the input is available. */
5634 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5636 rtx set = single_set (insn);
5639 && rtx_equal_p (rld[r].out, SET_DEST (set))
5640 && CONSTANT_P (SET_SRC (set)))
5641 search_equiv = SET_SRC (set);
5647 = find_equiv_reg (search_equiv, insn, rld[r].class,
5648 -1, NULL, 0, rld[r].mode);
5653 if (GET_CODE (equiv) == REG)
5654 regno = REGNO (equiv);
5655 else if (GET_CODE (equiv) == SUBREG)
5657 /* This must be a SUBREG of a hard register.
5658 Make a new REG since this might be used in an
5659 address and not all machines support SUBREGs
5661 regno = subreg_regno (equiv);
5662 equiv = gen_rtx_REG (rld[r].mode, regno);
5668 /* If we found a spill reg, reject it unless it is free
5669 and of the desired class. */
5673 int bad_for_class = 0;
5674 int max_regno = regno + rld[r].nregs;
5676 for (i = regno; i < max_regno; i++)
5678 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5680 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5685 && ! free_for_value_p (regno, rld[r].mode,
5686 rld[r].opnum, rld[r].when_needed,
5687 rld[r].in, rld[r].out, r, 1))
5692 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5695 /* We found a register that contains the value we need.
5696 If this register is the same as an `earlyclobber' operand
5697 of the current insn, just mark it as a place to reload from
5698 since we can't use it as the reload register itself. */
5701 for (i = 0; i < n_earlyclobbers; i++)
5702 if (reg_overlap_mentioned_for_reload_p (equiv,
5703 reload_earlyclobbers[i]))
5705 if (! rld[r].optional)
5706 reload_override_in[r] = equiv;
5711 /* If the equiv register we have found is explicitly clobbered
5712 in the current insn, it depends on the reload type if we
5713 can use it, use it for reload_override_in, or not at all.
5714 In particular, we then can't use EQUIV for a
5715 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5719 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5720 switch (rld[r].when_needed)
5722 case RELOAD_FOR_OTHER_ADDRESS:
5723 case RELOAD_FOR_INPADDR_ADDRESS:
5724 case RELOAD_FOR_INPUT_ADDRESS:
5725 case RELOAD_FOR_OPADDR_ADDR:
5728 case RELOAD_FOR_INPUT:
5729 case RELOAD_FOR_OPERAND_ADDRESS:
5730 if (! rld[r].optional)
5731 reload_override_in[r] = equiv;
5737 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5738 switch (rld[r].when_needed)
5740 case RELOAD_FOR_OTHER_ADDRESS:
5741 case RELOAD_FOR_INPADDR_ADDRESS:
5742 case RELOAD_FOR_INPUT_ADDRESS:
5743 case RELOAD_FOR_OPADDR_ADDR:
5744 case RELOAD_FOR_OPERAND_ADDRESS:
5745 case RELOAD_FOR_INPUT:
5748 if (! rld[r].optional)
5749 reload_override_in[r] = equiv;
5757 /* If we found an equivalent reg, say no code need be generated
5758 to load it, and use it as our reload reg. */
5760 && (regno != HARD_FRAME_POINTER_REGNUM
5761 || !frame_pointer_needed))
5763 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5765 rld[r].reg_rtx = equiv;
5766 reload_inherited[r] = 1;
5768 /* If reg_reloaded_valid is not set for this register,
5769 there might be a stale spill_reg_store lying around.
5770 We must clear it, since otherwise emit_reload_insns
5771 might delete the store. */
5772 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5773 spill_reg_store[regno] = NULL_RTX;
5774 /* If any of the hard registers in EQUIV are spill
5775 registers, mark them as in use for this insn. */
5776 for (k = 0; k < nr; k++)
5778 i = spill_reg_order[regno + k];
5781 mark_reload_reg_in_use (regno, rld[r].opnum,
5784 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5791 /* If we found a register to use already, or if this is an optional
5792 reload, we are done. */
5793 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5797 /* No longer needed for correct operation. Might or might
5798 not give better code on the average. Want to experiment? */
5800 /* See if there is a later reload that has a class different from our
5801 class that intersects our class or that requires less register
5802 than our reload. If so, we must allocate a register to this
5803 reload now, since that reload might inherit a previous reload
5804 and take the only available register in our class. Don't do this
5805 for optional reloads since they will force all previous reloads
5806 to be allocated. Also don't do this for reloads that have been
5809 for (i = j + 1; i < n_reloads; i++)
5811 int s = reload_order[i];
5813 if ((rld[s].in == 0 && rld[s].out == 0
5814 && ! rld[s].secondary_p)
5818 if ((rld[s].class != rld[r].class
5819 && reg_classes_intersect_p (rld[r].class,
5821 || rld[s].nregs < rld[r].nregs)
5828 allocate_reload_reg (chain, r, j == n_reloads - 1);
5832 /* Now allocate reload registers for anything non-optional that
5833 didn't get one yet. */
5834 for (j = 0; j < n_reloads; j++)
5836 int r = reload_order[j];
5838 /* Ignore reloads that got marked inoperative. */
5839 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5842 /* Skip reloads that already have a register allocated or are
5844 if (rld[r].reg_rtx != 0 || rld[r].optional)
5847 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5851 /* If that loop got all the way, we have won. */
5858 /* Loop around and try without any inheritance. */
5863 /* First undo everything done by the failed attempt
5864 to allocate with inheritance. */
5865 choose_reload_regs_init (chain, save_reload_reg_rtx);
5867 /* Some sanity tests to verify that the reloads found in the first
5868 pass are identical to the ones we have now. */
5869 if (chain->n_reloads != n_reloads)
5872 for (i = 0; i < n_reloads; i++)
5874 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5876 if (chain->rld[i].when_needed != rld[i].when_needed)
5878 for (j = 0; j < n_spills; j++)
5879 if (spill_regs[j] == chain->rld[i].regno)
5880 if (! set_reload_reg (j, i))
5881 failed_reload (chain->insn, i);
5885 /* If we thought we could inherit a reload, because it seemed that
5886 nothing else wanted the same reload register earlier in the insn,
5887 verify that assumption, now that all reloads have been assigned.
5888 Likewise for reloads where reload_override_in has been set. */
5890 /* If doing expensive optimizations, do one preliminary pass that doesn't
5891 cancel any inheritance, but removes reloads that have been needed only
5892 for reloads that we know can be inherited. */
5893 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5895 for (j = 0; j < n_reloads; j++)
5897 int r = reload_order[j];
5899 if (reload_inherited[r] && rld[r].reg_rtx)
5900 check_reg = rld[r].reg_rtx;
5901 else if (reload_override_in[r]
5902 && (GET_CODE (reload_override_in[r]) == REG
5903 || GET_CODE (reload_override_in[r]) == SUBREG))
5904 check_reg = reload_override_in[r];
5907 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5908 rld[r].opnum, rld[r].when_needed, rld[r].in,
5909 (reload_inherited[r]
5910 ? rld[r].out : const0_rtx),
5915 reload_inherited[r] = 0;
5916 reload_override_in[r] = 0;
5918 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5919 reload_override_in, then we do not need its related
5920 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5921 likewise for other reload types.
5922 We handle this by removing a reload when its only replacement
5923 is mentioned in reload_in of the reload we are going to inherit.
5924 A special case are auto_inc expressions; even if the input is
5925 inherited, we still need the address for the output. We can
5926 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5927 If we succeeded removing some reload and we are doing a preliminary
5928 pass just to remove such reloads, make another pass, since the
5929 removal of one reload might allow us to inherit another one. */
5931 && rld[r].out != rld[r].in
5932 && remove_address_replacements (rld[r].in) && pass)
5937 /* Now that reload_override_in is known valid,
5938 actually override reload_in. */
5939 for (j = 0; j < n_reloads; j++)
5940 if (reload_override_in[j])
5941 rld[j].in = reload_override_in[j];
5943 /* If this reload won't be done because it has been canceled or is
5944 optional and not inherited, clear reload_reg_rtx so other
5945 routines (such as subst_reloads) don't get confused. */
5946 for (j = 0; j < n_reloads; j++)
5947 if (rld[j].reg_rtx != 0
5948 && ((rld[j].optional && ! reload_inherited[j])
5949 || (rld[j].in == 0 && rld[j].out == 0
5950 && ! rld[j].secondary_p)))
5952 int regno = true_regnum (rld[j].reg_rtx);
5954 if (spill_reg_order[regno] >= 0)
5955 clear_reload_reg_in_use (regno, rld[j].opnum,
5956 rld[j].when_needed, rld[j].mode);
5958 reload_spill_index[j] = -1;
5961 /* Record which pseudos and which spill regs have output reloads. */
5962 for (j = 0; j < n_reloads; j++)
5964 int r = reload_order[j];
5966 i = reload_spill_index[r];
5968 /* I is nonneg if this reload uses a register.
5969 If rld[r].reg_rtx is 0, this is an optional reload
5970 that we opted to ignore. */
5971 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5972 && rld[r].reg_rtx != 0)
5974 int nregno = REGNO (rld[r].out_reg);
5977 if (nregno < FIRST_PSEUDO_REGISTER)
5978 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5981 reg_has_output_reload[nregno + nr] = 1;
5985 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5987 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5990 if (rld[r].when_needed != RELOAD_OTHER
5991 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5992 && rld[r].when_needed != RELOAD_FOR_INSN)
5998 /* Deallocate the reload register for reload R. This is called from
5999 remove_address_replacements. */
6002 deallocate_reload_reg (r)
6007 if (! rld[r].reg_rtx)
6009 regno = true_regnum (rld[r].reg_rtx);
6011 if (spill_reg_order[regno] >= 0)
6012 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6014 reload_spill_index[r] = -1;
6017 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6018 reloads of the same item for fear that we might not have enough reload
6019 registers. However, normally they will get the same reload register
6020 and hence actually need not be loaded twice.
6022 Here we check for the most common case of this phenomenon: when we have
6023 a number of reloads for the same object, each of which were allocated
6024 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6025 reload, and is not modified in the insn itself. If we find such,
6026 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6027 This will not increase the number of spill registers needed and will
6028 prevent redundant code. */
6031 merge_assigned_reloads (insn)
6036 /* Scan all the reloads looking for ones that only load values and
6037 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6038 assigned and not modified by INSN. */
6040 for (i = 0; i < n_reloads; i++)
6042 int conflicting_input = 0;
6043 int max_input_address_opnum = -1;
6044 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6046 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6047 || rld[i].out != 0 || rld[i].reg_rtx == 0
6048 || reg_set_p (rld[i].reg_rtx, insn))
6051 /* Look at all other reloads. Ensure that the only use of this
6052 reload_reg_rtx is in a reload that just loads the same value
6053 as we do. Note that any secondary reloads must be of the identical
6054 class since the values, modes, and result registers are the
6055 same, so we need not do anything with any secondary reloads. */
6057 for (j = 0; j < n_reloads; j++)
6059 if (i == j || rld[j].reg_rtx == 0
6060 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6064 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6065 && rld[j].opnum > max_input_address_opnum)
6066 max_input_address_opnum = rld[j].opnum;
6068 /* If the reload regs aren't exactly the same (e.g, different modes)
6069 or if the values are different, we can't merge this reload.
6070 But if it is an input reload, we might still merge
6071 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6073 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6074 || rld[j].out != 0 || rld[j].in == 0
6075 || ! rtx_equal_p (rld[i].in, rld[j].in))
6077 if (rld[j].when_needed != RELOAD_FOR_INPUT
6078 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6079 || rld[i].opnum > rld[j].opnum)
6080 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6082 conflicting_input = 1;
6083 if (min_conflicting_input_opnum > rld[j].opnum)
6084 min_conflicting_input_opnum = rld[j].opnum;
6088 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6089 we, in fact, found any matching reloads. */
6092 && max_input_address_opnum <= min_conflicting_input_opnum)
6094 for (j = 0; j < n_reloads; j++)
6095 if (i != j && rld[j].reg_rtx != 0
6096 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6097 && (! conflicting_input
6098 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6099 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6101 rld[i].when_needed = RELOAD_OTHER;
6103 reload_spill_index[j] = -1;
6104 transfer_replacements (i, j);
6107 /* If this is now RELOAD_OTHER, look for any reloads that load
6108 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6109 if they were for inputs, RELOAD_OTHER for outputs. Note that
6110 this test is equivalent to looking for reloads for this operand
6112 /* We must take special care when there are two or more reloads to
6113 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6114 same value or a part of it; we must not change its type if there
6115 is a conflicting input. */
6117 if (rld[i].when_needed == RELOAD_OTHER)
6118 for (j = 0; j < n_reloads; j++)
6120 && rld[j].when_needed != RELOAD_OTHER
6121 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6122 && (! conflicting_input
6123 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6124 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6125 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6131 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6132 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6133 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6135 /* Check to see if we accidentally converted two reloads
6136 that use the same reload register with different inputs
6137 to the same type. If so, the resulting code won't work,
6140 for (k = 0; k < j; k++)
6141 if (rld[k].in != 0 && rld[k].reg_rtx != 0
6142 && rld[k].when_needed == rld[j].when_needed
6143 && rtx_equal_p (rld[k].reg_rtx, rld[j].reg_rtx)
6144 && ! rtx_equal_p (rld[k].in, rld[j].in))
6151 /* These arrays are filled by emit_reload_insns and its subroutines. */
6152 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6153 static rtx other_input_address_reload_insns = 0;
6154 static rtx other_input_reload_insns = 0;
6155 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6156 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6157 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6158 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6159 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6160 static rtx operand_reload_insns = 0;
6161 static rtx other_operand_reload_insns = 0;
6162 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6164 /* Values to be put in spill_reg_store are put here first. */
6165 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6166 static HARD_REG_SET reg_reloaded_died;
6168 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6169 has the number J. OLD contains the value to be used as input. */
6172 emit_input_reload_insns (chain, rl, old, j)
6173 struct insn_chain *chain;
6178 rtx insn = chain->insn;
6179 rtx reloadreg = rl->reg_rtx;
6180 rtx oldequiv_reg = 0;
6183 enum machine_mode mode;
6186 /* Determine the mode to reload in.
6187 This is very tricky because we have three to choose from.
6188 There is the mode the insn operand wants (rl->inmode).
6189 There is the mode of the reload register RELOADREG.
6190 There is the intrinsic mode of the operand, which we could find
6191 by stripping some SUBREGs.
6192 It turns out that RELOADREG's mode is irrelevant:
6193 we can change that arbitrarily.
6195 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6196 then the reload reg may not support QImode moves, so use SImode.
6197 If foo is in memory due to spilling a pseudo reg, this is safe,
6198 because the QImode value is in the least significant part of a
6199 slot big enough for a SImode. If foo is some other sort of
6200 memory reference, then it is impossible to reload this case,
6201 so previous passes had better make sure this never happens.
6203 Then consider a one-word union which has SImode and one of its
6204 members is a float, being fetched as (SUBREG:SF union:SI).
6205 We must fetch that as SFmode because we could be loading into
6206 a float-only register. In this case OLD's mode is correct.
6208 Consider an immediate integer: it has VOIDmode. Here we need
6209 to get a mode from something else.
6211 In some cases, there is a fourth mode, the operand's
6212 containing mode. If the insn specifies a containing mode for
6213 this operand, it overrides all others.
6215 I am not sure whether the algorithm here is always right,
6216 but it does the right things in those cases. */
6218 mode = GET_MODE (old);
6219 if (mode == VOIDmode)
6222 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6223 /* If we need a secondary register for this operation, see if
6224 the value is already in a register in that class. Don't
6225 do this if the secondary register will be used as a scratch
6228 if (rl->secondary_in_reload >= 0
6229 && rl->secondary_in_icode == CODE_FOR_nothing
6232 = find_equiv_reg (old, insn,
6233 rld[rl->secondary_in_reload].class,
6237 /* If reloading from memory, see if there is a register
6238 that already holds the same value. If so, reload from there.
6239 We can pass 0 as the reload_reg_p argument because
6240 any other reload has either already been emitted,
6241 in which case find_equiv_reg will see the reload-insn,
6242 or has yet to be emitted, in which case it doesn't matter
6243 because we will use this equiv reg right away. */
6245 if (oldequiv == 0 && optimize
6246 && (GET_CODE (old) == MEM
6247 || (GET_CODE (old) == REG
6248 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6249 && reg_renumber[REGNO (old)] < 0)))
6250 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6254 unsigned int regno = true_regnum (oldequiv);
6256 /* Don't use OLDEQUIV if any other reload changes it at an
6257 earlier stage of this insn or at this stage. */
6258 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6259 rl->in, const0_rtx, j, 0))
6262 /* If it is no cheaper to copy from OLDEQUIV into the
6263 reload register than it would be to move from memory,
6264 don't use it. Likewise, if we need a secondary register
6268 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6269 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6271 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6272 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6273 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6277 #ifdef SECONDARY_MEMORY_NEEDED
6278 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6286 /* delete_output_reload is only invoked properly if old contains
6287 the original pseudo register. Since this is replaced with a
6288 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6289 find the pseudo in RELOAD_IN_REG. */
6291 && reload_override_in[j]
6292 && GET_CODE (rl->in_reg) == REG)
6299 else if (GET_CODE (oldequiv) == REG)
6300 oldequiv_reg = oldequiv;
6301 else if (GET_CODE (oldequiv) == SUBREG)
6302 oldequiv_reg = SUBREG_REG (oldequiv);
6304 /* If we are reloading from a register that was recently stored in
6305 with an output-reload, see if we can prove there was
6306 actually no need to store the old value in it. */
6308 if (optimize && GET_CODE (oldequiv) == REG
6309 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6310 && spill_reg_store[REGNO (oldequiv)]
6311 && GET_CODE (old) == REG
6312 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6313 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6315 delete_output_reload (insn, j, REGNO (oldequiv));
6317 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6318 then load RELOADREG from OLDEQUIV. Note that we cannot use
6319 gen_lowpart_common since it can do the wrong thing when
6320 RELOADREG has a multi-word mode. Note that RELOADREG
6321 must always be a REG here. */
6323 if (GET_MODE (reloadreg) != mode)
6324 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6325 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6326 oldequiv = SUBREG_REG (oldequiv);
6327 if (GET_MODE (oldequiv) != VOIDmode
6328 && mode != GET_MODE (oldequiv))
6329 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6331 /* Switch to the right place to emit the reload insns. */
6332 switch (rl->when_needed)
6335 where = &other_input_reload_insns;
6337 case RELOAD_FOR_INPUT:
6338 where = &input_reload_insns[rl->opnum];
6340 case RELOAD_FOR_INPUT_ADDRESS:
6341 where = &input_address_reload_insns[rl->opnum];
6343 case RELOAD_FOR_INPADDR_ADDRESS:
6344 where = &inpaddr_address_reload_insns[rl->opnum];
6346 case RELOAD_FOR_OUTPUT_ADDRESS:
6347 where = &output_address_reload_insns[rl->opnum];
6349 case RELOAD_FOR_OUTADDR_ADDRESS:
6350 where = &outaddr_address_reload_insns[rl->opnum];
6352 case RELOAD_FOR_OPERAND_ADDRESS:
6353 where = &operand_reload_insns;
6355 case RELOAD_FOR_OPADDR_ADDR:
6356 where = &other_operand_reload_insns;
6358 case RELOAD_FOR_OTHER_ADDRESS:
6359 where = &other_input_address_reload_insns;
6365 push_to_sequence (*where);
6367 /* Auto-increment addresses must be reloaded in a special way. */
6368 if (rl->out && ! rl->out_reg)
6370 /* We are not going to bother supporting the case where a
6371 incremented register can't be copied directly from
6372 OLDEQUIV since this seems highly unlikely. */
6373 if (rl->secondary_in_reload >= 0)
6376 if (reload_inherited[j])
6377 oldequiv = reloadreg;
6379 old = XEXP (rl->in_reg, 0);
6381 if (optimize && GET_CODE (oldequiv) == REG
6382 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6383 && spill_reg_store[REGNO (oldequiv)]
6384 && GET_CODE (old) == REG
6385 && (dead_or_set_p (insn,
6386 spill_reg_stored_to[REGNO (oldequiv)])
6387 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6389 delete_output_reload (insn, j, REGNO (oldequiv));
6391 /* Prevent normal processing of this reload. */
6393 /* Output a special code sequence for this case. */
6394 new_spill_reg_store[REGNO (reloadreg)]
6395 = inc_for_reload (reloadreg, oldequiv, rl->out,
6399 /* If we are reloading a pseudo-register that was set by the previous
6400 insn, see if we can get rid of that pseudo-register entirely
6401 by redirecting the previous insn into our reload register. */
6403 else if (optimize && GET_CODE (old) == REG
6404 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6405 && dead_or_set_p (insn, old)
6406 /* This is unsafe if some other reload
6407 uses the same reg first. */
6408 && ! conflicts_with_override (reloadreg)
6409 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6410 rl->when_needed, old, rl->out, j, 0))
6412 rtx temp = PREV_INSN (insn);
6413 while (temp && GET_CODE (temp) == NOTE)
6414 temp = PREV_INSN (temp);
6416 && GET_CODE (temp) == INSN
6417 && GET_CODE (PATTERN (temp)) == SET
6418 && SET_DEST (PATTERN (temp)) == old
6419 /* Make sure we can access insn_operand_constraint. */
6420 && asm_noperands (PATTERN (temp)) < 0
6421 /* This is unsafe if operand occurs more than once in current
6422 insn. Perhaps some occurrences aren't reloaded. */
6423 && count_occurrences (PATTERN (insn), old, 0) == 1)
6425 rtx old = SET_DEST (PATTERN (temp));
6426 /* Store into the reload register instead of the pseudo. */
6427 SET_DEST (PATTERN (temp)) = reloadreg;
6429 /* Verify that resulting insn is valid. */
6430 extract_insn (temp);
6431 if (constrain_operands (1))
6433 /* If the previous insn is an output reload, the source is
6434 a reload register, and its spill_reg_store entry will
6435 contain the previous destination. This is now
6437 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6438 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6440 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6441 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6444 /* If these are the only uses of the pseudo reg,
6445 pretend for GDB it lives in the reload reg we used. */
6446 if (REG_N_DEATHS (REGNO (old)) == 1
6447 && REG_N_SETS (REGNO (old)) == 1)
6449 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6450 alter_reg (REGNO (old), -1);
6456 SET_DEST (PATTERN (temp)) = old;
6461 /* We can't do that, so output an insn to load RELOADREG. */
6463 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6464 /* If we have a secondary reload, pick up the secondary register
6465 and icode, if any. If OLDEQUIV and OLD are different or
6466 if this is an in-out reload, recompute whether or not we
6467 still need a secondary register and what the icode should
6468 be. If we still need a secondary register and the class or
6469 icode is different, go back to reloading from OLD if using
6470 OLDEQUIV means that we got the wrong type of register. We
6471 cannot have different class or icode due to an in-out reload
6472 because we don't make such reloads when both the input and
6473 output need secondary reload registers. */
6475 if (! special && rl->secondary_in_reload >= 0)
6477 rtx second_reload_reg = 0;
6478 int secondary_reload = rl->secondary_in_reload;
6479 rtx real_oldequiv = oldequiv;
6482 enum insn_code icode;
6484 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6485 and similarly for OLD.
6486 See comments in get_secondary_reload in reload.c. */
6487 /* If it is a pseudo that cannot be replaced with its
6488 equivalent MEM, we must fall back to reload_in, which
6489 will have all the necessary substitutions registered.
6490 Likewise for a pseudo that can't be replaced with its
6491 equivalent constant.
6493 Take extra care for subregs of such pseudos. Note that
6494 we cannot use reg_equiv_mem in this case because it is
6495 not in the right mode. */
6498 if (GET_CODE (tmp) == SUBREG)
6499 tmp = SUBREG_REG (tmp);
6500 if (GET_CODE (tmp) == REG
6501 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6502 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6503 || reg_equiv_constant[REGNO (tmp)] != 0))
6505 if (! reg_equiv_mem[REGNO (tmp)]
6506 || num_not_at_initial_offset
6507 || GET_CODE (oldequiv) == SUBREG)
6508 real_oldequiv = rl->in;
6510 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6514 if (GET_CODE (tmp) == SUBREG)
6515 tmp = SUBREG_REG (tmp);
6516 if (GET_CODE (tmp) == REG
6517 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6518 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6519 || reg_equiv_constant[REGNO (tmp)] != 0))
6521 if (! reg_equiv_mem[REGNO (tmp)]
6522 || num_not_at_initial_offset
6523 || GET_CODE (old) == SUBREG)
6526 real_old = reg_equiv_mem[REGNO (tmp)];
6529 second_reload_reg = rld[secondary_reload].reg_rtx;
6530 icode = rl->secondary_in_icode;
6532 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6533 || (rl->in != 0 && rl->out != 0))
6535 enum reg_class new_class
6536 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6537 mode, real_oldequiv);
6539 if (new_class == NO_REGS)
6540 second_reload_reg = 0;
6543 enum insn_code new_icode;
6544 enum machine_mode new_mode;
6546 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6547 REGNO (second_reload_reg)))
6548 oldequiv = old, real_oldequiv = real_old;
6551 new_icode = reload_in_optab[(int) mode];
6552 if (new_icode != CODE_FOR_nothing
6553 && ((insn_data[(int) new_icode].operand[0].predicate
6554 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6556 || (insn_data[(int) new_icode].operand[1].predicate
6557 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6558 (real_oldequiv, mode)))))
6559 new_icode = CODE_FOR_nothing;
6561 if (new_icode == CODE_FOR_nothing)
6564 new_mode = insn_data[(int) new_icode].operand[2].mode;
6566 if (GET_MODE (second_reload_reg) != new_mode)
6568 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6570 oldequiv = old, real_oldequiv = real_old;
6573 = reload_adjust_reg_for_mode (second_reload_reg,
6580 /* If we still need a secondary reload register, check
6581 to see if it is being used as a scratch or intermediate
6582 register and generate code appropriately. If we need
6583 a scratch register, use REAL_OLDEQUIV since the form of
6584 the insn may depend on the actual address if it is
6587 if (second_reload_reg)
6589 if (icode != CODE_FOR_nothing)
6591 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6592 second_reload_reg));
6597 /* See if we need a scratch register to load the
6598 intermediate register (a tertiary reload). */
6599 enum insn_code tertiary_icode
6600 = rld[secondary_reload].secondary_in_icode;
6602 if (tertiary_icode != CODE_FOR_nothing)
6604 rtx third_reload_reg
6605 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6607 emit_insn ((GEN_FCN (tertiary_icode)
6608 (second_reload_reg, real_oldequiv,
6609 third_reload_reg)));
6612 gen_reload (second_reload_reg, real_oldequiv,
6616 oldequiv = second_reload_reg;
6622 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6624 rtx real_oldequiv = oldequiv;
6626 if ((GET_CODE (oldequiv) == REG
6627 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6628 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6629 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6630 || (GET_CODE (oldequiv) == SUBREG
6631 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6632 && (REGNO (SUBREG_REG (oldequiv))
6633 >= FIRST_PSEUDO_REGISTER)
6634 && ((reg_equiv_memory_loc
6635 [REGNO (SUBREG_REG (oldequiv))] != 0)
6636 || (reg_equiv_constant
6637 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6638 || (CONSTANT_P (oldequiv)
6639 && (PREFERRED_RELOAD_CLASS (oldequiv,
6640 REGNO_REG_CLASS (REGNO (reloadreg)))
6642 real_oldequiv = rl->in;
6643 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6647 if (flag_non_call_exceptions)
6648 copy_eh_notes (insn, get_insns ());
6650 /* End this sequence. */
6651 *where = get_insns ();
6654 /* Update reload_override_in so that delete_address_reloads_1
6655 can see the actual register usage. */
6657 reload_override_in[j] = oldequiv;
6660 /* Generate insns to for the output reload RL, which is for the insn described
6661 by CHAIN and has the number J. */
6663 emit_output_reload_insns (chain, rl, j)
6664 struct insn_chain *chain;
6668 rtx reloadreg = rl->reg_rtx;
6669 rtx insn = chain->insn;
6672 enum machine_mode mode = GET_MODE (old);
6675 if (rl->when_needed == RELOAD_OTHER)
6678 push_to_sequence (output_reload_insns[rl->opnum]);
6680 /* Determine the mode to reload in.
6681 See comments above (for input reloading). */
6683 if (mode == VOIDmode)
6685 /* VOIDmode should never happen for an output. */
6686 if (asm_noperands (PATTERN (insn)) < 0)
6687 /* It's the compiler's fault. */
6688 fatal_insn ("VOIDmode on an output", insn);
6689 error_for_asm (insn, "output operand is constant in `asm'");
6690 /* Prevent crash--use something we know is valid. */
6692 old = gen_rtx_REG (mode, REGNO (reloadreg));
6695 if (GET_MODE (reloadreg) != mode)
6696 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6698 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6700 /* If we need two reload regs, set RELOADREG to the intermediate
6701 one, since it will be stored into OLD. We might need a secondary
6702 register only for an input reload, so check again here. */
6704 if (rl->secondary_out_reload >= 0)
6708 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6709 && reg_equiv_mem[REGNO (old)] != 0)
6710 real_old = reg_equiv_mem[REGNO (old)];
6712 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6716 rtx second_reloadreg = reloadreg;
6717 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6719 /* See if RELOADREG is to be used as a scratch register
6720 or as an intermediate register. */
6721 if (rl->secondary_out_icode != CODE_FOR_nothing)
6723 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6724 (real_old, second_reloadreg, reloadreg)));
6729 /* See if we need both a scratch and intermediate reload
6732 int secondary_reload = rl->secondary_out_reload;
6733 enum insn_code tertiary_icode
6734 = rld[secondary_reload].secondary_out_icode;
6736 if (GET_MODE (reloadreg) != mode)
6737 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6739 if (tertiary_icode != CODE_FOR_nothing)
6742 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6745 /* Copy primary reload reg to secondary reload reg.
6746 (Note that these have been swapped above, then
6747 secondary reload reg to OLD using our insn.) */
6749 /* If REAL_OLD is a paradoxical SUBREG, remove it
6750 and try to put the opposite SUBREG on
6752 if (GET_CODE (real_old) == SUBREG
6753 && (GET_MODE_SIZE (GET_MODE (real_old))
6754 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6755 && 0 != (tem = gen_lowpart_common
6756 (GET_MODE (SUBREG_REG (real_old)),
6758 real_old = SUBREG_REG (real_old), reloadreg = tem;
6760 gen_reload (reloadreg, second_reloadreg,
6761 rl->opnum, rl->when_needed);
6762 emit_insn ((GEN_FCN (tertiary_icode)
6763 (real_old, reloadreg, third_reloadreg)));
6768 /* Copy between the reload regs here and then to
6771 gen_reload (reloadreg, second_reloadreg,
6772 rl->opnum, rl->when_needed);
6778 /* Output the last reload insn. */
6783 /* Don't output the last reload if OLD is not the dest of
6784 INSN and is in the src and is clobbered by INSN. */
6785 if (! flag_expensive_optimizations
6786 || GET_CODE (old) != REG
6787 || !(set = single_set (insn))
6788 || rtx_equal_p (old, SET_DEST (set))
6789 || !reg_mentioned_p (old, SET_SRC (set))
6790 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6791 gen_reload (old, reloadreg, rl->opnum,
6795 /* Look at all insns we emitted, just to be safe. */
6796 for (p = get_insns (); p; p = NEXT_INSN (p))
6799 rtx pat = PATTERN (p);
6801 /* If this output reload doesn't come from a spill reg,
6802 clear any memory of reloaded copies of the pseudo reg.
6803 If this output reload comes from a spill reg,
6804 reg_has_output_reload will make this do nothing. */
6805 note_stores (pat, forget_old_reloads_1, NULL);
6807 if (reg_mentioned_p (rl->reg_rtx, pat))
6809 rtx set = single_set (insn);
6810 if (reload_spill_index[j] < 0
6812 && SET_SRC (set) == rl->reg_rtx)
6814 int src = REGNO (SET_SRC (set));
6816 reload_spill_index[j] = src;
6817 SET_HARD_REG_BIT (reg_is_output_reload, src);
6818 if (find_regno_note (insn, REG_DEAD, src))
6819 SET_HARD_REG_BIT (reg_reloaded_died, src);
6821 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6823 int s = rl->secondary_out_reload;
6824 set = single_set (p);
6825 /* If this reload copies only to the secondary reload
6826 register, the secondary reload does the actual
6828 if (s >= 0 && set == NULL_RTX)
6829 /* We can't tell what function the secondary reload
6830 has and where the actual store to the pseudo is
6831 made; leave new_spill_reg_store alone. */
6834 && SET_SRC (set) == rl->reg_rtx
6835 && SET_DEST (set) == rld[s].reg_rtx)
6837 /* Usually the next instruction will be the
6838 secondary reload insn; if we can confirm
6839 that it is, setting new_spill_reg_store to
6840 that insn will allow an extra optimization. */
6841 rtx s_reg = rld[s].reg_rtx;
6842 rtx next = NEXT_INSN (p);
6843 rld[s].out = rl->out;
6844 rld[s].out_reg = rl->out_reg;
6845 set = single_set (next);
6846 if (set && SET_SRC (set) == s_reg
6847 && ! new_spill_reg_store[REGNO (s_reg)])
6849 SET_HARD_REG_BIT (reg_is_output_reload,
6851 new_spill_reg_store[REGNO (s_reg)] = next;
6855 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6860 if (rl->when_needed == RELOAD_OTHER)
6862 emit_insn (other_output_reload_insns[rl->opnum]);
6863 other_output_reload_insns[rl->opnum] = get_insns ();
6866 output_reload_insns[rl->opnum] = get_insns ();
6868 if (flag_non_call_exceptions)
6869 copy_eh_notes (insn, get_insns ());
6874 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6875 and has the number J. */
6877 do_input_reload (chain, rl, j)
6878 struct insn_chain *chain;
6882 rtx insn = chain->insn;
6883 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6884 ? rl->in_reg : rl->in);
6887 /* AUTO_INC reloads need to be handled even if inherited. We got an
6888 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6889 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6890 && ! rtx_equal_p (rl->reg_rtx, old)
6891 && rl->reg_rtx != 0)
6892 emit_input_reload_insns (chain, rld + j, old, j);
6894 /* When inheriting a wider reload, we have a MEM in rl->in,
6895 e.g. inheriting a SImode output reload for
6896 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6897 if (optimize && reload_inherited[j] && rl->in
6898 && GET_CODE (rl->in) == MEM
6899 && GET_CODE (rl->in_reg) == MEM
6900 && reload_spill_index[j] >= 0
6901 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6902 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6904 /* If we are reloading a register that was recently stored in with an
6905 output-reload, see if we can prove there was
6906 actually no need to store the old value in it. */
6909 && (reload_inherited[j] || reload_override_in[j])
6911 && GET_CODE (rl->reg_rtx) == REG
6912 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6914 /* There doesn't seem to be any reason to restrict this to pseudos
6915 and doing so loses in the case where we are copying from a
6916 register of the wrong class. */
6917 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6918 >= FIRST_PSEUDO_REGISTER)
6920 /* The insn might have already some references to stackslots
6921 replaced by MEMs, while reload_out_reg still names the
6923 && (dead_or_set_p (insn,
6924 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6925 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6927 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6930 /* Do output reloading for reload RL, which is for the insn described by
6931 CHAIN and has the number J.
6932 ??? At some point we need to support handling output reloads of
6933 JUMP_INSNs or insns that set cc0. */
6935 do_output_reload (chain, rl, j)
6936 struct insn_chain *chain;
6941 rtx insn = chain->insn;
6942 /* If this is an output reload that stores something that is
6943 not loaded in this same reload, see if we can eliminate a previous
6945 rtx pseudo = rl->out_reg;
6949 && GET_CODE (pseudo) == REG
6950 && ! rtx_equal_p (rl->in_reg, pseudo)
6951 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6952 && reg_last_reload_reg[REGNO (pseudo)])
6954 int pseudo_no = REGNO (pseudo);
6955 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6957 /* We don't need to test full validity of last_regno for
6958 inherit here; we only want to know if the store actually
6959 matches the pseudo. */
6960 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6961 && reg_reloaded_contents[last_regno] == pseudo_no
6962 && spill_reg_store[last_regno]
6963 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6964 delete_output_reload (insn, j, last_regno);
6969 || rl->reg_rtx == old
6970 || rl->reg_rtx == 0)
6973 /* An output operand that dies right away does need a reload,
6974 but need not be copied from it. Show the new location in the
6976 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6977 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6979 XEXP (note, 0) = rl->reg_rtx;
6982 /* Likewise for a SUBREG of an operand that dies. */
6983 else if (GET_CODE (old) == SUBREG
6984 && GET_CODE (SUBREG_REG (old)) == REG
6985 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6988 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6992 else if (GET_CODE (old) == SCRATCH)
6993 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6994 but we don't want to make an output reload. */
6997 /* If is a JUMP_INSN, we can't support output reloads yet. */
6998 if (GET_CODE (insn) == JUMP_INSN)
7001 emit_output_reload_insns (chain, rld + j, j);
7004 /* Output insns to reload values in and out of the chosen reload regs. */
7007 emit_reload_insns (chain)
7008 struct insn_chain *chain;
7010 rtx insn = chain->insn;
7014 CLEAR_HARD_REG_SET (reg_reloaded_died);
7016 for (j = 0; j < reload_n_operands; j++)
7017 input_reload_insns[j] = input_address_reload_insns[j]
7018 = inpaddr_address_reload_insns[j]
7019 = output_reload_insns[j] = output_address_reload_insns[j]
7020 = outaddr_address_reload_insns[j]
7021 = other_output_reload_insns[j] = 0;
7022 other_input_address_reload_insns = 0;
7023 other_input_reload_insns = 0;
7024 operand_reload_insns = 0;
7025 other_operand_reload_insns = 0;
7027 /* Dump reloads into the dump file. */
7030 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7031 debug_reload_to_stream (rtl_dump_file);
7034 /* Now output the instructions to copy the data into and out of the
7035 reload registers. Do these in the order that the reloads were reported,
7036 since reloads of base and index registers precede reloads of operands
7037 and the operands may need the base and index registers reloaded. */
7039 for (j = 0; j < n_reloads; j++)
7042 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7043 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7045 do_input_reload (chain, rld + j, j);
7046 do_output_reload (chain, rld + j, j);
7049 /* Now write all the insns we made for reloads in the order expected by
7050 the allocation functions. Prior to the insn being reloaded, we write
7051 the following reloads:
7053 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7055 RELOAD_OTHER reloads.
7057 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7058 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7059 RELOAD_FOR_INPUT reload for the operand.
7061 RELOAD_FOR_OPADDR_ADDRS reloads.
7063 RELOAD_FOR_OPERAND_ADDRESS reloads.
7065 After the insn being reloaded, we write the following:
7067 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7068 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7069 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7070 reloads for the operand. The RELOAD_OTHER output reloads are
7071 output in descending order by reload number. */
7073 emit_insn_before (other_input_address_reload_insns, insn);
7074 emit_insn_before (other_input_reload_insns, insn);
7076 for (j = 0; j < reload_n_operands; j++)
7078 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7079 emit_insn_before (input_address_reload_insns[j], insn);
7080 emit_insn_before (input_reload_insns[j], insn);
7083 emit_insn_before (other_operand_reload_insns, insn);
7084 emit_insn_before (operand_reload_insns, insn);
7086 for (j = 0; j < reload_n_operands; j++)
7088 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7089 x = emit_insn_after (output_address_reload_insns[j], x);
7090 x = emit_insn_after (output_reload_insns[j], x);
7091 emit_insn_after (other_output_reload_insns[j], x);
7094 /* For all the spill regs newly reloaded in this instruction,
7095 record what they were reloaded from, so subsequent instructions
7096 can inherit the reloads.
7098 Update spill_reg_store for the reloads of this insn.
7099 Copy the elements that were updated in the loop above. */
7101 for (j = 0; j < n_reloads; j++)
7103 int r = reload_order[j];
7104 int i = reload_spill_index[r];
7106 /* If this is a non-inherited input reload from a pseudo, we must
7107 clear any memory of a previous store to the same pseudo. Only do
7108 something if there will not be an output reload for the pseudo
7110 if (rld[r].in_reg != 0
7111 && ! (reload_inherited[r] || reload_override_in[r]))
7113 rtx reg = rld[r].in_reg;
7115 if (GET_CODE (reg) == SUBREG)
7116 reg = SUBREG_REG (reg);
7118 if (GET_CODE (reg) == REG
7119 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7120 && ! reg_has_output_reload[REGNO (reg)])
7122 int nregno = REGNO (reg);
7124 if (reg_last_reload_reg[nregno])
7126 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7128 if (reg_reloaded_contents[last_regno] == nregno)
7129 spill_reg_store[last_regno] = 0;
7134 /* I is nonneg if this reload used a register.
7135 If rld[r].reg_rtx is 0, this is an optional reload
7136 that we opted to ignore. */
7138 if (i >= 0 && rld[r].reg_rtx != 0)
7140 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7142 int part_reaches_end = 0;
7143 int all_reaches_end = 1;
7145 /* For a multi register reload, we need to check if all or part
7146 of the value lives to the end. */
7147 for (k = 0; k < nr; k++)
7149 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7150 rld[r].when_needed))
7151 part_reaches_end = 1;
7153 all_reaches_end = 0;
7156 /* Ignore reloads that don't reach the end of the insn in
7158 if (all_reaches_end)
7160 /* First, clear out memory of what used to be in this spill reg.
7161 If consecutive registers are used, clear them all. */
7163 for (k = 0; k < nr; k++)
7164 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7166 /* Maybe the spill reg contains a copy of reload_out. */
7168 && (GET_CODE (rld[r].out) == REG
7172 || GET_CODE (rld[r].out_reg) == REG))
7174 rtx out = (GET_CODE (rld[r].out) == REG
7178 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7179 int nregno = REGNO (out);
7180 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7181 : HARD_REGNO_NREGS (nregno,
7182 GET_MODE (rld[r].reg_rtx)));
7184 spill_reg_store[i] = new_spill_reg_store[i];
7185 spill_reg_stored_to[i] = out;
7186 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7188 /* If NREGNO is a hard register, it may occupy more than
7189 one register. If it does, say what is in the
7190 rest of the registers assuming that both registers
7191 agree on how many words the object takes. If not,
7192 invalidate the subsequent registers. */
7194 if (nregno < FIRST_PSEUDO_REGISTER)
7195 for (k = 1; k < nnr; k++)
7196 reg_last_reload_reg[nregno + k]
7198 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7201 /* Now do the inverse operation. */
7202 for (k = 0; k < nr; k++)
7204 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7205 reg_reloaded_contents[i + k]
7206 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7209 reg_reloaded_insn[i + k] = insn;
7210 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7214 /* Maybe the spill reg contains a copy of reload_in. Only do
7215 something if there will not be an output reload for
7216 the register being reloaded. */
7217 else if (rld[r].out_reg == 0
7219 && ((GET_CODE (rld[r].in) == REG
7220 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7221 && ! reg_has_output_reload[REGNO (rld[r].in)])
7222 || (GET_CODE (rld[r].in_reg) == REG
7223 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7224 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7229 if (GET_CODE (rld[r].in) == REG
7230 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7231 nregno = REGNO (rld[r].in);
7232 else if (GET_CODE (rld[r].in_reg) == REG)
7233 nregno = REGNO (rld[r].in_reg);
7235 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7237 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7238 : HARD_REGNO_NREGS (nregno,
7239 GET_MODE (rld[r].reg_rtx)));
7241 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7243 if (nregno < FIRST_PSEUDO_REGISTER)
7244 for (k = 1; k < nnr; k++)
7245 reg_last_reload_reg[nregno + k]
7247 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7250 /* Unless we inherited this reload, show we haven't
7251 recently done a store.
7252 Previous stores of inherited auto_inc expressions
7253 also have to be discarded. */
7254 if (! reload_inherited[r]
7255 || (rld[r].out && ! rld[r].out_reg))
7256 spill_reg_store[i] = 0;
7258 for (k = 0; k < nr; k++)
7260 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7261 reg_reloaded_contents[i + k]
7262 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7265 reg_reloaded_insn[i + k] = insn;
7266 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7271 /* However, if part of the reload reaches the end, then we must
7272 invalidate the old info for the part that survives to the end. */
7273 else if (part_reaches_end)
7275 for (k = 0; k < nr; k++)
7276 if (reload_reg_reaches_end_p (i + k,
7278 rld[r].when_needed))
7279 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7283 /* The following if-statement was #if 0'd in 1.34 (or before...).
7284 It's reenabled in 1.35 because supposedly nothing else
7285 deals with this problem. */
7287 /* If a register gets output-reloaded from a non-spill register,
7288 that invalidates any previous reloaded copy of it.
7289 But forget_old_reloads_1 won't get to see it, because
7290 it thinks only about the original insn. So invalidate it here. */
7291 if (i < 0 && rld[r].out != 0
7292 && (GET_CODE (rld[r].out) == REG
7293 || (GET_CODE (rld[r].out) == MEM
7294 && GET_CODE (rld[r].out_reg) == REG)))
7296 rtx out = (GET_CODE (rld[r].out) == REG
7297 ? rld[r].out : rld[r].out_reg);
7298 int nregno = REGNO (out);
7299 if (nregno >= FIRST_PSEUDO_REGISTER)
7301 rtx src_reg, store_insn = NULL_RTX;
7303 reg_last_reload_reg[nregno] = 0;
7305 /* If we can find a hard register that is stored, record
7306 the storing insn so that we may delete this insn with
7307 delete_output_reload. */
7308 src_reg = rld[r].reg_rtx;
7310 /* If this is an optional reload, try to find the source reg
7311 from an input reload. */
7314 rtx set = single_set (insn);
7315 if (set && SET_DEST (set) == rld[r].out)
7319 src_reg = SET_SRC (set);
7321 for (k = 0; k < n_reloads; k++)
7323 if (rld[k].in == src_reg)
7325 src_reg = rld[k].reg_rtx;
7332 store_insn = new_spill_reg_store[REGNO (src_reg)];
7333 if (src_reg && GET_CODE (src_reg) == REG
7334 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7336 int src_regno = REGNO (src_reg);
7337 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7338 /* The place where to find a death note varies with
7339 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7340 necessarily checked exactly in the code that moves
7341 notes, so just check both locations. */
7342 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7343 if (! note && store_insn)
7344 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7347 spill_reg_store[src_regno + nr] = store_insn;
7348 spill_reg_stored_to[src_regno + nr] = out;
7349 reg_reloaded_contents[src_regno + nr] = nregno;
7350 reg_reloaded_insn[src_regno + nr] = store_insn;
7351 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7352 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7353 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7355 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7357 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7359 reg_last_reload_reg[nregno] = src_reg;
7364 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7366 while (num_regs-- > 0)
7367 reg_last_reload_reg[nregno + num_regs] = 0;
7371 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7374 /* Emit code to perform a reload from IN (which may be a reload register) to
7375 OUT (which may also be a reload register). IN or OUT is from operand
7376 OPNUM with reload type TYPE.
7378 Returns first insn emitted. */
7381 gen_reload (out, in, opnum, type)
7385 enum reload_type type;
7387 rtx last = get_last_insn ();
7390 /* If IN is a paradoxical SUBREG, remove it and try to put the
7391 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7392 if (GET_CODE (in) == SUBREG
7393 && (GET_MODE_SIZE (GET_MODE (in))
7394 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7395 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7396 in = SUBREG_REG (in), out = tem;
7397 else if (GET_CODE (out) == SUBREG
7398 && (GET_MODE_SIZE (GET_MODE (out))
7399 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7400 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7401 out = SUBREG_REG (out), in = tem;
7403 /* How to do this reload can get quite tricky. Normally, we are being
7404 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7405 register that didn't get a hard register. In that case we can just
7406 call emit_move_insn.
7408 We can also be asked to reload a PLUS that adds a register or a MEM to
7409 another register, constant or MEM. This can occur during frame pointer
7410 elimination and while reloading addresses. This case is handled by
7411 trying to emit a single insn to perform the add. If it is not valid,
7412 we use a two insn sequence.
7414 Finally, we could be called to handle an 'o' constraint by putting
7415 an address into a register. In that case, we first try to do this
7416 with a named pattern of "reload_load_address". If no such pattern
7417 exists, we just emit a SET insn and hope for the best (it will normally
7418 be valid on machines that use 'o').
7420 This entire process is made complex because reload will never
7421 process the insns we generate here and so we must ensure that
7422 they will fit their constraints and also by the fact that parts of
7423 IN might be being reloaded separately and replaced with spill registers.
7424 Because of this, we are, in some sense, just guessing the right approach
7425 here. The one listed above seems to work.
7427 ??? At some point, this whole thing needs to be rethought. */
7429 if (GET_CODE (in) == PLUS
7430 && (GET_CODE (XEXP (in, 0)) == REG
7431 || GET_CODE (XEXP (in, 0)) == SUBREG
7432 || GET_CODE (XEXP (in, 0)) == MEM)
7433 && (GET_CODE (XEXP (in, 1)) == REG
7434 || GET_CODE (XEXP (in, 1)) == SUBREG
7435 || CONSTANT_P (XEXP (in, 1))
7436 || GET_CODE (XEXP (in, 1)) == MEM))
7438 /* We need to compute the sum of a register or a MEM and another
7439 register, constant, or MEM, and put it into the reload
7440 register. The best possible way of doing this is if the machine
7441 has a three-operand ADD insn that accepts the required operands.
7443 The simplest approach is to try to generate such an insn and see if it
7444 is recognized and matches its constraints. If so, it can be used.
7446 It might be better not to actually emit the insn unless it is valid,
7447 but we need to pass the insn as an operand to `recog' and
7448 `extract_insn' and it is simpler to emit and then delete the insn if
7449 not valid than to dummy things up. */
7451 rtx op0, op1, tem, insn;
7454 op0 = find_replacement (&XEXP (in, 0));
7455 op1 = find_replacement (&XEXP (in, 1));
7457 /* Since constraint checking is strict, commutativity won't be
7458 checked, so we need to do that here to avoid spurious failure
7459 if the add instruction is two-address and the second operand
7460 of the add is the same as the reload reg, which is frequently
7461 the case. If the insn would be A = B + A, rearrange it so
7462 it will be A = A + B as constrain_operands expects. */
7464 if (GET_CODE (XEXP (in, 1)) == REG
7465 && REGNO (out) == REGNO (XEXP (in, 1)))
7466 tem = op0, op0 = op1, op1 = tem;
7468 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7469 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7471 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7472 code = recog_memoized (insn);
7476 extract_insn (insn);
7477 /* We want constrain operands to treat this insn strictly in
7478 its validity determination, i.e., the way it would after reload
7480 if (constrain_operands (1))
7484 delete_insns_since (last);
7486 /* If that failed, we must use a conservative two-insn sequence.
7488 Use a move to copy one operand into the reload register. Prefer
7489 to reload a constant, MEM or pseudo since the move patterns can
7490 handle an arbitrary operand. If OP1 is not a constant, MEM or
7491 pseudo and OP1 is not a valid operand for an add instruction, then
7494 After reloading one of the operands into the reload register, add
7495 the reload register to the output register.
7497 If there is another way to do this for a specific machine, a
7498 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7501 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7503 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7504 || (GET_CODE (op1) == REG
7505 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7506 || (code != CODE_FOR_nothing
7507 && ! ((*insn_data[code].operand[2].predicate)
7508 (op1, insn_data[code].operand[2].mode))))
7509 tem = op0, op0 = op1, op1 = tem;
7511 gen_reload (out, op0, opnum, type);
7513 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7514 This fixes a problem on the 32K where the stack pointer cannot
7515 be used as an operand of an add insn. */
7517 if (rtx_equal_p (op0, op1))
7520 insn = emit_insn (gen_add2_insn (out, op1));
7522 /* If that failed, copy the address register to the reload register.
7523 Then add the constant to the reload register. */
7525 code = recog_memoized (insn);
7529 extract_insn (insn);
7530 /* We want constrain operands to treat this insn strictly in
7531 its validity determination, i.e., the way it would after reload
7533 if (constrain_operands (1))
7535 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7537 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7542 delete_insns_since (last);
7544 gen_reload (out, op1, opnum, type);
7545 insn = emit_insn (gen_add2_insn (out, op0));
7546 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7549 #ifdef SECONDARY_MEMORY_NEEDED
7550 /* If we need a memory location to do the move, do it that way. */
7551 else if ((GET_CODE (in) == REG || GET_CODE (in) == SUBREG)
7552 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7553 && (GET_CODE (out) == REG || GET_CODE (out) == SUBREG)
7554 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7555 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7556 REGNO_REG_CLASS (reg_or_subregno (out)),
7559 /* Get the memory to use and rewrite both registers to its mode. */
7560 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7562 if (GET_MODE (loc) != GET_MODE (out))
7563 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7565 if (GET_MODE (loc) != GET_MODE (in))
7566 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7568 gen_reload (loc, in, opnum, type);
7569 gen_reload (out, loc, opnum, type);
7573 /* If IN is a simple operand, use gen_move_insn. */
7574 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7575 emit_insn (gen_move_insn (out, in));
7577 #ifdef HAVE_reload_load_address
7578 else if (HAVE_reload_load_address)
7579 emit_insn (gen_reload_load_address (out, in));
7582 /* Otherwise, just write (set OUT IN) and hope for the best. */
7584 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7586 /* Return the first insn emitted.
7587 We can not just return get_last_insn, because there may have
7588 been multiple instructions emitted. Also note that gen_move_insn may
7589 emit more than one insn itself, so we can not assume that there is one
7590 insn emitted per emit_insn_before call. */
7592 return last ? NEXT_INSN (last) : get_insns ();
7595 /* Delete a previously made output-reload whose result we now believe
7596 is not needed. First we double-check.
7598 INSN is the insn now being processed.
7599 LAST_RELOAD_REG is the hard register number for which we want to delete
7600 the last output reload.
7601 J is the reload-number that originally used REG. The caller has made
7602 certain that reload J doesn't use REG any longer for input. */
7605 delete_output_reload (insn, j, last_reload_reg)
7608 int last_reload_reg;
7610 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7611 rtx reg = spill_reg_stored_to[last_reload_reg];
7614 int n_inherited = 0;
7618 /* It is possible that this reload has been only used to set another reload
7619 we eliminated earlier and thus deleted this instruction too. */
7620 if (INSN_DELETED_P (output_reload_insn))
7623 /* Get the raw pseudo-register referred to. */
7625 while (GET_CODE (reg) == SUBREG)
7626 reg = SUBREG_REG (reg);
7627 substed = reg_equiv_memory_loc[REGNO (reg)];
7629 /* This is unsafe if the operand occurs more often in the current
7630 insn than it is inherited. */
7631 for (k = n_reloads - 1; k >= 0; k--)
7633 rtx reg2 = rld[k].in;
7636 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7637 reg2 = rld[k].in_reg;
7639 if (rld[k].out && ! rld[k].out_reg)
7640 reg2 = XEXP (rld[k].in_reg, 0);
7642 while (GET_CODE (reg2) == SUBREG)
7643 reg2 = SUBREG_REG (reg2);
7644 if (rtx_equal_p (reg2, reg))
7646 if (reload_inherited[k] || reload_override_in[k] || k == j)
7649 reg2 = rld[k].out_reg;
7652 while (GET_CODE (reg2) == SUBREG)
7653 reg2 = XEXP (reg2, 0);
7654 if (rtx_equal_p (reg2, reg))
7661 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7663 n_occurrences += count_occurrences (PATTERN (insn),
7664 eliminate_regs (substed, 0,
7666 if (n_occurrences > n_inherited)
7669 /* If the pseudo-reg we are reloading is no longer referenced
7670 anywhere between the store into it and here,
7671 and no jumps or labels intervene, then the value can get
7672 here through the reload reg alone.
7673 Otherwise, give up--return. */
7674 for (i1 = NEXT_INSN (output_reload_insn);
7675 i1 != insn; i1 = NEXT_INSN (i1))
7677 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7679 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7680 && reg_mentioned_p (reg, PATTERN (i1)))
7682 /* If this is USE in front of INSN, we only have to check that
7683 there are no more references than accounted for by inheritance. */
7684 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7686 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7687 i1 = NEXT_INSN (i1);
7689 if (n_occurrences <= n_inherited && i1 == insn)
7695 /* We will be deleting the insn. Remove the spill reg information. */
7696 for (k = HARD_REGNO_NREGS (last_reload_reg, GET_MODE (reg)); k-- > 0; )
7698 spill_reg_store[last_reload_reg + k] = 0;
7699 spill_reg_stored_to[last_reload_reg + k] = 0;
7702 /* The caller has already checked that REG dies or is set in INSN.
7703 It has also checked that we are optimizing, and thus some
7704 inaccuracies in the debugging information are acceptable.
7705 So we could just delete output_reload_insn. But in some cases
7706 we can improve the debugging information without sacrificing
7707 optimization - maybe even improving the code: See if the pseudo
7708 reg has been completely replaced with reload regs. If so, delete
7709 the store insn and forget we had a stack slot for the pseudo. */
7710 if (rld[j].out != rld[j].in
7711 && REG_N_DEATHS (REGNO (reg)) == 1
7712 && REG_N_SETS (REGNO (reg)) == 1
7713 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7714 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7718 /* We know that it was used only between here and the beginning of
7719 the current basic block. (We also know that the last use before
7720 INSN was the output reload we are thinking of deleting, but never
7721 mind that.) Search that range; see if any ref remains. */
7722 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7724 rtx set = single_set (i2);
7726 /* Uses which just store in the pseudo don't count,
7727 since if they are the only uses, they are dead. */
7728 if (set != 0 && SET_DEST (set) == reg)
7730 if (GET_CODE (i2) == CODE_LABEL
7731 || GET_CODE (i2) == JUMP_INSN)
7733 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7734 && reg_mentioned_p (reg, PATTERN (i2)))
7736 /* Some other ref remains; just delete the output reload we
7738 delete_address_reloads (output_reload_insn, insn);
7739 delete_insn (output_reload_insn);
7744 /* Delete the now-dead stores into this pseudo. Note that this
7745 loop also takes care of deleting output_reload_insn. */
7746 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7748 rtx set = single_set (i2);
7750 if (set != 0 && SET_DEST (set) == reg)
7752 delete_address_reloads (i2, insn);
7755 if (GET_CODE (i2) == CODE_LABEL
7756 || GET_CODE (i2) == JUMP_INSN)
7760 /* For the debugging info, say the pseudo lives in this reload reg. */
7761 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7762 alter_reg (REGNO (reg), -1);
7766 delete_address_reloads (output_reload_insn, insn);
7767 delete_insn (output_reload_insn);
7771 /* We are going to delete DEAD_INSN. Recursively delete loads of
7772 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7773 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7775 delete_address_reloads (dead_insn, current_insn)
7776 rtx dead_insn, current_insn;
7778 rtx set = single_set (dead_insn);
7779 rtx set2, dst, prev, next;
7782 rtx dst = SET_DEST (set);
7783 if (GET_CODE (dst) == MEM)
7784 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7786 /* If we deleted the store from a reloaded post_{in,de}c expression,
7787 we can delete the matching adds. */
7788 prev = PREV_INSN (dead_insn);
7789 next = NEXT_INSN (dead_insn);
7790 if (! prev || ! next)
7792 set = single_set (next);
7793 set2 = single_set (prev);
7795 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7796 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7797 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7799 dst = SET_DEST (set);
7800 if (! rtx_equal_p (dst, SET_DEST (set2))
7801 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7802 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7803 || (INTVAL (XEXP (SET_SRC (set), 1))
7804 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7806 delete_related_insns (prev);
7807 delete_related_insns (next);
7810 /* Subfunction of delete_address_reloads: process registers found in X. */
7812 delete_address_reloads_1 (dead_insn, x, current_insn)
7813 rtx dead_insn, x, current_insn;
7815 rtx prev, set, dst, i2;
7817 enum rtx_code code = GET_CODE (x);
7821 const char *fmt = GET_RTX_FORMAT (code);
7822 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7825 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7826 else if (fmt[i] == 'E')
7828 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7829 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7836 if (spill_reg_order[REGNO (x)] < 0)
7839 /* Scan backwards for the insn that sets x. This might be a way back due
7841 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7843 code = GET_CODE (prev);
7844 if (code == CODE_LABEL || code == JUMP_INSN)
7846 if (GET_RTX_CLASS (code) != 'i')
7848 if (reg_set_p (x, PATTERN (prev)))
7850 if (reg_referenced_p (x, PATTERN (prev)))
7853 if (! prev || INSN_UID (prev) < reload_first_uid)
7855 /* Check that PREV only sets the reload register. */
7856 set = single_set (prev);
7859 dst = SET_DEST (set);
7860 if (GET_CODE (dst) != REG
7861 || ! rtx_equal_p (dst, x))
7863 if (! reg_set_p (dst, PATTERN (dead_insn)))
7865 /* Check if DST was used in a later insn -
7866 it might have been inherited. */
7867 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7869 if (GET_CODE (i2) == CODE_LABEL)
7873 if (reg_referenced_p (dst, PATTERN (i2)))
7875 /* If there is a reference to the register in the current insn,
7876 it might be loaded in a non-inherited reload. If no other
7877 reload uses it, that means the register is set before
7879 if (i2 == current_insn)
7881 for (j = n_reloads - 1; j >= 0; j--)
7882 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7883 || reload_override_in[j] == dst)
7885 for (j = n_reloads - 1; j >= 0; j--)
7886 if (rld[j].in && rld[j].reg_rtx == dst)
7893 if (GET_CODE (i2) == JUMP_INSN)
7895 /* If DST is still live at CURRENT_INSN, check if it is used for
7896 any reload. Note that even if CURRENT_INSN sets DST, we still
7897 have to check the reloads. */
7898 if (i2 == current_insn)
7900 for (j = n_reloads - 1; j >= 0; j--)
7901 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7902 || reload_override_in[j] == dst)
7904 /* ??? We can't finish the loop here, because dst might be
7905 allocated to a pseudo in this block if no reload in this
7906 block needs any of the classes containing DST - see
7907 spill_hard_reg. There is no easy way to tell this, so we
7908 have to scan till the end of the basic block. */
7910 if (reg_set_p (dst, PATTERN (i2)))
7914 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7915 reg_reloaded_contents[REGNO (dst)] = -1;
7919 /* Output reload-insns to reload VALUE into RELOADREG.
7920 VALUE is an autoincrement or autodecrement RTX whose operand
7921 is a register or memory location;
7922 so reloading involves incrementing that location.
7923 IN is either identical to VALUE, or some cheaper place to reload from.
7925 INC_AMOUNT is the number to increment or decrement by (always positive).
7926 This cannot be deduced from VALUE.
7928 Return the instruction that stores into RELOADREG. */
7931 inc_for_reload (reloadreg, in, value, inc_amount)
7936 /* REG or MEM to be copied and incremented. */
7937 rtx incloc = XEXP (value, 0);
7938 /* Nonzero if increment after copying. */
7939 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7945 rtx real_in = in == value ? XEXP (in, 0) : in;
7947 /* No hard register is equivalent to this register after
7948 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7949 we could inc/dec that register as well (maybe even using it for
7950 the source), but I'm not sure it's worth worrying about. */
7951 if (GET_CODE (incloc) == REG)
7952 reg_last_reload_reg[REGNO (incloc)] = 0;
7954 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7955 inc_amount = -inc_amount;
7957 inc = GEN_INT (inc_amount);
7959 /* If this is post-increment, first copy the location to the reload reg. */
7960 if (post && real_in != reloadreg)
7961 emit_insn (gen_move_insn (reloadreg, real_in));
7965 /* See if we can directly increment INCLOC. Use a method similar to
7966 that in gen_reload. */
7968 last = get_last_insn ();
7969 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7970 gen_rtx_PLUS (GET_MODE (incloc),
7973 code = recog_memoized (add_insn);
7976 extract_insn (add_insn);
7977 if (constrain_operands (1))
7979 /* If this is a pre-increment and we have incremented the value
7980 where it lives, copy the incremented value to RELOADREG to
7981 be used as an address. */
7984 emit_insn (gen_move_insn (reloadreg, incloc));
7989 delete_insns_since (last);
7992 /* If couldn't do the increment directly, must increment in RELOADREG.
7993 The way we do this depends on whether this is pre- or post-increment.
7994 For pre-increment, copy INCLOC to the reload register, increment it
7995 there, then save back. */
7999 if (in != reloadreg)
8000 emit_insn (gen_move_insn (reloadreg, real_in));
8001 emit_insn (gen_add2_insn (reloadreg, inc));
8002 store = emit_insn (gen_move_insn (incloc, reloadreg));
8007 Because this might be a jump insn or a compare, and because RELOADREG
8008 may not be available after the insn in an input reload, we must do
8009 the incrementation before the insn being reloaded for.
8011 We have already copied IN to RELOADREG. Increment the copy in
8012 RELOADREG, save that back, then decrement RELOADREG so it has
8013 the original value. */
8015 emit_insn (gen_add2_insn (reloadreg, inc));
8016 store = emit_insn (gen_move_insn (incloc, reloadreg));
8017 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8025 add_auto_inc_notes (insn, x)
8029 enum rtx_code code = GET_CODE (x);
8033 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8036 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8040 /* Scan all the operand sub-expressions. */
8041 fmt = GET_RTX_FORMAT (code);
8042 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8045 add_auto_inc_notes (insn, XEXP (x, i));
8046 else if (fmt[i] == 'E')
8047 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8048 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8053 /* Copy EH notes from an insn to its reloads. */
8055 copy_eh_notes (insn, x)
8059 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8062 for (; x != 0; x = NEXT_INSN (x))
8064 if (may_trap_p (PATTERN (x)))
8066 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8072 /* This is used by reload pass, that does emit some instructions after
8073 abnormal calls moving basic block end, but in fact it wants to emit
8074 them on the edge. Looks for abnormal call edges, find backward the
8075 proper call and fix the damage.
8077 Similar handle instructions throwing exceptions internally. */
8079 fixup_abnormal_edges ()
8081 bool inserted = false;
8088 /* Look for cases we are interested in - calls or instructions causing
8090 for (e = bb->succ; e; e = e->succ_next)
8092 if (e->flags & EDGE_ABNORMAL_CALL)
8094 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8095 == (EDGE_ABNORMAL | EDGE_EH))
8098 if (e && GET_CODE (bb->end) != CALL_INSN && !can_throw_internal (bb->end))
8100 rtx insn = bb->end, stop = NEXT_INSN (bb->end);
8102 for (e = bb->succ; e; e = e->succ_next)
8103 if (e->flags & EDGE_FALLTHRU)
8105 /* Get past the new insns generated. Allow notes, as the insns may
8106 be already deleted. */
8107 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE)
8108 && !can_throw_internal (insn)
8109 && insn != bb->head)
8110 insn = PREV_INSN (insn);
8111 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn))
8115 insn = NEXT_INSN (insn);
8116 while (insn && insn != stop)
8118 next = NEXT_INSN (insn);
8123 /* Sometimes there's still the return value USE.
8124 If it's placed after a trapping call (i.e. that
8125 call is the last insn anyway), we have no fallthru
8126 edge. Simply delete this use and don't try to insert
8127 on the non-existent edge. */
8128 if (GET_CODE (PATTERN (insn)) != USE)
8130 /* We're not deleting it, we're moving it. */
8131 INSN_DELETED_P (insn) = 0;
8132 PREV_INSN (insn) = NULL_RTX;
8133 NEXT_INSN (insn) = NULL_RTX;
8135 insert_insn_on_edge (insn, e);
8142 /* We've possibly turned single trapping insn into multiple ones. */
8143 if (flag_non_call_exceptions)
8146 blocks = sbitmap_alloc (last_basic_block);
8147 sbitmap_ones (blocks);
8148 find_many_sub_basic_blocks (blocks);
8151 commit_edge_insertions ();
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