1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 88, 89, 92-6, 1997 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "insn-config.h"
27 #include "insn-flags.h"
28 #include "insn-codes.h"
32 #include "hard-reg-set.h"
35 #include "basic-block.h"
39 /* This file contains the reload pass of the compiler, which is
40 run after register allocation has been done. It checks that
41 each insn is valid (operands required to be in registers really
42 are in registers of the proper class) and fixes up invalid ones
43 by copying values temporarily into registers for the insns
46 The results of register allocation are described by the vector
47 reg_renumber; the insns still contain pseudo regs, but reg_renumber
48 can be used to find which hard reg, if any, a pseudo reg is in.
50 The technique we always use is to free up a few hard regs that are
51 called ``reload regs'', and for each place where a pseudo reg
52 must be in a hard reg, copy it temporarily into one of the reload regs.
54 All the pseudos that were formerly allocated to the hard regs that
55 are now in use as reload regs must be ``spilled''. This means
56 that they go to other hard regs, or to stack slots if no other
57 available hard regs can be found. Spilling can invalidate more
58 insns, requiring additional need for reloads, so we must keep checking
59 until the process stabilizes.
61 For machines with different classes of registers, we must keep track
62 of the register class needed for each reload, and make sure that
63 we allocate enough reload registers of each class.
65 The file reload.c contains the code that checks one insn for
66 validity and reports the reloads that it needs. This file
67 is in charge of scanning the entire rtl code, accumulating the
68 reload needs, spilling, assigning reload registers to use for
69 fixing up each insn, and generating the new insns to copy values
70 into the reload registers. */
73 #ifndef REGISTER_MOVE_COST
74 #define REGISTER_MOVE_COST(x, y) 2
77 #ifndef MEMORY_MOVE_COST
78 #define MEMORY_MOVE_COST(x) 4
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
106 This is used when the address is not valid as a memory address
107 (because its displacement is too big for the machine.) */
108 rtx *reg_equiv_address;
110 /* Element N is the memory slot to which pseudo reg N is equivalent,
111 or zero if pseudo reg N is not equivalent to a memory slot. */
114 /* Widest width in which each pseudo reg is referred to (via subreg). */
115 static int *reg_max_ref_width;
117 /* Element N is the insn that initialized reg N from its equivalent
118 constant or memory slot. */
119 static rtx *reg_equiv_init;
121 /* During reload_as_needed, element N contains the last pseudo regno
122 reloaded into the Nth reload register. This vector is in parallel
123 with spill_regs. If that pseudo reg occupied more than one register,
124 reg_reloaded_contents points to that pseudo for each spill register in
125 use; all of these must remain set for an inheritance to occur. */
126 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
128 /* During reload_as_needed, element N contains the insn for which
129 the Nth reload register was last used. This vector is in parallel
130 with spill_regs, and its contents are significant only when
131 reg_reloaded_contents is significant. */
132 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
134 /* Number of spill-regs so far; number of valid elements of spill_regs. */
137 /* In parallel with spill_regs, contains REG rtx's for those regs.
138 Holds the last rtx used for any given reg, or 0 if it has never
139 been used for spilling yet. This rtx is reused, provided it has
141 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
143 /* In parallel with spill_regs, contains nonzero for a spill reg
144 that was stored after the last time it was used.
145 The precise value is the insn generated to do the store. */
146 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
148 /* This table is the inverse mapping of spill_regs:
149 indexed by hard reg number,
150 it contains the position of that reg in spill_regs,
151 or -1 for something that is not in spill_regs. */
152 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
154 /* This reg set indicates registers that may not be used for retrying global
155 allocation. The registers that may not be used include all spill registers
156 and the frame pointer (if we are using one). */
157 HARD_REG_SET forbidden_regs;
159 /* This reg set indicates registers that are not good for spill registers.
160 They will not be used to complete groups of spill registers. This includes
161 all fixed registers, registers that may be eliminated, and, if
162 SMALL_REGISTER_CLASSES is not defined, registers explicitly used in the rtl.
164 (spill_reg_order prevents these registers from being used to start a
166 static HARD_REG_SET bad_spill_regs;
168 /* Describes order of use of registers for reloading
169 of spilled pseudo-registers. `spills' is the number of
170 elements that are actually valid; new ones are added at the end. */
171 static short spill_regs[FIRST_PSEUDO_REGISTER];
173 /* This reg set indicates those registers that have been used a spill
174 registers. This information is used in reorg.c, to help figure out
175 what registers are live at any point. It is assumed that all spill_regs
176 are dead at every CODE_LABEL. */
178 HARD_REG_SET used_spill_regs;
180 /* Index of last register assigned as a spill register. We allocate in
181 a round-robin fashion. */
183 static int last_spill_reg;
185 /* Describes order of preference for putting regs into spill_regs.
186 Contains the numbers of all the hard regs, in order most preferred first.
187 This order is different for each function.
188 It is set up by order_regs_for_reload.
189 Empty elements at the end contain -1. */
190 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
192 /* 1 for a hard register that appears explicitly in the rtl
193 (for example, function value registers, special registers
194 used by insns, structure value pointer registers). */
195 static char regs_explicitly_used[FIRST_PSEUDO_REGISTER];
197 /* Indicates if a register was counted against the need for
198 groups. 0 means it can count against max_nongroup instead. */
199 static HARD_REG_SET counted_for_groups;
201 /* Indicates if a register was counted against the need for
202 non-groups. 0 means it can become part of a new group.
203 During choose_reload_regs, 1 here means don't use this reg
204 as part of a group, even if it seems to be otherwise ok. */
205 static HARD_REG_SET counted_for_nongroups;
207 /* Indexed by pseudo reg number N,
208 says may not delete stores into the real (memory) home of pseudo N.
209 This is set if we already substituted a memory equivalent in some uses,
210 which happens when we have to eliminate the fp from it. */
211 static char *cannot_omit_stores;
213 /* Nonzero if indirect addressing is supported on the machine; this means
214 that spilling (REG n) does not require reloading it into a register in
215 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
216 value indicates the level of indirect addressing supported, e.g., two
217 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
220 static char spill_indirect_levels;
222 /* Nonzero if indirect addressing is supported when the innermost MEM is
223 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
224 which these are valid is the same as spill_indirect_levels, above. */
226 char indirect_symref_ok;
228 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
230 char double_reg_address_ok;
232 /* Record the stack slot for each spilled hard register. */
234 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
236 /* Width allocated so far for that stack slot. */
238 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
240 /* Indexed by register class and basic block number, nonzero if there is
241 any need for a spill register of that class in that basic block.
242 The pointer is 0 if we did stupid allocation and don't know
243 the structure of basic blocks. */
245 char *basic_block_needs[N_REG_CLASSES];
247 /* First uid used by insns created by reload in this function.
248 Used in find_equiv_reg. */
249 int reload_first_uid;
251 /* Flag set by local-alloc or global-alloc if anything is live in
252 a call-clobbered reg across calls. */
254 int caller_save_needed;
256 /* The register class to use for a base register when reloading an
257 address. This is normally BASE_REG_CLASS, but it may be different
258 when using SMALL_REGISTER_CLASSES and passing parameters in
260 enum reg_class reload_address_base_reg_class;
262 /* The register class to use for an index register when reloading an
263 address. This is normally INDEX_REG_CLASS, but it may be different
264 when using SMALL_REGISTER_CLASSES and passing parameters in
266 enum reg_class reload_address_index_reg_class;
268 /* Set to 1 while reload_as_needed is operating.
269 Required by some machines to handle any generated moves differently. */
271 int reload_in_progress = 0;
273 /* These arrays record the insn_code of insns that may be needed to
274 perform input and output reloads of special objects. They provide a
275 place to pass a scratch register. */
277 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
278 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
280 /* This obstack is used for allocation of rtl during register elimination.
281 The allocated storage can be freed once find_reloads has processed the
284 struct obstack reload_obstack;
285 char *reload_firstobj;
287 #define obstack_chunk_alloc xmalloc
288 #define obstack_chunk_free free
290 /* List of labels that must never be deleted. */
291 extern rtx forced_labels;
293 /* Allocation number table from global register allocation. */
294 extern int *reg_allocno;
296 /* This structure is used to record information about register eliminations.
297 Each array entry describes one possible way of eliminating a register
298 in favor of another. If there is more than one way of eliminating a
299 particular register, the most preferred should be specified first. */
301 static struct elim_table
303 int from; /* Register number to be eliminated. */
304 int to; /* Register number used as replacement. */
305 int initial_offset; /* Initial difference between values. */
306 int can_eliminate; /* Non-zero if this elimination can be done. */
307 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
308 insns made by reload. */
309 int offset; /* Current offset between the two regs. */
310 int max_offset; /* Maximum offset between the two regs. */
311 int previous_offset; /* Offset at end of previous insn. */
312 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
313 rtx from_rtx; /* REG rtx for the register to be eliminated.
314 We cannot simply compare the number since
315 we might then spuriously replace a hard
316 register corresponding to a pseudo
317 assigned to the reg to be eliminated. */
318 rtx to_rtx; /* REG rtx for the replacement. */
321 /* If a set of eliminable registers was specified, define the table from it.
322 Otherwise, default to the normal case of the frame pointer being
323 replaced by the stack pointer. */
325 #ifdef ELIMINABLE_REGS
328 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
331 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0])
333 /* Record the number of pending eliminations that have an offset not equal
334 to their initial offset. If non-zero, we use a new copy of each
335 replacement result in any insns encountered. */
336 static int num_not_at_initial_offset;
338 /* Count the number of registers that we may be able to eliminate. */
339 static int num_eliminable;
341 /* For each label, we record the offset of each elimination. If we reach
342 a label by more than one path and an offset differs, we cannot do the
343 elimination. This information is indexed by the number of the label.
344 The first table is an array of flags that records whether we have yet
345 encountered a label and the second table is an array of arrays, one
346 entry in the latter array for each elimination. */
348 static char *offsets_known_at;
349 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
351 /* Number of labels in the current function. */
353 static int num_labels;
355 struct hard_reg_n_uses { int regno; int uses; };
357 static int possible_group_p PROTO((int, int *));
358 static void count_possible_groups PROTO((int *, enum machine_mode *,
360 static int modes_equiv_for_class_p PROTO((enum machine_mode,
363 static void spill_failure PROTO((rtx));
364 static int new_spill_reg PROTO((int, int, int *, int *, int,
366 static void delete_dead_insn PROTO((rtx));
367 static void alter_reg PROTO((int, int));
368 static void mark_scratch_live PROTO((rtx));
369 static void set_label_offsets PROTO((rtx, rtx, int));
370 static int eliminate_regs_in_insn PROTO((rtx, int));
371 static void mark_not_eliminable PROTO((rtx, rtx));
372 static int spill_hard_reg PROTO((int, int, FILE *, int));
373 static void scan_paradoxical_subregs PROTO((rtx));
374 static int hard_reg_use_compare PROTO((const GENERIC_PTR, const GENERIC_PTR));
375 static void order_regs_for_reload PROTO((int));
376 static int compare_spill_regs PROTO((const GENERIC_PTR, const GENERIC_PTR));
377 static void reload_as_needed PROTO((rtx, int));
378 static void forget_old_reloads_1 PROTO((rtx, rtx));
379 static int reload_reg_class_lower PROTO((const GENERIC_PTR, const GENERIC_PTR));
380 static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
382 static void clear_reload_reg_in_use PROTO((int, int, enum reload_type,
384 static int reload_reg_free_p PROTO((int, int, enum reload_type));
385 static int reload_reg_free_before_p PROTO((int, int, enum reload_type));
386 static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
387 static int reloads_conflict PROTO((int, int));
388 static int allocate_reload_reg PROTO((int, rtx, int, int));
389 static void choose_reload_regs PROTO((rtx, rtx));
390 static void merge_assigned_reloads PROTO((rtx));
391 static void emit_reload_insns PROTO((rtx));
392 static void delete_output_reload PROTO((rtx, int, rtx));
393 static void inc_for_reload PROTO((rtx, rtx, int));
394 static int constraint_accepts_reg_p PROTO((char *, rtx));
395 static int count_occurrences PROTO((rtx, rtx));
397 /* Initialize the reload pass once per compilation. */
404 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
405 Set spill_indirect_levels to the number of levels such addressing is
406 permitted, zero if it is not permitted at all. */
409 = gen_rtx (MEM, Pmode,
410 gen_rtx (PLUS, Pmode,
411 gen_rtx (REG, Pmode, LAST_VIRTUAL_REGISTER + 1),
413 spill_indirect_levels = 0;
415 while (memory_address_p (QImode, tem))
417 spill_indirect_levels++;
418 tem = gen_rtx (MEM, Pmode, tem);
421 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
423 tem = gen_rtx (MEM, Pmode, gen_rtx (SYMBOL_REF, Pmode, "foo"));
424 indirect_symref_ok = memory_address_p (QImode, tem);
426 /* See if reg+reg is a valid (and offsettable) address. */
428 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
430 tem = gen_rtx (PLUS, Pmode,
431 gen_rtx (REG, Pmode, HARD_FRAME_POINTER_REGNUM),
432 gen_rtx (REG, Pmode, i));
433 /* This way, we make sure that reg+reg is an offsettable address. */
434 tem = plus_constant (tem, 4);
436 if (memory_address_p (QImode, tem))
438 double_reg_address_ok = 1;
443 /* Initialize obstack for our rtl allocation. */
444 gcc_obstack_init (&reload_obstack);
445 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
447 /* Decide which register class should be used when reloading
448 addresses. If we are using SMALL_REGISTER_CLASSES, and any
449 parameters are passed in registers, then we do not want to use
450 those registers when reloading an address. Otherwise, if a
451 function argument needs a reload, we may wind up clobbering
452 another argument to the function which was already computed. If
453 we find a subset class which simply avoids those registers, we
454 use it instead. ??? It would be better to only use the
455 restricted class when we actually are loading function arguments,
456 but that is hard to determine. */
457 reload_address_base_reg_class = BASE_REG_CLASS;
458 reload_address_index_reg_class = INDEX_REG_CLASS;
459 #ifdef SMALL_REGISTER_CLASSES
460 if (SMALL_REGISTER_CLASSES)
463 HARD_REG_SET base, index;
466 COPY_HARD_REG_SET (base, reg_class_contents[BASE_REG_CLASS]);
467 COPY_HARD_REG_SET (index, reg_class_contents[INDEX_REG_CLASS]);
468 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
470 if (FUNCTION_ARG_REGNO_P (regno))
472 CLEAR_HARD_REG_BIT (base, regno);
473 CLEAR_HARD_REG_BIT (index, regno);
477 GO_IF_HARD_REG_EQUAL (base, reg_class_contents[BASE_REG_CLASS],
479 for (p = reg_class_subclasses[BASE_REG_CLASS];
480 *p != LIM_REG_CLASSES;
483 GO_IF_HARD_REG_EQUAL (base, reg_class_contents[*p], usebase);
486 reload_address_base_reg_class = *p;
491 GO_IF_HARD_REG_EQUAL (index, reg_class_contents[INDEX_REG_CLASS],
493 for (p = reg_class_subclasses[INDEX_REG_CLASS];
494 *p != LIM_REG_CLASSES;
497 GO_IF_HARD_REG_EQUAL (index, reg_class_contents[*p], useindex);
500 reload_address_index_reg_class = *p;
505 #endif /* SMALL_REGISTER_CLASSES */
508 /* Main entry point for the reload pass.
510 FIRST is the first insn of the function being compiled.
512 GLOBAL nonzero means we were called from global_alloc
513 and should attempt to reallocate any pseudoregs that we
514 displace from hard regs we will use for reloads.
515 If GLOBAL is zero, we do not have enough information to do that,
516 so any pseudo reg that is spilled must go to the stack.
518 DUMPFILE is the global-reg debugging dump file stream, or 0.
519 If it is nonzero, messages are written to it to describe
520 which registers are seized as reload regs, which pseudo regs
521 are spilled from them, and where the pseudo regs are reallocated to.
523 Return value is nonzero if reload failed
524 and we must not do any more for this function. */
527 reload (first, global, dumpfile)
533 register int i, j, k;
535 register struct elim_table *ep;
537 int something_changed;
538 int something_needs_reloads;
539 int something_needs_elimination;
540 int new_basic_block_needs;
541 enum reg_class caller_save_spill_class = NO_REGS;
542 int caller_save_group_size = 1;
544 /* Nonzero means we couldn't get enough spill regs. */
547 /* The basic block number currently being processed for INSN. */
550 /* Make sure even insns with volatile mem refs are recognizable. */
553 /* Enable find_equiv_reg to distinguish insns made by reload. */
554 reload_first_uid = get_max_uid ();
556 for (i = 0; i < N_REG_CLASSES; i++)
557 basic_block_needs[i] = 0;
559 #ifdef SECONDARY_MEMORY_NEEDED
560 /* Initialize the secondary memory table. */
561 clear_secondary_mem ();
564 /* Remember which hard regs appear explicitly
565 before we merge into `regs_ever_live' the ones in which
566 pseudo regs have been allocated. */
567 bcopy (regs_ever_live, regs_explicitly_used, sizeof regs_ever_live);
569 /* We don't have a stack slot for any spill reg yet. */
570 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
571 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
573 /* Initialize the save area information for caller-save, in case some
577 /* Compute which hard registers are now in use
578 as homes for pseudo registers.
579 This is done here rather than (eg) in global_alloc
580 because this point is reached even if not optimizing. */
582 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
585 for (i = 0; i < scratch_list_length; i++)
587 mark_scratch_live (scratch_list[i]);
589 /* Make sure that the last insn in the chain
590 is not something that needs reloading. */
591 emit_note (NULL_PTR, NOTE_INSN_DELETED);
593 /* Find all the pseudo registers that didn't get hard regs
594 but do have known equivalent constants or memory slots.
595 These include parameters (known equivalent to parameter slots)
596 and cse'd or loop-moved constant memory addresses.
598 Record constant equivalents in reg_equiv_constant
599 so they will be substituted by find_reloads.
600 Record memory equivalents in reg_mem_equiv so they can
601 be substituted eventually by altering the REG-rtx's. */
603 reg_equiv_constant = (rtx *) alloca (max_regno * sizeof (rtx));
604 bzero ((char *) reg_equiv_constant, max_regno * sizeof (rtx));
605 reg_equiv_memory_loc = (rtx *) alloca (max_regno * sizeof (rtx));
606 bzero ((char *) reg_equiv_memory_loc, max_regno * sizeof (rtx));
607 reg_equiv_mem = (rtx *) alloca (max_regno * sizeof (rtx));
608 bzero ((char *) reg_equiv_mem, max_regno * sizeof (rtx));
609 reg_equiv_init = (rtx *) alloca (max_regno * sizeof (rtx));
610 bzero ((char *) reg_equiv_init, max_regno * sizeof (rtx));
611 reg_equiv_address = (rtx *) alloca (max_regno * sizeof (rtx));
612 bzero ((char *) reg_equiv_address, max_regno * sizeof (rtx));
613 reg_max_ref_width = (int *) alloca (max_regno * sizeof (int));
614 bzero ((char *) reg_max_ref_width, max_regno * sizeof (int));
615 cannot_omit_stores = (char *) alloca (max_regno);
616 bzero (cannot_omit_stores, max_regno);
618 #ifdef SMALL_REGISTER_CLASSES
619 if (SMALL_REGISTER_CLASSES)
620 CLEAR_HARD_REG_SET (forbidden_regs);
623 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
624 Also find all paradoxical subregs and find largest such for each pseudo.
625 On machines with small register classes, record hard registers that
626 are used for user variables. These can never be used for spills.
627 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
628 caller-saved registers must be marked live. */
630 for (insn = first; insn; insn = NEXT_INSN (insn))
632 rtx set = single_set (insn);
634 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
635 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
636 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
637 if (! call_used_regs[i])
638 regs_ever_live[i] = 1;
640 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
642 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
644 #ifdef LEGITIMATE_PIC_OPERAND_P
645 && (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic
646 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
650 rtx x = XEXP (note, 0);
651 i = REGNO (SET_DEST (set));
652 if (i > LAST_VIRTUAL_REGISTER)
654 if (GET_CODE (x) == MEM)
655 reg_equiv_memory_loc[i] = x;
656 else if (CONSTANT_P (x))
658 if (LEGITIMATE_CONSTANT_P (x))
659 reg_equiv_constant[i] = x;
661 reg_equiv_memory_loc[i]
662 = force_const_mem (GET_MODE (SET_DEST (set)), x);
667 /* If this register is being made equivalent to a MEM
668 and the MEM is not SET_SRC, the equivalencing insn
669 is one with the MEM as a SET_DEST and it occurs later.
670 So don't mark this insn now. */
671 if (GET_CODE (x) != MEM
672 || rtx_equal_p (SET_SRC (set), x))
673 reg_equiv_init[i] = insn;
678 /* If this insn is setting a MEM from a register equivalent to it,
679 this is the equivalencing insn. */
680 else if (set && GET_CODE (SET_DEST (set)) == MEM
681 && GET_CODE (SET_SRC (set)) == REG
682 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
683 && rtx_equal_p (SET_DEST (set),
684 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
685 reg_equiv_init[REGNO (SET_SRC (set))] = insn;
687 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
688 scan_paradoxical_subregs (PATTERN (insn));
691 /* Does this function require a frame pointer? */
693 frame_pointer_needed = (! flag_omit_frame_pointer
694 #ifdef EXIT_IGNORE_STACK
695 /* ?? If EXIT_IGNORE_STACK is set, we will not save
696 and restore sp for alloca. So we can't eliminate
697 the frame pointer in that case. At some point,
698 we should improve this by emitting the
699 sp-adjusting insns for this case. */
700 || (current_function_calls_alloca
701 && EXIT_IGNORE_STACK)
703 || FRAME_POINTER_REQUIRED);
707 /* Initialize the table of registers to eliminate. The way we do this
708 depends on how the eliminable registers were defined. */
709 #ifdef ELIMINABLE_REGS
710 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
712 ep->can_eliminate = ep->can_eliminate_previous
713 = (CAN_ELIMINATE (ep->from, ep->to)
714 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
717 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
718 = ! frame_pointer_needed;
721 /* Count the number of eliminable registers and build the FROM and TO
722 REG rtx's. Note that code in gen_rtx will cause, e.g.,
723 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
724 We depend on this. */
725 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
727 num_eliminable += ep->can_eliminate;
728 ep->from_rtx = gen_rtx (REG, Pmode, ep->from);
729 ep->to_rtx = gen_rtx (REG, Pmode, ep->to);
732 num_labels = max_label_num () - get_first_label_num ();
734 /* Allocate the tables used to store offset information at labels. */
735 offsets_known_at = (char *) alloca (num_labels);
737 = (int (*)[NUM_ELIMINABLE_REGS])
738 alloca (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
740 offsets_known_at -= get_first_label_num ();
741 offsets_at -= get_first_label_num ();
743 /* Alter each pseudo-reg rtx to contain its hard reg number.
744 Assign stack slots to the pseudos that lack hard regs or equivalents.
745 Do not touch virtual registers. */
747 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
750 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done here
751 because the stack size may be a part of the offset computation for
752 register elimination. */
753 assign_stack_local (BLKmode, 0, 0);
755 /* If we have some registers we think can be eliminated, scan all insns to
756 see if there is an insn that sets one of these registers to something
757 other than itself plus a constant. If so, the register cannot be
758 eliminated. Doing this scan here eliminates an extra pass through the
759 main reload loop in the most common case where register elimination
761 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
762 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
763 || GET_CODE (insn) == CALL_INSN)
764 note_stores (PATTERN (insn), mark_not_eliminable);
766 #ifndef REGISTER_CONSTRAINTS
767 /* If all the pseudo regs have hard regs,
768 except for those that are never referenced,
769 we know that no reloads are needed. */
770 /* But that is not true if there are register constraints, since
771 in that case some pseudos might be in the wrong kind of hard reg. */
773 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
774 if (reg_renumber[i] == -1 && reg_n_refs[i] != 0)
777 if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
781 /* Compute the order of preference for hard registers to spill.
782 Store them by decreasing preference in potential_reload_regs. */
784 order_regs_for_reload (global);
786 /* So far, no hard regs have been spilled. */
788 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
789 spill_reg_order[i] = -1;
791 /* Initialize to -1, which means take the first spill register. */
794 /* On most machines, we can't use any register explicitly used in the
795 rtl as a spill register. But on some, we have to. Those will have
796 taken care to keep the life of hard regs as short as possible. */
798 #ifdef SMALL_REGISTER_CLASSES
799 if (! SMALL_REGISTER_CLASSES)
801 COPY_HARD_REG_SET (forbidden_regs, bad_spill_regs);
803 /* Spill any hard regs that we know we can't eliminate. */
804 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
805 if (! ep->can_eliminate)
806 spill_hard_reg (ep->from, global, dumpfile, 1);
808 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
809 if (frame_pointer_needed)
810 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, global, dumpfile, 1);
814 for (i = 0; i < N_REG_CLASSES; i++)
816 basic_block_needs[i] = (char *) alloca (n_basic_blocks);
817 bzero (basic_block_needs[i], n_basic_blocks);
820 /* From now on, we need to emit any moves without making new pseudos. */
821 reload_in_progress = 1;
823 /* This loop scans the entire function each go-round
824 and repeats until one repetition spills no additional hard regs. */
826 /* This flag is set when a pseudo reg is spilled,
827 to require another pass. Note that getting an additional reload
828 reg does not necessarily imply any pseudo reg was spilled;
829 sometimes we find a reload reg that no pseudo reg was allocated in. */
830 something_changed = 1;
831 /* This flag is set if there are any insns that require reloading. */
832 something_needs_reloads = 0;
833 /* This flag is set if there are any insns that require register
835 something_needs_elimination = 0;
836 while (something_changed)
840 /* For each class, number of reload regs needed in that class.
841 This is the maximum over all insns of the needs in that class
842 of the individual insn. */
843 int max_needs[N_REG_CLASSES];
844 /* For each class, size of group of consecutive regs
845 that is needed for the reloads of this class. */
846 int group_size[N_REG_CLASSES];
847 /* For each class, max number of consecutive groups needed.
848 (Each group contains group_size[CLASS] consecutive registers.) */
849 int max_groups[N_REG_CLASSES];
850 /* For each class, max number needed of regs that don't belong
851 to any of the groups. */
852 int max_nongroups[N_REG_CLASSES];
853 /* For each class, the machine mode which requires consecutive
854 groups of regs of that class.
855 If two different modes ever require groups of one class,
856 they must be the same size and equally restrictive for that class,
857 otherwise we can't handle the complexity. */
858 enum machine_mode group_mode[N_REG_CLASSES];
859 /* Record the insn where each maximum need is first found. */
860 rtx max_needs_insn[N_REG_CLASSES];
861 rtx max_groups_insn[N_REG_CLASSES];
862 rtx max_nongroups_insn[N_REG_CLASSES];
864 HOST_WIDE_INT starting_frame_size = get_frame_size ();
865 int previous_frame_pointer_needed = frame_pointer_needed;
866 static char *reg_class_names[] = REG_CLASS_NAMES;
868 something_changed = 0;
869 bzero ((char *) max_needs, sizeof max_needs);
870 bzero ((char *) max_groups, sizeof max_groups);
871 bzero ((char *) max_nongroups, sizeof max_nongroups);
872 bzero ((char *) max_needs_insn, sizeof max_needs_insn);
873 bzero ((char *) max_groups_insn, sizeof max_groups_insn);
874 bzero ((char *) max_nongroups_insn, sizeof max_nongroups_insn);
875 bzero ((char *) group_size, sizeof group_size);
876 for (i = 0; i < N_REG_CLASSES; i++)
877 group_mode[i] = VOIDmode;
879 /* Keep track of which basic blocks are needing the reloads. */
882 /* Remember whether any element of basic_block_needs
883 changes from 0 to 1 in this pass. */
884 new_basic_block_needs = 0;
886 /* Reset all offsets on eliminable registers to their initial values. */
887 #ifdef ELIMINABLE_REGS
888 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
890 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
891 ep->previous_offset = ep->offset
892 = ep->max_offset = ep->initial_offset;
895 #ifdef INITIAL_FRAME_POINTER_OFFSET
896 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
898 if (!FRAME_POINTER_REQUIRED)
900 reg_eliminate[0].initial_offset = 0;
902 reg_eliminate[0].previous_offset = reg_eliminate[0].max_offset
903 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
906 num_not_at_initial_offset = 0;
908 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
910 /* Set a known offset for each forced label to be at the initial offset
911 of each elimination. We do this because we assume that all
912 computed jumps occur from a location where each elimination is
913 at its initial offset. */
915 for (x = forced_labels; x; x = XEXP (x, 1))
917 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
919 /* For each pseudo register that has an equivalent location defined,
920 try to eliminate any eliminable registers (such as the frame pointer)
921 assuming initial offsets for the replacement register, which
924 If the resulting location is directly addressable, substitute
925 the MEM we just got directly for the old REG.
927 If it is not addressable but is a constant or the sum of a hard reg
928 and constant, it is probably not addressable because the constant is
929 out of range, in that case record the address; we will generate
930 hairy code to compute the address in a register each time it is
931 needed. Similarly if it is a hard register, but one that is not
932 valid as an address register.
934 If the location is not addressable, but does not have one of the
935 above forms, assign a stack slot. We have to do this to avoid the
936 potential of producing lots of reloads if, e.g., a location involves
937 a pseudo that didn't get a hard register and has an equivalent memory
938 location that also involves a pseudo that didn't get a hard register.
940 Perhaps at some point we will improve reload_when_needed handling
941 so this problem goes away. But that's very hairy. */
943 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
944 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
946 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
948 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
950 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
951 else if (CONSTANT_P (XEXP (x, 0))
952 || (GET_CODE (XEXP (x, 0)) == REG
953 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
954 || (GET_CODE (XEXP (x, 0)) == PLUS
955 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
956 && (REGNO (XEXP (XEXP (x, 0), 0))
957 < FIRST_PSEUDO_REGISTER)
958 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
959 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
962 /* Make a new stack slot. Then indicate that something
963 changed so we go back and recompute offsets for
964 eliminable registers because the allocation of memory
965 below might change some offset. reg_equiv_{mem,address}
966 will be set up for this pseudo on the next pass around
968 reg_equiv_memory_loc[i] = 0;
969 reg_equiv_init[i] = 0;
971 something_changed = 1;
975 /* If we allocated another pseudo to the stack, redo elimination
977 if (something_changed)
980 /* If caller-saves needs a group, initialize the group to include
981 the size and mode required for caller-saves. */
983 if (caller_save_group_size > 1)
985 group_mode[(int) caller_save_spill_class] = Pmode;
986 group_size[(int) caller_save_spill_class] = caller_save_group_size;
989 /* Compute the most additional registers needed by any instruction.
990 Collect information separately for each class of regs. */
992 for (insn = first; insn; insn = NEXT_INSN (insn))
994 if (global && this_block + 1 < n_basic_blocks
995 && insn == basic_block_head[this_block+1])
998 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which
999 might include REG_LABEL), we need to see what effects this
1000 has on the known offsets at labels. */
1002 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1003 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1004 && REG_NOTES (insn) != 0))
1005 set_label_offsets (insn, insn, 0);
1007 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1009 /* Nonzero means don't use a reload reg that overlaps
1010 the place where a function value can be returned. */
1011 rtx avoid_return_reg = 0;
1013 rtx old_body = PATTERN (insn);
1014 int old_code = INSN_CODE (insn);
1015 rtx old_notes = REG_NOTES (insn);
1016 int did_elimination = 0;
1018 /* To compute the number of reload registers of each class
1019 needed for an insn, we must simulate what choose_reload_regs
1020 can do. We do this by splitting an insn into an "input" and
1021 an "output" part. RELOAD_OTHER reloads are used in both.
1022 The input part uses those reloads, RELOAD_FOR_INPUT reloads,
1023 which must be live over the entire input section of reloads,
1024 and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
1025 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the
1028 The registers needed for output are RELOAD_OTHER and
1029 RELOAD_FOR_OUTPUT, which are live for the entire output
1030 portion, and the maximum of all the RELOAD_FOR_OUTPUT_ADDRESS
1031 reloads for each operand.
1033 The total number of registers needed is the maximum of the
1034 inputs and outputs. */
1038 /* [0] is normal, [1] is nongroup. */
1039 int regs[2][N_REG_CLASSES];
1040 int groups[N_REG_CLASSES];
1043 /* Each `struct needs' corresponds to one RELOAD_... type. */
1047 struct needs output;
1049 struct needs other_addr;
1050 struct needs op_addr;
1051 struct needs op_addr_reload;
1052 struct needs in_addr[MAX_RECOG_OPERANDS];
1053 struct needs out_addr[MAX_RECOG_OPERANDS];
1056 /* If needed, eliminate any eliminable registers. */
1058 did_elimination = eliminate_regs_in_insn (insn, 0);
1060 #ifdef SMALL_REGISTER_CLASSES
1061 /* Set avoid_return_reg if this is an insn
1062 that might use the value of a function call. */
1063 if (SMALL_REGISTER_CLASSES && GET_CODE (insn) == CALL_INSN)
1065 if (GET_CODE (PATTERN (insn)) == SET)
1066 after_call = SET_DEST (PATTERN (insn));
1067 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1068 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1069 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
1073 else if (SMALL_REGISTER_CLASSES
1075 && !(GET_CODE (PATTERN (insn)) == SET
1076 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
1078 if (reg_referenced_p (after_call, PATTERN (insn)))
1079 avoid_return_reg = after_call;
1082 #endif /* SMALL_REGISTER_CLASSES */
1084 /* Analyze the instruction. */
1085 find_reloads (insn, 0, spill_indirect_levels, global,
1088 /* Remember for later shortcuts which insns had any reloads or
1089 register eliminations.
1091 One might think that it would be worthwhile to mark insns
1092 that need register replacements but not reloads, but this is
1093 not safe because find_reloads may do some manipulation of
1094 the insn (such as swapping commutative operands), which would
1095 be lost when we restore the old pattern after register
1096 replacement. So the actions of find_reloads must be redone in
1097 subsequent passes or in reload_as_needed.
1099 However, it is safe to mark insns that need reloads
1100 but not register replacement. */
1102 PUT_MODE (insn, (did_elimination ? QImode
1103 : n_reloads ? HImode
1104 : GET_MODE (insn) == DImode ? DImode
1107 /* Discard any register replacements done. */
1108 if (did_elimination)
1110 obstack_free (&reload_obstack, reload_firstobj);
1111 PATTERN (insn) = old_body;
1112 INSN_CODE (insn) = old_code;
1113 REG_NOTES (insn) = old_notes;
1114 something_needs_elimination = 1;
1117 /* If this insn has no reloads, we need not do anything except
1118 in the case of a CALL_INSN when we have caller-saves and
1119 caller-save needs reloads. */
1122 && ! (GET_CODE (insn) == CALL_INSN
1123 && caller_save_spill_class != NO_REGS))
1126 something_needs_reloads = 1;
1127 bzero ((char *) &insn_needs, sizeof insn_needs);
1129 /* Count each reload once in every class
1130 containing the reload's own class. */
1132 for (i = 0; i < n_reloads; i++)
1134 register enum reg_class *p;
1135 enum reg_class class = reload_reg_class[i];
1137 enum machine_mode mode;
1139 struct needs *this_needs;
1141 /* Don't count the dummy reloads, for which one of the
1142 regs mentioned in the insn can be used for reloading.
1143 Don't count optional reloads.
1144 Don't count reloads that got combined with others. */
1145 if (reload_reg_rtx[i] != 0
1146 || reload_optional[i] != 0
1147 || (reload_out[i] == 0 && reload_in[i] == 0
1148 && ! reload_secondary_p[i]))
1151 /* Show that a reload register of this class is needed
1152 in this basic block. We do not use insn_needs and
1153 insn_groups because they are overly conservative for
1155 if (global && ! basic_block_needs[(int) class][this_block])
1157 basic_block_needs[(int) class][this_block] = 1;
1158 new_basic_block_needs = 1;
1162 mode = reload_inmode[i];
1163 if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1164 mode = reload_outmode[i];
1165 size = CLASS_MAX_NREGS (class, mode);
1167 /* If this class doesn't want a group, determine if we have
1168 a nongroup need or a regular need. We have a nongroup
1169 need if this reload conflicts with a group reload whose
1170 class intersects with this reload's class. */
1174 for (j = 0; j < n_reloads; j++)
1175 if ((CLASS_MAX_NREGS (reload_reg_class[j],
1176 (GET_MODE_SIZE (reload_outmode[j])
1177 > GET_MODE_SIZE (reload_inmode[j]))
1181 && (!reload_optional[j])
1182 && (reload_in[j] != 0 || reload_out[j] != 0
1183 || reload_secondary_p[j])
1184 && reloads_conflict (i, j)
1185 && reg_classes_intersect_p (class,
1186 reload_reg_class[j]))
1192 /* Decide which time-of-use to count this reload for. */
1193 switch (reload_when_needed[i])
1196 this_needs = &insn_needs.other;
1198 case RELOAD_FOR_INPUT:
1199 this_needs = &insn_needs.input;
1201 case RELOAD_FOR_OUTPUT:
1202 this_needs = &insn_needs.output;
1204 case RELOAD_FOR_INSN:
1205 this_needs = &insn_needs.insn;
1207 case RELOAD_FOR_OTHER_ADDRESS:
1208 this_needs = &insn_needs.other_addr;
1210 case RELOAD_FOR_INPUT_ADDRESS:
1211 this_needs = &insn_needs.in_addr[reload_opnum[i]];
1213 case RELOAD_FOR_OUTPUT_ADDRESS:
1214 this_needs = &insn_needs.out_addr[reload_opnum[i]];
1216 case RELOAD_FOR_OPERAND_ADDRESS:
1217 this_needs = &insn_needs.op_addr;
1219 case RELOAD_FOR_OPADDR_ADDR:
1220 this_needs = &insn_needs.op_addr_reload;
1226 enum machine_mode other_mode, allocate_mode;
1228 /* Count number of groups needed separately from
1229 number of individual regs needed. */
1230 this_needs->groups[(int) class]++;
1231 p = reg_class_superclasses[(int) class];
1232 while (*p != LIM_REG_CLASSES)
1233 this_needs->groups[(int) *p++]++;
1235 /* Record size and mode of a group of this class. */
1236 /* If more than one size group is needed,
1237 make all groups the largest needed size. */
1238 if (group_size[(int) class] < size)
1240 other_mode = group_mode[(int) class];
1241 allocate_mode = mode;
1243 group_size[(int) class] = size;
1244 group_mode[(int) class] = mode;
1249 allocate_mode = group_mode[(int) class];
1252 /* Crash if two dissimilar machine modes both need
1253 groups of consecutive regs of the same class. */
1255 if (other_mode != VOIDmode && other_mode != allocate_mode
1256 && ! modes_equiv_for_class_p (allocate_mode,
1258 fatal_insn ("Two dissimilar machine modes both need groups of consecutive regs of the same class",
1263 this_needs->regs[nongroup_need][(int) class] += 1;
1264 p = reg_class_superclasses[(int) class];
1265 while (*p != LIM_REG_CLASSES)
1266 this_needs->regs[nongroup_need][(int) *p++] += 1;
1272 /* All reloads have been counted for this insn;
1273 now merge the various times of use.
1274 This sets insn_needs, etc., to the maximum total number
1275 of registers needed at any point in this insn. */
1277 for (i = 0; i < N_REG_CLASSES; i++)
1279 int in_max, out_max;
1281 /* Compute normal and nongroup needs. */
1282 for (j = 0; j <= 1; j++)
1284 for (in_max = 0, out_max = 0, k = 0;
1285 k < reload_n_operands; k++)
1288 = MAX (in_max, insn_needs.in_addr[k].regs[j][i]);
1290 = MAX (out_max, insn_needs.out_addr[k].regs[j][i]);
1293 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1294 and operand addresses but not things used to reload
1295 them. Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads
1296 don't conflict with things needed to reload inputs or
1299 in_max = MAX (MAX (insn_needs.op_addr.regs[j][i],
1300 insn_needs.op_addr_reload.regs[j][i]),
1303 out_max = MAX (out_max, insn_needs.insn.regs[j][i]);
1305 insn_needs.input.regs[j][i]
1306 = MAX (insn_needs.input.regs[j][i]
1307 + insn_needs.op_addr.regs[j][i]
1308 + insn_needs.insn.regs[j][i],
1309 in_max + insn_needs.input.regs[j][i]);
1311 insn_needs.output.regs[j][i] += out_max;
1312 insn_needs.other.regs[j][i]
1313 += MAX (MAX (insn_needs.input.regs[j][i],
1314 insn_needs.output.regs[j][i]),
1315 insn_needs.other_addr.regs[j][i]);
1319 /* Now compute group needs. */
1320 for (in_max = 0, out_max = 0, j = 0;
1321 j < reload_n_operands; j++)
1323 in_max = MAX (in_max, insn_needs.in_addr[j].groups[i]);
1325 = MAX (out_max, insn_needs.out_addr[j].groups[i]);
1328 in_max = MAX (MAX (insn_needs.op_addr.groups[i],
1329 insn_needs.op_addr_reload.groups[i]),
1331 out_max = MAX (out_max, insn_needs.insn.groups[i]);
1333 insn_needs.input.groups[i]
1334 = MAX (insn_needs.input.groups[i]
1335 + insn_needs.op_addr.groups[i]
1336 + insn_needs.insn.groups[i],
1337 in_max + insn_needs.input.groups[i]);
1339 insn_needs.output.groups[i] += out_max;
1340 insn_needs.other.groups[i]
1341 += MAX (MAX (insn_needs.input.groups[i],
1342 insn_needs.output.groups[i]),
1343 insn_needs.other_addr.groups[i]);
1346 /* If this is a CALL_INSN and caller-saves will need
1347 a spill register, act as if the spill register is
1348 needed for this insn. However, the spill register
1349 can be used by any reload of this insn, so we only
1350 need do something if no need for that class has
1353 The assumption that every CALL_INSN will trigger a
1354 caller-save is highly conservative, however, the number
1355 of cases where caller-saves will need a spill register but
1356 a block containing a CALL_INSN won't need a spill register
1357 of that class should be quite rare.
1359 If a group is needed, the size and mode of the group will
1360 have been set up at the beginning of this loop. */
1362 if (GET_CODE (insn) == CALL_INSN
1363 && caller_save_spill_class != NO_REGS)
1365 /* See if this register would conflict with any reload
1366 that needs a group. */
1367 int nongroup_need = 0;
1368 int *caller_save_needs;
1370 for (j = 0; j < n_reloads; j++)
1371 if ((CLASS_MAX_NREGS (reload_reg_class[j],
1372 (GET_MODE_SIZE (reload_outmode[j])
1373 > GET_MODE_SIZE (reload_inmode[j]))
1377 && reg_classes_intersect_p (caller_save_spill_class,
1378 reload_reg_class[j]))
1385 = (caller_save_group_size > 1
1386 ? insn_needs.other.groups
1387 : insn_needs.other.regs[nongroup_need]);
1389 if (caller_save_needs[(int) caller_save_spill_class] == 0)
1391 register enum reg_class *p
1392 = reg_class_superclasses[(int) caller_save_spill_class];
1394 caller_save_needs[(int) caller_save_spill_class]++;
1396 while (*p != LIM_REG_CLASSES)
1397 caller_save_needs[(int) *p++] += 1;
1400 /* Show that this basic block will need a register of
1404 && ! (basic_block_needs[(int) caller_save_spill_class]
1407 basic_block_needs[(int) caller_save_spill_class]
1409 new_basic_block_needs = 1;
1413 #ifdef SMALL_REGISTER_CLASSES
1414 /* If this insn stores the value of a function call,
1415 and that value is in a register that has been spilled,
1416 and if the insn needs a reload in a class
1417 that might use that register as the reload register,
1418 then add add an extra need in that class.
1419 This makes sure we have a register available that does
1420 not overlap the return value. */
1422 if (SMALL_REGISTER_CLASSES && avoid_return_reg)
1424 int regno = REGNO (avoid_return_reg);
1426 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
1428 int basic_needs[N_REG_CLASSES], basic_groups[N_REG_CLASSES];
1430 /* First compute the "basic needs", which counts a
1431 need only in the smallest class in which it
1434 bcopy ((char *) insn_needs.other.regs[0],
1435 (char *) basic_needs, sizeof basic_needs);
1436 bcopy ((char *) insn_needs.other.groups,
1437 (char *) basic_groups, sizeof basic_groups);
1439 for (i = 0; i < N_REG_CLASSES; i++)
1443 if (basic_needs[i] >= 0)
1444 for (p = reg_class_superclasses[i];
1445 *p != LIM_REG_CLASSES; p++)
1446 basic_needs[(int) *p] -= basic_needs[i];
1448 if (basic_groups[i] >= 0)
1449 for (p = reg_class_superclasses[i];
1450 *p != LIM_REG_CLASSES; p++)
1451 basic_groups[(int) *p] -= basic_groups[i];
1454 /* Now count extra regs if there might be a conflict with
1455 the return value register. */
1457 for (r = regno; r < regno + nregs; r++)
1458 if (spill_reg_order[r] >= 0)
1459 for (i = 0; i < N_REG_CLASSES; i++)
1460 if (TEST_HARD_REG_BIT (reg_class_contents[i], r))
1462 if (basic_needs[i] > 0)
1466 insn_needs.other.regs[0][i]++;
1467 p = reg_class_superclasses[i];
1468 while (*p != LIM_REG_CLASSES)
1469 insn_needs.other.regs[0][(int) *p++]++;
1471 if (basic_groups[i] > 0)
1475 insn_needs.other.groups[i]++;
1476 p = reg_class_superclasses[i];
1477 while (*p != LIM_REG_CLASSES)
1478 insn_needs.other.groups[(int) *p++]++;
1482 #endif /* SMALL_REGISTER_CLASSES */
1484 /* For each class, collect maximum need of any insn. */
1486 for (i = 0; i < N_REG_CLASSES; i++)
1488 if (max_needs[i] < insn_needs.other.regs[0][i])
1490 max_needs[i] = insn_needs.other.regs[0][i];
1491 max_needs_insn[i] = insn;
1493 if (max_groups[i] < insn_needs.other.groups[i])
1495 max_groups[i] = insn_needs.other.groups[i];
1496 max_groups_insn[i] = insn;
1498 if (max_nongroups[i] < insn_needs.other.regs[1][i])
1500 max_nongroups[i] = insn_needs.other.regs[1][i];
1501 max_nongroups_insn[i] = insn;
1505 /* Note that there is a continue statement above. */
1508 /* If we allocated any new memory locations, make another pass
1509 since it might have changed elimination offsets. */
1510 if (starting_frame_size != get_frame_size ())
1511 something_changed = 1;
1514 for (i = 0; i < N_REG_CLASSES; i++)
1516 if (max_needs[i] > 0)
1518 ";; Need %d reg%s of class %s (for insn %d).\n",
1519 max_needs[i], max_needs[i] == 1 ? "" : "s",
1520 reg_class_names[i], INSN_UID (max_needs_insn[i]));
1521 if (max_nongroups[i] > 0)
1523 ";; Need %d nongroup reg%s of class %s (for insn %d).\n",
1524 max_nongroups[i], max_nongroups[i] == 1 ? "" : "s",
1525 reg_class_names[i], INSN_UID (max_nongroups_insn[i]));
1526 if (max_groups[i] > 0)
1528 ";; Need %d group%s (%smode) of class %s (for insn %d).\n",
1529 max_groups[i], max_groups[i] == 1 ? "" : "s",
1530 mode_name[(int) group_mode[i]],
1531 reg_class_names[i], INSN_UID (max_groups_insn[i]));
1534 /* If we have caller-saves, set up the save areas and see if caller-save
1535 will need a spill register. */
1537 if (caller_save_needed)
1539 /* Set the offsets for setup_save_areas. */
1540 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
1542 ep->previous_offset = ep->max_offset;
1544 if ( ! setup_save_areas (&something_changed)
1545 && caller_save_spill_class == NO_REGS)
1547 /* The class we will need depends on whether the machine
1548 supports the sum of two registers for an address; see
1549 find_address_reloads for details. */
1551 caller_save_spill_class
1552 = double_reg_address_ok ? INDEX_REG_CLASS : BASE_REG_CLASS;
1553 caller_save_group_size
1554 = CLASS_MAX_NREGS (caller_save_spill_class, Pmode);
1555 something_changed = 1;
1559 /* See if anything that happened changes which eliminations are valid.
1560 For example, on the Sparc, whether or not the frame pointer can
1561 be eliminated can depend on what registers have been used. We need
1562 not check some conditions again (such as flag_omit_frame_pointer)
1563 since they can't have changed. */
1565 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1566 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
1567 #ifdef ELIMINABLE_REGS
1568 || ! CAN_ELIMINATE (ep->from, ep->to)
1571 ep->can_eliminate = 0;
1573 /* Look for the case where we have discovered that we can't replace
1574 register A with register B and that means that we will now be
1575 trying to replace register A with register C. This means we can
1576 no longer replace register C with register B and we need to disable
1577 such an elimination, if it exists. This occurs often with A == ap,
1578 B == sp, and C == fp. */
1580 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1582 struct elim_table *op;
1583 register int new_to = -1;
1585 if (! ep->can_eliminate && ep->can_eliminate_previous)
1587 /* Find the current elimination for ep->from, if there is a
1589 for (op = reg_eliminate;
1590 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1591 if (op->from == ep->from && op->can_eliminate)
1597 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
1599 for (op = reg_eliminate;
1600 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1601 if (op->from == new_to && op->to == ep->to)
1602 op->can_eliminate = 0;
1606 /* See if any registers that we thought we could eliminate the previous
1607 time are no longer eliminable. If so, something has changed and we
1608 must spill the register. Also, recompute the number of eliminable
1609 registers and see if the frame pointer is needed; it is if there is
1610 no elimination of the frame pointer that we can perform. */
1612 frame_pointer_needed = 1;
1613 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1615 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
1616 && ep->to != HARD_FRAME_POINTER_REGNUM)
1617 frame_pointer_needed = 0;
1619 if (! ep->can_eliminate && ep->can_eliminate_previous)
1621 ep->can_eliminate_previous = 0;
1622 spill_hard_reg (ep->from, global, dumpfile, 1);
1623 something_changed = 1;
1628 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1629 /* If we didn't need a frame pointer last time, but we do now, spill
1630 the hard frame pointer. */
1631 if (frame_pointer_needed && ! previous_frame_pointer_needed)
1633 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, global, dumpfile, 1);
1634 something_changed = 1;
1638 /* If all needs are met, we win. */
1640 for (i = 0; i < N_REG_CLASSES; i++)
1641 if (max_needs[i] > 0 || max_groups[i] > 0 || max_nongroups[i] > 0)
1643 if (i == N_REG_CLASSES && !new_basic_block_needs && ! something_changed)
1646 /* Not all needs are met; must spill some hard regs. */
1648 /* Put all registers spilled so far back in potential_reload_regs, but
1649 put them at the front, since we've already spilled most of the
1650 pseudos in them (we might have left some pseudos unspilled if they
1651 were in a block that didn't need any spill registers of a conflicting
1652 class. We used to try to mark off the need for those registers,
1653 but doing so properly is very complex and reallocating them is the
1654 simpler approach. First, "pack" potential_reload_regs by pushing
1655 any nonnegative entries towards the end. That will leave room
1656 for the registers we already spilled.
1658 Also, undo the marking of the spill registers from the last time
1659 around in FORBIDDEN_REGS since we will be probably be allocating
1662 ??? It is theoretically possible that we might end up not using one
1663 of our previously-spilled registers in this allocation, even though
1664 they are at the head of the list. It's not clear what to do about
1665 this, but it was no better before, when we marked off the needs met
1666 by the previously-spilled registers. With the current code, globals
1667 can be allocated into these registers, but locals cannot. */
1671 for (i = j = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
1672 if (potential_reload_regs[i] != -1)
1673 potential_reload_regs[j--] = potential_reload_regs[i];
1675 for (i = 0; i < n_spills; i++)
1677 potential_reload_regs[i] = spill_regs[i];
1678 spill_reg_order[spill_regs[i]] = -1;
1679 CLEAR_HARD_REG_BIT (forbidden_regs, spill_regs[i]);
1685 /* Now find more reload regs to satisfy the remaining need
1686 Do it by ascending class number, since otherwise a reg
1687 might be spilled for a big class and might fail to count
1688 for a smaller class even though it belongs to that class.
1690 Count spilled regs in `spills', and add entries to
1691 `spill_regs' and `spill_reg_order'.
1693 ??? Note there is a problem here.
1694 When there is a need for a group in a high-numbered class,
1695 and also need for non-group regs that come from a lower class,
1696 the non-group regs are chosen first. If there aren't many regs,
1697 they might leave no room for a group.
1699 This was happening on the 386. To fix it, we added the code
1700 that calls possible_group_p, so that the lower class won't
1701 break up the last possible group.
1703 Really fixing the problem would require changes above
1704 in counting the regs already spilled, and in choose_reload_regs.
1705 It might be hard to avoid introducing bugs there. */
1707 CLEAR_HARD_REG_SET (counted_for_groups);
1708 CLEAR_HARD_REG_SET (counted_for_nongroups);
1710 for (class = 0; class < N_REG_CLASSES; class++)
1712 /* First get the groups of registers.
1713 If we got single registers first, we might fragment
1715 while (max_groups[class] > 0)
1717 /* If any single spilled regs happen to form groups,
1718 count them now. Maybe we don't really need
1719 to spill another group. */
1720 count_possible_groups (group_size, group_mode, max_groups,
1723 if (max_groups[class] <= 0)
1726 /* Groups of size 2 (the only groups used on most machines)
1727 are treated specially. */
1728 if (group_size[class] == 2)
1730 /* First, look for a register that will complete a group. */
1731 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1735 j = potential_reload_regs[i];
1736 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1738 ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1739 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1740 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1741 && HARD_REGNO_MODE_OK (other, group_mode[class])
1742 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1744 /* We don't want one part of another group.
1745 We could get "two groups" that overlap! */
1746 && ! TEST_HARD_REG_BIT (counted_for_groups, other))
1748 (j < FIRST_PSEUDO_REGISTER - 1
1749 && (other = j + 1, spill_reg_order[other] >= 0)
1750 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1751 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1752 && HARD_REGNO_MODE_OK (j, group_mode[class])
1753 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1755 && ! TEST_HARD_REG_BIT (counted_for_groups,
1758 register enum reg_class *p;
1760 /* We have found one that will complete a group,
1761 so count off one group as provided. */
1762 max_groups[class]--;
1763 p = reg_class_superclasses[class];
1764 while (*p != LIM_REG_CLASSES)
1766 if (group_size [(int) *p] <= group_size [class])
1767 max_groups[(int) *p]--;
1771 /* Indicate both these regs are part of a group. */
1772 SET_HARD_REG_BIT (counted_for_groups, j);
1773 SET_HARD_REG_BIT (counted_for_groups, other);
1777 /* We can't complete a group, so start one. */
1778 #ifdef SMALL_REGISTER_CLASSES
1779 /* Look for a pair neither of which is explicitly used. */
1780 if (SMALL_REGISTER_CLASSES && i == FIRST_PSEUDO_REGISTER)
1781 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1784 j = potential_reload_regs[i];
1785 /* Verify that J+1 is a potential reload reg. */
1786 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1787 if (potential_reload_regs[k] == j + 1)
1789 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1790 && k < FIRST_PSEUDO_REGISTER
1791 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1792 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1793 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1794 && HARD_REGNO_MODE_OK (j, group_mode[class])
1795 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1797 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1)
1798 /* Reject J at this stage
1799 if J+1 was explicitly used. */
1800 && ! regs_explicitly_used[j + 1])
1804 /* Now try any group at all
1805 whose registers are not in bad_spill_regs. */
1806 if (i == FIRST_PSEUDO_REGISTER)
1807 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1810 j = potential_reload_regs[i];
1811 /* Verify that J+1 is a potential reload reg. */
1812 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1813 if (potential_reload_regs[k] == j + 1)
1815 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1816 && k < FIRST_PSEUDO_REGISTER
1817 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1818 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1819 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1820 && HARD_REGNO_MODE_OK (j, group_mode[class])
1821 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1823 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1))
1827 /* I should be the index in potential_reload_regs
1828 of the new reload reg we have found. */
1830 if (i >= FIRST_PSEUDO_REGISTER)
1832 /* There are no groups left to spill. */
1833 spill_failure (max_groups_insn[class]);
1839 |= new_spill_reg (i, class, max_needs, NULL_PTR,
1844 /* For groups of more than 2 registers,
1845 look for a sufficient sequence of unspilled registers,
1846 and spill them all at once. */
1847 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1851 j = potential_reload_regs[i];
1853 && j + group_size[class] <= FIRST_PSEUDO_REGISTER
1854 && HARD_REGNO_MODE_OK (j, group_mode[class]))
1856 /* Check each reg in the sequence. */
1857 for (k = 0; k < group_size[class]; k++)
1858 if (! (spill_reg_order[j + k] < 0
1859 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1860 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1862 /* We got a full sequence, so spill them all. */
1863 if (k == group_size[class])
1865 register enum reg_class *p;
1866 for (k = 0; k < group_size[class]; k++)
1869 SET_HARD_REG_BIT (counted_for_groups, j + k);
1870 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1871 if (potential_reload_regs[idx] == j + k)
1874 |= new_spill_reg (idx, class,
1875 max_needs, NULL_PTR,
1879 /* We have found one that will complete a group,
1880 so count off one group as provided. */
1881 max_groups[class]--;
1882 p = reg_class_superclasses[class];
1883 while (*p != LIM_REG_CLASSES)
1885 if (group_size [(int) *p]
1886 <= group_size [class])
1887 max_groups[(int) *p]--;
1894 /* We couldn't find any registers for this reload.
1895 Avoid going into an infinite loop. */
1896 if (i >= FIRST_PSEUDO_REGISTER)
1898 /* There are no groups left. */
1899 spill_failure (max_groups_insn[class]);
1906 /* Now similarly satisfy all need for single registers. */
1908 while (max_needs[class] > 0 || max_nongroups[class] > 0)
1910 /* If we spilled enough regs, but they weren't counted
1911 against the non-group need, see if we can count them now.
1912 If so, we can avoid some actual spilling. */
1913 if (max_needs[class] <= 0 && max_nongroups[class] > 0)
1914 for (i = 0; i < n_spills; i++)
1915 if (TEST_HARD_REG_BIT (reg_class_contents[class],
1917 && !TEST_HARD_REG_BIT (counted_for_groups,
1919 && !TEST_HARD_REG_BIT (counted_for_nongroups,
1921 && max_nongroups[class] > 0)
1923 register enum reg_class *p;
1925 SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]);
1926 max_nongroups[class]--;
1927 p = reg_class_superclasses[class];
1928 while (*p != LIM_REG_CLASSES)
1929 max_nongroups[(int) *p++]--;
1931 if (max_needs[class] <= 0 && max_nongroups[class] <= 0)
1934 /* Consider the potential reload regs that aren't
1935 yet in use as reload regs, in order of preference.
1936 Find the most preferred one that's in this class. */
1938 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1939 if (potential_reload_regs[i] >= 0
1940 && TEST_HARD_REG_BIT (reg_class_contents[class],
1941 potential_reload_regs[i])
1942 /* If this reg will not be available for groups,
1943 pick one that does not foreclose possible groups.
1944 This is a kludge, and not very general,
1945 but it should be sufficient to make the 386 work,
1946 and the problem should not occur on machines with
1948 && (max_nongroups[class] == 0
1949 || possible_group_p (potential_reload_regs[i], max_groups)))
1952 /* If we couldn't get a register, try to get one even if we
1953 might foreclose possible groups. This may cause problems
1954 later, but that's better than aborting now, since it is
1955 possible that we will, in fact, be able to form the needed
1956 group even with this allocation. */
1958 if (i >= FIRST_PSEUDO_REGISTER
1959 && (asm_noperands (max_needs[class] > 0
1960 ? max_needs_insn[class]
1961 : max_nongroups_insn[class])
1963 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1964 if (potential_reload_regs[i] >= 0
1965 && TEST_HARD_REG_BIT (reg_class_contents[class],
1966 potential_reload_regs[i]))
1969 /* I should be the index in potential_reload_regs
1970 of the new reload reg we have found. */
1972 if (i >= FIRST_PSEUDO_REGISTER)
1974 /* There are no possible registers left to spill. */
1975 spill_failure (max_needs[class] > 0 ? max_needs_insn[class]
1976 : max_nongroups_insn[class]);
1982 |= new_spill_reg (i, class, max_needs, max_nongroups,
1988 /* If global-alloc was run, notify it of any register eliminations we have
1991 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1992 if (ep->can_eliminate)
1993 mark_elimination (ep->from, ep->to);
1995 /* Insert code to save and restore call-clobbered hard regs
1996 around calls. Tell if what mode to use so that we will process
1997 those insns in reload_as_needed if we have to. */
1999 if (caller_save_needed)
2000 save_call_clobbered_regs (num_eliminable ? QImode
2001 : caller_save_spill_class != NO_REGS ? HImode
2004 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
2005 If that insn didn't set the register (i.e., it copied the register to
2006 memory), just delete that insn instead of the equivalencing insn plus
2007 anything now dead. If we call delete_dead_insn on that insn, we may
2008 delete the insn that actually sets the register if the register die
2009 there and that is incorrect. */
2011 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2012 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0
2013 && GET_CODE (reg_equiv_init[i]) != NOTE)
2015 if (reg_set_p (regno_reg_rtx[i], PATTERN (reg_equiv_init[i])))
2016 delete_dead_insn (reg_equiv_init[i]);
2019 PUT_CODE (reg_equiv_init[i], NOTE);
2020 NOTE_SOURCE_FILE (reg_equiv_init[i]) = 0;
2021 NOTE_LINE_NUMBER (reg_equiv_init[i]) = NOTE_INSN_DELETED;
2025 /* Use the reload registers where necessary
2026 by generating move instructions to move the must-be-register
2027 values into or out of the reload registers. */
2029 if (something_needs_reloads || something_needs_elimination
2030 || (caller_save_needed && num_eliminable)
2031 || caller_save_spill_class != NO_REGS)
2032 reload_as_needed (first, global);
2034 /* If we were able to eliminate the frame pointer, show that it is no
2035 longer live at the start of any basic block. If it ls live by
2036 virtue of being in a pseudo, that pseudo will be marked live
2037 and hence the frame pointer will be known to be live via that
2040 if (! frame_pointer_needed)
2041 for (i = 0; i < n_basic_blocks; i++)
2042 basic_block_live_at_start[i][HARD_FRAME_POINTER_REGNUM / REGSET_ELT_BITS]
2043 &= ~ ((REGSET_ELT_TYPE) 1 << (HARD_FRAME_POINTER_REGNUM
2044 % REGSET_ELT_BITS));
2046 /* Come here (with failure set nonzero) if we can't get enough spill regs
2047 and we decide not to abort about it. */
2050 reload_in_progress = 0;
2052 /* Now eliminate all pseudo regs by modifying them into
2053 their equivalent memory references.
2054 The REG-rtx's for the pseudos are modified in place,
2055 so all insns that used to refer to them now refer to memory.
2057 For a reg that has a reg_equiv_address, all those insns
2058 were changed by reloading so that no insns refer to it any longer;
2059 but the DECL_RTL of a variable decl may refer to it,
2060 and if so this causes the debugging info to mention the variable. */
2062 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2066 if (reg_equiv_mem[i])
2068 addr = XEXP (reg_equiv_mem[i], 0);
2069 in_struct = MEM_IN_STRUCT_P (reg_equiv_mem[i]);
2071 if (reg_equiv_address[i])
2072 addr = reg_equiv_address[i];
2075 if (reg_renumber[i] < 0)
2077 rtx reg = regno_reg_rtx[i];
2078 XEXP (reg, 0) = addr;
2079 REG_USERVAR_P (reg) = 0;
2080 MEM_IN_STRUCT_P (reg) = in_struct;
2081 PUT_CODE (reg, MEM);
2083 else if (reg_equiv_mem[i])
2084 XEXP (reg_equiv_mem[i], 0) = addr;
2088 #ifdef PRESERVE_DEATH_INFO_REGNO_P
2089 /* Make a pass over all the insns and remove death notes for things that
2090 are no longer registers or no longer die in the insn (e.g., an input
2091 and output pseudo being tied). */
2093 for (insn = first; insn; insn = NEXT_INSN (insn))
2094 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
2098 for (note = REG_NOTES (insn); note; note = next)
2100 next = XEXP (note, 1);
2101 if (REG_NOTE_KIND (note) == REG_DEAD
2102 && (GET_CODE (XEXP (note, 0)) != REG
2103 || reg_set_p (XEXP (note, 0), PATTERN (insn))))
2104 remove_note (insn, note);
2109 /* Indicate that we no longer have known memory locations or constants. */
2110 reg_equiv_constant = 0;
2111 reg_equiv_memory_loc = 0;
2114 free (scratch_list);
2117 free (scratch_block);
2120 CLEAR_HARD_REG_SET (used_spill_regs);
2121 for (i = 0; i < n_spills; i++)
2122 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
2127 /* Nonzero if, after spilling reg REGNO for non-groups,
2128 it will still be possible to find a group if we still need one. */
2131 possible_group_p (regno, max_groups)
2136 int class = (int) NO_REGS;
2138 for (i = 0; i < (int) N_REG_CLASSES; i++)
2139 if (max_groups[i] > 0)
2145 if (class == (int) NO_REGS)
2148 /* Consider each pair of consecutive registers. */
2149 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
2151 /* Ignore pairs that include reg REGNO. */
2152 if (i == regno || i + 1 == regno)
2155 /* Ignore pairs that are outside the class that needs the group.
2156 ??? Here we fail to handle the case where two different classes
2157 independently need groups. But this never happens with our
2158 current machine descriptions. */
2159 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
2160 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
2163 /* A pair of consecutive regs we can still spill does the trick. */
2164 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
2165 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2166 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
2169 /* A pair of one already spilled and one we can spill does it
2170 provided the one already spilled is not otherwise reserved. */
2171 if (spill_reg_order[i] < 0
2172 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2173 && spill_reg_order[i + 1] >= 0
2174 && ! TEST_HARD_REG_BIT (counted_for_groups, i + 1)
2175 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i + 1))
2177 if (spill_reg_order[i + 1] < 0
2178 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
2179 && spill_reg_order[i] >= 0
2180 && ! TEST_HARD_REG_BIT (counted_for_groups, i)
2181 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i))
2188 /* Count any groups of CLASS that can be formed from the registers recently
2192 count_possible_groups (group_size, group_mode, max_groups, class)
2194 enum machine_mode *group_mode;
2201 /* Now find all consecutive groups of spilled registers
2202 and mark each group off against the need for such groups.
2203 But don't count them against ordinary need, yet. */
2205 if (group_size[class] == 0)
2208 CLEAR_HARD_REG_SET (new);
2210 /* Make a mask of all the regs that are spill regs in class I. */
2211 for (i = 0; i < n_spills; i++)
2212 if (TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
2213 && ! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[i])
2214 && ! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
2215 SET_HARD_REG_BIT (new, spill_regs[i]);
2217 /* Find each consecutive group of them. */
2218 for (i = 0; i < FIRST_PSEUDO_REGISTER && max_groups[class] > 0; i++)
2219 if (TEST_HARD_REG_BIT (new, i)
2220 && i + group_size[class] <= FIRST_PSEUDO_REGISTER
2221 && HARD_REGNO_MODE_OK (i, group_mode[class]))
2223 for (j = 1; j < group_size[class]; j++)
2224 if (! TEST_HARD_REG_BIT (new, i + j))
2227 if (j == group_size[class])
2229 /* We found a group. Mark it off against this class's need for
2230 groups, and against each superclass too. */
2231 register enum reg_class *p;
2233 max_groups[class]--;
2234 p = reg_class_superclasses[class];
2235 while (*p != LIM_REG_CLASSES)
2237 if (group_size [(int) *p] <= group_size [class])
2238 max_groups[(int) *p]--;
2242 /* Don't count these registers again. */
2243 for (j = 0; j < group_size[class]; j++)
2244 SET_HARD_REG_BIT (counted_for_groups, i + j);
2247 /* Skip to the last reg in this group. When i is incremented above,
2248 it will then point to the first reg of the next possible group. */
2253 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2254 another mode that needs to be reloaded for the same register class CLASS.
2255 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2256 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2258 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2259 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2260 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2261 causes unnecessary failures on machines requiring alignment of register
2262 groups when the two modes are different sizes, because the larger mode has
2263 more strict alignment rules than the smaller mode. */
2266 modes_equiv_for_class_p (allocate_mode, other_mode, class)
2267 enum machine_mode allocate_mode, other_mode;
2268 enum reg_class class;
2271 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2273 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
2274 && HARD_REGNO_MODE_OK (regno, allocate_mode)
2275 && ! HARD_REGNO_MODE_OK (regno, other_mode))
2281 /* Handle the failure to find a register to spill.
2282 INSN should be one of the insns which needed this particular spill reg. */
2285 spill_failure (insn)
2288 if (asm_noperands (PATTERN (insn)) >= 0)
2289 error_for_asm (insn, "`asm' needs too many reloads");
2291 fatal_insn ("Unable to find a register to spill.", insn);
2294 /* Add a new register to the tables of available spill-registers
2295 (as well as spilling all pseudos allocated to the register).
2296 I is the index of this register in potential_reload_regs.
2297 CLASS is the regclass whose need is being satisfied.
2298 MAX_NEEDS and MAX_NONGROUPS are the vectors of needs,
2299 so that this register can count off against them.
2300 MAX_NONGROUPS is 0 if this register is part of a group.
2301 GLOBAL and DUMPFILE are the same as the args that `reload' got. */
2304 new_spill_reg (i, class, max_needs, max_nongroups, global, dumpfile)
2312 register enum reg_class *p;
2314 int regno = potential_reload_regs[i];
2316 if (i >= FIRST_PSEUDO_REGISTER)
2317 abort (); /* Caller failed to find any register. */
2319 if (fixed_regs[regno] || TEST_HARD_REG_BIT (forbidden_regs, regno))
2320 fatal ("fixed or forbidden register was spilled.\n\
2321 This may be due to a compiler bug or to impossible asm\n\
2322 statements or clauses.");
2324 /* Make reg REGNO an additional reload reg. */
2326 potential_reload_regs[i] = -1;
2327 spill_regs[n_spills] = regno;
2328 spill_reg_order[regno] = n_spills;
2330 fprintf (dumpfile, "Spilling reg %d.\n", spill_regs[n_spills]);
2332 /* Clear off the needs we just satisfied. */
2335 p = reg_class_superclasses[class];
2336 while (*p != LIM_REG_CLASSES)
2337 max_needs[(int) *p++]--;
2339 if (max_nongroups && max_nongroups[class] > 0)
2341 SET_HARD_REG_BIT (counted_for_nongroups, regno);
2342 max_nongroups[class]--;
2343 p = reg_class_superclasses[class];
2344 while (*p != LIM_REG_CLASSES)
2345 max_nongroups[(int) *p++]--;
2348 /* Spill every pseudo reg that was allocated to this reg
2349 or to something that overlaps this reg. */
2351 val = spill_hard_reg (spill_regs[n_spills], global, dumpfile, 0);
2353 /* If there are some registers still to eliminate and this register
2354 wasn't ever used before, additional stack space may have to be
2355 allocated to store this register. Thus, we may have changed the offset
2356 between the stack and frame pointers, so mark that something has changed.
2357 (If new pseudos were spilled, thus requiring more space, VAL would have
2358 been set non-zero by the call to spill_hard_reg above since additional
2359 reloads may be needed in that case.
2361 One might think that we need only set VAL to 1 if this is a call-used
2362 register. However, the set of registers that must be saved by the
2363 prologue is not identical to the call-used set. For example, the
2364 register used by the call insn for the return PC is a call-used register,
2365 but must be saved by the prologue. */
2366 if (num_eliminable && ! regs_ever_live[spill_regs[n_spills]])
2369 regs_ever_live[spill_regs[n_spills]] = 1;
2375 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2376 data that is dead in INSN. */
2379 delete_dead_insn (insn)
2382 rtx prev = prev_real_insn (insn);
2385 /* If the previous insn sets a register that dies in our insn, delete it
2387 if (prev && GET_CODE (PATTERN (prev)) == SET
2388 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2389 && reg_mentioned_p (prev_dest, PATTERN (insn))
2390 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)))
2391 delete_dead_insn (prev);
2393 PUT_CODE (insn, NOTE);
2394 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2395 NOTE_SOURCE_FILE (insn) = 0;
2398 /* Modify the home of pseudo-reg I.
2399 The new home is present in reg_renumber[I].
2401 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2402 or it may be -1, meaning there is none or it is not relevant.
2403 This is used so that all pseudos spilled from a given hard reg
2404 can share one stack slot. */
2407 alter_reg (i, from_reg)
2411 /* When outputting an inline function, this can happen
2412 for a reg that isn't actually used. */
2413 if (regno_reg_rtx[i] == 0)
2416 /* If the reg got changed to a MEM at rtl-generation time,
2418 if (GET_CODE (regno_reg_rtx[i]) != REG)
2421 /* Modify the reg-rtx to contain the new hard reg
2422 number or else to contain its pseudo reg number. */
2423 REGNO (regno_reg_rtx[i])
2424 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2426 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2427 allocate a stack slot for it. */
2429 if (reg_renumber[i] < 0
2430 && reg_n_refs[i] > 0
2431 && reg_equiv_constant[i] == 0
2432 && reg_equiv_memory_loc[i] == 0)
2435 int inherent_size = PSEUDO_REGNO_BYTES (i);
2436 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2439 /* Each pseudo reg has an inherent size which comes from its own mode,
2440 and a total size which provides room for paradoxical subregs
2441 which refer to the pseudo reg in wider modes.
2443 We can use a slot already allocated if it provides both
2444 enough inherent space and enough total space.
2445 Otherwise, we allocate a new slot, making sure that it has no less
2446 inherent space, and no less total space, then the previous slot. */
2449 /* No known place to spill from => no slot to reuse. */
2450 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size, -1);
2451 if (BYTES_BIG_ENDIAN)
2452 /* Cancel the big-endian correction done in assign_stack_local.
2453 Get the address of the beginning of the slot.
2454 This is so we can do a big-endian correction unconditionally
2456 adjust = inherent_size - total_size;
2458 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2460 /* Reuse a stack slot if possible. */
2461 else if (spill_stack_slot[from_reg] != 0
2462 && spill_stack_slot_width[from_reg] >= total_size
2463 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2465 x = spill_stack_slot[from_reg];
2466 /* Allocate a bigger slot. */
2469 /* Compute maximum size needed, both for inherent size
2470 and for total size. */
2471 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2473 if (spill_stack_slot[from_reg])
2475 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2477 mode = GET_MODE (spill_stack_slot[from_reg]);
2478 if (spill_stack_slot_width[from_reg] > total_size)
2479 total_size = spill_stack_slot_width[from_reg];
2481 /* Make a slot with that size. */
2482 x = assign_stack_local (mode, total_size, -1);
2484 if (BYTES_BIG_ENDIAN)
2486 /* Cancel the big-endian correction done in assign_stack_local.
2487 Get the address of the beginning of the slot.
2488 This is so we can do a big-endian correction unconditionally
2490 adjust = GET_MODE_SIZE (mode) - total_size;
2492 stack_slot = gen_rtx (MEM, mode_for_size (total_size
2495 plus_constant (XEXP (x, 0), adjust));
2497 spill_stack_slot[from_reg] = stack_slot;
2498 spill_stack_slot_width[from_reg] = total_size;
2501 /* On a big endian machine, the "address" of the slot
2502 is the address of the low part that fits its inherent mode. */
2503 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2504 adjust += (total_size - inherent_size);
2506 /* If we have any adjustment to make, or if the stack slot is the
2507 wrong mode, make a new stack slot. */
2508 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2510 x = gen_rtx (MEM, GET_MODE (regno_reg_rtx[i]),
2511 plus_constant (XEXP (x, 0), adjust));
2512 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2515 /* Save the stack slot for later. */
2516 reg_equiv_memory_loc[i] = x;
2520 /* Mark the slots in regs_ever_live for the hard regs
2521 used by pseudo-reg number REGNO. */
2524 mark_home_live (regno)
2527 register int i, lim;
2528 i = reg_renumber[regno];
2531 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2533 regs_ever_live[i++] = 1;
2536 /* Mark the registers used in SCRATCH as being live. */
2539 mark_scratch_live (scratch)
2543 int regno = REGNO (scratch);
2544 int lim = regno + HARD_REGNO_NREGS (regno, GET_MODE (scratch));
2546 for (i = regno; i < lim; i++)
2547 regs_ever_live[i] = 1;
2550 /* This function handles the tracking of elimination offsets around branches.
2552 X is a piece of RTL being scanned.
2554 INSN is the insn that it came from, if any.
2556 INITIAL_P is non-zero if we are to set the offset to be the initial
2557 offset and zero if we are setting the offset of the label to be the
2561 set_label_offsets (x, insn, initial_p)
2566 enum rtx_code code = GET_CODE (x);
2569 struct elim_table *p;
2574 if (LABEL_REF_NONLOCAL_P (x))
2579 /* ... fall through ... */
2582 /* If we know nothing about this label, set the desired offsets. Note
2583 that this sets the offset at a label to be the offset before a label
2584 if we don't know anything about the label. This is not correct for
2585 the label after a BARRIER, but is the best guess we can make. If
2586 we guessed wrong, we will suppress an elimination that might have
2587 been possible had we been able to guess correctly. */
2589 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2591 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2592 offsets_at[CODE_LABEL_NUMBER (x)][i]
2593 = (initial_p ? reg_eliminate[i].initial_offset
2594 : reg_eliminate[i].offset);
2595 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2598 /* Otherwise, if this is the definition of a label and it is
2599 preceded by a BARRIER, set our offsets to the known offset of
2603 && (tem = prev_nonnote_insn (insn)) != 0
2604 && GET_CODE (tem) == BARRIER)
2606 num_not_at_initial_offset = 0;
2607 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2609 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
2610 = offsets_at[CODE_LABEL_NUMBER (x)][i];
2611 if (reg_eliminate[i].can_eliminate
2612 && (reg_eliminate[i].offset
2613 != reg_eliminate[i].initial_offset))
2614 num_not_at_initial_offset++;
2619 /* If neither of the above cases is true, compare each offset
2620 with those previously recorded and suppress any eliminations
2621 where the offsets disagree. */
2623 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2624 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2625 != (initial_p ? reg_eliminate[i].initial_offset
2626 : reg_eliminate[i].offset))
2627 reg_eliminate[i].can_eliminate = 0;
2632 set_label_offsets (PATTERN (insn), insn, initial_p);
2634 /* ... fall through ... */
2638 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2639 and hence must have all eliminations at their initial offsets. */
2640 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2641 if (REG_NOTE_KIND (tem) == REG_LABEL)
2642 set_label_offsets (XEXP (tem, 0), insn, 1);
2647 /* Each of the labels in the address vector must be at their initial
2648 offsets. We want the first first for ADDR_VEC and the second
2649 field for ADDR_DIFF_VEC. */
2651 for (i = 0; i < XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2652 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2657 /* We only care about setting PC. If the source is not RETURN,
2658 IF_THEN_ELSE, or a label, disable any eliminations not at
2659 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2660 isn't one of those possibilities. For branches to a label,
2661 call ourselves recursively.
2663 Note that this can disable elimination unnecessarily when we have
2664 a non-local goto since it will look like a non-constant jump to
2665 someplace in the current function. This isn't a significant
2666 problem since such jumps will normally be when all elimination
2667 pairs are back to their initial offsets. */
2669 if (SET_DEST (x) != pc_rtx)
2672 switch (GET_CODE (SET_SRC (x)))
2679 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2683 tem = XEXP (SET_SRC (x), 1);
2684 if (GET_CODE (tem) == LABEL_REF)
2685 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2686 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2689 tem = XEXP (SET_SRC (x), 2);
2690 if (GET_CODE (tem) == LABEL_REF)
2691 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2692 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2697 /* If we reach here, all eliminations must be at their initial
2698 offset because we are doing a jump to a variable address. */
2699 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2700 if (p->offset != p->initial_offset)
2701 p->can_eliminate = 0;
2705 /* Used for communication between the next two function to properly share
2706 the vector for an ASM_OPERANDS. */
2708 static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2710 /* Scan X and replace any eliminable registers (such as fp) with a
2711 replacement (such as sp), plus an offset.
2713 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2714 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2715 MEM, we are allowed to replace a sum of a register and the constant zero
2716 with the register, which we cannot do outside a MEM. In addition, we need
2717 to record the fact that a register is referenced outside a MEM.
2719 If INSN is an insn, it is the insn containing X. If we replace a REG
2720 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2721 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2722 that the REG is being modified.
2724 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2725 That's used when we eliminate in expressions stored in notes.
2726 This means, do not set ref_outside_mem even if the reference
2729 If we see a modification to a register we know about, take the
2730 appropriate action (see case SET, below).
2732 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2733 replacements done assuming all offsets are at their initial values. If
2734 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2735 encounter, return the actual location so that find_reloads will do
2736 the proper thing. */
2739 eliminate_regs (x, mem_mode, insn)
2741 enum machine_mode mem_mode;
2744 enum rtx_code code = GET_CODE (x);
2745 struct elim_table *ep;
2770 /* First handle the case where we encounter a bare register that
2771 is eliminable. Replace it with a PLUS. */
2772 if (regno < FIRST_PSEUDO_REGISTER)
2774 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2776 if (ep->from_rtx == x && ep->can_eliminate)
2779 /* Refs inside notes don't count for this purpose. */
2780 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2781 || GET_CODE (insn) == INSN_LIST)))
2782 ep->ref_outside_mem = 1;
2783 return plus_constant (ep->to_rtx, ep->previous_offset);
2787 else if (reg_equiv_memory_loc && reg_equiv_memory_loc[regno]
2788 && (reg_equiv_address[regno] || num_not_at_initial_offset))
2790 /* In this case, find_reloads would attempt to either use an
2791 incorrect address (if something is not at its initial offset)
2792 or substitute an replaced address into an insn (which loses
2793 if the offset is changed by some later action). So we simply
2794 return the replaced stack slot (assuming it is changed by
2795 elimination) and ignore the fact that this is actually a
2796 reference to the pseudo. Ensure we make a copy of the
2797 address in case it is shared. */
2798 new = eliminate_regs (reg_equiv_memory_loc[regno],
2800 if (new != reg_equiv_memory_loc[regno])
2802 cannot_omit_stores[regno] = 1;
2803 return copy_rtx (new);
2809 /* If this is the sum of an eliminable register and a constant, rework
2811 if (GET_CODE (XEXP (x, 0)) == REG
2812 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2813 && CONSTANT_P (XEXP (x, 1)))
2815 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2817 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2820 /* Refs inside notes don't count for this purpose. */
2821 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2822 || GET_CODE (insn) == INSN_LIST)))
2823 ep->ref_outside_mem = 1;
2825 /* The only time we want to replace a PLUS with a REG (this
2826 occurs when the constant operand of the PLUS is the negative
2827 of the offset) is when we are inside a MEM. We won't want
2828 to do so at other times because that would change the
2829 structure of the insn in a way that reload can't handle.
2830 We special-case the commonest situation in
2831 eliminate_regs_in_insn, so just replace a PLUS with a
2832 PLUS here, unless inside a MEM. */
2833 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2834 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2837 return gen_rtx (PLUS, Pmode, ep->to_rtx,
2838 plus_constant (XEXP (x, 1),
2839 ep->previous_offset));
2842 /* If the register is not eliminable, we are done since the other
2843 operand is a constant. */
2847 /* If this is part of an address, we want to bring any constant to the
2848 outermost PLUS. We will do this by doing register replacement in
2849 our operands and seeing if a constant shows up in one of them.
2851 We assume here this is part of an address (or a "load address" insn)
2852 since an eliminable register is not likely to appear in any other
2855 If we have (plus (eliminable) (reg)), we want to produce
2856 (plus (plus (replacement) (reg)) (const)). If this was part of a
2857 normal add insn, (plus (replacement) (reg)) will be pushed as a
2858 reload. This is the desired action. */
2861 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2862 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2864 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2866 /* If one side is a PLUS and the other side is a pseudo that
2867 didn't get a hard register but has a reg_equiv_constant,
2868 we must replace the constant here since it may no longer
2869 be in the position of any operand. */
2870 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2871 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2872 && reg_renumber[REGNO (new1)] < 0
2873 && reg_equiv_constant != 0
2874 && reg_equiv_constant[REGNO (new1)] != 0)
2875 new1 = reg_equiv_constant[REGNO (new1)];
2876 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2877 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2878 && reg_renumber[REGNO (new0)] < 0
2879 && reg_equiv_constant[REGNO (new0)] != 0)
2880 new0 = reg_equiv_constant[REGNO (new0)];
2882 new = form_sum (new0, new1);
2884 /* As above, if we are not inside a MEM we do not want to
2885 turn a PLUS into something else. We might try to do so here
2886 for an addition of 0 if we aren't optimizing. */
2887 if (! mem_mode && GET_CODE (new) != PLUS)
2888 return gen_rtx (PLUS, GET_MODE (x), new, const0_rtx);
2896 /* If we have (minus (eliminable) (reg)), we want to produce
2897 (plus (minus (replacement) (reg)) (const)). The main reason being
2898 to be consistent with what is done for PLUS. find_reloads_address
2899 assumes that we do this. */
2901 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2902 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2904 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2906 if (GET_CODE (new0) == PLUS)
2907 return gen_rtx (PLUS, GET_MODE (x),
2908 gen_rtx (MINUS, GET_MODE (x),
2909 XEXP (new0, 0), new1),
2912 return gen_rtx (MINUS, GET_MODE (x), new0, new1);
2918 /* If this is the product of an eliminable register and a
2919 constant, apply the distribute law and move the constant out
2920 so that we have (plus (mult ..) ..). This is needed in order
2921 to keep load-address insns valid. This case is pathological.
2922 We ignore the possibility of overflow here. */
2923 if (GET_CODE (XEXP (x, 0)) == REG
2924 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2925 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2926 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2928 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2931 /* Refs inside notes don't count for this purpose. */
2932 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2933 || GET_CODE (insn) == INSN_LIST)))
2934 ep->ref_outside_mem = 1;
2937 plus_constant (gen_rtx (MULT, Pmode, ep->to_rtx, XEXP (x, 1)),
2938 ep->previous_offset * INTVAL (XEXP (x, 1)));
2941 /* ... fall through ... */
2945 case DIV: case UDIV:
2946 case MOD: case UMOD:
2947 case AND: case IOR: case XOR:
2948 case ROTATERT: case ROTATE:
2949 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2951 case GE: case GT: case GEU: case GTU:
2952 case LE: case LT: case LEU: case LTU:
2954 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2956 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2958 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2959 return gen_rtx (code, GET_MODE (x), new0, new1);
2964 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2967 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2968 if (new != XEXP (x, 0))
2969 x = gen_rtx (EXPR_LIST, REG_NOTE_KIND (x), new, XEXP (x, 1));
2972 /* ... fall through ... */
2975 /* Now do eliminations in the rest of the chain. If this was
2976 an EXPR_LIST, this might result in allocating more memory than is
2977 strictly needed, but it simplifies the code. */
2980 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2981 if (new != XEXP (x, 1))
2982 return gen_rtx (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2990 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2991 if (ep->to_rtx == XEXP (x, 0))
2993 int size = GET_MODE_SIZE (mem_mode);
2995 /* If more bytes than MEM_MODE are pushed, account for them. */
2996 #ifdef PUSH_ROUNDING
2997 if (ep->to_rtx == stack_pointer_rtx)
2998 size = PUSH_ROUNDING (size);
3000 if (code == PRE_DEC || code == POST_DEC)
3006 /* Fall through to generic unary operation case. */
3007 case STRICT_LOW_PART:
3009 case SIGN_EXTEND: case ZERO_EXTEND:
3010 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3011 case FLOAT: case FIX:
3012 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3016 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3017 if (new != XEXP (x, 0))
3018 return gen_rtx (code, GET_MODE (x), new);
3022 /* Similar to above processing, but preserve SUBREG_WORD.
3023 Convert (subreg (mem)) to (mem) if not paradoxical.
3024 Also, if we have a non-paradoxical (subreg (pseudo)) and the
3025 pseudo didn't get a hard reg, we must replace this with the
3026 eliminated version of the memory location because push_reloads
3027 may do the replacement in certain circumstances. */
3028 if (GET_CODE (SUBREG_REG (x)) == REG
3029 && (GET_MODE_SIZE (GET_MODE (x))
3030 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3031 && reg_equiv_memory_loc != 0
3032 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
3034 new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
3037 /* If we didn't change anything, we must retain the pseudo. */
3038 if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
3039 new = SUBREG_REG (x);
3042 /* Otherwise, ensure NEW isn't shared in case we have to reload
3044 new = copy_rtx (new);
3046 /* In this case, we must show that the pseudo is used in this
3047 insn so that delete_output_reload will do the right thing. */
3048 if (insn != 0 && GET_CODE (insn) != EXPR_LIST
3049 && GET_CODE (insn) != INSN_LIST)
3050 emit_insn_before (gen_rtx (USE, VOIDmode, SUBREG_REG (x)),
3055 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
3057 if (new != XEXP (x, 0))
3059 if (GET_CODE (new) == MEM
3060 && (GET_MODE_SIZE (GET_MODE (x))
3061 <= GET_MODE_SIZE (GET_MODE (new)))
3062 #ifdef LOAD_EXTEND_OP
3063 /* On these machines we will be reloading what is
3064 inside the SUBREG if it originally was a pseudo and
3065 the inner and outer modes are both a word or
3066 smaller. So leave the SUBREG then. */
3067 && ! (GET_CODE (SUBREG_REG (x)) == REG
3068 && GET_MODE_SIZE (GET_MODE (x)) <= UNITS_PER_WORD
3069 && GET_MODE_SIZE (GET_MODE (new)) <= UNITS_PER_WORD
3070 && (GET_MODE_SIZE (GET_MODE (x))
3071 > GET_MODE_SIZE (GET_MODE (new)))
3072 && INTEGRAL_MODE_P (GET_MODE (new))
3073 && LOAD_EXTEND_OP (GET_MODE (new)) != NIL)
3077 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
3078 enum machine_mode mode = GET_MODE (x);
3080 if (BYTES_BIG_ENDIAN)
3081 offset += (MIN (UNITS_PER_WORD,
3082 GET_MODE_SIZE (GET_MODE (new)))
3083 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
3085 PUT_MODE (new, mode);
3086 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
3090 return gen_rtx (SUBREG, GET_MODE (x), new, SUBREG_WORD (x));
3096 /* If using a register that is the source of an eliminate we still
3097 think can be performed, note it cannot be performed since we don't
3098 know how this register is used. */
3099 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3100 if (ep->from_rtx == XEXP (x, 0))
3101 ep->can_eliminate = 0;
3103 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3104 if (new != XEXP (x, 0))
3105 return gen_rtx (code, GET_MODE (x), new);
3109 /* If clobbering a register that is the replacement register for an
3110 elimination we still think can be performed, note that it cannot
3111 be performed. Otherwise, we need not be concerned about it. */
3112 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3113 if (ep->to_rtx == XEXP (x, 0))
3114 ep->can_eliminate = 0;
3116 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3117 if (new != XEXP (x, 0))
3118 return gen_rtx (code, GET_MODE (x), new);
3124 /* Properly handle sharing input and constraint vectors. */
3125 if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
3127 /* When we come to a new vector not seen before,
3128 scan all its elements; keep the old vector if none
3129 of them changes; otherwise, make a copy. */
3130 old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
3131 temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
3132 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3133 temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
3136 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3137 if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
3140 if (i == ASM_OPERANDS_INPUT_LENGTH (x))
3141 new_asm_operands_vec = old_asm_operands_vec;
3143 new_asm_operands_vec
3144 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
3147 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
3148 if (new_asm_operands_vec == old_asm_operands_vec)
3151 new = gen_rtx (ASM_OPERANDS, VOIDmode, ASM_OPERANDS_TEMPLATE (x),
3152 ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
3153 ASM_OPERANDS_OUTPUT_IDX (x), new_asm_operands_vec,
3154 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
3155 ASM_OPERANDS_SOURCE_FILE (x),
3156 ASM_OPERANDS_SOURCE_LINE (x));
3157 new->volatil = x->volatil;
3162 /* Check for setting a register that we know about. */
3163 if (GET_CODE (SET_DEST (x)) == REG)
3165 /* See if this is setting the replacement register for an
3168 If DEST is the hard frame pointer, we do nothing because we
3169 assume that all assignments to the frame pointer are for
3170 non-local gotos and are being done at a time when they are valid
3171 and do not disturb anything else. Some machines want to
3172 eliminate a fake argument pointer (or even a fake frame pointer)
3173 with either the real frame or the stack pointer. Assignments to
3174 the hard frame pointer must not prevent this elimination. */
3176 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3178 if (ep->to_rtx == SET_DEST (x)
3179 && SET_DEST (x) != hard_frame_pointer_rtx)
3181 /* If it is being incremented, adjust the offset. Otherwise,
3182 this elimination can't be done. */
3183 rtx src = SET_SRC (x);
3185 if (GET_CODE (src) == PLUS
3186 && XEXP (src, 0) == SET_DEST (x)
3187 && GET_CODE (XEXP (src, 1)) == CONST_INT)
3188 ep->offset -= INTVAL (XEXP (src, 1));
3190 ep->can_eliminate = 0;
3193 /* Now check to see we are assigning to a register that can be
3194 eliminated. If so, it must be as part of a PARALLEL, since we
3195 will not have been called if this is a single SET. So indicate
3196 that we can no longer eliminate this reg. */
3197 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3199 if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
3200 ep->can_eliminate = 0;
3203 /* Now avoid the loop below in this common case. */
3205 rtx new0 = eliminate_regs (SET_DEST (x), 0, insn);
3206 rtx new1 = eliminate_regs (SET_SRC (x), 0, insn);
3208 /* If SET_DEST changed from a REG to a MEM and INSN is an insn,
3209 write a CLOBBER insn. */
3210 if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
3211 && insn != 0 && GET_CODE (insn) != EXPR_LIST
3212 && GET_CODE (insn) != INSN_LIST)
3213 emit_insn_after (gen_rtx (CLOBBER, VOIDmode, SET_DEST (x)), insn);
3215 if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
3216 return gen_rtx (SET, VOIDmode, new0, new1);
3222 /* Our only special processing is to pass the mode of the MEM to our
3223 recursive call and copy the flags. While we are here, handle this
3224 case more efficiently. */
3225 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
3226 if (new != XEXP (x, 0))
3228 new = gen_rtx (MEM, GET_MODE (x), new);
3229 new->volatil = x->volatil;
3230 new->unchanging = x->unchanging;
3231 new->in_struct = x->in_struct;
3238 /* Process each of our operands recursively. If any have changed, make a
3240 fmt = GET_RTX_FORMAT (code);
3241 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3245 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
3246 if (new != XEXP (x, i) && ! copied)
3248 rtx new_x = rtx_alloc (code);
3249 bcopy ((char *) x, (char *) new_x,
3250 (sizeof (*new_x) - sizeof (new_x->fld)
3251 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
3257 else if (*fmt == 'E')
3260 for (j = 0; j < XVECLEN (x, i); j++)
3262 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
3263 if (new != XVECEXP (x, i, j) && ! copied_vec)
3265 rtvec new_v = gen_rtvec_vv (XVECLEN (x, i),
3269 rtx new_x = rtx_alloc (code);
3270 bcopy ((char *) x, (char *) new_x,
3271 (sizeof (*new_x) - sizeof (new_x->fld)
3272 + (sizeof (new_x->fld[0])
3273 * GET_RTX_LENGTH (code))));
3277 XVEC (x, i) = new_v;
3280 XVECEXP (x, i, j) = new;
3288 /* Scan INSN and eliminate all eliminable registers in it.
3290 If REPLACE is nonzero, do the replacement destructively. Also
3291 delete the insn as dead it if it is setting an eliminable register.
3293 If REPLACE is zero, do all our allocations in reload_obstack.
3295 If no eliminations were done and this insn doesn't require any elimination
3296 processing (these are not identical conditions: it might be updating sp,
3297 but not referencing fp; this needs to be seen during reload_as_needed so
3298 that the offset between fp and sp can be taken into consideration), zero
3299 is returned. Otherwise, 1 is returned. */
3302 eliminate_regs_in_insn (insn, replace)
3306 rtx old_body = PATTERN (insn);
3307 rtx old_set = single_set (insn);
3310 struct elim_table *ep;
3313 push_obstacks (&reload_obstack, &reload_obstack);
3315 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
3316 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3318 /* Check for setting an eliminable register. */
3319 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3320 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3322 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3323 /* If this is setting the frame pointer register to the
3324 hardware frame pointer register and this is an elimination
3325 that will be done (tested above), this insn is really
3326 adjusting the frame pointer downward to compensate for
3327 the adjustment done before a nonlocal goto. */
3328 if (ep->from == FRAME_POINTER_REGNUM
3329 && ep->to == HARD_FRAME_POINTER_REGNUM)
3331 rtx src = SET_SRC (old_set);
3333 rtx prev_insn, prev_set;
3335 if (src == ep->to_rtx)
3337 else if (GET_CODE (src) == PLUS
3338 && GET_CODE (XEXP (src, 0)) == CONST_INT)
3339 offset = INTVAL (XEXP (src, 0)), ok = 1;
3340 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
3341 && (prev_set = single_set (prev_insn)) != 0
3342 && rtx_equal_p (SET_DEST (prev_set), src))
3344 src = SET_SRC (prev_set);
3345 if (src == ep->to_rtx)
3347 else if (GET_CODE (src) == PLUS
3348 && GET_CODE (XEXP (src, 0)) == CONST_INT
3349 && XEXP (src, 1) == ep->to_rtx)
3350 offset = INTVAL (XEXP (src, 0)), ok = 1;
3351 else if (GET_CODE (src) == PLUS
3352 && GET_CODE (XEXP (src, 1)) == CONST_INT
3353 && XEXP (src, 0) == ep->to_rtx)
3354 offset = INTVAL (XEXP (src, 1)), ok = 1;
3362 = plus_constant (ep->to_rtx, offset - ep->offset);
3364 /* First see if this insn remains valid when we
3365 make the change. If not, keep the INSN_CODE
3366 the same and let reload fit it up. */
3367 validate_change (insn, &SET_SRC (old_set), src, 1);
3368 validate_change (insn, &SET_DEST (old_set),
3370 if (! apply_change_group ())
3372 SET_SRC (old_set) = src;
3373 SET_DEST (old_set) = ep->to_rtx;
3383 /* In this case this insn isn't serving a useful purpose. We
3384 will delete it in reload_as_needed once we know that this
3385 elimination is, in fact, being done.
3387 If REPLACE isn't set, we can't delete this insn, but needn't
3388 process it since it won't be used unless something changes. */
3390 delete_dead_insn (insn);
3395 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3396 in the insn is the negative of the offset in FROM. Substitute
3397 (set (reg) (reg to)) for the insn and change its code.
3399 We have to do this here, rather than in eliminate_regs, do that we can
3400 change the insn code. */
3402 if (GET_CODE (SET_SRC (old_set)) == PLUS
3403 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3404 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT)
3405 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3407 if (ep->from_rtx == XEXP (SET_SRC (old_set), 0)
3408 && ep->can_eliminate)
3410 /* We must stop at the first elimination that will be used.
3411 If this one would replace the PLUS with a REG, do it
3412 now. Otherwise, quit the loop and let eliminate_regs
3413 do its normal replacement. */
3414 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_set), 1)))
3416 /* We assume here that we don't need a PARALLEL of
3417 any CLOBBERs for this assignment. There's not
3418 much we can do if we do need it. */
3419 PATTERN (insn) = gen_rtx (SET, VOIDmode,
3420 SET_DEST (old_set), ep->to_rtx);
3421 INSN_CODE (insn) = -1;
3430 old_asm_operands_vec = 0;
3432 /* Replace the body of this insn with a substituted form. If we changed
3433 something, return non-zero.
3435 If we are replacing a body that was a (set X (plus Y Z)), try to
3436 re-recognize the insn. We do this in case we had a simple addition
3437 but now can do this as a load-address. This saves an insn in this
3440 new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX);
3441 if (new_body != old_body)
3443 /* If we aren't replacing things permanently and we changed something,
3444 make another copy to ensure that all the RTL is new. Otherwise
3445 things can go wrong if find_reload swaps commutative operands
3446 and one is inside RTL that has been copied while the other is not. */
3448 /* Don't copy an asm_operands because (1) there's no need and (2)
3449 copy_rtx can't do it properly when there are multiple outputs. */
3450 if (! replace && asm_noperands (old_body) < 0)
3451 new_body = copy_rtx (new_body);
3453 /* If we had a move insn but now we don't, rerecognize it. This will
3454 cause spurious re-recognition if the old move had a PARALLEL since
3455 the new one still will, but we can't call single_set without
3456 having put NEW_BODY into the insn and the re-recognition won't
3457 hurt in this rare case. */
3459 && ((GET_CODE (SET_SRC (old_set)) == REG
3460 && (GET_CODE (new_body) != SET
3461 || GET_CODE (SET_SRC (new_body)) != REG))
3462 /* If this was a load from or store to memory, compare
3463 the MEM in recog_operand to the one in the insn. If they
3464 are not equal, then rerecognize the insn. */
3466 && ((GET_CODE (SET_SRC (old_set)) == MEM
3467 && SET_SRC (old_set) != recog_operand[1])
3468 || (GET_CODE (SET_DEST (old_set)) == MEM
3469 && SET_DEST (old_set) != recog_operand[0])))
3470 /* If this was an add insn before, rerecognize. */
3471 || GET_CODE (SET_SRC (old_set)) == PLUS))
3473 if (! validate_change (insn, &PATTERN (insn), new_body, 0))
3474 /* If recognition fails, store the new body anyway.
3475 It's normal to have recognition failures here
3476 due to bizarre memory addresses; reloading will fix them. */
3477 PATTERN (insn) = new_body;
3480 PATTERN (insn) = new_body;
3485 /* Loop through all elimination pairs. See if any have changed and
3486 recalculate the number not at initial offset.
3488 Compute the maximum offset (minimum offset if the stack does not
3489 grow downward) for each elimination pair.
3491 We also detect a cases where register elimination cannot be done,
3492 namely, if a register would be both changed and referenced outside a MEM
3493 in the resulting insn since such an insn is often undefined and, even if
3494 not, we cannot know what meaning will be given to it. Note that it is
3495 valid to have a register used in an address in an insn that changes it
3496 (presumably with a pre- or post-increment or decrement).
3498 If anything changes, return nonzero. */
3500 num_not_at_initial_offset = 0;
3501 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3503 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3504 ep->can_eliminate = 0;
3506 ep->ref_outside_mem = 0;
3508 if (ep->previous_offset != ep->offset)
3511 ep->previous_offset = ep->offset;
3512 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3513 num_not_at_initial_offset++;
3515 #ifdef STACK_GROWS_DOWNWARD
3516 ep->max_offset = MAX (ep->max_offset, ep->offset);
3518 ep->max_offset = MIN (ep->max_offset, ep->offset);
3523 /* If we changed something, perform elimination in REG_NOTES. This is
3524 needed even when REPLACE is zero because a REG_DEAD note might refer
3525 to a register that we eliminate and could cause a different number
3526 of spill registers to be needed in the final reload pass than in
3528 if (val && REG_NOTES (insn) != 0)
3529 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3537 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3538 replacement we currently believe is valid, mark it as not eliminable if X
3539 modifies DEST in any way other than by adding a constant integer to it.
3541 If DEST is the frame pointer, we do nothing because we assume that
3542 all assignments to the hard frame pointer are nonlocal gotos and are being
3543 done at a time when they are valid and do not disturb anything else.
3544 Some machines want to eliminate a fake argument pointer with either the
3545 frame or stack pointer. Assignments to the hard frame pointer must not
3546 prevent this elimination.
3548 Called via note_stores from reload before starting its passes to scan
3549 the insns of the function. */
3552 mark_not_eliminable (dest, x)
3558 /* A SUBREG of a hard register here is just changing its mode. We should
3559 not see a SUBREG of an eliminable hard register, but check just in
3561 if (GET_CODE (dest) == SUBREG)
3562 dest = SUBREG_REG (dest);
3564 if (dest == hard_frame_pointer_rtx)
3567 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3568 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3569 && (GET_CODE (x) != SET
3570 || GET_CODE (SET_SRC (x)) != PLUS
3571 || XEXP (SET_SRC (x), 0) != dest
3572 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3574 reg_eliminate[i].can_eliminate_previous
3575 = reg_eliminate[i].can_eliminate = 0;
3580 /* Kick all pseudos out of hard register REGNO.
3581 If GLOBAL is nonzero, try to find someplace else to put them.
3582 If DUMPFILE is nonzero, log actions taken on that file.
3584 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3585 because we found we can't eliminate some register. In the case, no pseudos
3586 are allowed to be in the register, even if they are only in a block that
3587 doesn't require spill registers, unlike the case when we are spilling this
3588 hard reg to produce another spill register.
3590 Return nonzero if any pseudos needed to be kicked out. */
3593 spill_hard_reg (regno, global, dumpfile, cant_eliminate)
3599 enum reg_class class = REGNO_REG_CLASS (regno);
3600 int something_changed = 0;
3603 SET_HARD_REG_BIT (forbidden_regs, regno);
3606 regs_ever_live[regno] = 1;
3608 /* Spill every pseudo reg that was allocated to this reg
3609 or to something that overlaps this reg. */
3611 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3612 if (reg_renumber[i] >= 0
3613 && reg_renumber[i] <= regno
3615 + HARD_REGNO_NREGS (reg_renumber[i],
3616 PSEUDO_REGNO_MODE (i))
3619 /* If this register belongs solely to a basic block which needed no
3620 spilling of any class that this register is contained in,
3621 leave it be, unless we are spilling this register because
3622 it was a hard register that can't be eliminated. */
3624 if (! cant_eliminate
3625 && basic_block_needs[0]
3626 && reg_basic_block[i] >= 0
3627 && basic_block_needs[(int) class][reg_basic_block[i]] == 0)
3631 for (p = reg_class_superclasses[(int) class];
3632 *p != LIM_REG_CLASSES; p++)
3633 if (basic_block_needs[(int) *p][reg_basic_block[i]] > 0)
3636 if (*p == LIM_REG_CLASSES)
3640 /* Mark it as no longer having a hard register home. */
3641 reg_renumber[i] = -1;
3642 /* We will need to scan everything again. */
3643 something_changed = 1;
3645 retry_global_alloc (i, forbidden_regs);
3647 alter_reg (i, regno);
3650 if (reg_renumber[i] == -1)
3651 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3653 fprintf (dumpfile, " Register %d now in %d.\n\n",
3654 i, reg_renumber[i]);
3657 for (i = 0; i < scratch_list_length; i++)
3659 if (scratch_list[i] && REGNO (scratch_list[i]) == regno)
3661 if (! cant_eliminate && basic_block_needs[0]
3662 && ! basic_block_needs[(int) class][scratch_block[i]])
3666 for (p = reg_class_superclasses[(int) class];
3667 *p != LIM_REG_CLASSES; p++)
3668 if (basic_block_needs[(int) *p][scratch_block[i]] > 0)
3671 if (*p == LIM_REG_CLASSES)
3674 PUT_CODE (scratch_list[i], SCRATCH);
3675 scratch_list[i] = 0;
3676 something_changed = 1;
3681 return something_changed;
3684 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3685 Also mark any hard registers used to store user variables as
3686 forbidden from being used for spill registers. */
3689 scan_paradoxical_subregs (x)
3694 register enum rtx_code code = GET_CODE (x);
3699 #ifdef SMALL_REGISTER_CLASSES
3700 if (SMALL_REGISTER_CLASSES
3701 && REGNO (x) < FIRST_PSEUDO_REGISTER
3702 && REG_USERVAR_P (x))
3703 SET_HARD_REG_BIT (forbidden_regs, REGNO (x));
3719 if (GET_CODE (SUBREG_REG (x)) == REG
3720 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3721 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3722 = GET_MODE_SIZE (GET_MODE (x));
3726 fmt = GET_RTX_FORMAT (code);
3727 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3730 scan_paradoxical_subregs (XEXP (x, i));
3731 else if (fmt[i] == 'E')
3734 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3735 scan_paradoxical_subregs (XVECEXP (x, i, j));
3741 hard_reg_use_compare (p1p, p2p)
3742 const GENERIC_PTR p1p;
3743 const GENERIC_PTR p2p;
3745 struct hard_reg_n_uses *p1 = (struct hard_reg_n_uses *)p1p,
3746 *p2 = (struct hard_reg_n_uses *)p2p;
3747 int tem = p1->uses - p2->uses;
3748 if (tem != 0) return tem;
3749 /* If regs are equally good, sort by regno,
3750 so that the results of qsort leave nothing to chance. */
3751 return p1->regno - p2->regno;
3754 /* Choose the order to consider regs for use as reload registers
3755 based on how much trouble would be caused by spilling one.
3756 Store them in order of decreasing preference in potential_reload_regs. */
3759 order_regs_for_reload (global)
3766 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
3768 CLEAR_HARD_REG_SET (bad_spill_regs);
3770 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3771 potential_reload_regs[i] = -1;
3773 /* Count number of uses of each hard reg by pseudo regs allocated to it
3774 and then order them by decreasing use. */
3776 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3778 hard_reg_n_uses[i].uses = 0;
3779 hard_reg_n_uses[i].regno = i;
3782 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3784 int regno = reg_renumber[i];
3787 int lim = regno + HARD_REGNO_NREGS (regno, PSEUDO_REGNO_MODE (i));
3790 /* If allocated by local-alloc, show more uses since
3791 we're not going to be able to reallocate it, but
3792 we might if allocated by global alloc. */
3793 if (global && reg_allocno[i] < 0)
3794 hard_reg_n_uses[regno].uses += (reg_n_refs[i] + 1) / 2;
3796 hard_reg_n_uses[regno++].uses += reg_n_refs[i];
3799 large += reg_n_refs[i];
3802 /* Now fixed registers (which cannot safely be used for reloading)
3803 get a very high use count so they will be considered least desirable.
3804 Registers used explicitly in the rtl code are almost as bad. */
3806 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3810 hard_reg_n_uses[i].uses += 2 * large + 2;
3811 SET_HARD_REG_BIT (bad_spill_regs, i);
3813 else if (regs_explicitly_used[i])
3815 hard_reg_n_uses[i].uses += large + 1;
3816 /* ??? We are doing this here because of the potential that
3817 bad code may be generated if a register explicitly used in
3818 an insn was used as a spill register for that insn. But
3819 not using these are spill registers may lose on some machine.
3820 We'll have to see how this works out. */
3821 #ifdef SMALL_REGISTER_CLASSES
3822 if (! SMALL_REGISTER_CLASSES)
3824 SET_HARD_REG_BIT (bad_spill_regs, i);
3827 hard_reg_n_uses[HARD_FRAME_POINTER_REGNUM].uses += 2 * large + 2;
3828 SET_HARD_REG_BIT (bad_spill_regs, HARD_FRAME_POINTER_REGNUM);
3830 #ifdef ELIMINABLE_REGS
3831 /* If registers other than the frame pointer are eliminable, mark them as
3833 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3835 hard_reg_n_uses[reg_eliminate[i].from].uses += 2 * large + 2;
3836 SET_HARD_REG_BIT (bad_spill_regs, reg_eliminate[i].from);
3840 /* Prefer registers not so far used, for use in temporary loading.
3841 Among them, if REG_ALLOC_ORDER is defined, use that order.
3842 Otherwise, prefer registers not preserved by calls. */
3844 #ifdef REG_ALLOC_ORDER
3845 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3847 int regno = reg_alloc_order[i];
3849 if (hard_reg_n_uses[regno].uses == 0)
3850 potential_reload_regs[o++] = regno;
3853 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3855 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i])
3856 potential_reload_regs[o++] = i;
3858 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3860 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i])
3861 potential_reload_regs[o++] = i;
3865 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
3866 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
3868 /* Now add the regs that are already used,
3869 preferring those used less often. The fixed and otherwise forbidden
3870 registers will be at the end of this list. */
3872 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3873 if (hard_reg_n_uses[i].uses != 0)
3874 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
3877 /* Used in reload_as_needed to sort the spilled regs. */
3880 compare_spill_regs (r1p, r2p)
3881 const GENERIC_PTR r1p;
3882 const GENERIC_PTR r2p;
3884 short r1 = *(short *)r1p, r2 = *(short *)r2p;
3888 /* Reload pseudo-registers into hard regs around each insn as needed.
3889 Additional register load insns are output before the insn that needs it
3890 and perhaps store insns after insns that modify the reloaded pseudo reg.
3892 reg_last_reload_reg and reg_reloaded_contents keep track of
3893 which registers are already available in reload registers.
3894 We update these for the reloads that we perform,
3895 as the insns are scanned. */
3898 reload_as_needed (first, live_known)
3908 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
3909 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
3910 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
3911 bzero ((char *) reg_last_reload_reg, max_regno * sizeof (rtx));
3912 reg_has_output_reload = (char *) alloca (max_regno);
3913 for (i = 0; i < n_spills; i++)
3915 reg_reloaded_contents[i] = -1;
3916 reg_reloaded_insn[i] = 0;
3919 /* Reset all offsets on eliminable registers to their initial values. */
3920 #ifdef ELIMINABLE_REGS
3921 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3923 INITIAL_ELIMINATION_OFFSET (reg_eliminate[i].from, reg_eliminate[i].to,
3924 reg_eliminate[i].initial_offset);
3925 reg_eliminate[i].previous_offset
3926 = reg_eliminate[i].offset = reg_eliminate[i].initial_offset;
3929 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
3930 reg_eliminate[0].previous_offset
3931 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
3934 num_not_at_initial_offset = 0;
3936 /* Order the spilled regs, so that allocate_reload_regs can guarantee to
3937 pack registers with group needs. */
3940 qsort (spill_regs, n_spills, sizeof (short), compare_spill_regs);
3941 for (i = 0; i < n_spills; i++)
3942 spill_reg_order[spill_regs[i]] = i;
3945 for (insn = first; insn;)
3947 register rtx next = NEXT_INSN (insn);
3949 /* Notice when we move to a new basic block. */
3950 if (live_known && this_block + 1 < n_basic_blocks
3951 && insn == basic_block_head[this_block+1])
3954 /* If we pass a label, copy the offsets from the label information
3955 into the current offsets of each elimination. */
3956 if (GET_CODE (insn) == CODE_LABEL)
3958 num_not_at_initial_offset = 0;
3959 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3961 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
3962 = offsets_at[CODE_LABEL_NUMBER (insn)][i];
3963 if (reg_eliminate[i].can_eliminate
3964 && (reg_eliminate[i].offset
3965 != reg_eliminate[i].initial_offset))
3966 num_not_at_initial_offset++;
3970 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3972 rtx avoid_return_reg = 0;
3973 rtx oldpat = PATTERN (insn);
3975 #ifdef SMALL_REGISTER_CLASSES
3976 /* Set avoid_return_reg if this is an insn
3977 that might use the value of a function call. */
3978 if (SMALL_REGISTER_CLASSES && GET_CODE (insn) == CALL_INSN)
3980 if (GET_CODE (PATTERN (insn)) == SET)
3981 after_call = SET_DEST (PATTERN (insn));
3982 else if (GET_CODE (PATTERN (insn)) == PARALLEL
3983 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
3984 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
3988 else if (SMALL_REGISTER_CLASSES
3990 && !(GET_CODE (PATTERN (insn)) == SET
3991 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
3993 if (reg_referenced_p (after_call, PATTERN (insn)))
3994 avoid_return_reg = after_call;
3997 #endif /* SMALL_REGISTER_CLASSES */
3999 /* If this is a USE and CLOBBER of a MEM, ensure that any
4000 references to eliminable registers have been removed. */
4002 if ((GET_CODE (PATTERN (insn)) == USE
4003 || GET_CODE (PATTERN (insn)) == CLOBBER)
4004 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
4005 XEXP (XEXP (PATTERN (insn), 0), 0)
4006 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4007 GET_MODE (XEXP (PATTERN (insn), 0)), NULL_RTX);
4009 /* If we need to do register elimination processing, do so.
4010 This might delete the insn, in which case we are done. */
4011 if (num_eliminable && GET_MODE (insn) == QImode)
4013 eliminate_regs_in_insn (insn, 1);
4014 if (GET_CODE (insn) == NOTE)
4021 if (GET_MODE (insn) == VOIDmode)
4023 /* First find the pseudo regs that must be reloaded for this insn.
4024 This info is returned in the tables reload_... (see reload.h).
4025 Also modify the body of INSN by substituting RELOAD
4026 rtx's for those pseudo regs. */
4029 bzero (reg_has_output_reload, max_regno);
4030 CLEAR_HARD_REG_SET (reg_is_output_reload);
4032 find_reloads (insn, 1, spill_indirect_levels, live_known,
4038 rtx prev = PREV_INSN (insn), next = NEXT_INSN (insn);
4042 /* If this block has not had spilling done for a
4043 particular clas and we have any non-optionals that need a
4044 spill reg in that class, abort. */
4046 for (class = 0; class < N_REG_CLASSES; class++)
4047 if (basic_block_needs[class] != 0
4048 && basic_block_needs[class][this_block] == 0)
4049 for (i = 0; i < n_reloads; i++)
4050 if (class == (int) reload_reg_class[i]
4051 && reload_reg_rtx[i] == 0
4052 && ! reload_optional[i]
4053 && (reload_in[i] != 0 || reload_out[i] != 0
4054 || reload_secondary_p[i] != 0))
4055 fatal_insn ("Non-optional registers need a spill register", insn);
4057 /* Now compute which reload regs to reload them into. Perhaps
4058 reusing reload regs from previous insns, or else output
4059 load insns to reload them. Maybe output store insns too.
4060 Record the choices of reload reg in reload_reg_rtx. */
4061 choose_reload_regs (insn, avoid_return_reg);
4063 #ifdef SMALL_REGISTER_CLASSES
4064 /* Merge any reloads that we didn't combine for fear of
4065 increasing the number of spill registers needed but now
4066 discover can be safely merged. */
4067 if (SMALL_REGISTER_CLASSES)
4068 merge_assigned_reloads (insn);
4071 /* Generate the insns to reload operands into or out of
4072 their reload regs. */
4073 emit_reload_insns (insn);
4075 /* Substitute the chosen reload regs from reload_reg_rtx
4076 into the insn's body (or perhaps into the bodies of other
4077 load and store insn that we just made for reloading
4078 and that we moved the structure into). */
4081 /* If this was an ASM, make sure that all the reload insns
4082 we have generated are valid. If not, give an error
4085 if (asm_noperands (PATTERN (insn)) >= 0)
4086 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4087 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
4088 && (recog_memoized (p) < 0
4089 || (insn_extract (p),
4090 ! constrain_operands (INSN_CODE (p), 1))))
4092 error_for_asm (insn,
4093 "`asm' operand requires impossible reload");
4095 NOTE_SOURCE_FILE (p) = 0;
4096 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
4099 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4100 is no longer validly lying around to save a future reload.
4101 Note that this does not detect pseudos that were reloaded
4102 for this insn in order to be stored in
4103 (obeying register constraints). That is correct; such reload
4104 registers ARE still valid. */
4105 note_stores (oldpat, forget_old_reloads_1);
4107 /* There may have been CLOBBER insns placed after INSN. So scan
4108 between INSN and NEXT and use them to forget old reloads. */
4109 for (x = NEXT_INSN (insn); x != next; x = NEXT_INSN (x))
4110 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
4111 note_stores (PATTERN (x), forget_old_reloads_1);
4114 /* Likewise for regs altered by auto-increment in this insn.
4115 But note that the reg-notes are not changed by reloading:
4116 they still contain the pseudo-regs, not the spill regs. */
4117 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4118 if (REG_NOTE_KIND (x) == REG_INC)
4120 /* See if this pseudo reg was reloaded in this insn.
4121 If so, its last-reload info is still valid
4122 because it is based on this insn's reload. */
4123 for (i = 0; i < n_reloads; i++)
4124 if (reload_out[i] == XEXP (x, 0))
4128 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX);
4132 /* A reload reg's contents are unknown after a label. */
4133 if (GET_CODE (insn) == CODE_LABEL)
4134 for (i = 0; i < n_spills; i++)
4136 reg_reloaded_contents[i] = -1;
4137 reg_reloaded_insn[i] = 0;
4140 /* Don't assume a reload reg is still good after a call insn
4141 if it is a call-used reg. */
4142 else if (GET_CODE (insn) == CALL_INSN)
4143 for (i = 0; i < n_spills; i++)
4144 if (call_used_regs[spill_regs[i]])
4146 reg_reloaded_contents[i] = -1;
4147 reg_reloaded_insn[i] = 0;
4150 /* In case registers overlap, allow certain insns to invalidate
4151 particular hard registers. */
4153 #ifdef INSN_CLOBBERS_REGNO_P
4154 for (i = 0 ; i < n_spills ; i++)
4155 if (INSN_CLOBBERS_REGNO_P (insn, spill_regs[i]))
4157 reg_reloaded_contents[i] = -1;
4158 reg_reloaded_insn[i] = 0;
4170 /* Discard all record of any value reloaded from X,
4171 or reloaded in X from someplace else;
4172 unless X is an output reload reg of the current insn.
4174 X may be a hard reg (the reload reg)
4175 or it may be a pseudo reg that was reloaded from. */
4178 forget_old_reloads_1 (x, ignored)
4186 /* note_stores does give us subregs of hard regs. */
4187 while (GET_CODE (x) == SUBREG)
4189 offset += SUBREG_WORD (x);
4193 if (GET_CODE (x) != REG)
4196 regno = REGNO (x) + offset;
4198 if (regno >= FIRST_PSEUDO_REGISTER)
4203 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4204 /* Storing into a spilled-reg invalidates its contents.
4205 This can happen if a block-local pseudo is allocated to that reg
4206 and it wasn't spilled because this block's total need is 0.
4207 Then some insn might have an optional reload and use this reg. */
4208 for (i = 0; i < nr; i++)
4209 if (spill_reg_order[regno + i] >= 0
4210 /* But don't do this if the reg actually serves as an output
4211 reload reg in the current instruction. */
4213 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)))
4215 reg_reloaded_contents[spill_reg_order[regno + i]] = -1;
4216 reg_reloaded_insn[spill_reg_order[regno + i]] = 0;
4220 /* Since value of X has changed,
4221 forget any value previously copied from it. */
4224 /* But don't forget a copy if this is the output reload
4225 that establishes the copy's validity. */
4226 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4227 reg_last_reload_reg[regno + nr] = 0;
4230 /* For each reload, the mode of the reload register. */
4231 static enum machine_mode reload_mode[MAX_RELOADS];
4233 /* For each reload, the largest number of registers it will require. */
4234 static int reload_nregs[MAX_RELOADS];
4236 /* Comparison function for qsort to decide which of two reloads
4237 should be handled first. *P1 and *P2 are the reload numbers. */
4240 reload_reg_class_lower (r1p, r2p)
4241 const GENERIC_PTR r1p;
4242 const GENERIC_PTR r2p;
4244 register int r1 = *(short *)r1p, r2 = *(short *)r2p;
4247 /* Consider required reloads before optional ones. */
4248 t = reload_optional[r1] - reload_optional[r2];
4252 /* Count all solitary classes before non-solitary ones. */
4253 t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
4254 - (reg_class_size[(int) reload_reg_class[r1]] == 1));
4258 /* Aside from solitaires, consider all multi-reg groups first. */
4259 t = reload_nregs[r2] - reload_nregs[r1];
4263 /* Consider reloads in order of increasing reg-class number. */
4264 t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
4268 /* If reloads are equally urgent, sort by reload number,
4269 so that the results of qsort leave nothing to chance. */
4273 /* The following HARD_REG_SETs indicate when each hard register is
4274 used for a reload of various parts of the current insn. */
4276 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4277 static HARD_REG_SET reload_reg_used;
4278 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4279 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4280 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4281 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4282 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4283 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4284 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4285 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4286 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4287 static HARD_REG_SET reload_reg_used_in_op_addr;
4288 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4289 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4290 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4291 static HARD_REG_SET reload_reg_used_in_insn;
4292 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4293 static HARD_REG_SET reload_reg_used_in_other_addr;
4295 /* If reg is in use as a reload reg for any sort of reload. */
4296 static HARD_REG_SET reload_reg_used_at_all;
4298 /* If reg is use as an inherited reload. We just mark the first register
4300 static HARD_REG_SET reload_reg_used_for_inherit;
4302 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4303 TYPE. MODE is used to indicate how many consecutive regs are
4307 mark_reload_reg_in_use (regno, opnum, type, mode)
4310 enum reload_type type;
4311 enum machine_mode mode;
4313 int nregs = HARD_REGNO_NREGS (regno, mode);
4316 for (i = regno; i < nregs + regno; i++)
4321 SET_HARD_REG_BIT (reload_reg_used, i);
4324 case RELOAD_FOR_INPUT_ADDRESS:
4325 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4328 case RELOAD_FOR_OUTPUT_ADDRESS:
4329 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4332 case RELOAD_FOR_OPERAND_ADDRESS:
4333 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4336 case RELOAD_FOR_OPADDR_ADDR:
4337 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4340 case RELOAD_FOR_OTHER_ADDRESS:
4341 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4344 case RELOAD_FOR_INPUT:
4345 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4348 case RELOAD_FOR_OUTPUT:
4349 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4352 case RELOAD_FOR_INSN:
4353 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4357 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4361 /* Similarly, but show REGNO is no longer in use for a reload. */
4364 clear_reload_reg_in_use (regno, opnum, type, mode)
4367 enum reload_type type;
4368 enum machine_mode mode;
4370 int nregs = HARD_REGNO_NREGS (regno, mode);
4373 for (i = regno; i < nregs + regno; i++)
4378 CLEAR_HARD_REG_BIT (reload_reg_used, i);
4381 case RELOAD_FOR_INPUT_ADDRESS:
4382 CLEAR_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4385 case RELOAD_FOR_OUTPUT_ADDRESS:
4386 CLEAR_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4389 case RELOAD_FOR_OPERAND_ADDRESS:
4390 CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4393 case RELOAD_FOR_OPADDR_ADDR:
4394 CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4397 case RELOAD_FOR_OTHER_ADDRESS:
4398 CLEAR_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4401 case RELOAD_FOR_INPUT:
4402 CLEAR_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4405 case RELOAD_FOR_OUTPUT:
4406 CLEAR_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4409 case RELOAD_FOR_INSN:
4410 CLEAR_HARD_REG_BIT (reload_reg_used_in_insn, i);
4416 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4417 specified by OPNUM and TYPE. */
4420 reload_reg_free_p (regno, opnum, type)
4423 enum reload_type type;
4427 /* In use for a RELOAD_OTHER means it's not available for anything. */
4428 if (TEST_HARD_REG_BIT (reload_reg_used, regno))
4434 /* In use for anything means we can't use it for RELOAD_OTHER. */
4435 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4436 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4437 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4440 for (i = 0; i < reload_n_operands; i++)
4441 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4442 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4443 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4444 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4449 case RELOAD_FOR_INPUT:
4450 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4451 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4454 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4457 /* If it is used for some other input, can't use it. */
4458 for (i = 0; i < reload_n_operands; i++)
4459 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4462 /* If it is used in a later operand's address, can't use it. */
4463 for (i = opnum + 1; i < reload_n_operands; i++)
4464 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4469 case RELOAD_FOR_INPUT_ADDRESS:
4470 /* Can't use a register if it is used for an input address for this
4471 operand or used as an input in an earlier one. */
4472 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno))
4475 for (i = 0; i < opnum; i++)
4476 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4481 case RELOAD_FOR_OUTPUT_ADDRESS:
4482 /* Can't use a register if it is used for an output address for this
4483 operand or used as an output in this or a later operand. */
4484 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4487 for (i = opnum; i < reload_n_operands; i++)
4488 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4493 case RELOAD_FOR_OPERAND_ADDRESS:
4494 for (i = 0; i < reload_n_operands; i++)
4495 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4498 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4499 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4501 case RELOAD_FOR_OPADDR_ADDR:
4502 for (i = 0; i < reload_n_operands; i++)
4503 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4506 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4508 case RELOAD_FOR_OUTPUT:
4509 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4510 outputs, or an operand address for this or an earlier output. */
4511 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4514 for (i = 0; i < reload_n_operands; i++)
4515 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4518 for (i = 0; i <= opnum; i++)
4519 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno))
4524 case RELOAD_FOR_INSN:
4525 for (i = 0; i < reload_n_operands; i++)
4526 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4527 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4530 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4531 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4533 case RELOAD_FOR_OTHER_ADDRESS:
4534 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4539 /* Return 1 if the value in reload reg REGNO, as used by a reload
4540 needed for the part of the insn specified by OPNUM and TYPE,
4541 is not in use for a reload in any prior part of the insn.
4543 We can assume that the reload reg was already tested for availability
4544 at the time it is needed, and we should not check this again,
4545 in case the reg has already been marked in use. */
4548 reload_reg_free_before_p (regno, opnum, type)
4551 enum reload_type type;
4557 case RELOAD_FOR_OTHER_ADDRESS:
4558 /* These always come first. */
4562 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4564 /* If this use is for part of the insn,
4565 check the reg is not in use for any prior part. It is tempting
4566 to try to do this by falling through from objecs that occur
4567 later in the insn to ones that occur earlier, but that will not
4568 correctly take into account the fact that here we MUST ignore
4569 things that would prevent the register from being allocated in
4570 the first place, since we know that it was allocated. */
4572 case RELOAD_FOR_OUTPUT_ADDRESS:
4573 /* Earlier reloads are for earlier outputs or their addresses,
4574 any RELOAD_FOR_INSN reloads, any inputs or their addresses, or any
4575 RELOAD_FOR_OTHER_ADDRESS reloads (we know it can't conflict with
4577 for (i = 0; i < opnum; i++)
4578 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4579 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4582 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4585 for (i = 0; i < reload_n_operands; i++)
4586 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4587 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4590 return (! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4591 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4592 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4594 case RELOAD_FOR_OUTPUT:
4595 /* This can't be used in the output address for this operand and
4596 anything that can't be used for it, except that we've already
4597 tested for RELOAD_FOR_INSN objects. */
4599 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4602 for (i = 0; i < opnum; i++)
4603 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4604 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4607 for (i = 0; i < reload_n_operands; i++)
4608 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4609 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4610 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4613 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4615 case RELOAD_FOR_OPERAND_ADDRESS:
4616 case RELOAD_FOR_OPADDR_ADDR:
4617 case RELOAD_FOR_INSN:
4618 /* These can't conflict with inputs, or each other, so all we have to
4619 test is input addresses and the addresses of OTHER items. */
4621 for (i = 0; i < reload_n_operands; i++)
4622 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4625 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4627 case RELOAD_FOR_INPUT:
4628 /* The only things earlier are the address for this and
4629 earlier inputs, other inputs (which we know we don't conflict
4630 with), and addresses of RELOAD_OTHER objects. */
4632 for (i = 0; i <= opnum; i++)
4633 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4636 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4638 case RELOAD_FOR_INPUT_ADDRESS:
4639 /* Similarly, all we have to check is for use in earlier inputs'
4641 for (i = 0; i < opnum; i++)
4642 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4645 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4650 /* Return 1 if the value in reload reg REGNO, as used by a reload
4651 needed for the part of the insn specified by OPNUM and TYPE,
4652 is still available in REGNO at the end of the insn.
4654 We can assume that the reload reg was already tested for availability
4655 at the time it is needed, and we should not check this again,
4656 in case the reg has already been marked in use. */
4659 reload_reg_reaches_end_p (regno, opnum, type)
4662 enum reload_type type;
4669 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4670 its value must reach the end. */
4673 /* If this use is for part of the insn,
4674 its value reaches if no subsequent part uses the same register.
4675 Just like the above function, don't try to do this with lots
4678 case RELOAD_FOR_OTHER_ADDRESS:
4679 /* Here we check for everything else, since these don't conflict
4680 with anything else and everything comes later. */
4682 for (i = 0; i < reload_n_operands; i++)
4683 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4684 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4685 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4686 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4689 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4690 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4691 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4693 case RELOAD_FOR_INPUT_ADDRESS:
4694 /* Similar, except that we check only for this and subsequent inputs
4695 and the address of only subsequent inputs and we do not need
4696 to check for RELOAD_OTHER objects since they are known not to
4699 for (i = opnum; i < reload_n_operands; i++)
4700 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4703 for (i = opnum + 1; i < reload_n_operands; i++)
4704 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4707 for (i = 0; i < reload_n_operands; i++)
4708 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4709 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4712 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4715 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4716 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4718 case RELOAD_FOR_INPUT:
4719 /* Similar to input address, except we start at the next operand for
4720 both input and input address and we do not check for
4721 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4724 for (i = opnum + 1; i < reload_n_operands; i++)
4725 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4726 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4729 /* ... fall through ... */
4731 case RELOAD_FOR_OPERAND_ADDRESS:
4732 /* Check outputs and their addresses. */
4734 for (i = 0; i < reload_n_operands; i++)
4735 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4736 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4741 case RELOAD_FOR_OPADDR_ADDR:
4742 for (i = 0; i < reload_n_operands; i++)
4743 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4744 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4747 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4748 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4750 case RELOAD_FOR_INSN:
4751 /* These conflict with other outputs with RELOAD_OTHER. So
4752 we need only check for output addresses. */
4756 /* ... fall through ... */
4758 case RELOAD_FOR_OUTPUT:
4759 case RELOAD_FOR_OUTPUT_ADDRESS:
4760 /* We already know these can't conflict with a later output. So the
4761 only thing to check are later output addresses. */
4762 for (i = opnum + 1; i < reload_n_operands; i++)
4763 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno))
4772 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4775 This function uses the same algorithm as reload_reg_free_p above. */
4778 reloads_conflict (r1, r2)
4781 enum reload_type r1_type = reload_when_needed[r1];
4782 enum reload_type r2_type = reload_when_needed[r2];
4783 int r1_opnum = reload_opnum[r1];
4784 int r2_opnum = reload_opnum[r2];
4786 /* RELOAD_OTHER conflicts with everything. */
4787 if (r2_type == RELOAD_OTHER)
4790 /* Otherwise, check conflicts differently for each type. */
4794 case RELOAD_FOR_INPUT:
4795 return (r2_type == RELOAD_FOR_INSN
4796 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4797 || r2_type == RELOAD_FOR_OPADDR_ADDR
4798 || r2_type == RELOAD_FOR_INPUT
4799 || (r2_type == RELOAD_FOR_INPUT_ADDRESS && r2_opnum > r1_opnum));
4801 case RELOAD_FOR_INPUT_ADDRESS:
4802 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4803 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4805 case RELOAD_FOR_OUTPUT_ADDRESS:
4806 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4807 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4809 case RELOAD_FOR_OPERAND_ADDRESS:
4810 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4811 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4813 case RELOAD_FOR_OPADDR_ADDR:
4814 return (r2_type == RELOAD_FOR_INPUT
4815 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4817 case RELOAD_FOR_OUTPUT:
4818 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4819 || (r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4820 && r2_opnum >= r1_opnum));
4822 case RELOAD_FOR_INSN:
4823 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4824 || r2_type == RELOAD_FOR_INSN
4825 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4827 case RELOAD_FOR_OTHER_ADDRESS:
4828 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4838 /* Vector of reload-numbers showing the order in which the reloads should
4840 short reload_order[MAX_RELOADS];
4842 /* Indexed by reload number, 1 if incoming value
4843 inherited from previous insns. */
4844 char reload_inherited[MAX_RELOADS];
4846 /* For an inherited reload, this is the insn the reload was inherited from,
4847 if we know it. Otherwise, this is 0. */
4848 rtx reload_inheritance_insn[MAX_RELOADS];
4850 /* If non-zero, this is a place to get the value of the reload,
4851 rather than using reload_in. */
4852 rtx reload_override_in[MAX_RELOADS];
4854 /* For each reload, the index in spill_regs of the spill register used,
4855 or -1 if we did not need one of the spill registers for this reload. */
4856 int reload_spill_index[MAX_RELOADS];
4858 /* Find a spill register to use as a reload register for reload R.
4859 LAST_RELOAD is non-zero if this is the last reload for the insn being
4862 Set reload_reg_rtx[R] to the register allocated.
4864 If NOERROR is nonzero, we return 1 if successful,
4865 or 0 if we couldn't find a spill reg and we didn't change anything. */
4868 allocate_reload_reg (r, insn, last_reload, noerror)
4880 /* If we put this reload ahead, thinking it is a group,
4881 then insist on finding a group. Otherwise we can grab a
4882 reg that some other reload needs.
4883 (That can happen when we have a 68000 DATA_OR_FP_REG
4884 which is a group of data regs or one fp reg.)
4885 We need not be so restrictive if there are no more reloads
4888 ??? Really it would be nicer to have smarter handling
4889 for that kind of reg class, where a problem like this is normal.
4890 Perhaps those classes should be avoided for reloading
4891 by use of more alternatives. */
4893 int force_group = reload_nregs[r] > 1 && ! last_reload;
4895 /* If we want a single register and haven't yet found one,
4896 take any reg in the right class and not in use.
4897 If we want a consecutive group, here is where we look for it.
4899 We use two passes so we can first look for reload regs to
4900 reuse, which are already in use for other reloads in this insn,
4901 and only then use additional registers.
4902 I think that maximizing reuse is needed to make sure we don't
4903 run out of reload regs. Suppose we have three reloads, and
4904 reloads A and B can share regs. These need two regs.
4905 Suppose A and B are given different regs.
4906 That leaves none for C. */
4907 for (pass = 0; pass < 2; pass++)
4909 /* I is the index in spill_regs.
4910 We advance it round-robin between insns to use all spill regs
4911 equally, so that inherited reloads have a chance
4912 of leapfrogging each other. Don't do this, however, when we have
4913 group needs and failure would be fatal; if we only have a relatively
4914 small number of spill registers, and more than one of them has
4915 group needs, then by starting in the middle, we may end up
4916 allocating the first one in such a way that we are not left with
4917 sufficient groups to handle the rest. */
4919 if (noerror || ! force_group)
4924 for (count = 0; count < n_spills; count++)
4926 int class = (int) reload_reg_class[r];
4928 i = (i + 1) % n_spills;
4930 if (reload_reg_free_p (spill_regs[i], reload_opnum[r],
4931 reload_when_needed[r])
4932 && TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
4933 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
4934 /* Look first for regs to share, then for unshared. But
4935 don't share regs used for inherited reloads; they are
4936 the ones we want to preserve. */
4938 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
4940 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
4943 int nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
4944 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
4945 (on 68000) got us two FP regs. If NR is 1,
4946 we would reject both of them. */
4948 nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
4949 /* If we need only one reg, we have already won. */
4952 /* But reject a single reg if we demand a group. */
4957 /* Otherwise check that as many consecutive regs as we need
4959 Also, don't use for a group registers that are
4960 needed for nongroups. */
4961 if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
4964 regno = spill_regs[i] + nr - 1;
4965 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
4966 && spill_reg_order[regno] >= 0
4967 && reload_reg_free_p (regno, reload_opnum[r],
4968 reload_when_needed[r])
4969 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
4979 /* If we found something on pass 1, omit pass 2. */
4980 if (count < n_spills)
4984 /* We should have found a spill register by now. */
4985 if (count == n_spills)
4992 /* I is the index in SPILL_REG_RTX of the reload register we are to
4993 allocate. Get an rtx for it and find its register number. */
4995 new = spill_reg_rtx[i];
4997 if (new == 0 || GET_MODE (new) != reload_mode[r])
4998 spill_reg_rtx[i] = new
4999 = gen_rtx (REG, reload_mode[r], spill_regs[i]);
5001 regno = true_regnum (new);
5003 /* Detect when the reload reg can't hold the reload mode.
5004 This used to be one `if', but Sequent compiler can't handle that. */
5005 if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5007 enum machine_mode test_mode = VOIDmode;
5009 test_mode = GET_MODE (reload_in[r]);
5010 /* If reload_in[r] has VOIDmode, it means we will load it
5011 in whatever mode the reload reg has: to wit, reload_mode[r].
5012 We have already tested that for validity. */
5013 /* Aside from that, we need to test that the expressions
5014 to reload from or into have modes which are valid for this
5015 reload register. Otherwise the reload insns would be invalid. */
5016 if (! (reload_in[r] != 0 && test_mode != VOIDmode
5017 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5018 if (! (reload_out[r] != 0
5019 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
5021 /* The reg is OK. */
5024 /* Mark as in use for this insn the reload regs we use
5026 mark_reload_reg_in_use (spill_regs[i], reload_opnum[r],
5027 reload_when_needed[r], reload_mode[r]);
5029 reload_reg_rtx[r] = new;
5030 reload_spill_index[r] = i;
5035 /* The reg is not OK. */
5040 if (asm_noperands (PATTERN (insn)) < 0)
5041 /* It's the compiler's fault. */
5042 fatal_insn ("Could not find a spill register", insn);
5044 /* It's the user's fault; the operand's mode and constraint
5045 don't match. Disable this reload so we don't crash in final. */
5046 error_for_asm (insn,
5047 "`asm' operand constraint incompatible with operand size");
5050 reload_reg_rtx[r] = 0;
5051 reload_optional[r] = 1;
5052 reload_secondary_p[r] = 1;
5057 /* Assign hard reg targets for the pseudo-registers we must reload
5058 into hard regs for this insn.
5059 Also output the instructions to copy them in and out of the hard regs.
5061 For machines with register classes, we are responsible for
5062 finding a reload reg in the proper class. */
5065 choose_reload_regs (insn, avoid_return_reg)
5067 rtx avoid_return_reg;
5070 int max_group_size = 1;
5071 enum reg_class group_class = NO_REGS;
5074 rtx save_reload_reg_rtx[MAX_RELOADS];
5075 char save_reload_inherited[MAX_RELOADS];
5076 rtx save_reload_inheritance_insn[MAX_RELOADS];
5077 rtx save_reload_override_in[MAX_RELOADS];
5078 int save_reload_spill_index[MAX_RELOADS];
5079 HARD_REG_SET save_reload_reg_used;
5080 HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
5081 HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
5082 HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS];
5083 HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS];
5084 HARD_REG_SET save_reload_reg_used_in_op_addr;
5085 HARD_REG_SET save_reload_reg_used_in_op_addr_reload;
5086 HARD_REG_SET save_reload_reg_used_in_insn;
5087 HARD_REG_SET save_reload_reg_used_in_other_addr;
5088 HARD_REG_SET save_reload_reg_used_at_all;
5090 bzero (reload_inherited, MAX_RELOADS);
5091 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5092 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5094 CLEAR_HARD_REG_SET (reload_reg_used);
5095 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5096 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5097 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5098 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5099 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5101 for (i = 0; i < reload_n_operands; i++)
5103 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5104 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5105 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5106 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5109 #ifdef SMALL_REGISTER_CLASSES
5110 /* Don't bother with avoiding the return reg
5111 if we have no mandatory reload that could use it. */
5112 if (SMALL_REGISTER_CLASSES && avoid_return_reg)
5115 int regno = REGNO (avoid_return_reg);
5117 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
5120 for (r = regno; r < regno + nregs; r++)
5121 if (spill_reg_order[r] >= 0)
5122 for (j = 0; j < n_reloads; j++)
5123 if (!reload_optional[j] && reload_reg_rtx[j] == 0
5124 && (reload_in[j] != 0 || reload_out[j] != 0
5125 || reload_secondary_p[j])
5127 TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[j]], r))
5130 avoid_return_reg = 0;
5132 #endif /* SMALL_REGISTER_CLASSES */
5134 #if 0 /* Not needed, now that we can always retry without inheritance. */
5135 /* See if we have more mandatory reloads than spill regs.
5136 If so, then we cannot risk optimizations that could prevent
5137 reloads from sharing one spill register.
5139 Since we will try finding a better register than reload_reg_rtx
5140 unless it is equal to reload_in or reload_out, count such reloads. */
5144 #ifdef SMALL_REGISTER_CLASSES
5145 if (SMALL_REGISTER_CLASSES)
5146 tem = (avoid_return_reg != 0);
5148 for (j = 0; j < n_reloads; j++)
5149 if (! reload_optional[j]
5150 && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
5151 && (reload_reg_rtx[j] == 0
5152 || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
5153 && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
5160 #ifdef SMALL_REGISTER_CLASSES
5161 /* Don't use the subroutine call return reg for a reload
5162 if we are supposed to avoid it. */
5163 if (SMALL_REGISTER_CLASSES && avoid_return_reg)
5165 int regno = REGNO (avoid_return_reg);
5167 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
5170 for (r = regno; r < regno + nregs; r++)
5171 if (spill_reg_order[r] >= 0)
5172 SET_HARD_REG_BIT (reload_reg_used, r);
5174 #endif /* SMALL_REGISTER_CLASSES */
5176 /* In order to be certain of getting the registers we need,
5177 we must sort the reloads into order of increasing register class.
5178 Then our grabbing of reload registers will parallel the process
5179 that provided the reload registers.
5181 Also note whether any of the reloads wants a consecutive group of regs.
5182 If so, record the maximum size of the group desired and what
5183 register class contains all the groups needed by this insn. */
5185 for (j = 0; j < n_reloads; j++)
5187 reload_order[j] = j;
5188 reload_spill_index[j] = -1;
5191 = (reload_inmode[j] == VOIDmode
5192 || (GET_MODE_SIZE (reload_outmode[j])
5193 > GET_MODE_SIZE (reload_inmode[j])))
5194 ? reload_outmode[j] : reload_inmode[j];
5196 reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
5198 if (reload_nregs[j] > 1)
5200 max_group_size = MAX (reload_nregs[j], max_group_size);
5201 group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
5204 /* If we have already decided to use a certain register,
5205 don't use it in another way. */
5206 if (reload_reg_rtx[j])
5207 mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j],
5208 reload_when_needed[j], reload_mode[j]);
5212 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5214 bcopy ((char *) reload_reg_rtx, (char *) save_reload_reg_rtx,
5215 sizeof reload_reg_rtx);
5216 bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
5217 bcopy ((char *) reload_inheritance_insn,
5218 (char *) save_reload_inheritance_insn,
5219 sizeof reload_inheritance_insn);
5220 bcopy ((char *) reload_override_in, (char *) save_reload_override_in,
5221 sizeof reload_override_in);
5222 bcopy ((char *) reload_spill_index, (char *) save_reload_spill_index,
5223 sizeof reload_spill_index);
5224 COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
5225 COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
5226 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
5227 reload_reg_used_in_op_addr);
5229 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr_reload,
5230 reload_reg_used_in_op_addr_reload);
5232 COPY_HARD_REG_SET (save_reload_reg_used_in_insn,
5233 reload_reg_used_in_insn);
5234 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr,
5235 reload_reg_used_in_other_addr);
5237 for (i = 0; i < reload_n_operands; i++)
5239 COPY_HARD_REG_SET (save_reload_reg_used_in_output[i],
5240 reload_reg_used_in_output[i]);
5241 COPY_HARD_REG_SET (save_reload_reg_used_in_input[i],
5242 reload_reg_used_in_input[i]);
5243 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i],
5244 reload_reg_used_in_input_addr[i]);
5245 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i],
5246 reload_reg_used_in_output_addr[i]);
5249 /* If -O, try first with inheritance, then turning it off.
5250 If not -O, don't do inheritance.
5251 Using inheritance when not optimizing leads to paradoxes
5252 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5253 because one side of the comparison might be inherited. */
5255 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5257 /* Process the reloads in order of preference just found.
5258 Beyond this point, subregs can be found in reload_reg_rtx.
5260 This used to look for an existing reloaded home for all
5261 of the reloads, and only then perform any new reloads.
5262 But that could lose if the reloads were done out of reg-class order
5263 because a later reload with a looser constraint might have an old
5264 home in a register needed by an earlier reload with a tighter constraint.
5266 To solve this, we make two passes over the reloads, in the order
5267 described above. In the first pass we try to inherit a reload
5268 from a previous insn. If there is a later reload that needs a
5269 class that is a proper subset of the class being processed, we must
5270 also allocate a spill register during the first pass.
5272 Then make a second pass over the reloads to allocate any reloads
5273 that haven't been given registers yet. */
5275 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5277 for (j = 0; j < n_reloads; j++)
5279 register int r = reload_order[j];
5281 /* Ignore reloads that got marked inoperative. */
5282 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
5285 /* If find_reloads chose a to use reload_in or reload_out as a reload
5286 register, we don't need to chose one. Otherwise, try even if it found
5287 one since we might save an insn if we find the value lying around. */
5288 if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
5289 && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
5290 || rtx_equal_p (reload_out[r], reload_reg_rtx[r])))
5293 #if 0 /* No longer needed for correct operation.
5294 It might give better code, or might not; worth an experiment? */
5295 /* If this is an optional reload, we can't inherit from earlier insns
5296 until we are sure that any non-optional reloads have been allocated.
5297 The following code takes advantage of the fact that optional reloads
5298 are at the end of reload_order. */
5299 if (reload_optional[r] != 0)
5300 for (i = 0; i < j; i++)
5301 if ((reload_out[reload_order[i]] != 0
5302 || reload_in[reload_order[i]] != 0
5303 || reload_secondary_p[reload_order[i]])
5304 && ! reload_optional[reload_order[i]]
5305 && reload_reg_rtx[reload_order[i]] == 0)
5306 allocate_reload_reg (reload_order[i], insn, 0, inheritance);
5309 /* First see if this pseudo is already available as reloaded
5310 for a previous insn. We cannot try to inherit for reloads
5311 that are smaller than the maximum number of registers needed
5312 for groups unless the register we would allocate cannot be used
5315 We could check here to see if this is a secondary reload for
5316 an object that is already in a register of the desired class.
5317 This would avoid the need for the secondary reload register.
5318 But this is complex because we can't easily determine what
5319 objects might want to be loaded via this reload. So let a register
5320 be allocated here. In `emit_reload_insns' we suppress one of the
5321 loads in the case described above. */
5325 register int regno = -1;
5326 enum machine_mode mode;
5328 if (reload_in[r] == 0)
5330 else if (GET_CODE (reload_in[r]) == REG)
5332 regno = REGNO (reload_in[r]);
5333 mode = GET_MODE (reload_in[r]);
5335 else if (GET_CODE (reload_in_reg[r]) == REG)
5337 regno = REGNO (reload_in_reg[r]);
5338 mode = GET_MODE (reload_in_reg[r]);
5341 /* This won't work, since REGNO can be a pseudo reg number.
5342 Also, it takes much more hair to keep track of all the things
5343 that can invalidate an inherited reload of part of a pseudoreg. */
5344 else if (GET_CODE (reload_in[r]) == SUBREG
5345 && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
5346 regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
5349 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5351 i = spill_reg_order[REGNO (reg_last_reload_reg[regno])];
5353 if (reg_reloaded_contents[i] == regno
5354 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
5355 >= GET_MODE_SIZE (mode))
5356 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
5357 && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5359 && (reload_nregs[r] == max_group_size
5360 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5362 && reload_reg_free_p (spill_regs[i], reload_opnum[r],
5363 reload_when_needed[r])
5364 && reload_reg_free_before_p (spill_regs[i],
5366 reload_when_needed[r]))
5368 /* If a group is needed, verify that all the subsequent
5369 registers still have their values intact. */
5371 = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
5374 for (k = 1; k < nr; k++)
5375 if (reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
5383 /* We found a register that contains the
5384 value we need. If this register is the
5385 same as an `earlyclobber' operand of the
5386 current insn, just mark it as a place to
5387 reload from since we can't use it as the
5388 reload register itself. */
5390 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5391 if (reg_overlap_mentioned_for_reload_p
5392 (reg_last_reload_reg[regno],
5393 reload_earlyclobbers[i1]))
5396 if (i1 != n_earlyclobbers
5397 /* Don't really use the inherited spill reg
5398 if we need it wider than we've got it. */
5399 || (GET_MODE_SIZE (reload_mode[r])
5400 > GET_MODE_SIZE (mode)))
5401 reload_override_in[r] = reg_last_reload_reg[regno];
5405 /* We can use this as a reload reg. */
5406 /* Mark the register as in use for this part of
5408 mark_reload_reg_in_use (spill_regs[i],
5410 reload_when_needed[r],
5412 reload_reg_rtx[r] = reg_last_reload_reg[regno];
5413 reload_inherited[r] = 1;
5414 reload_inheritance_insn[r]
5415 = reg_reloaded_insn[i];
5416 reload_spill_index[r] = i;
5417 for (k = 0; k < nr; k++)
5418 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5426 /* Here's another way to see if the value is already lying around. */
5428 && reload_in[r] != 0
5429 && ! reload_inherited[r]
5430 && reload_out[r] == 0
5431 && (CONSTANT_P (reload_in[r])
5432 || GET_CODE (reload_in[r]) == PLUS
5433 || GET_CODE (reload_in[r]) == REG
5434 || GET_CODE (reload_in[r]) == MEM)
5435 && (reload_nregs[r] == max_group_size
5436 || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
5439 = find_equiv_reg (reload_in[r], insn, reload_reg_class[r],
5440 -1, NULL_PTR, 0, reload_mode[r]);
5445 if (GET_CODE (equiv) == REG)
5446 regno = REGNO (equiv);
5447 else if (GET_CODE (equiv) == SUBREG)
5449 /* This must be a SUBREG of a hard register.
5450 Make a new REG since this might be used in an
5451 address and not all machines support SUBREGs
5453 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5454 equiv = gen_rtx (REG, reload_mode[r], regno);
5460 /* If we found a spill reg, reject it unless it is free
5461 and of the desired class. */
5463 && ((spill_reg_order[regno] >= 0
5464 && ! reload_reg_free_before_p (regno, reload_opnum[r],
5465 reload_when_needed[r]))
5466 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5470 if (equiv != 0 && TEST_HARD_REG_BIT (reload_reg_used_at_all, regno))
5473 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5476 /* We found a register that contains the value we need.
5477 If this register is the same as an `earlyclobber' operand
5478 of the current insn, just mark it as a place to reload from
5479 since we can't use it as the reload register itself. */
5482 for (i = 0; i < n_earlyclobbers; i++)
5483 if (reg_overlap_mentioned_for_reload_p (equiv,
5484 reload_earlyclobbers[i]))
5486 reload_override_in[r] = equiv;
5491 /* JRV: If the equiv register we have found is
5492 explicitly clobbered in the current insn, mark but
5493 don't use, as above. */
5495 if (equiv != 0 && regno_clobbered_p (regno, insn))
5497 reload_override_in[r] = equiv;
5501 /* If we found an equivalent reg, say no code need be generated
5502 to load it, and use it as our reload reg. */
5503 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5505 int nr = HARD_REGNO_NREGS (regno, reload_mode[r]);
5507 reload_reg_rtx[r] = equiv;
5508 reload_inherited[r] = 1;
5510 /* If any of the hard registers in EQUIV are spill
5511 registers, mark them as in use for this insn. */
5512 for (k = 0; k < nr; k++)
5514 i = spill_reg_order[regno + k];
5517 mark_reload_reg_in_use (regno, reload_opnum[r],
5518 reload_when_needed[r],
5520 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5527 /* If we found a register to use already, or if this is an optional
5528 reload, we are done. */
5529 if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
5532 #if 0 /* No longer needed for correct operation. Might or might not
5533 give better code on the average. Want to experiment? */
5535 /* See if there is a later reload that has a class different from our
5536 class that intersects our class or that requires less register
5537 than our reload. If so, we must allocate a register to this
5538 reload now, since that reload might inherit a previous reload
5539 and take the only available register in our class. Don't do this
5540 for optional reloads since they will force all previous reloads
5541 to be allocated. Also don't do this for reloads that have been
5544 for (i = j + 1; i < n_reloads; i++)
5546 int s = reload_order[i];
5548 if ((reload_in[s] == 0 && reload_out[s] == 0
5549 && ! reload_secondary_p[s])
5550 || reload_optional[s])
5553 if ((reload_reg_class[s] != reload_reg_class[r]
5554 && reg_classes_intersect_p (reload_reg_class[r],
5555 reload_reg_class[s]))
5556 || reload_nregs[s] < reload_nregs[r])
5563 allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance);
5567 /* Now allocate reload registers for anything non-optional that
5568 didn't get one yet. */
5569 for (j = 0; j < n_reloads; j++)
5571 register int r = reload_order[j];
5573 /* Ignore reloads that got marked inoperative. */
5574 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
5577 /* Skip reloads that already have a register allocated or are
5579 if (reload_reg_rtx[r] != 0 || reload_optional[r])
5582 if (! allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance))
5586 /* If that loop got all the way, we have won. */
5591 /* Loop around and try without any inheritance. */
5592 /* First undo everything done by the failed attempt
5593 to allocate with inheritance. */
5594 bcopy ((char *) save_reload_reg_rtx, (char *) reload_reg_rtx,
5595 sizeof reload_reg_rtx);
5596 bcopy ((char *) save_reload_inherited, (char *) reload_inherited,
5597 sizeof reload_inherited);
5598 bcopy ((char *) save_reload_inheritance_insn,
5599 (char *) reload_inheritance_insn,
5600 sizeof reload_inheritance_insn);
5601 bcopy ((char *) save_reload_override_in, (char *) reload_override_in,
5602 sizeof reload_override_in);
5603 bcopy ((char *) save_reload_spill_index, (char *) reload_spill_index,
5604 sizeof reload_spill_index);
5605 COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
5606 COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
5607 COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
5608 save_reload_reg_used_in_op_addr);
5609 COPY_HARD_REG_SET (reload_reg_used_in_op_addr_reload,
5610 save_reload_reg_used_in_op_addr_reload);
5611 COPY_HARD_REG_SET (reload_reg_used_in_insn,
5612 save_reload_reg_used_in_insn);
5613 COPY_HARD_REG_SET (reload_reg_used_in_other_addr,
5614 save_reload_reg_used_in_other_addr);
5616 for (i = 0; i < reload_n_operands; i++)
5618 COPY_HARD_REG_SET (reload_reg_used_in_input[i],
5619 save_reload_reg_used_in_input[i]);
5620 COPY_HARD_REG_SET (reload_reg_used_in_output[i],
5621 save_reload_reg_used_in_output[i]);
5622 COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i],
5623 save_reload_reg_used_in_input_addr[i]);
5624 COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i],
5625 save_reload_reg_used_in_output_addr[i]);
5629 /* If we thought we could inherit a reload, because it seemed that
5630 nothing else wanted the same reload register earlier in the insn,
5631 verify that assumption, now that all reloads have been assigned. */
5633 for (j = 0; j < n_reloads; j++)
5635 register int r = reload_order[j];
5637 if (reload_inherited[r] && reload_reg_rtx[r] != 0
5638 && ! reload_reg_free_before_p (true_regnum (reload_reg_rtx[r]),
5640 reload_when_needed[r]))
5641 reload_inherited[r] = 0;
5643 /* If we found a better place to reload from,
5644 validate it in the same fashion, if it is a reload reg. */
5645 if (reload_override_in[r]
5646 && (GET_CODE (reload_override_in[r]) == REG
5647 || GET_CODE (reload_override_in[r]) == SUBREG))
5649 int regno = true_regnum (reload_override_in[r]);
5650 if (spill_reg_order[regno] >= 0
5651 && ! reload_reg_free_before_p (regno, reload_opnum[r],
5652 reload_when_needed[r]))
5653 reload_override_in[r] = 0;
5657 /* Now that reload_override_in is known valid,
5658 actually override reload_in. */
5659 for (j = 0; j < n_reloads; j++)
5660 if (reload_override_in[j])
5661 reload_in[j] = reload_override_in[j];
5663 /* If this reload won't be done because it has been cancelled or is
5664 optional and not inherited, clear reload_reg_rtx so other
5665 routines (such as subst_reloads) don't get confused. */
5666 for (j = 0; j < n_reloads; j++)
5667 if (reload_reg_rtx[j] != 0
5668 && ((reload_optional[j] && ! reload_inherited[j])
5669 || (reload_in[j] == 0 && reload_out[j] == 0
5670 && ! reload_secondary_p[j])))
5672 int regno = true_regnum (reload_reg_rtx[j]);
5674 if (spill_reg_order[regno] >= 0)
5675 clear_reload_reg_in_use (regno, reload_opnum[j],
5676 reload_when_needed[j], reload_mode[j]);
5677 reload_reg_rtx[j] = 0;
5680 /* Record which pseudos and which spill regs have output reloads. */
5681 for (j = 0; j < n_reloads; j++)
5683 register int r = reload_order[j];
5685 i = reload_spill_index[r];
5687 /* I is nonneg if this reload used one of the spill regs.
5688 If reload_reg_rtx[r] is 0, this is an optional reload
5689 that we opted to ignore. */
5690 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG
5691 && reload_reg_rtx[r] != 0)
5693 register int nregno = REGNO (reload_out[r]);
5696 if (nregno < FIRST_PSEUDO_REGISTER)
5697 nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
5700 reg_has_output_reload[nregno + nr] = 1;
5704 nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
5706 SET_HARD_REG_BIT (reg_is_output_reload, spill_regs[i] + nr);
5709 if (reload_when_needed[r] != RELOAD_OTHER
5710 && reload_when_needed[r] != RELOAD_FOR_OUTPUT
5711 && reload_when_needed[r] != RELOAD_FOR_INSN)
5717 /* If SMALL_REGISTER_CLASSES are defined, we may not have merged two
5718 reloads of the same item for fear that we might not have enough reload
5719 registers. However, normally they will get the same reload register
5720 and hence actually need not be loaded twice.
5722 Here we check for the most common case of this phenomenon: when we have
5723 a number of reloads for the same object, each of which were allocated
5724 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5725 reload, and is not modified in the insn itself. If we find such,
5726 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5727 This will not increase the number of spill registers needed and will
5728 prevent redundant code. */
5730 #ifdef SMALL_REGISTER_CLASSES
5733 merge_assigned_reloads (insn)
5738 /* Scan all the reloads looking for ones that only load values and
5739 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5740 assigned and not modified by INSN. */
5742 for (i = 0; i < n_reloads; i++)
5744 if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER
5745 || reload_out[i] != 0 || reload_reg_rtx[i] == 0
5746 || reg_set_p (reload_reg_rtx[i], insn))
5749 /* Look at all other reloads. Ensure that the only use of this
5750 reload_reg_rtx is in a reload that just loads the same value
5751 as we do. Note that any secondary reloads must be of the identical
5752 class since the values, modes, and result registers are the
5753 same, so we need not do anything with any secondary reloads. */
5755 for (j = 0; j < n_reloads; j++)
5757 if (i == j || reload_reg_rtx[j] == 0
5758 || ! reg_overlap_mentioned_p (reload_reg_rtx[j],
5762 /* If the reload regs aren't exactly the same (e.g, different modes)
5763 or if the values are different, we can't merge anything with this
5766 if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
5767 || reload_out[j] != 0 || reload_in[j] == 0
5768 || ! rtx_equal_p (reload_in[i], reload_in[j]))
5772 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5773 we, in fact, found any matching reloads. */
5777 for (j = 0; j < n_reloads; j++)
5778 if (i != j && reload_reg_rtx[j] != 0
5779 && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j]))
5781 reload_when_needed[i] = RELOAD_OTHER;
5783 transfer_replacements (i, j);
5786 /* If this is now RELOAD_OTHER, look for any reloads that load
5787 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5788 if they were for inputs, RELOAD_OTHER for outputs. Note that
5789 this test is equivalent to looking for reloads for this operand
5792 if (reload_when_needed[i] == RELOAD_OTHER)
5793 for (j = 0; j < n_reloads; j++)
5794 if (reload_in[j] != 0
5795 && reload_when_needed[i] != RELOAD_OTHER
5796 && reg_overlap_mentioned_for_reload_p (reload_in[j],
5798 reload_when_needed[j]
5799 = reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
5800 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER;
5804 #endif /* SMALL_RELOAD_CLASSES */
5806 /* Output insns to reload values in and out of the chosen reload regs. */
5809 emit_reload_insns (insn)
5813 rtx input_reload_insns[MAX_RECOG_OPERANDS];
5814 rtx other_input_address_reload_insns = 0;
5815 rtx other_input_reload_insns = 0;
5816 rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
5817 rtx output_reload_insns[MAX_RECOG_OPERANDS];
5818 rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
5819 rtx operand_reload_insns = 0;
5820 rtx other_operand_reload_insns = 0;
5821 rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
5822 rtx following_insn = NEXT_INSN (insn);
5823 rtx before_insn = insn;
5825 /* Values to be put in spill_reg_store are put here first. */
5826 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
5828 for (j = 0; j < reload_n_operands; j++)
5829 input_reload_insns[j] = input_address_reload_insns[j]
5830 = output_reload_insns[j] = output_address_reload_insns[j]
5831 = other_output_reload_insns[j] = 0;
5833 /* Now output the instructions to copy the data into and out of the
5834 reload registers. Do these in the order that the reloads were reported,
5835 since reloads of base and index registers precede reloads of operands
5836 and the operands may need the base and index registers reloaded. */
5838 for (j = 0; j < n_reloads; j++)
5841 rtx oldequiv_reg = 0;
5842 rtx this_reload_insn = 0;
5844 if (reload_spill_index[j] >= 0)
5845 new_spill_reg_store[reload_spill_index[j]] = 0;
5848 if (old != 0 && ! reload_inherited[j]
5849 && ! rtx_equal_p (reload_reg_rtx[j], old)
5850 && reload_reg_rtx[j] != 0)
5852 register rtx reloadreg = reload_reg_rtx[j];
5854 enum machine_mode mode;
5857 /* Determine the mode to reload in.
5858 This is very tricky because we have three to choose from.
5859 There is the mode the insn operand wants (reload_inmode[J]).
5860 There is the mode of the reload register RELOADREG.
5861 There is the intrinsic mode of the operand, which we could find
5862 by stripping some SUBREGs.
5863 It turns out that RELOADREG's mode is irrelevant:
5864 we can change that arbitrarily.
5866 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
5867 then the reload reg may not support QImode moves, so use SImode.
5868 If foo is in memory due to spilling a pseudo reg, this is safe,
5869 because the QImode value is in the least significant part of a
5870 slot big enough for a SImode. If foo is some other sort of
5871 memory reference, then it is impossible to reload this case,
5872 so previous passes had better make sure this never happens.
5874 Then consider a one-word union which has SImode and one of its
5875 members is a float, being fetched as (SUBREG:SF union:SI).
5876 We must fetch that as SFmode because we could be loading into
5877 a float-only register. In this case OLD's mode is correct.
5879 Consider an immediate integer: it has VOIDmode. Here we need
5880 to get a mode from something else.
5882 In some cases, there is a fourth mode, the operand's
5883 containing mode. If the insn specifies a containing mode for
5884 this operand, it overrides all others.
5886 I am not sure whether the algorithm here is always right,
5887 but it does the right things in those cases. */
5889 mode = GET_MODE (old);
5890 if (mode == VOIDmode)
5891 mode = reload_inmode[j];
5893 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5894 /* If we need a secondary register for this operation, see if
5895 the value is already in a register in that class. Don't
5896 do this if the secondary register will be used as a scratch
5899 if (reload_secondary_in_reload[j] >= 0
5900 && reload_secondary_in_icode[j] == CODE_FOR_nothing
5903 = find_equiv_reg (old, insn,
5904 reload_reg_class[reload_secondary_in_reload[j]],
5905 -1, NULL_PTR, 0, mode);
5908 /* If reloading from memory, see if there is a register
5909 that already holds the same value. If so, reload from there.
5910 We can pass 0 as the reload_reg_p argument because
5911 any other reload has either already been emitted,
5912 in which case find_equiv_reg will see the reload-insn,
5913 or has yet to be emitted, in which case it doesn't matter
5914 because we will use this equiv reg right away. */
5916 if (oldequiv == 0 && optimize
5917 && (GET_CODE (old) == MEM
5918 || (GET_CODE (old) == REG
5919 && REGNO (old) >= FIRST_PSEUDO_REGISTER
5920 && reg_renumber[REGNO (old)] < 0)))
5921 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
5922 -1, NULL_PTR, 0, mode);
5926 int regno = true_regnum (oldequiv);
5928 /* If OLDEQUIV is a spill register, don't use it for this
5929 if any other reload needs it at an earlier stage of this insn
5930 or at this stage. */
5931 if (spill_reg_order[regno] >= 0
5932 && (! reload_reg_free_p (regno, reload_opnum[j],
5933 reload_when_needed[j])
5934 || ! reload_reg_free_before_p (regno, reload_opnum[j],
5935 reload_when_needed[j])))
5938 /* If OLDEQUIV is not a spill register,
5939 don't use it if any other reload wants it. */
5940 if (spill_reg_order[regno] < 0)
5943 for (k = 0; k < n_reloads; k++)
5944 if (reload_reg_rtx[k] != 0 && k != j
5945 && reg_overlap_mentioned_for_reload_p (reload_reg_rtx[k],
5953 /* If it is no cheaper to copy from OLDEQUIV into the
5954 reload register than it would be to move from memory,
5955 don't use it. Likewise, if we need a secondary register
5959 && ((REGNO_REG_CLASS (regno) != reload_reg_class[j]
5960 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
5961 reload_reg_class[j])
5962 >= MEMORY_MOVE_COST (mode)))
5963 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5964 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
5968 #ifdef SECONDARY_MEMORY_NEEDED
5969 || SECONDARY_MEMORY_NEEDED (reload_reg_class[j],
5970 REGNO_REG_CLASS (regno),
5979 else if (GET_CODE (oldequiv) == REG)
5980 oldequiv_reg = oldequiv;
5981 else if (GET_CODE (oldequiv) == SUBREG)
5982 oldequiv_reg = SUBREG_REG (oldequiv);
5984 /* If we are reloading from a register that was recently stored in
5985 with an output-reload, see if we can prove there was
5986 actually no need to store the old value in it. */
5988 if (optimize && GET_CODE (oldequiv) == REG
5989 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
5990 && spill_reg_order[REGNO (oldequiv)] >= 0
5991 && spill_reg_store[spill_reg_order[REGNO (oldequiv)]] != 0
5992 && find_reg_note (insn, REG_DEAD, reload_in[j])
5993 /* This is unsafe if operand occurs more than once in current
5994 insn. Perhaps some occurrences weren't reloaded. */
5995 && count_occurrences (PATTERN (insn), reload_in[j]) == 1)
5996 delete_output_reload
5997 (insn, j, spill_reg_store[spill_reg_order[REGNO (oldequiv)]]);
5999 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6000 then load RELOADREG from OLDEQUIV. Note that we cannot use
6001 gen_lowpart_common since it can do the wrong thing when
6002 RELOADREG has a multi-word mode. Note that RELOADREG
6003 must always be a REG here. */
6005 if (GET_MODE (reloadreg) != mode)
6006 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
6007 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6008 oldequiv = SUBREG_REG (oldequiv);
6009 if (GET_MODE (oldequiv) != VOIDmode
6010 && mode != GET_MODE (oldequiv))
6011 oldequiv = gen_rtx (SUBREG, mode, oldequiv, 0);
6013 /* Switch to the right place to emit the reload insns. */
6014 switch (reload_when_needed[j])
6017 where = &other_input_reload_insns;
6019 case RELOAD_FOR_INPUT:
6020 where = &input_reload_insns[reload_opnum[j]];
6022 case RELOAD_FOR_INPUT_ADDRESS:
6023 where = &input_address_reload_insns[reload_opnum[j]];
6025 case RELOAD_FOR_OUTPUT_ADDRESS:
6026 where = &output_address_reload_insns[reload_opnum[j]];
6028 case RELOAD_FOR_OPERAND_ADDRESS:
6029 where = &operand_reload_insns;
6031 case RELOAD_FOR_OPADDR_ADDR:
6032 where = &other_operand_reload_insns;
6034 case RELOAD_FOR_OTHER_ADDRESS:
6035 where = &other_input_address_reload_insns;
6041 push_to_sequence (*where);
6044 /* Auto-increment addresses must be reloaded in a special way. */
6045 if (GET_CODE (oldequiv) == POST_INC
6046 || GET_CODE (oldequiv) == POST_DEC
6047 || GET_CODE (oldequiv) == PRE_INC
6048 || GET_CODE (oldequiv) == PRE_DEC)
6050 /* We are not going to bother supporting the case where a
6051 incremented register can't be copied directly from
6052 OLDEQUIV since this seems highly unlikely. */
6053 if (reload_secondary_in_reload[j] >= 0)
6055 /* Prevent normal processing of this reload. */
6057 /* Output a special code sequence for this case. */
6058 inc_for_reload (reloadreg, oldequiv, reload_inc[j]);
6061 /* If we are reloading a pseudo-register that was set by the previous
6062 insn, see if we can get rid of that pseudo-register entirely
6063 by redirecting the previous insn into our reload register. */
6065 else if (optimize && GET_CODE (old) == REG
6066 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6067 && dead_or_set_p (insn, old)
6068 /* This is unsafe if some other reload
6069 uses the same reg first. */
6070 && reload_reg_free_before_p (REGNO (reloadreg),
6072 reload_when_needed[j]))
6074 rtx temp = PREV_INSN (insn);
6075 while (temp && GET_CODE (temp) == NOTE)
6076 temp = PREV_INSN (temp);
6078 && GET_CODE (temp) == INSN
6079 && GET_CODE (PATTERN (temp)) == SET
6080 && SET_DEST (PATTERN (temp)) == old
6081 /* Make sure we can access insn_operand_constraint. */
6082 && asm_noperands (PATTERN (temp)) < 0
6083 /* This is unsafe if prev insn rejects our reload reg. */
6084 && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
6086 /* This is unsafe if operand occurs more than once in current
6087 insn. Perhaps some occurrences aren't reloaded. */
6088 && count_occurrences (PATTERN (insn), old) == 1
6089 /* Don't risk splitting a matching pair of operands. */
6090 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6092 /* Store into the reload register instead of the pseudo. */
6093 SET_DEST (PATTERN (temp)) = reloadreg;
6094 /* If these are the only uses of the pseudo reg,
6095 pretend for GDB it lives in the reload reg we used. */
6096 if (reg_n_deaths[REGNO (old)] == 1
6097 && reg_n_sets[REGNO (old)] == 1)
6099 reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
6100 alter_reg (REGNO (old), -1);
6106 /* We can't do that, so output an insn to load RELOADREG. */
6110 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6111 rtx second_reload_reg = 0;
6112 enum insn_code icode;
6114 /* If we have a secondary reload, pick up the secondary register
6115 and icode, if any. If OLDEQUIV and OLD are different or
6116 if this is an in-out reload, recompute whether or not we
6117 still need a secondary register and what the icode should
6118 be. If we still need a secondary register and the class or
6119 icode is different, go back to reloading from OLD if using
6120 OLDEQUIV means that we got the wrong type of register. We
6121 cannot have different class or icode due to an in-out reload
6122 because we don't make such reloads when both the input and
6123 output need secondary reload registers. */
6125 if (reload_secondary_in_reload[j] >= 0)
6127 int secondary_reload = reload_secondary_in_reload[j];
6128 rtx real_oldequiv = oldequiv;
6131 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6132 and similarly for OLD.
6133 See comments in get_secondary_reload in reload.c. */
6134 if (GET_CODE (oldequiv) == REG
6135 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6136 && reg_equiv_mem[REGNO (oldequiv)] != 0)
6137 real_oldequiv = reg_equiv_mem[REGNO (oldequiv)];
6139 if (GET_CODE (old) == REG
6140 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6141 && reg_equiv_mem[REGNO (old)] != 0)
6142 real_old = reg_equiv_mem[REGNO (old)];
6144 second_reload_reg = reload_reg_rtx[secondary_reload];
6145 icode = reload_secondary_in_icode[j];
6147 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6148 || (reload_in[j] != 0 && reload_out[j] != 0))
6150 enum reg_class new_class
6151 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6152 mode, real_oldequiv);
6154 if (new_class == NO_REGS)
6155 second_reload_reg = 0;
6158 enum insn_code new_icode;
6159 enum machine_mode new_mode;
6161 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6162 REGNO (second_reload_reg)))
6163 oldequiv = old, real_oldequiv = real_old;
6166 new_icode = reload_in_optab[(int) mode];
6167 if (new_icode != CODE_FOR_nothing
6168 && ((insn_operand_predicate[(int) new_icode][0]
6169 && ! ((*insn_operand_predicate[(int) new_icode][0])
6171 || (insn_operand_predicate[(int) new_icode][1]
6172 && ! ((*insn_operand_predicate[(int) new_icode][1])
6173 (real_oldequiv, mode)))))
6174 new_icode = CODE_FOR_nothing;
6176 if (new_icode == CODE_FOR_nothing)
6179 new_mode = insn_operand_mode[(int) new_icode][2];
6181 if (GET_MODE (second_reload_reg) != new_mode)
6183 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6185 oldequiv = old, real_oldequiv = real_old;
6188 = gen_rtx (REG, new_mode,
6189 REGNO (second_reload_reg));
6195 /* If we still need a secondary reload register, check
6196 to see if it is being used as a scratch or intermediate
6197 register and generate code appropriately. If we need
6198 a scratch register, use REAL_OLDEQUIV since the form of
6199 the insn may depend on the actual address if it is
6202 if (second_reload_reg)
6204 if (icode != CODE_FOR_nothing)
6206 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6207 second_reload_reg));
6212 /* See if we need a scratch register to load the
6213 intermediate register (a tertiary reload). */
6214 enum insn_code tertiary_icode
6215 = reload_secondary_in_icode[secondary_reload];
6217 if (tertiary_icode != CODE_FOR_nothing)
6219 rtx third_reload_reg
6220 = reload_reg_rtx[reload_secondary_in_reload[secondary_reload]];
6222 emit_insn ((GEN_FCN (tertiary_icode)
6223 (second_reload_reg, real_oldequiv,
6224 third_reload_reg)));
6227 gen_reload (second_reload_reg, oldequiv,
6229 reload_when_needed[j]);
6231 oldequiv = second_reload_reg;
6237 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6238 gen_reload (reloadreg, oldequiv, reload_opnum[j],
6239 reload_when_needed[j]);
6241 #if defined(SECONDARY_INPUT_RELOAD_CLASS) && defined(PRESERVE_DEATH_INFO_REGNO_P)
6242 /* We may have to make a REG_DEAD note for the secondary reload
6243 register in the insns we just made. Find the last insn that
6244 mentioned the register. */
6245 if (! special && second_reload_reg
6246 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reload_reg)))
6250 for (prev = get_last_insn (); prev;
6251 prev = PREV_INSN (prev))
6252 if (GET_RTX_CLASS (GET_CODE (prev) == 'i')
6253 && reg_overlap_mentioned_for_reload_p (second_reload_reg,
6256 REG_NOTES (prev) = gen_rtx (EXPR_LIST, REG_DEAD,
6265 this_reload_insn = get_last_insn ();
6266 /* End this sequence. */
6267 *where = get_insns ();
6271 /* Add a note saying the input reload reg
6272 dies in this insn, if anyone cares. */
6273 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6275 && reload_reg_rtx[j] != old
6276 && reload_reg_rtx[j] != 0
6277 && reload_out[j] == 0
6278 && ! reload_inherited[j]
6279 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j])))
6281 register rtx reloadreg = reload_reg_rtx[j];
6284 /* We can't abort here because we need to support this for sched.c.
6285 It's not terrible to miss a REG_DEAD note, but we should try
6286 to figure out how to do this correctly. */
6287 /* The code below is incorrect for address-only reloads. */
6288 if (reload_when_needed[j] != RELOAD_OTHER
6289 && reload_when_needed[j] != RELOAD_FOR_INPUT)
6293 /* Add a death note to this insn, for an input reload. */
6295 if ((reload_when_needed[j] == RELOAD_OTHER
6296 || reload_when_needed[j] == RELOAD_FOR_INPUT)
6297 && ! dead_or_set_p (insn, reloadreg))
6299 = gen_rtx (EXPR_LIST, REG_DEAD,
6300 reloadreg, REG_NOTES (insn));
6303 /* When we inherit a reload, the last marked death of the reload reg
6304 may no longer really be a death. */
6305 if (reload_reg_rtx[j] != 0
6306 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j]))
6307 && reload_inherited[j])
6309 /* Handle inheriting an output reload.
6310 Remove the death note from the output reload insn. */
6311 if (reload_spill_index[j] >= 0
6312 && GET_CODE (reload_in[j]) == REG
6313 && spill_reg_store[reload_spill_index[j]] != 0
6314 && find_regno_note (spill_reg_store[reload_spill_index[j]],
6315 REG_DEAD, REGNO (reload_reg_rtx[j])))
6316 remove_death (REGNO (reload_reg_rtx[j]),
6317 spill_reg_store[reload_spill_index[j]]);
6318 /* Likewise for input reloads that were inherited. */
6319 else if (reload_spill_index[j] >= 0
6320 && GET_CODE (reload_in[j]) == REG
6321 && spill_reg_store[reload_spill_index[j]] == 0
6322 && reload_inheritance_insn[j] != 0
6323 && find_regno_note (reload_inheritance_insn[j], REG_DEAD,
6324 REGNO (reload_reg_rtx[j])))
6325 remove_death (REGNO (reload_reg_rtx[j]),
6326 reload_inheritance_insn[j]);
6331 /* We got this register from find_equiv_reg.
6332 Search back for its last death note and get rid of it.
6333 But don't search back too far.
6334 Don't go past a place where this reg is set,
6335 since a death note before that remains valid. */
6336 for (prev = PREV_INSN (insn);
6337 prev && GET_CODE (prev) != CODE_LABEL;
6338 prev = PREV_INSN (prev))
6339 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
6340 && dead_or_set_p (prev, reload_reg_rtx[j]))
6342 if (find_regno_note (prev, REG_DEAD,
6343 REGNO (reload_reg_rtx[j])))
6344 remove_death (REGNO (reload_reg_rtx[j]), prev);
6350 /* We might have used find_equiv_reg above to choose an alternate
6351 place from which to reload. If so, and it died, we need to remove
6352 that death and move it to one of the insns we just made. */
6354 if (oldequiv_reg != 0
6355 && PRESERVE_DEATH_INFO_REGNO_P (true_regnum (oldequiv_reg)))
6359 for (prev = PREV_INSN (insn); prev && GET_CODE (prev) != CODE_LABEL;
6360 prev = PREV_INSN (prev))
6361 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
6362 && dead_or_set_p (prev, oldequiv_reg))
6364 if (find_regno_note (prev, REG_DEAD, REGNO (oldequiv_reg)))
6366 for (prev1 = this_reload_insn;
6367 prev1; prev1 = PREV_INSN (prev1))
6368 if (GET_RTX_CLASS (GET_CODE (prev1) == 'i')
6369 && reg_overlap_mentioned_for_reload_p (oldequiv_reg,
6372 REG_NOTES (prev1) = gen_rtx (EXPR_LIST, REG_DEAD,
6377 remove_death (REGNO (oldequiv_reg), prev);
6384 /* If we are reloading a register that was recently stored in with an
6385 output-reload, see if we can prove there was
6386 actually no need to store the old value in it. */
6388 if (optimize && reload_inherited[j] && reload_spill_index[j] >= 0
6389 && reload_in[j] != 0
6390 && GET_CODE (reload_in[j]) == REG
6392 /* There doesn't seem to be any reason to restrict this to pseudos
6393 and doing so loses in the case where we are copying from a
6394 register of the wrong class. */
6395 && REGNO (reload_in[j]) >= FIRST_PSEUDO_REGISTER
6397 && spill_reg_store[reload_spill_index[j]] != 0
6398 /* This is unsafe if some other reload uses the same reg first. */
6399 && reload_reg_free_before_p (spill_regs[reload_spill_index[j]],
6400 reload_opnum[j], reload_when_needed[j])
6401 && dead_or_set_p (insn, reload_in[j])
6402 /* This is unsafe if operand occurs more than once in current
6403 insn. Perhaps some occurrences weren't reloaded. */
6404 && count_occurrences (PATTERN (insn), reload_in[j]) == 1)
6405 delete_output_reload (insn, j,
6406 spill_reg_store[reload_spill_index[j]]);
6408 /* Input-reloading is done. Now do output-reloading,
6409 storing the value from the reload-register after the main insn
6410 if reload_out[j] is nonzero.
6412 ??? At some point we need to support handling output reloads of
6413 JUMP_INSNs or insns that set cc0. */
6414 old = reload_out[j];
6416 && reload_reg_rtx[j] != old
6417 && reload_reg_rtx[j] != 0)
6419 register rtx reloadreg = reload_reg_rtx[j];
6420 register rtx second_reloadreg = 0;
6422 enum machine_mode mode;
6425 /* An output operand that dies right away does need a reload,
6426 but need not be copied from it. Show the new location in the
6428 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6429 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6431 XEXP (note, 0) = reload_reg_rtx[j];
6434 /* Likewise for a SUBREG of an operand that dies. */
6435 else if (GET_CODE (old) == SUBREG
6436 && GET_CODE (SUBREG_REG (old)) == REG
6437 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6440 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6444 else if (GET_CODE (old) == SCRATCH)
6445 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6446 but we don't want to make an output reload. */
6450 /* Strip off of OLD any size-increasing SUBREGs such as
6451 (SUBREG:SI foo:QI 0). */
6453 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
6454 && (GET_MODE_SIZE (GET_MODE (old))
6455 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
6456 old = SUBREG_REG (old);
6459 /* If is a JUMP_INSN, we can't support output reloads yet. */
6460 if (GET_CODE (insn) == JUMP_INSN)
6463 if (reload_when_needed[j] == RELOAD_OTHER)
6466 push_to_sequence (output_reload_insns[reload_opnum[j]]);
6468 /* Determine the mode to reload in.
6469 See comments above (for input reloading). */
6471 mode = GET_MODE (old);
6472 if (mode == VOIDmode)
6474 /* VOIDmode should never happen for an output. */
6475 if (asm_noperands (PATTERN (insn)) < 0)
6476 /* It's the compiler's fault. */
6477 fatal_insn ("VOIDmode on an output", insn);
6478 error_for_asm (insn, "output operand is constant in `asm'");
6479 /* Prevent crash--use something we know is valid. */
6481 old = gen_rtx (REG, mode, REGNO (reloadreg));
6484 if (GET_MODE (reloadreg) != mode)
6485 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
6487 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6489 /* If we need two reload regs, set RELOADREG to the intermediate
6490 one, since it will be stored into OLD. We might need a secondary
6491 register only for an input reload, so check again here. */
6493 if (reload_secondary_out_reload[j] >= 0)
6497 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6498 && reg_equiv_mem[REGNO (old)] != 0)
6499 real_old = reg_equiv_mem[REGNO (old)];
6501 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
6505 second_reloadreg = reloadreg;
6506 reloadreg = reload_reg_rtx[reload_secondary_out_reload[j]];
6508 /* See if RELOADREG is to be used as a scratch register
6509 or as an intermediate register. */
6510 if (reload_secondary_out_icode[j] != CODE_FOR_nothing)
6512 emit_insn ((GEN_FCN (reload_secondary_out_icode[j])
6513 (real_old, second_reloadreg, reloadreg)));
6518 /* See if we need both a scratch and intermediate reload
6521 int secondary_reload = reload_secondary_out_reload[j];
6522 enum insn_code tertiary_icode
6523 = reload_secondary_out_icode[secondary_reload];
6525 if (GET_MODE (reloadreg) != mode)
6526 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
6528 if (tertiary_icode != CODE_FOR_nothing)
6531 = reload_reg_rtx[reload_secondary_out_reload[secondary_reload]];
6534 /* Copy primary reload reg to secondary reload reg.
6535 (Note that these have been swapped above, then
6536 secondary reload reg to OLD using our insn. */
6538 /* If REAL_OLD is a paradoxical SUBREG, remove it
6539 and try to put the opposite SUBREG on
6541 if (GET_CODE (real_old) == SUBREG
6542 && (GET_MODE_SIZE (GET_MODE (real_old))
6543 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6544 && 0 != (tem = gen_lowpart_common
6545 (GET_MODE (SUBREG_REG (real_old)),
6547 real_old = SUBREG_REG (real_old), reloadreg = tem;
6549 gen_reload (reloadreg, second_reloadreg,
6550 reload_opnum[j], reload_when_needed[j]);
6551 emit_insn ((GEN_FCN (tertiary_icode)
6552 (real_old, reloadreg, third_reloadreg)));
6557 /* Copy between the reload regs here and then to
6560 gen_reload (reloadreg, second_reloadreg,
6561 reload_opnum[j], reload_when_needed[j]);
6567 /* Output the last reload insn. */
6569 gen_reload (old, reloadreg, reload_opnum[j],
6570 reload_when_needed[j]);
6572 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6573 /* If final will look at death notes for this reg,
6574 put one on the last output-reload insn to use it. Similarly
6575 for any secondary register. */
6576 if (PRESERVE_DEATH_INFO_REGNO_P (REGNO (reloadreg)))
6577 for (p = get_last_insn (); p; p = PREV_INSN (p))
6578 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
6579 && reg_overlap_mentioned_for_reload_p (reloadreg,
6581 REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
6582 reloadreg, REG_NOTES (p));
6584 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6585 if (! special && second_reloadreg
6586 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reloadreg)))
6587 for (p = get_last_insn (); p; p = PREV_INSN (p))
6588 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
6589 && reg_overlap_mentioned_for_reload_p (second_reloadreg,
6591 REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
6592 second_reloadreg, REG_NOTES (p));
6595 /* Look at all insns we emitted, just to be safe. */
6596 for (p = get_insns (); p; p = NEXT_INSN (p))
6597 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
6599 /* If this output reload doesn't come from a spill reg,
6600 clear any memory of reloaded copies of the pseudo reg.
6601 If this output reload comes from a spill reg,
6602 reg_has_output_reload will make this do nothing. */
6603 note_stores (PATTERN (p), forget_old_reloads_1);
6605 if (reg_mentioned_p (reload_reg_rtx[j], PATTERN (p))
6606 && reload_spill_index[j] >= 0)
6607 new_spill_reg_store[reload_spill_index[j]] = p;
6610 if (reload_when_needed[j] == RELOAD_OTHER)
6612 emit_insns (other_output_reload_insns[reload_opnum[j]]);
6613 other_output_reload_insns[reload_opnum[j]] = get_insns ();
6616 output_reload_insns[reload_opnum[j]] = get_insns ();
6622 /* Now write all the insns we made for reloads in the order expected by
6623 the allocation functions. Prior to the insn being reloaded, we write
6624 the following reloads:
6626 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6628 RELOAD_OTHER reloads.
6630 For each operand, any RELOAD_FOR_INPUT_ADDRESS reloads followed by
6631 the RELOAD_FOR_INPUT reload for the operand.
6633 RELOAD_FOR_OPADDR_ADDRS reloads.
6635 RELOAD_FOR_OPERAND_ADDRESS reloads.
6637 After the insn being reloaded, we write the following:
6639 For each operand, any RELOAD_FOR_OUTPUT_ADDRESS reload followed by
6640 the RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6641 reloads for the operand. The RELOAD_OTHER output reloads are output
6642 in descending order by reload number. */
6644 emit_insns_before (other_input_address_reload_insns, before_insn);
6645 emit_insns_before (other_input_reload_insns, before_insn);
6647 for (j = 0; j < reload_n_operands; j++)
6649 emit_insns_before (input_address_reload_insns[j], before_insn);
6650 emit_insns_before (input_reload_insns[j], before_insn);
6653 emit_insns_before (other_operand_reload_insns, before_insn);
6654 emit_insns_before (operand_reload_insns, before_insn);
6656 for (j = 0; j < reload_n_operands; j++)
6658 emit_insns_before (output_address_reload_insns[j], following_insn);
6659 emit_insns_before (output_reload_insns[j], following_insn);
6660 emit_insns_before (other_output_reload_insns[j], following_insn);
6663 /* Move death notes from INSN
6664 to output-operand-address and output reload insns. */
6665 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6668 /* Loop over those insns, last ones first. */
6669 for (insn1 = PREV_INSN (following_insn); insn1 != insn;
6670 insn1 = PREV_INSN (insn1))
6671 if (GET_CODE (insn1) == INSN && GET_CODE (PATTERN (insn1)) == SET)
6673 rtx source = SET_SRC (PATTERN (insn1));
6674 rtx dest = SET_DEST (PATTERN (insn1));
6676 /* The note we will examine next. */
6677 rtx reg_notes = REG_NOTES (insn);
6678 /* The place that pointed to this note. */
6679 rtx *prev_reg_note = ®_NOTES (insn);
6681 /* If the note is for something used in the source of this
6682 reload insn, or in the output address, move the note. */
6685 rtx next_reg_notes = XEXP (reg_notes, 1);
6686 if (REG_NOTE_KIND (reg_notes) == REG_DEAD
6687 && GET_CODE (XEXP (reg_notes, 0)) == REG
6688 && ((GET_CODE (dest) != REG
6689 && reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
6691 || reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
6694 *prev_reg_note = next_reg_notes;
6695 XEXP (reg_notes, 1) = REG_NOTES (insn1);
6696 REG_NOTES (insn1) = reg_notes;
6699 prev_reg_note = &XEXP (reg_notes, 1);
6701 reg_notes = next_reg_notes;
6707 /* For all the spill regs newly reloaded in this instruction,
6708 record what they were reloaded from, so subsequent instructions
6709 can inherit the reloads.
6711 Update spill_reg_store for the reloads of this insn.
6712 Copy the elements that were updated in the loop above. */
6714 for (j = 0; j < n_reloads; j++)
6716 register int r = reload_order[j];
6717 register int i = reload_spill_index[r];
6719 /* I is nonneg if this reload used one of the spill regs.
6720 If reload_reg_rtx[r] is 0, this is an optional reload
6721 that we opted to ignore. */
6723 if (i >= 0 && reload_reg_rtx[r] != 0)
6726 = HARD_REGNO_NREGS (spill_regs[i], GET_MODE (reload_reg_rtx[r]));
6728 int part_reaches_end = 0;
6729 int all_reaches_end = 1;
6731 /* For a multi register reload, we need to check if all or part
6732 of the value lives to the end. */
6733 for (k = 0; k < nr; k++)
6735 if (reload_reg_reaches_end_p (spill_regs[i] + k, reload_opnum[r],
6736 reload_when_needed[r]))
6737 part_reaches_end = 1;
6739 all_reaches_end = 0;
6742 /* Ignore reloads that don't reach the end of the insn in
6744 if (all_reaches_end)
6746 /* First, clear out memory of what used to be in this spill reg.
6747 If consecutive registers are used, clear them all. */
6749 for (k = 0; k < nr; k++)
6751 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] = -1;
6752 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = 0;
6755 /* Maybe the spill reg contains a copy of reload_out. */
6756 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
6758 register int nregno = REGNO (reload_out[r]);
6759 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6760 : HARD_REGNO_NREGS (nregno,
6761 GET_MODE (reload_reg_rtx[r])));
6763 spill_reg_store[i] = new_spill_reg_store[i];
6764 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
6766 /* If NREGNO is a hard register, it may occupy more than
6767 one register. If it does, say what is in the
6768 rest of the registers assuming that both registers
6769 agree on how many words the object takes. If not,
6770 invalidate the subsequent registers. */
6772 if (nregno < FIRST_PSEUDO_REGISTER)
6773 for (k = 1; k < nnr; k++)
6774 reg_last_reload_reg[nregno + k]
6777 reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
6778 REGNO (reload_reg_rtx[r]) + k)
6781 /* Now do the inverse operation. */
6782 for (k = 0; k < nr; k++)
6784 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
6785 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
6788 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = insn;
6792 /* Maybe the spill reg contains a copy of reload_in. Only do
6793 something if there will not be an output reload for
6794 the register being reloaded. */
6795 else if (reload_out[r] == 0
6796 && reload_in[r] != 0
6797 && ((GET_CODE (reload_in[r]) == REG
6798 && ! reg_has_output_reload[REGNO (reload_in[r])])
6799 || (GET_CODE (reload_in_reg[r]) == REG
6800 && ! reg_has_output_reload[REGNO (reload_in_reg[r])])))
6802 register int nregno;
6805 if (GET_CODE (reload_in[r]) == REG)
6806 nregno = REGNO (reload_in[r]);
6808 nregno = REGNO (reload_in_reg[r]);
6810 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6811 : HARD_REGNO_NREGS (nregno,
6812 GET_MODE (reload_reg_rtx[r])));
6814 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
6816 if (nregno < FIRST_PSEUDO_REGISTER)
6817 for (k = 1; k < nnr; k++)
6818 reg_last_reload_reg[nregno + k]
6821 reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
6822 REGNO (reload_reg_rtx[r]) + k)
6825 /* Unless we inherited this reload, show we haven't
6826 recently done a store. */
6827 if (! reload_inherited[r])
6828 spill_reg_store[i] = 0;
6830 for (k = 0; k < nr; k++)
6832 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
6833 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
6836 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]]
6842 /* However, if part of the reload reaches the end, then we must
6843 invalidate the old info for the part that survives to the end. */
6844 else if (part_reaches_end)
6846 for (k = 0; k < nr; k++)
6847 if (reload_reg_reaches_end_p (spill_regs[i] + k,
6849 reload_when_needed[r]))
6851 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] = -1;
6852 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = 0;
6857 /* The following if-statement was #if 0'd in 1.34 (or before...).
6858 It's reenabled in 1.35 because supposedly nothing else
6859 deals with this problem. */
6861 /* If a register gets output-reloaded from a non-spill register,
6862 that invalidates any previous reloaded copy of it.
6863 But forget_old_reloads_1 won't get to see it, because
6864 it thinks only about the original insn. So invalidate it here. */
6865 if (i < 0 && reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
6867 register int nregno = REGNO (reload_out[r]);
6868 if (nregno >= FIRST_PSEUDO_REGISTER)
6869 reg_last_reload_reg[nregno] = 0;
6872 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (reload_out[r]));
6874 while (num_regs-- > 0)
6875 reg_last_reload_reg[nregno + num_regs] = 0;
6881 /* Emit code to perform a reload from IN (which may be a reload register) to
6882 OUT (which may also be a reload register). IN or OUT is from operand
6883 OPNUM with reload type TYPE.
6885 Returns first insn emitted. */
6888 gen_reload (out, in, opnum, type)
6892 enum reload_type type;
6894 rtx last = get_last_insn ();
6897 /* If IN is a paradoxical SUBREG, remove it and try to put the
6898 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
6899 if (GET_CODE (in) == SUBREG
6900 && (GET_MODE_SIZE (GET_MODE (in))
6901 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
6902 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
6903 in = SUBREG_REG (in), out = tem;
6904 else if (GET_CODE (out) == SUBREG
6905 && (GET_MODE_SIZE (GET_MODE (out))
6906 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
6907 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
6908 out = SUBREG_REG (out), in = tem;
6910 /* How to do this reload can get quite tricky. Normally, we are being
6911 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
6912 register that didn't get a hard register. In that case we can just
6913 call emit_move_insn.
6915 We can also be asked to reload a PLUS that adds a register or a MEM to
6916 another register, constant or MEM. This can occur during frame pointer
6917 elimination and while reloading addresses. This case is handled by
6918 trying to emit a single insn to perform the add. If it is not valid,
6919 we use a two insn sequence.
6921 Finally, we could be called to handle an 'o' constraint by putting
6922 an address into a register. In that case, we first try to do this
6923 with a named pattern of "reload_load_address". If no such pattern
6924 exists, we just emit a SET insn and hope for the best (it will normally
6925 be valid on machines that use 'o').
6927 This entire process is made complex because reload will never
6928 process the insns we generate here and so we must ensure that
6929 they will fit their constraints and also by the fact that parts of
6930 IN might be being reloaded separately and replaced with spill registers.
6931 Because of this, we are, in some sense, just guessing the right approach
6932 here. The one listed above seems to work.
6934 ??? At some point, this whole thing needs to be rethought. */
6936 if (GET_CODE (in) == PLUS
6937 && (GET_CODE (XEXP (in, 0)) == REG
6938 || GET_CODE (XEXP (in, 0)) == SUBREG
6939 || GET_CODE (XEXP (in, 0)) == MEM)
6940 && (GET_CODE (XEXP (in, 1)) == REG
6941 || GET_CODE (XEXP (in, 1)) == SUBREG
6942 || CONSTANT_P (XEXP (in, 1))
6943 || GET_CODE (XEXP (in, 1)) == MEM))
6945 /* We need to compute the sum of a register or a MEM and another
6946 register, constant, or MEM, and put it into the reload
6947 register. The best possible way of doing this is if the machine
6948 has a three-operand ADD insn that accepts the required operands.
6950 The simplest approach is to try to generate such an insn and see if it
6951 is recognized and matches its constraints. If so, it can be used.
6953 It might be better not to actually emit the insn unless it is valid,
6954 but we need to pass the insn as an operand to `recog' and
6955 `insn_extract' and it is simpler to emit and then delete the insn if
6956 not valid than to dummy things up. */
6958 rtx op0, op1, tem, insn;
6961 op0 = find_replacement (&XEXP (in, 0));
6962 op1 = find_replacement (&XEXP (in, 1));
6964 /* Since constraint checking is strict, commutativity won't be
6965 checked, so we need to do that here to avoid spurious failure
6966 if the add instruction is two-address and the second operand
6967 of the add is the same as the reload reg, which is frequently
6968 the case. If the insn would be A = B + A, rearrange it so
6969 it will be A = A + B as constrain_operands expects. */
6971 if (GET_CODE (XEXP (in, 1)) == REG
6972 && REGNO (out) == REGNO (XEXP (in, 1)))
6973 tem = op0, op0 = op1, op1 = tem;
6975 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
6976 in = gen_rtx (PLUS, GET_MODE (in), op0, op1);
6978 insn = emit_insn (gen_rtx (SET, VOIDmode, out, in));
6979 code = recog_memoized (insn);
6983 insn_extract (insn);
6984 /* We want constrain operands to treat this insn strictly in
6985 its validity determination, i.e., the way it would after reload
6987 if (constrain_operands (code, 1))
6991 delete_insns_since (last);
6993 /* If that failed, we must use a conservative two-insn sequence.
6994 use move to copy constant, MEM, or pseudo register to the reload
6995 register since "move" will be able to handle an arbitrary operand,
6996 unlike add which can't, in general. Then add the registers.
6998 If there is another way to do this for a specific machine, a
6999 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7002 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7003 || (GET_CODE (op1) == REG
7004 && REGNO (op1) >= FIRST_PSEUDO_REGISTER))
7005 tem = op0, op0 = op1, op1 = tem;
7007 gen_reload (out, op0, opnum, type);
7009 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7010 This fixes a problem on the 32K where the stack pointer cannot
7011 be used as an operand of an add insn. */
7013 if (rtx_equal_p (op0, op1))
7016 insn = emit_insn (gen_add2_insn (out, op1));
7018 /* If that failed, copy the address register to the reload register.
7019 Then add the constant to the reload register. */
7021 code = recog_memoized (insn);
7025 insn_extract (insn);
7026 /* We want constrain operands to treat this insn strictly in
7027 its validity determination, i.e., the way it would after reload
7029 if (constrain_operands (code, 1))
7033 delete_insns_since (last);
7035 gen_reload (out, op1, opnum, type);
7036 emit_insn (gen_add2_insn (out, op0));
7039 #ifdef SECONDARY_MEMORY_NEEDED
7040 /* If we need a memory location to do the move, do it that way. */
7041 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7042 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7043 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7044 REGNO_REG_CLASS (REGNO (out)),
7047 /* Get the memory to use and rewrite both registers to its mode. */
7048 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7050 if (GET_MODE (loc) != GET_MODE (out))
7051 out = gen_rtx (REG, GET_MODE (loc), REGNO (out));
7053 if (GET_MODE (loc) != GET_MODE (in))
7054 in = gen_rtx (REG, GET_MODE (loc), REGNO (in));
7056 gen_reload (loc, in, opnum, type);
7057 gen_reload (out, loc, opnum, type);
7061 /* If IN is a simple operand, use gen_move_insn. */
7062 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7063 emit_insn (gen_move_insn (out, in));
7065 #ifdef HAVE_reload_load_address
7066 else if (HAVE_reload_load_address)
7067 emit_insn (gen_reload_load_address (out, in));
7070 /* Otherwise, just write (set OUT IN) and hope for the best. */
7072 emit_insn (gen_rtx (SET, VOIDmode, out, in));
7074 /* Return the first insn emitted.
7075 We can not just return get_last_insn, because there may have
7076 been multiple instructions emitted. Also note that gen_move_insn may
7077 emit more than one insn itself, so we can not assume that there is one
7078 insn emitted per emit_insn_before call. */
7080 return last ? NEXT_INSN (last) : get_insns ();
7083 /* Delete a previously made output-reload
7084 whose result we now believe is not needed.
7085 First we double-check.
7087 INSN is the insn now being processed.
7088 OUTPUT_RELOAD_INSN is the insn of the output reload.
7089 J is the reload-number for this insn. */
7092 delete_output_reload (insn, j, output_reload_insn)
7095 rtx output_reload_insn;
7099 /* Get the raw pseudo-register referred to. */
7101 rtx reg = reload_in[j];
7102 while (GET_CODE (reg) == SUBREG)
7103 reg = SUBREG_REG (reg);
7105 /* If the pseudo-reg we are reloading is no longer referenced
7106 anywhere between the store into it and here,
7107 and no jumps or labels intervene, then the value can get
7108 here through the reload reg alone.
7109 Otherwise, give up--return. */
7110 for (i1 = NEXT_INSN (output_reload_insn);
7111 i1 != insn; i1 = NEXT_INSN (i1))
7113 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7115 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7116 && reg_mentioned_p (reg, PATTERN (i1)))
7120 if (cannot_omit_stores[REGNO (reg)])
7123 /* If this insn will store in the pseudo again,
7124 the previous store can be removed. */
7125 if (reload_out[j] == reload_in[j])
7126 delete_insn (output_reload_insn);
7128 /* See if the pseudo reg has been completely replaced
7129 with reload regs. If so, delete the store insn
7130 and forget we had a stack slot for the pseudo. */
7131 else if (reg_n_deaths[REGNO (reg)] == 1
7132 && reg_basic_block[REGNO (reg)] >= 0
7133 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7137 /* We know that it was used only between here
7138 and the beginning of the current basic block.
7139 (We also know that the last use before INSN was
7140 the output reload we are thinking of deleting, but never mind that.)
7141 Search that range; see if any ref remains. */
7142 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7144 rtx set = single_set (i2);
7146 /* Uses which just store in the pseudo don't count,
7147 since if they are the only uses, they are dead. */
7148 if (set != 0 && SET_DEST (set) == reg)
7150 if (GET_CODE (i2) == CODE_LABEL
7151 || GET_CODE (i2) == JUMP_INSN)
7153 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7154 && reg_mentioned_p (reg, PATTERN (i2)))
7155 /* Some other ref remains;
7156 we can't do anything. */
7160 /* Delete the now-dead stores into this pseudo. */
7161 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7163 rtx set = single_set (i2);
7165 if (set != 0 && SET_DEST (set) == reg)
7167 /* This might be a basic block head,
7168 thus don't use delete_insn. */
7169 PUT_CODE (i2, NOTE);
7170 NOTE_SOURCE_FILE (i2) = 0;
7171 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7173 if (GET_CODE (i2) == CODE_LABEL
7174 || GET_CODE (i2) == JUMP_INSN)
7178 /* For the debugging info,
7179 say the pseudo lives in this reload reg. */
7180 reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
7181 alter_reg (REGNO (reg), -1);
7185 /* Output reload-insns to reload VALUE into RELOADREG.
7186 VALUE is an autoincrement or autodecrement RTX whose operand
7187 is a register or memory location;
7188 so reloading involves incrementing that location.
7190 INC_AMOUNT is the number to increment or decrement by (always positive).
7191 This cannot be deduced from VALUE. */
7194 inc_for_reload (reloadreg, value, inc_amount)
7199 /* REG or MEM to be copied and incremented. */
7200 rtx incloc = XEXP (value, 0);
7201 /* Nonzero if increment after copying. */
7202 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7208 /* No hard register is equivalent to this register after
7209 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7210 we could inc/dec that register as well (maybe even using it for
7211 the source), but I'm not sure it's worth worrying about. */
7212 if (GET_CODE (incloc) == REG)
7213 reg_last_reload_reg[REGNO (incloc)] = 0;
7215 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7216 inc_amount = - inc_amount;
7218 inc = GEN_INT (inc_amount);
7220 /* If this is post-increment, first copy the location to the reload reg. */
7222 emit_insn (gen_move_insn (reloadreg, incloc));
7224 /* See if we can directly increment INCLOC. Use a method similar to that
7227 last = get_last_insn ();
7228 add_insn = emit_insn (gen_rtx (SET, VOIDmode, incloc,
7229 gen_rtx (PLUS, GET_MODE (incloc),
7232 code = recog_memoized (add_insn);
7235 insn_extract (add_insn);
7236 if (constrain_operands (code, 1))
7238 /* If this is a pre-increment and we have incremented the value
7239 where it lives, copy the incremented value to RELOADREG to
7240 be used as an address. */
7243 emit_insn (gen_move_insn (reloadreg, incloc));
7249 delete_insns_since (last);
7251 /* If couldn't do the increment directly, must increment in RELOADREG.
7252 The way we do this depends on whether this is pre- or post-increment.
7253 For pre-increment, copy INCLOC to the reload register, increment it
7254 there, then save back. */
7258 emit_insn (gen_move_insn (reloadreg, incloc));
7259 emit_insn (gen_add2_insn (reloadreg, inc));
7260 emit_insn (gen_move_insn (incloc, reloadreg));
7265 Because this might be a jump insn or a compare, and because RELOADREG
7266 may not be available after the insn in an input reload, we must do
7267 the incrementation before the insn being reloaded for.
7269 We have already copied INCLOC to RELOADREG. Increment the copy in
7270 RELOADREG, save that back, then decrement RELOADREG so it has
7271 the original value. */
7273 emit_insn (gen_add2_insn (reloadreg, inc));
7274 emit_insn (gen_move_insn (incloc, reloadreg));
7275 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7281 /* Return 1 if we are certain that the constraint-string STRING allows
7282 the hard register REG. Return 0 if we can't be sure of this. */
7285 constraint_accepts_reg_p (string, reg)
7290 int regno = true_regnum (reg);
7293 /* Initialize for first alternative. */
7295 /* Check that each alternative contains `g' or `r'. */
7297 switch (c = *string++)
7300 /* If an alternative lacks `g' or `r', we lose. */
7303 /* If an alternative lacks `g' or `r', we lose. */
7306 /* Initialize for next alternative. */
7311 /* Any general reg wins for this alternative. */
7312 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7316 /* Any reg in specified class wins for this alternative. */
7318 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7320 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
7326 /* Return the number of places FIND appears within X, but don't count
7327 an occurrence if some SET_DEST is FIND. */
7330 count_occurrences (x, find)
7331 register rtx x, find;
7334 register enum rtx_code code;
7335 register char *format_ptr;
7343 code = GET_CODE (x);
7358 if (SET_DEST (x) == find)
7359 return count_occurrences (SET_SRC (x), find);
7363 format_ptr = GET_RTX_FORMAT (code);
7366 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7368 switch (*format_ptr++)
7371 count += count_occurrences (XEXP (x, i), find);
7375 if (XVEC (x, i) != NULL)
7377 for (j = 0; j < XVECLEN (x, i); j++)
7378 count += count_occurrences (XVECEXP (x, i, j), find);
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