1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 88, 89, 92-6, 1997 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "insn-config.h"
27 #include "insn-flags.h"
28 #include "insn-codes.h"
32 #include "hard-reg-set.h"
35 #include "basic-block.h"
39 /* This file contains the reload pass of the compiler, which is
40 run after register allocation has been done. It checks that
41 each insn is valid (operands required to be in registers really
42 are in registers of the proper class) and fixes up invalid ones
43 by copying values temporarily into registers for the insns
46 The results of register allocation are described by the vector
47 reg_renumber; the insns still contain pseudo regs, but reg_renumber
48 can be used to find which hard reg, if any, a pseudo reg is in.
50 The technique we always use is to free up a few hard regs that are
51 called ``reload regs'', and for each place where a pseudo reg
52 must be in a hard reg, copy it temporarily into one of the reload regs.
54 All the pseudos that were formerly allocated to the hard regs that
55 are now in use as reload regs must be ``spilled''. This means
56 that they go to other hard regs, or to stack slots if no other
57 available hard regs can be found. Spilling can invalidate more
58 insns, requiring additional need for reloads, so we must keep checking
59 until the process stabilizes.
61 For machines with different classes of registers, we must keep track
62 of the register class needed for each reload, and make sure that
63 we allocate enough reload registers of each class.
65 The file reload.c contains the code that checks one insn for
66 validity and reports the reloads that it needs. This file
67 is in charge of scanning the entire rtl code, accumulating the
68 reload needs, spilling, assigning reload registers to use for
69 fixing up each insn, and generating the new insns to copy values
70 into the reload registers. */
73 #ifndef REGISTER_MOVE_COST
74 #define REGISTER_MOVE_COST(x, y) 2
77 #ifndef MEMORY_MOVE_COST
78 #define MEMORY_MOVE_COST(x) 4
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
106 This is used when the address is not valid as a memory address
107 (because its displacement is too big for the machine.) */
108 rtx *reg_equiv_address;
110 /* Element N is the memory slot to which pseudo reg N is equivalent,
111 or zero if pseudo reg N is not equivalent to a memory slot. */
114 /* Widest width in which each pseudo reg is referred to (via subreg). */
115 static int *reg_max_ref_width;
117 /* Element N is the insn that initialized reg N from its equivalent
118 constant or memory slot. */
119 static rtx *reg_equiv_init;
121 /* During reload_as_needed, element N contains the last pseudo regno
122 reloaded into the Nth reload register. This vector is in parallel
123 with spill_regs. If that pseudo reg occupied more than one register,
124 reg_reloaded_contents points to that pseudo for each spill register in
125 use; all of these must remain set for an inheritance to occur. */
126 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
128 /* During reload_as_needed, element N contains the insn for which
129 the Nth reload register was last used. This vector is in parallel
130 with spill_regs, and its contents are significant only when
131 reg_reloaded_contents is significant. */
132 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
134 /* Number of spill-regs so far; number of valid elements of spill_regs. */
137 /* In parallel with spill_regs, contains REG rtx's for those regs.
138 Holds the last rtx used for any given reg, or 0 if it has never
139 been used for spilling yet. This rtx is reused, provided it has
141 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
143 /* In parallel with spill_regs, contains nonzero for a spill reg
144 that was stored after the last time it was used.
145 The precise value is the insn generated to do the store. */
146 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
148 /* This table is the inverse mapping of spill_regs:
149 indexed by hard reg number,
150 it contains the position of that reg in spill_regs,
151 or -1 for something that is not in spill_regs. */
152 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
154 /* This reg set indicates registers that may not be used for retrying global
155 allocation. The registers that may not be used include all spill registers
156 and the frame pointer (if we are using one). */
157 HARD_REG_SET forbidden_regs;
159 /* This reg set indicates registers that are not good for spill registers.
160 They will not be used to complete groups of spill registers. This includes
161 all fixed registers, registers that may be eliminated, and, if
162 SMALL_REGISTER_CLASSES is zero, registers explicitly used in the rtl.
164 (spill_reg_order prevents these registers from being used to start a
166 static HARD_REG_SET bad_spill_regs;
168 /* Describes order of use of registers for reloading
169 of spilled pseudo-registers. `spills' is the number of
170 elements that are actually valid; new ones are added at the end. */
171 static short spill_regs[FIRST_PSEUDO_REGISTER];
173 /* This reg set indicates those registers that have been used a spill
174 registers. This information is used in reorg.c, to help figure out
175 what registers are live at any point. It is assumed that all spill_regs
176 are dead at every CODE_LABEL. */
178 HARD_REG_SET used_spill_regs;
180 /* Index of last register assigned as a spill register. We allocate in
181 a round-robin fashion. */
183 static int last_spill_reg;
185 /* Describes order of preference for putting regs into spill_regs.
186 Contains the numbers of all the hard regs, in order most preferred first.
187 This order is different for each function.
188 It is set up by order_regs_for_reload.
189 Empty elements at the end contain -1. */
190 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
192 /* 1 for a hard register that appears explicitly in the rtl
193 (for example, function value registers, special registers
194 used by insns, structure value pointer registers). */
195 static char regs_explicitly_used[FIRST_PSEUDO_REGISTER];
197 /* Indicates if a register was counted against the need for
198 groups. 0 means it can count against max_nongroup instead. */
199 static HARD_REG_SET counted_for_groups;
201 /* Indicates if a register was counted against the need for
202 non-groups. 0 means it can become part of a new group.
203 During choose_reload_regs, 1 here means don't use this reg
204 as part of a group, even if it seems to be otherwise ok. */
205 static HARD_REG_SET counted_for_nongroups;
207 /* Indexed by pseudo reg number N,
208 says may not delete stores into the real (memory) home of pseudo N.
209 This is set if we already substituted a memory equivalent in some uses,
210 which happens when we have to eliminate the fp from it. */
211 static char *cannot_omit_stores;
213 /* Nonzero if indirect addressing is supported on the machine; this means
214 that spilling (REG n) does not require reloading it into a register in
215 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
216 value indicates the level of indirect addressing supported, e.g., two
217 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
220 static char spill_indirect_levels;
222 /* Nonzero if indirect addressing is supported when the innermost MEM is
223 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
224 which these are valid is the same as spill_indirect_levels, above. */
226 char indirect_symref_ok;
228 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
230 char double_reg_address_ok;
232 /* Record the stack slot for each spilled hard register. */
234 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
236 /* Width allocated so far for that stack slot. */
238 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
240 /* Indexed by register class and basic block number, nonzero if there is
241 any need for a spill register of that class in that basic block.
242 The pointer is 0 if we did stupid allocation and don't know
243 the structure of basic blocks. */
245 char *basic_block_needs[N_REG_CLASSES];
247 /* First uid used by insns created by reload in this function.
248 Used in find_equiv_reg. */
249 int reload_first_uid;
251 /* Flag set by local-alloc or global-alloc if anything is live in
252 a call-clobbered reg across calls. */
254 int caller_save_needed;
256 /* The register class to use for a base register when reloading an
257 address. This is normally BASE_REG_CLASS, but it may be different
258 when using SMALL_REGISTER_CLASSES and passing parameters in
260 enum reg_class reload_address_base_reg_class;
262 /* The register class to use for an index register when reloading an
263 address. This is normally INDEX_REG_CLASS, but it may be different
264 when using SMALL_REGISTER_CLASSES and passing parameters in
266 enum reg_class reload_address_index_reg_class;
268 /* Set to 1 while reload_as_needed is operating.
269 Required by some machines to handle any generated moves differently. */
271 int reload_in_progress = 0;
273 /* These arrays record the insn_code of insns that may be needed to
274 perform input and output reloads of special objects. They provide a
275 place to pass a scratch register. */
277 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
278 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
280 /* This obstack is used for allocation of rtl during register elimination.
281 The allocated storage can be freed once find_reloads has processed the
284 struct obstack reload_obstack;
285 char *reload_firstobj;
287 #define obstack_chunk_alloc xmalloc
288 #define obstack_chunk_free free
290 /* List of labels that must never be deleted. */
291 extern rtx forced_labels;
293 /* Allocation number table from global register allocation. */
294 extern int *reg_allocno;
296 /* This structure is used to record information about register eliminations.
297 Each array entry describes one possible way of eliminating a register
298 in favor of another. If there is more than one way of eliminating a
299 particular register, the most preferred should be specified first. */
301 static struct elim_table
303 int from; /* Register number to be eliminated. */
304 int to; /* Register number used as replacement. */
305 int initial_offset; /* Initial difference between values. */
306 int can_eliminate; /* Non-zero if this elimination can be done. */
307 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
308 insns made by reload. */
309 int offset; /* Current offset between the two regs. */
310 int max_offset; /* Maximum offset between the two regs. */
311 int previous_offset; /* Offset at end of previous insn. */
312 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
313 rtx from_rtx; /* REG rtx for the register to be eliminated.
314 We cannot simply compare the number since
315 we might then spuriously replace a hard
316 register corresponding to a pseudo
317 assigned to the reg to be eliminated. */
318 rtx to_rtx; /* REG rtx for the replacement. */
321 /* If a set of eliminable registers was specified, define the table from it.
322 Otherwise, default to the normal case of the frame pointer being
323 replaced by the stack pointer. */
325 #ifdef ELIMINABLE_REGS
328 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
331 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0])
333 /* Record the number of pending eliminations that have an offset not equal
334 to their initial offset. If non-zero, we use a new copy of each
335 replacement result in any insns encountered. */
336 static int num_not_at_initial_offset;
338 /* Count the number of registers that we may be able to eliminate. */
339 static int num_eliminable;
341 /* For each label, we record the offset of each elimination. If we reach
342 a label by more than one path and an offset differs, we cannot do the
343 elimination. This information is indexed by the number of the label.
344 The first table is an array of flags that records whether we have yet
345 encountered a label and the second table is an array of arrays, one
346 entry in the latter array for each elimination. */
348 static char *offsets_known_at;
349 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
351 /* Number of labels in the current function. */
353 static int num_labels;
355 struct hard_reg_n_uses { int regno; int uses; };
357 static int possible_group_p PROTO((int, int *));
358 static void count_possible_groups PROTO((int *, enum machine_mode *,
360 static int modes_equiv_for_class_p PROTO((enum machine_mode,
363 static void spill_failure PROTO((rtx));
364 static int new_spill_reg PROTO((int, int, int *, int *, int,
366 static void delete_dead_insn PROTO((rtx));
367 static void alter_reg PROTO((int, int));
368 static void mark_scratch_live PROTO((rtx));
369 static void set_label_offsets PROTO((rtx, rtx, int));
370 static int eliminate_regs_in_insn PROTO((rtx, int));
371 static void mark_not_eliminable PROTO((rtx, rtx));
372 static int spill_hard_reg PROTO((int, int, FILE *, int));
373 static void scan_paradoxical_subregs PROTO((rtx));
374 static int hard_reg_use_compare PROTO((const GENERIC_PTR, const GENERIC_PTR));
375 static void order_regs_for_reload PROTO((int));
376 static int compare_spill_regs PROTO((const GENERIC_PTR, const GENERIC_PTR));
377 static void reload_as_needed PROTO((rtx, int));
378 static void forget_old_reloads_1 PROTO((rtx, rtx));
379 static int reload_reg_class_lower PROTO((const GENERIC_PTR, const GENERIC_PTR));
380 static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
382 static void clear_reload_reg_in_use PROTO((int, int, enum reload_type,
384 static int reload_reg_free_p PROTO((int, int, enum reload_type));
385 static int reload_reg_free_before_p PROTO((int, int, enum reload_type));
386 static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
387 static int reloads_conflict PROTO((int, int));
388 static int allocate_reload_reg PROTO((int, rtx, int, int));
389 static void choose_reload_regs PROTO((rtx, rtx));
390 static void merge_assigned_reloads PROTO((rtx));
391 static void emit_reload_insns PROTO((rtx));
392 static void delete_output_reload PROTO((rtx, int, rtx));
393 static void inc_for_reload PROTO((rtx, rtx, int));
394 static int constraint_accepts_reg_p PROTO((char *, rtx));
395 static int count_occurrences PROTO((rtx, rtx));
396 static void reload_cse_invalidate_regno PROTO((int, enum machine_mode, int));
397 static int reload_cse_mem_conflict_p PROTO((rtx, rtx));
398 static void reload_cse_invalidate_mem PROTO((rtx));
399 static void reload_cse_invalidate_rtx PROTO((rtx, rtx));
400 static int reload_cse_regno_equal_p PROTO((int, rtx, enum machine_mode));
401 static int reload_cse_noop_set_p PROTO((rtx, rtx));
402 static int reload_cse_simplify_set PROTO((rtx, rtx));
403 static int reload_cse_simplify_operands PROTO((rtx));
404 static void reload_cse_check_clobber PROTO((rtx, rtx));
405 static void reload_cse_record_set PROTO((rtx, rtx));
406 static void reload_cse_delete_death_notes PROTO((rtx));
407 static void reload_cse_no_longer_dead PROTO((int, enum machine_mode));
409 /* Initialize the reload pass once per compilation. */
416 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
417 Set spill_indirect_levels to the number of levels such addressing is
418 permitted, zero if it is not permitted at all. */
421 = gen_rtx (MEM, Pmode,
422 gen_rtx (PLUS, Pmode,
423 gen_rtx (REG, Pmode, LAST_VIRTUAL_REGISTER + 1),
425 spill_indirect_levels = 0;
427 while (memory_address_p (QImode, tem))
429 spill_indirect_levels++;
430 tem = gen_rtx (MEM, Pmode, tem);
433 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
435 tem = gen_rtx (MEM, Pmode, gen_rtx (SYMBOL_REF, Pmode, "foo"));
436 indirect_symref_ok = memory_address_p (QImode, tem);
438 /* See if reg+reg is a valid (and offsettable) address. */
440 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
442 tem = gen_rtx (PLUS, Pmode,
443 gen_rtx (REG, Pmode, HARD_FRAME_POINTER_REGNUM),
444 gen_rtx (REG, Pmode, i));
445 /* This way, we make sure that reg+reg is an offsettable address. */
446 tem = plus_constant (tem, 4);
448 if (memory_address_p (QImode, tem))
450 double_reg_address_ok = 1;
455 /* Initialize obstack for our rtl allocation. */
456 gcc_obstack_init (&reload_obstack);
457 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
459 /* Decide which register class should be used when reloading
460 addresses. If we are using SMALL_REGISTER_CLASSES, and any
461 parameters are passed in registers, then we do not want to use
462 those registers when reloading an address. Otherwise, if a
463 function argument needs a reload, we may wind up clobbering
464 another argument to the function which was already computed. If
465 we find a subset class which simply avoids those registers, we
466 use it instead. ??? It would be better to only use the
467 restricted class when we actually are loading function arguments,
468 but that is hard to determine. */
469 reload_address_base_reg_class = BASE_REG_CLASS;
470 reload_address_index_reg_class = INDEX_REG_CLASS;
471 if (SMALL_REGISTER_CLASSES)
474 HARD_REG_SET base, index;
477 COPY_HARD_REG_SET (base, reg_class_contents[BASE_REG_CLASS]);
478 COPY_HARD_REG_SET (index, reg_class_contents[INDEX_REG_CLASS]);
479 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
481 if (FUNCTION_ARG_REGNO_P (regno))
483 CLEAR_HARD_REG_BIT (base, regno);
484 CLEAR_HARD_REG_BIT (index, regno);
488 GO_IF_HARD_REG_EQUAL (base, reg_class_contents[BASE_REG_CLASS],
490 for (p = reg_class_subclasses[BASE_REG_CLASS];
491 *p != LIM_REG_CLASSES;
494 GO_IF_HARD_REG_EQUAL (base, reg_class_contents[*p], usebase);
497 reload_address_base_reg_class = *p;
502 GO_IF_HARD_REG_EQUAL (index, reg_class_contents[INDEX_REG_CLASS],
504 for (p = reg_class_subclasses[INDEX_REG_CLASS];
505 *p != LIM_REG_CLASSES;
508 GO_IF_HARD_REG_EQUAL (index, reg_class_contents[*p], useindex);
511 reload_address_index_reg_class = *p;
518 /* Main entry point for the reload pass.
520 FIRST is the first insn of the function being compiled.
522 GLOBAL nonzero means we were called from global_alloc
523 and should attempt to reallocate any pseudoregs that we
524 displace from hard regs we will use for reloads.
525 If GLOBAL is zero, we do not have enough information to do that,
526 so any pseudo reg that is spilled must go to the stack.
528 DUMPFILE is the global-reg debugging dump file stream, or 0.
529 If it is nonzero, messages are written to it to describe
530 which registers are seized as reload regs, which pseudo regs
531 are spilled from them, and where the pseudo regs are reallocated to.
533 Return value is nonzero if reload failed
534 and we must not do any more for this function. */
537 reload (first, global, dumpfile)
543 register int i, j, k;
545 register struct elim_table *ep;
547 /* The two pointers used to track the true location of the memory used
548 for label offsets. */
549 char *real_known_ptr = NULL_PTR;
550 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
552 int something_changed;
553 int something_needs_reloads;
554 int something_needs_elimination;
555 int new_basic_block_needs;
556 enum reg_class caller_save_spill_class = NO_REGS;
557 int caller_save_group_size = 1;
559 /* Nonzero means we couldn't get enough spill regs. */
562 /* The basic block number currently being processed for INSN. */
565 /* Make sure even insns with volatile mem refs are recognizable. */
568 /* Enable find_equiv_reg to distinguish insns made by reload. */
569 reload_first_uid = get_max_uid ();
571 for (i = 0; i < N_REG_CLASSES; i++)
572 basic_block_needs[i] = 0;
574 #ifdef SECONDARY_MEMORY_NEEDED
575 /* Initialize the secondary memory table. */
576 clear_secondary_mem ();
579 /* Remember which hard regs appear explicitly
580 before we merge into `regs_ever_live' the ones in which
581 pseudo regs have been allocated. */
582 bcopy (regs_ever_live, regs_explicitly_used, sizeof regs_ever_live);
584 /* We don't have a stack slot for any spill reg yet. */
585 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
586 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
588 /* Initialize the save area information for caller-save, in case some
592 /* Compute which hard registers are now in use
593 as homes for pseudo registers.
594 This is done here rather than (eg) in global_alloc
595 because this point is reached even if not optimizing. */
596 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
599 /* A function that receives a nonlocal goto must save all call-saved
601 if (current_function_has_nonlocal_label)
602 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
604 if (! call_used_regs[i] && ! fixed_regs[i])
605 regs_ever_live[i] = 1;
608 for (i = 0; i < scratch_list_length; i++)
610 mark_scratch_live (scratch_list[i]);
612 /* Make sure that the last insn in the chain
613 is not something that needs reloading. */
614 emit_note (NULL_PTR, NOTE_INSN_DELETED);
616 /* Find all the pseudo registers that didn't get hard regs
617 but do have known equivalent constants or memory slots.
618 These include parameters (known equivalent to parameter slots)
619 and cse'd or loop-moved constant memory addresses.
621 Record constant equivalents in reg_equiv_constant
622 so they will be substituted by find_reloads.
623 Record memory equivalents in reg_mem_equiv so they can
624 be substituted eventually by altering the REG-rtx's. */
626 reg_equiv_constant = (rtx *) alloca (max_regno * sizeof (rtx));
627 bzero ((char *) reg_equiv_constant, max_regno * sizeof (rtx));
628 reg_equiv_memory_loc = (rtx *) alloca (max_regno * sizeof (rtx));
629 bzero ((char *) reg_equiv_memory_loc, max_regno * sizeof (rtx));
630 reg_equiv_mem = (rtx *) alloca (max_regno * sizeof (rtx));
631 bzero ((char *) reg_equiv_mem, max_regno * sizeof (rtx));
632 reg_equiv_init = (rtx *) alloca (max_regno * sizeof (rtx));
633 bzero ((char *) reg_equiv_init, max_regno * sizeof (rtx));
634 reg_equiv_address = (rtx *) alloca (max_regno * sizeof (rtx));
635 bzero ((char *) reg_equiv_address, max_regno * sizeof (rtx));
636 reg_max_ref_width = (int *) alloca (max_regno * sizeof (int));
637 bzero ((char *) reg_max_ref_width, max_regno * sizeof (int));
638 cannot_omit_stores = (char *) alloca (max_regno);
639 bzero (cannot_omit_stores, max_regno);
641 if (SMALL_REGISTER_CLASSES)
642 CLEAR_HARD_REG_SET (forbidden_regs);
644 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
645 Also find all paradoxical subregs and find largest such for each pseudo.
646 On machines with small register classes, record hard registers that
647 are used for user variables. These can never be used for spills.
648 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
649 caller-saved registers must be marked live. */
651 for (insn = first; insn; insn = NEXT_INSN (insn))
653 rtx set = single_set (insn);
655 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
656 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
657 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
658 if (! call_used_regs[i])
659 regs_ever_live[i] = 1;
661 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
663 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
665 #ifdef LEGITIMATE_PIC_OPERAND_P
666 && (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic
667 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
671 rtx x = XEXP (note, 0);
672 i = REGNO (SET_DEST (set));
673 if (i > LAST_VIRTUAL_REGISTER)
675 if (GET_CODE (x) == MEM)
677 /* If the operand is a PLUS, the MEM may be shared,
678 so make sure we have an unshared copy here. */
679 if (GET_CODE (XEXP (x, 0)) == PLUS)
682 reg_equiv_memory_loc[i] = x;
684 else if (CONSTANT_P (x))
686 if (LEGITIMATE_CONSTANT_P (x))
687 reg_equiv_constant[i] = x;
689 reg_equiv_memory_loc[i]
690 = force_const_mem (GET_MODE (SET_DEST (set)), x);
695 /* If this register is being made equivalent to a MEM
696 and the MEM is not SET_SRC, the equivalencing insn
697 is one with the MEM as a SET_DEST and it occurs later.
698 So don't mark this insn now. */
699 if (GET_CODE (x) != MEM
700 || rtx_equal_p (SET_SRC (set), x))
701 reg_equiv_init[i] = insn;
706 /* If this insn is setting a MEM from a register equivalent to it,
707 this is the equivalencing insn. */
708 else if (set && GET_CODE (SET_DEST (set)) == MEM
709 && GET_CODE (SET_SRC (set)) == REG
710 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
711 && rtx_equal_p (SET_DEST (set),
712 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
713 reg_equiv_init[REGNO (SET_SRC (set))] = insn;
715 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
716 scan_paradoxical_subregs (PATTERN (insn));
719 /* Does this function require a frame pointer? */
721 frame_pointer_needed = (! flag_omit_frame_pointer
722 #ifdef EXIT_IGNORE_STACK
723 /* ?? If EXIT_IGNORE_STACK is set, we will not save
724 and restore sp for alloca. So we can't eliminate
725 the frame pointer in that case. At some point,
726 we should improve this by emitting the
727 sp-adjusting insns for this case. */
728 || (current_function_calls_alloca
729 && EXIT_IGNORE_STACK)
731 || FRAME_POINTER_REQUIRED);
735 /* Initialize the table of registers to eliminate. The way we do this
736 depends on how the eliminable registers were defined. */
737 #ifdef ELIMINABLE_REGS
738 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
740 ep->can_eliminate = ep->can_eliminate_previous
741 = (CAN_ELIMINATE (ep->from, ep->to)
742 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
745 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
746 = ! frame_pointer_needed;
749 /* Count the number of eliminable registers and build the FROM and TO
750 REG rtx's. Note that code in gen_rtx will cause, e.g.,
751 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
752 We depend on this. */
753 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
755 num_eliminable += ep->can_eliminate;
756 ep->from_rtx = gen_rtx (REG, Pmode, ep->from);
757 ep->to_rtx = gen_rtx (REG, Pmode, ep->to);
760 num_labels = max_label_num () - get_first_label_num ();
762 /* Allocate the tables used to store offset information at labels. */
763 /* We used to use alloca here, but the size of what it would try to
764 allocate would occasionally cause it to exceed the stack limit and
765 cause a core dump. */
766 real_known_ptr = xmalloc (num_labels);
768 = (int (*)[NUM_ELIMINABLE_REGS])
769 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
771 offsets_known_at = real_known_ptr - get_first_label_num ();
773 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
775 /* Alter each pseudo-reg rtx to contain its hard reg number.
776 Assign stack slots to the pseudos that lack hard regs or equivalents.
777 Do not touch virtual registers. */
779 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
782 /* If we have some registers we think can be eliminated, scan all insns to
783 see if there is an insn that sets one of these registers to something
784 other than itself plus a constant. If so, the register cannot be
785 eliminated. Doing this scan here eliminates an extra pass through the
786 main reload loop in the most common case where register elimination
788 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
789 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
790 || GET_CODE (insn) == CALL_INSN)
791 note_stores (PATTERN (insn), mark_not_eliminable);
793 #ifndef REGISTER_CONSTRAINTS
794 /* If all the pseudo regs have hard regs,
795 except for those that are never referenced,
796 we know that no reloads are needed. */
797 /* But that is not true if there are register constraints, since
798 in that case some pseudos might be in the wrong kind of hard reg. */
800 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
801 if (reg_renumber[i] == -1 && REG_N_REFS (i) != 0)
804 if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
806 free (real_known_ptr);
812 /* Compute the order of preference for hard registers to spill.
813 Store them by decreasing preference in potential_reload_regs. */
815 order_regs_for_reload (global);
817 /* So far, no hard regs have been spilled. */
819 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
820 spill_reg_order[i] = -1;
822 /* Initialize to -1, which means take the first spill register. */
825 /* On most machines, we can't use any register explicitly used in the
826 rtl as a spill register. But on some, we have to. Those will have
827 taken care to keep the life of hard regs as short as possible. */
829 if (! SMALL_REGISTER_CLASSES)
830 COPY_HARD_REG_SET (forbidden_regs, bad_spill_regs);
832 /* Spill any hard regs that we know we can't eliminate. */
833 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
834 if (! ep->can_eliminate)
835 spill_hard_reg (ep->from, global, dumpfile, 1);
837 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
838 if (frame_pointer_needed)
839 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, global, dumpfile, 1);
843 for (i = 0; i < N_REG_CLASSES; i++)
845 basic_block_needs[i] = (char *) alloca (n_basic_blocks);
846 bzero (basic_block_needs[i], n_basic_blocks);
849 /* From now on, we need to emit any moves without making new pseudos. */
850 reload_in_progress = 1;
852 /* This loop scans the entire function each go-round
853 and repeats until one repetition spills no additional hard regs. */
855 /* This flag is set when a pseudo reg is spilled,
856 to require another pass. Note that getting an additional reload
857 reg does not necessarily imply any pseudo reg was spilled;
858 sometimes we find a reload reg that no pseudo reg was allocated in. */
859 something_changed = 1;
860 /* This flag is set if there are any insns that require reloading. */
861 something_needs_reloads = 0;
862 /* This flag is set if there are any insns that require register
864 something_needs_elimination = 0;
865 while (something_changed)
869 /* For each class, number of reload regs needed in that class.
870 This is the maximum over all insns of the needs in that class
871 of the individual insn. */
872 int max_needs[N_REG_CLASSES];
873 /* For each class, size of group of consecutive regs
874 that is needed for the reloads of this class. */
875 int group_size[N_REG_CLASSES];
876 /* For each class, max number of consecutive groups needed.
877 (Each group contains group_size[CLASS] consecutive registers.) */
878 int max_groups[N_REG_CLASSES];
879 /* For each class, max number needed of regs that don't belong
880 to any of the groups. */
881 int max_nongroups[N_REG_CLASSES];
882 /* For each class, the machine mode which requires consecutive
883 groups of regs of that class.
884 If two different modes ever require groups of one class,
885 they must be the same size and equally restrictive for that class,
886 otherwise we can't handle the complexity. */
887 enum machine_mode group_mode[N_REG_CLASSES];
888 /* Record the insn where each maximum need is first found. */
889 rtx max_needs_insn[N_REG_CLASSES];
890 rtx max_groups_insn[N_REG_CLASSES];
891 rtx max_nongroups_insn[N_REG_CLASSES];
893 HOST_WIDE_INT starting_frame_size;
894 int previous_frame_pointer_needed = frame_pointer_needed;
895 static char *reg_class_names[] = REG_CLASS_NAMES;
897 something_changed = 0;
898 bzero ((char *) max_needs, sizeof max_needs);
899 bzero ((char *) max_groups, sizeof max_groups);
900 bzero ((char *) max_nongroups, sizeof max_nongroups);
901 bzero ((char *) max_needs_insn, sizeof max_needs_insn);
902 bzero ((char *) max_groups_insn, sizeof max_groups_insn);
903 bzero ((char *) max_nongroups_insn, sizeof max_nongroups_insn);
904 bzero ((char *) group_size, sizeof group_size);
905 for (i = 0; i < N_REG_CLASSES; i++)
906 group_mode[i] = VOIDmode;
908 /* Keep track of which basic blocks are needing the reloads. */
911 /* Remember whether any element of basic_block_needs
912 changes from 0 to 1 in this pass. */
913 new_basic_block_needs = 0;
915 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done
916 here because the stack size may be a part of the offset computation
917 for register elimination, and there might have been new stack slots
918 created in the last iteration of this loop. */
919 assign_stack_local (BLKmode, 0, 0);
921 starting_frame_size = get_frame_size ();
923 /* Reset all offsets on eliminable registers to their initial values. */
924 #ifdef ELIMINABLE_REGS
925 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
927 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
928 ep->previous_offset = ep->offset
929 = ep->max_offset = ep->initial_offset;
932 #ifdef INITIAL_FRAME_POINTER_OFFSET
933 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
935 if (!FRAME_POINTER_REQUIRED)
937 reg_eliminate[0].initial_offset = 0;
939 reg_eliminate[0].previous_offset = reg_eliminate[0].max_offset
940 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
943 num_not_at_initial_offset = 0;
945 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
947 /* Set a known offset for each forced label to be at the initial offset
948 of each elimination. We do this because we assume that all
949 computed jumps occur from a location where each elimination is
950 at its initial offset. */
952 for (x = forced_labels; x; x = XEXP (x, 1))
954 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
956 /* For each pseudo register that has an equivalent location defined,
957 try to eliminate any eliminable registers (such as the frame pointer)
958 assuming initial offsets for the replacement register, which
961 If the resulting location is directly addressable, substitute
962 the MEM we just got directly for the old REG.
964 If it is not addressable but is a constant or the sum of a hard reg
965 and constant, it is probably not addressable because the constant is
966 out of range, in that case record the address; we will generate
967 hairy code to compute the address in a register each time it is
968 needed. Similarly if it is a hard register, but one that is not
969 valid as an address register.
971 If the location is not addressable, but does not have one of the
972 above forms, assign a stack slot. We have to do this to avoid the
973 potential of producing lots of reloads if, e.g., a location involves
974 a pseudo that didn't get a hard register and has an equivalent memory
975 location that also involves a pseudo that didn't get a hard register.
977 Perhaps at some point we will improve reload_when_needed handling
978 so this problem goes away. But that's very hairy. */
980 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
981 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
983 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX, 0);
985 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
987 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
988 else if (CONSTANT_P (XEXP (x, 0))
989 || (GET_CODE (XEXP (x, 0)) == REG
990 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
991 || (GET_CODE (XEXP (x, 0)) == PLUS
992 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
993 && (REGNO (XEXP (XEXP (x, 0), 0))
994 < FIRST_PSEUDO_REGISTER)
995 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
996 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
999 /* Make a new stack slot. Then indicate that something
1000 changed so we go back and recompute offsets for
1001 eliminable registers because the allocation of memory
1002 below might change some offset. reg_equiv_{mem,address}
1003 will be set up for this pseudo on the next pass around
1005 reg_equiv_memory_loc[i] = 0;
1006 reg_equiv_init[i] = 0;
1008 something_changed = 1;
1012 /* If we allocated another pseudo to the stack, redo elimination
1014 if (something_changed)
1017 /* If caller-saves needs a group, initialize the group to include
1018 the size and mode required for caller-saves. */
1020 if (caller_save_group_size > 1)
1022 group_mode[(int) caller_save_spill_class] = Pmode;
1023 group_size[(int) caller_save_spill_class] = caller_save_group_size;
1026 /* Compute the most additional registers needed by any instruction.
1027 Collect information separately for each class of regs. */
1029 for (insn = first; insn; insn = NEXT_INSN (insn))
1031 if (global && this_block + 1 < n_basic_blocks
1032 && insn == basic_block_head[this_block+1])
1035 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which
1036 might include REG_LABEL), we need to see what effects this
1037 has on the known offsets at labels. */
1039 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1040 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1041 && REG_NOTES (insn) != 0))
1042 set_label_offsets (insn, insn, 0);
1044 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1046 /* Nonzero means don't use a reload reg that overlaps
1047 the place where a function value can be returned. */
1048 rtx avoid_return_reg = 0;
1050 rtx old_body = PATTERN (insn);
1051 int old_code = INSN_CODE (insn);
1052 rtx old_notes = REG_NOTES (insn);
1053 int did_elimination = 0;
1055 /* To compute the number of reload registers of each class
1056 needed for an insn, we must simulate what choose_reload_regs
1057 can do. We do this by splitting an insn into an "input" and
1058 an "output" part. RELOAD_OTHER reloads are used in both.
1059 The input part uses those reloads, RELOAD_FOR_INPUT reloads,
1060 which must be live over the entire input section of reloads,
1061 and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
1062 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the
1065 The registers needed for output are RELOAD_OTHER and
1066 RELOAD_FOR_OUTPUT, which are live for the entire output
1067 portion, and the maximum of all the RELOAD_FOR_OUTPUT_ADDRESS
1068 reloads for each operand.
1070 The total number of registers needed is the maximum of the
1071 inputs and outputs. */
1075 /* [0] is normal, [1] is nongroup. */
1076 int regs[2][N_REG_CLASSES];
1077 int groups[N_REG_CLASSES];
1080 /* Each `struct needs' corresponds to one RELOAD_... type. */
1084 struct needs output;
1086 struct needs other_addr;
1087 struct needs op_addr;
1088 struct needs op_addr_reload;
1089 struct needs in_addr[MAX_RECOG_OPERANDS];
1090 struct needs in_addr_addr[MAX_RECOG_OPERANDS];
1091 struct needs out_addr[MAX_RECOG_OPERANDS];
1092 struct needs out_addr_addr[MAX_RECOG_OPERANDS];
1095 /* If needed, eliminate any eliminable registers. */
1097 did_elimination = eliminate_regs_in_insn (insn, 0);
1099 /* Set avoid_return_reg if this is an insn
1100 that might use the value of a function call. */
1101 if (SMALL_REGISTER_CLASSES && GET_CODE (insn) == CALL_INSN)
1103 if (GET_CODE (PATTERN (insn)) == SET)
1104 after_call = SET_DEST (PATTERN (insn));
1105 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1106 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1107 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
1111 else if (SMALL_REGISTER_CLASSES && after_call != 0
1112 && !(GET_CODE (PATTERN (insn)) == SET
1113 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
1115 if (reg_referenced_p (after_call, PATTERN (insn)))
1116 avoid_return_reg = after_call;
1120 /* Analyze the instruction. */
1121 find_reloads (insn, 0, spill_indirect_levels, global,
1124 /* Remember for later shortcuts which insns had any reloads or
1125 register eliminations.
1127 One might think that it would be worthwhile to mark insns
1128 that need register replacements but not reloads, but this is
1129 not safe because find_reloads may do some manipulation of
1130 the insn (such as swapping commutative operands), which would
1131 be lost when we restore the old pattern after register
1132 replacement. So the actions of find_reloads must be redone in
1133 subsequent passes or in reload_as_needed.
1135 However, it is safe to mark insns that need reloads
1136 but not register replacement. */
1138 PUT_MODE (insn, (did_elimination ? QImode
1139 : n_reloads ? HImode
1140 : GET_MODE (insn) == DImode ? DImode
1143 /* Discard any register replacements done. */
1144 if (did_elimination)
1146 obstack_free (&reload_obstack, reload_firstobj);
1147 PATTERN (insn) = old_body;
1148 INSN_CODE (insn) = old_code;
1149 REG_NOTES (insn) = old_notes;
1150 something_needs_elimination = 1;
1153 /* If this insn has no reloads, we need not do anything except
1154 in the case of a CALL_INSN when we have caller-saves and
1155 caller-save needs reloads. */
1158 && ! (GET_CODE (insn) == CALL_INSN
1159 && caller_save_spill_class != NO_REGS))
1162 something_needs_reloads = 1;
1163 bzero ((char *) &insn_needs, sizeof insn_needs);
1165 /* Count each reload once in every class
1166 containing the reload's own class. */
1168 for (i = 0; i < n_reloads; i++)
1170 register enum reg_class *p;
1171 enum reg_class class = reload_reg_class[i];
1173 enum machine_mode mode;
1175 struct needs *this_needs;
1177 /* Don't count the dummy reloads, for which one of the
1178 regs mentioned in the insn can be used for reloading.
1179 Don't count optional reloads.
1180 Don't count reloads that got combined with others. */
1181 if (reload_reg_rtx[i] != 0
1182 || reload_optional[i] != 0
1183 || (reload_out[i] == 0 && reload_in[i] == 0
1184 && ! reload_secondary_p[i]))
1187 /* Show that a reload register of this class is needed
1188 in this basic block. We do not use insn_needs and
1189 insn_groups because they are overly conservative for
1191 if (global && ! basic_block_needs[(int) class][this_block])
1193 basic_block_needs[(int) class][this_block] = 1;
1194 new_basic_block_needs = 1;
1197 mode = reload_inmode[i];
1198 if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1199 mode = reload_outmode[i];
1200 size = CLASS_MAX_NREGS (class, mode);
1202 /* If this class doesn't want a group, determine if we have
1203 a nongroup need or a regular need. We have a nongroup
1204 need if this reload conflicts with a group reload whose
1205 class intersects with this reload's class. */
1209 for (j = 0; j < n_reloads; j++)
1210 if ((CLASS_MAX_NREGS (reload_reg_class[j],
1211 (GET_MODE_SIZE (reload_outmode[j])
1212 > GET_MODE_SIZE (reload_inmode[j]))
1216 && (!reload_optional[j])
1217 && (reload_in[j] != 0 || reload_out[j] != 0
1218 || reload_secondary_p[j])
1219 && reloads_conflict (i, j)
1220 && reg_classes_intersect_p (class,
1221 reload_reg_class[j]))
1227 /* Decide which time-of-use to count this reload for. */
1228 switch (reload_when_needed[i])
1231 this_needs = &insn_needs.other;
1233 case RELOAD_FOR_INPUT:
1234 this_needs = &insn_needs.input;
1236 case RELOAD_FOR_OUTPUT:
1237 this_needs = &insn_needs.output;
1239 case RELOAD_FOR_INSN:
1240 this_needs = &insn_needs.insn;
1242 case RELOAD_FOR_OTHER_ADDRESS:
1243 this_needs = &insn_needs.other_addr;
1245 case RELOAD_FOR_INPUT_ADDRESS:
1246 this_needs = &insn_needs.in_addr[reload_opnum[i]];
1248 case RELOAD_FOR_INPADDR_ADDRESS:
1249 this_needs = &insn_needs.in_addr_addr[reload_opnum[i]];
1251 case RELOAD_FOR_OUTPUT_ADDRESS:
1252 this_needs = &insn_needs.out_addr[reload_opnum[i]];
1254 case RELOAD_FOR_OUTADDR_ADDRESS:
1255 this_needs = &insn_needs.out_addr_addr[reload_opnum[i]];
1257 case RELOAD_FOR_OPERAND_ADDRESS:
1258 this_needs = &insn_needs.op_addr;
1260 case RELOAD_FOR_OPADDR_ADDR:
1261 this_needs = &insn_needs.op_addr_reload;
1267 enum machine_mode other_mode, allocate_mode;
1269 /* Count number of groups needed separately from
1270 number of individual regs needed. */
1271 this_needs->groups[(int) class]++;
1272 p = reg_class_superclasses[(int) class];
1273 while (*p != LIM_REG_CLASSES)
1274 this_needs->groups[(int) *p++]++;
1276 /* Record size and mode of a group of this class. */
1277 /* If more than one size group is needed,
1278 make all groups the largest needed size. */
1279 if (group_size[(int) class] < size)
1281 other_mode = group_mode[(int) class];
1282 allocate_mode = mode;
1284 group_size[(int) class] = size;
1285 group_mode[(int) class] = mode;
1290 allocate_mode = group_mode[(int) class];
1293 /* Crash if two dissimilar machine modes both need
1294 groups of consecutive regs of the same class. */
1296 if (other_mode != VOIDmode && other_mode != allocate_mode
1297 && ! modes_equiv_for_class_p (allocate_mode,
1299 fatal_insn ("Two dissimilar machine modes both need groups of consecutive regs of the same class",
1304 this_needs->regs[nongroup_need][(int) class] += 1;
1305 p = reg_class_superclasses[(int) class];
1306 while (*p != LIM_REG_CLASSES)
1307 this_needs->regs[nongroup_need][(int) *p++] += 1;
1313 /* All reloads have been counted for this insn;
1314 now merge the various times of use.
1315 This sets insn_needs, etc., to the maximum total number
1316 of registers needed at any point in this insn. */
1318 for (i = 0; i < N_REG_CLASSES; i++)
1320 int in_max, out_max;
1322 /* Compute normal and nongroup needs. */
1323 for (j = 0; j <= 1; j++)
1325 for (in_max = 0, out_max = 0, k = 0;
1326 k < reload_n_operands; k++)
1330 (insn_needs.in_addr[k].regs[j][i]
1331 + insn_needs.in_addr_addr[k].regs[j][i]));
1333 = MAX (out_max, insn_needs.out_addr[k].regs[j][i]);
1336 insn_needs.out_addr_addr[k].regs[j][i]);
1339 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1340 and operand addresses but not things used to reload
1341 them. Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads
1342 don't conflict with things needed to reload inputs or
1345 in_max = MAX (MAX (insn_needs.op_addr.regs[j][i],
1346 insn_needs.op_addr_reload.regs[j][i]),
1349 out_max = MAX (out_max, insn_needs.insn.regs[j][i]);
1351 insn_needs.input.regs[j][i]
1352 = MAX (insn_needs.input.regs[j][i]
1353 + insn_needs.op_addr.regs[j][i]
1354 + insn_needs.insn.regs[j][i],
1355 in_max + insn_needs.input.regs[j][i]);
1357 insn_needs.output.regs[j][i] += out_max;
1358 insn_needs.other.regs[j][i]
1359 += MAX (MAX (insn_needs.input.regs[j][i],
1360 insn_needs.output.regs[j][i]),
1361 insn_needs.other_addr.regs[j][i]);
1365 /* Now compute group needs. */
1366 for (in_max = 0, out_max = 0, j = 0;
1367 j < reload_n_operands; j++)
1369 in_max = MAX (in_max, insn_needs.in_addr[j].groups[i]);
1370 in_max = MAX (in_max,
1371 insn_needs.in_addr_addr[j].groups[i]);
1373 = MAX (out_max, insn_needs.out_addr[j].groups[i]);
1375 = MAX (out_max, insn_needs.out_addr_addr[j].groups[i]);
1378 in_max = MAX (MAX (insn_needs.op_addr.groups[i],
1379 insn_needs.op_addr_reload.groups[i]),
1381 out_max = MAX (out_max, insn_needs.insn.groups[i]);
1383 insn_needs.input.groups[i]
1384 = MAX (insn_needs.input.groups[i]
1385 + insn_needs.op_addr.groups[i]
1386 + insn_needs.insn.groups[i],
1387 in_max + insn_needs.input.groups[i]);
1389 insn_needs.output.groups[i] += out_max;
1390 insn_needs.other.groups[i]
1391 += MAX (MAX (insn_needs.input.groups[i],
1392 insn_needs.output.groups[i]),
1393 insn_needs.other_addr.groups[i]);
1396 /* If this is a CALL_INSN and caller-saves will need
1397 a spill register, act as if the spill register is
1398 needed for this insn. However, the spill register
1399 can be used by any reload of this insn, so we only
1400 need do something if no need for that class has
1403 The assumption that every CALL_INSN will trigger a
1404 caller-save is highly conservative, however, the number
1405 of cases where caller-saves will need a spill register but
1406 a block containing a CALL_INSN won't need a spill register
1407 of that class should be quite rare.
1409 If a group is needed, the size and mode of the group will
1410 have been set up at the beginning of this loop. */
1412 if (GET_CODE (insn) == CALL_INSN
1413 && caller_save_spill_class != NO_REGS)
1415 /* See if this register would conflict with any reload
1416 that needs a group. */
1417 int nongroup_need = 0;
1418 int *caller_save_needs;
1420 for (j = 0; j < n_reloads; j++)
1421 if ((CLASS_MAX_NREGS (reload_reg_class[j],
1422 (GET_MODE_SIZE (reload_outmode[j])
1423 > GET_MODE_SIZE (reload_inmode[j]))
1427 && reg_classes_intersect_p (caller_save_spill_class,
1428 reload_reg_class[j]))
1435 = (caller_save_group_size > 1
1436 ? insn_needs.other.groups
1437 : insn_needs.other.regs[nongroup_need]);
1439 if (caller_save_needs[(int) caller_save_spill_class] == 0)
1441 register enum reg_class *p
1442 = reg_class_superclasses[(int) caller_save_spill_class];
1444 caller_save_needs[(int) caller_save_spill_class]++;
1446 while (*p != LIM_REG_CLASSES)
1447 caller_save_needs[(int) *p++] += 1;
1450 /* Show that this basic block will need a register of
1454 && ! (basic_block_needs[(int) caller_save_spill_class]
1457 basic_block_needs[(int) caller_save_spill_class]
1459 new_basic_block_needs = 1;
1463 /* If this insn stores the value of a function call,
1464 and that value is in a register that has been spilled,
1465 and if the insn needs a reload in a class
1466 that might use that register as the reload register,
1467 then add add an extra need in that class.
1468 This makes sure we have a register available that does
1469 not overlap the return value. */
1471 if (SMALL_REGISTER_CLASSES && avoid_return_reg)
1473 int regno = REGNO (avoid_return_reg);
1475 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
1477 int basic_needs[N_REG_CLASSES], basic_groups[N_REG_CLASSES];
1479 /* First compute the "basic needs", which counts a
1480 need only in the smallest class in which it
1483 bcopy ((char *) insn_needs.other.regs[0],
1484 (char *) basic_needs, sizeof basic_needs);
1485 bcopy ((char *) insn_needs.other.groups,
1486 (char *) basic_groups, sizeof basic_groups);
1488 for (i = 0; i < N_REG_CLASSES; i++)
1492 if (basic_needs[i] >= 0)
1493 for (p = reg_class_superclasses[i];
1494 *p != LIM_REG_CLASSES; p++)
1495 basic_needs[(int) *p] -= basic_needs[i];
1497 if (basic_groups[i] >= 0)
1498 for (p = reg_class_superclasses[i];
1499 *p != LIM_REG_CLASSES; p++)
1500 basic_groups[(int) *p] -= basic_groups[i];
1503 /* Now count extra regs if there might be a conflict with
1504 the return value register. */
1506 for (r = regno; r < regno + nregs; r++)
1507 if (spill_reg_order[r] >= 0)
1508 for (i = 0; i < N_REG_CLASSES; i++)
1509 if (TEST_HARD_REG_BIT (reg_class_contents[i], r))
1511 if (basic_needs[i] > 0)
1515 insn_needs.other.regs[0][i]++;
1516 p = reg_class_superclasses[i];
1517 while (*p != LIM_REG_CLASSES)
1518 insn_needs.other.regs[0][(int) *p++]++;
1520 if (basic_groups[i] > 0)
1524 insn_needs.other.groups[i]++;
1525 p = reg_class_superclasses[i];
1526 while (*p != LIM_REG_CLASSES)
1527 insn_needs.other.groups[(int) *p++]++;
1532 /* For each class, collect maximum need of any insn. */
1534 for (i = 0; i < N_REG_CLASSES; i++)
1536 if (max_needs[i] < insn_needs.other.regs[0][i])
1538 max_needs[i] = insn_needs.other.regs[0][i];
1539 max_needs_insn[i] = insn;
1541 if (max_groups[i] < insn_needs.other.groups[i])
1543 max_groups[i] = insn_needs.other.groups[i];
1544 max_groups_insn[i] = insn;
1546 if (max_nongroups[i] < insn_needs.other.regs[1][i])
1548 max_nongroups[i] = insn_needs.other.regs[1][i];
1549 max_nongroups_insn[i] = insn;
1553 /* Note that there is a continue statement above. */
1556 /* If we allocated any new memory locations, make another pass
1557 since it might have changed elimination offsets. */
1558 if (starting_frame_size != get_frame_size ())
1559 something_changed = 1;
1562 for (i = 0; i < N_REG_CLASSES; i++)
1564 if (max_needs[i] > 0)
1566 ";; Need %d reg%s of class %s (for insn %d).\n",
1567 max_needs[i], max_needs[i] == 1 ? "" : "s",
1568 reg_class_names[i], INSN_UID (max_needs_insn[i]));
1569 if (max_nongroups[i] > 0)
1571 ";; Need %d nongroup reg%s of class %s (for insn %d).\n",
1572 max_nongroups[i], max_nongroups[i] == 1 ? "" : "s",
1573 reg_class_names[i], INSN_UID (max_nongroups_insn[i]));
1574 if (max_groups[i] > 0)
1576 ";; Need %d group%s (%smode) of class %s (for insn %d).\n",
1577 max_groups[i], max_groups[i] == 1 ? "" : "s",
1578 mode_name[(int) group_mode[i]],
1579 reg_class_names[i], INSN_UID (max_groups_insn[i]));
1582 /* If we have caller-saves, set up the save areas and see if caller-save
1583 will need a spill register. */
1585 if (caller_save_needed)
1587 /* Set the offsets for setup_save_areas. */
1588 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
1590 ep->previous_offset = ep->max_offset;
1592 if ( ! setup_save_areas (&something_changed)
1593 && caller_save_spill_class == NO_REGS)
1595 /* The class we will need depends on whether the machine
1596 supports the sum of two registers for an address; see
1597 find_address_reloads for details. */
1599 caller_save_spill_class
1600 = double_reg_address_ok ? INDEX_REG_CLASS : BASE_REG_CLASS;
1601 caller_save_group_size
1602 = CLASS_MAX_NREGS (caller_save_spill_class, Pmode);
1603 something_changed = 1;
1607 /* See if anything that happened changes which eliminations are valid.
1608 For example, on the Sparc, whether or not the frame pointer can
1609 be eliminated can depend on what registers have been used. We need
1610 not check some conditions again (such as flag_omit_frame_pointer)
1611 since they can't have changed. */
1613 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1614 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
1615 #ifdef ELIMINABLE_REGS
1616 || ! CAN_ELIMINATE (ep->from, ep->to)
1619 ep->can_eliminate = 0;
1621 /* Look for the case where we have discovered that we can't replace
1622 register A with register B and that means that we will now be
1623 trying to replace register A with register C. This means we can
1624 no longer replace register C with register B and we need to disable
1625 such an elimination, if it exists. This occurs often with A == ap,
1626 B == sp, and C == fp. */
1628 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1630 struct elim_table *op;
1631 register int new_to = -1;
1633 if (! ep->can_eliminate && ep->can_eliminate_previous)
1635 /* Find the current elimination for ep->from, if there is a
1637 for (op = reg_eliminate;
1638 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1639 if (op->from == ep->from && op->can_eliminate)
1645 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
1647 for (op = reg_eliminate;
1648 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1649 if (op->from == new_to && op->to == ep->to)
1650 op->can_eliminate = 0;
1654 /* See if any registers that we thought we could eliminate the previous
1655 time are no longer eliminable. If so, something has changed and we
1656 must spill the register. Also, recompute the number of eliminable
1657 registers and see if the frame pointer is needed; it is if there is
1658 no elimination of the frame pointer that we can perform. */
1660 frame_pointer_needed = 1;
1661 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1663 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
1664 && ep->to != HARD_FRAME_POINTER_REGNUM)
1665 frame_pointer_needed = 0;
1667 if (! ep->can_eliminate && ep->can_eliminate_previous)
1669 ep->can_eliminate_previous = 0;
1670 spill_hard_reg (ep->from, global, dumpfile, 1);
1671 something_changed = 1;
1676 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1677 /* If we didn't need a frame pointer last time, but we do now, spill
1678 the hard frame pointer. */
1679 if (frame_pointer_needed && ! previous_frame_pointer_needed)
1681 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, global, dumpfile, 1);
1682 something_changed = 1;
1686 /* If all needs are met, we win. */
1688 for (i = 0; i < N_REG_CLASSES; i++)
1689 if (max_needs[i] > 0 || max_groups[i] > 0 || max_nongroups[i] > 0)
1691 if (i == N_REG_CLASSES && !new_basic_block_needs && ! something_changed)
1694 /* Not all needs are met; must spill some hard regs. */
1696 /* Put all registers spilled so far back in potential_reload_regs, but
1697 put them at the front, since we've already spilled most of the
1698 pseudos in them (we might have left some pseudos unspilled if they
1699 were in a block that didn't need any spill registers of a conflicting
1700 class. We used to try to mark off the need for those registers,
1701 but doing so properly is very complex and reallocating them is the
1702 simpler approach. First, "pack" potential_reload_regs by pushing
1703 any nonnegative entries towards the end. That will leave room
1704 for the registers we already spilled.
1706 Also, undo the marking of the spill registers from the last time
1707 around in FORBIDDEN_REGS since we will be probably be allocating
1710 ??? It is theoretically possible that we might end up not using one
1711 of our previously-spilled registers in this allocation, even though
1712 they are at the head of the list. It's not clear what to do about
1713 this, but it was no better before, when we marked off the needs met
1714 by the previously-spilled registers. With the current code, globals
1715 can be allocated into these registers, but locals cannot. */
1719 for (i = j = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
1720 if (potential_reload_regs[i] != -1)
1721 potential_reload_regs[j--] = potential_reload_regs[i];
1723 for (i = 0; i < n_spills; i++)
1725 potential_reload_regs[i] = spill_regs[i];
1726 spill_reg_order[spill_regs[i]] = -1;
1727 CLEAR_HARD_REG_BIT (forbidden_regs, spill_regs[i]);
1733 /* Now find more reload regs to satisfy the remaining need
1734 Do it by ascending class number, since otherwise a reg
1735 might be spilled for a big class and might fail to count
1736 for a smaller class even though it belongs to that class.
1738 Count spilled regs in `spills', and add entries to
1739 `spill_regs' and `spill_reg_order'.
1741 ??? Note there is a problem here.
1742 When there is a need for a group in a high-numbered class,
1743 and also need for non-group regs that come from a lower class,
1744 the non-group regs are chosen first. If there aren't many regs,
1745 they might leave no room for a group.
1747 This was happening on the 386. To fix it, we added the code
1748 that calls possible_group_p, so that the lower class won't
1749 break up the last possible group.
1751 Really fixing the problem would require changes above
1752 in counting the regs already spilled, and in choose_reload_regs.
1753 It might be hard to avoid introducing bugs there. */
1755 CLEAR_HARD_REG_SET (counted_for_groups);
1756 CLEAR_HARD_REG_SET (counted_for_nongroups);
1758 for (class = 0; class < N_REG_CLASSES; class++)
1760 /* First get the groups of registers.
1761 If we got single registers first, we might fragment
1763 while (max_groups[class] > 0)
1765 /* If any single spilled regs happen to form groups,
1766 count them now. Maybe we don't really need
1767 to spill another group. */
1768 count_possible_groups (group_size, group_mode, max_groups,
1771 if (max_groups[class] <= 0)
1774 /* Groups of size 2 (the only groups used on most machines)
1775 are treated specially. */
1776 if (group_size[class] == 2)
1778 /* First, look for a register that will complete a group. */
1779 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1783 j = potential_reload_regs[i];
1784 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1786 ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1787 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1788 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1789 && HARD_REGNO_MODE_OK (other, group_mode[class])
1790 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1792 /* We don't want one part of another group.
1793 We could get "two groups" that overlap! */
1794 && ! TEST_HARD_REG_BIT (counted_for_groups, other))
1796 (j < FIRST_PSEUDO_REGISTER - 1
1797 && (other = j + 1, spill_reg_order[other] >= 0)
1798 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1799 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1800 && HARD_REGNO_MODE_OK (j, group_mode[class])
1801 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1803 && ! TEST_HARD_REG_BIT (counted_for_groups,
1806 register enum reg_class *p;
1808 /* We have found one that will complete a group,
1809 so count off one group as provided. */
1810 max_groups[class]--;
1811 p = reg_class_superclasses[class];
1812 while (*p != LIM_REG_CLASSES)
1814 if (group_size [(int) *p] <= group_size [class])
1815 max_groups[(int) *p]--;
1819 /* Indicate both these regs are part of a group. */
1820 SET_HARD_REG_BIT (counted_for_groups, j);
1821 SET_HARD_REG_BIT (counted_for_groups, other);
1825 /* We can't complete a group, so start one. */
1826 /* Look for a pair neither of which is explicitly used. */
1827 if (SMALL_REGISTER_CLASSES && i == FIRST_PSEUDO_REGISTER)
1828 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1831 j = potential_reload_regs[i];
1832 /* Verify that J+1 is a potential reload reg. */
1833 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1834 if (potential_reload_regs[k] == j + 1)
1836 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1837 && k < FIRST_PSEUDO_REGISTER
1838 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1839 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1840 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1841 && HARD_REGNO_MODE_OK (j, group_mode[class])
1842 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1844 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1)
1845 /* Reject J at this stage
1846 if J+1 was explicitly used. */
1847 && ! regs_explicitly_used[j + 1])
1850 /* Now try any group at all
1851 whose registers are not in bad_spill_regs. */
1852 if (i == FIRST_PSEUDO_REGISTER)
1853 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1856 j = potential_reload_regs[i];
1857 /* Verify that J+1 is a potential reload reg. */
1858 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1859 if (potential_reload_regs[k] == j + 1)
1861 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1862 && k < FIRST_PSEUDO_REGISTER
1863 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1864 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1865 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1866 && HARD_REGNO_MODE_OK (j, group_mode[class])
1867 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1869 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1))
1873 /* I should be the index in potential_reload_regs
1874 of the new reload reg we have found. */
1876 if (i >= FIRST_PSEUDO_REGISTER)
1878 /* There are no groups left to spill. */
1879 spill_failure (max_groups_insn[class]);
1885 |= new_spill_reg (i, class, max_needs, NULL_PTR,
1890 /* For groups of more than 2 registers,
1891 look for a sufficient sequence of unspilled registers,
1892 and spill them all at once. */
1893 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1897 j = potential_reload_regs[i];
1899 && j + group_size[class] <= FIRST_PSEUDO_REGISTER
1900 && HARD_REGNO_MODE_OK (j, group_mode[class]))
1902 /* Check each reg in the sequence. */
1903 for (k = 0; k < group_size[class]; k++)
1904 if (! (spill_reg_order[j + k] < 0
1905 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1906 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1908 /* We got a full sequence, so spill them all. */
1909 if (k == group_size[class])
1911 register enum reg_class *p;
1912 for (k = 0; k < group_size[class]; k++)
1915 SET_HARD_REG_BIT (counted_for_groups, j + k);
1916 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1917 if (potential_reload_regs[idx] == j + k)
1920 |= new_spill_reg (idx, class,
1921 max_needs, NULL_PTR,
1925 /* We have found one that will complete a group,
1926 so count off one group as provided. */
1927 max_groups[class]--;
1928 p = reg_class_superclasses[class];
1929 while (*p != LIM_REG_CLASSES)
1931 if (group_size [(int) *p]
1932 <= group_size [class])
1933 max_groups[(int) *p]--;
1940 /* We couldn't find any registers for this reload.
1941 Avoid going into an infinite loop. */
1942 if (i >= FIRST_PSEUDO_REGISTER)
1944 /* There are no groups left. */
1945 spill_failure (max_groups_insn[class]);
1952 /* Now similarly satisfy all need for single registers. */
1954 while (max_needs[class] > 0 || max_nongroups[class] > 0)
1956 /* If we spilled enough regs, but they weren't counted
1957 against the non-group need, see if we can count them now.
1958 If so, we can avoid some actual spilling. */
1959 if (max_needs[class] <= 0 && max_nongroups[class] > 0)
1960 for (i = 0; i < n_spills; i++)
1961 if (TEST_HARD_REG_BIT (reg_class_contents[class],
1963 && !TEST_HARD_REG_BIT (counted_for_groups,
1965 && !TEST_HARD_REG_BIT (counted_for_nongroups,
1967 && max_nongroups[class] > 0)
1969 register enum reg_class *p;
1971 SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]);
1972 max_nongroups[class]--;
1973 p = reg_class_superclasses[class];
1974 while (*p != LIM_REG_CLASSES)
1975 max_nongroups[(int) *p++]--;
1977 if (max_needs[class] <= 0 && max_nongroups[class] <= 0)
1980 /* Consider the potential reload regs that aren't
1981 yet in use as reload regs, in order of preference.
1982 Find the most preferred one that's in this class. */
1984 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1985 if (potential_reload_regs[i] >= 0
1986 && TEST_HARD_REG_BIT (reg_class_contents[class],
1987 potential_reload_regs[i])
1988 /* If this reg will not be available for groups,
1989 pick one that does not foreclose possible groups.
1990 This is a kludge, and not very general,
1991 but it should be sufficient to make the 386 work,
1992 and the problem should not occur on machines with
1994 && (max_nongroups[class] == 0
1995 || possible_group_p (potential_reload_regs[i], max_groups)))
1998 /* If we couldn't get a register, try to get one even if we
1999 might foreclose possible groups. This may cause problems
2000 later, but that's better than aborting now, since it is
2001 possible that we will, in fact, be able to form the needed
2002 group even with this allocation. */
2004 if (i >= FIRST_PSEUDO_REGISTER
2005 && (asm_noperands (max_needs[class] > 0
2006 ? max_needs_insn[class]
2007 : max_nongroups_insn[class])
2009 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2010 if (potential_reload_regs[i] >= 0
2011 && TEST_HARD_REG_BIT (reg_class_contents[class],
2012 potential_reload_regs[i]))
2015 /* I should be the index in potential_reload_regs
2016 of the new reload reg we have found. */
2018 if (i >= FIRST_PSEUDO_REGISTER)
2020 /* There are no possible registers left to spill. */
2021 spill_failure (max_needs[class] > 0 ? max_needs_insn[class]
2022 : max_nongroups_insn[class]);
2028 |= new_spill_reg (i, class, max_needs, max_nongroups,
2034 /* If global-alloc was run, notify it of any register eliminations we have
2037 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2038 if (ep->can_eliminate)
2039 mark_elimination (ep->from, ep->to);
2041 /* Insert code to save and restore call-clobbered hard regs
2042 around calls. Tell if what mode to use so that we will process
2043 those insns in reload_as_needed if we have to. */
2045 if (caller_save_needed)
2046 save_call_clobbered_regs (num_eliminable ? QImode
2047 : caller_save_spill_class != NO_REGS ? HImode
2050 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
2051 If that insn didn't set the register (i.e., it copied the register to
2052 memory), just delete that insn instead of the equivalencing insn plus
2053 anything now dead. If we call delete_dead_insn on that insn, we may
2054 delete the insn that actually sets the register if the register die
2055 there and that is incorrect. */
2057 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2058 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0
2059 && GET_CODE (reg_equiv_init[i]) != NOTE)
2061 if (reg_set_p (regno_reg_rtx[i], PATTERN (reg_equiv_init[i])))
2062 delete_dead_insn (reg_equiv_init[i]);
2065 PUT_CODE (reg_equiv_init[i], NOTE);
2066 NOTE_SOURCE_FILE (reg_equiv_init[i]) = 0;
2067 NOTE_LINE_NUMBER (reg_equiv_init[i]) = NOTE_INSN_DELETED;
2071 /* Use the reload registers where necessary
2072 by generating move instructions to move the must-be-register
2073 values into or out of the reload registers. */
2075 if (something_needs_reloads || something_needs_elimination
2076 || (caller_save_needed && num_eliminable)
2077 || caller_save_spill_class != NO_REGS)
2078 reload_as_needed (first, global);
2080 /* If we were able to eliminate the frame pointer, show that it is no
2081 longer live at the start of any basic block. If it ls live by
2082 virtue of being in a pseudo, that pseudo will be marked live
2083 and hence the frame pointer will be known to be live via that
2086 if (! frame_pointer_needed)
2087 for (i = 0; i < n_basic_blocks; i++)
2088 CLEAR_REGNO_REG_SET (basic_block_live_at_start[i],
2089 HARD_FRAME_POINTER_REGNUM);
2091 /* Come here (with failure set nonzero) if we can't get enough spill regs
2092 and we decide not to abort about it. */
2095 reload_in_progress = 0;
2097 /* Now eliminate all pseudo regs by modifying them into
2098 their equivalent memory references.
2099 The REG-rtx's for the pseudos are modified in place,
2100 so all insns that used to refer to them now refer to memory.
2102 For a reg that has a reg_equiv_address, all those insns
2103 were changed by reloading so that no insns refer to it any longer;
2104 but the DECL_RTL of a variable decl may refer to it,
2105 and if so this causes the debugging info to mention the variable. */
2107 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2111 if (reg_equiv_mem[i])
2113 addr = XEXP (reg_equiv_mem[i], 0);
2114 in_struct = MEM_IN_STRUCT_P (reg_equiv_mem[i]);
2116 if (reg_equiv_address[i])
2117 addr = reg_equiv_address[i];
2120 if (reg_renumber[i] < 0)
2122 rtx reg = regno_reg_rtx[i];
2123 XEXP (reg, 0) = addr;
2124 REG_USERVAR_P (reg) = 0;
2125 MEM_IN_STRUCT_P (reg) = in_struct;
2126 PUT_CODE (reg, MEM);
2128 else if (reg_equiv_mem[i])
2129 XEXP (reg_equiv_mem[i], 0) = addr;
2133 #ifdef PRESERVE_DEATH_INFO_REGNO_P
2134 /* Make a pass over all the insns and remove death notes for things that
2135 are no longer registers or no longer die in the insn (e.g., an input
2136 and output pseudo being tied). */
2138 for (insn = first; insn; insn = NEXT_INSN (insn))
2139 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
2143 for (note = REG_NOTES (insn); note; note = next)
2145 next = XEXP (note, 1);
2146 if (REG_NOTE_KIND (note) == REG_DEAD
2147 && (GET_CODE (XEXP (note, 0)) != REG
2148 || reg_set_p (XEXP (note, 0), PATTERN (insn))))
2149 remove_note (insn, note);
2154 /* If we are doing stack checking, give a warning if this function's
2155 frame size is larger than we expect. */
2156 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
2158 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
2160 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2161 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
2162 size += UNITS_PER_WORD;
2164 if (size > STACK_CHECK_MAX_FRAME_SIZE)
2165 warning ("frame size too large for reliable stack checking");
2168 /* Indicate that we no longer have known memory locations or constants. */
2169 reg_equiv_constant = 0;
2170 reg_equiv_memory_loc = 0;
2173 free (real_known_ptr);
2178 free (scratch_list);
2181 free (scratch_block);
2184 CLEAR_HARD_REG_SET (used_spill_regs);
2185 for (i = 0; i < n_spills; i++)
2186 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
2191 /* Nonzero if, after spilling reg REGNO for non-groups,
2192 it will still be possible to find a group if we still need one. */
2195 possible_group_p (regno, max_groups)
2200 int class = (int) NO_REGS;
2202 for (i = 0; i < (int) N_REG_CLASSES; i++)
2203 if (max_groups[i] > 0)
2209 if (class == (int) NO_REGS)
2212 /* Consider each pair of consecutive registers. */
2213 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
2215 /* Ignore pairs that include reg REGNO. */
2216 if (i == regno || i + 1 == regno)
2219 /* Ignore pairs that are outside the class that needs the group.
2220 ??? Here we fail to handle the case where two different classes
2221 independently need groups. But this never happens with our
2222 current machine descriptions. */
2223 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
2224 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
2227 /* A pair of consecutive regs we can still spill does the trick. */
2228 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
2229 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2230 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
2233 /* A pair of one already spilled and one we can spill does it
2234 provided the one already spilled is not otherwise reserved. */
2235 if (spill_reg_order[i] < 0
2236 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2237 && spill_reg_order[i + 1] >= 0
2238 && ! TEST_HARD_REG_BIT (counted_for_groups, i + 1)
2239 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i + 1))
2241 if (spill_reg_order[i + 1] < 0
2242 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
2243 && spill_reg_order[i] >= 0
2244 && ! TEST_HARD_REG_BIT (counted_for_groups, i)
2245 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i))
2252 /* Count any groups of CLASS that can be formed from the registers recently
2256 count_possible_groups (group_size, group_mode, max_groups, class)
2258 enum machine_mode *group_mode;
2265 /* Now find all consecutive groups of spilled registers
2266 and mark each group off against the need for such groups.
2267 But don't count them against ordinary need, yet. */
2269 if (group_size[class] == 0)
2272 CLEAR_HARD_REG_SET (new);
2274 /* Make a mask of all the regs that are spill regs in class I. */
2275 for (i = 0; i < n_spills; i++)
2276 if (TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
2277 && ! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[i])
2278 && ! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
2279 SET_HARD_REG_BIT (new, spill_regs[i]);
2281 /* Find each consecutive group of them. */
2282 for (i = 0; i < FIRST_PSEUDO_REGISTER && max_groups[class] > 0; i++)
2283 if (TEST_HARD_REG_BIT (new, i)
2284 && i + group_size[class] <= FIRST_PSEUDO_REGISTER
2285 && HARD_REGNO_MODE_OK (i, group_mode[class]))
2287 for (j = 1; j < group_size[class]; j++)
2288 if (! TEST_HARD_REG_BIT (new, i + j))
2291 if (j == group_size[class])
2293 /* We found a group. Mark it off against this class's need for
2294 groups, and against each superclass too. */
2295 register enum reg_class *p;
2297 max_groups[class]--;
2298 p = reg_class_superclasses[class];
2299 while (*p != LIM_REG_CLASSES)
2301 if (group_size [(int) *p] <= group_size [class])
2302 max_groups[(int) *p]--;
2306 /* Don't count these registers again. */
2307 for (j = 0; j < group_size[class]; j++)
2308 SET_HARD_REG_BIT (counted_for_groups, i + j);
2311 /* Skip to the last reg in this group. When i is incremented above,
2312 it will then point to the first reg of the next possible group. */
2317 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2318 another mode that needs to be reloaded for the same register class CLASS.
2319 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2320 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2322 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2323 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2324 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2325 causes unnecessary failures on machines requiring alignment of register
2326 groups when the two modes are different sizes, because the larger mode has
2327 more strict alignment rules than the smaller mode. */
2330 modes_equiv_for_class_p (allocate_mode, other_mode, class)
2331 enum machine_mode allocate_mode, other_mode;
2332 enum reg_class class;
2335 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2337 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
2338 && HARD_REGNO_MODE_OK (regno, allocate_mode)
2339 && ! HARD_REGNO_MODE_OK (regno, other_mode))
2345 /* Handle the failure to find a register to spill.
2346 INSN should be one of the insns which needed this particular spill reg. */
2349 spill_failure (insn)
2352 if (asm_noperands (PATTERN (insn)) >= 0)
2353 error_for_asm (insn, "`asm' needs too many reloads");
2355 fatal_insn ("Unable to find a register to spill.", insn);
2358 /* Add a new register to the tables of available spill-registers
2359 (as well as spilling all pseudos allocated to the register).
2360 I is the index of this register in potential_reload_regs.
2361 CLASS is the regclass whose need is being satisfied.
2362 MAX_NEEDS and MAX_NONGROUPS are the vectors of needs,
2363 so that this register can count off against them.
2364 MAX_NONGROUPS is 0 if this register is part of a group.
2365 GLOBAL and DUMPFILE are the same as the args that `reload' got. */
2368 new_spill_reg (i, class, max_needs, max_nongroups, global, dumpfile)
2376 register enum reg_class *p;
2378 int regno = potential_reload_regs[i];
2380 if (i >= FIRST_PSEUDO_REGISTER)
2381 abort (); /* Caller failed to find any register. */
2383 if (fixed_regs[regno] || TEST_HARD_REG_BIT (forbidden_regs, regno))
2385 static char *reg_class_names[] = REG_CLASS_NAMES;
2386 fatal ("fixed or forbidden register %d (%s) was spilled for class %s.\n\
2387 This may be due to a compiler bug or to impossible asm\n\
2388 statements or clauses.", regno, reg_names[regno], reg_class_names[class]);
2391 /* Make reg REGNO an additional reload reg. */
2393 potential_reload_regs[i] = -1;
2394 spill_regs[n_spills] = regno;
2395 spill_reg_order[regno] = n_spills;
2397 fprintf (dumpfile, "Spilling reg %d.\n", spill_regs[n_spills]);
2399 /* Clear off the needs we just satisfied. */
2402 p = reg_class_superclasses[class];
2403 while (*p != LIM_REG_CLASSES)
2404 max_needs[(int) *p++]--;
2406 if (max_nongroups && max_nongroups[class] > 0)
2408 SET_HARD_REG_BIT (counted_for_nongroups, regno);
2409 max_nongroups[class]--;
2410 p = reg_class_superclasses[class];
2411 while (*p != LIM_REG_CLASSES)
2412 max_nongroups[(int) *p++]--;
2415 /* Spill every pseudo reg that was allocated to this reg
2416 or to something that overlaps this reg. */
2418 val = spill_hard_reg (spill_regs[n_spills], global, dumpfile, 0);
2420 /* If there are some registers still to eliminate and this register
2421 wasn't ever used before, additional stack space may have to be
2422 allocated to store this register. Thus, we may have changed the offset
2423 between the stack and frame pointers, so mark that something has changed.
2424 (If new pseudos were spilled, thus requiring more space, VAL would have
2425 been set non-zero by the call to spill_hard_reg above since additional
2426 reloads may be needed in that case.
2428 One might think that we need only set VAL to 1 if this is a call-used
2429 register. However, the set of registers that must be saved by the
2430 prologue is not identical to the call-used set. For example, the
2431 register used by the call insn for the return PC is a call-used register,
2432 but must be saved by the prologue. */
2433 if (num_eliminable && ! regs_ever_live[spill_regs[n_spills]])
2436 regs_ever_live[spill_regs[n_spills]] = 1;
2442 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2443 data that is dead in INSN. */
2446 delete_dead_insn (insn)
2449 rtx prev = prev_real_insn (insn);
2452 /* If the previous insn sets a register that dies in our insn, delete it
2454 if (prev && GET_CODE (PATTERN (prev)) == SET
2455 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2456 && reg_mentioned_p (prev_dest, PATTERN (insn))
2457 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)))
2458 delete_dead_insn (prev);
2460 PUT_CODE (insn, NOTE);
2461 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2462 NOTE_SOURCE_FILE (insn) = 0;
2465 /* Modify the home of pseudo-reg I.
2466 The new home is present in reg_renumber[I].
2468 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2469 or it may be -1, meaning there is none or it is not relevant.
2470 This is used so that all pseudos spilled from a given hard reg
2471 can share one stack slot. */
2474 alter_reg (i, from_reg)
2478 /* When outputting an inline function, this can happen
2479 for a reg that isn't actually used. */
2480 if (regno_reg_rtx[i] == 0)
2483 /* If the reg got changed to a MEM at rtl-generation time,
2485 if (GET_CODE (regno_reg_rtx[i]) != REG)
2488 /* Modify the reg-rtx to contain the new hard reg
2489 number or else to contain its pseudo reg number. */
2490 REGNO (regno_reg_rtx[i])
2491 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2493 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2494 allocate a stack slot for it. */
2496 if (reg_renumber[i] < 0
2497 && REG_N_REFS (i) > 0
2498 && reg_equiv_constant[i] == 0
2499 && reg_equiv_memory_loc[i] == 0)
2502 int inherent_size = PSEUDO_REGNO_BYTES (i);
2503 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2506 /* Each pseudo reg has an inherent size which comes from its own mode,
2507 and a total size which provides room for paradoxical subregs
2508 which refer to the pseudo reg in wider modes.
2510 We can use a slot already allocated if it provides both
2511 enough inherent space and enough total space.
2512 Otherwise, we allocate a new slot, making sure that it has no less
2513 inherent space, and no less total space, then the previous slot. */
2516 /* No known place to spill from => no slot to reuse. */
2517 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
2518 inherent_size == total_size ? 0 : -1);
2519 if (BYTES_BIG_ENDIAN)
2520 /* Cancel the big-endian correction done in assign_stack_local.
2521 Get the address of the beginning of the slot.
2522 This is so we can do a big-endian correction unconditionally
2524 adjust = inherent_size - total_size;
2526 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2528 /* Reuse a stack slot if possible. */
2529 else if (spill_stack_slot[from_reg] != 0
2530 && spill_stack_slot_width[from_reg] >= total_size
2531 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2533 x = spill_stack_slot[from_reg];
2534 /* Allocate a bigger slot. */
2537 /* Compute maximum size needed, both for inherent size
2538 and for total size. */
2539 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2541 if (spill_stack_slot[from_reg])
2543 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2545 mode = GET_MODE (spill_stack_slot[from_reg]);
2546 if (spill_stack_slot_width[from_reg] > total_size)
2547 total_size = spill_stack_slot_width[from_reg];
2549 /* Make a slot with that size. */
2550 x = assign_stack_local (mode, total_size,
2551 inherent_size == total_size ? 0 : -1);
2553 if (BYTES_BIG_ENDIAN)
2555 /* Cancel the big-endian correction done in assign_stack_local.
2556 Get the address of the beginning of the slot.
2557 This is so we can do a big-endian correction unconditionally
2559 adjust = GET_MODE_SIZE (mode) - total_size;
2561 stack_slot = gen_rtx (MEM, mode_for_size (total_size
2564 plus_constant (XEXP (x, 0), adjust));
2566 spill_stack_slot[from_reg] = stack_slot;
2567 spill_stack_slot_width[from_reg] = total_size;
2570 /* On a big endian machine, the "address" of the slot
2571 is the address of the low part that fits its inherent mode. */
2572 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2573 adjust += (total_size - inherent_size);
2575 /* If we have any adjustment to make, or if the stack slot is the
2576 wrong mode, make a new stack slot. */
2577 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2579 x = gen_rtx (MEM, GET_MODE (regno_reg_rtx[i]),
2580 plus_constant (XEXP (x, 0), adjust));
2581 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2584 /* Save the stack slot for later. */
2585 reg_equiv_memory_loc[i] = x;
2589 /* Mark the slots in regs_ever_live for the hard regs
2590 used by pseudo-reg number REGNO. */
2593 mark_home_live (regno)
2596 register int i, lim;
2597 i = reg_renumber[regno];
2600 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2602 regs_ever_live[i++] = 1;
2605 /* Mark the registers used in SCRATCH as being live. */
2608 mark_scratch_live (scratch)
2612 int regno = REGNO (scratch);
2613 int lim = regno + HARD_REGNO_NREGS (regno, GET_MODE (scratch));
2615 for (i = regno; i < lim; i++)
2616 regs_ever_live[i] = 1;
2619 /* This function handles the tracking of elimination offsets around branches.
2621 X is a piece of RTL being scanned.
2623 INSN is the insn that it came from, if any.
2625 INITIAL_P is non-zero if we are to set the offset to be the initial
2626 offset and zero if we are setting the offset of the label to be the
2630 set_label_offsets (x, insn, initial_p)
2635 enum rtx_code code = GET_CODE (x);
2638 struct elim_table *p;
2643 if (LABEL_REF_NONLOCAL_P (x))
2648 /* ... fall through ... */
2651 /* If we know nothing about this label, set the desired offsets. Note
2652 that this sets the offset at a label to be the offset before a label
2653 if we don't know anything about the label. This is not correct for
2654 the label after a BARRIER, but is the best guess we can make. If
2655 we guessed wrong, we will suppress an elimination that might have
2656 been possible had we been able to guess correctly. */
2658 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2660 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2661 offsets_at[CODE_LABEL_NUMBER (x)][i]
2662 = (initial_p ? reg_eliminate[i].initial_offset
2663 : reg_eliminate[i].offset);
2664 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2667 /* Otherwise, if this is the definition of a label and it is
2668 preceded by a BARRIER, set our offsets to the known offset of
2672 && (tem = prev_nonnote_insn (insn)) != 0
2673 && GET_CODE (tem) == BARRIER)
2675 num_not_at_initial_offset = 0;
2676 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2678 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
2679 = offsets_at[CODE_LABEL_NUMBER (x)][i];
2680 if (reg_eliminate[i].can_eliminate
2681 && (reg_eliminate[i].offset
2682 != reg_eliminate[i].initial_offset))
2683 num_not_at_initial_offset++;
2688 /* If neither of the above cases is true, compare each offset
2689 with those previously recorded and suppress any eliminations
2690 where the offsets disagree. */
2692 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2693 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2694 != (initial_p ? reg_eliminate[i].initial_offset
2695 : reg_eliminate[i].offset))
2696 reg_eliminate[i].can_eliminate = 0;
2701 set_label_offsets (PATTERN (insn), insn, initial_p);
2703 /* ... fall through ... */
2707 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2708 and hence must have all eliminations at their initial offsets. */
2709 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2710 if (REG_NOTE_KIND (tem) == REG_LABEL)
2711 set_label_offsets (XEXP (tem, 0), insn, 1);
2716 /* Each of the labels in the address vector must be at their initial
2717 offsets. We want the first first for ADDR_VEC and the second
2718 field for ADDR_DIFF_VEC. */
2720 for (i = 0; i < XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2721 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2726 /* We only care about setting PC. If the source is not RETURN,
2727 IF_THEN_ELSE, or a label, disable any eliminations not at
2728 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2729 isn't one of those possibilities. For branches to a label,
2730 call ourselves recursively.
2732 Note that this can disable elimination unnecessarily when we have
2733 a non-local goto since it will look like a non-constant jump to
2734 someplace in the current function. This isn't a significant
2735 problem since such jumps will normally be when all elimination
2736 pairs are back to their initial offsets. */
2738 if (SET_DEST (x) != pc_rtx)
2741 switch (GET_CODE (SET_SRC (x)))
2748 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2752 tem = XEXP (SET_SRC (x), 1);
2753 if (GET_CODE (tem) == LABEL_REF)
2754 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2755 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2758 tem = XEXP (SET_SRC (x), 2);
2759 if (GET_CODE (tem) == LABEL_REF)
2760 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2761 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2769 /* If we reach here, all eliminations must be at their initial
2770 offset because we are doing a jump to a variable address. */
2771 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2772 if (p->offset != p->initial_offset)
2773 p->can_eliminate = 0;
2781 /* Used for communication between the next two function to properly share
2782 the vector for an ASM_OPERANDS. */
2784 static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2786 /* Scan X and replace any eliminable registers (such as fp) with a
2787 replacement (such as sp), plus an offset.
2789 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2790 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2791 MEM, we are allowed to replace a sum of a register and the constant zero
2792 with the register, which we cannot do outside a MEM. In addition, we need
2793 to record the fact that a register is referenced outside a MEM.
2795 If INSN is an insn, it is the insn containing X. If we replace a REG
2796 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2797 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2798 that the REG is being modified.
2800 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2801 That's used when we eliminate in expressions stored in notes.
2802 This means, do not set ref_outside_mem even if the reference
2805 If we see a modification to a register we know about, take the
2806 appropriate action (see case SET, below).
2808 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2809 replacements done assuming all offsets are at their initial values. If
2810 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2811 encounter, return the actual location so that find_reloads will do
2812 the proper thing. */
2815 eliminate_regs (x, mem_mode, insn, storing)
2817 enum machine_mode mem_mode;
2821 enum rtx_code code = GET_CODE (x);
2822 struct elim_table *ep;
2845 /* This is only for the benefit of the debugging backends, which call
2846 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2847 removed after CSE. */
2848 new = eliminate_regs (XEXP (x, 0), 0, insn, 0);
2849 if (GET_CODE (new) == MEM)
2850 return XEXP (new, 0);
2856 /* First handle the case where we encounter a bare register that
2857 is eliminable. Replace it with a PLUS. */
2858 if (regno < FIRST_PSEUDO_REGISTER)
2860 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2862 if (ep->from_rtx == x && ep->can_eliminate)
2865 /* Refs inside notes don't count for this purpose. */
2866 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2867 || GET_CODE (insn) == INSN_LIST)))
2868 ep->ref_outside_mem = 1;
2869 return plus_constant (ep->to_rtx, ep->previous_offset);
2873 else if (reg_equiv_memory_loc && reg_equiv_memory_loc[regno]
2874 && (reg_equiv_address[regno] || num_not_at_initial_offset))
2876 /* In this case, find_reloads would attempt to either use an
2877 incorrect address (if something is not at its initial offset)
2878 or substitute an replaced address into an insn (which loses
2879 if the offset is changed by some later action). So we simply
2880 return the replaced stack slot (assuming it is changed by
2881 elimination) and ignore the fact that this is actually a
2882 reference to the pseudo. Ensure we make a copy of the
2883 address in case it is shared. */
2884 new = eliminate_regs (reg_equiv_memory_loc[regno],
2886 if (new != reg_equiv_memory_loc[regno])
2888 cannot_omit_stores[regno] = 1;
2889 return copy_rtx (new);
2895 /* If this is the sum of an eliminable register and a constant, rework
2897 if (GET_CODE (XEXP (x, 0)) == REG
2898 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2899 && CONSTANT_P (XEXP (x, 1)))
2901 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2903 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2906 /* Refs inside notes don't count for this purpose. */
2907 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2908 || GET_CODE (insn) == INSN_LIST)))
2909 ep->ref_outside_mem = 1;
2911 /* The only time we want to replace a PLUS with a REG (this
2912 occurs when the constant operand of the PLUS is the negative
2913 of the offset) is when we are inside a MEM. We won't want
2914 to do so at other times because that would change the
2915 structure of the insn in a way that reload can't handle.
2916 We special-case the commonest situation in
2917 eliminate_regs_in_insn, so just replace a PLUS with a
2918 PLUS here, unless inside a MEM. */
2919 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2920 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2923 return gen_rtx (PLUS, Pmode, ep->to_rtx,
2924 plus_constant (XEXP (x, 1),
2925 ep->previous_offset));
2928 /* If the register is not eliminable, we are done since the other
2929 operand is a constant. */
2933 /* If this is part of an address, we want to bring any constant to the
2934 outermost PLUS. We will do this by doing register replacement in
2935 our operands and seeing if a constant shows up in one of them.
2937 We assume here this is part of an address (or a "load address" insn)
2938 since an eliminable register is not likely to appear in any other
2941 If we have (plus (eliminable) (reg)), we want to produce
2942 (plus (plus (replacement) (reg) (const))). If this was part of a
2943 normal add insn, (plus (replacement) (reg)) will be pushed as a
2944 reload. This is the desired action. */
2947 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn, 0);
2948 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn, 0);
2950 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2952 /* If one side is a PLUS and the other side is a pseudo that
2953 didn't get a hard register but has a reg_equiv_constant,
2954 we must replace the constant here since it may no longer
2955 be in the position of any operand. */
2956 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2957 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2958 && reg_renumber[REGNO (new1)] < 0
2959 && reg_equiv_constant != 0
2960 && reg_equiv_constant[REGNO (new1)] != 0)
2961 new1 = reg_equiv_constant[REGNO (new1)];
2962 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2963 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2964 && reg_renumber[REGNO (new0)] < 0
2965 && reg_equiv_constant[REGNO (new0)] != 0)
2966 new0 = reg_equiv_constant[REGNO (new0)];
2968 new = form_sum (new0, new1);
2970 /* As above, if we are not inside a MEM we do not want to
2971 turn a PLUS into something else. We might try to do so here
2972 for an addition of 0 if we aren't optimizing. */
2973 if (! mem_mode && GET_CODE (new) != PLUS)
2974 return gen_rtx (PLUS, GET_MODE (x), new, const0_rtx);
2982 /* If this is the product of an eliminable register and a
2983 constant, apply the distribute law and move the constant out
2984 so that we have (plus (mult ..) ..). This is needed in order
2985 to keep load-address insns valid. This case is pathological.
2986 We ignore the possibility of overflow here. */
2987 if (GET_CODE (XEXP (x, 0)) == REG
2988 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2989 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2990 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2992 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2995 /* Refs inside notes don't count for this purpose. */
2996 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2997 || GET_CODE (insn) == INSN_LIST)))
2998 ep->ref_outside_mem = 1;
3001 plus_constant (gen_rtx (MULT, Pmode, ep->to_rtx, XEXP (x, 1)),
3002 ep->previous_offset * INTVAL (XEXP (x, 1)));
3005 /* ... fall through ... */
3010 case DIV: case UDIV:
3011 case MOD: case UMOD:
3012 case AND: case IOR: case XOR:
3013 case ROTATERT: case ROTATE:
3014 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
3016 case GE: case GT: case GEU: case GTU:
3017 case LE: case LT: case LEU: case LTU:
3019 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn, 0);
3021 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn, 0) : 0;
3023 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
3024 return gen_rtx (code, GET_MODE (x), new0, new1);
3029 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
3032 new = eliminate_regs (XEXP (x, 0), mem_mode, insn, 0);
3033 if (new != XEXP (x, 0))
3034 x = gen_rtx (EXPR_LIST, REG_NOTE_KIND (x), new, XEXP (x, 1));
3037 /* ... fall through ... */
3040 /* Now do eliminations in the rest of the chain. If this was
3041 an EXPR_LIST, this might result in allocating more memory than is
3042 strictly needed, but it simplifies the code. */
3045 new = eliminate_regs (XEXP (x, 1), mem_mode, insn, 0);
3046 if (new != XEXP (x, 1))
3047 return gen_rtx (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
3055 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3056 if (ep->to_rtx == XEXP (x, 0))
3058 int size = GET_MODE_SIZE (mem_mode);
3060 /* If more bytes than MEM_MODE are pushed, account for them. */
3061 #ifdef PUSH_ROUNDING
3062 if (ep->to_rtx == stack_pointer_rtx)
3063 size = PUSH_ROUNDING (size);
3065 if (code == PRE_DEC || code == POST_DEC)
3071 /* Fall through to generic unary operation case. */
3072 case STRICT_LOW_PART:
3074 case SIGN_EXTEND: case ZERO_EXTEND:
3075 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3076 case FLOAT: case FIX:
3077 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3081 new = eliminate_regs (XEXP (x, 0), mem_mode, insn, 0);
3082 if (new != XEXP (x, 0))
3083 return gen_rtx (code, GET_MODE (x), new);
3087 /* Similar to above processing, but preserve SUBREG_WORD.
3088 Convert (subreg (mem)) to (mem) if not paradoxical.
3089 Also, if we have a non-paradoxical (subreg (pseudo)) and the
3090 pseudo didn't get a hard reg, we must replace this with the
3091 eliminated version of the memory location because push_reloads
3092 may do the replacement in certain circumstances. */
3093 if (GET_CODE (SUBREG_REG (x)) == REG
3094 && (GET_MODE_SIZE (GET_MODE (x))
3095 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3096 && reg_equiv_memory_loc != 0
3097 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
3099 new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
3102 /* If we didn't change anything, we must retain the pseudo. */
3103 if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
3104 new = SUBREG_REG (x);
3107 /* Otherwise, ensure NEW isn't shared in case we have to reload
3109 new = copy_rtx (new);
3111 /* In this case, we must show that the pseudo is used in this
3112 insn so that delete_output_reload will do the right thing. */
3113 if (insn != 0 && GET_CODE (insn) != EXPR_LIST
3114 && GET_CODE (insn) != INSN_LIST)
3115 emit_insn_before (gen_rtx (USE, VOIDmode, SUBREG_REG (x)),
3120 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn, 0);
3122 if (new != XEXP (x, 0))
3124 int x_size = GET_MODE_SIZE (GET_MODE (x));
3125 int new_size = GET_MODE_SIZE (GET_MODE (new));
3127 /* When asked to spill a partial word subreg, we need to go
3128 ahead and spill the whole thing against the possibility
3129 that we reload the whole reg and find garbage at the top. */
3131 && GET_CODE (new) == MEM
3132 && x_size < new_size
3133 && ((x_size + UNITS_PER_WORD-1) / UNITS_PER_WORD
3134 == (new_size + UNITS_PER_WORD-1) / UNITS_PER_WORD))
3136 else if (GET_CODE (new) == MEM
3137 && x_size <= new_size
3138 #ifdef LOAD_EXTEND_OP
3139 /* On these machines we will be reloading what is
3140 inside the SUBREG if it originally was a pseudo and
3141 the inner and outer modes are both a word or
3142 smaller. So leave the SUBREG then. */
3143 && ! (GET_CODE (SUBREG_REG (x)) == REG
3144 && x_size <= UNITS_PER_WORD
3145 && new_size <= UNITS_PER_WORD
3146 && x_size > new_size
3147 && INTEGRAL_MODE_P (GET_MODE (new))
3148 && LOAD_EXTEND_OP (GET_MODE (new)) != NIL)
3152 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
3153 enum machine_mode mode = GET_MODE (x);
3155 if (BYTES_BIG_ENDIAN)
3156 offset += (MIN (UNITS_PER_WORD,
3157 GET_MODE_SIZE (GET_MODE (new)))
3158 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
3160 PUT_MODE (new, mode);
3161 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
3165 return gen_rtx (SUBREG, GET_MODE (x), new, SUBREG_WORD (x));
3171 /* If using a register that is the source of an eliminate we still
3172 think can be performed, note it cannot be performed since we don't
3173 know how this register is used. */
3174 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3175 if (ep->from_rtx == XEXP (x, 0))
3176 ep->can_eliminate = 0;
3178 new = eliminate_regs (XEXP (x, 0), mem_mode, insn, 0);
3179 if (new != XEXP (x, 0))
3180 return gen_rtx (code, GET_MODE (x), new);
3184 /* If clobbering a register that is the replacement register for an
3185 elimination we still think can be performed, note that it cannot
3186 be performed. Otherwise, we need not be concerned about it. */
3187 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3188 if (ep->to_rtx == XEXP (x, 0))
3189 ep->can_eliminate = 0;
3191 new = eliminate_regs (XEXP (x, 0), mem_mode, insn, 0);
3192 if (new != XEXP (x, 0))
3193 return gen_rtx (code, GET_MODE (x), new);
3199 /* Properly handle sharing input and constraint vectors. */
3200 if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
3202 /* When we come to a new vector not seen before,
3203 scan all its elements; keep the old vector if none
3204 of them changes; otherwise, make a copy. */
3205 old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
3206 temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
3207 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3208 temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
3211 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3212 if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
3215 if (i == ASM_OPERANDS_INPUT_LENGTH (x))
3216 new_asm_operands_vec = old_asm_operands_vec;
3218 new_asm_operands_vec
3219 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
3222 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
3223 if (new_asm_operands_vec == old_asm_operands_vec)
3226 new = gen_rtx (ASM_OPERANDS, VOIDmode, ASM_OPERANDS_TEMPLATE (x),
3227 ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
3228 ASM_OPERANDS_OUTPUT_IDX (x), new_asm_operands_vec,
3229 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
3230 ASM_OPERANDS_SOURCE_FILE (x),
3231 ASM_OPERANDS_SOURCE_LINE (x));
3232 new->volatil = x->volatil;
3237 /* Check for setting a register that we know about. */
3238 if (GET_CODE (SET_DEST (x)) == REG)
3240 /* See if this is setting the replacement register for an
3243 If DEST is the hard frame pointer, we do nothing because we
3244 assume that all assignments to the frame pointer are for
3245 non-local gotos and are being done at a time when they are valid
3246 and do not disturb anything else. Some machines want to
3247 eliminate a fake argument pointer (or even a fake frame pointer)
3248 with either the real frame or the stack pointer. Assignments to
3249 the hard frame pointer must not prevent this elimination. */
3251 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3253 if (ep->to_rtx == SET_DEST (x)
3254 && SET_DEST (x) != hard_frame_pointer_rtx)
3256 /* If it is being incremented, adjust the offset. Otherwise,
3257 this elimination can't be done. */
3258 rtx src = SET_SRC (x);
3260 if (GET_CODE (src) == PLUS
3261 && XEXP (src, 0) == SET_DEST (x)
3262 && GET_CODE (XEXP (src, 1)) == CONST_INT)
3263 ep->offset -= INTVAL (XEXP (src, 1));
3265 ep->can_eliminate = 0;
3268 /* Now check to see we are assigning to a register that can be
3269 eliminated. If so, it must be as part of a PARALLEL, since we
3270 will not have been called if this is a single SET. So indicate
3271 that we can no longer eliminate this reg. */
3272 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3274 if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
3275 ep->can_eliminate = 0;
3278 /* Now avoid the loop below in this common case. */
3280 rtx new0 = eliminate_regs (SET_DEST (x), 0, insn, 1);
3281 rtx new1 = eliminate_regs (SET_SRC (x), 0, insn, 0);
3283 /* If SET_DEST changed from a REG to a MEM and INSN is an insn,
3284 write a CLOBBER insn. */
3285 if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
3286 && insn != 0 && GET_CODE (insn) != EXPR_LIST
3287 && GET_CODE (insn) != INSN_LIST)
3288 emit_insn_after (gen_rtx (CLOBBER, VOIDmode, SET_DEST (x)), insn);
3290 /* If SET_DEST was a partial-word subreg, NEW0 may have been widened
3291 to spill the entire register (see SUBREG case above). If the
3292 widths of SET_DEST and NEW0 no longer match, adjust NEW1. */
3293 if (GET_MODE (SET_DEST (x)) != GET_MODE (new0))
3294 new1 = gen_rtx (SUBREG, GET_MODE (new0), new1, 0);
3296 if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
3297 return gen_rtx (SET, VOIDmode, new0, new1);
3303 /* This is only for the benefit of the debugging backends, which call
3304 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
3305 removed after CSE. */
3306 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
3307 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn, 0);
3309 /* Our only special processing is to pass the mode of the MEM to our
3310 recursive call and copy the flags. While we are here, handle this
3311 case more efficiently. */
3312 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn, 0);
3313 if (new != XEXP (x, 0))
3315 new = gen_rtx (MEM, GET_MODE (x), new);
3316 new->volatil = x->volatil;
3317 new->unchanging = x->unchanging;
3318 new->in_struct = x->in_struct;
3328 /* Process each of our operands recursively. If any have changed, make a
3330 fmt = GET_RTX_FORMAT (code);
3331 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3335 new = eliminate_regs (XEXP (x, i), mem_mode, insn, 0);
3336 if (new != XEXP (x, i) && ! copied)
3338 rtx new_x = rtx_alloc (code);
3339 bcopy ((char *) x, (char *) new_x,
3340 (sizeof (*new_x) - sizeof (new_x->fld)
3341 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
3347 else if (*fmt == 'E')
3350 for (j = 0; j < XVECLEN (x, i); j++)
3352 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn, 0);
3353 if (new != XVECEXP (x, i, j) && ! copied_vec)
3355 rtvec new_v = gen_rtvec_vv (XVECLEN (x, i),
3359 rtx new_x = rtx_alloc (code);
3360 bcopy ((char *) x, (char *) new_x,
3361 (sizeof (*new_x) - sizeof (new_x->fld)
3362 + (sizeof (new_x->fld[0])
3363 * GET_RTX_LENGTH (code))));
3367 XVEC (x, i) = new_v;
3370 XVECEXP (x, i, j) = new;
3378 /* Scan INSN and eliminate all eliminable registers in it.
3380 If REPLACE is nonzero, do the replacement destructively. Also
3381 delete the insn as dead it if it is setting an eliminable register.
3383 If REPLACE is zero, do all our allocations in reload_obstack.
3385 If no eliminations were done and this insn doesn't require any elimination
3386 processing (these are not identical conditions: it might be updating sp,
3387 but not referencing fp; this needs to be seen during reload_as_needed so
3388 that the offset between fp and sp can be taken into consideration), zero
3389 is returned. Otherwise, 1 is returned. */
3392 eliminate_regs_in_insn (insn, replace)
3396 rtx old_body = PATTERN (insn);
3397 rtx old_set = single_set (insn);
3400 struct elim_table *ep;
3403 push_obstacks (&reload_obstack, &reload_obstack);
3405 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
3406 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3408 /* Check for setting an eliminable register. */
3409 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3410 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3412 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3413 /* If this is setting the frame pointer register to the
3414 hardware frame pointer register and this is an elimination
3415 that will be done (tested above), this insn is really
3416 adjusting the frame pointer downward to compensate for
3417 the adjustment done before a nonlocal goto. */
3418 if (ep->from == FRAME_POINTER_REGNUM
3419 && ep->to == HARD_FRAME_POINTER_REGNUM)
3421 rtx src = SET_SRC (old_set);
3423 rtx prev_insn, prev_set;
3425 if (src == ep->to_rtx)
3427 else if (GET_CODE (src) == PLUS
3428 && GET_CODE (XEXP (src, 0)) == CONST_INT)
3429 offset = INTVAL (XEXP (src, 0)), ok = 1;
3430 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
3431 && (prev_set = single_set (prev_insn)) != 0
3432 && rtx_equal_p (SET_DEST (prev_set), src))
3434 src = SET_SRC (prev_set);
3435 if (src == ep->to_rtx)
3437 else if (GET_CODE (src) == PLUS
3438 && GET_CODE (XEXP (src, 0)) == CONST_INT
3439 && XEXP (src, 1) == ep->to_rtx)
3440 offset = INTVAL (XEXP (src, 0)), ok = 1;
3441 else if (GET_CODE (src) == PLUS
3442 && GET_CODE (XEXP (src, 1)) == CONST_INT
3443 && XEXP (src, 0) == ep->to_rtx)
3444 offset = INTVAL (XEXP (src, 1)), ok = 1;
3452 = plus_constant (ep->to_rtx, offset - ep->offset);
3454 /* First see if this insn remains valid when we
3455 make the change. If not, keep the INSN_CODE
3456 the same and let reload fit it up. */
3457 validate_change (insn, &SET_SRC (old_set), src, 1);
3458 validate_change (insn, &SET_DEST (old_set),
3460 if (! apply_change_group ())
3462 SET_SRC (old_set) = src;
3463 SET_DEST (old_set) = ep->to_rtx;
3473 /* In this case this insn isn't serving a useful purpose. We
3474 will delete it in reload_as_needed once we know that this
3475 elimination is, in fact, being done.
3477 If REPLACE isn't set, we can't delete this insn, but needn't
3478 process it since it won't be used unless something changes. */
3480 delete_dead_insn (insn);
3485 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3486 in the insn is the negative of the offset in FROM. Substitute
3487 (set (reg) (reg to)) for the insn and change its code.
3489 We have to do this here, rather than in eliminate_regs, do that we can
3490 change the insn code. */
3492 if (GET_CODE (SET_SRC (old_set)) == PLUS
3493 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3494 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT)
3495 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3497 if (ep->from_rtx == XEXP (SET_SRC (old_set), 0)
3498 && ep->can_eliminate)
3500 /* We must stop at the first elimination that will be used.
3501 If this one would replace the PLUS with a REG, do it
3502 now. Otherwise, quit the loop and let eliminate_regs
3503 do its normal replacement. */
3504 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_set), 1)))
3506 /* We assume here that we don't need a PARALLEL of
3507 any CLOBBERs for this assignment. There's not
3508 much we can do if we do need it. */
3509 PATTERN (insn) = gen_rtx (SET, VOIDmode,
3510 SET_DEST (old_set), ep->to_rtx);
3511 INSN_CODE (insn) = -1;
3520 old_asm_operands_vec = 0;
3522 /* Replace the body of this insn with a substituted form. If we changed
3523 something, return non-zero.
3525 If we are replacing a body that was a (set X (plus Y Z)), try to
3526 re-recognize the insn. We do this in case we had a simple addition
3527 but now can do this as a load-address. This saves an insn in this
3530 new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX, 0);
3531 if (new_body != old_body)
3533 /* If we aren't replacing things permanently and we changed something,
3534 make another copy to ensure that all the RTL is new. Otherwise
3535 things can go wrong if find_reload swaps commutative operands
3536 and one is inside RTL that has been copied while the other is not. */
3538 /* Don't copy an asm_operands because (1) there's no need and (2)
3539 copy_rtx can't do it properly when there are multiple outputs. */
3540 if (! replace && asm_noperands (old_body) < 0)
3541 new_body = copy_rtx (new_body);
3543 /* If we had a move insn but now we don't, rerecognize it. This will
3544 cause spurious re-recognition if the old move had a PARALLEL since
3545 the new one still will, but we can't call single_set without
3546 having put NEW_BODY into the insn and the re-recognition won't
3547 hurt in this rare case. */
3549 && ((GET_CODE (SET_SRC (old_set)) == REG
3550 && (GET_CODE (new_body) != SET
3551 || GET_CODE (SET_SRC (new_body)) != REG))
3552 /* If this was a load from or store to memory, compare
3553 the MEM in recog_operand to the one in the insn. If they
3554 are not equal, then rerecognize the insn. */
3556 && ((GET_CODE (SET_SRC (old_set)) == MEM
3557 && SET_SRC (old_set) != recog_operand[1])
3558 || (GET_CODE (SET_DEST (old_set)) == MEM
3559 && SET_DEST (old_set) != recog_operand[0])))
3560 /* If this was an add insn before, rerecognize. */
3561 || GET_CODE (SET_SRC (old_set)) == PLUS))
3563 if (! validate_change (insn, &PATTERN (insn), new_body, 0))
3564 /* If recognition fails, store the new body anyway.
3565 It's normal to have recognition failures here
3566 due to bizarre memory addresses; reloading will fix them. */
3567 PATTERN (insn) = new_body;
3570 PATTERN (insn) = new_body;
3575 /* Loop through all elimination pairs. See if any have changed and
3576 recalculate the number not at initial offset.
3578 Compute the maximum offset (minimum offset if the stack does not
3579 grow downward) for each elimination pair.
3581 We also detect a cases where register elimination cannot be done,
3582 namely, if a register would be both changed and referenced outside a MEM
3583 in the resulting insn since such an insn is often undefined and, even if
3584 not, we cannot know what meaning will be given to it. Note that it is
3585 valid to have a register used in an address in an insn that changes it
3586 (presumably with a pre- or post-increment or decrement).
3588 If anything changes, return nonzero. */
3590 num_not_at_initial_offset = 0;
3591 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3593 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3594 ep->can_eliminate = 0;
3596 ep->ref_outside_mem = 0;
3598 if (ep->previous_offset != ep->offset)
3601 ep->previous_offset = ep->offset;
3602 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3603 num_not_at_initial_offset++;
3605 #ifdef STACK_GROWS_DOWNWARD
3606 ep->max_offset = MAX (ep->max_offset, ep->offset);
3608 ep->max_offset = MIN (ep->max_offset, ep->offset);
3613 /* If we changed something, perform elimination in REG_NOTES. This is
3614 needed even when REPLACE is zero because a REG_DEAD note might refer
3615 to a register that we eliminate and could cause a different number
3616 of spill registers to be needed in the final reload pass than in
3618 if (val && REG_NOTES (insn) != 0)
3619 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn), 0);
3627 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3628 replacement we currently believe is valid, mark it as not eliminable if X
3629 modifies DEST in any way other than by adding a constant integer to it.
3631 If DEST is the frame pointer, we do nothing because we assume that
3632 all assignments to the hard frame pointer are nonlocal gotos and are being
3633 done at a time when they are valid and do not disturb anything else.
3634 Some machines want to eliminate a fake argument pointer with either the
3635 frame or stack pointer. Assignments to the hard frame pointer must not
3636 prevent this elimination.
3638 Called via note_stores from reload before starting its passes to scan
3639 the insns of the function. */
3642 mark_not_eliminable (dest, x)
3648 /* A SUBREG of a hard register here is just changing its mode. We should
3649 not see a SUBREG of an eliminable hard register, but check just in
3651 if (GET_CODE (dest) == SUBREG)
3652 dest = SUBREG_REG (dest);
3654 if (dest == hard_frame_pointer_rtx)
3657 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3658 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3659 && (GET_CODE (x) != SET
3660 || GET_CODE (SET_SRC (x)) != PLUS
3661 || XEXP (SET_SRC (x), 0) != dest
3662 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3664 reg_eliminate[i].can_eliminate_previous
3665 = reg_eliminate[i].can_eliminate = 0;
3670 /* Kick all pseudos out of hard register REGNO.
3671 If GLOBAL is nonzero, try to find someplace else to put them.
3672 If DUMPFILE is nonzero, log actions taken on that file.
3674 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3675 because we found we can't eliminate some register. In the case, no pseudos
3676 are allowed to be in the register, even if they are only in a block that
3677 doesn't require spill registers, unlike the case when we are spilling this
3678 hard reg to produce another spill register.
3680 Return nonzero if any pseudos needed to be kicked out. */
3683 spill_hard_reg (regno, global, dumpfile, cant_eliminate)
3689 enum reg_class class = REGNO_REG_CLASS (regno);
3690 int something_changed = 0;
3693 SET_HARD_REG_BIT (forbidden_regs, regno);
3696 regs_ever_live[regno] = 1;
3698 /* Spill every pseudo reg that was allocated to this reg
3699 or to something that overlaps this reg. */
3701 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3702 if (reg_renumber[i] >= 0
3703 && reg_renumber[i] <= regno
3705 + HARD_REGNO_NREGS (reg_renumber[i],
3706 PSEUDO_REGNO_MODE (i))
3709 /* If this register belongs solely to a basic block which needed no
3710 spilling of any class that this register is contained in,
3711 leave it be, unless we are spilling this register because
3712 it was a hard register that can't be eliminated. */
3714 if (! cant_eliminate
3715 && basic_block_needs[0]
3716 && REG_BASIC_BLOCK (i) >= 0
3717 && basic_block_needs[(int) class][REG_BASIC_BLOCK (i)] == 0)
3721 for (p = reg_class_superclasses[(int) class];
3722 *p != LIM_REG_CLASSES; p++)
3723 if (basic_block_needs[(int) *p][REG_BASIC_BLOCK (i)] > 0)
3726 if (*p == LIM_REG_CLASSES)
3730 /* Mark it as no longer having a hard register home. */
3731 reg_renumber[i] = -1;
3732 /* We will need to scan everything again. */
3733 something_changed = 1;
3735 retry_global_alloc (i, forbidden_regs);
3737 alter_reg (i, regno);
3740 if (reg_renumber[i] == -1)
3741 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3743 fprintf (dumpfile, " Register %d now in %d.\n\n",
3744 i, reg_renumber[i]);
3747 for (i = 0; i < scratch_list_length; i++)
3749 if (scratch_list[i] && REGNO (scratch_list[i]) == regno)
3751 if (! cant_eliminate && basic_block_needs[0]
3752 && ! basic_block_needs[(int) class][scratch_block[i]])
3756 for (p = reg_class_superclasses[(int) class];
3757 *p != LIM_REG_CLASSES; p++)
3758 if (basic_block_needs[(int) *p][scratch_block[i]] > 0)
3761 if (*p == LIM_REG_CLASSES)
3764 PUT_CODE (scratch_list[i], SCRATCH);
3765 scratch_list[i] = 0;
3766 something_changed = 1;
3771 return something_changed;
3774 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3775 Also mark any hard registers used to store user variables as
3776 forbidden from being used for spill registers. */
3779 scan_paradoxical_subregs (x)
3784 register enum rtx_code code = GET_CODE (x);
3789 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3790 && REG_USERVAR_P (x))
3791 SET_HARD_REG_BIT (forbidden_regs, REGNO (x));
3806 if (GET_CODE (SUBREG_REG (x)) == REG
3807 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3808 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3809 = GET_MODE_SIZE (GET_MODE (x));
3816 fmt = GET_RTX_FORMAT (code);
3817 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3820 scan_paradoxical_subregs (XEXP (x, i));
3821 else if (fmt[i] == 'E')
3824 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3825 scan_paradoxical_subregs (XVECEXP (x, i, j));
3831 hard_reg_use_compare (p1p, p2p)
3832 const GENERIC_PTR p1p;
3833 const GENERIC_PTR p2p;
3835 struct hard_reg_n_uses *p1 = (struct hard_reg_n_uses *)p1p,
3836 *p2 = (struct hard_reg_n_uses *)p2p;
3837 int tem = p1->uses - p2->uses;
3838 if (tem != 0) return tem;
3839 /* If regs are equally good, sort by regno,
3840 so that the results of qsort leave nothing to chance. */
3841 return p1->regno - p2->regno;
3844 /* Choose the order to consider regs for use as reload registers
3845 based on how much trouble would be caused by spilling one.
3846 Store them in order of decreasing preference in potential_reload_regs. */
3849 order_regs_for_reload (global)
3856 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
3858 CLEAR_HARD_REG_SET (bad_spill_regs);
3860 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3861 potential_reload_regs[i] = -1;
3863 /* Count number of uses of each hard reg by pseudo regs allocated to it
3864 and then order them by decreasing use. */
3866 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3868 hard_reg_n_uses[i].uses = 0;
3869 hard_reg_n_uses[i].regno = i;
3872 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3874 int regno = reg_renumber[i];
3877 int lim = regno + HARD_REGNO_NREGS (regno, PSEUDO_REGNO_MODE (i));
3880 /* If allocated by local-alloc, show more uses since
3881 we're not going to be able to reallocate it, but
3882 we might if allocated by global alloc. */
3883 if (global && reg_allocno[i] < 0)
3884 hard_reg_n_uses[regno].uses += (REG_N_REFS (i) + 1) / 2;
3886 hard_reg_n_uses[regno++].uses += REG_N_REFS (i);
3889 large += REG_N_REFS (i);
3892 /* Now fixed registers (which cannot safely be used for reloading)
3893 get a very high use count so they will be considered least desirable.
3894 Registers used explicitly in the rtl code are almost as bad. */
3896 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3900 hard_reg_n_uses[i].uses += 2 * large + 2;
3901 SET_HARD_REG_BIT (bad_spill_regs, i);
3903 else if (regs_explicitly_used[i])
3905 hard_reg_n_uses[i].uses += large + 1;
3906 if (! SMALL_REGISTER_CLASSES)
3907 /* ??? We are doing this here because of the potential
3908 that bad code may be generated if a register explicitly
3909 used in an insn was used as a spill register for that
3910 insn. But not using these are spill registers may lose
3911 on some machine. We'll have to see how this works out. */
3912 SET_HARD_REG_BIT (bad_spill_regs, i);
3915 hard_reg_n_uses[HARD_FRAME_POINTER_REGNUM].uses += 2 * large + 2;
3916 SET_HARD_REG_BIT (bad_spill_regs, HARD_FRAME_POINTER_REGNUM);
3918 #ifdef ELIMINABLE_REGS
3919 /* If registers other than the frame pointer are eliminable, mark them as
3921 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3923 hard_reg_n_uses[reg_eliminate[i].from].uses += 2 * large + 2;
3924 SET_HARD_REG_BIT (bad_spill_regs, reg_eliminate[i].from);
3928 /* Prefer registers not so far used, for use in temporary loading.
3929 Among them, if REG_ALLOC_ORDER is defined, use that order.
3930 Otherwise, prefer registers not preserved by calls. */
3932 #ifdef REG_ALLOC_ORDER
3933 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3935 int regno = reg_alloc_order[i];
3937 if (hard_reg_n_uses[regno].uses == 0)
3938 potential_reload_regs[o++] = regno;
3941 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3943 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i])
3944 potential_reload_regs[o++] = i;
3946 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3948 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i])
3949 potential_reload_regs[o++] = i;
3953 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
3954 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
3956 /* Now add the regs that are already used,
3957 preferring those used less often. The fixed and otherwise forbidden
3958 registers will be at the end of this list. */
3960 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3961 if (hard_reg_n_uses[i].uses != 0)
3962 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
3965 /* Used in reload_as_needed to sort the spilled regs. */
3968 compare_spill_regs (r1p, r2p)
3969 const GENERIC_PTR r1p;
3970 const GENERIC_PTR r2p;
3972 short r1 = *(short *)r1p, r2 = *(short *)r2p;
3976 /* Reload pseudo-registers into hard regs around each insn as needed.
3977 Additional register load insns are output before the insn that needs it
3978 and perhaps store insns after insns that modify the reloaded pseudo reg.
3980 reg_last_reload_reg and reg_reloaded_contents keep track of
3981 which registers are already available in reload registers.
3982 We update these for the reloads that we perform,
3983 as the insns are scanned. */
3986 reload_as_needed (first, live_known)
3996 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
3997 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
3998 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
3999 bzero ((char *) reg_last_reload_reg, max_regno * sizeof (rtx));
4000 reg_has_output_reload = (char *) alloca (max_regno);
4001 for (i = 0; i < n_spills; i++)
4003 reg_reloaded_contents[i] = -1;
4004 reg_reloaded_insn[i] = 0;
4007 /* Reset all offsets on eliminable registers to their initial values. */
4008 #ifdef ELIMINABLE_REGS
4009 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
4011 INITIAL_ELIMINATION_OFFSET (reg_eliminate[i].from, reg_eliminate[i].to,
4012 reg_eliminate[i].initial_offset);
4013 reg_eliminate[i].previous_offset
4014 = reg_eliminate[i].offset = reg_eliminate[i].initial_offset;
4017 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
4018 reg_eliminate[0].previous_offset
4019 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
4022 num_not_at_initial_offset = 0;
4024 /* Order the spilled regs, so that allocate_reload_regs can guarantee to
4025 pack registers with group needs. */
4028 qsort (spill_regs, n_spills, sizeof (short), compare_spill_regs);
4029 for (i = 0; i < n_spills; i++)
4030 spill_reg_order[spill_regs[i]] = i;
4033 for (insn = first; insn;)
4035 register rtx next = NEXT_INSN (insn);
4037 /* Notice when we move to a new basic block. */
4038 if (live_known && this_block + 1 < n_basic_blocks
4039 && insn == basic_block_head[this_block+1])
4042 /* If we pass a label, copy the offsets from the label information
4043 into the current offsets of each elimination. */
4044 if (GET_CODE (insn) == CODE_LABEL)
4046 num_not_at_initial_offset = 0;
4047 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
4049 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
4050 = offsets_at[CODE_LABEL_NUMBER (insn)][i];
4051 if (reg_eliminate[i].can_eliminate
4052 && (reg_eliminate[i].offset
4053 != reg_eliminate[i].initial_offset))
4054 num_not_at_initial_offset++;
4058 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
4060 rtx avoid_return_reg = 0;
4061 rtx oldpat = PATTERN (insn);
4063 /* Set avoid_return_reg if this is an insn
4064 that might use the value of a function call. */
4065 if (SMALL_REGISTER_CLASSES && GET_CODE (insn) == CALL_INSN)
4067 if (GET_CODE (PATTERN (insn)) == SET)
4068 after_call = SET_DEST (PATTERN (insn));
4069 else if (GET_CODE (PATTERN (insn)) == PARALLEL
4070 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
4071 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
4075 else if (SMALL_REGISTER_CLASSES && after_call != 0
4076 && !(GET_CODE (PATTERN (insn)) == SET
4077 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
4079 if (reg_referenced_p (after_call, PATTERN (insn)))
4080 avoid_return_reg = after_call;
4084 /* If this is a USE and CLOBBER of a MEM, ensure that any
4085 references to eliminable registers have been removed. */
4087 if ((GET_CODE (PATTERN (insn)) == USE
4088 || GET_CODE (PATTERN (insn)) == CLOBBER)
4089 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
4090 XEXP (XEXP (PATTERN (insn), 0), 0)
4091 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4092 GET_MODE (XEXP (PATTERN (insn), 0)),
4095 /* If we need to do register elimination processing, do so.
4096 This might delete the insn, in which case we are done. */
4097 if (num_eliminable && GET_MODE (insn) == QImode)
4099 eliminate_regs_in_insn (insn, 1);
4100 if (GET_CODE (insn) == NOTE)
4107 if (GET_MODE (insn) == VOIDmode)
4109 /* First find the pseudo regs that must be reloaded for this insn.
4110 This info is returned in the tables reload_... (see reload.h).
4111 Also modify the body of INSN by substituting RELOAD
4112 rtx's for those pseudo regs. */
4115 bzero (reg_has_output_reload, max_regno);
4116 CLEAR_HARD_REG_SET (reg_is_output_reload);
4118 find_reloads (insn, 1, spill_indirect_levels, live_known,
4124 rtx prev = PREV_INSN (insn), next = NEXT_INSN (insn);
4128 /* If this block has not had spilling done for a
4129 particular clas and we have any non-optionals that need a
4130 spill reg in that class, abort. */
4132 for (class = 0; class < N_REG_CLASSES; class++)
4133 if (basic_block_needs[class] != 0
4134 && basic_block_needs[class][this_block] == 0)
4135 for (i = 0; i < n_reloads; i++)
4136 if (class == (int) reload_reg_class[i]
4137 && reload_reg_rtx[i] == 0
4138 && ! reload_optional[i]
4139 && (reload_in[i] != 0 || reload_out[i] != 0
4140 || reload_secondary_p[i] != 0))
4141 fatal_insn ("Non-optional registers need a spill register", insn);
4143 /* Now compute which reload regs to reload them into. Perhaps
4144 reusing reload regs from previous insns, or else output
4145 load insns to reload them. Maybe output store insns too.
4146 Record the choices of reload reg in reload_reg_rtx. */
4147 choose_reload_regs (insn, avoid_return_reg);
4149 /* Merge any reloads that we didn't combine for fear of
4150 increasing the number of spill registers needed but now
4151 discover can be safely merged. */
4152 if (SMALL_REGISTER_CLASSES)
4153 merge_assigned_reloads (insn);
4155 /* Generate the insns to reload operands into or out of
4156 their reload regs. */
4157 emit_reload_insns (insn);
4159 /* Substitute the chosen reload regs from reload_reg_rtx
4160 into the insn's body (or perhaps into the bodies of other
4161 load and store insn that we just made for reloading
4162 and that we moved the structure into). */
4165 /* If this was an ASM, make sure that all the reload insns
4166 we have generated are valid. If not, give an error
4169 if (asm_noperands (PATTERN (insn)) >= 0)
4170 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4171 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
4172 && (recog_memoized (p) < 0
4173 || (insn_extract (p),
4174 ! constrain_operands (INSN_CODE (p), 1))))
4176 error_for_asm (insn,
4177 "`asm' operand requires impossible reload");
4179 NOTE_SOURCE_FILE (p) = 0;
4180 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
4183 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4184 is no longer validly lying around to save a future reload.
4185 Note that this does not detect pseudos that were reloaded
4186 for this insn in order to be stored in
4187 (obeying register constraints). That is correct; such reload
4188 registers ARE still valid. */
4189 note_stores (oldpat, forget_old_reloads_1);
4191 /* There may have been CLOBBER insns placed after INSN. So scan
4192 between INSN and NEXT and use them to forget old reloads. */
4193 for (x = NEXT_INSN (insn); x != next; x = NEXT_INSN (x))
4194 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
4195 note_stores (PATTERN (x), forget_old_reloads_1);
4198 /* Likewise for regs altered by auto-increment in this insn.
4199 But note that the reg-notes are not changed by reloading:
4200 they still contain the pseudo-regs, not the spill regs. */
4201 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4202 if (REG_NOTE_KIND (x) == REG_INC)
4204 /* See if this pseudo reg was reloaded in this insn.
4205 If so, its last-reload info is still valid
4206 because it is based on this insn's reload. */
4207 for (i = 0; i < n_reloads; i++)
4208 if (reload_out[i] == XEXP (x, 0))
4212 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX);
4216 /* A reload reg's contents are unknown after a label. */
4217 if (GET_CODE (insn) == CODE_LABEL)
4218 for (i = 0; i < n_spills; i++)
4220 reg_reloaded_contents[i] = -1;
4221 reg_reloaded_insn[i] = 0;
4224 /* Don't assume a reload reg is still good after a call insn
4225 if it is a call-used reg. */
4226 else if (GET_CODE (insn) == CALL_INSN)
4227 for (i = 0; i < n_spills; i++)
4228 if (call_used_regs[spill_regs[i]])
4230 reg_reloaded_contents[i] = -1;
4231 reg_reloaded_insn[i] = 0;
4234 /* In case registers overlap, allow certain insns to invalidate
4235 particular hard registers. */
4237 #ifdef INSN_CLOBBERS_REGNO_P
4238 for (i = 0 ; i < n_spills ; i++)
4239 if (INSN_CLOBBERS_REGNO_P (insn, spill_regs[i]))
4241 reg_reloaded_contents[i] = -1;
4242 reg_reloaded_insn[i] = 0;
4254 /* Discard all record of any value reloaded from X,
4255 or reloaded in X from someplace else;
4256 unless X is an output reload reg of the current insn.
4258 X may be a hard reg (the reload reg)
4259 or it may be a pseudo reg that was reloaded from. */
4262 forget_old_reloads_1 (x, ignored)
4270 /* note_stores does give us subregs of hard regs. */
4271 while (GET_CODE (x) == SUBREG)
4273 offset += SUBREG_WORD (x);
4277 if (GET_CODE (x) != REG)
4280 regno = REGNO (x) + offset;
4282 if (regno >= FIRST_PSEUDO_REGISTER)
4287 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4288 /* Storing into a spilled-reg invalidates its contents.
4289 This can happen if a block-local pseudo is allocated to that reg
4290 and it wasn't spilled because this block's total need is 0.
4291 Then some insn might have an optional reload and use this reg. */
4292 for (i = 0; i < nr; i++)
4293 if (spill_reg_order[regno + i] >= 0
4294 /* But don't do this if the reg actually serves as an output
4295 reload reg in the current instruction. */
4297 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)))
4299 reg_reloaded_contents[spill_reg_order[regno + i]] = -1;
4300 reg_reloaded_insn[spill_reg_order[regno + i]] = 0;
4304 /* Since value of X has changed,
4305 forget any value previously copied from it. */
4308 /* But don't forget a copy if this is the output reload
4309 that establishes the copy's validity. */
4310 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4311 reg_last_reload_reg[regno + nr] = 0;
4314 /* For each reload, the mode of the reload register. */
4315 static enum machine_mode reload_mode[MAX_RELOADS];
4317 /* For each reload, the largest number of registers it will require. */
4318 static int reload_nregs[MAX_RELOADS];
4320 /* Comparison function for qsort to decide which of two reloads
4321 should be handled first. *P1 and *P2 are the reload numbers. */
4324 reload_reg_class_lower (r1p, r2p)
4325 const GENERIC_PTR r1p;
4326 const GENERIC_PTR r2p;
4328 register int r1 = *(short *)r1p, r2 = *(short *)r2p;
4331 /* Consider required reloads before optional ones. */
4332 t = reload_optional[r1] - reload_optional[r2];
4336 /* Count all solitary classes before non-solitary ones. */
4337 t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
4338 - (reg_class_size[(int) reload_reg_class[r1]] == 1));
4342 /* Aside from solitaires, consider all multi-reg groups first. */
4343 t = reload_nregs[r2] - reload_nregs[r1];
4347 /* Consider reloads in order of increasing reg-class number. */
4348 t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
4352 /* If reloads are equally urgent, sort by reload number,
4353 so that the results of qsort leave nothing to chance. */
4357 /* The following HARD_REG_SETs indicate when each hard register is
4358 used for a reload of various parts of the current insn. */
4360 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4361 static HARD_REG_SET reload_reg_used;
4362 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4363 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4364 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4365 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4366 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4367 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4368 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4369 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4370 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4371 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4372 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4373 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4374 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4375 static HARD_REG_SET reload_reg_used_in_op_addr;
4376 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4377 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4378 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4379 static HARD_REG_SET reload_reg_used_in_insn;
4380 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4381 static HARD_REG_SET reload_reg_used_in_other_addr;
4383 /* If reg is in use as a reload reg for any sort of reload. */
4384 static HARD_REG_SET reload_reg_used_at_all;
4386 /* If reg is use as an inherited reload. We just mark the first register
4388 static HARD_REG_SET reload_reg_used_for_inherit;
4390 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4391 TYPE. MODE is used to indicate how many consecutive regs are
4395 mark_reload_reg_in_use (regno, opnum, type, mode)
4398 enum reload_type type;
4399 enum machine_mode mode;
4401 int nregs = HARD_REGNO_NREGS (regno, mode);
4404 for (i = regno; i < nregs + regno; i++)
4409 SET_HARD_REG_BIT (reload_reg_used, i);
4412 case RELOAD_FOR_INPUT_ADDRESS:
4413 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4416 case RELOAD_FOR_INPADDR_ADDRESS:
4417 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4420 case RELOAD_FOR_OUTPUT_ADDRESS:
4421 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4424 case RELOAD_FOR_OUTADDR_ADDRESS:
4425 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4428 case RELOAD_FOR_OPERAND_ADDRESS:
4429 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4432 case RELOAD_FOR_OPADDR_ADDR:
4433 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4436 case RELOAD_FOR_OTHER_ADDRESS:
4437 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4440 case RELOAD_FOR_INPUT:
4441 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4444 case RELOAD_FOR_OUTPUT:
4445 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4448 case RELOAD_FOR_INSN:
4449 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4453 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4457 /* Similarly, but show REGNO is no longer in use for a reload. */
4460 clear_reload_reg_in_use (regno, opnum, type, mode)
4463 enum reload_type type;
4464 enum machine_mode mode;
4466 int nregs = HARD_REGNO_NREGS (regno, mode);
4469 for (i = regno; i < nregs + regno; i++)
4474 CLEAR_HARD_REG_BIT (reload_reg_used, i);
4477 case RELOAD_FOR_INPUT_ADDRESS:
4478 CLEAR_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4481 case RELOAD_FOR_INPADDR_ADDRESS:
4482 CLEAR_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4485 case RELOAD_FOR_OUTPUT_ADDRESS:
4486 CLEAR_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4489 case RELOAD_FOR_OUTADDR_ADDRESS:
4490 CLEAR_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4493 case RELOAD_FOR_OPERAND_ADDRESS:
4494 CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4497 case RELOAD_FOR_OPADDR_ADDR:
4498 CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4501 case RELOAD_FOR_OTHER_ADDRESS:
4502 CLEAR_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4505 case RELOAD_FOR_INPUT:
4506 CLEAR_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4509 case RELOAD_FOR_OUTPUT:
4510 CLEAR_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4513 case RELOAD_FOR_INSN:
4514 CLEAR_HARD_REG_BIT (reload_reg_used_in_insn, i);
4520 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4521 specified by OPNUM and TYPE. */
4524 reload_reg_free_p (regno, opnum, type)
4527 enum reload_type type;
4531 /* In use for a RELOAD_OTHER means it's not available for anything. */
4532 if (TEST_HARD_REG_BIT (reload_reg_used, regno))
4538 /* In use for anything means we can't use it for RELOAD_OTHER. */
4539 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4540 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4541 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4544 for (i = 0; i < reload_n_operands; i++)
4545 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4546 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4547 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4548 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4549 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4550 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4555 case RELOAD_FOR_INPUT:
4556 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4557 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4560 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4563 /* If it is used for some other input, can't use it. */
4564 for (i = 0; i < reload_n_operands; i++)
4565 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4568 /* If it is used in a later operand's address, can't use it. */
4569 for (i = opnum + 1; i < reload_n_operands; i++)
4570 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4571 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4576 case RELOAD_FOR_INPUT_ADDRESS:
4577 /* Can't use a register if it is used for an input address for this
4578 operand or used as an input in an earlier one. */
4579 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4580 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4583 for (i = 0; i < opnum; i++)
4584 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4589 case RELOAD_FOR_INPADDR_ADDRESS:
4590 /* Can't use a register if it is used for an input address
4591 address for this operand or used as an input in an earlier
4593 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4596 for (i = 0; i < opnum; i++)
4597 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4602 case RELOAD_FOR_OUTPUT_ADDRESS:
4603 /* Can't use a register if it is used for an output address for this
4604 operand or used as an output in this or a later operand. */
4605 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4608 for (i = opnum; i < reload_n_operands; i++)
4609 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4614 case RELOAD_FOR_OUTADDR_ADDRESS:
4615 /* Can't use a register if it is used for an output address
4616 address for this operand or used as an output in this or a
4618 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4621 for (i = opnum; i < reload_n_operands; i++)
4622 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4627 case RELOAD_FOR_OPERAND_ADDRESS:
4628 for (i = 0; i < reload_n_operands; i++)
4629 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4632 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4633 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4635 case RELOAD_FOR_OPADDR_ADDR:
4636 for (i = 0; i < reload_n_operands; i++)
4637 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4640 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4642 case RELOAD_FOR_OUTPUT:
4643 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4644 outputs, or an operand address for this or an earlier output. */
4645 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4648 for (i = 0; i < reload_n_operands; i++)
4649 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4652 for (i = 0; i <= opnum; i++)
4653 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4654 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4659 case RELOAD_FOR_INSN:
4660 for (i = 0; i < reload_n_operands; i++)
4661 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4662 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4665 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4666 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4668 case RELOAD_FOR_OTHER_ADDRESS:
4669 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4674 /* Return 1 if the value in reload reg REGNO, as used by a reload
4675 needed for the part of the insn specified by OPNUM and TYPE,
4676 is not in use for a reload in any prior part of the insn.
4678 We can assume that the reload reg was already tested for availability
4679 at the time it is needed, and we should not check this again,
4680 in case the reg has already been marked in use. */
4683 reload_reg_free_before_p (regno, opnum, type)
4686 enum reload_type type;
4692 case RELOAD_FOR_OTHER_ADDRESS:
4693 /* These always come first. */
4697 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4699 /* If this use is for part of the insn,
4700 check the reg is not in use for any prior part. It is tempting
4701 to try to do this by falling through from objecs that occur
4702 later in the insn to ones that occur earlier, but that will not
4703 correctly take into account the fact that here we MUST ignore
4704 things that would prevent the register from being allocated in
4705 the first place, since we know that it was allocated. */
4707 case RELOAD_FOR_OUTPUT_ADDRESS:
4708 case RELOAD_FOR_OUTADDR_ADDRESS:
4709 /* Earlier reloads are for earlier outputs or their addresses,
4710 any RELOAD_FOR_INSN reloads, any inputs or their addresses, or any
4711 RELOAD_FOR_OTHER_ADDRESS reloads (we know it can't conflict with
4713 for (i = 0; i < opnum; i++)
4714 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4715 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4716 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4719 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4722 for (i = 0; i < reload_n_operands; i++)
4723 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4724 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4725 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4728 return (! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4729 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4730 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4732 case RELOAD_FOR_OUTPUT:
4733 /* This can't be used in the output address for this operand and
4734 anything that can't be used for it, except that we've already
4735 tested for RELOAD_FOR_INSN objects. */
4737 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno)
4738 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4741 for (i = 0; i < opnum; i++)
4742 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4743 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4744 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4747 for (i = 0; i < reload_n_operands; i++)
4748 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4749 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4750 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4751 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4754 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4756 case RELOAD_FOR_OPERAND_ADDRESS:
4757 /* Earlier reloads include RELOAD_FOR_OPADDR_ADDR reloads. */
4758 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4761 /* ... fall through ... */
4763 case RELOAD_FOR_OPADDR_ADDR:
4764 case RELOAD_FOR_INSN:
4765 /* These can't conflict with inputs, or each other, so all we have to
4766 test is input addresses and the addresses of OTHER items. */
4768 for (i = 0; i < reload_n_operands; i++)
4769 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4770 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4773 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4775 case RELOAD_FOR_INPUT:
4776 /* The only things earlier are the address for this and
4777 earlier inputs, other inputs (which we know we don't conflict
4778 with), and addresses of RELOAD_OTHER objects. */
4780 for (i = 0; i <= opnum; i++)
4781 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4782 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4785 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4787 case RELOAD_FOR_INPUT_ADDRESS:
4788 case RELOAD_FOR_INPADDR_ADDRESS:
4789 /* Similarly, all we have to check is for use in earlier inputs'
4791 for (i = 0; i < opnum; i++)
4792 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4793 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4796 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4801 /* Return 1 if the value in reload reg REGNO, as used by a reload
4802 needed for the part of the insn specified by OPNUM and TYPE,
4803 is still available in REGNO at the end of the insn.
4805 We can assume that the reload reg was already tested for availability
4806 at the time it is needed, and we should not check this again,
4807 in case the reg has already been marked in use. */
4810 reload_reg_reaches_end_p (regno, opnum, type)
4813 enum reload_type type;
4820 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4821 its value must reach the end. */
4824 /* If this use is for part of the insn,
4825 its value reaches if no subsequent part uses the same register.
4826 Just like the above function, don't try to do this with lots
4829 case RELOAD_FOR_OTHER_ADDRESS:
4830 /* Here we check for everything else, since these don't conflict
4831 with anything else and everything comes later. */
4833 for (i = 0; i < reload_n_operands; i++)
4834 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4835 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4836 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4837 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4838 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4839 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4842 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4843 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4844 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4846 case RELOAD_FOR_INPUT_ADDRESS:
4847 case RELOAD_FOR_INPADDR_ADDRESS:
4848 /* Similar, except that we check only for this and subsequent inputs
4849 and the address of only subsequent inputs and we do not need
4850 to check for RELOAD_OTHER objects since they are known not to
4853 for (i = opnum; i < reload_n_operands; i++)
4854 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4857 for (i = opnum + 1; i < reload_n_operands; i++)
4858 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4859 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4862 for (i = 0; i < reload_n_operands; i++)
4863 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4864 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4865 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4868 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4871 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4872 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4874 case RELOAD_FOR_INPUT:
4875 /* Similar to input address, except we start at the next operand for
4876 both input and input address and we do not check for
4877 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4880 for (i = opnum + 1; i < reload_n_operands; i++)
4881 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4882 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4883 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4886 /* ... fall through ... */
4888 case RELOAD_FOR_OPERAND_ADDRESS:
4889 /* Check outputs and their addresses. */
4891 for (i = 0; i < reload_n_operands; i++)
4892 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4893 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4894 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4899 case RELOAD_FOR_OPADDR_ADDR:
4900 for (i = 0; i < reload_n_operands; i++)
4901 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4902 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4903 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4906 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4907 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4909 case RELOAD_FOR_INSN:
4910 /* These conflict with other outputs with RELOAD_OTHER. So
4911 we need only check for output addresses. */
4915 /* ... fall through ... */
4917 case RELOAD_FOR_OUTPUT:
4918 case RELOAD_FOR_OUTPUT_ADDRESS:
4919 case RELOAD_FOR_OUTADDR_ADDRESS:
4920 /* We already know these can't conflict with a later output. So the
4921 only thing to check are later output addresses. */
4922 for (i = opnum + 1; i < reload_n_operands; i++)
4923 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4924 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4933 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4936 This function uses the same algorithm as reload_reg_free_p above. */
4939 reloads_conflict (r1, r2)
4942 enum reload_type r1_type = reload_when_needed[r1];
4943 enum reload_type r2_type = reload_when_needed[r2];
4944 int r1_opnum = reload_opnum[r1];
4945 int r2_opnum = reload_opnum[r2];
4947 /* RELOAD_OTHER conflicts with everything. */
4948 if (r2_type == RELOAD_OTHER)
4951 /* Otherwise, check conflicts differently for each type. */
4955 case RELOAD_FOR_INPUT:
4956 return (r2_type == RELOAD_FOR_INSN
4957 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4958 || r2_type == RELOAD_FOR_OPADDR_ADDR
4959 || r2_type == RELOAD_FOR_INPUT
4960 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4961 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4962 && r2_opnum > r1_opnum));
4964 case RELOAD_FOR_INPUT_ADDRESS:
4965 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4966 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4968 case RELOAD_FOR_INPADDR_ADDRESS:
4969 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4970 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4972 case RELOAD_FOR_OUTPUT_ADDRESS:
4973 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4974 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4976 case RELOAD_FOR_OUTADDR_ADDRESS:
4977 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4978 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4980 case RELOAD_FOR_OPERAND_ADDRESS:
4981 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4982 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4984 case RELOAD_FOR_OPADDR_ADDR:
4985 return (r2_type == RELOAD_FOR_INPUT
4986 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4988 case RELOAD_FOR_OUTPUT:
4989 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4990 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4991 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4992 && r2_opnum >= r1_opnum));
4994 case RELOAD_FOR_INSN:
4995 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4996 || r2_type == RELOAD_FOR_INSN
4997 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4999 case RELOAD_FOR_OTHER_ADDRESS:
5000 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5010 /* Vector of reload-numbers showing the order in which the reloads should
5012 short reload_order[MAX_RELOADS];
5014 /* Indexed by reload number, 1 if incoming value
5015 inherited from previous insns. */
5016 char reload_inherited[MAX_RELOADS];
5018 /* For an inherited reload, this is the insn the reload was inherited from,
5019 if we know it. Otherwise, this is 0. */
5020 rtx reload_inheritance_insn[MAX_RELOADS];
5022 /* If non-zero, this is a place to get the value of the reload,
5023 rather than using reload_in. */
5024 rtx reload_override_in[MAX_RELOADS];
5026 /* For each reload, the index in spill_regs of the spill register used,
5027 or -1 if we did not need one of the spill registers for this reload. */
5028 int reload_spill_index[MAX_RELOADS];
5030 /* Find a spill register to use as a reload register for reload R.
5031 LAST_RELOAD is non-zero if this is the last reload for the insn being
5034 Set reload_reg_rtx[R] to the register allocated.
5036 If NOERROR is nonzero, we return 1 if successful,
5037 or 0 if we couldn't find a spill reg and we didn't change anything. */
5040 allocate_reload_reg (r, insn, last_reload, noerror)
5052 /* If we put this reload ahead, thinking it is a group,
5053 then insist on finding a group. Otherwise we can grab a
5054 reg that some other reload needs.
5055 (That can happen when we have a 68000 DATA_OR_FP_REG
5056 which is a group of data regs or one fp reg.)
5057 We need not be so restrictive if there are no more reloads
5060 ??? Really it would be nicer to have smarter handling
5061 for that kind of reg class, where a problem like this is normal.
5062 Perhaps those classes should be avoided for reloading
5063 by use of more alternatives. */
5065 int force_group = reload_nregs[r] > 1 && ! last_reload;
5067 /* If we want a single register and haven't yet found one,
5068 take any reg in the right class and not in use.
5069 If we want a consecutive group, here is where we look for it.
5071 We use two passes so we can first look for reload regs to
5072 reuse, which are already in use for other reloads in this insn,
5073 and only then use additional registers.
5074 I think that maximizing reuse is needed to make sure we don't
5075 run out of reload regs. Suppose we have three reloads, and
5076 reloads A and B can share regs. These need two regs.
5077 Suppose A and B are given different regs.
5078 That leaves none for C. */
5079 for (pass = 0; pass < 2; pass++)
5081 /* I is the index in spill_regs.
5082 We advance it round-robin between insns to use all spill regs
5083 equally, so that inherited reloads have a chance
5084 of leapfrogging each other. Don't do this, however, when we have
5085 group needs and failure would be fatal; if we only have a relatively
5086 small number of spill registers, and more than one of them has
5087 group needs, then by starting in the middle, we may end up
5088 allocating the first one in such a way that we are not left with
5089 sufficient groups to handle the rest. */
5091 if (noerror || ! force_group)
5096 for (count = 0; count < n_spills; count++)
5098 int class = (int) reload_reg_class[r];
5100 i = (i + 1) % n_spills;
5102 if (reload_reg_free_p (spill_regs[i], reload_opnum[r],
5103 reload_when_needed[r])
5104 && TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
5105 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
5106 /* Look first for regs to share, then for unshared. But
5107 don't share regs used for inherited reloads; they are
5108 the ones we want to preserve. */
5110 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5112 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5115 int nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
5116 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5117 (on 68000) got us two FP regs. If NR is 1,
5118 we would reject both of them. */
5120 nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
5121 /* If we need only one reg, we have already won. */
5124 /* But reject a single reg if we demand a group. */
5129 /* Otherwise check that as many consecutive regs as we need
5131 Also, don't use for a group registers that are
5132 needed for nongroups. */
5133 if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
5136 regno = spill_regs[i] + nr - 1;
5137 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5138 && spill_reg_order[regno] >= 0
5139 && reload_reg_free_p (regno, reload_opnum[r],
5140 reload_when_needed[r])
5141 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
5151 /* If we found something on pass 1, omit pass 2. */
5152 if (count < n_spills)
5156 /* We should have found a spill register by now. */
5157 if (count == n_spills)
5164 /* I is the index in SPILL_REG_RTX of the reload register we are to
5165 allocate. Get an rtx for it and find its register number. */
5167 new = spill_reg_rtx[i];
5169 if (new == 0 || GET_MODE (new) != reload_mode[r])
5170 spill_reg_rtx[i] = new
5171 = gen_rtx (REG, reload_mode[r], spill_regs[i]);
5173 regno = true_regnum (new);
5175 /* Detect when the reload reg can't hold the reload mode.
5176 This used to be one `if', but Sequent compiler can't handle that. */
5177 if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5179 enum machine_mode test_mode = VOIDmode;
5181 test_mode = GET_MODE (reload_in[r]);
5182 /* If reload_in[r] has VOIDmode, it means we will load it
5183 in whatever mode the reload reg has: to wit, reload_mode[r].
5184 We have already tested that for validity. */
5185 /* Aside from that, we need to test that the expressions
5186 to reload from or into have modes which are valid for this
5187 reload register. Otherwise the reload insns would be invalid. */
5188 if (! (reload_in[r] != 0 && test_mode != VOIDmode
5189 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5190 if (! (reload_out[r] != 0
5191 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
5193 /* The reg is OK. */
5196 /* Mark as in use for this insn the reload regs we use
5198 mark_reload_reg_in_use (spill_regs[i], reload_opnum[r],
5199 reload_when_needed[r], reload_mode[r]);
5201 reload_reg_rtx[r] = new;
5202 reload_spill_index[r] = i;
5207 /* The reg is not OK. */
5212 if (asm_noperands (PATTERN (insn)) < 0)
5213 /* It's the compiler's fault. */
5214 fatal_insn ("Could not find a spill register", insn);
5216 /* It's the user's fault; the operand's mode and constraint
5217 don't match. Disable this reload so we don't crash in final. */
5218 error_for_asm (insn,
5219 "`asm' operand constraint incompatible with operand size");
5222 reload_reg_rtx[r] = 0;
5223 reload_optional[r] = 1;
5224 reload_secondary_p[r] = 1;
5229 /* Assign hard reg targets for the pseudo-registers we must reload
5230 into hard regs for this insn.
5231 Also output the instructions to copy them in and out of the hard regs.
5233 For machines with register classes, we are responsible for
5234 finding a reload reg in the proper class. */
5237 choose_reload_regs (insn, avoid_return_reg)
5239 rtx avoid_return_reg;
5242 int max_group_size = 1;
5243 enum reg_class group_class = NO_REGS;
5246 rtx save_reload_reg_rtx[MAX_RELOADS];
5247 char save_reload_inherited[MAX_RELOADS];
5248 rtx save_reload_inheritance_insn[MAX_RELOADS];
5249 rtx save_reload_override_in[MAX_RELOADS];
5250 int save_reload_spill_index[MAX_RELOADS];
5251 HARD_REG_SET save_reload_reg_used;
5252 HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
5253 HARD_REG_SET save_reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
5254 HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
5255 HARD_REG_SET save_reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
5256 HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS];
5257 HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS];
5258 HARD_REG_SET save_reload_reg_used_in_op_addr;
5259 HARD_REG_SET save_reload_reg_used_in_op_addr_reload;
5260 HARD_REG_SET save_reload_reg_used_in_insn;
5261 HARD_REG_SET save_reload_reg_used_in_other_addr;
5262 HARD_REG_SET save_reload_reg_used_at_all;
5264 bzero (reload_inherited, MAX_RELOADS);
5265 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5266 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5268 CLEAR_HARD_REG_SET (reload_reg_used);
5269 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5270 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5271 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5272 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5273 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5275 for (i = 0; i < reload_n_operands; i++)
5277 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5278 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5279 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5280 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5281 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5282 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5285 /* Don't bother with avoiding the return reg
5286 if we have no mandatory reload that could use it. */
5287 if (SMALL_REGISTER_CLASSES && avoid_return_reg)
5290 int regno = REGNO (avoid_return_reg);
5292 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
5295 for (r = regno; r < regno + nregs; r++)
5296 if (spill_reg_order[r] >= 0)
5297 for (j = 0; j < n_reloads; j++)
5298 if (!reload_optional[j] && reload_reg_rtx[j] == 0
5299 && (reload_in[j] != 0 || reload_out[j] != 0
5300 || reload_secondary_p[j])
5302 TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[j]], r))
5305 avoid_return_reg = 0;
5308 #if 0 /* Not needed, now that we can always retry without inheritance. */
5309 /* See if we have more mandatory reloads than spill regs.
5310 If so, then we cannot risk optimizations that could prevent
5311 reloads from sharing one spill register.
5313 Since we will try finding a better register than reload_reg_rtx
5314 unless it is equal to reload_in or reload_out, count such reloads. */
5317 int tem = SMALL_REGISTER_CLASSES? (avoid_return_reg != 0): 0;
5318 for (j = 0; j < n_reloads; j++)
5319 if (! reload_optional[j]
5320 && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
5321 && (reload_reg_rtx[j] == 0
5322 || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
5323 && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
5330 /* Don't use the subroutine call return reg for a reload
5331 if we are supposed to avoid it. */
5332 if (SMALL_REGISTER_CLASSES && avoid_return_reg)
5334 int regno = REGNO (avoid_return_reg);
5336 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
5339 for (r = regno; r < regno + nregs; r++)
5340 if (spill_reg_order[r] >= 0)
5341 SET_HARD_REG_BIT (reload_reg_used, r);
5344 /* In order to be certain of getting the registers we need,
5345 we must sort the reloads into order of increasing register class.
5346 Then our grabbing of reload registers will parallel the process
5347 that provided the reload registers.
5349 Also note whether any of the reloads wants a consecutive group of regs.
5350 If so, record the maximum size of the group desired and what
5351 register class contains all the groups needed by this insn. */
5353 for (j = 0; j < n_reloads; j++)
5355 reload_order[j] = j;
5356 reload_spill_index[j] = -1;
5359 = (reload_inmode[j] == VOIDmode
5360 || (GET_MODE_SIZE (reload_outmode[j])
5361 > GET_MODE_SIZE (reload_inmode[j])))
5362 ? reload_outmode[j] : reload_inmode[j];
5364 reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
5366 if (reload_nregs[j] > 1)
5368 max_group_size = MAX (reload_nregs[j], max_group_size);
5369 group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
5372 /* If we have already decided to use a certain register,
5373 don't use it in another way. */
5374 if (reload_reg_rtx[j])
5375 mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j],
5376 reload_when_needed[j], reload_mode[j]);
5380 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5382 bcopy ((char *) reload_reg_rtx, (char *) save_reload_reg_rtx,
5383 sizeof reload_reg_rtx);
5384 bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
5385 bcopy ((char *) reload_inheritance_insn,
5386 (char *) save_reload_inheritance_insn,
5387 sizeof reload_inheritance_insn);
5388 bcopy ((char *) reload_override_in, (char *) save_reload_override_in,
5389 sizeof reload_override_in);
5390 bcopy ((char *) reload_spill_index, (char *) save_reload_spill_index,
5391 sizeof reload_spill_index);
5392 COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
5393 COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
5394 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
5395 reload_reg_used_in_op_addr);
5397 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr_reload,
5398 reload_reg_used_in_op_addr_reload);
5400 COPY_HARD_REG_SET (save_reload_reg_used_in_insn,
5401 reload_reg_used_in_insn);
5402 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr,
5403 reload_reg_used_in_other_addr);
5405 for (i = 0; i < reload_n_operands; i++)
5407 COPY_HARD_REG_SET (save_reload_reg_used_in_output[i],
5408 reload_reg_used_in_output[i]);
5409 COPY_HARD_REG_SET (save_reload_reg_used_in_input[i],
5410 reload_reg_used_in_input[i]);
5411 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i],
5412 reload_reg_used_in_input_addr[i]);
5413 COPY_HARD_REG_SET (save_reload_reg_used_in_inpaddr_addr[i],
5414 reload_reg_used_in_inpaddr_addr[i]);
5415 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i],
5416 reload_reg_used_in_output_addr[i]);
5417 COPY_HARD_REG_SET (save_reload_reg_used_in_outaddr_addr[i],
5418 reload_reg_used_in_outaddr_addr[i]);
5421 /* If -O, try first with inheritance, then turning it off.
5422 If not -O, don't do inheritance.
5423 Using inheritance when not optimizing leads to paradoxes
5424 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5425 because one side of the comparison might be inherited. */
5427 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5429 /* Process the reloads in order of preference just found.
5430 Beyond this point, subregs can be found in reload_reg_rtx.
5432 This used to look for an existing reloaded home for all
5433 of the reloads, and only then perform any new reloads.
5434 But that could lose if the reloads were done out of reg-class order
5435 because a later reload with a looser constraint might have an old
5436 home in a register needed by an earlier reload with a tighter constraint.
5438 To solve this, we make two passes over the reloads, in the order
5439 described above. In the first pass we try to inherit a reload
5440 from a previous insn. If there is a later reload that needs a
5441 class that is a proper subset of the class being processed, we must
5442 also allocate a spill register during the first pass.
5444 Then make a second pass over the reloads to allocate any reloads
5445 that haven't been given registers yet. */
5447 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5449 for (j = 0; j < n_reloads; j++)
5451 register int r = reload_order[j];
5453 /* Ignore reloads that got marked inoperative. */
5454 if (reload_out[r] == 0 && reload_in[r] == 0
5455 && ! reload_secondary_p[r])
5458 /* If find_reloads chose a to use reload_in or reload_out as a reload
5459 register, we don't need to chose one. Otherwise, try even if it
5460 found one since we might save an insn if we find the value lying
5462 if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
5463 && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
5464 || rtx_equal_p (reload_out[r], reload_reg_rtx[r])))
5467 #if 0 /* No longer needed for correct operation.
5468 It might give better code, or might not; worth an experiment? */
5469 /* If this is an optional reload, we can't inherit from earlier insns
5470 until we are sure that any non-optional reloads have been allocated.
5471 The following code takes advantage of the fact that optional reloads
5472 are at the end of reload_order. */
5473 if (reload_optional[r] != 0)
5474 for (i = 0; i < j; i++)
5475 if ((reload_out[reload_order[i]] != 0
5476 || reload_in[reload_order[i]] != 0
5477 || reload_secondary_p[reload_order[i]])
5478 && ! reload_optional[reload_order[i]]
5479 && reload_reg_rtx[reload_order[i]] == 0)
5480 allocate_reload_reg (reload_order[i], insn, 0, inheritance);
5483 /* First see if this pseudo is already available as reloaded
5484 for a previous insn. We cannot try to inherit for reloads
5485 that are smaller than the maximum number of registers needed
5486 for groups unless the register we would allocate cannot be used
5489 We could check here to see if this is a secondary reload for
5490 an object that is already in a register of the desired class.
5491 This would avoid the need for the secondary reload register.
5492 But this is complex because we can't easily determine what
5493 objects might want to be loaded via this reload. So let a
5494 register be allocated here. In `emit_reload_insns' we suppress
5495 one of the loads in the case described above. */
5499 register int regno = -1;
5500 enum machine_mode mode;
5502 if (reload_in[r] == 0)
5504 else if (GET_CODE (reload_in[r]) == REG)
5506 regno = REGNO (reload_in[r]);
5507 mode = GET_MODE (reload_in[r]);
5509 else if (GET_CODE (reload_in_reg[r]) == REG)
5511 regno = REGNO (reload_in_reg[r]);
5512 mode = GET_MODE (reload_in_reg[r]);
5515 /* This won't work, since REGNO can be a pseudo reg number.
5516 Also, it takes much more hair to keep track of all the things
5517 that can invalidate an inherited reload of part of a pseudoreg. */
5518 else if (GET_CODE (reload_in[r]) == SUBREG
5519 && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
5520 regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
5523 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5525 i = spill_reg_order[REGNO (reg_last_reload_reg[regno])];
5527 if (reg_reloaded_contents[i] == regno
5528 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
5529 >= GET_MODE_SIZE (mode))
5530 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
5531 && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5533 && (reload_nregs[r] == max_group_size
5534 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5536 && reload_reg_free_p (spill_regs[i], reload_opnum[r],
5537 reload_when_needed[r])
5538 && reload_reg_free_before_p (spill_regs[i],
5540 reload_when_needed[r]))
5542 /* If a group is needed, verify that all the subsequent
5543 registers still have their values intact. */
5545 = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
5548 for (k = 1; k < nr; k++)
5549 if (reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
5557 /* We found a register that contains the
5558 value we need. If this register is the
5559 same as an `earlyclobber' operand of the
5560 current insn, just mark it as a place to
5561 reload from since we can't use it as the
5562 reload register itself. */
5564 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5565 if (reg_overlap_mentioned_for_reload_p
5566 (reg_last_reload_reg[regno],
5567 reload_earlyclobbers[i1]))
5570 if (i1 != n_earlyclobbers
5571 /* Don't really use the inherited spill reg
5572 if we need it wider than we've got it. */
5573 || (GET_MODE_SIZE (reload_mode[r])
5574 > GET_MODE_SIZE (mode)))
5575 reload_override_in[r] = reg_last_reload_reg[regno];
5579 /* We can use this as a reload reg. */
5580 /* Mark the register as in use for this part of
5582 mark_reload_reg_in_use (spill_regs[i],
5584 reload_when_needed[r],
5586 reload_reg_rtx[r] = reg_last_reload_reg[regno];
5587 reload_inherited[r] = 1;
5588 reload_inheritance_insn[r]
5589 = reg_reloaded_insn[i];
5590 reload_spill_index[r] = i;
5591 for (k = 0; k < nr; k++)
5592 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5600 /* Here's another way to see if the value is already lying around. */
5602 && reload_in[r] != 0
5603 && ! reload_inherited[r]
5604 && reload_out[r] == 0
5605 && (CONSTANT_P (reload_in[r])
5606 || GET_CODE (reload_in[r]) == PLUS
5607 || GET_CODE (reload_in[r]) == REG
5608 || GET_CODE (reload_in[r]) == MEM)
5609 && (reload_nregs[r] == max_group_size
5610 || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
5613 = find_equiv_reg (reload_in[r], insn, reload_reg_class[r],
5614 -1, NULL_PTR, 0, reload_mode[r]);
5619 if (GET_CODE (equiv) == REG)
5620 regno = REGNO (equiv);
5621 else if (GET_CODE (equiv) == SUBREG)
5623 /* This must be a SUBREG of a hard register.
5624 Make a new REG since this might be used in an
5625 address and not all machines support SUBREGs
5627 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5628 equiv = gen_rtx (REG, reload_mode[r], regno);
5634 /* If we found a spill reg, reject it unless it is free
5635 and of the desired class. */
5637 && ((spill_reg_order[regno] >= 0
5638 && ! reload_reg_free_before_p (regno, reload_opnum[r],
5639 reload_when_needed[r]))
5640 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5644 if (equiv != 0 && TEST_HARD_REG_BIT (reload_reg_used_at_all, regno))
5647 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5650 /* We found a register that contains the value we need.
5651 If this register is the same as an `earlyclobber' operand
5652 of the current insn, just mark it as a place to reload from
5653 since we can't use it as the reload register itself. */
5656 for (i = 0; i < n_earlyclobbers; i++)
5657 if (reg_overlap_mentioned_for_reload_p (equiv,
5658 reload_earlyclobbers[i]))
5660 reload_override_in[r] = equiv;
5665 /* JRV: If the equiv register we have found is
5666 explicitly clobbered in the current insn, mark but
5667 don't use, as above. */
5669 if (equiv != 0 && regno_clobbered_p (regno, insn))
5671 reload_override_in[r] = equiv;
5675 /* If we found an equivalent reg, say no code need be generated
5676 to load it, and use it as our reload reg. */
5677 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5679 int nr = HARD_REGNO_NREGS (regno, reload_mode[r]);
5681 reload_reg_rtx[r] = equiv;
5682 reload_inherited[r] = 1;
5684 /* If any of the hard registers in EQUIV are spill
5685 registers, mark them as in use for this insn. */
5686 for (k = 0; k < nr; k++)
5688 i = spill_reg_order[regno + k];
5691 mark_reload_reg_in_use (regno, reload_opnum[r],
5692 reload_when_needed[r],
5694 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5701 /* If we found a register to use already, or if this is an optional
5702 reload, we are done. */
5703 if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
5706 #if 0 /* No longer needed for correct operation. Might or might not
5707 give better code on the average. Want to experiment? */
5709 /* See if there is a later reload that has a class different from our
5710 class that intersects our class or that requires less register
5711 than our reload. If so, we must allocate a register to this
5712 reload now, since that reload might inherit a previous reload
5713 and take the only available register in our class. Don't do this
5714 for optional reloads since they will force all previous reloads
5715 to be allocated. Also don't do this for reloads that have been
5718 for (i = j + 1; i < n_reloads; i++)
5720 int s = reload_order[i];
5722 if ((reload_in[s] == 0 && reload_out[s] == 0
5723 && ! reload_secondary_p[s])
5724 || reload_optional[s])
5727 if ((reload_reg_class[s] != reload_reg_class[r]
5728 && reg_classes_intersect_p (reload_reg_class[r],
5729 reload_reg_class[s]))
5730 || reload_nregs[s] < reload_nregs[r])
5737 allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance);
5741 /* Now allocate reload registers for anything non-optional that
5742 didn't get one yet. */
5743 for (j = 0; j < n_reloads; j++)
5745 register int r = reload_order[j];
5747 /* Ignore reloads that got marked inoperative. */
5748 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
5751 /* Skip reloads that already have a register allocated or are
5753 if (reload_reg_rtx[r] != 0 || reload_optional[r])
5756 if (! allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance))
5760 /* If that loop got all the way, we have won. */
5765 /* Loop around and try without any inheritance. */
5766 /* First undo everything done by the failed attempt
5767 to allocate with inheritance. */
5768 bcopy ((char *) save_reload_reg_rtx, (char *) reload_reg_rtx,
5769 sizeof reload_reg_rtx);
5770 bcopy ((char *) save_reload_inherited, (char *) reload_inherited,
5771 sizeof reload_inherited);
5772 bcopy ((char *) save_reload_inheritance_insn,
5773 (char *) reload_inheritance_insn,
5774 sizeof reload_inheritance_insn);
5775 bcopy ((char *) save_reload_override_in, (char *) reload_override_in,
5776 sizeof reload_override_in);
5777 bcopy ((char *) save_reload_spill_index, (char *) reload_spill_index,
5778 sizeof reload_spill_index);
5779 COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
5780 COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
5781 COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
5782 save_reload_reg_used_in_op_addr);
5783 COPY_HARD_REG_SET (reload_reg_used_in_op_addr_reload,
5784 save_reload_reg_used_in_op_addr_reload);
5785 COPY_HARD_REG_SET (reload_reg_used_in_insn,
5786 save_reload_reg_used_in_insn);
5787 COPY_HARD_REG_SET (reload_reg_used_in_other_addr,
5788 save_reload_reg_used_in_other_addr);
5790 for (i = 0; i < reload_n_operands; i++)
5792 COPY_HARD_REG_SET (reload_reg_used_in_input[i],
5793 save_reload_reg_used_in_input[i]);
5794 COPY_HARD_REG_SET (reload_reg_used_in_output[i],
5795 save_reload_reg_used_in_output[i]);
5796 COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i],
5797 save_reload_reg_used_in_input_addr[i]);
5798 COPY_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i],
5799 save_reload_reg_used_in_inpaddr_addr[i]);
5800 COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i],
5801 save_reload_reg_used_in_output_addr[i]);
5802 COPY_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i],
5803 save_reload_reg_used_in_outaddr_addr[i]);
5807 /* If we thought we could inherit a reload, because it seemed that
5808 nothing else wanted the same reload register earlier in the insn,
5809 verify that assumption, now that all reloads have been assigned. */
5811 for (j = 0; j < n_reloads; j++)
5813 register int r = reload_order[j];
5815 if (reload_inherited[r] && reload_reg_rtx[r] != 0
5816 && ! reload_reg_free_before_p (true_regnum (reload_reg_rtx[r]),
5818 reload_when_needed[r]))
5819 reload_inherited[r] = 0;
5821 /* If we found a better place to reload from,
5822 validate it in the same fashion, if it is a reload reg. */
5823 if (reload_override_in[r]
5824 && (GET_CODE (reload_override_in[r]) == REG
5825 || GET_CODE (reload_override_in[r]) == SUBREG))
5827 int regno = true_regnum (reload_override_in[r]);
5828 if (spill_reg_order[regno] >= 0
5829 && ! reload_reg_free_before_p (regno, reload_opnum[r],
5830 reload_when_needed[r]))
5831 reload_override_in[r] = 0;
5835 /* Now that reload_override_in is known valid,
5836 actually override reload_in. */
5837 for (j = 0; j < n_reloads; j++)
5838 if (reload_override_in[j])
5839 reload_in[j] = reload_override_in[j];
5841 /* If this reload won't be done because it has been cancelled or is
5842 optional and not inherited, clear reload_reg_rtx so other
5843 routines (such as subst_reloads) don't get confused. */
5844 for (j = 0; j < n_reloads; j++)
5845 if (reload_reg_rtx[j] != 0
5846 && ((reload_optional[j] && ! reload_inherited[j])
5847 || (reload_in[j] == 0 && reload_out[j] == 0
5848 && ! reload_secondary_p[j])))
5850 int regno = true_regnum (reload_reg_rtx[j]);
5852 if (spill_reg_order[regno] >= 0)
5853 clear_reload_reg_in_use (regno, reload_opnum[j],
5854 reload_when_needed[j], reload_mode[j]);
5855 reload_reg_rtx[j] = 0;
5858 /* Record which pseudos and which spill regs have output reloads. */
5859 for (j = 0; j < n_reloads; j++)
5861 register int r = reload_order[j];
5863 i = reload_spill_index[r];
5865 /* I is nonneg if this reload used one of the spill regs.
5866 If reload_reg_rtx[r] is 0, this is an optional reload
5867 that we opted to ignore. */
5868 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG
5869 && reload_reg_rtx[r] != 0)
5871 register int nregno = REGNO (reload_out[r]);
5874 if (nregno < FIRST_PSEUDO_REGISTER)
5875 nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
5878 reg_has_output_reload[nregno + nr] = 1;
5882 nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
5884 SET_HARD_REG_BIT (reg_is_output_reload, spill_regs[i] + nr);
5887 if (reload_when_needed[r] != RELOAD_OTHER
5888 && reload_when_needed[r] != RELOAD_FOR_OUTPUT
5889 && reload_when_needed[r] != RELOAD_FOR_INSN)
5895 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5896 reloads of the same item for fear that we might not have enough reload
5897 registers. However, normally they will get the same reload register
5898 and hence actually need not be loaded twice.
5900 Here we check for the most common case of this phenomenon: when we have
5901 a number of reloads for the same object, each of which were allocated
5902 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5903 reload, and is not modified in the insn itself. If we find such,
5904 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5905 This will not increase the number of spill registers needed and will
5906 prevent redundant code. */
5909 merge_assigned_reloads (insn)
5914 /* Scan all the reloads looking for ones that only load values and
5915 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5916 assigned and not modified by INSN. */
5918 for (i = 0; i < n_reloads; i++)
5920 if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER
5921 || reload_out[i] != 0 || reload_reg_rtx[i] == 0
5922 || reg_set_p (reload_reg_rtx[i], insn))
5925 /* Look at all other reloads. Ensure that the only use of this
5926 reload_reg_rtx is in a reload that just loads the same value
5927 as we do. Note that any secondary reloads must be of the identical
5928 class since the values, modes, and result registers are the
5929 same, so we need not do anything with any secondary reloads. */
5931 for (j = 0; j < n_reloads; j++)
5933 if (i == j || reload_reg_rtx[j] == 0
5934 || ! reg_overlap_mentioned_p (reload_reg_rtx[j],
5938 /* If the reload regs aren't exactly the same (e.g, different modes)
5939 or if the values are different, we can't merge anything with this
5942 if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
5943 || reload_out[j] != 0 || reload_in[j] == 0
5944 || ! rtx_equal_p (reload_in[i], reload_in[j]))
5948 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5949 we, in fact, found any matching reloads. */
5953 for (j = 0; j < n_reloads; j++)
5954 if (i != j && reload_reg_rtx[j] != 0
5955 && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j]))
5957 reload_when_needed[i] = RELOAD_OTHER;
5959 transfer_replacements (i, j);
5962 /* If this is now RELOAD_OTHER, look for any reloads that load
5963 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5964 if they were for inputs, RELOAD_OTHER for outputs. Note that
5965 this test is equivalent to looking for reloads for this operand
5968 if (reload_when_needed[i] == RELOAD_OTHER)
5969 for (j = 0; j < n_reloads; j++)
5970 if (reload_in[j] != 0
5971 && reload_when_needed[i] != RELOAD_OTHER
5972 && reg_overlap_mentioned_for_reload_p (reload_in[j],
5974 reload_when_needed[j]
5975 = ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
5976 || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS)
5977 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
5983 /* Output insns to reload values in and out of the chosen reload regs. */
5986 emit_reload_insns (insn)
5990 rtx input_reload_insns[MAX_RECOG_OPERANDS];
5991 rtx other_input_address_reload_insns = 0;
5992 rtx other_input_reload_insns = 0;
5993 rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
5994 rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5995 rtx output_reload_insns[MAX_RECOG_OPERANDS];
5996 rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
5997 rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5998 rtx operand_reload_insns = 0;
5999 rtx other_operand_reload_insns = 0;
6000 rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6001 rtx following_insn = NEXT_INSN (insn);
6002 rtx before_insn = insn;
6004 /* Values to be put in spill_reg_store are put here first. */
6005 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6007 for (j = 0; j < reload_n_operands; j++)
6008 input_reload_insns[j] = input_address_reload_insns[j]
6009 = inpaddr_address_reload_insns[j]
6010 = output_reload_insns[j] = output_address_reload_insns[j]
6011 = outaddr_address_reload_insns[j]
6012 = other_output_reload_insns[j] = 0;
6014 /* Now output the instructions to copy the data into and out of the
6015 reload registers. Do these in the order that the reloads were reported,
6016 since reloads of base and index registers precede reloads of operands
6017 and the operands may need the base and index registers reloaded. */
6019 for (j = 0; j < n_reloads; j++)
6022 rtx oldequiv_reg = 0;
6023 rtx this_reload_insn = 0;
6025 if (reload_spill_index[j] >= 0)
6026 new_spill_reg_store[reload_spill_index[j]] = 0;
6029 if (old != 0 && ! reload_inherited[j]
6030 && ! rtx_equal_p (reload_reg_rtx[j], old)
6031 && reload_reg_rtx[j] != 0)
6033 register rtx reloadreg = reload_reg_rtx[j];
6035 enum machine_mode mode;
6038 /* Determine the mode to reload in.
6039 This is very tricky because we have three to choose from.
6040 There is the mode the insn operand wants (reload_inmode[J]).
6041 There is the mode of the reload register RELOADREG.
6042 There is the intrinsic mode of the operand, which we could find
6043 by stripping some SUBREGs.
6044 It turns out that RELOADREG's mode is irrelevant:
6045 we can change that arbitrarily.
6047 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6048 then the reload reg may not support QImode moves, so use SImode.
6049 If foo is in memory due to spilling a pseudo reg, this is safe,
6050 because the QImode value is in the least significant part of a
6051 slot big enough for a SImode. If foo is some other sort of
6052 memory reference, then it is impossible to reload this case,
6053 so previous passes had better make sure this never happens.
6055 Then consider a one-word union which has SImode and one of its
6056 members is a float, being fetched as (SUBREG:SF union:SI).
6057 We must fetch that as SFmode because we could be loading into
6058 a float-only register. In this case OLD's mode is correct.
6060 Consider an immediate integer: it has VOIDmode. Here we need
6061 to get a mode from something else.
6063 In some cases, there is a fourth mode, the operand's
6064 containing mode. If the insn specifies a containing mode for
6065 this operand, it overrides all others.
6067 I am not sure whether the algorithm here is always right,
6068 but it does the right things in those cases. */
6070 mode = GET_MODE (old);
6071 if (mode == VOIDmode)
6072 mode = reload_inmode[j];
6074 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6075 /* If we need a secondary register for this operation, see if
6076 the value is already in a register in that class. Don't
6077 do this if the secondary register will be used as a scratch
6080 if (reload_secondary_in_reload[j] >= 0
6081 && reload_secondary_in_icode[j] == CODE_FOR_nothing
6084 = find_equiv_reg (old, insn,
6085 reload_reg_class[reload_secondary_in_reload[j]],
6086 -1, NULL_PTR, 0, mode);
6089 /* If reloading from memory, see if there is a register
6090 that already holds the same value. If so, reload from there.
6091 We can pass 0 as the reload_reg_p argument because
6092 any other reload has either already been emitted,
6093 in which case find_equiv_reg will see the reload-insn,
6094 or has yet to be emitted, in which case it doesn't matter
6095 because we will use this equiv reg right away. */
6097 if (oldequiv == 0 && optimize
6098 && (GET_CODE (old) == MEM
6099 || (GET_CODE (old) == REG
6100 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6101 && reg_renumber[REGNO (old)] < 0)))
6102 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6103 -1, NULL_PTR, 0, mode);
6107 int regno = true_regnum (oldequiv);
6109 /* If OLDEQUIV is a spill register, don't use it for this
6110 if any other reload needs it at an earlier stage of this insn
6111 or at this stage. */
6112 if (spill_reg_order[regno] >= 0
6113 && (! reload_reg_free_p (regno, reload_opnum[j],
6114 reload_when_needed[j])
6115 || ! reload_reg_free_before_p (regno, reload_opnum[j],
6116 reload_when_needed[j])))
6119 /* If OLDEQUIV is not a spill register,
6120 don't use it if any other reload wants it. */
6121 if (spill_reg_order[regno] < 0)
6124 for (k = 0; k < n_reloads; k++)
6125 if (reload_reg_rtx[k] != 0 && k != j
6126 && reg_overlap_mentioned_for_reload_p (reload_reg_rtx[k],
6134 /* If it is no cheaper to copy from OLDEQUIV into the
6135 reload register than it would be to move from memory,
6136 don't use it. Likewise, if we need a secondary register
6140 && ((REGNO_REG_CLASS (regno) != reload_reg_class[j]
6141 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
6142 reload_reg_class[j])
6143 >= MEMORY_MOVE_COST (mode)))
6144 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6145 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6149 #ifdef SECONDARY_MEMORY_NEEDED
6150 || SECONDARY_MEMORY_NEEDED (reload_reg_class[j],
6151 REGNO_REG_CLASS (regno),
6160 else if (GET_CODE (oldequiv) == REG)
6161 oldequiv_reg = oldequiv;
6162 else if (GET_CODE (oldequiv) == SUBREG)
6163 oldequiv_reg = SUBREG_REG (oldequiv);
6165 /* If we are reloading from a register that was recently stored in
6166 with an output-reload, see if we can prove there was
6167 actually no need to store the old value in it. */
6169 if (optimize && GET_CODE (oldequiv) == REG
6170 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6171 && spill_reg_order[REGNO (oldequiv)] >= 0
6172 && spill_reg_store[spill_reg_order[REGNO (oldequiv)]] != 0
6173 && find_reg_note (insn, REG_DEAD, reload_in[j])
6174 /* This is unsafe if operand occurs more than once in current
6175 insn. Perhaps some occurrences weren't reloaded. */
6176 && count_occurrences (PATTERN (insn), reload_in[j]) == 1)
6177 delete_output_reload
6178 (insn, j, spill_reg_store[spill_reg_order[REGNO (oldequiv)]]);
6180 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6181 then load RELOADREG from OLDEQUIV. Note that we cannot use
6182 gen_lowpart_common since it can do the wrong thing when
6183 RELOADREG has a multi-word mode. Note that RELOADREG
6184 must always be a REG here. */
6186 if (GET_MODE (reloadreg) != mode)
6187 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
6188 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6189 oldequiv = SUBREG_REG (oldequiv);
6190 if (GET_MODE (oldequiv) != VOIDmode
6191 && mode != GET_MODE (oldequiv))
6192 oldequiv = gen_rtx (SUBREG, mode, oldequiv, 0);
6194 /* Switch to the right place to emit the reload insns. */
6195 switch (reload_when_needed[j])
6198 where = &other_input_reload_insns;
6200 case RELOAD_FOR_INPUT:
6201 where = &input_reload_insns[reload_opnum[j]];
6203 case RELOAD_FOR_INPUT_ADDRESS:
6204 where = &input_address_reload_insns[reload_opnum[j]];
6206 case RELOAD_FOR_INPADDR_ADDRESS:
6207 where = &inpaddr_address_reload_insns[reload_opnum[j]];
6209 case RELOAD_FOR_OUTPUT_ADDRESS:
6210 where = &output_address_reload_insns[reload_opnum[j]];
6212 case RELOAD_FOR_OUTADDR_ADDRESS:
6213 where = &outaddr_address_reload_insns[reload_opnum[j]];
6215 case RELOAD_FOR_OPERAND_ADDRESS:
6216 where = &operand_reload_insns;
6218 case RELOAD_FOR_OPADDR_ADDR:
6219 where = &other_operand_reload_insns;
6221 case RELOAD_FOR_OTHER_ADDRESS:
6222 where = &other_input_address_reload_insns;
6228 push_to_sequence (*where);
6231 /* Auto-increment addresses must be reloaded in a special way. */
6232 if (GET_CODE (oldequiv) == POST_INC
6233 || GET_CODE (oldequiv) == POST_DEC
6234 || GET_CODE (oldequiv) == PRE_INC
6235 || GET_CODE (oldequiv) == PRE_DEC)
6237 /* We are not going to bother supporting the case where a
6238 incremented register can't be copied directly from
6239 OLDEQUIV since this seems highly unlikely. */
6240 if (reload_secondary_in_reload[j] >= 0)
6242 /* Prevent normal processing of this reload. */
6244 /* Output a special code sequence for this case. */
6245 inc_for_reload (reloadreg, oldequiv, reload_inc[j]);
6248 /* If we are reloading a pseudo-register that was set by the previous
6249 insn, see if we can get rid of that pseudo-register entirely
6250 by redirecting the previous insn into our reload register. */
6252 else if (optimize && GET_CODE (old) == REG
6253 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6254 && dead_or_set_p (insn, old)
6255 /* This is unsafe if some other reload
6256 uses the same reg first. */
6257 && reload_reg_free_before_p (REGNO (reloadreg),
6259 reload_when_needed[j]))
6261 rtx temp = PREV_INSN (insn);
6262 while (temp && GET_CODE (temp) == NOTE)
6263 temp = PREV_INSN (temp);
6265 && GET_CODE (temp) == INSN
6266 && GET_CODE (PATTERN (temp)) == SET
6267 && SET_DEST (PATTERN (temp)) == old
6268 /* Make sure we can access insn_operand_constraint. */
6269 && asm_noperands (PATTERN (temp)) < 0
6270 /* This is unsafe if prev insn rejects our reload reg. */
6271 && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
6273 /* This is unsafe if operand occurs more than once in current
6274 insn. Perhaps some occurrences aren't reloaded. */
6275 && count_occurrences (PATTERN (insn), old) == 1
6276 /* Don't risk splitting a matching pair of operands. */
6277 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6279 /* Store into the reload register instead of the pseudo. */
6280 SET_DEST (PATTERN (temp)) = reloadreg;
6281 /* If these are the only uses of the pseudo reg,
6282 pretend for GDB it lives in the reload reg we used. */
6283 if (REG_N_DEATHS (REGNO (old)) == 1
6284 && REG_N_SETS (REGNO (old)) == 1)
6286 reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
6287 alter_reg (REGNO (old), -1);
6293 /* We can't do that, so output an insn to load RELOADREG. */
6297 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6298 rtx second_reload_reg = 0;
6299 enum insn_code icode;
6301 /* If we have a secondary reload, pick up the secondary register
6302 and icode, if any. If OLDEQUIV and OLD are different or
6303 if this is an in-out reload, recompute whether or not we
6304 still need a secondary register and what the icode should
6305 be. If we still need a secondary register and the class or
6306 icode is different, go back to reloading from OLD if using
6307 OLDEQUIV means that we got the wrong type of register. We
6308 cannot have different class or icode due to an in-out reload
6309 because we don't make such reloads when both the input and
6310 output need secondary reload registers. */
6312 if (reload_secondary_in_reload[j] >= 0)
6314 int secondary_reload = reload_secondary_in_reload[j];
6315 rtx real_oldequiv = oldequiv;
6318 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6319 and similarly for OLD.
6320 See comments in get_secondary_reload in reload.c. */
6321 if (GET_CODE (oldequiv) == REG
6322 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6323 && reg_equiv_mem[REGNO (oldequiv)] != 0)
6324 real_oldequiv = reg_equiv_mem[REGNO (oldequiv)];
6326 if (GET_CODE (old) == REG
6327 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6328 && reg_equiv_mem[REGNO (old)] != 0)
6329 real_old = reg_equiv_mem[REGNO (old)];
6331 second_reload_reg = reload_reg_rtx[secondary_reload];
6332 icode = reload_secondary_in_icode[j];
6334 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6335 || (reload_in[j] != 0 && reload_out[j] != 0))
6337 enum reg_class new_class
6338 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6339 mode, real_oldequiv);
6341 if (new_class == NO_REGS)
6342 second_reload_reg = 0;
6345 enum insn_code new_icode;
6346 enum machine_mode new_mode;
6348 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6349 REGNO (second_reload_reg)))
6350 oldequiv = old, real_oldequiv = real_old;
6353 new_icode = reload_in_optab[(int) mode];
6354 if (new_icode != CODE_FOR_nothing
6355 && ((insn_operand_predicate[(int) new_icode][0]
6356 && ! ((*insn_operand_predicate[(int) new_icode][0])
6358 || (insn_operand_predicate[(int) new_icode][1]
6359 && ! ((*insn_operand_predicate[(int) new_icode][1])
6360 (real_oldequiv, mode)))))
6361 new_icode = CODE_FOR_nothing;
6363 if (new_icode == CODE_FOR_nothing)
6366 new_mode = insn_operand_mode[(int) new_icode][2];
6368 if (GET_MODE (second_reload_reg) != new_mode)
6370 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6372 oldequiv = old, real_oldequiv = real_old;
6375 = gen_rtx (REG, new_mode,
6376 REGNO (second_reload_reg));
6382 /* If we still need a secondary reload register, check
6383 to see if it is being used as a scratch or intermediate
6384 register and generate code appropriately. If we need
6385 a scratch register, use REAL_OLDEQUIV since the form of
6386 the insn may depend on the actual address if it is
6389 if (second_reload_reg)
6391 if (icode != CODE_FOR_nothing)
6393 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6394 second_reload_reg));
6399 /* See if we need a scratch register to load the
6400 intermediate register (a tertiary reload). */
6401 enum insn_code tertiary_icode
6402 = reload_secondary_in_icode[secondary_reload];
6404 if (tertiary_icode != CODE_FOR_nothing)
6406 rtx third_reload_reg
6407 = reload_reg_rtx[reload_secondary_in_reload[secondary_reload]];
6409 emit_insn ((GEN_FCN (tertiary_icode)
6410 (second_reload_reg, real_oldequiv,
6411 third_reload_reg)));
6414 gen_reload (second_reload_reg, oldequiv,
6416 reload_when_needed[j]);
6418 oldequiv = second_reload_reg;
6424 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6425 gen_reload (reloadreg, oldequiv, reload_opnum[j],
6426 reload_when_needed[j]);
6428 #if defined(SECONDARY_INPUT_RELOAD_CLASS) && defined(PRESERVE_DEATH_INFO_REGNO_P)
6429 /* We may have to make a REG_DEAD note for the secondary reload
6430 register in the insns we just made. Find the last insn that
6431 mentioned the register. */
6432 if (! special && second_reload_reg
6433 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reload_reg)))
6437 for (prev = get_last_insn (); prev;
6438 prev = PREV_INSN (prev))
6439 if (GET_RTX_CLASS (GET_CODE (prev) == 'i')
6440 && reg_overlap_mentioned_for_reload_p (second_reload_reg,
6443 REG_NOTES (prev) = gen_rtx (EXPR_LIST, REG_DEAD,
6452 this_reload_insn = get_last_insn ();
6453 /* End this sequence. */
6454 *where = get_insns ();
6458 /* Add a note saying the input reload reg
6459 dies in this insn, if anyone cares. */
6460 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6462 && reload_reg_rtx[j] != old
6463 && reload_reg_rtx[j] != 0
6464 && reload_out[j] == 0
6465 && ! reload_inherited[j]
6466 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j])))
6468 register rtx reloadreg = reload_reg_rtx[j];
6471 /* We can't abort here because we need to support this for sched.c.
6472 It's not terrible to miss a REG_DEAD note, but we should try
6473 to figure out how to do this correctly. */
6474 /* The code below is incorrect for address-only reloads. */
6475 if (reload_when_needed[j] != RELOAD_OTHER
6476 && reload_when_needed[j] != RELOAD_FOR_INPUT)
6480 /* Add a death note to this insn, for an input reload. */
6482 if ((reload_when_needed[j] == RELOAD_OTHER
6483 || reload_when_needed[j] == RELOAD_FOR_INPUT)
6484 && ! dead_or_set_p (insn, reloadreg))
6486 = gen_rtx (EXPR_LIST, REG_DEAD,
6487 reloadreg, REG_NOTES (insn));
6490 /* When we inherit a reload, the last marked death of the reload reg
6491 may no longer really be a death. */
6492 if (reload_reg_rtx[j] != 0
6493 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j]))
6494 && reload_inherited[j])
6496 /* Handle inheriting an output reload.
6497 Remove the death note from the output reload insn. */
6498 if (reload_spill_index[j] >= 0
6499 && GET_CODE (reload_in[j]) == REG
6500 && spill_reg_store[reload_spill_index[j]] != 0
6501 && find_regno_note (spill_reg_store[reload_spill_index[j]],
6502 REG_DEAD, REGNO (reload_reg_rtx[j])))
6503 remove_death (REGNO (reload_reg_rtx[j]),
6504 spill_reg_store[reload_spill_index[j]]);
6505 /* Likewise for input reloads that were inherited. */
6506 else if (reload_spill_index[j] >= 0
6507 && GET_CODE (reload_in[j]) == REG
6508 && spill_reg_store[reload_spill_index[j]] == 0
6509 && reload_inheritance_insn[j] != 0
6510 && find_regno_note (reload_inheritance_insn[j], REG_DEAD,
6511 REGNO (reload_reg_rtx[j])))
6512 remove_death (REGNO (reload_reg_rtx[j]),
6513 reload_inheritance_insn[j]);
6518 /* We got this register from find_equiv_reg.
6519 Search back for its last death note and get rid of it.
6520 But don't search back too far.
6521 Don't go past a place where this reg is set,
6522 since a death note before that remains valid. */
6523 for (prev = PREV_INSN (insn);
6524 prev && GET_CODE (prev) != CODE_LABEL;
6525 prev = PREV_INSN (prev))
6526 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
6527 && dead_or_set_p (prev, reload_reg_rtx[j]))
6529 if (find_regno_note (prev, REG_DEAD,
6530 REGNO (reload_reg_rtx[j])))
6531 remove_death (REGNO (reload_reg_rtx[j]), prev);
6537 /* We might have used find_equiv_reg above to choose an alternate
6538 place from which to reload. If so, and it died, we need to remove
6539 that death and move it to one of the insns we just made. */
6541 if (oldequiv_reg != 0
6542 && PRESERVE_DEATH_INFO_REGNO_P (true_regnum (oldequiv_reg)))
6546 for (prev = PREV_INSN (insn); prev && GET_CODE (prev) != CODE_LABEL;
6547 prev = PREV_INSN (prev))
6548 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
6549 && dead_or_set_p (prev, oldequiv_reg))
6551 if (find_regno_note (prev, REG_DEAD, REGNO (oldequiv_reg)))
6553 for (prev1 = this_reload_insn;
6554 prev1; prev1 = PREV_INSN (prev1))
6555 if (GET_RTX_CLASS (GET_CODE (prev1) == 'i')
6556 && reg_overlap_mentioned_for_reload_p (oldequiv_reg,
6559 REG_NOTES (prev1) = gen_rtx (EXPR_LIST, REG_DEAD,
6564 remove_death (REGNO (oldequiv_reg), prev);
6571 /* If we are reloading a register that was recently stored in with an
6572 output-reload, see if we can prove there was
6573 actually no need to store the old value in it. */
6575 if (optimize && reload_inherited[j] && reload_spill_index[j] >= 0
6576 && reload_in[j] != 0
6577 && GET_CODE (reload_in[j]) == REG
6579 /* There doesn't seem to be any reason to restrict this to pseudos
6580 and doing so loses in the case where we are copying from a
6581 register of the wrong class. */
6582 && REGNO (reload_in[j]) >= FIRST_PSEUDO_REGISTER
6584 && spill_reg_store[reload_spill_index[j]] != 0
6585 /* This is unsafe if some other reload uses the same reg first. */
6586 && reload_reg_free_before_p (spill_regs[reload_spill_index[j]],
6587 reload_opnum[j], reload_when_needed[j])
6588 && dead_or_set_p (insn, reload_in[j])
6589 /* This is unsafe if operand occurs more than once in current
6590 insn. Perhaps some occurrences weren't reloaded. */
6591 && count_occurrences (PATTERN (insn), reload_in[j]) == 1)
6592 delete_output_reload (insn, j,
6593 spill_reg_store[reload_spill_index[j]]);
6595 /* Input-reloading is done. Now do output-reloading,
6596 storing the value from the reload-register after the main insn
6597 if reload_out[j] is nonzero.
6599 ??? At some point we need to support handling output reloads of
6600 JUMP_INSNs or insns that set cc0. */
6601 old = reload_out[j];
6603 && reload_reg_rtx[j] != old
6604 && reload_reg_rtx[j] != 0)
6606 register rtx reloadreg = reload_reg_rtx[j];
6607 register rtx second_reloadreg = 0;
6609 enum machine_mode mode;
6612 /* An output operand that dies right away does need a reload,
6613 but need not be copied from it. Show the new location in the
6615 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6616 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6618 XEXP (note, 0) = reload_reg_rtx[j];
6621 /* Likewise for a SUBREG of an operand that dies. */
6622 else if (GET_CODE (old) == SUBREG
6623 && GET_CODE (SUBREG_REG (old)) == REG
6624 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6627 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6631 else if (GET_CODE (old) == SCRATCH)
6632 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6633 but we don't want to make an output reload. */
6637 /* Strip off of OLD any size-increasing SUBREGs such as
6638 (SUBREG:SI foo:QI 0). */
6640 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
6641 && (GET_MODE_SIZE (GET_MODE (old))
6642 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
6643 old = SUBREG_REG (old);
6646 /* If is a JUMP_INSN, we can't support output reloads yet. */
6647 if (GET_CODE (insn) == JUMP_INSN)
6650 if (reload_when_needed[j] == RELOAD_OTHER)
6653 push_to_sequence (output_reload_insns[reload_opnum[j]]);
6655 /* Determine the mode to reload in.
6656 See comments above (for input reloading). */
6658 mode = GET_MODE (old);
6659 if (mode == VOIDmode)
6661 /* VOIDmode should never happen for an output. */
6662 if (asm_noperands (PATTERN (insn)) < 0)
6663 /* It's the compiler's fault. */
6664 fatal_insn ("VOIDmode on an output", insn);
6665 error_for_asm (insn, "output operand is constant in `asm'");
6666 /* Prevent crash--use something we know is valid. */
6668 old = gen_rtx (REG, mode, REGNO (reloadreg));
6671 if (GET_MODE (reloadreg) != mode)
6672 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
6674 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6676 /* If we need two reload regs, set RELOADREG to the intermediate
6677 one, since it will be stored into OLD. We might need a secondary
6678 register only for an input reload, so check again here. */
6680 if (reload_secondary_out_reload[j] >= 0)
6684 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6685 && reg_equiv_mem[REGNO (old)] != 0)
6686 real_old = reg_equiv_mem[REGNO (old)];
6688 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
6692 second_reloadreg = reloadreg;
6693 reloadreg = reload_reg_rtx[reload_secondary_out_reload[j]];
6695 /* See if RELOADREG is to be used as a scratch register
6696 or as an intermediate register. */
6697 if (reload_secondary_out_icode[j] != CODE_FOR_nothing)
6699 emit_insn ((GEN_FCN (reload_secondary_out_icode[j])
6700 (real_old, second_reloadreg, reloadreg)));
6705 /* See if we need both a scratch and intermediate reload
6708 int secondary_reload = reload_secondary_out_reload[j];
6709 enum insn_code tertiary_icode
6710 = reload_secondary_out_icode[secondary_reload];
6712 if (GET_MODE (reloadreg) != mode)
6713 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
6715 if (tertiary_icode != CODE_FOR_nothing)
6718 = reload_reg_rtx[reload_secondary_out_reload[secondary_reload]];
6721 /* Copy primary reload reg to secondary reload reg.
6722 (Note that these have been swapped above, then
6723 secondary reload reg to OLD using our insn. */
6725 /* If REAL_OLD is a paradoxical SUBREG, remove it
6726 and try to put the opposite SUBREG on
6728 if (GET_CODE (real_old) == SUBREG
6729 && (GET_MODE_SIZE (GET_MODE (real_old))
6730 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6731 && 0 != (tem = gen_lowpart_common
6732 (GET_MODE (SUBREG_REG (real_old)),
6734 real_old = SUBREG_REG (real_old), reloadreg = tem;
6736 gen_reload (reloadreg, second_reloadreg,
6737 reload_opnum[j], reload_when_needed[j]);
6738 emit_insn ((GEN_FCN (tertiary_icode)
6739 (real_old, reloadreg, third_reloadreg)));
6744 /* Copy between the reload regs here and then to
6747 gen_reload (reloadreg, second_reloadreg,
6748 reload_opnum[j], reload_when_needed[j]);
6754 /* Output the last reload insn. */
6756 gen_reload (old, reloadreg, reload_opnum[j],
6757 reload_when_needed[j]);
6759 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6760 /* If final will look at death notes for this reg,
6761 put one on the last output-reload insn to use it. Similarly
6762 for any secondary register. */
6763 if (PRESERVE_DEATH_INFO_REGNO_P (REGNO (reloadreg)))
6764 for (p = get_last_insn (); p; p = PREV_INSN (p))
6765 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
6766 && reg_overlap_mentioned_for_reload_p (reloadreg,
6768 REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
6769 reloadreg, REG_NOTES (p));
6771 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6772 if (! special && second_reloadreg
6773 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reloadreg)))
6774 for (p = get_last_insn (); p; p = PREV_INSN (p))
6775 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
6776 && reg_overlap_mentioned_for_reload_p (second_reloadreg,
6778 REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
6779 second_reloadreg, REG_NOTES (p));
6782 /* Look at all insns we emitted, just to be safe. */
6783 for (p = get_insns (); p; p = NEXT_INSN (p))
6784 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
6786 /* If this output reload doesn't come from a spill reg,
6787 clear any memory of reloaded copies of the pseudo reg.
6788 If this output reload comes from a spill reg,
6789 reg_has_output_reload will make this do nothing. */
6790 note_stores (PATTERN (p), forget_old_reloads_1);
6792 if (reg_mentioned_p (reload_reg_rtx[j], PATTERN (p))
6793 && reload_spill_index[j] >= 0)
6794 new_spill_reg_store[reload_spill_index[j]] = p;
6797 if (reload_when_needed[j] == RELOAD_OTHER)
6799 emit_insns (other_output_reload_insns[reload_opnum[j]]);
6800 other_output_reload_insns[reload_opnum[j]] = get_insns ();
6803 output_reload_insns[reload_opnum[j]] = get_insns ();
6809 /* Now write all the insns we made for reloads in the order expected by
6810 the allocation functions. Prior to the insn being reloaded, we write
6811 the following reloads:
6813 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6815 RELOAD_OTHER reloads.
6817 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6818 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6819 RELOAD_FOR_INPUT reload for the operand.
6821 RELOAD_FOR_OPADDR_ADDRS reloads.
6823 RELOAD_FOR_OPERAND_ADDRESS reloads.
6825 After the insn being reloaded, we write the following:
6827 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6828 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6829 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6830 reloads for the operand. The RELOAD_OTHER output reloads are
6831 output in descending order by reload number. */
6833 emit_insns_before (other_input_address_reload_insns, before_insn);
6834 emit_insns_before (other_input_reload_insns, before_insn);
6836 for (j = 0; j < reload_n_operands; j++)
6838 emit_insns_before (inpaddr_address_reload_insns[j], before_insn);
6839 emit_insns_before (input_address_reload_insns[j], before_insn);
6840 emit_insns_before (input_reload_insns[j], before_insn);
6843 emit_insns_before (other_operand_reload_insns, before_insn);
6844 emit_insns_before (operand_reload_insns, before_insn);
6846 for (j = 0; j < reload_n_operands; j++)
6848 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
6849 emit_insns_before (output_address_reload_insns[j], following_insn);
6850 emit_insns_before (output_reload_insns[j], following_insn);
6851 emit_insns_before (other_output_reload_insns[j], following_insn);
6854 /* Move death notes from INSN
6855 to output-operand-address and output reload insns. */
6856 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6859 /* Loop over those insns, last ones first. */
6860 for (insn1 = PREV_INSN (following_insn); insn1 != insn;
6861 insn1 = PREV_INSN (insn1))
6862 if (GET_CODE (insn1) == INSN && GET_CODE (PATTERN (insn1)) == SET)
6864 rtx source = SET_SRC (PATTERN (insn1));
6865 rtx dest = SET_DEST (PATTERN (insn1));
6867 /* The note we will examine next. */
6868 rtx reg_notes = REG_NOTES (insn);
6869 /* The place that pointed to this note. */
6870 rtx *prev_reg_note = ®_NOTES (insn);
6872 /* If the note is for something used in the source of this
6873 reload insn, or in the output address, move the note. */
6876 rtx next_reg_notes = XEXP (reg_notes, 1);
6877 if (REG_NOTE_KIND (reg_notes) == REG_DEAD
6878 && GET_CODE (XEXP (reg_notes, 0)) == REG
6879 && ((GET_CODE (dest) != REG
6880 && reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
6882 || reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
6885 *prev_reg_note = next_reg_notes;
6886 XEXP (reg_notes, 1) = REG_NOTES (insn1);
6887 REG_NOTES (insn1) = reg_notes;
6890 prev_reg_note = &XEXP (reg_notes, 1);
6892 reg_notes = next_reg_notes;
6898 /* For all the spill regs newly reloaded in this instruction,
6899 record what they were reloaded from, so subsequent instructions
6900 can inherit the reloads.
6902 Update spill_reg_store for the reloads of this insn.
6903 Copy the elements that were updated in the loop above. */
6905 for (j = 0; j < n_reloads; j++)
6907 register int r = reload_order[j];
6908 register int i = reload_spill_index[r];
6910 /* I is nonneg if this reload used one of the spill regs.
6911 If reload_reg_rtx[r] is 0, this is an optional reload
6912 that we opted to ignore. */
6914 if (i >= 0 && reload_reg_rtx[r] != 0)
6917 = HARD_REGNO_NREGS (spill_regs[i], GET_MODE (reload_reg_rtx[r]));
6919 int part_reaches_end = 0;
6920 int all_reaches_end = 1;
6922 /* For a multi register reload, we need to check if all or part
6923 of the value lives to the end. */
6924 for (k = 0; k < nr; k++)
6926 if (reload_reg_reaches_end_p (spill_regs[i] + k, reload_opnum[r],
6927 reload_when_needed[r]))
6928 part_reaches_end = 1;
6930 all_reaches_end = 0;
6933 /* Ignore reloads that don't reach the end of the insn in
6935 if (all_reaches_end)
6937 /* First, clear out memory of what used to be in this spill reg.
6938 If consecutive registers are used, clear them all. */
6940 for (k = 0; k < nr; k++)
6942 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] = -1;
6943 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = 0;
6946 /* Maybe the spill reg contains a copy of reload_out. */
6947 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
6949 register int nregno = REGNO (reload_out[r]);
6950 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6951 : HARD_REGNO_NREGS (nregno,
6952 GET_MODE (reload_reg_rtx[r])));
6954 spill_reg_store[i] = new_spill_reg_store[i];
6955 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
6957 /* If NREGNO is a hard register, it may occupy more than
6958 one register. If it does, say what is in the
6959 rest of the registers assuming that both registers
6960 agree on how many words the object takes. If not,
6961 invalidate the subsequent registers. */
6963 if (nregno < FIRST_PSEUDO_REGISTER)
6964 for (k = 1; k < nnr; k++)
6965 reg_last_reload_reg[nregno + k]
6968 reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
6969 REGNO (reload_reg_rtx[r]) + k)
6972 /* Now do the inverse operation. */
6973 for (k = 0; k < nr; k++)
6975 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
6976 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
6979 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = insn;
6983 /* Maybe the spill reg contains a copy of reload_in. Only do
6984 something if there will not be an output reload for
6985 the register being reloaded. */
6986 else if (reload_out[r] == 0
6987 && reload_in[r] != 0
6988 && ((GET_CODE (reload_in[r]) == REG
6989 && ! reg_has_output_reload[REGNO (reload_in[r])])
6990 || (GET_CODE (reload_in_reg[r]) == REG
6991 && ! reg_has_output_reload[REGNO (reload_in_reg[r])])))
6993 register int nregno;
6996 if (GET_CODE (reload_in[r]) == REG)
6997 nregno = REGNO (reload_in[r]);
6999 nregno = REGNO (reload_in_reg[r]);
7001 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7002 : HARD_REGNO_NREGS (nregno,
7003 GET_MODE (reload_reg_rtx[r])));
7005 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
7007 if (nregno < FIRST_PSEUDO_REGISTER)
7008 for (k = 1; k < nnr; k++)
7009 reg_last_reload_reg[nregno + k]
7012 reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
7013 REGNO (reload_reg_rtx[r]) + k)
7016 /* Unless we inherited this reload, show we haven't
7017 recently done a store. */
7018 if (! reload_inherited[r])
7019 spill_reg_store[i] = 0;
7021 for (k = 0; k < nr; k++)
7023 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
7024 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7027 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]]
7033 /* However, if part of the reload reaches the end, then we must
7034 invalidate the old info for the part that survives to the end. */
7035 else if (part_reaches_end)
7037 for (k = 0; k < nr; k++)
7038 if (reload_reg_reaches_end_p (spill_regs[i] + k,
7040 reload_when_needed[r]))
7042 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] = -1;
7043 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = 0;
7048 /* The following if-statement was #if 0'd in 1.34 (or before...).
7049 It's reenabled in 1.35 because supposedly nothing else
7050 deals with this problem. */
7052 /* If a register gets output-reloaded from a non-spill register,
7053 that invalidates any previous reloaded copy of it.
7054 But forget_old_reloads_1 won't get to see it, because
7055 it thinks only about the original insn. So invalidate it here. */
7056 if (i < 0 && reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
7058 register int nregno = REGNO (reload_out[r]);
7059 if (nregno >= FIRST_PSEUDO_REGISTER)
7060 reg_last_reload_reg[nregno] = 0;
7063 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (reload_out[r]));
7065 while (num_regs-- > 0)
7066 reg_last_reload_reg[nregno + num_regs] = 0;
7072 /* Emit code to perform a reload from IN (which may be a reload register) to
7073 OUT (which may also be a reload register). IN or OUT is from operand
7074 OPNUM with reload type TYPE.
7076 Returns first insn emitted. */
7079 gen_reload (out, in, opnum, type)
7083 enum reload_type type;
7085 rtx last = get_last_insn ();
7088 /* If IN is a paradoxical SUBREG, remove it and try to put the
7089 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7090 if (GET_CODE (in) == SUBREG
7091 && (GET_MODE_SIZE (GET_MODE (in))
7092 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7093 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7094 in = SUBREG_REG (in), out = tem;
7095 else if (GET_CODE (out) == SUBREG
7096 && (GET_MODE_SIZE (GET_MODE (out))
7097 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7098 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7099 out = SUBREG_REG (out), in = tem;
7101 /* How to do this reload can get quite tricky. Normally, we are being
7102 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7103 register that didn't get a hard register. In that case we can just
7104 call emit_move_insn.
7106 We can also be asked to reload a PLUS that adds a register or a MEM to
7107 another register, constant or MEM. This can occur during frame pointer
7108 elimination and while reloading addresses. This case is handled by
7109 trying to emit a single insn to perform the add. If it is not valid,
7110 we use a two insn sequence.
7112 Finally, we could be called to handle an 'o' constraint by putting
7113 an address into a register. In that case, we first try to do this
7114 with a named pattern of "reload_load_address". If no such pattern
7115 exists, we just emit a SET insn and hope for the best (it will normally
7116 be valid on machines that use 'o').
7118 This entire process is made complex because reload will never
7119 process the insns we generate here and so we must ensure that
7120 they will fit their constraints and also by the fact that parts of
7121 IN might be being reloaded separately and replaced with spill registers.
7122 Because of this, we are, in some sense, just guessing the right approach
7123 here. The one listed above seems to work.
7125 ??? At some point, this whole thing needs to be rethought. */
7127 if (GET_CODE (in) == PLUS
7128 && (GET_CODE (XEXP (in, 0)) == REG
7129 || GET_CODE (XEXP (in, 0)) == SUBREG
7130 || GET_CODE (XEXP (in, 0)) == MEM)
7131 && (GET_CODE (XEXP (in, 1)) == REG
7132 || GET_CODE (XEXP (in, 1)) == SUBREG
7133 || CONSTANT_P (XEXP (in, 1))
7134 || GET_CODE (XEXP (in, 1)) == MEM))
7136 /* We need to compute the sum of a register or a MEM and another
7137 register, constant, or MEM, and put it into the reload
7138 register. The best possible way of doing this is if the machine
7139 has a three-operand ADD insn that accepts the required operands.
7141 The simplest approach is to try to generate such an insn and see if it
7142 is recognized and matches its constraints. If so, it can be used.
7144 It might be better not to actually emit the insn unless it is valid,
7145 but we need to pass the insn as an operand to `recog' and
7146 `insn_extract' and it is simpler to emit and then delete the insn if
7147 not valid than to dummy things up. */
7149 rtx op0, op1, tem, insn;
7152 op0 = find_replacement (&XEXP (in, 0));
7153 op1 = find_replacement (&XEXP (in, 1));
7155 /* Since constraint checking is strict, commutativity won't be
7156 checked, so we need to do that here to avoid spurious failure
7157 if the add instruction is two-address and the second operand
7158 of the add is the same as the reload reg, which is frequently
7159 the case. If the insn would be A = B + A, rearrange it so
7160 it will be A = A + B as constrain_operands expects. */
7162 if (GET_CODE (XEXP (in, 1)) == REG
7163 && REGNO (out) == REGNO (XEXP (in, 1)))
7164 tem = op0, op0 = op1, op1 = tem;
7166 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7167 in = gen_rtx (PLUS, GET_MODE (in), op0, op1);
7169 insn = emit_insn (gen_rtx (SET, VOIDmode, out, in));
7170 code = recog_memoized (insn);
7174 insn_extract (insn);
7175 /* We want constrain operands to treat this insn strictly in
7176 its validity determination, i.e., the way it would after reload
7178 if (constrain_operands (code, 1))
7182 delete_insns_since (last);
7184 /* If that failed, we must use a conservative two-insn sequence.
7185 use move to copy constant, MEM, or pseudo register to the reload
7186 register since "move" will be able to handle an arbitrary operand,
7187 unlike add which can't, in general. Then add the registers.
7189 If there is another way to do this for a specific machine, a
7190 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7193 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7194 || (GET_CODE (op1) == REG
7195 && REGNO (op1) >= FIRST_PSEUDO_REGISTER))
7196 tem = op0, op0 = op1, op1 = tem;
7198 gen_reload (out, op0, opnum, type);
7200 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7201 This fixes a problem on the 32K where the stack pointer cannot
7202 be used as an operand of an add insn. */
7204 if (rtx_equal_p (op0, op1))
7207 insn = emit_insn (gen_add2_insn (out, op1));
7209 /* If that failed, copy the address register to the reload register.
7210 Then add the constant to the reload register. */
7212 code = recog_memoized (insn);
7216 insn_extract (insn);
7217 /* We want constrain operands to treat this insn strictly in
7218 its validity determination, i.e., the way it would after reload
7220 if (constrain_operands (code, 1))
7224 delete_insns_since (last);
7226 gen_reload (out, op1, opnum, type);
7227 emit_insn (gen_add2_insn (out, op0));
7230 #ifdef SECONDARY_MEMORY_NEEDED
7231 /* If we need a memory location to do the move, do it that way. */
7232 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7233 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7234 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7235 REGNO_REG_CLASS (REGNO (out)),
7238 /* Get the memory to use and rewrite both registers to its mode. */
7239 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7241 if (GET_MODE (loc) != GET_MODE (out))
7242 out = gen_rtx (REG, GET_MODE (loc), REGNO (out));
7244 if (GET_MODE (loc) != GET_MODE (in))
7245 in = gen_rtx (REG, GET_MODE (loc), REGNO (in));
7247 gen_reload (loc, in, opnum, type);
7248 gen_reload (out, loc, opnum, type);
7252 /* If IN is a simple operand, use gen_move_insn. */
7253 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7254 emit_insn (gen_move_insn (out, in));
7256 #ifdef HAVE_reload_load_address
7257 else if (HAVE_reload_load_address)
7258 emit_insn (gen_reload_load_address (out, in));
7261 /* Otherwise, just write (set OUT IN) and hope for the best. */
7263 emit_insn (gen_rtx (SET, VOIDmode, out, in));
7265 /* Return the first insn emitted.
7266 We can not just return get_last_insn, because there may have
7267 been multiple instructions emitted. Also note that gen_move_insn may
7268 emit more than one insn itself, so we can not assume that there is one
7269 insn emitted per emit_insn_before call. */
7271 return last ? NEXT_INSN (last) : get_insns ();
7274 /* Delete a previously made output-reload
7275 whose result we now believe is not needed.
7276 First we double-check.
7278 INSN is the insn now being processed.
7279 OUTPUT_RELOAD_INSN is the insn of the output reload.
7280 J is the reload-number for this insn. */
7283 delete_output_reload (insn, j, output_reload_insn)
7286 rtx output_reload_insn;
7290 /* Get the raw pseudo-register referred to. */
7292 rtx reg = reload_in[j];
7293 while (GET_CODE (reg) == SUBREG)
7294 reg = SUBREG_REG (reg);
7296 /* If the pseudo-reg we are reloading is no longer referenced
7297 anywhere between the store into it and here,
7298 and no jumps or labels intervene, then the value can get
7299 here through the reload reg alone.
7300 Otherwise, give up--return. */
7301 for (i1 = NEXT_INSN (output_reload_insn);
7302 i1 != insn; i1 = NEXT_INSN (i1))
7304 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7306 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7307 && reg_mentioned_p (reg, PATTERN (i1)))
7311 if (cannot_omit_stores[REGNO (reg)])
7314 /* If this insn will store in the pseudo again,
7315 the previous store can be removed. */
7316 if (reload_out[j] == reload_in[j])
7317 delete_insn (output_reload_insn);
7319 /* See if the pseudo reg has been completely replaced
7320 with reload regs. If so, delete the store insn
7321 and forget we had a stack slot for the pseudo. */
7322 else if (REG_N_DEATHS (REGNO (reg)) == 1
7323 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7324 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7328 /* We know that it was used only between here
7329 and the beginning of the current basic block.
7330 (We also know that the last use before INSN was
7331 the output reload we are thinking of deleting, but never mind that.)
7332 Search that range; see if any ref remains. */
7333 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7335 rtx set = single_set (i2);
7337 /* Uses which just store in the pseudo don't count,
7338 since if they are the only uses, they are dead. */
7339 if (set != 0 && SET_DEST (set) == reg)
7341 if (GET_CODE (i2) == CODE_LABEL
7342 || GET_CODE (i2) == JUMP_INSN)
7344 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7345 && reg_mentioned_p (reg, PATTERN (i2)))
7346 /* Some other ref remains;
7347 we can't do anything. */
7351 /* Delete the now-dead stores into this pseudo. */
7352 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7354 rtx set = single_set (i2);
7356 if (set != 0 && SET_DEST (set) == reg)
7358 /* This might be a basic block head,
7359 thus don't use delete_insn. */
7360 PUT_CODE (i2, NOTE);
7361 NOTE_SOURCE_FILE (i2) = 0;
7362 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7364 if (GET_CODE (i2) == CODE_LABEL
7365 || GET_CODE (i2) == JUMP_INSN)
7369 /* For the debugging info,
7370 say the pseudo lives in this reload reg. */
7371 reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
7372 alter_reg (REGNO (reg), -1);
7376 /* Output reload-insns to reload VALUE into RELOADREG.
7377 VALUE is an autoincrement or autodecrement RTX whose operand
7378 is a register or memory location;
7379 so reloading involves incrementing that location.
7381 INC_AMOUNT is the number to increment or decrement by (always positive).
7382 This cannot be deduced from VALUE. */
7385 inc_for_reload (reloadreg, value, inc_amount)
7390 /* REG or MEM to be copied and incremented. */
7391 rtx incloc = XEXP (value, 0);
7392 /* Nonzero if increment after copying. */
7393 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7399 /* No hard register is equivalent to this register after
7400 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7401 we could inc/dec that register as well (maybe even using it for
7402 the source), but I'm not sure it's worth worrying about. */
7403 if (GET_CODE (incloc) == REG)
7404 reg_last_reload_reg[REGNO (incloc)] = 0;
7406 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7407 inc_amount = - inc_amount;
7409 inc = GEN_INT (inc_amount);
7411 /* If this is post-increment, first copy the location to the reload reg. */
7413 emit_insn (gen_move_insn (reloadreg, incloc));
7415 /* See if we can directly increment INCLOC. Use a method similar to that
7418 last = get_last_insn ();
7419 add_insn = emit_insn (gen_rtx (SET, VOIDmode, incloc,
7420 gen_rtx (PLUS, GET_MODE (incloc),
7423 code = recog_memoized (add_insn);
7426 insn_extract (add_insn);
7427 if (constrain_operands (code, 1))
7429 /* If this is a pre-increment and we have incremented the value
7430 where it lives, copy the incremented value to RELOADREG to
7431 be used as an address. */
7434 emit_insn (gen_move_insn (reloadreg, incloc));
7440 delete_insns_since (last);
7442 /* If couldn't do the increment directly, must increment in RELOADREG.
7443 The way we do this depends on whether this is pre- or post-increment.
7444 For pre-increment, copy INCLOC to the reload register, increment it
7445 there, then save back. */
7449 emit_insn (gen_move_insn (reloadreg, incloc));
7450 emit_insn (gen_add2_insn (reloadreg, inc));
7451 emit_insn (gen_move_insn (incloc, reloadreg));
7456 Because this might be a jump insn or a compare, and because RELOADREG
7457 may not be available after the insn in an input reload, we must do
7458 the incrementation before the insn being reloaded for.
7460 We have already copied INCLOC to RELOADREG. Increment the copy in
7461 RELOADREG, save that back, then decrement RELOADREG so it has
7462 the original value. */
7464 emit_insn (gen_add2_insn (reloadreg, inc));
7465 emit_insn (gen_move_insn (incloc, reloadreg));
7466 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7472 /* Return 1 if we are certain that the constraint-string STRING allows
7473 the hard register REG. Return 0 if we can't be sure of this. */
7476 constraint_accepts_reg_p (string, reg)
7481 int regno = true_regnum (reg);
7484 /* Initialize for first alternative. */
7486 /* Check that each alternative contains `g' or `r'. */
7488 switch (c = *string++)
7491 /* If an alternative lacks `g' or `r', we lose. */
7494 /* If an alternative lacks `g' or `r', we lose. */
7497 /* Initialize for next alternative. */
7502 /* Any general reg wins for this alternative. */
7503 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7507 /* Any reg in specified class wins for this alternative. */
7509 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7511 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
7517 /* Return the number of places FIND appears within X, but don't count
7518 an occurrence if some SET_DEST is FIND. */
7521 count_occurrences (x, find)
7522 register rtx x, find;
7525 register enum rtx_code code;
7526 register char *format_ptr;
7534 code = GET_CODE (x);
7549 if (SET_DEST (x) == find)
7550 return count_occurrences (SET_SRC (x), find);
7557 format_ptr = GET_RTX_FORMAT (code);
7560 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7562 switch (*format_ptr++)
7565 count += count_occurrences (XEXP (x, i), find);
7569 if (XVEC (x, i) != NULL)
7571 for (j = 0; j < XVECLEN (x, i); j++)
7572 count += count_occurrences (XVECEXP (x, i, j), find);
7580 /* This array holds values which are equivalent to a hard register
7581 during reload_cse_regs. Each array element is an EXPR_LIST of
7582 values. Each time a hard register is set, we set the corresponding
7583 array element to the value. Each time a hard register is copied
7584 into memory, we add the memory location to the corresponding array
7585 element. We don't store values or memory addresses with side
7586 effects in this array.
7588 If the value is a CONST_INT, then the mode of the containing
7589 EXPR_LIST is the mode in which that CONST_INT was referenced.
7591 We sometimes clobber a specific entry in a list. In that case, we
7592 just set XEXP (list-entry, 0) to 0. */
7594 static rtx *reg_values;
7596 /* This is a preallocated REG rtx which we use as a temporary in
7597 reload_cse_invalidate_regno, so that we don't need to allocate a
7598 new one each time through a loop in that function. */
7600 static rtx invalidate_regno_rtx;
7602 /* This is a set of registers for which we must remove REG_DEAD notes in
7603 previous insns, because our modifications made them invalid. That can
7604 happen if we introduced the register into the current insn, or we deleted
7605 the current insn which used to set the register. */
7607 static HARD_REG_SET no_longer_dead_regs;
7609 /* Invalidate any entries in reg_values which depend on REGNO,
7610 including those for REGNO itself. This is called if REGNO is
7611 changing. If CLOBBER is true, then always forget anything we
7612 currently know about REGNO. MODE is the mode of the assignment to
7613 REGNO, which is used to determine how many hard registers are being
7614 changed. If MODE is VOIDmode, then only REGNO is being changed;
7615 this is used when invalidating call clobbered registers across a
7619 reload_cse_invalidate_regno (regno, mode, clobber)
7621 enum machine_mode mode;
7627 /* Our callers don't always go through true_regnum; we may see a
7628 pseudo-register here from a CLOBBER or the like. We probably
7629 won't ever see a pseudo-register that has a real register number,
7630 for we check anyhow for safety. */
7631 if (regno >= FIRST_PSEUDO_REGISTER)
7632 regno = reg_renumber[regno];
7636 if (mode == VOIDmode)
7637 endregno = regno + 1;
7639 endregno = regno + HARD_REGNO_NREGS (regno, mode);
7642 for (i = regno; i < endregno; i++)
7645 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
7649 for (x = reg_values[i]; x; x = XEXP (x, 1))
7651 if (XEXP (x, 0) != 0
7652 && refers_to_regno_p (regno, endregno, XEXP (x, 0), NULL_PTR))
7654 /* If this is the only entry on the list, clear
7655 reg_values[i]. Otherwise, just clear this entry on
7657 if (XEXP (x, 1) == 0 && x == reg_values[i])
7667 /* We must look at earlier registers, in case REGNO is part of a
7668 multi word value but is not the first register. If an earlier
7669 register has a value in a mode which overlaps REGNO, then we must
7670 invalidate that earlier register. Note that we do not need to
7671 check REGNO or later registers (we must not check REGNO itself,
7672 because we would incorrectly conclude that there was a conflict). */
7674 for (i = 0; i < regno; i++)
7678 for (x = reg_values[i]; x; x = XEXP (x, 1))
7680 if (XEXP (x, 0) != 0)
7682 PUT_MODE (invalidate_regno_rtx, GET_MODE (x));
7683 REGNO (invalidate_regno_rtx) = i;
7684 if (refers_to_regno_p (regno, endregno, invalidate_regno_rtx,
7687 reload_cse_invalidate_regno (i, VOIDmode, 1);
7695 /* The memory at address MEM_BASE is being changed.
7696 Return whether this change will invalidate VAL. */
7699 reload_cse_mem_conflict_p (mem_base, val)
7707 code = GET_CODE (val);
7710 /* Get rid of a few simple cases quickly. */
7723 if (GET_MODE (mem_base) == BLKmode
7724 || GET_MODE (val) == BLKmode)
7726 if (anti_dependence (val, mem_base))
7728 /* The address may contain nested MEMs. */
7735 fmt = GET_RTX_FORMAT (code);
7737 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7741 if (reload_cse_mem_conflict_p (mem_base, XEXP (val, i)))
7744 else if (fmt[i] == 'E')
7748 for (j = 0; j < XVECLEN (val, i); j++)
7749 if (reload_cse_mem_conflict_p (mem_base, XVECEXP (val, i, j)))
7757 /* Invalidate any entries in reg_values which are changed because of a
7758 store to MEM_RTX. If this is called because of a non-const call
7759 instruction, MEM_RTX is (mem:BLK const0_rtx). */
7762 reload_cse_invalidate_mem (mem_rtx)
7767 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
7771 for (x = reg_values[i]; x; x = XEXP (x, 1))
7773 if (XEXP (x, 0) != 0
7774 && reload_cse_mem_conflict_p (mem_rtx, XEXP (x, 0)))
7776 /* If this is the only entry on the list, clear
7777 reg_values[i]. Otherwise, just clear this entry on
7779 if (XEXP (x, 1) == 0 && x == reg_values[i])
7790 /* Invalidate DEST, which is being assigned to or clobbered. The
7791 second parameter exists so that this function can be passed to
7792 note_stores; it is ignored. */
7795 reload_cse_invalidate_rtx (dest, ignore)
7799 while (GET_CODE (dest) == STRICT_LOW_PART
7800 || GET_CODE (dest) == SIGN_EXTRACT
7801 || GET_CODE (dest) == ZERO_EXTRACT
7802 || GET_CODE (dest) == SUBREG)
7803 dest = XEXP (dest, 0);
7805 if (GET_CODE (dest) == REG)
7806 reload_cse_invalidate_regno (REGNO (dest), GET_MODE (dest), 1);
7807 else if (GET_CODE (dest) == MEM)
7808 reload_cse_invalidate_mem (dest);
7811 /* Possibly delete death notes on the insns before INSN if modifying INSN
7812 extended the lifespan of the registers. */
7815 reload_cse_delete_death_notes (insn)
7820 for (dreg = 0; dreg < FIRST_PSEUDO_REGISTER; dreg++)
7824 if (! TEST_HARD_REG_BIT (no_longer_dead_regs, dreg))
7827 for (trial = prev_nonnote_insn (insn);
7829 && GET_CODE (trial) != CODE_LABEL
7830 && GET_CODE (trial) != BARRIER);
7831 trial = prev_nonnote_insn (trial))
7833 if (find_regno_note (trial, REG_DEAD, dreg))
7835 remove_death (dreg, trial);
7842 /* Record that the current insn uses hard reg REGNO in mode MODE. This
7843 will be used in reload_cse_delete_death_notes to delete prior REG_DEAD
7844 notes for this register. */
7847 reload_cse_no_longer_dead (regno, mode)
7849 enum machine_mode mode;
7851 int nregs = HARD_REGNO_NREGS (regno, mode);
7854 SET_HARD_REG_BIT (no_longer_dead_regs, regno);
7860 /* Do a very simple CSE pass over the hard registers.
7862 This function detects no-op moves where we happened to assign two
7863 different pseudo-registers to the same hard register, and then
7864 copied one to the other. Reload will generate a useless
7865 instruction copying a register to itself.
7867 This function also detects cases where we load a value from memory
7868 into two different registers, and (if memory is more expensive than
7869 registers) changes it to simply copy the first register into the
7872 Another optimization is performed that scans the operands of each
7873 instruction to see whether the value is already available in a
7874 hard register. It then replaces the operand with the hard register
7875 if possible, much like an optional reload would. */
7878 reload_cse_regs (first)
7886 init_alias_analysis ();
7888 reg_values = (rtx *) alloca (FIRST_PSEUDO_REGISTER * sizeof (rtx));
7889 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
7892 /* Create our EXPR_LIST structures on reload_obstack, so that we can
7893 free them when we are done. */
7894 push_obstacks (&reload_obstack, &reload_obstack);
7895 firstobj = (char *) obstack_alloc (&reload_obstack, 0);
7897 /* We pass this to reload_cse_invalidate_mem to invalidate all of
7898 memory for a non-const call instruction. */
7899 callmem = gen_rtx (MEM, BLKmode, const0_rtx);
7901 /* This is used in reload_cse_invalidate_regno to avoid consing a
7902 new REG in a loop in that function. */
7903 invalidate_regno_rtx = gen_rtx (REG, VOIDmode, 0);
7905 for (insn = first; insn; insn = NEXT_INSN (insn))
7909 if (GET_CODE (insn) == CODE_LABEL)
7911 /* Forget all the register values at a code label. We don't
7912 try to do anything clever around jumps. */
7913 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
7919 #ifdef NON_SAVING_SETJMP
7920 if (NON_SAVING_SETJMP && GET_CODE (insn) == NOTE
7921 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
7923 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
7930 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
7933 CLEAR_HARD_REG_SET (no_longer_dead_regs);
7935 /* If this is a call instruction, forget anything stored in a
7936 call clobbered register, or, if this is not a const call, in
7938 if (GET_CODE (insn) == CALL_INSN)
7940 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
7941 if (call_used_regs[i])
7942 reload_cse_invalidate_regno (i, VOIDmode, 1);
7944 if (! CONST_CALL_P (insn))
7945 reload_cse_invalidate_mem (callmem);
7948 body = PATTERN (insn);
7949 if (GET_CODE (body) == SET)
7952 if (reload_cse_noop_set_p (body, insn))
7954 PUT_CODE (insn, NOTE);
7955 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
7956 NOTE_SOURCE_FILE (insn) = 0;
7957 reload_cse_delete_death_notes (insn);
7959 /* We're done with this insn. */
7963 /* It's not a no-op, but we can try to simplify it. */
7964 CLEAR_HARD_REG_SET (no_longer_dead_regs);
7965 count += reload_cse_simplify_set (body, insn);
7967 if (count > 0 && apply_change_group ())
7968 reload_cse_delete_death_notes (insn);
7969 else if (reload_cse_simplify_operands (insn))
7970 reload_cse_delete_death_notes (insn);
7972 reload_cse_record_set (body, body);
7974 else if (GET_CODE (body) == PARALLEL)
7978 /* If every action in a PARALLEL is a noop, we can delete
7979 the entire PARALLEL. */
7980 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
7981 if ((GET_CODE (XVECEXP (body, 0, i)) != SET
7982 || ! reload_cse_noop_set_p (XVECEXP (body, 0, i), insn))
7983 && GET_CODE (XVECEXP (body, 0, i)) != CLOBBER)
7987 PUT_CODE (insn, NOTE);
7988 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
7989 NOTE_SOURCE_FILE (insn) = 0;
7990 reload_cse_delete_death_notes (insn);
7992 /* We're done with this insn. */
7996 /* It's not a no-op, but we can try to simplify it. */
7997 CLEAR_HARD_REG_SET (no_longer_dead_regs);
7998 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
7999 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8000 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8002 if (count > 0 && apply_change_group ())
8003 reload_cse_delete_death_notes (insn);
8004 else if (reload_cse_simplify_operands (insn))
8005 reload_cse_delete_death_notes (insn);
8007 /* Look through the PARALLEL and record the values being
8008 set, if possible. Also handle any CLOBBERs. */
8009 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8011 rtx x = XVECEXP (body, 0, i);
8013 if (GET_CODE (x) == SET)
8014 reload_cse_record_set (x, body);
8016 note_stores (x, reload_cse_invalidate_rtx);
8020 note_stores (body, reload_cse_invalidate_rtx);
8023 /* Clobber any registers which appear in REG_INC notes. We
8024 could keep track of the changes to their values, but it is
8025 unlikely to help. */
8029 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
8030 if (REG_NOTE_KIND (x) == REG_INC)
8031 reload_cse_invalidate_rtx (XEXP (x, 0), NULL_RTX);
8035 /* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only
8036 after we have processed the insn. */
8037 if (GET_CODE (insn) == CALL_INSN)
8041 for (x = CALL_INSN_FUNCTION_USAGE (insn); x; x = XEXP (x, 1))
8042 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
8043 reload_cse_invalidate_rtx (XEXP (XEXP (x, 0), 0), NULL_RTX);
8047 /* Free all the temporary structures we created, and go back to the
8048 regular obstacks. */
8049 obstack_free (&reload_obstack, firstobj);
8053 /* Return whether the values known for REGNO are equal to VAL. MODE
8054 is the mode of the object that VAL is being copied to; this matters
8055 if VAL is a CONST_INT. */
8058 reload_cse_regno_equal_p (regno, val, mode)
8061 enum machine_mode mode;
8068 for (x = reg_values[regno]; x; x = XEXP (x, 1))
8069 if (XEXP (x, 0) != 0
8070 && rtx_equal_p (XEXP (x, 0), val)
8071 && (GET_CODE (val) != CONST_INT
8072 || mode == GET_MODE (x)
8073 || (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8074 /* On a big endian machine if the value spans more than
8075 one register then this register holds the high part of
8076 it and we can't use it.
8078 ??? We should also compare with the high part of the
8080 && !(WORDS_BIG_ENDIAN
8081 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
8082 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
8083 GET_MODE_BITSIZE (GET_MODE (x))))))
8089 /* See whether a single set is a noop. SET is the set instruction we
8090 are should check, and INSN is the instruction from which it came. */
8093 reload_cse_noop_set_p (set, insn)
8098 enum machine_mode dest_mode;
8102 src = SET_SRC (set);
8103 dest = SET_DEST (set);
8104 dest_mode = GET_MODE (dest);
8106 if (side_effects_p (src))
8109 dreg = true_regnum (dest);
8110 sreg = true_regnum (src);
8112 /* Check for setting a register to itself. In this case, we don't
8113 have to worry about REG_DEAD notes. */
8114 if (dreg >= 0 && dreg == sreg)
8120 /* Check for setting a register to itself. */
8124 /* Check for setting a register to a value which we already know
8125 is in the register. */
8126 else if (reload_cse_regno_equal_p (dreg, src, dest_mode))
8129 /* Check for setting a register DREG to another register SREG
8130 where SREG is equal to a value which is already in DREG. */
8135 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
8139 if (XEXP (x, 0) == 0)
8142 if (dest_mode == GET_MODE (x))
8144 else if (GET_MODE_BITSIZE (dest_mode)
8145 < GET_MODE_BITSIZE (GET_MODE (x)))
8146 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
8151 && reload_cse_regno_equal_p (dreg, tmp, dest_mode))
8159 else if (GET_CODE (dest) == MEM)
8161 /* Check for storing a register to memory when we know that the
8162 register is equivalent to the memory location. */
8164 && reload_cse_regno_equal_p (sreg, dest, dest_mode)
8165 && ! side_effects_p (dest))
8169 /* If we can delete this SET, then we need to look for an earlier
8170 REG_DEAD note on DREG, and remove it if it exists. */
8171 if (ret && dreg >= 0)
8173 if (! find_regno_note (insn, REG_UNUSED, dreg))
8174 reload_cse_no_longer_dead (dreg, dest_mode);
8180 /* Try to simplify a single SET instruction. SET is the set pattern.
8181 INSN is the instruction it came from.
8182 This function only handles one case: if we set a register to a value
8183 which is not a register, we try to find that value in some other register
8184 and change the set into a register copy. */
8187 reload_cse_simplify_set (set, insn)
8193 enum machine_mode dest_mode;
8194 enum reg_class dclass;
8197 dreg = true_regnum (SET_DEST (set));
8201 src = SET_SRC (set);
8202 if (side_effects_p (src) || true_regnum (src) >= 0)
8205 /* If memory loads are cheaper than register copies, don't change
8207 if (GET_CODE (src) == MEM && MEMORY_MOVE_COST (GET_MODE (src)) < 2)
8210 dest_mode = GET_MODE (SET_DEST (set));
8211 dclass = REGNO_REG_CLASS (dreg);
8212 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
8215 && REGISTER_MOVE_COST (REGNO_REG_CLASS (i), dclass) == 2
8216 && reload_cse_regno_equal_p (i, src, dest_mode))
8220 /* Pop back to the real obstacks while changing the insn. */
8223 validated = validate_change (insn, &SET_SRC (set),
8224 gen_rtx (REG, dest_mode, i), 1);
8226 /* Go back to the obstack we are using for temporary
8228 push_obstacks (&reload_obstack, &reload_obstack);
8230 if (validated && ! find_regno_note (insn, REG_UNUSED, i))
8232 reload_cse_no_longer_dead (i, dest_mode);
8240 /* Try to replace operands in INSN with equivalent values that are already
8241 in registers. This can be viewed as optional reloading.
8243 For each non-register operand in the insn, see if any hard regs are
8244 known to be equivalent to that operand. Record the alternatives which
8245 can accept these hard registers. Among all alternatives, select the
8246 ones which are better or equal to the one currently matching, where
8247 "better" is in terms of '?' and '!' constraints. Among the remaining
8248 alternatives, select the one which replaces most operands with
8252 reload_cse_simplify_operands (insn)
8255 #ifdef REGISTER_CONSTRAINTS
8256 int insn_code_number, n_operands, n_alternatives;
8259 char *constraints[MAX_RECOG_OPERANDS];
8261 /* Vector recording how bad an alternative is. */
8262 int *alternative_reject;
8263 /* Vector recording how many registers can be introduced by choosing
8264 this alternative. */
8265 int *alternative_nregs;
8266 /* Array of vectors recording, for each operand and each alternative,
8267 which hard register to substitute, or -1 if the operand should be
8269 int *op_alt_regno[MAX_RECOG_OPERANDS];
8270 /* Array of alternatives, sorted in order of decreasing desirability. */
8271 int *alternative_order;
8273 /* Find out some information about this insn. */
8274 insn_code_number = recog_memoized (insn);
8275 /* We don't modify asm instructions. */
8276 if (insn_code_number < 0)
8279 n_operands = insn_n_operands[insn_code_number];
8280 n_alternatives = insn_n_alternatives[insn_code_number];
8282 if (n_alternatives == 0 || n_operands == 0)
8284 insn_extract (insn);
8286 /* Figure out which alternative currently matches. */
8287 if (! constrain_operands (insn_code_number, 1))
8290 alternative_reject = (int *) alloca (n_alternatives * sizeof (int));
8291 alternative_nregs = (int *) alloca (n_alternatives * sizeof (int));
8292 alternative_order = (int *) alloca (n_alternatives * sizeof (int));
8293 bzero ((char *)alternative_reject, n_alternatives * sizeof (int));
8294 bzero ((char *)alternative_nregs, n_alternatives * sizeof (int));
8296 for (i = 0; i < n_operands; i++)
8298 enum machine_mode mode;
8302 op_alt_regno[i] = (int *) alloca (n_alternatives * sizeof (int));
8303 for (j = 0; j < n_alternatives; j++)
8304 op_alt_regno[i][j] = -1;
8306 p = constraints[i] = insn_operand_constraint[insn_code_number][i];
8307 mode = insn_operand_mode[insn_code_number][i];
8309 /* Add the reject values for each alternative given by the constraints
8310 for this operand. */
8318 alternative_reject[j] += 3;
8320 alternative_reject[j] += 300;
8323 /* We won't change operands which are already registers. We
8324 also don't want to modify output operands. */
8325 regno = true_regnum (recog_operand[i]);
8327 || constraints[i][0] == '='
8328 || constraints[i][0] == '+')
8331 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8333 int class = (int) NO_REGS;
8335 if (! reload_cse_regno_equal_p (regno, recog_operand[i], mode))
8338 /* We found a register equal to this operand. Now look for all
8339 alternatives that can accept this register and have not been
8340 assigned a register they can use yet. */
8349 case '=': case '+': case '?':
8350 case '#': case '&': case '!':
8352 case '0': case '1': case '2': case '3': case '4':
8353 case 'm': case '<': case '>': case 'V': case 'o':
8354 case 'E': case 'F': case 'G': case 'H':
8355 case 's': case 'i': case 'n':
8356 case 'I': case 'J': case 'K': case 'L':
8357 case 'M': case 'N': case 'O': case 'P':
8358 #ifdef EXTRA_CONSTRAINT
8359 case 'Q': case 'R': case 'S': case 'T': case 'U':
8362 /* These don't say anything we care about. */
8366 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8371 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER (c)];
8374 case ',': case '\0':
8375 /* See if REGNO fits this alternative, and set it up as the
8376 replacement register if we don't have one for this
8378 if (op_alt_regno[i][j] == -1
8379 && reg_fits_class_p (gen_rtx (REG, mode, regno), class,
8382 alternative_nregs[j]++;
8383 op_alt_regno[i][j] = regno;
8395 /* Record all alternatives which are better or equal to the currently
8396 matching one in the alternative_order array. */
8397 for (i = j = 0; i < n_alternatives; i++)
8398 if (alternative_reject[i] <= alternative_reject[which_alternative])
8399 alternative_order[j++] = i;
8402 /* Sort it. Given a small number of alternatives, a dumb algorithm
8403 won't hurt too much. */
8404 for (i = 0; i < n_alternatives - 1; i++)
8407 int best_reject = alternative_reject[alternative_order[i]];
8408 int best_nregs = alternative_nregs[alternative_order[i]];
8411 for (j = i + 1; j < n_alternatives; j++)
8413 int this_reject = alternative_reject[alternative_order[j]];
8414 int this_nregs = alternative_nregs[alternative_order[j]];
8416 if (this_reject < best_reject
8417 || (this_reject == best_reject && this_nregs < best_nregs))
8420 best_reject = this_reject;
8421 best_nregs = this_nregs;
8425 tmp = alternative_order[best];
8426 alternative_order[best] = alternative_order[i];
8427 alternative_order[i] = tmp;
8430 /* Substitute the operands as determined by op_alt_regno for the best
8432 j = alternative_order[0];
8433 CLEAR_HARD_REG_SET (no_longer_dead_regs);
8435 /* Pop back to the real obstacks while changing the insn. */
8438 for (i = 0; i < n_operands; i++)
8440 enum machine_mode mode = insn_operand_mode[insn_code_number][i];
8441 if (op_alt_regno[i][j] == -1)
8444 reload_cse_no_longer_dead (op_alt_regno[i][j], mode);
8445 validate_change (insn, recog_operand_loc[i],
8446 gen_rtx (REG, mode, op_alt_regno[i][j]), 1);
8449 for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--)
8451 int op = recog_dup_num[i];
8452 enum machine_mode mode = insn_operand_mode[insn_code_number][op];
8454 if (op_alt_regno[op][j] == -1)
8457 reload_cse_no_longer_dead (op_alt_regno[op][j], mode);
8458 validate_change (insn, recog_dup_loc[i],
8459 gen_rtx (REG, mode, op_alt_regno[op][j]), 1);
8462 /* Go back to the obstack we are using for temporary
8464 push_obstacks (&reload_obstack, &reload_obstack);
8466 return apply_change_group ();
8472 /* These two variables are used to pass information from
8473 reload_cse_record_set to reload_cse_check_clobber. */
8475 static int reload_cse_check_clobbered;
8476 static rtx reload_cse_check_src;
8478 /* See if DEST overlaps with RELOAD_CSE_CHECK_SRC. If it does, set
8479 RELOAD_CSE_CHECK_CLOBBERED. This is called via note_stores. The
8480 second argument, which is passed by note_stores, is ignored. */
8483 reload_cse_check_clobber (dest, ignore)
8487 if (reg_overlap_mentioned_p (dest, reload_cse_check_src))
8488 reload_cse_check_clobbered = 1;
8491 /* Record the result of a SET instruction. SET is the set pattern.
8492 BODY is the pattern of the insn that it came from. */
8495 reload_cse_record_set (set, body)
8501 enum machine_mode dest_mode;
8503 dest = SET_DEST (set);
8504 src = SET_SRC (set);
8505 dreg = true_regnum (dest);
8506 sreg = true_regnum (src);
8507 dest_mode = GET_MODE (dest);
8509 /* Some machines don't define AUTO_INC_DEC, but they still use push
8510 instructions. We need to catch that case here in order to
8511 invalidate the stack pointer correctly. Note that invalidating
8512 the stack pointer is different from invalidating DEST. */
8514 while (GET_CODE (x) == SUBREG
8515 || GET_CODE (x) == ZERO_EXTRACT
8516 || GET_CODE (x) == SIGN_EXTRACT
8517 || GET_CODE (x) == STRICT_LOW_PART)
8519 if (push_operand (x, GET_MODE (x)))
8521 reload_cse_invalidate_rtx (stack_pointer_rtx, NULL_RTX);
8522 reload_cse_invalidate_rtx (dest, NULL_RTX);
8526 /* We can only handle an assignment to a register, or a store of a
8527 register to a memory location. For other cases, we just clobber
8528 the destination. We also have to just clobber if there are side
8529 effects in SRC or DEST. */
8530 if ((dreg < 0 && GET_CODE (dest) != MEM)
8531 || side_effects_p (src)
8532 || side_effects_p (dest))
8534 reload_cse_invalidate_rtx (dest, NULL_RTX);
8539 /* We don't try to handle values involving CC, because it's a pain
8540 to keep track of when they have to be invalidated. */
8541 if (reg_mentioned_p (cc0_rtx, src)
8542 || reg_mentioned_p (cc0_rtx, dest))
8544 reload_cse_invalidate_rtx (dest, NULL_RTX);
8549 /* If BODY is a PARALLEL, then we need to see whether the source of
8550 SET is clobbered by some other instruction in the PARALLEL. */
8551 if (GET_CODE (body) == PARALLEL)
8555 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8559 x = XVECEXP (body, 0, i);
8563 reload_cse_check_clobbered = 0;
8564 reload_cse_check_src = src;
8565 note_stores (x, reload_cse_check_clobber);
8566 if (reload_cse_check_clobbered)
8568 reload_cse_invalidate_rtx (dest, NULL_RTX);
8578 /* This is an assignment to a register. Update the value we
8579 have stored for the register. */
8584 /* This is a copy from one register to another. Any values
8585 which were valid for SREG are now valid for DREG. If the
8586 mode changes, we use gen_lowpart_common to extract only
8587 the part of the value that is copied. */
8588 reg_values[dreg] = 0;
8589 for (x = reg_values[sreg]; x; x = XEXP (x, 1))
8593 if (XEXP (x, 0) == 0)
8595 if (dest_mode == GET_MODE (XEXP (x, 0)))
8597 else if (GET_MODE_BITSIZE (dest_mode)
8598 > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
8601 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
8603 reg_values[dreg] = gen_rtx (EXPR_LIST, dest_mode, tmp,
8608 reg_values[dreg] = gen_rtx (EXPR_LIST, dest_mode, src, NULL_RTX);
8610 /* We've changed DREG, so invalidate any values held by other
8611 registers that depend upon it. */
8612 reload_cse_invalidate_regno (dreg, dest_mode, 0);
8614 /* If this assignment changes more than one hard register,
8615 forget anything we know about the others. */
8616 for (i = 1; i < HARD_REGNO_NREGS (dreg, dest_mode); i++)
8617 reg_values[dreg + i] = 0;
8619 else if (GET_CODE (dest) == MEM)
8621 /* Invalidate conflicting memory locations. */
8622 reload_cse_invalidate_mem (dest);
8624 /* If we're storing a register to memory, add DEST to the list
8626 if (sreg >= 0 && ! side_effects_p (dest))
8627 reg_values[sreg] = gen_rtx (EXPR_LIST, dest_mode, dest,
8632 /* We should have bailed out earlier. */
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