1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
106 This is used when the address is not valid as a memory address
107 (because its displacement is too big for the machine.) */
108 rtx *reg_equiv_address;
110 /* Element N is the memory slot to which pseudo reg N is equivalent,
111 or zero if pseudo reg N is not equivalent to a memory slot. */
114 /* Widest width in which each pseudo reg is referred to (via subreg). */
115 static unsigned int *reg_max_ref_width;
117 /* Element N is the list of insns that initialized reg N from its equivalent
118 constant or memory slot. */
119 static rtx *reg_equiv_init;
121 /* Vector to remember old contents of reg_renumber before spilling. */
122 static short *reg_old_renumber;
124 /* During reload_as_needed, element N contains the last pseudo regno reloaded
125 into hard register N. If that pseudo reg occupied more than one register,
126 reg_reloaded_contents points to that pseudo for each spill register in
127 use; all of these must remain set for an inheritance to occur. */
128 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
130 /* During reload_as_needed, element N contains the insn for which
131 hard register N was last used. Its contents are significant only
132 when reg_reloaded_valid is set for this register. */
133 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
135 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
136 static HARD_REG_SET reg_reloaded_valid;
137 /* Indicate if the register was dead at the end of the reload.
138 This is only valid if reg_reloaded_contents is set and valid. */
139 static HARD_REG_SET reg_reloaded_dead;
141 /* Indicate whether the register's current value is one that is not
142 safe to retain across a call, even for registers that are normally
144 static HARD_REG_SET reg_reloaded_call_part_clobbered;
146 /* Number of spill-regs so far; number of valid elements of spill_regs. */
149 /* In parallel with spill_regs, contains REG rtx's for those regs.
150 Holds the last rtx used for any given reg, or 0 if it has never
151 been used for spilling yet. This rtx is reused, provided it has
153 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
155 /* In parallel with spill_regs, contains nonzero for a spill reg
156 that was stored after the last time it was used.
157 The precise value is the insn generated to do the store. */
158 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
160 /* This is the register that was stored with spill_reg_store. This is a
161 copy of reload_out / reload_out_reg when the value was stored; if
162 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
163 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
165 /* This table is the inverse mapping of spill_regs:
166 indexed by hard reg number,
167 it contains the position of that reg in spill_regs,
168 or -1 for something that is not in spill_regs.
170 ?!? This is no longer accurate. */
171 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
173 /* This reg set indicates registers that can't be used as spill registers for
174 the currently processed insn. These are the hard registers which are live
175 during the insn, but not allocated to pseudos, as well as fixed
177 static HARD_REG_SET bad_spill_regs;
179 /* These are the hard registers that can't be used as spill register for any
180 insn. This includes registers used for user variables and registers that
181 we can't eliminate. A register that appears in this set also can't be used
182 to retry register allocation. */
183 static HARD_REG_SET bad_spill_regs_global;
185 /* Describes order of use of registers for reloading
186 of spilled pseudo-registers. `n_spills' is the number of
187 elements that are actually valid; new ones are added at the end.
189 Both spill_regs and spill_reg_order are used on two occasions:
190 once during find_reload_regs, where they keep track of the spill registers
191 for a single insn, but also during reload_as_needed where they show all
192 the registers ever used by reload. For the latter case, the information
193 is calculated during finish_spills. */
194 static short spill_regs[FIRST_PSEUDO_REGISTER];
196 /* This vector of reg sets indicates, for each pseudo, which hard registers
197 may not be used for retrying global allocation because the register was
198 formerly spilled from one of them. If we allowed reallocating a pseudo to
199 a register that it was already allocated to, reload might not
201 static HARD_REG_SET *pseudo_previous_regs;
203 /* This vector of reg sets indicates, for each pseudo, which hard
204 registers may not be used for retrying global allocation because they
205 are used as spill registers during one of the insns in which the
207 static HARD_REG_SET *pseudo_forbidden_regs;
209 /* All hard regs that have been used as spill registers for any insn are
210 marked in this set. */
211 static HARD_REG_SET used_spill_regs;
213 /* Index of last register assigned as a spill register. We allocate in
214 a round-robin fashion. */
215 static int last_spill_reg;
217 /* Nonzero if indirect addressing is supported on the machine; this means
218 that spilling (REG n) does not require reloading it into a register in
219 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
220 value indicates the level of indirect addressing supported, e.g., two
221 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
223 static char spill_indirect_levels;
225 /* Nonzero if indirect addressing is supported when the innermost MEM is
226 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
227 which these are valid is the same as spill_indirect_levels, above. */
228 char indirect_symref_ok;
230 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
231 char double_reg_address_ok;
233 /* Record the stack slot for each spilled hard register. */
234 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
236 /* Width allocated so far for that stack slot. */
237 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
239 /* Record which pseudos needed to be spilled. */
240 static regset_head spilled_pseudos;
242 /* Used for communication between order_regs_for_reload and count_pseudo.
243 Used to avoid counting one pseudo twice. */
244 static regset_head pseudos_counted;
246 /* First uid used by insns created by reload in this function.
247 Used in find_equiv_reg. */
248 int reload_first_uid;
250 /* Flag set by local-alloc or global-alloc if anything is live in
251 a call-clobbered reg across calls. */
252 int caller_save_needed;
254 /* Set to 1 while reload_as_needed is operating.
255 Required by some machines to handle any generated moves differently. */
256 int reload_in_progress = 0;
258 /* These arrays record the insn_code of insns that may be needed to
259 perform input and output reloads of special objects. They provide a
260 place to pass a scratch register. */
261 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
262 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
264 /* This obstack is used for allocation of rtl during register elimination.
265 The allocated storage can be freed once find_reloads has processed the
267 struct obstack reload_obstack;
269 /* Points to the beginning of the reload_obstack. All insn_chain structures
270 are allocated first. */
271 char *reload_startobj;
273 /* The point after all insn_chain structures. Used to quickly deallocate
274 memory allocated in copy_reloads during calculate_needs_all_insns. */
275 char *reload_firstobj;
277 /* This points before all local rtl generated by register elimination.
278 Used to quickly free all memory after processing one insn. */
279 static char *reload_insn_firstobj;
281 /* List of insn_chain instructions, one for every insn that reload needs to
283 struct insn_chain *reload_insn_chain;
285 /* List of all insns needing reloads. */
286 static struct insn_chain *insns_need_reload;
288 /* This structure is used to record information about register eliminations.
289 Each array entry describes one possible way of eliminating a register
290 in favor of another. If there is more than one way of eliminating a
291 particular register, the most preferred should be specified first. */
295 int from; /* Register number to be eliminated. */
296 int to; /* Register number used as replacement. */
297 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
298 int can_eliminate; /* Nonzero if this elimination can be done. */
299 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
300 insns made by reload. */
301 HOST_WIDE_INT offset; /* Current offset between the two regs. */
302 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
303 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
304 rtx from_rtx; /* REG rtx for the register to be eliminated.
305 We cannot simply compare the number since
306 we might then spuriously replace a hard
307 register corresponding to a pseudo
308 assigned to the reg to be eliminated. */
309 rtx to_rtx; /* REG rtx for the replacement. */
312 static struct elim_table *reg_eliminate = 0;
314 /* This is an intermediate structure to initialize the table. It has
315 exactly the members provided by ELIMINABLE_REGS. */
316 static const struct elim_table_1
320 } reg_eliminate_1[] =
322 /* If a set of eliminable registers was specified, define the table from it.
323 Otherwise, default to the normal case of the frame pointer being
324 replaced by the stack pointer. */
326 #ifdef ELIMINABLE_REGS
329 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
332 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
334 /* Record the number of pending eliminations that have an offset not equal
335 to their initial offset. If nonzero, we use a new copy of each
336 replacement result in any insns encountered. */
337 int num_not_at_initial_offset;
339 /* Count the number of registers that we may be able to eliminate. */
340 static int num_eliminable;
341 /* And the number of registers that are equivalent to a constant that
342 can be eliminated to frame_pointer / arg_pointer + constant. */
343 static int num_eliminable_invariants;
345 /* For each label, we record the offset of each elimination. If we reach
346 a label by more than one path and an offset differs, we cannot do the
347 elimination. This information is indexed by the difference of the
348 number of the label and the first label number. We can't offset the
349 pointer itself as this can cause problems on machines with segmented
350 memory. The first table is an array of flags that records whether we
351 have yet encountered a label and the second table is an array of arrays,
352 one entry in the latter array for each elimination. */
354 static int first_label_num;
355 static char *offsets_known_at;
356 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
358 /* Number of labels in the current function. */
360 static int num_labels;
362 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
363 static void maybe_fix_stack_asms (void);
364 static void copy_reloads (struct insn_chain *);
365 static void calculate_needs_all_insns (int);
366 static int find_reg (struct insn_chain *, int);
367 static void find_reload_regs (struct insn_chain *);
368 static void select_reload_regs (void);
369 static void delete_caller_save_insns (void);
371 static void spill_failure (rtx, enum reg_class);
372 static void count_spilled_pseudo (int, int, int);
373 static void delete_dead_insn (rtx);
374 static void alter_reg (int, int);
375 static void set_label_offsets (rtx, rtx, int);
376 static void check_eliminable_occurrences (rtx);
377 static void elimination_effects (rtx, enum machine_mode);
378 static int eliminate_regs_in_insn (rtx, int);
379 static void update_eliminable_offsets (void);
380 static void mark_not_eliminable (rtx, rtx, void *);
381 static void set_initial_elim_offsets (void);
382 static void verify_initial_elim_offsets (void);
383 static void set_initial_label_offsets (void);
384 static void set_offsets_for_label (rtx);
385 static void init_elim_table (void);
386 static void update_eliminables (HARD_REG_SET *);
387 static void spill_hard_reg (unsigned int, int);
388 static int finish_spills (int);
389 static void ior_hard_reg_set (HARD_REG_SET *, HARD_REG_SET *);
390 static void scan_paradoxical_subregs (rtx);
391 static void count_pseudo (int);
392 static void order_regs_for_reload (struct insn_chain *);
393 static void reload_as_needed (int);
394 static void forget_old_reloads_1 (rtx, rtx, void *);
395 static int reload_reg_class_lower (const void *, const void *);
396 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
398 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
400 static int reload_reg_free_p (unsigned int, int, enum reload_type);
401 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
403 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
405 static int function_invariant_p (rtx);
406 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
407 static int allocate_reload_reg (struct insn_chain *, int, int);
408 static int conflicts_with_override (rtx);
409 static void failed_reload (rtx, int);
410 static int set_reload_reg (int, int);
411 static void choose_reload_regs_init (struct insn_chain *, rtx *);
412 static void choose_reload_regs (struct insn_chain *);
413 static void merge_assigned_reloads (rtx);
414 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
416 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
418 static void do_input_reload (struct insn_chain *, struct reload *, int);
419 static void do_output_reload (struct insn_chain *, struct reload *, int);
420 static bool inherit_piecemeal_p (int, int);
421 static void emit_reload_insns (struct insn_chain *);
422 static void delete_output_reload (rtx, int, int);
423 static void delete_address_reloads (rtx, rtx);
424 static void delete_address_reloads_1 (rtx, rtx, rtx);
425 static rtx inc_for_reload (rtx, rtx, rtx, int);
427 static void add_auto_inc_notes (rtx, rtx);
429 static void copy_eh_notes (rtx, rtx);
431 /* Initialize the reload pass once per compilation. */
438 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
439 Set spill_indirect_levels to the number of levels such addressing is
440 permitted, zero if it is not permitted at all. */
443 = gen_rtx_MEM (Pmode,
446 LAST_VIRTUAL_REGISTER + 1),
448 spill_indirect_levels = 0;
450 while (memory_address_p (QImode, tem))
452 spill_indirect_levels++;
453 tem = gen_rtx_MEM (Pmode, tem);
456 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
458 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
459 indirect_symref_ok = memory_address_p (QImode, tem);
461 /* See if reg+reg is a valid (and offsettable) address. */
463 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
465 tem = gen_rtx_PLUS (Pmode,
466 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
467 gen_rtx_REG (Pmode, i));
469 /* This way, we make sure that reg+reg is an offsettable address. */
470 tem = plus_constant (tem, 4);
472 if (memory_address_p (QImode, tem))
474 double_reg_address_ok = 1;
479 /* Initialize obstack for our rtl allocation. */
480 gcc_obstack_init (&reload_obstack);
481 reload_startobj = obstack_alloc (&reload_obstack, 0);
483 INIT_REG_SET (&spilled_pseudos);
484 INIT_REG_SET (&pseudos_counted);
487 /* List of insn chains that are currently unused. */
488 static struct insn_chain *unused_insn_chains = 0;
490 /* Allocate an empty insn_chain structure. */
492 new_insn_chain (void)
494 struct insn_chain *c;
496 if (unused_insn_chains == 0)
498 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
499 INIT_REG_SET (&c->live_throughout);
500 INIT_REG_SET (&c->dead_or_set);
504 c = unused_insn_chains;
505 unused_insn_chains = c->next;
507 c->is_caller_save_insn = 0;
508 c->need_operand_change = 0;
514 /* Small utility function to set all regs in hard reg set TO which are
515 allocated to pseudos in regset FROM. */
518 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
522 EXECUTE_IF_SET_IN_REG_SET
523 (from, FIRST_PSEUDO_REGISTER, regno,
525 int r = reg_renumber[regno];
530 /* reload_combine uses the information from
531 BASIC_BLOCK->global_live_at_start, which might still
532 contain registers that have not actually been allocated
533 since they have an equivalence. */
534 if (! reload_completed)
539 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
541 SET_HARD_REG_BIT (*to, r + nregs);
546 /* Replace all pseudos found in LOC with their corresponding
550 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
563 unsigned int regno = REGNO (x);
565 if (regno < FIRST_PSEUDO_REGISTER)
568 x = eliminate_regs (x, mem_mode, usage);
572 replace_pseudos_in (loc, mem_mode, usage);
576 if (reg_equiv_constant[regno])
577 *loc = reg_equiv_constant[regno];
578 else if (reg_equiv_mem[regno])
579 *loc = reg_equiv_mem[regno];
580 else if (reg_equiv_address[regno])
581 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
582 else if (GET_CODE (regno_reg_rtx[regno]) != REG
583 || REGNO (regno_reg_rtx[regno]) != regno)
584 *loc = regno_reg_rtx[regno];
590 else if (code == MEM)
592 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
596 /* Process each of our operands recursively. */
597 fmt = GET_RTX_FORMAT (code);
598 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
600 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
601 else if (*fmt == 'E')
602 for (j = 0; j < XVECLEN (x, i); j++)
603 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
607 /* Global variables used by reload and its subroutines. */
609 /* Set during calculate_needs if an insn needs register elimination. */
610 static int something_needs_elimination;
611 /* Set during calculate_needs if an insn needs an operand changed. */
612 int something_needs_operands_changed;
614 /* Nonzero means we couldn't get enough spill regs. */
617 /* Main entry point for the reload pass.
619 FIRST is the first insn of the function being compiled.
621 GLOBAL nonzero means we were called from global_alloc
622 and should attempt to reallocate any pseudoregs that we
623 displace from hard regs we will use for reloads.
624 If GLOBAL is zero, we do not have enough information to do that,
625 so any pseudo reg that is spilled must go to the stack.
627 Return value is nonzero if reload failed
628 and we must not do any more for this function. */
631 reload (rtx first, int global)
635 struct elim_table *ep;
638 /* Make sure even insns with volatile mem refs are recognizable. */
643 reload_firstobj = obstack_alloc (&reload_obstack, 0);
645 /* Make sure that the last insn in the chain
646 is not something that needs reloading. */
647 emit_note (NOTE_INSN_DELETED);
649 /* Enable find_equiv_reg to distinguish insns made by reload. */
650 reload_first_uid = get_max_uid ();
652 #ifdef SECONDARY_MEMORY_NEEDED
653 /* Initialize the secondary memory table. */
654 clear_secondary_mem ();
657 /* We don't have a stack slot for any spill reg yet. */
658 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
659 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
661 /* Initialize the save area information for caller-save, in case some
665 /* Compute which hard registers are now in use
666 as homes for pseudo registers.
667 This is done here rather than (eg) in global_alloc
668 because this point is reached even if not optimizing. */
669 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
672 /* A function that receives a nonlocal goto must save all call-saved
674 if (current_function_has_nonlocal_label)
675 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
676 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
677 regs_ever_live[i] = 1;
679 #ifdef NON_SAVING_SETJMP
680 /* A function that calls setjmp should save and restore all the
681 call-saved registers on a system where longjmp clobbers them. */
682 if (NON_SAVING_SETJMP && current_function_calls_setjmp)
684 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
685 if (! call_used_regs[i])
686 regs_ever_live[i] = 1;
690 /* Find all the pseudo registers that didn't get hard regs
691 but do have known equivalent constants or memory slots.
692 These include parameters (known equivalent to parameter slots)
693 and cse'd or loop-moved constant memory addresses.
695 Record constant equivalents in reg_equiv_constant
696 so they will be substituted by find_reloads.
697 Record memory equivalents in reg_mem_equiv so they can
698 be substituted eventually by altering the REG-rtx's. */
700 reg_equiv_constant = xcalloc (max_regno, sizeof (rtx));
701 reg_equiv_mem = xcalloc (max_regno, sizeof (rtx));
702 reg_equiv_init = xcalloc (max_regno, sizeof (rtx));
703 reg_equiv_address = xcalloc (max_regno, sizeof (rtx));
704 reg_max_ref_width = xcalloc (max_regno, sizeof (int));
705 reg_old_renumber = xcalloc (max_regno, sizeof (short));
706 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
707 pseudo_forbidden_regs = xmalloc (max_regno * sizeof (HARD_REG_SET));
708 pseudo_previous_regs = xcalloc (max_regno, sizeof (HARD_REG_SET));
710 CLEAR_HARD_REG_SET (bad_spill_regs_global);
712 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
713 to. Also find all paradoxical subregs and find largest such for
716 num_eliminable_invariants = 0;
717 for (insn = first; insn; insn = NEXT_INSN (insn))
719 rtx set = single_set (insn);
721 /* We may introduce USEs that we want to remove at the end, so
722 we'll mark them with QImode. Make sure there are no
723 previously-marked insns left by say regmove. */
724 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
725 && GET_MODE (insn) != VOIDmode)
726 PUT_MODE (insn, VOIDmode);
728 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
730 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
732 #ifdef LEGITIMATE_PIC_OPERAND_P
733 && (! function_invariant_p (XEXP (note, 0))
735 /* A function invariant is often CONSTANT_P but may
736 include a register. We promise to only pass
737 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
738 || (CONSTANT_P (XEXP (note, 0))
739 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))))
743 rtx x = XEXP (note, 0);
744 i = REGNO (SET_DEST (set));
745 if (i > LAST_VIRTUAL_REGISTER)
747 /* It can happen that a REG_EQUIV note contains a MEM
748 that is not a legitimate memory operand. As later
749 stages of reload assume that all addresses found
750 in the reg_equiv_* arrays were originally legitimate,
751 we ignore such REG_EQUIV notes. */
752 if (memory_operand (x, VOIDmode))
754 /* Always unshare the equivalence, so we can
755 substitute into this insn without touching the
757 reg_equiv_memory_loc[i] = copy_rtx (x);
759 else if (function_invariant_p (x))
761 if (GET_CODE (x) == PLUS)
763 /* This is PLUS of frame pointer and a constant,
764 and might be shared. Unshare it. */
765 reg_equiv_constant[i] = copy_rtx (x);
766 num_eliminable_invariants++;
768 else if (x == frame_pointer_rtx
769 || x == arg_pointer_rtx)
771 reg_equiv_constant[i] = x;
772 num_eliminable_invariants++;
774 else if (LEGITIMATE_CONSTANT_P (x))
775 reg_equiv_constant[i] = x;
778 reg_equiv_memory_loc[i]
779 = force_const_mem (GET_MODE (SET_DEST (set)), x);
780 if (!reg_equiv_memory_loc[i])
787 /* If this register is being made equivalent to a MEM
788 and the MEM is not SET_SRC, the equivalencing insn
789 is one with the MEM as a SET_DEST and it occurs later.
790 So don't mark this insn now. */
791 if (GET_CODE (x) != MEM
792 || rtx_equal_p (SET_SRC (set), x))
794 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
799 /* If this insn is setting a MEM from a register equivalent to it,
800 this is the equivalencing insn. */
801 else if (set && GET_CODE (SET_DEST (set)) == MEM
802 && GET_CODE (SET_SRC (set)) == REG
803 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
804 && rtx_equal_p (SET_DEST (set),
805 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
806 reg_equiv_init[REGNO (SET_SRC (set))]
807 = gen_rtx_INSN_LIST (VOIDmode, insn,
808 reg_equiv_init[REGNO (SET_SRC (set))]);
811 scan_paradoxical_subregs (PATTERN (insn));
816 first_label_num = get_first_label_num ();
817 num_labels = max_label_num () - first_label_num;
819 /* Allocate the tables used to store offset information at labels. */
820 /* We used to use alloca here, but the size of what it would try to
821 allocate would occasionally cause it to exceed the stack limit and
822 cause a core dump. */
823 offsets_known_at = xmalloc (num_labels);
824 offsets_at = xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
826 /* Alter each pseudo-reg rtx to contain its hard reg number.
827 Assign stack slots to the pseudos that lack hard regs or equivalents.
828 Do not touch virtual registers. */
830 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
833 /* If we have some registers we think can be eliminated, scan all insns to
834 see if there is an insn that sets one of these registers to something
835 other than itself plus a constant. If so, the register cannot be
836 eliminated. Doing this scan here eliminates an extra pass through the
837 main reload loop in the most common case where register elimination
839 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
840 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
841 || GET_CODE (insn) == CALL_INSN)
842 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
844 maybe_fix_stack_asms ();
846 insns_need_reload = 0;
847 something_needs_elimination = 0;
849 /* Initialize to -1, which means take the first spill register. */
852 /* Spill any hard regs that we know we can't eliminate. */
853 CLEAR_HARD_REG_SET (used_spill_regs);
854 /* There can be multiple ways to eliminate a register;
855 they should be listed adjacently.
856 Elimination for any register fails only if all possible ways fail. */
857 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
860 int can_eliminate = 0;
863 can_eliminate |= ep->can_eliminate;
866 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
868 spill_hard_reg (from, 1);
871 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
872 if (frame_pointer_needed)
873 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
875 finish_spills (global);
877 /* From now on, we may need to generate moves differently. We may also
878 allow modifications of insns which cause them to not be recognized.
879 Any such modifications will be cleaned up during reload itself. */
880 reload_in_progress = 1;
882 /* This loop scans the entire function each go-round
883 and repeats until one repetition spills no additional hard regs. */
886 int something_changed;
889 HOST_WIDE_INT starting_frame_size;
891 /* Round size of stack frame to stack_alignment_needed. This must be done
892 here because the stack size may be a part of the offset computation
893 for register elimination, and there might have been new stack slots
894 created in the last iteration of this loop. */
895 if (cfun->stack_alignment_needed)
896 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
898 starting_frame_size = get_frame_size ();
900 set_initial_elim_offsets ();
901 set_initial_label_offsets ();
903 /* For each pseudo register that has an equivalent location defined,
904 try to eliminate any eliminable registers (such as the frame pointer)
905 assuming initial offsets for the replacement register, which
908 If the resulting location is directly addressable, substitute
909 the MEM we just got directly for the old REG.
911 If it is not addressable but is a constant or the sum of a hard reg
912 and constant, it is probably not addressable because the constant is
913 out of range, in that case record the address; we will generate
914 hairy code to compute the address in a register each time it is
915 needed. Similarly if it is a hard register, but one that is not
916 valid as an address register.
918 If the location is not addressable, but does not have one of the
919 above forms, assign a stack slot. We have to do this to avoid the
920 potential of producing lots of reloads if, e.g., a location involves
921 a pseudo that didn't get a hard register and has an equivalent memory
922 location that also involves a pseudo that didn't get a hard register.
924 Perhaps at some point we will improve reload_when_needed handling
925 so this problem goes away. But that's very hairy. */
927 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
928 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
930 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
932 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
934 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
935 else if (CONSTANT_P (XEXP (x, 0))
936 || (GET_CODE (XEXP (x, 0)) == REG
937 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
938 || (GET_CODE (XEXP (x, 0)) == PLUS
939 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
940 && (REGNO (XEXP (XEXP (x, 0), 0))
941 < FIRST_PSEUDO_REGISTER)
942 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
943 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
946 /* Make a new stack slot. Then indicate that something
947 changed so we go back and recompute offsets for
948 eliminable registers because the allocation of memory
949 below might change some offset. reg_equiv_{mem,address}
950 will be set up for this pseudo on the next pass around
952 reg_equiv_memory_loc[i] = 0;
953 reg_equiv_init[i] = 0;
958 if (caller_save_needed)
961 /* If we allocated another stack slot, redo elimination bookkeeping. */
962 if (starting_frame_size != get_frame_size ())
965 if (caller_save_needed)
967 save_call_clobbered_regs ();
968 /* That might have allocated new insn_chain structures. */
969 reload_firstobj = obstack_alloc (&reload_obstack, 0);
972 calculate_needs_all_insns (global);
974 CLEAR_REG_SET (&spilled_pseudos);
977 something_changed = 0;
979 /* If we allocated any new memory locations, make another pass
980 since it might have changed elimination offsets. */
981 if (starting_frame_size != get_frame_size ())
982 something_changed = 1;
985 HARD_REG_SET to_spill;
986 CLEAR_HARD_REG_SET (to_spill);
987 update_eliminables (&to_spill);
988 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
989 if (TEST_HARD_REG_BIT (to_spill, i))
991 spill_hard_reg (i, 1);
994 /* Regardless of the state of spills, if we previously had
995 a register that we thought we could eliminate, but now can
996 not eliminate, we must run another pass.
998 Consider pseudos which have an entry in reg_equiv_* which
999 reference an eliminable register. We must make another pass
1000 to update reg_equiv_* so that we do not substitute in the
1001 old value from when we thought the elimination could be
1003 something_changed = 1;
1007 select_reload_regs ();
1011 if (insns_need_reload != 0 || did_spill)
1012 something_changed |= finish_spills (global);
1014 if (! something_changed)
1017 if (caller_save_needed)
1018 delete_caller_save_insns ();
1020 obstack_free (&reload_obstack, reload_firstobj);
1023 /* If global-alloc was run, notify it of any register eliminations we have
1026 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1027 if (ep->can_eliminate)
1028 mark_elimination (ep->from, ep->to);
1030 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1031 If that insn didn't set the register (i.e., it copied the register to
1032 memory), just delete that insn instead of the equivalencing insn plus
1033 anything now dead. If we call delete_dead_insn on that insn, we may
1034 delete the insn that actually sets the register if the register dies
1035 there and that is incorrect. */
1037 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1039 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1042 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1044 rtx equiv_insn = XEXP (list, 0);
1046 /* If we already deleted the insn or if it may trap, we can't
1047 delete it. The latter case shouldn't happen, but can
1048 if an insn has a variable address, gets a REG_EH_REGION
1049 note added to it, and then gets converted into an load
1050 from a constant address. */
1051 if (GET_CODE (equiv_insn) == NOTE
1052 || can_throw_internal (equiv_insn))
1054 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1055 delete_dead_insn (equiv_insn);
1058 PUT_CODE (equiv_insn, NOTE);
1059 NOTE_SOURCE_FILE (equiv_insn) = 0;
1060 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1066 /* Use the reload registers where necessary
1067 by generating move instructions to move the must-be-register
1068 values into or out of the reload registers. */
1070 if (insns_need_reload != 0 || something_needs_elimination
1071 || something_needs_operands_changed)
1073 HOST_WIDE_INT old_frame_size = get_frame_size ();
1075 reload_as_needed (global);
1077 if (old_frame_size != get_frame_size ())
1081 verify_initial_elim_offsets ();
1084 /* If we were able to eliminate the frame pointer, show that it is no
1085 longer live at the start of any basic block. If it ls live by
1086 virtue of being in a pseudo, that pseudo will be marked live
1087 and hence the frame pointer will be known to be live via that
1090 if (! frame_pointer_needed)
1092 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1093 HARD_FRAME_POINTER_REGNUM);
1095 /* Come here (with failure set nonzero) if we can't get enough spill regs
1096 and we decide not to abort about it. */
1099 CLEAR_REG_SET (&spilled_pseudos);
1100 reload_in_progress = 0;
1102 /* Now eliminate all pseudo regs by modifying them into
1103 their equivalent memory references.
1104 The REG-rtx's for the pseudos are modified in place,
1105 so all insns that used to refer to them now refer to memory.
1107 For a reg that has a reg_equiv_address, all those insns
1108 were changed by reloading so that no insns refer to it any longer;
1109 but the DECL_RTL of a variable decl may refer to it,
1110 and if so this causes the debugging info to mention the variable. */
1112 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1116 if (reg_equiv_mem[i])
1117 addr = XEXP (reg_equiv_mem[i], 0);
1119 if (reg_equiv_address[i])
1120 addr = reg_equiv_address[i];
1124 if (reg_renumber[i] < 0)
1126 rtx reg = regno_reg_rtx[i];
1128 REG_USERVAR_P (reg) = 0;
1129 PUT_CODE (reg, MEM);
1130 XEXP (reg, 0) = addr;
1131 if (reg_equiv_memory_loc[i])
1132 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1135 RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg)
1136 = MEM_SCALAR_P (reg) = 0;
1137 MEM_ATTRS (reg) = 0;
1140 else if (reg_equiv_mem[i])
1141 XEXP (reg_equiv_mem[i], 0) = addr;
1145 /* We must set reload_completed now since the cleanup_subreg_operands call
1146 below will re-recognize each insn and reload may have generated insns
1147 which are only valid during and after reload. */
1148 reload_completed = 1;
1150 /* Make a pass over all the insns and delete all USEs which we inserted
1151 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1152 notes. Delete all CLOBBER insns, except those that refer to the return
1153 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1154 from misarranging variable-array code, and simplify (subreg (reg))
1155 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1156 are no longer useful or accurate. Strip and regenerate REG_INC notes
1157 that may have been moved around. */
1159 for (insn = first; insn; insn = NEXT_INSN (insn))
1164 if (GET_CODE (insn) == CALL_INSN)
1165 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1166 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1168 if ((GET_CODE (PATTERN (insn)) == USE
1169 /* We mark with QImode USEs introduced by reload itself. */
1170 && (GET_MODE (insn) == QImode
1171 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1172 || (GET_CODE (PATTERN (insn)) == CLOBBER
1173 && (GET_CODE (XEXP (PATTERN (insn), 0)) != MEM
1174 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1175 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1176 && XEXP (XEXP (PATTERN (insn), 0), 0)
1177 != stack_pointer_rtx))
1178 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1179 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1185 /* Some CLOBBERs may survive until here and still reference unassigned
1186 pseudos with const equivalent, which may in turn cause ICE in later
1187 passes if the reference remains in place. */
1188 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1189 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1190 VOIDmode, PATTERN (insn));
1192 pnote = ®_NOTES (insn);
1195 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1196 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1197 || REG_NOTE_KIND (*pnote) == REG_INC
1198 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1199 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1200 *pnote = XEXP (*pnote, 1);
1202 pnote = &XEXP (*pnote, 1);
1206 add_auto_inc_notes (insn, PATTERN (insn));
1209 /* And simplify (subreg (reg)) if it appears as an operand. */
1210 cleanup_subreg_operands (insn);
1213 /* If we are doing stack checking, give a warning if this function's
1214 frame size is larger than we expect. */
1215 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1217 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1218 static int verbose_warned = 0;
1220 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1221 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1222 size += UNITS_PER_WORD;
1224 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1226 warning ("frame size too large for reliable stack checking");
1227 if (! verbose_warned)
1229 warning ("try reducing the number of local variables");
1235 /* Indicate that we no longer have known memory locations or constants. */
1236 if (reg_equiv_constant)
1237 free (reg_equiv_constant);
1238 reg_equiv_constant = 0;
1239 if (reg_equiv_memory_loc)
1240 free (reg_equiv_memory_loc);
1241 reg_equiv_memory_loc = 0;
1243 if (offsets_known_at)
1244 free (offsets_known_at);
1248 free (reg_equiv_mem);
1249 free (reg_equiv_init);
1250 free (reg_equiv_address);
1251 free (reg_max_ref_width);
1252 free (reg_old_renumber);
1253 free (pseudo_previous_regs);
1254 free (pseudo_forbidden_regs);
1256 CLEAR_HARD_REG_SET (used_spill_regs);
1257 for (i = 0; i < n_spills; i++)
1258 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1260 /* Free all the insn_chain structures at once. */
1261 obstack_free (&reload_obstack, reload_startobj);
1262 unused_insn_chains = 0;
1263 fixup_abnormal_edges ();
1265 /* Replacing pseudos with their memory equivalents might have
1266 created shared rtx. Subsequent passes would get confused
1267 by this, so unshare everything here. */
1268 unshare_all_rtl_again (first);
1270 #ifdef STACK_BOUNDARY
1271 /* init_emit has set the alignment of the hard frame pointer
1272 to STACK_BOUNDARY. It is very likely no longer valid if
1273 the hard frame pointer was used for register allocation. */
1274 if (!frame_pointer_needed)
1275 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1281 /* Yet another special case. Unfortunately, reg-stack forces people to
1282 write incorrect clobbers in asm statements. These clobbers must not
1283 cause the register to appear in bad_spill_regs, otherwise we'll call
1284 fatal_insn later. We clear the corresponding regnos in the live
1285 register sets to avoid this.
1286 The whole thing is rather sick, I'm afraid. */
1289 maybe_fix_stack_asms (void)
1292 const char *constraints[MAX_RECOG_OPERANDS];
1293 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1294 struct insn_chain *chain;
1296 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1299 HARD_REG_SET clobbered, allowed;
1302 if (! INSN_P (chain->insn)
1303 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1305 pat = PATTERN (chain->insn);
1306 if (GET_CODE (pat) != PARALLEL)
1309 CLEAR_HARD_REG_SET (clobbered);
1310 CLEAR_HARD_REG_SET (allowed);
1312 /* First, make a mask of all stack regs that are clobbered. */
1313 for (i = 0; i < XVECLEN (pat, 0); i++)
1315 rtx t = XVECEXP (pat, 0, i);
1316 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1317 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1320 /* Get the operand values and constraints out of the insn. */
1321 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1322 constraints, operand_mode);
1324 /* For every operand, see what registers are allowed. */
1325 for (i = 0; i < noperands; i++)
1327 const char *p = constraints[i];
1328 /* For every alternative, we compute the class of registers allowed
1329 for reloading in CLS, and merge its contents into the reg set
1331 int cls = (int) NO_REGS;
1337 if (c == '\0' || c == ',' || c == '#')
1339 /* End of one alternative - mark the regs in the current
1340 class, and reset the class. */
1341 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1347 } while (c != '\0' && c != ',');
1355 case '=': case '+': case '*': case '%': case '?': case '!':
1356 case '0': case '1': case '2': case '3': case '4': case 'm':
1357 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1358 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1359 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1364 cls = (int) reg_class_subunion[cls]
1365 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1370 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1374 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1375 cls = (int) reg_class_subunion[cls]
1376 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1378 cls = (int) reg_class_subunion[cls]
1379 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1381 p += CONSTRAINT_LEN (c, p);
1384 /* Those of the registers which are clobbered, but allowed by the
1385 constraints, must be usable as reload registers. So clear them
1386 out of the life information. */
1387 AND_HARD_REG_SET (allowed, clobbered);
1388 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1389 if (TEST_HARD_REG_BIT (allowed, i))
1391 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1392 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1399 /* Copy the global variables n_reloads and rld into the corresponding elts
1402 copy_reloads (struct insn_chain *chain)
1404 chain->n_reloads = n_reloads;
1405 chain->rld = obstack_alloc (&reload_obstack,
1406 n_reloads * sizeof (struct reload));
1407 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1408 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1411 /* Walk the chain of insns, and determine for each whether it needs reloads
1412 and/or eliminations. Build the corresponding insns_need_reload list, and
1413 set something_needs_elimination as appropriate. */
1415 calculate_needs_all_insns (int global)
1417 struct insn_chain **pprev_reload = &insns_need_reload;
1418 struct insn_chain *chain, *next = 0;
1420 something_needs_elimination = 0;
1422 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1423 for (chain = reload_insn_chain; chain != 0; chain = next)
1425 rtx insn = chain->insn;
1429 /* Clear out the shortcuts. */
1430 chain->n_reloads = 0;
1431 chain->need_elim = 0;
1432 chain->need_reload = 0;
1433 chain->need_operand_change = 0;
1435 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1436 include REG_LABEL), we need to see what effects this has on the
1437 known offsets at labels. */
1439 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1440 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1441 set_label_offsets (insn, insn, 0);
1445 rtx old_body = PATTERN (insn);
1446 int old_code = INSN_CODE (insn);
1447 rtx old_notes = REG_NOTES (insn);
1448 int did_elimination = 0;
1449 int operands_changed = 0;
1450 rtx set = single_set (insn);
1452 /* Skip insns that only set an equivalence. */
1453 if (set && GET_CODE (SET_DEST (set)) == REG
1454 && reg_renumber[REGNO (SET_DEST (set))] < 0
1455 && reg_equiv_constant[REGNO (SET_DEST (set))])
1458 /* If needed, eliminate any eliminable registers. */
1459 if (num_eliminable || num_eliminable_invariants)
1460 did_elimination = eliminate_regs_in_insn (insn, 0);
1462 /* Analyze the instruction. */
1463 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1464 global, spill_reg_order);
1466 /* If a no-op set needs more than one reload, this is likely
1467 to be something that needs input address reloads. We
1468 can't get rid of this cleanly later, and it is of no use
1469 anyway, so discard it now.
1470 We only do this when expensive_optimizations is enabled,
1471 since this complements reload inheritance / output
1472 reload deletion, and it can make debugging harder. */
1473 if (flag_expensive_optimizations && n_reloads > 1)
1475 rtx set = single_set (insn);
1477 && SET_SRC (set) == SET_DEST (set)
1478 && GET_CODE (SET_SRC (set)) == REG
1479 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1482 /* Delete it from the reload chain. */
1484 chain->prev->next = next;
1486 reload_insn_chain = next;
1488 next->prev = chain->prev;
1489 chain->next = unused_insn_chains;
1490 unused_insn_chains = chain;
1495 update_eliminable_offsets ();
1497 /* Remember for later shortcuts which insns had any reloads or
1498 register eliminations. */
1499 chain->need_elim = did_elimination;
1500 chain->need_reload = n_reloads > 0;
1501 chain->need_operand_change = operands_changed;
1503 /* Discard any register replacements done. */
1504 if (did_elimination)
1506 obstack_free (&reload_obstack, reload_insn_firstobj);
1507 PATTERN (insn) = old_body;
1508 INSN_CODE (insn) = old_code;
1509 REG_NOTES (insn) = old_notes;
1510 something_needs_elimination = 1;
1513 something_needs_operands_changed |= operands_changed;
1517 copy_reloads (chain);
1518 *pprev_reload = chain;
1519 pprev_reload = &chain->next_need_reload;
1526 /* Comparison function for qsort to decide which of two reloads
1527 should be handled first. *P1 and *P2 are the reload numbers. */
1530 reload_reg_class_lower (const void *r1p, const void *r2p)
1532 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1535 /* Consider required reloads before optional ones. */
1536 t = rld[r1].optional - rld[r2].optional;
1540 /* Count all solitary classes before non-solitary ones. */
1541 t = ((reg_class_size[(int) rld[r2].class] == 1)
1542 - (reg_class_size[(int) rld[r1].class] == 1));
1546 /* Aside from solitaires, consider all multi-reg groups first. */
1547 t = rld[r2].nregs - rld[r1].nregs;
1551 /* Consider reloads in order of increasing reg-class number. */
1552 t = (int) rld[r1].class - (int) rld[r2].class;
1556 /* If reloads are equally urgent, sort by reload number,
1557 so that the results of qsort leave nothing to chance. */
1561 /* The cost of spilling each hard reg. */
1562 static int spill_cost[FIRST_PSEUDO_REGISTER];
1564 /* When spilling multiple hard registers, we use SPILL_COST for the first
1565 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1566 only the first hard reg for a multi-reg pseudo. */
1567 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1569 /* Update the spill cost arrays, considering that pseudo REG is live. */
1572 count_pseudo (int reg)
1574 int freq = REG_FREQ (reg);
1575 int r = reg_renumber[reg];
1578 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1579 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1582 SET_REGNO_REG_SET (&pseudos_counted, reg);
1587 spill_add_cost[r] += freq;
1589 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1591 spill_cost[r + nregs] += freq;
1594 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1595 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1598 order_regs_for_reload (struct insn_chain *chain)
1601 HARD_REG_SET used_by_pseudos;
1602 HARD_REG_SET used_by_pseudos2;
1604 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1606 memset (spill_cost, 0, sizeof spill_cost);
1607 memset (spill_add_cost, 0, sizeof spill_add_cost);
1609 /* Count number of uses of each hard reg by pseudo regs allocated to it
1610 and then order them by decreasing use. First exclude hard registers
1611 that are live in or across this insn. */
1613 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1614 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1615 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1616 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1618 /* Now find out which pseudos are allocated to it, and update
1620 CLEAR_REG_SET (&pseudos_counted);
1622 EXECUTE_IF_SET_IN_REG_SET
1623 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1627 EXECUTE_IF_SET_IN_REG_SET
1628 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1632 CLEAR_REG_SET (&pseudos_counted);
1635 /* Vector of reload-numbers showing the order in which the reloads should
1637 static short reload_order[MAX_RELOADS];
1639 /* This is used to keep track of the spill regs used in one insn. */
1640 static HARD_REG_SET used_spill_regs_local;
1642 /* We decided to spill hard register SPILLED, which has a size of
1643 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1644 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1645 update SPILL_COST/SPILL_ADD_COST. */
1648 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1650 int r = reg_renumber[reg];
1651 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1653 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1654 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1657 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1659 spill_add_cost[r] -= REG_FREQ (reg);
1661 spill_cost[r + nregs] -= REG_FREQ (reg);
1664 /* Find reload register to use for reload number ORDER. */
1667 find_reg (struct insn_chain *chain, int order)
1669 int rnum = reload_order[order];
1670 struct reload *rl = rld + rnum;
1671 int best_cost = INT_MAX;
1675 HARD_REG_SET not_usable;
1676 HARD_REG_SET used_by_other_reload;
1678 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1679 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1680 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1682 CLEAR_HARD_REG_SET (used_by_other_reload);
1683 for (k = 0; k < order; k++)
1685 int other = reload_order[k];
1687 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1688 for (j = 0; j < rld[other].nregs; j++)
1689 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1692 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1694 unsigned int regno = i;
1696 if (! TEST_HARD_REG_BIT (not_usable, regno)
1697 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1698 && HARD_REGNO_MODE_OK (regno, rl->mode))
1700 int this_cost = spill_cost[regno];
1702 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1704 for (j = 1; j < this_nregs; j++)
1706 this_cost += spill_add_cost[regno + j];
1707 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1708 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1713 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1715 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1717 if (this_cost < best_cost
1718 /* Among registers with equal cost, prefer caller-saved ones, or
1719 use REG_ALLOC_ORDER if it is defined. */
1720 || (this_cost == best_cost
1721 #ifdef REG_ALLOC_ORDER
1722 && (inv_reg_alloc_order[regno]
1723 < inv_reg_alloc_order[best_reg])
1725 && call_used_regs[regno]
1726 && ! call_used_regs[best_reg]
1731 best_cost = this_cost;
1739 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1741 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1742 rl->regno = best_reg;
1744 EXECUTE_IF_SET_IN_REG_SET
1745 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1747 count_spilled_pseudo (best_reg, rl->nregs, j);
1750 EXECUTE_IF_SET_IN_REG_SET
1751 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1753 count_spilled_pseudo (best_reg, rl->nregs, j);
1756 for (i = 0; i < rl->nregs; i++)
1758 if (spill_cost[best_reg + i] != 0
1759 || spill_add_cost[best_reg + i] != 0)
1761 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1766 /* Find more reload regs to satisfy the remaining need of an insn, which
1768 Do it by ascending class number, since otherwise a reg
1769 might be spilled for a big class and might fail to count
1770 for a smaller class even though it belongs to that class. */
1773 find_reload_regs (struct insn_chain *chain)
1777 /* In order to be certain of getting the registers we need,
1778 we must sort the reloads into order of increasing register class.
1779 Then our grabbing of reload registers will parallel the process
1780 that provided the reload registers. */
1781 for (i = 0; i < chain->n_reloads; i++)
1783 /* Show whether this reload already has a hard reg. */
1784 if (chain->rld[i].reg_rtx)
1786 int regno = REGNO (chain->rld[i].reg_rtx);
1787 chain->rld[i].regno = regno;
1789 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1792 chain->rld[i].regno = -1;
1793 reload_order[i] = i;
1796 n_reloads = chain->n_reloads;
1797 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1799 CLEAR_HARD_REG_SET (used_spill_regs_local);
1802 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1804 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1806 /* Compute the order of preference for hard registers to spill. */
1808 order_regs_for_reload (chain);
1810 for (i = 0; i < n_reloads; i++)
1812 int r = reload_order[i];
1814 /* Ignore reloads that got marked inoperative. */
1815 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1816 && ! rld[r].optional
1817 && rld[r].regno == -1)
1818 if (! find_reg (chain, i))
1820 spill_failure (chain->insn, rld[r].class);
1826 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1827 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1829 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1833 select_reload_regs (void)
1835 struct insn_chain *chain;
1837 /* Try to satisfy the needs for each insn. */
1838 for (chain = insns_need_reload; chain != 0;
1839 chain = chain->next_need_reload)
1840 find_reload_regs (chain);
1843 /* Delete all insns that were inserted by emit_caller_save_insns during
1846 delete_caller_save_insns (void)
1848 struct insn_chain *c = reload_insn_chain;
1852 while (c != 0 && c->is_caller_save_insn)
1854 struct insn_chain *next = c->next;
1857 if (c == reload_insn_chain)
1858 reload_insn_chain = next;
1862 next->prev = c->prev;
1864 c->prev->next = next;
1865 c->next = unused_insn_chains;
1866 unused_insn_chains = c;
1874 /* Handle the failure to find a register to spill.
1875 INSN should be one of the insns which needed this particular spill reg. */
1878 spill_failure (rtx insn, enum reg_class class)
1880 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1881 if (asm_noperands (PATTERN (insn)) >= 0)
1882 error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'",
1883 reg_class_names[class]);
1886 error ("unable to find a register to spill in class `%s'",
1887 reg_class_names[class]);
1888 fatal_insn ("this is the insn:", insn);
1892 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1893 data that is dead in INSN. */
1896 delete_dead_insn (rtx insn)
1898 rtx prev = prev_real_insn (insn);
1901 /* If the previous insn sets a register that dies in our insn, delete it
1903 if (prev && GET_CODE (PATTERN (prev)) == SET
1904 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1905 && reg_mentioned_p (prev_dest, PATTERN (insn))
1906 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1907 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1908 delete_dead_insn (prev);
1910 PUT_CODE (insn, NOTE);
1911 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1912 NOTE_SOURCE_FILE (insn) = 0;
1915 /* Modify the home of pseudo-reg I.
1916 The new home is present in reg_renumber[I].
1918 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1919 or it may be -1, meaning there is none or it is not relevant.
1920 This is used so that all pseudos spilled from a given hard reg
1921 can share one stack slot. */
1924 alter_reg (int i, int from_reg)
1926 /* When outputting an inline function, this can happen
1927 for a reg that isn't actually used. */
1928 if (regno_reg_rtx[i] == 0)
1931 /* If the reg got changed to a MEM at rtl-generation time,
1933 if (GET_CODE (regno_reg_rtx[i]) != REG)
1936 /* Modify the reg-rtx to contain the new hard reg
1937 number or else to contain its pseudo reg number. */
1938 REGNO (regno_reg_rtx[i])
1939 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1941 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1942 allocate a stack slot for it. */
1944 if (reg_renumber[i] < 0
1945 && REG_N_REFS (i) > 0
1946 && reg_equiv_constant[i] == 0
1947 && reg_equiv_memory_loc[i] == 0)
1950 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1951 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1954 /* Each pseudo reg has an inherent size which comes from its own mode,
1955 and a total size which provides room for paradoxical subregs
1956 which refer to the pseudo reg in wider modes.
1958 We can use a slot already allocated if it provides both
1959 enough inherent space and enough total space.
1960 Otherwise, we allocate a new slot, making sure that it has no less
1961 inherent space, and no less total space, then the previous slot. */
1964 /* No known place to spill from => no slot to reuse. */
1965 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1966 inherent_size == total_size ? 0 : -1);
1967 if (BYTES_BIG_ENDIAN)
1968 /* Cancel the big-endian correction done in assign_stack_local.
1969 Get the address of the beginning of the slot.
1970 This is so we can do a big-endian correction unconditionally
1972 adjust = inherent_size - total_size;
1974 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1976 /* Nothing can alias this slot except this pseudo. */
1977 set_mem_alias_set (x, new_alias_set ());
1980 /* Reuse a stack slot if possible. */
1981 else if (spill_stack_slot[from_reg] != 0
1982 && spill_stack_slot_width[from_reg] >= total_size
1983 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1985 x = spill_stack_slot[from_reg];
1987 /* Allocate a bigger slot. */
1990 /* Compute maximum size needed, both for inherent size
1991 and for total size. */
1992 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1995 if (spill_stack_slot[from_reg])
1997 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1999 mode = GET_MODE (spill_stack_slot[from_reg]);
2000 if (spill_stack_slot_width[from_reg] > total_size)
2001 total_size = spill_stack_slot_width[from_reg];
2004 /* Make a slot with that size. */
2005 x = assign_stack_local (mode, total_size,
2006 inherent_size == total_size ? 0 : -1);
2009 /* All pseudos mapped to this slot can alias each other. */
2010 if (spill_stack_slot[from_reg])
2011 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2013 set_mem_alias_set (x, new_alias_set ());
2015 if (BYTES_BIG_ENDIAN)
2017 /* Cancel the big-endian correction done in assign_stack_local.
2018 Get the address of the beginning of the slot.
2019 This is so we can do a big-endian correction unconditionally
2021 adjust = GET_MODE_SIZE (mode) - total_size;
2024 = adjust_address_nv (x, mode_for_size (total_size
2030 spill_stack_slot[from_reg] = stack_slot;
2031 spill_stack_slot_width[from_reg] = total_size;
2034 /* On a big endian machine, the "address" of the slot
2035 is the address of the low part that fits its inherent mode. */
2036 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2037 adjust += (total_size - inherent_size);
2039 /* If we have any adjustment to make, or if the stack slot is the
2040 wrong mode, make a new stack slot. */
2041 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2043 /* If we have a decl for the original register, set it for the
2044 memory. If this is a shared MEM, make a copy. */
2045 if (REG_EXPR (regno_reg_rtx[i])
2046 && TREE_CODE_CLASS (TREE_CODE (REG_EXPR (regno_reg_rtx[i]))) == 'd')
2048 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2050 /* We can do this only for the DECLs home pseudo, not for
2051 any copies of it, since otherwise when the stack slot
2052 is reused, nonoverlapping_memrefs_p might think they
2054 if (decl && GET_CODE (decl) == REG && REGNO (decl) == (unsigned) i)
2056 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2059 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2063 /* Save the stack slot for later. */
2064 reg_equiv_memory_loc[i] = x;
2068 /* Mark the slots in regs_ever_live for the hard regs
2069 used by pseudo-reg number REGNO. */
2072 mark_home_live (int regno)
2076 i = reg_renumber[regno];
2079 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2081 regs_ever_live[i++] = 1;
2084 /* This function handles the tracking of elimination offsets around branches.
2086 X is a piece of RTL being scanned.
2088 INSN is the insn that it came from, if any.
2090 INITIAL_P is nonzero if we are to set the offset to be the initial
2091 offset and zero if we are setting the offset of the label to be the
2095 set_label_offsets (rtx x, rtx insn, int initial_p)
2097 enum rtx_code code = GET_CODE (x);
2100 struct elim_table *p;
2105 if (LABEL_REF_NONLOCAL_P (x))
2110 /* ... fall through ... */
2113 /* If we know nothing about this label, set the desired offsets. Note
2114 that this sets the offset at a label to be the offset before a label
2115 if we don't know anything about the label. This is not correct for
2116 the label after a BARRIER, but is the best guess we can make. If
2117 we guessed wrong, we will suppress an elimination that might have
2118 been possible had we been able to guess correctly. */
2120 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2122 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2123 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2124 = (initial_p ? reg_eliminate[i].initial_offset
2125 : reg_eliminate[i].offset);
2126 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2129 /* Otherwise, if this is the definition of a label and it is
2130 preceded by a BARRIER, set our offsets to the known offset of
2134 && (tem = prev_nonnote_insn (insn)) != 0
2135 && GET_CODE (tem) == BARRIER)
2136 set_offsets_for_label (insn);
2138 /* If neither of the above cases is true, compare each offset
2139 with those previously recorded and suppress any eliminations
2140 where the offsets disagree. */
2142 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2143 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2144 != (initial_p ? reg_eliminate[i].initial_offset
2145 : reg_eliminate[i].offset))
2146 reg_eliminate[i].can_eliminate = 0;
2151 set_label_offsets (PATTERN (insn), insn, initial_p);
2153 /* ... fall through ... */
2157 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2158 and hence must have all eliminations at their initial offsets. */
2159 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2160 if (REG_NOTE_KIND (tem) == REG_LABEL)
2161 set_label_offsets (XEXP (tem, 0), insn, 1);
2167 /* Each of the labels in the parallel or address vector must be
2168 at their initial offsets. We want the first field for PARALLEL
2169 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2171 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2172 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2177 /* We only care about setting PC. If the source is not RETURN,
2178 IF_THEN_ELSE, or a label, disable any eliminations not at
2179 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2180 isn't one of those possibilities. For branches to a label,
2181 call ourselves recursively.
2183 Note that this can disable elimination unnecessarily when we have
2184 a non-local goto since it will look like a non-constant jump to
2185 someplace in the current function. This isn't a significant
2186 problem since such jumps will normally be when all elimination
2187 pairs are back to their initial offsets. */
2189 if (SET_DEST (x) != pc_rtx)
2192 switch (GET_CODE (SET_SRC (x)))
2199 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2203 tem = XEXP (SET_SRC (x), 1);
2204 if (GET_CODE (tem) == LABEL_REF)
2205 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2206 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2209 tem = XEXP (SET_SRC (x), 2);
2210 if (GET_CODE (tem) == LABEL_REF)
2211 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2212 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2220 /* If we reach here, all eliminations must be at their initial
2221 offset because we are doing a jump to a variable address. */
2222 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2223 if (p->offset != p->initial_offset)
2224 p->can_eliminate = 0;
2232 /* Scan X and replace any eliminable registers (such as fp) with a
2233 replacement (such as sp), plus an offset.
2235 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2236 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2237 MEM, we are allowed to replace a sum of a register and the constant zero
2238 with the register, which we cannot do outside a MEM. In addition, we need
2239 to record the fact that a register is referenced outside a MEM.
2241 If INSN is an insn, it is the insn containing X. If we replace a REG
2242 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2243 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2244 the REG is being modified.
2246 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2247 That's used when we eliminate in expressions stored in notes.
2248 This means, do not set ref_outside_mem even if the reference
2251 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2252 replacements done assuming all offsets are at their initial values. If
2253 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2254 encounter, return the actual location so that find_reloads will do
2255 the proper thing. */
2258 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2260 enum rtx_code code = GET_CODE (x);
2261 struct elim_table *ep;
2268 if (! current_function_decl)
2288 /* This is only for the benefit of the debugging backends, which call
2289 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2290 removed after CSE. */
2291 new = eliminate_regs (XEXP (x, 0), 0, insn);
2292 if (GET_CODE (new) == MEM)
2293 return XEXP (new, 0);
2299 /* First handle the case where we encounter a bare register that
2300 is eliminable. Replace it with a PLUS. */
2301 if (regno < FIRST_PSEUDO_REGISTER)
2303 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2305 if (ep->from_rtx == x && ep->can_eliminate)
2306 return plus_constant (ep->to_rtx, ep->previous_offset);
2309 else if (reg_renumber && reg_renumber[regno] < 0
2310 && reg_equiv_constant && reg_equiv_constant[regno]
2311 && ! CONSTANT_P (reg_equiv_constant[regno]))
2312 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2316 /* You might think handling MINUS in a manner similar to PLUS is a
2317 good idea. It is not. It has been tried multiple times and every
2318 time the change has had to have been reverted.
2320 Other parts of reload know a PLUS is special (gen_reload for example)
2321 and require special code to handle code a reloaded PLUS operand.
2323 Also consider backends where the flags register is clobbered by a
2324 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2325 lea instruction comes to mind). If we try to reload a MINUS, we
2326 may kill the flags register that was holding a useful value.
2328 So, please before trying to handle MINUS, consider reload as a
2329 whole instead of this little section as well as the backend issues. */
2331 /* If this is the sum of an eliminable register and a constant, rework
2333 if (GET_CODE (XEXP (x, 0)) == REG
2334 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2335 && CONSTANT_P (XEXP (x, 1)))
2337 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2339 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2341 /* The only time we want to replace a PLUS with a REG (this
2342 occurs when the constant operand of the PLUS is the negative
2343 of the offset) is when we are inside a MEM. We won't want
2344 to do so at other times because that would change the
2345 structure of the insn in a way that reload can't handle.
2346 We special-case the commonest situation in
2347 eliminate_regs_in_insn, so just replace a PLUS with a
2348 PLUS here, unless inside a MEM. */
2349 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2350 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2353 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2354 plus_constant (XEXP (x, 1),
2355 ep->previous_offset));
2358 /* If the register is not eliminable, we are done since the other
2359 operand is a constant. */
2363 /* If this is part of an address, we want to bring any constant to the
2364 outermost PLUS. We will do this by doing register replacement in
2365 our operands and seeing if a constant shows up in one of them.
2367 Note that there is no risk of modifying the structure of the insn,
2368 since we only get called for its operands, thus we are either
2369 modifying the address inside a MEM, or something like an address
2370 operand of a load-address insn. */
2373 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2374 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2376 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2378 /* If one side is a PLUS and the other side is a pseudo that
2379 didn't get a hard register but has a reg_equiv_constant,
2380 we must replace the constant here since it may no longer
2381 be in the position of any operand. */
2382 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2383 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2384 && reg_renumber[REGNO (new1)] < 0
2385 && reg_equiv_constant != 0
2386 && reg_equiv_constant[REGNO (new1)] != 0)
2387 new1 = reg_equiv_constant[REGNO (new1)];
2388 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2389 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2390 && reg_renumber[REGNO (new0)] < 0
2391 && reg_equiv_constant[REGNO (new0)] != 0)
2392 new0 = reg_equiv_constant[REGNO (new0)];
2394 new = form_sum (new0, new1);
2396 /* As above, if we are not inside a MEM we do not want to
2397 turn a PLUS into something else. We might try to do so here
2398 for an addition of 0 if we aren't optimizing. */
2399 if (! mem_mode && GET_CODE (new) != PLUS)
2400 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2408 /* If this is the product of an eliminable register and a
2409 constant, apply the distribute law and move the constant out
2410 so that we have (plus (mult ..) ..). This is needed in order
2411 to keep load-address insns valid. This case is pathological.
2412 We ignore the possibility of overflow here. */
2413 if (GET_CODE (XEXP (x, 0)) == REG
2414 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2415 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2416 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2418 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2421 /* Refs inside notes don't count for this purpose. */
2422 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2423 || GET_CODE (insn) == INSN_LIST)))
2424 ep->ref_outside_mem = 1;
2427 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2428 ep->previous_offset * INTVAL (XEXP (x, 1)));
2431 /* ... fall through ... */
2435 /* See comments before PLUS about handling MINUS. */
2437 case DIV: case UDIV:
2438 case MOD: case UMOD:
2439 case AND: case IOR: case XOR:
2440 case ROTATERT: case ROTATE:
2441 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2443 case GE: case GT: case GEU: case GTU:
2444 case LE: case LT: case LEU: case LTU:
2446 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2448 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2450 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2451 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2456 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2459 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2460 if (new != XEXP (x, 0))
2462 /* If this is a REG_DEAD note, it is not valid anymore.
2463 Using the eliminated version could result in creating a
2464 REG_DEAD note for the stack or frame pointer. */
2465 if (GET_MODE (x) == REG_DEAD)
2467 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2470 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2474 /* ... fall through ... */
2477 /* Now do eliminations in the rest of the chain. If this was
2478 an EXPR_LIST, this might result in allocating more memory than is
2479 strictly needed, but it simplifies the code. */
2482 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2483 if (new != XEXP (x, 1))
2485 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2493 case STRICT_LOW_PART:
2495 case SIGN_EXTEND: case ZERO_EXTEND:
2496 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2497 case FLOAT: case FIX:
2498 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2506 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2507 if (new != XEXP (x, 0))
2508 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2512 /* Similar to above processing, but preserve SUBREG_BYTE.
2513 Convert (subreg (mem)) to (mem) if not paradoxical.
2514 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2515 pseudo didn't get a hard reg, we must replace this with the
2516 eliminated version of the memory location because push_reload
2517 may do the replacement in certain circumstances. */
2518 if (GET_CODE (SUBREG_REG (x)) == REG
2519 && (GET_MODE_SIZE (GET_MODE (x))
2520 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2521 && reg_equiv_memory_loc != 0
2522 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2524 new = SUBREG_REG (x);
2527 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2529 if (new != SUBREG_REG (x))
2531 int x_size = GET_MODE_SIZE (GET_MODE (x));
2532 int new_size = GET_MODE_SIZE (GET_MODE (new));
2534 if (GET_CODE (new) == MEM
2535 && ((x_size < new_size
2536 #ifdef WORD_REGISTER_OPERATIONS
2537 /* On these machines, combine can create rtl of the form
2538 (set (subreg:m1 (reg:m2 R) 0) ...)
2539 where m1 < m2, and expects something interesting to
2540 happen to the entire word. Moreover, it will use the
2541 (reg:m2 R) later, expecting all bits to be preserved.
2542 So if the number of words is the same, preserve the
2543 subreg so that push_reload can see it. */
2544 && ! ((x_size - 1) / UNITS_PER_WORD
2545 == (new_size -1 ) / UNITS_PER_WORD)
2548 || x_size == new_size)
2550 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2552 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2558 /* This is only for the benefit of the debugging backends, which call
2559 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2560 removed after CSE. */
2561 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2562 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2564 /* Our only special processing is to pass the mode of the MEM to our
2565 recursive call and copy the flags. While we are here, handle this
2566 case more efficiently. */
2568 replace_equiv_address_nv (x,
2569 eliminate_regs (XEXP (x, 0),
2570 GET_MODE (x), insn));
2573 /* Handle insn_list USE that a call to a pure function may generate. */
2574 new = eliminate_regs (XEXP (x, 0), 0, insn);
2575 if (new != XEXP (x, 0))
2576 return gen_rtx_USE (GET_MODE (x), new);
2588 /* Process each of our operands recursively. If any have changed, make a
2590 fmt = GET_RTX_FORMAT (code);
2591 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2595 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2596 if (new != XEXP (x, i) && ! copied)
2598 rtx new_x = rtx_alloc (code);
2599 memcpy (new_x, x, RTX_SIZE (code));
2605 else if (*fmt == 'E')
2608 for (j = 0; j < XVECLEN (x, i); j++)
2610 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2611 if (new != XVECEXP (x, i, j) && ! copied_vec)
2613 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2617 rtx new_x = rtx_alloc (code);
2618 memcpy (new_x, x, RTX_SIZE (code));
2622 XVEC (x, i) = new_v;
2625 XVECEXP (x, i, j) = new;
2633 /* Scan rtx X for modifications of elimination target registers. Update
2634 the table of eliminables to reflect the changed state. MEM_MODE is
2635 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2638 elimination_effects (rtx x, enum machine_mode mem_mode)
2640 enum rtx_code code = GET_CODE (x);
2641 struct elim_table *ep;
2668 /* First handle the case where we encounter a bare register that
2669 is eliminable. Replace it with a PLUS. */
2670 if (regno < FIRST_PSEUDO_REGISTER)
2672 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2674 if (ep->from_rtx == x && ep->can_eliminate)
2677 ep->ref_outside_mem = 1;
2682 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2683 && reg_equiv_constant[regno]
2684 && ! function_invariant_p (reg_equiv_constant[regno]))
2685 elimination_effects (reg_equiv_constant[regno], mem_mode);
2694 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2695 if (ep->to_rtx == XEXP (x, 0))
2697 int size = GET_MODE_SIZE (mem_mode);
2699 /* If more bytes than MEM_MODE are pushed, account for them. */
2700 #ifdef PUSH_ROUNDING
2701 if (ep->to_rtx == stack_pointer_rtx)
2702 size = PUSH_ROUNDING (size);
2704 if (code == PRE_DEC || code == POST_DEC)
2706 else if (code == PRE_INC || code == POST_INC)
2708 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2709 && GET_CODE (XEXP (x, 1)) == PLUS
2710 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2711 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2712 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2715 /* These two aren't unary operators. */
2716 if (code == POST_MODIFY || code == PRE_MODIFY)
2719 /* Fall through to generic unary operation case. */
2720 case STRICT_LOW_PART:
2722 case SIGN_EXTEND: case ZERO_EXTEND:
2723 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2724 case FLOAT: case FIX:
2725 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2733 elimination_effects (XEXP (x, 0), mem_mode);
2737 if (GET_CODE (SUBREG_REG (x)) == REG
2738 && (GET_MODE_SIZE (GET_MODE (x))
2739 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2740 && reg_equiv_memory_loc != 0
2741 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2744 elimination_effects (SUBREG_REG (x), mem_mode);
2748 /* If using a register that is the source of an eliminate we still
2749 think can be performed, note it cannot be performed since we don't
2750 know how this register is used. */
2751 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2752 if (ep->from_rtx == XEXP (x, 0))
2753 ep->can_eliminate = 0;
2755 elimination_effects (XEXP (x, 0), mem_mode);
2759 /* If clobbering a register that is the replacement register for an
2760 elimination we still think can be performed, note that it cannot
2761 be performed. Otherwise, we need not be concerned about it. */
2762 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2763 if (ep->to_rtx == XEXP (x, 0))
2764 ep->can_eliminate = 0;
2766 elimination_effects (XEXP (x, 0), mem_mode);
2770 /* Check for setting a register that we know about. */
2771 if (GET_CODE (SET_DEST (x)) == REG)
2773 /* See if this is setting the replacement register for an
2776 If DEST is the hard frame pointer, we do nothing because we
2777 assume that all assignments to the frame pointer are for
2778 non-local gotos and are being done at a time when they are valid
2779 and do not disturb anything else. Some machines want to
2780 eliminate a fake argument pointer (or even a fake frame pointer)
2781 with either the real frame or the stack pointer. Assignments to
2782 the hard frame pointer must not prevent this elimination. */
2784 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2786 if (ep->to_rtx == SET_DEST (x)
2787 && SET_DEST (x) != hard_frame_pointer_rtx)
2789 /* If it is being incremented, adjust the offset. Otherwise,
2790 this elimination can't be done. */
2791 rtx src = SET_SRC (x);
2793 if (GET_CODE (src) == PLUS
2794 && XEXP (src, 0) == SET_DEST (x)
2795 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2796 ep->offset -= INTVAL (XEXP (src, 1));
2798 ep->can_eliminate = 0;
2802 elimination_effects (SET_DEST (x), 0);
2803 elimination_effects (SET_SRC (x), 0);
2807 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2810 /* Our only special processing is to pass the mode of the MEM to our
2812 elimination_effects (XEXP (x, 0), GET_MODE (x));
2819 fmt = GET_RTX_FORMAT (code);
2820 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2823 elimination_effects (XEXP (x, i), mem_mode);
2824 else if (*fmt == 'E')
2825 for (j = 0; j < XVECLEN (x, i); j++)
2826 elimination_effects (XVECEXP (x, i, j), mem_mode);
2830 /* Descend through rtx X and verify that no references to eliminable registers
2831 remain. If any do remain, mark the involved register as not
2835 check_eliminable_occurrences (rtx x)
2844 code = GET_CODE (x);
2846 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2848 struct elim_table *ep;
2850 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2851 if (ep->from_rtx == x)
2852 ep->can_eliminate = 0;
2856 fmt = GET_RTX_FORMAT (code);
2857 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2860 check_eliminable_occurrences (XEXP (x, i));
2861 else if (*fmt == 'E')
2864 for (j = 0; j < XVECLEN (x, i); j++)
2865 check_eliminable_occurrences (XVECEXP (x, i, j));
2870 /* Scan INSN and eliminate all eliminable registers in it.
2872 If REPLACE is nonzero, do the replacement destructively. Also
2873 delete the insn as dead it if it is setting an eliminable register.
2875 If REPLACE is zero, do all our allocations in reload_obstack.
2877 If no eliminations were done and this insn doesn't require any elimination
2878 processing (these are not identical conditions: it might be updating sp,
2879 but not referencing fp; this needs to be seen during reload_as_needed so
2880 that the offset between fp and sp can be taken into consideration), zero
2881 is returned. Otherwise, 1 is returned. */
2884 eliminate_regs_in_insn (rtx insn, int replace)
2886 int icode = recog_memoized (insn);
2887 rtx old_body = PATTERN (insn);
2888 int insn_is_asm = asm_noperands (old_body) >= 0;
2889 rtx old_set = single_set (insn);
2893 rtx substed_operand[MAX_RECOG_OPERANDS];
2894 rtx orig_operand[MAX_RECOG_OPERANDS];
2895 struct elim_table *ep;
2898 if (! insn_is_asm && icode < 0)
2900 if (GET_CODE (PATTERN (insn)) == USE
2901 || GET_CODE (PATTERN (insn)) == CLOBBER
2902 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2903 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2904 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2909 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2910 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2912 /* Check for setting an eliminable register. */
2913 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2914 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2916 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2917 /* If this is setting the frame pointer register to the
2918 hardware frame pointer register and this is an elimination
2919 that will be done (tested above), this insn is really
2920 adjusting the frame pointer downward to compensate for
2921 the adjustment done before a nonlocal goto. */
2922 if (ep->from == FRAME_POINTER_REGNUM
2923 && ep->to == HARD_FRAME_POINTER_REGNUM)
2925 rtx base = SET_SRC (old_set);
2926 rtx base_insn = insn;
2927 HOST_WIDE_INT offset = 0;
2929 while (base != ep->to_rtx)
2931 rtx prev_insn, prev_set;
2933 if (GET_CODE (base) == PLUS
2934 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2936 offset += INTVAL (XEXP (base, 1));
2937 base = XEXP (base, 0);
2939 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2940 && (prev_set = single_set (prev_insn)) != 0
2941 && rtx_equal_p (SET_DEST (prev_set), base))
2943 base = SET_SRC (prev_set);
2944 base_insn = prev_insn;
2950 if (base == ep->to_rtx)
2953 = plus_constant (ep->to_rtx, offset - ep->offset);
2955 new_body = old_body;
2958 new_body = copy_insn (old_body);
2959 if (REG_NOTES (insn))
2960 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2962 PATTERN (insn) = new_body;
2963 old_set = single_set (insn);
2965 /* First see if this insn remains valid when we
2966 make the change. If not, keep the INSN_CODE
2967 the same and let reload fit it up. */
2968 validate_change (insn, &SET_SRC (old_set), src, 1);
2969 validate_change (insn, &SET_DEST (old_set),
2971 if (! apply_change_group ())
2973 SET_SRC (old_set) = src;
2974 SET_DEST (old_set) = ep->to_rtx;
2983 /* In this case this insn isn't serving a useful purpose. We
2984 will delete it in reload_as_needed once we know that this
2985 elimination is, in fact, being done.
2987 If REPLACE isn't set, we can't delete this insn, but needn't
2988 process it since it won't be used unless something changes. */
2991 delete_dead_insn (insn);
2999 /* We allow one special case which happens to work on all machines we
3000 currently support: a single set with the source or a REG_EQUAL
3001 note being a PLUS of an eliminable register and a constant. */
3003 if (old_set && GET_CODE (SET_DEST (old_set)) == REG)
3005 /* First see if the source is of the form (plus (reg) CST). */
3006 if (GET_CODE (SET_SRC (old_set)) == PLUS
3007 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3008 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
3009 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
3010 plus_src = SET_SRC (old_set);
3011 else if (GET_CODE (SET_SRC (old_set)) == REG)
3013 /* Otherwise, see if we have a REG_EQUAL note of the form
3014 (plus (reg) CST). */
3016 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3018 if (REG_NOTE_KIND (links) == REG_EQUAL
3019 && GET_CODE (XEXP (links, 0)) == PLUS
3020 && GET_CODE (XEXP (XEXP (links, 0), 0)) == REG
3021 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT
3022 && REGNO (XEXP (XEXP (links, 0), 0)) < FIRST_PSEUDO_REGISTER)
3024 plus_src = XEXP (links, 0);
3032 rtx reg = XEXP (plus_src, 0);
3033 HOST_WIDE_INT offset = INTVAL (XEXP (plus_src, 1));
3035 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3036 if (ep->from_rtx == reg && ep->can_eliminate)
3038 offset += ep->offset;
3043 /* We assume here that if we need a PARALLEL with
3044 CLOBBERs for this assignment, we can do with the
3045 MATCH_SCRATCHes that add_clobbers allocates.
3046 There's not much we can do if that doesn't work. */
3047 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3051 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3054 rtvec vec = rtvec_alloc (num_clobbers + 1);
3056 vec->elem[0] = PATTERN (insn);
3057 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3058 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3060 if (INSN_CODE (insn) < 0)
3063 /* If we have a nonzero offset, and the source is already
3064 a simple REG, the following transformation would
3065 increase the cost of the insn by replacing a simple REG
3066 with (plus (reg sp) CST). So try only when plus_src
3067 comes from old_set proper, not REG_NOTES. */
3068 else if (SET_SRC (old_set) == plus_src)
3070 new_body = old_body;
3073 new_body = copy_insn (old_body);
3074 if (REG_NOTES (insn))
3075 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3077 PATTERN (insn) = new_body;
3078 old_set = single_set (insn);
3080 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3081 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3087 /* This can't have an effect on elimination offsets, so skip right
3093 /* Determine the effects of this insn on elimination offsets. */
3094 elimination_effects (old_body, 0);
3096 /* Eliminate all eliminable registers occurring in operands that
3097 can be handled by reload. */
3098 extract_insn (insn);
3099 for (i = 0; i < recog_data.n_operands; i++)
3101 orig_operand[i] = recog_data.operand[i];
3102 substed_operand[i] = recog_data.operand[i];
3104 /* For an asm statement, every operand is eliminable. */
3105 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3107 /* Check for setting a register that we know about. */
3108 if (recog_data.operand_type[i] != OP_IN
3109 && GET_CODE (orig_operand[i]) == REG)
3111 /* If we are assigning to a register that can be eliminated, it
3112 must be as part of a PARALLEL, since the code above handles
3113 single SETs. We must indicate that we can no longer
3114 eliminate this reg. */
3115 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3117 if (ep->from_rtx == orig_operand[i])
3118 ep->can_eliminate = 0;
3121 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3122 replace ? insn : NULL_RTX);
3123 if (substed_operand[i] != orig_operand[i])
3125 /* Terminate the search in check_eliminable_occurrences at
3127 *recog_data.operand_loc[i] = 0;
3129 /* If an output operand changed from a REG to a MEM and INSN is an
3130 insn, write a CLOBBER insn. */
3131 if (recog_data.operand_type[i] != OP_IN
3132 && GET_CODE (orig_operand[i]) == REG
3133 && GET_CODE (substed_operand[i]) == MEM
3135 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3140 for (i = 0; i < recog_data.n_dups; i++)
3141 *recog_data.dup_loc[i]
3142 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3144 /* If any eliminable remain, they aren't eliminable anymore. */
3145 check_eliminable_occurrences (old_body);
3147 /* Substitute the operands; the new values are in the substed_operand
3149 for (i = 0; i < recog_data.n_operands; i++)
3150 *recog_data.operand_loc[i] = substed_operand[i];
3151 for (i = 0; i < recog_data.n_dups; i++)
3152 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3154 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3155 re-recognize the insn. We do this in case we had a simple addition
3156 but now can do this as a load-address. This saves an insn in this
3158 If re-recognition fails, the old insn code number will still be used,
3159 and some register operands may have changed into PLUS expressions.
3160 These will be handled by find_reloads by loading them into a register
3165 /* If we aren't replacing things permanently and we changed something,
3166 make another copy to ensure that all the RTL is new. Otherwise
3167 things can go wrong if find_reload swaps commutative operands
3168 and one is inside RTL that has been copied while the other is not. */
3169 new_body = old_body;
3172 new_body = copy_insn (old_body);
3173 if (REG_NOTES (insn))
3174 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3176 PATTERN (insn) = new_body;
3178 /* If we had a move insn but now we don't, rerecognize it. This will
3179 cause spurious re-recognition if the old move had a PARALLEL since
3180 the new one still will, but we can't call single_set without
3181 having put NEW_BODY into the insn and the re-recognition won't
3182 hurt in this rare case. */
3183 /* ??? Why this huge if statement - why don't we just rerecognize the
3187 && ((GET_CODE (SET_SRC (old_set)) == REG
3188 && (GET_CODE (new_body) != SET
3189 || GET_CODE (SET_SRC (new_body)) != REG))
3190 /* If this was a load from or store to memory, compare
3191 the MEM in recog_data.operand to the one in the insn.
3192 If they are not equal, then rerecognize the insn. */
3194 && ((GET_CODE (SET_SRC (old_set)) == MEM
3195 && SET_SRC (old_set) != recog_data.operand[1])
3196 || (GET_CODE (SET_DEST (old_set)) == MEM
3197 && SET_DEST (old_set) != recog_data.operand[0])))
3198 /* If this was an add insn before, rerecognize. */
3199 || GET_CODE (SET_SRC (old_set)) == PLUS))
3201 int new_icode = recog (PATTERN (insn), insn, 0);
3203 INSN_CODE (insn) = icode;
3207 /* Restore the old body. If there were any changes to it, we made a copy
3208 of it while the changes were still in place, so we'll correctly return
3209 a modified insn below. */
3212 /* Restore the old body. */
3213 for (i = 0; i < recog_data.n_operands; i++)
3214 *recog_data.operand_loc[i] = orig_operand[i];
3215 for (i = 0; i < recog_data.n_dups; i++)
3216 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3219 /* Update all elimination pairs to reflect the status after the current
3220 insn. The changes we make were determined by the earlier call to
3221 elimination_effects.
3223 We also detect cases where register elimination cannot be done,
3224 namely, if a register would be both changed and referenced outside a MEM
3225 in the resulting insn since such an insn is often undefined and, even if
3226 not, we cannot know what meaning will be given to it. Note that it is
3227 valid to have a register used in an address in an insn that changes it
3228 (presumably with a pre- or post-increment or decrement).
3230 If anything changes, return nonzero. */
3232 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3234 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3235 ep->can_eliminate = 0;
3237 ep->ref_outside_mem = 0;
3239 if (ep->previous_offset != ep->offset)
3244 /* If we changed something, perform elimination in REG_NOTES. This is
3245 needed even when REPLACE is zero because a REG_DEAD note might refer
3246 to a register that we eliminate and could cause a different number
3247 of spill registers to be needed in the final reload pass than in
3249 if (val && REG_NOTES (insn) != 0)
3250 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3255 /* Loop through all elimination pairs.
3256 Recalculate the number not at initial offset.
3258 Compute the maximum offset (minimum offset if the stack does not
3259 grow downward) for each elimination pair. */
3262 update_eliminable_offsets (void)
3264 struct elim_table *ep;
3266 num_not_at_initial_offset = 0;
3267 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3269 ep->previous_offset = ep->offset;
3270 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3271 num_not_at_initial_offset++;
3275 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3276 replacement we currently believe is valid, mark it as not eliminable if X
3277 modifies DEST in any way other than by adding a constant integer to it.
3279 If DEST is the frame pointer, we do nothing because we assume that
3280 all assignments to the hard frame pointer are nonlocal gotos and are being
3281 done at a time when they are valid and do not disturb anything else.
3282 Some machines want to eliminate a fake argument pointer with either the
3283 frame or stack pointer. Assignments to the hard frame pointer must not
3284 prevent this elimination.
3286 Called via note_stores from reload before starting its passes to scan
3287 the insns of the function. */
3290 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3294 /* A SUBREG of a hard register here is just changing its mode. We should
3295 not see a SUBREG of an eliminable hard register, but check just in
3297 if (GET_CODE (dest) == SUBREG)
3298 dest = SUBREG_REG (dest);
3300 if (dest == hard_frame_pointer_rtx)
3303 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3304 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3305 && (GET_CODE (x) != SET
3306 || GET_CODE (SET_SRC (x)) != PLUS
3307 || XEXP (SET_SRC (x), 0) != dest
3308 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3310 reg_eliminate[i].can_eliminate_previous
3311 = reg_eliminate[i].can_eliminate = 0;
3316 /* Verify that the initial elimination offsets did not change since the
3317 last call to set_initial_elim_offsets. This is used to catch cases
3318 where something illegal happened during reload_as_needed that could
3319 cause incorrect code to be generated if we did not check for it. */
3322 verify_initial_elim_offsets (void)
3326 #ifdef ELIMINABLE_REGS
3327 struct elim_table *ep;
3329 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3331 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3332 if (t != ep->initial_offset)
3336 INITIAL_FRAME_POINTER_OFFSET (t);
3337 if (t != reg_eliminate[0].initial_offset)
3342 /* Reset all offsets on eliminable registers to their initial values. */
3345 set_initial_elim_offsets (void)
3347 struct elim_table *ep = reg_eliminate;
3349 #ifdef ELIMINABLE_REGS
3350 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3352 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3353 ep->previous_offset = ep->offset = ep->initial_offset;
3356 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3357 ep->previous_offset = ep->offset = ep->initial_offset;
3360 num_not_at_initial_offset = 0;
3363 /* Initialize the known label offsets.
3364 Set a known offset for each forced label to be at the initial offset
3365 of each elimination. We do this because we assume that all
3366 computed jumps occur from a location where each elimination is
3367 at its initial offset.
3368 For all other labels, show that we don't know the offsets. */
3371 set_initial_label_offsets (void)
3374 memset (offsets_known_at, 0, num_labels);
3376 for (x = forced_labels; x; x = XEXP (x, 1))
3378 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3381 /* Set all elimination offsets to the known values for the code label given
3385 set_offsets_for_label (rtx insn)
3388 int label_nr = CODE_LABEL_NUMBER (insn);
3389 struct elim_table *ep;
3391 num_not_at_initial_offset = 0;
3392 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3394 ep->offset = ep->previous_offset
3395 = offsets_at[label_nr - first_label_num][i];
3396 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3397 num_not_at_initial_offset++;
3401 /* See if anything that happened changes which eliminations are valid.
3402 For example, on the SPARC, whether or not the frame pointer can
3403 be eliminated can depend on what registers have been used. We need
3404 not check some conditions again (such as flag_omit_frame_pointer)
3405 since they can't have changed. */
3408 update_eliminables (HARD_REG_SET *pset)
3410 int previous_frame_pointer_needed = frame_pointer_needed;
3411 struct elim_table *ep;
3413 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3414 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3415 #ifdef ELIMINABLE_REGS
3416 || ! CAN_ELIMINATE (ep->from, ep->to)
3419 ep->can_eliminate = 0;
3421 /* Look for the case where we have discovered that we can't replace
3422 register A with register B and that means that we will now be
3423 trying to replace register A with register C. This means we can
3424 no longer replace register C with register B and we need to disable
3425 such an elimination, if it exists. This occurs often with A == ap,
3426 B == sp, and C == fp. */
3428 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3430 struct elim_table *op;
3433 if (! ep->can_eliminate && ep->can_eliminate_previous)
3435 /* Find the current elimination for ep->from, if there is a
3437 for (op = reg_eliminate;
3438 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3439 if (op->from == ep->from && op->can_eliminate)
3445 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3447 for (op = reg_eliminate;
3448 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3449 if (op->from == new_to && op->to == ep->to)
3450 op->can_eliminate = 0;
3454 /* See if any registers that we thought we could eliminate the previous
3455 time are no longer eliminable. If so, something has changed and we
3456 must spill the register. Also, recompute the number of eliminable
3457 registers and see if the frame pointer is needed; it is if there is
3458 no elimination of the frame pointer that we can perform. */
3460 frame_pointer_needed = 1;
3461 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3463 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3464 && ep->to != HARD_FRAME_POINTER_REGNUM)
3465 frame_pointer_needed = 0;
3467 if (! ep->can_eliminate && ep->can_eliminate_previous)
3469 ep->can_eliminate_previous = 0;
3470 SET_HARD_REG_BIT (*pset, ep->from);
3475 /* If we didn't need a frame pointer last time, but we do now, spill
3476 the hard frame pointer. */
3477 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3478 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3481 /* Initialize the table of registers to eliminate. */
3484 init_elim_table (void)
3486 struct elim_table *ep;
3487 #ifdef ELIMINABLE_REGS
3488 const struct elim_table_1 *ep1;
3492 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3494 /* Does this function require a frame pointer? */
3496 frame_pointer_needed = (! flag_omit_frame_pointer
3497 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3498 and restore sp for alloca. So we can't eliminate
3499 the frame pointer in that case. At some point,
3500 we should improve this by emitting the
3501 sp-adjusting insns for this case. */
3502 || (current_function_calls_alloca
3503 && EXIT_IGNORE_STACK)
3504 || FRAME_POINTER_REQUIRED);
3508 #ifdef ELIMINABLE_REGS
3509 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3510 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3512 ep->from = ep1->from;
3514 ep->can_eliminate = ep->can_eliminate_previous
3515 = (CAN_ELIMINATE (ep->from, ep->to)
3516 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3519 reg_eliminate[0].from = reg_eliminate_1[0].from;
3520 reg_eliminate[0].to = reg_eliminate_1[0].to;
3521 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3522 = ! frame_pointer_needed;
3525 /* Count the number of eliminable registers and build the FROM and TO
3526 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3527 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3528 We depend on this. */
3529 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3531 num_eliminable += ep->can_eliminate;
3532 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3533 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3537 /* Kick all pseudos out of hard register REGNO.
3539 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3540 because we found we can't eliminate some register. In the case, no pseudos
3541 are allowed to be in the register, even if they are only in a block that
3542 doesn't require spill registers, unlike the case when we are spilling this
3543 hard reg to produce another spill register.
3545 Return nonzero if any pseudos needed to be kicked out. */
3548 spill_hard_reg (unsigned int regno, int cant_eliminate)
3554 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3555 regs_ever_live[regno] = 1;
3558 /* Spill every pseudo reg that was allocated to this reg
3559 or to something that overlaps this reg. */
3561 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3562 if (reg_renumber[i] >= 0
3563 && (unsigned int) reg_renumber[i] <= regno
3564 && ((unsigned int) reg_renumber[i]
3565 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3566 [PSEUDO_REGNO_MODE (i)]
3568 SET_REGNO_REG_SET (&spilled_pseudos, i);
3571 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3572 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3575 ior_hard_reg_set (HARD_REG_SET *set1, HARD_REG_SET *set2)
3577 IOR_HARD_REG_SET (*set1, *set2);
3580 /* After find_reload_regs has been run for all insn that need reloads,
3581 and/or spill_hard_regs was called, this function is used to actually
3582 spill pseudo registers and try to reallocate them. It also sets up the
3583 spill_regs array for use by choose_reload_regs. */
3586 finish_spills (int global)
3588 struct insn_chain *chain;
3589 int something_changed = 0;
3592 /* Build the spill_regs array for the function. */
3593 /* If there are some registers still to eliminate and one of the spill regs
3594 wasn't ever used before, additional stack space may have to be
3595 allocated to store this register. Thus, we may have changed the offset
3596 between the stack and frame pointers, so mark that something has changed.
3598 One might think that we need only set VAL to 1 if this is a call-used
3599 register. However, the set of registers that must be saved by the
3600 prologue is not identical to the call-used set. For example, the
3601 register used by the call insn for the return PC is a call-used register,
3602 but must be saved by the prologue. */
3605 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3606 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3608 spill_reg_order[i] = n_spills;
3609 spill_regs[n_spills++] = i;
3610 if (num_eliminable && ! regs_ever_live[i])
3611 something_changed = 1;
3612 regs_ever_live[i] = 1;
3615 spill_reg_order[i] = -1;
3617 EXECUTE_IF_SET_IN_REG_SET
3618 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3620 /* Record the current hard register the pseudo is allocated to in
3621 pseudo_previous_regs so we avoid reallocating it to the same
3622 hard reg in a later pass. */
3623 if (reg_renumber[i] < 0)
3626 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3627 /* Mark it as no longer having a hard register home. */
3628 reg_renumber[i] = -1;
3629 /* We will need to scan everything again. */
3630 something_changed = 1;
3633 /* Retry global register allocation if possible. */
3636 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3637 /* For every insn that needs reloads, set the registers used as spill
3638 regs in pseudo_forbidden_regs for every pseudo live across the
3640 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3642 EXECUTE_IF_SET_IN_REG_SET
3643 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3645 ior_hard_reg_set (pseudo_forbidden_regs + i,
3646 &chain->used_spill_regs);
3648 EXECUTE_IF_SET_IN_REG_SET
3649 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3651 ior_hard_reg_set (pseudo_forbidden_regs + i,
3652 &chain->used_spill_regs);
3656 /* Retry allocating the spilled pseudos. For each reg, merge the
3657 various reg sets that indicate which hard regs can't be used,
3658 and call retry_global_alloc.
3659 We change spill_pseudos here to only contain pseudos that did not
3660 get a new hard register. */
3661 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3662 if (reg_old_renumber[i] != reg_renumber[i])
3664 HARD_REG_SET forbidden;
3665 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3666 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3667 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3668 retry_global_alloc (i, forbidden);
3669 if (reg_renumber[i] >= 0)
3670 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3674 /* Fix up the register information in the insn chain.
3675 This involves deleting those of the spilled pseudos which did not get
3676 a new hard register home from the live_{before,after} sets. */
3677 for (chain = reload_insn_chain; chain; chain = chain->next)
3679 HARD_REG_SET used_by_pseudos;
3680 HARD_REG_SET used_by_pseudos2;
3682 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3683 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3685 /* Mark any unallocated hard regs as available for spills. That
3686 makes inheritance work somewhat better. */
3687 if (chain->need_reload)
3689 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3690 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3691 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3693 /* Save the old value for the sanity test below. */
3694 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3696 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3697 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3698 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3699 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3701 /* Make sure we only enlarge the set. */
3702 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3708 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3709 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3711 int regno = reg_renumber[i];
3712 if (reg_old_renumber[i] == regno)
3715 alter_reg (i, reg_old_renumber[i]);
3716 reg_old_renumber[i] = regno;
3720 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3722 fprintf (dump_file, " Register %d now in %d.\n\n",
3723 i, reg_renumber[i]);
3727 return something_changed;
3730 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3733 scan_paradoxical_subregs (rtx x)
3737 enum rtx_code code = GET_CODE (x);
3747 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3755 if (GET_CODE (SUBREG_REG (x)) == REG
3756 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3757 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3758 = GET_MODE_SIZE (GET_MODE (x));
3765 fmt = GET_RTX_FORMAT (code);
3766 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3769 scan_paradoxical_subregs (XEXP (x, i));
3770 else if (fmt[i] == 'E')
3773 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3774 scan_paradoxical_subregs (XVECEXP (x, i, j));
3779 /* Reload pseudo-registers into hard regs around each insn as needed.
3780 Additional register load insns are output before the insn that needs it
3781 and perhaps store insns after insns that modify the reloaded pseudo reg.
3783 reg_last_reload_reg and reg_reloaded_contents keep track of
3784 which registers are already available in reload registers.
3785 We update these for the reloads that we perform,
3786 as the insns are scanned. */
3789 reload_as_needed (int live_known)
3791 struct insn_chain *chain;
3792 #if defined (AUTO_INC_DEC)
3797 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3798 memset (spill_reg_store, 0, sizeof spill_reg_store);
3799 reg_last_reload_reg = xcalloc (max_regno, sizeof (rtx));
3800 reg_has_output_reload = xmalloc (max_regno);
3801 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3802 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3804 set_initial_elim_offsets ();
3806 for (chain = reload_insn_chain; chain; chain = chain->next)
3809 rtx insn = chain->insn;
3810 rtx old_next = NEXT_INSN (insn);
3812 /* If we pass a label, copy the offsets from the label information
3813 into the current offsets of each elimination. */
3814 if (GET_CODE (insn) == CODE_LABEL)
3815 set_offsets_for_label (insn);
3817 else if (INSN_P (insn))
3819 rtx oldpat = copy_rtx (PATTERN (insn));
3821 /* If this is a USE and CLOBBER of a MEM, ensure that any
3822 references to eliminable registers have been removed. */
3824 if ((GET_CODE (PATTERN (insn)) == USE
3825 || GET_CODE (PATTERN (insn)) == CLOBBER)
3826 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3827 XEXP (XEXP (PATTERN (insn), 0), 0)
3828 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3829 GET_MODE (XEXP (PATTERN (insn), 0)),
3832 /* If we need to do register elimination processing, do so.
3833 This might delete the insn, in which case we are done. */
3834 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3836 eliminate_regs_in_insn (insn, 1);
3837 if (GET_CODE (insn) == NOTE)
3839 update_eliminable_offsets ();
3844 /* If need_elim is nonzero but need_reload is zero, one might think
3845 that we could simply set n_reloads to 0. However, find_reloads
3846 could have done some manipulation of the insn (such as swapping
3847 commutative operands), and these manipulations are lost during
3848 the first pass for every insn that needs register elimination.
3849 So the actions of find_reloads must be redone here. */
3851 if (! chain->need_elim && ! chain->need_reload
3852 && ! chain->need_operand_change)
3854 /* First find the pseudo regs that must be reloaded for this insn.
3855 This info is returned in the tables reload_... (see reload.h).
3856 Also modify the body of INSN by substituting RELOAD
3857 rtx's for those pseudo regs. */
3860 memset (reg_has_output_reload, 0, max_regno);
3861 CLEAR_HARD_REG_SET (reg_is_output_reload);
3863 find_reloads (insn, 1, spill_indirect_levels, live_known,
3869 rtx next = NEXT_INSN (insn);
3872 prev = PREV_INSN (insn);
3874 /* Now compute which reload regs to reload them into. Perhaps
3875 reusing reload regs from previous insns, or else output
3876 load insns to reload them. Maybe output store insns too.
3877 Record the choices of reload reg in reload_reg_rtx. */
3878 choose_reload_regs (chain);
3880 /* Merge any reloads that we didn't combine for fear of
3881 increasing the number of spill registers needed but now
3882 discover can be safely merged. */
3883 if (SMALL_REGISTER_CLASSES)
3884 merge_assigned_reloads (insn);
3886 /* Generate the insns to reload operands into or out of
3887 their reload regs. */
3888 emit_reload_insns (chain);
3890 /* Substitute the chosen reload regs from reload_reg_rtx
3891 into the insn's body (or perhaps into the bodies of other
3892 load and store insn that we just made for reloading
3893 and that we moved the structure into). */
3894 subst_reloads (insn);
3896 /* If this was an ASM, make sure that all the reload insns
3897 we have generated are valid. If not, give an error
3900 if (asm_noperands (PATTERN (insn)) >= 0)
3901 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3902 if (p != insn && INSN_P (p)
3903 && GET_CODE (PATTERN (p)) != USE
3904 && (recog_memoized (p) < 0
3905 || (extract_insn (p), ! constrain_operands (1))))
3907 error_for_asm (insn,
3908 "`asm' operand requires impossible reload");
3913 if (num_eliminable && chain->need_elim)
3914 update_eliminable_offsets ();
3916 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3917 is no longer validly lying around to save a future reload.
3918 Note that this does not detect pseudos that were reloaded
3919 for this insn in order to be stored in
3920 (obeying register constraints). That is correct; such reload
3921 registers ARE still valid. */
3922 note_stores (oldpat, forget_old_reloads_1, NULL);
3924 /* There may have been CLOBBER insns placed after INSN. So scan
3925 between INSN and NEXT and use them to forget old reloads. */
3926 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3927 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3928 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3931 /* Likewise for regs altered by auto-increment in this insn.
3932 REG_INC notes have been changed by reloading:
3933 find_reloads_address_1 records substitutions for them,
3934 which have been performed by subst_reloads above. */
3935 for (i = n_reloads - 1; i >= 0; i--)
3937 rtx in_reg = rld[i].in_reg;
3940 enum rtx_code code = GET_CODE (in_reg);
3941 /* PRE_INC / PRE_DEC will have the reload register ending up
3942 with the same value as the stack slot, but that doesn't
3943 hold true for POST_INC / POST_DEC. Either we have to
3944 convert the memory access to a true POST_INC / POST_DEC,
3945 or we can't use the reload register for inheritance. */
3946 if ((code == POST_INC || code == POST_DEC)
3947 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3948 REGNO (rld[i].reg_rtx))
3949 /* Make sure it is the inc/dec pseudo, and not
3950 some other (e.g. output operand) pseudo. */
3951 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3952 == REGNO (XEXP (in_reg, 0))))
3955 rtx reload_reg = rld[i].reg_rtx;
3956 enum machine_mode mode = GET_MODE (reload_reg);
3960 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3962 /* We really want to ignore REG_INC notes here, so
3963 use PATTERN (p) as argument to reg_set_p . */
3964 if (reg_set_p (reload_reg, PATTERN (p)))
3966 n = count_occurrences (PATTERN (p), reload_reg, 0);
3971 n = validate_replace_rtx (reload_reg,
3972 gen_rtx_fmt_e (code,
3977 /* We must also verify that the constraints
3978 are met after the replacement. */
3981 n = constrain_operands (1);
3985 /* If the constraints were not met, then
3986 undo the replacement. */
3989 validate_replace_rtx (gen_rtx_fmt_e (code,
4002 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4004 /* Mark this as having an output reload so that the
4005 REG_INC processing code below won't invalidate
4006 the reload for inheritance. */
4007 SET_HARD_REG_BIT (reg_is_output_reload,
4008 REGNO (reload_reg));
4009 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4012 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4015 else if ((code == PRE_INC || code == PRE_DEC)
4016 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4017 REGNO (rld[i].reg_rtx))
4018 /* Make sure it is the inc/dec pseudo, and not
4019 some other (e.g. output operand) pseudo. */
4020 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4021 == REGNO (XEXP (in_reg, 0))))
4023 SET_HARD_REG_BIT (reg_is_output_reload,
4024 REGNO (rld[i].reg_rtx));
4025 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4029 /* If a pseudo that got a hard register is auto-incremented,
4030 we must purge records of copying it into pseudos without
4032 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4033 if (REG_NOTE_KIND (x) == REG_INC)
4035 /* See if this pseudo reg was reloaded in this insn.
4036 If so, its last-reload info is still valid
4037 because it is based on this insn's reload. */
4038 for (i = 0; i < n_reloads; i++)
4039 if (rld[i].out == XEXP (x, 0))
4043 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4047 /* A reload reg's contents are unknown after a label. */
4048 if (GET_CODE (insn) == CODE_LABEL)
4049 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4051 /* Don't assume a reload reg is still good after a call insn
4052 if it is a call-used reg, or if it contains a value that will
4053 be partially clobbered by the call. */
4054 else if (GET_CODE (insn) == CALL_INSN)
4056 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4057 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4062 free (reg_last_reload_reg);
4063 free (reg_has_output_reload);
4066 /* Discard all record of any value reloaded from X,
4067 or reloaded in X from someplace else;
4068 unless X is an output reload reg of the current insn.
4070 X may be a hard reg (the reload reg)
4071 or it may be a pseudo reg that was reloaded from. */
4074 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4075 void *data ATTRIBUTE_UNUSED)
4080 /* note_stores does give us subregs of hard regs,
4081 subreg_regno_offset will abort if it is not a hard reg. */
4082 while (GET_CODE (x) == SUBREG)
4084 /* We ignore the subreg offset when calculating the regno,
4085 because we are using the entire underlying hard register
4090 if (GET_CODE (x) != REG)
4095 if (regno >= FIRST_PSEUDO_REGISTER)
4101 nr = hard_regno_nregs[regno][GET_MODE (x)];
4102 /* Storing into a spilled-reg invalidates its contents.
4103 This can happen if a block-local pseudo is allocated to that reg
4104 and it wasn't spilled because this block's total need is 0.
4105 Then some insn might have an optional reload and use this reg. */
4106 for (i = 0; i < nr; i++)
4107 /* But don't do this if the reg actually serves as an output
4108 reload reg in the current instruction. */
4110 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4112 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4113 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4114 spill_reg_store[regno + i] = 0;
4118 /* Since value of X has changed,
4119 forget any value previously copied from it. */
4122 /* But don't forget a copy if this is the output reload
4123 that establishes the copy's validity. */
4124 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4125 reg_last_reload_reg[regno + nr] = 0;
4128 /* The following HARD_REG_SETs indicate when each hard register is
4129 used for a reload of various parts of the current insn. */
4131 /* If reg is unavailable for all reloads. */
4132 static HARD_REG_SET reload_reg_unavailable;
4133 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4134 static HARD_REG_SET reload_reg_used;
4135 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4136 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4137 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4138 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4139 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4140 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4141 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4142 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4143 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4144 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4145 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4146 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4147 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4148 static HARD_REG_SET reload_reg_used_in_op_addr;
4149 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4150 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4151 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4152 static HARD_REG_SET reload_reg_used_in_insn;
4153 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4154 static HARD_REG_SET reload_reg_used_in_other_addr;
4156 /* If reg is in use as a reload reg for any sort of reload. */
4157 static HARD_REG_SET reload_reg_used_at_all;
4159 /* If reg is use as an inherited reload. We just mark the first register
4161 static HARD_REG_SET reload_reg_used_for_inherit;
4163 /* Records which hard regs are used in any way, either as explicit use or
4164 by being allocated to a pseudo during any point of the current insn. */
4165 static HARD_REG_SET reg_used_in_insn;
4167 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4168 TYPE. MODE is used to indicate how many consecutive regs are
4172 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4173 enum machine_mode mode)
4175 unsigned int nregs = hard_regno_nregs[regno][mode];
4178 for (i = regno; i < nregs + regno; i++)
4183 SET_HARD_REG_BIT (reload_reg_used, i);
4186 case RELOAD_FOR_INPUT_ADDRESS:
4187 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4190 case RELOAD_FOR_INPADDR_ADDRESS:
4191 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4194 case RELOAD_FOR_OUTPUT_ADDRESS:
4195 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4198 case RELOAD_FOR_OUTADDR_ADDRESS:
4199 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4202 case RELOAD_FOR_OPERAND_ADDRESS:
4203 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4206 case RELOAD_FOR_OPADDR_ADDR:
4207 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4210 case RELOAD_FOR_OTHER_ADDRESS:
4211 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4214 case RELOAD_FOR_INPUT:
4215 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4218 case RELOAD_FOR_OUTPUT:
4219 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4222 case RELOAD_FOR_INSN:
4223 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4227 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4231 /* Similarly, but show REGNO is no longer in use for a reload. */
4234 clear_reload_reg_in_use (unsigned int regno, int opnum,
4235 enum reload_type type, enum machine_mode mode)
4237 unsigned int nregs = hard_regno_nregs[regno][mode];
4238 unsigned int start_regno, end_regno, r;
4240 /* A complication is that for some reload types, inheritance might
4241 allow multiple reloads of the same types to share a reload register.
4242 We set check_opnum if we have to check only reloads with the same
4243 operand number, and check_any if we have to check all reloads. */
4244 int check_opnum = 0;
4246 HARD_REG_SET *used_in_set;
4251 used_in_set = &reload_reg_used;
4254 case RELOAD_FOR_INPUT_ADDRESS:
4255 used_in_set = &reload_reg_used_in_input_addr[opnum];
4258 case RELOAD_FOR_INPADDR_ADDRESS:
4260 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4263 case RELOAD_FOR_OUTPUT_ADDRESS:
4264 used_in_set = &reload_reg_used_in_output_addr[opnum];
4267 case RELOAD_FOR_OUTADDR_ADDRESS:
4269 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4272 case RELOAD_FOR_OPERAND_ADDRESS:
4273 used_in_set = &reload_reg_used_in_op_addr;
4276 case RELOAD_FOR_OPADDR_ADDR:
4278 used_in_set = &reload_reg_used_in_op_addr_reload;
4281 case RELOAD_FOR_OTHER_ADDRESS:
4282 used_in_set = &reload_reg_used_in_other_addr;
4286 case RELOAD_FOR_INPUT:
4287 used_in_set = &reload_reg_used_in_input[opnum];
4290 case RELOAD_FOR_OUTPUT:
4291 used_in_set = &reload_reg_used_in_output[opnum];
4294 case RELOAD_FOR_INSN:
4295 used_in_set = &reload_reg_used_in_insn;
4300 /* We resolve conflicts with remaining reloads of the same type by
4301 excluding the intervals of reload registers by them from the
4302 interval of freed reload registers. Since we only keep track of
4303 one set of interval bounds, we might have to exclude somewhat
4304 more than what would be necessary if we used a HARD_REG_SET here.
4305 But this should only happen very infrequently, so there should
4306 be no reason to worry about it. */
4308 start_regno = regno;
4309 end_regno = regno + nregs;
4310 if (check_opnum || check_any)
4312 for (i = n_reloads - 1; i >= 0; i--)
4314 if (rld[i].when_needed == type
4315 && (check_any || rld[i].opnum == opnum)
4318 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4319 unsigned int conflict_end
4321 + hard_regno_nregs[conflict_start][rld[i].mode]);
4323 /* If there is an overlap with the first to-be-freed register,
4324 adjust the interval start. */
4325 if (conflict_start <= start_regno && conflict_end > start_regno)
4326 start_regno = conflict_end;
4327 /* Otherwise, if there is a conflict with one of the other
4328 to-be-freed registers, adjust the interval end. */
4329 if (conflict_start > start_regno && conflict_start < end_regno)
4330 end_regno = conflict_start;
4335 for (r = start_regno; r < end_regno; r++)
4336 CLEAR_HARD_REG_BIT (*used_in_set, r);
4339 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4340 specified by OPNUM and TYPE. */
4343 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4347 /* In use for a RELOAD_OTHER means it's not available for anything. */
4348 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4349 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4355 /* In use for anything means we can't use it for RELOAD_OTHER. */
4356 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4357 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4358 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4359 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4362 for (i = 0; i < reload_n_operands; i++)
4363 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4364 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4365 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4366 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4367 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4368 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4373 case RELOAD_FOR_INPUT:
4374 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4375 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4378 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4381 /* If it is used for some other input, can't use it. */
4382 for (i = 0; i < reload_n_operands; i++)
4383 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4386 /* If it is used in a later operand's address, can't use it. */
4387 for (i = opnum + 1; i < reload_n_operands; i++)
4388 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4389 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4394 case RELOAD_FOR_INPUT_ADDRESS:
4395 /* Can't use a register if it is used for an input address for this
4396 operand or used as an input in an earlier one. */
4397 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4398 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4401 for (i = 0; i < opnum; i++)
4402 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4407 case RELOAD_FOR_INPADDR_ADDRESS:
4408 /* Can't use a register if it is used for an input address
4409 for this operand or used as an input in an earlier
4411 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4414 for (i = 0; i < opnum; i++)
4415 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4420 case RELOAD_FOR_OUTPUT_ADDRESS:
4421 /* Can't use a register if it is used for an output address for this
4422 operand or used as an output in this or a later operand. Note
4423 that multiple output operands are emitted in reverse order, so
4424 the conflicting ones are those with lower indices. */
4425 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4428 for (i = 0; i <= opnum; i++)
4429 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4434 case RELOAD_FOR_OUTADDR_ADDRESS:
4435 /* Can't use a register if it is used for an output address
4436 for this operand or used as an output in this or a
4437 later operand. Note that multiple output operands are
4438 emitted in reverse order, so the conflicting ones are
4439 those with lower indices. */
4440 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4443 for (i = 0; i <= opnum; i++)
4444 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4449 case RELOAD_FOR_OPERAND_ADDRESS:
4450 for (i = 0; i < reload_n_operands; i++)
4451 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4454 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4455 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4457 case RELOAD_FOR_OPADDR_ADDR:
4458 for (i = 0; i < reload_n_operands; i++)
4459 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4462 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4464 case RELOAD_FOR_OUTPUT:
4465 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4466 outputs, or an operand address for this or an earlier output.
4467 Note that multiple output operands are emitted in reverse order,
4468 so the conflicting ones are those with higher indices. */
4469 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4472 for (i = 0; i < reload_n_operands; i++)
4473 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4476 for (i = opnum; i < reload_n_operands; i++)
4477 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4478 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4483 case RELOAD_FOR_INSN:
4484 for (i = 0; i < reload_n_operands; i++)
4485 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4486 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4489 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4490 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4492 case RELOAD_FOR_OTHER_ADDRESS:
4493 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4498 /* Return 1 if the value in reload reg REGNO, as used by a reload
4499 needed for the part of the insn specified by OPNUM and TYPE,
4500 is still available in REGNO at the end of the insn.
4502 We can assume that the reload reg was already tested for availability
4503 at the time it is needed, and we should not check this again,
4504 in case the reg has already been marked in use. */
4507 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4514 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4515 its value must reach the end. */
4518 /* If this use is for part of the insn,
4519 its value reaches if no subsequent part uses the same register.
4520 Just like the above function, don't try to do this with lots
4523 case RELOAD_FOR_OTHER_ADDRESS:
4524 /* Here we check for everything else, since these don't conflict
4525 with anything else and everything comes later. */
4527 for (i = 0; i < reload_n_operands; i++)
4528 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4529 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4530 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4531 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4532 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4533 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4536 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4537 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4538 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4539 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4541 case RELOAD_FOR_INPUT_ADDRESS:
4542 case RELOAD_FOR_INPADDR_ADDRESS:
4543 /* Similar, except that we check only for this and subsequent inputs
4544 and the address of only subsequent inputs and we do not need
4545 to check for RELOAD_OTHER objects since they are known not to
4548 for (i = opnum; i < reload_n_operands; i++)
4549 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4552 for (i = opnum + 1; i < reload_n_operands; i++)
4553 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4554 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4557 for (i = 0; i < reload_n_operands; i++)
4558 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4559 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4560 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4563 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4566 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4567 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4568 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4570 case RELOAD_FOR_INPUT:
4571 /* Similar to input address, except we start at the next operand for
4572 both input and input address and we do not check for
4573 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4576 for (i = opnum + 1; i < reload_n_operands; i++)
4577 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4578 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4579 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4582 /* ... fall through ... */
4584 case RELOAD_FOR_OPERAND_ADDRESS:
4585 /* Check outputs and their addresses. */
4587 for (i = 0; i < reload_n_operands; i++)
4588 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4589 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4590 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4593 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4595 case RELOAD_FOR_OPADDR_ADDR:
4596 for (i = 0; i < reload_n_operands; i++)
4597 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4598 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4599 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4602 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4603 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4604 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4606 case RELOAD_FOR_INSN:
4607 /* These conflict with other outputs with RELOAD_OTHER. So
4608 we need only check for output addresses. */
4610 opnum = reload_n_operands;
4612 /* ... fall through ... */
4614 case RELOAD_FOR_OUTPUT:
4615 case RELOAD_FOR_OUTPUT_ADDRESS:
4616 case RELOAD_FOR_OUTADDR_ADDRESS:
4617 /* We already know these can't conflict with a later output. So the
4618 only thing to check are later output addresses.
4619 Note that multiple output operands are emitted in reverse order,
4620 so the conflicting ones are those with lower indices. */
4621 for (i = 0; i < opnum; i++)
4622 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4623 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4632 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4635 This function uses the same algorithm as reload_reg_free_p above. */
4638 reloads_conflict (int r1, int r2)
4640 enum reload_type r1_type = rld[r1].when_needed;
4641 enum reload_type r2_type = rld[r2].when_needed;
4642 int r1_opnum = rld[r1].opnum;
4643 int r2_opnum = rld[r2].opnum;
4645 /* RELOAD_OTHER conflicts with everything. */
4646 if (r2_type == RELOAD_OTHER)
4649 /* Otherwise, check conflicts differently for each type. */
4653 case RELOAD_FOR_INPUT:
4654 return (r2_type == RELOAD_FOR_INSN
4655 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4656 || r2_type == RELOAD_FOR_OPADDR_ADDR
4657 || r2_type == RELOAD_FOR_INPUT
4658 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4659 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4660 && r2_opnum > r1_opnum));
4662 case RELOAD_FOR_INPUT_ADDRESS:
4663 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4664 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4666 case RELOAD_FOR_INPADDR_ADDRESS:
4667 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4668 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4670 case RELOAD_FOR_OUTPUT_ADDRESS:
4671 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4672 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4674 case RELOAD_FOR_OUTADDR_ADDRESS:
4675 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4676 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4678 case RELOAD_FOR_OPERAND_ADDRESS:
4679 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4680 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4682 case RELOAD_FOR_OPADDR_ADDR:
4683 return (r2_type == RELOAD_FOR_INPUT
4684 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4686 case RELOAD_FOR_OUTPUT:
4687 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4688 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4689 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4690 && r2_opnum >= r1_opnum));
4692 case RELOAD_FOR_INSN:
4693 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4694 || r2_type == RELOAD_FOR_INSN
4695 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4697 case RELOAD_FOR_OTHER_ADDRESS:
4698 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4708 /* Indexed by reload number, 1 if incoming value
4709 inherited from previous insns. */
4710 char reload_inherited[MAX_RELOADS];
4712 /* For an inherited reload, this is the insn the reload was inherited from,
4713 if we know it. Otherwise, this is 0. */
4714 rtx reload_inheritance_insn[MAX_RELOADS];
4716 /* If nonzero, this is a place to get the value of the reload,
4717 rather than using reload_in. */
4718 rtx reload_override_in[MAX_RELOADS];
4720 /* For each reload, the hard register number of the register used,
4721 or -1 if we did not need a register for this reload. */
4722 int reload_spill_index[MAX_RELOADS];
4724 /* Subroutine of free_for_value_p, used to check a single register.
4725 START_REGNO is the starting regno of the full reload register
4726 (possibly comprising multiple hard registers) that we are considering. */
4729 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4730 enum reload_type type, rtx value, rtx out,
4731 int reloadnum, int ignore_address_reloads)
4734 /* Set if we see an input reload that must not share its reload register
4735 with any new earlyclobber, but might otherwise share the reload
4736 register with an output or input-output reload. */
4737 int check_earlyclobber = 0;
4741 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4744 if (out == const0_rtx)
4750 /* We use some pseudo 'time' value to check if the lifetimes of the
4751 new register use would overlap with the one of a previous reload
4752 that is not read-only or uses a different value.
4753 The 'time' used doesn't have to be linear in any shape or form, just
4755 Some reload types use different 'buckets' for each operand.
4756 So there are MAX_RECOG_OPERANDS different time values for each
4758 We compute TIME1 as the time when the register for the prospective
4759 new reload ceases to be live, and TIME2 for each existing
4760 reload as the time when that the reload register of that reload
4762 Where there is little to be gained by exact lifetime calculations,
4763 we just make conservative assumptions, i.e. a longer lifetime;
4764 this is done in the 'default:' cases. */
4767 case RELOAD_FOR_OTHER_ADDRESS:
4768 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4769 time1 = copy ? 0 : 1;
4772 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4774 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4775 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4776 respectively, to the time values for these, we get distinct time
4777 values. To get distinct time values for each operand, we have to
4778 multiply opnum by at least three. We round that up to four because
4779 multiply by four is often cheaper. */
4780 case RELOAD_FOR_INPADDR_ADDRESS:
4781 time1 = opnum * 4 + 2;
4783 case RELOAD_FOR_INPUT_ADDRESS:
4784 time1 = opnum * 4 + 3;
4786 case RELOAD_FOR_INPUT:
4787 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4788 executes (inclusive). */
4789 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4791 case RELOAD_FOR_OPADDR_ADDR:
4793 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4794 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4796 case RELOAD_FOR_OPERAND_ADDRESS:
4797 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4799 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4801 case RELOAD_FOR_OUTADDR_ADDRESS:
4802 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4804 case RELOAD_FOR_OUTPUT_ADDRESS:
4805 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4808 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4811 for (i = 0; i < n_reloads; i++)
4813 rtx reg = rld[i].reg_rtx;
4814 if (reg && GET_CODE (reg) == REG
4815 && ((unsigned) regno - true_regnum (reg)
4816 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
4819 rtx other_input = rld[i].in;
4821 /* If the other reload loads the same input value, that
4822 will not cause a conflict only if it's loading it into
4823 the same register. */
4824 if (true_regnum (reg) != start_regno)
4825 other_input = NULL_RTX;
4826 if (! other_input || ! rtx_equal_p (other_input, value)
4827 || rld[i].out || out)
4830 switch (rld[i].when_needed)
4832 case RELOAD_FOR_OTHER_ADDRESS:
4835 case RELOAD_FOR_INPADDR_ADDRESS:
4836 /* find_reloads makes sure that a
4837 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4838 by at most one - the first -
4839 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4840 address reload is inherited, the address address reload
4841 goes away, so we can ignore this conflict. */
4842 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4843 && ignore_address_reloads
4844 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4845 Then the address address is still needed to store
4846 back the new address. */
4847 && ! rld[reloadnum].out)
4849 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4850 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4852 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4853 && ignore_address_reloads
4854 /* Unless we are reloading an auto_inc expression. */
4855 && ! rld[reloadnum].out)
4857 time2 = rld[i].opnum * 4 + 2;
4859 case RELOAD_FOR_INPUT_ADDRESS:
4860 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4861 && ignore_address_reloads
4862 && ! rld[reloadnum].out)
4864 time2 = rld[i].opnum * 4 + 3;
4866 case RELOAD_FOR_INPUT:
4867 time2 = rld[i].opnum * 4 + 4;
4868 check_earlyclobber = 1;
4870 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4871 == MAX_RECOG_OPERAND * 4 */
4872 case RELOAD_FOR_OPADDR_ADDR:
4873 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4874 && ignore_address_reloads
4875 && ! rld[reloadnum].out)
4877 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4879 case RELOAD_FOR_OPERAND_ADDRESS:
4880 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4881 check_earlyclobber = 1;
4883 case RELOAD_FOR_INSN:
4884 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4886 case RELOAD_FOR_OUTPUT:
4887 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4888 instruction is executed. */
4889 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4891 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4892 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4894 case RELOAD_FOR_OUTADDR_ADDRESS:
4895 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4896 && ignore_address_reloads
4897 && ! rld[reloadnum].out)
4899 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4901 case RELOAD_FOR_OUTPUT_ADDRESS:
4902 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4905 /* If there is no conflict in the input part, handle this
4906 like an output reload. */
4907 if (! rld[i].in || rtx_equal_p (other_input, value))
4909 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4910 /* Earlyclobbered outputs must conflict with inputs. */
4911 if (earlyclobber_operand_p (rld[i].out))
4912 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4917 /* RELOAD_OTHER might be live beyond instruction execution,
4918 but this is not obvious when we set time2 = 1. So check
4919 here if there might be a problem with the new reload
4920 clobbering the register used by the RELOAD_OTHER. */
4928 && (! rld[i].in || rld[i].out
4929 || ! rtx_equal_p (other_input, value)))
4930 || (out && rld[reloadnum].out_reg
4931 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4937 /* Earlyclobbered outputs must conflict with inputs. */
4938 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4944 /* Return 1 if the value in reload reg REGNO, as used by a reload
4945 needed for the part of the insn specified by OPNUM and TYPE,
4946 may be used to load VALUE into it.
4948 MODE is the mode in which the register is used, this is needed to
4949 determine how many hard regs to test.
4951 Other read-only reloads with the same value do not conflict
4952 unless OUT is nonzero and these other reloads have to live while
4953 output reloads live.
4954 If OUT is CONST0_RTX, this is a special case: it means that the
4955 test should not be for using register REGNO as reload register, but
4956 for copying from register REGNO into the reload register.
4958 RELOADNUM is the number of the reload we want to load this value for;
4959 a reload does not conflict with itself.
4961 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4962 reloads that load an address for the very reload we are considering.
4964 The caller has to make sure that there is no conflict with the return
4968 free_for_value_p (int regno, enum machine_mode mode, int opnum,
4969 enum reload_type type, rtx value, rtx out, int reloadnum,
4970 int ignore_address_reloads)
4972 int nregs = hard_regno_nregs[regno][mode];
4974 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4975 value, out, reloadnum,
4976 ignore_address_reloads))
4981 /* Return nonzero if the rtx X is invariant over the current function. */
4982 /* ??? Actually, the places where we use this expect exactly what
4983 * is tested here, and not everything that is function invariant. In
4984 * particular, the frame pointer and arg pointer are special cased;
4985 * pic_offset_table_rtx is not, and this will cause aborts when we
4986 * go to spill these things to memory. */
4989 function_invariant_p (rtx x)
4993 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4995 if (GET_CODE (x) == PLUS
4996 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
4997 && CONSTANT_P (XEXP (x, 1)))
5002 /* Determine whether the reload reg X overlaps any rtx'es used for
5003 overriding inheritance. Return nonzero if so. */
5006 conflicts_with_override (rtx x)
5009 for (i = 0; i < n_reloads; i++)
5010 if (reload_override_in[i]
5011 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5016 /* Give an error message saying we failed to find a reload for INSN,
5017 and clear out reload R. */
5019 failed_reload (rtx insn, int r)
5021 if (asm_noperands (PATTERN (insn)) < 0)
5022 /* It's the compiler's fault. */
5023 fatal_insn ("could not find a spill register", insn);
5025 /* It's the user's fault; the operand's mode and constraint
5026 don't match. Disable this reload so we don't crash in final. */
5027 error_for_asm (insn,
5028 "`asm' operand constraint incompatible with operand size");
5032 rld[r].optional = 1;
5033 rld[r].secondary_p = 1;
5036 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5037 for reload R. If it's valid, get an rtx for it. Return nonzero if
5040 set_reload_reg (int i, int r)
5043 rtx reg = spill_reg_rtx[i];
5045 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5046 spill_reg_rtx[i] = reg
5047 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5049 regno = true_regnum (reg);
5051 /* Detect when the reload reg can't hold the reload mode.
5052 This used to be one `if', but Sequent compiler can't handle that. */
5053 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5055 enum machine_mode test_mode = VOIDmode;
5057 test_mode = GET_MODE (rld[r].in);
5058 /* If rld[r].in has VOIDmode, it means we will load it
5059 in whatever mode the reload reg has: to wit, rld[r].mode.
5060 We have already tested that for validity. */
5061 /* Aside from that, we need to test that the expressions
5062 to reload from or into have modes which are valid for this
5063 reload register. Otherwise the reload insns would be invalid. */
5064 if (! (rld[r].in != 0 && test_mode != VOIDmode
5065 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5066 if (! (rld[r].out != 0
5067 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5069 /* The reg is OK. */
5072 /* Mark as in use for this insn the reload regs we use
5074 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5075 rld[r].when_needed, rld[r].mode);
5077 rld[r].reg_rtx = reg;
5078 reload_spill_index[r] = spill_regs[i];
5085 /* Find a spill register to use as a reload register for reload R.
5086 LAST_RELOAD is nonzero if this is the last reload for the insn being
5089 Set rld[R].reg_rtx to the register allocated.
5091 We return 1 if successful, or 0 if we couldn't find a spill reg and
5092 we didn't change anything. */
5095 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5100 /* If we put this reload ahead, thinking it is a group,
5101 then insist on finding a group. Otherwise we can grab a
5102 reg that some other reload needs.
5103 (That can happen when we have a 68000 DATA_OR_FP_REG
5104 which is a group of data regs or one fp reg.)
5105 We need not be so restrictive if there are no more reloads
5108 ??? Really it would be nicer to have smarter handling
5109 for that kind of reg class, where a problem like this is normal.
5110 Perhaps those classes should be avoided for reloading
5111 by use of more alternatives. */
5113 int force_group = rld[r].nregs > 1 && ! last_reload;
5115 /* If we want a single register and haven't yet found one,
5116 take any reg in the right class and not in use.
5117 If we want a consecutive group, here is where we look for it.
5119 We use two passes so we can first look for reload regs to
5120 reuse, which are already in use for other reloads in this insn,
5121 and only then use additional registers.
5122 I think that maximizing reuse is needed to make sure we don't
5123 run out of reload regs. Suppose we have three reloads, and
5124 reloads A and B can share regs. These need two regs.
5125 Suppose A and B are given different regs.
5126 That leaves none for C. */
5127 for (pass = 0; pass < 2; pass++)
5129 /* I is the index in spill_regs.
5130 We advance it round-robin between insns to use all spill regs
5131 equally, so that inherited reloads have a chance
5132 of leapfrogging each other. */
5136 for (count = 0; count < n_spills; count++)
5138 int class = (int) rld[r].class;
5144 regnum = spill_regs[i];
5146 if ((reload_reg_free_p (regnum, rld[r].opnum,
5149 /* We check reload_reg_used to make sure we
5150 don't clobber the return register. */
5151 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5152 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5153 rld[r].when_needed, rld[r].in,
5155 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5156 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5157 /* Look first for regs to share, then for unshared. But
5158 don't share regs used for inherited reloads; they are
5159 the ones we want to preserve. */
5161 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5163 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5166 int nr = hard_regno_nregs[regnum][rld[r].mode];
5167 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5168 (on 68000) got us two FP regs. If NR is 1,
5169 we would reject both of them. */
5172 /* If we need only one reg, we have already won. */
5175 /* But reject a single reg if we demand a group. */
5180 /* Otherwise check that as many consecutive regs as we need
5181 are available here. */
5184 int regno = regnum + nr - 1;
5185 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5186 && spill_reg_order[regno] >= 0
5187 && reload_reg_free_p (regno, rld[r].opnum,
5188 rld[r].when_needed)))
5197 /* If we found something on pass 1, omit pass 2. */
5198 if (count < n_spills)
5202 /* We should have found a spill register by now. */
5203 if (count >= n_spills)
5206 /* I is the index in SPILL_REG_RTX of the reload register we are to
5207 allocate. Get an rtx for it and find its register number. */
5209 return set_reload_reg (i, r);
5212 /* Initialize all the tables needed to allocate reload registers.
5213 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5214 is the array we use to restore the reg_rtx field for every reload. */
5217 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5221 for (i = 0; i < n_reloads; i++)
5222 rld[i].reg_rtx = save_reload_reg_rtx[i];
5224 memset (reload_inherited, 0, MAX_RELOADS);
5225 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5226 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5228 CLEAR_HARD_REG_SET (reload_reg_used);
5229 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5230 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5231 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5232 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5233 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5235 CLEAR_HARD_REG_SET (reg_used_in_insn);
5238 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5239 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5240 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5241 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5242 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5243 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5246 for (i = 0; i < reload_n_operands; i++)
5248 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5249 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5250 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5251 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5252 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5253 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5256 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5258 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5260 for (i = 0; i < n_reloads; i++)
5261 /* If we have already decided to use a certain register,
5262 don't use it in another way. */
5264 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5265 rld[i].when_needed, rld[i].mode);
5268 /* Assign hard reg targets for the pseudo-registers we must reload
5269 into hard regs for this insn.
5270 Also output the instructions to copy them in and out of the hard regs.
5272 For machines with register classes, we are responsible for
5273 finding a reload reg in the proper class. */
5276 choose_reload_regs (struct insn_chain *chain)
5278 rtx insn = chain->insn;
5280 unsigned int max_group_size = 1;
5281 enum reg_class group_class = NO_REGS;
5282 int pass, win, inheritance;
5284 rtx save_reload_reg_rtx[MAX_RELOADS];
5286 /* In order to be certain of getting the registers we need,
5287 we must sort the reloads into order of increasing register class.
5288 Then our grabbing of reload registers will parallel the process
5289 that provided the reload registers.
5291 Also note whether any of the reloads wants a consecutive group of regs.
5292 If so, record the maximum size of the group desired and what
5293 register class contains all the groups needed by this insn. */
5295 for (j = 0; j < n_reloads; j++)
5297 reload_order[j] = j;
5298 reload_spill_index[j] = -1;
5300 if (rld[j].nregs > 1)
5302 max_group_size = MAX (rld[j].nregs, max_group_size);
5304 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5307 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5311 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5313 /* If -O, try first with inheritance, then turning it off.
5314 If not -O, don't do inheritance.
5315 Using inheritance when not optimizing leads to paradoxes
5316 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5317 because one side of the comparison might be inherited. */
5319 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5321 choose_reload_regs_init (chain, save_reload_reg_rtx);
5323 /* Process the reloads in order of preference just found.
5324 Beyond this point, subregs can be found in reload_reg_rtx.
5326 This used to look for an existing reloaded home for all of the
5327 reloads, and only then perform any new reloads. But that could lose
5328 if the reloads were done out of reg-class order because a later
5329 reload with a looser constraint might have an old home in a register
5330 needed by an earlier reload with a tighter constraint.
5332 To solve this, we make two passes over the reloads, in the order
5333 described above. In the first pass we try to inherit a reload
5334 from a previous insn. If there is a later reload that needs a
5335 class that is a proper subset of the class being processed, we must
5336 also allocate a spill register during the first pass.
5338 Then make a second pass over the reloads to allocate any reloads
5339 that haven't been given registers yet. */
5341 for (j = 0; j < n_reloads; j++)
5343 int r = reload_order[j];
5344 rtx search_equiv = NULL_RTX;
5346 /* Ignore reloads that got marked inoperative. */
5347 if (rld[r].out == 0 && rld[r].in == 0
5348 && ! rld[r].secondary_p)
5351 /* If find_reloads chose to use reload_in or reload_out as a reload
5352 register, we don't need to chose one. Otherwise, try even if it
5353 found one since we might save an insn if we find the value lying
5355 Try also when reload_in is a pseudo without a hard reg. */
5356 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5357 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5358 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5359 && GET_CODE (rld[r].in) != MEM
5360 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5363 #if 0 /* No longer needed for correct operation.
5364 It might give better code, or might not; worth an experiment? */
5365 /* If this is an optional reload, we can't inherit from earlier insns
5366 until we are sure that any non-optional reloads have been allocated.
5367 The following code takes advantage of the fact that optional reloads
5368 are at the end of reload_order. */
5369 if (rld[r].optional != 0)
5370 for (i = 0; i < j; i++)
5371 if ((rld[reload_order[i]].out != 0
5372 || rld[reload_order[i]].in != 0
5373 || rld[reload_order[i]].secondary_p)
5374 && ! rld[reload_order[i]].optional
5375 && rld[reload_order[i]].reg_rtx == 0)
5376 allocate_reload_reg (chain, reload_order[i], 0);
5379 /* First see if this pseudo is already available as reloaded
5380 for a previous insn. We cannot try to inherit for reloads
5381 that are smaller than the maximum number of registers needed
5382 for groups unless the register we would allocate cannot be used
5385 We could check here to see if this is a secondary reload for
5386 an object that is already in a register of the desired class.
5387 This would avoid the need for the secondary reload register.
5388 But this is complex because we can't easily determine what
5389 objects might want to be loaded via this reload. So let a
5390 register be allocated here. In `emit_reload_insns' we suppress
5391 one of the loads in the case described above. */
5397 enum machine_mode mode = VOIDmode;
5401 else if (GET_CODE (rld[r].in) == REG)
5403 regno = REGNO (rld[r].in);
5404 mode = GET_MODE (rld[r].in);
5406 else if (GET_CODE (rld[r].in_reg) == REG)
5408 regno = REGNO (rld[r].in_reg);
5409 mode = GET_MODE (rld[r].in_reg);
5411 else if (GET_CODE (rld[r].in_reg) == SUBREG
5412 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5414 byte = SUBREG_BYTE (rld[r].in_reg);
5415 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5416 if (regno < FIRST_PSEUDO_REGISTER)
5417 regno = subreg_regno (rld[r].in_reg);
5418 mode = GET_MODE (rld[r].in_reg);
5421 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5422 || GET_CODE (rld[r].in_reg) == PRE_DEC
5423 || GET_CODE (rld[r].in_reg) == POST_INC
5424 || GET_CODE (rld[r].in_reg) == POST_DEC)
5425 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5427 regno = REGNO (XEXP (rld[r].in_reg, 0));
5428 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5429 rld[r].out = rld[r].in;
5433 /* This won't work, since REGNO can be a pseudo reg number.
5434 Also, it takes much more hair to keep track of all the things
5435 that can invalidate an inherited reload of part of a pseudoreg. */
5436 else if (GET_CODE (rld[r].in) == SUBREG
5437 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5438 regno = subreg_regno (rld[r].in);
5441 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5443 enum reg_class class = rld[r].class, last_class;
5444 rtx last_reg = reg_last_reload_reg[regno];
5445 enum machine_mode need_mode;
5447 i = REGNO (last_reg);
5448 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5449 last_class = REGNO_REG_CLASS (i);
5455 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5456 GET_MODE_CLASS (mode));
5459 #ifdef CANNOT_CHANGE_MODE_CLASS
5460 (!REG_CANNOT_CHANGE_MODE_P (i, GET_MODE (last_reg),
5464 (GET_MODE_SIZE (GET_MODE (last_reg))
5465 >= GET_MODE_SIZE (need_mode))
5466 #ifdef CANNOT_CHANGE_MODE_CLASS
5469 && reg_reloaded_contents[i] == regno
5470 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5471 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5472 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5473 /* Even if we can't use this register as a reload
5474 register, we might use it for reload_override_in,
5475 if copying it to the desired class is cheap
5477 || ((REGISTER_MOVE_COST (mode, last_class, class)
5478 < MEMORY_MOVE_COST (mode, class, 1))
5479 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5480 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5484 #ifdef SECONDARY_MEMORY_NEEDED
5485 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5490 && (rld[r].nregs == max_group_size
5491 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5493 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5494 rld[r].when_needed, rld[r].in,
5497 /* If a group is needed, verify that all the subsequent
5498 registers still have their values intact. */
5499 int nr = hard_regno_nregs[i][rld[r].mode];
5502 for (k = 1; k < nr; k++)
5503 if (reg_reloaded_contents[i + k] != regno
5504 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5512 last_reg = (GET_MODE (last_reg) == mode
5513 ? last_reg : gen_rtx_REG (mode, i));
5516 for (k = 0; k < nr; k++)
5517 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5520 /* We found a register that contains the
5521 value we need. If this register is the
5522 same as an `earlyclobber' operand of the
5523 current insn, just mark it as a place to
5524 reload from since we can't use it as the
5525 reload register itself. */
5527 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5528 if (reg_overlap_mentioned_for_reload_p
5529 (reg_last_reload_reg[regno],
5530 reload_earlyclobbers[i1]))
5533 if (i1 != n_earlyclobbers
5534 || ! (free_for_value_p (i, rld[r].mode,
5536 rld[r].when_needed, rld[r].in,
5538 /* Don't use it if we'd clobber a pseudo reg. */
5539 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5541 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5542 /* Don't clobber the frame pointer. */
5543 || (i == HARD_FRAME_POINTER_REGNUM
5544 && frame_pointer_needed
5546 /* Don't really use the inherited spill reg
5547 if we need it wider than we've got it. */
5548 || (GET_MODE_SIZE (rld[r].mode)
5549 > GET_MODE_SIZE (mode))
5552 /* If find_reloads chose reload_out as reload
5553 register, stay with it - that leaves the
5554 inherited register for subsequent reloads. */
5555 || (rld[r].out && rld[r].reg_rtx
5556 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5558 if (! rld[r].optional)
5560 reload_override_in[r] = last_reg;
5561 reload_inheritance_insn[r]
5562 = reg_reloaded_insn[i];
5568 /* We can use this as a reload reg. */
5569 /* Mark the register as in use for this part of
5571 mark_reload_reg_in_use (i,
5575 rld[r].reg_rtx = last_reg;
5576 reload_inherited[r] = 1;
5577 reload_inheritance_insn[r]
5578 = reg_reloaded_insn[i];
5579 reload_spill_index[r] = i;
5580 for (k = 0; k < nr; k++)
5581 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5589 /* Here's another way to see if the value is already lying around. */
5592 && ! reload_inherited[r]
5594 && (CONSTANT_P (rld[r].in)
5595 || GET_CODE (rld[r].in) == PLUS
5596 || GET_CODE (rld[r].in) == REG
5597 || GET_CODE (rld[r].in) == MEM)
5598 && (rld[r].nregs == max_group_size
5599 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5600 search_equiv = rld[r].in;
5601 /* If this is an output reload from a simple move insn, look
5602 if an equivalence for the input is available. */
5603 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5605 rtx set = single_set (insn);
5608 && rtx_equal_p (rld[r].out, SET_DEST (set))
5609 && CONSTANT_P (SET_SRC (set)))
5610 search_equiv = SET_SRC (set);
5616 = find_equiv_reg (search_equiv, insn, rld[r].class,
5617 -1, NULL, 0, rld[r].mode);
5622 if (GET_CODE (equiv) == REG)
5623 regno = REGNO (equiv);
5624 else if (GET_CODE (equiv) == SUBREG)
5626 /* This must be a SUBREG of a hard register.
5627 Make a new REG since this might be used in an
5628 address and not all machines support SUBREGs
5630 regno = subreg_regno (equiv);
5631 equiv = gen_rtx_REG (rld[r].mode, regno);
5637 /* If we found a spill reg, reject it unless it is free
5638 and of the desired class. */
5642 int bad_for_class = 0;
5643 int max_regno = regno + rld[r].nregs;
5645 for (i = regno; i < max_regno; i++)
5647 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5649 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5654 && ! free_for_value_p (regno, rld[r].mode,
5655 rld[r].opnum, rld[r].when_needed,
5656 rld[r].in, rld[r].out, r, 1))
5661 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5664 /* We found a register that contains the value we need.
5665 If this register is the same as an `earlyclobber' operand
5666 of the current insn, just mark it as a place to reload from
5667 since we can't use it as the reload register itself. */
5670 for (i = 0; i < n_earlyclobbers; i++)
5671 if (reg_overlap_mentioned_for_reload_p (equiv,
5672 reload_earlyclobbers[i]))
5674 if (! rld[r].optional)
5675 reload_override_in[r] = equiv;
5680 /* If the equiv register we have found is explicitly clobbered
5681 in the current insn, it depends on the reload type if we
5682 can use it, use it for reload_override_in, or not at all.
5683 In particular, we then can't use EQUIV for a
5684 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5688 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5689 switch (rld[r].when_needed)
5691 case RELOAD_FOR_OTHER_ADDRESS:
5692 case RELOAD_FOR_INPADDR_ADDRESS:
5693 case RELOAD_FOR_INPUT_ADDRESS:
5694 case RELOAD_FOR_OPADDR_ADDR:
5697 case RELOAD_FOR_INPUT:
5698 case RELOAD_FOR_OPERAND_ADDRESS:
5699 if (! rld[r].optional)
5700 reload_override_in[r] = equiv;
5706 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5707 switch (rld[r].when_needed)
5709 case RELOAD_FOR_OTHER_ADDRESS:
5710 case RELOAD_FOR_INPADDR_ADDRESS:
5711 case RELOAD_FOR_INPUT_ADDRESS:
5712 case RELOAD_FOR_OPADDR_ADDR:
5713 case RELOAD_FOR_OPERAND_ADDRESS:
5714 case RELOAD_FOR_INPUT:
5717 if (! rld[r].optional)
5718 reload_override_in[r] = equiv;
5726 /* If we found an equivalent reg, say no code need be generated
5727 to load it, and use it as our reload reg. */
5729 && (regno != HARD_FRAME_POINTER_REGNUM
5730 || !frame_pointer_needed))
5732 int nr = hard_regno_nregs[regno][rld[r].mode];
5734 rld[r].reg_rtx = equiv;
5735 reload_inherited[r] = 1;
5737 /* If reg_reloaded_valid is not set for this register,
5738 there might be a stale spill_reg_store lying around.
5739 We must clear it, since otherwise emit_reload_insns
5740 might delete the store. */
5741 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5742 spill_reg_store[regno] = NULL_RTX;
5743 /* If any of the hard registers in EQUIV are spill
5744 registers, mark them as in use for this insn. */
5745 for (k = 0; k < nr; k++)
5747 i = spill_reg_order[regno + k];
5750 mark_reload_reg_in_use (regno, rld[r].opnum,
5753 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5760 /* If we found a register to use already, or if this is an optional
5761 reload, we are done. */
5762 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5766 /* No longer needed for correct operation. Might or might
5767 not give better code on the average. Want to experiment? */
5769 /* See if there is a later reload that has a class different from our
5770 class that intersects our class or that requires less register
5771 than our reload. If so, we must allocate a register to this
5772 reload now, since that reload might inherit a previous reload
5773 and take the only available register in our class. Don't do this
5774 for optional reloads since they will force all previous reloads
5775 to be allocated. Also don't do this for reloads that have been
5778 for (i = j + 1; i < n_reloads; i++)
5780 int s = reload_order[i];
5782 if ((rld[s].in == 0 && rld[s].out == 0
5783 && ! rld[s].secondary_p)
5787 if ((rld[s].class != rld[r].class
5788 && reg_classes_intersect_p (rld[r].class,
5790 || rld[s].nregs < rld[r].nregs)
5797 allocate_reload_reg (chain, r, j == n_reloads - 1);
5801 /* Now allocate reload registers for anything non-optional that
5802 didn't get one yet. */
5803 for (j = 0; j < n_reloads; j++)
5805 int r = reload_order[j];
5807 /* Ignore reloads that got marked inoperative. */
5808 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5811 /* Skip reloads that already have a register allocated or are
5813 if (rld[r].reg_rtx != 0 || rld[r].optional)
5816 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5820 /* If that loop got all the way, we have won. */
5827 /* Loop around and try without any inheritance. */
5832 /* First undo everything done by the failed attempt
5833 to allocate with inheritance. */
5834 choose_reload_regs_init (chain, save_reload_reg_rtx);
5836 /* Some sanity tests to verify that the reloads found in the first
5837 pass are identical to the ones we have now. */
5838 if (chain->n_reloads != n_reloads)
5841 for (i = 0; i < n_reloads; i++)
5843 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5845 if (chain->rld[i].when_needed != rld[i].when_needed)
5847 for (j = 0; j < n_spills; j++)
5848 if (spill_regs[j] == chain->rld[i].regno)
5849 if (! set_reload_reg (j, i))
5850 failed_reload (chain->insn, i);
5854 /* If we thought we could inherit a reload, because it seemed that
5855 nothing else wanted the same reload register earlier in the insn,
5856 verify that assumption, now that all reloads have been assigned.
5857 Likewise for reloads where reload_override_in has been set. */
5859 /* If doing expensive optimizations, do one preliminary pass that doesn't
5860 cancel any inheritance, but removes reloads that have been needed only
5861 for reloads that we know can be inherited. */
5862 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5864 for (j = 0; j < n_reloads; j++)
5866 int r = reload_order[j];
5868 if (reload_inherited[r] && rld[r].reg_rtx)
5869 check_reg = rld[r].reg_rtx;
5870 else if (reload_override_in[r]
5871 && (GET_CODE (reload_override_in[r]) == REG
5872 || GET_CODE (reload_override_in[r]) == SUBREG))
5873 check_reg = reload_override_in[r];
5876 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5877 rld[r].opnum, rld[r].when_needed, rld[r].in,
5878 (reload_inherited[r]
5879 ? rld[r].out : const0_rtx),
5884 reload_inherited[r] = 0;
5885 reload_override_in[r] = 0;
5887 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5888 reload_override_in, then we do not need its related
5889 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5890 likewise for other reload types.
5891 We handle this by removing a reload when its only replacement
5892 is mentioned in reload_in of the reload we are going to inherit.
5893 A special case are auto_inc expressions; even if the input is
5894 inherited, we still need the address for the output. We can
5895 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5896 If we succeeded removing some reload and we are doing a preliminary
5897 pass just to remove such reloads, make another pass, since the
5898 removal of one reload might allow us to inherit another one. */
5900 && rld[r].out != rld[r].in
5901 && remove_address_replacements (rld[r].in) && pass)
5906 /* Now that reload_override_in is known valid,
5907 actually override reload_in. */
5908 for (j = 0; j < n_reloads; j++)
5909 if (reload_override_in[j])
5910 rld[j].in = reload_override_in[j];
5912 /* If this reload won't be done because it has been canceled or is
5913 optional and not inherited, clear reload_reg_rtx so other
5914 routines (such as subst_reloads) don't get confused. */
5915 for (j = 0; j < n_reloads; j++)
5916 if (rld[j].reg_rtx != 0
5917 && ((rld[j].optional && ! reload_inherited[j])
5918 || (rld[j].in == 0 && rld[j].out == 0
5919 && ! rld[j].secondary_p)))
5921 int regno = true_regnum (rld[j].reg_rtx);
5923 if (spill_reg_order[regno] >= 0)
5924 clear_reload_reg_in_use (regno, rld[j].opnum,
5925 rld[j].when_needed, rld[j].mode);
5927 reload_spill_index[j] = -1;
5930 /* Record which pseudos and which spill regs have output reloads. */
5931 for (j = 0; j < n_reloads; j++)
5933 int r = reload_order[j];
5935 i = reload_spill_index[r];
5937 /* I is nonneg if this reload uses a register.
5938 If rld[r].reg_rtx is 0, this is an optional reload
5939 that we opted to ignore. */
5940 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5941 && rld[r].reg_rtx != 0)
5943 int nregno = REGNO (rld[r].out_reg);
5946 if (nregno < FIRST_PSEUDO_REGISTER)
5947 nr = hard_regno_nregs[nregno][rld[r].mode];
5950 reg_has_output_reload[nregno + nr] = 1;
5954 nr = hard_regno_nregs[i][rld[r].mode];
5956 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5959 if (rld[r].when_needed != RELOAD_OTHER
5960 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5961 && rld[r].when_needed != RELOAD_FOR_INSN)
5967 /* Deallocate the reload register for reload R. This is called from
5968 remove_address_replacements. */
5971 deallocate_reload_reg (int r)
5975 if (! rld[r].reg_rtx)
5977 regno = true_regnum (rld[r].reg_rtx);
5979 if (spill_reg_order[regno] >= 0)
5980 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5982 reload_spill_index[r] = -1;
5985 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
5986 reloads of the same item for fear that we might not have enough reload
5987 registers. However, normally they will get the same reload register
5988 and hence actually need not be loaded twice.
5990 Here we check for the most common case of this phenomenon: when we have
5991 a number of reloads for the same object, each of which were allocated
5992 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5993 reload, and is not modified in the insn itself. If we find such,
5994 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5995 This will not increase the number of spill registers needed and will
5996 prevent redundant code. */
5999 merge_assigned_reloads (rtx insn)
6003 /* Scan all the reloads looking for ones that only load values and
6004 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6005 assigned and not modified by INSN. */
6007 for (i = 0; i < n_reloads; i++)
6009 int conflicting_input = 0;
6010 int max_input_address_opnum = -1;
6011 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6013 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6014 || rld[i].out != 0 || rld[i].reg_rtx == 0
6015 || reg_set_p (rld[i].reg_rtx, insn))
6018 /* Look at all other reloads. Ensure that the only use of this
6019 reload_reg_rtx is in a reload that just loads the same value
6020 as we do. Note that any secondary reloads must be of the identical
6021 class since the values, modes, and result registers are the
6022 same, so we need not do anything with any secondary reloads. */
6024 for (j = 0; j < n_reloads; j++)
6026 if (i == j || rld[j].reg_rtx == 0
6027 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6031 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6032 && rld[j].opnum > max_input_address_opnum)
6033 max_input_address_opnum = rld[j].opnum;
6035 /* If the reload regs aren't exactly the same (e.g, different modes)
6036 or if the values are different, we can't merge this reload.
6037 But if it is an input reload, we might still merge
6038 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6040 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6041 || rld[j].out != 0 || rld[j].in == 0
6042 || ! rtx_equal_p (rld[i].in, rld[j].in))
6044 if (rld[j].when_needed != RELOAD_FOR_INPUT
6045 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6046 || rld[i].opnum > rld[j].opnum)
6047 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6049 conflicting_input = 1;
6050 if (min_conflicting_input_opnum > rld[j].opnum)
6051 min_conflicting_input_opnum = rld[j].opnum;
6055 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6056 we, in fact, found any matching reloads. */
6059 && max_input_address_opnum <= min_conflicting_input_opnum)
6061 for (j = 0; j < n_reloads; j++)
6062 if (i != j && rld[j].reg_rtx != 0
6063 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6064 && (! conflicting_input
6065 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6066 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6068 rld[i].when_needed = RELOAD_OTHER;
6070 reload_spill_index[j] = -1;
6071 transfer_replacements (i, j);
6074 /* If this is now RELOAD_OTHER, look for any reloads that load
6075 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6076 if they were for inputs, RELOAD_OTHER for outputs. Note that
6077 this test is equivalent to looking for reloads for this operand
6079 /* We must take special care when there are two or more reloads to
6080 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6081 same value or a part of it; we must not change its type if there
6082 is a conflicting input. */
6084 if (rld[i].when_needed == RELOAD_OTHER)
6085 for (j = 0; j < n_reloads; j++)
6087 && rld[j].when_needed != RELOAD_OTHER
6088 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6089 && (! conflicting_input
6090 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6091 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6092 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6098 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6099 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6100 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6102 /* Check to see if we accidentally converted two reloads
6103 that use the same reload register with different inputs
6104 to the same type. If so, the resulting code won't work,
6107 for (k = 0; k < j; k++)
6108 if (rld[k].in != 0 && rld[k].reg_rtx != 0
6109 && rld[k].when_needed == rld[j].when_needed
6110 && rtx_equal_p (rld[k].reg_rtx, rld[j].reg_rtx)
6111 && ! rtx_equal_p (rld[k].in, rld[j].in))
6118 /* These arrays are filled by emit_reload_insns and its subroutines. */
6119 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6120 static rtx other_input_address_reload_insns = 0;
6121 static rtx other_input_reload_insns = 0;
6122 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6123 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6124 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6125 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6126 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6127 static rtx operand_reload_insns = 0;
6128 static rtx other_operand_reload_insns = 0;
6129 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6131 /* Values to be put in spill_reg_store are put here first. */
6132 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6133 static HARD_REG_SET reg_reloaded_died;
6135 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6136 has the number J. OLD contains the value to be used as input. */
6139 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6142 rtx insn = chain->insn;
6143 rtx reloadreg = rl->reg_rtx;
6144 rtx oldequiv_reg = 0;
6147 enum machine_mode mode;
6150 /* Determine the mode to reload in.
6151 This is very tricky because we have three to choose from.
6152 There is the mode the insn operand wants (rl->inmode).
6153 There is the mode of the reload register RELOADREG.
6154 There is the intrinsic mode of the operand, which we could find
6155 by stripping some SUBREGs.
6156 It turns out that RELOADREG's mode is irrelevant:
6157 we can change that arbitrarily.
6159 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6160 then the reload reg may not support QImode moves, so use SImode.
6161 If foo is in memory due to spilling a pseudo reg, this is safe,
6162 because the QImode value is in the least significant part of a
6163 slot big enough for a SImode. If foo is some other sort of
6164 memory reference, then it is impossible to reload this case,
6165 so previous passes had better make sure this never happens.
6167 Then consider a one-word union which has SImode and one of its
6168 members is a float, being fetched as (SUBREG:SF union:SI).
6169 We must fetch that as SFmode because we could be loading into
6170 a float-only register. In this case OLD's mode is correct.
6172 Consider an immediate integer: it has VOIDmode. Here we need
6173 to get a mode from something else.
6175 In some cases, there is a fourth mode, the operand's
6176 containing mode. If the insn specifies a containing mode for
6177 this operand, it overrides all others.
6179 I am not sure whether the algorithm here is always right,
6180 but it does the right things in those cases. */
6182 mode = GET_MODE (old);
6183 if (mode == VOIDmode)
6186 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6187 /* If we need a secondary register for this operation, see if
6188 the value is already in a register in that class. Don't
6189 do this if the secondary register will be used as a scratch
6192 if (rl->secondary_in_reload >= 0
6193 && rl->secondary_in_icode == CODE_FOR_nothing
6196 = find_equiv_reg (old, insn,
6197 rld[rl->secondary_in_reload].class,
6201 /* If reloading from memory, see if there is a register
6202 that already holds the same value. If so, reload from there.
6203 We can pass 0 as the reload_reg_p argument because
6204 any other reload has either already been emitted,
6205 in which case find_equiv_reg will see the reload-insn,
6206 or has yet to be emitted, in which case it doesn't matter
6207 because we will use this equiv reg right away. */
6209 if (oldequiv == 0 && optimize
6210 && (GET_CODE (old) == MEM
6211 || (GET_CODE (old) == REG
6212 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6213 && reg_renumber[REGNO (old)] < 0)))
6214 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6218 unsigned int regno = true_regnum (oldequiv);
6220 /* Don't use OLDEQUIV if any other reload changes it at an
6221 earlier stage of this insn or at this stage. */
6222 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6223 rl->in, const0_rtx, j, 0))
6226 /* If it is no cheaper to copy from OLDEQUIV into the
6227 reload register than it would be to move from memory,
6228 don't use it. Likewise, if we need a secondary register
6232 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6233 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6235 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6236 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6237 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6241 #ifdef SECONDARY_MEMORY_NEEDED
6242 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6250 /* delete_output_reload is only invoked properly if old contains
6251 the original pseudo register. Since this is replaced with a
6252 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6253 find the pseudo in RELOAD_IN_REG. */
6255 && reload_override_in[j]
6256 && GET_CODE (rl->in_reg) == REG)
6263 else if (GET_CODE (oldequiv) == REG)
6264 oldequiv_reg = oldequiv;
6265 else if (GET_CODE (oldequiv) == SUBREG)
6266 oldequiv_reg = SUBREG_REG (oldequiv);
6268 /* If we are reloading from a register that was recently stored in
6269 with an output-reload, see if we can prove there was
6270 actually no need to store the old value in it. */
6272 if (optimize && GET_CODE (oldequiv) == REG
6273 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6274 && spill_reg_store[REGNO (oldequiv)]
6275 && GET_CODE (old) == REG
6276 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6277 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6279 delete_output_reload (insn, j, REGNO (oldequiv));
6281 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6282 then load RELOADREG from OLDEQUIV. Note that we cannot use
6283 gen_lowpart_common since it can do the wrong thing when
6284 RELOADREG has a multi-word mode. Note that RELOADREG
6285 must always be a REG here. */
6287 if (GET_MODE (reloadreg) != mode)
6288 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6289 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6290 oldequiv = SUBREG_REG (oldequiv);
6291 if (GET_MODE (oldequiv) != VOIDmode
6292 && mode != GET_MODE (oldequiv))
6293 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6295 /* Switch to the right place to emit the reload insns. */
6296 switch (rl->when_needed)
6299 where = &other_input_reload_insns;
6301 case RELOAD_FOR_INPUT:
6302 where = &input_reload_insns[rl->opnum];
6304 case RELOAD_FOR_INPUT_ADDRESS:
6305 where = &input_address_reload_insns[rl->opnum];
6307 case RELOAD_FOR_INPADDR_ADDRESS:
6308 where = &inpaddr_address_reload_insns[rl->opnum];
6310 case RELOAD_FOR_OUTPUT_ADDRESS:
6311 where = &output_address_reload_insns[rl->opnum];
6313 case RELOAD_FOR_OUTADDR_ADDRESS:
6314 where = &outaddr_address_reload_insns[rl->opnum];
6316 case RELOAD_FOR_OPERAND_ADDRESS:
6317 where = &operand_reload_insns;
6319 case RELOAD_FOR_OPADDR_ADDR:
6320 where = &other_operand_reload_insns;
6322 case RELOAD_FOR_OTHER_ADDRESS:
6323 where = &other_input_address_reload_insns;
6329 push_to_sequence (*where);
6331 /* Auto-increment addresses must be reloaded in a special way. */
6332 if (rl->out && ! rl->out_reg)
6334 /* We are not going to bother supporting the case where a
6335 incremented register can't be copied directly from
6336 OLDEQUIV since this seems highly unlikely. */
6337 if (rl->secondary_in_reload >= 0)
6340 if (reload_inherited[j])
6341 oldequiv = reloadreg;
6343 old = XEXP (rl->in_reg, 0);
6345 if (optimize && GET_CODE (oldequiv) == REG
6346 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6347 && spill_reg_store[REGNO (oldequiv)]
6348 && GET_CODE (old) == REG
6349 && (dead_or_set_p (insn,
6350 spill_reg_stored_to[REGNO (oldequiv)])
6351 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6353 delete_output_reload (insn, j, REGNO (oldequiv));
6355 /* Prevent normal processing of this reload. */
6357 /* Output a special code sequence for this case. */
6358 new_spill_reg_store[REGNO (reloadreg)]
6359 = inc_for_reload (reloadreg, oldequiv, rl->out,
6363 /* If we are reloading a pseudo-register that was set by the previous
6364 insn, see if we can get rid of that pseudo-register entirely
6365 by redirecting the previous insn into our reload register. */
6367 else if (optimize && GET_CODE (old) == REG
6368 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6369 && dead_or_set_p (insn, old)
6370 /* This is unsafe if some other reload
6371 uses the same reg first. */
6372 && ! conflicts_with_override (reloadreg)
6373 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6374 rl->when_needed, old, rl->out, j, 0))
6376 rtx temp = PREV_INSN (insn);
6377 while (temp && GET_CODE (temp) == NOTE)
6378 temp = PREV_INSN (temp);
6380 && GET_CODE (temp) == INSN
6381 && GET_CODE (PATTERN (temp)) == SET
6382 && SET_DEST (PATTERN (temp)) == old
6383 /* Make sure we can access insn_operand_constraint. */
6384 && asm_noperands (PATTERN (temp)) < 0
6385 /* This is unsafe if operand occurs more than once in current
6386 insn. Perhaps some occurrences aren't reloaded. */
6387 && count_occurrences (PATTERN (insn), old, 0) == 1)
6389 rtx old = SET_DEST (PATTERN (temp));
6390 /* Store into the reload register instead of the pseudo. */
6391 SET_DEST (PATTERN (temp)) = reloadreg;
6393 /* Verify that resulting insn is valid. */
6394 extract_insn (temp);
6395 if (constrain_operands (1))
6397 /* If the previous insn is an output reload, the source is
6398 a reload register, and its spill_reg_store entry will
6399 contain the previous destination. This is now
6401 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6402 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6404 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6405 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6408 /* If these are the only uses of the pseudo reg,
6409 pretend for GDB it lives in the reload reg we used. */
6410 if (REG_N_DEATHS (REGNO (old)) == 1
6411 && REG_N_SETS (REGNO (old)) == 1)
6413 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6414 alter_reg (REGNO (old), -1);
6420 SET_DEST (PATTERN (temp)) = old;
6425 /* We can't do that, so output an insn to load RELOADREG. */
6427 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6428 /* If we have a secondary reload, pick up the secondary register
6429 and icode, if any. If OLDEQUIV and OLD are different or
6430 if this is an in-out reload, recompute whether or not we
6431 still need a secondary register and what the icode should
6432 be. If we still need a secondary register and the class or
6433 icode is different, go back to reloading from OLD if using
6434 OLDEQUIV means that we got the wrong type of register. We
6435 cannot have different class or icode due to an in-out reload
6436 because we don't make such reloads when both the input and
6437 output need secondary reload registers. */
6439 if (! special && rl->secondary_in_reload >= 0)
6441 rtx second_reload_reg = 0;
6442 int secondary_reload = rl->secondary_in_reload;
6443 rtx real_oldequiv = oldequiv;
6446 enum insn_code icode;
6448 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6449 and similarly for OLD.
6450 See comments in get_secondary_reload in reload.c. */
6451 /* If it is a pseudo that cannot be replaced with its
6452 equivalent MEM, we must fall back to reload_in, which
6453 will have all the necessary substitutions registered.
6454 Likewise for a pseudo that can't be replaced with its
6455 equivalent constant.
6457 Take extra care for subregs of such pseudos. Note that
6458 we cannot use reg_equiv_mem in this case because it is
6459 not in the right mode. */
6462 if (GET_CODE (tmp) == SUBREG)
6463 tmp = SUBREG_REG (tmp);
6464 if (GET_CODE (tmp) == REG
6465 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6466 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6467 || reg_equiv_constant[REGNO (tmp)] != 0))
6469 if (! reg_equiv_mem[REGNO (tmp)]
6470 || num_not_at_initial_offset
6471 || GET_CODE (oldequiv) == SUBREG)
6472 real_oldequiv = rl->in;
6474 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6478 if (GET_CODE (tmp) == SUBREG)
6479 tmp = SUBREG_REG (tmp);
6480 if (GET_CODE (tmp) == REG
6481 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6482 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6483 || reg_equiv_constant[REGNO (tmp)] != 0))
6485 if (! reg_equiv_mem[REGNO (tmp)]
6486 || num_not_at_initial_offset
6487 || GET_CODE (old) == SUBREG)
6490 real_old = reg_equiv_mem[REGNO (tmp)];
6493 second_reload_reg = rld[secondary_reload].reg_rtx;
6494 icode = rl->secondary_in_icode;
6496 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6497 || (rl->in != 0 && rl->out != 0))
6499 enum reg_class new_class
6500 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6501 mode, real_oldequiv);
6503 if (new_class == NO_REGS)
6504 second_reload_reg = 0;
6507 enum insn_code new_icode;
6508 enum machine_mode new_mode;
6510 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6511 REGNO (second_reload_reg)))
6512 oldequiv = old, real_oldequiv = real_old;
6515 new_icode = reload_in_optab[(int) mode];
6516 if (new_icode != CODE_FOR_nothing
6517 && ((insn_data[(int) new_icode].operand[0].predicate
6518 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6520 || (insn_data[(int) new_icode].operand[1].predicate
6521 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6522 (real_oldequiv, mode)))))
6523 new_icode = CODE_FOR_nothing;
6525 if (new_icode == CODE_FOR_nothing)
6528 new_mode = insn_data[(int) new_icode].operand[2].mode;
6530 if (GET_MODE (second_reload_reg) != new_mode)
6532 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6534 oldequiv = old, real_oldequiv = real_old;
6537 = reload_adjust_reg_for_mode (second_reload_reg,
6544 /* If we still need a secondary reload register, check
6545 to see if it is being used as a scratch or intermediate
6546 register and generate code appropriately. If we need
6547 a scratch register, use REAL_OLDEQUIV since the form of
6548 the insn may depend on the actual address if it is
6551 if (second_reload_reg)
6553 if (icode != CODE_FOR_nothing)
6555 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6556 second_reload_reg));
6561 /* See if we need a scratch register to load the
6562 intermediate register (a tertiary reload). */
6563 enum insn_code tertiary_icode
6564 = rld[secondary_reload].secondary_in_icode;
6566 if (tertiary_icode != CODE_FOR_nothing)
6568 rtx third_reload_reg
6569 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6571 emit_insn ((GEN_FCN (tertiary_icode)
6572 (second_reload_reg, real_oldequiv,
6573 third_reload_reg)));
6576 gen_reload (second_reload_reg, real_oldequiv,
6580 oldequiv = second_reload_reg;
6586 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6588 rtx real_oldequiv = oldequiv;
6590 if ((GET_CODE (oldequiv) == REG
6591 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6592 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6593 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6594 || (GET_CODE (oldequiv) == SUBREG
6595 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6596 && (REGNO (SUBREG_REG (oldequiv))
6597 >= FIRST_PSEUDO_REGISTER)
6598 && ((reg_equiv_memory_loc
6599 [REGNO (SUBREG_REG (oldequiv))] != 0)
6600 || (reg_equiv_constant
6601 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6602 || (CONSTANT_P (oldequiv)
6603 && (PREFERRED_RELOAD_CLASS (oldequiv,
6604 REGNO_REG_CLASS (REGNO (reloadreg)))
6606 real_oldequiv = rl->in;
6607 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6611 if (flag_non_call_exceptions)
6612 copy_eh_notes (insn, get_insns ());
6614 /* End this sequence. */
6615 *where = get_insns ();
6618 /* Update reload_override_in so that delete_address_reloads_1
6619 can see the actual register usage. */
6621 reload_override_in[j] = oldequiv;
6624 /* Generate insns to for the output reload RL, which is for the insn described
6625 by CHAIN and has the number J. */
6627 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6630 rtx reloadreg = rl->reg_rtx;
6631 rtx insn = chain->insn;
6634 enum machine_mode mode = GET_MODE (old);
6637 if (rl->when_needed == RELOAD_OTHER)
6640 push_to_sequence (output_reload_insns[rl->opnum]);
6642 /* Determine the mode to reload in.
6643 See comments above (for input reloading). */
6645 if (mode == VOIDmode)
6647 /* VOIDmode should never happen for an output. */
6648 if (asm_noperands (PATTERN (insn)) < 0)
6649 /* It's the compiler's fault. */
6650 fatal_insn ("VOIDmode on an output", insn);
6651 error_for_asm (insn, "output operand is constant in `asm'");
6652 /* Prevent crash--use something we know is valid. */
6654 old = gen_rtx_REG (mode, REGNO (reloadreg));
6657 if (GET_MODE (reloadreg) != mode)
6658 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6660 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6662 /* If we need two reload regs, set RELOADREG to the intermediate
6663 one, since it will be stored into OLD. We might need a secondary
6664 register only for an input reload, so check again here. */
6666 if (rl->secondary_out_reload >= 0)
6670 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6671 && reg_equiv_mem[REGNO (old)] != 0)
6672 real_old = reg_equiv_mem[REGNO (old)];
6674 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6678 rtx second_reloadreg = reloadreg;
6679 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6681 /* See if RELOADREG is to be used as a scratch register
6682 or as an intermediate register. */
6683 if (rl->secondary_out_icode != CODE_FOR_nothing)
6685 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6686 (real_old, second_reloadreg, reloadreg)));
6691 /* See if we need both a scratch and intermediate reload
6694 int secondary_reload = rl->secondary_out_reload;
6695 enum insn_code tertiary_icode
6696 = rld[secondary_reload].secondary_out_icode;
6698 if (GET_MODE (reloadreg) != mode)
6699 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6701 if (tertiary_icode != CODE_FOR_nothing)
6704 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6707 /* Copy primary reload reg to secondary reload reg.
6708 (Note that these have been swapped above, then
6709 secondary reload reg to OLD using our insn.) */
6711 /* If REAL_OLD is a paradoxical SUBREG, remove it
6712 and try to put the opposite SUBREG on
6714 if (GET_CODE (real_old) == SUBREG
6715 && (GET_MODE_SIZE (GET_MODE (real_old))
6716 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6717 && 0 != (tem = gen_lowpart_common
6718 (GET_MODE (SUBREG_REG (real_old)),
6720 real_old = SUBREG_REG (real_old), reloadreg = tem;
6722 gen_reload (reloadreg, second_reloadreg,
6723 rl->opnum, rl->when_needed);
6724 emit_insn ((GEN_FCN (tertiary_icode)
6725 (real_old, reloadreg, third_reloadreg)));
6730 /* Copy between the reload regs here and then to
6733 gen_reload (reloadreg, second_reloadreg,
6734 rl->opnum, rl->when_needed);
6740 /* Output the last reload insn. */
6745 /* Don't output the last reload if OLD is not the dest of
6746 INSN and is in the src and is clobbered by INSN. */
6747 if (! flag_expensive_optimizations
6748 || GET_CODE (old) != REG
6749 || !(set = single_set (insn))
6750 || rtx_equal_p (old, SET_DEST (set))
6751 || !reg_mentioned_p (old, SET_SRC (set))
6752 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6753 gen_reload (old, reloadreg, rl->opnum,
6757 /* Look at all insns we emitted, just to be safe. */
6758 for (p = get_insns (); p; p = NEXT_INSN (p))
6761 rtx pat = PATTERN (p);
6763 /* If this output reload doesn't come from a spill reg,
6764 clear any memory of reloaded copies of the pseudo reg.
6765 If this output reload comes from a spill reg,
6766 reg_has_output_reload will make this do nothing. */
6767 note_stores (pat, forget_old_reloads_1, NULL);
6769 if (reg_mentioned_p (rl->reg_rtx, pat))
6771 rtx set = single_set (insn);
6772 if (reload_spill_index[j] < 0
6774 && SET_SRC (set) == rl->reg_rtx)
6776 int src = REGNO (SET_SRC (set));
6778 reload_spill_index[j] = src;
6779 SET_HARD_REG_BIT (reg_is_output_reload, src);
6780 if (find_regno_note (insn, REG_DEAD, src))
6781 SET_HARD_REG_BIT (reg_reloaded_died, src);
6783 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6785 int s = rl->secondary_out_reload;
6786 set = single_set (p);
6787 /* If this reload copies only to the secondary reload
6788 register, the secondary reload does the actual
6790 if (s >= 0 && set == NULL_RTX)
6791 /* We can't tell what function the secondary reload
6792 has and where the actual store to the pseudo is
6793 made; leave new_spill_reg_store alone. */
6796 && SET_SRC (set) == rl->reg_rtx
6797 && SET_DEST (set) == rld[s].reg_rtx)
6799 /* Usually the next instruction will be the
6800 secondary reload insn; if we can confirm
6801 that it is, setting new_spill_reg_store to
6802 that insn will allow an extra optimization. */
6803 rtx s_reg = rld[s].reg_rtx;
6804 rtx next = NEXT_INSN (p);
6805 rld[s].out = rl->out;
6806 rld[s].out_reg = rl->out_reg;
6807 set = single_set (next);
6808 if (set && SET_SRC (set) == s_reg
6809 && ! new_spill_reg_store[REGNO (s_reg)])
6811 SET_HARD_REG_BIT (reg_is_output_reload,
6813 new_spill_reg_store[REGNO (s_reg)] = next;
6817 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6822 if (rl->when_needed == RELOAD_OTHER)
6824 emit_insn (other_output_reload_insns[rl->opnum]);
6825 other_output_reload_insns[rl->opnum] = get_insns ();
6828 output_reload_insns[rl->opnum] = get_insns ();
6830 if (flag_non_call_exceptions)
6831 copy_eh_notes (insn, get_insns ());
6836 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6837 and has the number J. */
6839 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
6841 rtx insn = chain->insn;
6842 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6843 ? rl->in_reg : rl->in);
6846 /* AUTO_INC reloads need to be handled even if inherited. We got an
6847 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6848 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6849 && ! rtx_equal_p (rl->reg_rtx, old)
6850 && rl->reg_rtx != 0)
6851 emit_input_reload_insns (chain, rld + j, old, j);
6853 /* When inheriting a wider reload, we have a MEM in rl->in,
6854 e.g. inheriting a SImode output reload for
6855 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6856 if (optimize && reload_inherited[j] && rl->in
6857 && GET_CODE (rl->in) == MEM
6858 && GET_CODE (rl->in_reg) == MEM
6859 && reload_spill_index[j] >= 0
6860 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6861 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6863 /* If we are reloading a register that was recently stored in with an
6864 output-reload, see if we can prove there was
6865 actually no need to store the old value in it. */
6868 && (reload_inherited[j] || reload_override_in[j])
6870 && GET_CODE (rl->reg_rtx) == REG
6871 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6873 /* There doesn't seem to be any reason to restrict this to pseudos
6874 and doing so loses in the case where we are copying from a
6875 register of the wrong class. */
6876 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6877 >= FIRST_PSEUDO_REGISTER)
6879 /* The insn might have already some references to stackslots
6880 replaced by MEMs, while reload_out_reg still names the
6882 && (dead_or_set_p (insn,
6883 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6884 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6886 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6889 /* Do output reloading for reload RL, which is for the insn described by
6890 CHAIN and has the number J.
6891 ??? At some point we need to support handling output reloads of
6892 JUMP_INSNs or insns that set cc0. */
6894 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
6897 rtx insn = chain->insn;
6898 /* If this is an output reload that stores something that is
6899 not loaded in this same reload, see if we can eliminate a previous
6901 rtx pseudo = rl->out_reg;
6905 && GET_CODE (pseudo) == REG
6906 && ! rtx_equal_p (rl->in_reg, pseudo)
6907 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6908 && reg_last_reload_reg[REGNO (pseudo)])
6910 int pseudo_no = REGNO (pseudo);
6911 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6913 /* We don't need to test full validity of last_regno for
6914 inherit here; we only want to know if the store actually
6915 matches the pseudo. */
6916 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6917 && reg_reloaded_contents[last_regno] == pseudo_no
6918 && spill_reg_store[last_regno]
6919 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6920 delete_output_reload (insn, j, last_regno);
6925 || rl->reg_rtx == old
6926 || rl->reg_rtx == 0)
6929 /* An output operand that dies right away does need a reload,
6930 but need not be copied from it. Show the new location in the
6932 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6933 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6935 XEXP (note, 0) = rl->reg_rtx;
6938 /* Likewise for a SUBREG of an operand that dies. */
6939 else if (GET_CODE (old) == SUBREG
6940 && GET_CODE (SUBREG_REG (old)) == REG
6941 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6944 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6948 else if (GET_CODE (old) == SCRATCH)
6949 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6950 but we don't want to make an output reload. */
6953 /* If is a JUMP_INSN, we can't support output reloads yet. */
6954 if (GET_CODE (insn) == JUMP_INSN)
6957 emit_output_reload_insns (chain, rld + j, j);
6960 /* Reload number R reloads from or to a group of hard registers starting at
6961 register REGNO. Return true if it can be treated for inheritance purposes
6962 like a group of reloads, each one reloading a single hard register.
6963 The caller has already checked that the spill register and REGNO use
6964 the same number of registers to store the reload value. */
6967 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
6969 #ifdef CANNOT_CHANGE_MODE_CLASS
6970 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
6971 GET_MODE (rld[r].reg_rtx),
6972 reg_raw_mode[reload_spill_index[r]])
6973 && !REG_CANNOT_CHANGE_MODE_P (regno,
6974 GET_MODE (rld[r].reg_rtx),
6975 reg_raw_mode[regno]));
6981 /* Output insns to reload values in and out of the chosen reload regs. */
6984 emit_reload_insns (struct insn_chain *chain)
6986 rtx insn = chain->insn;
6990 CLEAR_HARD_REG_SET (reg_reloaded_died);
6992 for (j = 0; j < reload_n_operands; j++)
6993 input_reload_insns[j] = input_address_reload_insns[j]
6994 = inpaddr_address_reload_insns[j]
6995 = output_reload_insns[j] = output_address_reload_insns[j]
6996 = outaddr_address_reload_insns[j]
6997 = other_output_reload_insns[j] = 0;
6998 other_input_address_reload_insns = 0;
6999 other_input_reload_insns = 0;
7000 operand_reload_insns = 0;
7001 other_operand_reload_insns = 0;
7003 /* Dump reloads into the dump file. */
7006 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7007 debug_reload_to_stream (dump_file);
7010 /* Now output the instructions to copy the data into and out of the
7011 reload registers. Do these in the order that the reloads were reported,
7012 since reloads of base and index registers precede reloads of operands
7013 and the operands may need the base and index registers reloaded. */
7015 for (j = 0; j < n_reloads; j++)
7018 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7019 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7021 do_input_reload (chain, rld + j, j);
7022 do_output_reload (chain, rld + j, j);
7025 /* Now write all the insns we made for reloads in the order expected by
7026 the allocation functions. Prior to the insn being reloaded, we write
7027 the following reloads:
7029 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7031 RELOAD_OTHER reloads.
7033 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7034 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7035 RELOAD_FOR_INPUT reload for the operand.
7037 RELOAD_FOR_OPADDR_ADDRS reloads.
7039 RELOAD_FOR_OPERAND_ADDRESS reloads.
7041 After the insn being reloaded, we write the following:
7043 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7044 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7045 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7046 reloads for the operand. The RELOAD_OTHER output reloads are
7047 output in descending order by reload number. */
7049 emit_insn_before_sameloc (other_input_address_reload_insns, insn);
7050 emit_insn_before_sameloc (other_input_reload_insns, insn);
7052 for (j = 0; j < reload_n_operands; j++)
7054 emit_insn_before_sameloc (inpaddr_address_reload_insns[j], insn);
7055 emit_insn_before_sameloc (input_address_reload_insns[j], insn);
7056 emit_insn_before_sameloc (input_reload_insns[j], insn);
7059 emit_insn_before_sameloc (other_operand_reload_insns, insn);
7060 emit_insn_before_sameloc (operand_reload_insns, insn);
7062 for (j = 0; j < reload_n_operands; j++)
7064 rtx x = emit_insn_after_sameloc (outaddr_address_reload_insns[j], insn);
7065 x = emit_insn_after_sameloc (output_address_reload_insns[j], x);
7066 x = emit_insn_after_sameloc (output_reload_insns[j], x);
7067 emit_insn_after_sameloc (other_output_reload_insns[j], x);
7070 /* For all the spill regs newly reloaded in this instruction,
7071 record what they were reloaded from, so subsequent instructions
7072 can inherit the reloads.
7074 Update spill_reg_store for the reloads of this insn.
7075 Copy the elements that were updated in the loop above. */
7077 for (j = 0; j < n_reloads; j++)
7079 int r = reload_order[j];
7080 int i = reload_spill_index[r];
7082 /* If this is a non-inherited input reload from a pseudo, we must
7083 clear any memory of a previous store to the same pseudo. Only do
7084 something if there will not be an output reload for the pseudo
7086 if (rld[r].in_reg != 0
7087 && ! (reload_inherited[r] || reload_override_in[r]))
7089 rtx reg = rld[r].in_reg;
7091 if (GET_CODE (reg) == SUBREG)
7092 reg = SUBREG_REG (reg);
7094 if (GET_CODE (reg) == REG
7095 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7096 && ! reg_has_output_reload[REGNO (reg)])
7098 int nregno = REGNO (reg);
7100 if (reg_last_reload_reg[nregno])
7102 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7104 if (reg_reloaded_contents[last_regno] == nregno)
7105 spill_reg_store[last_regno] = 0;
7110 /* I is nonneg if this reload used a register.
7111 If rld[r].reg_rtx is 0, this is an optional reload
7112 that we opted to ignore. */
7114 if (i >= 0 && rld[r].reg_rtx != 0)
7116 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7118 int part_reaches_end = 0;
7119 int all_reaches_end = 1;
7121 /* For a multi register reload, we need to check if all or part
7122 of the value lives to the end. */
7123 for (k = 0; k < nr; k++)
7125 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7126 rld[r].when_needed))
7127 part_reaches_end = 1;
7129 all_reaches_end = 0;
7132 /* Ignore reloads that don't reach the end of the insn in
7134 if (all_reaches_end)
7136 /* First, clear out memory of what used to be in this spill reg.
7137 If consecutive registers are used, clear them all. */
7139 for (k = 0; k < nr; k++)
7141 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7142 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7145 /* Maybe the spill reg contains a copy of reload_out. */
7147 && (GET_CODE (rld[r].out) == REG
7151 || GET_CODE (rld[r].out_reg) == REG))
7153 rtx out = (GET_CODE (rld[r].out) == REG
7157 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7158 int nregno = REGNO (out);
7159 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7160 : hard_regno_nregs[nregno]
7161 [GET_MODE (rld[r].reg_rtx)]);
7164 spill_reg_store[i] = new_spill_reg_store[i];
7165 spill_reg_stored_to[i] = out;
7166 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7168 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7170 && inherit_piecemeal_p (r, nregno));
7172 /* If NREGNO is a hard register, it may occupy more than
7173 one register. If it does, say what is in the
7174 rest of the registers assuming that both registers
7175 agree on how many words the object takes. If not,
7176 invalidate the subsequent registers. */
7178 if (nregno < FIRST_PSEUDO_REGISTER)
7179 for (k = 1; k < nnr; k++)
7180 reg_last_reload_reg[nregno + k]
7182 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7185 /* Now do the inverse operation. */
7186 for (k = 0; k < nr; k++)
7188 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7189 reg_reloaded_contents[i + k]
7190 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7193 reg_reloaded_insn[i + k] = insn;
7194 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7195 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7196 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7200 /* Maybe the spill reg contains a copy of reload_in. Only do
7201 something if there will not be an output reload for
7202 the register being reloaded. */
7203 else if (rld[r].out_reg == 0
7205 && ((GET_CODE (rld[r].in) == REG
7206 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7207 && ! reg_has_output_reload[REGNO (rld[r].in)])
7208 || (GET_CODE (rld[r].in_reg) == REG
7209 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7210 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7217 if (GET_CODE (rld[r].in) == REG
7218 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7220 else if (GET_CODE (rld[r].in_reg) == REG)
7223 in = XEXP (rld[r].in_reg, 0);
7224 nregno = REGNO (in);
7226 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7227 : hard_regno_nregs[nregno]
7228 [GET_MODE (rld[r].reg_rtx)]);
7230 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7232 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7234 && inherit_piecemeal_p (r, nregno));
7236 if (nregno < FIRST_PSEUDO_REGISTER)
7237 for (k = 1; k < nnr; k++)
7238 reg_last_reload_reg[nregno + k]
7240 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7243 /* Unless we inherited this reload, show we haven't
7244 recently done a store.
7245 Previous stores of inherited auto_inc expressions
7246 also have to be discarded. */
7247 if (! reload_inherited[r]
7248 || (rld[r].out && ! rld[r].out_reg))
7249 spill_reg_store[i] = 0;
7251 for (k = 0; k < nr; k++)
7253 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7254 reg_reloaded_contents[i + k]
7255 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7258 reg_reloaded_insn[i + k] = insn;
7259 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7260 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7261 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7266 /* However, if part of the reload reaches the end, then we must
7267 invalidate the old info for the part that survives to the end. */
7268 else if (part_reaches_end)
7270 for (k = 0; k < nr; k++)
7271 if (reload_reg_reaches_end_p (i + k,
7273 rld[r].when_needed))
7274 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7278 /* The following if-statement was #if 0'd in 1.34 (or before...).
7279 It's reenabled in 1.35 because supposedly nothing else
7280 deals with this problem. */
7282 /* If a register gets output-reloaded from a non-spill register,
7283 that invalidates any previous reloaded copy of it.
7284 But forget_old_reloads_1 won't get to see it, because
7285 it thinks only about the original insn. So invalidate it here. */
7286 if (i < 0 && rld[r].out != 0
7287 && (GET_CODE (rld[r].out) == REG
7288 || (GET_CODE (rld[r].out) == MEM
7289 && GET_CODE (rld[r].out_reg) == REG)))
7291 rtx out = (GET_CODE (rld[r].out) == REG
7292 ? rld[r].out : rld[r].out_reg);
7293 int nregno = REGNO (out);
7294 if (nregno >= FIRST_PSEUDO_REGISTER)
7296 rtx src_reg, store_insn = NULL_RTX;
7298 reg_last_reload_reg[nregno] = 0;
7300 /* If we can find a hard register that is stored, record
7301 the storing insn so that we may delete this insn with
7302 delete_output_reload. */
7303 src_reg = rld[r].reg_rtx;
7305 /* If this is an optional reload, try to find the source reg
7306 from an input reload. */
7309 rtx set = single_set (insn);
7310 if (set && SET_DEST (set) == rld[r].out)
7314 src_reg = SET_SRC (set);
7316 for (k = 0; k < n_reloads; k++)
7318 if (rld[k].in == src_reg)
7320 src_reg = rld[k].reg_rtx;
7327 store_insn = new_spill_reg_store[REGNO (src_reg)];
7328 if (src_reg && GET_CODE (src_reg) == REG
7329 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7331 int src_regno = REGNO (src_reg);
7332 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7333 /* The place where to find a death note varies with
7334 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7335 necessarily checked exactly in the code that moves
7336 notes, so just check both locations. */
7337 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7338 if (! note && store_insn)
7339 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7342 spill_reg_store[src_regno + nr] = store_insn;
7343 spill_reg_stored_to[src_regno + nr] = out;
7344 reg_reloaded_contents[src_regno + nr] = nregno;
7345 reg_reloaded_insn[src_regno + nr] = store_insn;
7346 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7347 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7348 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7349 GET_MODE (src_reg)))
7350 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7352 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7354 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7356 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7358 reg_last_reload_reg[nregno] = src_reg;
7359 /* We have to set reg_has_output_reload here, or else
7360 forget_old_reloads_1 will clear reg_last_reload_reg
7362 reg_has_output_reload[nregno] = 1;
7367 int num_regs = hard_regno_nregs[nregno][GET_MODE (rld[r].out)];
7369 while (num_regs-- > 0)
7370 reg_last_reload_reg[nregno + num_regs] = 0;
7374 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7377 /* Emit code to perform a reload from IN (which may be a reload register) to
7378 OUT (which may also be a reload register). IN or OUT is from operand
7379 OPNUM with reload type TYPE.
7381 Returns first insn emitted. */
7384 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7386 rtx last = get_last_insn ();
7389 /* If IN is a paradoxical SUBREG, remove it and try to put the
7390 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7391 if (GET_CODE (in) == SUBREG
7392 && (GET_MODE_SIZE (GET_MODE (in))
7393 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7394 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7395 in = SUBREG_REG (in), out = tem;
7396 else if (GET_CODE (out) == SUBREG
7397 && (GET_MODE_SIZE (GET_MODE (out))
7398 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7399 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7400 out = SUBREG_REG (out), in = tem;
7402 /* How to do this reload can get quite tricky. Normally, we are being
7403 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7404 register that didn't get a hard register. In that case we can just
7405 call emit_move_insn.
7407 We can also be asked to reload a PLUS that adds a register or a MEM to
7408 another register, constant or MEM. This can occur during frame pointer
7409 elimination and while reloading addresses. This case is handled by
7410 trying to emit a single insn to perform the add. If it is not valid,
7411 we use a two insn sequence.
7413 Finally, we could be called to handle an 'o' constraint by putting
7414 an address into a register. In that case, we first try to do this
7415 with a named pattern of "reload_load_address". If no such pattern
7416 exists, we just emit a SET insn and hope for the best (it will normally
7417 be valid on machines that use 'o').
7419 This entire process is made complex because reload will never
7420 process the insns we generate here and so we must ensure that
7421 they will fit their constraints and also by the fact that parts of
7422 IN might be being reloaded separately and replaced with spill registers.
7423 Because of this, we are, in some sense, just guessing the right approach
7424 here. The one listed above seems to work.
7426 ??? At some point, this whole thing needs to be rethought. */
7428 if (GET_CODE (in) == PLUS
7429 && (GET_CODE (XEXP (in, 0)) == REG
7430 || GET_CODE (XEXP (in, 0)) == SUBREG
7431 || GET_CODE (XEXP (in, 0)) == MEM)
7432 && (GET_CODE (XEXP (in, 1)) == REG
7433 || GET_CODE (XEXP (in, 1)) == SUBREG
7434 || CONSTANT_P (XEXP (in, 1))
7435 || GET_CODE (XEXP (in, 1)) == MEM))
7437 /* We need to compute the sum of a register or a MEM and another
7438 register, constant, or MEM, and put it into the reload
7439 register. The best possible way of doing this is if the machine
7440 has a three-operand ADD insn that accepts the required operands.
7442 The simplest approach is to try to generate such an insn and see if it
7443 is recognized and matches its constraints. If so, it can be used.
7445 It might be better not to actually emit the insn unless it is valid,
7446 but we need to pass the insn as an operand to `recog' and
7447 `extract_insn' and it is simpler to emit and then delete the insn if
7448 not valid than to dummy things up. */
7450 rtx op0, op1, tem, insn;
7453 op0 = find_replacement (&XEXP (in, 0));
7454 op1 = find_replacement (&XEXP (in, 1));
7456 /* Since constraint checking is strict, commutativity won't be
7457 checked, so we need to do that here to avoid spurious failure
7458 if the add instruction is two-address and the second operand
7459 of the add is the same as the reload reg, which is frequently
7460 the case. If the insn would be A = B + A, rearrange it so
7461 it will be A = A + B as constrain_operands expects. */
7463 if (GET_CODE (XEXP (in, 1)) == REG
7464 && REGNO (out) == REGNO (XEXP (in, 1)))
7465 tem = op0, op0 = op1, op1 = tem;
7467 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7468 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7470 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7471 code = recog_memoized (insn);
7475 extract_insn (insn);
7476 /* We want constrain operands to treat this insn strictly in
7477 its validity determination, i.e., the way it would after reload
7479 if (constrain_operands (1))
7483 delete_insns_since (last);
7485 /* If that failed, we must use a conservative two-insn sequence.
7487 Use a move to copy one operand into the reload register. Prefer
7488 to reload a constant, MEM or pseudo since the move patterns can
7489 handle an arbitrary operand. If OP1 is not a constant, MEM or
7490 pseudo and OP1 is not a valid operand for an add instruction, then
7493 After reloading one of the operands into the reload register, add
7494 the reload register to the output register.
7496 If there is another way to do this for a specific machine, a
7497 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7500 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7502 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7503 || (GET_CODE (op1) == REG
7504 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7505 || (code != CODE_FOR_nothing
7506 && ! ((*insn_data[code].operand[2].predicate)
7507 (op1, insn_data[code].operand[2].mode))))
7508 tem = op0, op0 = op1, op1 = tem;
7510 gen_reload (out, op0, opnum, type);
7512 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7513 This fixes a problem on the 32K where the stack pointer cannot
7514 be used as an operand of an add insn. */
7516 if (rtx_equal_p (op0, op1))
7519 insn = emit_insn (gen_add2_insn (out, op1));
7521 /* If that failed, copy the address register to the reload register.
7522 Then add the constant to the reload register. */
7524 code = recog_memoized (insn);
7528 extract_insn (insn);
7529 /* We want constrain operands to treat this insn strictly in
7530 its validity determination, i.e., the way it would after reload
7532 if (constrain_operands (1))
7534 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7536 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7541 delete_insns_since (last);
7543 gen_reload (out, op1, opnum, type);
7544 insn = emit_insn (gen_add2_insn (out, op0));
7545 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7548 #ifdef SECONDARY_MEMORY_NEEDED
7549 /* If we need a memory location to do the move, do it that way. */
7550 else if ((GET_CODE (in) == REG || GET_CODE (in) == SUBREG)
7551 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7552 && (GET_CODE (out) == REG || GET_CODE (out) == SUBREG)
7553 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7554 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7555 REGNO_REG_CLASS (reg_or_subregno (out)),
7558 /* Get the memory to use and rewrite both registers to its mode. */
7559 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7561 if (GET_MODE (loc) != GET_MODE (out))
7562 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7564 if (GET_MODE (loc) != GET_MODE (in))
7565 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7567 gen_reload (loc, in, opnum, type);
7568 gen_reload (out, loc, opnum, type);
7572 /* If IN is a simple operand, use gen_move_insn. */
7573 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
7574 emit_insn (gen_move_insn (out, in));
7576 #ifdef HAVE_reload_load_address
7577 else if (HAVE_reload_load_address)
7578 emit_insn (gen_reload_load_address (out, in));
7581 /* Otherwise, just write (set OUT IN) and hope for the best. */
7583 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7585 /* Return the first insn emitted.
7586 We can not just return get_last_insn, because there may have
7587 been multiple instructions emitted. Also note that gen_move_insn may
7588 emit more than one insn itself, so we can not assume that there is one
7589 insn emitted per emit_insn_before call. */
7591 return last ? NEXT_INSN (last) : get_insns ();
7594 /* Delete a previously made output-reload whose result we now believe
7595 is not needed. First we double-check.
7597 INSN is the insn now being processed.
7598 LAST_RELOAD_REG is the hard register number for which we want to delete
7599 the last output reload.
7600 J is the reload-number that originally used REG. The caller has made
7601 certain that reload J doesn't use REG any longer for input. */
7604 delete_output_reload (rtx insn, int j, int last_reload_reg)
7606 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7607 rtx reg = spill_reg_stored_to[last_reload_reg];
7610 int n_inherited = 0;
7614 /* It is possible that this reload has been only used to set another reload
7615 we eliminated earlier and thus deleted this instruction too. */
7616 if (INSN_DELETED_P (output_reload_insn))
7619 /* Get the raw pseudo-register referred to. */
7621 while (GET_CODE (reg) == SUBREG)
7622 reg = SUBREG_REG (reg);
7623 substed = reg_equiv_memory_loc[REGNO (reg)];
7625 /* This is unsafe if the operand occurs more often in the current
7626 insn than it is inherited. */
7627 for (k = n_reloads - 1; k >= 0; k--)
7629 rtx reg2 = rld[k].in;
7632 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7633 reg2 = rld[k].in_reg;
7635 if (rld[k].out && ! rld[k].out_reg)
7636 reg2 = XEXP (rld[k].in_reg, 0);
7638 while (GET_CODE (reg2) == SUBREG)
7639 reg2 = SUBREG_REG (reg2);
7640 if (rtx_equal_p (reg2, reg))
7642 if (reload_inherited[k] || reload_override_in[k] || k == j)
7645 reg2 = rld[k].out_reg;
7648 while (GET_CODE (reg2) == SUBREG)
7649 reg2 = XEXP (reg2, 0);
7650 if (rtx_equal_p (reg2, reg))
7657 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7659 n_occurrences += count_occurrences (PATTERN (insn),
7660 eliminate_regs (substed, 0,
7662 if (n_occurrences > n_inherited)
7665 /* If the pseudo-reg we are reloading is no longer referenced
7666 anywhere between the store into it and here,
7667 and no jumps or labels intervene, then the value can get
7668 here through the reload reg alone.
7669 Otherwise, give up--return. */
7670 for (i1 = NEXT_INSN (output_reload_insn);
7671 i1 != insn; i1 = NEXT_INSN (i1))
7673 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7675 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7676 && reg_mentioned_p (reg, PATTERN (i1)))
7678 /* If this is USE in front of INSN, we only have to check that
7679 there are no more references than accounted for by inheritance. */
7680 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7682 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7683 i1 = NEXT_INSN (i1);
7685 if (n_occurrences <= n_inherited && i1 == insn)
7691 /* We will be deleting the insn. Remove the spill reg information. */
7692 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
7694 spill_reg_store[last_reload_reg + k] = 0;
7695 spill_reg_stored_to[last_reload_reg + k] = 0;
7698 /* The caller has already checked that REG dies or is set in INSN.
7699 It has also checked that we are optimizing, and thus some
7700 inaccuracies in the debugging information are acceptable.
7701 So we could just delete output_reload_insn. But in some cases
7702 we can improve the debugging information without sacrificing
7703 optimization - maybe even improving the code: See if the pseudo
7704 reg has been completely replaced with reload regs. If so, delete
7705 the store insn and forget we had a stack slot for the pseudo. */
7706 if (rld[j].out != rld[j].in
7707 && REG_N_DEATHS (REGNO (reg)) == 1
7708 && REG_N_SETS (REGNO (reg)) == 1
7709 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7710 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7714 /* We know that it was used only between here and the beginning of
7715 the current basic block. (We also know that the last use before
7716 INSN was the output reload we are thinking of deleting, but never
7717 mind that.) Search that range; see if any ref remains. */
7718 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7720 rtx set = single_set (i2);
7722 /* Uses which just store in the pseudo don't count,
7723 since if they are the only uses, they are dead. */
7724 if (set != 0 && SET_DEST (set) == reg)
7726 if (GET_CODE (i2) == CODE_LABEL
7727 || GET_CODE (i2) == JUMP_INSN)
7729 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7730 && reg_mentioned_p (reg, PATTERN (i2)))
7732 /* Some other ref remains; just delete the output reload we
7734 delete_address_reloads (output_reload_insn, insn);
7735 delete_insn (output_reload_insn);
7740 /* Delete the now-dead stores into this pseudo. Note that this
7741 loop also takes care of deleting output_reload_insn. */
7742 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7744 rtx set = single_set (i2);
7746 if (set != 0 && SET_DEST (set) == reg)
7748 delete_address_reloads (i2, insn);
7751 if (GET_CODE (i2) == CODE_LABEL
7752 || GET_CODE (i2) == JUMP_INSN)
7756 /* For the debugging info, say the pseudo lives in this reload reg. */
7757 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7758 alter_reg (REGNO (reg), -1);
7762 delete_address_reloads (output_reload_insn, insn);
7763 delete_insn (output_reload_insn);
7767 /* We are going to delete DEAD_INSN. Recursively delete loads of
7768 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7769 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7771 delete_address_reloads (rtx dead_insn, rtx current_insn)
7773 rtx set = single_set (dead_insn);
7774 rtx set2, dst, prev, next;
7777 rtx dst = SET_DEST (set);
7778 if (GET_CODE (dst) == MEM)
7779 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7781 /* If we deleted the store from a reloaded post_{in,de}c expression,
7782 we can delete the matching adds. */
7783 prev = PREV_INSN (dead_insn);
7784 next = NEXT_INSN (dead_insn);
7785 if (! prev || ! next)
7787 set = single_set (next);
7788 set2 = single_set (prev);
7790 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7791 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7792 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7794 dst = SET_DEST (set);
7795 if (! rtx_equal_p (dst, SET_DEST (set2))
7796 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7797 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7798 || (INTVAL (XEXP (SET_SRC (set), 1))
7799 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7801 delete_related_insns (prev);
7802 delete_related_insns (next);
7805 /* Subfunction of delete_address_reloads: process registers found in X. */
7807 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
7809 rtx prev, set, dst, i2;
7811 enum rtx_code code = GET_CODE (x);
7815 const char *fmt = GET_RTX_FORMAT (code);
7816 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7819 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7820 else if (fmt[i] == 'E')
7822 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7823 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7830 if (spill_reg_order[REGNO (x)] < 0)
7833 /* Scan backwards for the insn that sets x. This might be a way back due
7835 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7837 code = GET_CODE (prev);
7838 if (code == CODE_LABEL || code == JUMP_INSN)
7842 if (reg_set_p (x, PATTERN (prev)))
7844 if (reg_referenced_p (x, PATTERN (prev)))
7847 if (! prev || INSN_UID (prev) < reload_first_uid)
7849 /* Check that PREV only sets the reload register. */
7850 set = single_set (prev);
7853 dst = SET_DEST (set);
7854 if (GET_CODE (dst) != REG
7855 || ! rtx_equal_p (dst, x))
7857 if (! reg_set_p (dst, PATTERN (dead_insn)))
7859 /* Check if DST was used in a later insn -
7860 it might have been inherited. */
7861 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7863 if (GET_CODE (i2) == CODE_LABEL)
7867 if (reg_referenced_p (dst, PATTERN (i2)))
7869 /* If there is a reference to the register in the current insn,
7870 it might be loaded in a non-inherited reload. If no other
7871 reload uses it, that means the register is set before
7873 if (i2 == current_insn)
7875 for (j = n_reloads - 1; j >= 0; j--)
7876 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7877 || reload_override_in[j] == dst)
7879 for (j = n_reloads - 1; j >= 0; j--)
7880 if (rld[j].in && rld[j].reg_rtx == dst)
7887 if (GET_CODE (i2) == JUMP_INSN)
7889 /* If DST is still live at CURRENT_INSN, check if it is used for
7890 any reload. Note that even if CURRENT_INSN sets DST, we still
7891 have to check the reloads. */
7892 if (i2 == current_insn)
7894 for (j = n_reloads - 1; j >= 0; j--)
7895 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7896 || reload_override_in[j] == dst)
7898 /* ??? We can't finish the loop here, because dst might be
7899 allocated to a pseudo in this block if no reload in this
7900 block needs any of the classes containing DST - see
7901 spill_hard_reg. There is no easy way to tell this, so we
7902 have to scan till the end of the basic block. */
7904 if (reg_set_p (dst, PATTERN (i2)))
7908 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7909 reg_reloaded_contents[REGNO (dst)] = -1;
7913 /* Output reload-insns to reload VALUE into RELOADREG.
7914 VALUE is an autoincrement or autodecrement RTX whose operand
7915 is a register or memory location;
7916 so reloading involves incrementing that location.
7917 IN is either identical to VALUE, or some cheaper place to reload from.
7919 INC_AMOUNT is the number to increment or decrement by (always positive).
7920 This cannot be deduced from VALUE.
7922 Return the instruction that stores into RELOADREG. */
7925 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
7927 /* REG or MEM to be copied and incremented. */
7928 rtx incloc = XEXP (value, 0);
7929 /* Nonzero if increment after copying. */
7930 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7936 rtx real_in = in == value ? XEXP (in, 0) : in;
7938 /* No hard register is equivalent to this register after
7939 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7940 we could inc/dec that register as well (maybe even using it for
7941 the source), but I'm not sure it's worth worrying about. */
7942 if (GET_CODE (incloc) == REG)
7943 reg_last_reload_reg[REGNO (incloc)] = 0;
7945 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7946 inc_amount = -inc_amount;
7948 inc = GEN_INT (inc_amount);
7950 /* If this is post-increment, first copy the location to the reload reg. */
7951 if (post && real_in != reloadreg)
7952 emit_insn (gen_move_insn (reloadreg, real_in));
7956 /* See if we can directly increment INCLOC. Use a method similar to
7957 that in gen_reload. */
7959 last = get_last_insn ();
7960 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7961 gen_rtx_PLUS (GET_MODE (incloc),
7964 code = recog_memoized (add_insn);
7967 extract_insn (add_insn);
7968 if (constrain_operands (1))
7970 /* If this is a pre-increment and we have incremented the value
7971 where it lives, copy the incremented value to RELOADREG to
7972 be used as an address. */
7975 emit_insn (gen_move_insn (reloadreg, incloc));
7980 delete_insns_since (last);
7983 /* If couldn't do the increment directly, must increment in RELOADREG.
7984 The way we do this depends on whether this is pre- or post-increment.
7985 For pre-increment, copy INCLOC to the reload register, increment it
7986 there, then save back. */
7990 if (in != reloadreg)
7991 emit_insn (gen_move_insn (reloadreg, real_in));
7992 emit_insn (gen_add2_insn (reloadreg, inc));
7993 store = emit_insn (gen_move_insn (incloc, reloadreg));
7998 Because this might be a jump insn or a compare, and because RELOADREG
7999 may not be available after the insn in an input reload, we must do
8000 the incrementation before the insn being reloaded for.
8002 We have already copied IN to RELOADREG. Increment the copy in
8003 RELOADREG, save that back, then decrement RELOADREG so it has
8004 the original value. */
8006 emit_insn (gen_add2_insn (reloadreg, inc));
8007 store = emit_insn (gen_move_insn (incloc, reloadreg));
8008 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8016 add_auto_inc_notes (rtx insn, rtx x)
8018 enum rtx_code code = GET_CODE (x);
8022 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8025 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8029 /* Scan all the operand sub-expressions. */
8030 fmt = GET_RTX_FORMAT (code);
8031 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8034 add_auto_inc_notes (insn, XEXP (x, i));
8035 else if (fmt[i] == 'E')
8036 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8037 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8042 /* Copy EH notes from an insn to its reloads. */
8044 copy_eh_notes (rtx insn, rtx x)
8046 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8049 for (; x != 0; x = NEXT_INSN (x))
8051 if (may_trap_p (PATTERN (x)))
8053 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8059 /* This is used by reload pass, that does emit some instructions after
8060 abnormal calls moving basic block end, but in fact it wants to emit
8061 them on the edge. Looks for abnormal call edges, find backward the
8062 proper call and fix the damage.
8064 Similar handle instructions throwing exceptions internally. */
8066 fixup_abnormal_edges (void)
8068 bool inserted = false;
8075 /* Look for cases we are interested in - calls or instructions causing
8077 for (e = bb->succ; e; e = e->succ_next)
8079 if (e->flags & EDGE_ABNORMAL_CALL)
8081 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8082 == (EDGE_ABNORMAL | EDGE_EH))
8085 if (e && GET_CODE (BB_END (bb)) != CALL_INSN
8086 && !can_throw_internal (BB_END (bb)))
8088 rtx insn = BB_END (bb), stop = NEXT_INSN (BB_END (bb));
8090 for (e = bb->succ; e; e = e->succ_next)
8091 if (e->flags & EDGE_FALLTHRU)
8093 /* Get past the new insns generated. Allow notes, as the insns may
8094 be already deleted. */
8095 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE)
8096 && !can_throw_internal (insn)
8097 && insn != BB_HEAD (bb))
8098 insn = PREV_INSN (insn);
8099 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn))
8103 insn = NEXT_INSN (insn);
8104 while (insn && insn != stop)
8106 next = NEXT_INSN (insn);
8111 /* Sometimes there's still the return value USE.
8112 If it's placed after a trapping call (i.e. that
8113 call is the last insn anyway), we have no fallthru
8114 edge. Simply delete this use and don't try to insert
8115 on the non-existent edge. */
8116 if (GET_CODE (PATTERN (insn)) != USE)
8118 /* We're not deleting it, we're moving it. */
8119 INSN_DELETED_P (insn) = 0;
8120 PREV_INSN (insn) = NULL_RTX;
8121 NEXT_INSN (insn) = NULL_RTX;
8123 insert_insn_on_edge (insn, e);
8130 /* We've possibly turned single trapping insn into multiple ones. */
8131 if (flag_non_call_exceptions)
8134 blocks = sbitmap_alloc (last_basic_block);
8135 sbitmap_ones (blocks);
8136 find_many_sub_basic_blocks (blocks);
8139 commit_edge_insertions ();
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