1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
106 This is used when the address is not valid as a memory address
107 (because its displacement is too big for the machine.) */
108 rtx *reg_equiv_address;
110 /* Element N is the memory slot to which pseudo reg N is equivalent,
111 or zero if pseudo reg N is not equivalent to a memory slot. */
114 /* Widest width in which each pseudo reg is referred to (via subreg). */
115 static unsigned int *reg_max_ref_width;
117 /* Element N is the list of insns that initialized reg N from its equivalent
118 constant or memory slot. */
119 static rtx *reg_equiv_init;
121 /* Vector to remember old contents of reg_renumber before spilling. */
122 static short *reg_old_renumber;
124 /* During reload_as_needed, element N contains the last pseudo regno reloaded
125 into hard register N. If that pseudo reg occupied more than one register,
126 reg_reloaded_contents points to that pseudo for each spill register in
127 use; all of these must remain set for an inheritance to occur. */
128 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
130 /* During reload_as_needed, element N contains the insn for which
131 hard register N was last used. Its contents are significant only
132 when reg_reloaded_valid is set for this register. */
133 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
135 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
136 static HARD_REG_SET reg_reloaded_valid;
137 /* Indicate if the register was dead at the end of the reload.
138 This is only valid if reg_reloaded_contents is set and valid. */
139 static HARD_REG_SET reg_reloaded_dead;
141 /* Indicate whether the register's current value is one that is not
142 safe to retain across a call, even for registers that are normally
144 static HARD_REG_SET reg_reloaded_call_part_clobbered;
146 /* Number of spill-regs so far; number of valid elements of spill_regs. */
149 /* In parallel with spill_regs, contains REG rtx's for those regs.
150 Holds the last rtx used for any given reg, or 0 if it has never
151 been used for spilling yet. This rtx is reused, provided it has
153 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
155 /* In parallel with spill_regs, contains nonzero for a spill reg
156 that was stored after the last time it was used.
157 The precise value is the insn generated to do the store. */
158 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
160 /* This is the register that was stored with spill_reg_store. This is a
161 copy of reload_out / reload_out_reg when the value was stored; if
162 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
163 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
165 /* This table is the inverse mapping of spill_regs:
166 indexed by hard reg number,
167 it contains the position of that reg in spill_regs,
168 or -1 for something that is not in spill_regs.
170 ?!? This is no longer accurate. */
171 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
173 /* This reg set indicates registers that can't be used as spill registers for
174 the currently processed insn. These are the hard registers which are live
175 during the insn, but not allocated to pseudos, as well as fixed
177 static HARD_REG_SET bad_spill_regs;
179 /* These are the hard registers that can't be used as spill register for any
180 insn. This includes registers used for user variables and registers that
181 we can't eliminate. A register that appears in this set also can't be used
182 to retry register allocation. */
183 static HARD_REG_SET bad_spill_regs_global;
185 /* Describes order of use of registers for reloading
186 of spilled pseudo-registers. `n_spills' is the number of
187 elements that are actually valid; new ones are added at the end.
189 Both spill_regs and spill_reg_order are used on two occasions:
190 once during find_reload_regs, where they keep track of the spill registers
191 for a single insn, but also during reload_as_needed where they show all
192 the registers ever used by reload. For the latter case, the information
193 is calculated during finish_spills. */
194 static short spill_regs[FIRST_PSEUDO_REGISTER];
196 /* This vector of reg sets indicates, for each pseudo, which hard registers
197 may not be used for retrying global allocation because the register was
198 formerly spilled from one of them. If we allowed reallocating a pseudo to
199 a register that it was already allocated to, reload might not
201 static HARD_REG_SET *pseudo_previous_regs;
203 /* This vector of reg sets indicates, for each pseudo, which hard
204 registers may not be used for retrying global allocation because they
205 are used as spill registers during one of the insns in which the
207 static HARD_REG_SET *pseudo_forbidden_regs;
209 /* All hard regs that have been used as spill registers for any insn are
210 marked in this set. */
211 static HARD_REG_SET used_spill_regs;
213 /* Index of last register assigned as a spill register. We allocate in
214 a round-robin fashion. */
215 static int last_spill_reg;
217 /* Nonzero if indirect addressing is supported on the machine; this means
218 that spilling (REG n) does not require reloading it into a register in
219 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
220 value indicates the level of indirect addressing supported, e.g., two
221 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
223 static char spill_indirect_levels;
225 /* Nonzero if indirect addressing is supported when the innermost MEM is
226 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
227 which these are valid is the same as spill_indirect_levels, above. */
228 char indirect_symref_ok;
230 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
231 char double_reg_address_ok;
233 /* Record the stack slot for each spilled hard register. */
234 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
236 /* Width allocated so far for that stack slot. */
237 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
239 /* Record which pseudos needed to be spilled. */
240 static regset_head spilled_pseudos;
242 /* Used for communication between order_regs_for_reload and count_pseudo.
243 Used to avoid counting one pseudo twice. */
244 static regset_head pseudos_counted;
246 /* First uid used by insns created by reload in this function.
247 Used in find_equiv_reg. */
248 int reload_first_uid;
250 /* Flag set by local-alloc or global-alloc if anything is live in
251 a call-clobbered reg across calls. */
252 int caller_save_needed;
254 /* Set to 1 while reload_as_needed is operating.
255 Required by some machines to handle any generated moves differently. */
256 int reload_in_progress = 0;
258 /* These arrays record the insn_code of insns that may be needed to
259 perform input and output reloads of special objects. They provide a
260 place to pass a scratch register. */
261 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
262 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
264 /* This obstack is used for allocation of rtl during register elimination.
265 The allocated storage can be freed once find_reloads has processed the
267 struct obstack reload_obstack;
269 /* Points to the beginning of the reload_obstack. All insn_chain structures
270 are allocated first. */
271 char *reload_startobj;
273 /* The point after all insn_chain structures. Used to quickly deallocate
274 memory allocated in copy_reloads during calculate_needs_all_insns. */
275 char *reload_firstobj;
277 /* This points before all local rtl generated by register elimination.
278 Used to quickly free all memory after processing one insn. */
279 static char *reload_insn_firstobj;
281 /* List of insn_chain instructions, one for every insn that reload needs to
283 struct insn_chain *reload_insn_chain;
285 /* List of all insns needing reloads. */
286 static struct insn_chain *insns_need_reload;
288 /* This structure is used to record information about register eliminations.
289 Each array entry describes one possible way of eliminating a register
290 in favor of another. If there is more than one way of eliminating a
291 particular register, the most preferred should be specified first. */
295 int from; /* Register number to be eliminated. */
296 int to; /* Register number used as replacement. */
297 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
298 int can_eliminate; /* Nonzero if this elimination can be done. */
299 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
300 insns made by reload. */
301 HOST_WIDE_INT offset; /* Current offset between the two regs. */
302 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
303 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
304 rtx from_rtx; /* REG rtx for the register to be eliminated.
305 We cannot simply compare the number since
306 we might then spuriously replace a hard
307 register corresponding to a pseudo
308 assigned to the reg to be eliminated. */
309 rtx to_rtx; /* REG rtx for the replacement. */
312 static struct elim_table *reg_eliminate = 0;
314 /* This is an intermediate structure to initialize the table. It has
315 exactly the members provided by ELIMINABLE_REGS. */
316 static const struct elim_table_1
320 } reg_eliminate_1[] =
322 /* If a set of eliminable registers was specified, define the table from it.
323 Otherwise, default to the normal case of the frame pointer being
324 replaced by the stack pointer. */
326 #ifdef ELIMINABLE_REGS
329 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
332 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
334 /* Record the number of pending eliminations that have an offset not equal
335 to their initial offset. If nonzero, we use a new copy of each
336 replacement result in any insns encountered. */
337 int num_not_at_initial_offset;
339 /* Count the number of registers that we may be able to eliminate. */
340 static int num_eliminable;
341 /* And the number of registers that are equivalent to a constant that
342 can be eliminated to frame_pointer / arg_pointer + constant. */
343 static int num_eliminable_invariants;
345 /* For each label, we record the offset of each elimination. If we reach
346 a label by more than one path and an offset differs, we cannot do the
347 elimination. This information is indexed by the difference of the
348 number of the label and the first label number. We can't offset the
349 pointer itself as this can cause problems on machines with segmented
350 memory. The first table is an array of flags that records whether we
351 have yet encountered a label and the second table is an array of arrays,
352 one entry in the latter array for each elimination. */
354 static int first_label_num;
355 static char *offsets_known_at;
356 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
358 /* Number of labels in the current function. */
360 static int num_labels;
362 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
363 static void maybe_fix_stack_asms (void);
364 static void copy_reloads (struct insn_chain *);
365 static void calculate_needs_all_insns (int);
366 static int find_reg (struct insn_chain *, int);
367 static void find_reload_regs (struct insn_chain *);
368 static void select_reload_regs (void);
369 static void delete_caller_save_insns (void);
371 static void spill_failure (rtx, enum reg_class);
372 static void count_spilled_pseudo (int, int, int);
373 static void delete_dead_insn (rtx);
374 static void alter_reg (int, int);
375 static void set_label_offsets (rtx, rtx, int);
376 static void check_eliminable_occurrences (rtx);
377 static void elimination_effects (rtx, enum machine_mode);
378 static int eliminate_regs_in_insn (rtx, int);
379 static void update_eliminable_offsets (void);
380 static void mark_not_eliminable (rtx, rtx, void *);
381 static void set_initial_elim_offsets (void);
382 static void verify_initial_elim_offsets (void);
383 static void set_initial_label_offsets (void);
384 static void set_offsets_for_label (rtx);
385 static void init_elim_table (void);
386 static void update_eliminables (HARD_REG_SET *);
387 static void spill_hard_reg (unsigned int, int);
388 static int finish_spills (int);
389 static void ior_hard_reg_set (HARD_REG_SET *, HARD_REG_SET *);
390 static void scan_paradoxical_subregs (rtx);
391 static void count_pseudo (int);
392 static void order_regs_for_reload (struct insn_chain *);
393 static void reload_as_needed (int);
394 static void forget_old_reloads_1 (rtx, rtx, void *);
395 static int reload_reg_class_lower (const void *, const void *);
396 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
398 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
400 static int reload_reg_free_p (unsigned int, int, enum reload_type);
401 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
403 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
405 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
406 static int allocate_reload_reg (struct insn_chain *, int, int);
407 static int conflicts_with_override (rtx);
408 static void failed_reload (rtx, int);
409 static int set_reload_reg (int, int);
410 static void choose_reload_regs_init (struct insn_chain *, rtx *);
411 static void choose_reload_regs (struct insn_chain *);
412 static void merge_assigned_reloads (rtx);
413 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
415 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
417 static void do_input_reload (struct insn_chain *, struct reload *, int);
418 static void do_output_reload (struct insn_chain *, struct reload *, int);
419 static void emit_reload_insns (struct insn_chain *);
420 static void delete_output_reload (rtx, int, int);
421 static void delete_address_reloads (rtx, rtx);
422 static void delete_address_reloads_1 (rtx, rtx, rtx);
423 static rtx inc_for_reload (rtx, rtx, rtx, int);
425 static void add_auto_inc_notes (rtx, rtx);
427 static void copy_eh_notes (rtx, rtx);
429 /* Initialize the reload pass once per compilation. */
436 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
437 Set spill_indirect_levels to the number of levels such addressing is
438 permitted, zero if it is not permitted at all. */
441 = gen_rtx_MEM (Pmode,
444 LAST_VIRTUAL_REGISTER + 1),
446 spill_indirect_levels = 0;
448 while (memory_address_p (QImode, tem))
450 spill_indirect_levels++;
451 tem = gen_rtx_MEM (Pmode, tem);
454 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
456 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
457 indirect_symref_ok = memory_address_p (QImode, tem);
459 /* See if reg+reg is a valid (and offsettable) address. */
461 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
463 tem = gen_rtx_PLUS (Pmode,
464 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
465 gen_rtx_REG (Pmode, i));
467 /* This way, we make sure that reg+reg is an offsettable address. */
468 tem = plus_constant (tem, 4);
470 if (memory_address_p (QImode, tem))
472 double_reg_address_ok = 1;
477 /* Initialize obstack for our rtl allocation. */
478 gcc_obstack_init (&reload_obstack);
479 reload_startobj = obstack_alloc (&reload_obstack, 0);
481 INIT_REG_SET (&spilled_pseudos);
482 INIT_REG_SET (&pseudos_counted);
485 /* List of insn chains that are currently unused. */
486 static struct insn_chain *unused_insn_chains = 0;
488 /* Allocate an empty insn_chain structure. */
490 new_insn_chain (void)
492 struct insn_chain *c;
494 if (unused_insn_chains == 0)
496 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
497 INIT_REG_SET (&c->live_throughout);
498 INIT_REG_SET (&c->dead_or_set);
502 c = unused_insn_chains;
503 unused_insn_chains = c->next;
505 c->is_caller_save_insn = 0;
506 c->need_operand_change = 0;
512 /* Small utility function to set all regs in hard reg set TO which are
513 allocated to pseudos in regset FROM. */
516 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
520 EXECUTE_IF_SET_IN_REG_SET
521 (from, FIRST_PSEUDO_REGISTER, regno,
523 int r = reg_renumber[regno];
528 /* reload_combine uses the information from
529 BASIC_BLOCK->global_live_at_start, which might still
530 contain registers that have not actually been allocated
531 since they have an equivalence. */
532 if (! reload_completed)
537 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
539 SET_HARD_REG_BIT (*to, r + nregs);
544 /* Replace all pseudos found in LOC with their corresponding
548 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
561 unsigned int regno = REGNO (x);
563 if (regno < FIRST_PSEUDO_REGISTER)
566 x = eliminate_regs (x, mem_mode, usage);
570 replace_pseudos_in (loc, mem_mode, usage);
574 if (reg_equiv_constant[regno])
575 *loc = reg_equiv_constant[regno];
576 else if (reg_equiv_mem[regno])
577 *loc = reg_equiv_mem[regno];
578 else if (reg_equiv_address[regno])
579 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
580 else if (GET_CODE (regno_reg_rtx[regno]) != REG
581 || REGNO (regno_reg_rtx[regno]) != regno)
582 *loc = regno_reg_rtx[regno];
588 else if (code == MEM)
590 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
594 /* Process each of our operands recursively. */
595 fmt = GET_RTX_FORMAT (code);
596 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
598 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
599 else if (*fmt == 'E')
600 for (j = 0; j < XVECLEN (x, i); j++)
601 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
605 /* Global variables used by reload and its subroutines. */
607 /* Set during calculate_needs if an insn needs register elimination. */
608 static int something_needs_elimination;
609 /* Set during calculate_needs if an insn needs an operand changed. */
610 int something_needs_operands_changed;
612 /* Nonzero means we couldn't get enough spill regs. */
615 /* Main entry point for the reload pass.
617 FIRST is the first insn of the function being compiled.
619 GLOBAL nonzero means we were called from global_alloc
620 and should attempt to reallocate any pseudoregs that we
621 displace from hard regs we will use for reloads.
622 If GLOBAL is zero, we do not have enough information to do that,
623 so any pseudo reg that is spilled must go to the stack.
625 Return value is nonzero if reload failed
626 and we must not do any more for this function. */
629 reload (rtx first, int global)
633 struct elim_table *ep;
636 /* Make sure even insns with volatile mem refs are recognizable. */
641 reload_firstobj = obstack_alloc (&reload_obstack, 0);
643 /* Make sure that the last insn in the chain
644 is not something that needs reloading. */
645 emit_note (NOTE_INSN_DELETED);
647 /* Enable find_equiv_reg to distinguish insns made by reload. */
648 reload_first_uid = get_max_uid ();
650 #ifdef SECONDARY_MEMORY_NEEDED
651 /* Initialize the secondary memory table. */
652 clear_secondary_mem ();
655 /* We don't have a stack slot for any spill reg yet. */
656 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
657 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
659 /* Initialize the save area information for caller-save, in case some
663 /* Compute which hard registers are now in use
664 as homes for pseudo registers.
665 This is done here rather than (eg) in global_alloc
666 because this point is reached even if not optimizing. */
667 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
670 /* A function that receives a nonlocal goto must save all call-saved
672 if (current_function_has_nonlocal_label)
673 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
674 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
675 regs_ever_live[i] = 1;
677 #ifdef NON_SAVING_SETJMP
678 /* A function that calls setjmp should save and restore all the
679 call-saved registers on a system where longjmp clobbers them. */
680 if (NON_SAVING_SETJMP && current_function_calls_setjmp)
682 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
683 if (! call_used_regs[i])
684 regs_ever_live[i] = 1;
688 /* Find all the pseudo registers that didn't get hard regs
689 but do have known equivalent constants or memory slots.
690 These include parameters (known equivalent to parameter slots)
691 and cse'd or loop-moved constant memory addresses.
693 Record constant equivalents in reg_equiv_constant
694 so they will be substituted by find_reloads.
695 Record memory equivalents in reg_mem_equiv so they can
696 be substituted eventually by altering the REG-rtx's. */
698 reg_equiv_constant = xcalloc (max_regno, sizeof (rtx));
699 reg_equiv_mem = xcalloc (max_regno, sizeof (rtx));
700 reg_equiv_init = xcalloc (max_regno, sizeof (rtx));
701 reg_equiv_address = xcalloc (max_regno, sizeof (rtx));
702 reg_max_ref_width = xcalloc (max_regno, sizeof (int));
703 reg_old_renumber = xcalloc (max_regno, sizeof (short));
704 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
705 pseudo_forbidden_regs = xmalloc (max_regno * sizeof (HARD_REG_SET));
706 pseudo_previous_regs = xcalloc (max_regno, sizeof (HARD_REG_SET));
708 CLEAR_HARD_REG_SET (bad_spill_regs_global);
710 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
711 to. Also find all paradoxical subregs and find largest such for
714 num_eliminable_invariants = 0;
715 for (insn = first; insn; insn = NEXT_INSN (insn))
717 rtx set = single_set (insn);
719 /* We may introduce USEs that we want to remove at the end, so
720 we'll mark them with QImode. Make sure there are no
721 previously-marked insns left by say regmove. */
722 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
723 && GET_MODE (insn) != VOIDmode)
724 PUT_MODE (insn, VOIDmode);
726 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
728 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
730 #ifdef LEGITIMATE_PIC_OPERAND_P
731 && (! function_invariant_p (XEXP (note, 0))
733 /* A function invariant is often CONSTANT_P but may
734 include a register. We promise to only pass
735 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
736 || (CONSTANT_P (XEXP (note, 0))
737 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))))
741 rtx x = XEXP (note, 0);
742 i = REGNO (SET_DEST (set));
743 if (i > LAST_VIRTUAL_REGISTER)
745 /* It can happen that a REG_EQUIV note contains a MEM
746 that is not a legitimate memory operand. As later
747 stages of reload assume that all addresses found
748 in the reg_equiv_* arrays were originally legitimate,
749 we ignore such REG_EQUIV notes. */
750 if (memory_operand (x, VOIDmode))
752 /* Always unshare the equivalence, so we can
753 substitute into this insn without touching the
755 reg_equiv_memory_loc[i] = copy_rtx (x);
757 else if (function_invariant_p (x))
759 if (GET_CODE (x) == PLUS)
761 /* This is PLUS of frame pointer and a constant,
762 and might be shared. Unshare it. */
763 reg_equiv_constant[i] = copy_rtx (x);
764 num_eliminable_invariants++;
766 else if (x == frame_pointer_rtx
767 || x == arg_pointer_rtx)
769 reg_equiv_constant[i] = x;
770 num_eliminable_invariants++;
772 else if (LEGITIMATE_CONSTANT_P (x))
773 reg_equiv_constant[i] = x;
776 reg_equiv_memory_loc[i]
777 = force_const_mem (GET_MODE (SET_DEST (set)), x);
778 if (!reg_equiv_memory_loc[i])
785 /* If this register is being made equivalent to a MEM
786 and the MEM is not SET_SRC, the equivalencing insn
787 is one with the MEM as a SET_DEST and it occurs later.
788 So don't mark this insn now. */
789 if (GET_CODE (x) != MEM
790 || rtx_equal_p (SET_SRC (set), x))
792 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
797 /* If this insn is setting a MEM from a register equivalent to it,
798 this is the equivalencing insn. */
799 else if (set && GET_CODE (SET_DEST (set)) == MEM
800 && GET_CODE (SET_SRC (set)) == REG
801 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
802 && rtx_equal_p (SET_DEST (set),
803 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
804 reg_equiv_init[REGNO (SET_SRC (set))]
805 = gen_rtx_INSN_LIST (VOIDmode, insn,
806 reg_equiv_init[REGNO (SET_SRC (set))]);
809 scan_paradoxical_subregs (PATTERN (insn));
814 first_label_num = get_first_label_num ();
815 num_labels = max_label_num () - first_label_num;
817 /* Allocate the tables used to store offset information at labels. */
818 /* We used to use alloca here, but the size of what it would try to
819 allocate would occasionally cause it to exceed the stack limit and
820 cause a core dump. */
821 offsets_known_at = xmalloc (num_labels);
822 offsets_at = xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
824 /* Alter each pseudo-reg rtx to contain its hard reg number.
825 Assign stack slots to the pseudos that lack hard regs or equivalents.
826 Do not touch virtual registers. */
828 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
831 /* If we have some registers we think can be eliminated, scan all insns to
832 see if there is an insn that sets one of these registers to something
833 other than itself plus a constant. If so, the register cannot be
834 eliminated. Doing this scan here eliminates an extra pass through the
835 main reload loop in the most common case where register elimination
837 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
838 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
839 || GET_CODE (insn) == CALL_INSN)
840 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
842 maybe_fix_stack_asms ();
844 insns_need_reload = 0;
845 something_needs_elimination = 0;
847 /* Initialize to -1, which means take the first spill register. */
850 /* Spill any hard regs that we know we can't eliminate. */
851 CLEAR_HARD_REG_SET (used_spill_regs);
852 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
853 if (! ep->can_eliminate)
854 spill_hard_reg (ep->from, 1);
856 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
857 if (frame_pointer_needed)
858 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
860 finish_spills (global);
862 /* From now on, we may need to generate moves differently. We may also
863 allow modifications of insns which cause them to not be recognized.
864 Any such modifications will be cleaned up during reload itself. */
865 reload_in_progress = 1;
867 /* This loop scans the entire function each go-round
868 and repeats until one repetition spills no additional hard regs. */
871 int something_changed;
874 HOST_WIDE_INT starting_frame_size;
876 /* Round size of stack frame to stack_alignment_needed. This must be done
877 here because the stack size may be a part of the offset computation
878 for register elimination, and there might have been new stack slots
879 created in the last iteration of this loop. */
880 if (cfun->stack_alignment_needed)
881 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
883 starting_frame_size = get_frame_size ();
885 set_initial_elim_offsets ();
886 set_initial_label_offsets ();
888 /* For each pseudo register that has an equivalent location defined,
889 try to eliminate any eliminable registers (such as the frame pointer)
890 assuming initial offsets for the replacement register, which
893 If the resulting location is directly addressable, substitute
894 the MEM we just got directly for the old REG.
896 If it is not addressable but is a constant or the sum of a hard reg
897 and constant, it is probably not addressable because the constant is
898 out of range, in that case record the address; we will generate
899 hairy code to compute the address in a register each time it is
900 needed. Similarly if it is a hard register, but one that is not
901 valid as an address register.
903 If the location is not addressable, but does not have one of the
904 above forms, assign a stack slot. We have to do this to avoid the
905 potential of producing lots of reloads if, e.g., a location involves
906 a pseudo that didn't get a hard register and has an equivalent memory
907 location that also involves a pseudo that didn't get a hard register.
909 Perhaps at some point we will improve reload_when_needed handling
910 so this problem goes away. But that's very hairy. */
912 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
913 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
915 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
917 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
919 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
920 else if (CONSTANT_P (XEXP (x, 0))
921 || (GET_CODE (XEXP (x, 0)) == REG
922 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
923 || (GET_CODE (XEXP (x, 0)) == PLUS
924 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
925 && (REGNO (XEXP (XEXP (x, 0), 0))
926 < FIRST_PSEUDO_REGISTER)
927 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
928 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
931 /* Make a new stack slot. Then indicate that something
932 changed so we go back and recompute offsets for
933 eliminable registers because the allocation of memory
934 below might change some offset. reg_equiv_{mem,address}
935 will be set up for this pseudo on the next pass around
937 reg_equiv_memory_loc[i] = 0;
938 reg_equiv_init[i] = 0;
943 if (caller_save_needed)
946 /* If we allocated another stack slot, redo elimination bookkeeping. */
947 if (starting_frame_size != get_frame_size ())
950 if (caller_save_needed)
952 save_call_clobbered_regs ();
953 /* That might have allocated new insn_chain structures. */
954 reload_firstobj = obstack_alloc (&reload_obstack, 0);
957 calculate_needs_all_insns (global);
959 CLEAR_REG_SET (&spilled_pseudos);
962 something_changed = 0;
964 /* If we allocated any new memory locations, make another pass
965 since it might have changed elimination offsets. */
966 if (starting_frame_size != get_frame_size ())
967 something_changed = 1;
970 HARD_REG_SET to_spill;
971 CLEAR_HARD_REG_SET (to_spill);
972 update_eliminables (&to_spill);
973 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
974 if (TEST_HARD_REG_BIT (to_spill, i))
976 spill_hard_reg (i, 1);
979 /* Regardless of the state of spills, if we previously had
980 a register that we thought we could eliminate, but now can
981 not eliminate, we must run another pass.
983 Consider pseudos which have an entry in reg_equiv_* which
984 reference an eliminable register. We must make another pass
985 to update reg_equiv_* so that we do not substitute in the
986 old value from when we thought the elimination could be
988 something_changed = 1;
992 select_reload_regs ();
996 if (insns_need_reload != 0 || did_spill)
997 something_changed |= finish_spills (global);
999 if (! something_changed)
1002 if (caller_save_needed)
1003 delete_caller_save_insns ();
1005 obstack_free (&reload_obstack, reload_firstobj);
1008 /* If global-alloc was run, notify it of any register eliminations we have
1011 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1012 if (ep->can_eliminate)
1013 mark_elimination (ep->from, ep->to);
1015 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1016 If that insn didn't set the register (i.e., it copied the register to
1017 memory), just delete that insn instead of the equivalencing insn plus
1018 anything now dead. If we call delete_dead_insn on that insn, we may
1019 delete the insn that actually sets the register if the register dies
1020 there and that is incorrect. */
1022 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1024 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1027 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1029 rtx equiv_insn = XEXP (list, 0);
1031 /* If we already deleted the insn or if it may trap, we can't
1032 delete it. The latter case shouldn't happen, but can
1033 if an insn has a variable address, gets a REG_EH_REGION
1034 note added to it, and then gets converted into an load
1035 from a constant address. */
1036 if (GET_CODE (equiv_insn) == NOTE
1037 || can_throw_internal (equiv_insn))
1039 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1040 delete_dead_insn (equiv_insn);
1043 PUT_CODE (equiv_insn, NOTE);
1044 NOTE_SOURCE_FILE (equiv_insn) = 0;
1045 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1051 /* Use the reload registers where necessary
1052 by generating move instructions to move the must-be-register
1053 values into or out of the reload registers. */
1055 if (insns_need_reload != 0 || something_needs_elimination
1056 || something_needs_operands_changed)
1058 HOST_WIDE_INT old_frame_size = get_frame_size ();
1060 reload_as_needed (global);
1062 if (old_frame_size != get_frame_size ())
1066 verify_initial_elim_offsets ();
1069 /* If we were able to eliminate the frame pointer, show that it is no
1070 longer live at the start of any basic block. If it ls live by
1071 virtue of being in a pseudo, that pseudo will be marked live
1072 and hence the frame pointer will be known to be live via that
1075 if (! frame_pointer_needed)
1077 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1078 HARD_FRAME_POINTER_REGNUM);
1080 /* Come here (with failure set nonzero) if we can't get enough spill regs
1081 and we decide not to abort about it. */
1084 CLEAR_REG_SET (&spilled_pseudos);
1085 reload_in_progress = 0;
1087 /* Now eliminate all pseudo regs by modifying them into
1088 their equivalent memory references.
1089 The REG-rtx's for the pseudos are modified in place,
1090 so all insns that used to refer to them now refer to memory.
1092 For a reg that has a reg_equiv_address, all those insns
1093 were changed by reloading so that no insns refer to it any longer;
1094 but the DECL_RTL of a variable decl may refer to it,
1095 and if so this causes the debugging info to mention the variable. */
1097 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1101 if (reg_equiv_mem[i])
1102 addr = XEXP (reg_equiv_mem[i], 0);
1104 if (reg_equiv_address[i])
1105 addr = reg_equiv_address[i];
1109 if (reg_renumber[i] < 0)
1111 rtx reg = regno_reg_rtx[i];
1113 REG_USERVAR_P (reg) = 0;
1114 PUT_CODE (reg, MEM);
1115 XEXP (reg, 0) = addr;
1116 if (reg_equiv_memory_loc[i])
1117 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1120 RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg)
1121 = MEM_SCALAR_P (reg) = 0;
1122 MEM_ATTRS (reg) = 0;
1125 else if (reg_equiv_mem[i])
1126 XEXP (reg_equiv_mem[i], 0) = addr;
1130 /* We must set reload_completed now since the cleanup_subreg_operands call
1131 below will re-recognize each insn and reload may have generated insns
1132 which are only valid during and after reload. */
1133 reload_completed = 1;
1135 /* Make a pass over all the insns and delete all USEs which we inserted
1136 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1137 notes. Delete all CLOBBER insns, except those that refer to the return
1138 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1139 from misarranging variable-array code, and simplify (subreg (reg))
1140 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1141 are no longer useful or accurate. Strip and regenerate REG_INC notes
1142 that may have been moved around. */
1144 for (insn = first; insn; insn = NEXT_INSN (insn))
1149 if (GET_CODE (insn) == CALL_INSN)
1150 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1151 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1153 if ((GET_CODE (PATTERN (insn)) == USE
1154 /* We mark with QImode USEs introduced by reload itself. */
1155 && (GET_MODE (insn) == QImode
1156 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1157 || (GET_CODE (PATTERN (insn)) == CLOBBER
1158 && (GET_CODE (XEXP (PATTERN (insn), 0)) != MEM
1159 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1160 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1161 && XEXP (XEXP (PATTERN (insn), 0), 0)
1162 != stack_pointer_rtx))
1163 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1164 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1170 /* Some CLOBBERs may survive until here and still reference unassigned
1171 pseudos with const equivalent, which may in turn cause ICE in later
1172 passes if the reference remains in place. */
1173 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1174 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1175 VOIDmode, PATTERN (insn));
1177 pnote = ®_NOTES (insn);
1180 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1181 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1182 || REG_NOTE_KIND (*pnote) == REG_INC
1183 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1184 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1185 *pnote = XEXP (*pnote, 1);
1187 pnote = &XEXP (*pnote, 1);
1191 add_auto_inc_notes (insn, PATTERN (insn));
1194 /* And simplify (subreg (reg)) if it appears as an operand. */
1195 cleanup_subreg_operands (insn);
1198 /* If we are doing stack checking, give a warning if this function's
1199 frame size is larger than we expect. */
1200 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1202 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1203 static int verbose_warned = 0;
1205 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1206 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1207 size += UNITS_PER_WORD;
1209 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1211 warning ("frame size too large for reliable stack checking");
1212 if (! verbose_warned)
1214 warning ("try reducing the number of local variables");
1220 /* Indicate that we no longer have known memory locations or constants. */
1221 if (reg_equiv_constant)
1222 free (reg_equiv_constant);
1223 reg_equiv_constant = 0;
1224 if (reg_equiv_memory_loc)
1225 free (reg_equiv_memory_loc);
1226 reg_equiv_memory_loc = 0;
1228 if (offsets_known_at)
1229 free (offsets_known_at);
1233 free (reg_equiv_mem);
1234 free (reg_equiv_init);
1235 free (reg_equiv_address);
1236 free (reg_max_ref_width);
1237 free (reg_old_renumber);
1238 free (pseudo_previous_regs);
1239 free (pseudo_forbidden_regs);
1241 CLEAR_HARD_REG_SET (used_spill_regs);
1242 for (i = 0; i < n_spills; i++)
1243 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1245 /* Free all the insn_chain structures at once. */
1246 obstack_free (&reload_obstack, reload_startobj);
1247 unused_insn_chains = 0;
1248 fixup_abnormal_edges ();
1250 /* Replacing pseudos with their memory equivalents might have
1251 created shared rtx. Subsequent passes would get confused
1252 by this, so unshare everything here. */
1253 unshare_all_rtl_again (first);
1255 #ifdef STACK_BOUNDARY
1256 /* init_emit has set the alignment of the hard frame pointer
1257 to STACK_BOUNDARY. It is very likely no longer valid if
1258 the hard frame pointer was used for register allocation. */
1259 if (!frame_pointer_needed)
1260 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1266 /* Yet another special case. Unfortunately, reg-stack forces people to
1267 write incorrect clobbers in asm statements. These clobbers must not
1268 cause the register to appear in bad_spill_regs, otherwise we'll call
1269 fatal_insn later. We clear the corresponding regnos in the live
1270 register sets to avoid this.
1271 The whole thing is rather sick, I'm afraid. */
1274 maybe_fix_stack_asms (void)
1277 const char *constraints[MAX_RECOG_OPERANDS];
1278 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1279 struct insn_chain *chain;
1281 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1284 HARD_REG_SET clobbered, allowed;
1287 if (! INSN_P (chain->insn)
1288 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1290 pat = PATTERN (chain->insn);
1291 if (GET_CODE (pat) != PARALLEL)
1294 CLEAR_HARD_REG_SET (clobbered);
1295 CLEAR_HARD_REG_SET (allowed);
1297 /* First, make a mask of all stack regs that are clobbered. */
1298 for (i = 0; i < XVECLEN (pat, 0); i++)
1300 rtx t = XVECEXP (pat, 0, i);
1301 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1302 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1305 /* Get the operand values and constraints out of the insn. */
1306 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1307 constraints, operand_mode);
1309 /* For every operand, see what registers are allowed. */
1310 for (i = 0; i < noperands; i++)
1312 const char *p = constraints[i];
1313 /* For every alternative, we compute the class of registers allowed
1314 for reloading in CLS, and merge its contents into the reg set
1316 int cls = (int) NO_REGS;
1322 if (c == '\0' || c == ',' || c == '#')
1324 /* End of one alternative - mark the regs in the current
1325 class, and reset the class. */
1326 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1332 } while (c != '\0' && c != ',');
1340 case '=': case '+': case '*': case '%': case '?': case '!':
1341 case '0': case '1': case '2': case '3': case '4': case 'm':
1342 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1343 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1344 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1349 cls = (int) reg_class_subunion[cls]
1350 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1355 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1359 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1360 cls = (int) reg_class_subunion[cls]
1361 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1363 cls = (int) reg_class_subunion[cls]
1364 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1366 p += CONSTRAINT_LEN (c, p);
1369 /* Those of the registers which are clobbered, but allowed by the
1370 constraints, must be usable as reload registers. So clear them
1371 out of the life information. */
1372 AND_HARD_REG_SET (allowed, clobbered);
1373 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1374 if (TEST_HARD_REG_BIT (allowed, i))
1376 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1377 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1384 /* Copy the global variables n_reloads and rld into the corresponding elts
1387 copy_reloads (struct insn_chain *chain)
1389 chain->n_reloads = n_reloads;
1390 chain->rld = obstack_alloc (&reload_obstack,
1391 n_reloads * sizeof (struct reload));
1392 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1393 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1396 /* Walk the chain of insns, and determine for each whether it needs reloads
1397 and/or eliminations. Build the corresponding insns_need_reload list, and
1398 set something_needs_elimination as appropriate. */
1400 calculate_needs_all_insns (int global)
1402 struct insn_chain **pprev_reload = &insns_need_reload;
1403 struct insn_chain *chain, *next = 0;
1405 something_needs_elimination = 0;
1407 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1408 for (chain = reload_insn_chain; chain != 0; chain = next)
1410 rtx insn = chain->insn;
1414 /* Clear out the shortcuts. */
1415 chain->n_reloads = 0;
1416 chain->need_elim = 0;
1417 chain->need_reload = 0;
1418 chain->need_operand_change = 0;
1420 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1421 include REG_LABEL), we need to see what effects this has on the
1422 known offsets at labels. */
1424 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1425 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1426 set_label_offsets (insn, insn, 0);
1430 rtx old_body = PATTERN (insn);
1431 int old_code = INSN_CODE (insn);
1432 rtx old_notes = REG_NOTES (insn);
1433 int did_elimination = 0;
1434 int operands_changed = 0;
1435 rtx set = single_set (insn);
1437 /* Skip insns that only set an equivalence. */
1438 if (set && GET_CODE (SET_DEST (set)) == REG
1439 && reg_renumber[REGNO (SET_DEST (set))] < 0
1440 && reg_equiv_constant[REGNO (SET_DEST (set))])
1443 /* If needed, eliminate any eliminable registers. */
1444 if (num_eliminable || num_eliminable_invariants)
1445 did_elimination = eliminate_regs_in_insn (insn, 0);
1447 /* Analyze the instruction. */
1448 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1449 global, spill_reg_order);
1451 /* If a no-op set needs more than one reload, this is likely
1452 to be something that needs input address reloads. We
1453 can't get rid of this cleanly later, and it is of no use
1454 anyway, so discard it now.
1455 We only do this when expensive_optimizations is enabled,
1456 since this complements reload inheritance / output
1457 reload deletion, and it can make debugging harder. */
1458 if (flag_expensive_optimizations && n_reloads > 1)
1460 rtx set = single_set (insn);
1462 && SET_SRC (set) == SET_DEST (set)
1463 && GET_CODE (SET_SRC (set)) == REG
1464 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1467 /* Delete it from the reload chain. */
1469 chain->prev->next = next;
1471 reload_insn_chain = next;
1473 next->prev = chain->prev;
1474 chain->next = unused_insn_chains;
1475 unused_insn_chains = chain;
1480 update_eliminable_offsets ();
1482 /* Remember for later shortcuts which insns had any reloads or
1483 register eliminations. */
1484 chain->need_elim = did_elimination;
1485 chain->need_reload = n_reloads > 0;
1486 chain->need_operand_change = operands_changed;
1488 /* Discard any register replacements done. */
1489 if (did_elimination)
1491 obstack_free (&reload_obstack, reload_insn_firstobj);
1492 PATTERN (insn) = old_body;
1493 INSN_CODE (insn) = old_code;
1494 REG_NOTES (insn) = old_notes;
1495 something_needs_elimination = 1;
1498 something_needs_operands_changed |= operands_changed;
1502 copy_reloads (chain);
1503 *pprev_reload = chain;
1504 pprev_reload = &chain->next_need_reload;
1511 /* Comparison function for qsort to decide which of two reloads
1512 should be handled first. *P1 and *P2 are the reload numbers. */
1515 reload_reg_class_lower (const void *r1p, const void *r2p)
1517 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1520 /* Consider required reloads before optional ones. */
1521 t = rld[r1].optional - rld[r2].optional;
1525 /* Count all solitary classes before non-solitary ones. */
1526 t = ((reg_class_size[(int) rld[r2].class] == 1)
1527 - (reg_class_size[(int) rld[r1].class] == 1));
1531 /* Aside from solitaires, consider all multi-reg groups first. */
1532 t = rld[r2].nregs - rld[r1].nregs;
1536 /* Consider reloads in order of increasing reg-class number. */
1537 t = (int) rld[r1].class - (int) rld[r2].class;
1541 /* If reloads are equally urgent, sort by reload number,
1542 so that the results of qsort leave nothing to chance. */
1546 /* The cost of spilling each hard reg. */
1547 static int spill_cost[FIRST_PSEUDO_REGISTER];
1549 /* When spilling multiple hard registers, we use SPILL_COST for the first
1550 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1551 only the first hard reg for a multi-reg pseudo. */
1552 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1554 /* Update the spill cost arrays, considering that pseudo REG is live. */
1557 count_pseudo (int reg)
1559 int freq = REG_FREQ (reg);
1560 int r = reg_renumber[reg];
1563 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1564 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1567 SET_REGNO_REG_SET (&pseudos_counted, reg);
1572 spill_add_cost[r] += freq;
1574 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1576 spill_cost[r + nregs] += freq;
1579 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1580 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1583 order_regs_for_reload (struct insn_chain *chain)
1586 HARD_REG_SET used_by_pseudos;
1587 HARD_REG_SET used_by_pseudos2;
1589 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1591 memset (spill_cost, 0, sizeof spill_cost);
1592 memset (spill_add_cost, 0, sizeof spill_add_cost);
1594 /* Count number of uses of each hard reg by pseudo regs allocated to it
1595 and then order them by decreasing use. First exclude hard registers
1596 that are live in or across this insn. */
1598 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1599 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1600 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1601 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1603 /* Now find out which pseudos are allocated to it, and update
1605 CLEAR_REG_SET (&pseudos_counted);
1607 EXECUTE_IF_SET_IN_REG_SET
1608 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1612 EXECUTE_IF_SET_IN_REG_SET
1613 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1617 CLEAR_REG_SET (&pseudos_counted);
1620 /* Vector of reload-numbers showing the order in which the reloads should
1622 static short reload_order[MAX_RELOADS];
1624 /* This is used to keep track of the spill regs used in one insn. */
1625 static HARD_REG_SET used_spill_regs_local;
1627 /* We decided to spill hard register SPILLED, which has a size of
1628 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1629 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1630 update SPILL_COST/SPILL_ADD_COST. */
1633 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1635 int r = reg_renumber[reg];
1636 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1638 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1639 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1642 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1644 spill_add_cost[r] -= REG_FREQ (reg);
1646 spill_cost[r + nregs] -= REG_FREQ (reg);
1649 /* Find reload register to use for reload number ORDER. */
1652 find_reg (struct insn_chain *chain, int order)
1654 int rnum = reload_order[order];
1655 struct reload *rl = rld + rnum;
1656 int best_cost = INT_MAX;
1660 HARD_REG_SET not_usable;
1661 HARD_REG_SET used_by_other_reload;
1663 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1664 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1665 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1667 CLEAR_HARD_REG_SET (used_by_other_reload);
1668 for (k = 0; k < order; k++)
1670 int other = reload_order[k];
1672 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1673 for (j = 0; j < rld[other].nregs; j++)
1674 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1677 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1679 unsigned int regno = i;
1681 if (! TEST_HARD_REG_BIT (not_usable, regno)
1682 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1683 && HARD_REGNO_MODE_OK (regno, rl->mode))
1685 int this_cost = spill_cost[regno];
1687 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1689 for (j = 1; j < this_nregs; j++)
1691 this_cost += spill_add_cost[regno + j];
1692 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1693 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1698 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1700 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1702 if (this_cost < best_cost
1703 /* Among registers with equal cost, prefer caller-saved ones, or
1704 use REG_ALLOC_ORDER if it is defined. */
1705 || (this_cost == best_cost
1706 #ifdef REG_ALLOC_ORDER
1707 && (inv_reg_alloc_order[regno]
1708 < inv_reg_alloc_order[best_reg])
1710 && call_used_regs[regno]
1711 && ! call_used_regs[best_reg]
1716 best_cost = this_cost;
1724 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1726 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1727 rl->regno = best_reg;
1729 EXECUTE_IF_SET_IN_REG_SET
1730 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1732 count_spilled_pseudo (best_reg, rl->nregs, j);
1735 EXECUTE_IF_SET_IN_REG_SET
1736 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1738 count_spilled_pseudo (best_reg, rl->nregs, j);
1741 for (i = 0; i < rl->nregs; i++)
1743 if (spill_cost[best_reg + i] != 0
1744 || spill_add_cost[best_reg + i] != 0)
1746 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1751 /* Find more reload regs to satisfy the remaining need of an insn, which
1753 Do it by ascending class number, since otherwise a reg
1754 might be spilled for a big class and might fail to count
1755 for a smaller class even though it belongs to that class. */
1758 find_reload_regs (struct insn_chain *chain)
1762 /* In order to be certain of getting the registers we need,
1763 we must sort the reloads into order of increasing register class.
1764 Then our grabbing of reload registers will parallel the process
1765 that provided the reload registers. */
1766 for (i = 0; i < chain->n_reloads; i++)
1768 /* Show whether this reload already has a hard reg. */
1769 if (chain->rld[i].reg_rtx)
1771 int regno = REGNO (chain->rld[i].reg_rtx);
1772 chain->rld[i].regno = regno;
1774 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1777 chain->rld[i].regno = -1;
1778 reload_order[i] = i;
1781 n_reloads = chain->n_reloads;
1782 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1784 CLEAR_HARD_REG_SET (used_spill_regs_local);
1787 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1789 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1791 /* Compute the order of preference for hard registers to spill. */
1793 order_regs_for_reload (chain);
1795 for (i = 0; i < n_reloads; i++)
1797 int r = reload_order[i];
1799 /* Ignore reloads that got marked inoperative. */
1800 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1801 && ! rld[r].optional
1802 && rld[r].regno == -1)
1803 if (! find_reg (chain, i))
1805 spill_failure (chain->insn, rld[r].class);
1811 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1812 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1814 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1818 select_reload_regs (void)
1820 struct insn_chain *chain;
1822 /* Try to satisfy the needs for each insn. */
1823 for (chain = insns_need_reload; chain != 0;
1824 chain = chain->next_need_reload)
1825 find_reload_regs (chain);
1828 /* Delete all insns that were inserted by emit_caller_save_insns during
1831 delete_caller_save_insns (void)
1833 struct insn_chain *c = reload_insn_chain;
1837 while (c != 0 && c->is_caller_save_insn)
1839 struct insn_chain *next = c->next;
1842 if (c == reload_insn_chain)
1843 reload_insn_chain = next;
1847 next->prev = c->prev;
1849 c->prev->next = next;
1850 c->next = unused_insn_chains;
1851 unused_insn_chains = c;
1859 /* Handle the failure to find a register to spill.
1860 INSN should be one of the insns which needed this particular spill reg. */
1863 spill_failure (rtx insn, enum reg_class class)
1865 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1866 if (asm_noperands (PATTERN (insn)) >= 0)
1867 error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'",
1868 reg_class_names[class]);
1871 error ("unable to find a register to spill in class `%s'",
1872 reg_class_names[class]);
1873 fatal_insn ("this is the insn:", insn);
1877 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1878 data that is dead in INSN. */
1881 delete_dead_insn (rtx insn)
1883 rtx prev = prev_real_insn (insn);
1886 /* If the previous insn sets a register that dies in our insn, delete it
1888 if (prev && GET_CODE (PATTERN (prev)) == SET
1889 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1890 && reg_mentioned_p (prev_dest, PATTERN (insn))
1891 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1892 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1893 delete_dead_insn (prev);
1895 PUT_CODE (insn, NOTE);
1896 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1897 NOTE_SOURCE_FILE (insn) = 0;
1900 /* Modify the home of pseudo-reg I.
1901 The new home is present in reg_renumber[I].
1903 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1904 or it may be -1, meaning there is none or it is not relevant.
1905 This is used so that all pseudos spilled from a given hard reg
1906 can share one stack slot. */
1909 alter_reg (int i, int from_reg)
1911 /* When outputting an inline function, this can happen
1912 for a reg that isn't actually used. */
1913 if (regno_reg_rtx[i] == 0)
1916 /* If the reg got changed to a MEM at rtl-generation time,
1918 if (GET_CODE (regno_reg_rtx[i]) != REG)
1921 /* Modify the reg-rtx to contain the new hard reg
1922 number or else to contain its pseudo reg number. */
1923 REGNO (regno_reg_rtx[i])
1924 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1926 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1927 allocate a stack slot for it. */
1929 if (reg_renumber[i] < 0
1930 && REG_N_REFS (i) > 0
1931 && reg_equiv_constant[i] == 0
1932 && reg_equiv_memory_loc[i] == 0)
1935 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1936 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1939 /* Each pseudo reg has an inherent size which comes from its own mode,
1940 and a total size which provides room for paradoxical subregs
1941 which refer to the pseudo reg in wider modes.
1943 We can use a slot already allocated if it provides both
1944 enough inherent space and enough total space.
1945 Otherwise, we allocate a new slot, making sure that it has no less
1946 inherent space, and no less total space, then the previous slot. */
1949 /* No known place to spill from => no slot to reuse. */
1950 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1951 inherent_size == total_size ? 0 : -1);
1952 if (BYTES_BIG_ENDIAN)
1953 /* Cancel the big-endian correction done in assign_stack_local.
1954 Get the address of the beginning of the slot.
1955 This is so we can do a big-endian correction unconditionally
1957 adjust = inherent_size - total_size;
1959 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1961 /* Nothing can alias this slot except this pseudo. */
1962 set_mem_alias_set (x, new_alias_set ());
1965 /* Reuse a stack slot if possible. */
1966 else if (spill_stack_slot[from_reg] != 0
1967 && spill_stack_slot_width[from_reg] >= total_size
1968 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1970 x = spill_stack_slot[from_reg];
1972 /* Allocate a bigger slot. */
1975 /* Compute maximum size needed, both for inherent size
1976 and for total size. */
1977 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1980 if (spill_stack_slot[from_reg])
1982 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1984 mode = GET_MODE (spill_stack_slot[from_reg]);
1985 if (spill_stack_slot_width[from_reg] > total_size)
1986 total_size = spill_stack_slot_width[from_reg];
1989 /* Make a slot with that size. */
1990 x = assign_stack_local (mode, total_size,
1991 inherent_size == total_size ? 0 : -1);
1994 /* All pseudos mapped to this slot can alias each other. */
1995 if (spill_stack_slot[from_reg])
1996 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
1998 set_mem_alias_set (x, new_alias_set ());
2000 if (BYTES_BIG_ENDIAN)
2002 /* Cancel the big-endian correction done in assign_stack_local.
2003 Get the address of the beginning of the slot.
2004 This is so we can do a big-endian correction unconditionally
2006 adjust = GET_MODE_SIZE (mode) - total_size;
2009 = adjust_address_nv (x, mode_for_size (total_size
2015 spill_stack_slot[from_reg] = stack_slot;
2016 spill_stack_slot_width[from_reg] = total_size;
2019 /* On a big endian machine, the "address" of the slot
2020 is the address of the low part that fits its inherent mode. */
2021 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2022 adjust += (total_size - inherent_size);
2024 /* If we have any adjustment to make, or if the stack slot is the
2025 wrong mode, make a new stack slot. */
2026 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2028 /* If we have a decl for the original register, set it for the
2029 memory. If this is a shared MEM, make a copy. */
2030 if (REG_EXPR (regno_reg_rtx[i])
2031 && TREE_CODE_CLASS (TREE_CODE (REG_EXPR (regno_reg_rtx[i]))) == 'd')
2033 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2035 /* We can do this only for the DECLs home pseudo, not for
2036 any copies of it, since otherwise when the stack slot
2037 is reused, nonoverlapping_memrefs_p might think they
2039 if (decl && GET_CODE (decl) == REG && REGNO (decl) == (unsigned) i)
2041 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2044 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2048 /* Save the stack slot for later. */
2049 reg_equiv_memory_loc[i] = x;
2053 /* Mark the slots in regs_ever_live for the hard regs
2054 used by pseudo-reg number REGNO. */
2057 mark_home_live (int regno)
2061 i = reg_renumber[regno];
2064 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2066 regs_ever_live[i++] = 1;
2069 /* This function handles the tracking of elimination offsets around branches.
2071 X is a piece of RTL being scanned.
2073 INSN is the insn that it came from, if any.
2075 INITIAL_P is nonzero if we are to set the offset to be the initial
2076 offset and zero if we are setting the offset of the label to be the
2080 set_label_offsets (rtx x, rtx insn, int initial_p)
2082 enum rtx_code code = GET_CODE (x);
2085 struct elim_table *p;
2090 if (LABEL_REF_NONLOCAL_P (x))
2095 /* ... fall through ... */
2098 /* If we know nothing about this label, set the desired offsets. Note
2099 that this sets the offset at a label to be the offset before a label
2100 if we don't know anything about the label. This is not correct for
2101 the label after a BARRIER, but is the best guess we can make. If
2102 we guessed wrong, we will suppress an elimination that might have
2103 been possible had we been able to guess correctly. */
2105 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2107 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2108 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2109 = (initial_p ? reg_eliminate[i].initial_offset
2110 : reg_eliminate[i].offset);
2111 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2114 /* Otherwise, if this is the definition of a label and it is
2115 preceded by a BARRIER, set our offsets to the known offset of
2119 && (tem = prev_nonnote_insn (insn)) != 0
2120 && GET_CODE (tem) == BARRIER)
2121 set_offsets_for_label (insn);
2123 /* If neither of the above cases is true, compare each offset
2124 with those previously recorded and suppress any eliminations
2125 where the offsets disagree. */
2127 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2128 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2129 != (initial_p ? reg_eliminate[i].initial_offset
2130 : reg_eliminate[i].offset))
2131 reg_eliminate[i].can_eliminate = 0;
2136 set_label_offsets (PATTERN (insn), insn, initial_p);
2138 /* ... fall through ... */
2142 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2143 and hence must have all eliminations at their initial offsets. */
2144 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2145 if (REG_NOTE_KIND (tem) == REG_LABEL)
2146 set_label_offsets (XEXP (tem, 0), insn, 1);
2152 /* Each of the labels in the parallel or address vector must be
2153 at their initial offsets. We want the first field for PARALLEL
2154 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2156 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2157 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2162 /* We only care about setting PC. If the source is not RETURN,
2163 IF_THEN_ELSE, or a label, disable any eliminations not at
2164 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2165 isn't one of those possibilities. For branches to a label,
2166 call ourselves recursively.
2168 Note that this can disable elimination unnecessarily when we have
2169 a non-local goto since it will look like a non-constant jump to
2170 someplace in the current function. This isn't a significant
2171 problem since such jumps will normally be when all elimination
2172 pairs are back to their initial offsets. */
2174 if (SET_DEST (x) != pc_rtx)
2177 switch (GET_CODE (SET_SRC (x)))
2184 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2188 tem = XEXP (SET_SRC (x), 1);
2189 if (GET_CODE (tem) == LABEL_REF)
2190 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2191 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2194 tem = XEXP (SET_SRC (x), 2);
2195 if (GET_CODE (tem) == LABEL_REF)
2196 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2197 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2205 /* If we reach here, all eliminations must be at their initial
2206 offset because we are doing a jump to a variable address. */
2207 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2208 if (p->offset != p->initial_offset)
2209 p->can_eliminate = 0;
2217 /* Scan X and replace any eliminable registers (such as fp) with a
2218 replacement (such as sp), plus an offset.
2220 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2221 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2222 MEM, we are allowed to replace a sum of a register and the constant zero
2223 with the register, which we cannot do outside a MEM. In addition, we need
2224 to record the fact that a register is referenced outside a MEM.
2226 If INSN is an insn, it is the insn containing X. If we replace a REG
2227 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2228 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2229 the REG is being modified.
2231 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2232 That's used when we eliminate in expressions stored in notes.
2233 This means, do not set ref_outside_mem even if the reference
2236 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2237 replacements done assuming all offsets are at their initial values. If
2238 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2239 encounter, return the actual location so that find_reloads will do
2240 the proper thing. */
2243 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2245 enum rtx_code code = GET_CODE (x);
2246 struct elim_table *ep;
2253 if (! current_function_decl)
2273 /* This is only for the benefit of the debugging backends, which call
2274 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2275 removed after CSE. */
2276 new = eliminate_regs (XEXP (x, 0), 0, insn);
2277 if (GET_CODE (new) == MEM)
2278 return XEXP (new, 0);
2284 /* First handle the case where we encounter a bare register that
2285 is eliminable. Replace it with a PLUS. */
2286 if (regno < FIRST_PSEUDO_REGISTER)
2288 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2290 if (ep->from_rtx == x && ep->can_eliminate)
2291 return plus_constant (ep->to_rtx, ep->previous_offset);
2294 else if (reg_renumber && reg_renumber[regno] < 0
2295 && reg_equiv_constant && reg_equiv_constant[regno]
2296 && ! CONSTANT_P (reg_equiv_constant[regno]))
2297 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2301 /* You might think handling MINUS in a manner similar to PLUS is a
2302 good idea. It is not. It has been tried multiple times and every
2303 time the change has had to have been reverted.
2305 Other parts of reload know a PLUS is special (gen_reload for example)
2306 and require special code to handle code a reloaded PLUS operand.
2308 Also consider backends where the flags register is clobbered by a
2309 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2310 lea instruction comes to mind). If we try to reload a MINUS, we
2311 may kill the flags register that was holding a useful value.
2313 So, please before trying to handle MINUS, consider reload as a
2314 whole instead of this little section as well as the backend issues. */
2316 /* If this is the sum of an eliminable register and a constant, rework
2318 if (GET_CODE (XEXP (x, 0)) == REG
2319 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2320 && CONSTANT_P (XEXP (x, 1)))
2322 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2324 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2326 /* The only time we want to replace a PLUS with a REG (this
2327 occurs when the constant operand of the PLUS is the negative
2328 of the offset) is when we are inside a MEM. We won't want
2329 to do so at other times because that would change the
2330 structure of the insn in a way that reload can't handle.
2331 We special-case the commonest situation in
2332 eliminate_regs_in_insn, so just replace a PLUS with a
2333 PLUS here, unless inside a MEM. */
2334 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2335 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2338 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2339 plus_constant (XEXP (x, 1),
2340 ep->previous_offset));
2343 /* If the register is not eliminable, we are done since the other
2344 operand is a constant. */
2348 /* If this is part of an address, we want to bring any constant to the
2349 outermost PLUS. We will do this by doing register replacement in
2350 our operands and seeing if a constant shows up in one of them.
2352 Note that there is no risk of modifying the structure of the insn,
2353 since we only get called for its operands, thus we are either
2354 modifying the address inside a MEM, or something like an address
2355 operand of a load-address insn. */
2358 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2359 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2361 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2363 /* If one side is a PLUS and the other side is a pseudo that
2364 didn't get a hard register but has a reg_equiv_constant,
2365 we must replace the constant here since it may no longer
2366 be in the position of any operand. */
2367 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2368 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2369 && reg_renumber[REGNO (new1)] < 0
2370 && reg_equiv_constant != 0
2371 && reg_equiv_constant[REGNO (new1)] != 0)
2372 new1 = reg_equiv_constant[REGNO (new1)];
2373 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2374 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2375 && reg_renumber[REGNO (new0)] < 0
2376 && reg_equiv_constant[REGNO (new0)] != 0)
2377 new0 = reg_equiv_constant[REGNO (new0)];
2379 new = form_sum (new0, new1);
2381 /* As above, if we are not inside a MEM we do not want to
2382 turn a PLUS into something else. We might try to do so here
2383 for an addition of 0 if we aren't optimizing. */
2384 if (! mem_mode && GET_CODE (new) != PLUS)
2385 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2393 /* If this is the product of an eliminable register and a
2394 constant, apply the distribute law and move the constant out
2395 so that we have (plus (mult ..) ..). This is needed in order
2396 to keep load-address insns valid. This case is pathological.
2397 We ignore the possibility of overflow here. */
2398 if (GET_CODE (XEXP (x, 0)) == REG
2399 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2400 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2401 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2403 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2406 /* Refs inside notes don't count for this purpose. */
2407 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2408 || GET_CODE (insn) == INSN_LIST)))
2409 ep->ref_outside_mem = 1;
2412 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2413 ep->previous_offset * INTVAL (XEXP (x, 1)));
2416 /* ... fall through ... */
2420 /* See comments before PLUS about handling MINUS. */
2422 case DIV: case UDIV:
2423 case MOD: case UMOD:
2424 case AND: case IOR: case XOR:
2425 case ROTATERT: case ROTATE:
2426 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2428 case GE: case GT: case GEU: case GTU:
2429 case LE: case LT: case LEU: case LTU:
2431 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2433 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2435 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2436 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2441 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2444 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2445 if (new != XEXP (x, 0))
2447 /* If this is a REG_DEAD note, it is not valid anymore.
2448 Using the eliminated version could result in creating a
2449 REG_DEAD note for the stack or frame pointer. */
2450 if (GET_MODE (x) == REG_DEAD)
2452 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2455 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2459 /* ... fall through ... */
2462 /* Now do eliminations in the rest of the chain. If this was
2463 an EXPR_LIST, this might result in allocating more memory than is
2464 strictly needed, but it simplifies the code. */
2467 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2468 if (new != XEXP (x, 1))
2470 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2478 case STRICT_LOW_PART:
2480 case SIGN_EXTEND: case ZERO_EXTEND:
2481 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2482 case FLOAT: case FIX:
2483 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2491 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2492 if (new != XEXP (x, 0))
2493 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2497 /* Similar to above processing, but preserve SUBREG_BYTE.
2498 Convert (subreg (mem)) to (mem) if not paradoxical.
2499 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2500 pseudo didn't get a hard reg, we must replace this with the
2501 eliminated version of the memory location because push_reload
2502 may do the replacement in certain circumstances. */
2503 if (GET_CODE (SUBREG_REG (x)) == REG
2504 && (GET_MODE_SIZE (GET_MODE (x))
2505 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2506 && reg_equiv_memory_loc != 0
2507 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2509 new = SUBREG_REG (x);
2512 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2514 if (new != SUBREG_REG (x))
2516 int x_size = GET_MODE_SIZE (GET_MODE (x));
2517 int new_size = GET_MODE_SIZE (GET_MODE (new));
2519 if (GET_CODE (new) == MEM
2520 && ((x_size < new_size
2521 #ifdef WORD_REGISTER_OPERATIONS
2522 /* On these machines, combine can create rtl of the form
2523 (set (subreg:m1 (reg:m2 R) 0) ...)
2524 where m1 < m2, and expects something interesting to
2525 happen to the entire word. Moreover, it will use the
2526 (reg:m2 R) later, expecting all bits to be preserved.
2527 So if the number of words is the same, preserve the
2528 subreg so that push_reload can see it. */
2529 && ! ((x_size - 1) / UNITS_PER_WORD
2530 == (new_size -1 ) / UNITS_PER_WORD)
2533 || x_size == new_size)
2535 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2537 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2543 /* This is only for the benefit of the debugging backends, which call
2544 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2545 removed after CSE. */
2546 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2547 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2549 /* Our only special processing is to pass the mode of the MEM to our
2550 recursive call and copy the flags. While we are here, handle this
2551 case more efficiently. */
2553 replace_equiv_address_nv (x,
2554 eliminate_regs (XEXP (x, 0),
2555 GET_MODE (x), insn));
2558 /* Handle insn_list USE that a call to a pure function may generate. */
2559 new = eliminate_regs (XEXP (x, 0), 0, insn);
2560 if (new != XEXP (x, 0))
2561 return gen_rtx_USE (GET_MODE (x), new);
2573 /* Process each of our operands recursively. If any have changed, make a
2575 fmt = GET_RTX_FORMAT (code);
2576 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2580 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2581 if (new != XEXP (x, i) && ! copied)
2583 rtx new_x = rtx_alloc (code);
2584 memcpy (new_x, x, RTX_SIZE (code));
2590 else if (*fmt == 'E')
2593 for (j = 0; j < XVECLEN (x, i); j++)
2595 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2596 if (new != XVECEXP (x, i, j) && ! copied_vec)
2598 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2602 rtx new_x = rtx_alloc (code);
2603 memcpy (new_x, x, RTX_SIZE (code));
2607 XVEC (x, i) = new_v;
2610 XVECEXP (x, i, j) = new;
2618 /* Scan rtx X for modifications of elimination target registers. Update
2619 the table of eliminables to reflect the changed state. MEM_MODE is
2620 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2623 elimination_effects (rtx x, enum machine_mode mem_mode)
2625 enum rtx_code code = GET_CODE (x);
2626 struct elim_table *ep;
2653 /* First handle the case where we encounter a bare register that
2654 is eliminable. Replace it with a PLUS. */
2655 if (regno < FIRST_PSEUDO_REGISTER)
2657 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2659 if (ep->from_rtx == x && ep->can_eliminate)
2662 ep->ref_outside_mem = 1;
2667 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2668 && reg_equiv_constant[regno]
2669 && ! function_invariant_p (reg_equiv_constant[regno]))
2670 elimination_effects (reg_equiv_constant[regno], mem_mode);
2679 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2680 if (ep->to_rtx == XEXP (x, 0))
2682 int size = GET_MODE_SIZE (mem_mode);
2684 /* If more bytes than MEM_MODE are pushed, account for them. */
2685 #ifdef PUSH_ROUNDING
2686 if (ep->to_rtx == stack_pointer_rtx)
2687 size = PUSH_ROUNDING (size);
2689 if (code == PRE_DEC || code == POST_DEC)
2691 else if (code == PRE_INC || code == POST_INC)
2693 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2694 && GET_CODE (XEXP (x, 1)) == PLUS
2695 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2696 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2697 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2700 /* These two aren't unary operators. */
2701 if (code == POST_MODIFY || code == PRE_MODIFY)
2704 /* Fall through to generic unary operation case. */
2705 case STRICT_LOW_PART:
2707 case SIGN_EXTEND: case ZERO_EXTEND:
2708 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2709 case FLOAT: case FIX:
2710 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2718 elimination_effects (XEXP (x, 0), mem_mode);
2722 if (GET_CODE (SUBREG_REG (x)) == REG
2723 && (GET_MODE_SIZE (GET_MODE (x))
2724 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2725 && reg_equiv_memory_loc != 0
2726 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2729 elimination_effects (SUBREG_REG (x), mem_mode);
2733 /* If using a register that is the source of an eliminate we still
2734 think can be performed, note it cannot be performed since we don't
2735 know how this register is used. */
2736 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2737 if (ep->from_rtx == XEXP (x, 0))
2738 ep->can_eliminate = 0;
2740 elimination_effects (XEXP (x, 0), mem_mode);
2744 /* If clobbering a register that is the replacement register for an
2745 elimination we still think can be performed, note that it cannot
2746 be performed. Otherwise, we need not be concerned about it. */
2747 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2748 if (ep->to_rtx == XEXP (x, 0))
2749 ep->can_eliminate = 0;
2751 elimination_effects (XEXP (x, 0), mem_mode);
2755 /* Check for setting a register that we know about. */
2756 if (GET_CODE (SET_DEST (x)) == REG)
2758 /* See if this is setting the replacement register for an
2761 If DEST is the hard frame pointer, we do nothing because we
2762 assume that all assignments to the frame pointer are for
2763 non-local gotos and are being done at a time when they are valid
2764 and do not disturb anything else. Some machines want to
2765 eliminate a fake argument pointer (or even a fake frame pointer)
2766 with either the real frame or the stack pointer. Assignments to
2767 the hard frame pointer must not prevent this elimination. */
2769 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2771 if (ep->to_rtx == SET_DEST (x)
2772 && SET_DEST (x) != hard_frame_pointer_rtx)
2774 /* If it is being incremented, adjust the offset. Otherwise,
2775 this elimination can't be done. */
2776 rtx src = SET_SRC (x);
2778 if (GET_CODE (src) == PLUS
2779 && XEXP (src, 0) == SET_DEST (x)
2780 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2781 ep->offset -= INTVAL (XEXP (src, 1));
2783 ep->can_eliminate = 0;
2787 elimination_effects (SET_DEST (x), 0);
2788 elimination_effects (SET_SRC (x), 0);
2792 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2795 /* Our only special processing is to pass the mode of the MEM to our
2797 elimination_effects (XEXP (x, 0), GET_MODE (x));
2804 fmt = GET_RTX_FORMAT (code);
2805 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2808 elimination_effects (XEXP (x, i), mem_mode);
2809 else if (*fmt == 'E')
2810 for (j = 0; j < XVECLEN (x, i); j++)
2811 elimination_effects (XVECEXP (x, i, j), mem_mode);
2815 /* Descend through rtx X and verify that no references to eliminable registers
2816 remain. If any do remain, mark the involved register as not
2820 check_eliminable_occurrences (rtx x)
2829 code = GET_CODE (x);
2831 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2833 struct elim_table *ep;
2835 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2836 if (ep->from_rtx == x)
2837 ep->can_eliminate = 0;
2841 fmt = GET_RTX_FORMAT (code);
2842 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2845 check_eliminable_occurrences (XEXP (x, i));
2846 else if (*fmt == 'E')
2849 for (j = 0; j < XVECLEN (x, i); j++)
2850 check_eliminable_occurrences (XVECEXP (x, i, j));
2855 /* Scan INSN and eliminate all eliminable registers in it.
2857 If REPLACE is nonzero, do the replacement destructively. Also
2858 delete the insn as dead it if it is setting an eliminable register.
2860 If REPLACE is zero, do all our allocations in reload_obstack.
2862 If no eliminations were done and this insn doesn't require any elimination
2863 processing (these are not identical conditions: it might be updating sp,
2864 but not referencing fp; this needs to be seen during reload_as_needed so
2865 that the offset between fp and sp can be taken into consideration), zero
2866 is returned. Otherwise, 1 is returned. */
2869 eliminate_regs_in_insn (rtx insn, int replace)
2871 int icode = recog_memoized (insn);
2872 rtx old_body = PATTERN (insn);
2873 int insn_is_asm = asm_noperands (old_body) >= 0;
2874 rtx old_set = single_set (insn);
2878 rtx substed_operand[MAX_RECOG_OPERANDS];
2879 rtx orig_operand[MAX_RECOG_OPERANDS];
2880 struct elim_table *ep;
2883 if (! insn_is_asm && icode < 0)
2885 if (GET_CODE (PATTERN (insn)) == USE
2886 || GET_CODE (PATTERN (insn)) == CLOBBER
2887 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2888 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2889 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2894 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2895 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2897 /* Check for setting an eliminable register. */
2898 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2899 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2901 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2902 /* If this is setting the frame pointer register to the
2903 hardware frame pointer register and this is an elimination
2904 that will be done (tested above), this insn is really
2905 adjusting the frame pointer downward to compensate for
2906 the adjustment done before a nonlocal goto. */
2907 if (ep->from == FRAME_POINTER_REGNUM
2908 && ep->to == HARD_FRAME_POINTER_REGNUM)
2910 rtx base = SET_SRC (old_set);
2911 rtx base_insn = insn;
2912 HOST_WIDE_INT offset = 0;
2914 while (base != ep->to_rtx)
2916 rtx prev_insn, prev_set;
2918 if (GET_CODE (base) == PLUS
2919 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2921 offset += INTVAL (XEXP (base, 1));
2922 base = XEXP (base, 0);
2924 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2925 && (prev_set = single_set (prev_insn)) != 0
2926 && rtx_equal_p (SET_DEST (prev_set), base))
2928 base = SET_SRC (prev_set);
2929 base_insn = prev_insn;
2935 if (base == ep->to_rtx)
2938 = plus_constant (ep->to_rtx, offset - ep->offset);
2940 new_body = old_body;
2943 new_body = copy_insn (old_body);
2944 if (REG_NOTES (insn))
2945 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2947 PATTERN (insn) = new_body;
2948 old_set = single_set (insn);
2950 /* First see if this insn remains valid when we
2951 make the change. If not, keep the INSN_CODE
2952 the same and let reload fit it up. */
2953 validate_change (insn, &SET_SRC (old_set), src, 1);
2954 validate_change (insn, &SET_DEST (old_set),
2956 if (! apply_change_group ())
2958 SET_SRC (old_set) = src;
2959 SET_DEST (old_set) = ep->to_rtx;
2968 /* In this case this insn isn't serving a useful purpose. We
2969 will delete it in reload_as_needed once we know that this
2970 elimination is, in fact, being done.
2972 If REPLACE isn't set, we can't delete this insn, but needn't
2973 process it since it won't be used unless something changes. */
2976 delete_dead_insn (insn);
2984 /* We allow one special case which happens to work on all machines we
2985 currently support: a single set with the source or a REG_EQUAL
2986 note being a PLUS of an eliminable register and a constant. */
2988 if (old_set && GET_CODE (SET_DEST (old_set)) == REG)
2990 /* First see if the source is of the form (plus (reg) CST). */
2991 if (GET_CODE (SET_SRC (old_set)) == PLUS
2992 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
2993 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
2994 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
2995 plus_src = SET_SRC (old_set);
2996 else if (GET_CODE (SET_SRC (old_set)) == REG)
2998 /* Otherwise, see if we have a REG_EQUAL note of the form
2999 (plus (reg) CST). */
3001 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3003 if (REG_NOTE_KIND (links) == REG_EQUAL
3004 && GET_CODE (XEXP (links, 0)) == PLUS
3005 && GET_CODE (XEXP (XEXP (links, 0), 0)) == REG
3006 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT
3007 && REGNO (XEXP (XEXP (links, 0), 0)) < FIRST_PSEUDO_REGISTER)
3009 plus_src = XEXP (links, 0);
3017 rtx reg = XEXP (plus_src, 0);
3018 HOST_WIDE_INT offset = INTVAL (XEXP (plus_src, 1));
3020 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3021 if (ep->from_rtx == reg && ep->can_eliminate)
3023 offset += ep->offset;
3028 /* We assume here that if we need a PARALLEL with
3029 CLOBBERs for this assignment, we can do with the
3030 MATCH_SCRATCHes that add_clobbers allocates.
3031 There's not much we can do if that doesn't work. */
3032 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3036 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3039 rtvec vec = rtvec_alloc (num_clobbers + 1);
3041 vec->elem[0] = PATTERN (insn);
3042 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3043 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3045 if (INSN_CODE (insn) < 0)
3048 /* If we have a nonzero offset, and the source is already
3049 a simple REG, the following transformation would
3050 increase the cost of the insn by replacing a simple REG
3051 with (plus (reg sp) CST). So try only when plus_src
3052 comes from old_set proper, not REG_NOTES. */
3053 else if (SET_SRC (old_set) == plus_src)
3055 new_body = old_body;
3058 new_body = copy_insn (old_body);
3059 if (REG_NOTES (insn))
3060 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3062 PATTERN (insn) = new_body;
3063 old_set = single_set (insn);
3065 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3066 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3072 /* This can't have an effect on elimination offsets, so skip right
3078 /* Determine the effects of this insn on elimination offsets. */
3079 elimination_effects (old_body, 0);
3081 /* Eliminate all eliminable registers occurring in operands that
3082 can be handled by reload. */
3083 extract_insn (insn);
3084 for (i = 0; i < recog_data.n_operands; i++)
3086 orig_operand[i] = recog_data.operand[i];
3087 substed_operand[i] = recog_data.operand[i];
3089 /* For an asm statement, every operand is eliminable. */
3090 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3092 /* Check for setting a register that we know about. */
3093 if (recog_data.operand_type[i] != OP_IN
3094 && GET_CODE (orig_operand[i]) == REG)
3096 /* If we are assigning to a register that can be eliminated, it
3097 must be as part of a PARALLEL, since the code above handles
3098 single SETs. We must indicate that we can no longer
3099 eliminate this reg. */
3100 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3102 if (ep->from_rtx == orig_operand[i])
3103 ep->can_eliminate = 0;
3106 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3107 replace ? insn : NULL_RTX);
3108 if (substed_operand[i] != orig_operand[i])
3110 /* Terminate the search in check_eliminable_occurrences at
3112 *recog_data.operand_loc[i] = 0;
3114 /* If an output operand changed from a REG to a MEM and INSN is an
3115 insn, write a CLOBBER insn. */
3116 if (recog_data.operand_type[i] != OP_IN
3117 && GET_CODE (orig_operand[i]) == REG
3118 && GET_CODE (substed_operand[i]) == MEM
3120 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3125 for (i = 0; i < recog_data.n_dups; i++)
3126 *recog_data.dup_loc[i]
3127 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3129 /* If any eliminable remain, they aren't eliminable anymore. */
3130 check_eliminable_occurrences (old_body);
3132 /* Substitute the operands; the new values are in the substed_operand
3134 for (i = 0; i < recog_data.n_operands; i++)
3135 *recog_data.operand_loc[i] = substed_operand[i];
3136 for (i = 0; i < recog_data.n_dups; i++)
3137 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3139 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3140 re-recognize the insn. We do this in case we had a simple addition
3141 but now can do this as a load-address. This saves an insn in this
3143 If re-recognition fails, the old insn code number will still be used,
3144 and some register operands may have changed into PLUS expressions.
3145 These will be handled by find_reloads by loading them into a register
3150 /* If we aren't replacing things permanently and we changed something,
3151 make another copy to ensure that all the RTL is new. Otherwise
3152 things can go wrong if find_reload swaps commutative operands
3153 and one is inside RTL that has been copied while the other is not. */
3154 new_body = old_body;
3157 new_body = copy_insn (old_body);
3158 if (REG_NOTES (insn))
3159 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3161 PATTERN (insn) = new_body;
3163 /* If we had a move insn but now we don't, rerecognize it. This will
3164 cause spurious re-recognition if the old move had a PARALLEL since
3165 the new one still will, but we can't call single_set without
3166 having put NEW_BODY into the insn and the re-recognition won't
3167 hurt in this rare case. */
3168 /* ??? Why this huge if statement - why don't we just rerecognize the
3172 && ((GET_CODE (SET_SRC (old_set)) == REG
3173 && (GET_CODE (new_body) != SET
3174 || GET_CODE (SET_SRC (new_body)) != REG))
3175 /* If this was a load from or store to memory, compare
3176 the MEM in recog_data.operand to the one in the insn.
3177 If they are not equal, then rerecognize the insn. */
3179 && ((GET_CODE (SET_SRC (old_set)) == MEM
3180 && SET_SRC (old_set) != recog_data.operand[1])
3181 || (GET_CODE (SET_DEST (old_set)) == MEM
3182 && SET_DEST (old_set) != recog_data.operand[0])))
3183 /* If this was an add insn before, rerecognize. */
3184 || GET_CODE (SET_SRC (old_set)) == PLUS))
3186 int new_icode = recog (PATTERN (insn), insn, 0);
3188 INSN_CODE (insn) = icode;
3192 /* Restore the old body. If there were any changes to it, we made a copy
3193 of it while the changes were still in place, so we'll correctly return
3194 a modified insn below. */
3197 /* Restore the old body. */
3198 for (i = 0; i < recog_data.n_operands; i++)
3199 *recog_data.operand_loc[i] = orig_operand[i];
3200 for (i = 0; i < recog_data.n_dups; i++)
3201 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3204 /* Update all elimination pairs to reflect the status after the current
3205 insn. The changes we make were determined by the earlier call to
3206 elimination_effects.
3208 We also detect cases where register elimination cannot be done,
3209 namely, if a register would be both changed and referenced outside a MEM
3210 in the resulting insn since such an insn is often undefined and, even if
3211 not, we cannot know what meaning will be given to it. Note that it is
3212 valid to have a register used in an address in an insn that changes it
3213 (presumably with a pre- or post-increment or decrement).
3215 If anything changes, return nonzero. */
3217 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3219 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3220 ep->can_eliminate = 0;
3222 ep->ref_outside_mem = 0;
3224 if (ep->previous_offset != ep->offset)
3229 /* If we changed something, perform elimination in REG_NOTES. This is
3230 needed even when REPLACE is zero because a REG_DEAD note might refer
3231 to a register that we eliminate and could cause a different number
3232 of spill registers to be needed in the final reload pass than in
3234 if (val && REG_NOTES (insn) != 0)
3235 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3240 /* Loop through all elimination pairs.
3241 Recalculate the number not at initial offset.
3243 Compute the maximum offset (minimum offset if the stack does not
3244 grow downward) for each elimination pair. */
3247 update_eliminable_offsets (void)
3249 struct elim_table *ep;
3251 num_not_at_initial_offset = 0;
3252 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3254 ep->previous_offset = ep->offset;
3255 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3256 num_not_at_initial_offset++;
3260 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3261 replacement we currently believe is valid, mark it as not eliminable if X
3262 modifies DEST in any way other than by adding a constant integer to it.
3264 If DEST is the frame pointer, we do nothing because we assume that
3265 all assignments to the hard frame pointer are nonlocal gotos and are being
3266 done at a time when they are valid and do not disturb anything else.
3267 Some machines want to eliminate a fake argument pointer with either the
3268 frame or stack pointer. Assignments to the hard frame pointer must not
3269 prevent this elimination.
3271 Called via note_stores from reload before starting its passes to scan
3272 the insns of the function. */
3275 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3279 /* A SUBREG of a hard register here is just changing its mode. We should
3280 not see a SUBREG of an eliminable hard register, but check just in
3282 if (GET_CODE (dest) == SUBREG)
3283 dest = SUBREG_REG (dest);
3285 if (dest == hard_frame_pointer_rtx)
3288 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3289 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3290 && (GET_CODE (x) != SET
3291 || GET_CODE (SET_SRC (x)) != PLUS
3292 || XEXP (SET_SRC (x), 0) != dest
3293 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3295 reg_eliminate[i].can_eliminate_previous
3296 = reg_eliminate[i].can_eliminate = 0;
3301 /* Verify that the initial elimination offsets did not change since the
3302 last call to set_initial_elim_offsets. This is used to catch cases
3303 where something illegal happened during reload_as_needed that could
3304 cause incorrect code to be generated if we did not check for it. */
3307 verify_initial_elim_offsets (void)
3311 #ifdef ELIMINABLE_REGS
3312 struct elim_table *ep;
3314 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3316 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3317 if (t != ep->initial_offset)
3321 INITIAL_FRAME_POINTER_OFFSET (t);
3322 if (t != reg_eliminate[0].initial_offset)
3327 /* Reset all offsets on eliminable registers to their initial values. */
3330 set_initial_elim_offsets (void)
3332 struct elim_table *ep = reg_eliminate;
3334 #ifdef ELIMINABLE_REGS
3335 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3337 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3338 ep->previous_offset = ep->offset = ep->initial_offset;
3341 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3342 ep->previous_offset = ep->offset = ep->initial_offset;
3345 num_not_at_initial_offset = 0;
3348 /* Initialize the known label offsets.
3349 Set a known offset for each forced label to be at the initial offset
3350 of each elimination. We do this because we assume that all
3351 computed jumps occur from a location where each elimination is
3352 at its initial offset.
3353 For all other labels, show that we don't know the offsets. */
3356 set_initial_label_offsets (void)
3359 memset (offsets_known_at, 0, num_labels);
3361 for (x = forced_labels; x; x = XEXP (x, 1))
3363 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3366 /* Set all elimination offsets to the known values for the code label given
3370 set_offsets_for_label (rtx insn)
3373 int label_nr = CODE_LABEL_NUMBER (insn);
3374 struct elim_table *ep;
3376 num_not_at_initial_offset = 0;
3377 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3379 ep->offset = ep->previous_offset
3380 = offsets_at[label_nr - first_label_num][i];
3381 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3382 num_not_at_initial_offset++;
3386 /* See if anything that happened changes which eliminations are valid.
3387 For example, on the SPARC, whether or not the frame pointer can
3388 be eliminated can depend on what registers have been used. We need
3389 not check some conditions again (such as flag_omit_frame_pointer)
3390 since they can't have changed. */
3393 update_eliminables (HARD_REG_SET *pset)
3395 int previous_frame_pointer_needed = frame_pointer_needed;
3396 struct elim_table *ep;
3398 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3399 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3400 #ifdef ELIMINABLE_REGS
3401 || ! CAN_ELIMINATE (ep->from, ep->to)
3404 ep->can_eliminate = 0;
3406 /* Look for the case where we have discovered that we can't replace
3407 register A with register B and that means that we will now be
3408 trying to replace register A with register C. This means we can
3409 no longer replace register C with register B and we need to disable
3410 such an elimination, if it exists. This occurs often with A == ap,
3411 B == sp, and C == fp. */
3413 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3415 struct elim_table *op;
3418 if (! ep->can_eliminate && ep->can_eliminate_previous)
3420 /* Find the current elimination for ep->from, if there is a
3422 for (op = reg_eliminate;
3423 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3424 if (op->from == ep->from && op->can_eliminate)
3430 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3432 for (op = reg_eliminate;
3433 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3434 if (op->from == new_to && op->to == ep->to)
3435 op->can_eliminate = 0;
3439 /* See if any registers that we thought we could eliminate the previous
3440 time are no longer eliminable. If so, something has changed and we
3441 must spill the register. Also, recompute the number of eliminable
3442 registers and see if the frame pointer is needed; it is if there is
3443 no elimination of the frame pointer that we can perform. */
3445 frame_pointer_needed = 1;
3446 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3448 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3449 && ep->to != HARD_FRAME_POINTER_REGNUM)
3450 frame_pointer_needed = 0;
3452 if (! ep->can_eliminate && ep->can_eliminate_previous)
3454 ep->can_eliminate_previous = 0;
3455 SET_HARD_REG_BIT (*pset, ep->from);
3460 /* If we didn't need a frame pointer last time, but we do now, spill
3461 the hard frame pointer. */
3462 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3463 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3466 /* Initialize the table of registers to eliminate. */
3469 init_elim_table (void)
3471 struct elim_table *ep;
3472 #ifdef ELIMINABLE_REGS
3473 const struct elim_table_1 *ep1;
3477 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3479 /* Does this function require a frame pointer? */
3481 frame_pointer_needed = (! flag_omit_frame_pointer
3482 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3483 and restore sp for alloca. So we can't eliminate
3484 the frame pointer in that case. At some point,
3485 we should improve this by emitting the
3486 sp-adjusting insns for this case. */
3487 || (current_function_calls_alloca
3488 && EXIT_IGNORE_STACK)
3489 || FRAME_POINTER_REQUIRED);
3493 #ifdef ELIMINABLE_REGS
3494 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3495 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3497 ep->from = ep1->from;
3499 ep->can_eliminate = ep->can_eliminate_previous
3500 = (CAN_ELIMINATE (ep->from, ep->to)
3501 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3504 reg_eliminate[0].from = reg_eliminate_1[0].from;
3505 reg_eliminate[0].to = reg_eliminate_1[0].to;
3506 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3507 = ! frame_pointer_needed;
3510 /* Count the number of eliminable registers and build the FROM and TO
3511 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3512 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3513 We depend on this. */
3514 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3516 num_eliminable += ep->can_eliminate;
3517 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3518 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3522 /* Kick all pseudos out of hard register REGNO.
3524 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3525 because we found we can't eliminate some register. In the case, no pseudos
3526 are allowed to be in the register, even if they are only in a block that
3527 doesn't require spill registers, unlike the case when we are spilling this
3528 hard reg to produce another spill register.
3530 Return nonzero if any pseudos needed to be kicked out. */
3533 spill_hard_reg (unsigned int regno, int cant_eliminate)
3539 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3540 regs_ever_live[regno] = 1;
3543 /* Spill every pseudo reg that was allocated to this reg
3544 or to something that overlaps this reg. */
3546 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3547 if (reg_renumber[i] >= 0
3548 && (unsigned int) reg_renumber[i] <= regno
3549 && ((unsigned int) reg_renumber[i]
3550 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3551 [PSEUDO_REGNO_MODE (i)]
3553 SET_REGNO_REG_SET (&spilled_pseudos, i);
3556 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3557 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3560 ior_hard_reg_set (HARD_REG_SET *set1, HARD_REG_SET *set2)
3562 IOR_HARD_REG_SET (*set1, *set2);
3565 /* After find_reload_regs has been run for all insn that need reloads,
3566 and/or spill_hard_regs was called, this function is used to actually
3567 spill pseudo registers and try to reallocate them. It also sets up the
3568 spill_regs array for use by choose_reload_regs. */
3571 finish_spills (int global)
3573 struct insn_chain *chain;
3574 int something_changed = 0;
3577 /* Build the spill_regs array for the function. */
3578 /* If there are some registers still to eliminate and one of the spill regs
3579 wasn't ever used before, additional stack space may have to be
3580 allocated to store this register. Thus, we may have changed the offset
3581 between the stack and frame pointers, so mark that something has changed.
3583 One might think that we need only set VAL to 1 if this is a call-used
3584 register. However, the set of registers that must be saved by the
3585 prologue is not identical to the call-used set. For example, the
3586 register used by the call insn for the return PC is a call-used register,
3587 but must be saved by the prologue. */
3590 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3591 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3593 spill_reg_order[i] = n_spills;
3594 spill_regs[n_spills++] = i;
3595 if (num_eliminable && ! regs_ever_live[i])
3596 something_changed = 1;
3597 regs_ever_live[i] = 1;
3600 spill_reg_order[i] = -1;
3602 EXECUTE_IF_SET_IN_REG_SET
3603 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3605 /* Record the current hard register the pseudo is allocated to in
3606 pseudo_previous_regs so we avoid reallocating it to the same
3607 hard reg in a later pass. */
3608 if (reg_renumber[i] < 0)
3611 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3612 /* Mark it as no longer having a hard register home. */
3613 reg_renumber[i] = -1;
3614 /* We will need to scan everything again. */
3615 something_changed = 1;
3618 /* Retry global register allocation if possible. */
3621 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3622 /* For every insn that needs reloads, set the registers used as spill
3623 regs in pseudo_forbidden_regs for every pseudo live across the
3625 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3627 EXECUTE_IF_SET_IN_REG_SET
3628 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3630 ior_hard_reg_set (pseudo_forbidden_regs + i,
3631 &chain->used_spill_regs);
3633 EXECUTE_IF_SET_IN_REG_SET
3634 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3636 ior_hard_reg_set (pseudo_forbidden_regs + i,
3637 &chain->used_spill_regs);
3641 /* Retry allocating the spilled pseudos. For each reg, merge the
3642 various reg sets that indicate which hard regs can't be used,
3643 and call retry_global_alloc.
3644 We change spill_pseudos here to only contain pseudos that did not
3645 get a new hard register. */
3646 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3647 if (reg_old_renumber[i] != reg_renumber[i])
3649 HARD_REG_SET forbidden;
3650 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3651 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3652 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3653 retry_global_alloc (i, forbidden);
3654 if (reg_renumber[i] >= 0)
3655 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3659 /* Fix up the register information in the insn chain.
3660 This involves deleting those of the spilled pseudos which did not get
3661 a new hard register home from the live_{before,after} sets. */
3662 for (chain = reload_insn_chain; chain; chain = chain->next)
3664 HARD_REG_SET used_by_pseudos;
3665 HARD_REG_SET used_by_pseudos2;
3667 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3668 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3670 /* Mark any unallocated hard regs as available for spills. That
3671 makes inheritance work somewhat better. */
3672 if (chain->need_reload)
3674 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3675 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3676 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3678 /* Save the old value for the sanity test below. */
3679 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3681 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3682 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3683 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3684 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3686 /* Make sure we only enlarge the set. */
3687 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3693 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3694 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3696 int regno = reg_renumber[i];
3697 if (reg_old_renumber[i] == regno)
3700 alter_reg (i, reg_old_renumber[i]);
3701 reg_old_renumber[i] = regno;
3705 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3707 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3708 i, reg_renumber[i]);
3712 return something_changed;
3715 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3718 scan_paradoxical_subregs (rtx x)
3722 enum rtx_code code = GET_CODE (x);
3732 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3740 if (GET_CODE (SUBREG_REG (x)) == REG
3741 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3742 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3743 = GET_MODE_SIZE (GET_MODE (x));
3750 fmt = GET_RTX_FORMAT (code);
3751 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3754 scan_paradoxical_subregs (XEXP (x, i));
3755 else if (fmt[i] == 'E')
3758 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3759 scan_paradoxical_subregs (XVECEXP (x, i, j));
3764 /* Reload pseudo-registers into hard regs around each insn as needed.
3765 Additional register load insns are output before the insn that needs it
3766 and perhaps store insns after insns that modify the reloaded pseudo reg.
3768 reg_last_reload_reg and reg_reloaded_contents keep track of
3769 which registers are already available in reload registers.
3770 We update these for the reloads that we perform,
3771 as the insns are scanned. */
3774 reload_as_needed (int live_known)
3776 struct insn_chain *chain;
3777 #if defined (AUTO_INC_DEC)
3782 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3783 memset (spill_reg_store, 0, sizeof spill_reg_store);
3784 reg_last_reload_reg = xcalloc (max_regno, sizeof (rtx));
3785 reg_has_output_reload = xmalloc (max_regno);
3786 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3787 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3789 set_initial_elim_offsets ();
3791 for (chain = reload_insn_chain; chain; chain = chain->next)
3794 rtx insn = chain->insn;
3795 rtx old_next = NEXT_INSN (insn);
3797 /* If we pass a label, copy the offsets from the label information
3798 into the current offsets of each elimination. */
3799 if (GET_CODE (insn) == CODE_LABEL)
3800 set_offsets_for_label (insn);
3802 else if (INSN_P (insn))
3804 rtx oldpat = copy_rtx (PATTERN (insn));
3806 /* If this is a USE and CLOBBER of a MEM, ensure that any
3807 references to eliminable registers have been removed. */
3809 if ((GET_CODE (PATTERN (insn)) == USE
3810 || GET_CODE (PATTERN (insn)) == CLOBBER)
3811 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3812 XEXP (XEXP (PATTERN (insn), 0), 0)
3813 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3814 GET_MODE (XEXP (PATTERN (insn), 0)),
3817 /* If we need to do register elimination processing, do so.
3818 This might delete the insn, in which case we are done. */
3819 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3821 eliminate_regs_in_insn (insn, 1);
3822 if (GET_CODE (insn) == NOTE)
3824 update_eliminable_offsets ();
3829 /* If need_elim is nonzero but need_reload is zero, one might think
3830 that we could simply set n_reloads to 0. However, find_reloads
3831 could have done some manipulation of the insn (such as swapping
3832 commutative operands), and these manipulations are lost during
3833 the first pass for every insn that needs register elimination.
3834 So the actions of find_reloads must be redone here. */
3836 if (! chain->need_elim && ! chain->need_reload
3837 && ! chain->need_operand_change)
3839 /* First find the pseudo regs that must be reloaded for this insn.
3840 This info is returned in the tables reload_... (see reload.h).
3841 Also modify the body of INSN by substituting RELOAD
3842 rtx's for those pseudo regs. */
3845 memset (reg_has_output_reload, 0, max_regno);
3846 CLEAR_HARD_REG_SET (reg_is_output_reload);
3848 find_reloads (insn, 1, spill_indirect_levels, live_known,
3854 rtx next = NEXT_INSN (insn);
3857 prev = PREV_INSN (insn);
3859 /* Now compute which reload regs to reload them into. Perhaps
3860 reusing reload regs from previous insns, or else output
3861 load insns to reload them. Maybe output store insns too.
3862 Record the choices of reload reg in reload_reg_rtx. */
3863 choose_reload_regs (chain);
3865 /* Merge any reloads that we didn't combine for fear of
3866 increasing the number of spill registers needed but now
3867 discover can be safely merged. */
3868 if (SMALL_REGISTER_CLASSES)
3869 merge_assigned_reloads (insn);
3871 /* Generate the insns to reload operands into or out of
3872 their reload regs. */
3873 emit_reload_insns (chain);
3875 /* Substitute the chosen reload regs from reload_reg_rtx
3876 into the insn's body (or perhaps into the bodies of other
3877 load and store insn that we just made for reloading
3878 and that we moved the structure into). */
3879 subst_reloads (insn);
3881 /* If this was an ASM, make sure that all the reload insns
3882 we have generated are valid. If not, give an error
3885 if (asm_noperands (PATTERN (insn)) >= 0)
3886 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3887 if (p != insn && INSN_P (p)
3888 && GET_CODE (PATTERN (p)) != USE
3889 && (recog_memoized (p) < 0
3890 || (extract_insn (p), ! constrain_operands (1))))
3892 error_for_asm (insn,
3893 "`asm' operand requires impossible reload");
3898 if (num_eliminable && chain->need_elim)
3899 update_eliminable_offsets ();
3901 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3902 is no longer validly lying around to save a future reload.
3903 Note that this does not detect pseudos that were reloaded
3904 for this insn in order to be stored in
3905 (obeying register constraints). That is correct; such reload
3906 registers ARE still valid. */
3907 note_stores (oldpat, forget_old_reloads_1, NULL);
3909 /* There may have been CLOBBER insns placed after INSN. So scan
3910 between INSN and NEXT and use them to forget old reloads. */
3911 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3912 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3913 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3916 /* Likewise for regs altered by auto-increment in this insn.
3917 REG_INC notes have been changed by reloading:
3918 find_reloads_address_1 records substitutions for them,
3919 which have been performed by subst_reloads above. */
3920 for (i = n_reloads - 1; i >= 0; i--)
3922 rtx in_reg = rld[i].in_reg;
3925 enum rtx_code code = GET_CODE (in_reg);
3926 /* PRE_INC / PRE_DEC will have the reload register ending up
3927 with the same value as the stack slot, but that doesn't
3928 hold true for POST_INC / POST_DEC. Either we have to
3929 convert the memory access to a true POST_INC / POST_DEC,
3930 or we can't use the reload register for inheritance. */
3931 if ((code == POST_INC || code == POST_DEC)
3932 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3933 REGNO (rld[i].reg_rtx))
3934 /* Make sure it is the inc/dec pseudo, and not
3935 some other (e.g. output operand) pseudo. */
3936 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3937 == REGNO (XEXP (in_reg, 0))))
3940 rtx reload_reg = rld[i].reg_rtx;
3941 enum machine_mode mode = GET_MODE (reload_reg);
3945 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3947 /* We really want to ignore REG_INC notes here, so
3948 use PATTERN (p) as argument to reg_set_p . */
3949 if (reg_set_p (reload_reg, PATTERN (p)))
3951 n = count_occurrences (PATTERN (p), reload_reg, 0);
3956 n = validate_replace_rtx (reload_reg,
3957 gen_rtx_fmt_e (code,
3962 /* We must also verify that the constraints
3963 are met after the replacement. */
3966 n = constrain_operands (1);
3970 /* If the constraints were not met, then
3971 undo the replacement. */
3974 validate_replace_rtx (gen_rtx_fmt_e (code,
3987 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3989 /* Mark this as having an output reload so that the
3990 REG_INC processing code below won't invalidate
3991 the reload for inheritance. */
3992 SET_HARD_REG_BIT (reg_is_output_reload,
3993 REGNO (reload_reg));
3994 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3997 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4000 else if ((code == PRE_INC || code == PRE_DEC)
4001 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4002 REGNO (rld[i].reg_rtx))
4003 /* Make sure it is the inc/dec pseudo, and not
4004 some other (e.g. output operand) pseudo. */
4005 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4006 == REGNO (XEXP (in_reg, 0))))
4008 SET_HARD_REG_BIT (reg_is_output_reload,
4009 REGNO (rld[i].reg_rtx));
4010 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4014 /* If a pseudo that got a hard register is auto-incremented,
4015 we must purge records of copying it into pseudos without
4017 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4018 if (REG_NOTE_KIND (x) == REG_INC)
4020 /* See if this pseudo reg was reloaded in this insn.
4021 If so, its last-reload info is still valid
4022 because it is based on this insn's reload. */
4023 for (i = 0; i < n_reloads; i++)
4024 if (rld[i].out == XEXP (x, 0))
4028 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4032 /* A reload reg's contents are unknown after a label. */
4033 if (GET_CODE (insn) == CODE_LABEL)
4034 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4036 /* Don't assume a reload reg is still good after a call insn
4037 if it is a call-used reg, or if it contains a value that will
4038 be partially clobbered by the call. */
4039 else if (GET_CODE (insn) == CALL_INSN)
4041 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4042 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4047 free (reg_last_reload_reg);
4048 free (reg_has_output_reload);
4051 /* Discard all record of any value reloaded from X,
4052 or reloaded in X from someplace else;
4053 unless X is an output reload reg of the current insn.
4055 X may be a hard reg (the reload reg)
4056 or it may be a pseudo reg that was reloaded from. */
4059 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4060 void *data ATTRIBUTE_UNUSED)
4065 /* note_stores does give us subregs of hard regs,
4066 subreg_regno_offset will abort if it is not a hard reg. */
4067 while (GET_CODE (x) == SUBREG)
4069 /* We ignore the subreg offset when calculating the regno,
4070 because we are using the entire underlying hard register
4075 if (GET_CODE (x) != REG)
4080 if (regno >= FIRST_PSEUDO_REGISTER)
4086 nr = hard_regno_nregs[regno][GET_MODE (x)];
4087 /* Storing into a spilled-reg invalidates its contents.
4088 This can happen if a block-local pseudo is allocated to that reg
4089 and it wasn't spilled because this block's total need is 0.
4090 Then some insn might have an optional reload and use this reg. */
4091 for (i = 0; i < nr; i++)
4092 /* But don't do this if the reg actually serves as an output
4093 reload reg in the current instruction. */
4095 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4097 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4098 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4099 spill_reg_store[regno + i] = 0;
4103 /* Since value of X has changed,
4104 forget any value previously copied from it. */
4107 /* But don't forget a copy if this is the output reload
4108 that establishes the copy's validity. */
4109 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4110 reg_last_reload_reg[regno + nr] = 0;
4113 /* The following HARD_REG_SETs indicate when each hard register is
4114 used for a reload of various parts of the current insn. */
4116 /* If reg is unavailable for all reloads. */
4117 static HARD_REG_SET reload_reg_unavailable;
4118 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4119 static HARD_REG_SET reload_reg_used;
4120 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4121 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4122 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4123 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4124 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4125 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4126 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4127 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4128 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4129 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4130 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4131 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4132 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4133 static HARD_REG_SET reload_reg_used_in_op_addr;
4134 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4135 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4136 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4137 static HARD_REG_SET reload_reg_used_in_insn;
4138 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4139 static HARD_REG_SET reload_reg_used_in_other_addr;
4141 /* If reg is in use as a reload reg for any sort of reload. */
4142 static HARD_REG_SET reload_reg_used_at_all;
4144 /* If reg is use as an inherited reload. We just mark the first register
4146 static HARD_REG_SET reload_reg_used_for_inherit;
4148 /* Records which hard regs are used in any way, either as explicit use or
4149 by being allocated to a pseudo during any point of the current insn. */
4150 static HARD_REG_SET reg_used_in_insn;
4152 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4153 TYPE. MODE is used to indicate how many consecutive regs are
4157 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4158 enum machine_mode mode)
4160 unsigned int nregs = hard_regno_nregs[regno][mode];
4163 for (i = regno; i < nregs + regno; i++)
4168 SET_HARD_REG_BIT (reload_reg_used, i);
4171 case RELOAD_FOR_INPUT_ADDRESS:
4172 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4175 case RELOAD_FOR_INPADDR_ADDRESS:
4176 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4179 case RELOAD_FOR_OUTPUT_ADDRESS:
4180 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4183 case RELOAD_FOR_OUTADDR_ADDRESS:
4184 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4187 case RELOAD_FOR_OPERAND_ADDRESS:
4188 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4191 case RELOAD_FOR_OPADDR_ADDR:
4192 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4195 case RELOAD_FOR_OTHER_ADDRESS:
4196 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4199 case RELOAD_FOR_INPUT:
4200 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4203 case RELOAD_FOR_OUTPUT:
4204 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4207 case RELOAD_FOR_INSN:
4208 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4212 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4216 /* Similarly, but show REGNO is no longer in use for a reload. */
4219 clear_reload_reg_in_use (unsigned int regno, int opnum,
4220 enum reload_type type, enum machine_mode mode)
4222 unsigned int nregs = hard_regno_nregs[regno][mode];
4223 unsigned int start_regno, end_regno, r;
4225 /* A complication is that for some reload types, inheritance might
4226 allow multiple reloads of the same types to share a reload register.
4227 We set check_opnum if we have to check only reloads with the same
4228 operand number, and check_any if we have to check all reloads. */
4229 int check_opnum = 0;
4231 HARD_REG_SET *used_in_set;
4236 used_in_set = &reload_reg_used;
4239 case RELOAD_FOR_INPUT_ADDRESS:
4240 used_in_set = &reload_reg_used_in_input_addr[opnum];
4243 case RELOAD_FOR_INPADDR_ADDRESS:
4245 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4248 case RELOAD_FOR_OUTPUT_ADDRESS:
4249 used_in_set = &reload_reg_used_in_output_addr[opnum];
4252 case RELOAD_FOR_OUTADDR_ADDRESS:
4254 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4257 case RELOAD_FOR_OPERAND_ADDRESS:
4258 used_in_set = &reload_reg_used_in_op_addr;
4261 case RELOAD_FOR_OPADDR_ADDR:
4263 used_in_set = &reload_reg_used_in_op_addr_reload;
4266 case RELOAD_FOR_OTHER_ADDRESS:
4267 used_in_set = &reload_reg_used_in_other_addr;
4271 case RELOAD_FOR_INPUT:
4272 used_in_set = &reload_reg_used_in_input[opnum];
4275 case RELOAD_FOR_OUTPUT:
4276 used_in_set = &reload_reg_used_in_output[opnum];
4279 case RELOAD_FOR_INSN:
4280 used_in_set = &reload_reg_used_in_insn;
4285 /* We resolve conflicts with remaining reloads of the same type by
4286 excluding the intervals of reload registers by them from the
4287 interval of freed reload registers. Since we only keep track of
4288 one set of interval bounds, we might have to exclude somewhat
4289 more than what would be necessary if we used a HARD_REG_SET here.
4290 But this should only happen very infrequently, so there should
4291 be no reason to worry about it. */
4293 start_regno = regno;
4294 end_regno = regno + nregs;
4295 if (check_opnum || check_any)
4297 for (i = n_reloads - 1; i >= 0; i--)
4299 if (rld[i].when_needed == type
4300 && (check_any || rld[i].opnum == opnum)
4303 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4304 unsigned int conflict_end
4306 + hard_regno_nregs[conflict_start][rld[i].mode]);
4308 /* If there is an overlap with the first to-be-freed register,
4309 adjust the interval start. */
4310 if (conflict_start <= start_regno && conflict_end > start_regno)
4311 start_regno = conflict_end;
4312 /* Otherwise, if there is a conflict with one of the other
4313 to-be-freed registers, adjust the interval end. */
4314 if (conflict_start > start_regno && conflict_start < end_regno)
4315 end_regno = conflict_start;
4320 for (r = start_regno; r < end_regno; r++)
4321 CLEAR_HARD_REG_BIT (*used_in_set, r);
4324 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4325 specified by OPNUM and TYPE. */
4328 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4332 /* In use for a RELOAD_OTHER means it's not available for anything. */
4333 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4334 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4340 /* In use for anything means we can't use it for RELOAD_OTHER. */
4341 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4342 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4343 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4344 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4347 for (i = 0; i < reload_n_operands; i++)
4348 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4349 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4350 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4351 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4352 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4353 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4358 case RELOAD_FOR_INPUT:
4359 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4360 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4363 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4366 /* If it is used for some other input, can't use it. */
4367 for (i = 0; i < reload_n_operands; i++)
4368 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4371 /* If it is used in a later operand's address, can't use it. */
4372 for (i = opnum + 1; i < reload_n_operands; i++)
4373 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4374 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4379 case RELOAD_FOR_INPUT_ADDRESS:
4380 /* Can't use a register if it is used for an input address for this
4381 operand or used as an input in an earlier one. */
4382 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4383 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4386 for (i = 0; i < opnum; i++)
4387 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4392 case RELOAD_FOR_INPADDR_ADDRESS:
4393 /* Can't use a register if it is used for an input address
4394 for this operand or used as an input in an earlier
4396 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4399 for (i = 0; i < opnum; i++)
4400 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4405 case RELOAD_FOR_OUTPUT_ADDRESS:
4406 /* Can't use a register if it is used for an output address for this
4407 operand or used as an output in this or a later operand. Note
4408 that multiple output operands are emitted in reverse order, so
4409 the conflicting ones are those with lower indices. */
4410 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4413 for (i = 0; i <= opnum; i++)
4414 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4419 case RELOAD_FOR_OUTADDR_ADDRESS:
4420 /* Can't use a register if it is used for an output address
4421 for this operand or used as an output in this or a
4422 later operand. Note that multiple output operands are
4423 emitted in reverse order, so the conflicting ones are
4424 those with lower indices. */
4425 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4428 for (i = 0; i <= opnum; i++)
4429 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4434 case RELOAD_FOR_OPERAND_ADDRESS:
4435 for (i = 0; i < reload_n_operands; i++)
4436 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4439 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4440 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4442 case RELOAD_FOR_OPADDR_ADDR:
4443 for (i = 0; i < reload_n_operands; i++)
4444 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4447 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4449 case RELOAD_FOR_OUTPUT:
4450 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4451 outputs, or an operand address for this or an earlier output.
4452 Note that multiple output operands are emitted in reverse order,
4453 so the conflicting ones are those with higher indices. */
4454 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4457 for (i = 0; i < reload_n_operands; i++)
4458 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4461 for (i = opnum; i < reload_n_operands; i++)
4462 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4463 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4468 case RELOAD_FOR_INSN:
4469 for (i = 0; i < reload_n_operands; i++)
4470 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4471 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4474 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4475 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4477 case RELOAD_FOR_OTHER_ADDRESS:
4478 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4483 /* Return 1 if the value in reload reg REGNO, as used by a reload
4484 needed for the part of the insn specified by OPNUM and TYPE,
4485 is still available in REGNO at the end of the insn.
4487 We can assume that the reload reg was already tested for availability
4488 at the time it is needed, and we should not check this again,
4489 in case the reg has already been marked in use. */
4492 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4499 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4500 its value must reach the end. */
4503 /* If this use is for part of the insn,
4504 its value reaches if no subsequent part uses the same register.
4505 Just like the above function, don't try to do this with lots
4508 case RELOAD_FOR_OTHER_ADDRESS:
4509 /* Here we check for everything else, since these don't conflict
4510 with anything else and everything comes later. */
4512 for (i = 0; i < reload_n_operands; i++)
4513 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4514 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4515 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4516 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4517 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4518 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4521 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4522 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4523 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4524 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4526 case RELOAD_FOR_INPUT_ADDRESS:
4527 case RELOAD_FOR_INPADDR_ADDRESS:
4528 /* Similar, except that we check only for this and subsequent inputs
4529 and the address of only subsequent inputs and we do not need
4530 to check for RELOAD_OTHER objects since they are known not to
4533 for (i = opnum; i < reload_n_operands; i++)
4534 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4537 for (i = opnum + 1; i < reload_n_operands; i++)
4538 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4539 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4542 for (i = 0; i < reload_n_operands; i++)
4543 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4544 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4545 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4548 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4551 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4552 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4553 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4555 case RELOAD_FOR_INPUT:
4556 /* Similar to input address, except we start at the next operand for
4557 both input and input address and we do not check for
4558 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4561 for (i = opnum + 1; i < reload_n_operands; i++)
4562 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4563 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4564 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4567 /* ... fall through ... */
4569 case RELOAD_FOR_OPERAND_ADDRESS:
4570 /* Check outputs and their addresses. */
4572 for (i = 0; i < reload_n_operands; i++)
4573 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4574 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4575 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4578 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4580 case RELOAD_FOR_OPADDR_ADDR:
4581 for (i = 0; i < reload_n_operands; i++)
4582 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4583 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4584 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4587 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4588 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4589 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4591 case RELOAD_FOR_INSN:
4592 /* These conflict with other outputs with RELOAD_OTHER. So
4593 we need only check for output addresses. */
4595 opnum = reload_n_operands;
4597 /* ... fall through ... */
4599 case RELOAD_FOR_OUTPUT:
4600 case RELOAD_FOR_OUTPUT_ADDRESS:
4601 case RELOAD_FOR_OUTADDR_ADDRESS:
4602 /* We already know these can't conflict with a later output. So the
4603 only thing to check are later output addresses.
4604 Note that multiple output operands are emitted in reverse order,
4605 so the conflicting ones are those with lower indices. */
4606 for (i = 0; i < opnum; i++)
4607 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4608 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4617 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4620 This function uses the same algorithm as reload_reg_free_p above. */
4623 reloads_conflict (int r1, int r2)
4625 enum reload_type r1_type = rld[r1].when_needed;
4626 enum reload_type r2_type = rld[r2].when_needed;
4627 int r1_opnum = rld[r1].opnum;
4628 int r2_opnum = rld[r2].opnum;
4630 /* RELOAD_OTHER conflicts with everything. */
4631 if (r2_type == RELOAD_OTHER)
4634 /* Otherwise, check conflicts differently for each type. */
4638 case RELOAD_FOR_INPUT:
4639 return (r2_type == RELOAD_FOR_INSN
4640 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4641 || r2_type == RELOAD_FOR_OPADDR_ADDR
4642 || r2_type == RELOAD_FOR_INPUT
4643 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4644 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4645 && r2_opnum > r1_opnum));
4647 case RELOAD_FOR_INPUT_ADDRESS:
4648 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4649 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4651 case RELOAD_FOR_INPADDR_ADDRESS:
4652 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4653 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4655 case RELOAD_FOR_OUTPUT_ADDRESS:
4656 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4657 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4659 case RELOAD_FOR_OUTADDR_ADDRESS:
4660 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4661 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4663 case RELOAD_FOR_OPERAND_ADDRESS:
4664 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4665 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4667 case RELOAD_FOR_OPADDR_ADDR:
4668 return (r2_type == RELOAD_FOR_INPUT
4669 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4671 case RELOAD_FOR_OUTPUT:
4672 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4673 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4674 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4675 && r2_opnum >= r1_opnum));
4677 case RELOAD_FOR_INSN:
4678 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4679 || r2_type == RELOAD_FOR_INSN
4680 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4682 case RELOAD_FOR_OTHER_ADDRESS:
4683 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4693 /* Indexed by reload number, 1 if incoming value
4694 inherited from previous insns. */
4695 char reload_inherited[MAX_RELOADS];
4697 /* For an inherited reload, this is the insn the reload was inherited from,
4698 if we know it. Otherwise, this is 0. */
4699 rtx reload_inheritance_insn[MAX_RELOADS];
4701 /* If nonzero, this is a place to get the value of the reload,
4702 rather than using reload_in. */
4703 rtx reload_override_in[MAX_RELOADS];
4705 /* For each reload, the hard register number of the register used,
4706 or -1 if we did not need a register for this reload. */
4707 int reload_spill_index[MAX_RELOADS];
4709 /* Subroutine of free_for_value_p, used to check a single register.
4710 START_REGNO is the starting regno of the full reload register
4711 (possibly comprising multiple hard registers) that we are considering. */
4714 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4715 enum reload_type type, rtx value, rtx out,
4716 int reloadnum, int ignore_address_reloads)
4719 /* Set if we see an input reload that must not share its reload register
4720 with any new earlyclobber, but might otherwise share the reload
4721 register with an output or input-output reload. */
4722 int check_earlyclobber = 0;
4726 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4729 if (out == const0_rtx)
4735 /* We use some pseudo 'time' value to check if the lifetimes of the
4736 new register use would overlap with the one of a previous reload
4737 that is not read-only or uses a different value.
4738 The 'time' used doesn't have to be linear in any shape or form, just
4740 Some reload types use different 'buckets' for each operand.
4741 So there are MAX_RECOG_OPERANDS different time values for each
4743 We compute TIME1 as the time when the register for the prospective
4744 new reload ceases to be live, and TIME2 for each existing
4745 reload as the time when that the reload register of that reload
4747 Where there is little to be gained by exact lifetime calculations,
4748 we just make conservative assumptions, i.e. a longer lifetime;
4749 this is done in the 'default:' cases. */
4752 case RELOAD_FOR_OTHER_ADDRESS:
4753 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4754 time1 = copy ? 0 : 1;
4757 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4759 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4760 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4761 respectively, to the time values for these, we get distinct time
4762 values. To get distinct time values for each operand, we have to
4763 multiply opnum by at least three. We round that up to four because
4764 multiply by four is often cheaper. */
4765 case RELOAD_FOR_INPADDR_ADDRESS:
4766 time1 = opnum * 4 + 2;
4768 case RELOAD_FOR_INPUT_ADDRESS:
4769 time1 = opnum * 4 + 3;
4771 case RELOAD_FOR_INPUT:
4772 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4773 executes (inclusive). */
4774 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4776 case RELOAD_FOR_OPADDR_ADDR:
4778 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4779 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4781 case RELOAD_FOR_OPERAND_ADDRESS:
4782 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4784 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4786 case RELOAD_FOR_OUTADDR_ADDRESS:
4787 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4789 case RELOAD_FOR_OUTPUT_ADDRESS:
4790 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4793 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4796 for (i = 0; i < n_reloads; i++)
4798 rtx reg = rld[i].reg_rtx;
4799 if (reg && GET_CODE (reg) == REG
4800 && ((unsigned) regno - true_regnum (reg)
4801 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
4804 rtx other_input = rld[i].in;
4806 /* If the other reload loads the same input value, that
4807 will not cause a conflict only if it's loading it into
4808 the same register. */
4809 if (true_regnum (reg) != start_regno)
4810 other_input = NULL_RTX;
4811 if (! other_input || ! rtx_equal_p (other_input, value)
4812 || rld[i].out || out)
4815 switch (rld[i].when_needed)
4817 case RELOAD_FOR_OTHER_ADDRESS:
4820 case RELOAD_FOR_INPADDR_ADDRESS:
4821 /* find_reloads makes sure that a
4822 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4823 by at most one - the first -
4824 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4825 address reload is inherited, the address address reload
4826 goes away, so we can ignore this conflict. */
4827 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4828 && ignore_address_reloads
4829 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4830 Then the address address is still needed to store
4831 back the new address. */
4832 && ! rld[reloadnum].out)
4834 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4835 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4837 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4838 && ignore_address_reloads
4839 /* Unless we are reloading an auto_inc expression. */
4840 && ! rld[reloadnum].out)
4842 time2 = rld[i].opnum * 4 + 2;
4844 case RELOAD_FOR_INPUT_ADDRESS:
4845 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4846 && ignore_address_reloads
4847 && ! rld[reloadnum].out)
4849 time2 = rld[i].opnum * 4 + 3;
4851 case RELOAD_FOR_INPUT:
4852 time2 = rld[i].opnum * 4 + 4;
4853 check_earlyclobber = 1;
4855 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4856 == MAX_RECOG_OPERAND * 4 */
4857 case RELOAD_FOR_OPADDR_ADDR:
4858 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4859 && ignore_address_reloads
4860 && ! rld[reloadnum].out)
4862 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4864 case RELOAD_FOR_OPERAND_ADDRESS:
4865 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4866 check_earlyclobber = 1;
4868 case RELOAD_FOR_INSN:
4869 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4871 case RELOAD_FOR_OUTPUT:
4872 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4873 instruction is executed. */
4874 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4876 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4877 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4879 case RELOAD_FOR_OUTADDR_ADDRESS:
4880 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4881 && ignore_address_reloads
4882 && ! rld[reloadnum].out)
4884 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4886 case RELOAD_FOR_OUTPUT_ADDRESS:
4887 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4890 /* If there is no conflict in the input part, handle this
4891 like an output reload. */
4892 if (! rld[i].in || rtx_equal_p (other_input, value))
4894 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4895 /* Earlyclobbered outputs must conflict with inputs. */
4896 if (earlyclobber_operand_p (rld[i].out))
4897 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4902 /* RELOAD_OTHER might be live beyond instruction execution,
4903 but this is not obvious when we set time2 = 1. So check
4904 here if there might be a problem with the new reload
4905 clobbering the register used by the RELOAD_OTHER. */
4913 && (! rld[i].in || rld[i].out
4914 || ! rtx_equal_p (other_input, value)))
4915 || (out && rld[reloadnum].out_reg
4916 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4922 /* Earlyclobbered outputs must conflict with inputs. */
4923 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4929 /* Return 1 if the value in reload reg REGNO, as used by a reload
4930 needed for the part of the insn specified by OPNUM and TYPE,
4931 may be used to load VALUE into it.
4933 MODE is the mode in which the register is used, this is needed to
4934 determine how many hard regs to test.
4936 Other read-only reloads with the same value do not conflict
4937 unless OUT is nonzero and these other reloads have to live while
4938 output reloads live.
4939 If OUT is CONST0_RTX, this is a special case: it means that the
4940 test should not be for using register REGNO as reload register, but
4941 for copying from register REGNO into the reload register.
4943 RELOADNUM is the number of the reload we want to load this value for;
4944 a reload does not conflict with itself.
4946 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4947 reloads that load an address for the very reload we are considering.
4949 The caller has to make sure that there is no conflict with the return
4953 free_for_value_p (int regno, enum machine_mode mode, int opnum,
4954 enum reload_type type, rtx value, rtx out, int reloadnum,
4955 int ignore_address_reloads)
4957 int nregs = hard_regno_nregs[regno][mode];
4959 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4960 value, out, reloadnum,
4961 ignore_address_reloads))
4966 /* Determine whether the reload reg X overlaps any rtx'es used for
4967 overriding inheritance. Return nonzero if so. */
4970 conflicts_with_override (rtx x)
4973 for (i = 0; i < n_reloads; i++)
4974 if (reload_override_in[i]
4975 && reg_overlap_mentioned_p (x, reload_override_in[i]))
4980 /* Give an error message saying we failed to find a reload for INSN,
4981 and clear out reload R. */
4983 failed_reload (rtx insn, int r)
4985 if (asm_noperands (PATTERN (insn)) < 0)
4986 /* It's the compiler's fault. */
4987 fatal_insn ("could not find a spill register", insn);
4989 /* It's the user's fault; the operand's mode and constraint
4990 don't match. Disable this reload so we don't crash in final. */
4991 error_for_asm (insn,
4992 "`asm' operand constraint incompatible with operand size");
4996 rld[r].optional = 1;
4997 rld[r].secondary_p = 1;
5000 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5001 for reload R. If it's valid, get an rtx for it. Return nonzero if
5004 set_reload_reg (int i, int r)
5007 rtx reg = spill_reg_rtx[i];
5009 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5010 spill_reg_rtx[i] = reg
5011 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5013 regno = true_regnum (reg);
5015 /* Detect when the reload reg can't hold the reload mode.
5016 This used to be one `if', but Sequent compiler can't handle that. */
5017 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5019 enum machine_mode test_mode = VOIDmode;
5021 test_mode = GET_MODE (rld[r].in);
5022 /* If rld[r].in has VOIDmode, it means we will load it
5023 in whatever mode the reload reg has: to wit, rld[r].mode.
5024 We have already tested that for validity. */
5025 /* Aside from that, we need to test that the expressions
5026 to reload from or into have modes which are valid for this
5027 reload register. Otherwise the reload insns would be invalid. */
5028 if (! (rld[r].in != 0 && test_mode != VOIDmode
5029 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5030 if (! (rld[r].out != 0
5031 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5033 /* The reg is OK. */
5036 /* Mark as in use for this insn the reload regs we use
5038 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5039 rld[r].when_needed, rld[r].mode);
5041 rld[r].reg_rtx = reg;
5042 reload_spill_index[r] = spill_regs[i];
5049 /* Find a spill register to use as a reload register for reload R.
5050 LAST_RELOAD is nonzero if this is the last reload for the insn being
5053 Set rld[R].reg_rtx to the register allocated.
5055 We return 1 if successful, or 0 if we couldn't find a spill reg and
5056 we didn't change anything. */
5059 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5064 /* If we put this reload ahead, thinking it is a group,
5065 then insist on finding a group. Otherwise we can grab a
5066 reg that some other reload needs.
5067 (That can happen when we have a 68000 DATA_OR_FP_REG
5068 which is a group of data regs or one fp reg.)
5069 We need not be so restrictive if there are no more reloads
5072 ??? Really it would be nicer to have smarter handling
5073 for that kind of reg class, where a problem like this is normal.
5074 Perhaps those classes should be avoided for reloading
5075 by use of more alternatives. */
5077 int force_group = rld[r].nregs > 1 && ! last_reload;
5079 /* If we want a single register and haven't yet found one,
5080 take any reg in the right class and not in use.
5081 If we want a consecutive group, here is where we look for it.
5083 We use two passes so we can first look for reload regs to
5084 reuse, which are already in use for other reloads in this insn,
5085 and only then use additional registers.
5086 I think that maximizing reuse is needed to make sure we don't
5087 run out of reload regs. Suppose we have three reloads, and
5088 reloads A and B can share regs. These need two regs.
5089 Suppose A and B are given different regs.
5090 That leaves none for C. */
5091 for (pass = 0; pass < 2; pass++)
5093 /* I is the index in spill_regs.
5094 We advance it round-robin between insns to use all spill regs
5095 equally, so that inherited reloads have a chance
5096 of leapfrogging each other. */
5100 for (count = 0; count < n_spills; count++)
5102 int class = (int) rld[r].class;
5108 regnum = spill_regs[i];
5110 if ((reload_reg_free_p (regnum, rld[r].opnum,
5113 /* We check reload_reg_used to make sure we
5114 don't clobber the return register. */
5115 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5116 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5117 rld[r].when_needed, rld[r].in,
5119 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5120 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5121 /* Look first for regs to share, then for unshared. But
5122 don't share regs used for inherited reloads; they are
5123 the ones we want to preserve. */
5125 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5127 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5130 int nr = hard_regno_nregs[regnum][rld[r].mode];
5131 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5132 (on 68000) got us two FP regs. If NR is 1,
5133 we would reject both of them. */
5136 /* If we need only one reg, we have already won. */
5139 /* But reject a single reg if we demand a group. */
5144 /* Otherwise check that as many consecutive regs as we need
5145 are available here. */
5148 int regno = regnum + nr - 1;
5149 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5150 && spill_reg_order[regno] >= 0
5151 && reload_reg_free_p (regno, rld[r].opnum,
5152 rld[r].when_needed)))
5161 /* If we found something on pass 1, omit pass 2. */
5162 if (count < n_spills)
5166 /* We should have found a spill register by now. */
5167 if (count >= n_spills)
5170 /* I is the index in SPILL_REG_RTX of the reload register we are to
5171 allocate. Get an rtx for it and find its register number. */
5173 return set_reload_reg (i, r);
5176 /* Initialize all the tables needed to allocate reload registers.
5177 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5178 is the array we use to restore the reg_rtx field for every reload. */
5181 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5185 for (i = 0; i < n_reloads; i++)
5186 rld[i].reg_rtx = save_reload_reg_rtx[i];
5188 memset (reload_inherited, 0, MAX_RELOADS);
5189 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5190 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5192 CLEAR_HARD_REG_SET (reload_reg_used);
5193 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5194 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5195 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5196 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5197 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5199 CLEAR_HARD_REG_SET (reg_used_in_insn);
5202 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5203 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5204 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5205 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5206 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5207 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5210 for (i = 0; i < reload_n_operands; i++)
5212 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5213 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5214 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5215 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5216 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5217 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5220 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5222 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5224 for (i = 0; i < n_reloads; i++)
5225 /* If we have already decided to use a certain register,
5226 don't use it in another way. */
5228 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5229 rld[i].when_needed, rld[i].mode);
5232 /* Assign hard reg targets for the pseudo-registers we must reload
5233 into hard regs for this insn.
5234 Also output the instructions to copy them in and out of the hard regs.
5236 For machines with register classes, we are responsible for
5237 finding a reload reg in the proper class. */
5240 choose_reload_regs (struct insn_chain *chain)
5242 rtx insn = chain->insn;
5244 unsigned int max_group_size = 1;
5245 enum reg_class group_class = NO_REGS;
5246 int pass, win, inheritance;
5248 rtx save_reload_reg_rtx[MAX_RELOADS];
5250 /* In order to be certain of getting the registers we need,
5251 we must sort the reloads into order of increasing register class.
5252 Then our grabbing of reload registers will parallel the process
5253 that provided the reload registers.
5255 Also note whether any of the reloads wants a consecutive group of regs.
5256 If so, record the maximum size of the group desired and what
5257 register class contains all the groups needed by this insn. */
5259 for (j = 0; j < n_reloads; j++)
5261 reload_order[j] = j;
5262 reload_spill_index[j] = -1;
5264 if (rld[j].nregs > 1)
5266 max_group_size = MAX (rld[j].nregs, max_group_size);
5268 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5271 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5275 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5277 /* If -O, try first with inheritance, then turning it off.
5278 If not -O, don't do inheritance.
5279 Using inheritance when not optimizing leads to paradoxes
5280 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5281 because one side of the comparison might be inherited. */
5283 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5285 choose_reload_regs_init (chain, save_reload_reg_rtx);
5287 /* Process the reloads in order of preference just found.
5288 Beyond this point, subregs can be found in reload_reg_rtx.
5290 This used to look for an existing reloaded home for all of the
5291 reloads, and only then perform any new reloads. But that could lose
5292 if the reloads were done out of reg-class order because a later
5293 reload with a looser constraint might have an old home in a register
5294 needed by an earlier reload with a tighter constraint.
5296 To solve this, we make two passes over the reloads, in the order
5297 described above. In the first pass we try to inherit a reload
5298 from a previous insn. If there is a later reload that needs a
5299 class that is a proper subset of the class being processed, we must
5300 also allocate a spill register during the first pass.
5302 Then make a second pass over the reloads to allocate any reloads
5303 that haven't been given registers yet. */
5305 for (j = 0; j < n_reloads; j++)
5307 int r = reload_order[j];
5308 rtx search_equiv = NULL_RTX;
5310 /* Ignore reloads that got marked inoperative. */
5311 if (rld[r].out == 0 && rld[r].in == 0
5312 && ! rld[r].secondary_p)
5315 /* If find_reloads chose to use reload_in or reload_out as a reload
5316 register, we don't need to chose one. Otherwise, try even if it
5317 found one since we might save an insn if we find the value lying
5319 Try also when reload_in is a pseudo without a hard reg. */
5320 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5321 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5322 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5323 && GET_CODE (rld[r].in) != MEM
5324 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5327 #if 0 /* No longer needed for correct operation.
5328 It might give better code, or might not; worth an experiment? */
5329 /* If this is an optional reload, we can't inherit from earlier insns
5330 until we are sure that any non-optional reloads have been allocated.
5331 The following code takes advantage of the fact that optional reloads
5332 are at the end of reload_order. */
5333 if (rld[r].optional != 0)
5334 for (i = 0; i < j; i++)
5335 if ((rld[reload_order[i]].out != 0
5336 || rld[reload_order[i]].in != 0
5337 || rld[reload_order[i]].secondary_p)
5338 && ! rld[reload_order[i]].optional
5339 && rld[reload_order[i]].reg_rtx == 0)
5340 allocate_reload_reg (chain, reload_order[i], 0);
5343 /* First see if this pseudo is already available as reloaded
5344 for a previous insn. We cannot try to inherit for reloads
5345 that are smaller than the maximum number of registers needed
5346 for groups unless the register we would allocate cannot be used
5349 We could check here to see if this is a secondary reload for
5350 an object that is already in a register of the desired class.
5351 This would avoid the need for the secondary reload register.
5352 But this is complex because we can't easily determine what
5353 objects might want to be loaded via this reload. So let a
5354 register be allocated here. In `emit_reload_insns' we suppress
5355 one of the loads in the case described above. */
5361 enum machine_mode mode = VOIDmode;
5365 else if (GET_CODE (rld[r].in) == REG)
5367 regno = REGNO (rld[r].in);
5368 mode = GET_MODE (rld[r].in);
5370 else if (GET_CODE (rld[r].in_reg) == REG)
5372 regno = REGNO (rld[r].in_reg);
5373 mode = GET_MODE (rld[r].in_reg);
5375 else if (GET_CODE (rld[r].in_reg) == SUBREG
5376 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5378 byte = SUBREG_BYTE (rld[r].in_reg);
5379 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5380 if (regno < FIRST_PSEUDO_REGISTER)
5381 regno = subreg_regno (rld[r].in_reg);
5382 mode = GET_MODE (rld[r].in_reg);
5385 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5386 || GET_CODE (rld[r].in_reg) == PRE_DEC
5387 || GET_CODE (rld[r].in_reg) == POST_INC
5388 || GET_CODE (rld[r].in_reg) == POST_DEC)
5389 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5391 regno = REGNO (XEXP (rld[r].in_reg, 0));
5392 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5393 rld[r].out = rld[r].in;
5397 /* This won't work, since REGNO can be a pseudo reg number.
5398 Also, it takes much more hair to keep track of all the things
5399 that can invalidate an inherited reload of part of a pseudoreg. */
5400 else if (GET_CODE (rld[r].in) == SUBREG
5401 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5402 regno = subreg_regno (rld[r].in);
5405 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5407 enum reg_class class = rld[r].class, last_class;
5408 rtx last_reg = reg_last_reload_reg[regno];
5409 enum machine_mode need_mode;
5411 i = REGNO (last_reg);
5412 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5413 last_class = REGNO_REG_CLASS (i);
5419 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5420 GET_MODE_CLASS (mode));
5423 #ifdef CANNOT_CHANGE_MODE_CLASS
5424 (!REG_CANNOT_CHANGE_MODE_P (i, GET_MODE (last_reg),
5428 (GET_MODE_SIZE (GET_MODE (last_reg))
5429 >= GET_MODE_SIZE (need_mode))
5430 #ifdef CANNOT_CHANGE_MODE_CLASS
5433 && reg_reloaded_contents[i] == regno
5434 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5435 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5436 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5437 /* Even if we can't use this register as a reload
5438 register, we might use it for reload_override_in,
5439 if copying it to the desired class is cheap
5441 || ((REGISTER_MOVE_COST (mode, last_class, class)
5442 < MEMORY_MOVE_COST (mode, class, 1))
5443 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5444 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5448 #ifdef SECONDARY_MEMORY_NEEDED
5449 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5454 && (rld[r].nregs == max_group_size
5455 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5457 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5458 rld[r].when_needed, rld[r].in,
5461 /* If a group is needed, verify that all the subsequent
5462 registers still have their values intact. */
5463 int nr = hard_regno_nregs[i][rld[r].mode];
5466 for (k = 1; k < nr; k++)
5467 if (reg_reloaded_contents[i + k] != regno
5468 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5476 last_reg = (GET_MODE (last_reg) == mode
5477 ? last_reg : gen_rtx_REG (mode, i));
5480 for (k = 0; k < nr; k++)
5481 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5484 /* We found a register that contains the
5485 value we need. If this register is the
5486 same as an `earlyclobber' operand of the
5487 current insn, just mark it as a place to
5488 reload from since we can't use it as the
5489 reload register itself. */
5491 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5492 if (reg_overlap_mentioned_for_reload_p
5493 (reg_last_reload_reg[regno],
5494 reload_earlyclobbers[i1]))
5497 if (i1 != n_earlyclobbers
5498 || ! (free_for_value_p (i, rld[r].mode,
5500 rld[r].when_needed, rld[r].in,
5502 /* Don't use it if we'd clobber a pseudo reg. */
5503 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5505 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5506 /* Don't clobber the frame pointer. */
5507 || (i == HARD_FRAME_POINTER_REGNUM
5508 && frame_pointer_needed
5510 /* Don't really use the inherited spill reg
5511 if we need it wider than we've got it. */
5512 || (GET_MODE_SIZE (rld[r].mode)
5513 > GET_MODE_SIZE (mode))
5516 /* If find_reloads chose reload_out as reload
5517 register, stay with it - that leaves the
5518 inherited register for subsequent reloads. */
5519 || (rld[r].out && rld[r].reg_rtx
5520 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5522 if (! rld[r].optional)
5524 reload_override_in[r] = last_reg;
5525 reload_inheritance_insn[r]
5526 = reg_reloaded_insn[i];
5532 /* We can use this as a reload reg. */
5533 /* Mark the register as in use for this part of
5535 mark_reload_reg_in_use (i,
5539 rld[r].reg_rtx = last_reg;
5540 reload_inherited[r] = 1;
5541 reload_inheritance_insn[r]
5542 = reg_reloaded_insn[i];
5543 reload_spill_index[r] = i;
5544 for (k = 0; k < nr; k++)
5545 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5553 /* Here's another way to see if the value is already lying around. */
5556 && ! reload_inherited[r]
5558 && (CONSTANT_P (rld[r].in)
5559 || GET_CODE (rld[r].in) == PLUS
5560 || GET_CODE (rld[r].in) == REG
5561 || GET_CODE (rld[r].in) == MEM)
5562 && (rld[r].nregs == max_group_size
5563 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5564 search_equiv = rld[r].in;
5565 /* If this is an output reload from a simple move insn, look
5566 if an equivalence for the input is available. */
5567 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5569 rtx set = single_set (insn);
5572 && rtx_equal_p (rld[r].out, SET_DEST (set))
5573 && CONSTANT_P (SET_SRC (set)))
5574 search_equiv = SET_SRC (set);
5580 = find_equiv_reg (search_equiv, insn, rld[r].class,
5581 -1, NULL, 0, rld[r].mode);
5586 if (GET_CODE (equiv) == REG)
5587 regno = REGNO (equiv);
5588 else if (GET_CODE (equiv) == SUBREG)
5590 /* This must be a SUBREG of a hard register.
5591 Make a new REG since this might be used in an
5592 address and not all machines support SUBREGs
5594 regno = subreg_regno (equiv);
5595 equiv = gen_rtx_REG (rld[r].mode, regno);
5601 /* If we found a spill reg, reject it unless it is free
5602 and of the desired class. */
5606 int bad_for_class = 0;
5607 int max_regno = regno + rld[r].nregs;
5609 for (i = regno; i < max_regno; i++)
5611 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5613 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5618 && ! free_for_value_p (regno, rld[r].mode,
5619 rld[r].opnum, rld[r].when_needed,
5620 rld[r].in, rld[r].out, r, 1))
5625 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5628 /* We found a register that contains the value we need.
5629 If this register is the same as an `earlyclobber' operand
5630 of the current insn, just mark it as a place to reload from
5631 since we can't use it as the reload register itself. */
5634 for (i = 0; i < n_earlyclobbers; i++)
5635 if (reg_overlap_mentioned_for_reload_p (equiv,
5636 reload_earlyclobbers[i]))
5638 if (! rld[r].optional)
5639 reload_override_in[r] = equiv;
5644 /* If the equiv register we have found is explicitly clobbered
5645 in the current insn, it depends on the reload type if we
5646 can use it, use it for reload_override_in, or not at all.
5647 In particular, we then can't use EQUIV for a
5648 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5652 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5653 switch (rld[r].when_needed)
5655 case RELOAD_FOR_OTHER_ADDRESS:
5656 case RELOAD_FOR_INPADDR_ADDRESS:
5657 case RELOAD_FOR_INPUT_ADDRESS:
5658 case RELOAD_FOR_OPADDR_ADDR:
5661 case RELOAD_FOR_INPUT:
5662 case RELOAD_FOR_OPERAND_ADDRESS:
5663 if (! rld[r].optional)
5664 reload_override_in[r] = equiv;
5670 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5671 switch (rld[r].when_needed)
5673 case RELOAD_FOR_OTHER_ADDRESS:
5674 case RELOAD_FOR_INPADDR_ADDRESS:
5675 case RELOAD_FOR_INPUT_ADDRESS:
5676 case RELOAD_FOR_OPADDR_ADDR:
5677 case RELOAD_FOR_OPERAND_ADDRESS:
5678 case RELOAD_FOR_INPUT:
5681 if (! rld[r].optional)
5682 reload_override_in[r] = equiv;
5690 /* If we found an equivalent reg, say no code need be generated
5691 to load it, and use it as our reload reg. */
5693 && (regno != HARD_FRAME_POINTER_REGNUM
5694 || !frame_pointer_needed))
5696 int nr = hard_regno_nregs[regno][rld[r].mode];
5698 rld[r].reg_rtx = equiv;
5699 reload_inherited[r] = 1;
5701 /* If reg_reloaded_valid is not set for this register,
5702 there might be a stale spill_reg_store lying around.
5703 We must clear it, since otherwise emit_reload_insns
5704 might delete the store. */
5705 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5706 spill_reg_store[regno] = NULL_RTX;
5707 /* If any of the hard registers in EQUIV are spill
5708 registers, mark them as in use for this insn. */
5709 for (k = 0; k < nr; k++)
5711 i = spill_reg_order[regno + k];
5714 mark_reload_reg_in_use (regno, rld[r].opnum,
5717 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5724 /* If we found a register to use already, or if this is an optional
5725 reload, we are done. */
5726 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5730 /* No longer needed for correct operation. Might or might
5731 not give better code on the average. Want to experiment? */
5733 /* See if there is a later reload that has a class different from our
5734 class that intersects our class or that requires less register
5735 than our reload. If so, we must allocate a register to this
5736 reload now, since that reload might inherit a previous reload
5737 and take the only available register in our class. Don't do this
5738 for optional reloads since they will force all previous reloads
5739 to be allocated. Also don't do this for reloads that have been
5742 for (i = j + 1; i < n_reloads; i++)
5744 int s = reload_order[i];
5746 if ((rld[s].in == 0 && rld[s].out == 0
5747 && ! rld[s].secondary_p)
5751 if ((rld[s].class != rld[r].class
5752 && reg_classes_intersect_p (rld[r].class,
5754 || rld[s].nregs < rld[r].nregs)
5761 allocate_reload_reg (chain, r, j == n_reloads - 1);
5765 /* Now allocate reload registers for anything non-optional that
5766 didn't get one yet. */
5767 for (j = 0; j < n_reloads; j++)
5769 int r = reload_order[j];
5771 /* Ignore reloads that got marked inoperative. */
5772 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5775 /* Skip reloads that already have a register allocated or are
5777 if (rld[r].reg_rtx != 0 || rld[r].optional)
5780 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5784 /* If that loop got all the way, we have won. */
5791 /* Loop around and try without any inheritance. */
5796 /* First undo everything done by the failed attempt
5797 to allocate with inheritance. */
5798 choose_reload_regs_init (chain, save_reload_reg_rtx);
5800 /* Some sanity tests to verify that the reloads found in the first
5801 pass are identical to the ones we have now. */
5802 if (chain->n_reloads != n_reloads)
5805 for (i = 0; i < n_reloads; i++)
5807 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5809 if (chain->rld[i].when_needed != rld[i].when_needed)
5811 for (j = 0; j < n_spills; j++)
5812 if (spill_regs[j] == chain->rld[i].regno)
5813 if (! set_reload_reg (j, i))
5814 failed_reload (chain->insn, i);
5818 /* If we thought we could inherit a reload, because it seemed that
5819 nothing else wanted the same reload register earlier in the insn,
5820 verify that assumption, now that all reloads have been assigned.
5821 Likewise for reloads where reload_override_in has been set. */
5823 /* If doing expensive optimizations, do one preliminary pass that doesn't
5824 cancel any inheritance, but removes reloads that have been needed only
5825 for reloads that we know can be inherited. */
5826 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5828 for (j = 0; j < n_reloads; j++)
5830 int r = reload_order[j];
5832 if (reload_inherited[r] && rld[r].reg_rtx)
5833 check_reg = rld[r].reg_rtx;
5834 else if (reload_override_in[r]
5835 && (GET_CODE (reload_override_in[r]) == REG
5836 || GET_CODE (reload_override_in[r]) == SUBREG))
5837 check_reg = reload_override_in[r];
5840 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5841 rld[r].opnum, rld[r].when_needed, rld[r].in,
5842 (reload_inherited[r]
5843 ? rld[r].out : const0_rtx),
5848 reload_inherited[r] = 0;
5849 reload_override_in[r] = 0;
5851 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5852 reload_override_in, then we do not need its related
5853 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5854 likewise for other reload types.
5855 We handle this by removing a reload when its only replacement
5856 is mentioned in reload_in of the reload we are going to inherit.
5857 A special case are auto_inc expressions; even if the input is
5858 inherited, we still need the address for the output. We can
5859 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5860 If we succeeded removing some reload and we are doing a preliminary
5861 pass just to remove such reloads, make another pass, since the
5862 removal of one reload might allow us to inherit another one. */
5864 && rld[r].out != rld[r].in
5865 && remove_address_replacements (rld[r].in) && pass)
5870 /* Now that reload_override_in is known valid,
5871 actually override reload_in. */
5872 for (j = 0; j < n_reloads; j++)
5873 if (reload_override_in[j])
5874 rld[j].in = reload_override_in[j];
5876 /* If this reload won't be done because it has been canceled or is
5877 optional and not inherited, clear reload_reg_rtx so other
5878 routines (such as subst_reloads) don't get confused. */
5879 for (j = 0; j < n_reloads; j++)
5880 if (rld[j].reg_rtx != 0
5881 && ((rld[j].optional && ! reload_inherited[j])
5882 || (rld[j].in == 0 && rld[j].out == 0
5883 && ! rld[j].secondary_p)))
5885 int regno = true_regnum (rld[j].reg_rtx);
5887 if (spill_reg_order[regno] >= 0)
5888 clear_reload_reg_in_use (regno, rld[j].opnum,
5889 rld[j].when_needed, rld[j].mode);
5891 reload_spill_index[j] = -1;
5894 /* Record which pseudos and which spill regs have output reloads. */
5895 for (j = 0; j < n_reloads; j++)
5897 int r = reload_order[j];
5899 i = reload_spill_index[r];
5901 /* I is nonneg if this reload uses a register.
5902 If rld[r].reg_rtx is 0, this is an optional reload
5903 that we opted to ignore. */
5904 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5905 && rld[r].reg_rtx != 0)
5907 int nregno = REGNO (rld[r].out_reg);
5910 if (nregno < FIRST_PSEUDO_REGISTER)
5911 nr = hard_regno_nregs[nregno][rld[r].mode];
5914 reg_has_output_reload[nregno + nr] = 1;
5918 nr = hard_regno_nregs[i][rld[r].mode];
5920 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5923 if (rld[r].when_needed != RELOAD_OTHER
5924 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5925 && rld[r].when_needed != RELOAD_FOR_INSN)
5931 /* Deallocate the reload register for reload R. This is called from
5932 remove_address_replacements. */
5935 deallocate_reload_reg (int r)
5939 if (! rld[r].reg_rtx)
5941 regno = true_regnum (rld[r].reg_rtx);
5943 if (spill_reg_order[regno] >= 0)
5944 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5946 reload_spill_index[r] = -1;
5949 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
5950 reloads of the same item for fear that we might not have enough reload
5951 registers. However, normally they will get the same reload register
5952 and hence actually need not be loaded twice.
5954 Here we check for the most common case of this phenomenon: when we have
5955 a number of reloads for the same object, each of which were allocated
5956 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5957 reload, and is not modified in the insn itself. If we find such,
5958 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5959 This will not increase the number of spill registers needed and will
5960 prevent redundant code. */
5963 merge_assigned_reloads (rtx insn)
5967 /* Scan all the reloads looking for ones that only load values and
5968 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5969 assigned and not modified by INSN. */
5971 for (i = 0; i < n_reloads; i++)
5973 int conflicting_input = 0;
5974 int max_input_address_opnum = -1;
5975 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5977 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5978 || rld[i].out != 0 || rld[i].reg_rtx == 0
5979 || reg_set_p (rld[i].reg_rtx, insn))
5982 /* Look at all other reloads. Ensure that the only use of this
5983 reload_reg_rtx is in a reload that just loads the same value
5984 as we do. Note that any secondary reloads must be of the identical
5985 class since the values, modes, and result registers are the
5986 same, so we need not do anything with any secondary reloads. */
5988 for (j = 0; j < n_reloads; j++)
5990 if (i == j || rld[j].reg_rtx == 0
5991 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
5995 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5996 && rld[j].opnum > max_input_address_opnum)
5997 max_input_address_opnum = rld[j].opnum;
5999 /* If the reload regs aren't exactly the same (e.g, different modes)
6000 or if the values are different, we can't merge this reload.
6001 But if it is an input reload, we might still merge
6002 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6004 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6005 || rld[j].out != 0 || rld[j].in == 0
6006 || ! rtx_equal_p (rld[i].in, rld[j].in))
6008 if (rld[j].when_needed != RELOAD_FOR_INPUT
6009 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6010 || rld[i].opnum > rld[j].opnum)
6011 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6013 conflicting_input = 1;
6014 if (min_conflicting_input_opnum > rld[j].opnum)
6015 min_conflicting_input_opnum = rld[j].opnum;
6019 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6020 we, in fact, found any matching reloads. */
6023 && max_input_address_opnum <= min_conflicting_input_opnum)
6025 for (j = 0; j < n_reloads; j++)
6026 if (i != j && rld[j].reg_rtx != 0
6027 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6028 && (! conflicting_input
6029 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6030 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6032 rld[i].when_needed = RELOAD_OTHER;
6034 reload_spill_index[j] = -1;
6035 transfer_replacements (i, j);
6038 /* If this is now RELOAD_OTHER, look for any reloads that load
6039 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6040 if they were for inputs, RELOAD_OTHER for outputs. Note that
6041 this test is equivalent to looking for reloads for this operand
6043 /* We must take special care when there are two or more reloads to
6044 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6045 same value or a part of it; we must not change its type if there
6046 is a conflicting input. */
6048 if (rld[i].when_needed == RELOAD_OTHER)
6049 for (j = 0; j < n_reloads; j++)
6051 && rld[j].when_needed != RELOAD_OTHER
6052 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6053 && (! conflicting_input
6054 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6055 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6056 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6062 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6063 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6064 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6066 /* Check to see if we accidentally converted two reloads
6067 that use the same reload register with different inputs
6068 to the same type. If so, the resulting code won't work,
6071 for (k = 0; k < j; k++)
6072 if (rld[k].in != 0 && rld[k].reg_rtx != 0
6073 && rld[k].when_needed == rld[j].when_needed
6074 && rtx_equal_p (rld[k].reg_rtx, rld[j].reg_rtx)
6075 && ! rtx_equal_p (rld[k].in, rld[j].in))
6082 /* These arrays are filled by emit_reload_insns and its subroutines. */
6083 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6084 static rtx other_input_address_reload_insns = 0;
6085 static rtx other_input_reload_insns = 0;
6086 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6087 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6088 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6089 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6090 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6091 static rtx operand_reload_insns = 0;
6092 static rtx other_operand_reload_insns = 0;
6093 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6095 /* Values to be put in spill_reg_store are put here first. */
6096 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6097 static HARD_REG_SET reg_reloaded_died;
6099 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6100 has the number J. OLD contains the value to be used as input. */
6103 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6106 rtx insn = chain->insn;
6107 rtx reloadreg = rl->reg_rtx;
6108 rtx oldequiv_reg = 0;
6111 enum machine_mode mode;
6114 /* Determine the mode to reload in.
6115 This is very tricky because we have three to choose from.
6116 There is the mode the insn operand wants (rl->inmode).
6117 There is the mode of the reload register RELOADREG.
6118 There is the intrinsic mode of the operand, which we could find
6119 by stripping some SUBREGs.
6120 It turns out that RELOADREG's mode is irrelevant:
6121 we can change that arbitrarily.
6123 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6124 then the reload reg may not support QImode moves, so use SImode.
6125 If foo is in memory due to spilling a pseudo reg, this is safe,
6126 because the QImode value is in the least significant part of a
6127 slot big enough for a SImode. If foo is some other sort of
6128 memory reference, then it is impossible to reload this case,
6129 so previous passes had better make sure this never happens.
6131 Then consider a one-word union which has SImode and one of its
6132 members is a float, being fetched as (SUBREG:SF union:SI).
6133 We must fetch that as SFmode because we could be loading into
6134 a float-only register. In this case OLD's mode is correct.
6136 Consider an immediate integer: it has VOIDmode. Here we need
6137 to get a mode from something else.
6139 In some cases, there is a fourth mode, the operand's
6140 containing mode. If the insn specifies a containing mode for
6141 this operand, it overrides all others.
6143 I am not sure whether the algorithm here is always right,
6144 but it does the right things in those cases. */
6146 mode = GET_MODE (old);
6147 if (mode == VOIDmode)
6150 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6151 /* If we need a secondary register for this operation, see if
6152 the value is already in a register in that class. Don't
6153 do this if the secondary register will be used as a scratch
6156 if (rl->secondary_in_reload >= 0
6157 && rl->secondary_in_icode == CODE_FOR_nothing
6160 = find_equiv_reg (old, insn,
6161 rld[rl->secondary_in_reload].class,
6165 /* If reloading from memory, see if there is a register
6166 that already holds the same value. If so, reload from there.
6167 We can pass 0 as the reload_reg_p argument because
6168 any other reload has either already been emitted,
6169 in which case find_equiv_reg will see the reload-insn,
6170 or has yet to be emitted, in which case it doesn't matter
6171 because we will use this equiv reg right away. */
6173 if (oldequiv == 0 && optimize
6174 && (GET_CODE (old) == MEM
6175 || (GET_CODE (old) == REG
6176 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6177 && reg_renumber[REGNO (old)] < 0)))
6178 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6182 unsigned int regno = true_regnum (oldequiv);
6184 /* Don't use OLDEQUIV if any other reload changes it at an
6185 earlier stage of this insn or at this stage. */
6186 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6187 rl->in, const0_rtx, j, 0))
6190 /* If it is no cheaper to copy from OLDEQUIV into the
6191 reload register than it would be to move from memory,
6192 don't use it. Likewise, if we need a secondary register
6196 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6197 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6199 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6200 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6201 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6205 #ifdef SECONDARY_MEMORY_NEEDED
6206 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6214 /* delete_output_reload is only invoked properly if old contains
6215 the original pseudo register. Since this is replaced with a
6216 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6217 find the pseudo in RELOAD_IN_REG. */
6219 && reload_override_in[j]
6220 && GET_CODE (rl->in_reg) == REG)
6227 else if (GET_CODE (oldequiv) == REG)
6228 oldequiv_reg = oldequiv;
6229 else if (GET_CODE (oldequiv) == SUBREG)
6230 oldequiv_reg = SUBREG_REG (oldequiv);
6232 /* If we are reloading from a register that was recently stored in
6233 with an output-reload, see if we can prove there was
6234 actually no need to store the old value in it. */
6236 if (optimize && GET_CODE (oldequiv) == REG
6237 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6238 && spill_reg_store[REGNO (oldequiv)]
6239 && GET_CODE (old) == REG
6240 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6241 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6243 delete_output_reload (insn, j, REGNO (oldequiv));
6245 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6246 then load RELOADREG from OLDEQUIV. Note that we cannot use
6247 gen_lowpart_common since it can do the wrong thing when
6248 RELOADREG has a multi-word mode. Note that RELOADREG
6249 must always be a REG here. */
6251 if (GET_MODE (reloadreg) != mode)
6252 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6253 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6254 oldequiv = SUBREG_REG (oldequiv);
6255 if (GET_MODE (oldequiv) != VOIDmode
6256 && mode != GET_MODE (oldequiv))
6257 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6259 /* Switch to the right place to emit the reload insns. */
6260 switch (rl->when_needed)
6263 where = &other_input_reload_insns;
6265 case RELOAD_FOR_INPUT:
6266 where = &input_reload_insns[rl->opnum];
6268 case RELOAD_FOR_INPUT_ADDRESS:
6269 where = &input_address_reload_insns[rl->opnum];
6271 case RELOAD_FOR_INPADDR_ADDRESS:
6272 where = &inpaddr_address_reload_insns[rl->opnum];
6274 case RELOAD_FOR_OUTPUT_ADDRESS:
6275 where = &output_address_reload_insns[rl->opnum];
6277 case RELOAD_FOR_OUTADDR_ADDRESS:
6278 where = &outaddr_address_reload_insns[rl->opnum];
6280 case RELOAD_FOR_OPERAND_ADDRESS:
6281 where = &operand_reload_insns;
6283 case RELOAD_FOR_OPADDR_ADDR:
6284 where = &other_operand_reload_insns;
6286 case RELOAD_FOR_OTHER_ADDRESS:
6287 where = &other_input_address_reload_insns;
6293 push_to_sequence (*where);
6295 /* Auto-increment addresses must be reloaded in a special way. */
6296 if (rl->out && ! rl->out_reg)
6298 /* We are not going to bother supporting the case where a
6299 incremented register can't be copied directly from
6300 OLDEQUIV since this seems highly unlikely. */
6301 if (rl->secondary_in_reload >= 0)
6304 if (reload_inherited[j])
6305 oldequiv = reloadreg;
6307 old = XEXP (rl->in_reg, 0);
6309 if (optimize && GET_CODE (oldequiv) == REG
6310 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6311 && spill_reg_store[REGNO (oldequiv)]
6312 && GET_CODE (old) == REG
6313 && (dead_or_set_p (insn,
6314 spill_reg_stored_to[REGNO (oldequiv)])
6315 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6317 delete_output_reload (insn, j, REGNO (oldequiv));
6319 /* Prevent normal processing of this reload. */
6321 /* Output a special code sequence for this case. */
6322 new_spill_reg_store[REGNO (reloadreg)]
6323 = inc_for_reload (reloadreg, oldequiv, rl->out,
6327 /* If we are reloading a pseudo-register that was set by the previous
6328 insn, see if we can get rid of that pseudo-register entirely
6329 by redirecting the previous insn into our reload register. */
6331 else if (optimize && GET_CODE (old) == REG
6332 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6333 && dead_or_set_p (insn, old)
6334 /* This is unsafe if some other reload
6335 uses the same reg first. */
6336 && ! conflicts_with_override (reloadreg)
6337 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6338 rl->when_needed, old, rl->out, j, 0))
6340 rtx temp = PREV_INSN (insn);
6341 while (temp && GET_CODE (temp) == NOTE)
6342 temp = PREV_INSN (temp);
6344 && GET_CODE (temp) == INSN
6345 && GET_CODE (PATTERN (temp)) == SET
6346 && SET_DEST (PATTERN (temp)) == old
6347 /* Make sure we can access insn_operand_constraint. */
6348 && asm_noperands (PATTERN (temp)) < 0
6349 /* This is unsafe if operand occurs more than once in current
6350 insn. Perhaps some occurrences aren't reloaded. */
6351 && count_occurrences (PATTERN (insn), old, 0) == 1)
6353 rtx old = SET_DEST (PATTERN (temp));
6354 /* Store into the reload register instead of the pseudo. */
6355 SET_DEST (PATTERN (temp)) = reloadreg;
6357 /* Verify that resulting insn is valid. */
6358 extract_insn (temp);
6359 if (constrain_operands (1))
6361 /* If the previous insn is an output reload, the source is
6362 a reload register, and its spill_reg_store entry will
6363 contain the previous destination. This is now
6365 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6366 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6368 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6369 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6372 /* If these are the only uses of the pseudo reg,
6373 pretend for GDB it lives in the reload reg we used. */
6374 if (REG_N_DEATHS (REGNO (old)) == 1
6375 && REG_N_SETS (REGNO (old)) == 1)
6377 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6378 alter_reg (REGNO (old), -1);
6384 SET_DEST (PATTERN (temp)) = old;
6389 /* We can't do that, so output an insn to load RELOADREG. */
6391 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6392 /* If we have a secondary reload, pick up the secondary register
6393 and icode, if any. If OLDEQUIV and OLD are different or
6394 if this is an in-out reload, recompute whether or not we
6395 still need a secondary register and what the icode should
6396 be. If we still need a secondary register and the class or
6397 icode is different, go back to reloading from OLD if using
6398 OLDEQUIV means that we got the wrong type of register. We
6399 cannot have different class or icode due to an in-out reload
6400 because we don't make such reloads when both the input and
6401 output need secondary reload registers. */
6403 if (! special && rl->secondary_in_reload >= 0)
6405 rtx second_reload_reg = 0;
6406 int secondary_reload = rl->secondary_in_reload;
6407 rtx real_oldequiv = oldequiv;
6410 enum insn_code icode;
6412 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6413 and similarly for OLD.
6414 See comments in get_secondary_reload in reload.c. */
6415 /* If it is a pseudo that cannot be replaced with its
6416 equivalent MEM, we must fall back to reload_in, which
6417 will have all the necessary substitutions registered.
6418 Likewise for a pseudo that can't be replaced with its
6419 equivalent constant.
6421 Take extra care for subregs of such pseudos. Note that
6422 we cannot use reg_equiv_mem in this case because it is
6423 not in the right mode. */
6426 if (GET_CODE (tmp) == SUBREG)
6427 tmp = SUBREG_REG (tmp);
6428 if (GET_CODE (tmp) == REG
6429 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6430 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6431 || reg_equiv_constant[REGNO (tmp)] != 0))
6433 if (! reg_equiv_mem[REGNO (tmp)]
6434 || num_not_at_initial_offset
6435 || GET_CODE (oldequiv) == SUBREG)
6436 real_oldequiv = rl->in;
6438 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6442 if (GET_CODE (tmp) == SUBREG)
6443 tmp = SUBREG_REG (tmp);
6444 if (GET_CODE (tmp) == REG
6445 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6446 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6447 || reg_equiv_constant[REGNO (tmp)] != 0))
6449 if (! reg_equiv_mem[REGNO (tmp)]
6450 || num_not_at_initial_offset
6451 || GET_CODE (old) == SUBREG)
6454 real_old = reg_equiv_mem[REGNO (tmp)];
6457 second_reload_reg = rld[secondary_reload].reg_rtx;
6458 icode = rl->secondary_in_icode;
6460 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6461 || (rl->in != 0 && rl->out != 0))
6463 enum reg_class new_class
6464 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6465 mode, real_oldequiv);
6467 if (new_class == NO_REGS)
6468 second_reload_reg = 0;
6471 enum insn_code new_icode;
6472 enum machine_mode new_mode;
6474 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6475 REGNO (second_reload_reg)))
6476 oldequiv = old, real_oldequiv = real_old;
6479 new_icode = reload_in_optab[(int) mode];
6480 if (new_icode != CODE_FOR_nothing
6481 && ((insn_data[(int) new_icode].operand[0].predicate
6482 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6484 || (insn_data[(int) new_icode].operand[1].predicate
6485 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6486 (real_oldequiv, mode)))))
6487 new_icode = CODE_FOR_nothing;
6489 if (new_icode == CODE_FOR_nothing)
6492 new_mode = insn_data[(int) new_icode].operand[2].mode;
6494 if (GET_MODE (second_reload_reg) != new_mode)
6496 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6498 oldequiv = old, real_oldequiv = real_old;
6501 = reload_adjust_reg_for_mode (second_reload_reg,
6508 /* If we still need a secondary reload register, check
6509 to see if it is being used as a scratch or intermediate
6510 register and generate code appropriately. If we need
6511 a scratch register, use REAL_OLDEQUIV since the form of
6512 the insn may depend on the actual address if it is
6515 if (second_reload_reg)
6517 if (icode != CODE_FOR_nothing)
6519 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6520 second_reload_reg));
6525 /* See if we need a scratch register to load the
6526 intermediate register (a tertiary reload). */
6527 enum insn_code tertiary_icode
6528 = rld[secondary_reload].secondary_in_icode;
6530 if (tertiary_icode != CODE_FOR_nothing)
6532 rtx third_reload_reg
6533 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6535 emit_insn ((GEN_FCN (tertiary_icode)
6536 (second_reload_reg, real_oldequiv,
6537 third_reload_reg)));
6540 gen_reload (second_reload_reg, real_oldequiv,
6544 oldequiv = second_reload_reg;
6550 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6552 rtx real_oldequiv = oldequiv;
6554 if ((GET_CODE (oldequiv) == REG
6555 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6556 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6557 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6558 || (GET_CODE (oldequiv) == SUBREG
6559 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6560 && (REGNO (SUBREG_REG (oldequiv))
6561 >= FIRST_PSEUDO_REGISTER)
6562 && ((reg_equiv_memory_loc
6563 [REGNO (SUBREG_REG (oldequiv))] != 0)
6564 || (reg_equiv_constant
6565 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6566 || (CONSTANT_P (oldequiv)
6567 && (PREFERRED_RELOAD_CLASS (oldequiv,
6568 REGNO_REG_CLASS (REGNO (reloadreg)))
6570 real_oldequiv = rl->in;
6571 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6575 if (flag_non_call_exceptions)
6576 copy_eh_notes (insn, get_insns ());
6578 /* End this sequence. */
6579 *where = get_insns ();
6582 /* Update reload_override_in so that delete_address_reloads_1
6583 can see the actual register usage. */
6585 reload_override_in[j] = oldequiv;
6588 /* Generate insns to for the output reload RL, which is for the insn described
6589 by CHAIN and has the number J. */
6591 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6594 rtx reloadreg = rl->reg_rtx;
6595 rtx insn = chain->insn;
6598 enum machine_mode mode = GET_MODE (old);
6601 if (rl->when_needed == RELOAD_OTHER)
6604 push_to_sequence (output_reload_insns[rl->opnum]);
6606 /* Determine the mode to reload in.
6607 See comments above (for input reloading). */
6609 if (mode == VOIDmode)
6611 /* VOIDmode should never happen for an output. */
6612 if (asm_noperands (PATTERN (insn)) < 0)
6613 /* It's the compiler's fault. */
6614 fatal_insn ("VOIDmode on an output", insn);
6615 error_for_asm (insn, "output operand is constant in `asm'");
6616 /* Prevent crash--use something we know is valid. */
6618 old = gen_rtx_REG (mode, REGNO (reloadreg));
6621 if (GET_MODE (reloadreg) != mode)
6622 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6624 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6626 /* If we need two reload regs, set RELOADREG to the intermediate
6627 one, since it will be stored into OLD. We might need a secondary
6628 register only for an input reload, so check again here. */
6630 if (rl->secondary_out_reload >= 0)
6634 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6635 && reg_equiv_mem[REGNO (old)] != 0)
6636 real_old = reg_equiv_mem[REGNO (old)];
6638 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6642 rtx second_reloadreg = reloadreg;
6643 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6645 /* See if RELOADREG is to be used as a scratch register
6646 or as an intermediate register. */
6647 if (rl->secondary_out_icode != CODE_FOR_nothing)
6649 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6650 (real_old, second_reloadreg, reloadreg)));
6655 /* See if we need both a scratch and intermediate reload
6658 int secondary_reload = rl->secondary_out_reload;
6659 enum insn_code tertiary_icode
6660 = rld[secondary_reload].secondary_out_icode;
6662 if (GET_MODE (reloadreg) != mode)
6663 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6665 if (tertiary_icode != CODE_FOR_nothing)
6668 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6671 /* Copy primary reload reg to secondary reload reg.
6672 (Note that these have been swapped above, then
6673 secondary reload reg to OLD using our insn.) */
6675 /* If REAL_OLD is a paradoxical SUBREG, remove it
6676 and try to put the opposite SUBREG on
6678 if (GET_CODE (real_old) == SUBREG
6679 && (GET_MODE_SIZE (GET_MODE (real_old))
6680 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6681 && 0 != (tem = gen_lowpart_common
6682 (GET_MODE (SUBREG_REG (real_old)),
6684 real_old = SUBREG_REG (real_old), reloadreg = tem;
6686 gen_reload (reloadreg, second_reloadreg,
6687 rl->opnum, rl->when_needed);
6688 emit_insn ((GEN_FCN (tertiary_icode)
6689 (real_old, reloadreg, third_reloadreg)));
6694 /* Copy between the reload regs here and then to
6697 gen_reload (reloadreg, second_reloadreg,
6698 rl->opnum, rl->when_needed);
6704 /* Output the last reload insn. */
6709 /* Don't output the last reload if OLD is not the dest of
6710 INSN and is in the src and is clobbered by INSN. */
6711 if (! flag_expensive_optimizations
6712 || GET_CODE (old) != REG
6713 || !(set = single_set (insn))
6714 || rtx_equal_p (old, SET_DEST (set))
6715 || !reg_mentioned_p (old, SET_SRC (set))
6716 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6717 gen_reload (old, reloadreg, rl->opnum,
6721 /* Look at all insns we emitted, just to be safe. */
6722 for (p = get_insns (); p; p = NEXT_INSN (p))
6725 rtx pat = PATTERN (p);
6727 /* If this output reload doesn't come from a spill reg,
6728 clear any memory of reloaded copies of the pseudo reg.
6729 If this output reload comes from a spill reg,
6730 reg_has_output_reload will make this do nothing. */
6731 note_stores (pat, forget_old_reloads_1, NULL);
6733 if (reg_mentioned_p (rl->reg_rtx, pat))
6735 rtx set = single_set (insn);
6736 if (reload_spill_index[j] < 0
6738 && SET_SRC (set) == rl->reg_rtx)
6740 int src = REGNO (SET_SRC (set));
6742 reload_spill_index[j] = src;
6743 SET_HARD_REG_BIT (reg_is_output_reload, src);
6744 if (find_regno_note (insn, REG_DEAD, src))
6745 SET_HARD_REG_BIT (reg_reloaded_died, src);
6747 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6749 int s = rl->secondary_out_reload;
6750 set = single_set (p);
6751 /* If this reload copies only to the secondary reload
6752 register, the secondary reload does the actual
6754 if (s >= 0 && set == NULL_RTX)
6755 /* We can't tell what function the secondary reload
6756 has and where the actual store to the pseudo is
6757 made; leave new_spill_reg_store alone. */
6760 && SET_SRC (set) == rl->reg_rtx
6761 && SET_DEST (set) == rld[s].reg_rtx)
6763 /* Usually the next instruction will be the
6764 secondary reload insn; if we can confirm
6765 that it is, setting new_spill_reg_store to
6766 that insn will allow an extra optimization. */
6767 rtx s_reg = rld[s].reg_rtx;
6768 rtx next = NEXT_INSN (p);
6769 rld[s].out = rl->out;
6770 rld[s].out_reg = rl->out_reg;
6771 set = single_set (next);
6772 if (set && SET_SRC (set) == s_reg
6773 && ! new_spill_reg_store[REGNO (s_reg)])
6775 SET_HARD_REG_BIT (reg_is_output_reload,
6777 new_spill_reg_store[REGNO (s_reg)] = next;
6781 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6786 if (rl->when_needed == RELOAD_OTHER)
6788 emit_insn (other_output_reload_insns[rl->opnum]);
6789 other_output_reload_insns[rl->opnum] = get_insns ();
6792 output_reload_insns[rl->opnum] = get_insns ();
6794 if (flag_non_call_exceptions)
6795 copy_eh_notes (insn, get_insns ());
6800 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6801 and has the number J. */
6803 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
6805 rtx insn = chain->insn;
6806 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6807 ? rl->in_reg : rl->in);
6810 /* AUTO_INC reloads need to be handled even if inherited. We got an
6811 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6812 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6813 && ! rtx_equal_p (rl->reg_rtx, old)
6814 && rl->reg_rtx != 0)
6815 emit_input_reload_insns (chain, rld + j, old, j);
6817 /* When inheriting a wider reload, we have a MEM in rl->in,
6818 e.g. inheriting a SImode output reload for
6819 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6820 if (optimize && reload_inherited[j] && rl->in
6821 && GET_CODE (rl->in) == MEM
6822 && GET_CODE (rl->in_reg) == MEM
6823 && reload_spill_index[j] >= 0
6824 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6825 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6827 /* If we are reloading a register that was recently stored in with an
6828 output-reload, see if we can prove there was
6829 actually no need to store the old value in it. */
6832 && (reload_inherited[j] || reload_override_in[j])
6834 && GET_CODE (rl->reg_rtx) == REG
6835 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6837 /* There doesn't seem to be any reason to restrict this to pseudos
6838 and doing so loses in the case where we are copying from a
6839 register of the wrong class. */
6840 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6841 >= FIRST_PSEUDO_REGISTER)
6843 /* The insn might have already some references to stackslots
6844 replaced by MEMs, while reload_out_reg still names the
6846 && (dead_or_set_p (insn,
6847 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6848 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6850 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6853 /* Do output reloading for reload RL, which is for the insn described by
6854 CHAIN and has the number J.
6855 ??? At some point we need to support handling output reloads of
6856 JUMP_INSNs or insns that set cc0. */
6858 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
6861 rtx insn = chain->insn;
6862 /* If this is an output reload that stores something that is
6863 not loaded in this same reload, see if we can eliminate a previous
6865 rtx pseudo = rl->out_reg;
6869 && GET_CODE (pseudo) == REG
6870 && ! rtx_equal_p (rl->in_reg, pseudo)
6871 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6872 && reg_last_reload_reg[REGNO (pseudo)])
6874 int pseudo_no = REGNO (pseudo);
6875 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6877 /* We don't need to test full validity of last_regno for
6878 inherit here; we only want to know if the store actually
6879 matches the pseudo. */
6880 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6881 && reg_reloaded_contents[last_regno] == pseudo_no
6882 && spill_reg_store[last_regno]
6883 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6884 delete_output_reload (insn, j, last_regno);
6889 || rl->reg_rtx == old
6890 || rl->reg_rtx == 0)
6893 /* An output operand that dies right away does need a reload,
6894 but need not be copied from it. Show the new location in the
6896 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6897 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6899 XEXP (note, 0) = rl->reg_rtx;
6902 /* Likewise for a SUBREG of an operand that dies. */
6903 else if (GET_CODE (old) == SUBREG
6904 && GET_CODE (SUBREG_REG (old)) == REG
6905 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6908 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6912 else if (GET_CODE (old) == SCRATCH)
6913 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6914 but we don't want to make an output reload. */
6917 /* If is a JUMP_INSN, we can't support output reloads yet. */
6918 if (GET_CODE (insn) == JUMP_INSN)
6921 emit_output_reload_insns (chain, rld + j, j);
6924 /* Output insns to reload values in and out of the chosen reload regs. */
6927 emit_reload_insns (struct insn_chain *chain)
6929 rtx insn = chain->insn;
6933 CLEAR_HARD_REG_SET (reg_reloaded_died);
6935 for (j = 0; j < reload_n_operands; j++)
6936 input_reload_insns[j] = input_address_reload_insns[j]
6937 = inpaddr_address_reload_insns[j]
6938 = output_reload_insns[j] = output_address_reload_insns[j]
6939 = outaddr_address_reload_insns[j]
6940 = other_output_reload_insns[j] = 0;
6941 other_input_address_reload_insns = 0;
6942 other_input_reload_insns = 0;
6943 operand_reload_insns = 0;
6944 other_operand_reload_insns = 0;
6946 /* Dump reloads into the dump file. */
6949 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6950 debug_reload_to_stream (rtl_dump_file);
6953 /* Now output the instructions to copy the data into and out of the
6954 reload registers. Do these in the order that the reloads were reported,
6955 since reloads of base and index registers precede reloads of operands
6956 and the operands may need the base and index registers reloaded. */
6958 for (j = 0; j < n_reloads; j++)
6961 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6962 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6964 do_input_reload (chain, rld + j, j);
6965 do_output_reload (chain, rld + j, j);
6968 /* Now write all the insns we made for reloads in the order expected by
6969 the allocation functions. Prior to the insn being reloaded, we write
6970 the following reloads:
6972 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6974 RELOAD_OTHER reloads.
6976 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6977 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6978 RELOAD_FOR_INPUT reload for the operand.
6980 RELOAD_FOR_OPADDR_ADDRS reloads.
6982 RELOAD_FOR_OPERAND_ADDRESS reloads.
6984 After the insn being reloaded, we write the following:
6986 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6987 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6988 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6989 reloads for the operand. The RELOAD_OTHER output reloads are
6990 output in descending order by reload number. */
6992 emit_insn_before_sameloc (other_input_address_reload_insns, insn);
6993 emit_insn_before_sameloc (other_input_reload_insns, insn);
6995 for (j = 0; j < reload_n_operands; j++)
6997 emit_insn_before_sameloc (inpaddr_address_reload_insns[j], insn);
6998 emit_insn_before_sameloc (input_address_reload_insns[j], insn);
6999 emit_insn_before_sameloc (input_reload_insns[j], insn);
7002 emit_insn_before_sameloc (other_operand_reload_insns, insn);
7003 emit_insn_before_sameloc (operand_reload_insns, insn);
7005 for (j = 0; j < reload_n_operands; j++)
7007 rtx x = emit_insn_after_sameloc (outaddr_address_reload_insns[j], insn);
7008 x = emit_insn_after_sameloc (output_address_reload_insns[j], x);
7009 x = emit_insn_after_sameloc (output_reload_insns[j], x);
7010 emit_insn_after_sameloc (other_output_reload_insns[j], x);
7013 /* For all the spill regs newly reloaded in this instruction,
7014 record what they were reloaded from, so subsequent instructions
7015 can inherit the reloads.
7017 Update spill_reg_store for the reloads of this insn.
7018 Copy the elements that were updated in the loop above. */
7020 for (j = 0; j < n_reloads; j++)
7022 int r = reload_order[j];
7023 int i = reload_spill_index[r];
7025 /* If this is a non-inherited input reload from a pseudo, we must
7026 clear any memory of a previous store to the same pseudo. Only do
7027 something if there will not be an output reload for the pseudo
7029 if (rld[r].in_reg != 0
7030 && ! (reload_inherited[r] || reload_override_in[r]))
7032 rtx reg = rld[r].in_reg;
7034 if (GET_CODE (reg) == SUBREG)
7035 reg = SUBREG_REG (reg);
7037 if (GET_CODE (reg) == REG
7038 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7039 && ! reg_has_output_reload[REGNO (reg)])
7041 int nregno = REGNO (reg);
7043 if (reg_last_reload_reg[nregno])
7045 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7047 if (reg_reloaded_contents[last_regno] == nregno)
7048 spill_reg_store[last_regno] = 0;
7053 /* I is nonneg if this reload used a register.
7054 If rld[r].reg_rtx is 0, this is an optional reload
7055 that we opted to ignore. */
7057 if (i >= 0 && rld[r].reg_rtx != 0)
7059 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7061 int part_reaches_end = 0;
7062 int all_reaches_end = 1;
7064 /* For a multi register reload, we need to check if all or part
7065 of the value lives to the end. */
7066 for (k = 0; k < nr; k++)
7068 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7069 rld[r].when_needed))
7070 part_reaches_end = 1;
7072 all_reaches_end = 0;
7075 /* Ignore reloads that don't reach the end of the insn in
7077 if (all_reaches_end)
7079 /* First, clear out memory of what used to be in this spill reg.
7080 If consecutive registers are used, clear them all. */
7082 for (k = 0; k < nr; k++)
7084 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7085 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7088 /* Maybe the spill reg contains a copy of reload_out. */
7090 && (GET_CODE (rld[r].out) == REG
7094 || GET_CODE (rld[r].out_reg) == REG))
7096 rtx out = (GET_CODE (rld[r].out) == REG
7100 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7101 int nregno = REGNO (out);
7102 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7103 : hard_regno_nregs[nregno]
7104 [GET_MODE (rld[r].reg_rtx)]);
7106 spill_reg_store[i] = new_spill_reg_store[i];
7107 spill_reg_stored_to[i] = out;
7108 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7110 /* If NREGNO is a hard register, it may occupy more than
7111 one register. If it does, say what is in the
7112 rest of the registers assuming that both registers
7113 agree on how many words the object takes. If not,
7114 invalidate the subsequent registers. */
7116 if (nregno < FIRST_PSEUDO_REGISTER)
7117 for (k = 1; k < nnr; k++)
7118 reg_last_reload_reg[nregno + k]
7120 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7123 /* Now do the inverse operation. */
7124 for (k = 0; k < nr; k++)
7126 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7127 reg_reloaded_contents[i + k]
7128 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7131 reg_reloaded_insn[i + k] = insn;
7132 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7133 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7134 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7138 /* Maybe the spill reg contains a copy of reload_in. Only do
7139 something if there will not be an output reload for
7140 the register being reloaded. */
7141 else if (rld[r].out_reg == 0
7143 && ((GET_CODE (rld[r].in) == REG
7144 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7145 && ! reg_has_output_reload[REGNO (rld[r].in)])
7146 || (GET_CODE (rld[r].in_reg) == REG
7147 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7148 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7154 if (GET_CODE (rld[r].in) == REG
7155 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7157 else if (GET_CODE (rld[r].in_reg) == REG)
7160 in = XEXP (rld[r].in_reg, 0);
7161 nregno = REGNO (in);
7163 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7164 : hard_regno_nregs[nregno]
7165 [GET_MODE (rld[r].reg_rtx)]);
7167 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7169 if (nregno < FIRST_PSEUDO_REGISTER)
7170 for (k = 1; k < nnr; k++)
7171 reg_last_reload_reg[nregno + k]
7173 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7176 /* Unless we inherited this reload, show we haven't
7177 recently done a store.
7178 Previous stores of inherited auto_inc expressions
7179 also have to be discarded. */
7180 if (! reload_inherited[r]
7181 || (rld[r].out && ! rld[r].out_reg))
7182 spill_reg_store[i] = 0;
7184 for (k = 0; k < nr; k++)
7186 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7187 reg_reloaded_contents[i + k]
7188 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7191 reg_reloaded_insn[i + k] = insn;
7192 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7193 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7194 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7199 /* However, if part of the reload reaches the end, then we must
7200 invalidate the old info for the part that survives to the end. */
7201 else if (part_reaches_end)
7203 for (k = 0; k < nr; k++)
7204 if (reload_reg_reaches_end_p (i + k,
7206 rld[r].when_needed))
7207 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7211 /* The following if-statement was #if 0'd in 1.34 (or before...).
7212 It's reenabled in 1.35 because supposedly nothing else
7213 deals with this problem. */
7215 /* If a register gets output-reloaded from a non-spill register,
7216 that invalidates any previous reloaded copy of it.
7217 But forget_old_reloads_1 won't get to see it, because
7218 it thinks only about the original insn. So invalidate it here. */
7219 if (i < 0 && rld[r].out != 0
7220 && (GET_CODE (rld[r].out) == REG
7221 || (GET_CODE (rld[r].out) == MEM
7222 && GET_CODE (rld[r].out_reg) == REG)))
7224 rtx out = (GET_CODE (rld[r].out) == REG
7225 ? rld[r].out : rld[r].out_reg);
7226 int nregno = REGNO (out);
7227 if (nregno >= FIRST_PSEUDO_REGISTER)
7229 rtx src_reg, store_insn = NULL_RTX;
7231 reg_last_reload_reg[nregno] = 0;
7233 /* If we can find a hard register that is stored, record
7234 the storing insn so that we may delete this insn with
7235 delete_output_reload. */
7236 src_reg = rld[r].reg_rtx;
7238 /* If this is an optional reload, try to find the source reg
7239 from an input reload. */
7242 rtx set = single_set (insn);
7243 if (set && SET_DEST (set) == rld[r].out)
7247 src_reg = SET_SRC (set);
7249 for (k = 0; k < n_reloads; k++)
7251 if (rld[k].in == src_reg)
7253 src_reg = rld[k].reg_rtx;
7260 store_insn = new_spill_reg_store[REGNO (src_reg)];
7261 if (src_reg && GET_CODE (src_reg) == REG
7262 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7264 int src_regno = REGNO (src_reg);
7265 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7266 /* The place where to find a death note varies with
7267 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7268 necessarily checked exactly in the code that moves
7269 notes, so just check both locations. */
7270 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7271 if (! note && store_insn)
7272 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7275 spill_reg_store[src_regno + nr] = store_insn;
7276 spill_reg_stored_to[src_regno + nr] = out;
7277 reg_reloaded_contents[src_regno + nr] = nregno;
7278 reg_reloaded_insn[src_regno + nr] = store_insn;
7279 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7280 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7281 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7282 GET_MODE (src_reg)))
7283 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7285 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7287 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7289 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7291 reg_last_reload_reg[nregno] = src_reg;
7296 int num_regs = hard_regno_nregs[nregno][GET_MODE (rld[r].out)];
7298 while (num_regs-- > 0)
7299 reg_last_reload_reg[nregno + num_regs] = 0;
7303 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7306 /* Emit code to perform a reload from IN (which may be a reload register) to
7307 OUT (which may also be a reload register). IN or OUT is from operand
7308 OPNUM with reload type TYPE.
7310 Returns first insn emitted. */
7313 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7315 rtx last = get_last_insn ();
7318 /* If IN is a paradoxical SUBREG, remove it and try to put the
7319 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7320 if (GET_CODE (in) == SUBREG
7321 && (GET_MODE_SIZE (GET_MODE (in))
7322 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7323 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7324 in = SUBREG_REG (in), out = tem;
7325 else if (GET_CODE (out) == SUBREG
7326 && (GET_MODE_SIZE (GET_MODE (out))
7327 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7328 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7329 out = SUBREG_REG (out), in = tem;
7331 /* How to do this reload can get quite tricky. Normally, we are being
7332 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7333 register that didn't get a hard register. In that case we can just
7334 call emit_move_insn.
7336 We can also be asked to reload a PLUS that adds a register or a MEM to
7337 another register, constant or MEM. This can occur during frame pointer
7338 elimination and while reloading addresses. This case is handled by
7339 trying to emit a single insn to perform the add. If it is not valid,
7340 we use a two insn sequence.
7342 Finally, we could be called to handle an 'o' constraint by putting
7343 an address into a register. In that case, we first try to do this
7344 with a named pattern of "reload_load_address". If no such pattern
7345 exists, we just emit a SET insn and hope for the best (it will normally
7346 be valid on machines that use 'o').
7348 This entire process is made complex because reload will never
7349 process the insns we generate here and so we must ensure that
7350 they will fit their constraints and also by the fact that parts of
7351 IN might be being reloaded separately and replaced with spill registers.
7352 Because of this, we are, in some sense, just guessing the right approach
7353 here. The one listed above seems to work.
7355 ??? At some point, this whole thing needs to be rethought. */
7357 if (GET_CODE (in) == PLUS
7358 && (GET_CODE (XEXP (in, 0)) == REG
7359 || GET_CODE (XEXP (in, 0)) == SUBREG
7360 || GET_CODE (XEXP (in, 0)) == MEM)
7361 && (GET_CODE (XEXP (in, 1)) == REG
7362 || GET_CODE (XEXP (in, 1)) == SUBREG
7363 || CONSTANT_P (XEXP (in, 1))
7364 || GET_CODE (XEXP (in, 1)) == MEM))
7366 /* We need to compute the sum of a register or a MEM and another
7367 register, constant, or MEM, and put it into the reload
7368 register. The best possible way of doing this is if the machine
7369 has a three-operand ADD insn that accepts the required operands.
7371 The simplest approach is to try to generate such an insn and see if it
7372 is recognized and matches its constraints. If so, it can be used.
7374 It might be better not to actually emit the insn unless it is valid,
7375 but we need to pass the insn as an operand to `recog' and
7376 `extract_insn' and it is simpler to emit and then delete the insn if
7377 not valid than to dummy things up. */
7379 rtx op0, op1, tem, insn;
7382 op0 = find_replacement (&XEXP (in, 0));
7383 op1 = find_replacement (&XEXP (in, 1));
7385 /* Since constraint checking is strict, commutativity won't be
7386 checked, so we need to do that here to avoid spurious failure
7387 if the add instruction is two-address and the second operand
7388 of the add is the same as the reload reg, which is frequently
7389 the case. If the insn would be A = B + A, rearrange it so
7390 it will be A = A + B as constrain_operands expects. */
7392 if (GET_CODE (XEXP (in, 1)) == REG
7393 && REGNO (out) == REGNO (XEXP (in, 1)))
7394 tem = op0, op0 = op1, op1 = tem;
7396 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7397 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7399 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7400 code = recog_memoized (insn);
7404 extract_insn (insn);
7405 /* We want constrain operands to treat this insn strictly in
7406 its validity determination, i.e., the way it would after reload
7408 if (constrain_operands (1))
7412 delete_insns_since (last);
7414 /* If that failed, we must use a conservative two-insn sequence.
7416 Use a move to copy one operand into the reload register. Prefer
7417 to reload a constant, MEM or pseudo since the move patterns can
7418 handle an arbitrary operand. If OP1 is not a constant, MEM or
7419 pseudo and OP1 is not a valid operand for an add instruction, then
7422 After reloading one of the operands into the reload register, add
7423 the reload register to the output register.
7425 If there is another way to do this for a specific machine, a
7426 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7429 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7431 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7432 || (GET_CODE (op1) == REG
7433 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7434 || (code != CODE_FOR_nothing
7435 && ! ((*insn_data[code].operand[2].predicate)
7436 (op1, insn_data[code].operand[2].mode))))
7437 tem = op0, op0 = op1, op1 = tem;
7439 gen_reload (out, op0, opnum, type);
7441 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7442 This fixes a problem on the 32K where the stack pointer cannot
7443 be used as an operand of an add insn. */
7445 if (rtx_equal_p (op0, op1))
7448 insn = emit_insn (gen_add2_insn (out, op1));
7450 /* If that failed, copy the address register to the reload register.
7451 Then add the constant to the reload register. */
7453 code = recog_memoized (insn);
7457 extract_insn (insn);
7458 /* We want constrain operands to treat this insn strictly in
7459 its validity determination, i.e., the way it would after reload
7461 if (constrain_operands (1))
7463 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7465 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7470 delete_insns_since (last);
7472 gen_reload (out, op1, opnum, type);
7473 insn = emit_insn (gen_add2_insn (out, op0));
7474 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7477 #ifdef SECONDARY_MEMORY_NEEDED
7478 /* If we need a memory location to do the move, do it that way. */
7479 else if ((GET_CODE (in) == REG || GET_CODE (in) == SUBREG)
7480 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7481 && (GET_CODE (out) == REG || GET_CODE (out) == SUBREG)
7482 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7483 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7484 REGNO_REG_CLASS (reg_or_subregno (out)),
7487 /* Get the memory to use and rewrite both registers to its mode. */
7488 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7490 if (GET_MODE (loc) != GET_MODE (out))
7491 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7493 if (GET_MODE (loc) != GET_MODE (in))
7494 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7496 gen_reload (loc, in, opnum, type);
7497 gen_reload (out, loc, opnum, type);
7501 /* If IN is a simple operand, use gen_move_insn. */
7502 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7503 emit_insn (gen_move_insn (out, in));
7505 #ifdef HAVE_reload_load_address
7506 else if (HAVE_reload_load_address)
7507 emit_insn (gen_reload_load_address (out, in));
7510 /* Otherwise, just write (set OUT IN) and hope for the best. */
7512 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7514 /* Return the first insn emitted.
7515 We can not just return get_last_insn, because there may have
7516 been multiple instructions emitted. Also note that gen_move_insn may
7517 emit more than one insn itself, so we can not assume that there is one
7518 insn emitted per emit_insn_before call. */
7520 return last ? NEXT_INSN (last) : get_insns ();
7523 /* Delete a previously made output-reload whose result we now believe
7524 is not needed. First we double-check.
7526 INSN is the insn now being processed.
7527 LAST_RELOAD_REG is the hard register number for which we want to delete
7528 the last output reload.
7529 J is the reload-number that originally used REG. The caller has made
7530 certain that reload J doesn't use REG any longer for input. */
7533 delete_output_reload (rtx insn, int j, int last_reload_reg)
7535 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7536 rtx reg = spill_reg_stored_to[last_reload_reg];
7539 int n_inherited = 0;
7543 /* It is possible that this reload has been only used to set another reload
7544 we eliminated earlier and thus deleted this instruction too. */
7545 if (INSN_DELETED_P (output_reload_insn))
7548 /* Get the raw pseudo-register referred to. */
7550 while (GET_CODE (reg) == SUBREG)
7551 reg = SUBREG_REG (reg);
7552 substed = reg_equiv_memory_loc[REGNO (reg)];
7554 /* This is unsafe if the operand occurs more often in the current
7555 insn than it is inherited. */
7556 for (k = n_reloads - 1; k >= 0; k--)
7558 rtx reg2 = rld[k].in;
7561 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7562 reg2 = rld[k].in_reg;
7564 if (rld[k].out && ! rld[k].out_reg)
7565 reg2 = XEXP (rld[k].in_reg, 0);
7567 while (GET_CODE (reg2) == SUBREG)
7568 reg2 = SUBREG_REG (reg2);
7569 if (rtx_equal_p (reg2, reg))
7571 if (reload_inherited[k] || reload_override_in[k] || k == j)
7574 reg2 = rld[k].out_reg;
7577 while (GET_CODE (reg2) == SUBREG)
7578 reg2 = XEXP (reg2, 0);
7579 if (rtx_equal_p (reg2, reg))
7586 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7588 n_occurrences += count_occurrences (PATTERN (insn),
7589 eliminate_regs (substed, 0,
7591 if (n_occurrences > n_inherited)
7594 /* If the pseudo-reg we are reloading is no longer referenced
7595 anywhere between the store into it and here,
7596 and no jumps or labels intervene, then the value can get
7597 here through the reload reg alone.
7598 Otherwise, give up--return. */
7599 for (i1 = NEXT_INSN (output_reload_insn);
7600 i1 != insn; i1 = NEXT_INSN (i1))
7602 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7604 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7605 && reg_mentioned_p (reg, PATTERN (i1)))
7607 /* If this is USE in front of INSN, we only have to check that
7608 there are no more references than accounted for by inheritance. */
7609 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7611 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7612 i1 = NEXT_INSN (i1);
7614 if (n_occurrences <= n_inherited && i1 == insn)
7620 /* We will be deleting the insn. Remove the spill reg information. */
7621 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
7623 spill_reg_store[last_reload_reg + k] = 0;
7624 spill_reg_stored_to[last_reload_reg + k] = 0;
7627 /* The caller has already checked that REG dies or is set in INSN.
7628 It has also checked that we are optimizing, and thus some
7629 inaccuracies in the debugging information are acceptable.
7630 So we could just delete output_reload_insn. But in some cases
7631 we can improve the debugging information without sacrificing
7632 optimization - maybe even improving the code: See if the pseudo
7633 reg has been completely replaced with reload regs. If so, delete
7634 the store insn and forget we had a stack slot for the pseudo. */
7635 if (rld[j].out != rld[j].in
7636 && REG_N_DEATHS (REGNO (reg)) == 1
7637 && REG_N_SETS (REGNO (reg)) == 1
7638 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7639 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7643 /* We know that it was used only between here and the beginning of
7644 the current basic block. (We also know that the last use before
7645 INSN was the output reload we are thinking of deleting, but never
7646 mind that.) Search that range; see if any ref remains. */
7647 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7649 rtx set = single_set (i2);
7651 /* Uses which just store in the pseudo don't count,
7652 since if they are the only uses, they are dead. */
7653 if (set != 0 && SET_DEST (set) == reg)
7655 if (GET_CODE (i2) == CODE_LABEL
7656 || GET_CODE (i2) == JUMP_INSN)
7658 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7659 && reg_mentioned_p (reg, PATTERN (i2)))
7661 /* Some other ref remains; just delete the output reload we
7663 delete_address_reloads (output_reload_insn, insn);
7664 delete_insn (output_reload_insn);
7669 /* Delete the now-dead stores into this pseudo. Note that this
7670 loop also takes care of deleting output_reload_insn. */
7671 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7673 rtx set = single_set (i2);
7675 if (set != 0 && SET_DEST (set) == reg)
7677 delete_address_reloads (i2, insn);
7680 if (GET_CODE (i2) == CODE_LABEL
7681 || GET_CODE (i2) == JUMP_INSN)
7685 /* For the debugging info, say the pseudo lives in this reload reg. */
7686 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7687 alter_reg (REGNO (reg), -1);
7691 delete_address_reloads (output_reload_insn, insn);
7692 delete_insn (output_reload_insn);
7696 /* We are going to delete DEAD_INSN. Recursively delete loads of
7697 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7698 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7700 delete_address_reloads (rtx dead_insn, rtx current_insn)
7702 rtx set = single_set (dead_insn);
7703 rtx set2, dst, prev, next;
7706 rtx dst = SET_DEST (set);
7707 if (GET_CODE (dst) == MEM)
7708 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7710 /* If we deleted the store from a reloaded post_{in,de}c expression,
7711 we can delete the matching adds. */
7712 prev = PREV_INSN (dead_insn);
7713 next = NEXT_INSN (dead_insn);
7714 if (! prev || ! next)
7716 set = single_set (next);
7717 set2 = single_set (prev);
7719 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7720 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7721 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7723 dst = SET_DEST (set);
7724 if (! rtx_equal_p (dst, SET_DEST (set2))
7725 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7726 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7727 || (INTVAL (XEXP (SET_SRC (set), 1))
7728 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7730 delete_related_insns (prev);
7731 delete_related_insns (next);
7734 /* Subfunction of delete_address_reloads: process registers found in X. */
7736 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
7738 rtx prev, set, dst, i2;
7740 enum rtx_code code = GET_CODE (x);
7744 const char *fmt = GET_RTX_FORMAT (code);
7745 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7748 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7749 else if (fmt[i] == 'E')
7751 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7752 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7759 if (spill_reg_order[REGNO (x)] < 0)
7762 /* Scan backwards for the insn that sets x. This might be a way back due
7764 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7766 code = GET_CODE (prev);
7767 if (code == CODE_LABEL || code == JUMP_INSN)
7769 if (GET_RTX_CLASS (code) != 'i')
7771 if (reg_set_p (x, PATTERN (prev)))
7773 if (reg_referenced_p (x, PATTERN (prev)))
7776 if (! prev || INSN_UID (prev) < reload_first_uid)
7778 /* Check that PREV only sets the reload register. */
7779 set = single_set (prev);
7782 dst = SET_DEST (set);
7783 if (GET_CODE (dst) != REG
7784 || ! rtx_equal_p (dst, x))
7786 if (! reg_set_p (dst, PATTERN (dead_insn)))
7788 /* Check if DST was used in a later insn -
7789 it might have been inherited. */
7790 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7792 if (GET_CODE (i2) == CODE_LABEL)
7796 if (reg_referenced_p (dst, PATTERN (i2)))
7798 /* If there is a reference to the register in the current insn,
7799 it might be loaded in a non-inherited reload. If no other
7800 reload uses it, that means the register is set before
7802 if (i2 == current_insn)
7804 for (j = n_reloads - 1; j >= 0; j--)
7805 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7806 || reload_override_in[j] == dst)
7808 for (j = n_reloads - 1; j >= 0; j--)
7809 if (rld[j].in && rld[j].reg_rtx == dst)
7816 if (GET_CODE (i2) == JUMP_INSN)
7818 /* If DST is still live at CURRENT_INSN, check if it is used for
7819 any reload. Note that even if CURRENT_INSN sets DST, we still
7820 have to check the reloads. */
7821 if (i2 == current_insn)
7823 for (j = n_reloads - 1; j >= 0; j--)
7824 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7825 || reload_override_in[j] == dst)
7827 /* ??? We can't finish the loop here, because dst might be
7828 allocated to a pseudo in this block if no reload in this
7829 block needs any of the classes containing DST - see
7830 spill_hard_reg. There is no easy way to tell this, so we
7831 have to scan till the end of the basic block. */
7833 if (reg_set_p (dst, PATTERN (i2)))
7837 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7838 reg_reloaded_contents[REGNO (dst)] = -1;
7842 /* Output reload-insns to reload VALUE into RELOADREG.
7843 VALUE is an autoincrement or autodecrement RTX whose operand
7844 is a register or memory location;
7845 so reloading involves incrementing that location.
7846 IN is either identical to VALUE, or some cheaper place to reload from.
7848 INC_AMOUNT is the number to increment or decrement by (always positive).
7849 This cannot be deduced from VALUE.
7851 Return the instruction that stores into RELOADREG. */
7854 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
7856 /* REG or MEM to be copied and incremented. */
7857 rtx incloc = XEXP (value, 0);
7858 /* Nonzero if increment after copying. */
7859 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7865 rtx real_in = in == value ? XEXP (in, 0) : in;
7867 /* No hard register is equivalent to this register after
7868 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7869 we could inc/dec that register as well (maybe even using it for
7870 the source), but I'm not sure it's worth worrying about. */
7871 if (GET_CODE (incloc) == REG)
7872 reg_last_reload_reg[REGNO (incloc)] = 0;
7874 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7875 inc_amount = -inc_amount;
7877 inc = GEN_INT (inc_amount);
7879 /* If this is post-increment, first copy the location to the reload reg. */
7880 if (post && real_in != reloadreg)
7881 emit_insn (gen_move_insn (reloadreg, real_in));
7885 /* See if we can directly increment INCLOC. Use a method similar to
7886 that in gen_reload. */
7888 last = get_last_insn ();
7889 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7890 gen_rtx_PLUS (GET_MODE (incloc),
7893 code = recog_memoized (add_insn);
7896 extract_insn (add_insn);
7897 if (constrain_operands (1))
7899 /* If this is a pre-increment and we have incremented the value
7900 where it lives, copy the incremented value to RELOADREG to
7901 be used as an address. */
7904 emit_insn (gen_move_insn (reloadreg, incloc));
7909 delete_insns_since (last);
7912 /* If couldn't do the increment directly, must increment in RELOADREG.
7913 The way we do this depends on whether this is pre- or post-increment.
7914 For pre-increment, copy INCLOC to the reload register, increment it
7915 there, then save back. */
7919 if (in != reloadreg)
7920 emit_insn (gen_move_insn (reloadreg, real_in));
7921 emit_insn (gen_add2_insn (reloadreg, inc));
7922 store = emit_insn (gen_move_insn (incloc, reloadreg));
7927 Because this might be a jump insn or a compare, and because RELOADREG
7928 may not be available after the insn in an input reload, we must do
7929 the incrementation before the insn being reloaded for.
7931 We have already copied IN to RELOADREG. Increment the copy in
7932 RELOADREG, save that back, then decrement RELOADREG so it has
7933 the original value. */
7935 emit_insn (gen_add2_insn (reloadreg, inc));
7936 store = emit_insn (gen_move_insn (incloc, reloadreg));
7937 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7945 add_auto_inc_notes (rtx insn, rtx x)
7947 enum rtx_code code = GET_CODE (x);
7951 if (code == MEM && auto_inc_p (XEXP (x, 0)))
7954 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
7958 /* Scan all the operand sub-expressions. */
7959 fmt = GET_RTX_FORMAT (code);
7960 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7963 add_auto_inc_notes (insn, XEXP (x, i));
7964 else if (fmt[i] == 'E')
7965 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7966 add_auto_inc_notes (insn, XVECEXP (x, i, j));
7971 /* Copy EH notes from an insn to its reloads. */
7973 copy_eh_notes (rtx insn, rtx x)
7975 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
7978 for (; x != 0; x = NEXT_INSN (x))
7980 if (may_trap_p (PATTERN (x)))
7982 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
7988 /* This is used by reload pass, that does emit some instructions after
7989 abnormal calls moving basic block end, but in fact it wants to emit
7990 them on the edge. Looks for abnormal call edges, find backward the
7991 proper call and fix the damage.
7993 Similar handle instructions throwing exceptions internally. */
7995 fixup_abnormal_edges (void)
7997 bool inserted = false;
8004 /* Look for cases we are interested in - calls or instructions causing
8006 for (e = bb->succ; e; e = e->succ_next)
8008 if (e->flags & EDGE_ABNORMAL_CALL)
8010 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8011 == (EDGE_ABNORMAL | EDGE_EH))
8014 if (e && GET_CODE (BB_END (bb)) != CALL_INSN
8015 && !can_throw_internal (BB_END (bb)))
8017 rtx insn = BB_END (bb), stop = NEXT_INSN (BB_END (bb));
8019 for (e = bb->succ; e; e = e->succ_next)
8020 if (e->flags & EDGE_FALLTHRU)
8022 /* Get past the new insns generated. Allow notes, as the insns may
8023 be already deleted. */
8024 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE)
8025 && !can_throw_internal (insn)
8026 && insn != BB_HEAD (bb))
8027 insn = PREV_INSN (insn);
8028 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn))
8032 insn = NEXT_INSN (insn);
8033 while (insn && insn != stop)
8035 next = NEXT_INSN (insn);
8040 /* Sometimes there's still the return value USE.
8041 If it's placed after a trapping call (i.e. that
8042 call is the last insn anyway), we have no fallthru
8043 edge. Simply delete this use and don't try to insert
8044 on the non-existent edge. */
8045 if (GET_CODE (PATTERN (insn)) != USE)
8047 /* We're not deleting it, we're moving it. */
8048 INSN_DELETED_P (insn) = 0;
8049 PREV_INSN (insn) = NULL_RTX;
8050 NEXT_INSN (insn) = NULL_RTX;
8052 insert_insn_on_edge (insn, e);
8059 /* We've possibly turned single trapping insn into multiple ones. */
8060 if (flag_non_call_exceptions)
8063 blocks = sbitmap_alloc (last_basic_block);
8064 sbitmap_ones (blocks);
8065 find_many_sub_basic_blocks (blocks);
8068 commit_edge_insertions ();
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