1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "addresses.h"
39 #include "basic-block.h"
51 /* This file contains the reload pass of the compiler, which is
52 run after register allocation has been done. It checks that
53 each insn is valid (operands required to be in registers really
54 are in registers of the proper class) and fixes up invalid ones
55 by copying values temporarily into registers for the insns
58 The results of register allocation are described by the vector
59 reg_renumber; the insns still contain pseudo regs, but reg_renumber
60 can be used to find which hard reg, if any, a pseudo reg is in.
62 The technique we always use is to free up a few hard regs that are
63 called ``reload regs'', and for each place where a pseudo reg
64 must be in a hard reg, copy it temporarily into one of the reload regs.
66 Reload regs are allocated locally for every instruction that needs
67 reloads. When there are pseudos which are allocated to a register that
68 has been chosen as a reload reg, such pseudos must be ``spilled''.
69 This means that they go to other hard regs, or to stack slots if no other
70 available hard regs can be found. Spilling can invalidate more
71 insns, requiring additional need for reloads, so we must keep checking
72 until the process stabilizes.
74 For machines with different classes of registers, we must keep track
75 of the register class needed for each reload, and make sure that
76 we allocate enough reload registers of each class.
78 The file reload.c contains the code that checks one insn for
79 validity and reports the reloads that it needs. This file
80 is in charge of scanning the entire rtl code, accumulating the
81 reload needs, spilling, assigning reload registers to use for
82 fixing up each insn, and generating the new insns to copy values
83 into the reload registers. */
85 /* During reload_as_needed, element N contains a REG rtx for the hard reg
86 into which reg N has been reloaded (perhaps for a previous insn). */
87 static rtx *reg_last_reload_reg;
89 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
90 for an output reload that stores into reg N. */
91 static regset_head reg_has_output_reload;
93 /* Indicates which hard regs are reload-registers for an output reload
94 in the current insn. */
95 static HARD_REG_SET reg_is_output_reload;
97 /* Element N is the constant value to which pseudo reg N is equivalent,
98 or zero if pseudo reg N is not equivalent to a constant.
99 find_reloads looks at this in order to replace pseudo reg N
100 with the constant it stands for. */
101 rtx *reg_equiv_constant;
103 /* Element N is an invariant value to which pseudo reg N is equivalent.
104 eliminate_regs_in_insn uses this to replace pseudos in particular
106 rtx *reg_equiv_invariant;
108 /* Element N is a memory location to which pseudo reg N is equivalent,
109 prior to any register elimination (such as frame pointer to stack
110 pointer). Depending on whether or not it is a valid address, this value
111 is transferred to either reg_equiv_address or reg_equiv_mem. */
112 rtx *reg_equiv_memory_loc;
114 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
115 collector can keep track of what is inside. */
116 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
118 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
119 This is used when the address is not valid as a memory address
120 (because its displacement is too big for the machine.) */
121 rtx *reg_equiv_address;
123 /* Element N is the memory slot to which pseudo reg N is equivalent,
124 or zero if pseudo reg N is not equivalent to a memory slot. */
127 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
128 alternate representations of the location of pseudo reg N. */
129 rtx *reg_equiv_alt_mem_list;
131 /* Widest width in which each pseudo reg is referred to (via subreg). */
132 static unsigned int *reg_max_ref_width;
134 /* Element N is the list of insns that initialized reg N from its equivalent
135 constant or memory slot. */
137 int reg_equiv_init_size;
139 /* Vector to remember old contents of reg_renumber before spilling. */
140 static short *reg_old_renumber;
142 /* During reload_as_needed, element N contains the last pseudo regno reloaded
143 into hard register N. If that pseudo reg occupied more than one register,
144 reg_reloaded_contents points to that pseudo for each spill register in
145 use; all of these must remain set for an inheritance to occur. */
146 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
148 /* During reload_as_needed, element N contains the insn for which
149 hard register N was last used. Its contents are significant only
150 when reg_reloaded_valid is set for this register. */
151 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
153 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
154 static HARD_REG_SET reg_reloaded_valid;
155 /* Indicate if the register was dead at the end of the reload.
156 This is only valid if reg_reloaded_contents is set and valid. */
157 static HARD_REG_SET reg_reloaded_dead;
159 /* Indicate whether the register's current value is one that is not
160 safe to retain across a call, even for registers that are normally
161 call-saved. This is only meaningful for members of reg_reloaded_valid. */
162 static HARD_REG_SET reg_reloaded_call_part_clobbered;
164 /* Number of spill-regs so far; number of valid elements of spill_regs. */
167 /* In parallel with spill_regs, contains REG rtx's for those regs.
168 Holds the last rtx used for any given reg, or 0 if it has never
169 been used for spilling yet. This rtx is reused, provided it has
171 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
173 /* In parallel with spill_regs, contains nonzero for a spill reg
174 that was stored after the last time it was used.
175 The precise value is the insn generated to do the store. */
176 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
178 /* This is the register that was stored with spill_reg_store. This is a
179 copy of reload_out / reload_out_reg when the value was stored; if
180 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
181 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
183 /* This table is the inverse mapping of spill_regs:
184 indexed by hard reg number,
185 it contains the position of that reg in spill_regs,
186 or -1 for something that is not in spill_regs.
188 ?!? This is no longer accurate. */
189 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
191 /* This reg set indicates registers that can't be used as spill registers for
192 the currently processed insn. These are the hard registers which are live
193 during the insn, but not allocated to pseudos, as well as fixed
195 static HARD_REG_SET bad_spill_regs;
197 /* These are the hard registers that can't be used as spill register for any
198 insn. This includes registers used for user variables and registers that
199 we can't eliminate. A register that appears in this set also can't be used
200 to retry register allocation. */
201 static HARD_REG_SET bad_spill_regs_global;
203 /* Describes order of use of registers for reloading
204 of spilled pseudo-registers. `n_spills' is the number of
205 elements that are actually valid; new ones are added at the end.
207 Both spill_regs and spill_reg_order are used on two occasions:
208 once during find_reload_regs, where they keep track of the spill registers
209 for a single insn, but also during reload_as_needed where they show all
210 the registers ever used by reload. For the latter case, the information
211 is calculated during finish_spills. */
212 static short spill_regs[FIRST_PSEUDO_REGISTER];
214 /* This vector of reg sets indicates, for each pseudo, which hard registers
215 may not be used for retrying global allocation because the register was
216 formerly spilled from one of them. If we allowed reallocating a pseudo to
217 a register that it was already allocated to, reload might not
219 static HARD_REG_SET *pseudo_previous_regs;
221 /* This vector of reg sets indicates, for each pseudo, which hard
222 registers may not be used for retrying global allocation because they
223 are used as spill registers during one of the insns in which the
225 static HARD_REG_SET *pseudo_forbidden_regs;
227 /* All hard regs that have been used as spill registers for any insn are
228 marked in this set. */
229 static HARD_REG_SET used_spill_regs;
231 /* Index of last register assigned as a spill register. We allocate in
232 a round-robin fashion. */
233 static int last_spill_reg;
235 /* Nonzero if indirect addressing is supported on the machine; this means
236 that spilling (REG n) does not require reloading it into a register in
237 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
238 value indicates the level of indirect addressing supported, e.g., two
239 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
241 static char spill_indirect_levels;
243 /* Nonzero if indirect addressing is supported when the innermost MEM is
244 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
245 which these are valid is the same as spill_indirect_levels, above. */
246 char indirect_symref_ok;
248 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
249 char double_reg_address_ok;
251 /* Record the stack slot for each spilled hard register. */
252 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
254 /* Width allocated so far for that stack slot. */
255 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
257 /* Record which pseudos needed to be spilled. */
258 static regset_head spilled_pseudos;
260 /* Used for communication between order_regs_for_reload and count_pseudo.
261 Used to avoid counting one pseudo twice. */
262 static regset_head pseudos_counted;
264 /* First uid used by insns created by reload in this function.
265 Used in find_equiv_reg. */
266 int reload_first_uid;
268 /* Flag set by local-alloc or global-alloc if anything is live in
269 a call-clobbered reg across calls. */
270 int caller_save_needed;
272 /* Set to 1 while reload_as_needed is operating.
273 Required by some machines to handle any generated moves differently. */
274 int reload_in_progress = 0;
276 /* These arrays record the insn_code of insns that may be needed to
277 perform input and output reloads of special objects. They provide a
278 place to pass a scratch register. */
279 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
280 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
282 /* This obstack is used for allocation of rtl during register elimination.
283 The allocated storage can be freed once find_reloads has processed the
285 static struct obstack reload_obstack;
287 /* Points to the beginning of the reload_obstack. All insn_chain structures
288 are allocated first. */
289 static char *reload_startobj;
291 /* The point after all insn_chain structures. Used to quickly deallocate
292 memory allocated in copy_reloads during calculate_needs_all_insns. */
293 static char *reload_firstobj;
295 /* This points before all local rtl generated by register elimination.
296 Used to quickly free all memory after processing one insn. */
297 static char *reload_insn_firstobj;
299 /* List of insn_chain instructions, one for every insn that reload needs to
301 struct insn_chain *reload_insn_chain;
303 /* List of all insns needing reloads. */
304 static struct insn_chain *insns_need_reload;
306 /* This structure is used to record information about register eliminations.
307 Each array entry describes one possible way of eliminating a register
308 in favor of another. If there is more than one way of eliminating a
309 particular register, the most preferred should be specified first. */
313 int from; /* Register number to be eliminated. */
314 int to; /* Register number used as replacement. */
315 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
316 int can_eliminate; /* Nonzero if this elimination can be done. */
317 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
318 insns made by reload. */
319 HOST_WIDE_INT offset; /* Current offset between the two regs. */
320 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
321 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
322 rtx from_rtx; /* REG rtx for the register to be eliminated.
323 We cannot simply compare the number since
324 we might then spuriously replace a hard
325 register corresponding to a pseudo
326 assigned to the reg to be eliminated. */
327 rtx to_rtx; /* REG rtx for the replacement. */
330 static struct elim_table *reg_eliminate = 0;
332 /* This is an intermediate structure to initialize the table. It has
333 exactly the members provided by ELIMINABLE_REGS. */
334 static const struct elim_table_1
338 } reg_eliminate_1[] =
340 /* If a set of eliminable registers was specified, define the table from it.
341 Otherwise, default to the normal case of the frame pointer being
342 replaced by the stack pointer. */
344 #ifdef ELIMINABLE_REGS
347 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
350 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
352 /* Record the number of pending eliminations that have an offset not equal
353 to their initial offset. If nonzero, we use a new copy of each
354 replacement result in any insns encountered. */
355 int num_not_at_initial_offset;
357 /* Count the number of registers that we may be able to eliminate. */
358 static int num_eliminable;
359 /* And the number of registers that are equivalent to a constant that
360 can be eliminated to frame_pointer / arg_pointer + constant. */
361 static int num_eliminable_invariants;
363 /* For each label, we record the offset of each elimination. If we reach
364 a label by more than one path and an offset differs, we cannot do the
365 elimination. This information is indexed by the difference of the
366 number of the label and the first label number. We can't offset the
367 pointer itself as this can cause problems on machines with segmented
368 memory. The first table is an array of flags that records whether we
369 have yet encountered a label and the second table is an array of arrays,
370 one entry in the latter array for each elimination. */
372 static int first_label_num;
373 static char *offsets_known_at;
374 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
376 /* Number of labels in the current function. */
378 static int num_labels;
380 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
381 static void maybe_fix_stack_asms (void);
382 static void copy_reloads (struct insn_chain *);
383 static void calculate_needs_all_insns (int);
384 static int find_reg (struct insn_chain *, int);
385 static void find_reload_regs (struct insn_chain *);
386 static void select_reload_regs (void);
387 static void delete_caller_save_insns (void);
389 static void spill_failure (rtx, enum reg_class);
390 static void count_spilled_pseudo (int, int, int);
391 static void delete_dead_insn (rtx);
392 static void alter_reg (int, int);
393 static void set_label_offsets (rtx, rtx, int);
394 static void check_eliminable_occurrences (rtx);
395 static void elimination_effects (rtx, enum machine_mode);
396 static int eliminate_regs_in_insn (rtx, int);
397 static void update_eliminable_offsets (void);
398 static void mark_not_eliminable (rtx, const_rtx, void *);
399 static void set_initial_elim_offsets (void);
400 static bool verify_initial_elim_offsets (void);
401 static void set_initial_label_offsets (void);
402 static void set_offsets_for_label (rtx);
403 static void init_elim_table (void);
404 static void update_eliminables (HARD_REG_SET *);
405 static void spill_hard_reg (unsigned int, int);
406 static int finish_spills (int);
407 static void scan_paradoxical_subregs (rtx);
408 static void count_pseudo (int);
409 static void order_regs_for_reload (struct insn_chain *);
410 static void reload_as_needed (int);
411 static void forget_old_reloads_1 (rtx, const_rtx, void *);
412 static void forget_marked_reloads (regset);
413 static int reload_reg_class_lower (const void *, const void *);
414 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
416 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
418 static int reload_reg_free_p (unsigned int, int, enum reload_type);
419 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
421 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
423 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
424 static int allocate_reload_reg (struct insn_chain *, int, int);
425 static int conflicts_with_override (rtx);
426 static void failed_reload (rtx, int);
427 static int set_reload_reg (int, int);
428 static void choose_reload_regs_init (struct insn_chain *, rtx *);
429 static void choose_reload_regs (struct insn_chain *);
430 static void merge_assigned_reloads (rtx);
431 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
433 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
435 static void do_input_reload (struct insn_chain *, struct reload *, int);
436 static void do_output_reload (struct insn_chain *, struct reload *, int);
437 static void emit_reload_insns (struct insn_chain *);
438 static void delete_output_reload (rtx, int, int, rtx);
439 static void delete_address_reloads (rtx, rtx);
440 static void delete_address_reloads_1 (rtx, rtx, rtx);
441 static rtx inc_for_reload (rtx, rtx, rtx, int);
443 static void add_auto_inc_notes (rtx, rtx);
445 static void copy_eh_notes (rtx, rtx);
446 static int reloads_conflict (int, int);
447 static rtx gen_reload (rtx, rtx, int, enum reload_type);
448 static rtx emit_insn_if_valid_for_reload (rtx);
450 /* Initialize the reload pass. This is called at the beginning of compilation
451 and may be called again if the target is reinitialized. */
458 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
459 Set spill_indirect_levels to the number of levels such addressing is
460 permitted, zero if it is not permitted at all. */
463 = gen_rtx_MEM (Pmode,
466 LAST_VIRTUAL_REGISTER + 1),
468 spill_indirect_levels = 0;
470 while (memory_address_p (QImode, tem))
472 spill_indirect_levels++;
473 tem = gen_rtx_MEM (Pmode, tem);
476 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
478 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
479 indirect_symref_ok = memory_address_p (QImode, tem);
481 /* See if reg+reg is a valid (and offsettable) address. */
483 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
485 tem = gen_rtx_PLUS (Pmode,
486 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
487 gen_rtx_REG (Pmode, i));
489 /* This way, we make sure that reg+reg is an offsettable address. */
490 tem = plus_constant (tem, 4);
492 if (memory_address_p (QImode, tem))
494 double_reg_address_ok = 1;
499 /* Initialize obstack for our rtl allocation. */
500 gcc_obstack_init (&reload_obstack);
501 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
503 INIT_REG_SET (&spilled_pseudos);
504 INIT_REG_SET (&pseudos_counted);
507 /* List of insn chains that are currently unused. */
508 static struct insn_chain *unused_insn_chains = 0;
510 /* Allocate an empty insn_chain structure. */
512 new_insn_chain (void)
514 struct insn_chain *c;
516 if (unused_insn_chains == 0)
518 c = XOBNEW (&reload_obstack, struct insn_chain);
519 INIT_REG_SET (&c->live_throughout);
520 INIT_REG_SET (&c->dead_or_set);
524 c = unused_insn_chains;
525 unused_insn_chains = c->next;
527 c->is_caller_save_insn = 0;
528 c->need_operand_change = 0;
534 /* Small utility function to set all regs in hard reg set TO which are
535 allocated to pseudos in regset FROM. */
538 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
541 reg_set_iterator rsi;
543 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
545 int r = reg_renumber[regno];
549 /* reload_combine uses the information from
550 DF_LIVE_IN (BASIC_BLOCK), which might still
551 contain registers that have not actually been allocated
552 since they have an equivalence. */
553 gcc_assert (reload_completed);
556 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
560 /* Replace all pseudos found in LOC with their corresponding
564 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
577 unsigned int regno = REGNO (x);
579 if (regno < FIRST_PSEUDO_REGISTER)
582 x = eliminate_regs (x, mem_mode, usage);
586 replace_pseudos_in (loc, mem_mode, usage);
590 if (reg_equiv_constant[regno])
591 *loc = reg_equiv_constant[regno];
592 else if (reg_equiv_mem[regno])
593 *loc = reg_equiv_mem[regno];
594 else if (reg_equiv_address[regno])
595 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
598 gcc_assert (!REG_P (regno_reg_rtx[regno])
599 || REGNO (regno_reg_rtx[regno]) != regno);
600 *loc = regno_reg_rtx[regno];
605 else if (code == MEM)
607 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
611 /* Process each of our operands recursively. */
612 fmt = GET_RTX_FORMAT (code);
613 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
615 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
616 else if (*fmt == 'E')
617 for (j = 0; j < XVECLEN (x, i); j++)
618 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
621 /* Determine if the current function has an exception receiver block
622 that reaches the exit block via non-exceptional edges */
625 has_nonexceptional_receiver (void)
629 basic_block *tos, *worklist, bb;
631 /* If we're not optimizing, then just err on the safe side. */
635 /* First determine which blocks can reach exit via normal paths. */
636 tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1);
639 bb->flags &= ~BB_REACHABLE;
641 /* Place the exit block on our worklist. */
642 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
643 *tos++ = EXIT_BLOCK_PTR;
645 /* Iterate: find everything reachable from what we've already seen. */
646 while (tos != worklist)
650 FOR_EACH_EDGE (e, ei, bb->preds)
651 if (!(e->flags & EDGE_ABNORMAL))
653 basic_block src = e->src;
655 if (!(src->flags & BB_REACHABLE))
657 src->flags |= BB_REACHABLE;
664 /* Now see if there's a reachable block with an exceptional incoming
667 if (bb->flags & BB_REACHABLE)
668 FOR_EACH_EDGE (e, ei, bb->preds)
669 if (e->flags & EDGE_ABNORMAL)
672 /* No exceptional block reached exit unexceptionally. */
677 /* Global variables used by reload and its subroutines. */
679 /* Set during calculate_needs if an insn needs register elimination. */
680 static int something_needs_elimination;
681 /* Set during calculate_needs if an insn needs an operand changed. */
682 static int something_needs_operands_changed;
684 /* Nonzero means we couldn't get enough spill regs. */
687 /* Main entry point for the reload pass.
689 FIRST is the first insn of the function being compiled.
691 GLOBAL nonzero means we were called from global_alloc
692 and should attempt to reallocate any pseudoregs that we
693 displace from hard regs we will use for reloads.
694 If GLOBAL is zero, we do not have enough information to do that,
695 so any pseudo reg that is spilled must go to the stack.
697 Return value is nonzero if reload failed
698 and we must not do any more for this function. */
701 reload (rtx first, int global)
705 struct elim_table *ep;
708 /* Make sure even insns with volatile mem refs are recognizable. */
713 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
715 /* Make sure that the last insn in the chain
716 is not something that needs reloading. */
717 emit_note (NOTE_INSN_DELETED);
719 /* Enable find_equiv_reg to distinguish insns made by reload. */
720 reload_first_uid = get_max_uid ();
722 #ifdef SECONDARY_MEMORY_NEEDED
723 /* Initialize the secondary memory table. */
724 clear_secondary_mem ();
727 /* We don't have a stack slot for any spill reg yet. */
728 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
729 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
731 /* Initialize the save area information for caller-save, in case some
735 /* Compute which hard registers are now in use
736 as homes for pseudo registers.
737 This is done here rather than (eg) in global_alloc
738 because this point is reached even if not optimizing. */
739 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
742 /* A function that has a nonlocal label that can reach the exit
743 block via non-exceptional paths must save all call-saved
745 if (cfun->has_nonlocal_label
746 && has_nonexceptional_receiver ())
747 crtl->saves_all_registers = 1;
749 if (crtl->saves_all_registers)
750 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
751 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
752 df_set_regs_ever_live (i, true);
754 /* Find all the pseudo registers that didn't get hard regs
755 but do have known equivalent constants or memory slots.
756 These include parameters (known equivalent to parameter slots)
757 and cse'd or loop-moved constant memory addresses.
759 Record constant equivalents in reg_equiv_constant
760 so they will be substituted by find_reloads.
761 Record memory equivalents in reg_mem_equiv so they can
762 be substituted eventually by altering the REG-rtx's. */
764 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
765 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
766 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
767 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
768 reg_equiv_address = XCNEWVEC (rtx, max_regno);
769 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
770 reg_old_renumber = XCNEWVEC (short, max_regno);
771 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
772 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
773 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
775 CLEAR_HARD_REG_SET (bad_spill_regs_global);
777 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
778 to. Also find all paradoxical subregs and find largest such for
781 num_eliminable_invariants = 0;
782 for (insn = first; insn; insn = NEXT_INSN (insn))
784 rtx set = single_set (insn);
786 /* We may introduce USEs that we want to remove at the end, so
787 we'll mark them with QImode. Make sure there are no
788 previously-marked insns left by say regmove. */
789 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
790 && GET_MODE (insn) != VOIDmode)
791 PUT_MODE (insn, VOIDmode);
794 scan_paradoxical_subregs (PATTERN (insn));
796 if (set != 0 && REG_P (SET_DEST (set)))
798 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
804 i = REGNO (SET_DEST (set));
807 if (i <= LAST_VIRTUAL_REGISTER)
810 if (! function_invariant_p (x)
812 /* A function invariant is often CONSTANT_P but may
813 include a register. We promise to only pass
814 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
816 && LEGITIMATE_PIC_OPERAND_P (x)))
818 /* It can happen that a REG_EQUIV note contains a MEM
819 that is not a legitimate memory operand. As later
820 stages of reload assume that all addresses found
821 in the reg_equiv_* arrays were originally legitimate,
822 we ignore such REG_EQUIV notes. */
823 if (memory_operand (x, VOIDmode))
825 /* Always unshare the equivalence, so we can
826 substitute into this insn without touching the
828 reg_equiv_memory_loc[i] = copy_rtx (x);
830 else if (function_invariant_p (x))
832 if (GET_CODE (x) == PLUS)
834 /* This is PLUS of frame pointer and a constant,
835 and might be shared. Unshare it. */
836 reg_equiv_invariant[i] = copy_rtx (x);
837 num_eliminable_invariants++;
839 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
841 reg_equiv_invariant[i] = x;
842 num_eliminable_invariants++;
844 else if (LEGITIMATE_CONSTANT_P (x))
845 reg_equiv_constant[i] = x;
848 reg_equiv_memory_loc[i]
849 = force_const_mem (GET_MODE (SET_DEST (set)), x);
850 if (! reg_equiv_memory_loc[i])
851 reg_equiv_init[i] = NULL_RTX;
856 reg_equiv_init[i] = NULL_RTX;
861 reg_equiv_init[i] = NULL_RTX;
866 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
867 if (reg_equiv_init[i])
869 fprintf (dump_file, "init_insns for %u: ", i);
870 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
871 fprintf (dump_file, "\n");
876 first_label_num = get_first_label_num ();
877 num_labels = max_label_num () - first_label_num;
879 /* Allocate the tables used to store offset information at labels. */
880 /* We used to use alloca here, but the size of what it would try to
881 allocate would occasionally cause it to exceed the stack limit and
882 cause a core dump. */
883 offsets_known_at = XNEWVEC (char, num_labels);
884 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
886 /* Alter each pseudo-reg rtx to contain its hard reg number.
887 Assign stack slots to the pseudos that lack hard regs or equivalents.
888 Do not touch virtual registers. */
890 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
893 /* If we have some registers we think can be eliminated, scan all insns to
894 see if there is an insn that sets one of these registers to something
895 other than itself plus a constant. If so, the register cannot be
896 eliminated. Doing this scan here eliminates an extra pass through the
897 main reload loop in the most common case where register elimination
899 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
901 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
903 maybe_fix_stack_asms ();
905 insns_need_reload = 0;
906 something_needs_elimination = 0;
908 /* Initialize to -1, which means take the first spill register. */
911 /* Spill any hard regs that we know we can't eliminate. */
912 CLEAR_HARD_REG_SET (used_spill_regs);
913 /* There can be multiple ways to eliminate a register;
914 they should be listed adjacently.
915 Elimination for any register fails only if all possible ways fail. */
916 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
919 int can_eliminate = 0;
922 can_eliminate |= ep->can_eliminate;
925 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
927 spill_hard_reg (from, 1);
930 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
931 if (frame_pointer_needed)
932 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
934 finish_spills (global);
936 /* From now on, we may need to generate moves differently. We may also
937 allow modifications of insns which cause them to not be recognized.
938 Any such modifications will be cleaned up during reload itself. */
939 reload_in_progress = 1;
941 /* This loop scans the entire function each go-round
942 and repeats until one repetition spills no additional hard regs. */
945 int something_changed;
947 HOST_WIDE_INT starting_frame_size;
949 starting_frame_size = get_frame_size ();
951 set_initial_elim_offsets ();
952 set_initial_label_offsets ();
954 /* For each pseudo register that has an equivalent location defined,
955 try to eliminate any eliminable registers (such as the frame pointer)
956 assuming initial offsets for the replacement register, which
959 If the resulting location is directly addressable, substitute
960 the MEM we just got directly for the old REG.
962 If it is not addressable but is a constant or the sum of a hard reg
963 and constant, it is probably not addressable because the constant is
964 out of range, in that case record the address; we will generate
965 hairy code to compute the address in a register each time it is
966 needed. Similarly if it is a hard register, but one that is not
967 valid as an address register.
969 If the location is not addressable, but does not have one of the
970 above forms, assign a stack slot. We have to do this to avoid the
971 potential of producing lots of reloads if, e.g., a location involves
972 a pseudo that didn't get a hard register and has an equivalent memory
973 location that also involves a pseudo that didn't get a hard register.
975 Perhaps at some point we will improve reload_when_needed handling
976 so this problem goes away. But that's very hairy. */
978 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
979 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
981 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
983 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
985 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
986 else if (CONSTANT_P (XEXP (x, 0))
987 || (REG_P (XEXP (x, 0))
988 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
989 || (GET_CODE (XEXP (x, 0)) == PLUS
990 && REG_P (XEXP (XEXP (x, 0), 0))
991 && (REGNO (XEXP (XEXP (x, 0), 0))
992 < FIRST_PSEUDO_REGISTER)
993 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
994 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
997 /* Make a new stack slot. Then indicate that something
998 changed so we go back and recompute offsets for
999 eliminable registers because the allocation of memory
1000 below might change some offset. reg_equiv_{mem,address}
1001 will be set up for this pseudo on the next pass around
1003 reg_equiv_memory_loc[i] = 0;
1004 reg_equiv_init[i] = 0;
1009 if (caller_save_needed)
1010 setup_save_areas ();
1012 /* If we allocated another stack slot, redo elimination bookkeeping. */
1013 if (starting_frame_size != get_frame_size ())
1015 if (starting_frame_size && crtl->stack_alignment_needed)
1017 /* If we have a stack frame, we must align it now. The
1018 stack size may be a part of the offset computation for
1019 register elimination. So if this changes the stack size,
1020 then repeat the elimination bookkeeping. We don't
1021 realign when there is no stack, as that will cause a
1022 stack frame when none is needed should
1023 STARTING_FRAME_OFFSET not be already aligned to
1025 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
1026 if (starting_frame_size != get_frame_size ())
1030 if (caller_save_needed)
1032 save_call_clobbered_regs ();
1033 /* That might have allocated new insn_chain structures. */
1034 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1037 calculate_needs_all_insns (global);
1039 CLEAR_REG_SET (&spilled_pseudos);
1042 something_changed = 0;
1044 /* If we allocated any new memory locations, make another pass
1045 since it might have changed elimination offsets. */
1046 if (starting_frame_size != get_frame_size ())
1047 something_changed = 1;
1049 /* Even if the frame size remained the same, we might still have
1050 changed elimination offsets, e.g. if find_reloads called
1051 force_const_mem requiring the back end to allocate a constant
1052 pool base register that needs to be saved on the stack. */
1053 else if (!verify_initial_elim_offsets ())
1054 something_changed = 1;
1057 HARD_REG_SET to_spill;
1058 CLEAR_HARD_REG_SET (to_spill);
1059 update_eliminables (&to_spill);
1060 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
1062 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1063 if (TEST_HARD_REG_BIT (to_spill, i))
1065 spill_hard_reg (i, 1);
1068 /* Regardless of the state of spills, if we previously had
1069 a register that we thought we could eliminate, but now can
1070 not eliminate, we must run another pass.
1072 Consider pseudos which have an entry in reg_equiv_* which
1073 reference an eliminable register. We must make another pass
1074 to update reg_equiv_* so that we do not substitute in the
1075 old value from when we thought the elimination could be
1077 something_changed = 1;
1081 select_reload_regs ();
1085 if (insns_need_reload != 0 || did_spill)
1086 something_changed |= finish_spills (global);
1088 if (! something_changed)
1091 if (caller_save_needed)
1092 delete_caller_save_insns ();
1094 obstack_free (&reload_obstack, reload_firstobj);
1097 /* If global-alloc was run, notify it of any register eliminations we have
1100 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1101 if (ep->can_eliminate)
1102 mark_elimination (ep->from, ep->to);
1104 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1105 If that insn didn't set the register (i.e., it copied the register to
1106 memory), just delete that insn instead of the equivalencing insn plus
1107 anything now dead. If we call delete_dead_insn on that insn, we may
1108 delete the insn that actually sets the register if the register dies
1109 there and that is incorrect. */
1111 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1113 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1116 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1118 rtx equiv_insn = XEXP (list, 0);
1120 /* If we already deleted the insn or if it may trap, we can't
1121 delete it. The latter case shouldn't happen, but can
1122 if an insn has a variable address, gets a REG_EH_REGION
1123 note added to it, and then gets converted into a load
1124 from a constant address. */
1125 if (NOTE_P (equiv_insn)
1126 || can_throw_internal (equiv_insn))
1128 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1129 delete_dead_insn (equiv_insn);
1131 SET_INSN_DELETED (equiv_insn);
1136 /* Use the reload registers where necessary
1137 by generating move instructions to move the must-be-register
1138 values into or out of the reload registers. */
1140 if (insns_need_reload != 0 || something_needs_elimination
1141 || something_needs_operands_changed)
1143 HOST_WIDE_INT old_frame_size = get_frame_size ();
1145 reload_as_needed (global);
1147 gcc_assert (old_frame_size == get_frame_size ());
1149 gcc_assert (verify_initial_elim_offsets ());
1152 /* If we were able to eliminate the frame pointer, show that it is no
1153 longer live at the start of any basic block. If it ls live by
1154 virtue of being in a pseudo, that pseudo will be marked live
1155 and hence the frame pointer will be known to be live via that
1158 if (! frame_pointer_needed)
1160 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1162 /* Come here (with failure set nonzero) if we can't get enough spill
1166 CLEAR_REG_SET (&spilled_pseudos);
1167 reload_in_progress = 0;
1169 /* Now eliminate all pseudo regs by modifying them into
1170 their equivalent memory references.
1171 The REG-rtx's for the pseudos are modified in place,
1172 so all insns that used to refer to them now refer to memory.
1174 For a reg that has a reg_equiv_address, all those insns
1175 were changed by reloading so that no insns refer to it any longer;
1176 but the DECL_RTL of a variable decl may refer to it,
1177 and if so this causes the debugging info to mention the variable. */
1179 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1183 if (reg_equiv_mem[i])
1184 addr = XEXP (reg_equiv_mem[i], 0);
1186 if (reg_equiv_address[i])
1187 addr = reg_equiv_address[i];
1191 if (reg_renumber[i] < 0)
1193 rtx reg = regno_reg_rtx[i];
1195 REG_USERVAR_P (reg) = 0;
1196 PUT_CODE (reg, MEM);
1197 XEXP (reg, 0) = addr;
1198 if (reg_equiv_memory_loc[i])
1199 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1202 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1203 MEM_ATTRS (reg) = 0;
1205 MEM_NOTRAP_P (reg) = 1;
1207 else if (reg_equiv_mem[i])
1208 XEXP (reg_equiv_mem[i], 0) = addr;
1212 /* We must set reload_completed now since the cleanup_subreg_operands call
1213 below will re-recognize each insn and reload may have generated insns
1214 which are only valid during and after reload. */
1215 reload_completed = 1;
1217 /* Make a pass over all the insns and delete all USEs which we inserted
1218 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1219 notes. Delete all CLOBBER insns, except those that refer to the return
1220 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1221 from misarranging variable-array code, and simplify (subreg (reg))
1222 operands. Strip and regenerate REG_INC notes that may have been moved
1225 for (insn = first; insn; insn = NEXT_INSN (insn))
1231 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1232 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1234 if ((GET_CODE (PATTERN (insn)) == USE
1235 /* We mark with QImode USEs introduced by reload itself. */
1236 && (GET_MODE (insn) == QImode
1237 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1238 || (GET_CODE (PATTERN (insn)) == CLOBBER
1239 && (!MEM_P (XEXP (PATTERN (insn), 0))
1240 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1241 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1242 && XEXP (XEXP (PATTERN (insn), 0), 0)
1243 != stack_pointer_rtx))
1244 && (!REG_P (XEXP (PATTERN (insn), 0))
1245 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1251 /* Some CLOBBERs may survive until here and still reference unassigned
1252 pseudos with const equivalent, which may in turn cause ICE in later
1253 passes if the reference remains in place. */
1254 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1255 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1256 VOIDmode, PATTERN (insn));
1258 /* Discard obvious no-ops, even without -O. This optimization
1259 is fast and doesn't interfere with debugging. */
1260 if (NONJUMP_INSN_P (insn)
1261 && GET_CODE (PATTERN (insn)) == SET
1262 && REG_P (SET_SRC (PATTERN (insn)))
1263 && REG_P (SET_DEST (PATTERN (insn)))
1264 && (REGNO (SET_SRC (PATTERN (insn)))
1265 == REGNO (SET_DEST (PATTERN (insn)))))
1271 pnote = ®_NOTES (insn);
1274 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1275 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1276 || REG_NOTE_KIND (*pnote) == REG_INC)
1277 *pnote = XEXP (*pnote, 1);
1279 pnote = &XEXP (*pnote, 1);
1283 add_auto_inc_notes (insn, PATTERN (insn));
1286 /* Simplify (subreg (reg)) if it appears as an operand. */
1287 cleanup_subreg_operands (insn);
1289 /* Clean up invalid ASMs so that they don't confuse later passes.
1291 if (asm_noperands (PATTERN (insn)) >= 0)
1293 extract_insn (insn);
1294 if (!constrain_operands (1))
1296 error_for_asm (insn,
1297 "%<asm%> operand has impossible constraints");
1304 /* If we are doing stack checking, give a warning if this function's
1305 frame size is larger than we expect. */
1306 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1308 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1309 static int verbose_warned = 0;
1311 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1312 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1313 size += UNITS_PER_WORD;
1315 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1317 warning (0, "frame size too large for reliable stack checking");
1318 if (! verbose_warned)
1320 warning (0, "try reducing the number of local variables");
1326 /* Indicate that we no longer have known memory locations or constants. */
1327 if (reg_equiv_constant)
1328 free (reg_equiv_constant);
1329 if (reg_equiv_invariant)
1330 free (reg_equiv_invariant);
1331 reg_equiv_constant = 0;
1332 reg_equiv_invariant = 0;
1333 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1334 reg_equiv_memory_loc = 0;
1336 if (offsets_known_at)
1337 free (offsets_known_at);
1341 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1342 if (reg_equiv_alt_mem_list[i])
1343 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1344 free (reg_equiv_alt_mem_list);
1346 free (reg_equiv_mem);
1348 free (reg_equiv_address);
1349 free (reg_max_ref_width);
1350 free (reg_old_renumber);
1351 free (pseudo_previous_regs);
1352 free (pseudo_forbidden_regs);
1354 CLEAR_HARD_REG_SET (used_spill_regs);
1355 for (i = 0; i < n_spills; i++)
1356 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1358 /* Free all the insn_chain structures at once. */
1359 obstack_free (&reload_obstack, reload_startobj);
1360 unused_insn_chains = 0;
1361 fixup_abnormal_edges ();
1363 /* Replacing pseudos with their memory equivalents might have
1364 created shared rtx. Subsequent passes would get confused
1365 by this, so unshare everything here. */
1366 unshare_all_rtl_again (first);
1368 #ifdef STACK_BOUNDARY
1369 /* init_emit has set the alignment of the hard frame pointer
1370 to STACK_BOUNDARY. It is very likely no longer valid if
1371 the hard frame pointer was used for register allocation. */
1372 if (!frame_pointer_needed)
1373 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1379 /* Yet another special case. Unfortunately, reg-stack forces people to
1380 write incorrect clobbers in asm statements. These clobbers must not
1381 cause the register to appear in bad_spill_regs, otherwise we'll call
1382 fatal_insn later. We clear the corresponding regnos in the live
1383 register sets to avoid this.
1384 The whole thing is rather sick, I'm afraid. */
1387 maybe_fix_stack_asms (void)
1390 const char *constraints[MAX_RECOG_OPERANDS];
1391 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1392 struct insn_chain *chain;
1394 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1397 HARD_REG_SET clobbered, allowed;
1400 if (! INSN_P (chain->insn)
1401 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1403 pat = PATTERN (chain->insn);
1404 if (GET_CODE (pat) != PARALLEL)
1407 CLEAR_HARD_REG_SET (clobbered);
1408 CLEAR_HARD_REG_SET (allowed);
1410 /* First, make a mask of all stack regs that are clobbered. */
1411 for (i = 0; i < XVECLEN (pat, 0); i++)
1413 rtx t = XVECEXP (pat, 0, i);
1414 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1415 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1418 /* Get the operand values and constraints out of the insn. */
1419 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1420 constraints, operand_mode, NULL);
1422 /* For every operand, see what registers are allowed. */
1423 for (i = 0; i < noperands; i++)
1425 const char *p = constraints[i];
1426 /* For every alternative, we compute the class of registers allowed
1427 for reloading in CLS, and merge its contents into the reg set
1429 int cls = (int) NO_REGS;
1435 if (c == '\0' || c == ',' || c == '#')
1437 /* End of one alternative - mark the regs in the current
1438 class, and reset the class. */
1439 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1445 } while (c != '\0' && c != ',');
1453 case '=': case '+': case '*': case '%': case '?': case '!':
1454 case '0': case '1': case '2': case '3': case '4': case '<':
1455 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1456 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1457 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1458 case TARGET_MEM_CONSTRAINT:
1462 cls = (int) reg_class_subunion[cls]
1463 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1468 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1472 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1473 cls = (int) reg_class_subunion[cls]
1474 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1476 cls = (int) reg_class_subunion[cls]
1477 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1479 p += CONSTRAINT_LEN (c, p);
1482 /* Those of the registers which are clobbered, but allowed by the
1483 constraints, must be usable as reload registers. So clear them
1484 out of the life information. */
1485 AND_HARD_REG_SET (allowed, clobbered);
1486 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1487 if (TEST_HARD_REG_BIT (allowed, i))
1489 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1490 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1497 /* Copy the global variables n_reloads and rld into the corresponding elts
1500 copy_reloads (struct insn_chain *chain)
1502 chain->n_reloads = n_reloads;
1503 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1504 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1505 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1508 /* Walk the chain of insns, and determine for each whether it needs reloads
1509 and/or eliminations. Build the corresponding insns_need_reload list, and
1510 set something_needs_elimination as appropriate. */
1512 calculate_needs_all_insns (int global)
1514 struct insn_chain **pprev_reload = &insns_need_reload;
1515 struct insn_chain *chain, *next = 0;
1517 something_needs_elimination = 0;
1519 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1520 for (chain = reload_insn_chain; chain != 0; chain = next)
1522 rtx insn = chain->insn;
1526 /* Clear out the shortcuts. */
1527 chain->n_reloads = 0;
1528 chain->need_elim = 0;
1529 chain->need_reload = 0;
1530 chain->need_operand_change = 0;
1532 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1533 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1534 what effects this has on the known offsets at labels. */
1536 if (LABEL_P (insn) || JUMP_P (insn)
1537 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1538 set_label_offsets (insn, insn, 0);
1542 rtx old_body = PATTERN (insn);
1543 int old_code = INSN_CODE (insn);
1544 rtx old_notes = REG_NOTES (insn);
1545 int did_elimination = 0;
1546 int operands_changed = 0;
1547 rtx set = single_set (insn);
1549 /* Skip insns that only set an equivalence. */
1550 if (set && REG_P (SET_DEST (set))
1551 && reg_renumber[REGNO (SET_DEST (set))] < 0
1552 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1553 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1554 && reg_equiv_init[REGNO (SET_DEST (set))])
1557 /* If needed, eliminate any eliminable registers. */
1558 if (num_eliminable || num_eliminable_invariants)
1559 did_elimination = eliminate_regs_in_insn (insn, 0);
1561 /* Analyze the instruction. */
1562 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1563 global, spill_reg_order);
1565 /* If a no-op set needs more than one reload, this is likely
1566 to be something that needs input address reloads. We
1567 can't get rid of this cleanly later, and it is of no use
1568 anyway, so discard it now.
1569 We only do this when expensive_optimizations is enabled,
1570 since this complements reload inheritance / output
1571 reload deletion, and it can make debugging harder. */
1572 if (flag_expensive_optimizations && n_reloads > 1)
1574 rtx set = single_set (insn);
1576 && SET_SRC (set) == SET_DEST (set)
1577 && REG_P (SET_SRC (set))
1578 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1581 /* Delete it from the reload chain. */
1583 chain->prev->next = next;
1585 reload_insn_chain = next;
1587 next->prev = chain->prev;
1588 chain->next = unused_insn_chains;
1589 unused_insn_chains = chain;
1594 update_eliminable_offsets ();
1596 /* Remember for later shortcuts which insns had any reloads or
1597 register eliminations. */
1598 chain->need_elim = did_elimination;
1599 chain->need_reload = n_reloads > 0;
1600 chain->need_operand_change = operands_changed;
1602 /* Discard any register replacements done. */
1603 if (did_elimination)
1605 obstack_free (&reload_obstack, reload_insn_firstobj);
1606 PATTERN (insn) = old_body;
1607 INSN_CODE (insn) = old_code;
1608 REG_NOTES (insn) = old_notes;
1609 something_needs_elimination = 1;
1612 something_needs_operands_changed |= operands_changed;
1616 copy_reloads (chain);
1617 *pprev_reload = chain;
1618 pprev_reload = &chain->next_need_reload;
1625 /* Comparison function for qsort to decide which of two reloads
1626 should be handled first. *P1 and *P2 are the reload numbers. */
1629 reload_reg_class_lower (const void *r1p, const void *r2p)
1631 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1634 /* Consider required reloads before optional ones. */
1635 t = rld[r1].optional - rld[r2].optional;
1639 /* Count all solitary classes before non-solitary ones. */
1640 t = ((reg_class_size[(int) rld[r2].class] == 1)
1641 - (reg_class_size[(int) rld[r1].class] == 1));
1645 /* Aside from solitaires, consider all multi-reg groups first. */
1646 t = rld[r2].nregs - rld[r1].nregs;
1650 /* Consider reloads in order of increasing reg-class number. */
1651 t = (int) rld[r1].class - (int) rld[r2].class;
1655 /* If reloads are equally urgent, sort by reload number,
1656 so that the results of qsort leave nothing to chance. */
1660 /* The cost of spilling each hard reg. */
1661 static int spill_cost[FIRST_PSEUDO_REGISTER];
1663 /* When spilling multiple hard registers, we use SPILL_COST for the first
1664 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1665 only the first hard reg for a multi-reg pseudo. */
1666 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1668 /* Update the spill cost arrays, considering that pseudo REG is live. */
1671 count_pseudo (int reg)
1673 int freq = REG_FREQ (reg);
1674 int r = reg_renumber[reg];
1677 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1678 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1681 SET_REGNO_REG_SET (&pseudos_counted, reg);
1683 gcc_assert (r >= 0);
1685 spill_add_cost[r] += freq;
1687 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1689 spill_cost[r + nregs] += freq;
1692 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1693 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1696 order_regs_for_reload (struct insn_chain *chain)
1699 HARD_REG_SET used_by_pseudos;
1700 HARD_REG_SET used_by_pseudos2;
1701 reg_set_iterator rsi;
1703 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1705 memset (spill_cost, 0, sizeof spill_cost);
1706 memset (spill_add_cost, 0, sizeof spill_add_cost);
1708 /* Count number of uses of each hard reg by pseudo regs allocated to it
1709 and then order them by decreasing use. First exclude hard registers
1710 that are live in or across this insn. */
1712 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1713 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1714 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1715 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1717 /* Now find out which pseudos are allocated to it, and update
1719 CLEAR_REG_SET (&pseudos_counted);
1721 EXECUTE_IF_SET_IN_REG_SET
1722 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1726 EXECUTE_IF_SET_IN_REG_SET
1727 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1731 CLEAR_REG_SET (&pseudos_counted);
1734 /* Vector of reload-numbers showing the order in which the reloads should
1736 static short reload_order[MAX_RELOADS];
1738 /* This is used to keep track of the spill regs used in one insn. */
1739 static HARD_REG_SET used_spill_regs_local;
1741 /* We decided to spill hard register SPILLED, which has a size of
1742 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1743 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1744 update SPILL_COST/SPILL_ADD_COST. */
1747 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1749 int r = reg_renumber[reg];
1750 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1752 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1753 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1756 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1758 spill_add_cost[r] -= REG_FREQ (reg);
1760 spill_cost[r + nregs] -= REG_FREQ (reg);
1763 /* Find reload register to use for reload number ORDER. */
1766 find_reg (struct insn_chain *chain, int order)
1768 int rnum = reload_order[order];
1769 struct reload *rl = rld + rnum;
1770 int best_cost = INT_MAX;
1774 HARD_REG_SET not_usable;
1775 HARD_REG_SET used_by_other_reload;
1776 reg_set_iterator rsi;
1778 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1779 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1780 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1782 CLEAR_HARD_REG_SET (used_by_other_reload);
1783 for (k = 0; k < order; k++)
1785 int other = reload_order[k];
1787 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1788 for (j = 0; j < rld[other].nregs; j++)
1789 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1792 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1794 unsigned int regno = i;
1796 if (! TEST_HARD_REG_BIT (not_usable, regno)
1797 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1798 && HARD_REGNO_MODE_OK (regno, rl->mode))
1800 int this_cost = spill_cost[regno];
1802 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1804 for (j = 1; j < this_nregs; j++)
1806 this_cost += spill_add_cost[regno + j];
1807 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1808 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1813 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1815 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1817 if (this_cost < best_cost
1818 /* Among registers with equal cost, prefer caller-saved ones, or
1819 use REG_ALLOC_ORDER if it is defined. */
1820 || (this_cost == best_cost
1821 #ifdef REG_ALLOC_ORDER
1822 && (inv_reg_alloc_order[regno]
1823 < inv_reg_alloc_order[best_reg])
1825 && call_used_regs[regno]
1826 && ! call_used_regs[best_reg]
1831 best_cost = this_cost;
1839 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1841 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1842 rl->regno = best_reg;
1844 EXECUTE_IF_SET_IN_REG_SET
1845 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1847 count_spilled_pseudo (best_reg, rl->nregs, j);
1850 EXECUTE_IF_SET_IN_REG_SET
1851 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1853 count_spilled_pseudo (best_reg, rl->nregs, j);
1856 for (i = 0; i < rl->nregs; i++)
1858 gcc_assert (spill_cost[best_reg + i] == 0);
1859 gcc_assert (spill_add_cost[best_reg + i] == 0);
1860 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1865 /* Find more reload regs to satisfy the remaining need of an insn, which
1867 Do it by ascending class number, since otherwise a reg
1868 might be spilled for a big class and might fail to count
1869 for a smaller class even though it belongs to that class. */
1872 find_reload_regs (struct insn_chain *chain)
1876 /* In order to be certain of getting the registers we need,
1877 we must sort the reloads into order of increasing register class.
1878 Then our grabbing of reload registers will parallel the process
1879 that provided the reload registers. */
1880 for (i = 0; i < chain->n_reloads; i++)
1882 /* Show whether this reload already has a hard reg. */
1883 if (chain->rld[i].reg_rtx)
1885 int regno = REGNO (chain->rld[i].reg_rtx);
1886 chain->rld[i].regno = regno;
1888 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1891 chain->rld[i].regno = -1;
1892 reload_order[i] = i;
1895 n_reloads = chain->n_reloads;
1896 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1898 CLEAR_HARD_REG_SET (used_spill_regs_local);
1901 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1903 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1905 /* Compute the order of preference for hard registers to spill. */
1907 order_regs_for_reload (chain);
1909 for (i = 0; i < n_reloads; i++)
1911 int r = reload_order[i];
1913 /* Ignore reloads that got marked inoperative. */
1914 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1915 && ! rld[r].optional
1916 && rld[r].regno == -1)
1917 if (! find_reg (chain, i))
1920 fprintf (dump_file, "reload failure for reload %d\n", r);
1921 spill_failure (chain->insn, rld[r].class);
1927 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1928 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1930 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1934 select_reload_regs (void)
1936 struct insn_chain *chain;
1938 /* Try to satisfy the needs for each insn. */
1939 for (chain = insns_need_reload; chain != 0;
1940 chain = chain->next_need_reload)
1941 find_reload_regs (chain);
1944 /* Delete all insns that were inserted by emit_caller_save_insns during
1947 delete_caller_save_insns (void)
1949 struct insn_chain *c = reload_insn_chain;
1953 while (c != 0 && c->is_caller_save_insn)
1955 struct insn_chain *next = c->next;
1958 if (c == reload_insn_chain)
1959 reload_insn_chain = next;
1963 next->prev = c->prev;
1965 c->prev->next = next;
1966 c->next = unused_insn_chains;
1967 unused_insn_chains = c;
1975 /* Handle the failure to find a register to spill.
1976 INSN should be one of the insns which needed this particular spill reg. */
1979 spill_failure (rtx insn, enum reg_class class)
1981 if (asm_noperands (PATTERN (insn)) >= 0)
1982 error_for_asm (insn, "can't find a register in class %qs while "
1983 "reloading %<asm%>",
1984 reg_class_names[class]);
1987 error ("unable to find a register to spill in class %qs",
1988 reg_class_names[class]);
1992 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
1993 debug_reload_to_stream (dump_file);
1995 fatal_insn ("this is the insn:", insn);
1999 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2000 data that is dead in INSN. */
2003 delete_dead_insn (rtx insn)
2005 rtx prev = prev_real_insn (insn);
2008 /* If the previous insn sets a register that dies in our insn, delete it
2010 if (prev && GET_CODE (PATTERN (prev)) == SET
2011 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2012 && reg_mentioned_p (prev_dest, PATTERN (insn))
2013 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2014 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2015 delete_dead_insn (prev);
2017 SET_INSN_DELETED (insn);
2020 /* Modify the home of pseudo-reg I.
2021 The new home is present in reg_renumber[I].
2023 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2024 or it may be -1, meaning there is none or it is not relevant.
2025 This is used so that all pseudos spilled from a given hard reg
2026 can share one stack slot. */
2029 alter_reg (int i, int from_reg)
2031 /* When outputting an inline function, this can happen
2032 for a reg that isn't actually used. */
2033 if (regno_reg_rtx[i] == 0)
2036 /* If the reg got changed to a MEM at rtl-generation time,
2038 if (!REG_P (regno_reg_rtx[i]))
2041 /* Modify the reg-rtx to contain the new hard reg
2042 number or else to contain its pseudo reg number. */
2043 SET_REGNO (regno_reg_rtx[i],
2044 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2046 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2047 allocate a stack slot for it. */
2049 if (reg_renumber[i] < 0
2050 && REG_N_REFS (i) > 0
2051 && reg_equiv_constant[i] == 0
2052 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
2053 && reg_equiv_memory_loc[i] == 0)
2056 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2057 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2058 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2059 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2060 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2063 /* Each pseudo reg has an inherent size which comes from its own mode,
2064 and a total size which provides room for paradoxical subregs
2065 which refer to the pseudo reg in wider modes.
2067 We can use a slot already allocated if it provides both
2068 enough inherent space and enough total space.
2069 Otherwise, we allocate a new slot, making sure that it has no less
2070 inherent space, and no less total space, then the previous slot. */
2073 alias_set_type alias_set = new_alias_set ();
2075 /* No known place to spill from => no slot to reuse. */
2076 x = assign_stack_local (mode, total_size,
2077 min_align > inherent_align
2078 || total_size > inherent_size ? -1 : 0);
2079 if (BYTES_BIG_ENDIAN)
2080 /* Cancel the big-endian correction done in assign_stack_local.
2081 Get the address of the beginning of the slot.
2082 This is so we can do a big-endian correction unconditionally
2084 adjust = inherent_size - total_size;
2086 /* Nothing can alias this slot except this pseudo. */
2087 set_mem_alias_set (x, alias_set);
2088 dse_record_singleton_alias_set (alias_set, mode);
2091 /* Reuse a stack slot if possible. */
2092 else if (spill_stack_slot[from_reg] != 0
2093 && spill_stack_slot_width[from_reg] >= total_size
2094 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2096 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2097 x = spill_stack_slot[from_reg];
2098 /* Allocate a bigger slot. */
2101 /* Compute maximum size needed, both for inherent size
2102 and for total size. */
2105 if (spill_stack_slot[from_reg])
2107 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2109 mode = GET_MODE (spill_stack_slot[from_reg]);
2110 if (spill_stack_slot_width[from_reg] > total_size)
2111 total_size = spill_stack_slot_width[from_reg];
2112 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2113 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2116 /* Make a slot with that size. */
2117 x = assign_stack_local (mode, total_size,
2118 min_align > inherent_align
2119 || total_size > inherent_size ? -1 : 0);
2122 /* All pseudos mapped to this slot can alias each other. */
2123 if (spill_stack_slot[from_reg])
2125 alias_set_type alias_set
2126 = MEM_ALIAS_SET (spill_stack_slot[from_reg]);
2127 set_mem_alias_set (x, alias_set);
2128 dse_invalidate_singleton_alias_set (alias_set);
2132 alias_set_type alias_set = new_alias_set ();
2133 set_mem_alias_set (x, alias_set);
2134 dse_record_singleton_alias_set (alias_set, mode);
2137 if (BYTES_BIG_ENDIAN)
2139 /* Cancel the big-endian correction done in assign_stack_local.
2140 Get the address of the beginning of the slot.
2141 This is so we can do a big-endian correction unconditionally
2143 adjust = GET_MODE_SIZE (mode) - total_size;
2146 = adjust_address_nv (x, mode_for_size (total_size
2152 spill_stack_slot[from_reg] = stack_slot;
2153 spill_stack_slot_width[from_reg] = total_size;
2156 /* On a big endian machine, the "address" of the slot
2157 is the address of the low part that fits its inherent mode. */
2158 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2159 adjust += (total_size - inherent_size);
2161 /* If we have any adjustment to make, or if the stack slot is the
2162 wrong mode, make a new stack slot. */
2163 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2165 /* If we have a decl for the original register, set it for the
2166 memory. If this is a shared MEM, make a copy. */
2167 if (REG_EXPR (regno_reg_rtx[i])
2168 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2170 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2172 /* We can do this only for the DECLs home pseudo, not for
2173 any copies of it, since otherwise when the stack slot
2174 is reused, nonoverlapping_memrefs_p might think they
2176 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2178 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2181 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2185 /* Save the stack slot for later. */
2186 reg_equiv_memory_loc[i] = x;
2190 /* Mark the slots in regs_ever_live for the hard regs used by
2191 pseudo-reg number REGNO, accessed in MODE. */
2194 mark_home_live_1 (int regno, enum machine_mode mode)
2198 i = reg_renumber[regno];
2201 lim = end_hard_regno (mode, i);
2203 df_set_regs_ever_live(i++, true);
2206 /* Mark the slots in regs_ever_live for the hard regs
2207 used by pseudo-reg number REGNO. */
2210 mark_home_live (int regno)
2212 if (reg_renumber[regno] >= 0)
2213 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2216 /* This function handles the tracking of elimination offsets around branches.
2218 X is a piece of RTL being scanned.
2220 INSN is the insn that it came from, if any.
2222 INITIAL_P is nonzero if we are to set the offset to be the initial
2223 offset and zero if we are setting the offset of the label to be the
2227 set_label_offsets (rtx x, rtx insn, int initial_p)
2229 enum rtx_code code = GET_CODE (x);
2232 struct elim_table *p;
2237 if (LABEL_REF_NONLOCAL_P (x))
2242 /* ... fall through ... */
2245 /* If we know nothing about this label, set the desired offsets. Note
2246 that this sets the offset at a label to be the offset before a label
2247 if we don't know anything about the label. This is not correct for
2248 the label after a BARRIER, but is the best guess we can make. If
2249 we guessed wrong, we will suppress an elimination that might have
2250 been possible had we been able to guess correctly. */
2252 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2254 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2255 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2256 = (initial_p ? reg_eliminate[i].initial_offset
2257 : reg_eliminate[i].offset);
2258 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2261 /* Otherwise, if this is the definition of a label and it is
2262 preceded by a BARRIER, set our offsets to the known offset of
2266 && (tem = prev_nonnote_insn (insn)) != 0
2268 set_offsets_for_label (insn);
2270 /* If neither of the above cases is true, compare each offset
2271 with those previously recorded and suppress any eliminations
2272 where the offsets disagree. */
2274 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2275 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2276 != (initial_p ? reg_eliminate[i].initial_offset
2277 : reg_eliminate[i].offset))
2278 reg_eliminate[i].can_eliminate = 0;
2283 set_label_offsets (PATTERN (insn), insn, initial_p);
2285 /* ... fall through ... */
2289 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2290 to indirectly and hence must have all eliminations at their
2292 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2293 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2294 set_label_offsets (XEXP (tem, 0), insn, 1);
2300 /* Each of the labels in the parallel or address vector must be
2301 at their initial offsets. We want the first field for PARALLEL
2302 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2304 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2305 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2310 /* We only care about setting PC. If the source is not RETURN,
2311 IF_THEN_ELSE, or a label, disable any eliminations not at
2312 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2313 isn't one of those possibilities. For branches to a label,
2314 call ourselves recursively.
2316 Note that this can disable elimination unnecessarily when we have
2317 a non-local goto since it will look like a non-constant jump to
2318 someplace in the current function. This isn't a significant
2319 problem since such jumps will normally be when all elimination
2320 pairs are back to their initial offsets. */
2322 if (SET_DEST (x) != pc_rtx)
2325 switch (GET_CODE (SET_SRC (x)))
2332 set_label_offsets (SET_SRC (x), insn, initial_p);
2336 tem = XEXP (SET_SRC (x), 1);
2337 if (GET_CODE (tem) == LABEL_REF)
2338 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2339 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2342 tem = XEXP (SET_SRC (x), 2);
2343 if (GET_CODE (tem) == LABEL_REF)
2344 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2345 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2353 /* If we reach here, all eliminations must be at their initial
2354 offset because we are doing a jump to a variable address. */
2355 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2356 if (p->offset != p->initial_offset)
2357 p->can_eliminate = 0;
2365 /* Scan X and replace any eliminable registers (such as fp) with a
2366 replacement (such as sp), plus an offset.
2368 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2369 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2370 MEM, we are allowed to replace a sum of a register and the constant zero
2371 with the register, which we cannot do outside a MEM. In addition, we need
2372 to record the fact that a register is referenced outside a MEM.
2374 If INSN is an insn, it is the insn containing X. If we replace a REG
2375 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2376 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2377 the REG is being modified.
2379 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2380 That's used when we eliminate in expressions stored in notes.
2381 This means, do not set ref_outside_mem even if the reference
2384 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2385 replacements done assuming all offsets are at their initial values. If
2386 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2387 encounter, return the actual location so that find_reloads will do
2388 the proper thing. */
2391 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2392 bool may_use_invariant)
2394 enum rtx_code code = GET_CODE (x);
2395 struct elim_table *ep;
2402 if (! current_function_decl)
2425 /* First handle the case where we encounter a bare register that
2426 is eliminable. Replace it with a PLUS. */
2427 if (regno < FIRST_PSEUDO_REGISTER)
2429 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2431 if (ep->from_rtx == x && ep->can_eliminate)
2432 return plus_constant (ep->to_rtx, ep->previous_offset);
2435 else if (reg_renumber && reg_renumber[regno] < 0
2436 && reg_equiv_invariant && reg_equiv_invariant[regno])
2438 if (may_use_invariant)
2439 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2440 mem_mode, insn, true);
2441 /* There exists at least one use of REGNO that cannot be
2442 eliminated. Prevent the defining insn from being deleted. */
2443 reg_equiv_init[regno] = NULL_RTX;
2444 alter_reg (regno, -1);
2448 /* You might think handling MINUS in a manner similar to PLUS is a
2449 good idea. It is not. It has been tried multiple times and every
2450 time the change has had to have been reverted.
2452 Other parts of reload know a PLUS is special (gen_reload for example)
2453 and require special code to handle code a reloaded PLUS operand.
2455 Also consider backends where the flags register is clobbered by a
2456 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2457 lea instruction comes to mind). If we try to reload a MINUS, we
2458 may kill the flags register that was holding a useful value.
2460 So, please before trying to handle MINUS, consider reload as a
2461 whole instead of this little section as well as the backend issues. */
2463 /* If this is the sum of an eliminable register and a constant, rework
2465 if (REG_P (XEXP (x, 0))
2466 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2467 && CONSTANT_P (XEXP (x, 1)))
2469 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2471 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2473 /* The only time we want to replace a PLUS with a REG (this
2474 occurs when the constant operand of the PLUS is the negative
2475 of the offset) is when we are inside a MEM. We won't want
2476 to do so at other times because that would change the
2477 structure of the insn in a way that reload can't handle.
2478 We special-case the commonest situation in
2479 eliminate_regs_in_insn, so just replace a PLUS with a
2480 PLUS here, unless inside a MEM. */
2481 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2482 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2485 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2486 plus_constant (XEXP (x, 1),
2487 ep->previous_offset));
2490 /* If the register is not eliminable, we are done since the other
2491 operand is a constant. */
2495 /* If this is part of an address, we want to bring any constant to the
2496 outermost PLUS. We will do this by doing register replacement in
2497 our operands and seeing if a constant shows up in one of them.
2499 Note that there is no risk of modifying the structure of the insn,
2500 since we only get called for its operands, thus we are either
2501 modifying the address inside a MEM, or something like an address
2502 operand of a load-address insn. */
2505 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2506 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2508 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2510 /* If one side is a PLUS and the other side is a pseudo that
2511 didn't get a hard register but has a reg_equiv_constant,
2512 we must replace the constant here since it may no longer
2513 be in the position of any operand. */
2514 if (GET_CODE (new0) == PLUS && REG_P (new1)
2515 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2516 && reg_renumber[REGNO (new1)] < 0
2517 && reg_equiv_constant != 0
2518 && reg_equiv_constant[REGNO (new1)] != 0)
2519 new1 = reg_equiv_constant[REGNO (new1)];
2520 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2521 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2522 && reg_renumber[REGNO (new0)] < 0
2523 && reg_equiv_constant[REGNO (new0)] != 0)
2524 new0 = reg_equiv_constant[REGNO (new0)];
2526 new = form_sum (new0, new1);
2528 /* As above, if we are not inside a MEM we do not want to
2529 turn a PLUS into something else. We might try to do so here
2530 for an addition of 0 if we aren't optimizing. */
2531 if (! mem_mode && GET_CODE (new) != PLUS)
2532 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2540 /* If this is the product of an eliminable register and a
2541 constant, apply the distribute law and move the constant out
2542 so that we have (plus (mult ..) ..). This is needed in order
2543 to keep load-address insns valid. This case is pathological.
2544 We ignore the possibility of overflow here. */
2545 if (REG_P (XEXP (x, 0))
2546 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2547 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2548 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2550 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2553 /* Refs inside notes don't count for this purpose. */
2554 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2555 || GET_CODE (insn) == INSN_LIST)))
2556 ep->ref_outside_mem = 1;
2559 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2560 ep->previous_offset * INTVAL (XEXP (x, 1)));
2563 /* ... fall through ... */
2567 /* See comments before PLUS about handling MINUS. */
2569 case DIV: case UDIV:
2570 case MOD: case UMOD:
2571 case AND: case IOR: case XOR:
2572 case ROTATERT: case ROTATE:
2573 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2575 case GE: case GT: case GEU: case GTU:
2576 case LE: case LT: case LEU: case LTU:
2578 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2579 rtx new1 = XEXP (x, 1)
2580 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2582 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2583 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2588 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2591 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2592 if (new != XEXP (x, 0))
2594 /* If this is a REG_DEAD note, it is not valid anymore.
2595 Using the eliminated version could result in creating a
2596 REG_DEAD note for the stack or frame pointer. */
2597 if (GET_MODE (x) == REG_DEAD)
2599 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2602 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2606 /* ... fall through ... */
2609 /* Now do eliminations in the rest of the chain. If this was
2610 an EXPR_LIST, this might result in allocating more memory than is
2611 strictly needed, but it simplifies the code. */
2614 new = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2615 if (new != XEXP (x, 1))
2617 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2625 /* We do not support elimination of a register that is modified.
2626 elimination_effects has already make sure that this does not
2632 /* We do not support elimination of a register that is modified.
2633 elimination_effects has already make sure that this does not
2634 happen. The only remaining case we need to consider here is
2635 that the increment value may be an eliminable register. */
2636 if (GET_CODE (XEXP (x, 1)) == PLUS
2637 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2639 rtx new = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2642 if (new != XEXP (XEXP (x, 1), 1))
2643 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2644 gen_rtx_PLUS (GET_MODE (x),
2649 case STRICT_LOW_PART:
2651 case SIGN_EXTEND: case ZERO_EXTEND:
2652 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2653 case FLOAT: case FIX:
2654 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2663 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2664 if (new != XEXP (x, 0))
2665 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2669 /* Similar to above processing, but preserve SUBREG_BYTE.
2670 Convert (subreg (mem)) to (mem) if not paradoxical.
2671 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2672 pseudo didn't get a hard reg, we must replace this with the
2673 eliminated version of the memory location because push_reload
2674 may do the replacement in certain circumstances. */
2675 if (REG_P (SUBREG_REG (x))
2676 && (GET_MODE_SIZE (GET_MODE (x))
2677 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2678 && reg_equiv_memory_loc != 0
2679 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2681 new = SUBREG_REG (x);
2684 new = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2686 if (new != SUBREG_REG (x))
2688 int x_size = GET_MODE_SIZE (GET_MODE (x));
2689 int new_size = GET_MODE_SIZE (GET_MODE (new));
2692 && ((x_size < new_size
2693 #ifdef WORD_REGISTER_OPERATIONS
2694 /* On these machines, combine can create rtl of the form
2695 (set (subreg:m1 (reg:m2 R) 0) ...)
2696 where m1 < m2, and expects something interesting to
2697 happen to the entire word. Moreover, it will use the
2698 (reg:m2 R) later, expecting all bits to be preserved.
2699 So if the number of words is the same, preserve the
2700 subreg so that push_reload can see it. */
2701 && ! ((x_size - 1) / UNITS_PER_WORD
2702 == (new_size -1 ) / UNITS_PER_WORD)
2705 || x_size == new_size)
2707 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2709 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2715 /* Our only special processing is to pass the mode of the MEM to our
2716 recursive call and copy the flags. While we are here, handle this
2717 case more efficiently. */
2719 replace_equiv_address_nv (x,
2720 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2724 /* Handle insn_list USE that a call to a pure function may generate. */
2725 new = eliminate_regs_1 (XEXP (x, 0), 0, insn, false);
2726 if (new != XEXP (x, 0))
2727 return gen_rtx_USE (GET_MODE (x), new);
2739 /* Process each of our operands recursively. If any have changed, make a
2741 fmt = GET_RTX_FORMAT (code);
2742 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2746 new = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2747 if (new != XEXP (x, i) && ! copied)
2749 x = shallow_copy_rtx (x);
2754 else if (*fmt == 'E')
2757 for (j = 0; j < XVECLEN (x, i); j++)
2759 new = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2760 if (new != XVECEXP (x, i, j) && ! copied_vec)
2762 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2766 x = shallow_copy_rtx (x);
2769 XVEC (x, i) = new_v;
2772 XVECEXP (x, i, j) = new;
2781 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2783 return eliminate_regs_1 (x, mem_mode, insn, false);
2786 /* Scan rtx X for modifications of elimination target registers. Update
2787 the table of eliminables to reflect the changed state. MEM_MODE is
2788 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2791 elimination_effects (rtx x, enum machine_mode mem_mode)
2793 enum rtx_code code = GET_CODE (x);
2794 struct elim_table *ep;
2819 /* First handle the case where we encounter a bare register that
2820 is eliminable. Replace it with a PLUS. */
2821 if (regno < FIRST_PSEUDO_REGISTER)
2823 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2825 if (ep->from_rtx == x && ep->can_eliminate)
2828 ep->ref_outside_mem = 1;
2833 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2834 && reg_equiv_constant[regno]
2835 && ! function_invariant_p (reg_equiv_constant[regno]))
2836 elimination_effects (reg_equiv_constant[regno], mem_mode);
2845 /* If we modify the source of an elimination rule, disable it. */
2846 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2847 if (ep->from_rtx == XEXP (x, 0))
2848 ep->can_eliminate = 0;
2850 /* If we modify the target of an elimination rule by adding a constant,
2851 update its offset. If we modify the target in any other way, we'll
2852 have to disable the rule as well. */
2853 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2854 if (ep->to_rtx == XEXP (x, 0))
2856 int size = GET_MODE_SIZE (mem_mode);
2858 /* If more bytes than MEM_MODE are pushed, account for them. */
2859 #ifdef PUSH_ROUNDING
2860 if (ep->to_rtx == stack_pointer_rtx)
2861 size = PUSH_ROUNDING (size);
2863 if (code == PRE_DEC || code == POST_DEC)
2865 else if (code == PRE_INC || code == POST_INC)
2867 else if (code == PRE_MODIFY || code == POST_MODIFY)
2869 if (GET_CODE (XEXP (x, 1)) == PLUS
2870 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2871 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
2872 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2874 ep->can_eliminate = 0;
2878 /* These two aren't unary operators. */
2879 if (code == POST_MODIFY || code == PRE_MODIFY)
2882 /* Fall through to generic unary operation case. */
2883 case STRICT_LOW_PART:
2885 case SIGN_EXTEND: case ZERO_EXTEND:
2886 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2887 case FLOAT: case FIX:
2888 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2897 elimination_effects (XEXP (x, 0), mem_mode);
2901 if (REG_P (SUBREG_REG (x))
2902 && (GET_MODE_SIZE (GET_MODE (x))
2903 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2904 && reg_equiv_memory_loc != 0
2905 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2908 elimination_effects (SUBREG_REG (x), mem_mode);
2912 /* If using a register that is the source of an eliminate we still
2913 think can be performed, note it cannot be performed since we don't
2914 know how this register is used. */
2915 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2916 if (ep->from_rtx == XEXP (x, 0))
2917 ep->can_eliminate = 0;
2919 elimination_effects (XEXP (x, 0), mem_mode);
2923 /* If clobbering a register that is the replacement register for an
2924 elimination we still think can be performed, note that it cannot
2925 be performed. Otherwise, we need not be concerned about it. */
2926 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2927 if (ep->to_rtx == XEXP (x, 0))
2928 ep->can_eliminate = 0;
2930 elimination_effects (XEXP (x, 0), mem_mode);
2934 /* Check for setting a register that we know about. */
2935 if (REG_P (SET_DEST (x)))
2937 /* See if this is setting the replacement register for an
2940 If DEST is the hard frame pointer, we do nothing because we
2941 assume that all assignments to the frame pointer are for
2942 non-local gotos and are being done at a time when they are valid
2943 and do not disturb anything else. Some machines want to
2944 eliminate a fake argument pointer (or even a fake frame pointer)
2945 with either the real frame or the stack pointer. Assignments to
2946 the hard frame pointer must not prevent this elimination. */
2948 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2950 if (ep->to_rtx == SET_DEST (x)
2951 && SET_DEST (x) != hard_frame_pointer_rtx)
2953 /* If it is being incremented, adjust the offset. Otherwise,
2954 this elimination can't be done. */
2955 rtx src = SET_SRC (x);
2957 if (GET_CODE (src) == PLUS
2958 && XEXP (src, 0) == SET_DEST (x)
2959 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2960 ep->offset -= INTVAL (XEXP (src, 1));
2962 ep->can_eliminate = 0;
2966 elimination_effects (SET_DEST (x), 0);
2967 elimination_effects (SET_SRC (x), 0);
2971 /* Our only special processing is to pass the mode of the MEM to our
2973 elimination_effects (XEXP (x, 0), GET_MODE (x));
2980 fmt = GET_RTX_FORMAT (code);
2981 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2984 elimination_effects (XEXP (x, i), mem_mode);
2985 else if (*fmt == 'E')
2986 for (j = 0; j < XVECLEN (x, i); j++)
2987 elimination_effects (XVECEXP (x, i, j), mem_mode);
2991 /* Descend through rtx X and verify that no references to eliminable registers
2992 remain. If any do remain, mark the involved register as not
2996 check_eliminable_occurrences (rtx x)
3005 code = GET_CODE (x);
3007 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3009 struct elim_table *ep;
3011 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3012 if (ep->from_rtx == x)
3013 ep->can_eliminate = 0;
3017 fmt = GET_RTX_FORMAT (code);
3018 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3021 check_eliminable_occurrences (XEXP (x, i));
3022 else if (*fmt == 'E')
3025 for (j = 0; j < XVECLEN (x, i); j++)
3026 check_eliminable_occurrences (XVECEXP (x, i, j));
3031 /* Scan INSN and eliminate all eliminable registers in it.
3033 If REPLACE is nonzero, do the replacement destructively. Also
3034 delete the insn as dead it if it is setting an eliminable register.
3036 If REPLACE is zero, do all our allocations in reload_obstack.
3038 If no eliminations were done and this insn doesn't require any elimination
3039 processing (these are not identical conditions: it might be updating sp,
3040 but not referencing fp; this needs to be seen during reload_as_needed so
3041 that the offset between fp and sp can be taken into consideration), zero
3042 is returned. Otherwise, 1 is returned. */
3045 eliminate_regs_in_insn (rtx insn, int replace)
3047 int icode = recog_memoized (insn);
3048 rtx old_body = PATTERN (insn);
3049 int insn_is_asm = asm_noperands (old_body) >= 0;
3050 rtx old_set = single_set (insn);
3054 rtx substed_operand[MAX_RECOG_OPERANDS];
3055 rtx orig_operand[MAX_RECOG_OPERANDS];
3056 struct elim_table *ep;
3057 rtx plus_src, plus_cst_src;
3059 if (! insn_is_asm && icode < 0)
3061 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3062 || GET_CODE (PATTERN (insn)) == CLOBBER
3063 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3064 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3065 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3069 if (old_set != 0 && REG_P (SET_DEST (old_set))
3070 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3072 /* Check for setting an eliminable register. */
3073 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3074 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3076 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3077 /* If this is setting the frame pointer register to the
3078 hardware frame pointer register and this is an elimination
3079 that will be done (tested above), this insn is really
3080 adjusting the frame pointer downward to compensate for
3081 the adjustment done before a nonlocal goto. */
3082 if (ep->from == FRAME_POINTER_REGNUM
3083 && ep->to == HARD_FRAME_POINTER_REGNUM)
3085 rtx base = SET_SRC (old_set);
3086 rtx base_insn = insn;
3087 HOST_WIDE_INT offset = 0;
3089 while (base != ep->to_rtx)
3091 rtx prev_insn, prev_set;
3093 if (GET_CODE (base) == PLUS
3094 && GET_CODE (XEXP (base, 1)) == CONST_INT)
3096 offset += INTVAL (XEXP (base, 1));
3097 base = XEXP (base, 0);
3099 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3100 && (prev_set = single_set (prev_insn)) != 0
3101 && rtx_equal_p (SET_DEST (prev_set), base))
3103 base = SET_SRC (prev_set);
3104 base_insn = prev_insn;
3110 if (base == ep->to_rtx)
3113 = plus_constant (ep->to_rtx, offset - ep->offset);
3115 new_body = old_body;
3118 new_body = copy_insn (old_body);
3119 if (REG_NOTES (insn))
3120 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3122 PATTERN (insn) = new_body;
3123 old_set = single_set (insn);
3125 /* First see if this insn remains valid when we
3126 make the change. If not, keep the INSN_CODE
3127 the same and let reload fit it up. */
3128 validate_change (insn, &SET_SRC (old_set), src, 1);
3129 validate_change (insn, &SET_DEST (old_set),
3131 if (! apply_change_group ())
3133 SET_SRC (old_set) = src;
3134 SET_DEST (old_set) = ep->to_rtx;
3143 /* In this case this insn isn't serving a useful purpose. We
3144 will delete it in reload_as_needed once we know that this
3145 elimination is, in fact, being done.
3147 If REPLACE isn't set, we can't delete this insn, but needn't
3148 process it since it won't be used unless something changes. */
3151 delete_dead_insn (insn);
3159 /* We allow one special case which happens to work on all machines we
3160 currently support: a single set with the source or a REG_EQUAL
3161 note being a PLUS of an eliminable register and a constant. */
3162 plus_src = plus_cst_src = 0;
3163 if (old_set && REG_P (SET_DEST (old_set)))
3165 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3166 plus_src = SET_SRC (old_set);
3167 /* First see if the source is of the form (plus (...) CST). */
3169 && GET_CODE (XEXP (plus_src, 1)) == CONST_INT)
3170 plus_cst_src = plus_src;
3171 else if (REG_P (SET_SRC (old_set))
3174 /* Otherwise, see if we have a REG_EQUAL note of the form
3175 (plus (...) CST). */
3177 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3179 if ((REG_NOTE_KIND (links) == REG_EQUAL
3180 || REG_NOTE_KIND (links) == REG_EQUIV)
3181 && GET_CODE (XEXP (links, 0)) == PLUS
3182 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT)
3184 plus_cst_src = XEXP (links, 0);
3190 /* Check that the first operand of the PLUS is a hard reg or
3191 the lowpart subreg of one. */
3194 rtx reg = XEXP (plus_cst_src, 0);
3195 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3196 reg = SUBREG_REG (reg);
3198 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3204 rtx reg = XEXP (plus_cst_src, 0);
3205 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3207 if (GET_CODE (reg) == SUBREG)
3208 reg = SUBREG_REG (reg);
3210 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3211 if (ep->from_rtx == reg && ep->can_eliminate)
3213 rtx to_rtx = ep->to_rtx;
3214 offset += ep->offset;
3215 offset = trunc_int_for_mode (offset, GET_MODE (reg));
3217 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3218 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3220 /* If we have a nonzero offset, and the source is already
3221 a simple REG, the following transformation would
3222 increase the cost of the insn by replacing a simple REG
3223 with (plus (reg sp) CST). So try only when we already
3224 had a PLUS before. */
3225 if (offset == 0 || plus_src)
3227 rtx new_src = plus_constant (to_rtx, offset);
3229 new_body = old_body;
3232 new_body = copy_insn (old_body);
3233 if (REG_NOTES (insn))
3234 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3236 PATTERN (insn) = new_body;
3237 old_set = single_set (insn);
3239 /* First see if this insn remains valid when we make the
3240 change. If not, try to replace the whole pattern with
3241 a simple set (this may help if the original insn was a
3242 PARALLEL that was only recognized as single_set due to
3243 REG_UNUSED notes). If this isn't valid either, keep
3244 the INSN_CODE the same and let reload fix it up. */
3245 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3247 rtx new_pat = gen_rtx_SET (VOIDmode,
3248 SET_DEST (old_set), new_src);
3250 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3251 SET_SRC (old_set) = new_src;
3258 /* This can't have an effect on elimination offsets, so skip right
3264 /* Determine the effects of this insn on elimination offsets. */
3265 elimination_effects (old_body, 0);
3267 /* Eliminate all eliminable registers occurring in operands that
3268 can be handled by reload. */
3269 extract_insn (insn);
3270 for (i = 0; i < recog_data.n_operands; i++)
3272 orig_operand[i] = recog_data.operand[i];
3273 substed_operand[i] = recog_data.operand[i];
3275 /* For an asm statement, every operand is eliminable. */
3276 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3278 bool is_set_src, in_plus;
3280 /* Check for setting a register that we know about. */
3281 if (recog_data.operand_type[i] != OP_IN
3282 && REG_P (orig_operand[i]))
3284 /* If we are assigning to a register that can be eliminated, it
3285 must be as part of a PARALLEL, since the code above handles
3286 single SETs. We must indicate that we can no longer
3287 eliminate this reg. */
3288 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3290 if (ep->from_rtx == orig_operand[i])
3291 ep->can_eliminate = 0;
3294 /* Companion to the above plus substitution, we can allow
3295 invariants as the source of a plain move. */
3297 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3301 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3302 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3306 = eliminate_regs_1 (recog_data.operand[i], 0,
3307 replace ? insn : NULL_RTX,
3308 is_set_src || in_plus);
3309 if (substed_operand[i] != orig_operand[i])
3311 /* Terminate the search in check_eliminable_occurrences at
3313 *recog_data.operand_loc[i] = 0;
3315 /* If an output operand changed from a REG to a MEM and INSN is an
3316 insn, write a CLOBBER insn. */
3317 if (recog_data.operand_type[i] != OP_IN
3318 && REG_P (orig_operand[i])
3319 && MEM_P (substed_operand[i])
3321 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3325 for (i = 0; i < recog_data.n_dups; i++)
3326 *recog_data.dup_loc[i]
3327 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3329 /* If any eliminable remain, they aren't eliminable anymore. */
3330 check_eliminable_occurrences (old_body);
3332 /* Substitute the operands; the new values are in the substed_operand
3334 for (i = 0; i < recog_data.n_operands; i++)
3335 *recog_data.operand_loc[i] = substed_operand[i];
3336 for (i = 0; i < recog_data.n_dups; i++)
3337 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3339 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3340 re-recognize the insn. We do this in case we had a simple addition
3341 but now can do this as a load-address. This saves an insn in this
3343 If re-recognition fails, the old insn code number will still be used,
3344 and some register operands may have changed into PLUS expressions.
3345 These will be handled by find_reloads by loading them into a register
3350 /* If we aren't replacing things permanently and we changed something,
3351 make another copy to ensure that all the RTL is new. Otherwise
3352 things can go wrong if find_reload swaps commutative operands
3353 and one is inside RTL that has been copied while the other is not. */
3354 new_body = old_body;
3357 new_body = copy_insn (old_body);
3358 if (REG_NOTES (insn))
3359 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3361 PATTERN (insn) = new_body;
3363 /* If we had a move insn but now we don't, rerecognize it. This will
3364 cause spurious re-recognition if the old move had a PARALLEL since
3365 the new one still will, but we can't call single_set without
3366 having put NEW_BODY into the insn and the re-recognition won't
3367 hurt in this rare case. */
3368 /* ??? Why this huge if statement - why don't we just rerecognize the
3372 && ((REG_P (SET_SRC (old_set))
3373 && (GET_CODE (new_body) != SET
3374 || !REG_P (SET_SRC (new_body))))
3375 /* If this was a load from or store to memory, compare
3376 the MEM in recog_data.operand to the one in the insn.
3377 If they are not equal, then rerecognize the insn. */
3379 && ((MEM_P (SET_SRC (old_set))
3380 && SET_SRC (old_set) != recog_data.operand[1])
3381 || (MEM_P (SET_DEST (old_set))
3382 && SET_DEST (old_set) != recog_data.operand[0])))
3383 /* If this was an add insn before, rerecognize. */
3384 || GET_CODE (SET_SRC (old_set)) == PLUS))
3386 int new_icode = recog (PATTERN (insn), insn, 0);
3388 INSN_CODE (insn) = new_icode;
3392 /* Restore the old body. If there were any changes to it, we made a copy
3393 of it while the changes were still in place, so we'll correctly return
3394 a modified insn below. */
3397 /* Restore the old body. */
3398 for (i = 0; i < recog_data.n_operands; i++)
3399 *recog_data.operand_loc[i] = orig_operand[i];
3400 for (i = 0; i < recog_data.n_dups; i++)
3401 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3404 /* Update all elimination pairs to reflect the status after the current
3405 insn. The changes we make were determined by the earlier call to
3406 elimination_effects.
3408 We also detect cases where register elimination cannot be done,
3409 namely, if a register would be both changed and referenced outside a MEM
3410 in the resulting insn since such an insn is often undefined and, even if
3411 not, we cannot know what meaning will be given to it. Note that it is
3412 valid to have a register used in an address in an insn that changes it
3413 (presumably with a pre- or post-increment or decrement).
3415 If anything changes, return nonzero. */
3417 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3419 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3420 ep->can_eliminate = 0;
3422 ep->ref_outside_mem = 0;
3424 if (ep->previous_offset != ep->offset)
3429 /* If we changed something, perform elimination in REG_NOTES. This is
3430 needed even when REPLACE is zero because a REG_DEAD note might refer
3431 to a register that we eliminate and could cause a different number
3432 of spill registers to be needed in the final reload pass than in
3434 if (val && REG_NOTES (insn) != 0)
3436 = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true);
3441 /* Loop through all elimination pairs.
3442 Recalculate the number not at initial offset.
3444 Compute the maximum offset (minimum offset if the stack does not
3445 grow downward) for each elimination pair. */
3448 update_eliminable_offsets (void)
3450 struct elim_table *ep;
3452 num_not_at_initial_offset = 0;
3453 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3455 ep->previous_offset = ep->offset;
3456 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3457 num_not_at_initial_offset++;
3461 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3462 replacement we currently believe is valid, mark it as not eliminable if X
3463 modifies DEST in any way other than by adding a constant integer to it.
3465 If DEST is the frame pointer, we do nothing because we assume that
3466 all assignments to the hard frame pointer are nonlocal gotos and are being
3467 done at a time when they are valid and do not disturb anything else.
3468 Some machines want to eliminate a fake argument pointer with either the
3469 frame or stack pointer. Assignments to the hard frame pointer must not
3470 prevent this elimination.
3472 Called via note_stores from reload before starting its passes to scan
3473 the insns of the function. */
3476 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3480 /* A SUBREG of a hard register here is just changing its mode. We should
3481 not see a SUBREG of an eliminable hard register, but check just in
3483 if (GET_CODE (dest) == SUBREG)
3484 dest = SUBREG_REG (dest);
3486 if (dest == hard_frame_pointer_rtx)
3489 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3490 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3491 && (GET_CODE (x) != SET
3492 || GET_CODE (SET_SRC (x)) != PLUS
3493 || XEXP (SET_SRC (x), 0) != dest
3494 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3496 reg_eliminate[i].can_eliminate_previous
3497 = reg_eliminate[i].can_eliminate = 0;
3502 /* Verify that the initial elimination offsets did not change since the
3503 last call to set_initial_elim_offsets. This is used to catch cases
3504 where something illegal happened during reload_as_needed that could
3505 cause incorrect code to be generated if we did not check for it. */
3508 verify_initial_elim_offsets (void)
3512 if (!num_eliminable)
3515 #ifdef ELIMINABLE_REGS
3517 struct elim_table *ep;
3519 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3521 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3522 if (t != ep->initial_offset)
3527 INITIAL_FRAME_POINTER_OFFSET (t);
3528 if (t != reg_eliminate[0].initial_offset)
3535 /* Reset all offsets on eliminable registers to their initial values. */
3538 set_initial_elim_offsets (void)
3540 struct elim_table *ep = reg_eliminate;
3542 #ifdef ELIMINABLE_REGS
3543 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3545 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3546 ep->previous_offset = ep->offset = ep->initial_offset;
3549 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3550 ep->previous_offset = ep->offset = ep->initial_offset;
3553 num_not_at_initial_offset = 0;
3556 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3559 set_initial_eh_label_offset (rtx label)
3561 set_label_offsets (label, NULL_RTX, 1);
3564 /* Initialize the known label offsets.
3565 Set a known offset for each forced label to be at the initial offset
3566 of each elimination. We do this because we assume that all
3567 computed jumps occur from a location where each elimination is
3568 at its initial offset.
3569 For all other labels, show that we don't know the offsets. */
3572 set_initial_label_offsets (void)
3575 memset (offsets_known_at, 0, num_labels);
3577 for (x = forced_labels; x; x = XEXP (x, 1))
3579 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3581 for_each_eh_label (set_initial_eh_label_offset);
3584 /* Set all elimination offsets to the known values for the code label given
3588 set_offsets_for_label (rtx insn)
3591 int label_nr = CODE_LABEL_NUMBER (insn);
3592 struct elim_table *ep;
3594 num_not_at_initial_offset = 0;
3595 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3597 ep->offset = ep->previous_offset
3598 = offsets_at[label_nr - first_label_num][i];
3599 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3600 num_not_at_initial_offset++;
3604 /* See if anything that happened changes which eliminations are valid.
3605 For example, on the SPARC, whether or not the frame pointer can
3606 be eliminated can depend on what registers have been used. We need
3607 not check some conditions again (such as flag_omit_frame_pointer)
3608 since they can't have changed. */
3611 update_eliminables (HARD_REG_SET *pset)
3613 int previous_frame_pointer_needed = frame_pointer_needed;
3614 struct elim_table *ep;
3616 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3617 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3618 #ifdef ELIMINABLE_REGS
3619 || ! CAN_ELIMINATE (ep->from, ep->to)
3622 ep->can_eliminate = 0;
3624 /* Look for the case where we have discovered that we can't replace
3625 register A with register B and that means that we will now be
3626 trying to replace register A with register C. This means we can
3627 no longer replace register C with register B and we need to disable
3628 such an elimination, if it exists. This occurs often with A == ap,
3629 B == sp, and C == fp. */
3631 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3633 struct elim_table *op;
3636 if (! ep->can_eliminate && ep->can_eliminate_previous)
3638 /* Find the current elimination for ep->from, if there is a
3640 for (op = reg_eliminate;
3641 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3642 if (op->from == ep->from && op->can_eliminate)
3648 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3650 for (op = reg_eliminate;
3651 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3652 if (op->from == new_to && op->to == ep->to)
3653 op->can_eliminate = 0;
3657 /* See if any registers that we thought we could eliminate the previous
3658 time are no longer eliminable. If so, something has changed and we
3659 must spill the register. Also, recompute the number of eliminable
3660 registers and see if the frame pointer is needed; it is if there is
3661 no elimination of the frame pointer that we can perform. */
3663 frame_pointer_needed = 1;
3664 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3666 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3667 && ep->to != HARD_FRAME_POINTER_REGNUM)
3668 frame_pointer_needed = 0;
3670 if (! ep->can_eliminate && ep->can_eliminate_previous)
3672 ep->can_eliminate_previous = 0;
3673 SET_HARD_REG_BIT (*pset, ep->from);
3678 /* If we didn't need a frame pointer last time, but we do now, spill
3679 the hard frame pointer. */
3680 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3681 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3684 /* Return true if X is used as the target register of an elimination. */
3687 elimination_target_reg_p (rtx x)
3689 struct elim_table *ep;
3691 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3692 if (ep->to_rtx == x && ep->can_eliminate)
3698 /* Initialize the table of registers to eliminate. */
3701 init_elim_table (void)
3703 struct elim_table *ep;
3704 #ifdef ELIMINABLE_REGS
3705 const struct elim_table_1 *ep1;
3709 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
3711 /* Does this function require a frame pointer? */
3713 frame_pointer_needed = (! flag_omit_frame_pointer
3714 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3715 and restore sp for alloca. So we can't eliminate
3716 the frame pointer in that case. At some point,
3717 we should improve this by emitting the
3718 sp-adjusting insns for this case. */
3719 || (cfun->calls_alloca
3720 && EXIT_IGNORE_STACK)
3721 || crtl->accesses_prior_frames
3722 || FRAME_POINTER_REQUIRED);
3726 #ifdef ELIMINABLE_REGS
3727 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3728 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3730 ep->from = ep1->from;
3732 ep->can_eliminate = ep->can_eliminate_previous
3733 = (CAN_ELIMINATE (ep->from, ep->to)
3734 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3737 reg_eliminate[0].from = reg_eliminate_1[0].from;
3738 reg_eliminate[0].to = reg_eliminate_1[0].to;
3739 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3740 = ! frame_pointer_needed;
3743 /* Count the number of eliminable registers and build the FROM and TO
3744 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3745 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3746 We depend on this. */
3747 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3749 num_eliminable += ep->can_eliminate;
3750 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3751 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3755 /* Kick all pseudos out of hard register REGNO.
3757 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3758 because we found we can't eliminate some register. In the case, no pseudos
3759 are allowed to be in the register, even if they are only in a block that
3760 doesn't require spill registers, unlike the case when we are spilling this
3761 hard reg to produce another spill register.
3763 Return nonzero if any pseudos needed to be kicked out. */
3766 spill_hard_reg (unsigned int regno, int cant_eliminate)
3772 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3773 df_set_regs_ever_live (regno, true);
3776 /* Spill every pseudo reg that was allocated to this reg
3777 or to something that overlaps this reg. */
3779 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3780 if (reg_renumber[i] >= 0
3781 && (unsigned int) reg_renumber[i] <= regno
3782 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
3783 SET_REGNO_REG_SET (&spilled_pseudos, i);
3786 /* After find_reload_regs has been run for all insn that need reloads,
3787 and/or spill_hard_regs was called, this function is used to actually
3788 spill pseudo registers and try to reallocate them. It also sets up the
3789 spill_regs array for use by choose_reload_regs. */
3792 finish_spills (int global)
3794 struct insn_chain *chain;
3795 int something_changed = 0;
3797 reg_set_iterator rsi;
3799 /* Build the spill_regs array for the function. */
3800 /* If there are some registers still to eliminate and one of the spill regs
3801 wasn't ever used before, additional stack space may have to be
3802 allocated to store this register. Thus, we may have changed the offset
3803 between the stack and frame pointers, so mark that something has changed.
3805 One might think that we need only set VAL to 1 if this is a call-used
3806 register. However, the set of registers that must be saved by the
3807 prologue is not identical to the call-used set. For example, the
3808 register used by the call insn for the return PC is a call-used register,
3809 but must be saved by the prologue. */
3812 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3813 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3815 spill_reg_order[i] = n_spills;
3816 spill_regs[n_spills++] = i;
3817 if (num_eliminable && ! df_regs_ever_live_p (i))
3818 something_changed = 1;
3819 df_set_regs_ever_live (i, true);
3822 spill_reg_order[i] = -1;
3824 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3826 /* Record the current hard register the pseudo is allocated to in
3827 pseudo_previous_regs so we avoid reallocating it to the same
3828 hard reg in a later pass. */
3829 gcc_assert (reg_renumber[i] >= 0);
3831 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3832 /* Mark it as no longer having a hard register home. */
3833 reg_renumber[i] = -1;
3834 /* We will need to scan everything again. */
3835 something_changed = 1;
3838 /* Retry global register allocation if possible. */
3841 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3842 /* For every insn that needs reloads, set the registers used as spill
3843 regs in pseudo_forbidden_regs for every pseudo live across the
3845 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3847 EXECUTE_IF_SET_IN_REG_SET
3848 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3850 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3851 chain->used_spill_regs);
3853 EXECUTE_IF_SET_IN_REG_SET
3854 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3856 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3857 chain->used_spill_regs);
3861 /* Retry allocating the spilled pseudos. For each reg, merge the
3862 various reg sets that indicate which hard regs can't be used,
3863 and call retry_global_alloc.
3864 We change spill_pseudos here to only contain pseudos that did not
3865 get a new hard register. */
3866 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3867 if (reg_old_renumber[i] != reg_renumber[i])
3869 HARD_REG_SET forbidden;
3870 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3871 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3872 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3873 retry_global_alloc (i, forbidden);
3874 if (reg_renumber[i] >= 0)
3875 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3879 /* Fix up the register information in the insn chain.
3880 This involves deleting those of the spilled pseudos which did not get
3881 a new hard register home from the live_{before,after} sets. */
3882 for (chain = reload_insn_chain; chain; chain = chain->next)
3884 HARD_REG_SET used_by_pseudos;
3885 HARD_REG_SET used_by_pseudos2;
3887 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3888 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3890 /* Mark any unallocated hard regs as available for spills. That
3891 makes inheritance work somewhat better. */
3892 if (chain->need_reload)
3894 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3895 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3896 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3898 /* Save the old value for the sanity test below. */
3899 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3901 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3902 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3903 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3904 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3906 /* Make sure we only enlarge the set. */
3907 gcc_assert (hard_reg_set_subset_p (used_by_pseudos2,
3908 chain->used_spill_regs));
3912 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3913 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3915 int regno = reg_renumber[i];
3916 if (reg_old_renumber[i] == regno)
3919 alter_reg (i, reg_old_renumber[i]);
3920 reg_old_renumber[i] = regno;
3924 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3926 fprintf (dump_file, " Register %d now in %d.\n\n",
3927 i, reg_renumber[i]);
3931 return something_changed;
3934 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3937 scan_paradoxical_subregs (rtx x)
3941 enum rtx_code code = GET_CODE (x);
3952 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3960 if (REG_P (SUBREG_REG (x))
3961 && (GET_MODE_SIZE (GET_MODE (x))
3962 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
3964 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3965 = GET_MODE_SIZE (GET_MODE (x));
3966 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
3974 fmt = GET_RTX_FORMAT (code);
3975 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3978 scan_paradoxical_subregs (XEXP (x, i));
3979 else if (fmt[i] == 'E')
3982 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3983 scan_paradoxical_subregs (XVECEXP (x, i, j));
3988 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
3989 examine all of the reload insns between PREV and NEXT exclusive, and
3990 annotate all that may trap. */
3993 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
3995 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
3996 unsigned int trap_count;
4002 if (may_trap_p (PATTERN (insn)))
4006 remove_note (insn, note);
4010 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
4011 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
4015 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0), REG_NOTES (i));
4019 /* Reload pseudo-registers into hard regs around each insn as needed.
4020 Additional register load insns are output before the insn that needs it
4021 and perhaps store insns after insns that modify the reloaded pseudo reg.
4023 reg_last_reload_reg and reg_reloaded_contents keep track of
4024 which registers are already available in reload registers.
4025 We update these for the reloads that we perform,
4026 as the insns are scanned. */
4029 reload_as_needed (int live_known)
4031 struct insn_chain *chain;
4032 #if defined (AUTO_INC_DEC)
4037 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4038 memset (spill_reg_store, 0, sizeof spill_reg_store);
4039 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4040 INIT_REG_SET (®_has_output_reload);
4041 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4042 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4044 set_initial_elim_offsets ();
4046 for (chain = reload_insn_chain; chain; chain = chain->next)
4049 rtx insn = chain->insn;
4050 rtx old_next = NEXT_INSN (insn);
4052 /* If we pass a label, copy the offsets from the label information
4053 into the current offsets of each elimination. */
4055 set_offsets_for_label (insn);
4057 else if (INSN_P (insn))
4059 regset_head regs_to_forget;
4060 INIT_REG_SET (®s_to_forget);
4061 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4063 /* If this is a USE and CLOBBER of a MEM, ensure that any
4064 references to eliminable registers have been removed. */
4066 if ((GET_CODE (PATTERN (insn)) == USE
4067 || GET_CODE (PATTERN (insn)) == CLOBBER)
4068 && MEM_P (XEXP (PATTERN (insn), 0)))
4069 XEXP (XEXP (PATTERN (insn), 0), 0)
4070 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4071 GET_MODE (XEXP (PATTERN (insn), 0)),
4074 /* If we need to do register elimination processing, do so.
4075 This might delete the insn, in which case we are done. */
4076 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4078 eliminate_regs_in_insn (insn, 1);
4081 update_eliminable_offsets ();
4082 CLEAR_REG_SET (®s_to_forget);
4087 /* If need_elim is nonzero but need_reload is zero, one might think
4088 that we could simply set n_reloads to 0. However, find_reloads
4089 could have done some manipulation of the insn (such as swapping
4090 commutative operands), and these manipulations are lost during
4091 the first pass for every insn that needs register elimination.
4092 So the actions of find_reloads must be redone here. */
4094 if (! chain->need_elim && ! chain->need_reload
4095 && ! chain->need_operand_change)
4097 /* First find the pseudo regs that must be reloaded for this insn.
4098 This info is returned in the tables reload_... (see reload.h).
4099 Also modify the body of INSN by substituting RELOAD
4100 rtx's for those pseudo regs. */
4103 CLEAR_REG_SET (®_has_output_reload);
4104 CLEAR_HARD_REG_SET (reg_is_output_reload);
4106 find_reloads (insn, 1, spill_indirect_levels, live_known,
4112 rtx next = NEXT_INSN (insn);
4115 prev = PREV_INSN (insn);
4117 /* Now compute which reload regs to reload them into. Perhaps
4118 reusing reload regs from previous insns, or else output
4119 load insns to reload them. Maybe output store insns too.
4120 Record the choices of reload reg in reload_reg_rtx. */
4121 choose_reload_regs (chain);
4123 /* Merge any reloads that we didn't combine for fear of
4124 increasing the number of spill registers needed but now
4125 discover can be safely merged. */
4126 if (SMALL_REGISTER_CLASSES)
4127 merge_assigned_reloads (insn);
4129 /* Generate the insns to reload operands into or out of
4130 their reload regs. */
4131 emit_reload_insns (chain);
4133 /* Substitute the chosen reload regs from reload_reg_rtx
4134 into the insn's body (or perhaps into the bodies of other
4135 load and store insn that we just made for reloading
4136 and that we moved the structure into). */
4137 subst_reloads (insn);
4139 /* Adjust the exception region notes for loads and stores. */
4140 if (flag_non_call_exceptions && !CALL_P (insn))
4141 fixup_eh_region_note (insn, prev, next);
4143 /* If this was an ASM, make sure that all the reload insns
4144 we have generated are valid. If not, give an error
4146 if (asm_noperands (PATTERN (insn)) >= 0)
4147 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4148 if (p != insn && INSN_P (p)
4149 && GET_CODE (PATTERN (p)) != USE
4150 && (recog_memoized (p) < 0
4151 || (extract_insn (p), ! constrain_operands (1))))
4153 error_for_asm (insn,
4154 "%<asm%> operand requires "
4155 "impossible reload");
4160 if (num_eliminable && chain->need_elim)
4161 update_eliminable_offsets ();
4163 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4164 is no longer validly lying around to save a future reload.
4165 Note that this does not detect pseudos that were reloaded
4166 for this insn in order to be stored in
4167 (obeying register constraints). That is correct; such reload
4168 registers ARE still valid. */
4169 forget_marked_reloads (®s_to_forget);
4170 CLEAR_REG_SET (®s_to_forget);
4172 /* There may have been CLOBBER insns placed after INSN. So scan
4173 between INSN and NEXT and use them to forget old reloads. */
4174 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4175 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4176 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4179 /* Likewise for regs altered by auto-increment in this insn.
4180 REG_INC notes have been changed by reloading:
4181 find_reloads_address_1 records substitutions for them,
4182 which have been performed by subst_reloads above. */
4183 for (i = n_reloads - 1; i >= 0; i--)
4185 rtx in_reg = rld[i].in_reg;
4188 enum rtx_code code = GET_CODE (in_reg);
4189 /* PRE_INC / PRE_DEC will have the reload register ending up
4190 with the same value as the stack slot, but that doesn't
4191 hold true for POST_INC / POST_DEC. Either we have to
4192 convert the memory access to a true POST_INC / POST_DEC,
4193 or we can't use the reload register for inheritance. */
4194 if ((code == POST_INC || code == POST_DEC)
4195 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4196 REGNO (rld[i].reg_rtx))
4197 /* Make sure it is the inc/dec pseudo, and not
4198 some other (e.g. output operand) pseudo. */
4199 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4200 == REGNO (XEXP (in_reg, 0))))
4203 rtx reload_reg = rld[i].reg_rtx;
4204 enum machine_mode mode = GET_MODE (reload_reg);
4208 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4210 /* We really want to ignore REG_INC notes here, so
4211 use PATTERN (p) as argument to reg_set_p . */
4212 if (reg_set_p (reload_reg, PATTERN (p)))
4214 n = count_occurrences (PATTERN (p), reload_reg, 0);
4219 n = validate_replace_rtx (reload_reg,
4220 gen_rtx_fmt_e (code,
4225 /* We must also verify that the constraints
4226 are met after the replacement. */
4229 n = constrain_operands (1);
4233 /* If the constraints were not met, then
4234 undo the replacement. */
4237 validate_replace_rtx (gen_rtx_fmt_e (code,
4250 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4252 /* Mark this as having an output reload so that the
4253 REG_INC processing code below won't invalidate
4254 the reload for inheritance. */
4255 SET_HARD_REG_BIT (reg_is_output_reload,
4256 REGNO (reload_reg));
4257 SET_REGNO_REG_SET (®_has_output_reload,
4258 REGNO (XEXP (in_reg, 0)));
4261 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4264 else if ((code == PRE_INC || code == PRE_DEC)
4265 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4266 REGNO (rld[i].reg_rtx))
4267 /* Make sure it is the inc/dec pseudo, and not
4268 some other (e.g. output operand) pseudo. */
4269 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4270 == REGNO (XEXP (in_reg, 0))))
4272 SET_HARD_REG_BIT (reg_is_output_reload,
4273 REGNO (rld[i].reg_rtx));
4274 SET_REGNO_REG_SET (®_has_output_reload,
4275 REGNO (XEXP (in_reg, 0)));
4279 /* If a pseudo that got a hard register is auto-incremented,
4280 we must purge records of copying it into pseudos without
4282 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4283 if (REG_NOTE_KIND (x) == REG_INC)
4285 /* See if this pseudo reg was reloaded in this insn.
4286 If so, its last-reload info is still valid
4287 because it is based on this insn's reload. */
4288 for (i = 0; i < n_reloads; i++)
4289 if (rld[i].out == XEXP (x, 0))
4293 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4297 /* A reload reg's contents are unknown after a label. */
4299 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4301 /* Don't assume a reload reg is still good after a call insn
4302 if it is a call-used reg, or if it contains a value that will
4303 be partially clobbered by the call. */
4304 else if (CALL_P (insn))
4306 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4307 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4312 free (reg_last_reload_reg);
4313 CLEAR_REG_SET (®_has_output_reload);
4316 /* Discard all record of any value reloaded from X,
4317 or reloaded in X from someplace else;
4318 unless X is an output reload reg of the current insn.
4320 X may be a hard reg (the reload reg)
4321 or it may be a pseudo reg that was reloaded from.
4323 When DATA is non-NULL just mark the registers in regset
4324 to be forgotten later. */
4327 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4332 regset regs = (regset) data;
4334 /* note_stores does give us subregs of hard regs,
4335 subreg_regno_offset requires a hard reg. */
4336 while (GET_CODE (x) == SUBREG)
4338 /* We ignore the subreg offset when calculating the regno,
4339 because we are using the entire underlying hard register
4349 if (regno >= FIRST_PSEUDO_REGISTER)
4355 nr = hard_regno_nregs[regno][GET_MODE (x)];
4356 /* Storing into a spilled-reg invalidates its contents.
4357 This can happen if a block-local pseudo is allocated to that reg
4358 and it wasn't spilled because this block's total need is 0.
4359 Then some insn might have an optional reload and use this reg. */
4361 for (i = 0; i < nr; i++)
4362 /* But don't do this if the reg actually serves as an output
4363 reload reg in the current instruction. */
4365 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4367 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4368 spill_reg_store[regno + i] = 0;
4374 SET_REGNO_REG_SET (regs, regno + nr);
4377 /* Since value of X has changed,
4378 forget any value previously copied from it. */
4381 /* But don't forget a copy if this is the output reload
4382 that establishes the copy's validity. */
4384 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4385 reg_last_reload_reg[regno + nr] = 0;
4389 /* Forget the reloads marked in regset by previous function. */
4391 forget_marked_reloads (regset regs)
4394 reg_set_iterator rsi;
4395 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4397 if (reg < FIRST_PSEUDO_REGISTER
4398 /* But don't do this if the reg actually serves as an output
4399 reload reg in the current instruction. */
4401 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4403 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4404 spill_reg_store[reg] = 0;
4407 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4408 reg_last_reload_reg[reg] = 0;
4412 /* The following HARD_REG_SETs indicate when each hard register is
4413 used for a reload of various parts of the current insn. */
4415 /* If reg is unavailable for all reloads. */
4416 static HARD_REG_SET reload_reg_unavailable;
4417 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4418 static HARD_REG_SET reload_reg_used;
4419 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4420 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4421 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4422 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4423 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4424 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4425 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4426 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4427 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4428 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4429 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4430 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4431 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4432 static HARD_REG_SET reload_reg_used_in_op_addr;
4433 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4434 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4435 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4436 static HARD_REG_SET reload_reg_used_in_insn;
4437 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4438 static HARD_REG_SET reload_reg_used_in_other_addr;
4440 /* If reg is in use as a reload reg for any sort of reload. */
4441 static HARD_REG_SET reload_reg_used_at_all;
4443 /* If reg is use as an inherited reload. We just mark the first register
4445 static HARD_REG_SET reload_reg_used_for_inherit;
4447 /* Records which hard regs are used in any way, either as explicit use or
4448 by being allocated to a pseudo during any point of the current insn. */
4449 static HARD_REG_SET reg_used_in_insn;
4451 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4452 TYPE. MODE is used to indicate how many consecutive regs are
4456 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4457 enum machine_mode mode)
4459 unsigned int nregs = hard_regno_nregs[regno][mode];
4462 for (i = regno; i < nregs + regno; i++)
4467 SET_HARD_REG_BIT (reload_reg_used, i);
4470 case RELOAD_FOR_INPUT_ADDRESS:
4471 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4474 case RELOAD_FOR_INPADDR_ADDRESS:
4475 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4478 case RELOAD_FOR_OUTPUT_ADDRESS:
4479 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4482 case RELOAD_FOR_OUTADDR_ADDRESS:
4483 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4486 case RELOAD_FOR_OPERAND_ADDRESS:
4487 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4490 case RELOAD_FOR_OPADDR_ADDR:
4491 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4494 case RELOAD_FOR_OTHER_ADDRESS:
4495 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4498 case RELOAD_FOR_INPUT:
4499 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4502 case RELOAD_FOR_OUTPUT:
4503 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4506 case RELOAD_FOR_INSN:
4507 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4511 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4515 /* Similarly, but show REGNO is no longer in use for a reload. */
4518 clear_reload_reg_in_use (unsigned int regno, int opnum,
4519 enum reload_type type, enum machine_mode mode)
4521 unsigned int nregs = hard_regno_nregs[regno][mode];
4522 unsigned int start_regno, end_regno, r;
4524 /* A complication is that for some reload types, inheritance might
4525 allow multiple reloads of the same types to share a reload register.
4526 We set check_opnum if we have to check only reloads with the same
4527 operand number, and check_any if we have to check all reloads. */
4528 int check_opnum = 0;
4530 HARD_REG_SET *used_in_set;
4535 used_in_set = &reload_reg_used;
4538 case RELOAD_FOR_INPUT_ADDRESS:
4539 used_in_set = &reload_reg_used_in_input_addr[opnum];
4542 case RELOAD_FOR_INPADDR_ADDRESS:
4544 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4547 case RELOAD_FOR_OUTPUT_ADDRESS:
4548 used_in_set = &reload_reg_used_in_output_addr[opnum];
4551 case RELOAD_FOR_OUTADDR_ADDRESS:
4553 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4556 case RELOAD_FOR_OPERAND_ADDRESS:
4557 used_in_set = &reload_reg_used_in_op_addr;
4560 case RELOAD_FOR_OPADDR_ADDR:
4562 used_in_set = &reload_reg_used_in_op_addr_reload;
4565 case RELOAD_FOR_OTHER_ADDRESS:
4566 used_in_set = &reload_reg_used_in_other_addr;
4570 case RELOAD_FOR_INPUT:
4571 used_in_set = &reload_reg_used_in_input[opnum];
4574 case RELOAD_FOR_OUTPUT:
4575 used_in_set = &reload_reg_used_in_output[opnum];
4578 case RELOAD_FOR_INSN:
4579 used_in_set = &reload_reg_used_in_insn;
4584 /* We resolve conflicts with remaining reloads of the same type by
4585 excluding the intervals of reload registers by them from the
4586 interval of freed reload registers. Since we only keep track of
4587 one set of interval bounds, we might have to exclude somewhat
4588 more than what would be necessary if we used a HARD_REG_SET here.
4589 But this should only happen very infrequently, so there should
4590 be no reason to worry about it. */
4592 start_regno = regno;
4593 end_regno = regno + nregs;
4594 if (check_opnum || check_any)
4596 for (i = n_reloads - 1; i >= 0; i--)
4598 if (rld[i].when_needed == type
4599 && (check_any || rld[i].opnum == opnum)
4602 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4603 unsigned int conflict_end
4604 = end_hard_regno (rld[i].mode, conflict_start);
4606 /* If there is an overlap with the first to-be-freed register,
4607 adjust the interval start. */
4608 if (conflict_start <= start_regno && conflict_end > start_regno)
4609 start_regno = conflict_end;
4610 /* Otherwise, if there is a conflict with one of the other
4611 to-be-freed registers, adjust the interval end. */
4612 if (conflict_start > start_regno && conflict_start < end_regno)
4613 end_regno = conflict_start;
4618 for (r = start_regno; r < end_regno; r++)
4619 CLEAR_HARD_REG_BIT (*used_in_set, r);
4622 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4623 specified by OPNUM and TYPE. */
4626 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4630 /* In use for a RELOAD_OTHER means it's not available for anything. */
4631 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4632 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4638 /* In use for anything means we can't use it for RELOAD_OTHER. */
4639 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4640 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4641 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4642 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4645 for (i = 0; i < reload_n_operands; i++)
4646 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4647 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4648 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4649 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4650 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4651 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4656 case RELOAD_FOR_INPUT:
4657 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4658 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4661 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4664 /* If it is used for some other input, can't use it. */
4665 for (i = 0; i < reload_n_operands; i++)
4666 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4669 /* If it is used in a later operand's address, can't use it. */
4670 for (i = opnum + 1; i < reload_n_operands; i++)
4671 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4672 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4677 case RELOAD_FOR_INPUT_ADDRESS:
4678 /* Can't use a register if it is used for an input address for this
4679 operand or used as an input in an earlier one. */
4680 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4681 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4684 for (i = 0; i < opnum; i++)
4685 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4690 case RELOAD_FOR_INPADDR_ADDRESS:
4691 /* Can't use a register if it is used for an input address
4692 for this operand or used as an input in an earlier
4694 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4697 for (i = 0; i < opnum; i++)
4698 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4703 case RELOAD_FOR_OUTPUT_ADDRESS:
4704 /* Can't use a register if it is used for an output address for this
4705 operand or used as an output in this or a later operand. Note
4706 that multiple output operands are emitted in reverse order, so
4707 the conflicting ones are those with lower indices. */
4708 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4711 for (i = 0; i <= opnum; i++)
4712 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4717 case RELOAD_FOR_OUTADDR_ADDRESS:
4718 /* Can't use a register if it is used for an output address
4719 for this operand or used as an output in this or a
4720 later operand. Note that multiple output operands are
4721 emitted in reverse order, so the conflicting ones are
4722 those with lower indices. */
4723 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4726 for (i = 0; i <= opnum; i++)
4727 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4732 case RELOAD_FOR_OPERAND_ADDRESS:
4733 for (i = 0; i < reload_n_operands; i++)
4734 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4737 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4738 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4740 case RELOAD_FOR_OPADDR_ADDR:
4741 for (i = 0; i < reload_n_operands; i++)
4742 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4745 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4747 case RELOAD_FOR_OUTPUT:
4748 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4749 outputs, or an operand address for this or an earlier output.
4750 Note that multiple output operands are emitted in reverse order,
4751 so the conflicting ones are those with higher indices. */
4752 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4755 for (i = 0; i < reload_n_operands; i++)
4756 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4759 for (i = opnum; i < reload_n_operands; i++)
4760 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4761 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4766 case RELOAD_FOR_INSN:
4767 for (i = 0; i < reload_n_operands; i++)
4768 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4769 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4772 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4773 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4775 case RELOAD_FOR_OTHER_ADDRESS:
4776 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4783 /* Return 1 if the value in reload reg REGNO, as used by a reload
4784 needed for the part of the insn specified by OPNUM and TYPE,
4785 is still available in REGNO at the end of the insn.
4787 We can assume that the reload reg was already tested for availability
4788 at the time it is needed, and we should not check this again,
4789 in case the reg has already been marked in use. */
4792 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4799 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4800 its value must reach the end. */
4803 /* If this use is for part of the insn,
4804 its value reaches if no subsequent part uses the same register.
4805 Just like the above function, don't try to do this with lots
4808 case RELOAD_FOR_OTHER_ADDRESS:
4809 /* Here we check for everything else, since these don't conflict
4810 with anything else and everything comes later. */
4812 for (i = 0; i < reload_n_operands; i++)
4813 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4814 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4815 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4816 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4817 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4818 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4821 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4822 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4823 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4824 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4826 case RELOAD_FOR_INPUT_ADDRESS:
4827 case RELOAD_FOR_INPADDR_ADDRESS:
4828 /* Similar, except that we check only for this and subsequent inputs
4829 and the address of only subsequent inputs and we do not need
4830 to check for RELOAD_OTHER objects since they are known not to
4833 for (i = opnum; i < reload_n_operands; i++)
4834 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4837 for (i = opnum + 1; i < reload_n_operands; i++)
4838 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4839 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4842 for (i = 0; i < reload_n_operands; i++)
4843 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4844 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4845 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4848 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4851 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4852 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4853 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4855 case RELOAD_FOR_INPUT:
4856 /* Similar to input address, except we start at the next operand for
4857 both input and input address and we do not check for
4858 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4861 for (i = opnum + 1; i < reload_n_operands; i++)
4862 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4863 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4864 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4867 /* ... fall through ... */
4869 case RELOAD_FOR_OPERAND_ADDRESS:
4870 /* Check outputs and their addresses. */
4872 for (i = 0; i < reload_n_operands; i++)
4873 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4874 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4875 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4878 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4880 case RELOAD_FOR_OPADDR_ADDR:
4881 for (i = 0; i < reload_n_operands; i++)
4882 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4883 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4884 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4887 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4888 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4889 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4891 case RELOAD_FOR_INSN:
4892 /* These conflict with other outputs with RELOAD_OTHER. So
4893 we need only check for output addresses. */
4895 opnum = reload_n_operands;
4897 /* ... fall through ... */
4899 case RELOAD_FOR_OUTPUT:
4900 case RELOAD_FOR_OUTPUT_ADDRESS:
4901 case RELOAD_FOR_OUTADDR_ADDRESS:
4902 /* We already know these can't conflict with a later output. So the
4903 only thing to check are later output addresses.
4904 Note that multiple output operands are emitted in reverse order,
4905 so the conflicting ones are those with lower indices. */
4906 for (i = 0; i < opnum; i++)
4907 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4908 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4918 /* Like reload_reg_reaches_end_p, but check that the condition holds for
4919 every register in the range [REGNO, REGNO + NREGS). */
4922 reload_regs_reach_end_p (unsigned int regno, int nregs,
4923 int opnum, enum reload_type type)
4927 for (i = 0; i < nregs; i++)
4928 if (!reload_reg_reaches_end_p (regno + i, opnum, type))
4934 /* Returns whether R1 and R2 are uniquely chained: the value of one
4935 is used by the other, and that value is not used by any other
4936 reload for this insn. This is used to partially undo the decision
4937 made in find_reloads when in the case of multiple
4938 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
4939 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
4940 reloads. This code tries to avoid the conflict created by that
4941 change. It might be cleaner to explicitly keep track of which
4942 RELOAD_FOR_OPADDR_ADDR reload is associated with which
4943 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
4944 this after the fact. */
4946 reloads_unique_chain_p (int r1, int r2)
4950 /* We only check input reloads. */
4951 if (! rld[r1].in || ! rld[r2].in)
4954 /* Avoid anything with output reloads. */
4955 if (rld[r1].out || rld[r2].out)
4958 /* "chained" means one reload is a component of the other reload,
4959 not the same as the other reload. */
4960 if (rld[r1].opnum != rld[r2].opnum
4961 || rtx_equal_p (rld[r1].in, rld[r2].in)
4962 || rld[r1].optional || rld[r2].optional
4963 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
4964 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
4967 for (i = 0; i < n_reloads; i ++)
4968 /* Look for input reloads that aren't our two */
4969 if (i != r1 && i != r2 && rld[i].in)
4971 /* If our reload is mentioned at all, it isn't a simple chain. */
4972 if (reg_mentioned_p (rld[r1].in, rld[i].in))
4978 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4981 This function uses the same algorithm as reload_reg_free_p above. */
4984 reloads_conflict (int r1, int r2)
4986 enum reload_type r1_type = rld[r1].when_needed;
4987 enum reload_type r2_type = rld[r2].when_needed;
4988 int r1_opnum = rld[r1].opnum;
4989 int r2_opnum = rld[r2].opnum;
4991 /* RELOAD_OTHER conflicts with everything. */
4992 if (r2_type == RELOAD_OTHER)
4995 /* Otherwise, check conflicts differently for each type. */
4999 case RELOAD_FOR_INPUT:
5000 return (r2_type == RELOAD_FOR_INSN
5001 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5002 || r2_type == RELOAD_FOR_OPADDR_ADDR
5003 || r2_type == RELOAD_FOR_INPUT
5004 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5005 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5006 && r2_opnum > r1_opnum));
5008 case RELOAD_FOR_INPUT_ADDRESS:
5009 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5010 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5012 case RELOAD_FOR_INPADDR_ADDRESS:
5013 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5014 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5016 case RELOAD_FOR_OUTPUT_ADDRESS:
5017 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5018 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5020 case RELOAD_FOR_OUTADDR_ADDRESS:
5021 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5022 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5024 case RELOAD_FOR_OPERAND_ADDRESS:
5025 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5026 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5027 && !reloads_unique_chain_p (r1, r2)));
5029 case RELOAD_FOR_OPADDR_ADDR:
5030 return (r2_type == RELOAD_FOR_INPUT
5031 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5033 case RELOAD_FOR_OUTPUT:
5034 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5035 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5036 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5037 && r2_opnum >= r1_opnum));
5039 case RELOAD_FOR_INSN:
5040 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5041 || r2_type == RELOAD_FOR_INSN
5042 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5044 case RELOAD_FOR_OTHER_ADDRESS:
5045 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5055 /* Indexed by reload number, 1 if incoming value
5056 inherited from previous insns. */
5057 static char reload_inherited[MAX_RELOADS];
5059 /* For an inherited reload, this is the insn the reload was inherited from,
5060 if we know it. Otherwise, this is 0. */
5061 static rtx reload_inheritance_insn[MAX_RELOADS];
5063 /* If nonzero, this is a place to get the value of the reload,
5064 rather than using reload_in. */
5065 static rtx reload_override_in[MAX_RELOADS];
5067 /* For each reload, the hard register number of the register used,
5068 or -1 if we did not need a register for this reload. */
5069 static int reload_spill_index[MAX_RELOADS];
5071 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5072 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5074 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5075 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5077 /* Subroutine of free_for_value_p, used to check a single register.
5078 START_REGNO is the starting regno of the full reload register
5079 (possibly comprising multiple hard registers) that we are considering. */
5082 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5083 enum reload_type type, rtx value, rtx out,
5084 int reloadnum, int ignore_address_reloads)
5087 /* Set if we see an input reload that must not share its reload register
5088 with any new earlyclobber, but might otherwise share the reload
5089 register with an output or input-output reload. */
5090 int check_earlyclobber = 0;
5094 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5097 if (out == const0_rtx)
5103 /* We use some pseudo 'time' value to check if the lifetimes of the
5104 new register use would overlap with the one of a previous reload
5105 that is not read-only or uses a different value.
5106 The 'time' used doesn't have to be linear in any shape or form, just
5108 Some reload types use different 'buckets' for each operand.
5109 So there are MAX_RECOG_OPERANDS different time values for each
5111 We compute TIME1 as the time when the register for the prospective
5112 new reload ceases to be live, and TIME2 for each existing
5113 reload as the time when that the reload register of that reload
5115 Where there is little to be gained by exact lifetime calculations,
5116 we just make conservative assumptions, i.e. a longer lifetime;
5117 this is done in the 'default:' cases. */
5120 case RELOAD_FOR_OTHER_ADDRESS:
5121 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5122 time1 = copy ? 0 : 1;
5125 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5127 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5128 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5129 respectively, to the time values for these, we get distinct time
5130 values. To get distinct time values for each operand, we have to
5131 multiply opnum by at least three. We round that up to four because
5132 multiply by four is often cheaper. */
5133 case RELOAD_FOR_INPADDR_ADDRESS:
5134 time1 = opnum * 4 + 2;
5136 case RELOAD_FOR_INPUT_ADDRESS:
5137 time1 = opnum * 4 + 3;
5139 case RELOAD_FOR_INPUT:
5140 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5141 executes (inclusive). */
5142 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5144 case RELOAD_FOR_OPADDR_ADDR:
5146 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5147 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5149 case RELOAD_FOR_OPERAND_ADDRESS:
5150 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5152 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5154 case RELOAD_FOR_OUTADDR_ADDRESS:
5155 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5157 case RELOAD_FOR_OUTPUT_ADDRESS:
5158 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5161 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5164 for (i = 0; i < n_reloads; i++)
5166 rtx reg = rld[i].reg_rtx;
5167 if (reg && REG_P (reg)
5168 && ((unsigned) regno - true_regnum (reg)
5169 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5172 rtx other_input = rld[i].in;
5174 /* If the other reload loads the same input value, that
5175 will not cause a conflict only if it's loading it into
5176 the same register. */
5177 if (true_regnum (reg) != start_regno)
5178 other_input = NULL_RTX;
5179 if (! other_input || ! rtx_equal_p (other_input, value)
5180 || rld[i].out || out)
5183 switch (rld[i].when_needed)
5185 case RELOAD_FOR_OTHER_ADDRESS:
5188 case RELOAD_FOR_INPADDR_ADDRESS:
5189 /* find_reloads makes sure that a
5190 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5191 by at most one - the first -
5192 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5193 address reload is inherited, the address address reload
5194 goes away, so we can ignore this conflict. */
5195 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5196 && ignore_address_reloads
5197 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5198 Then the address address is still needed to store
5199 back the new address. */
5200 && ! rld[reloadnum].out)
5202 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5203 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5205 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5206 && ignore_address_reloads
5207 /* Unless we are reloading an auto_inc expression. */
5208 && ! rld[reloadnum].out)
5210 time2 = rld[i].opnum * 4 + 2;
5212 case RELOAD_FOR_INPUT_ADDRESS:
5213 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5214 && ignore_address_reloads
5215 && ! rld[reloadnum].out)
5217 time2 = rld[i].opnum * 4 + 3;
5219 case RELOAD_FOR_INPUT:
5220 time2 = rld[i].opnum * 4 + 4;
5221 check_earlyclobber = 1;
5223 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5224 == MAX_RECOG_OPERAND * 4 */
5225 case RELOAD_FOR_OPADDR_ADDR:
5226 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5227 && ignore_address_reloads
5228 && ! rld[reloadnum].out)
5230 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5232 case RELOAD_FOR_OPERAND_ADDRESS:
5233 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5234 check_earlyclobber = 1;
5236 case RELOAD_FOR_INSN:
5237 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5239 case RELOAD_FOR_OUTPUT:
5240 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5241 instruction is executed. */
5242 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5244 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5245 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5247 case RELOAD_FOR_OUTADDR_ADDRESS:
5248 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5249 && ignore_address_reloads
5250 && ! rld[reloadnum].out)
5252 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5254 case RELOAD_FOR_OUTPUT_ADDRESS:
5255 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5258 /* If there is no conflict in the input part, handle this
5259 like an output reload. */
5260 if (! rld[i].in || rtx_equal_p (other_input, value))
5262 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5263 /* Earlyclobbered outputs must conflict with inputs. */
5264 if (earlyclobber_operand_p (rld[i].out))
5265 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5270 /* RELOAD_OTHER might be live beyond instruction execution,
5271 but this is not obvious when we set time2 = 1. So check
5272 here if there might be a problem with the new reload
5273 clobbering the register used by the RELOAD_OTHER. */
5281 && (! rld[i].in || rld[i].out
5282 || ! rtx_equal_p (other_input, value)))
5283 || (out && rld[reloadnum].out_reg
5284 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5290 /* Earlyclobbered outputs must conflict with inputs. */
5291 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5297 /* Return 1 if the value in reload reg REGNO, as used by a reload
5298 needed for the part of the insn specified by OPNUM and TYPE,
5299 may be used to load VALUE into it.
5301 MODE is the mode in which the register is used, this is needed to
5302 determine how many hard regs to test.
5304 Other read-only reloads with the same value do not conflict
5305 unless OUT is nonzero and these other reloads have to live while
5306 output reloads live.
5307 If OUT is CONST0_RTX, this is a special case: it means that the
5308 test should not be for using register REGNO as reload register, but
5309 for copying from register REGNO into the reload register.
5311 RELOADNUM is the number of the reload we want to load this value for;
5312 a reload does not conflict with itself.
5314 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5315 reloads that load an address for the very reload we are considering.
5317 The caller has to make sure that there is no conflict with the return
5321 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5322 enum reload_type type, rtx value, rtx out, int reloadnum,
5323 int ignore_address_reloads)
5325 int nregs = hard_regno_nregs[regno][mode];
5327 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5328 value, out, reloadnum,
5329 ignore_address_reloads))
5334 /* Return nonzero if the rtx X is invariant over the current function. */
5335 /* ??? Actually, the places where we use this expect exactly what is
5336 tested here, and not everything that is function invariant. In
5337 particular, the frame pointer and arg pointer are special cased;
5338 pic_offset_table_rtx is not, and we must not spill these things to
5342 function_invariant_p (const_rtx x)
5346 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5348 if (GET_CODE (x) == PLUS
5349 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5350 && CONSTANT_P (XEXP (x, 1)))
5355 /* Determine whether the reload reg X overlaps any rtx'es used for
5356 overriding inheritance. Return nonzero if so. */
5359 conflicts_with_override (rtx x)
5362 for (i = 0; i < n_reloads; i++)
5363 if (reload_override_in[i]
5364 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5369 /* Give an error message saying we failed to find a reload for INSN,
5370 and clear out reload R. */
5372 failed_reload (rtx insn, int r)
5374 if (asm_noperands (PATTERN (insn)) < 0)
5375 /* It's the compiler's fault. */
5376 fatal_insn ("could not find a spill register", insn);
5378 /* It's the user's fault; the operand's mode and constraint
5379 don't match. Disable this reload so we don't crash in final. */
5380 error_for_asm (insn,
5381 "%<asm%> operand constraint incompatible with operand size");
5385 rld[r].optional = 1;
5386 rld[r].secondary_p = 1;
5389 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5390 for reload R. If it's valid, get an rtx for it. Return nonzero if
5393 set_reload_reg (int i, int r)
5396 rtx reg = spill_reg_rtx[i];
5398 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5399 spill_reg_rtx[i] = reg
5400 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5402 regno = true_regnum (reg);
5404 /* Detect when the reload reg can't hold the reload mode.
5405 This used to be one `if', but Sequent compiler can't handle that. */
5406 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5408 enum machine_mode test_mode = VOIDmode;
5410 test_mode = GET_MODE (rld[r].in);
5411 /* If rld[r].in has VOIDmode, it means we will load it
5412 in whatever mode the reload reg has: to wit, rld[r].mode.
5413 We have already tested that for validity. */
5414 /* Aside from that, we need to test that the expressions
5415 to reload from or into have modes which are valid for this
5416 reload register. Otherwise the reload insns would be invalid. */
5417 if (! (rld[r].in != 0 && test_mode != VOIDmode
5418 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5419 if (! (rld[r].out != 0
5420 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5422 /* The reg is OK. */
5425 /* Mark as in use for this insn the reload regs we use
5427 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5428 rld[r].when_needed, rld[r].mode);
5430 rld[r].reg_rtx = reg;
5431 reload_spill_index[r] = spill_regs[i];
5438 /* Find a spill register to use as a reload register for reload R.
5439 LAST_RELOAD is nonzero if this is the last reload for the insn being
5442 Set rld[R].reg_rtx to the register allocated.
5444 We return 1 if successful, or 0 if we couldn't find a spill reg and
5445 we didn't change anything. */
5448 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5453 /* If we put this reload ahead, thinking it is a group,
5454 then insist on finding a group. Otherwise we can grab a
5455 reg that some other reload needs.
5456 (That can happen when we have a 68000 DATA_OR_FP_REG
5457 which is a group of data regs or one fp reg.)
5458 We need not be so restrictive if there are no more reloads
5461 ??? Really it would be nicer to have smarter handling
5462 for that kind of reg class, where a problem like this is normal.
5463 Perhaps those classes should be avoided for reloading
5464 by use of more alternatives. */
5466 int force_group = rld[r].nregs > 1 && ! last_reload;
5468 /* If we want a single register and haven't yet found one,
5469 take any reg in the right class and not in use.
5470 If we want a consecutive group, here is where we look for it.
5472 We use two passes so we can first look for reload regs to
5473 reuse, which are already in use for other reloads in this insn,
5474 and only then use additional registers.
5475 I think that maximizing reuse is needed to make sure we don't
5476 run out of reload regs. Suppose we have three reloads, and
5477 reloads A and B can share regs. These need two regs.
5478 Suppose A and B are given different regs.
5479 That leaves none for C. */
5480 for (pass = 0; pass < 2; pass++)
5482 /* I is the index in spill_regs.
5483 We advance it round-robin between insns to use all spill regs
5484 equally, so that inherited reloads have a chance
5485 of leapfrogging each other. */
5489 for (count = 0; count < n_spills; count++)
5491 int class = (int) rld[r].class;
5497 regnum = spill_regs[i];
5499 if ((reload_reg_free_p (regnum, rld[r].opnum,
5502 /* We check reload_reg_used to make sure we
5503 don't clobber the return register. */
5504 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5505 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5506 rld[r].when_needed, rld[r].in,
5508 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5509 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5510 /* Look first for regs to share, then for unshared. But
5511 don't share regs used for inherited reloads; they are
5512 the ones we want to preserve. */
5514 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5516 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5519 int nr = hard_regno_nregs[regnum][rld[r].mode];
5520 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5521 (on 68000) got us two FP regs. If NR is 1,
5522 we would reject both of them. */
5525 /* If we need only one reg, we have already won. */
5528 /* But reject a single reg if we demand a group. */
5533 /* Otherwise check that as many consecutive regs as we need
5534 are available here. */
5537 int regno = regnum + nr - 1;
5538 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5539 && spill_reg_order[regno] >= 0
5540 && reload_reg_free_p (regno, rld[r].opnum,
5541 rld[r].when_needed)))
5550 /* If we found something on pass 1, omit pass 2. */
5551 if (count < n_spills)
5555 /* We should have found a spill register by now. */
5556 if (count >= n_spills)
5559 /* I is the index in SPILL_REG_RTX of the reload register we are to
5560 allocate. Get an rtx for it and find its register number. */
5562 return set_reload_reg (i, r);
5565 /* Initialize all the tables needed to allocate reload registers.
5566 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5567 is the array we use to restore the reg_rtx field for every reload. */
5570 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5574 for (i = 0; i < n_reloads; i++)
5575 rld[i].reg_rtx = save_reload_reg_rtx[i];
5577 memset (reload_inherited, 0, MAX_RELOADS);
5578 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5579 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5581 CLEAR_HARD_REG_SET (reload_reg_used);
5582 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5583 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5584 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5585 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5586 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5588 CLEAR_HARD_REG_SET (reg_used_in_insn);
5591 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5592 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5593 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5594 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5595 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5596 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5599 for (i = 0; i < reload_n_operands; i++)
5601 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5602 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5603 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5604 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5605 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5606 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5609 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5611 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5613 for (i = 0; i < n_reloads; i++)
5614 /* If we have already decided to use a certain register,
5615 don't use it in another way. */
5617 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5618 rld[i].when_needed, rld[i].mode);
5621 /* Assign hard reg targets for the pseudo-registers we must reload
5622 into hard regs for this insn.
5623 Also output the instructions to copy them in and out of the hard regs.
5625 For machines with register classes, we are responsible for
5626 finding a reload reg in the proper class. */
5629 choose_reload_regs (struct insn_chain *chain)
5631 rtx insn = chain->insn;
5633 unsigned int max_group_size = 1;
5634 enum reg_class group_class = NO_REGS;
5635 int pass, win, inheritance;
5637 rtx save_reload_reg_rtx[MAX_RELOADS];
5639 /* In order to be certain of getting the registers we need,
5640 we must sort the reloads into order of increasing register class.
5641 Then our grabbing of reload registers will parallel the process
5642 that provided the reload registers.
5644 Also note whether any of the reloads wants a consecutive group of regs.
5645 If so, record the maximum size of the group desired and what
5646 register class contains all the groups needed by this insn. */
5648 for (j = 0; j < n_reloads; j++)
5650 reload_order[j] = j;
5651 if (rld[j].reg_rtx != NULL_RTX)
5653 gcc_assert (REG_P (rld[j].reg_rtx)
5654 && HARD_REGISTER_P (rld[j].reg_rtx));
5655 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
5658 reload_spill_index[j] = -1;
5660 if (rld[j].nregs > 1)
5662 max_group_size = MAX (rld[j].nregs, max_group_size);
5664 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5667 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5671 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5673 /* If -O, try first with inheritance, then turning it off.
5674 If not -O, don't do inheritance.
5675 Using inheritance when not optimizing leads to paradoxes
5676 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5677 because one side of the comparison might be inherited. */
5679 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5681 choose_reload_regs_init (chain, save_reload_reg_rtx);
5683 /* Process the reloads in order of preference just found.
5684 Beyond this point, subregs can be found in reload_reg_rtx.
5686 This used to look for an existing reloaded home for all of the
5687 reloads, and only then perform any new reloads. But that could lose
5688 if the reloads were done out of reg-class order because a later
5689 reload with a looser constraint might have an old home in a register
5690 needed by an earlier reload with a tighter constraint.
5692 To solve this, we make two passes over the reloads, in the order
5693 described above. In the first pass we try to inherit a reload
5694 from a previous insn. If there is a later reload that needs a
5695 class that is a proper subset of the class being processed, we must
5696 also allocate a spill register during the first pass.
5698 Then make a second pass over the reloads to allocate any reloads
5699 that haven't been given registers yet. */
5701 for (j = 0; j < n_reloads; j++)
5703 int r = reload_order[j];
5704 rtx search_equiv = NULL_RTX;
5706 /* Ignore reloads that got marked inoperative. */
5707 if (rld[r].out == 0 && rld[r].in == 0
5708 && ! rld[r].secondary_p)
5711 /* If find_reloads chose to use reload_in or reload_out as a reload
5712 register, we don't need to chose one. Otherwise, try even if it
5713 found one since we might save an insn if we find the value lying
5715 Try also when reload_in is a pseudo without a hard reg. */
5716 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5717 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5718 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5719 && !MEM_P (rld[r].in)
5720 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5723 #if 0 /* No longer needed for correct operation.
5724 It might give better code, or might not; worth an experiment? */
5725 /* If this is an optional reload, we can't inherit from earlier insns
5726 until we are sure that any non-optional reloads have been allocated.
5727 The following code takes advantage of the fact that optional reloads
5728 are at the end of reload_order. */
5729 if (rld[r].optional != 0)
5730 for (i = 0; i < j; i++)
5731 if ((rld[reload_order[i]].out != 0
5732 || rld[reload_order[i]].in != 0
5733 || rld[reload_order[i]].secondary_p)
5734 && ! rld[reload_order[i]].optional
5735 && rld[reload_order[i]].reg_rtx == 0)
5736 allocate_reload_reg (chain, reload_order[i], 0);
5739 /* First see if this pseudo is already available as reloaded
5740 for a previous insn. We cannot try to inherit for reloads
5741 that are smaller than the maximum number of registers needed
5742 for groups unless the register we would allocate cannot be used
5745 We could check here to see if this is a secondary reload for
5746 an object that is already in a register of the desired class.
5747 This would avoid the need for the secondary reload register.
5748 But this is complex because we can't easily determine what
5749 objects might want to be loaded via this reload. So let a
5750 register be allocated here. In `emit_reload_insns' we suppress
5751 one of the loads in the case described above. */
5757 enum machine_mode mode = VOIDmode;
5761 else if (REG_P (rld[r].in))
5763 regno = REGNO (rld[r].in);
5764 mode = GET_MODE (rld[r].in);
5766 else if (REG_P (rld[r].in_reg))
5768 regno = REGNO (rld[r].in_reg);
5769 mode = GET_MODE (rld[r].in_reg);
5771 else if (GET_CODE (rld[r].in_reg) == SUBREG
5772 && REG_P (SUBREG_REG (rld[r].in_reg)))
5774 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5775 if (regno < FIRST_PSEUDO_REGISTER)
5776 regno = subreg_regno (rld[r].in_reg);
5778 byte = SUBREG_BYTE (rld[r].in_reg);
5779 mode = GET_MODE (rld[r].in_reg);
5782 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
5783 && REG_P (XEXP (rld[r].in_reg, 0)))
5785 regno = REGNO (XEXP (rld[r].in_reg, 0));
5786 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5787 rld[r].out = rld[r].in;
5791 /* This won't work, since REGNO can be a pseudo reg number.
5792 Also, it takes much more hair to keep track of all the things
5793 that can invalidate an inherited reload of part of a pseudoreg. */
5794 else if (GET_CODE (rld[r].in) == SUBREG
5795 && REG_P (SUBREG_REG (rld[r].in)))
5796 regno = subreg_regno (rld[r].in);
5800 && reg_last_reload_reg[regno] != 0
5801 #ifdef CANNOT_CHANGE_MODE_CLASS
5802 /* Verify that the register it's in can be used in
5804 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
5805 GET_MODE (reg_last_reload_reg[regno]),
5810 enum reg_class class = rld[r].class, last_class;
5811 rtx last_reg = reg_last_reload_reg[regno];
5812 enum machine_mode need_mode;
5814 i = REGNO (last_reg);
5815 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5816 last_class = REGNO_REG_CLASS (i);
5822 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5823 + byte * BITS_PER_UNIT,
5824 GET_MODE_CLASS (mode));
5826 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5827 >= GET_MODE_SIZE (need_mode))
5828 && reg_reloaded_contents[i] == regno
5829 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5830 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5831 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5832 /* Even if we can't use this register as a reload
5833 register, we might use it for reload_override_in,
5834 if copying it to the desired class is cheap
5836 || ((REGISTER_MOVE_COST (mode, last_class, class)
5837 < MEMORY_MOVE_COST (mode, class, 1))
5838 && (secondary_reload_class (1, class, mode,
5841 #ifdef SECONDARY_MEMORY_NEEDED
5842 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5847 && (rld[r].nregs == max_group_size
5848 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5850 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5851 rld[r].when_needed, rld[r].in,
5854 /* If a group is needed, verify that all the subsequent
5855 registers still have their values intact. */
5856 int nr = hard_regno_nregs[i][rld[r].mode];
5859 for (k = 1; k < nr; k++)
5860 if (reg_reloaded_contents[i + k] != regno
5861 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5869 last_reg = (GET_MODE (last_reg) == mode
5870 ? last_reg : gen_rtx_REG (mode, i));
5873 for (k = 0; k < nr; k++)
5874 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5877 /* We found a register that contains the
5878 value we need. If this register is the
5879 same as an `earlyclobber' operand of the
5880 current insn, just mark it as a place to
5881 reload from since we can't use it as the
5882 reload register itself. */
5884 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5885 if (reg_overlap_mentioned_for_reload_p
5886 (reg_last_reload_reg[regno],
5887 reload_earlyclobbers[i1]))
5890 if (i1 != n_earlyclobbers
5891 || ! (free_for_value_p (i, rld[r].mode,
5893 rld[r].when_needed, rld[r].in,
5895 /* Don't use it if we'd clobber a pseudo reg. */
5896 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5898 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5899 /* Don't clobber the frame pointer. */
5900 || (i == HARD_FRAME_POINTER_REGNUM
5901 && frame_pointer_needed
5903 /* Don't really use the inherited spill reg
5904 if we need it wider than we've got it. */
5905 || (GET_MODE_SIZE (rld[r].mode)
5906 > GET_MODE_SIZE (mode))
5909 /* If find_reloads chose reload_out as reload
5910 register, stay with it - that leaves the
5911 inherited register for subsequent reloads. */
5912 || (rld[r].out && rld[r].reg_rtx
5913 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5915 if (! rld[r].optional)
5917 reload_override_in[r] = last_reg;
5918 reload_inheritance_insn[r]
5919 = reg_reloaded_insn[i];
5925 /* We can use this as a reload reg. */
5926 /* Mark the register as in use for this part of
5928 mark_reload_reg_in_use (i,
5932 rld[r].reg_rtx = last_reg;
5933 reload_inherited[r] = 1;
5934 reload_inheritance_insn[r]
5935 = reg_reloaded_insn[i];
5936 reload_spill_index[r] = i;
5937 for (k = 0; k < nr; k++)
5938 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5946 /* Here's another way to see if the value is already lying around. */
5949 && ! reload_inherited[r]
5951 && (CONSTANT_P (rld[r].in)
5952 || GET_CODE (rld[r].in) == PLUS
5953 || REG_P (rld[r].in)
5954 || MEM_P (rld[r].in))
5955 && (rld[r].nregs == max_group_size
5956 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5957 search_equiv = rld[r].in;
5958 /* If this is an output reload from a simple move insn, look
5959 if an equivalence for the input is available. */
5960 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5962 rtx set = single_set (insn);
5965 && rtx_equal_p (rld[r].out, SET_DEST (set))
5966 && CONSTANT_P (SET_SRC (set)))
5967 search_equiv = SET_SRC (set);
5973 = find_equiv_reg (search_equiv, insn, rld[r].class,
5974 -1, NULL, 0, rld[r].mode);
5980 regno = REGNO (equiv);
5983 /* This must be a SUBREG of a hard register.
5984 Make a new REG since this might be used in an
5985 address and not all machines support SUBREGs
5987 gcc_assert (GET_CODE (equiv) == SUBREG);
5988 regno = subreg_regno (equiv);
5989 equiv = gen_rtx_REG (rld[r].mode, regno);
5990 /* If we choose EQUIV as the reload register, but the
5991 loop below decides to cancel the inheritance, we'll
5992 end up reloading EQUIV in rld[r].mode, not the mode
5993 it had originally. That isn't safe when EQUIV isn't
5994 available as a spill register since its value might
5995 still be live at this point. */
5996 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5997 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6002 /* If we found a spill reg, reject it unless it is free
6003 and of the desired class. */
6007 int bad_for_class = 0;
6008 int max_regno = regno + rld[r].nregs;
6010 for (i = regno; i < max_regno; i++)
6012 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6014 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
6019 && ! free_for_value_p (regno, rld[r].mode,
6020 rld[r].opnum, rld[r].when_needed,
6021 rld[r].in, rld[r].out, r, 1))
6026 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6029 /* We found a register that contains the value we need.
6030 If this register is the same as an `earlyclobber' operand
6031 of the current insn, just mark it as a place to reload from
6032 since we can't use it as the reload register itself. */
6035 for (i = 0; i < n_earlyclobbers; i++)
6036 if (reg_overlap_mentioned_for_reload_p (equiv,
6037 reload_earlyclobbers[i]))
6039 if (! rld[r].optional)
6040 reload_override_in[r] = equiv;
6045 /* If the equiv register we have found is explicitly clobbered
6046 in the current insn, it depends on the reload type if we
6047 can use it, use it for reload_override_in, or not at all.
6048 In particular, we then can't use EQUIV for a
6049 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6053 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6054 switch (rld[r].when_needed)
6056 case RELOAD_FOR_OTHER_ADDRESS:
6057 case RELOAD_FOR_INPADDR_ADDRESS:
6058 case RELOAD_FOR_INPUT_ADDRESS:
6059 case RELOAD_FOR_OPADDR_ADDR:
6062 case RELOAD_FOR_INPUT:
6063 case RELOAD_FOR_OPERAND_ADDRESS:
6064 if (! rld[r].optional)
6065 reload_override_in[r] = equiv;
6071 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6072 switch (rld[r].when_needed)
6074 case RELOAD_FOR_OTHER_ADDRESS:
6075 case RELOAD_FOR_INPADDR_ADDRESS:
6076 case RELOAD_FOR_INPUT_ADDRESS:
6077 case RELOAD_FOR_OPADDR_ADDR:
6078 case RELOAD_FOR_OPERAND_ADDRESS:
6079 case RELOAD_FOR_INPUT:
6082 if (! rld[r].optional)
6083 reload_override_in[r] = equiv;
6091 /* If we found an equivalent reg, say no code need be generated
6092 to load it, and use it as our reload reg. */
6094 && (regno != HARD_FRAME_POINTER_REGNUM
6095 || !frame_pointer_needed))
6097 int nr = hard_regno_nregs[regno][rld[r].mode];
6099 rld[r].reg_rtx = equiv;
6100 reload_inherited[r] = 1;
6102 /* If reg_reloaded_valid is not set for this register,
6103 there might be a stale spill_reg_store lying around.
6104 We must clear it, since otherwise emit_reload_insns
6105 might delete the store. */
6106 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6107 spill_reg_store[regno] = NULL_RTX;
6108 /* If any of the hard registers in EQUIV are spill
6109 registers, mark them as in use for this insn. */
6110 for (k = 0; k < nr; k++)
6112 i = spill_reg_order[regno + k];
6115 mark_reload_reg_in_use (regno, rld[r].opnum,
6118 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6125 /* If we found a register to use already, or if this is an optional
6126 reload, we are done. */
6127 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6131 /* No longer needed for correct operation. Might or might
6132 not give better code on the average. Want to experiment? */
6134 /* See if there is a later reload that has a class different from our
6135 class that intersects our class or that requires less register
6136 than our reload. If so, we must allocate a register to this
6137 reload now, since that reload might inherit a previous reload
6138 and take the only available register in our class. Don't do this
6139 for optional reloads since they will force all previous reloads
6140 to be allocated. Also don't do this for reloads that have been
6143 for (i = j + 1; i < n_reloads; i++)
6145 int s = reload_order[i];
6147 if ((rld[s].in == 0 && rld[s].out == 0
6148 && ! rld[s].secondary_p)
6152 if ((rld[s].class != rld[r].class
6153 && reg_classes_intersect_p (rld[r].class,
6155 || rld[s].nregs < rld[r].nregs)
6162 allocate_reload_reg (chain, r, j == n_reloads - 1);
6166 /* Now allocate reload registers for anything non-optional that
6167 didn't get one yet. */
6168 for (j = 0; j < n_reloads; j++)
6170 int r = reload_order[j];
6172 /* Ignore reloads that got marked inoperative. */
6173 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6176 /* Skip reloads that already have a register allocated or are
6178 if (rld[r].reg_rtx != 0 || rld[r].optional)
6181 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6185 /* If that loop got all the way, we have won. */
6192 /* Loop around and try without any inheritance. */
6197 /* First undo everything done by the failed attempt
6198 to allocate with inheritance. */
6199 choose_reload_regs_init (chain, save_reload_reg_rtx);
6201 /* Some sanity tests to verify that the reloads found in the first
6202 pass are identical to the ones we have now. */
6203 gcc_assert (chain->n_reloads == n_reloads);
6205 for (i = 0; i < n_reloads; i++)
6207 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6209 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6210 for (j = 0; j < n_spills; j++)
6211 if (spill_regs[j] == chain->rld[i].regno)
6212 if (! set_reload_reg (j, i))
6213 failed_reload (chain->insn, i);
6217 /* If we thought we could inherit a reload, because it seemed that
6218 nothing else wanted the same reload register earlier in the insn,
6219 verify that assumption, now that all reloads have been assigned.
6220 Likewise for reloads where reload_override_in has been set. */
6222 /* If doing expensive optimizations, do one preliminary pass that doesn't
6223 cancel any inheritance, but removes reloads that have been needed only
6224 for reloads that we know can be inherited. */
6225 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6227 for (j = 0; j < n_reloads; j++)
6229 int r = reload_order[j];
6231 if (reload_inherited[r] && rld[r].reg_rtx)
6232 check_reg = rld[r].reg_rtx;
6233 else if (reload_override_in[r]
6234 && (REG_P (reload_override_in[r])
6235 || GET_CODE (reload_override_in[r]) == SUBREG))
6236 check_reg = reload_override_in[r];
6239 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6240 rld[r].opnum, rld[r].when_needed, rld[r].in,
6241 (reload_inherited[r]
6242 ? rld[r].out : const0_rtx),
6247 reload_inherited[r] = 0;
6248 reload_override_in[r] = 0;
6250 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6251 reload_override_in, then we do not need its related
6252 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6253 likewise for other reload types.
6254 We handle this by removing a reload when its only replacement
6255 is mentioned in reload_in of the reload we are going to inherit.
6256 A special case are auto_inc expressions; even if the input is
6257 inherited, we still need the address for the output. We can
6258 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6259 If we succeeded removing some reload and we are doing a preliminary
6260 pass just to remove such reloads, make another pass, since the
6261 removal of one reload might allow us to inherit another one. */
6263 && rld[r].out != rld[r].in
6264 && remove_address_replacements (rld[r].in) && pass)
6269 /* Now that reload_override_in is known valid,
6270 actually override reload_in. */
6271 for (j = 0; j < n_reloads; j++)
6272 if (reload_override_in[j])
6273 rld[j].in = reload_override_in[j];
6275 /* If this reload won't be done because it has been canceled or is
6276 optional and not inherited, clear reload_reg_rtx so other
6277 routines (such as subst_reloads) don't get confused. */
6278 for (j = 0; j < n_reloads; j++)
6279 if (rld[j].reg_rtx != 0
6280 && ((rld[j].optional && ! reload_inherited[j])
6281 || (rld[j].in == 0 && rld[j].out == 0
6282 && ! rld[j].secondary_p)))
6284 int regno = true_regnum (rld[j].reg_rtx);
6286 if (spill_reg_order[regno] >= 0)
6287 clear_reload_reg_in_use (regno, rld[j].opnum,
6288 rld[j].when_needed, rld[j].mode);
6290 reload_spill_index[j] = -1;
6293 /* Record which pseudos and which spill regs have output reloads. */
6294 for (j = 0; j < n_reloads; j++)
6296 int r = reload_order[j];
6298 i = reload_spill_index[r];
6300 /* I is nonneg if this reload uses a register.
6301 If rld[r].reg_rtx is 0, this is an optional reload
6302 that we opted to ignore. */
6303 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6304 && rld[r].reg_rtx != 0)
6306 int nregno = REGNO (rld[r].out_reg);
6309 if (nregno < FIRST_PSEUDO_REGISTER)
6310 nr = hard_regno_nregs[nregno][rld[r].mode];
6313 SET_REGNO_REG_SET (®_has_output_reload,
6318 nr = hard_regno_nregs[i][rld[r].mode];
6320 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6323 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6324 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6325 || rld[r].when_needed == RELOAD_FOR_INSN);
6330 /* Deallocate the reload register for reload R. This is called from
6331 remove_address_replacements. */
6334 deallocate_reload_reg (int r)
6338 if (! rld[r].reg_rtx)
6340 regno = true_regnum (rld[r].reg_rtx);
6342 if (spill_reg_order[regno] >= 0)
6343 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6345 reload_spill_index[r] = -1;
6348 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6349 reloads of the same item for fear that we might not have enough reload
6350 registers. However, normally they will get the same reload register
6351 and hence actually need not be loaded twice.
6353 Here we check for the most common case of this phenomenon: when we have
6354 a number of reloads for the same object, each of which were allocated
6355 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6356 reload, and is not modified in the insn itself. If we find such,
6357 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6358 This will not increase the number of spill registers needed and will
6359 prevent redundant code. */
6362 merge_assigned_reloads (rtx insn)
6366 /* Scan all the reloads looking for ones that only load values and
6367 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6368 assigned and not modified by INSN. */
6370 for (i = 0; i < n_reloads; i++)
6372 int conflicting_input = 0;
6373 int max_input_address_opnum = -1;
6374 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6376 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6377 || rld[i].out != 0 || rld[i].reg_rtx == 0
6378 || reg_set_p (rld[i].reg_rtx, insn))
6381 /* Look at all other reloads. Ensure that the only use of this
6382 reload_reg_rtx is in a reload that just loads the same value
6383 as we do. Note that any secondary reloads must be of the identical
6384 class since the values, modes, and result registers are the
6385 same, so we need not do anything with any secondary reloads. */
6387 for (j = 0; j < n_reloads; j++)
6389 if (i == j || rld[j].reg_rtx == 0
6390 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6394 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6395 && rld[j].opnum > max_input_address_opnum)
6396 max_input_address_opnum = rld[j].opnum;
6398 /* If the reload regs aren't exactly the same (e.g, different modes)
6399 or if the values are different, we can't merge this reload.
6400 But if it is an input reload, we might still merge
6401 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6403 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6404 || rld[j].out != 0 || rld[j].in == 0
6405 || ! rtx_equal_p (rld[i].in, rld[j].in))
6407 if (rld[j].when_needed != RELOAD_FOR_INPUT
6408 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6409 || rld[i].opnum > rld[j].opnum)
6410 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6412 conflicting_input = 1;
6413 if (min_conflicting_input_opnum > rld[j].opnum)
6414 min_conflicting_input_opnum = rld[j].opnum;
6418 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6419 we, in fact, found any matching reloads. */
6422 && max_input_address_opnum <= min_conflicting_input_opnum)
6424 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6426 for (j = 0; j < n_reloads; j++)
6427 if (i != j && rld[j].reg_rtx != 0
6428 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6429 && (! conflicting_input
6430 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6431 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6433 rld[i].when_needed = RELOAD_OTHER;
6435 reload_spill_index[j] = -1;
6436 transfer_replacements (i, j);
6439 /* If this is now RELOAD_OTHER, look for any reloads that
6440 load parts of this operand and set them to
6441 RELOAD_FOR_OTHER_ADDRESS if they were for inputs,
6442 RELOAD_OTHER for outputs. Note that this test is
6443 equivalent to looking for reloads for this operand
6446 We must take special care with RELOAD_FOR_OUTPUT_ADDRESS;
6447 it may share registers with a RELOAD_FOR_INPUT, so we can
6448 not change it to RELOAD_FOR_OTHER_ADDRESS. We should
6449 never need to, since we do not modify RELOAD_FOR_OUTPUT.
6451 It is possible that the RELOAD_FOR_OPERAND_ADDRESS
6452 instruction is assigned the same register as the earlier
6453 RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two
6454 instructions will cause the RELOAD_FOR_OTHER_ADDRESS
6455 instruction to be deleted later on. */
6457 if (rld[i].when_needed == RELOAD_OTHER)
6458 for (j = 0; j < n_reloads; j++)
6460 && rld[j].when_needed != RELOAD_OTHER
6461 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6462 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6463 && rld[j].when_needed != RELOAD_FOR_OPERAND_ADDRESS
6464 && (! conflicting_input
6465 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6466 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6467 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6473 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6474 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6475 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6477 /* Check to see if we accidentally converted two
6478 reloads that use the same reload register with
6479 different inputs to the same type. If so, the
6480 resulting code won't work. */
6482 for (k = 0; k < j; k++)
6483 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6484 || rld[k].when_needed != rld[j].when_needed
6485 || !rtx_equal_p (rld[k].reg_rtx,
6487 || rtx_equal_p (rld[k].in,
6494 /* These arrays are filled by emit_reload_insns and its subroutines. */
6495 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6496 static rtx other_input_address_reload_insns = 0;
6497 static rtx other_input_reload_insns = 0;
6498 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6499 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6500 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6501 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6502 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6503 static rtx operand_reload_insns = 0;
6504 static rtx other_operand_reload_insns = 0;
6505 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6507 /* Values to be put in spill_reg_store are put here first. */
6508 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6509 static HARD_REG_SET reg_reloaded_died;
6511 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6512 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6513 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6514 adjusted register, and return true. Otherwise, return false. */
6516 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6517 enum reg_class new_class,
6518 enum machine_mode new_mode)
6523 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6525 unsigned regno = REGNO (reg);
6527 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6529 if (GET_MODE (reg) != new_mode)
6531 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6533 if (hard_regno_nregs[regno][new_mode]
6534 > hard_regno_nregs[regno][GET_MODE (reg)])
6536 reg = reload_adjust_reg_for_mode (reg, new_mode);
6544 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6545 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6546 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6547 adjusted register, and return true. Otherwise, return false. */
6549 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6550 enum insn_code icode)
6553 enum reg_class new_class = scratch_reload_class (icode);
6554 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6556 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6557 new_class, new_mode);
6560 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6561 has the number J. OLD contains the value to be used as input. */
6564 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6567 rtx insn = chain->insn;
6569 rtx oldequiv_reg = 0;
6572 enum machine_mode mode;
6575 /* delete_output_reload is only invoked properly if old contains
6576 the original pseudo register. Since this is replaced with a
6577 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6578 find the pseudo in RELOAD_IN_REG. */
6579 if (reload_override_in[j]
6580 && REG_P (rl->in_reg))
6587 else if (REG_P (oldequiv))
6588 oldequiv_reg = oldequiv;
6589 else if (GET_CODE (oldequiv) == SUBREG)
6590 oldequiv_reg = SUBREG_REG (oldequiv);
6592 reloadreg = reload_reg_rtx_for_input[j];
6593 mode = GET_MODE (reloadreg);
6595 /* If we are reloading from a register that was recently stored in
6596 with an output-reload, see if we can prove there was
6597 actually no need to store the old value in it. */
6599 if (optimize && REG_P (oldequiv)
6600 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6601 && spill_reg_store[REGNO (oldequiv)]
6603 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6604 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6606 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6608 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
6611 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6612 oldequiv = SUBREG_REG (oldequiv);
6613 if (GET_MODE (oldequiv) != VOIDmode
6614 && mode != GET_MODE (oldequiv))
6615 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6617 /* Switch to the right place to emit the reload insns. */
6618 switch (rl->when_needed)
6621 where = &other_input_reload_insns;
6623 case RELOAD_FOR_INPUT:
6624 where = &input_reload_insns[rl->opnum];
6626 case RELOAD_FOR_INPUT_ADDRESS:
6627 where = &input_address_reload_insns[rl->opnum];
6629 case RELOAD_FOR_INPADDR_ADDRESS:
6630 where = &inpaddr_address_reload_insns[rl->opnum];
6632 case RELOAD_FOR_OUTPUT_ADDRESS:
6633 where = &output_address_reload_insns[rl->opnum];
6635 case RELOAD_FOR_OUTADDR_ADDRESS:
6636 where = &outaddr_address_reload_insns[rl->opnum];
6638 case RELOAD_FOR_OPERAND_ADDRESS:
6639 where = &operand_reload_insns;
6641 case RELOAD_FOR_OPADDR_ADDR:
6642 where = &other_operand_reload_insns;
6644 case RELOAD_FOR_OTHER_ADDRESS:
6645 where = &other_input_address_reload_insns;
6651 push_to_sequence (*where);
6653 /* Auto-increment addresses must be reloaded in a special way. */
6654 if (rl->out && ! rl->out_reg)
6656 /* We are not going to bother supporting the case where a
6657 incremented register can't be copied directly from
6658 OLDEQUIV since this seems highly unlikely. */
6659 gcc_assert (rl->secondary_in_reload < 0);
6661 if (reload_inherited[j])
6662 oldequiv = reloadreg;
6664 old = XEXP (rl->in_reg, 0);
6666 if (optimize && REG_P (oldequiv)
6667 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6668 && spill_reg_store[REGNO (oldequiv)]
6670 && (dead_or_set_p (insn,
6671 spill_reg_stored_to[REGNO (oldequiv)])
6672 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6674 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6676 /* Prevent normal processing of this reload. */
6678 /* Output a special code sequence for this case. */
6679 new_spill_reg_store[REGNO (reloadreg)]
6680 = inc_for_reload (reloadreg, oldequiv, rl->out,
6684 /* If we are reloading a pseudo-register that was set by the previous
6685 insn, see if we can get rid of that pseudo-register entirely
6686 by redirecting the previous insn into our reload register. */
6688 else if (optimize && REG_P (old)
6689 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6690 && dead_or_set_p (insn, old)
6691 /* This is unsafe if some other reload
6692 uses the same reg first. */
6693 && ! conflicts_with_override (reloadreg)
6694 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6695 rl->when_needed, old, rl->out, j, 0))
6697 rtx temp = PREV_INSN (insn);
6698 while (temp && NOTE_P (temp))
6699 temp = PREV_INSN (temp);
6701 && NONJUMP_INSN_P (temp)
6702 && GET_CODE (PATTERN (temp)) == SET
6703 && SET_DEST (PATTERN (temp)) == old
6704 /* Make sure we can access insn_operand_constraint. */
6705 && asm_noperands (PATTERN (temp)) < 0
6706 /* This is unsafe if operand occurs more than once in current
6707 insn. Perhaps some occurrences aren't reloaded. */
6708 && count_occurrences (PATTERN (insn), old, 0) == 1)
6710 rtx old = SET_DEST (PATTERN (temp));
6711 /* Store into the reload register instead of the pseudo. */
6712 SET_DEST (PATTERN (temp)) = reloadreg;
6714 /* Verify that resulting insn is valid. */
6715 extract_insn (temp);
6716 if (constrain_operands (1))
6718 /* If the previous insn is an output reload, the source is
6719 a reload register, and its spill_reg_store entry will
6720 contain the previous destination. This is now
6722 if (REG_P (SET_SRC (PATTERN (temp)))
6723 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6725 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6726 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6729 /* If these are the only uses of the pseudo reg,
6730 pretend for GDB it lives in the reload reg we used. */
6731 if (REG_N_DEATHS (REGNO (old)) == 1
6732 && REG_N_SETS (REGNO (old)) == 1)
6734 reg_renumber[REGNO (old)] = REGNO (reloadreg);
6735 alter_reg (REGNO (old), -1);
6741 SET_DEST (PATTERN (temp)) = old;
6746 /* We can't do that, so output an insn to load RELOADREG. */
6748 /* If we have a secondary reload, pick up the secondary register
6749 and icode, if any. If OLDEQUIV and OLD are different or
6750 if this is an in-out reload, recompute whether or not we
6751 still need a secondary register and what the icode should
6752 be. If we still need a secondary register and the class or
6753 icode is different, go back to reloading from OLD if using
6754 OLDEQUIV means that we got the wrong type of register. We
6755 cannot have different class or icode due to an in-out reload
6756 because we don't make such reloads when both the input and
6757 output need secondary reload registers. */
6759 if (! special && rl->secondary_in_reload >= 0)
6761 rtx second_reload_reg = 0;
6762 rtx third_reload_reg = 0;
6763 int secondary_reload = rl->secondary_in_reload;
6764 rtx real_oldequiv = oldequiv;
6767 enum insn_code icode;
6768 enum insn_code tertiary_icode = CODE_FOR_nothing;
6770 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6771 and similarly for OLD.
6772 See comments in get_secondary_reload in reload.c. */
6773 /* If it is a pseudo that cannot be replaced with its
6774 equivalent MEM, we must fall back to reload_in, which
6775 will have all the necessary substitutions registered.
6776 Likewise for a pseudo that can't be replaced with its
6777 equivalent constant.
6779 Take extra care for subregs of such pseudos. Note that
6780 we cannot use reg_equiv_mem in this case because it is
6781 not in the right mode. */
6784 if (GET_CODE (tmp) == SUBREG)
6785 tmp = SUBREG_REG (tmp);
6787 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6788 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6789 || reg_equiv_constant[REGNO (tmp)] != 0))
6791 if (! reg_equiv_mem[REGNO (tmp)]
6792 || num_not_at_initial_offset
6793 || GET_CODE (oldequiv) == SUBREG)
6794 real_oldequiv = rl->in;
6796 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6800 if (GET_CODE (tmp) == SUBREG)
6801 tmp = SUBREG_REG (tmp);
6803 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6804 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6805 || reg_equiv_constant[REGNO (tmp)] != 0))
6807 if (! reg_equiv_mem[REGNO (tmp)]
6808 || num_not_at_initial_offset
6809 || GET_CODE (old) == SUBREG)
6812 real_old = reg_equiv_mem[REGNO (tmp)];
6815 second_reload_reg = rld[secondary_reload].reg_rtx;
6816 if (rld[secondary_reload].secondary_in_reload >= 0)
6818 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
6820 third_reload_reg = rld[tertiary_reload].reg_rtx;
6821 tertiary_icode = rld[secondary_reload].secondary_in_icode;
6822 /* We'd have to add more code for quartary reloads. */
6823 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
6825 icode = rl->secondary_in_icode;
6827 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6828 || (rl->in != 0 && rl->out != 0))
6830 secondary_reload_info sri, sri2;
6831 enum reg_class new_class, new_t_class;
6833 sri.icode = CODE_FOR_nothing;
6834 sri.prev_sri = NULL;
6835 new_class = targetm.secondary_reload (1, real_oldequiv, rl->class,
6838 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
6839 second_reload_reg = 0;
6840 else if (new_class == NO_REGS)
6842 if (reload_adjust_reg_for_icode (&second_reload_reg,
6843 third_reload_reg, sri.icode))
6844 icode = sri.icode, third_reload_reg = 0;
6846 oldequiv = old, real_oldequiv = real_old;
6848 else if (sri.icode != CODE_FOR_nothing)
6849 /* We currently lack a way to express this in reloads. */
6853 sri2.icode = CODE_FOR_nothing;
6854 sri2.prev_sri = &sri;
6855 new_t_class = targetm.secondary_reload (1, real_oldequiv,
6856 new_class, mode, &sri);
6857 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
6859 if (reload_adjust_reg_for_temp (&second_reload_reg,
6862 third_reload_reg = 0, tertiary_icode = sri2.icode;
6864 oldequiv = old, real_oldequiv = real_old;
6866 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
6868 rtx intermediate = second_reload_reg;
6870 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6872 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
6875 second_reload_reg = intermediate;
6876 tertiary_icode = sri2.icode;
6879 oldequiv = old, real_oldequiv = real_old;
6881 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
6883 rtx intermediate = second_reload_reg;
6885 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6887 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
6890 second_reload_reg = intermediate;
6891 tertiary_icode = sri2.icode;
6894 oldequiv = old, real_oldequiv = real_old;
6897 /* This could be handled more intelligently too. */
6898 oldequiv = old, real_oldequiv = real_old;
6902 /* If we still need a secondary reload register, check
6903 to see if it is being used as a scratch or intermediate
6904 register and generate code appropriately. If we need
6905 a scratch register, use REAL_OLDEQUIV since the form of
6906 the insn may depend on the actual address if it is
6909 if (second_reload_reg)
6911 if (icode != CODE_FOR_nothing)
6913 /* We'd have to add extra code to handle this case. */
6914 gcc_assert (!third_reload_reg);
6916 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6917 second_reload_reg));
6922 /* See if we need a scratch register to load the
6923 intermediate register (a tertiary reload). */
6924 if (tertiary_icode != CODE_FOR_nothing)
6926 emit_insn ((GEN_FCN (tertiary_icode)
6927 (second_reload_reg, real_oldequiv,
6928 third_reload_reg)));
6930 else if (third_reload_reg)
6932 gen_reload (third_reload_reg, real_oldequiv,
6935 gen_reload (second_reload_reg, third_reload_reg,
6940 gen_reload (second_reload_reg, real_oldequiv,
6944 oldequiv = second_reload_reg;
6949 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6951 rtx real_oldequiv = oldequiv;
6953 if ((REG_P (oldequiv)
6954 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6955 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6956 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6957 || (GET_CODE (oldequiv) == SUBREG
6958 && REG_P (SUBREG_REG (oldequiv))
6959 && (REGNO (SUBREG_REG (oldequiv))
6960 >= FIRST_PSEUDO_REGISTER)
6961 && ((reg_equiv_memory_loc
6962 [REGNO (SUBREG_REG (oldequiv))] != 0)
6963 || (reg_equiv_constant
6964 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6965 || (CONSTANT_P (oldequiv)
6966 && (PREFERRED_RELOAD_CLASS (oldequiv,
6967 REGNO_REG_CLASS (REGNO (reloadreg)))
6969 real_oldequiv = rl->in;
6970 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6974 if (flag_non_call_exceptions)
6975 copy_eh_notes (insn, get_insns ());
6977 /* End this sequence. */
6978 *where = get_insns ();
6981 /* Update reload_override_in so that delete_address_reloads_1
6982 can see the actual register usage. */
6984 reload_override_in[j] = oldequiv;
6987 /* Generate insns to for the output reload RL, which is for the insn described
6988 by CHAIN and has the number J. */
6990 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6994 rtx insn = chain->insn;
6997 enum machine_mode mode;
7001 if (rl->when_needed == RELOAD_OTHER)
7004 push_to_sequence (output_reload_insns[rl->opnum]);
7006 rl_reg_rtx = reload_reg_rtx_for_output[j];
7007 mode = GET_MODE (rl_reg_rtx);
7009 reloadreg = rl_reg_rtx;
7011 /* If we need two reload regs, set RELOADREG to the intermediate
7012 one, since it will be stored into OLD. We might need a secondary
7013 register only for an input reload, so check again here. */
7015 if (rl->secondary_out_reload >= 0)
7018 int secondary_reload = rl->secondary_out_reload;
7019 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7021 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7022 && reg_equiv_mem[REGNO (old)] != 0)
7023 real_old = reg_equiv_mem[REGNO (old)];
7025 if (secondary_reload_class (0, rl->class, mode, real_old) != NO_REGS)
7027 rtx second_reloadreg = reloadreg;
7028 reloadreg = rld[secondary_reload].reg_rtx;
7030 /* See if RELOADREG is to be used as a scratch register
7031 or as an intermediate register. */
7032 if (rl->secondary_out_icode != CODE_FOR_nothing)
7034 /* We'd have to add extra code to handle this case. */
7035 gcc_assert (tertiary_reload < 0);
7037 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7038 (real_old, second_reloadreg, reloadreg)));
7043 /* See if we need both a scratch and intermediate reload
7046 enum insn_code tertiary_icode
7047 = rld[secondary_reload].secondary_out_icode;
7049 /* We'd have to add more code for quartary reloads. */
7050 gcc_assert (tertiary_reload < 0
7051 || rld[tertiary_reload].secondary_out_reload < 0);
7053 if (GET_MODE (reloadreg) != mode)
7054 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7056 if (tertiary_icode != CODE_FOR_nothing)
7058 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7061 /* Copy primary reload reg to secondary reload reg.
7062 (Note that these have been swapped above, then
7063 secondary reload reg to OLD using our insn.) */
7065 /* If REAL_OLD is a paradoxical SUBREG, remove it
7066 and try to put the opposite SUBREG on
7068 if (GET_CODE (real_old) == SUBREG
7069 && (GET_MODE_SIZE (GET_MODE (real_old))
7070 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7071 && 0 != (tem = gen_lowpart_common
7072 (GET_MODE (SUBREG_REG (real_old)),
7074 real_old = SUBREG_REG (real_old), reloadreg = tem;
7076 gen_reload (reloadreg, second_reloadreg,
7077 rl->opnum, rl->when_needed);
7078 emit_insn ((GEN_FCN (tertiary_icode)
7079 (real_old, reloadreg, third_reloadreg)));
7085 /* Copy between the reload regs here and then to
7088 gen_reload (reloadreg, second_reloadreg,
7089 rl->opnum, rl->when_needed);
7090 if (tertiary_reload >= 0)
7092 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7094 gen_reload (third_reloadreg, reloadreg,
7095 rl->opnum, rl->when_needed);
7096 reloadreg = third_reloadreg;
7103 /* Output the last reload insn. */
7108 /* Don't output the last reload if OLD is not the dest of
7109 INSN and is in the src and is clobbered by INSN. */
7110 if (! flag_expensive_optimizations
7112 || !(set = single_set (insn))
7113 || rtx_equal_p (old, SET_DEST (set))
7114 || !reg_mentioned_p (old, SET_SRC (set))
7115 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7116 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7117 gen_reload (old, reloadreg, rl->opnum,
7121 /* Look at all insns we emitted, just to be safe. */
7122 for (p = get_insns (); p; p = NEXT_INSN (p))
7125 rtx pat = PATTERN (p);
7127 /* If this output reload doesn't come from a spill reg,
7128 clear any memory of reloaded copies of the pseudo reg.
7129 If this output reload comes from a spill reg,
7130 reg_has_output_reload will make this do nothing. */
7131 note_stores (pat, forget_old_reloads_1, NULL);
7133 if (reg_mentioned_p (rl_reg_rtx, pat))
7135 rtx set = single_set (insn);
7136 if (reload_spill_index[j] < 0
7138 && SET_SRC (set) == rl_reg_rtx)
7140 int src = REGNO (SET_SRC (set));
7142 reload_spill_index[j] = src;
7143 SET_HARD_REG_BIT (reg_is_output_reload, src);
7144 if (find_regno_note (insn, REG_DEAD, src))
7145 SET_HARD_REG_BIT (reg_reloaded_died, src);
7147 if (HARD_REGISTER_P (rl_reg_rtx))
7149 int s = rl->secondary_out_reload;
7150 set = single_set (p);
7151 /* If this reload copies only to the secondary reload
7152 register, the secondary reload does the actual
7154 if (s >= 0 && set == NULL_RTX)
7155 /* We can't tell what function the secondary reload
7156 has and where the actual store to the pseudo is
7157 made; leave new_spill_reg_store alone. */
7160 && SET_SRC (set) == rl_reg_rtx
7161 && SET_DEST (set) == rld[s].reg_rtx)
7163 /* Usually the next instruction will be the
7164 secondary reload insn; if we can confirm
7165 that it is, setting new_spill_reg_store to
7166 that insn will allow an extra optimization. */
7167 rtx s_reg = rld[s].reg_rtx;
7168 rtx next = NEXT_INSN (p);
7169 rld[s].out = rl->out;
7170 rld[s].out_reg = rl->out_reg;
7171 set = single_set (next);
7172 if (set && SET_SRC (set) == s_reg
7173 && ! new_spill_reg_store[REGNO (s_reg)])
7175 SET_HARD_REG_BIT (reg_is_output_reload,
7177 new_spill_reg_store[REGNO (s_reg)] = next;
7181 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7186 if (rl->when_needed == RELOAD_OTHER)
7188 emit_insn (other_output_reload_insns[rl->opnum]);
7189 other_output_reload_insns[rl->opnum] = get_insns ();
7192 output_reload_insns[rl->opnum] = get_insns ();
7194 if (flag_non_call_exceptions)
7195 copy_eh_notes (insn, get_insns ());
7200 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7201 and has the number J. */
7203 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7205 rtx insn = chain->insn;
7206 rtx old = (rl->in && MEM_P (rl->in)
7207 ? rl->in_reg : rl->in);
7208 rtx reg_rtx = rl->reg_rtx;
7212 enum machine_mode mode;
7214 /* Determine the mode to reload in.
7215 This is very tricky because we have three to choose from.
7216 There is the mode the insn operand wants (rl->inmode).
7217 There is the mode of the reload register RELOADREG.
7218 There is the intrinsic mode of the operand, which we could find
7219 by stripping some SUBREGs.
7220 It turns out that RELOADREG's mode is irrelevant:
7221 we can change that arbitrarily.
7223 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7224 then the reload reg may not support QImode moves, so use SImode.
7225 If foo is in memory due to spilling a pseudo reg, this is safe,
7226 because the QImode value is in the least significant part of a
7227 slot big enough for a SImode. If foo is some other sort of
7228 memory reference, then it is impossible to reload this case,
7229 so previous passes had better make sure this never happens.
7231 Then consider a one-word union which has SImode and one of its
7232 members is a float, being fetched as (SUBREG:SF union:SI).
7233 We must fetch that as SFmode because we could be loading into
7234 a float-only register. In this case OLD's mode is correct.
7236 Consider an immediate integer: it has VOIDmode. Here we need
7237 to get a mode from something else.
7239 In some cases, there is a fourth mode, the operand's
7240 containing mode. If the insn specifies a containing mode for
7241 this operand, it overrides all others.
7243 I am not sure whether the algorithm here is always right,
7244 but it does the right things in those cases. */
7246 mode = GET_MODE (old);
7247 if (mode == VOIDmode)
7250 /* We cannot use gen_lowpart_common since it can do the wrong thing
7251 when REG_RTX has a multi-word mode. Note that REG_RTX must
7252 always be a REG here. */
7253 if (GET_MODE (reg_rtx) != mode)
7254 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7256 reload_reg_rtx_for_input[j] = reg_rtx;
7259 /* AUTO_INC reloads need to be handled even if inherited. We got an
7260 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7261 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7262 && ! rtx_equal_p (reg_rtx, old)
7264 emit_input_reload_insns (chain, rld + j, old, j);
7266 /* When inheriting a wider reload, we have a MEM in rl->in,
7267 e.g. inheriting a SImode output reload for
7268 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7269 if (optimize && reload_inherited[j] && rl->in
7271 && MEM_P (rl->in_reg)
7272 && reload_spill_index[j] >= 0
7273 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7274 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7276 /* If we are reloading a register that was recently stored in with an
7277 output-reload, see if we can prove there was
7278 actually no need to store the old value in it. */
7281 && (reload_inherited[j] || reload_override_in[j])
7284 && spill_reg_store[REGNO (reg_rtx)] != 0
7286 /* There doesn't seem to be any reason to restrict this to pseudos
7287 and doing so loses in the case where we are copying from a
7288 register of the wrong class. */
7289 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7291 /* The insn might have already some references to stackslots
7292 replaced by MEMs, while reload_out_reg still names the
7294 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7295 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7296 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7299 /* Do output reloading for reload RL, which is for the insn described by
7300 CHAIN and has the number J.
7301 ??? At some point we need to support handling output reloads of
7302 JUMP_INSNs or insns that set cc0. */
7304 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7307 rtx insn = chain->insn;
7308 /* If this is an output reload that stores something that is
7309 not loaded in this same reload, see if we can eliminate a previous
7311 rtx pseudo = rl->out_reg;
7312 rtx reg_rtx = rl->reg_rtx;
7314 if (rl->out && reg_rtx)
7316 enum machine_mode mode;
7318 /* Determine the mode to reload in.
7319 See comments above (for input reloading). */
7320 mode = GET_MODE (rl->out);
7321 if (mode == VOIDmode)
7323 /* VOIDmode should never happen for an output. */
7324 if (asm_noperands (PATTERN (insn)) < 0)
7325 /* It's the compiler's fault. */
7326 fatal_insn ("VOIDmode on an output", insn);
7327 error_for_asm (insn, "output operand is constant in %<asm%>");
7328 /* Prevent crash--use something we know is valid. */
7330 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7332 if (GET_MODE (reg_rtx) != mode)
7333 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7335 reload_reg_rtx_for_output[j] = reg_rtx;
7340 && ! rtx_equal_p (rl->in_reg, pseudo)
7341 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7342 && reg_last_reload_reg[REGNO (pseudo)])
7344 int pseudo_no = REGNO (pseudo);
7345 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7347 /* We don't need to test full validity of last_regno for
7348 inherit here; we only want to know if the store actually
7349 matches the pseudo. */
7350 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7351 && reg_reloaded_contents[last_regno] == pseudo_no
7352 && spill_reg_store[last_regno]
7353 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7354 delete_output_reload (insn, j, last_regno, reg_rtx);
7360 || rtx_equal_p (old, reg_rtx))
7363 /* An output operand that dies right away does need a reload,
7364 but need not be copied from it. Show the new location in the
7366 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7367 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7369 XEXP (note, 0) = reg_rtx;
7372 /* Likewise for a SUBREG of an operand that dies. */
7373 else if (GET_CODE (old) == SUBREG
7374 && REG_P (SUBREG_REG (old))
7375 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7378 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7381 else if (GET_CODE (old) == SCRATCH)
7382 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7383 but we don't want to make an output reload. */
7386 /* If is a JUMP_INSN, we can't support output reloads yet. */
7387 gcc_assert (NONJUMP_INSN_P (insn));
7389 emit_output_reload_insns (chain, rld + j, j);
7392 /* A reload copies values of MODE from register SRC to register DEST.
7393 Return true if it can be treated for inheritance purposes like a
7394 group of reloads, each one reloading a single hard register. The
7395 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7396 occupy the same number of hard registers. */
7399 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
7400 int src ATTRIBUTE_UNUSED,
7401 enum machine_mode mode ATTRIBUTE_UNUSED)
7403 #ifdef CANNOT_CHANGE_MODE_CLASS
7404 return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
7405 && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
7411 /* Output insns to reload values in and out of the chosen reload regs. */
7414 emit_reload_insns (struct insn_chain *chain)
7416 rtx insn = chain->insn;
7420 CLEAR_HARD_REG_SET (reg_reloaded_died);
7422 for (j = 0; j < reload_n_operands; j++)
7423 input_reload_insns[j] = input_address_reload_insns[j]
7424 = inpaddr_address_reload_insns[j]
7425 = output_reload_insns[j] = output_address_reload_insns[j]
7426 = outaddr_address_reload_insns[j]
7427 = other_output_reload_insns[j] = 0;
7428 other_input_address_reload_insns = 0;
7429 other_input_reload_insns = 0;
7430 operand_reload_insns = 0;
7431 other_operand_reload_insns = 0;
7433 /* Dump reloads into the dump file. */
7436 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7437 debug_reload_to_stream (dump_file);
7440 /* Now output the instructions to copy the data into and out of the
7441 reload registers. Do these in the order that the reloads were reported,
7442 since reloads of base and index registers precede reloads of operands
7443 and the operands may need the base and index registers reloaded. */
7445 for (j = 0; j < n_reloads; j++)
7447 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
7451 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
7452 new_spill_reg_store[i] = 0;
7455 do_input_reload (chain, rld + j, j);
7456 do_output_reload (chain, rld + j, j);
7459 /* Now write all the insns we made for reloads in the order expected by
7460 the allocation functions. Prior to the insn being reloaded, we write
7461 the following reloads:
7463 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7465 RELOAD_OTHER reloads.
7467 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7468 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7469 RELOAD_FOR_INPUT reload for the operand.
7471 RELOAD_FOR_OPADDR_ADDRS reloads.
7473 RELOAD_FOR_OPERAND_ADDRESS reloads.
7475 After the insn being reloaded, we write the following:
7477 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7478 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7479 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7480 reloads for the operand. The RELOAD_OTHER output reloads are
7481 output in descending order by reload number. */
7483 emit_insn_before (other_input_address_reload_insns, insn);
7484 emit_insn_before (other_input_reload_insns, insn);
7486 for (j = 0; j < reload_n_operands; j++)
7488 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7489 emit_insn_before (input_address_reload_insns[j], insn);
7490 emit_insn_before (input_reload_insns[j], insn);
7493 emit_insn_before (other_operand_reload_insns, insn);
7494 emit_insn_before (operand_reload_insns, insn);
7496 for (j = 0; j < reload_n_operands; j++)
7498 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7499 x = emit_insn_after (output_address_reload_insns[j], x);
7500 x = emit_insn_after (output_reload_insns[j], x);
7501 emit_insn_after (other_output_reload_insns[j], x);
7504 /* For all the spill regs newly reloaded in this instruction,
7505 record what they were reloaded from, so subsequent instructions
7506 can inherit the reloads.
7508 Update spill_reg_store for the reloads of this insn.
7509 Copy the elements that were updated in the loop above. */
7511 for (j = 0; j < n_reloads; j++)
7513 int r = reload_order[j];
7514 int i = reload_spill_index[r];
7516 /* If this is a non-inherited input reload from a pseudo, we must
7517 clear any memory of a previous store to the same pseudo. Only do
7518 something if there will not be an output reload for the pseudo
7520 if (rld[r].in_reg != 0
7521 && ! (reload_inherited[r] || reload_override_in[r]))
7523 rtx reg = rld[r].in_reg;
7525 if (GET_CODE (reg) == SUBREG)
7526 reg = SUBREG_REG (reg);
7529 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7530 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7532 int nregno = REGNO (reg);
7534 if (reg_last_reload_reg[nregno])
7536 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7538 if (reg_reloaded_contents[last_regno] == nregno)
7539 spill_reg_store[last_regno] = 0;
7544 /* I is nonneg if this reload used a register.
7545 If rld[r].reg_rtx is 0, this is an optional reload
7546 that we opted to ignore. */
7548 if (i >= 0 && rld[r].reg_rtx != 0)
7550 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7553 /* For a multi register reload, we need to check if all or part
7554 of the value lives to the end. */
7555 for (k = 0; k < nr; k++)
7556 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7557 rld[r].when_needed))
7558 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7560 /* Maybe the spill reg contains a copy of reload_out. */
7562 && (REG_P (rld[r].out)
7566 || REG_P (rld[r].out_reg)))
7569 enum machine_mode mode;
7572 reg = reload_reg_rtx_for_output[r];
7573 mode = GET_MODE (reg);
7574 regno = REGNO (reg);
7575 nregs = hard_regno_nregs[regno][mode];
7576 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7577 rld[r].when_needed))
7579 rtx out = (REG_P (rld[r].out)
7583 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7584 int out_regno = REGNO (out);
7585 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
7586 : hard_regno_nregs[out_regno][mode]);
7589 spill_reg_store[regno] = new_spill_reg_store[regno];
7590 spill_reg_stored_to[regno] = out;
7591 reg_last_reload_reg[out_regno] = reg;
7593 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
7594 && nregs == out_nregs
7595 && inherit_piecemeal_p (out_regno, regno, mode));
7597 /* If OUT_REGNO is a hard register, it may occupy more than
7598 one register. If it does, say what is in the
7599 rest of the registers assuming that both registers
7600 agree on how many words the object takes. If not,
7601 invalidate the subsequent registers. */
7603 if (HARD_REGISTER_NUM_P (out_regno))
7604 for (k = 1; k < out_nregs; k++)
7605 reg_last_reload_reg[out_regno + k]
7606 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7608 /* Now do the inverse operation. */
7609 for (k = 0; k < nregs; k++)
7611 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
7612 reg_reloaded_contents[regno + k]
7613 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
7616 reg_reloaded_insn[regno + k] = insn;
7617 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
7618 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
7619 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7622 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7627 /* Maybe the spill reg contains a copy of reload_in. Only do
7628 something if there will not be an output reload for
7629 the register being reloaded. */
7630 else if (rld[r].out_reg == 0
7632 && ((REG_P (rld[r].in)
7633 && !HARD_REGISTER_P (rld[r].in)
7634 && !REGNO_REG_SET_P (®_has_output_reload,
7636 || (REG_P (rld[r].in_reg)
7637 && !REGNO_REG_SET_P (®_has_output_reload,
7638 REGNO (rld[r].in_reg))))
7639 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
7642 enum machine_mode mode;
7645 reg = reload_reg_rtx_for_input[r];
7646 mode = GET_MODE (reg);
7647 regno = REGNO (reg);
7648 nregs = hard_regno_nregs[regno][mode];
7649 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7650 rld[r].when_needed))
7657 if (REG_P (rld[r].in)
7658 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7660 else if (REG_P (rld[r].in_reg))
7663 in = XEXP (rld[r].in_reg, 0);
7664 in_regno = REGNO (in);
7666 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
7667 : hard_regno_nregs[in_regno][mode]);
7669 reg_last_reload_reg[in_regno] = reg;
7671 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
7672 && nregs == in_nregs
7673 && inherit_piecemeal_p (regno, in_regno, mode));
7675 if (HARD_REGISTER_NUM_P (in_regno))
7676 for (k = 1; k < in_nregs; k++)
7677 reg_last_reload_reg[in_regno + k]
7678 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7680 /* Unless we inherited this reload, show we haven't
7681 recently done a store.
7682 Previous stores of inherited auto_inc expressions
7683 also have to be discarded. */
7684 if (! reload_inherited[r]
7685 || (rld[r].out && ! rld[r].out_reg))
7686 spill_reg_store[regno] = 0;
7688 for (k = 0; k < nregs; k++)
7690 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
7691 reg_reloaded_contents[regno + k]
7692 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
7695 reg_reloaded_insn[regno + k] = insn;
7696 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
7697 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
7698 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7701 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7708 /* The following if-statement was #if 0'd in 1.34 (or before...).
7709 It's reenabled in 1.35 because supposedly nothing else
7710 deals with this problem. */
7712 /* If a register gets output-reloaded from a non-spill register,
7713 that invalidates any previous reloaded copy of it.
7714 But forget_old_reloads_1 won't get to see it, because
7715 it thinks only about the original insn. So invalidate it here.
7716 Also do the same thing for RELOAD_OTHER constraints where the
7717 output is discarded. */
7719 && ((rld[r].out != 0
7720 && (REG_P (rld[r].out)
7721 || (MEM_P (rld[r].out)
7722 && REG_P (rld[r].out_reg))))
7723 || (rld[r].out == 0 && rld[r].out_reg
7724 && REG_P (rld[r].out_reg))))
7726 rtx out = ((rld[r].out && REG_P (rld[r].out))
7727 ? rld[r].out : rld[r].out_reg);
7728 int out_regno = REGNO (out);
7729 enum machine_mode mode = GET_MODE (out);
7731 /* REG_RTX is now set or clobbered by the main instruction.
7732 As the comment above explains, forget_old_reloads_1 only
7733 sees the original instruction, and there is no guarantee
7734 that the original instruction also clobbered REG_RTX.
7735 For example, if find_reloads sees that the input side of
7736 a matched operand pair dies in this instruction, it may
7737 use the input register as the reload register.
7739 Calling forget_old_reloads_1 is a waste of effort if
7740 REG_RTX is also the output register.
7742 If we know that REG_RTX holds the value of a pseudo
7743 register, the code after the call will record that fact. */
7744 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
7745 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
7747 if (!HARD_REGISTER_NUM_P (out_regno))
7749 rtx src_reg, store_insn = NULL_RTX;
7751 reg_last_reload_reg[out_regno] = 0;
7753 /* If we can find a hard register that is stored, record
7754 the storing insn so that we may delete this insn with
7755 delete_output_reload. */
7756 src_reg = reload_reg_rtx_for_output[r];
7758 /* If this is an optional reload, try to find the source reg
7759 from an input reload. */
7762 rtx set = single_set (insn);
7763 if (set && SET_DEST (set) == rld[r].out)
7767 src_reg = SET_SRC (set);
7769 for (k = 0; k < n_reloads; k++)
7771 if (rld[k].in == src_reg)
7773 src_reg = reload_reg_rtx_for_input[k];
7780 store_insn = new_spill_reg_store[REGNO (src_reg)];
7781 if (src_reg && REG_P (src_reg)
7782 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7784 int src_regno, src_nregs, k;
7787 gcc_assert (GET_MODE (src_reg) == mode);
7788 src_regno = REGNO (src_reg);
7789 src_nregs = hard_regno_nregs[src_regno][mode];
7790 /* The place where to find a death note varies with
7791 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7792 necessarily checked exactly in the code that moves
7793 notes, so just check both locations. */
7794 note = find_regno_note (insn, REG_DEAD, src_regno);
7795 if (! note && store_insn)
7796 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7797 for (k = 0; k < src_nregs; k++)
7799 spill_reg_store[src_regno + k] = store_insn;
7800 spill_reg_stored_to[src_regno + k] = out;
7801 reg_reloaded_contents[src_regno + k] = out_regno;
7802 reg_reloaded_insn[src_regno + k] = store_insn;
7803 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
7804 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
7805 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
7807 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7810 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7812 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
7814 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7816 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7818 reg_last_reload_reg[out_regno] = src_reg;
7819 /* We have to set reg_has_output_reload here, or else
7820 forget_old_reloads_1 will clear reg_last_reload_reg
7822 SET_REGNO_REG_SET (®_has_output_reload,
7828 int k, out_nregs = hard_regno_nregs[out_regno][mode];
7830 for (k = 0; k < out_nregs; k++)
7831 reg_last_reload_reg[out_regno + k] = 0;
7835 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7838 /* Go through the motions to emit INSN and test if it is strictly valid.
7839 Return the emitted insn if valid, else return NULL. */
7842 emit_insn_if_valid_for_reload (rtx insn)
7844 rtx last = get_last_insn ();
7847 insn = emit_insn (insn);
7848 code = recog_memoized (insn);
7852 extract_insn (insn);
7853 /* We want constrain operands to treat this insn strictly in its
7854 validity determination, i.e., the way it would after reload has
7856 if (constrain_operands (1))
7860 delete_insns_since (last);
7864 /* Emit code to perform a reload from IN (which may be a reload register) to
7865 OUT (which may also be a reload register). IN or OUT is from operand
7866 OPNUM with reload type TYPE.
7868 Returns first insn emitted. */
7871 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7873 rtx last = get_last_insn ();
7876 /* If IN is a paradoxical SUBREG, remove it and try to put the
7877 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7878 if (GET_CODE (in) == SUBREG
7879 && (GET_MODE_SIZE (GET_MODE (in))
7880 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7881 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7882 in = SUBREG_REG (in), out = tem;
7883 else if (GET_CODE (out) == SUBREG
7884 && (GET_MODE_SIZE (GET_MODE (out))
7885 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7886 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7887 out = SUBREG_REG (out), in = tem;
7889 /* How to do this reload can get quite tricky. Normally, we are being
7890 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7891 register that didn't get a hard register. In that case we can just
7892 call emit_move_insn.
7894 We can also be asked to reload a PLUS that adds a register or a MEM to
7895 another register, constant or MEM. This can occur during frame pointer
7896 elimination and while reloading addresses. This case is handled by
7897 trying to emit a single insn to perform the add. If it is not valid,
7898 we use a two insn sequence.
7900 Or we can be asked to reload an unary operand that was a fragment of
7901 an addressing mode, into a register. If it isn't recognized as-is,
7902 we try making the unop operand and the reload-register the same:
7903 (set reg:X (unop:X expr:Y))
7904 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
7906 Finally, we could be called to handle an 'o' constraint by putting
7907 an address into a register. In that case, we first try to do this
7908 with a named pattern of "reload_load_address". If no such pattern
7909 exists, we just emit a SET insn and hope for the best (it will normally
7910 be valid on machines that use 'o').
7912 This entire process is made complex because reload will never
7913 process the insns we generate here and so we must ensure that
7914 they will fit their constraints and also by the fact that parts of
7915 IN might be being reloaded separately and replaced with spill registers.
7916 Because of this, we are, in some sense, just guessing the right approach
7917 here. The one listed above seems to work.
7919 ??? At some point, this whole thing needs to be rethought. */
7921 if (GET_CODE (in) == PLUS
7922 && (REG_P (XEXP (in, 0))
7923 || GET_CODE (XEXP (in, 0)) == SUBREG
7924 || MEM_P (XEXP (in, 0)))
7925 && (REG_P (XEXP (in, 1))
7926 || GET_CODE (XEXP (in, 1)) == SUBREG
7927 || CONSTANT_P (XEXP (in, 1))
7928 || MEM_P (XEXP (in, 1))))
7930 /* We need to compute the sum of a register or a MEM and another
7931 register, constant, or MEM, and put it into the reload
7932 register. The best possible way of doing this is if the machine
7933 has a three-operand ADD insn that accepts the required operands.
7935 The simplest approach is to try to generate such an insn and see if it
7936 is recognized and matches its constraints. If so, it can be used.
7938 It might be better not to actually emit the insn unless it is valid,
7939 but we need to pass the insn as an operand to `recog' and
7940 `extract_insn' and it is simpler to emit and then delete the insn if
7941 not valid than to dummy things up. */
7943 rtx op0, op1, tem, insn;
7946 op0 = find_replacement (&XEXP (in, 0));
7947 op1 = find_replacement (&XEXP (in, 1));
7949 /* Since constraint checking is strict, commutativity won't be
7950 checked, so we need to do that here to avoid spurious failure
7951 if the add instruction is two-address and the second operand
7952 of the add is the same as the reload reg, which is frequently
7953 the case. If the insn would be A = B + A, rearrange it so
7954 it will be A = A + B as constrain_operands expects. */
7956 if (REG_P (XEXP (in, 1))
7957 && REGNO (out) == REGNO (XEXP (in, 1)))
7958 tem = op0, op0 = op1, op1 = tem;
7960 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7961 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7963 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7967 /* If that failed, we must use a conservative two-insn sequence.
7969 Use a move to copy one operand into the reload register. Prefer
7970 to reload a constant, MEM or pseudo since the move patterns can
7971 handle an arbitrary operand. If OP1 is not a constant, MEM or
7972 pseudo and OP1 is not a valid operand for an add instruction, then
7975 After reloading one of the operands into the reload register, add
7976 the reload register to the output register.
7978 If there is another way to do this for a specific machine, a
7979 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7982 code = (int) optab_handler (add_optab, GET_MODE (out))->insn_code;
7984 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7986 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7987 || (code != CODE_FOR_nothing
7988 && ! ((*insn_data[code].operand[2].predicate)
7989 (op1, insn_data[code].operand[2].mode))))
7990 tem = op0, op0 = op1, op1 = tem;
7992 gen_reload (out, op0, opnum, type);
7994 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7995 This fixes a problem on the 32K where the stack pointer cannot
7996 be used as an operand of an add insn. */
7998 if (rtx_equal_p (op0, op1))
8001 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8004 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8005 set_unique_reg_note (insn, REG_EQUIV, in);
8009 /* If that failed, copy the address register to the reload register.
8010 Then add the constant to the reload register. */
8012 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8013 gen_reload (out, op1, opnum, type);
8014 insn = emit_insn (gen_add2_insn (out, op0));
8015 set_unique_reg_note (insn, REG_EQUIV, in);
8018 #ifdef SECONDARY_MEMORY_NEEDED
8019 /* If we need a memory location to do the move, do it that way. */
8020 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
8021 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
8022 && (REG_P (out) || GET_CODE (out) == SUBREG)
8023 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
8024 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
8025 REGNO_REG_CLASS (reg_or_subregno (out)),
8028 /* Get the memory to use and rewrite both registers to its mode. */
8029 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8031 if (GET_MODE (loc) != GET_MODE (out))
8032 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
8034 if (GET_MODE (loc) != GET_MODE (in))
8035 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
8037 gen_reload (loc, in, opnum, type);
8038 gen_reload (out, loc, opnum, type);
8041 else if (REG_P (out) && UNARY_P (in))
8048 op1 = find_replacement (&XEXP (in, 0));
8049 if (op1 != XEXP (in, 0))
8050 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8052 /* First, try a plain SET. */
8053 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8057 /* If that failed, move the inner operand to the reload
8058 register, and try the same unop with the inner expression
8059 replaced with the reload register. */
8061 if (GET_MODE (op1) != GET_MODE (out))
8062 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8066 gen_reload (out_moded, op1, opnum, type);
8069 = gen_rtx_SET (VOIDmode, out,
8070 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8072 insn = emit_insn_if_valid_for_reload (insn);
8075 set_unique_reg_note (insn, REG_EQUIV, in);
8079 fatal_insn ("Failure trying to reload:", set);
8081 /* If IN is a simple operand, use gen_move_insn. */
8082 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8084 tem = emit_insn (gen_move_insn (out, in));
8085 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8086 mark_jump_label (in, tem, 0);
8089 #ifdef HAVE_reload_load_address
8090 else if (HAVE_reload_load_address)
8091 emit_insn (gen_reload_load_address (out, in));
8094 /* Otherwise, just write (set OUT IN) and hope for the best. */
8096 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8098 /* Return the first insn emitted.
8099 We can not just return get_last_insn, because there may have
8100 been multiple instructions emitted. Also note that gen_move_insn may
8101 emit more than one insn itself, so we can not assume that there is one
8102 insn emitted per emit_insn_before call. */
8104 return last ? NEXT_INSN (last) : get_insns ();
8107 /* Delete a previously made output-reload whose result we now believe
8108 is not needed. First we double-check.
8110 INSN is the insn now being processed.
8111 LAST_RELOAD_REG is the hard register number for which we want to delete
8112 the last output reload.
8113 J is the reload-number that originally used REG. The caller has made
8114 certain that reload J doesn't use REG any longer for input.
8115 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8118 delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg)
8120 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8121 rtx reg = spill_reg_stored_to[last_reload_reg];
8124 int n_inherited = 0;
8128 /* It is possible that this reload has been only used to set another reload
8129 we eliminated earlier and thus deleted this instruction too. */
8130 if (INSN_DELETED_P (output_reload_insn))
8133 /* Get the raw pseudo-register referred to. */
8135 while (GET_CODE (reg) == SUBREG)
8136 reg = SUBREG_REG (reg);
8137 substed = reg_equiv_memory_loc[REGNO (reg)];
8139 /* This is unsafe if the operand occurs more often in the current
8140 insn than it is inherited. */
8141 for (k = n_reloads - 1; k >= 0; k--)
8143 rtx reg2 = rld[k].in;
8146 if (MEM_P (reg2) || reload_override_in[k])
8147 reg2 = rld[k].in_reg;
8149 if (rld[k].out && ! rld[k].out_reg)
8150 reg2 = XEXP (rld[k].in_reg, 0);
8152 while (GET_CODE (reg2) == SUBREG)
8153 reg2 = SUBREG_REG (reg2);
8154 if (rtx_equal_p (reg2, reg))
8156 if (reload_inherited[k] || reload_override_in[k] || k == j)
8162 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8163 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8164 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8167 n_occurrences += count_occurrences (PATTERN (insn),
8168 eliminate_regs (substed, 0,
8170 for (i1 = reg_equiv_alt_mem_list [REGNO (reg)]; i1; i1 = XEXP (i1, 1))
8172 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8173 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8175 if (n_occurrences > n_inherited)
8178 /* If the pseudo-reg we are reloading is no longer referenced
8179 anywhere between the store into it and here,
8180 and we're within the same basic block, then the value can only
8181 pass through the reload reg and end up here.
8182 Otherwise, give up--return. */
8183 for (i1 = NEXT_INSN (output_reload_insn);
8184 i1 != insn; i1 = NEXT_INSN (i1))
8186 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8188 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8189 && reg_mentioned_p (reg, PATTERN (i1)))
8191 /* If this is USE in front of INSN, we only have to check that
8192 there are no more references than accounted for by inheritance. */
8193 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8195 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8196 i1 = NEXT_INSN (i1);
8198 if (n_occurrences <= n_inherited && i1 == insn)
8204 /* We will be deleting the insn. Remove the spill reg information. */
8205 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8207 spill_reg_store[last_reload_reg + k] = 0;
8208 spill_reg_stored_to[last_reload_reg + k] = 0;
8211 /* The caller has already checked that REG dies or is set in INSN.
8212 It has also checked that we are optimizing, and thus some
8213 inaccuracies in the debugging information are acceptable.
8214 So we could just delete output_reload_insn. But in some cases
8215 we can improve the debugging information without sacrificing
8216 optimization - maybe even improving the code: See if the pseudo
8217 reg has been completely replaced with reload regs. If so, delete
8218 the store insn and forget we had a stack slot for the pseudo. */
8219 if (rld[j].out != rld[j].in
8220 && REG_N_DEATHS (REGNO (reg)) == 1
8221 && REG_N_SETS (REGNO (reg)) == 1
8222 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8223 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8227 /* We know that it was used only between here and the beginning of
8228 the current basic block. (We also know that the last use before
8229 INSN was the output reload we are thinking of deleting, but never
8230 mind that.) Search that range; see if any ref remains. */
8231 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8233 rtx set = single_set (i2);
8235 /* Uses which just store in the pseudo don't count,
8236 since if they are the only uses, they are dead. */
8237 if (set != 0 && SET_DEST (set) == reg)
8242 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8243 && reg_mentioned_p (reg, PATTERN (i2)))
8245 /* Some other ref remains; just delete the output reload we
8247 delete_address_reloads (output_reload_insn, insn);
8248 delete_insn (output_reload_insn);
8253 /* Delete the now-dead stores into this pseudo. Note that this
8254 loop also takes care of deleting output_reload_insn. */
8255 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8257 rtx set = single_set (i2);
8259 if (set != 0 && SET_DEST (set) == reg)
8261 delete_address_reloads (i2, insn);
8269 /* For the debugging info, say the pseudo lives in this reload reg. */
8270 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8271 alter_reg (REGNO (reg), -1);
8275 delete_address_reloads (output_reload_insn, insn);
8276 delete_insn (output_reload_insn);
8280 /* We are going to delete DEAD_INSN. Recursively delete loads of
8281 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8282 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8284 delete_address_reloads (rtx dead_insn, rtx current_insn)
8286 rtx set = single_set (dead_insn);
8287 rtx set2, dst, prev, next;
8290 rtx dst = SET_DEST (set);
8292 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8294 /* If we deleted the store from a reloaded post_{in,de}c expression,
8295 we can delete the matching adds. */
8296 prev = PREV_INSN (dead_insn);
8297 next = NEXT_INSN (dead_insn);
8298 if (! prev || ! next)
8300 set = single_set (next);
8301 set2 = single_set (prev);
8303 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8304 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8305 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8307 dst = SET_DEST (set);
8308 if (! rtx_equal_p (dst, SET_DEST (set2))
8309 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8310 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8311 || (INTVAL (XEXP (SET_SRC (set), 1))
8312 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8314 delete_related_insns (prev);
8315 delete_related_insns (next);
8318 /* Subfunction of delete_address_reloads: process registers found in X. */
8320 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8322 rtx prev, set, dst, i2;
8324 enum rtx_code code = GET_CODE (x);
8328 const char *fmt = GET_RTX_FORMAT (code);
8329 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8332 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8333 else if (fmt[i] == 'E')
8335 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8336 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8343 if (spill_reg_order[REGNO (x)] < 0)
8346 /* Scan backwards for the insn that sets x. This might be a way back due
8348 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8350 code = GET_CODE (prev);
8351 if (code == CODE_LABEL || code == JUMP_INSN)
8355 if (reg_set_p (x, PATTERN (prev)))
8357 if (reg_referenced_p (x, PATTERN (prev)))
8360 if (! prev || INSN_UID (prev) < reload_first_uid)
8362 /* Check that PREV only sets the reload register. */
8363 set = single_set (prev);
8366 dst = SET_DEST (set);
8368 || ! rtx_equal_p (dst, x))
8370 if (! reg_set_p (dst, PATTERN (dead_insn)))
8372 /* Check if DST was used in a later insn -
8373 it might have been inherited. */
8374 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8380 if (reg_referenced_p (dst, PATTERN (i2)))
8382 /* If there is a reference to the register in the current insn,
8383 it might be loaded in a non-inherited reload. If no other
8384 reload uses it, that means the register is set before
8386 if (i2 == current_insn)
8388 for (j = n_reloads - 1; j >= 0; j--)
8389 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8390 || reload_override_in[j] == dst)
8392 for (j = n_reloads - 1; j >= 0; j--)
8393 if (rld[j].in && rld[j].reg_rtx == dst)
8402 /* If DST is still live at CURRENT_INSN, check if it is used for
8403 any reload. Note that even if CURRENT_INSN sets DST, we still
8404 have to check the reloads. */
8405 if (i2 == current_insn)
8407 for (j = n_reloads - 1; j >= 0; j--)
8408 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8409 || reload_override_in[j] == dst)
8411 /* ??? We can't finish the loop here, because dst might be
8412 allocated to a pseudo in this block if no reload in this
8413 block needs any of the classes containing DST - see
8414 spill_hard_reg. There is no easy way to tell this, so we
8415 have to scan till the end of the basic block. */
8417 if (reg_set_p (dst, PATTERN (i2)))
8421 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8422 reg_reloaded_contents[REGNO (dst)] = -1;
8426 /* Output reload-insns to reload VALUE into RELOADREG.
8427 VALUE is an autoincrement or autodecrement RTX whose operand
8428 is a register or memory location;
8429 so reloading involves incrementing that location.
8430 IN is either identical to VALUE, or some cheaper place to reload from.
8432 INC_AMOUNT is the number to increment or decrement by (always positive).
8433 This cannot be deduced from VALUE.
8435 Return the instruction that stores into RELOADREG. */
8438 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8440 /* REG or MEM to be copied and incremented. */
8441 rtx incloc = find_replacement (&XEXP (value, 0));
8442 /* Nonzero if increment after copying. */
8443 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8444 || GET_CODE (value) == POST_MODIFY);
8450 rtx real_in = in == value ? incloc : in;
8452 /* No hard register is equivalent to this register after
8453 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8454 we could inc/dec that register as well (maybe even using it for
8455 the source), but I'm not sure it's worth worrying about. */
8457 reg_last_reload_reg[REGNO (incloc)] = 0;
8459 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8461 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8462 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8466 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8467 inc_amount = -inc_amount;
8469 inc = GEN_INT (inc_amount);
8472 /* If this is post-increment, first copy the location to the reload reg. */
8473 if (post && real_in != reloadreg)
8474 emit_insn (gen_move_insn (reloadreg, real_in));
8478 /* See if we can directly increment INCLOC. Use a method similar to
8479 that in gen_reload. */
8481 last = get_last_insn ();
8482 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8483 gen_rtx_PLUS (GET_MODE (incloc),
8486 code = recog_memoized (add_insn);
8489 extract_insn (add_insn);
8490 if (constrain_operands (1))
8492 /* If this is a pre-increment and we have incremented the value
8493 where it lives, copy the incremented value to RELOADREG to
8494 be used as an address. */
8497 emit_insn (gen_move_insn (reloadreg, incloc));
8502 delete_insns_since (last);
8505 /* If couldn't do the increment directly, must increment in RELOADREG.
8506 The way we do this depends on whether this is pre- or post-increment.
8507 For pre-increment, copy INCLOC to the reload register, increment it
8508 there, then save back. */
8512 if (in != reloadreg)
8513 emit_insn (gen_move_insn (reloadreg, real_in));
8514 emit_insn (gen_add2_insn (reloadreg, inc));
8515 store = emit_insn (gen_move_insn (incloc, reloadreg));
8520 Because this might be a jump insn or a compare, and because RELOADREG
8521 may not be available after the insn in an input reload, we must do
8522 the incrementation before the insn being reloaded for.
8524 We have already copied IN to RELOADREG. Increment the copy in
8525 RELOADREG, save that back, then decrement RELOADREG so it has
8526 the original value. */
8528 emit_insn (gen_add2_insn (reloadreg, inc));
8529 store = emit_insn (gen_move_insn (incloc, reloadreg));
8530 if (GET_CODE (inc) == CONST_INT)
8531 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
8533 emit_insn (gen_sub2_insn (reloadreg, inc));
8541 add_auto_inc_notes (rtx insn, rtx x)
8543 enum rtx_code code = GET_CODE (x);
8547 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8550 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8554 /* Scan all the operand sub-expressions. */
8555 fmt = GET_RTX_FORMAT (code);
8556 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8559 add_auto_inc_notes (insn, XEXP (x, i));
8560 else if (fmt[i] == 'E')
8561 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8562 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8567 /* Copy EH notes from an insn to its reloads. */
8569 copy_eh_notes (rtx insn, rtx x)
8571 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8574 for (; x != 0; x = NEXT_INSN (x))
8576 if (may_trap_p (PATTERN (x)))
8578 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8584 /* This is used by reload pass, that does emit some instructions after
8585 abnormal calls moving basic block end, but in fact it wants to emit
8586 them on the edge. Looks for abnormal call edges, find backward the
8587 proper call and fix the damage.
8589 Similar handle instructions throwing exceptions internally. */
8591 fixup_abnormal_edges (void)
8593 bool inserted = false;
8601 /* Look for cases we are interested in - calls or instructions causing
8603 FOR_EACH_EDGE (e, ei, bb->succs)
8605 if (e->flags & EDGE_ABNORMAL_CALL)
8607 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8608 == (EDGE_ABNORMAL | EDGE_EH))
8611 if (e && !CALL_P (BB_END (bb))
8612 && !can_throw_internal (BB_END (bb)))
8616 /* Get past the new insns generated. Allow notes, as the insns
8617 may be already deleted. */
8619 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8620 && !can_throw_internal (insn)
8621 && insn != BB_HEAD (bb))
8622 insn = PREV_INSN (insn);
8624 if (CALL_P (insn) || can_throw_internal (insn))
8628 stop = NEXT_INSN (BB_END (bb));
8630 insn = NEXT_INSN (insn);
8632 FOR_EACH_EDGE (e, ei, bb->succs)
8633 if (e->flags & EDGE_FALLTHRU)
8636 while (insn && insn != stop)
8638 next = NEXT_INSN (insn);
8643 /* Sometimes there's still the return value USE.
8644 If it's placed after a trapping call (i.e. that
8645 call is the last insn anyway), we have no fallthru
8646 edge. Simply delete this use and don't try to insert
8647 on the non-existent edge. */
8648 if (GET_CODE (PATTERN (insn)) != USE)
8650 /* We're not deleting it, we're moving it. */
8651 INSN_DELETED_P (insn) = 0;
8652 PREV_INSN (insn) = NULL_RTX;
8653 NEXT_INSN (insn) = NULL_RTX;
8655 insert_insn_on_edge (insn, e);
8659 else if (!BARRIER_P (insn))
8660 set_block_for_insn (insn, NULL);
8665 /* It may be that we don't find any such trapping insn. In this
8666 case we discovered quite late that the insn that had been
8667 marked as can_throw_internal in fact couldn't trap at all.
8668 So we should in fact delete the EH edges out of the block. */
8670 purge_dead_edges (bb);
8674 /* We've possibly turned single trapping insn into multiple ones. */
8675 if (flag_non_call_exceptions)
8678 blocks = sbitmap_alloc (last_basic_block);
8679 sbitmap_ones (blocks);
8680 find_many_sub_basic_blocks (blocks);
8681 sbitmap_free (blocks);
8685 commit_edge_insertions ();
8687 #ifdef ENABLE_CHECKING
8688 /* Verify that we didn't turn one trapping insn into many, and that
8689 we found and corrected all of the problems wrt fixups on the
8691 verify_flow_info ();
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