1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
106 collector can keep track of what is inside. */
107 varray_type reg_equiv_memory_loc_varray;
109 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
110 This is used when the address is not valid as a memory address
111 (because its displacement is too big for the machine.) */
112 rtx *reg_equiv_address;
114 /* Element N is the memory slot to which pseudo reg N is equivalent,
115 or zero if pseudo reg N is not equivalent to a memory slot. */
118 /* Widest width in which each pseudo reg is referred to (via subreg). */
119 static unsigned int *reg_max_ref_width;
121 /* Element N is the list of insns that initialized reg N from its equivalent
122 constant or memory slot. */
123 static rtx *reg_equiv_init;
125 /* Vector to remember old contents of reg_renumber before spilling. */
126 static short *reg_old_renumber;
128 /* During reload_as_needed, element N contains the last pseudo regno reloaded
129 into hard register N. If that pseudo reg occupied more than one register,
130 reg_reloaded_contents points to that pseudo for each spill register in
131 use; all of these must remain set for an inheritance to occur. */
132 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
134 /* During reload_as_needed, element N contains the insn for which
135 hard register N was last used. Its contents are significant only
136 when reg_reloaded_valid is set for this register. */
137 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
139 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
140 static HARD_REG_SET reg_reloaded_valid;
141 /* Indicate if the register was dead at the end of the reload.
142 This is only valid if reg_reloaded_contents is set and valid. */
143 static HARD_REG_SET reg_reloaded_dead;
145 /* Indicate whether the register's current value is one that is not
146 safe to retain across a call, even for registers that are normally
148 static HARD_REG_SET reg_reloaded_call_part_clobbered;
150 /* Number of spill-regs so far; number of valid elements of spill_regs. */
153 /* In parallel with spill_regs, contains REG rtx's for those regs.
154 Holds the last rtx used for any given reg, or 0 if it has never
155 been used for spilling yet. This rtx is reused, provided it has
157 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
159 /* In parallel with spill_regs, contains nonzero for a spill reg
160 that was stored after the last time it was used.
161 The precise value is the insn generated to do the store. */
162 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
164 /* This is the register that was stored with spill_reg_store. This is a
165 copy of reload_out / reload_out_reg when the value was stored; if
166 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
167 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
169 /* This table is the inverse mapping of spill_regs:
170 indexed by hard reg number,
171 it contains the position of that reg in spill_regs,
172 or -1 for something that is not in spill_regs.
174 ?!? This is no longer accurate. */
175 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
177 /* This reg set indicates registers that can't be used as spill registers for
178 the currently processed insn. These are the hard registers which are live
179 during the insn, but not allocated to pseudos, as well as fixed
181 static HARD_REG_SET bad_spill_regs;
183 /* These are the hard registers that can't be used as spill register for any
184 insn. This includes registers used for user variables and registers that
185 we can't eliminate. A register that appears in this set also can't be used
186 to retry register allocation. */
187 static HARD_REG_SET bad_spill_regs_global;
189 /* Describes order of use of registers for reloading
190 of spilled pseudo-registers. `n_spills' is the number of
191 elements that are actually valid; new ones are added at the end.
193 Both spill_regs and spill_reg_order are used on two occasions:
194 once during find_reload_regs, where they keep track of the spill registers
195 for a single insn, but also during reload_as_needed where they show all
196 the registers ever used by reload. For the latter case, the information
197 is calculated during finish_spills. */
198 static short spill_regs[FIRST_PSEUDO_REGISTER];
200 /* This vector of reg sets indicates, for each pseudo, which hard registers
201 may not be used for retrying global allocation because the register was
202 formerly spilled from one of them. If we allowed reallocating a pseudo to
203 a register that it was already allocated to, reload might not
205 static HARD_REG_SET *pseudo_previous_regs;
207 /* This vector of reg sets indicates, for each pseudo, which hard
208 registers may not be used for retrying global allocation because they
209 are used as spill registers during one of the insns in which the
211 static HARD_REG_SET *pseudo_forbidden_regs;
213 /* All hard regs that have been used as spill registers for any insn are
214 marked in this set. */
215 static HARD_REG_SET used_spill_regs;
217 /* Index of last register assigned as a spill register. We allocate in
218 a round-robin fashion. */
219 static int last_spill_reg;
221 /* Nonzero if indirect addressing is supported on the machine; this means
222 that spilling (REG n) does not require reloading it into a register in
223 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
224 value indicates the level of indirect addressing supported, e.g., two
225 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
227 static char spill_indirect_levels;
229 /* Nonzero if indirect addressing is supported when the innermost MEM is
230 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
231 which these are valid is the same as spill_indirect_levels, above. */
232 char indirect_symref_ok;
234 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
235 char double_reg_address_ok;
237 /* Record the stack slot for each spilled hard register. */
238 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
240 /* Width allocated so far for that stack slot. */
241 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
243 /* Record which pseudos needed to be spilled. */
244 static regset_head spilled_pseudos;
246 /* Used for communication between order_regs_for_reload and count_pseudo.
247 Used to avoid counting one pseudo twice. */
248 static regset_head pseudos_counted;
250 /* First uid used by insns created by reload in this function.
251 Used in find_equiv_reg. */
252 int reload_first_uid;
254 /* Flag set by local-alloc or global-alloc if anything is live in
255 a call-clobbered reg across calls. */
256 int caller_save_needed;
258 /* Set to 1 while reload_as_needed is operating.
259 Required by some machines to handle any generated moves differently. */
260 int reload_in_progress = 0;
262 /* These arrays record the insn_code of insns that may be needed to
263 perform input and output reloads of special objects. They provide a
264 place to pass a scratch register. */
265 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
266 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
268 /* This obstack is used for allocation of rtl during register elimination.
269 The allocated storage can be freed once find_reloads has processed the
271 struct obstack reload_obstack;
273 /* Points to the beginning of the reload_obstack. All insn_chain structures
274 are allocated first. */
275 char *reload_startobj;
277 /* The point after all insn_chain structures. Used to quickly deallocate
278 memory allocated in copy_reloads during calculate_needs_all_insns. */
279 char *reload_firstobj;
281 /* This points before all local rtl generated by register elimination.
282 Used to quickly free all memory after processing one insn. */
283 static char *reload_insn_firstobj;
285 /* List of insn_chain instructions, one for every insn that reload needs to
287 struct insn_chain *reload_insn_chain;
289 /* List of all insns needing reloads. */
290 static struct insn_chain *insns_need_reload;
292 /* This structure is used to record information about register eliminations.
293 Each array entry describes one possible way of eliminating a register
294 in favor of another. If there is more than one way of eliminating a
295 particular register, the most preferred should be specified first. */
299 int from; /* Register number to be eliminated. */
300 int to; /* Register number used as replacement. */
301 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
302 int can_eliminate; /* Nonzero if this elimination can be done. */
303 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
304 insns made by reload. */
305 HOST_WIDE_INT offset; /* Current offset between the two regs. */
306 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
307 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
308 rtx from_rtx; /* REG rtx for the register to be eliminated.
309 We cannot simply compare the number since
310 we might then spuriously replace a hard
311 register corresponding to a pseudo
312 assigned to the reg to be eliminated. */
313 rtx to_rtx; /* REG rtx for the replacement. */
316 static struct elim_table *reg_eliminate = 0;
318 /* This is an intermediate structure to initialize the table. It has
319 exactly the members provided by ELIMINABLE_REGS. */
320 static const struct elim_table_1
324 } reg_eliminate_1[] =
326 /* If a set of eliminable registers was specified, define the table from it.
327 Otherwise, default to the normal case of the frame pointer being
328 replaced by the stack pointer. */
330 #ifdef ELIMINABLE_REGS
333 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
336 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
338 /* Record the number of pending eliminations that have an offset not equal
339 to their initial offset. If nonzero, we use a new copy of each
340 replacement result in any insns encountered. */
341 int num_not_at_initial_offset;
343 /* Count the number of registers that we may be able to eliminate. */
344 static int num_eliminable;
345 /* And the number of registers that are equivalent to a constant that
346 can be eliminated to frame_pointer / arg_pointer + constant. */
347 static int num_eliminable_invariants;
349 /* For each label, we record the offset of each elimination. If we reach
350 a label by more than one path and an offset differs, we cannot do the
351 elimination. This information is indexed by the difference of the
352 number of the label and the first label number. We can't offset the
353 pointer itself as this can cause problems on machines with segmented
354 memory. The first table is an array of flags that records whether we
355 have yet encountered a label and the second table is an array of arrays,
356 one entry in the latter array for each elimination. */
358 static int first_label_num;
359 static char *offsets_known_at;
360 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
362 /* Number of labels in the current function. */
364 static int num_labels;
366 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
367 static void maybe_fix_stack_asms (void);
368 static void copy_reloads (struct insn_chain *);
369 static void calculate_needs_all_insns (int);
370 static int find_reg (struct insn_chain *, int);
371 static void find_reload_regs (struct insn_chain *);
372 static void select_reload_regs (void);
373 static void delete_caller_save_insns (void);
375 static void spill_failure (rtx, enum reg_class);
376 static void count_spilled_pseudo (int, int, int);
377 static void delete_dead_insn (rtx);
378 static void alter_reg (int, int);
379 static void set_label_offsets (rtx, rtx, int);
380 static void check_eliminable_occurrences (rtx);
381 static void elimination_effects (rtx, enum machine_mode);
382 static int eliminate_regs_in_insn (rtx, int);
383 static void update_eliminable_offsets (void);
384 static void mark_not_eliminable (rtx, rtx, void *);
385 static void set_initial_elim_offsets (void);
386 static void verify_initial_elim_offsets (void);
387 static void set_initial_label_offsets (void);
388 static void set_offsets_for_label (rtx);
389 static void init_elim_table (void);
390 static void update_eliminables (HARD_REG_SET *);
391 static void spill_hard_reg (unsigned int, int);
392 static int finish_spills (int);
393 static void scan_paradoxical_subregs (rtx);
394 static void count_pseudo (int);
395 static void order_regs_for_reload (struct insn_chain *);
396 static void reload_as_needed (int);
397 static void forget_old_reloads_1 (rtx, rtx, void *);
398 static int reload_reg_class_lower (const void *, const void *);
399 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
401 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
403 static int reload_reg_free_p (unsigned int, int, enum reload_type);
404 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
406 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
408 static int function_invariant_p (rtx);
409 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
410 static int allocate_reload_reg (struct insn_chain *, int, int);
411 static int conflicts_with_override (rtx);
412 static void failed_reload (rtx, int);
413 static int set_reload_reg (int, int);
414 static void choose_reload_regs_init (struct insn_chain *, rtx *);
415 static void choose_reload_regs (struct insn_chain *);
416 static void merge_assigned_reloads (rtx);
417 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
419 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
421 static void do_input_reload (struct insn_chain *, struct reload *, int);
422 static void do_output_reload (struct insn_chain *, struct reload *, int);
423 static bool inherit_piecemeal_p (int, int);
424 static void emit_reload_insns (struct insn_chain *);
425 static void delete_output_reload (rtx, int, int);
426 static void delete_address_reloads (rtx, rtx);
427 static void delete_address_reloads_1 (rtx, rtx, rtx);
428 static rtx inc_for_reload (rtx, rtx, rtx, int);
430 static void add_auto_inc_notes (rtx, rtx);
432 static void copy_eh_notes (rtx, rtx);
433 static int reloads_conflict (int, int);
434 static rtx gen_reload (rtx, rtx, int, enum reload_type);
436 /* Initialize the reload pass once per compilation. */
443 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
444 Set spill_indirect_levels to the number of levels such addressing is
445 permitted, zero if it is not permitted at all. */
448 = gen_rtx_MEM (Pmode,
451 LAST_VIRTUAL_REGISTER + 1),
453 spill_indirect_levels = 0;
455 while (memory_address_p (QImode, tem))
457 spill_indirect_levels++;
458 tem = gen_rtx_MEM (Pmode, tem);
461 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
463 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
464 indirect_symref_ok = memory_address_p (QImode, tem);
466 /* See if reg+reg is a valid (and offsettable) address. */
468 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
470 tem = gen_rtx_PLUS (Pmode,
471 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
472 gen_rtx_REG (Pmode, i));
474 /* This way, we make sure that reg+reg is an offsettable address. */
475 tem = plus_constant (tem, 4);
477 if (memory_address_p (QImode, tem))
479 double_reg_address_ok = 1;
484 /* Initialize obstack for our rtl allocation. */
485 gcc_obstack_init (&reload_obstack);
486 reload_startobj = obstack_alloc (&reload_obstack, 0);
488 INIT_REG_SET (&spilled_pseudos);
489 INIT_REG_SET (&pseudos_counted);
490 VARRAY_RTX_INIT (reg_equiv_memory_loc_varray, 0, "reg_equiv_memory_loc");
493 /* List of insn chains that are currently unused. */
494 static struct insn_chain *unused_insn_chains = 0;
496 /* Allocate an empty insn_chain structure. */
498 new_insn_chain (void)
500 struct insn_chain *c;
502 if (unused_insn_chains == 0)
504 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
505 INIT_REG_SET (&c->live_throughout);
506 INIT_REG_SET (&c->dead_or_set);
510 c = unused_insn_chains;
511 unused_insn_chains = c->next;
513 c->is_caller_save_insn = 0;
514 c->need_operand_change = 0;
520 /* Small utility function to set all regs in hard reg set TO which are
521 allocated to pseudos in regset FROM. */
524 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
527 reg_set_iterator rsi;
529 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
531 int r = reg_renumber[regno];
536 /* reload_combine uses the information from
537 BASIC_BLOCK->global_live_at_start, which might still
538 contain registers that have not actually been allocated
539 since they have an equivalence. */
540 gcc_assert (reload_completed);
544 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
546 SET_HARD_REG_BIT (*to, r + nregs);
551 /* Replace all pseudos found in LOC with their corresponding
555 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
568 unsigned int regno = REGNO (x);
570 if (regno < FIRST_PSEUDO_REGISTER)
573 x = eliminate_regs (x, mem_mode, usage);
577 replace_pseudos_in (loc, mem_mode, usage);
581 if (reg_equiv_constant[regno])
582 *loc = reg_equiv_constant[regno];
583 else if (reg_equiv_mem[regno])
584 *loc = reg_equiv_mem[regno];
585 else if (reg_equiv_address[regno])
586 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
589 gcc_assert (!REG_P (regno_reg_rtx[regno])
590 || REGNO (regno_reg_rtx[regno]) != regno);
591 *loc = regno_reg_rtx[regno];
596 else if (code == MEM)
598 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
602 /* Process each of our operands recursively. */
603 fmt = GET_RTX_FORMAT (code);
604 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
606 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
607 else if (*fmt == 'E')
608 for (j = 0; j < XVECLEN (x, i); j++)
609 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
613 /* Global variables used by reload and its subroutines. */
615 /* Set during calculate_needs if an insn needs register elimination. */
616 static int something_needs_elimination;
617 /* Set during calculate_needs if an insn needs an operand changed. */
618 int something_needs_operands_changed;
620 /* Nonzero means we couldn't get enough spill regs. */
623 /* Main entry point for the reload pass.
625 FIRST is the first insn of the function being compiled.
627 GLOBAL nonzero means we were called from global_alloc
628 and should attempt to reallocate any pseudoregs that we
629 displace from hard regs we will use for reloads.
630 If GLOBAL is zero, we do not have enough information to do that,
631 so any pseudo reg that is spilled must go to the stack.
633 Return value is nonzero if reload failed
634 and we must not do any more for this function. */
637 reload (rtx first, int global)
641 struct elim_table *ep;
644 /* Make sure even insns with volatile mem refs are recognizable. */
649 reload_firstobj = obstack_alloc (&reload_obstack, 0);
651 /* Make sure that the last insn in the chain
652 is not something that needs reloading. */
653 emit_note (NOTE_INSN_DELETED);
655 /* Enable find_equiv_reg to distinguish insns made by reload. */
656 reload_first_uid = get_max_uid ();
658 #ifdef SECONDARY_MEMORY_NEEDED
659 /* Initialize the secondary memory table. */
660 clear_secondary_mem ();
663 /* We don't have a stack slot for any spill reg yet. */
664 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
665 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
667 /* Initialize the save area information for caller-save, in case some
671 /* Compute which hard registers are now in use
672 as homes for pseudo registers.
673 This is done here rather than (eg) in global_alloc
674 because this point is reached even if not optimizing. */
675 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
678 /* A function that receives a nonlocal goto must save all call-saved
680 if (current_function_has_nonlocal_label)
681 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
682 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
683 regs_ever_live[i] = 1;
685 /* Find all the pseudo registers that didn't get hard regs
686 but do have known equivalent constants or memory slots.
687 These include parameters (known equivalent to parameter slots)
688 and cse'd or loop-moved constant memory addresses.
690 Record constant equivalents in reg_equiv_constant
691 so they will be substituted by find_reloads.
692 Record memory equivalents in reg_mem_equiv so they can
693 be substituted eventually by altering the REG-rtx's. */
695 reg_equiv_constant = xcalloc (max_regno, sizeof (rtx));
696 reg_equiv_mem = xcalloc (max_regno, sizeof (rtx));
697 reg_equiv_init = xcalloc (max_regno, sizeof (rtx));
698 reg_equiv_address = xcalloc (max_regno, sizeof (rtx));
699 reg_max_ref_width = xcalloc (max_regno, sizeof (int));
700 reg_old_renumber = xcalloc (max_regno, sizeof (short));
701 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
702 pseudo_forbidden_regs = xmalloc (max_regno * sizeof (HARD_REG_SET));
703 pseudo_previous_regs = xcalloc (max_regno, sizeof (HARD_REG_SET));
705 CLEAR_HARD_REG_SET (bad_spill_regs_global);
707 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
708 to. Also find all paradoxical subregs and find largest such for
711 num_eliminable_invariants = 0;
712 for (insn = first; insn; insn = NEXT_INSN (insn))
714 rtx set = single_set (insn);
716 /* We may introduce USEs that we want to remove at the end, so
717 we'll mark them with QImode. Make sure there are no
718 previously-marked insns left by say regmove. */
719 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
720 && GET_MODE (insn) != VOIDmode)
721 PUT_MODE (insn, VOIDmode);
723 if (set != 0 && REG_P (SET_DEST (set)))
725 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
727 && (! function_invariant_p (XEXP (note, 0))
729 /* A function invariant is often CONSTANT_P but may
730 include a register. We promise to only pass
731 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
732 || (CONSTANT_P (XEXP (note, 0))
733 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))))
735 rtx x = XEXP (note, 0);
736 i = REGNO (SET_DEST (set));
737 if (i > LAST_VIRTUAL_REGISTER)
739 /* It can happen that a REG_EQUIV note contains a MEM
740 that is not a legitimate memory operand. As later
741 stages of reload assume that all addresses found
742 in the reg_equiv_* arrays were originally legitimate,
743 we ignore such REG_EQUIV notes. */
744 if (memory_operand (x, VOIDmode))
746 /* Always unshare the equivalence, so we can
747 substitute into this insn without touching the
749 reg_equiv_memory_loc[i] = copy_rtx (x);
751 else if (function_invariant_p (x))
753 if (GET_CODE (x) == PLUS)
755 /* This is PLUS of frame pointer and a constant,
756 and might be shared. Unshare it. */
757 reg_equiv_constant[i] = copy_rtx (x);
758 num_eliminable_invariants++;
760 else if (x == frame_pointer_rtx
761 || x == arg_pointer_rtx)
763 reg_equiv_constant[i] = x;
764 num_eliminable_invariants++;
766 else if (LEGITIMATE_CONSTANT_P (x))
767 reg_equiv_constant[i] = x;
770 reg_equiv_memory_loc[i]
771 = force_const_mem (GET_MODE (SET_DEST (set)), x);
772 if (!reg_equiv_memory_loc[i])
779 /* If this register is being made equivalent to a MEM
780 and the MEM is not SET_SRC, the equivalencing insn
781 is one with the MEM as a SET_DEST and it occurs later.
782 So don't mark this insn now. */
784 || rtx_equal_p (SET_SRC (set), x))
786 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
791 /* If this insn is setting a MEM from a register equivalent to it,
792 this is the equivalencing insn. */
793 else if (set && MEM_P (SET_DEST (set))
794 && REG_P (SET_SRC (set))
795 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
796 && rtx_equal_p (SET_DEST (set),
797 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
798 reg_equiv_init[REGNO (SET_SRC (set))]
799 = gen_rtx_INSN_LIST (VOIDmode, insn,
800 reg_equiv_init[REGNO (SET_SRC (set))]);
803 scan_paradoxical_subregs (PATTERN (insn));
808 first_label_num = get_first_label_num ();
809 num_labels = max_label_num () - first_label_num;
811 /* Allocate the tables used to store offset information at labels. */
812 /* We used to use alloca here, but the size of what it would try to
813 allocate would occasionally cause it to exceed the stack limit and
814 cause a core dump. */
815 offsets_known_at = xmalloc (num_labels);
816 offsets_at = xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
818 /* Alter each pseudo-reg rtx to contain its hard reg number.
819 Assign stack slots to the pseudos that lack hard regs or equivalents.
820 Do not touch virtual registers. */
822 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
825 /* If we have some registers we think can be eliminated, scan all insns to
826 see if there is an insn that sets one of these registers to something
827 other than itself plus a constant. If so, the register cannot be
828 eliminated. Doing this scan here eliminates an extra pass through the
829 main reload loop in the most common case where register elimination
831 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
833 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
835 maybe_fix_stack_asms ();
837 insns_need_reload = 0;
838 something_needs_elimination = 0;
840 /* Initialize to -1, which means take the first spill register. */
843 /* Spill any hard regs that we know we can't eliminate. */
844 CLEAR_HARD_REG_SET (used_spill_regs);
845 /* There can be multiple ways to eliminate a register;
846 they should be listed adjacently.
847 Elimination for any register fails only if all possible ways fail. */
848 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
851 int can_eliminate = 0;
854 can_eliminate |= ep->can_eliminate;
857 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
859 spill_hard_reg (from, 1);
862 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
863 if (frame_pointer_needed)
864 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
866 finish_spills (global);
868 /* From now on, we may need to generate moves differently. We may also
869 allow modifications of insns which cause them to not be recognized.
870 Any such modifications will be cleaned up during reload itself. */
871 reload_in_progress = 1;
873 /* This loop scans the entire function each go-round
874 and repeats until one repetition spills no additional hard regs. */
877 int something_changed;
880 HOST_WIDE_INT starting_frame_size;
882 /* Round size of stack frame to stack_alignment_needed. This must be done
883 here because the stack size may be a part of the offset computation
884 for register elimination, and there might have been new stack slots
885 created in the last iteration of this loop. */
886 if (cfun->stack_alignment_needed)
887 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
889 starting_frame_size = get_frame_size ();
891 set_initial_elim_offsets ();
892 set_initial_label_offsets ();
894 /* For each pseudo register that has an equivalent location defined,
895 try to eliminate any eliminable registers (such as the frame pointer)
896 assuming initial offsets for the replacement register, which
899 If the resulting location is directly addressable, substitute
900 the MEM we just got directly for the old REG.
902 If it is not addressable but is a constant or the sum of a hard reg
903 and constant, it is probably not addressable because the constant is
904 out of range, in that case record the address; we will generate
905 hairy code to compute the address in a register each time it is
906 needed. Similarly if it is a hard register, but one that is not
907 valid as an address register.
909 If the location is not addressable, but does not have one of the
910 above forms, assign a stack slot. We have to do this to avoid the
911 potential of producing lots of reloads if, e.g., a location involves
912 a pseudo that didn't get a hard register and has an equivalent memory
913 location that also involves a pseudo that didn't get a hard register.
915 Perhaps at some point we will improve reload_when_needed handling
916 so this problem goes away. But that's very hairy. */
918 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
919 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
921 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
923 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
925 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
926 else if (CONSTANT_P (XEXP (x, 0))
927 || (REG_P (XEXP (x, 0))
928 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
929 || (GET_CODE (XEXP (x, 0)) == PLUS
930 && REG_P (XEXP (XEXP (x, 0), 0))
931 && (REGNO (XEXP (XEXP (x, 0), 0))
932 < FIRST_PSEUDO_REGISTER)
933 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
934 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
937 /* Make a new stack slot. Then indicate that something
938 changed so we go back and recompute offsets for
939 eliminable registers because the allocation of memory
940 below might change some offset. reg_equiv_{mem,address}
941 will be set up for this pseudo on the next pass around
943 reg_equiv_memory_loc[i] = 0;
944 reg_equiv_init[i] = 0;
949 if (caller_save_needed)
952 /* If we allocated another stack slot, redo elimination bookkeeping. */
953 if (starting_frame_size != get_frame_size ())
956 if (caller_save_needed)
958 save_call_clobbered_regs ();
959 /* That might have allocated new insn_chain structures. */
960 reload_firstobj = obstack_alloc (&reload_obstack, 0);
963 calculate_needs_all_insns (global);
965 CLEAR_REG_SET (&spilled_pseudos);
968 something_changed = 0;
970 /* If we allocated any new memory locations, make another pass
971 since it might have changed elimination offsets. */
972 if (starting_frame_size != get_frame_size ())
973 something_changed = 1;
976 HARD_REG_SET to_spill;
977 CLEAR_HARD_REG_SET (to_spill);
978 update_eliminables (&to_spill);
979 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
980 if (TEST_HARD_REG_BIT (to_spill, i))
982 spill_hard_reg (i, 1);
985 /* Regardless of the state of spills, if we previously had
986 a register that we thought we could eliminate, but now can
987 not eliminate, we must run another pass.
989 Consider pseudos which have an entry in reg_equiv_* which
990 reference an eliminable register. We must make another pass
991 to update reg_equiv_* so that we do not substitute in the
992 old value from when we thought the elimination could be
994 something_changed = 1;
998 select_reload_regs ();
1002 if (insns_need_reload != 0 || did_spill)
1003 something_changed |= finish_spills (global);
1005 if (! something_changed)
1008 if (caller_save_needed)
1009 delete_caller_save_insns ();
1011 obstack_free (&reload_obstack, reload_firstobj);
1014 /* If global-alloc was run, notify it of any register eliminations we have
1017 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1018 if (ep->can_eliminate)
1019 mark_elimination (ep->from, ep->to);
1021 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1022 If that insn didn't set the register (i.e., it copied the register to
1023 memory), just delete that insn instead of the equivalencing insn plus
1024 anything now dead. If we call delete_dead_insn on that insn, we may
1025 delete the insn that actually sets the register if the register dies
1026 there and that is incorrect. */
1028 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1030 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1033 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1035 rtx equiv_insn = XEXP (list, 0);
1037 /* If we already deleted the insn or if it may trap, we can't
1038 delete it. The latter case shouldn't happen, but can
1039 if an insn has a variable address, gets a REG_EH_REGION
1040 note added to it, and then gets converted into an load
1041 from a constant address. */
1042 if (NOTE_P (equiv_insn)
1043 || can_throw_internal (equiv_insn))
1045 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1046 delete_dead_insn (equiv_insn);
1048 SET_INSN_DELETED (equiv_insn);
1053 /* Use the reload registers where necessary
1054 by generating move instructions to move the must-be-register
1055 values into or out of the reload registers. */
1057 if (insns_need_reload != 0 || something_needs_elimination
1058 || something_needs_operands_changed)
1060 HOST_WIDE_INT old_frame_size = get_frame_size ();
1062 reload_as_needed (global);
1064 gcc_assert (old_frame_size == get_frame_size ());
1067 verify_initial_elim_offsets ();
1070 /* If we were able to eliminate the frame pointer, show that it is no
1071 longer live at the start of any basic block. If it ls live by
1072 virtue of being in a pseudo, that pseudo will be marked live
1073 and hence the frame pointer will be known to be live via that
1076 if (! frame_pointer_needed)
1078 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1079 HARD_FRAME_POINTER_REGNUM);
1081 /* Come here (with failure set nonzero) if we can't get enough spill regs
1082 and we decide not to abort about it. */
1085 CLEAR_REG_SET (&spilled_pseudos);
1086 reload_in_progress = 0;
1088 /* Now eliminate all pseudo regs by modifying them into
1089 their equivalent memory references.
1090 The REG-rtx's for the pseudos are modified in place,
1091 so all insns that used to refer to them now refer to memory.
1093 For a reg that has a reg_equiv_address, all those insns
1094 were changed by reloading so that no insns refer to it any longer;
1095 but the DECL_RTL of a variable decl may refer to it,
1096 and if so this causes the debugging info to mention the variable. */
1098 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1102 if (reg_equiv_mem[i])
1103 addr = XEXP (reg_equiv_mem[i], 0);
1105 if (reg_equiv_address[i])
1106 addr = reg_equiv_address[i];
1110 if (reg_renumber[i] < 0)
1112 rtx reg = regno_reg_rtx[i];
1114 REG_USERVAR_P (reg) = 0;
1115 PUT_CODE (reg, MEM);
1116 XEXP (reg, 0) = addr;
1117 if (reg_equiv_memory_loc[i])
1118 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1121 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1122 MEM_ATTRS (reg) = 0;
1125 else if (reg_equiv_mem[i])
1126 XEXP (reg_equiv_mem[i], 0) = addr;
1130 /* We must set reload_completed now since the cleanup_subreg_operands call
1131 below will re-recognize each insn and reload may have generated insns
1132 which are only valid during and after reload. */
1133 reload_completed = 1;
1135 /* Make a pass over all the insns and delete all USEs which we inserted
1136 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1137 notes. Delete all CLOBBER insns, except those that refer to the return
1138 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1139 from misarranging variable-array code, and simplify (subreg (reg))
1140 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1141 are no longer useful or accurate. Strip and regenerate REG_INC notes
1142 that may have been moved around. */
1144 for (insn = first; insn; insn = NEXT_INSN (insn))
1150 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1151 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1153 if ((GET_CODE (PATTERN (insn)) == USE
1154 /* We mark with QImode USEs introduced by reload itself. */
1155 && (GET_MODE (insn) == QImode
1156 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1157 || (GET_CODE (PATTERN (insn)) == CLOBBER
1158 && (!MEM_P (XEXP (PATTERN (insn), 0))
1159 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1160 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1161 && XEXP (XEXP (PATTERN (insn), 0), 0)
1162 != stack_pointer_rtx))
1163 && (!REG_P (XEXP (PATTERN (insn), 0))
1164 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1170 /* Some CLOBBERs may survive until here and still reference unassigned
1171 pseudos with const equivalent, which may in turn cause ICE in later
1172 passes if the reference remains in place. */
1173 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1174 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1175 VOIDmode, PATTERN (insn));
1177 pnote = ®_NOTES (insn);
1180 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1181 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1182 || REG_NOTE_KIND (*pnote) == REG_INC
1183 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1184 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1185 *pnote = XEXP (*pnote, 1);
1187 pnote = &XEXP (*pnote, 1);
1191 add_auto_inc_notes (insn, PATTERN (insn));
1194 /* And simplify (subreg (reg)) if it appears as an operand. */
1195 cleanup_subreg_operands (insn);
1198 /* If we are doing stack checking, give a warning if this function's
1199 frame size is larger than we expect. */
1200 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1202 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1203 static int verbose_warned = 0;
1205 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1206 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1207 size += UNITS_PER_WORD;
1209 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1211 warning ("frame size too large for reliable stack checking");
1212 if (! verbose_warned)
1214 warning ("try reducing the number of local variables");
1220 /* Indicate that we no longer have known memory locations or constants. */
1221 if (reg_equiv_constant)
1222 free (reg_equiv_constant);
1223 reg_equiv_constant = 0;
1224 VARRAY_GROW (reg_equiv_memory_loc_varray, 0);
1225 reg_equiv_memory_loc = 0;
1227 if (offsets_known_at)
1228 free (offsets_known_at);
1232 free (reg_equiv_mem);
1233 free (reg_equiv_init);
1234 free (reg_equiv_address);
1235 free (reg_max_ref_width);
1236 free (reg_old_renumber);
1237 free (pseudo_previous_regs);
1238 free (pseudo_forbidden_regs);
1240 CLEAR_HARD_REG_SET (used_spill_regs);
1241 for (i = 0; i < n_spills; i++)
1242 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1244 /* Free all the insn_chain structures at once. */
1245 obstack_free (&reload_obstack, reload_startobj);
1246 unused_insn_chains = 0;
1247 fixup_abnormal_edges ();
1249 /* Replacing pseudos with their memory equivalents might have
1250 created shared rtx. Subsequent passes would get confused
1251 by this, so unshare everything here. */
1252 unshare_all_rtl_again (first);
1254 #ifdef STACK_BOUNDARY
1255 /* init_emit has set the alignment of the hard frame pointer
1256 to STACK_BOUNDARY. It is very likely no longer valid if
1257 the hard frame pointer was used for register allocation. */
1258 if (!frame_pointer_needed)
1259 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1265 /* Yet another special case. Unfortunately, reg-stack forces people to
1266 write incorrect clobbers in asm statements. These clobbers must not
1267 cause the register to appear in bad_spill_regs, otherwise we'll call
1268 fatal_insn later. We clear the corresponding regnos in the live
1269 register sets to avoid this.
1270 The whole thing is rather sick, I'm afraid. */
1273 maybe_fix_stack_asms (void)
1276 const char *constraints[MAX_RECOG_OPERANDS];
1277 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1278 struct insn_chain *chain;
1280 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1283 HARD_REG_SET clobbered, allowed;
1286 if (! INSN_P (chain->insn)
1287 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1289 pat = PATTERN (chain->insn);
1290 if (GET_CODE (pat) != PARALLEL)
1293 CLEAR_HARD_REG_SET (clobbered);
1294 CLEAR_HARD_REG_SET (allowed);
1296 /* First, make a mask of all stack regs that are clobbered. */
1297 for (i = 0; i < XVECLEN (pat, 0); i++)
1299 rtx t = XVECEXP (pat, 0, i);
1300 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1301 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1304 /* Get the operand values and constraints out of the insn. */
1305 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1306 constraints, operand_mode);
1308 /* For every operand, see what registers are allowed. */
1309 for (i = 0; i < noperands; i++)
1311 const char *p = constraints[i];
1312 /* For every alternative, we compute the class of registers allowed
1313 for reloading in CLS, and merge its contents into the reg set
1315 int cls = (int) NO_REGS;
1321 if (c == '\0' || c == ',' || c == '#')
1323 /* End of one alternative - mark the regs in the current
1324 class, and reset the class. */
1325 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1331 } while (c != '\0' && c != ',');
1339 case '=': case '+': case '*': case '%': case '?': case '!':
1340 case '0': case '1': case '2': case '3': case '4': case 'm':
1341 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1342 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1343 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1348 cls = (int) reg_class_subunion[cls]
1349 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1354 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1358 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1359 cls = (int) reg_class_subunion[cls]
1360 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1362 cls = (int) reg_class_subunion[cls]
1363 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1365 p += CONSTRAINT_LEN (c, p);
1368 /* Those of the registers which are clobbered, but allowed by the
1369 constraints, must be usable as reload registers. So clear them
1370 out of the life information. */
1371 AND_HARD_REG_SET (allowed, clobbered);
1372 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1373 if (TEST_HARD_REG_BIT (allowed, i))
1375 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1376 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1383 /* Copy the global variables n_reloads and rld into the corresponding elts
1386 copy_reloads (struct insn_chain *chain)
1388 chain->n_reloads = n_reloads;
1389 chain->rld = obstack_alloc (&reload_obstack,
1390 n_reloads * sizeof (struct reload));
1391 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1392 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1395 /* Walk the chain of insns, and determine for each whether it needs reloads
1396 and/or eliminations. Build the corresponding insns_need_reload list, and
1397 set something_needs_elimination as appropriate. */
1399 calculate_needs_all_insns (int global)
1401 struct insn_chain **pprev_reload = &insns_need_reload;
1402 struct insn_chain *chain, *next = 0;
1404 something_needs_elimination = 0;
1406 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1407 for (chain = reload_insn_chain; chain != 0; chain = next)
1409 rtx insn = chain->insn;
1413 /* Clear out the shortcuts. */
1414 chain->n_reloads = 0;
1415 chain->need_elim = 0;
1416 chain->need_reload = 0;
1417 chain->need_operand_change = 0;
1419 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1420 include REG_LABEL), we need to see what effects this has on the
1421 known offsets at labels. */
1423 if (LABEL_P (insn) || JUMP_P (insn)
1424 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1425 set_label_offsets (insn, insn, 0);
1429 rtx old_body = PATTERN (insn);
1430 int old_code = INSN_CODE (insn);
1431 rtx old_notes = REG_NOTES (insn);
1432 int did_elimination = 0;
1433 int operands_changed = 0;
1434 rtx set = single_set (insn);
1436 /* Skip insns that only set an equivalence. */
1437 if (set && REG_P (SET_DEST (set))
1438 && reg_renumber[REGNO (SET_DEST (set))] < 0
1439 && reg_equiv_constant[REGNO (SET_DEST (set))])
1442 /* If needed, eliminate any eliminable registers. */
1443 if (num_eliminable || num_eliminable_invariants)
1444 did_elimination = eliminate_regs_in_insn (insn, 0);
1446 /* Analyze the instruction. */
1447 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1448 global, spill_reg_order);
1450 /* If a no-op set needs more than one reload, this is likely
1451 to be something that needs input address reloads. We
1452 can't get rid of this cleanly later, and it is of no use
1453 anyway, so discard it now.
1454 We only do this when expensive_optimizations is enabled,
1455 since this complements reload inheritance / output
1456 reload deletion, and it can make debugging harder. */
1457 if (flag_expensive_optimizations && n_reloads > 1)
1459 rtx set = single_set (insn);
1461 && SET_SRC (set) == SET_DEST (set)
1462 && REG_P (SET_SRC (set))
1463 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1466 /* Delete it from the reload chain. */
1468 chain->prev->next = next;
1470 reload_insn_chain = next;
1472 next->prev = chain->prev;
1473 chain->next = unused_insn_chains;
1474 unused_insn_chains = chain;
1479 update_eliminable_offsets ();
1481 /* Remember for later shortcuts which insns had any reloads or
1482 register eliminations. */
1483 chain->need_elim = did_elimination;
1484 chain->need_reload = n_reloads > 0;
1485 chain->need_operand_change = operands_changed;
1487 /* Discard any register replacements done. */
1488 if (did_elimination)
1490 obstack_free (&reload_obstack, reload_insn_firstobj);
1491 PATTERN (insn) = old_body;
1492 INSN_CODE (insn) = old_code;
1493 REG_NOTES (insn) = old_notes;
1494 something_needs_elimination = 1;
1497 something_needs_operands_changed |= operands_changed;
1501 copy_reloads (chain);
1502 *pprev_reload = chain;
1503 pprev_reload = &chain->next_need_reload;
1510 /* Comparison function for qsort to decide which of two reloads
1511 should be handled first. *P1 and *P2 are the reload numbers. */
1514 reload_reg_class_lower (const void *r1p, const void *r2p)
1516 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1519 /* Consider required reloads before optional ones. */
1520 t = rld[r1].optional - rld[r2].optional;
1524 /* Count all solitary classes before non-solitary ones. */
1525 t = ((reg_class_size[(int) rld[r2].class] == 1)
1526 - (reg_class_size[(int) rld[r1].class] == 1));
1530 /* Aside from solitaires, consider all multi-reg groups first. */
1531 t = rld[r2].nregs - rld[r1].nregs;
1535 /* Consider reloads in order of increasing reg-class number. */
1536 t = (int) rld[r1].class - (int) rld[r2].class;
1540 /* If reloads are equally urgent, sort by reload number,
1541 so that the results of qsort leave nothing to chance. */
1545 /* The cost of spilling each hard reg. */
1546 static int spill_cost[FIRST_PSEUDO_REGISTER];
1548 /* When spilling multiple hard registers, we use SPILL_COST for the first
1549 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1550 only the first hard reg for a multi-reg pseudo. */
1551 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1553 /* Update the spill cost arrays, considering that pseudo REG is live. */
1556 count_pseudo (int reg)
1558 int freq = REG_FREQ (reg);
1559 int r = reg_renumber[reg];
1562 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1563 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1566 SET_REGNO_REG_SET (&pseudos_counted, reg);
1568 gcc_assert (r >= 0);
1570 spill_add_cost[r] += freq;
1572 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1574 spill_cost[r + nregs] += freq;
1577 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1578 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1581 order_regs_for_reload (struct insn_chain *chain)
1584 HARD_REG_SET used_by_pseudos;
1585 HARD_REG_SET used_by_pseudos2;
1586 reg_set_iterator rsi;
1588 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1590 memset (spill_cost, 0, sizeof spill_cost);
1591 memset (spill_add_cost, 0, sizeof spill_add_cost);
1593 /* Count number of uses of each hard reg by pseudo regs allocated to it
1594 and then order them by decreasing use. First exclude hard registers
1595 that are live in or across this insn. */
1597 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1598 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1599 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1600 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1602 /* Now find out which pseudos are allocated to it, and update
1604 CLEAR_REG_SET (&pseudos_counted);
1606 EXECUTE_IF_SET_IN_REG_SET
1607 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1611 EXECUTE_IF_SET_IN_REG_SET
1612 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1616 CLEAR_REG_SET (&pseudos_counted);
1619 /* Vector of reload-numbers showing the order in which the reloads should
1621 static short reload_order[MAX_RELOADS];
1623 /* This is used to keep track of the spill regs used in one insn. */
1624 static HARD_REG_SET used_spill_regs_local;
1626 /* We decided to spill hard register SPILLED, which has a size of
1627 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1628 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1629 update SPILL_COST/SPILL_ADD_COST. */
1632 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1634 int r = reg_renumber[reg];
1635 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1637 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1638 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1641 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1643 spill_add_cost[r] -= REG_FREQ (reg);
1645 spill_cost[r + nregs] -= REG_FREQ (reg);
1648 /* Find reload register to use for reload number ORDER. */
1651 find_reg (struct insn_chain *chain, int order)
1653 int rnum = reload_order[order];
1654 struct reload *rl = rld + rnum;
1655 int best_cost = INT_MAX;
1659 HARD_REG_SET not_usable;
1660 HARD_REG_SET used_by_other_reload;
1661 reg_set_iterator rsi;
1663 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1664 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1665 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1667 CLEAR_HARD_REG_SET (used_by_other_reload);
1668 for (k = 0; k < order; k++)
1670 int other = reload_order[k];
1672 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1673 for (j = 0; j < rld[other].nregs; j++)
1674 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1677 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1679 unsigned int regno = i;
1681 if (! TEST_HARD_REG_BIT (not_usable, regno)
1682 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1683 && HARD_REGNO_MODE_OK (regno, rl->mode))
1685 int this_cost = spill_cost[regno];
1687 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1689 for (j = 1; j < this_nregs; j++)
1691 this_cost += spill_add_cost[regno + j];
1692 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1693 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1698 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1700 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1702 if (this_cost < best_cost
1703 /* Among registers with equal cost, prefer caller-saved ones, or
1704 use REG_ALLOC_ORDER if it is defined. */
1705 || (this_cost == best_cost
1706 #ifdef REG_ALLOC_ORDER
1707 && (inv_reg_alloc_order[regno]
1708 < inv_reg_alloc_order[best_reg])
1710 && call_used_regs[regno]
1711 && ! call_used_regs[best_reg]
1716 best_cost = this_cost;
1724 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1726 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1727 rl->regno = best_reg;
1729 EXECUTE_IF_SET_IN_REG_SET
1730 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1732 count_spilled_pseudo (best_reg, rl->nregs, j);
1735 EXECUTE_IF_SET_IN_REG_SET
1736 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1738 count_spilled_pseudo (best_reg, rl->nregs, j);
1741 for (i = 0; i < rl->nregs; i++)
1743 gcc_assert (spill_cost[best_reg + i] == 0);
1744 gcc_assert (spill_add_cost[best_reg + i] == 0);
1745 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1750 /* Find more reload regs to satisfy the remaining need of an insn, which
1752 Do it by ascending class number, since otherwise a reg
1753 might be spilled for a big class and might fail to count
1754 for a smaller class even though it belongs to that class. */
1757 find_reload_regs (struct insn_chain *chain)
1761 /* In order to be certain of getting the registers we need,
1762 we must sort the reloads into order of increasing register class.
1763 Then our grabbing of reload registers will parallel the process
1764 that provided the reload registers. */
1765 for (i = 0; i < chain->n_reloads; i++)
1767 /* Show whether this reload already has a hard reg. */
1768 if (chain->rld[i].reg_rtx)
1770 int regno = REGNO (chain->rld[i].reg_rtx);
1771 chain->rld[i].regno = regno;
1773 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1776 chain->rld[i].regno = -1;
1777 reload_order[i] = i;
1780 n_reloads = chain->n_reloads;
1781 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1783 CLEAR_HARD_REG_SET (used_spill_regs_local);
1786 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1788 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1790 /* Compute the order of preference for hard registers to spill. */
1792 order_regs_for_reload (chain);
1794 for (i = 0; i < n_reloads; i++)
1796 int r = reload_order[i];
1798 /* Ignore reloads that got marked inoperative. */
1799 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1800 && ! rld[r].optional
1801 && rld[r].regno == -1)
1802 if (! find_reg (chain, i))
1804 spill_failure (chain->insn, rld[r].class);
1810 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1811 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1813 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1817 select_reload_regs (void)
1819 struct insn_chain *chain;
1821 /* Try to satisfy the needs for each insn. */
1822 for (chain = insns_need_reload; chain != 0;
1823 chain = chain->next_need_reload)
1824 find_reload_regs (chain);
1827 /* Delete all insns that were inserted by emit_caller_save_insns during
1830 delete_caller_save_insns (void)
1832 struct insn_chain *c = reload_insn_chain;
1836 while (c != 0 && c->is_caller_save_insn)
1838 struct insn_chain *next = c->next;
1841 if (c == reload_insn_chain)
1842 reload_insn_chain = next;
1846 next->prev = c->prev;
1848 c->prev->next = next;
1849 c->next = unused_insn_chains;
1850 unused_insn_chains = c;
1858 /* Handle the failure to find a register to spill.
1859 INSN should be one of the insns which needed this particular spill reg. */
1862 spill_failure (rtx insn, enum reg_class class)
1864 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1865 if (asm_noperands (PATTERN (insn)) >= 0)
1866 error_for_asm (insn, "can't find a register in class %qs while "
1867 "reloading %<asm%>",
1868 reg_class_names[class]);
1871 error ("unable to find a register to spill in class %qs",
1872 reg_class_names[class]);
1873 fatal_insn ("this is the insn:", insn);
1877 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1878 data that is dead in INSN. */
1881 delete_dead_insn (rtx insn)
1883 rtx prev = prev_real_insn (insn);
1886 /* If the previous insn sets a register that dies in our insn, delete it
1888 if (prev && GET_CODE (PATTERN (prev)) == SET
1889 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
1890 && reg_mentioned_p (prev_dest, PATTERN (insn))
1891 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1892 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1893 delete_dead_insn (prev);
1895 SET_INSN_DELETED (insn);
1898 /* Modify the home of pseudo-reg I.
1899 The new home is present in reg_renumber[I].
1901 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1902 or it may be -1, meaning there is none or it is not relevant.
1903 This is used so that all pseudos spilled from a given hard reg
1904 can share one stack slot. */
1907 alter_reg (int i, int from_reg)
1909 /* When outputting an inline function, this can happen
1910 for a reg that isn't actually used. */
1911 if (regno_reg_rtx[i] == 0)
1914 /* If the reg got changed to a MEM at rtl-generation time,
1916 if (!REG_P (regno_reg_rtx[i]))
1919 /* Modify the reg-rtx to contain the new hard reg
1920 number or else to contain its pseudo reg number. */
1921 REGNO (regno_reg_rtx[i])
1922 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1924 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1925 allocate a stack slot for it. */
1927 if (reg_renumber[i] < 0
1928 && REG_N_REFS (i) > 0
1929 && reg_equiv_constant[i] == 0
1930 && reg_equiv_memory_loc[i] == 0)
1933 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1934 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1937 /* Each pseudo reg has an inherent size which comes from its own mode,
1938 and a total size which provides room for paradoxical subregs
1939 which refer to the pseudo reg in wider modes.
1941 We can use a slot already allocated if it provides both
1942 enough inherent space and enough total space.
1943 Otherwise, we allocate a new slot, making sure that it has no less
1944 inherent space, and no less total space, then the previous slot. */
1947 /* No known place to spill from => no slot to reuse. */
1948 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1949 inherent_size == total_size ? 0 : -1);
1950 if (BYTES_BIG_ENDIAN)
1951 /* Cancel the big-endian correction done in assign_stack_local.
1952 Get the address of the beginning of the slot.
1953 This is so we can do a big-endian correction unconditionally
1955 adjust = inherent_size - total_size;
1957 /* Nothing can alias this slot except this pseudo. */
1958 set_mem_alias_set (x, new_alias_set ());
1961 /* Reuse a stack slot if possible. */
1962 else if (spill_stack_slot[from_reg] != 0
1963 && spill_stack_slot_width[from_reg] >= total_size
1964 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1966 x = spill_stack_slot[from_reg];
1968 /* Allocate a bigger slot. */
1971 /* Compute maximum size needed, both for inherent size
1972 and for total size. */
1973 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1976 if (spill_stack_slot[from_reg])
1978 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1980 mode = GET_MODE (spill_stack_slot[from_reg]);
1981 if (spill_stack_slot_width[from_reg] > total_size)
1982 total_size = spill_stack_slot_width[from_reg];
1985 /* Make a slot with that size. */
1986 x = assign_stack_local (mode, total_size,
1987 inherent_size == total_size ? 0 : -1);
1990 /* All pseudos mapped to this slot can alias each other. */
1991 if (spill_stack_slot[from_reg])
1992 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
1994 set_mem_alias_set (x, new_alias_set ());
1996 if (BYTES_BIG_ENDIAN)
1998 /* Cancel the big-endian correction done in assign_stack_local.
1999 Get the address of the beginning of the slot.
2000 This is so we can do a big-endian correction unconditionally
2002 adjust = GET_MODE_SIZE (mode) - total_size;
2005 = adjust_address_nv (x, mode_for_size (total_size
2011 spill_stack_slot[from_reg] = stack_slot;
2012 spill_stack_slot_width[from_reg] = total_size;
2015 /* On a big endian machine, the "address" of the slot
2016 is the address of the low part that fits its inherent mode. */
2017 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2018 adjust += (total_size - inherent_size);
2020 /* If we have any adjustment to make, or if the stack slot is the
2021 wrong mode, make a new stack slot. */
2022 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2024 /* If we have a decl for the original register, set it for the
2025 memory. If this is a shared MEM, make a copy. */
2026 if (REG_EXPR (regno_reg_rtx[i])
2027 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2029 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2031 /* We can do this only for the DECLs home pseudo, not for
2032 any copies of it, since otherwise when the stack slot
2033 is reused, nonoverlapping_memrefs_p might think they
2035 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2037 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2040 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2044 /* Save the stack slot for later. */
2045 reg_equiv_memory_loc[i] = x;
2049 /* Mark the slots in regs_ever_live for the hard regs
2050 used by pseudo-reg number REGNO. */
2053 mark_home_live (int regno)
2057 i = reg_renumber[regno];
2060 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2062 regs_ever_live[i++] = 1;
2065 /* This function handles the tracking of elimination offsets around branches.
2067 X is a piece of RTL being scanned.
2069 INSN is the insn that it came from, if any.
2071 INITIAL_P is nonzero if we are to set the offset to be the initial
2072 offset and zero if we are setting the offset of the label to be the
2076 set_label_offsets (rtx x, rtx insn, int initial_p)
2078 enum rtx_code code = GET_CODE (x);
2081 struct elim_table *p;
2086 if (LABEL_REF_NONLOCAL_P (x))
2091 /* ... fall through ... */
2094 /* If we know nothing about this label, set the desired offsets. Note
2095 that this sets the offset at a label to be the offset before a label
2096 if we don't know anything about the label. This is not correct for
2097 the label after a BARRIER, but is the best guess we can make. If
2098 we guessed wrong, we will suppress an elimination that might have
2099 been possible had we been able to guess correctly. */
2101 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2103 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2104 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2105 = (initial_p ? reg_eliminate[i].initial_offset
2106 : reg_eliminate[i].offset);
2107 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2110 /* Otherwise, if this is the definition of a label and it is
2111 preceded by a BARRIER, set our offsets to the known offset of
2115 && (tem = prev_nonnote_insn (insn)) != 0
2117 set_offsets_for_label (insn);
2119 /* If neither of the above cases is true, compare each offset
2120 with those previously recorded and suppress any eliminations
2121 where the offsets disagree. */
2123 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2124 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2125 != (initial_p ? reg_eliminate[i].initial_offset
2126 : reg_eliminate[i].offset))
2127 reg_eliminate[i].can_eliminate = 0;
2132 set_label_offsets (PATTERN (insn), insn, initial_p);
2134 /* ... fall through ... */
2138 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2139 and hence must have all eliminations at their initial offsets. */
2140 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2141 if (REG_NOTE_KIND (tem) == REG_LABEL)
2142 set_label_offsets (XEXP (tem, 0), insn, 1);
2148 /* Each of the labels in the parallel or address vector must be
2149 at their initial offsets. We want the first field for PARALLEL
2150 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2152 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2153 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2158 /* We only care about setting PC. If the source is not RETURN,
2159 IF_THEN_ELSE, or a label, disable any eliminations not at
2160 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2161 isn't one of those possibilities. For branches to a label,
2162 call ourselves recursively.
2164 Note that this can disable elimination unnecessarily when we have
2165 a non-local goto since it will look like a non-constant jump to
2166 someplace in the current function. This isn't a significant
2167 problem since such jumps will normally be when all elimination
2168 pairs are back to their initial offsets. */
2170 if (SET_DEST (x) != pc_rtx)
2173 switch (GET_CODE (SET_SRC (x)))
2180 set_label_offsets (SET_SRC (x), insn, initial_p);
2184 tem = XEXP (SET_SRC (x), 1);
2185 if (GET_CODE (tem) == LABEL_REF)
2186 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2187 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2190 tem = XEXP (SET_SRC (x), 2);
2191 if (GET_CODE (tem) == LABEL_REF)
2192 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2193 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2201 /* If we reach here, all eliminations must be at their initial
2202 offset because we are doing a jump to a variable address. */
2203 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2204 if (p->offset != p->initial_offset)
2205 p->can_eliminate = 0;
2213 /* Scan X and replace any eliminable registers (such as fp) with a
2214 replacement (such as sp), plus an offset.
2216 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2217 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2218 MEM, we are allowed to replace a sum of a register and the constant zero
2219 with the register, which we cannot do outside a MEM. In addition, we need
2220 to record the fact that a register is referenced outside a MEM.
2222 If INSN is an insn, it is the insn containing X. If we replace a REG
2223 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2224 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2225 the REG is being modified.
2227 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2228 That's used when we eliminate in expressions stored in notes.
2229 This means, do not set ref_outside_mem even if the reference
2232 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2233 replacements done assuming all offsets are at their initial values. If
2234 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2235 encounter, return the actual location so that find_reloads will do
2236 the proper thing. */
2239 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2241 enum rtx_code code = GET_CODE (x);
2242 struct elim_table *ep;
2249 if (! current_function_decl)
2271 /* First handle the case where we encounter a bare register that
2272 is eliminable. Replace it with a PLUS. */
2273 if (regno < FIRST_PSEUDO_REGISTER)
2275 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2277 if (ep->from_rtx == x && ep->can_eliminate)
2278 return plus_constant (ep->to_rtx, ep->previous_offset);
2281 else if (reg_renumber && reg_renumber[regno] < 0
2282 && reg_equiv_constant && reg_equiv_constant[regno]
2283 && ! CONSTANT_P (reg_equiv_constant[regno]))
2284 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2288 /* You might think handling MINUS in a manner similar to PLUS is a
2289 good idea. It is not. It has been tried multiple times and every
2290 time the change has had to have been reverted.
2292 Other parts of reload know a PLUS is special (gen_reload for example)
2293 and require special code to handle code a reloaded PLUS operand.
2295 Also consider backends where the flags register is clobbered by a
2296 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2297 lea instruction comes to mind). If we try to reload a MINUS, we
2298 may kill the flags register that was holding a useful value.
2300 So, please before trying to handle MINUS, consider reload as a
2301 whole instead of this little section as well as the backend issues. */
2303 /* If this is the sum of an eliminable register and a constant, rework
2305 if (REG_P (XEXP (x, 0))
2306 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2307 && CONSTANT_P (XEXP (x, 1)))
2309 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2311 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2313 /* The only time we want to replace a PLUS with a REG (this
2314 occurs when the constant operand of the PLUS is the negative
2315 of the offset) is when we are inside a MEM. We won't want
2316 to do so at other times because that would change the
2317 structure of the insn in a way that reload can't handle.
2318 We special-case the commonest situation in
2319 eliminate_regs_in_insn, so just replace a PLUS with a
2320 PLUS here, unless inside a MEM. */
2321 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2322 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2325 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2326 plus_constant (XEXP (x, 1),
2327 ep->previous_offset));
2330 /* If the register is not eliminable, we are done since the other
2331 operand is a constant. */
2335 /* If this is part of an address, we want to bring any constant to the
2336 outermost PLUS. We will do this by doing register replacement in
2337 our operands and seeing if a constant shows up in one of them.
2339 Note that there is no risk of modifying the structure of the insn,
2340 since we only get called for its operands, thus we are either
2341 modifying the address inside a MEM, or something like an address
2342 operand of a load-address insn. */
2345 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2346 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2348 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2350 /* If one side is a PLUS and the other side is a pseudo that
2351 didn't get a hard register but has a reg_equiv_constant,
2352 we must replace the constant here since it may no longer
2353 be in the position of any operand. */
2354 if (GET_CODE (new0) == PLUS && REG_P (new1)
2355 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2356 && reg_renumber[REGNO (new1)] < 0
2357 && reg_equiv_constant != 0
2358 && reg_equiv_constant[REGNO (new1)] != 0)
2359 new1 = reg_equiv_constant[REGNO (new1)];
2360 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2361 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2362 && reg_renumber[REGNO (new0)] < 0
2363 && reg_equiv_constant[REGNO (new0)] != 0)
2364 new0 = reg_equiv_constant[REGNO (new0)];
2366 new = form_sum (new0, new1);
2368 /* As above, if we are not inside a MEM we do not want to
2369 turn a PLUS into something else. We might try to do so here
2370 for an addition of 0 if we aren't optimizing. */
2371 if (! mem_mode && GET_CODE (new) != PLUS)
2372 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2380 /* If this is the product of an eliminable register and a
2381 constant, apply the distribute law and move the constant out
2382 so that we have (plus (mult ..) ..). This is needed in order
2383 to keep load-address insns valid. This case is pathological.
2384 We ignore the possibility of overflow here. */
2385 if (REG_P (XEXP (x, 0))
2386 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2387 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2388 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2390 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2393 /* Refs inside notes don't count for this purpose. */
2394 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2395 || GET_CODE (insn) == INSN_LIST)))
2396 ep->ref_outside_mem = 1;
2399 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2400 ep->previous_offset * INTVAL (XEXP (x, 1)));
2403 /* ... fall through ... */
2407 /* See comments before PLUS about handling MINUS. */
2409 case DIV: case UDIV:
2410 case MOD: case UMOD:
2411 case AND: case IOR: case XOR:
2412 case ROTATERT: case ROTATE:
2413 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2415 case GE: case GT: case GEU: case GTU:
2416 case LE: case LT: case LEU: case LTU:
2418 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2420 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2422 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2423 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2428 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2431 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2432 if (new != XEXP (x, 0))
2434 /* If this is a REG_DEAD note, it is not valid anymore.
2435 Using the eliminated version could result in creating a
2436 REG_DEAD note for the stack or frame pointer. */
2437 if (GET_MODE (x) == REG_DEAD)
2439 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2442 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2446 /* ... fall through ... */
2449 /* Now do eliminations in the rest of the chain. If this was
2450 an EXPR_LIST, this might result in allocating more memory than is
2451 strictly needed, but it simplifies the code. */
2454 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2455 if (new != XEXP (x, 1))
2457 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2465 case STRICT_LOW_PART:
2467 case SIGN_EXTEND: case ZERO_EXTEND:
2468 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2469 case FLOAT: case FIX:
2470 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2478 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2479 if (new != XEXP (x, 0))
2480 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2484 /* Similar to above processing, but preserve SUBREG_BYTE.
2485 Convert (subreg (mem)) to (mem) if not paradoxical.
2486 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2487 pseudo didn't get a hard reg, we must replace this with the
2488 eliminated version of the memory location because push_reload
2489 may do the replacement in certain circumstances. */
2490 if (REG_P (SUBREG_REG (x))
2491 && (GET_MODE_SIZE (GET_MODE (x))
2492 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2493 && reg_equiv_memory_loc != 0
2494 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2496 new = SUBREG_REG (x);
2499 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2501 if (new != SUBREG_REG (x))
2503 int x_size = GET_MODE_SIZE (GET_MODE (x));
2504 int new_size = GET_MODE_SIZE (GET_MODE (new));
2507 && ((x_size < new_size
2508 #ifdef WORD_REGISTER_OPERATIONS
2509 /* On these machines, combine can create rtl of the form
2510 (set (subreg:m1 (reg:m2 R) 0) ...)
2511 where m1 < m2, and expects something interesting to
2512 happen to the entire word. Moreover, it will use the
2513 (reg:m2 R) later, expecting all bits to be preserved.
2514 So if the number of words is the same, preserve the
2515 subreg so that push_reload can see it. */
2516 && ! ((x_size - 1) / UNITS_PER_WORD
2517 == (new_size -1 ) / UNITS_PER_WORD)
2520 || x_size == new_size)
2522 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2524 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2530 /* Our only special processing is to pass the mode of the MEM to our
2531 recursive call and copy the flags. While we are here, handle this
2532 case more efficiently. */
2534 replace_equiv_address_nv (x,
2535 eliminate_regs (XEXP (x, 0),
2536 GET_MODE (x), insn));
2539 /* Handle insn_list USE that a call to a pure function may generate. */
2540 new = eliminate_regs (XEXP (x, 0), 0, insn);
2541 if (new != XEXP (x, 0))
2542 return gen_rtx_USE (GET_MODE (x), new);
2554 /* Process each of our operands recursively. If any have changed, make a
2556 fmt = GET_RTX_FORMAT (code);
2557 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2561 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2562 if (new != XEXP (x, i) && ! copied)
2564 rtx new_x = rtx_alloc (code);
2565 memcpy (new_x, x, RTX_SIZE (code));
2571 else if (*fmt == 'E')
2574 for (j = 0; j < XVECLEN (x, i); j++)
2576 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2577 if (new != XVECEXP (x, i, j) && ! copied_vec)
2579 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2583 rtx new_x = rtx_alloc (code);
2584 memcpy (new_x, x, RTX_SIZE (code));
2588 XVEC (x, i) = new_v;
2591 XVECEXP (x, i, j) = new;
2599 /* Scan rtx X for modifications of elimination target registers. Update
2600 the table of eliminables to reflect the changed state. MEM_MODE is
2601 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2604 elimination_effects (rtx x, enum machine_mode mem_mode)
2606 enum rtx_code code = GET_CODE (x);
2607 struct elim_table *ep;
2631 /* First handle the case where we encounter a bare register that
2632 is eliminable. Replace it with a PLUS. */
2633 if (regno < FIRST_PSEUDO_REGISTER)
2635 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2637 if (ep->from_rtx == x && ep->can_eliminate)
2640 ep->ref_outside_mem = 1;
2645 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2646 && reg_equiv_constant[regno]
2647 && ! function_invariant_p (reg_equiv_constant[regno]))
2648 elimination_effects (reg_equiv_constant[regno], mem_mode);
2657 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2658 if (ep->to_rtx == XEXP (x, 0))
2660 int size = GET_MODE_SIZE (mem_mode);
2662 /* If more bytes than MEM_MODE are pushed, account for them. */
2663 #ifdef PUSH_ROUNDING
2664 if (ep->to_rtx == stack_pointer_rtx)
2665 size = PUSH_ROUNDING (size);
2667 if (code == PRE_DEC || code == POST_DEC)
2669 else if (code == PRE_INC || code == POST_INC)
2671 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2672 && GET_CODE (XEXP (x, 1)) == PLUS
2673 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2674 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2675 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2678 /* These two aren't unary operators. */
2679 if (code == POST_MODIFY || code == PRE_MODIFY)
2682 /* Fall through to generic unary operation case. */
2683 case STRICT_LOW_PART:
2685 case SIGN_EXTEND: case ZERO_EXTEND:
2686 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2687 case FLOAT: case FIX:
2688 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2696 elimination_effects (XEXP (x, 0), mem_mode);
2700 if (REG_P (SUBREG_REG (x))
2701 && (GET_MODE_SIZE (GET_MODE (x))
2702 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2703 && reg_equiv_memory_loc != 0
2704 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2707 elimination_effects (SUBREG_REG (x), mem_mode);
2711 /* If using a register that is the source of an eliminate we still
2712 think can be performed, note it cannot be performed since we don't
2713 know how this register is used. */
2714 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2715 if (ep->from_rtx == XEXP (x, 0))
2716 ep->can_eliminate = 0;
2718 elimination_effects (XEXP (x, 0), mem_mode);
2722 /* If clobbering a register that is the replacement register for an
2723 elimination we still think can be performed, note that it cannot
2724 be performed. Otherwise, we need not be concerned about it. */
2725 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2726 if (ep->to_rtx == XEXP (x, 0))
2727 ep->can_eliminate = 0;
2729 elimination_effects (XEXP (x, 0), mem_mode);
2733 /* Check for setting a register that we know about. */
2734 if (REG_P (SET_DEST (x)))
2736 /* See if this is setting the replacement register for an
2739 If DEST is the hard frame pointer, we do nothing because we
2740 assume that all assignments to the frame pointer are for
2741 non-local gotos and are being done at a time when they are valid
2742 and do not disturb anything else. Some machines want to
2743 eliminate a fake argument pointer (or even a fake frame pointer)
2744 with either the real frame or the stack pointer. Assignments to
2745 the hard frame pointer must not prevent this elimination. */
2747 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2749 if (ep->to_rtx == SET_DEST (x)
2750 && SET_DEST (x) != hard_frame_pointer_rtx)
2752 /* If it is being incremented, adjust the offset. Otherwise,
2753 this elimination can't be done. */
2754 rtx src = SET_SRC (x);
2756 if (GET_CODE (src) == PLUS
2757 && XEXP (src, 0) == SET_DEST (x)
2758 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2759 ep->offset -= INTVAL (XEXP (src, 1));
2761 ep->can_eliminate = 0;
2765 elimination_effects (SET_DEST (x), 0);
2766 elimination_effects (SET_SRC (x), 0);
2770 /* Our only special processing is to pass the mode of the MEM to our
2772 elimination_effects (XEXP (x, 0), GET_MODE (x));
2779 fmt = GET_RTX_FORMAT (code);
2780 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2783 elimination_effects (XEXP (x, i), mem_mode);
2784 else if (*fmt == 'E')
2785 for (j = 0; j < XVECLEN (x, i); j++)
2786 elimination_effects (XVECEXP (x, i, j), mem_mode);
2790 /* Descend through rtx X and verify that no references to eliminable registers
2791 remain. If any do remain, mark the involved register as not
2795 check_eliminable_occurrences (rtx x)
2804 code = GET_CODE (x);
2806 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2808 struct elim_table *ep;
2810 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2811 if (ep->from_rtx == x)
2812 ep->can_eliminate = 0;
2816 fmt = GET_RTX_FORMAT (code);
2817 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2820 check_eliminable_occurrences (XEXP (x, i));
2821 else if (*fmt == 'E')
2824 for (j = 0; j < XVECLEN (x, i); j++)
2825 check_eliminable_occurrences (XVECEXP (x, i, j));
2830 /* Scan INSN and eliminate all eliminable registers in it.
2832 If REPLACE is nonzero, do the replacement destructively. Also
2833 delete the insn as dead it if it is setting an eliminable register.
2835 If REPLACE is zero, do all our allocations in reload_obstack.
2837 If no eliminations were done and this insn doesn't require any elimination
2838 processing (these are not identical conditions: it might be updating sp,
2839 but not referencing fp; this needs to be seen during reload_as_needed so
2840 that the offset between fp and sp can be taken into consideration), zero
2841 is returned. Otherwise, 1 is returned. */
2844 eliminate_regs_in_insn (rtx insn, int replace)
2846 int icode = recog_memoized (insn);
2847 rtx old_body = PATTERN (insn);
2848 int insn_is_asm = asm_noperands (old_body) >= 0;
2849 rtx old_set = single_set (insn);
2853 rtx substed_operand[MAX_RECOG_OPERANDS];
2854 rtx orig_operand[MAX_RECOG_OPERANDS];
2855 struct elim_table *ep;
2858 if (! insn_is_asm && icode < 0)
2860 gcc_assert (GET_CODE (PATTERN (insn)) == USE
2861 || GET_CODE (PATTERN (insn)) == CLOBBER
2862 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2863 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2864 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
2868 if (old_set != 0 && REG_P (SET_DEST (old_set))
2869 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2871 /* Check for setting an eliminable register. */
2872 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2873 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2875 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2876 /* If this is setting the frame pointer register to the
2877 hardware frame pointer register and this is an elimination
2878 that will be done (tested above), this insn is really
2879 adjusting the frame pointer downward to compensate for
2880 the adjustment done before a nonlocal goto. */
2881 if (ep->from == FRAME_POINTER_REGNUM
2882 && ep->to == HARD_FRAME_POINTER_REGNUM)
2884 rtx base = SET_SRC (old_set);
2885 rtx base_insn = insn;
2886 HOST_WIDE_INT offset = 0;
2888 while (base != ep->to_rtx)
2890 rtx prev_insn, prev_set;
2892 if (GET_CODE (base) == PLUS
2893 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2895 offset += INTVAL (XEXP (base, 1));
2896 base = XEXP (base, 0);
2898 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2899 && (prev_set = single_set (prev_insn)) != 0
2900 && rtx_equal_p (SET_DEST (prev_set), base))
2902 base = SET_SRC (prev_set);
2903 base_insn = prev_insn;
2909 if (base == ep->to_rtx)
2912 = plus_constant (ep->to_rtx, offset - ep->offset);
2914 new_body = old_body;
2917 new_body = copy_insn (old_body);
2918 if (REG_NOTES (insn))
2919 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2921 PATTERN (insn) = new_body;
2922 old_set = single_set (insn);
2924 /* First see if this insn remains valid when we
2925 make the change. If not, keep the INSN_CODE
2926 the same and let reload fit it up. */
2927 validate_change (insn, &SET_SRC (old_set), src, 1);
2928 validate_change (insn, &SET_DEST (old_set),
2930 if (! apply_change_group ())
2932 SET_SRC (old_set) = src;
2933 SET_DEST (old_set) = ep->to_rtx;
2942 /* In this case this insn isn't serving a useful purpose. We
2943 will delete it in reload_as_needed once we know that this
2944 elimination is, in fact, being done.
2946 If REPLACE isn't set, we can't delete this insn, but needn't
2947 process it since it won't be used unless something changes. */
2950 delete_dead_insn (insn);
2958 /* We allow one special case which happens to work on all machines we
2959 currently support: a single set with the source or a REG_EQUAL
2960 note being a PLUS of an eliminable register and a constant. */
2962 if (old_set && REG_P (SET_DEST (old_set)))
2964 /* First see if the source is of the form (plus (reg) CST). */
2965 if (GET_CODE (SET_SRC (old_set)) == PLUS
2966 && REG_P (XEXP (SET_SRC (old_set), 0))
2967 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
2968 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
2969 plus_src = SET_SRC (old_set);
2970 else if (REG_P (SET_SRC (old_set)))
2972 /* Otherwise, see if we have a REG_EQUAL note of the form
2973 (plus (reg) CST). */
2975 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
2977 if (REG_NOTE_KIND (links) == REG_EQUAL
2978 && GET_CODE (XEXP (links, 0)) == PLUS
2979 && REG_P (XEXP (XEXP (links, 0), 0))
2980 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT
2981 && REGNO (XEXP (XEXP (links, 0), 0)) < FIRST_PSEUDO_REGISTER)
2983 plus_src = XEXP (links, 0);
2991 rtx reg = XEXP (plus_src, 0);
2992 HOST_WIDE_INT offset = INTVAL (XEXP (plus_src, 1));
2994 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2995 if (ep->from_rtx == reg && ep->can_eliminate)
2997 offset += ep->offset;
3002 /* We assume here that if we need a PARALLEL with
3003 CLOBBERs for this assignment, we can do with the
3004 MATCH_SCRATCHes that add_clobbers allocates.
3005 There's not much we can do if that doesn't work. */
3006 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3010 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3013 rtvec vec = rtvec_alloc (num_clobbers + 1);
3015 vec->elem[0] = PATTERN (insn);
3016 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3017 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3019 gcc_assert (INSN_CODE (insn) >= 0);
3021 /* If we have a nonzero offset, and the source is already
3022 a simple REG, the following transformation would
3023 increase the cost of the insn by replacing a simple REG
3024 with (plus (reg sp) CST). So try only when plus_src
3025 comes from old_set proper, not REG_NOTES. */
3026 else if (SET_SRC (old_set) == plus_src)
3028 new_body = old_body;
3031 new_body = copy_insn (old_body);
3032 if (REG_NOTES (insn))
3033 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3035 PATTERN (insn) = new_body;
3036 old_set = single_set (insn);
3038 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3039 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3045 /* This can't have an effect on elimination offsets, so skip right
3051 /* Determine the effects of this insn on elimination offsets. */
3052 elimination_effects (old_body, 0);
3054 /* Eliminate all eliminable registers occurring in operands that
3055 can be handled by reload. */
3056 extract_insn (insn);
3057 for (i = 0; i < recog_data.n_operands; i++)
3059 orig_operand[i] = recog_data.operand[i];
3060 substed_operand[i] = recog_data.operand[i];
3062 /* For an asm statement, every operand is eliminable. */
3063 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3065 /* Check for setting a register that we know about. */
3066 if (recog_data.operand_type[i] != OP_IN
3067 && REG_P (orig_operand[i]))
3069 /* If we are assigning to a register that can be eliminated, it
3070 must be as part of a PARALLEL, since the code above handles
3071 single SETs. We must indicate that we can no longer
3072 eliminate this reg. */
3073 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3075 if (ep->from_rtx == orig_operand[i])
3076 ep->can_eliminate = 0;
3079 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3080 replace ? insn : NULL_RTX);
3081 if (substed_operand[i] != orig_operand[i])
3083 /* Terminate the search in check_eliminable_occurrences at
3085 *recog_data.operand_loc[i] = 0;
3087 /* If an output operand changed from a REG to a MEM and INSN is an
3088 insn, write a CLOBBER insn. */
3089 if (recog_data.operand_type[i] != OP_IN
3090 && REG_P (orig_operand[i])
3091 && MEM_P (substed_operand[i])
3093 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3098 for (i = 0; i < recog_data.n_dups; i++)
3099 *recog_data.dup_loc[i]
3100 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3102 /* If any eliminable remain, they aren't eliminable anymore. */
3103 check_eliminable_occurrences (old_body);
3105 /* Substitute the operands; the new values are in the substed_operand
3107 for (i = 0; i < recog_data.n_operands; i++)
3108 *recog_data.operand_loc[i] = substed_operand[i];
3109 for (i = 0; i < recog_data.n_dups; i++)
3110 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3112 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3113 re-recognize the insn. We do this in case we had a simple addition
3114 but now can do this as a load-address. This saves an insn in this
3116 If re-recognition fails, the old insn code number will still be used,
3117 and some register operands may have changed into PLUS expressions.
3118 These will be handled by find_reloads by loading them into a register
3123 /* If we aren't replacing things permanently and we changed something,
3124 make another copy to ensure that all the RTL is new. Otherwise
3125 things can go wrong if find_reload swaps commutative operands
3126 and one is inside RTL that has been copied while the other is not. */
3127 new_body = old_body;
3130 new_body = copy_insn (old_body);
3131 if (REG_NOTES (insn))
3132 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3134 PATTERN (insn) = new_body;
3136 /* If we had a move insn but now we don't, rerecognize it. This will
3137 cause spurious re-recognition if the old move had a PARALLEL since
3138 the new one still will, but we can't call single_set without
3139 having put NEW_BODY into the insn and the re-recognition won't
3140 hurt in this rare case. */
3141 /* ??? Why this huge if statement - why don't we just rerecognize the
3145 && ((REG_P (SET_SRC (old_set))
3146 && (GET_CODE (new_body) != SET
3147 || !REG_P (SET_SRC (new_body))))
3148 /* If this was a load from or store to memory, compare
3149 the MEM in recog_data.operand to the one in the insn.
3150 If they are not equal, then rerecognize the insn. */
3152 && ((MEM_P (SET_SRC (old_set))
3153 && SET_SRC (old_set) != recog_data.operand[1])
3154 || (MEM_P (SET_DEST (old_set))
3155 && SET_DEST (old_set) != recog_data.operand[0])))
3156 /* If this was an add insn before, rerecognize. */
3157 || GET_CODE (SET_SRC (old_set)) == PLUS))
3159 int new_icode = recog (PATTERN (insn), insn, 0);
3161 INSN_CODE (insn) = icode;
3165 /* Restore the old body. If there were any changes to it, we made a copy
3166 of it while the changes were still in place, so we'll correctly return
3167 a modified insn below. */
3170 /* Restore the old body. */
3171 for (i = 0; i < recog_data.n_operands; i++)
3172 *recog_data.operand_loc[i] = orig_operand[i];
3173 for (i = 0; i < recog_data.n_dups; i++)
3174 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3177 /* Update all elimination pairs to reflect the status after the current
3178 insn. The changes we make were determined by the earlier call to
3179 elimination_effects.
3181 We also detect cases where register elimination cannot be done,
3182 namely, if a register would be both changed and referenced outside a MEM
3183 in the resulting insn since such an insn is often undefined and, even if
3184 not, we cannot know what meaning will be given to it. Note that it is
3185 valid to have a register used in an address in an insn that changes it
3186 (presumably with a pre- or post-increment or decrement).
3188 If anything changes, return nonzero. */
3190 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3192 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3193 ep->can_eliminate = 0;
3195 ep->ref_outside_mem = 0;
3197 if (ep->previous_offset != ep->offset)
3202 /* If we changed something, perform elimination in REG_NOTES. This is
3203 needed even when REPLACE is zero because a REG_DEAD note might refer
3204 to a register that we eliminate and could cause a different number
3205 of spill registers to be needed in the final reload pass than in
3207 if (val && REG_NOTES (insn) != 0)
3208 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3213 /* Loop through all elimination pairs.
3214 Recalculate the number not at initial offset.
3216 Compute the maximum offset (minimum offset if the stack does not
3217 grow downward) for each elimination pair. */
3220 update_eliminable_offsets (void)
3222 struct elim_table *ep;
3224 num_not_at_initial_offset = 0;
3225 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3227 ep->previous_offset = ep->offset;
3228 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3229 num_not_at_initial_offset++;
3233 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3234 replacement we currently believe is valid, mark it as not eliminable if X
3235 modifies DEST in any way other than by adding a constant integer to it.
3237 If DEST is the frame pointer, we do nothing because we assume that
3238 all assignments to the hard frame pointer are nonlocal gotos and are being
3239 done at a time when they are valid and do not disturb anything else.
3240 Some machines want to eliminate a fake argument pointer with either the
3241 frame or stack pointer. Assignments to the hard frame pointer must not
3242 prevent this elimination.
3244 Called via note_stores from reload before starting its passes to scan
3245 the insns of the function. */
3248 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3252 /* A SUBREG of a hard register here is just changing its mode. We should
3253 not see a SUBREG of an eliminable hard register, but check just in
3255 if (GET_CODE (dest) == SUBREG)
3256 dest = SUBREG_REG (dest);
3258 if (dest == hard_frame_pointer_rtx)
3261 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3262 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3263 && (GET_CODE (x) != SET
3264 || GET_CODE (SET_SRC (x)) != PLUS
3265 || XEXP (SET_SRC (x), 0) != dest
3266 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3268 reg_eliminate[i].can_eliminate_previous
3269 = reg_eliminate[i].can_eliminate = 0;
3274 /* Verify that the initial elimination offsets did not change since the
3275 last call to set_initial_elim_offsets. This is used to catch cases
3276 where something illegal happened during reload_as_needed that could
3277 cause incorrect code to be generated if we did not check for it. */
3280 verify_initial_elim_offsets (void)
3284 #ifdef ELIMINABLE_REGS
3285 struct elim_table *ep;
3287 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3289 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3290 gcc_assert (t == ep->initial_offset);
3293 INITIAL_FRAME_POINTER_OFFSET (t);
3294 gcc_assert (t == reg_eliminate[0].initial_offset);
3298 /* Reset all offsets on eliminable registers to their initial values. */
3301 set_initial_elim_offsets (void)
3303 struct elim_table *ep = reg_eliminate;
3305 #ifdef ELIMINABLE_REGS
3306 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3308 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3309 ep->previous_offset = ep->offset = ep->initial_offset;
3312 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3313 ep->previous_offset = ep->offset = ep->initial_offset;
3316 num_not_at_initial_offset = 0;
3319 /* Initialize the known label offsets.
3320 Set a known offset for each forced label to be at the initial offset
3321 of each elimination. We do this because we assume that all
3322 computed jumps occur from a location where each elimination is
3323 at its initial offset.
3324 For all other labels, show that we don't know the offsets. */
3327 set_initial_label_offsets (void)
3330 memset (offsets_known_at, 0, num_labels);
3332 for (x = forced_labels; x; x = XEXP (x, 1))
3334 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3337 /* Set all elimination offsets to the known values for the code label given
3341 set_offsets_for_label (rtx insn)
3344 int label_nr = CODE_LABEL_NUMBER (insn);
3345 struct elim_table *ep;
3347 num_not_at_initial_offset = 0;
3348 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3350 ep->offset = ep->previous_offset
3351 = offsets_at[label_nr - first_label_num][i];
3352 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3353 num_not_at_initial_offset++;
3357 /* See if anything that happened changes which eliminations are valid.
3358 For example, on the SPARC, whether or not the frame pointer can
3359 be eliminated can depend on what registers have been used. We need
3360 not check some conditions again (such as flag_omit_frame_pointer)
3361 since they can't have changed. */
3364 update_eliminables (HARD_REG_SET *pset)
3366 int previous_frame_pointer_needed = frame_pointer_needed;
3367 struct elim_table *ep;
3369 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3370 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3371 #ifdef ELIMINABLE_REGS
3372 || ! CAN_ELIMINATE (ep->from, ep->to)
3375 ep->can_eliminate = 0;
3377 /* Look for the case where we have discovered that we can't replace
3378 register A with register B and that means that we will now be
3379 trying to replace register A with register C. This means we can
3380 no longer replace register C with register B and we need to disable
3381 such an elimination, if it exists. This occurs often with A == ap,
3382 B == sp, and C == fp. */
3384 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3386 struct elim_table *op;
3389 if (! ep->can_eliminate && ep->can_eliminate_previous)
3391 /* Find the current elimination for ep->from, if there is a
3393 for (op = reg_eliminate;
3394 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3395 if (op->from == ep->from && op->can_eliminate)
3401 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3403 for (op = reg_eliminate;
3404 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3405 if (op->from == new_to && op->to == ep->to)
3406 op->can_eliminate = 0;
3410 /* See if any registers that we thought we could eliminate the previous
3411 time are no longer eliminable. If so, something has changed and we
3412 must spill the register. Also, recompute the number of eliminable
3413 registers and see if the frame pointer is needed; it is if there is
3414 no elimination of the frame pointer that we can perform. */
3416 frame_pointer_needed = 1;
3417 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3419 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3420 && ep->to != HARD_FRAME_POINTER_REGNUM)
3421 frame_pointer_needed = 0;
3423 if (! ep->can_eliminate && ep->can_eliminate_previous)
3425 ep->can_eliminate_previous = 0;
3426 SET_HARD_REG_BIT (*pset, ep->from);
3431 /* If we didn't need a frame pointer last time, but we do now, spill
3432 the hard frame pointer. */
3433 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3434 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3437 /* Initialize the table of registers to eliminate. */
3440 init_elim_table (void)
3442 struct elim_table *ep;
3443 #ifdef ELIMINABLE_REGS
3444 const struct elim_table_1 *ep1;
3448 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3450 /* Does this function require a frame pointer? */
3452 frame_pointer_needed = (! flag_omit_frame_pointer
3453 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3454 and restore sp for alloca. So we can't eliminate
3455 the frame pointer in that case. At some point,
3456 we should improve this by emitting the
3457 sp-adjusting insns for this case. */
3458 || (current_function_calls_alloca
3459 && EXIT_IGNORE_STACK)
3460 || FRAME_POINTER_REQUIRED);
3464 #ifdef ELIMINABLE_REGS
3465 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3466 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3468 ep->from = ep1->from;
3470 ep->can_eliminate = ep->can_eliminate_previous
3471 = (CAN_ELIMINATE (ep->from, ep->to)
3472 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3475 reg_eliminate[0].from = reg_eliminate_1[0].from;
3476 reg_eliminate[0].to = reg_eliminate_1[0].to;
3477 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3478 = ! frame_pointer_needed;
3481 /* Count the number of eliminable registers and build the FROM and TO
3482 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3483 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3484 We depend on this. */
3485 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3487 num_eliminable += ep->can_eliminate;
3488 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3489 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3493 /* Kick all pseudos out of hard register REGNO.
3495 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3496 because we found we can't eliminate some register. In the case, no pseudos
3497 are allowed to be in the register, even if they are only in a block that
3498 doesn't require spill registers, unlike the case when we are spilling this
3499 hard reg to produce another spill register.
3501 Return nonzero if any pseudos needed to be kicked out. */
3504 spill_hard_reg (unsigned int regno, int cant_eliminate)
3510 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3511 regs_ever_live[regno] = 1;
3514 /* Spill every pseudo reg that was allocated to this reg
3515 or to something that overlaps this reg. */
3517 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3518 if (reg_renumber[i] >= 0
3519 && (unsigned int) reg_renumber[i] <= regno
3520 && ((unsigned int) reg_renumber[i]
3521 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3522 [PSEUDO_REGNO_MODE (i)]
3524 SET_REGNO_REG_SET (&spilled_pseudos, i);
3527 /* After find_reload_regs has been run for all insn that need reloads,
3528 and/or spill_hard_regs was called, this function is used to actually
3529 spill pseudo registers and try to reallocate them. It also sets up the
3530 spill_regs array for use by choose_reload_regs. */
3533 finish_spills (int global)
3535 struct insn_chain *chain;
3536 int something_changed = 0;
3538 reg_set_iterator rsi;
3540 /* Build the spill_regs array for the function. */
3541 /* If there are some registers still to eliminate and one of the spill regs
3542 wasn't ever used before, additional stack space may have to be
3543 allocated to store this register. Thus, we may have changed the offset
3544 between the stack and frame pointers, so mark that something has changed.
3546 One might think that we need only set VAL to 1 if this is a call-used
3547 register. However, the set of registers that must be saved by the
3548 prologue is not identical to the call-used set. For example, the
3549 register used by the call insn for the return PC is a call-used register,
3550 but must be saved by the prologue. */
3553 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3554 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3556 spill_reg_order[i] = n_spills;
3557 spill_regs[n_spills++] = i;
3558 if (num_eliminable && ! regs_ever_live[i])
3559 something_changed = 1;
3560 regs_ever_live[i] = 1;
3563 spill_reg_order[i] = -1;
3565 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3567 /* Record the current hard register the pseudo is allocated to in
3568 pseudo_previous_regs so we avoid reallocating it to the same
3569 hard reg in a later pass. */
3570 gcc_assert (reg_renumber[i] >= 0);
3572 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3573 /* Mark it as no longer having a hard register home. */
3574 reg_renumber[i] = -1;
3575 /* We will need to scan everything again. */
3576 something_changed = 1;
3579 /* Retry global register allocation if possible. */
3582 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3583 /* For every insn that needs reloads, set the registers used as spill
3584 regs in pseudo_forbidden_regs for every pseudo live across the
3586 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3588 EXECUTE_IF_SET_IN_REG_SET
3589 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3591 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3592 chain->used_spill_regs);
3594 EXECUTE_IF_SET_IN_REG_SET
3595 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3597 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3598 chain->used_spill_regs);
3602 /* Retry allocating the spilled pseudos. For each reg, merge the
3603 various reg sets that indicate which hard regs can't be used,
3604 and call retry_global_alloc.
3605 We change spill_pseudos here to only contain pseudos that did not
3606 get a new hard register. */
3607 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3608 if (reg_old_renumber[i] != reg_renumber[i])
3610 HARD_REG_SET forbidden;
3611 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3612 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3613 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3614 retry_global_alloc (i, forbidden);
3615 if (reg_renumber[i] >= 0)
3616 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3620 /* Fix up the register information in the insn chain.
3621 This involves deleting those of the spilled pseudos which did not get
3622 a new hard register home from the live_{before,after} sets. */
3623 for (chain = reload_insn_chain; chain; chain = chain->next)
3625 HARD_REG_SET used_by_pseudos;
3626 HARD_REG_SET used_by_pseudos2;
3628 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3629 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3631 /* Mark any unallocated hard regs as available for spills. That
3632 makes inheritance work somewhat better. */
3633 if (chain->need_reload)
3635 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3636 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3637 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3639 /* Save the old value for the sanity test below. */
3640 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3642 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3643 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3644 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3645 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3647 /* Make sure we only enlarge the set. */
3648 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3654 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3655 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3657 int regno = reg_renumber[i];
3658 if (reg_old_renumber[i] == regno)
3661 alter_reg (i, reg_old_renumber[i]);
3662 reg_old_renumber[i] = regno;
3666 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3668 fprintf (dump_file, " Register %d now in %d.\n\n",
3669 i, reg_renumber[i]);
3673 return something_changed;
3676 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3679 scan_paradoxical_subregs (rtx x)
3683 enum rtx_code code = GET_CODE (x);
3693 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3701 if (REG_P (SUBREG_REG (x))
3702 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3703 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3704 = GET_MODE_SIZE (GET_MODE (x));
3711 fmt = GET_RTX_FORMAT (code);
3712 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3715 scan_paradoxical_subregs (XEXP (x, i));
3716 else if (fmt[i] == 'E')
3719 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3720 scan_paradoxical_subregs (XVECEXP (x, i, j));
3725 /* Reload pseudo-registers into hard regs around each insn as needed.
3726 Additional register load insns are output before the insn that needs it
3727 and perhaps store insns after insns that modify the reloaded pseudo reg.
3729 reg_last_reload_reg and reg_reloaded_contents keep track of
3730 which registers are already available in reload registers.
3731 We update these for the reloads that we perform,
3732 as the insns are scanned. */
3735 reload_as_needed (int live_known)
3737 struct insn_chain *chain;
3738 #if defined (AUTO_INC_DEC)
3743 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3744 memset (spill_reg_store, 0, sizeof spill_reg_store);
3745 reg_last_reload_reg = xcalloc (max_regno, sizeof (rtx));
3746 reg_has_output_reload = xmalloc (max_regno);
3747 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3748 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3750 set_initial_elim_offsets ();
3752 for (chain = reload_insn_chain; chain; chain = chain->next)
3755 rtx insn = chain->insn;
3756 rtx old_next = NEXT_INSN (insn);
3758 /* If we pass a label, copy the offsets from the label information
3759 into the current offsets of each elimination. */
3761 set_offsets_for_label (insn);
3763 else if (INSN_P (insn))
3765 rtx oldpat = copy_rtx (PATTERN (insn));
3767 /* If this is a USE and CLOBBER of a MEM, ensure that any
3768 references to eliminable registers have been removed. */
3770 if ((GET_CODE (PATTERN (insn)) == USE
3771 || GET_CODE (PATTERN (insn)) == CLOBBER)
3772 && MEM_P (XEXP (PATTERN (insn), 0)))
3773 XEXP (XEXP (PATTERN (insn), 0), 0)
3774 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3775 GET_MODE (XEXP (PATTERN (insn), 0)),
3778 /* If we need to do register elimination processing, do so.
3779 This might delete the insn, in which case we are done. */
3780 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3782 eliminate_regs_in_insn (insn, 1);
3785 update_eliminable_offsets ();
3790 /* If need_elim is nonzero but need_reload is zero, one might think
3791 that we could simply set n_reloads to 0. However, find_reloads
3792 could have done some manipulation of the insn (such as swapping
3793 commutative operands), and these manipulations are lost during
3794 the first pass for every insn that needs register elimination.
3795 So the actions of find_reloads must be redone here. */
3797 if (! chain->need_elim && ! chain->need_reload
3798 && ! chain->need_operand_change)
3800 /* First find the pseudo regs that must be reloaded for this insn.
3801 This info is returned in the tables reload_... (see reload.h).
3802 Also modify the body of INSN by substituting RELOAD
3803 rtx's for those pseudo regs. */
3806 memset (reg_has_output_reload, 0, max_regno);
3807 CLEAR_HARD_REG_SET (reg_is_output_reload);
3809 find_reloads (insn, 1, spill_indirect_levels, live_known,
3815 rtx next = NEXT_INSN (insn);
3818 prev = PREV_INSN (insn);
3820 /* Now compute which reload regs to reload them into. Perhaps
3821 reusing reload regs from previous insns, or else output
3822 load insns to reload them. Maybe output store insns too.
3823 Record the choices of reload reg in reload_reg_rtx. */
3824 choose_reload_regs (chain);
3826 /* Merge any reloads that we didn't combine for fear of
3827 increasing the number of spill registers needed but now
3828 discover can be safely merged. */
3829 if (SMALL_REGISTER_CLASSES)
3830 merge_assigned_reloads (insn);
3832 /* Generate the insns to reload operands into or out of
3833 their reload regs. */
3834 emit_reload_insns (chain);
3836 /* Substitute the chosen reload regs from reload_reg_rtx
3837 into the insn's body (or perhaps into the bodies of other
3838 load and store insn that we just made for reloading
3839 and that we moved the structure into). */
3840 subst_reloads (insn);
3842 /* If this was an ASM, make sure that all the reload insns
3843 we have generated are valid. If not, give an error
3846 if (asm_noperands (PATTERN (insn)) >= 0)
3847 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3848 if (p != insn && INSN_P (p)
3849 && GET_CODE (PATTERN (p)) != USE
3850 && (recog_memoized (p) < 0
3851 || (extract_insn (p), ! constrain_operands (1))))
3853 error_for_asm (insn,
3854 "%<asm%> operand requires "
3855 "impossible reload");
3860 if (num_eliminable && chain->need_elim)
3861 update_eliminable_offsets ();
3863 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3864 is no longer validly lying around to save a future reload.
3865 Note that this does not detect pseudos that were reloaded
3866 for this insn in order to be stored in
3867 (obeying register constraints). That is correct; such reload
3868 registers ARE still valid. */
3869 note_stores (oldpat, forget_old_reloads_1, NULL);
3871 /* There may have been CLOBBER insns placed after INSN. So scan
3872 between INSN and NEXT and use them to forget old reloads. */
3873 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3874 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
3875 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3878 /* Likewise for regs altered by auto-increment in this insn.
3879 REG_INC notes have been changed by reloading:
3880 find_reloads_address_1 records substitutions for them,
3881 which have been performed by subst_reloads above. */
3882 for (i = n_reloads - 1; i >= 0; i--)
3884 rtx in_reg = rld[i].in_reg;
3887 enum rtx_code code = GET_CODE (in_reg);
3888 /* PRE_INC / PRE_DEC will have the reload register ending up
3889 with the same value as the stack slot, but that doesn't
3890 hold true for POST_INC / POST_DEC. Either we have to
3891 convert the memory access to a true POST_INC / POST_DEC,
3892 or we can't use the reload register for inheritance. */
3893 if ((code == POST_INC || code == POST_DEC)
3894 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3895 REGNO (rld[i].reg_rtx))
3896 /* Make sure it is the inc/dec pseudo, and not
3897 some other (e.g. output operand) pseudo. */
3898 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3899 == REGNO (XEXP (in_reg, 0))))
3902 rtx reload_reg = rld[i].reg_rtx;
3903 enum machine_mode mode = GET_MODE (reload_reg);
3907 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3909 /* We really want to ignore REG_INC notes here, so
3910 use PATTERN (p) as argument to reg_set_p . */
3911 if (reg_set_p (reload_reg, PATTERN (p)))
3913 n = count_occurrences (PATTERN (p), reload_reg, 0);
3918 n = validate_replace_rtx (reload_reg,
3919 gen_rtx_fmt_e (code,
3924 /* We must also verify that the constraints
3925 are met after the replacement. */
3928 n = constrain_operands (1);
3932 /* If the constraints were not met, then
3933 undo the replacement. */
3936 validate_replace_rtx (gen_rtx_fmt_e (code,
3949 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3951 /* Mark this as having an output reload so that the
3952 REG_INC processing code below won't invalidate
3953 the reload for inheritance. */
3954 SET_HARD_REG_BIT (reg_is_output_reload,
3955 REGNO (reload_reg));
3956 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3959 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3962 else if ((code == PRE_INC || code == PRE_DEC)
3963 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3964 REGNO (rld[i].reg_rtx))
3965 /* Make sure it is the inc/dec pseudo, and not
3966 some other (e.g. output operand) pseudo. */
3967 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3968 == REGNO (XEXP (in_reg, 0))))
3970 SET_HARD_REG_BIT (reg_is_output_reload,
3971 REGNO (rld[i].reg_rtx));
3972 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3976 /* If a pseudo that got a hard register is auto-incremented,
3977 we must purge records of copying it into pseudos without
3979 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3980 if (REG_NOTE_KIND (x) == REG_INC)
3982 /* See if this pseudo reg was reloaded in this insn.
3983 If so, its last-reload info is still valid
3984 because it is based on this insn's reload. */
3985 for (i = 0; i < n_reloads; i++)
3986 if (rld[i].out == XEXP (x, 0))
3990 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
3994 /* A reload reg's contents are unknown after a label. */
3996 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3998 /* Don't assume a reload reg is still good after a call insn
3999 if it is a call-used reg, or if it contains a value that will
4000 be partially clobbered by the call. */
4001 else if (CALL_P (insn))
4003 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4004 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4009 free (reg_last_reload_reg);
4010 free (reg_has_output_reload);
4013 /* Discard all record of any value reloaded from X,
4014 or reloaded in X from someplace else;
4015 unless X is an output reload reg of the current insn.
4017 X may be a hard reg (the reload reg)
4018 or it may be a pseudo reg that was reloaded from. */
4021 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4022 void *data ATTRIBUTE_UNUSED)
4027 /* note_stores does give us subregs of hard regs,
4028 subreg_regno_offset will abort if it is not a hard reg. */
4029 while (GET_CODE (x) == SUBREG)
4031 /* We ignore the subreg offset when calculating the regno,
4032 because we are using the entire underlying hard register
4042 if (regno >= FIRST_PSEUDO_REGISTER)
4048 nr = hard_regno_nregs[regno][GET_MODE (x)];
4049 /* Storing into a spilled-reg invalidates its contents.
4050 This can happen if a block-local pseudo is allocated to that reg
4051 and it wasn't spilled because this block's total need is 0.
4052 Then some insn might have an optional reload and use this reg. */
4053 for (i = 0; i < nr; i++)
4054 /* But don't do this if the reg actually serves as an output
4055 reload reg in the current instruction. */
4057 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4059 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4060 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4061 spill_reg_store[regno + i] = 0;
4065 /* Since value of X has changed,
4066 forget any value previously copied from it. */
4069 /* But don't forget a copy if this is the output reload
4070 that establishes the copy's validity. */
4071 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4072 reg_last_reload_reg[regno + nr] = 0;
4075 /* The following HARD_REG_SETs indicate when each hard register is
4076 used for a reload of various parts of the current insn. */
4078 /* If reg is unavailable for all reloads. */
4079 static HARD_REG_SET reload_reg_unavailable;
4080 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4081 static HARD_REG_SET reload_reg_used;
4082 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4083 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4084 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4085 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4086 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4087 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4088 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4089 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4090 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4091 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4092 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4093 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4094 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4095 static HARD_REG_SET reload_reg_used_in_op_addr;
4096 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4097 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4098 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4099 static HARD_REG_SET reload_reg_used_in_insn;
4100 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4101 static HARD_REG_SET reload_reg_used_in_other_addr;
4103 /* If reg is in use as a reload reg for any sort of reload. */
4104 static HARD_REG_SET reload_reg_used_at_all;
4106 /* If reg is use as an inherited reload. We just mark the first register
4108 static HARD_REG_SET reload_reg_used_for_inherit;
4110 /* Records which hard regs are used in any way, either as explicit use or
4111 by being allocated to a pseudo during any point of the current insn. */
4112 static HARD_REG_SET reg_used_in_insn;
4114 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4115 TYPE. MODE is used to indicate how many consecutive regs are
4119 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4120 enum machine_mode mode)
4122 unsigned int nregs = hard_regno_nregs[regno][mode];
4125 for (i = regno; i < nregs + regno; i++)
4130 SET_HARD_REG_BIT (reload_reg_used, i);
4133 case RELOAD_FOR_INPUT_ADDRESS:
4134 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4137 case RELOAD_FOR_INPADDR_ADDRESS:
4138 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4141 case RELOAD_FOR_OUTPUT_ADDRESS:
4142 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4145 case RELOAD_FOR_OUTADDR_ADDRESS:
4146 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4149 case RELOAD_FOR_OPERAND_ADDRESS:
4150 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4153 case RELOAD_FOR_OPADDR_ADDR:
4154 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4157 case RELOAD_FOR_OTHER_ADDRESS:
4158 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4161 case RELOAD_FOR_INPUT:
4162 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4165 case RELOAD_FOR_OUTPUT:
4166 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4169 case RELOAD_FOR_INSN:
4170 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4174 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4178 /* Similarly, but show REGNO is no longer in use for a reload. */
4181 clear_reload_reg_in_use (unsigned int regno, int opnum,
4182 enum reload_type type, enum machine_mode mode)
4184 unsigned int nregs = hard_regno_nregs[regno][mode];
4185 unsigned int start_regno, end_regno, r;
4187 /* A complication is that for some reload types, inheritance might
4188 allow multiple reloads of the same types to share a reload register.
4189 We set check_opnum if we have to check only reloads with the same
4190 operand number, and check_any if we have to check all reloads. */
4191 int check_opnum = 0;
4193 HARD_REG_SET *used_in_set;
4198 used_in_set = &reload_reg_used;
4201 case RELOAD_FOR_INPUT_ADDRESS:
4202 used_in_set = &reload_reg_used_in_input_addr[opnum];
4205 case RELOAD_FOR_INPADDR_ADDRESS:
4207 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4210 case RELOAD_FOR_OUTPUT_ADDRESS:
4211 used_in_set = &reload_reg_used_in_output_addr[opnum];
4214 case RELOAD_FOR_OUTADDR_ADDRESS:
4216 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4219 case RELOAD_FOR_OPERAND_ADDRESS:
4220 used_in_set = &reload_reg_used_in_op_addr;
4223 case RELOAD_FOR_OPADDR_ADDR:
4225 used_in_set = &reload_reg_used_in_op_addr_reload;
4228 case RELOAD_FOR_OTHER_ADDRESS:
4229 used_in_set = &reload_reg_used_in_other_addr;
4233 case RELOAD_FOR_INPUT:
4234 used_in_set = &reload_reg_used_in_input[opnum];
4237 case RELOAD_FOR_OUTPUT:
4238 used_in_set = &reload_reg_used_in_output[opnum];
4241 case RELOAD_FOR_INSN:
4242 used_in_set = &reload_reg_used_in_insn;
4247 /* We resolve conflicts with remaining reloads of the same type by
4248 excluding the intervals of reload registers by them from the
4249 interval of freed reload registers. Since we only keep track of
4250 one set of interval bounds, we might have to exclude somewhat
4251 more than what would be necessary if we used a HARD_REG_SET here.
4252 But this should only happen very infrequently, so there should
4253 be no reason to worry about it. */
4255 start_regno = regno;
4256 end_regno = regno + nregs;
4257 if (check_opnum || check_any)
4259 for (i = n_reloads - 1; i >= 0; i--)
4261 if (rld[i].when_needed == type
4262 && (check_any || rld[i].opnum == opnum)
4265 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4266 unsigned int conflict_end
4268 + hard_regno_nregs[conflict_start][rld[i].mode]);
4270 /* If there is an overlap with the first to-be-freed register,
4271 adjust the interval start. */
4272 if (conflict_start <= start_regno && conflict_end > start_regno)
4273 start_regno = conflict_end;
4274 /* Otherwise, if there is a conflict with one of the other
4275 to-be-freed registers, adjust the interval end. */
4276 if (conflict_start > start_regno && conflict_start < end_regno)
4277 end_regno = conflict_start;
4282 for (r = start_regno; r < end_regno; r++)
4283 CLEAR_HARD_REG_BIT (*used_in_set, r);
4286 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4287 specified by OPNUM and TYPE. */
4290 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4294 /* In use for a RELOAD_OTHER means it's not available for anything. */
4295 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4296 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4302 /* In use for anything means we can't use it for RELOAD_OTHER. */
4303 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4304 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4305 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4306 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4309 for (i = 0; i < reload_n_operands; i++)
4310 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4311 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4312 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4313 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4314 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4315 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4320 case RELOAD_FOR_INPUT:
4321 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4322 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4325 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4328 /* If it is used for some other input, can't use it. */
4329 for (i = 0; i < reload_n_operands; i++)
4330 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4333 /* If it is used in a later operand's address, can't use it. */
4334 for (i = opnum + 1; i < reload_n_operands; i++)
4335 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4336 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4341 case RELOAD_FOR_INPUT_ADDRESS:
4342 /* Can't use a register if it is used for an input address for this
4343 operand or used as an input in an earlier one. */
4344 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4345 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4348 for (i = 0; i < opnum; i++)
4349 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4354 case RELOAD_FOR_INPADDR_ADDRESS:
4355 /* Can't use a register if it is used for an input address
4356 for this operand or used as an input in an earlier
4358 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4361 for (i = 0; i < opnum; i++)
4362 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4367 case RELOAD_FOR_OUTPUT_ADDRESS:
4368 /* Can't use a register if it is used for an output address for this
4369 operand or used as an output in this or a later operand. Note
4370 that multiple output operands are emitted in reverse order, so
4371 the conflicting ones are those with lower indices. */
4372 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4375 for (i = 0; i <= opnum; i++)
4376 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4381 case RELOAD_FOR_OUTADDR_ADDRESS:
4382 /* Can't use a register if it is used for an output address
4383 for this operand or used as an output in this or a
4384 later operand. Note that multiple output operands are
4385 emitted in reverse order, so the conflicting ones are
4386 those with lower indices. */
4387 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4390 for (i = 0; i <= opnum; i++)
4391 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4396 case RELOAD_FOR_OPERAND_ADDRESS:
4397 for (i = 0; i < reload_n_operands; i++)
4398 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4401 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4402 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4404 case RELOAD_FOR_OPADDR_ADDR:
4405 for (i = 0; i < reload_n_operands; i++)
4406 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4409 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4411 case RELOAD_FOR_OUTPUT:
4412 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4413 outputs, or an operand address for this or an earlier output.
4414 Note that multiple output operands are emitted in reverse order,
4415 so the conflicting ones are those with higher indices. */
4416 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4419 for (i = 0; i < reload_n_operands; i++)
4420 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4423 for (i = opnum; i < reload_n_operands; i++)
4424 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4425 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4430 case RELOAD_FOR_INSN:
4431 for (i = 0; i < reload_n_operands; i++)
4432 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4433 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4436 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4437 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4439 case RELOAD_FOR_OTHER_ADDRESS:
4440 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4447 /* Return 1 if the value in reload reg REGNO, as used by a reload
4448 needed for the part of the insn specified by OPNUM and TYPE,
4449 is still available in REGNO at the end of the insn.
4451 We can assume that the reload reg was already tested for availability
4452 at the time it is needed, and we should not check this again,
4453 in case the reg has already been marked in use. */
4456 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4463 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4464 its value must reach the end. */
4467 /* If this use is for part of the insn,
4468 its value reaches if no subsequent part uses the same register.
4469 Just like the above function, don't try to do this with lots
4472 case RELOAD_FOR_OTHER_ADDRESS:
4473 /* Here we check for everything else, since these don't conflict
4474 with anything else and everything comes later. */
4476 for (i = 0; i < reload_n_operands; i++)
4477 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4478 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4479 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4480 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4481 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4482 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4485 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4486 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4487 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4488 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4490 case RELOAD_FOR_INPUT_ADDRESS:
4491 case RELOAD_FOR_INPADDR_ADDRESS:
4492 /* Similar, except that we check only for this and subsequent inputs
4493 and the address of only subsequent inputs and we do not need
4494 to check for RELOAD_OTHER objects since they are known not to
4497 for (i = opnum; i < reload_n_operands; i++)
4498 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4501 for (i = opnum + 1; i < reload_n_operands; i++)
4502 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4503 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4506 for (i = 0; i < reload_n_operands; i++)
4507 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4508 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4509 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4512 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4515 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4516 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4517 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4519 case RELOAD_FOR_INPUT:
4520 /* Similar to input address, except we start at the next operand for
4521 both input and input address and we do not check for
4522 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4525 for (i = opnum + 1; i < reload_n_operands; i++)
4526 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4527 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4528 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4531 /* ... fall through ... */
4533 case RELOAD_FOR_OPERAND_ADDRESS:
4534 /* Check outputs and their addresses. */
4536 for (i = 0; i < reload_n_operands; i++)
4537 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4538 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4539 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4542 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4544 case RELOAD_FOR_OPADDR_ADDR:
4545 for (i = 0; i < reload_n_operands; i++)
4546 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4547 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4548 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4551 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4552 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4553 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4555 case RELOAD_FOR_INSN:
4556 /* These conflict with other outputs with RELOAD_OTHER. So
4557 we need only check for output addresses. */
4559 opnum = reload_n_operands;
4561 /* ... fall through ... */
4563 case RELOAD_FOR_OUTPUT:
4564 case RELOAD_FOR_OUTPUT_ADDRESS:
4565 case RELOAD_FOR_OUTADDR_ADDRESS:
4566 /* We already know these can't conflict with a later output. So the
4567 only thing to check are later output addresses.
4568 Note that multiple output operands are emitted in reverse order,
4569 so the conflicting ones are those with lower indices. */
4570 for (i = 0; i < opnum; i++)
4571 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4572 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4582 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4585 This function uses the same algorithm as reload_reg_free_p above. */
4588 reloads_conflict (int r1, int r2)
4590 enum reload_type r1_type = rld[r1].when_needed;
4591 enum reload_type r2_type = rld[r2].when_needed;
4592 int r1_opnum = rld[r1].opnum;
4593 int r2_opnum = rld[r2].opnum;
4595 /* RELOAD_OTHER conflicts with everything. */
4596 if (r2_type == RELOAD_OTHER)
4599 /* Otherwise, check conflicts differently for each type. */
4603 case RELOAD_FOR_INPUT:
4604 return (r2_type == RELOAD_FOR_INSN
4605 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4606 || r2_type == RELOAD_FOR_OPADDR_ADDR
4607 || r2_type == RELOAD_FOR_INPUT
4608 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4609 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4610 && r2_opnum > r1_opnum));
4612 case RELOAD_FOR_INPUT_ADDRESS:
4613 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4614 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4616 case RELOAD_FOR_INPADDR_ADDRESS:
4617 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4618 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4620 case RELOAD_FOR_OUTPUT_ADDRESS:
4621 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4622 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4624 case RELOAD_FOR_OUTADDR_ADDRESS:
4625 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4626 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4628 case RELOAD_FOR_OPERAND_ADDRESS:
4629 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4630 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4632 case RELOAD_FOR_OPADDR_ADDR:
4633 return (r2_type == RELOAD_FOR_INPUT
4634 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4636 case RELOAD_FOR_OUTPUT:
4637 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4638 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4639 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4640 && r2_opnum >= r1_opnum));
4642 case RELOAD_FOR_INSN:
4643 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4644 || r2_type == RELOAD_FOR_INSN
4645 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4647 case RELOAD_FOR_OTHER_ADDRESS:
4648 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4658 /* Indexed by reload number, 1 if incoming value
4659 inherited from previous insns. */
4660 char reload_inherited[MAX_RELOADS];
4662 /* For an inherited reload, this is the insn the reload was inherited from,
4663 if we know it. Otherwise, this is 0. */
4664 rtx reload_inheritance_insn[MAX_RELOADS];
4666 /* If nonzero, this is a place to get the value of the reload,
4667 rather than using reload_in. */
4668 rtx reload_override_in[MAX_RELOADS];
4670 /* For each reload, the hard register number of the register used,
4671 or -1 if we did not need a register for this reload. */
4672 int reload_spill_index[MAX_RELOADS];
4674 /* Subroutine of free_for_value_p, used to check a single register.
4675 START_REGNO is the starting regno of the full reload register
4676 (possibly comprising multiple hard registers) that we are considering. */
4679 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4680 enum reload_type type, rtx value, rtx out,
4681 int reloadnum, int ignore_address_reloads)
4684 /* Set if we see an input reload that must not share its reload register
4685 with any new earlyclobber, but might otherwise share the reload
4686 register with an output or input-output reload. */
4687 int check_earlyclobber = 0;
4691 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4694 if (out == const0_rtx)
4700 /* We use some pseudo 'time' value to check if the lifetimes of the
4701 new register use would overlap with the one of a previous reload
4702 that is not read-only or uses a different value.
4703 The 'time' used doesn't have to be linear in any shape or form, just
4705 Some reload types use different 'buckets' for each operand.
4706 So there are MAX_RECOG_OPERANDS different time values for each
4708 We compute TIME1 as the time when the register for the prospective
4709 new reload ceases to be live, and TIME2 for each existing
4710 reload as the time when that the reload register of that reload
4712 Where there is little to be gained by exact lifetime calculations,
4713 we just make conservative assumptions, i.e. a longer lifetime;
4714 this is done in the 'default:' cases. */
4717 case RELOAD_FOR_OTHER_ADDRESS:
4718 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4719 time1 = copy ? 0 : 1;
4722 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4724 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4725 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4726 respectively, to the time values for these, we get distinct time
4727 values. To get distinct time values for each operand, we have to
4728 multiply opnum by at least three. We round that up to four because
4729 multiply by four is often cheaper. */
4730 case RELOAD_FOR_INPADDR_ADDRESS:
4731 time1 = opnum * 4 + 2;
4733 case RELOAD_FOR_INPUT_ADDRESS:
4734 time1 = opnum * 4 + 3;
4736 case RELOAD_FOR_INPUT:
4737 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4738 executes (inclusive). */
4739 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4741 case RELOAD_FOR_OPADDR_ADDR:
4743 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4744 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4746 case RELOAD_FOR_OPERAND_ADDRESS:
4747 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4749 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4751 case RELOAD_FOR_OUTADDR_ADDRESS:
4752 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4754 case RELOAD_FOR_OUTPUT_ADDRESS:
4755 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4758 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4761 for (i = 0; i < n_reloads; i++)
4763 rtx reg = rld[i].reg_rtx;
4764 if (reg && REG_P (reg)
4765 && ((unsigned) regno - true_regnum (reg)
4766 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
4769 rtx other_input = rld[i].in;
4771 /* If the other reload loads the same input value, that
4772 will not cause a conflict only if it's loading it into
4773 the same register. */
4774 if (true_regnum (reg) != start_regno)
4775 other_input = NULL_RTX;
4776 if (! other_input || ! rtx_equal_p (other_input, value)
4777 || rld[i].out || out)
4780 switch (rld[i].when_needed)
4782 case RELOAD_FOR_OTHER_ADDRESS:
4785 case RELOAD_FOR_INPADDR_ADDRESS:
4786 /* find_reloads makes sure that a
4787 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4788 by at most one - the first -
4789 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4790 address reload is inherited, the address address reload
4791 goes away, so we can ignore this conflict. */
4792 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4793 && ignore_address_reloads
4794 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4795 Then the address address is still needed to store
4796 back the new address. */
4797 && ! rld[reloadnum].out)
4799 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4800 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4802 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4803 && ignore_address_reloads
4804 /* Unless we are reloading an auto_inc expression. */
4805 && ! rld[reloadnum].out)
4807 time2 = rld[i].opnum * 4 + 2;
4809 case RELOAD_FOR_INPUT_ADDRESS:
4810 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4811 && ignore_address_reloads
4812 && ! rld[reloadnum].out)
4814 time2 = rld[i].opnum * 4 + 3;
4816 case RELOAD_FOR_INPUT:
4817 time2 = rld[i].opnum * 4 + 4;
4818 check_earlyclobber = 1;
4820 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4821 == MAX_RECOG_OPERAND * 4 */
4822 case RELOAD_FOR_OPADDR_ADDR:
4823 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4824 && ignore_address_reloads
4825 && ! rld[reloadnum].out)
4827 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4829 case RELOAD_FOR_OPERAND_ADDRESS:
4830 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4831 check_earlyclobber = 1;
4833 case RELOAD_FOR_INSN:
4834 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4836 case RELOAD_FOR_OUTPUT:
4837 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4838 instruction is executed. */
4839 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4841 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4842 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4844 case RELOAD_FOR_OUTADDR_ADDRESS:
4845 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4846 && ignore_address_reloads
4847 && ! rld[reloadnum].out)
4849 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4851 case RELOAD_FOR_OUTPUT_ADDRESS:
4852 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4855 /* If there is no conflict in the input part, handle this
4856 like an output reload. */
4857 if (! rld[i].in || rtx_equal_p (other_input, value))
4859 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4860 /* Earlyclobbered outputs must conflict with inputs. */
4861 if (earlyclobber_operand_p (rld[i].out))
4862 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4867 /* RELOAD_OTHER might be live beyond instruction execution,
4868 but this is not obvious when we set time2 = 1. So check
4869 here if there might be a problem with the new reload
4870 clobbering the register used by the RELOAD_OTHER. */
4878 && (! rld[i].in || rld[i].out
4879 || ! rtx_equal_p (other_input, value)))
4880 || (out && rld[reloadnum].out_reg
4881 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4887 /* Earlyclobbered outputs must conflict with inputs. */
4888 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4894 /* Return 1 if the value in reload reg REGNO, as used by a reload
4895 needed for the part of the insn specified by OPNUM and TYPE,
4896 may be used to load VALUE into it.
4898 MODE is the mode in which the register is used, this is needed to
4899 determine how many hard regs to test.
4901 Other read-only reloads with the same value do not conflict
4902 unless OUT is nonzero and these other reloads have to live while
4903 output reloads live.
4904 If OUT is CONST0_RTX, this is a special case: it means that the
4905 test should not be for using register REGNO as reload register, but
4906 for copying from register REGNO into the reload register.
4908 RELOADNUM is the number of the reload we want to load this value for;
4909 a reload does not conflict with itself.
4911 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4912 reloads that load an address for the very reload we are considering.
4914 The caller has to make sure that there is no conflict with the return
4918 free_for_value_p (int regno, enum machine_mode mode, int opnum,
4919 enum reload_type type, rtx value, rtx out, int reloadnum,
4920 int ignore_address_reloads)
4922 int nregs = hard_regno_nregs[regno][mode];
4924 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4925 value, out, reloadnum,
4926 ignore_address_reloads))
4931 /* Return nonzero if the rtx X is invariant over the current function. */
4932 /* ??? Actually, the places where we use this expect exactly what
4933 * is tested here, and not everything that is function invariant. In
4934 * particular, the frame pointer and arg pointer are special cased;
4935 * pic_offset_table_rtx is not, and this will cause aborts when we
4936 * go to spill these things to memory. */
4939 function_invariant_p (rtx x)
4943 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4945 if (GET_CODE (x) == PLUS
4946 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
4947 && CONSTANT_P (XEXP (x, 1)))
4952 /* Determine whether the reload reg X overlaps any rtx'es used for
4953 overriding inheritance. Return nonzero if so. */
4956 conflicts_with_override (rtx x)
4959 for (i = 0; i < n_reloads; i++)
4960 if (reload_override_in[i]
4961 && reg_overlap_mentioned_p (x, reload_override_in[i]))
4966 /* Give an error message saying we failed to find a reload for INSN,
4967 and clear out reload R. */
4969 failed_reload (rtx insn, int r)
4971 if (asm_noperands (PATTERN (insn)) < 0)
4972 /* It's the compiler's fault. */
4973 fatal_insn ("could not find a spill register", insn);
4975 /* It's the user's fault; the operand's mode and constraint
4976 don't match. Disable this reload so we don't crash in final. */
4977 error_for_asm (insn,
4978 "%<asm%> operand constraint incompatible with operand size");
4982 rld[r].optional = 1;
4983 rld[r].secondary_p = 1;
4986 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
4987 for reload R. If it's valid, get an rtx for it. Return nonzero if
4990 set_reload_reg (int i, int r)
4993 rtx reg = spill_reg_rtx[i];
4995 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
4996 spill_reg_rtx[i] = reg
4997 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
4999 regno = true_regnum (reg);
5001 /* Detect when the reload reg can't hold the reload mode.
5002 This used to be one `if', but Sequent compiler can't handle that. */
5003 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5005 enum machine_mode test_mode = VOIDmode;
5007 test_mode = GET_MODE (rld[r].in);
5008 /* If rld[r].in has VOIDmode, it means we will load it
5009 in whatever mode the reload reg has: to wit, rld[r].mode.
5010 We have already tested that for validity. */
5011 /* Aside from that, we need to test that the expressions
5012 to reload from or into have modes which are valid for this
5013 reload register. Otherwise the reload insns would be invalid. */
5014 if (! (rld[r].in != 0 && test_mode != VOIDmode
5015 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5016 if (! (rld[r].out != 0
5017 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5019 /* The reg is OK. */
5022 /* Mark as in use for this insn the reload regs we use
5024 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5025 rld[r].when_needed, rld[r].mode);
5027 rld[r].reg_rtx = reg;
5028 reload_spill_index[r] = spill_regs[i];
5035 /* Find a spill register to use as a reload register for reload R.
5036 LAST_RELOAD is nonzero if this is the last reload for the insn being
5039 Set rld[R].reg_rtx to the register allocated.
5041 We return 1 if successful, or 0 if we couldn't find a spill reg and
5042 we didn't change anything. */
5045 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5050 /* If we put this reload ahead, thinking it is a group,
5051 then insist on finding a group. Otherwise we can grab a
5052 reg that some other reload needs.
5053 (That can happen when we have a 68000 DATA_OR_FP_REG
5054 which is a group of data regs or one fp reg.)
5055 We need not be so restrictive if there are no more reloads
5058 ??? Really it would be nicer to have smarter handling
5059 for that kind of reg class, where a problem like this is normal.
5060 Perhaps those classes should be avoided for reloading
5061 by use of more alternatives. */
5063 int force_group = rld[r].nregs > 1 && ! last_reload;
5065 /* If we want a single register and haven't yet found one,
5066 take any reg in the right class and not in use.
5067 If we want a consecutive group, here is where we look for it.
5069 We use two passes so we can first look for reload regs to
5070 reuse, which are already in use for other reloads in this insn,
5071 and only then use additional registers.
5072 I think that maximizing reuse is needed to make sure we don't
5073 run out of reload regs. Suppose we have three reloads, and
5074 reloads A and B can share regs. These need two regs.
5075 Suppose A and B are given different regs.
5076 That leaves none for C. */
5077 for (pass = 0; pass < 2; pass++)
5079 /* I is the index in spill_regs.
5080 We advance it round-robin between insns to use all spill regs
5081 equally, so that inherited reloads have a chance
5082 of leapfrogging each other. */
5086 for (count = 0; count < n_spills; count++)
5088 int class = (int) rld[r].class;
5094 regnum = spill_regs[i];
5096 if ((reload_reg_free_p (regnum, rld[r].opnum,
5099 /* We check reload_reg_used to make sure we
5100 don't clobber the return register. */
5101 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5102 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5103 rld[r].when_needed, rld[r].in,
5105 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5106 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5107 /* Look first for regs to share, then for unshared. But
5108 don't share regs used for inherited reloads; they are
5109 the ones we want to preserve. */
5111 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5113 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5116 int nr = hard_regno_nregs[regnum][rld[r].mode];
5117 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5118 (on 68000) got us two FP regs. If NR is 1,
5119 we would reject both of them. */
5122 /* If we need only one reg, we have already won. */
5125 /* But reject a single reg if we demand a group. */
5130 /* Otherwise check that as many consecutive regs as we need
5131 are available here. */
5134 int regno = regnum + nr - 1;
5135 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5136 && spill_reg_order[regno] >= 0
5137 && reload_reg_free_p (regno, rld[r].opnum,
5138 rld[r].when_needed)))
5147 /* If we found something on pass 1, omit pass 2. */
5148 if (count < n_spills)
5152 /* We should have found a spill register by now. */
5153 if (count >= n_spills)
5156 /* I is the index in SPILL_REG_RTX of the reload register we are to
5157 allocate. Get an rtx for it and find its register number. */
5159 return set_reload_reg (i, r);
5162 /* Initialize all the tables needed to allocate reload registers.
5163 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5164 is the array we use to restore the reg_rtx field for every reload. */
5167 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5171 for (i = 0; i < n_reloads; i++)
5172 rld[i].reg_rtx = save_reload_reg_rtx[i];
5174 memset (reload_inherited, 0, MAX_RELOADS);
5175 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5176 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5178 CLEAR_HARD_REG_SET (reload_reg_used);
5179 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5180 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5181 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5182 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5183 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5185 CLEAR_HARD_REG_SET (reg_used_in_insn);
5188 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5189 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5190 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5191 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5192 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5193 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5196 for (i = 0; i < reload_n_operands; i++)
5198 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5199 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5200 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5201 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5202 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5203 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5206 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5208 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5210 for (i = 0; i < n_reloads; i++)
5211 /* If we have already decided to use a certain register,
5212 don't use it in another way. */
5214 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5215 rld[i].when_needed, rld[i].mode);
5218 /* Assign hard reg targets for the pseudo-registers we must reload
5219 into hard regs for this insn.
5220 Also output the instructions to copy them in and out of the hard regs.
5222 For machines with register classes, we are responsible for
5223 finding a reload reg in the proper class. */
5226 choose_reload_regs (struct insn_chain *chain)
5228 rtx insn = chain->insn;
5230 unsigned int max_group_size = 1;
5231 enum reg_class group_class = NO_REGS;
5232 int pass, win, inheritance;
5234 rtx save_reload_reg_rtx[MAX_RELOADS];
5236 /* In order to be certain of getting the registers we need,
5237 we must sort the reloads into order of increasing register class.
5238 Then our grabbing of reload registers will parallel the process
5239 that provided the reload registers.
5241 Also note whether any of the reloads wants a consecutive group of regs.
5242 If so, record the maximum size of the group desired and what
5243 register class contains all the groups needed by this insn. */
5245 for (j = 0; j < n_reloads; j++)
5247 reload_order[j] = j;
5248 reload_spill_index[j] = -1;
5250 if (rld[j].nregs > 1)
5252 max_group_size = MAX (rld[j].nregs, max_group_size);
5254 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5257 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5261 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5263 /* If -O, try first with inheritance, then turning it off.
5264 If not -O, don't do inheritance.
5265 Using inheritance when not optimizing leads to paradoxes
5266 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5267 because one side of the comparison might be inherited. */
5269 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5271 choose_reload_regs_init (chain, save_reload_reg_rtx);
5273 /* Process the reloads in order of preference just found.
5274 Beyond this point, subregs can be found in reload_reg_rtx.
5276 This used to look for an existing reloaded home for all of the
5277 reloads, and only then perform any new reloads. But that could lose
5278 if the reloads were done out of reg-class order because a later
5279 reload with a looser constraint might have an old home in a register
5280 needed by an earlier reload with a tighter constraint.
5282 To solve this, we make two passes over the reloads, in the order
5283 described above. In the first pass we try to inherit a reload
5284 from a previous insn. If there is a later reload that needs a
5285 class that is a proper subset of the class being processed, we must
5286 also allocate a spill register during the first pass.
5288 Then make a second pass over the reloads to allocate any reloads
5289 that haven't been given registers yet. */
5291 for (j = 0; j < n_reloads; j++)
5293 int r = reload_order[j];
5294 rtx search_equiv = NULL_RTX;
5296 /* Ignore reloads that got marked inoperative. */
5297 if (rld[r].out == 0 && rld[r].in == 0
5298 && ! rld[r].secondary_p)
5301 /* If find_reloads chose to use reload_in or reload_out as a reload
5302 register, we don't need to chose one. Otherwise, try even if it
5303 found one since we might save an insn if we find the value lying
5305 Try also when reload_in is a pseudo without a hard reg. */
5306 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5307 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5308 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5309 && !MEM_P (rld[r].in)
5310 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5313 #if 0 /* No longer needed for correct operation.
5314 It might give better code, or might not; worth an experiment? */
5315 /* If this is an optional reload, we can't inherit from earlier insns
5316 until we are sure that any non-optional reloads have been allocated.
5317 The following code takes advantage of the fact that optional reloads
5318 are at the end of reload_order. */
5319 if (rld[r].optional != 0)
5320 for (i = 0; i < j; i++)
5321 if ((rld[reload_order[i]].out != 0
5322 || rld[reload_order[i]].in != 0
5323 || rld[reload_order[i]].secondary_p)
5324 && ! rld[reload_order[i]].optional
5325 && rld[reload_order[i]].reg_rtx == 0)
5326 allocate_reload_reg (chain, reload_order[i], 0);
5329 /* First see if this pseudo is already available as reloaded
5330 for a previous insn. We cannot try to inherit for reloads
5331 that are smaller than the maximum number of registers needed
5332 for groups unless the register we would allocate cannot be used
5335 We could check here to see if this is a secondary reload for
5336 an object that is already in a register of the desired class.
5337 This would avoid the need for the secondary reload register.
5338 But this is complex because we can't easily determine what
5339 objects might want to be loaded via this reload. So let a
5340 register be allocated here. In `emit_reload_insns' we suppress
5341 one of the loads in the case described above. */
5347 enum machine_mode mode = VOIDmode;
5351 else if (REG_P (rld[r].in))
5353 regno = REGNO (rld[r].in);
5354 mode = GET_MODE (rld[r].in);
5356 else if (REG_P (rld[r].in_reg))
5358 regno = REGNO (rld[r].in_reg);
5359 mode = GET_MODE (rld[r].in_reg);
5361 else if (GET_CODE (rld[r].in_reg) == SUBREG
5362 && REG_P (SUBREG_REG (rld[r].in_reg)))
5364 byte = SUBREG_BYTE (rld[r].in_reg);
5365 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5366 if (regno < FIRST_PSEUDO_REGISTER)
5367 regno = subreg_regno (rld[r].in_reg);
5368 mode = GET_MODE (rld[r].in_reg);
5371 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5372 || GET_CODE (rld[r].in_reg) == PRE_DEC
5373 || GET_CODE (rld[r].in_reg) == POST_INC
5374 || GET_CODE (rld[r].in_reg) == POST_DEC)
5375 && REG_P (XEXP (rld[r].in_reg, 0)))
5377 regno = REGNO (XEXP (rld[r].in_reg, 0));
5378 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5379 rld[r].out = rld[r].in;
5383 /* This won't work, since REGNO can be a pseudo reg number.
5384 Also, it takes much more hair to keep track of all the things
5385 that can invalidate an inherited reload of part of a pseudoreg. */
5386 else if (GET_CODE (rld[r].in) == SUBREG
5387 && REG_P (SUBREG_REG (rld[r].in)))
5388 regno = subreg_regno (rld[r].in);
5391 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5393 enum reg_class class = rld[r].class, last_class;
5394 rtx last_reg = reg_last_reload_reg[regno];
5395 enum machine_mode need_mode;
5397 i = REGNO (last_reg);
5398 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5399 last_class = REGNO_REG_CLASS (i);
5405 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5406 GET_MODE_CLASS (mode));
5409 #ifdef CANNOT_CHANGE_MODE_CLASS
5410 (!REG_CANNOT_CHANGE_MODE_P (i, GET_MODE (last_reg),
5414 (GET_MODE_SIZE (GET_MODE (last_reg))
5415 >= GET_MODE_SIZE (need_mode))
5416 #ifdef CANNOT_CHANGE_MODE_CLASS
5419 && reg_reloaded_contents[i] == regno
5420 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5421 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5422 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5423 /* Even if we can't use this register as a reload
5424 register, we might use it for reload_override_in,
5425 if copying it to the desired class is cheap
5427 || ((REGISTER_MOVE_COST (mode, last_class, class)
5428 < MEMORY_MOVE_COST (mode, class, 1))
5429 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5430 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5434 #ifdef SECONDARY_MEMORY_NEEDED
5435 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5440 && (rld[r].nregs == max_group_size
5441 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5443 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5444 rld[r].when_needed, rld[r].in,
5447 /* If a group is needed, verify that all the subsequent
5448 registers still have their values intact. */
5449 int nr = hard_regno_nregs[i][rld[r].mode];
5452 for (k = 1; k < nr; k++)
5453 if (reg_reloaded_contents[i + k] != regno
5454 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5462 last_reg = (GET_MODE (last_reg) == mode
5463 ? last_reg : gen_rtx_REG (mode, i));
5466 for (k = 0; k < nr; k++)
5467 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5470 /* We found a register that contains the
5471 value we need. If this register is the
5472 same as an `earlyclobber' operand of the
5473 current insn, just mark it as a place to
5474 reload from since we can't use it as the
5475 reload register itself. */
5477 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5478 if (reg_overlap_mentioned_for_reload_p
5479 (reg_last_reload_reg[regno],
5480 reload_earlyclobbers[i1]))
5483 if (i1 != n_earlyclobbers
5484 || ! (free_for_value_p (i, rld[r].mode,
5486 rld[r].when_needed, rld[r].in,
5488 /* Don't use it if we'd clobber a pseudo reg. */
5489 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5491 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5492 /* Don't clobber the frame pointer. */
5493 || (i == HARD_FRAME_POINTER_REGNUM
5494 && frame_pointer_needed
5496 /* Don't really use the inherited spill reg
5497 if we need it wider than we've got it. */
5498 || (GET_MODE_SIZE (rld[r].mode)
5499 > GET_MODE_SIZE (mode))
5502 /* If find_reloads chose reload_out as reload
5503 register, stay with it - that leaves the
5504 inherited register for subsequent reloads. */
5505 || (rld[r].out && rld[r].reg_rtx
5506 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5508 if (! rld[r].optional)
5510 reload_override_in[r] = last_reg;
5511 reload_inheritance_insn[r]
5512 = reg_reloaded_insn[i];
5518 /* We can use this as a reload reg. */
5519 /* Mark the register as in use for this part of
5521 mark_reload_reg_in_use (i,
5525 rld[r].reg_rtx = last_reg;
5526 reload_inherited[r] = 1;
5527 reload_inheritance_insn[r]
5528 = reg_reloaded_insn[i];
5529 reload_spill_index[r] = i;
5530 for (k = 0; k < nr; k++)
5531 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5539 /* Here's another way to see if the value is already lying around. */
5542 && ! reload_inherited[r]
5544 && (CONSTANT_P (rld[r].in)
5545 || GET_CODE (rld[r].in) == PLUS
5546 || REG_P (rld[r].in)
5547 || MEM_P (rld[r].in))
5548 && (rld[r].nregs == max_group_size
5549 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5550 search_equiv = rld[r].in;
5551 /* If this is an output reload from a simple move insn, look
5552 if an equivalence for the input is available. */
5553 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5555 rtx set = single_set (insn);
5558 && rtx_equal_p (rld[r].out, SET_DEST (set))
5559 && CONSTANT_P (SET_SRC (set)))
5560 search_equiv = SET_SRC (set);
5566 = find_equiv_reg (search_equiv, insn, rld[r].class,
5567 -1, NULL, 0, rld[r].mode);
5573 regno = REGNO (equiv);
5576 /* This must be a SUBREG of a hard register.
5577 Make a new REG since this might be used in an
5578 address and not all machines support SUBREGs
5580 gcc_assert (GET_CODE (equiv) == SUBREG);
5581 regno = subreg_regno (equiv);
5582 equiv = gen_rtx_REG (rld[r].mode, regno);
5586 /* If we found a spill reg, reject it unless it is free
5587 and of the desired class. */
5591 int bad_for_class = 0;
5592 int max_regno = regno + rld[r].nregs;
5594 for (i = regno; i < max_regno; i++)
5596 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5598 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5603 && ! free_for_value_p (regno, rld[r].mode,
5604 rld[r].opnum, rld[r].when_needed,
5605 rld[r].in, rld[r].out, r, 1))
5610 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5613 /* We found a register that contains the value we need.
5614 If this register is the same as an `earlyclobber' operand
5615 of the current insn, just mark it as a place to reload from
5616 since we can't use it as the reload register itself. */
5619 for (i = 0; i < n_earlyclobbers; i++)
5620 if (reg_overlap_mentioned_for_reload_p (equiv,
5621 reload_earlyclobbers[i]))
5623 if (! rld[r].optional)
5624 reload_override_in[r] = equiv;
5629 /* If the equiv register we have found is explicitly clobbered
5630 in the current insn, it depends on the reload type if we
5631 can use it, use it for reload_override_in, or not at all.
5632 In particular, we then can't use EQUIV for a
5633 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5637 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5638 switch (rld[r].when_needed)
5640 case RELOAD_FOR_OTHER_ADDRESS:
5641 case RELOAD_FOR_INPADDR_ADDRESS:
5642 case RELOAD_FOR_INPUT_ADDRESS:
5643 case RELOAD_FOR_OPADDR_ADDR:
5646 case RELOAD_FOR_INPUT:
5647 case RELOAD_FOR_OPERAND_ADDRESS:
5648 if (! rld[r].optional)
5649 reload_override_in[r] = equiv;
5655 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5656 switch (rld[r].when_needed)
5658 case RELOAD_FOR_OTHER_ADDRESS:
5659 case RELOAD_FOR_INPADDR_ADDRESS:
5660 case RELOAD_FOR_INPUT_ADDRESS:
5661 case RELOAD_FOR_OPADDR_ADDR:
5662 case RELOAD_FOR_OPERAND_ADDRESS:
5663 case RELOAD_FOR_INPUT:
5666 if (! rld[r].optional)
5667 reload_override_in[r] = equiv;
5675 /* If we found an equivalent reg, say no code need be generated
5676 to load it, and use it as our reload reg. */
5678 && (regno != HARD_FRAME_POINTER_REGNUM
5679 || !frame_pointer_needed))
5681 int nr = hard_regno_nregs[regno][rld[r].mode];
5683 rld[r].reg_rtx = equiv;
5684 reload_inherited[r] = 1;
5686 /* If reg_reloaded_valid is not set for this register,
5687 there might be a stale spill_reg_store lying around.
5688 We must clear it, since otherwise emit_reload_insns
5689 might delete the store. */
5690 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5691 spill_reg_store[regno] = NULL_RTX;
5692 /* If any of the hard registers in EQUIV are spill
5693 registers, mark them as in use for this insn. */
5694 for (k = 0; k < nr; k++)
5696 i = spill_reg_order[regno + k];
5699 mark_reload_reg_in_use (regno, rld[r].opnum,
5702 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5709 /* If we found a register to use already, or if this is an optional
5710 reload, we are done. */
5711 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5715 /* No longer needed for correct operation. Might or might
5716 not give better code on the average. Want to experiment? */
5718 /* See if there is a later reload that has a class different from our
5719 class that intersects our class or that requires less register
5720 than our reload. If so, we must allocate a register to this
5721 reload now, since that reload might inherit a previous reload
5722 and take the only available register in our class. Don't do this
5723 for optional reloads since they will force all previous reloads
5724 to be allocated. Also don't do this for reloads that have been
5727 for (i = j + 1; i < n_reloads; i++)
5729 int s = reload_order[i];
5731 if ((rld[s].in == 0 && rld[s].out == 0
5732 && ! rld[s].secondary_p)
5736 if ((rld[s].class != rld[r].class
5737 && reg_classes_intersect_p (rld[r].class,
5739 || rld[s].nregs < rld[r].nregs)
5746 allocate_reload_reg (chain, r, j == n_reloads - 1);
5750 /* Now allocate reload registers for anything non-optional that
5751 didn't get one yet. */
5752 for (j = 0; j < n_reloads; j++)
5754 int r = reload_order[j];
5756 /* Ignore reloads that got marked inoperative. */
5757 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5760 /* Skip reloads that already have a register allocated or are
5762 if (rld[r].reg_rtx != 0 || rld[r].optional)
5765 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5769 /* If that loop got all the way, we have won. */
5776 /* Loop around and try without any inheritance. */
5781 /* First undo everything done by the failed attempt
5782 to allocate with inheritance. */
5783 choose_reload_regs_init (chain, save_reload_reg_rtx);
5785 /* Some sanity tests to verify that the reloads found in the first
5786 pass are identical to the ones we have now. */
5787 gcc_assert (chain->n_reloads == n_reloads);
5789 for (i = 0; i < n_reloads; i++)
5791 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5793 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
5794 for (j = 0; j < n_spills; j++)
5795 if (spill_regs[j] == chain->rld[i].regno)
5796 if (! set_reload_reg (j, i))
5797 failed_reload (chain->insn, i);
5801 /* If we thought we could inherit a reload, because it seemed that
5802 nothing else wanted the same reload register earlier in the insn,
5803 verify that assumption, now that all reloads have been assigned.
5804 Likewise for reloads where reload_override_in has been set. */
5806 /* If doing expensive optimizations, do one preliminary pass that doesn't
5807 cancel any inheritance, but removes reloads that have been needed only
5808 for reloads that we know can be inherited. */
5809 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5811 for (j = 0; j < n_reloads; j++)
5813 int r = reload_order[j];
5815 if (reload_inherited[r] && rld[r].reg_rtx)
5816 check_reg = rld[r].reg_rtx;
5817 else if (reload_override_in[r]
5818 && (REG_P (reload_override_in[r])
5819 || GET_CODE (reload_override_in[r]) == SUBREG))
5820 check_reg = reload_override_in[r];
5823 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5824 rld[r].opnum, rld[r].when_needed, rld[r].in,
5825 (reload_inherited[r]
5826 ? rld[r].out : const0_rtx),
5831 reload_inherited[r] = 0;
5832 reload_override_in[r] = 0;
5834 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5835 reload_override_in, then we do not need its related
5836 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5837 likewise for other reload types.
5838 We handle this by removing a reload when its only replacement
5839 is mentioned in reload_in of the reload we are going to inherit.
5840 A special case are auto_inc expressions; even if the input is
5841 inherited, we still need the address for the output. We can
5842 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5843 If we succeeded removing some reload and we are doing a preliminary
5844 pass just to remove such reloads, make another pass, since the
5845 removal of one reload might allow us to inherit another one. */
5847 && rld[r].out != rld[r].in
5848 && remove_address_replacements (rld[r].in) && pass)
5853 /* Now that reload_override_in is known valid,
5854 actually override reload_in. */
5855 for (j = 0; j < n_reloads; j++)
5856 if (reload_override_in[j])
5857 rld[j].in = reload_override_in[j];
5859 /* If this reload won't be done because it has been canceled or is
5860 optional and not inherited, clear reload_reg_rtx so other
5861 routines (such as subst_reloads) don't get confused. */
5862 for (j = 0; j < n_reloads; j++)
5863 if (rld[j].reg_rtx != 0
5864 && ((rld[j].optional && ! reload_inherited[j])
5865 || (rld[j].in == 0 && rld[j].out == 0
5866 && ! rld[j].secondary_p)))
5868 int regno = true_regnum (rld[j].reg_rtx);
5870 if (spill_reg_order[regno] >= 0)
5871 clear_reload_reg_in_use (regno, rld[j].opnum,
5872 rld[j].when_needed, rld[j].mode);
5874 reload_spill_index[j] = -1;
5877 /* Record which pseudos and which spill regs have output reloads. */
5878 for (j = 0; j < n_reloads; j++)
5880 int r = reload_order[j];
5882 i = reload_spill_index[r];
5884 /* I is nonneg if this reload uses a register.
5885 If rld[r].reg_rtx is 0, this is an optional reload
5886 that we opted to ignore. */
5887 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
5888 && rld[r].reg_rtx != 0)
5890 int nregno = REGNO (rld[r].out_reg);
5893 if (nregno < FIRST_PSEUDO_REGISTER)
5894 nr = hard_regno_nregs[nregno][rld[r].mode];
5897 reg_has_output_reload[nregno + nr] = 1;
5901 nr = hard_regno_nregs[i][rld[r].mode];
5903 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5906 gcc_assert (rld[r].when_needed == RELOAD_OTHER
5907 || rld[r].when_needed == RELOAD_FOR_OUTPUT
5908 || rld[r].when_needed == RELOAD_FOR_INSN);
5913 /* Deallocate the reload register for reload R. This is called from
5914 remove_address_replacements. */
5917 deallocate_reload_reg (int r)
5921 if (! rld[r].reg_rtx)
5923 regno = true_regnum (rld[r].reg_rtx);
5925 if (spill_reg_order[regno] >= 0)
5926 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5928 reload_spill_index[r] = -1;
5931 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
5932 reloads of the same item for fear that we might not have enough reload
5933 registers. However, normally they will get the same reload register
5934 and hence actually need not be loaded twice.
5936 Here we check for the most common case of this phenomenon: when we have
5937 a number of reloads for the same object, each of which were allocated
5938 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5939 reload, and is not modified in the insn itself. If we find such,
5940 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5941 This will not increase the number of spill registers needed and will
5942 prevent redundant code. */
5945 merge_assigned_reloads (rtx insn)
5949 /* Scan all the reloads looking for ones that only load values and
5950 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5951 assigned and not modified by INSN. */
5953 for (i = 0; i < n_reloads; i++)
5955 int conflicting_input = 0;
5956 int max_input_address_opnum = -1;
5957 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5959 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5960 || rld[i].out != 0 || rld[i].reg_rtx == 0
5961 || reg_set_p (rld[i].reg_rtx, insn))
5964 /* Look at all other reloads. Ensure that the only use of this
5965 reload_reg_rtx is in a reload that just loads the same value
5966 as we do. Note that any secondary reloads must be of the identical
5967 class since the values, modes, and result registers are the
5968 same, so we need not do anything with any secondary reloads. */
5970 for (j = 0; j < n_reloads; j++)
5972 if (i == j || rld[j].reg_rtx == 0
5973 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
5977 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5978 && rld[j].opnum > max_input_address_opnum)
5979 max_input_address_opnum = rld[j].opnum;
5981 /* If the reload regs aren't exactly the same (e.g, different modes)
5982 or if the values are different, we can't merge this reload.
5983 But if it is an input reload, we might still merge
5984 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
5986 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5987 || rld[j].out != 0 || rld[j].in == 0
5988 || ! rtx_equal_p (rld[i].in, rld[j].in))
5990 if (rld[j].when_needed != RELOAD_FOR_INPUT
5991 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
5992 || rld[i].opnum > rld[j].opnum)
5993 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
5995 conflicting_input = 1;
5996 if (min_conflicting_input_opnum > rld[j].opnum)
5997 min_conflicting_input_opnum = rld[j].opnum;
6001 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6002 we, in fact, found any matching reloads. */
6005 && max_input_address_opnum <= min_conflicting_input_opnum)
6007 for (j = 0; j < n_reloads; j++)
6008 if (i != j && rld[j].reg_rtx != 0
6009 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6010 && (! conflicting_input
6011 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6012 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6014 rld[i].when_needed = RELOAD_OTHER;
6016 reload_spill_index[j] = -1;
6017 transfer_replacements (i, j);
6020 /* If this is now RELOAD_OTHER, look for any reloads that load
6021 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6022 if they were for inputs, RELOAD_OTHER for outputs. Note that
6023 this test is equivalent to looking for reloads for this operand
6025 /* We must take special care when there are two or more reloads to
6026 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6027 same value or a part of it; we must not change its type if there
6028 is a conflicting input. */
6030 if (rld[i].when_needed == RELOAD_OTHER)
6031 for (j = 0; j < n_reloads; j++)
6033 && rld[j].when_needed != RELOAD_OTHER
6034 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6035 && (! conflicting_input
6036 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6037 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6038 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6044 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6045 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6046 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6048 /* Check to see if we accidentally converted two reloads
6049 that use the same reload register with different inputs
6050 to the same type. If so, the resulting code won't work,
6053 for (k = 0; k < j; k++)
6054 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6055 || rld[k].when_needed != rld[j].when_needed
6056 || !rtx_equal_p (rld[k].reg_rtx,
6058 || rtx_equal_p (rld[k].in,
6065 /* These arrays are filled by emit_reload_insns and its subroutines. */
6066 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6067 static rtx other_input_address_reload_insns = 0;
6068 static rtx other_input_reload_insns = 0;
6069 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6070 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6071 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6072 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6073 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6074 static rtx operand_reload_insns = 0;
6075 static rtx other_operand_reload_insns = 0;
6076 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6078 /* Values to be put in spill_reg_store are put here first. */
6079 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6080 static HARD_REG_SET reg_reloaded_died;
6082 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6083 has the number J. OLD contains the value to be used as input. */
6086 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6089 rtx insn = chain->insn;
6090 rtx reloadreg = rl->reg_rtx;
6091 rtx oldequiv_reg = 0;
6094 enum machine_mode mode;
6097 /* Determine the mode to reload in.
6098 This is very tricky because we have three to choose from.
6099 There is the mode the insn operand wants (rl->inmode).
6100 There is the mode of the reload register RELOADREG.
6101 There is the intrinsic mode of the operand, which we could find
6102 by stripping some SUBREGs.
6103 It turns out that RELOADREG's mode is irrelevant:
6104 we can change that arbitrarily.
6106 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6107 then the reload reg may not support QImode moves, so use SImode.
6108 If foo is in memory due to spilling a pseudo reg, this is safe,
6109 because the QImode value is in the least significant part of a
6110 slot big enough for a SImode. If foo is some other sort of
6111 memory reference, then it is impossible to reload this case,
6112 so previous passes had better make sure this never happens.
6114 Then consider a one-word union which has SImode and one of its
6115 members is a float, being fetched as (SUBREG:SF union:SI).
6116 We must fetch that as SFmode because we could be loading into
6117 a float-only register. In this case OLD's mode is correct.
6119 Consider an immediate integer: it has VOIDmode. Here we need
6120 to get a mode from something else.
6122 In some cases, there is a fourth mode, the operand's
6123 containing mode. If the insn specifies a containing mode for
6124 this operand, it overrides all others.
6126 I am not sure whether the algorithm here is always right,
6127 but it does the right things in those cases. */
6129 mode = GET_MODE (old);
6130 if (mode == VOIDmode)
6133 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6134 /* If we need a secondary register for this operation, see if
6135 the value is already in a register in that class. Don't
6136 do this if the secondary register will be used as a scratch
6139 if (rl->secondary_in_reload >= 0
6140 && rl->secondary_in_icode == CODE_FOR_nothing
6143 = find_equiv_reg (old, insn,
6144 rld[rl->secondary_in_reload].class,
6148 /* If reloading from memory, see if there is a register
6149 that already holds the same value. If so, reload from there.
6150 We can pass 0 as the reload_reg_p argument because
6151 any other reload has either already been emitted,
6152 in which case find_equiv_reg will see the reload-insn,
6153 or has yet to be emitted, in which case it doesn't matter
6154 because we will use this equiv reg right away. */
6156 if (oldequiv == 0 && optimize
6159 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6160 && reg_renumber[REGNO (old)] < 0)))
6161 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6165 unsigned int regno = true_regnum (oldequiv);
6167 /* Don't use OLDEQUIV if any other reload changes it at an
6168 earlier stage of this insn or at this stage. */
6169 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6170 rl->in, const0_rtx, j, 0))
6173 /* If it is no cheaper to copy from OLDEQUIV into the
6174 reload register than it would be to move from memory,
6175 don't use it. Likewise, if we need a secondary register
6179 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6180 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6182 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6183 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6184 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6188 #ifdef SECONDARY_MEMORY_NEEDED
6189 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6197 /* delete_output_reload is only invoked properly if old contains
6198 the original pseudo register. Since this is replaced with a
6199 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6200 find the pseudo in RELOAD_IN_REG. */
6202 && reload_override_in[j]
6203 && REG_P (rl->in_reg))
6210 else if (REG_P (oldequiv))
6211 oldequiv_reg = oldequiv;
6212 else if (GET_CODE (oldequiv) == SUBREG)
6213 oldequiv_reg = SUBREG_REG (oldequiv);
6215 /* If we are reloading from a register that was recently stored in
6216 with an output-reload, see if we can prove there was
6217 actually no need to store the old value in it. */
6219 if (optimize && REG_P (oldequiv)
6220 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6221 && spill_reg_store[REGNO (oldequiv)]
6223 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6224 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6226 delete_output_reload (insn, j, REGNO (oldequiv));
6228 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6229 then load RELOADREG from OLDEQUIV. Note that we cannot use
6230 gen_lowpart_common since it can do the wrong thing when
6231 RELOADREG has a multi-word mode. Note that RELOADREG
6232 must always be a REG here. */
6234 if (GET_MODE (reloadreg) != mode)
6235 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6236 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6237 oldequiv = SUBREG_REG (oldequiv);
6238 if (GET_MODE (oldequiv) != VOIDmode
6239 && mode != GET_MODE (oldequiv))
6240 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6242 /* Switch to the right place to emit the reload insns. */
6243 switch (rl->when_needed)
6246 where = &other_input_reload_insns;
6248 case RELOAD_FOR_INPUT:
6249 where = &input_reload_insns[rl->opnum];
6251 case RELOAD_FOR_INPUT_ADDRESS:
6252 where = &input_address_reload_insns[rl->opnum];
6254 case RELOAD_FOR_INPADDR_ADDRESS:
6255 where = &inpaddr_address_reload_insns[rl->opnum];
6257 case RELOAD_FOR_OUTPUT_ADDRESS:
6258 where = &output_address_reload_insns[rl->opnum];
6260 case RELOAD_FOR_OUTADDR_ADDRESS:
6261 where = &outaddr_address_reload_insns[rl->opnum];
6263 case RELOAD_FOR_OPERAND_ADDRESS:
6264 where = &operand_reload_insns;
6266 case RELOAD_FOR_OPADDR_ADDR:
6267 where = &other_operand_reload_insns;
6269 case RELOAD_FOR_OTHER_ADDRESS:
6270 where = &other_input_address_reload_insns;
6276 push_to_sequence (*where);
6278 /* Auto-increment addresses must be reloaded in a special way. */
6279 if (rl->out && ! rl->out_reg)
6281 /* We are not going to bother supporting the case where a
6282 incremented register can't be copied directly from
6283 OLDEQUIV since this seems highly unlikely. */
6284 gcc_assert (rl->secondary_in_reload < 0);
6286 if (reload_inherited[j])
6287 oldequiv = reloadreg;
6289 old = XEXP (rl->in_reg, 0);
6291 if (optimize && REG_P (oldequiv)
6292 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6293 && spill_reg_store[REGNO (oldequiv)]
6295 && (dead_or_set_p (insn,
6296 spill_reg_stored_to[REGNO (oldequiv)])
6297 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6299 delete_output_reload (insn, j, REGNO (oldequiv));
6301 /* Prevent normal processing of this reload. */
6303 /* Output a special code sequence for this case. */
6304 new_spill_reg_store[REGNO (reloadreg)]
6305 = inc_for_reload (reloadreg, oldequiv, rl->out,
6309 /* If we are reloading a pseudo-register that was set by the previous
6310 insn, see if we can get rid of that pseudo-register entirely
6311 by redirecting the previous insn into our reload register. */
6313 else if (optimize && REG_P (old)
6314 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6315 && dead_or_set_p (insn, old)
6316 /* This is unsafe if some other reload
6317 uses the same reg first. */
6318 && ! conflicts_with_override (reloadreg)
6319 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6320 rl->when_needed, old, rl->out, j, 0))
6322 rtx temp = PREV_INSN (insn);
6323 while (temp && NOTE_P (temp))
6324 temp = PREV_INSN (temp);
6326 && NONJUMP_INSN_P (temp)
6327 && GET_CODE (PATTERN (temp)) == SET
6328 && SET_DEST (PATTERN (temp)) == old
6329 /* Make sure we can access insn_operand_constraint. */
6330 && asm_noperands (PATTERN (temp)) < 0
6331 /* This is unsafe if operand occurs more than once in current
6332 insn. Perhaps some occurrences aren't reloaded. */
6333 && count_occurrences (PATTERN (insn), old, 0) == 1)
6335 rtx old = SET_DEST (PATTERN (temp));
6336 /* Store into the reload register instead of the pseudo. */
6337 SET_DEST (PATTERN (temp)) = reloadreg;
6339 /* Verify that resulting insn is valid. */
6340 extract_insn (temp);
6341 if (constrain_operands (1))
6343 /* If the previous insn is an output reload, the source is
6344 a reload register, and its spill_reg_store entry will
6345 contain the previous destination. This is now
6347 if (REG_P (SET_SRC (PATTERN (temp)))
6348 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6350 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6351 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6354 /* If these are the only uses of the pseudo reg,
6355 pretend for GDB it lives in the reload reg we used. */
6356 if (REG_N_DEATHS (REGNO (old)) == 1
6357 && REG_N_SETS (REGNO (old)) == 1)
6359 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6360 alter_reg (REGNO (old), -1);
6366 SET_DEST (PATTERN (temp)) = old;
6371 /* We can't do that, so output an insn to load RELOADREG. */
6373 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6374 /* If we have a secondary reload, pick up the secondary register
6375 and icode, if any. If OLDEQUIV and OLD are different or
6376 if this is an in-out reload, recompute whether or not we
6377 still need a secondary register and what the icode should
6378 be. If we still need a secondary register and the class or
6379 icode is different, go back to reloading from OLD if using
6380 OLDEQUIV means that we got the wrong type of register. We
6381 cannot have different class or icode due to an in-out reload
6382 because we don't make such reloads when both the input and
6383 output need secondary reload registers. */
6385 if (! special && rl->secondary_in_reload >= 0)
6387 rtx second_reload_reg = 0;
6388 int secondary_reload = rl->secondary_in_reload;
6389 rtx real_oldequiv = oldequiv;
6392 enum insn_code icode;
6394 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6395 and similarly for OLD.
6396 See comments in get_secondary_reload in reload.c. */
6397 /* If it is a pseudo that cannot be replaced with its
6398 equivalent MEM, we must fall back to reload_in, which
6399 will have all the necessary substitutions registered.
6400 Likewise for a pseudo that can't be replaced with its
6401 equivalent constant.
6403 Take extra care for subregs of such pseudos. Note that
6404 we cannot use reg_equiv_mem in this case because it is
6405 not in the right mode. */
6408 if (GET_CODE (tmp) == SUBREG)
6409 tmp = SUBREG_REG (tmp);
6411 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6412 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6413 || reg_equiv_constant[REGNO (tmp)] != 0))
6415 if (! reg_equiv_mem[REGNO (tmp)]
6416 || num_not_at_initial_offset
6417 || GET_CODE (oldequiv) == SUBREG)
6418 real_oldequiv = rl->in;
6420 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6424 if (GET_CODE (tmp) == SUBREG)
6425 tmp = SUBREG_REG (tmp);
6427 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6428 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6429 || reg_equiv_constant[REGNO (tmp)] != 0))
6431 if (! reg_equiv_mem[REGNO (tmp)]
6432 || num_not_at_initial_offset
6433 || GET_CODE (old) == SUBREG)
6436 real_old = reg_equiv_mem[REGNO (tmp)];
6439 second_reload_reg = rld[secondary_reload].reg_rtx;
6440 icode = rl->secondary_in_icode;
6442 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6443 || (rl->in != 0 && rl->out != 0))
6445 enum reg_class new_class
6446 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6447 mode, real_oldequiv);
6449 if (new_class == NO_REGS)
6450 second_reload_reg = 0;
6453 enum insn_code new_icode;
6454 enum machine_mode new_mode;
6456 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6457 REGNO (second_reload_reg)))
6458 oldequiv = old, real_oldequiv = real_old;
6461 new_icode = reload_in_optab[(int) mode];
6462 if (new_icode != CODE_FOR_nothing
6463 && ((insn_data[(int) new_icode].operand[0].predicate
6464 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6466 || (insn_data[(int) new_icode].operand[1].predicate
6467 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6468 (real_oldequiv, mode)))))
6469 new_icode = CODE_FOR_nothing;
6471 if (new_icode == CODE_FOR_nothing)
6474 new_mode = insn_data[(int) new_icode].operand[2].mode;
6476 if (GET_MODE (second_reload_reg) != new_mode)
6478 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6480 oldequiv = old, real_oldequiv = real_old;
6483 = reload_adjust_reg_for_mode (second_reload_reg,
6490 /* If we still need a secondary reload register, check
6491 to see if it is being used as a scratch or intermediate
6492 register and generate code appropriately. If we need
6493 a scratch register, use REAL_OLDEQUIV since the form of
6494 the insn may depend on the actual address if it is
6497 if (second_reload_reg)
6499 if (icode != CODE_FOR_nothing)
6501 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6502 second_reload_reg));
6507 /* See if we need a scratch register to load the
6508 intermediate register (a tertiary reload). */
6509 enum insn_code tertiary_icode
6510 = rld[secondary_reload].secondary_in_icode;
6512 if (tertiary_icode != CODE_FOR_nothing)
6514 rtx third_reload_reg
6515 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6517 emit_insn ((GEN_FCN (tertiary_icode)
6518 (second_reload_reg, real_oldequiv,
6519 third_reload_reg)));
6522 gen_reload (second_reload_reg, real_oldequiv,
6526 oldequiv = second_reload_reg;
6532 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6534 rtx real_oldequiv = oldequiv;
6536 if ((REG_P (oldequiv)
6537 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6538 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6539 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6540 || (GET_CODE (oldequiv) == SUBREG
6541 && REG_P (SUBREG_REG (oldequiv))
6542 && (REGNO (SUBREG_REG (oldequiv))
6543 >= FIRST_PSEUDO_REGISTER)
6544 && ((reg_equiv_memory_loc
6545 [REGNO (SUBREG_REG (oldequiv))] != 0)
6546 || (reg_equiv_constant
6547 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6548 || (CONSTANT_P (oldequiv)
6549 && (PREFERRED_RELOAD_CLASS (oldequiv,
6550 REGNO_REG_CLASS (REGNO (reloadreg)))
6552 real_oldequiv = rl->in;
6553 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6557 if (flag_non_call_exceptions)
6558 copy_eh_notes (insn, get_insns ());
6560 /* End this sequence. */
6561 *where = get_insns ();
6564 /* Update reload_override_in so that delete_address_reloads_1
6565 can see the actual register usage. */
6567 reload_override_in[j] = oldequiv;
6570 /* Generate insns to for the output reload RL, which is for the insn described
6571 by CHAIN and has the number J. */
6573 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6576 rtx reloadreg = rl->reg_rtx;
6577 rtx insn = chain->insn;
6580 enum machine_mode mode = GET_MODE (old);
6583 if (rl->when_needed == RELOAD_OTHER)
6586 push_to_sequence (output_reload_insns[rl->opnum]);
6588 /* Determine the mode to reload in.
6589 See comments above (for input reloading). */
6591 if (mode == VOIDmode)
6593 /* VOIDmode should never happen for an output. */
6594 if (asm_noperands (PATTERN (insn)) < 0)
6595 /* It's the compiler's fault. */
6596 fatal_insn ("VOIDmode on an output", insn);
6597 error_for_asm (insn, "output operand is constant in %<asm%>");
6598 /* Prevent crash--use something we know is valid. */
6600 old = gen_rtx_REG (mode, REGNO (reloadreg));
6603 if (GET_MODE (reloadreg) != mode)
6604 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6606 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6608 /* If we need two reload regs, set RELOADREG to the intermediate
6609 one, since it will be stored into OLD. We might need a secondary
6610 register only for an input reload, so check again here. */
6612 if (rl->secondary_out_reload >= 0)
6616 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
6617 && reg_equiv_mem[REGNO (old)] != 0)
6618 real_old = reg_equiv_mem[REGNO (old)];
6620 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6624 rtx second_reloadreg = reloadreg;
6625 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6627 /* See if RELOADREG is to be used as a scratch register
6628 or as an intermediate register. */
6629 if (rl->secondary_out_icode != CODE_FOR_nothing)
6631 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6632 (real_old, second_reloadreg, reloadreg)));
6637 /* See if we need both a scratch and intermediate reload
6640 int secondary_reload = rl->secondary_out_reload;
6641 enum insn_code tertiary_icode
6642 = rld[secondary_reload].secondary_out_icode;
6644 if (GET_MODE (reloadreg) != mode)
6645 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6647 if (tertiary_icode != CODE_FOR_nothing)
6650 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6653 /* Copy primary reload reg to secondary reload reg.
6654 (Note that these have been swapped above, then
6655 secondary reload reg to OLD using our insn.) */
6657 /* If REAL_OLD is a paradoxical SUBREG, remove it
6658 and try to put the opposite SUBREG on
6660 if (GET_CODE (real_old) == SUBREG
6661 && (GET_MODE_SIZE (GET_MODE (real_old))
6662 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6663 && 0 != (tem = gen_lowpart_common
6664 (GET_MODE (SUBREG_REG (real_old)),
6666 real_old = SUBREG_REG (real_old), reloadreg = tem;
6668 gen_reload (reloadreg, second_reloadreg,
6669 rl->opnum, rl->when_needed);
6670 emit_insn ((GEN_FCN (tertiary_icode)
6671 (real_old, reloadreg, third_reloadreg)));
6676 /* Copy between the reload regs here and then to
6679 gen_reload (reloadreg, second_reloadreg,
6680 rl->opnum, rl->when_needed);
6686 /* Output the last reload insn. */
6691 /* Don't output the last reload if OLD is not the dest of
6692 INSN and is in the src and is clobbered by INSN. */
6693 if (! flag_expensive_optimizations
6695 || !(set = single_set (insn))
6696 || rtx_equal_p (old, SET_DEST (set))
6697 || !reg_mentioned_p (old, SET_SRC (set))
6698 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6699 gen_reload (old, reloadreg, rl->opnum,
6703 /* Look at all insns we emitted, just to be safe. */
6704 for (p = get_insns (); p; p = NEXT_INSN (p))
6707 rtx pat = PATTERN (p);
6709 /* If this output reload doesn't come from a spill reg,
6710 clear any memory of reloaded copies of the pseudo reg.
6711 If this output reload comes from a spill reg,
6712 reg_has_output_reload will make this do nothing. */
6713 note_stores (pat, forget_old_reloads_1, NULL);
6715 if (reg_mentioned_p (rl->reg_rtx, pat))
6717 rtx set = single_set (insn);
6718 if (reload_spill_index[j] < 0
6720 && SET_SRC (set) == rl->reg_rtx)
6722 int src = REGNO (SET_SRC (set));
6724 reload_spill_index[j] = src;
6725 SET_HARD_REG_BIT (reg_is_output_reload, src);
6726 if (find_regno_note (insn, REG_DEAD, src))
6727 SET_HARD_REG_BIT (reg_reloaded_died, src);
6729 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6731 int s = rl->secondary_out_reload;
6732 set = single_set (p);
6733 /* If this reload copies only to the secondary reload
6734 register, the secondary reload does the actual
6736 if (s >= 0 && set == NULL_RTX)
6737 /* We can't tell what function the secondary reload
6738 has and where the actual store to the pseudo is
6739 made; leave new_spill_reg_store alone. */
6742 && SET_SRC (set) == rl->reg_rtx
6743 && SET_DEST (set) == rld[s].reg_rtx)
6745 /* Usually the next instruction will be the
6746 secondary reload insn; if we can confirm
6747 that it is, setting new_spill_reg_store to
6748 that insn will allow an extra optimization. */
6749 rtx s_reg = rld[s].reg_rtx;
6750 rtx next = NEXT_INSN (p);
6751 rld[s].out = rl->out;
6752 rld[s].out_reg = rl->out_reg;
6753 set = single_set (next);
6754 if (set && SET_SRC (set) == s_reg
6755 && ! new_spill_reg_store[REGNO (s_reg)])
6757 SET_HARD_REG_BIT (reg_is_output_reload,
6759 new_spill_reg_store[REGNO (s_reg)] = next;
6763 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6768 if (rl->when_needed == RELOAD_OTHER)
6770 emit_insn (other_output_reload_insns[rl->opnum]);
6771 other_output_reload_insns[rl->opnum] = get_insns ();
6774 output_reload_insns[rl->opnum] = get_insns ();
6776 if (flag_non_call_exceptions)
6777 copy_eh_notes (insn, get_insns ());
6782 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6783 and has the number J. */
6785 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
6787 rtx insn = chain->insn;
6788 rtx old = (rl->in && MEM_P (rl->in)
6789 ? rl->in_reg : rl->in);
6792 /* AUTO_INC reloads need to be handled even if inherited. We got an
6793 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6794 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6795 && ! rtx_equal_p (rl->reg_rtx, old)
6796 && rl->reg_rtx != 0)
6797 emit_input_reload_insns (chain, rld + j, old, j);
6799 /* When inheriting a wider reload, we have a MEM in rl->in,
6800 e.g. inheriting a SImode output reload for
6801 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6802 if (optimize && reload_inherited[j] && rl->in
6804 && MEM_P (rl->in_reg)
6805 && reload_spill_index[j] >= 0
6806 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6807 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6809 /* If we are reloading a register that was recently stored in with an
6810 output-reload, see if we can prove there was
6811 actually no need to store the old value in it. */
6814 && (reload_inherited[j] || reload_override_in[j])
6816 && REG_P (rl->reg_rtx)
6817 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6819 /* There doesn't seem to be any reason to restrict this to pseudos
6820 and doing so loses in the case where we are copying from a
6821 register of the wrong class. */
6822 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6823 >= FIRST_PSEUDO_REGISTER)
6825 /* The insn might have already some references to stackslots
6826 replaced by MEMs, while reload_out_reg still names the
6828 && (dead_or_set_p (insn,
6829 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6830 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6832 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6835 /* Do output reloading for reload RL, which is for the insn described by
6836 CHAIN and has the number J.
6837 ??? At some point we need to support handling output reloads of
6838 JUMP_INSNs or insns that set cc0. */
6840 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
6843 rtx insn = chain->insn;
6844 /* If this is an output reload that stores something that is
6845 not loaded in this same reload, see if we can eliminate a previous
6847 rtx pseudo = rl->out_reg;
6852 && ! rtx_equal_p (rl->in_reg, pseudo)
6853 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6854 && reg_last_reload_reg[REGNO (pseudo)])
6856 int pseudo_no = REGNO (pseudo);
6857 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6859 /* We don't need to test full validity of last_regno for
6860 inherit here; we only want to know if the store actually
6861 matches the pseudo. */
6862 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6863 && reg_reloaded_contents[last_regno] == pseudo_no
6864 && spill_reg_store[last_regno]
6865 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6866 delete_output_reload (insn, j, last_regno);
6871 || rl->reg_rtx == old
6872 || rl->reg_rtx == 0)
6875 /* An output operand that dies right away does need a reload,
6876 but need not be copied from it. Show the new location in the
6878 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
6879 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6881 XEXP (note, 0) = rl->reg_rtx;
6884 /* Likewise for a SUBREG of an operand that dies. */
6885 else if (GET_CODE (old) == SUBREG
6886 && REG_P (SUBREG_REG (old))
6887 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6890 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6894 else if (GET_CODE (old) == SCRATCH)
6895 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6896 but we don't want to make an output reload. */
6899 /* If is a JUMP_INSN, we can't support output reloads yet. */
6900 gcc_assert (!JUMP_P (insn));
6902 emit_output_reload_insns (chain, rld + j, j);
6905 /* Reload number R reloads from or to a group of hard registers starting at
6906 register REGNO. Return true if it can be treated for inheritance purposes
6907 like a group of reloads, each one reloading a single hard register.
6908 The caller has already checked that the spill register and REGNO use
6909 the same number of registers to store the reload value. */
6912 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
6914 #ifdef CANNOT_CHANGE_MODE_CLASS
6915 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
6916 GET_MODE (rld[r].reg_rtx),
6917 reg_raw_mode[reload_spill_index[r]])
6918 && !REG_CANNOT_CHANGE_MODE_P (regno,
6919 GET_MODE (rld[r].reg_rtx),
6920 reg_raw_mode[regno]));
6926 /* Output insns to reload values in and out of the chosen reload regs. */
6929 emit_reload_insns (struct insn_chain *chain)
6931 rtx insn = chain->insn;
6935 CLEAR_HARD_REG_SET (reg_reloaded_died);
6937 for (j = 0; j < reload_n_operands; j++)
6938 input_reload_insns[j] = input_address_reload_insns[j]
6939 = inpaddr_address_reload_insns[j]
6940 = output_reload_insns[j] = output_address_reload_insns[j]
6941 = outaddr_address_reload_insns[j]
6942 = other_output_reload_insns[j] = 0;
6943 other_input_address_reload_insns = 0;
6944 other_input_reload_insns = 0;
6945 operand_reload_insns = 0;
6946 other_operand_reload_insns = 0;
6948 /* Dump reloads into the dump file. */
6951 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6952 debug_reload_to_stream (dump_file);
6955 /* Now output the instructions to copy the data into and out of the
6956 reload registers. Do these in the order that the reloads were reported,
6957 since reloads of base and index registers precede reloads of operands
6958 and the operands may need the base and index registers reloaded. */
6960 for (j = 0; j < n_reloads; j++)
6963 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6964 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6966 do_input_reload (chain, rld + j, j);
6967 do_output_reload (chain, rld + j, j);
6970 /* Now write all the insns we made for reloads in the order expected by
6971 the allocation functions. Prior to the insn being reloaded, we write
6972 the following reloads:
6974 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6976 RELOAD_OTHER reloads.
6978 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6979 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6980 RELOAD_FOR_INPUT reload for the operand.
6982 RELOAD_FOR_OPADDR_ADDRS reloads.
6984 RELOAD_FOR_OPERAND_ADDRESS reloads.
6986 After the insn being reloaded, we write the following:
6988 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6989 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6990 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6991 reloads for the operand. The RELOAD_OTHER output reloads are
6992 output in descending order by reload number. */
6994 emit_insn_before (other_input_address_reload_insns, insn);
6995 emit_insn_before (other_input_reload_insns, insn);
6997 for (j = 0; j < reload_n_operands; j++)
6999 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7000 emit_insn_before (input_address_reload_insns[j], insn);
7001 emit_insn_before (input_reload_insns[j], insn);
7004 emit_insn_before (other_operand_reload_insns, insn);
7005 emit_insn_before (operand_reload_insns, insn);
7007 for (j = 0; j < reload_n_operands; j++)
7009 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7010 x = emit_insn_after (output_address_reload_insns[j], x);
7011 x = emit_insn_after (output_reload_insns[j], x);
7012 emit_insn_after (other_output_reload_insns[j], x);
7015 /* For all the spill regs newly reloaded in this instruction,
7016 record what they were reloaded from, so subsequent instructions
7017 can inherit the reloads.
7019 Update spill_reg_store for the reloads of this insn.
7020 Copy the elements that were updated in the loop above. */
7022 for (j = 0; j < n_reloads; j++)
7024 int r = reload_order[j];
7025 int i = reload_spill_index[r];
7027 /* If this is a non-inherited input reload from a pseudo, we must
7028 clear any memory of a previous store to the same pseudo. Only do
7029 something if there will not be an output reload for the pseudo
7031 if (rld[r].in_reg != 0
7032 && ! (reload_inherited[r] || reload_override_in[r]))
7034 rtx reg = rld[r].in_reg;
7036 if (GET_CODE (reg) == SUBREG)
7037 reg = SUBREG_REG (reg);
7040 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7041 && ! reg_has_output_reload[REGNO (reg)])
7043 int nregno = REGNO (reg);
7045 if (reg_last_reload_reg[nregno])
7047 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7049 if (reg_reloaded_contents[last_regno] == nregno)
7050 spill_reg_store[last_regno] = 0;
7055 /* I is nonneg if this reload used a register.
7056 If rld[r].reg_rtx is 0, this is an optional reload
7057 that we opted to ignore. */
7059 if (i >= 0 && rld[r].reg_rtx != 0)
7061 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7063 int part_reaches_end = 0;
7064 int all_reaches_end = 1;
7066 /* For a multi register reload, we need to check if all or part
7067 of the value lives to the end. */
7068 for (k = 0; k < nr; k++)
7070 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7071 rld[r].when_needed))
7072 part_reaches_end = 1;
7074 all_reaches_end = 0;
7077 /* Ignore reloads that don't reach the end of the insn in
7079 if (all_reaches_end)
7081 /* First, clear out memory of what used to be in this spill reg.
7082 If consecutive registers are used, clear them all. */
7084 for (k = 0; k < nr; k++)
7086 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7087 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7090 /* Maybe the spill reg contains a copy of reload_out. */
7092 && (REG_P (rld[r].out)
7096 || REG_P (rld[r].out_reg)))
7098 rtx out = (REG_P (rld[r].out)
7102 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7103 int nregno = REGNO (out);
7104 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7105 : hard_regno_nregs[nregno]
7106 [GET_MODE (rld[r].reg_rtx)]);
7109 spill_reg_store[i] = new_spill_reg_store[i];
7110 spill_reg_stored_to[i] = out;
7111 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7113 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7115 && inherit_piecemeal_p (r, nregno));
7117 /* If NREGNO is a hard register, it may occupy more than
7118 one register. If it does, say what is in the
7119 rest of the registers assuming that both registers
7120 agree on how many words the object takes. If not,
7121 invalidate the subsequent registers. */
7123 if (nregno < FIRST_PSEUDO_REGISTER)
7124 for (k = 1; k < nnr; k++)
7125 reg_last_reload_reg[nregno + k]
7127 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7130 /* Now do the inverse operation. */
7131 for (k = 0; k < nr; k++)
7133 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7134 reg_reloaded_contents[i + k]
7135 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7138 reg_reloaded_insn[i + k] = insn;
7139 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7140 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7141 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7145 /* Maybe the spill reg contains a copy of reload_in. Only do
7146 something if there will not be an output reload for
7147 the register being reloaded. */
7148 else if (rld[r].out_reg == 0
7150 && ((REG_P (rld[r].in)
7151 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7152 && ! reg_has_output_reload[REGNO (rld[r].in)])
7153 || (REG_P (rld[r].in_reg)
7154 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7155 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7162 if (REG_P (rld[r].in)
7163 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7165 else if (REG_P (rld[r].in_reg))
7168 in = XEXP (rld[r].in_reg, 0);
7169 nregno = REGNO (in);
7171 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7172 : hard_regno_nregs[nregno]
7173 [GET_MODE (rld[r].reg_rtx)]);
7175 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7177 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7179 && inherit_piecemeal_p (r, nregno));
7181 if (nregno < FIRST_PSEUDO_REGISTER)
7182 for (k = 1; k < nnr; k++)
7183 reg_last_reload_reg[nregno + k]
7185 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7188 /* Unless we inherited this reload, show we haven't
7189 recently done a store.
7190 Previous stores of inherited auto_inc expressions
7191 also have to be discarded. */
7192 if (! reload_inherited[r]
7193 || (rld[r].out && ! rld[r].out_reg))
7194 spill_reg_store[i] = 0;
7196 for (k = 0; k < nr; k++)
7198 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7199 reg_reloaded_contents[i + k]
7200 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7203 reg_reloaded_insn[i + k] = insn;
7204 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7205 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7206 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7211 /* However, if part of the reload reaches the end, then we must
7212 invalidate the old info for the part that survives to the end. */
7213 else if (part_reaches_end)
7215 for (k = 0; k < nr; k++)
7216 if (reload_reg_reaches_end_p (i + k,
7218 rld[r].when_needed))
7219 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7223 /* The following if-statement was #if 0'd in 1.34 (or before...).
7224 It's reenabled in 1.35 because supposedly nothing else
7225 deals with this problem. */
7227 /* If a register gets output-reloaded from a non-spill register,
7228 that invalidates any previous reloaded copy of it.
7229 But forget_old_reloads_1 won't get to see it, because
7230 it thinks only about the original insn. So invalidate it here. */
7231 if (i < 0 && rld[r].out != 0
7232 && (REG_P (rld[r].out)
7233 || (MEM_P (rld[r].out)
7234 && REG_P (rld[r].out_reg))))
7236 rtx out = (REG_P (rld[r].out)
7237 ? rld[r].out : rld[r].out_reg);
7238 int nregno = REGNO (out);
7239 if (nregno >= FIRST_PSEUDO_REGISTER)
7241 rtx src_reg, store_insn = NULL_RTX;
7243 reg_last_reload_reg[nregno] = 0;
7245 /* If we can find a hard register that is stored, record
7246 the storing insn so that we may delete this insn with
7247 delete_output_reload. */
7248 src_reg = rld[r].reg_rtx;
7250 /* If this is an optional reload, try to find the source reg
7251 from an input reload. */
7254 rtx set = single_set (insn);
7255 if (set && SET_DEST (set) == rld[r].out)
7259 src_reg = SET_SRC (set);
7261 for (k = 0; k < n_reloads; k++)
7263 if (rld[k].in == src_reg)
7265 src_reg = rld[k].reg_rtx;
7272 store_insn = new_spill_reg_store[REGNO (src_reg)];
7273 if (src_reg && REG_P (src_reg)
7274 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7276 int src_regno = REGNO (src_reg);
7277 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7278 /* The place where to find a death note varies with
7279 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7280 necessarily checked exactly in the code that moves
7281 notes, so just check both locations. */
7282 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7283 if (! note && store_insn)
7284 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7287 spill_reg_store[src_regno + nr] = store_insn;
7288 spill_reg_stored_to[src_regno + nr] = out;
7289 reg_reloaded_contents[src_regno + nr] = nregno;
7290 reg_reloaded_insn[src_regno + nr] = store_insn;
7291 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7292 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7293 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7294 GET_MODE (src_reg)))
7295 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7297 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7299 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7301 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7303 reg_last_reload_reg[nregno] = src_reg;
7304 /* We have to set reg_has_output_reload here, or else
7305 forget_old_reloads_1 will clear reg_last_reload_reg
7307 reg_has_output_reload[nregno] = 1;
7312 int num_regs = hard_regno_nregs[nregno][GET_MODE (rld[r].out)];
7314 while (num_regs-- > 0)
7315 reg_last_reload_reg[nregno + num_regs] = 0;
7319 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7322 /* Emit code to perform a reload from IN (which may be a reload register) to
7323 OUT (which may also be a reload register). IN or OUT is from operand
7324 OPNUM with reload type TYPE.
7326 Returns first insn emitted. */
7329 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7331 rtx last = get_last_insn ();
7334 /* If IN is a paradoxical SUBREG, remove it and try to put the
7335 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7336 if (GET_CODE (in) == SUBREG
7337 && (GET_MODE_SIZE (GET_MODE (in))
7338 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7339 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7340 in = SUBREG_REG (in), out = tem;
7341 else if (GET_CODE (out) == SUBREG
7342 && (GET_MODE_SIZE (GET_MODE (out))
7343 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7344 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7345 out = SUBREG_REG (out), in = tem;
7347 /* How to do this reload can get quite tricky. Normally, we are being
7348 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7349 register that didn't get a hard register. In that case we can just
7350 call emit_move_insn.
7352 We can also be asked to reload a PLUS that adds a register or a MEM to
7353 another register, constant or MEM. This can occur during frame pointer
7354 elimination and while reloading addresses. This case is handled by
7355 trying to emit a single insn to perform the add. If it is not valid,
7356 we use a two insn sequence.
7358 Finally, we could be called to handle an 'o' constraint by putting
7359 an address into a register. In that case, we first try to do this
7360 with a named pattern of "reload_load_address". If no such pattern
7361 exists, we just emit a SET insn and hope for the best (it will normally
7362 be valid on machines that use 'o').
7364 This entire process is made complex because reload will never
7365 process the insns we generate here and so we must ensure that
7366 they will fit their constraints and also by the fact that parts of
7367 IN might be being reloaded separately and replaced with spill registers.
7368 Because of this, we are, in some sense, just guessing the right approach
7369 here. The one listed above seems to work.
7371 ??? At some point, this whole thing needs to be rethought. */
7373 if (GET_CODE (in) == PLUS
7374 && (REG_P (XEXP (in, 0))
7375 || GET_CODE (XEXP (in, 0)) == SUBREG
7376 || MEM_P (XEXP (in, 0)))
7377 && (REG_P (XEXP (in, 1))
7378 || GET_CODE (XEXP (in, 1)) == SUBREG
7379 || CONSTANT_P (XEXP (in, 1))
7380 || MEM_P (XEXP (in, 1))))
7382 /* We need to compute the sum of a register or a MEM and another
7383 register, constant, or MEM, and put it into the reload
7384 register. The best possible way of doing this is if the machine
7385 has a three-operand ADD insn that accepts the required operands.
7387 The simplest approach is to try to generate such an insn and see if it
7388 is recognized and matches its constraints. If so, it can be used.
7390 It might be better not to actually emit the insn unless it is valid,
7391 but we need to pass the insn as an operand to `recog' and
7392 `extract_insn' and it is simpler to emit and then delete the insn if
7393 not valid than to dummy things up. */
7395 rtx op0, op1, tem, insn;
7398 op0 = find_replacement (&XEXP (in, 0));
7399 op1 = find_replacement (&XEXP (in, 1));
7401 /* Since constraint checking is strict, commutativity won't be
7402 checked, so we need to do that here to avoid spurious failure
7403 if the add instruction is two-address and the second operand
7404 of the add is the same as the reload reg, which is frequently
7405 the case. If the insn would be A = B + A, rearrange it so
7406 it will be A = A + B as constrain_operands expects. */
7408 if (REG_P (XEXP (in, 1))
7409 && REGNO (out) == REGNO (XEXP (in, 1)))
7410 tem = op0, op0 = op1, op1 = tem;
7412 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7413 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7415 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7416 code = recog_memoized (insn);
7420 extract_insn (insn);
7421 /* We want constrain operands to treat this insn strictly in
7422 its validity determination, i.e., the way it would after reload
7424 if (constrain_operands (1))
7428 delete_insns_since (last);
7430 /* If that failed, we must use a conservative two-insn sequence.
7432 Use a move to copy one operand into the reload register. Prefer
7433 to reload a constant, MEM or pseudo since the move patterns can
7434 handle an arbitrary operand. If OP1 is not a constant, MEM or
7435 pseudo and OP1 is not a valid operand for an add instruction, then
7438 After reloading one of the operands into the reload register, add
7439 the reload register to the output register.
7441 If there is another way to do this for a specific machine, a
7442 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7445 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7447 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7449 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7450 || (code != CODE_FOR_nothing
7451 && ! ((*insn_data[code].operand[2].predicate)
7452 (op1, insn_data[code].operand[2].mode))))
7453 tem = op0, op0 = op1, op1 = tem;
7455 gen_reload (out, op0, opnum, type);
7457 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7458 This fixes a problem on the 32K where the stack pointer cannot
7459 be used as an operand of an add insn. */
7461 if (rtx_equal_p (op0, op1))
7464 insn = emit_insn (gen_add2_insn (out, op1));
7466 /* If that failed, copy the address register to the reload register.
7467 Then add the constant to the reload register. */
7469 code = recog_memoized (insn);
7473 extract_insn (insn);
7474 /* We want constrain operands to treat this insn strictly in
7475 its validity determination, i.e., the way it would after reload
7477 if (constrain_operands (1))
7479 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7481 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7486 delete_insns_since (last);
7488 gen_reload (out, op1, opnum, type);
7489 insn = emit_insn (gen_add2_insn (out, op0));
7490 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7493 #ifdef SECONDARY_MEMORY_NEEDED
7494 /* If we need a memory location to do the move, do it that way. */
7495 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7496 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7497 && (REG_P (out) || GET_CODE (out) == SUBREG)
7498 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7499 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7500 REGNO_REG_CLASS (reg_or_subregno (out)),
7503 /* Get the memory to use and rewrite both registers to its mode. */
7504 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7506 if (GET_MODE (loc) != GET_MODE (out))
7507 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7509 if (GET_MODE (loc) != GET_MODE (in))
7510 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7512 gen_reload (loc, in, opnum, type);
7513 gen_reload (out, loc, opnum, type);
7517 /* If IN is a simple operand, use gen_move_insn. */
7518 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
7519 emit_insn (gen_move_insn (out, in));
7521 #ifdef HAVE_reload_load_address
7522 else if (HAVE_reload_load_address)
7523 emit_insn (gen_reload_load_address (out, in));
7526 /* Otherwise, just write (set OUT IN) and hope for the best. */
7528 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7530 /* Return the first insn emitted.
7531 We can not just return get_last_insn, because there may have
7532 been multiple instructions emitted. Also note that gen_move_insn may
7533 emit more than one insn itself, so we can not assume that there is one
7534 insn emitted per emit_insn_before call. */
7536 return last ? NEXT_INSN (last) : get_insns ();
7539 /* Delete a previously made output-reload whose result we now believe
7540 is not needed. First we double-check.
7542 INSN is the insn now being processed.
7543 LAST_RELOAD_REG is the hard register number for which we want to delete
7544 the last output reload.
7545 J is the reload-number that originally used REG. The caller has made
7546 certain that reload J doesn't use REG any longer for input. */
7549 delete_output_reload (rtx insn, int j, int last_reload_reg)
7551 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7552 rtx reg = spill_reg_stored_to[last_reload_reg];
7555 int n_inherited = 0;
7559 /* It is possible that this reload has been only used to set another reload
7560 we eliminated earlier and thus deleted this instruction too. */
7561 if (INSN_DELETED_P (output_reload_insn))
7564 /* Get the raw pseudo-register referred to. */
7566 while (GET_CODE (reg) == SUBREG)
7567 reg = SUBREG_REG (reg);
7568 substed = reg_equiv_memory_loc[REGNO (reg)];
7570 /* This is unsafe if the operand occurs more often in the current
7571 insn than it is inherited. */
7572 for (k = n_reloads - 1; k >= 0; k--)
7574 rtx reg2 = rld[k].in;
7577 if (MEM_P (reg2) || reload_override_in[k])
7578 reg2 = rld[k].in_reg;
7580 if (rld[k].out && ! rld[k].out_reg)
7581 reg2 = XEXP (rld[k].in_reg, 0);
7583 while (GET_CODE (reg2) == SUBREG)
7584 reg2 = SUBREG_REG (reg2);
7585 if (rtx_equal_p (reg2, reg))
7587 if (reload_inherited[k] || reload_override_in[k] || k == j)
7590 reg2 = rld[k].out_reg;
7593 while (GET_CODE (reg2) == SUBREG)
7594 reg2 = XEXP (reg2, 0);
7595 if (rtx_equal_p (reg2, reg))
7602 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7604 n_occurrences += count_occurrences (PATTERN (insn),
7605 eliminate_regs (substed, 0,
7607 if (n_occurrences > n_inherited)
7610 /* If the pseudo-reg we are reloading is no longer referenced
7611 anywhere between the store into it and here,
7612 and no jumps or labels intervene, then the value can get
7613 here through the reload reg alone.
7614 Otherwise, give up--return. */
7615 for (i1 = NEXT_INSN (output_reload_insn);
7616 i1 != insn; i1 = NEXT_INSN (i1))
7618 if (LABEL_P (i1) || JUMP_P (i1))
7620 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
7621 && reg_mentioned_p (reg, PATTERN (i1)))
7623 /* If this is USE in front of INSN, we only have to check that
7624 there are no more references than accounted for by inheritance. */
7625 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
7627 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7628 i1 = NEXT_INSN (i1);
7630 if (n_occurrences <= n_inherited && i1 == insn)
7636 /* We will be deleting the insn. Remove the spill reg information. */
7637 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
7639 spill_reg_store[last_reload_reg + k] = 0;
7640 spill_reg_stored_to[last_reload_reg + k] = 0;
7643 /* The caller has already checked that REG dies or is set in INSN.
7644 It has also checked that we are optimizing, and thus some
7645 inaccuracies in the debugging information are acceptable.
7646 So we could just delete output_reload_insn. But in some cases
7647 we can improve the debugging information without sacrificing
7648 optimization - maybe even improving the code: See if the pseudo
7649 reg has been completely replaced with reload regs. If so, delete
7650 the store insn and forget we had a stack slot for the pseudo. */
7651 if (rld[j].out != rld[j].in
7652 && REG_N_DEATHS (REGNO (reg)) == 1
7653 && REG_N_SETS (REGNO (reg)) == 1
7654 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7655 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7659 /* We know that it was used only between here and the beginning of
7660 the current basic block. (We also know that the last use before
7661 INSN was the output reload we are thinking of deleting, but never
7662 mind that.) Search that range; see if any ref remains. */
7663 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7665 rtx set = single_set (i2);
7667 /* Uses which just store in the pseudo don't count,
7668 since if they are the only uses, they are dead. */
7669 if (set != 0 && SET_DEST (set) == reg)
7674 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
7675 && reg_mentioned_p (reg, PATTERN (i2)))
7677 /* Some other ref remains; just delete the output reload we
7679 delete_address_reloads (output_reload_insn, insn);
7680 delete_insn (output_reload_insn);
7685 /* Delete the now-dead stores into this pseudo. Note that this
7686 loop also takes care of deleting output_reload_insn. */
7687 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7689 rtx set = single_set (i2);
7691 if (set != 0 && SET_DEST (set) == reg)
7693 delete_address_reloads (i2, insn);
7701 /* For the debugging info, say the pseudo lives in this reload reg. */
7702 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7703 alter_reg (REGNO (reg), -1);
7707 delete_address_reloads (output_reload_insn, insn);
7708 delete_insn (output_reload_insn);
7712 /* We are going to delete DEAD_INSN. Recursively delete loads of
7713 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7714 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7716 delete_address_reloads (rtx dead_insn, rtx current_insn)
7718 rtx set = single_set (dead_insn);
7719 rtx set2, dst, prev, next;
7722 rtx dst = SET_DEST (set);
7724 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7726 /* If we deleted the store from a reloaded post_{in,de}c expression,
7727 we can delete the matching adds. */
7728 prev = PREV_INSN (dead_insn);
7729 next = NEXT_INSN (dead_insn);
7730 if (! prev || ! next)
7732 set = single_set (next);
7733 set2 = single_set (prev);
7735 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7736 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7737 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7739 dst = SET_DEST (set);
7740 if (! rtx_equal_p (dst, SET_DEST (set2))
7741 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7742 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7743 || (INTVAL (XEXP (SET_SRC (set), 1))
7744 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7746 delete_related_insns (prev);
7747 delete_related_insns (next);
7750 /* Subfunction of delete_address_reloads: process registers found in X. */
7752 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
7754 rtx prev, set, dst, i2;
7756 enum rtx_code code = GET_CODE (x);
7760 const char *fmt = GET_RTX_FORMAT (code);
7761 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7764 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7765 else if (fmt[i] == 'E')
7767 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7768 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7775 if (spill_reg_order[REGNO (x)] < 0)
7778 /* Scan backwards for the insn that sets x. This might be a way back due
7780 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7782 code = GET_CODE (prev);
7783 if (code == CODE_LABEL || code == JUMP_INSN)
7787 if (reg_set_p (x, PATTERN (prev)))
7789 if (reg_referenced_p (x, PATTERN (prev)))
7792 if (! prev || INSN_UID (prev) < reload_first_uid)
7794 /* Check that PREV only sets the reload register. */
7795 set = single_set (prev);
7798 dst = SET_DEST (set);
7800 || ! rtx_equal_p (dst, x))
7802 if (! reg_set_p (dst, PATTERN (dead_insn)))
7804 /* Check if DST was used in a later insn -
7805 it might have been inherited. */
7806 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7812 if (reg_referenced_p (dst, PATTERN (i2)))
7814 /* If there is a reference to the register in the current insn,
7815 it might be loaded in a non-inherited reload. If no other
7816 reload uses it, that means the register is set before
7818 if (i2 == current_insn)
7820 for (j = n_reloads - 1; j >= 0; j--)
7821 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7822 || reload_override_in[j] == dst)
7824 for (j = n_reloads - 1; j >= 0; j--)
7825 if (rld[j].in && rld[j].reg_rtx == dst)
7834 /* If DST is still live at CURRENT_INSN, check if it is used for
7835 any reload. Note that even if CURRENT_INSN sets DST, we still
7836 have to check the reloads. */
7837 if (i2 == current_insn)
7839 for (j = n_reloads - 1; j >= 0; j--)
7840 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7841 || reload_override_in[j] == dst)
7843 /* ??? We can't finish the loop here, because dst might be
7844 allocated to a pseudo in this block if no reload in this
7845 block needs any of the classes containing DST - see
7846 spill_hard_reg. There is no easy way to tell this, so we
7847 have to scan till the end of the basic block. */
7849 if (reg_set_p (dst, PATTERN (i2)))
7853 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7854 reg_reloaded_contents[REGNO (dst)] = -1;
7858 /* Output reload-insns to reload VALUE into RELOADREG.
7859 VALUE is an autoincrement or autodecrement RTX whose operand
7860 is a register or memory location;
7861 so reloading involves incrementing that location.
7862 IN is either identical to VALUE, or some cheaper place to reload from.
7864 INC_AMOUNT is the number to increment or decrement by (always positive).
7865 This cannot be deduced from VALUE.
7867 Return the instruction that stores into RELOADREG. */
7870 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
7872 /* REG or MEM to be copied and incremented. */
7873 rtx incloc = XEXP (value, 0);
7874 /* Nonzero if increment after copying. */
7875 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7881 rtx real_in = in == value ? XEXP (in, 0) : in;
7883 /* No hard register is equivalent to this register after
7884 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7885 we could inc/dec that register as well (maybe even using it for
7886 the source), but I'm not sure it's worth worrying about. */
7888 reg_last_reload_reg[REGNO (incloc)] = 0;
7890 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7891 inc_amount = -inc_amount;
7893 inc = GEN_INT (inc_amount);
7895 /* If this is post-increment, first copy the location to the reload reg. */
7896 if (post && real_in != reloadreg)
7897 emit_insn (gen_move_insn (reloadreg, real_in));
7901 /* See if we can directly increment INCLOC. Use a method similar to
7902 that in gen_reload. */
7904 last = get_last_insn ();
7905 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7906 gen_rtx_PLUS (GET_MODE (incloc),
7909 code = recog_memoized (add_insn);
7912 extract_insn (add_insn);
7913 if (constrain_operands (1))
7915 /* If this is a pre-increment and we have incremented the value
7916 where it lives, copy the incremented value to RELOADREG to
7917 be used as an address. */
7920 emit_insn (gen_move_insn (reloadreg, incloc));
7925 delete_insns_since (last);
7928 /* If couldn't do the increment directly, must increment in RELOADREG.
7929 The way we do this depends on whether this is pre- or post-increment.
7930 For pre-increment, copy INCLOC to the reload register, increment it
7931 there, then save back. */
7935 if (in != reloadreg)
7936 emit_insn (gen_move_insn (reloadreg, real_in));
7937 emit_insn (gen_add2_insn (reloadreg, inc));
7938 store = emit_insn (gen_move_insn (incloc, reloadreg));
7943 Because this might be a jump insn or a compare, and because RELOADREG
7944 may not be available after the insn in an input reload, we must do
7945 the incrementation before the insn being reloaded for.
7947 We have already copied IN to RELOADREG. Increment the copy in
7948 RELOADREG, save that back, then decrement RELOADREG so it has
7949 the original value. */
7951 emit_insn (gen_add2_insn (reloadreg, inc));
7952 store = emit_insn (gen_move_insn (incloc, reloadreg));
7953 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7961 add_auto_inc_notes (rtx insn, rtx x)
7963 enum rtx_code code = GET_CODE (x);
7967 if (code == MEM && auto_inc_p (XEXP (x, 0)))
7970 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
7974 /* Scan all the operand sub-expressions. */
7975 fmt = GET_RTX_FORMAT (code);
7976 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7979 add_auto_inc_notes (insn, XEXP (x, i));
7980 else if (fmt[i] == 'E')
7981 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7982 add_auto_inc_notes (insn, XVECEXP (x, i, j));
7987 /* Copy EH notes from an insn to its reloads. */
7989 copy_eh_notes (rtx insn, rtx x)
7991 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
7994 for (; x != 0; x = NEXT_INSN (x))
7996 if (may_trap_p (PATTERN (x)))
7998 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8004 /* This is used by reload pass, that does emit some instructions after
8005 abnormal calls moving basic block end, but in fact it wants to emit
8006 them on the edge. Looks for abnormal call edges, find backward the
8007 proper call and fix the damage.
8009 Similar handle instructions throwing exceptions internally. */
8011 fixup_abnormal_edges (void)
8013 bool inserted = false;
8021 /* Look for cases we are interested in - calls or instructions causing
8023 FOR_EACH_EDGE (e, ei, bb->succs)
8025 if (e->flags & EDGE_ABNORMAL_CALL)
8027 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8028 == (EDGE_ABNORMAL | EDGE_EH))
8031 if (e && !CALL_P (BB_END (bb))
8032 && !can_throw_internal (BB_END (bb)))
8034 rtx insn = BB_END (bb), stop = NEXT_INSN (BB_END (bb));
8036 FOR_EACH_EDGE (e, ei, bb->succs)
8037 if (e->flags & EDGE_FALLTHRU)
8039 /* Get past the new insns generated. Allow notes, as the insns may
8040 be already deleted. */
8041 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8042 && !can_throw_internal (insn)
8043 && insn != BB_HEAD (bb))
8044 insn = PREV_INSN (insn);
8045 gcc_assert (CALL_P (insn) || can_throw_internal (insn));
8048 insn = NEXT_INSN (insn);
8049 while (insn && insn != stop)
8051 next = NEXT_INSN (insn);
8056 /* Sometimes there's still the return value USE.
8057 If it's placed after a trapping call (i.e. that
8058 call is the last insn anyway), we have no fallthru
8059 edge. Simply delete this use and don't try to insert
8060 on the non-existent edge. */
8061 if (GET_CODE (PATTERN (insn)) != USE)
8063 /* We're not deleting it, we're moving it. */
8064 INSN_DELETED_P (insn) = 0;
8065 PREV_INSN (insn) = NULL_RTX;
8066 NEXT_INSN (insn) = NULL_RTX;
8068 insert_insn_on_edge (insn, e);
8075 /* We've possibly turned single trapping insn into multiple ones. */
8076 if (flag_non_call_exceptions)
8079 blocks = sbitmap_alloc (last_basic_block);
8080 sbitmap_ones (blocks);
8081 find_many_sub_basic_blocks (blocks);
8084 commit_edge_insertions ();
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