1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation,
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
33 #include "insn-config.h"
39 #include "basic-block.h"
49 /* This file contains the reload pass of the compiler, which is
50 run after register allocation has been done. It checks that
51 each insn is valid (operands required to be in registers really
52 are in registers of the proper class) and fixes up invalid ones
53 by copying values temporarily into registers for the insns
56 The results of register allocation are described by the vector
57 reg_renumber; the insns still contain pseudo regs, but reg_renumber
58 can be used to find which hard reg, if any, a pseudo reg is in.
60 The technique we always use is to free up a few hard regs that are
61 called ``reload regs'', and for each place where a pseudo reg
62 must be in a hard reg, copy it temporarily into one of the reload regs.
64 Reload regs are allocated locally for every instruction that needs
65 reloads. When there are pseudos which are allocated to a register that
66 has been chosen as a reload reg, such pseudos must be ``spilled''.
67 This means that they go to other hard regs, or to stack slots if no other
68 available hard regs can be found. Spilling can invalidate more
69 insns, requiring additional need for reloads, so we must keep checking
70 until the process stabilizes.
72 For machines with different classes of registers, we must keep track
73 of the register class needed for each reload, and make sure that
74 we allocate enough reload registers of each class.
76 The file reload.c contains the code that checks one insn for
77 validity and reports the reloads that it needs. This file
78 is in charge of scanning the entire rtl code, accumulating the
79 reload needs, spilling, assigning reload registers to use for
80 fixing up each insn, and generating the new insns to copy values
81 into the reload registers. */
83 /* During reload_as_needed, element N contains a REG rtx for the hard reg
84 into which reg N has been reloaded (perhaps for a previous insn). */
85 static rtx *reg_last_reload_reg;
87 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
88 for an output reload that stores into reg N. */
89 static char *reg_has_output_reload;
91 /* Indicates which hard regs are reload-registers for an output reload
92 in the current insn. */
93 static HARD_REG_SET reg_is_output_reload;
95 /* Element N is the constant value to which pseudo reg N is equivalent,
96 or zero if pseudo reg N is not equivalent to a constant.
97 find_reloads looks at this in order to replace pseudo reg N
98 with the constant it stands for. */
99 rtx *reg_equiv_constant;
101 /* Element N is an invariant value to which pseudo reg N is equivalent.
102 eliminate_regs_in_insn uses this to replace pseudos in particular
104 rtx *reg_equiv_invariant;
106 /* Element N is a memory location to which pseudo reg N is equivalent,
107 prior to any register elimination (such as frame pointer to stack
108 pointer). Depending on whether or not it is a valid address, this value
109 is transferred to either reg_equiv_address or reg_equiv_mem. */
110 rtx *reg_equiv_memory_loc;
112 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
113 collector can keep track of what is inside. */
114 varray_type reg_equiv_memory_loc_varray;
116 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
117 This is used when the address is not valid as a memory address
118 (because its displacement is too big for the machine.) */
119 rtx *reg_equiv_address;
121 /* Element N is the memory slot to which pseudo reg N is equivalent,
122 or zero if pseudo reg N is not equivalent to a memory slot. */
125 /* Widest width in which each pseudo reg is referred to (via subreg). */
126 static unsigned int *reg_max_ref_width;
128 /* Element N is the list of insns that initialized reg N from its equivalent
129 constant or memory slot. */
131 int reg_equiv_init_size;
133 /* Vector to remember old contents of reg_renumber before spilling. */
134 static short *reg_old_renumber;
136 /* During reload_as_needed, element N contains the last pseudo regno reloaded
137 into hard register N. If that pseudo reg occupied more than one register,
138 reg_reloaded_contents points to that pseudo for each spill register in
139 use; all of these must remain set for an inheritance to occur. */
140 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
142 /* During reload_as_needed, element N contains the insn for which
143 hard register N was last used. Its contents are significant only
144 when reg_reloaded_valid is set for this register. */
145 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
147 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
148 static HARD_REG_SET reg_reloaded_valid;
149 /* Indicate if the register was dead at the end of the reload.
150 This is only valid if reg_reloaded_contents is set and valid. */
151 static HARD_REG_SET reg_reloaded_dead;
153 /* Indicate whether the register's current value is one that is not
154 safe to retain across a call, even for registers that are normally
156 static HARD_REG_SET reg_reloaded_call_part_clobbered;
158 /* Number of spill-regs so far; number of valid elements of spill_regs. */
161 /* In parallel with spill_regs, contains REG rtx's for those regs.
162 Holds the last rtx used for any given reg, or 0 if it has never
163 been used for spilling yet. This rtx is reused, provided it has
165 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
167 /* In parallel with spill_regs, contains nonzero for a spill reg
168 that was stored after the last time it was used.
169 The precise value is the insn generated to do the store. */
170 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
172 /* This is the register that was stored with spill_reg_store. This is a
173 copy of reload_out / reload_out_reg when the value was stored; if
174 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
175 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
177 /* This table is the inverse mapping of spill_regs:
178 indexed by hard reg number,
179 it contains the position of that reg in spill_regs,
180 or -1 for something that is not in spill_regs.
182 ?!? This is no longer accurate. */
183 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
185 /* This reg set indicates registers that can't be used as spill registers for
186 the currently processed insn. These are the hard registers which are live
187 during the insn, but not allocated to pseudos, as well as fixed
189 static HARD_REG_SET bad_spill_regs;
191 /* These are the hard registers that can't be used as spill register for any
192 insn. This includes registers used for user variables and registers that
193 we can't eliminate. A register that appears in this set also can't be used
194 to retry register allocation. */
195 static HARD_REG_SET bad_spill_regs_global;
197 /* Describes order of use of registers for reloading
198 of spilled pseudo-registers. `n_spills' is the number of
199 elements that are actually valid; new ones are added at the end.
201 Both spill_regs and spill_reg_order are used on two occasions:
202 once during find_reload_regs, where they keep track of the spill registers
203 for a single insn, but also during reload_as_needed where they show all
204 the registers ever used by reload. For the latter case, the information
205 is calculated during finish_spills. */
206 static short spill_regs[FIRST_PSEUDO_REGISTER];
208 /* This vector of reg sets indicates, for each pseudo, which hard registers
209 may not be used for retrying global allocation because the register was
210 formerly spilled from one of them. If we allowed reallocating a pseudo to
211 a register that it was already allocated to, reload might not
213 static HARD_REG_SET *pseudo_previous_regs;
215 /* This vector of reg sets indicates, for each pseudo, which hard
216 registers may not be used for retrying global allocation because they
217 are used as spill registers during one of the insns in which the
219 static HARD_REG_SET *pseudo_forbidden_regs;
221 /* All hard regs that have been used as spill registers for any insn are
222 marked in this set. */
223 static HARD_REG_SET used_spill_regs;
225 /* Index of last register assigned as a spill register. We allocate in
226 a round-robin fashion. */
227 static int last_spill_reg;
229 /* Nonzero if indirect addressing is supported on the machine; this means
230 that spilling (REG n) does not require reloading it into a register in
231 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
232 value indicates the level of indirect addressing supported, e.g., two
233 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
235 static char spill_indirect_levels;
237 /* Nonzero if indirect addressing is supported when the innermost MEM is
238 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
239 which these are valid is the same as spill_indirect_levels, above. */
240 char indirect_symref_ok;
242 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
243 char double_reg_address_ok;
245 /* Record the stack slot for each spilled hard register. */
246 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
248 /* Width allocated so far for that stack slot. */
249 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
251 /* Record which pseudos needed to be spilled. */
252 static regset_head spilled_pseudos;
254 /* Used for communication between order_regs_for_reload and count_pseudo.
255 Used to avoid counting one pseudo twice. */
256 static regset_head pseudos_counted;
258 /* First uid used by insns created by reload in this function.
259 Used in find_equiv_reg. */
260 int reload_first_uid;
262 /* Flag set by local-alloc or global-alloc if anything is live in
263 a call-clobbered reg across calls. */
264 int caller_save_needed;
266 /* Set to 1 while reload_as_needed is operating.
267 Required by some machines to handle any generated moves differently. */
268 int reload_in_progress = 0;
270 /* These arrays record the insn_code of insns that may be needed to
271 perform input and output reloads of special objects. They provide a
272 place to pass a scratch register. */
273 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
274 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
276 /* This obstack is used for allocation of rtl during register elimination.
277 The allocated storage can be freed once find_reloads has processed the
279 static struct obstack reload_obstack;
281 /* Points to the beginning of the reload_obstack. All insn_chain structures
282 are allocated first. */
283 static char *reload_startobj;
285 /* The point after all insn_chain structures. Used to quickly deallocate
286 memory allocated in copy_reloads during calculate_needs_all_insns. */
287 static char *reload_firstobj;
289 /* This points before all local rtl generated by register elimination.
290 Used to quickly free all memory after processing one insn. */
291 static char *reload_insn_firstobj;
293 /* List of insn_chain instructions, one for every insn that reload needs to
295 struct insn_chain *reload_insn_chain;
297 /* List of all insns needing reloads. */
298 static struct insn_chain *insns_need_reload;
300 /* This structure is used to record information about register eliminations.
301 Each array entry describes one possible way of eliminating a register
302 in favor of another. If there is more than one way of eliminating a
303 particular register, the most preferred should be specified first. */
307 int from; /* Register number to be eliminated. */
308 int to; /* Register number used as replacement. */
309 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
310 int can_eliminate; /* Nonzero if this elimination can be done. */
311 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
312 insns made by reload. */
313 HOST_WIDE_INT offset; /* Current offset between the two regs. */
314 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
315 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
316 rtx from_rtx; /* REG rtx for the register to be eliminated.
317 We cannot simply compare the number since
318 we might then spuriously replace a hard
319 register corresponding to a pseudo
320 assigned to the reg to be eliminated. */
321 rtx to_rtx; /* REG rtx for the replacement. */
324 static struct elim_table *reg_eliminate = 0;
326 /* This is an intermediate structure to initialize the table. It has
327 exactly the members provided by ELIMINABLE_REGS. */
328 static const struct elim_table_1
332 } reg_eliminate_1[] =
334 /* If a set of eliminable registers was specified, define the table from it.
335 Otherwise, default to the normal case of the frame pointer being
336 replaced by the stack pointer. */
338 #ifdef ELIMINABLE_REGS
341 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
344 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
346 /* Record the number of pending eliminations that have an offset not equal
347 to their initial offset. If nonzero, we use a new copy of each
348 replacement result in any insns encountered. */
349 int num_not_at_initial_offset;
351 /* Count the number of registers that we may be able to eliminate. */
352 static int num_eliminable;
353 /* And the number of registers that are equivalent to a constant that
354 can be eliminated to frame_pointer / arg_pointer + constant. */
355 static int num_eliminable_invariants;
357 /* For each label, we record the offset of each elimination. If we reach
358 a label by more than one path and an offset differs, we cannot do the
359 elimination. This information is indexed by the difference of the
360 number of the label and the first label number. We can't offset the
361 pointer itself as this can cause problems on machines with segmented
362 memory. The first table is an array of flags that records whether we
363 have yet encountered a label and the second table is an array of arrays,
364 one entry in the latter array for each elimination. */
366 static int first_label_num;
367 static char *offsets_known_at;
368 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
370 /* Number of labels in the current function. */
372 static int num_labels;
374 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
375 static void maybe_fix_stack_asms (void);
376 static void copy_reloads (struct insn_chain *);
377 static void calculate_needs_all_insns (int);
378 static int find_reg (struct insn_chain *, int);
379 static void find_reload_regs (struct insn_chain *);
380 static void select_reload_regs (void);
381 static void delete_caller_save_insns (void);
383 static void spill_failure (rtx, enum reg_class);
384 static void count_spilled_pseudo (int, int, int);
385 static void delete_dead_insn (rtx);
386 static void alter_reg (int, int);
387 static void set_label_offsets (rtx, rtx, int);
388 static void check_eliminable_occurrences (rtx);
389 static void elimination_effects (rtx, enum machine_mode);
390 static int eliminate_regs_in_insn (rtx, int);
391 static void update_eliminable_offsets (void);
392 static void mark_not_eliminable (rtx, rtx, void *);
393 static void set_initial_elim_offsets (void);
394 static bool verify_initial_elim_offsets (void);
395 static void set_initial_label_offsets (void);
396 static void set_offsets_for_label (rtx);
397 static void init_elim_table (void);
398 static void update_eliminables (HARD_REG_SET *);
399 static void spill_hard_reg (unsigned int, int);
400 static int finish_spills (int);
401 static void scan_paradoxical_subregs (rtx);
402 static void count_pseudo (int);
403 static void order_regs_for_reload (struct insn_chain *);
404 static void reload_as_needed (int);
405 static void forget_old_reloads_1 (rtx, rtx, void *);
406 static int reload_reg_class_lower (const void *, const void *);
407 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
409 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
411 static int reload_reg_free_p (unsigned int, int, enum reload_type);
412 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
414 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
416 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
417 static int allocate_reload_reg (struct insn_chain *, int, int);
418 static int conflicts_with_override (rtx);
419 static void failed_reload (rtx, int);
420 static int set_reload_reg (int, int);
421 static void choose_reload_regs_init (struct insn_chain *, rtx *);
422 static void choose_reload_regs (struct insn_chain *);
423 static void merge_assigned_reloads (rtx);
424 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
426 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
428 static void do_input_reload (struct insn_chain *, struct reload *, int);
429 static void do_output_reload (struct insn_chain *, struct reload *, int);
430 static bool inherit_piecemeal_p (int, int);
431 static void emit_reload_insns (struct insn_chain *);
432 static void delete_output_reload (rtx, int, int);
433 static void delete_address_reloads (rtx, rtx);
434 static void delete_address_reloads_1 (rtx, rtx, rtx);
435 static rtx inc_for_reload (rtx, rtx, rtx, int);
437 static void add_auto_inc_notes (rtx, rtx);
439 static void copy_eh_notes (rtx, rtx);
440 static int reloads_conflict (int, int);
441 static rtx gen_reload (rtx, rtx, int, enum reload_type);
442 static rtx emit_insn_if_valid_for_reload (rtx);
444 /* Initialize the reload pass once per compilation. */
451 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
452 Set spill_indirect_levels to the number of levels such addressing is
453 permitted, zero if it is not permitted at all. */
456 = gen_rtx_MEM (Pmode,
459 LAST_VIRTUAL_REGISTER + 1),
461 spill_indirect_levels = 0;
463 while (memory_address_p (QImode, tem))
465 spill_indirect_levels++;
466 tem = gen_rtx_MEM (Pmode, tem);
469 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
471 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
472 indirect_symref_ok = memory_address_p (QImode, tem);
474 /* See if reg+reg is a valid (and offsettable) address. */
476 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
478 tem = gen_rtx_PLUS (Pmode,
479 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
480 gen_rtx_REG (Pmode, i));
482 /* This way, we make sure that reg+reg is an offsettable address. */
483 tem = plus_constant (tem, 4);
485 if (memory_address_p (QImode, tem))
487 double_reg_address_ok = 1;
492 /* Initialize obstack for our rtl allocation. */
493 gcc_obstack_init (&reload_obstack);
494 reload_startobj = obstack_alloc (&reload_obstack, 0);
496 INIT_REG_SET (&spilled_pseudos);
497 INIT_REG_SET (&pseudos_counted);
498 VARRAY_RTX_INIT (reg_equiv_memory_loc_varray, 0, "reg_equiv_memory_loc");
501 /* List of insn chains that are currently unused. */
502 static struct insn_chain *unused_insn_chains = 0;
504 /* Allocate an empty insn_chain structure. */
506 new_insn_chain (void)
508 struct insn_chain *c;
510 if (unused_insn_chains == 0)
512 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
513 INIT_REG_SET (&c->live_throughout);
514 INIT_REG_SET (&c->dead_or_set);
518 c = unused_insn_chains;
519 unused_insn_chains = c->next;
521 c->is_caller_save_insn = 0;
522 c->need_operand_change = 0;
528 /* Small utility function to set all regs in hard reg set TO which are
529 allocated to pseudos in regset FROM. */
532 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
535 reg_set_iterator rsi;
537 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
539 int r = reg_renumber[regno];
544 /* reload_combine uses the information from
545 BASIC_BLOCK->global_live_at_start, which might still
546 contain registers that have not actually been allocated
547 since they have an equivalence. */
548 gcc_assert (reload_completed);
552 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
554 SET_HARD_REG_BIT (*to, r + nregs);
559 /* Replace all pseudos found in LOC with their corresponding
563 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
576 unsigned int regno = REGNO (x);
578 if (regno < FIRST_PSEUDO_REGISTER)
581 x = eliminate_regs (x, mem_mode, usage);
585 replace_pseudos_in (loc, mem_mode, usage);
589 if (reg_equiv_constant[regno])
590 *loc = reg_equiv_constant[regno];
591 else if (reg_equiv_mem[regno])
592 *loc = reg_equiv_mem[regno];
593 else if (reg_equiv_address[regno])
594 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
597 gcc_assert (!REG_P (regno_reg_rtx[regno])
598 || REGNO (regno_reg_rtx[regno]) != regno);
599 *loc = regno_reg_rtx[regno];
604 else if (code == MEM)
606 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
610 /* Process each of our operands recursively. */
611 fmt = GET_RTX_FORMAT (code);
612 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
614 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
615 else if (*fmt == 'E')
616 for (j = 0; j < XVECLEN (x, i); j++)
617 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
621 /* Global variables used by reload and its subroutines. */
623 /* Set during calculate_needs if an insn needs register elimination. */
624 static int something_needs_elimination;
625 /* Set during calculate_needs if an insn needs an operand changed. */
626 static int something_needs_operands_changed;
628 /* Nonzero means we couldn't get enough spill regs. */
631 /* Main entry point for the reload pass.
633 FIRST is the first insn of the function being compiled.
635 GLOBAL nonzero means we were called from global_alloc
636 and should attempt to reallocate any pseudoregs that we
637 displace from hard regs we will use for reloads.
638 If GLOBAL is zero, we do not have enough information to do that,
639 so any pseudo reg that is spilled must go to the stack.
641 Return value is nonzero if reload failed
642 and we must not do any more for this function. */
645 reload (rtx first, int global)
649 struct elim_table *ep;
652 /* Make sure even insns with volatile mem refs are recognizable. */
657 reload_firstobj = obstack_alloc (&reload_obstack, 0);
659 /* Make sure that the last insn in the chain
660 is not something that needs reloading. */
661 emit_note (NOTE_INSN_DELETED);
663 /* Enable find_equiv_reg to distinguish insns made by reload. */
664 reload_first_uid = get_max_uid ();
666 #ifdef SECONDARY_MEMORY_NEEDED
667 /* Initialize the secondary memory table. */
668 clear_secondary_mem ();
671 /* We don't have a stack slot for any spill reg yet. */
672 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
673 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
675 /* Initialize the save area information for caller-save, in case some
679 /* Compute which hard registers are now in use
680 as homes for pseudo registers.
681 This is done here rather than (eg) in global_alloc
682 because this point is reached even if not optimizing. */
683 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
686 /* A function that receives a nonlocal goto must save all call-saved
688 if (current_function_has_nonlocal_label)
689 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
690 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
691 regs_ever_live[i] = 1;
693 /* Find all the pseudo registers that didn't get hard regs
694 but do have known equivalent constants or memory slots.
695 These include parameters (known equivalent to parameter slots)
696 and cse'd or loop-moved constant memory addresses.
698 Record constant equivalents in reg_equiv_constant
699 so they will be substituted by find_reloads.
700 Record memory equivalents in reg_mem_equiv so they can
701 be substituted eventually by altering the REG-rtx's. */
703 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
704 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
705 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
706 reg_equiv_address = XCNEWVEC (rtx, max_regno);
707 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
708 reg_old_renumber = XCNEWVEC (short, max_regno);
709 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
710 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
711 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
713 CLEAR_HARD_REG_SET (bad_spill_regs_global);
715 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
716 to. Also find all paradoxical subregs and find largest such for
719 num_eliminable_invariants = 0;
720 for (insn = first; insn; insn = NEXT_INSN (insn))
722 rtx set = single_set (insn);
724 /* We may introduce USEs that we want to remove at the end, so
725 we'll mark them with QImode. Make sure there are no
726 previously-marked insns left by say regmove. */
727 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
728 && GET_MODE (insn) != VOIDmode)
729 PUT_MODE (insn, VOIDmode);
732 scan_paradoxical_subregs (PATTERN (insn));
734 if (set != 0 && REG_P (SET_DEST (set)))
736 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
742 i = REGNO (SET_DEST (set));
745 if (i <= LAST_VIRTUAL_REGISTER)
748 if (! function_invariant_p (x)
750 /* A function invariant is often CONSTANT_P but may
751 include a register. We promise to only pass
752 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
754 && LEGITIMATE_PIC_OPERAND_P (x)))
756 /* It can happen that a REG_EQUIV note contains a MEM
757 that is not a legitimate memory operand. As later
758 stages of reload assume that all addresses found
759 in the reg_equiv_* arrays were originally legitimate,
760 we ignore such REG_EQUIV notes. */
761 if (memory_operand (x, VOIDmode))
763 /* Always unshare the equivalence, so we can
764 substitute into this insn without touching the
766 reg_equiv_memory_loc[i] = copy_rtx (x);
768 else if (function_invariant_p (x))
770 if (GET_CODE (x) == PLUS)
772 /* This is PLUS of frame pointer and a constant,
773 and might be shared. Unshare it. */
774 reg_equiv_invariant[i] = copy_rtx (x);
775 num_eliminable_invariants++;
777 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
779 reg_equiv_invariant[i] = x;
780 num_eliminable_invariants++;
782 else if (LEGITIMATE_CONSTANT_P (x))
783 reg_equiv_constant[i] = x;
786 reg_equiv_memory_loc[i]
787 = force_const_mem (GET_MODE (SET_DEST (set)), x);
788 if (! reg_equiv_memory_loc[i])
789 reg_equiv_init[i] = NULL_RTX;
794 reg_equiv_init[i] = NULL_RTX;
799 reg_equiv_init[i] = NULL_RTX;
804 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
805 if (reg_equiv_init[i])
807 fprintf (dump_file, "init_insns for %u: ", i);
808 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
809 fprintf (dump_file, "\n");
814 first_label_num = get_first_label_num ();
815 num_labels = max_label_num () - first_label_num;
817 /* Allocate the tables used to store offset information at labels. */
818 /* We used to use alloca here, but the size of what it would try to
819 allocate would occasionally cause it to exceed the stack limit and
820 cause a core dump. */
821 offsets_known_at = XNEWVEC (char, num_labels);
822 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
824 /* Alter each pseudo-reg rtx to contain its hard reg number.
825 Assign stack slots to the pseudos that lack hard regs or equivalents.
826 Do not touch virtual registers. */
828 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
831 /* If we have some registers we think can be eliminated, scan all insns to
832 see if there is an insn that sets one of these registers to something
833 other than itself plus a constant. If so, the register cannot be
834 eliminated. Doing this scan here eliminates an extra pass through the
835 main reload loop in the most common case where register elimination
837 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
839 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
841 maybe_fix_stack_asms ();
843 insns_need_reload = 0;
844 something_needs_elimination = 0;
846 /* Initialize to -1, which means take the first spill register. */
849 /* Spill any hard regs that we know we can't eliminate. */
850 CLEAR_HARD_REG_SET (used_spill_regs);
851 /* There can be multiple ways to eliminate a register;
852 they should be listed adjacently.
853 Elimination for any register fails only if all possible ways fail. */
854 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
857 int can_eliminate = 0;
860 can_eliminate |= ep->can_eliminate;
863 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
865 spill_hard_reg (from, 1);
868 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
869 if (frame_pointer_needed)
870 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
872 finish_spills (global);
874 /* From now on, we may need to generate moves differently. We may also
875 allow modifications of insns which cause them to not be recognized.
876 Any such modifications will be cleaned up during reload itself. */
877 reload_in_progress = 1;
879 /* This loop scans the entire function each go-round
880 and repeats until one repetition spills no additional hard regs. */
883 int something_changed;
886 HOST_WIDE_INT starting_frame_size;
888 /* Round size of stack frame to stack_alignment_needed. This must be done
889 here because the stack size may be a part of the offset computation
890 for register elimination, and there might have been new stack slots
891 created in the last iteration of this loop. */
892 if (cfun->stack_alignment_needed)
893 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
895 starting_frame_size = get_frame_size ();
897 set_initial_elim_offsets ();
898 set_initial_label_offsets ();
900 /* For each pseudo register that has an equivalent location defined,
901 try to eliminate any eliminable registers (such as the frame pointer)
902 assuming initial offsets for the replacement register, which
905 If the resulting location is directly addressable, substitute
906 the MEM we just got directly for the old REG.
908 If it is not addressable but is a constant or the sum of a hard reg
909 and constant, it is probably not addressable because the constant is
910 out of range, in that case record the address; we will generate
911 hairy code to compute the address in a register each time it is
912 needed. Similarly if it is a hard register, but one that is not
913 valid as an address register.
915 If the location is not addressable, but does not have one of the
916 above forms, assign a stack slot. We have to do this to avoid the
917 potential of producing lots of reloads if, e.g., a location involves
918 a pseudo that didn't get a hard register and has an equivalent memory
919 location that also involves a pseudo that didn't get a hard register.
921 Perhaps at some point we will improve reload_when_needed handling
922 so this problem goes away. But that's very hairy. */
924 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
925 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
927 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
929 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
931 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
932 else if (CONSTANT_P (XEXP (x, 0))
933 || (REG_P (XEXP (x, 0))
934 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
935 || (GET_CODE (XEXP (x, 0)) == PLUS
936 && REG_P (XEXP (XEXP (x, 0), 0))
937 && (REGNO (XEXP (XEXP (x, 0), 0))
938 < FIRST_PSEUDO_REGISTER)
939 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
940 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
943 /* Make a new stack slot. Then indicate that something
944 changed so we go back and recompute offsets for
945 eliminable registers because the allocation of memory
946 below might change some offset. reg_equiv_{mem,address}
947 will be set up for this pseudo on the next pass around
949 reg_equiv_memory_loc[i] = 0;
950 reg_equiv_init[i] = 0;
955 if (caller_save_needed)
958 /* If we allocated another stack slot, redo elimination bookkeeping. */
959 if (starting_frame_size != get_frame_size ())
962 if (caller_save_needed)
964 save_call_clobbered_regs ();
965 /* That might have allocated new insn_chain structures. */
966 reload_firstobj = obstack_alloc (&reload_obstack, 0);
969 calculate_needs_all_insns (global);
971 CLEAR_REG_SET (&spilled_pseudos);
974 something_changed = 0;
976 /* If we allocated any new memory locations, make another pass
977 since it might have changed elimination offsets. */
978 if (starting_frame_size != get_frame_size ())
979 something_changed = 1;
981 /* Even if the frame size remained the same, we might still have
982 changed elimination offsets, e.g. if find_reloads called
983 force_const_mem requiring the back end to allocate a constant
984 pool base register that needs to be saved on the stack. */
985 else if (!verify_initial_elim_offsets ())
986 something_changed = 1;
989 HARD_REG_SET to_spill;
990 CLEAR_HARD_REG_SET (to_spill);
991 update_eliminables (&to_spill);
992 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
993 if (TEST_HARD_REG_BIT (to_spill, i))
995 spill_hard_reg (i, 1);
998 /* Regardless of the state of spills, if we previously had
999 a register that we thought we could eliminate, but now can
1000 not eliminate, we must run another pass.
1002 Consider pseudos which have an entry in reg_equiv_* which
1003 reference an eliminable register. We must make another pass
1004 to update reg_equiv_* so that we do not substitute in the
1005 old value from when we thought the elimination could be
1007 something_changed = 1;
1011 select_reload_regs ();
1015 if (insns_need_reload != 0 || did_spill)
1016 something_changed |= finish_spills (global);
1018 if (! something_changed)
1021 if (caller_save_needed)
1022 delete_caller_save_insns ();
1024 obstack_free (&reload_obstack, reload_firstobj);
1027 /* If global-alloc was run, notify it of any register eliminations we have
1030 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1031 if (ep->can_eliminate)
1032 mark_elimination (ep->from, ep->to);
1034 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1035 If that insn didn't set the register (i.e., it copied the register to
1036 memory), just delete that insn instead of the equivalencing insn plus
1037 anything now dead. If we call delete_dead_insn on that insn, we may
1038 delete the insn that actually sets the register if the register dies
1039 there and that is incorrect. */
1041 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1043 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1046 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1048 rtx equiv_insn = XEXP (list, 0);
1050 /* If we already deleted the insn or if it may trap, we can't
1051 delete it. The latter case shouldn't happen, but can
1052 if an insn has a variable address, gets a REG_EH_REGION
1053 note added to it, and then gets converted into a load
1054 from a constant address. */
1055 if (NOTE_P (equiv_insn)
1056 || can_throw_internal (equiv_insn))
1058 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1059 delete_dead_insn (equiv_insn);
1061 SET_INSN_DELETED (equiv_insn);
1066 /* Use the reload registers where necessary
1067 by generating move instructions to move the must-be-register
1068 values into or out of the reload registers. */
1070 if (insns_need_reload != 0 || something_needs_elimination
1071 || something_needs_operands_changed)
1073 HOST_WIDE_INT old_frame_size = get_frame_size ();
1075 reload_as_needed (global);
1077 gcc_assert (old_frame_size == get_frame_size ());
1079 gcc_assert (verify_initial_elim_offsets ());
1082 /* If we were able to eliminate the frame pointer, show that it is no
1083 longer live at the start of any basic block. If it ls live by
1084 virtue of being in a pseudo, that pseudo will be marked live
1085 and hence the frame pointer will be known to be live via that
1088 if (! frame_pointer_needed)
1090 CLEAR_REGNO_REG_SET (bb->il.rtl->global_live_at_start,
1091 HARD_FRAME_POINTER_REGNUM);
1093 /* Come here (with failure set nonzero) if we can't get enough spill
1097 CLEAR_REG_SET (&spilled_pseudos);
1098 reload_in_progress = 0;
1100 /* Now eliminate all pseudo regs by modifying them into
1101 their equivalent memory references.
1102 The REG-rtx's for the pseudos are modified in place,
1103 so all insns that used to refer to them now refer to memory.
1105 For a reg that has a reg_equiv_address, all those insns
1106 were changed by reloading so that no insns refer to it any longer;
1107 but the DECL_RTL of a variable decl may refer to it,
1108 and if so this causes the debugging info to mention the variable. */
1110 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1114 if (reg_equiv_mem[i])
1115 addr = XEXP (reg_equiv_mem[i], 0);
1117 if (reg_equiv_address[i])
1118 addr = reg_equiv_address[i];
1122 if (reg_renumber[i] < 0)
1124 rtx reg = regno_reg_rtx[i];
1126 REG_USERVAR_P (reg) = 0;
1127 PUT_CODE (reg, MEM);
1128 XEXP (reg, 0) = addr;
1129 if (reg_equiv_memory_loc[i])
1130 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1133 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1134 MEM_ATTRS (reg) = 0;
1136 MEM_NOTRAP_P (reg) = 1;
1138 else if (reg_equiv_mem[i])
1139 XEXP (reg_equiv_mem[i], 0) = addr;
1143 /* We must set reload_completed now since the cleanup_subreg_operands call
1144 below will re-recognize each insn and reload may have generated insns
1145 which are only valid during and after reload. */
1146 reload_completed = 1;
1148 /* Make a pass over all the insns and delete all USEs which we inserted
1149 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1150 notes. Delete all CLOBBER insns, except those that refer to the return
1151 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1152 from misarranging variable-array code, and simplify (subreg (reg))
1153 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1154 are no longer useful or accurate. Strip and regenerate REG_INC notes
1155 that may have been moved around. */
1157 for (insn = first; insn; insn = NEXT_INSN (insn))
1163 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1164 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1166 if ((GET_CODE (PATTERN (insn)) == USE
1167 /* We mark with QImode USEs introduced by reload itself. */
1168 && (GET_MODE (insn) == QImode
1169 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1170 || (GET_CODE (PATTERN (insn)) == CLOBBER
1171 && (!MEM_P (XEXP (PATTERN (insn), 0))
1172 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1173 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1174 && XEXP (XEXP (PATTERN (insn), 0), 0)
1175 != stack_pointer_rtx))
1176 && (!REG_P (XEXP (PATTERN (insn), 0))
1177 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1183 /* Some CLOBBERs may survive until here and still reference unassigned
1184 pseudos with const equivalent, which may in turn cause ICE in later
1185 passes if the reference remains in place. */
1186 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1187 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1188 VOIDmode, PATTERN (insn));
1190 /* Discard obvious no-ops, even without -O. This optimization
1191 is fast and doesn't interfere with debugging. */
1192 if (NONJUMP_INSN_P (insn)
1193 && GET_CODE (PATTERN (insn)) == SET
1194 && REG_P (SET_SRC (PATTERN (insn)))
1195 && REG_P (SET_DEST (PATTERN (insn)))
1196 && (REGNO (SET_SRC (PATTERN (insn)))
1197 == REGNO (SET_DEST (PATTERN (insn)))))
1203 pnote = ®_NOTES (insn);
1206 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1207 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1208 || REG_NOTE_KIND (*pnote) == REG_INC
1209 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1210 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1211 *pnote = XEXP (*pnote, 1);
1213 pnote = &XEXP (*pnote, 1);
1217 add_auto_inc_notes (insn, PATTERN (insn));
1220 /* And simplify (subreg (reg)) if it appears as an operand. */
1221 cleanup_subreg_operands (insn);
1224 /* If we are doing stack checking, give a warning if this function's
1225 frame size is larger than we expect. */
1226 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1228 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1229 static int verbose_warned = 0;
1231 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1232 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1233 size += UNITS_PER_WORD;
1235 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1237 warning (0, "frame size too large for reliable stack checking");
1238 if (! verbose_warned)
1240 warning (0, "try reducing the number of local variables");
1246 /* Indicate that we no longer have known memory locations or constants. */
1247 if (reg_equiv_constant)
1248 free (reg_equiv_constant);
1249 if (reg_equiv_invariant)
1250 free (reg_equiv_invariant);
1251 reg_equiv_constant = 0;
1252 reg_equiv_invariant = 0;
1253 VARRAY_GROW (reg_equiv_memory_loc_varray, 0);
1254 reg_equiv_memory_loc = 0;
1256 if (offsets_known_at)
1257 free (offsets_known_at);
1261 free (reg_equiv_mem);
1263 free (reg_equiv_address);
1264 free (reg_max_ref_width);
1265 free (reg_old_renumber);
1266 free (pseudo_previous_regs);
1267 free (pseudo_forbidden_regs);
1269 CLEAR_HARD_REG_SET (used_spill_regs);
1270 for (i = 0; i < n_spills; i++)
1271 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1273 /* Free all the insn_chain structures at once. */
1274 obstack_free (&reload_obstack, reload_startobj);
1275 unused_insn_chains = 0;
1276 fixup_abnormal_edges ();
1278 /* Replacing pseudos with their memory equivalents might have
1279 created shared rtx. Subsequent passes would get confused
1280 by this, so unshare everything here. */
1281 unshare_all_rtl_again (first);
1283 #ifdef STACK_BOUNDARY
1284 /* init_emit has set the alignment of the hard frame pointer
1285 to STACK_BOUNDARY. It is very likely no longer valid if
1286 the hard frame pointer was used for register allocation. */
1287 if (!frame_pointer_needed)
1288 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1294 /* Yet another special case. Unfortunately, reg-stack forces people to
1295 write incorrect clobbers in asm statements. These clobbers must not
1296 cause the register to appear in bad_spill_regs, otherwise we'll call
1297 fatal_insn later. We clear the corresponding regnos in the live
1298 register sets to avoid this.
1299 The whole thing is rather sick, I'm afraid. */
1302 maybe_fix_stack_asms (void)
1305 const char *constraints[MAX_RECOG_OPERANDS];
1306 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1307 struct insn_chain *chain;
1309 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1312 HARD_REG_SET clobbered, allowed;
1315 if (! INSN_P (chain->insn)
1316 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1318 pat = PATTERN (chain->insn);
1319 if (GET_CODE (pat) != PARALLEL)
1322 CLEAR_HARD_REG_SET (clobbered);
1323 CLEAR_HARD_REG_SET (allowed);
1325 /* First, make a mask of all stack regs that are clobbered. */
1326 for (i = 0; i < XVECLEN (pat, 0); i++)
1328 rtx t = XVECEXP (pat, 0, i);
1329 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1330 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1333 /* Get the operand values and constraints out of the insn. */
1334 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1335 constraints, operand_mode);
1337 /* For every operand, see what registers are allowed. */
1338 for (i = 0; i < noperands; i++)
1340 const char *p = constraints[i];
1341 /* For every alternative, we compute the class of registers allowed
1342 for reloading in CLS, and merge its contents into the reg set
1344 int cls = (int) NO_REGS;
1350 if (c == '\0' || c == ',' || c == '#')
1352 /* End of one alternative - mark the regs in the current
1353 class, and reset the class. */
1354 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1360 } while (c != '\0' && c != ',');
1368 case '=': case '+': case '*': case '%': case '?': case '!':
1369 case '0': case '1': case '2': case '3': case '4': case 'm':
1370 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1371 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1372 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1377 cls = (int) reg_class_subunion[cls]
1378 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1383 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1387 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1388 cls = (int) reg_class_subunion[cls]
1389 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1391 cls = (int) reg_class_subunion[cls]
1392 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1394 p += CONSTRAINT_LEN (c, p);
1397 /* Those of the registers which are clobbered, but allowed by the
1398 constraints, must be usable as reload registers. So clear them
1399 out of the life information. */
1400 AND_HARD_REG_SET (allowed, clobbered);
1401 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1402 if (TEST_HARD_REG_BIT (allowed, i))
1404 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1405 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1412 /* Copy the global variables n_reloads and rld into the corresponding elts
1415 copy_reloads (struct insn_chain *chain)
1417 chain->n_reloads = n_reloads;
1418 chain->rld = obstack_alloc (&reload_obstack,
1419 n_reloads * sizeof (struct reload));
1420 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1421 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1424 /* Walk the chain of insns, and determine for each whether it needs reloads
1425 and/or eliminations. Build the corresponding insns_need_reload list, and
1426 set something_needs_elimination as appropriate. */
1428 calculate_needs_all_insns (int global)
1430 struct insn_chain **pprev_reload = &insns_need_reload;
1431 struct insn_chain *chain, *next = 0;
1433 something_needs_elimination = 0;
1435 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1436 for (chain = reload_insn_chain; chain != 0; chain = next)
1438 rtx insn = chain->insn;
1442 /* Clear out the shortcuts. */
1443 chain->n_reloads = 0;
1444 chain->need_elim = 0;
1445 chain->need_reload = 0;
1446 chain->need_operand_change = 0;
1448 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1449 include REG_LABEL), we need to see what effects this has on the
1450 known offsets at labels. */
1452 if (LABEL_P (insn) || JUMP_P (insn)
1453 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1454 set_label_offsets (insn, insn, 0);
1458 rtx old_body = PATTERN (insn);
1459 int old_code = INSN_CODE (insn);
1460 rtx old_notes = REG_NOTES (insn);
1461 int did_elimination = 0;
1462 int operands_changed = 0;
1463 rtx set = single_set (insn);
1465 /* Skip insns that only set an equivalence. */
1466 if (set && REG_P (SET_DEST (set))
1467 && reg_renumber[REGNO (SET_DEST (set))] < 0
1468 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1469 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1470 && reg_equiv_init[REGNO (SET_DEST (set))])
1473 /* If needed, eliminate any eliminable registers. */
1474 if (num_eliminable || num_eliminable_invariants)
1475 did_elimination = eliminate_regs_in_insn (insn, 0);
1477 /* Analyze the instruction. */
1478 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1479 global, spill_reg_order);
1481 /* If a no-op set needs more than one reload, this is likely
1482 to be something that needs input address reloads. We
1483 can't get rid of this cleanly later, and it is of no use
1484 anyway, so discard it now.
1485 We only do this when expensive_optimizations is enabled,
1486 since this complements reload inheritance / output
1487 reload deletion, and it can make debugging harder. */
1488 if (flag_expensive_optimizations && n_reloads > 1)
1490 rtx set = single_set (insn);
1492 && SET_SRC (set) == SET_DEST (set)
1493 && REG_P (SET_SRC (set))
1494 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1497 /* Delete it from the reload chain. */
1499 chain->prev->next = next;
1501 reload_insn_chain = next;
1503 next->prev = chain->prev;
1504 chain->next = unused_insn_chains;
1505 unused_insn_chains = chain;
1510 update_eliminable_offsets ();
1512 /* Remember for later shortcuts which insns had any reloads or
1513 register eliminations. */
1514 chain->need_elim = did_elimination;
1515 chain->need_reload = n_reloads > 0;
1516 chain->need_operand_change = operands_changed;
1518 /* Discard any register replacements done. */
1519 if (did_elimination)
1521 obstack_free (&reload_obstack, reload_insn_firstobj);
1522 PATTERN (insn) = old_body;
1523 INSN_CODE (insn) = old_code;
1524 REG_NOTES (insn) = old_notes;
1525 something_needs_elimination = 1;
1528 something_needs_operands_changed |= operands_changed;
1532 copy_reloads (chain);
1533 *pprev_reload = chain;
1534 pprev_reload = &chain->next_need_reload;
1541 /* Comparison function for qsort to decide which of two reloads
1542 should be handled first. *P1 and *P2 are the reload numbers. */
1545 reload_reg_class_lower (const void *r1p, const void *r2p)
1547 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1550 /* Consider required reloads before optional ones. */
1551 t = rld[r1].optional - rld[r2].optional;
1555 /* Count all solitary classes before non-solitary ones. */
1556 t = ((reg_class_size[(int) rld[r2].class] == 1)
1557 - (reg_class_size[(int) rld[r1].class] == 1));
1561 /* Aside from solitaires, consider all multi-reg groups first. */
1562 t = rld[r2].nregs - rld[r1].nregs;
1566 /* Consider reloads in order of increasing reg-class number. */
1567 t = (int) rld[r1].class - (int) rld[r2].class;
1571 /* If reloads are equally urgent, sort by reload number,
1572 so that the results of qsort leave nothing to chance. */
1576 /* The cost of spilling each hard reg. */
1577 static int spill_cost[FIRST_PSEUDO_REGISTER];
1579 /* When spilling multiple hard registers, we use SPILL_COST for the first
1580 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1581 only the first hard reg for a multi-reg pseudo. */
1582 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1584 /* Update the spill cost arrays, considering that pseudo REG is live. */
1587 count_pseudo (int reg)
1589 int freq = REG_FREQ (reg);
1590 int r = reg_renumber[reg];
1593 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1594 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1597 SET_REGNO_REG_SET (&pseudos_counted, reg);
1599 gcc_assert (r >= 0);
1601 spill_add_cost[r] += freq;
1603 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1605 spill_cost[r + nregs] += freq;
1608 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1609 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1612 order_regs_for_reload (struct insn_chain *chain)
1615 HARD_REG_SET used_by_pseudos;
1616 HARD_REG_SET used_by_pseudos2;
1617 reg_set_iterator rsi;
1619 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1621 memset (spill_cost, 0, sizeof spill_cost);
1622 memset (spill_add_cost, 0, sizeof spill_add_cost);
1624 /* Count number of uses of each hard reg by pseudo regs allocated to it
1625 and then order them by decreasing use. First exclude hard registers
1626 that are live in or across this insn. */
1628 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1629 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1630 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1631 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1633 /* Now find out which pseudos are allocated to it, and update
1635 CLEAR_REG_SET (&pseudos_counted);
1637 EXECUTE_IF_SET_IN_REG_SET
1638 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1642 EXECUTE_IF_SET_IN_REG_SET
1643 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1647 CLEAR_REG_SET (&pseudos_counted);
1650 /* Vector of reload-numbers showing the order in which the reloads should
1652 static short reload_order[MAX_RELOADS];
1654 /* This is used to keep track of the spill regs used in one insn. */
1655 static HARD_REG_SET used_spill_regs_local;
1657 /* We decided to spill hard register SPILLED, which has a size of
1658 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1659 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1660 update SPILL_COST/SPILL_ADD_COST. */
1663 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1665 int r = reg_renumber[reg];
1666 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1668 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1669 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1672 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1674 spill_add_cost[r] -= REG_FREQ (reg);
1676 spill_cost[r + nregs] -= REG_FREQ (reg);
1679 /* Find reload register to use for reload number ORDER. */
1682 find_reg (struct insn_chain *chain, int order)
1684 int rnum = reload_order[order];
1685 struct reload *rl = rld + rnum;
1686 int best_cost = INT_MAX;
1690 HARD_REG_SET not_usable;
1691 HARD_REG_SET used_by_other_reload;
1692 reg_set_iterator rsi;
1694 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1695 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1696 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1698 CLEAR_HARD_REG_SET (used_by_other_reload);
1699 for (k = 0; k < order; k++)
1701 int other = reload_order[k];
1703 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1704 for (j = 0; j < rld[other].nregs; j++)
1705 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1708 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1710 unsigned int regno = i;
1712 if (! TEST_HARD_REG_BIT (not_usable, regno)
1713 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1714 && HARD_REGNO_MODE_OK (regno, rl->mode))
1716 int this_cost = spill_cost[regno];
1718 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1720 for (j = 1; j < this_nregs; j++)
1722 this_cost += spill_add_cost[regno + j];
1723 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1724 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1729 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1731 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1733 if (this_cost < best_cost
1734 /* Among registers with equal cost, prefer caller-saved ones, or
1735 use REG_ALLOC_ORDER if it is defined. */
1736 || (this_cost == best_cost
1737 #ifdef REG_ALLOC_ORDER
1738 && (inv_reg_alloc_order[regno]
1739 < inv_reg_alloc_order[best_reg])
1741 && call_used_regs[regno]
1742 && ! call_used_regs[best_reg]
1747 best_cost = this_cost;
1755 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1757 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1758 rl->regno = best_reg;
1760 EXECUTE_IF_SET_IN_REG_SET
1761 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1763 count_spilled_pseudo (best_reg, rl->nregs, j);
1766 EXECUTE_IF_SET_IN_REG_SET
1767 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1769 count_spilled_pseudo (best_reg, rl->nregs, j);
1772 for (i = 0; i < rl->nregs; i++)
1774 gcc_assert (spill_cost[best_reg + i] == 0);
1775 gcc_assert (spill_add_cost[best_reg + i] == 0);
1776 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1781 /* Find more reload regs to satisfy the remaining need of an insn, which
1783 Do it by ascending class number, since otherwise a reg
1784 might be spilled for a big class and might fail to count
1785 for a smaller class even though it belongs to that class. */
1788 find_reload_regs (struct insn_chain *chain)
1792 /* In order to be certain of getting the registers we need,
1793 we must sort the reloads into order of increasing register class.
1794 Then our grabbing of reload registers will parallel the process
1795 that provided the reload registers. */
1796 for (i = 0; i < chain->n_reloads; i++)
1798 /* Show whether this reload already has a hard reg. */
1799 if (chain->rld[i].reg_rtx)
1801 int regno = REGNO (chain->rld[i].reg_rtx);
1802 chain->rld[i].regno = regno;
1804 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1807 chain->rld[i].regno = -1;
1808 reload_order[i] = i;
1811 n_reloads = chain->n_reloads;
1812 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1814 CLEAR_HARD_REG_SET (used_spill_regs_local);
1817 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1819 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1821 /* Compute the order of preference for hard registers to spill. */
1823 order_regs_for_reload (chain);
1825 for (i = 0; i < n_reloads; i++)
1827 int r = reload_order[i];
1829 /* Ignore reloads that got marked inoperative. */
1830 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1831 && ! rld[r].optional
1832 && rld[r].regno == -1)
1833 if (! find_reg (chain, i))
1836 fprintf(dump_file, "reload failure for reload %d\n", r);
1837 spill_failure (chain->insn, rld[r].class);
1843 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1844 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1846 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1850 select_reload_regs (void)
1852 struct insn_chain *chain;
1854 /* Try to satisfy the needs for each insn. */
1855 for (chain = insns_need_reload; chain != 0;
1856 chain = chain->next_need_reload)
1857 find_reload_regs (chain);
1860 /* Delete all insns that were inserted by emit_caller_save_insns during
1863 delete_caller_save_insns (void)
1865 struct insn_chain *c = reload_insn_chain;
1869 while (c != 0 && c->is_caller_save_insn)
1871 struct insn_chain *next = c->next;
1874 if (c == reload_insn_chain)
1875 reload_insn_chain = next;
1879 next->prev = c->prev;
1881 c->prev->next = next;
1882 c->next = unused_insn_chains;
1883 unused_insn_chains = c;
1891 /* Handle the failure to find a register to spill.
1892 INSN should be one of the insns which needed this particular spill reg. */
1895 spill_failure (rtx insn, enum reg_class class)
1897 if (asm_noperands (PATTERN (insn)) >= 0)
1898 error_for_asm (insn, "can't find a register in class %qs while "
1899 "reloading %<asm%>",
1900 reg_class_names[class]);
1903 error ("unable to find a register to spill in class %qs",
1904 reg_class_names[class]);
1908 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
1909 debug_reload_to_stream (dump_file);
1911 fatal_insn ("this is the insn:", insn);
1915 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1916 data that is dead in INSN. */
1919 delete_dead_insn (rtx insn)
1921 rtx prev = prev_real_insn (insn);
1924 /* If the previous insn sets a register that dies in our insn, delete it
1926 if (prev && GET_CODE (PATTERN (prev)) == SET
1927 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
1928 && reg_mentioned_p (prev_dest, PATTERN (insn))
1929 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1930 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1931 delete_dead_insn (prev);
1933 SET_INSN_DELETED (insn);
1936 /* Modify the home of pseudo-reg I.
1937 The new home is present in reg_renumber[I].
1939 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1940 or it may be -1, meaning there is none or it is not relevant.
1941 This is used so that all pseudos spilled from a given hard reg
1942 can share one stack slot. */
1945 alter_reg (int i, int from_reg)
1947 /* When outputting an inline function, this can happen
1948 for a reg that isn't actually used. */
1949 if (regno_reg_rtx[i] == 0)
1952 /* If the reg got changed to a MEM at rtl-generation time,
1954 if (!REG_P (regno_reg_rtx[i]))
1957 /* Modify the reg-rtx to contain the new hard reg
1958 number or else to contain its pseudo reg number. */
1959 REGNO (regno_reg_rtx[i])
1960 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1962 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1963 allocate a stack slot for it. */
1965 if (reg_renumber[i] < 0
1966 && REG_N_REFS (i) > 0
1967 && reg_equiv_constant[i] == 0
1968 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
1969 && reg_equiv_memory_loc[i] == 0)
1972 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1973 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1976 /* Each pseudo reg has an inherent size which comes from its own mode,
1977 and a total size which provides room for paradoxical subregs
1978 which refer to the pseudo reg in wider modes.
1980 We can use a slot already allocated if it provides both
1981 enough inherent space and enough total space.
1982 Otherwise, we allocate a new slot, making sure that it has no less
1983 inherent space, and no less total space, then the previous slot. */
1986 /* No known place to spill from => no slot to reuse. */
1987 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1988 inherent_size == total_size ? 0 : -1);
1989 if (BYTES_BIG_ENDIAN)
1990 /* Cancel the big-endian correction done in assign_stack_local.
1991 Get the address of the beginning of the slot.
1992 This is so we can do a big-endian correction unconditionally
1994 adjust = inherent_size - total_size;
1996 /* Nothing can alias this slot except this pseudo. */
1997 set_mem_alias_set (x, new_alias_set ());
2000 /* Reuse a stack slot if possible. */
2001 else if (spill_stack_slot[from_reg] != 0
2002 && spill_stack_slot_width[from_reg] >= total_size
2003 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2005 x = spill_stack_slot[from_reg];
2007 /* Allocate a bigger slot. */
2010 /* Compute maximum size needed, both for inherent size
2011 and for total size. */
2012 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2015 if (spill_stack_slot[from_reg])
2017 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2019 mode = GET_MODE (spill_stack_slot[from_reg]);
2020 if (spill_stack_slot_width[from_reg] > total_size)
2021 total_size = spill_stack_slot_width[from_reg];
2024 /* Make a slot with that size. */
2025 x = assign_stack_local (mode, total_size,
2026 inherent_size == total_size ? 0 : -1);
2029 /* All pseudos mapped to this slot can alias each other. */
2030 if (spill_stack_slot[from_reg])
2031 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2033 set_mem_alias_set (x, new_alias_set ());
2035 if (BYTES_BIG_ENDIAN)
2037 /* Cancel the big-endian correction done in assign_stack_local.
2038 Get the address of the beginning of the slot.
2039 This is so we can do a big-endian correction unconditionally
2041 adjust = GET_MODE_SIZE (mode) - total_size;
2044 = adjust_address_nv (x, mode_for_size (total_size
2050 spill_stack_slot[from_reg] = stack_slot;
2051 spill_stack_slot_width[from_reg] = total_size;
2054 /* On a big endian machine, the "address" of the slot
2055 is the address of the low part that fits its inherent mode. */
2056 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2057 adjust += (total_size - inherent_size);
2059 /* If we have any adjustment to make, or if the stack slot is the
2060 wrong mode, make a new stack slot. */
2061 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2063 /* If we have a decl for the original register, set it for the
2064 memory. If this is a shared MEM, make a copy. */
2065 if (REG_EXPR (regno_reg_rtx[i])
2066 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2068 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2070 /* We can do this only for the DECLs home pseudo, not for
2071 any copies of it, since otherwise when the stack slot
2072 is reused, nonoverlapping_memrefs_p might think they
2074 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2076 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2079 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2083 /* Save the stack slot for later. */
2084 reg_equiv_memory_loc[i] = x;
2088 /* Mark the slots in regs_ever_live for the hard regs
2089 used by pseudo-reg number REGNO. */
2092 mark_home_live (int regno)
2096 i = reg_renumber[regno];
2099 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2101 regs_ever_live[i++] = 1;
2104 /* This function handles the tracking of elimination offsets around branches.
2106 X is a piece of RTL being scanned.
2108 INSN is the insn that it came from, if any.
2110 INITIAL_P is nonzero if we are to set the offset to be the initial
2111 offset and zero if we are setting the offset of the label to be the
2115 set_label_offsets (rtx x, rtx insn, int initial_p)
2117 enum rtx_code code = GET_CODE (x);
2120 struct elim_table *p;
2125 if (LABEL_REF_NONLOCAL_P (x))
2130 /* ... fall through ... */
2133 /* If we know nothing about this label, set the desired offsets. Note
2134 that this sets the offset at a label to be the offset before a label
2135 if we don't know anything about the label. This is not correct for
2136 the label after a BARRIER, but is the best guess we can make. If
2137 we guessed wrong, we will suppress an elimination that might have
2138 been possible had we been able to guess correctly. */
2140 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2142 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2143 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2144 = (initial_p ? reg_eliminate[i].initial_offset
2145 : reg_eliminate[i].offset);
2146 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2149 /* Otherwise, if this is the definition of a label and it is
2150 preceded by a BARRIER, set our offsets to the known offset of
2154 && (tem = prev_nonnote_insn (insn)) != 0
2156 set_offsets_for_label (insn);
2158 /* If neither of the above cases is true, compare each offset
2159 with those previously recorded and suppress any eliminations
2160 where the offsets disagree. */
2162 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2163 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2164 != (initial_p ? reg_eliminate[i].initial_offset
2165 : reg_eliminate[i].offset))
2166 reg_eliminate[i].can_eliminate = 0;
2171 set_label_offsets (PATTERN (insn), insn, initial_p);
2173 /* ... fall through ... */
2177 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2178 and hence must have all eliminations at their initial offsets. */
2179 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2180 if (REG_NOTE_KIND (tem) == REG_LABEL)
2181 set_label_offsets (XEXP (tem, 0), insn, 1);
2187 /* Each of the labels in the parallel or address vector must be
2188 at their initial offsets. We want the first field for PARALLEL
2189 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2191 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2192 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2197 /* We only care about setting PC. If the source is not RETURN,
2198 IF_THEN_ELSE, or a label, disable any eliminations not at
2199 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2200 isn't one of those possibilities. For branches to a label,
2201 call ourselves recursively.
2203 Note that this can disable elimination unnecessarily when we have
2204 a non-local goto since it will look like a non-constant jump to
2205 someplace in the current function. This isn't a significant
2206 problem since such jumps will normally be when all elimination
2207 pairs are back to their initial offsets. */
2209 if (SET_DEST (x) != pc_rtx)
2212 switch (GET_CODE (SET_SRC (x)))
2219 set_label_offsets (SET_SRC (x), insn, initial_p);
2223 tem = XEXP (SET_SRC (x), 1);
2224 if (GET_CODE (tem) == LABEL_REF)
2225 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2226 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2229 tem = XEXP (SET_SRC (x), 2);
2230 if (GET_CODE (tem) == LABEL_REF)
2231 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2232 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2240 /* If we reach here, all eliminations must be at their initial
2241 offset because we are doing a jump to a variable address. */
2242 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2243 if (p->offset != p->initial_offset)
2244 p->can_eliminate = 0;
2252 /* Scan X and replace any eliminable registers (such as fp) with a
2253 replacement (such as sp), plus an offset.
2255 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2256 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2257 MEM, we are allowed to replace a sum of a register and the constant zero
2258 with the register, which we cannot do outside a MEM. In addition, we need
2259 to record the fact that a register is referenced outside a MEM.
2261 If INSN is an insn, it is the insn containing X. If we replace a REG
2262 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2263 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2264 the REG is being modified.
2266 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2267 That's used when we eliminate in expressions stored in notes.
2268 This means, do not set ref_outside_mem even if the reference
2271 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2272 replacements done assuming all offsets are at their initial values. If
2273 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2274 encounter, return the actual location so that find_reloads will do
2275 the proper thing. */
2278 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2279 bool may_use_invariant)
2281 enum rtx_code code = GET_CODE (x);
2282 struct elim_table *ep;
2289 if (! current_function_decl)
2311 /* First handle the case where we encounter a bare register that
2312 is eliminable. Replace it with a PLUS. */
2313 if (regno < FIRST_PSEUDO_REGISTER)
2315 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2317 if (ep->from_rtx == x && ep->can_eliminate)
2318 return plus_constant (ep->to_rtx, ep->previous_offset);
2321 else if (reg_renumber && reg_renumber[regno] < 0
2322 && reg_equiv_invariant && reg_equiv_invariant[regno])
2324 if (may_use_invariant)
2325 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2326 mem_mode, insn, true);
2327 /* There exists at least one use of REGNO that cannot be
2328 eliminated. Prevent the defining insn from being deleted. */
2329 reg_equiv_init[regno] = NULL_RTX;
2330 alter_reg (regno, -1);
2334 /* You might think handling MINUS in a manner similar to PLUS is a
2335 good idea. It is not. It has been tried multiple times and every
2336 time the change has had to have been reverted.
2338 Other parts of reload know a PLUS is special (gen_reload for example)
2339 and require special code to handle code a reloaded PLUS operand.
2341 Also consider backends where the flags register is clobbered by a
2342 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2343 lea instruction comes to mind). If we try to reload a MINUS, we
2344 may kill the flags register that was holding a useful value.
2346 So, please before trying to handle MINUS, consider reload as a
2347 whole instead of this little section as well as the backend issues. */
2349 /* If this is the sum of an eliminable register and a constant, rework
2351 if (REG_P (XEXP (x, 0))
2352 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2353 && CONSTANT_P (XEXP (x, 1)))
2355 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2357 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2359 /* The only time we want to replace a PLUS with a REG (this
2360 occurs when the constant operand of the PLUS is the negative
2361 of the offset) is when we are inside a MEM. We won't want
2362 to do so at other times because that would change the
2363 structure of the insn in a way that reload can't handle.
2364 We special-case the commonest situation in
2365 eliminate_regs_in_insn, so just replace a PLUS with a
2366 PLUS here, unless inside a MEM. */
2367 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2368 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2371 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2372 plus_constant (XEXP (x, 1),
2373 ep->previous_offset));
2376 /* If the register is not eliminable, we are done since the other
2377 operand is a constant. */
2381 /* If this is part of an address, we want to bring any constant to the
2382 outermost PLUS. We will do this by doing register replacement in
2383 our operands and seeing if a constant shows up in one of them.
2385 Note that there is no risk of modifying the structure of the insn,
2386 since we only get called for its operands, thus we are either
2387 modifying the address inside a MEM, or something like an address
2388 operand of a load-address insn. */
2391 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2392 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2394 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2396 /* If one side is a PLUS and the other side is a pseudo that
2397 didn't get a hard register but has a reg_equiv_constant,
2398 we must replace the constant here since it may no longer
2399 be in the position of any operand. */
2400 if (GET_CODE (new0) == PLUS && REG_P (new1)
2401 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2402 && reg_renumber[REGNO (new1)] < 0
2403 && reg_equiv_constant != 0
2404 && reg_equiv_constant[REGNO (new1)] != 0)
2405 new1 = reg_equiv_constant[REGNO (new1)];
2406 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2407 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2408 && reg_renumber[REGNO (new0)] < 0
2409 && reg_equiv_constant[REGNO (new0)] != 0)
2410 new0 = reg_equiv_constant[REGNO (new0)];
2412 new = form_sum (new0, new1);
2414 /* As above, if we are not inside a MEM we do not want to
2415 turn a PLUS into something else. We might try to do so here
2416 for an addition of 0 if we aren't optimizing. */
2417 if (! mem_mode && GET_CODE (new) != PLUS)
2418 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2426 /* If this is the product of an eliminable register and a
2427 constant, apply the distribute law and move the constant out
2428 so that we have (plus (mult ..) ..). This is needed in order
2429 to keep load-address insns valid. This case is pathological.
2430 We ignore the possibility of overflow here. */
2431 if (REG_P (XEXP (x, 0))
2432 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2433 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2434 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2436 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2439 /* Refs inside notes don't count for this purpose. */
2440 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2441 || GET_CODE (insn) == INSN_LIST)))
2442 ep->ref_outside_mem = 1;
2445 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2446 ep->previous_offset * INTVAL (XEXP (x, 1)));
2449 /* ... fall through ... */
2453 /* See comments before PLUS about handling MINUS. */
2455 case DIV: case UDIV:
2456 case MOD: case UMOD:
2457 case AND: case IOR: case XOR:
2458 case ROTATERT: case ROTATE:
2459 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2461 case GE: case GT: case GEU: case GTU:
2462 case LE: case LT: case LEU: case LTU:
2464 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2465 rtx new1 = XEXP (x, 1)
2466 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2468 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2469 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2474 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2477 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2478 if (new != XEXP (x, 0))
2480 /* If this is a REG_DEAD note, it is not valid anymore.
2481 Using the eliminated version could result in creating a
2482 REG_DEAD note for the stack or frame pointer. */
2483 if (GET_MODE (x) == REG_DEAD)
2485 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2488 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2492 /* ... fall through ... */
2495 /* Now do eliminations in the rest of the chain. If this was
2496 an EXPR_LIST, this might result in allocating more memory than is
2497 strictly needed, but it simplifies the code. */
2500 new = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2501 if (new != XEXP (x, 1))
2503 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2511 case STRICT_LOW_PART:
2513 case SIGN_EXTEND: case ZERO_EXTEND:
2514 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2515 case FLOAT: case FIX:
2516 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2524 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2525 if (new != XEXP (x, 0))
2526 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2530 /* Similar to above processing, but preserve SUBREG_BYTE.
2531 Convert (subreg (mem)) to (mem) if not paradoxical.
2532 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2533 pseudo didn't get a hard reg, we must replace this with the
2534 eliminated version of the memory location because push_reload
2535 may do the replacement in certain circumstances. */
2536 if (REG_P (SUBREG_REG (x))
2537 && (GET_MODE_SIZE (GET_MODE (x))
2538 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2539 && reg_equiv_memory_loc != 0
2540 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2542 new = SUBREG_REG (x);
2545 new = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2547 if (new != SUBREG_REG (x))
2549 int x_size = GET_MODE_SIZE (GET_MODE (x));
2550 int new_size = GET_MODE_SIZE (GET_MODE (new));
2553 && ((x_size < new_size
2554 #ifdef WORD_REGISTER_OPERATIONS
2555 /* On these machines, combine can create rtl of the form
2556 (set (subreg:m1 (reg:m2 R) 0) ...)
2557 where m1 < m2, and expects something interesting to
2558 happen to the entire word. Moreover, it will use the
2559 (reg:m2 R) later, expecting all bits to be preserved.
2560 So if the number of words is the same, preserve the
2561 subreg so that push_reload can see it. */
2562 && ! ((x_size - 1) / UNITS_PER_WORD
2563 == (new_size -1 ) / UNITS_PER_WORD)
2566 || x_size == new_size)
2568 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2570 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2576 /* Our only special processing is to pass the mode of the MEM to our
2577 recursive call and copy the flags. While we are here, handle this
2578 case more efficiently. */
2580 replace_equiv_address_nv (x,
2581 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2585 /* Handle insn_list USE that a call to a pure function may generate. */
2586 new = eliminate_regs_1 (XEXP (x, 0), 0, insn, false);
2587 if (new != XEXP (x, 0))
2588 return gen_rtx_USE (GET_MODE (x), new);
2600 /* Process each of our operands recursively. If any have changed, make a
2602 fmt = GET_RTX_FORMAT (code);
2603 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2607 new = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2608 if (new != XEXP (x, i) && ! copied)
2610 rtx new_x = rtx_alloc (code);
2611 memcpy (new_x, x, RTX_SIZE (code));
2617 else if (*fmt == 'E')
2620 for (j = 0; j < XVECLEN (x, i); j++)
2622 new = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2623 if (new != XVECEXP (x, i, j) && ! copied_vec)
2625 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2629 rtx new_x = rtx_alloc (code);
2630 memcpy (new_x, x, RTX_SIZE (code));
2634 XVEC (x, i) = new_v;
2637 XVECEXP (x, i, j) = new;
2646 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2648 return eliminate_regs_1 (x, mem_mode, insn, false);
2651 /* Scan rtx X for modifications of elimination target registers. Update
2652 the table of eliminables to reflect the changed state. MEM_MODE is
2653 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2656 elimination_effects (rtx x, enum machine_mode mem_mode)
2658 enum rtx_code code = GET_CODE (x);
2659 struct elim_table *ep;
2683 /* First handle the case where we encounter a bare register that
2684 is eliminable. Replace it with a PLUS. */
2685 if (regno < FIRST_PSEUDO_REGISTER)
2687 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2689 if (ep->from_rtx == x && ep->can_eliminate)
2692 ep->ref_outside_mem = 1;
2697 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2698 && reg_equiv_constant[regno]
2699 && ! function_invariant_p (reg_equiv_constant[regno]))
2700 elimination_effects (reg_equiv_constant[regno], mem_mode);
2709 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2710 if (ep->to_rtx == XEXP (x, 0))
2712 int size = GET_MODE_SIZE (mem_mode);
2714 /* If more bytes than MEM_MODE are pushed, account for them. */
2715 #ifdef PUSH_ROUNDING
2716 if (ep->to_rtx == stack_pointer_rtx)
2717 size = PUSH_ROUNDING (size);
2719 if (code == PRE_DEC || code == POST_DEC)
2721 else if (code == PRE_INC || code == POST_INC)
2723 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2724 && GET_CODE (XEXP (x, 1)) == PLUS
2725 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2726 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2727 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2730 /* These two aren't unary operators. */
2731 if (code == POST_MODIFY || code == PRE_MODIFY)
2734 /* Fall through to generic unary operation case. */
2735 case STRICT_LOW_PART:
2737 case SIGN_EXTEND: case ZERO_EXTEND:
2738 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2739 case FLOAT: case FIX:
2740 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2748 elimination_effects (XEXP (x, 0), mem_mode);
2752 if (REG_P (SUBREG_REG (x))
2753 && (GET_MODE_SIZE (GET_MODE (x))
2754 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2755 && reg_equiv_memory_loc != 0
2756 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2759 elimination_effects (SUBREG_REG (x), mem_mode);
2763 /* If using a register that is the source of an eliminate we still
2764 think can be performed, note it cannot be performed since we don't
2765 know how this register is used. */
2766 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2767 if (ep->from_rtx == XEXP (x, 0))
2768 ep->can_eliminate = 0;
2770 elimination_effects (XEXP (x, 0), mem_mode);
2774 /* If clobbering a register that is the replacement register for an
2775 elimination we still think can be performed, note that it cannot
2776 be performed. Otherwise, we need not be concerned about it. */
2777 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2778 if (ep->to_rtx == XEXP (x, 0))
2779 ep->can_eliminate = 0;
2781 elimination_effects (XEXP (x, 0), mem_mode);
2785 /* Check for setting a register that we know about. */
2786 if (REG_P (SET_DEST (x)))
2788 /* See if this is setting the replacement register for an
2791 If DEST is the hard frame pointer, we do nothing because we
2792 assume that all assignments to the frame pointer are for
2793 non-local gotos and are being done at a time when they are valid
2794 and do not disturb anything else. Some machines want to
2795 eliminate a fake argument pointer (or even a fake frame pointer)
2796 with either the real frame or the stack pointer. Assignments to
2797 the hard frame pointer must not prevent this elimination. */
2799 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2801 if (ep->to_rtx == SET_DEST (x)
2802 && SET_DEST (x) != hard_frame_pointer_rtx)
2804 /* If it is being incremented, adjust the offset. Otherwise,
2805 this elimination can't be done. */
2806 rtx src = SET_SRC (x);
2808 if (GET_CODE (src) == PLUS
2809 && XEXP (src, 0) == SET_DEST (x)
2810 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2811 ep->offset -= INTVAL (XEXP (src, 1));
2813 ep->can_eliminate = 0;
2817 elimination_effects (SET_DEST (x), 0);
2818 elimination_effects (SET_SRC (x), 0);
2822 /* Our only special processing is to pass the mode of the MEM to our
2824 elimination_effects (XEXP (x, 0), GET_MODE (x));
2831 fmt = GET_RTX_FORMAT (code);
2832 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2835 elimination_effects (XEXP (x, i), mem_mode);
2836 else if (*fmt == 'E')
2837 for (j = 0; j < XVECLEN (x, i); j++)
2838 elimination_effects (XVECEXP (x, i, j), mem_mode);
2842 /* Descend through rtx X and verify that no references to eliminable registers
2843 remain. If any do remain, mark the involved register as not
2847 check_eliminable_occurrences (rtx x)
2856 code = GET_CODE (x);
2858 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2860 struct elim_table *ep;
2862 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2863 if (ep->from_rtx == x)
2864 ep->can_eliminate = 0;
2868 fmt = GET_RTX_FORMAT (code);
2869 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2872 check_eliminable_occurrences (XEXP (x, i));
2873 else if (*fmt == 'E')
2876 for (j = 0; j < XVECLEN (x, i); j++)
2877 check_eliminable_occurrences (XVECEXP (x, i, j));
2882 /* Scan INSN and eliminate all eliminable registers in it.
2884 If REPLACE is nonzero, do the replacement destructively. Also
2885 delete the insn as dead it if it is setting an eliminable register.
2887 If REPLACE is zero, do all our allocations in reload_obstack.
2889 If no eliminations were done and this insn doesn't require any elimination
2890 processing (these are not identical conditions: it might be updating sp,
2891 but not referencing fp; this needs to be seen during reload_as_needed so
2892 that the offset between fp and sp can be taken into consideration), zero
2893 is returned. Otherwise, 1 is returned. */
2896 eliminate_regs_in_insn (rtx insn, int replace)
2898 int icode = recog_memoized (insn);
2899 rtx old_body = PATTERN (insn);
2900 int insn_is_asm = asm_noperands (old_body) >= 0;
2901 rtx old_set = single_set (insn);
2905 rtx substed_operand[MAX_RECOG_OPERANDS];
2906 rtx orig_operand[MAX_RECOG_OPERANDS];
2907 struct elim_table *ep;
2908 rtx plus_src, plus_cst_src;
2910 if (! insn_is_asm && icode < 0)
2912 gcc_assert (GET_CODE (PATTERN (insn)) == USE
2913 || GET_CODE (PATTERN (insn)) == CLOBBER
2914 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2915 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2916 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
2920 if (old_set != 0 && REG_P (SET_DEST (old_set))
2921 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2923 /* Check for setting an eliminable register. */
2924 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2925 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2927 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2928 /* If this is setting the frame pointer register to the
2929 hardware frame pointer register and this is an elimination
2930 that will be done (tested above), this insn is really
2931 adjusting the frame pointer downward to compensate for
2932 the adjustment done before a nonlocal goto. */
2933 if (ep->from == FRAME_POINTER_REGNUM
2934 && ep->to == HARD_FRAME_POINTER_REGNUM)
2936 rtx base = SET_SRC (old_set);
2937 rtx base_insn = insn;
2938 HOST_WIDE_INT offset = 0;
2940 while (base != ep->to_rtx)
2942 rtx prev_insn, prev_set;
2944 if (GET_CODE (base) == PLUS
2945 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2947 offset += INTVAL (XEXP (base, 1));
2948 base = XEXP (base, 0);
2950 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2951 && (prev_set = single_set (prev_insn)) != 0
2952 && rtx_equal_p (SET_DEST (prev_set), base))
2954 base = SET_SRC (prev_set);
2955 base_insn = prev_insn;
2961 if (base == ep->to_rtx)
2964 = plus_constant (ep->to_rtx, offset - ep->offset);
2966 new_body = old_body;
2969 new_body = copy_insn (old_body);
2970 if (REG_NOTES (insn))
2971 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2973 PATTERN (insn) = new_body;
2974 old_set = single_set (insn);
2976 /* First see if this insn remains valid when we
2977 make the change. If not, keep the INSN_CODE
2978 the same and let reload fit it up. */
2979 validate_change (insn, &SET_SRC (old_set), src, 1);
2980 validate_change (insn, &SET_DEST (old_set),
2982 if (! apply_change_group ())
2984 SET_SRC (old_set) = src;
2985 SET_DEST (old_set) = ep->to_rtx;
2994 /* In this case this insn isn't serving a useful purpose. We
2995 will delete it in reload_as_needed once we know that this
2996 elimination is, in fact, being done.
2998 If REPLACE isn't set, we can't delete this insn, but needn't
2999 process it since it won't be used unless something changes. */
3002 delete_dead_insn (insn);
3010 /* We allow one special case which happens to work on all machines we
3011 currently support: a single set with the source or a REG_EQUAL
3012 note being a PLUS of an eliminable register and a constant. */
3013 plus_src = plus_cst_src = 0;
3014 if (old_set && REG_P (SET_DEST (old_set)))
3016 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3017 plus_src = SET_SRC (old_set);
3018 /* First see if the source is of the form (plus (...) CST). */
3020 && GET_CODE (XEXP (plus_src, 1)) == CONST_INT)
3021 plus_cst_src = plus_src;
3022 else if (REG_P (SET_SRC (old_set))
3025 /* Otherwise, see if we have a REG_EQUAL note of the form
3026 (plus (...) CST). */
3028 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3030 if (REG_NOTE_KIND (links) == REG_EQUAL
3031 && GET_CODE (XEXP (links, 0)) == PLUS
3032 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT)
3034 plus_cst_src = XEXP (links, 0);
3040 /* Check that the first operand of the PLUS is a hard reg or
3041 the lowpart subreg of one. */
3044 rtx reg = XEXP (plus_cst_src, 0);
3045 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3046 reg = SUBREG_REG (reg);
3048 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3054 rtx reg = XEXP (plus_cst_src, 0);
3055 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3057 if (GET_CODE (reg) == SUBREG)
3058 reg = SUBREG_REG (reg);
3060 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3061 if (ep->from_rtx == reg && ep->can_eliminate)
3063 rtx to_rtx = ep->to_rtx;
3064 offset += ep->offset;
3066 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3067 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3072 /* We assume here that if we need a PARALLEL with
3073 CLOBBERs for this assignment, we can do with the
3074 MATCH_SCRATCHes that add_clobbers allocates.
3075 There's not much we can do if that doesn't work. */
3076 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3080 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3083 rtvec vec = rtvec_alloc (num_clobbers + 1);
3085 vec->elem[0] = PATTERN (insn);
3086 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3087 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3089 gcc_assert (INSN_CODE (insn) >= 0);
3091 /* If we have a nonzero offset, and the source is already
3092 a simple REG, the following transformation would
3093 increase the cost of the insn by replacing a simple REG
3094 with (plus (reg sp) CST). So try only when we already
3095 had a PLUS before. */
3098 new_body = old_body;
3101 new_body = copy_insn (old_body);
3102 if (REG_NOTES (insn))
3103 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3105 PATTERN (insn) = new_body;
3106 old_set = single_set (insn);
3108 XEXP (SET_SRC (old_set), 0) = to_rtx;
3109 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3115 /* This can't have an effect on elimination offsets, so skip right
3121 /* Determine the effects of this insn on elimination offsets. */
3122 elimination_effects (old_body, 0);
3124 /* Eliminate all eliminable registers occurring in operands that
3125 can be handled by reload. */
3126 extract_insn (insn);
3127 for (i = 0; i < recog_data.n_operands; i++)
3129 orig_operand[i] = recog_data.operand[i];
3130 substed_operand[i] = recog_data.operand[i];
3132 /* For an asm statement, every operand is eliminable. */
3133 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3135 bool is_set_src, in_plus;
3137 /* Check for setting a register that we know about. */
3138 if (recog_data.operand_type[i] != OP_IN
3139 && REG_P (orig_operand[i]))
3141 /* If we are assigning to a register that can be eliminated, it
3142 must be as part of a PARALLEL, since the code above handles
3143 single SETs. We must indicate that we can no longer
3144 eliminate this reg. */
3145 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3147 if (ep->from_rtx == orig_operand[i])
3148 ep->can_eliminate = 0;
3151 /* Companion to the above plus substitution, we can allow
3152 invariants as the source of a plain move. */
3154 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3158 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3159 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3163 = eliminate_regs_1 (recog_data.operand[i], 0,
3164 replace ? insn : NULL_RTX,
3165 is_set_src || in_plus);
3166 if (substed_operand[i] != orig_operand[i])
3168 /* Terminate the search in check_eliminable_occurrences at
3170 *recog_data.operand_loc[i] = 0;
3172 /* If an output operand changed from a REG to a MEM and INSN is an
3173 insn, write a CLOBBER insn. */
3174 if (recog_data.operand_type[i] != OP_IN
3175 && REG_P (orig_operand[i])
3176 && MEM_P (substed_operand[i])
3178 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3183 for (i = 0; i < recog_data.n_dups; i++)
3184 *recog_data.dup_loc[i]
3185 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3187 /* If any eliminable remain, they aren't eliminable anymore. */
3188 check_eliminable_occurrences (old_body);
3190 /* Substitute the operands; the new values are in the substed_operand
3192 for (i = 0; i < recog_data.n_operands; i++)
3193 *recog_data.operand_loc[i] = substed_operand[i];
3194 for (i = 0; i < recog_data.n_dups; i++)
3195 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3197 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3198 re-recognize the insn. We do this in case we had a simple addition
3199 but now can do this as a load-address. This saves an insn in this
3201 If re-recognition fails, the old insn code number will still be used,
3202 and some register operands may have changed into PLUS expressions.
3203 These will be handled by find_reloads by loading them into a register
3208 /* If we aren't replacing things permanently and we changed something,
3209 make another copy to ensure that all the RTL is new. Otherwise
3210 things can go wrong if find_reload swaps commutative operands
3211 and one is inside RTL that has been copied while the other is not. */
3212 new_body = old_body;
3215 new_body = copy_insn (old_body);
3216 if (REG_NOTES (insn))
3217 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3219 PATTERN (insn) = new_body;
3221 /* If we had a move insn but now we don't, rerecognize it. This will
3222 cause spurious re-recognition if the old move had a PARALLEL since
3223 the new one still will, but we can't call single_set without
3224 having put NEW_BODY into the insn and the re-recognition won't
3225 hurt in this rare case. */
3226 /* ??? Why this huge if statement - why don't we just rerecognize the
3230 && ((REG_P (SET_SRC (old_set))
3231 && (GET_CODE (new_body) != SET
3232 || !REG_P (SET_SRC (new_body))))
3233 /* If this was a load from or store to memory, compare
3234 the MEM in recog_data.operand to the one in the insn.
3235 If they are not equal, then rerecognize the insn. */
3237 && ((MEM_P (SET_SRC (old_set))
3238 && SET_SRC (old_set) != recog_data.operand[1])
3239 || (MEM_P (SET_DEST (old_set))
3240 && SET_DEST (old_set) != recog_data.operand[0])))
3241 /* If this was an add insn before, rerecognize. */
3242 || GET_CODE (SET_SRC (old_set)) == PLUS))
3244 int new_icode = recog (PATTERN (insn), insn, 0);
3246 INSN_CODE (insn) = new_icode;
3250 /* Restore the old body. If there were any changes to it, we made a copy
3251 of it while the changes were still in place, so we'll correctly return
3252 a modified insn below. */
3255 /* Restore the old body. */
3256 for (i = 0; i < recog_data.n_operands; i++)
3257 *recog_data.operand_loc[i] = orig_operand[i];
3258 for (i = 0; i < recog_data.n_dups; i++)
3259 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3262 /* Update all elimination pairs to reflect the status after the current
3263 insn. The changes we make were determined by the earlier call to
3264 elimination_effects.
3266 We also detect cases where register elimination cannot be done,
3267 namely, if a register would be both changed and referenced outside a MEM
3268 in the resulting insn since such an insn is often undefined and, even if
3269 not, we cannot know what meaning will be given to it. Note that it is
3270 valid to have a register used in an address in an insn that changes it
3271 (presumably with a pre- or post-increment or decrement).
3273 If anything changes, return nonzero. */
3275 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3277 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3278 ep->can_eliminate = 0;
3280 ep->ref_outside_mem = 0;
3282 if (ep->previous_offset != ep->offset)
3287 /* If we changed something, perform elimination in REG_NOTES. This is
3288 needed even when REPLACE is zero because a REG_DEAD note might refer
3289 to a register that we eliminate and could cause a different number
3290 of spill registers to be needed in the final reload pass than in
3292 if (val && REG_NOTES (insn) != 0)
3294 = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true);
3299 /* Loop through all elimination pairs.
3300 Recalculate the number not at initial offset.
3302 Compute the maximum offset (minimum offset if the stack does not
3303 grow downward) for each elimination pair. */
3306 update_eliminable_offsets (void)
3308 struct elim_table *ep;
3310 num_not_at_initial_offset = 0;
3311 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3313 ep->previous_offset = ep->offset;
3314 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3315 num_not_at_initial_offset++;
3319 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3320 replacement we currently believe is valid, mark it as not eliminable if X
3321 modifies DEST in any way other than by adding a constant integer to it.
3323 If DEST is the frame pointer, we do nothing because we assume that
3324 all assignments to the hard frame pointer are nonlocal gotos and are being
3325 done at a time when they are valid and do not disturb anything else.
3326 Some machines want to eliminate a fake argument pointer with either the
3327 frame or stack pointer. Assignments to the hard frame pointer must not
3328 prevent this elimination.
3330 Called via note_stores from reload before starting its passes to scan
3331 the insns of the function. */
3334 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3338 /* A SUBREG of a hard register here is just changing its mode. We should
3339 not see a SUBREG of an eliminable hard register, but check just in
3341 if (GET_CODE (dest) == SUBREG)
3342 dest = SUBREG_REG (dest);
3344 if (dest == hard_frame_pointer_rtx)
3347 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3348 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3349 && (GET_CODE (x) != SET
3350 || GET_CODE (SET_SRC (x)) != PLUS
3351 || XEXP (SET_SRC (x), 0) != dest
3352 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3354 reg_eliminate[i].can_eliminate_previous
3355 = reg_eliminate[i].can_eliminate = 0;
3360 /* Verify that the initial elimination offsets did not change since the
3361 last call to set_initial_elim_offsets. This is used to catch cases
3362 where something illegal happened during reload_as_needed that could
3363 cause incorrect code to be generated if we did not check for it. */
3366 verify_initial_elim_offsets (void)
3370 if (!num_eliminable)
3373 #ifdef ELIMINABLE_REGS
3375 struct elim_table *ep;
3377 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3379 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3380 if (t != ep->initial_offset)
3385 INITIAL_FRAME_POINTER_OFFSET (t);
3386 if (t != reg_eliminate[0].initial_offset)
3393 /* Reset all offsets on eliminable registers to their initial values. */
3396 set_initial_elim_offsets (void)
3398 struct elim_table *ep = reg_eliminate;
3400 #ifdef ELIMINABLE_REGS
3401 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3403 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3404 ep->previous_offset = ep->offset = ep->initial_offset;
3407 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3408 ep->previous_offset = ep->offset = ep->initial_offset;
3411 num_not_at_initial_offset = 0;
3414 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3417 set_initial_eh_label_offset (rtx label)
3419 set_label_offsets (label, NULL_RTX, 1);
3422 /* Initialize the known label offsets.
3423 Set a known offset for each forced label to be at the initial offset
3424 of each elimination. We do this because we assume that all
3425 computed jumps occur from a location where each elimination is
3426 at its initial offset.
3427 For all other labels, show that we don't know the offsets. */
3430 set_initial_label_offsets (void)
3433 memset (offsets_known_at, 0, num_labels);
3435 for (x = forced_labels; x; x = XEXP (x, 1))
3437 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3439 for_each_eh_label (set_initial_eh_label_offset);
3442 /* Set all elimination offsets to the known values for the code label given
3446 set_offsets_for_label (rtx insn)
3449 int label_nr = CODE_LABEL_NUMBER (insn);
3450 struct elim_table *ep;
3452 num_not_at_initial_offset = 0;
3453 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3455 ep->offset = ep->previous_offset
3456 = offsets_at[label_nr - first_label_num][i];
3457 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3458 num_not_at_initial_offset++;
3462 /* See if anything that happened changes which eliminations are valid.
3463 For example, on the SPARC, whether or not the frame pointer can
3464 be eliminated can depend on what registers have been used. We need
3465 not check some conditions again (such as flag_omit_frame_pointer)
3466 since they can't have changed. */
3469 update_eliminables (HARD_REG_SET *pset)
3471 int previous_frame_pointer_needed = frame_pointer_needed;
3472 struct elim_table *ep;
3474 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3475 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3476 #ifdef ELIMINABLE_REGS
3477 || ! CAN_ELIMINATE (ep->from, ep->to)
3480 ep->can_eliminate = 0;
3482 /* Look for the case where we have discovered that we can't replace
3483 register A with register B and that means that we will now be
3484 trying to replace register A with register C. This means we can
3485 no longer replace register C with register B and we need to disable
3486 such an elimination, if it exists. This occurs often with A == ap,
3487 B == sp, and C == fp. */
3489 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3491 struct elim_table *op;
3494 if (! ep->can_eliminate && ep->can_eliminate_previous)
3496 /* Find the current elimination for ep->from, if there is a
3498 for (op = reg_eliminate;
3499 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3500 if (op->from == ep->from && op->can_eliminate)
3506 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3508 for (op = reg_eliminate;
3509 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3510 if (op->from == new_to && op->to == ep->to)
3511 op->can_eliminate = 0;
3515 /* See if any registers that we thought we could eliminate the previous
3516 time are no longer eliminable. If so, something has changed and we
3517 must spill the register. Also, recompute the number of eliminable
3518 registers and see if the frame pointer is needed; it is if there is
3519 no elimination of the frame pointer that we can perform. */
3521 frame_pointer_needed = 1;
3522 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3524 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3525 && ep->to != HARD_FRAME_POINTER_REGNUM)
3526 frame_pointer_needed = 0;
3528 if (! ep->can_eliminate && ep->can_eliminate_previous)
3530 ep->can_eliminate_previous = 0;
3531 SET_HARD_REG_BIT (*pset, ep->from);
3536 /* If we didn't need a frame pointer last time, but we do now, spill
3537 the hard frame pointer. */
3538 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3539 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3542 /* Initialize the table of registers to eliminate. */
3545 init_elim_table (void)
3547 struct elim_table *ep;
3548 #ifdef ELIMINABLE_REGS
3549 const struct elim_table_1 *ep1;
3553 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3555 /* Does this function require a frame pointer? */
3557 frame_pointer_needed = (! flag_omit_frame_pointer
3558 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3559 and restore sp for alloca. So we can't eliminate
3560 the frame pointer in that case. At some point,
3561 we should improve this by emitting the
3562 sp-adjusting insns for this case. */
3563 || (current_function_calls_alloca
3564 && EXIT_IGNORE_STACK)
3565 || current_function_accesses_prior_frames
3566 || FRAME_POINTER_REQUIRED);
3570 #ifdef ELIMINABLE_REGS
3571 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3572 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3574 ep->from = ep1->from;
3576 ep->can_eliminate = ep->can_eliminate_previous
3577 = (CAN_ELIMINATE (ep->from, ep->to)
3578 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3581 reg_eliminate[0].from = reg_eliminate_1[0].from;
3582 reg_eliminate[0].to = reg_eliminate_1[0].to;
3583 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3584 = ! frame_pointer_needed;
3587 /* Count the number of eliminable registers and build the FROM and TO
3588 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3589 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3590 We depend on this. */
3591 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3593 num_eliminable += ep->can_eliminate;
3594 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3595 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3599 /* Kick all pseudos out of hard register REGNO.
3601 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3602 because we found we can't eliminate some register. In the case, no pseudos
3603 are allowed to be in the register, even if they are only in a block that
3604 doesn't require spill registers, unlike the case when we are spilling this
3605 hard reg to produce another spill register.
3607 Return nonzero if any pseudos needed to be kicked out. */
3610 spill_hard_reg (unsigned int regno, int cant_eliminate)
3616 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3617 regs_ever_live[regno] = 1;
3620 /* Spill every pseudo reg that was allocated to this reg
3621 or to something that overlaps this reg. */
3623 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3624 if (reg_renumber[i] >= 0
3625 && (unsigned int) reg_renumber[i] <= regno
3626 && ((unsigned int) reg_renumber[i]
3627 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3628 [PSEUDO_REGNO_MODE (i)]
3630 SET_REGNO_REG_SET (&spilled_pseudos, i);
3633 /* After find_reload_regs has been run for all insn that need reloads,
3634 and/or spill_hard_regs was called, this function is used to actually
3635 spill pseudo registers and try to reallocate them. It also sets up the
3636 spill_regs array for use by choose_reload_regs. */
3639 finish_spills (int global)
3641 struct insn_chain *chain;
3642 int something_changed = 0;
3644 reg_set_iterator rsi;
3646 /* Build the spill_regs array for the function. */
3647 /* If there are some registers still to eliminate and one of the spill regs
3648 wasn't ever used before, additional stack space may have to be
3649 allocated to store this register. Thus, we may have changed the offset
3650 between the stack and frame pointers, so mark that something has changed.
3652 One might think that we need only set VAL to 1 if this is a call-used
3653 register. However, the set of registers that must be saved by the
3654 prologue is not identical to the call-used set. For example, the
3655 register used by the call insn for the return PC is a call-used register,
3656 but must be saved by the prologue. */
3659 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3660 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3662 spill_reg_order[i] = n_spills;
3663 spill_regs[n_spills++] = i;
3664 if (num_eliminable && ! regs_ever_live[i])
3665 something_changed = 1;
3666 regs_ever_live[i] = 1;
3669 spill_reg_order[i] = -1;
3671 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3673 /* Record the current hard register the pseudo is allocated to in
3674 pseudo_previous_regs so we avoid reallocating it to the same
3675 hard reg in a later pass. */
3676 gcc_assert (reg_renumber[i] >= 0);
3678 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3679 /* Mark it as no longer having a hard register home. */
3680 reg_renumber[i] = -1;
3681 /* We will need to scan everything again. */
3682 something_changed = 1;
3685 /* Retry global register allocation if possible. */
3688 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3689 /* For every insn that needs reloads, set the registers used as spill
3690 regs in pseudo_forbidden_regs for every pseudo live across the
3692 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3694 EXECUTE_IF_SET_IN_REG_SET
3695 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3697 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3698 chain->used_spill_regs);
3700 EXECUTE_IF_SET_IN_REG_SET
3701 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3703 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3704 chain->used_spill_regs);
3708 /* Retry allocating the spilled pseudos. For each reg, merge the
3709 various reg sets that indicate which hard regs can't be used,
3710 and call retry_global_alloc.
3711 We change spill_pseudos here to only contain pseudos that did not
3712 get a new hard register. */
3713 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3714 if (reg_old_renumber[i] != reg_renumber[i])
3716 HARD_REG_SET forbidden;
3717 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3718 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3719 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3720 retry_global_alloc (i, forbidden);
3721 if (reg_renumber[i] >= 0)
3722 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3726 /* Fix up the register information in the insn chain.
3727 This involves deleting those of the spilled pseudos which did not get
3728 a new hard register home from the live_{before,after} sets. */
3729 for (chain = reload_insn_chain; chain; chain = chain->next)
3731 HARD_REG_SET used_by_pseudos;
3732 HARD_REG_SET used_by_pseudos2;
3734 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3735 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3737 /* Mark any unallocated hard regs as available for spills. That
3738 makes inheritance work somewhat better. */
3739 if (chain->need_reload)
3741 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3742 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3743 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3745 /* Save the old value for the sanity test below. */
3746 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3748 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3749 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3750 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3751 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3753 /* Make sure we only enlarge the set. */
3754 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3760 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3761 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3763 int regno = reg_renumber[i];
3764 if (reg_old_renumber[i] == regno)
3767 alter_reg (i, reg_old_renumber[i]);
3768 reg_old_renumber[i] = regno;
3772 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3774 fprintf (dump_file, " Register %d now in %d.\n\n",
3775 i, reg_renumber[i]);
3779 return something_changed;
3782 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3785 scan_paradoxical_subregs (rtx x)
3789 enum rtx_code code = GET_CODE (x);
3799 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3807 if (REG_P (SUBREG_REG (x))
3808 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3809 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3810 = GET_MODE_SIZE (GET_MODE (x));
3817 fmt = GET_RTX_FORMAT (code);
3818 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3821 scan_paradoxical_subregs (XEXP (x, i));
3822 else if (fmt[i] == 'E')
3825 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3826 scan_paradoxical_subregs (XVECEXP (x, i, j));
3831 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
3832 examine all of the reload insns between PREV and NEXT exclusive, and
3833 annotate all that may trap. */
3836 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
3838 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
3839 unsigned int trap_count;
3845 if (may_trap_p (PATTERN (insn)))
3849 remove_note (insn, note);
3853 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
3854 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
3858 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0), REG_NOTES (i));
3862 /* Reload pseudo-registers into hard regs around each insn as needed.
3863 Additional register load insns are output before the insn that needs it
3864 and perhaps store insns after insns that modify the reloaded pseudo reg.
3866 reg_last_reload_reg and reg_reloaded_contents keep track of
3867 which registers are already available in reload registers.
3868 We update these for the reloads that we perform,
3869 as the insns are scanned. */
3872 reload_as_needed (int live_known)
3874 struct insn_chain *chain;
3875 #if defined (AUTO_INC_DEC)
3880 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3881 memset (spill_reg_store, 0, sizeof spill_reg_store);
3882 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
3883 reg_has_output_reload = XNEWVEC (char, max_regno);
3884 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3885 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3887 set_initial_elim_offsets ();
3889 for (chain = reload_insn_chain; chain; chain = chain->next)
3892 rtx insn = chain->insn;
3893 rtx old_next = NEXT_INSN (insn);
3895 /* If we pass a label, copy the offsets from the label information
3896 into the current offsets of each elimination. */
3898 set_offsets_for_label (insn);
3900 else if (INSN_P (insn))
3902 rtx oldpat = copy_rtx (PATTERN (insn));
3904 /* If this is a USE and CLOBBER of a MEM, ensure that any
3905 references to eliminable registers have been removed. */
3907 if ((GET_CODE (PATTERN (insn)) == USE
3908 || GET_CODE (PATTERN (insn)) == CLOBBER)
3909 && MEM_P (XEXP (PATTERN (insn), 0)))
3910 XEXP (XEXP (PATTERN (insn), 0), 0)
3911 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3912 GET_MODE (XEXP (PATTERN (insn), 0)),
3915 /* If we need to do register elimination processing, do so.
3916 This might delete the insn, in which case we are done. */
3917 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3919 eliminate_regs_in_insn (insn, 1);
3922 update_eliminable_offsets ();
3927 /* If need_elim is nonzero but need_reload is zero, one might think
3928 that we could simply set n_reloads to 0. However, find_reloads
3929 could have done some manipulation of the insn (such as swapping
3930 commutative operands), and these manipulations are lost during
3931 the first pass for every insn that needs register elimination.
3932 So the actions of find_reloads must be redone here. */
3934 if (! chain->need_elim && ! chain->need_reload
3935 && ! chain->need_operand_change)
3937 /* First find the pseudo regs that must be reloaded for this insn.
3938 This info is returned in the tables reload_... (see reload.h).
3939 Also modify the body of INSN by substituting RELOAD
3940 rtx's for those pseudo regs. */
3943 memset (reg_has_output_reload, 0, max_regno);
3944 CLEAR_HARD_REG_SET (reg_is_output_reload);
3946 find_reloads (insn, 1, spill_indirect_levels, live_known,
3952 rtx next = NEXT_INSN (insn);
3955 prev = PREV_INSN (insn);
3957 /* Now compute which reload regs to reload them into. Perhaps
3958 reusing reload regs from previous insns, or else output
3959 load insns to reload them. Maybe output store insns too.
3960 Record the choices of reload reg in reload_reg_rtx. */
3961 choose_reload_regs (chain);
3963 /* Merge any reloads that we didn't combine for fear of
3964 increasing the number of spill registers needed but now
3965 discover can be safely merged. */
3966 if (SMALL_REGISTER_CLASSES)
3967 merge_assigned_reloads (insn);
3969 /* Generate the insns to reload operands into or out of
3970 their reload regs. */
3971 emit_reload_insns (chain);
3973 /* Substitute the chosen reload regs from reload_reg_rtx
3974 into the insn's body (or perhaps into the bodies of other
3975 load and store insn that we just made for reloading
3976 and that we moved the structure into). */
3977 subst_reloads (insn);
3979 /* Adjust the exception region notes for loads and stores. */
3980 if (flag_non_call_exceptions && !CALL_P (insn))
3981 fixup_eh_region_note (insn, prev, next);
3983 /* If this was an ASM, make sure that all the reload insns
3984 we have generated are valid. If not, give an error
3986 if (asm_noperands (PATTERN (insn)) >= 0)
3987 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3988 if (p != insn && INSN_P (p)
3989 && GET_CODE (PATTERN (p)) != USE
3990 && (recog_memoized (p) < 0
3991 || (extract_insn (p), ! constrain_operands (1))))
3993 error_for_asm (insn,
3994 "%<asm%> operand requires "
3995 "impossible reload");
4000 if (num_eliminable && chain->need_elim)
4001 update_eliminable_offsets ();
4003 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4004 is no longer validly lying around to save a future reload.
4005 Note that this does not detect pseudos that were reloaded
4006 for this insn in order to be stored in
4007 (obeying register constraints). That is correct; such reload
4008 registers ARE still valid. */
4009 note_stores (oldpat, forget_old_reloads_1, NULL);
4011 /* There may have been CLOBBER insns placed after INSN. So scan
4012 between INSN and NEXT and use them to forget old reloads. */
4013 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4014 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4015 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4018 /* Likewise for regs altered by auto-increment in this insn.
4019 REG_INC notes have been changed by reloading:
4020 find_reloads_address_1 records substitutions for them,
4021 which have been performed by subst_reloads above. */
4022 for (i = n_reloads - 1; i >= 0; i--)
4024 rtx in_reg = rld[i].in_reg;
4027 enum rtx_code code = GET_CODE (in_reg);
4028 /* PRE_INC / PRE_DEC will have the reload register ending up
4029 with the same value as the stack slot, but that doesn't
4030 hold true for POST_INC / POST_DEC. Either we have to
4031 convert the memory access to a true POST_INC / POST_DEC,
4032 or we can't use the reload register for inheritance. */
4033 if ((code == POST_INC || code == POST_DEC)
4034 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4035 REGNO (rld[i].reg_rtx))
4036 /* Make sure it is the inc/dec pseudo, and not
4037 some other (e.g. output operand) pseudo. */
4038 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4039 == REGNO (XEXP (in_reg, 0))))
4042 rtx reload_reg = rld[i].reg_rtx;
4043 enum machine_mode mode = GET_MODE (reload_reg);
4047 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4049 /* We really want to ignore REG_INC notes here, so
4050 use PATTERN (p) as argument to reg_set_p . */
4051 if (reg_set_p (reload_reg, PATTERN (p)))
4053 n = count_occurrences (PATTERN (p), reload_reg, 0);
4058 n = validate_replace_rtx (reload_reg,
4059 gen_rtx_fmt_e (code,
4064 /* We must also verify that the constraints
4065 are met after the replacement. */
4068 n = constrain_operands (1);
4072 /* If the constraints were not met, then
4073 undo the replacement. */
4076 validate_replace_rtx (gen_rtx_fmt_e (code,
4089 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4091 /* Mark this as having an output reload so that the
4092 REG_INC processing code below won't invalidate
4093 the reload for inheritance. */
4094 SET_HARD_REG_BIT (reg_is_output_reload,
4095 REGNO (reload_reg));
4096 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4099 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4102 else if ((code == PRE_INC || code == PRE_DEC)
4103 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4104 REGNO (rld[i].reg_rtx))
4105 /* Make sure it is the inc/dec pseudo, and not
4106 some other (e.g. output operand) pseudo. */
4107 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4108 == REGNO (XEXP (in_reg, 0))))
4110 SET_HARD_REG_BIT (reg_is_output_reload,
4111 REGNO (rld[i].reg_rtx));
4112 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4116 /* If a pseudo that got a hard register is auto-incremented,
4117 we must purge records of copying it into pseudos without
4119 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4120 if (REG_NOTE_KIND (x) == REG_INC)
4122 /* See if this pseudo reg was reloaded in this insn.
4123 If so, its last-reload info is still valid
4124 because it is based on this insn's reload. */
4125 for (i = 0; i < n_reloads; i++)
4126 if (rld[i].out == XEXP (x, 0))
4130 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4134 /* A reload reg's contents are unknown after a label. */
4136 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4138 /* Don't assume a reload reg is still good after a call insn
4139 if it is a call-used reg, or if it contains a value that will
4140 be partially clobbered by the call. */
4141 else if (CALL_P (insn))
4143 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4144 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4149 free (reg_last_reload_reg);
4150 free (reg_has_output_reload);
4153 /* Discard all record of any value reloaded from X,
4154 or reloaded in X from someplace else;
4155 unless X is an output reload reg of the current insn.
4157 X may be a hard reg (the reload reg)
4158 or it may be a pseudo reg that was reloaded from. */
4161 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4162 void *data ATTRIBUTE_UNUSED)
4167 /* note_stores does give us subregs of hard regs,
4168 subreg_regno_offset requires a hard reg. */
4169 while (GET_CODE (x) == SUBREG)
4171 /* We ignore the subreg offset when calculating the regno,
4172 because we are using the entire underlying hard register
4182 if (regno >= FIRST_PSEUDO_REGISTER)
4188 nr = hard_regno_nregs[regno][GET_MODE (x)];
4189 /* Storing into a spilled-reg invalidates its contents.
4190 This can happen if a block-local pseudo is allocated to that reg
4191 and it wasn't spilled because this block's total need is 0.
4192 Then some insn might have an optional reload and use this reg. */
4193 for (i = 0; i < nr; i++)
4194 /* But don't do this if the reg actually serves as an output
4195 reload reg in the current instruction. */
4197 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4199 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4200 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4201 spill_reg_store[regno + i] = 0;
4205 /* Since value of X has changed,
4206 forget any value previously copied from it. */
4209 /* But don't forget a copy if this is the output reload
4210 that establishes the copy's validity. */
4211 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4212 reg_last_reload_reg[regno + nr] = 0;
4215 /* The following HARD_REG_SETs indicate when each hard register is
4216 used for a reload of various parts of the current insn. */
4218 /* If reg is unavailable for all reloads. */
4219 static HARD_REG_SET reload_reg_unavailable;
4220 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4221 static HARD_REG_SET reload_reg_used;
4222 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4223 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4224 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4225 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4226 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4227 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4228 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4229 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4230 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4231 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4232 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4233 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4234 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4235 static HARD_REG_SET reload_reg_used_in_op_addr;
4236 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4237 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4238 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4239 static HARD_REG_SET reload_reg_used_in_insn;
4240 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4241 static HARD_REG_SET reload_reg_used_in_other_addr;
4243 /* If reg is in use as a reload reg for any sort of reload. */
4244 static HARD_REG_SET reload_reg_used_at_all;
4246 /* If reg is use as an inherited reload. We just mark the first register
4248 static HARD_REG_SET reload_reg_used_for_inherit;
4250 /* Records which hard regs are used in any way, either as explicit use or
4251 by being allocated to a pseudo during any point of the current insn. */
4252 static HARD_REG_SET reg_used_in_insn;
4254 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4255 TYPE. MODE is used to indicate how many consecutive regs are
4259 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4260 enum machine_mode mode)
4262 unsigned int nregs = hard_regno_nregs[regno][mode];
4265 for (i = regno; i < nregs + regno; i++)
4270 SET_HARD_REG_BIT (reload_reg_used, i);
4273 case RELOAD_FOR_INPUT_ADDRESS:
4274 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4277 case RELOAD_FOR_INPADDR_ADDRESS:
4278 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4281 case RELOAD_FOR_OUTPUT_ADDRESS:
4282 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4285 case RELOAD_FOR_OUTADDR_ADDRESS:
4286 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4289 case RELOAD_FOR_OPERAND_ADDRESS:
4290 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4293 case RELOAD_FOR_OPADDR_ADDR:
4294 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4297 case RELOAD_FOR_OTHER_ADDRESS:
4298 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4301 case RELOAD_FOR_INPUT:
4302 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4305 case RELOAD_FOR_OUTPUT:
4306 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4309 case RELOAD_FOR_INSN:
4310 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4314 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4318 /* Similarly, but show REGNO is no longer in use for a reload. */
4321 clear_reload_reg_in_use (unsigned int regno, int opnum,
4322 enum reload_type type, enum machine_mode mode)
4324 unsigned int nregs = hard_regno_nregs[regno][mode];
4325 unsigned int start_regno, end_regno, r;
4327 /* A complication is that for some reload types, inheritance might
4328 allow multiple reloads of the same types to share a reload register.
4329 We set check_opnum if we have to check only reloads with the same
4330 operand number, and check_any if we have to check all reloads. */
4331 int check_opnum = 0;
4333 HARD_REG_SET *used_in_set;
4338 used_in_set = &reload_reg_used;
4341 case RELOAD_FOR_INPUT_ADDRESS:
4342 used_in_set = &reload_reg_used_in_input_addr[opnum];
4345 case RELOAD_FOR_INPADDR_ADDRESS:
4347 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4350 case RELOAD_FOR_OUTPUT_ADDRESS:
4351 used_in_set = &reload_reg_used_in_output_addr[opnum];
4354 case RELOAD_FOR_OUTADDR_ADDRESS:
4356 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4359 case RELOAD_FOR_OPERAND_ADDRESS:
4360 used_in_set = &reload_reg_used_in_op_addr;
4363 case RELOAD_FOR_OPADDR_ADDR:
4365 used_in_set = &reload_reg_used_in_op_addr_reload;
4368 case RELOAD_FOR_OTHER_ADDRESS:
4369 used_in_set = &reload_reg_used_in_other_addr;
4373 case RELOAD_FOR_INPUT:
4374 used_in_set = &reload_reg_used_in_input[opnum];
4377 case RELOAD_FOR_OUTPUT:
4378 used_in_set = &reload_reg_used_in_output[opnum];
4381 case RELOAD_FOR_INSN:
4382 used_in_set = &reload_reg_used_in_insn;
4387 /* We resolve conflicts with remaining reloads of the same type by
4388 excluding the intervals of reload registers by them from the
4389 interval of freed reload registers. Since we only keep track of
4390 one set of interval bounds, we might have to exclude somewhat
4391 more than what would be necessary if we used a HARD_REG_SET here.
4392 But this should only happen very infrequently, so there should
4393 be no reason to worry about it. */
4395 start_regno = regno;
4396 end_regno = regno + nregs;
4397 if (check_opnum || check_any)
4399 for (i = n_reloads - 1; i >= 0; i--)
4401 if (rld[i].when_needed == type
4402 && (check_any || rld[i].opnum == opnum)
4405 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4406 unsigned int conflict_end
4408 + hard_regno_nregs[conflict_start][rld[i].mode]);
4410 /* If there is an overlap with the first to-be-freed register,
4411 adjust the interval start. */
4412 if (conflict_start <= start_regno && conflict_end > start_regno)
4413 start_regno = conflict_end;
4414 /* Otherwise, if there is a conflict with one of the other
4415 to-be-freed registers, adjust the interval end. */
4416 if (conflict_start > start_regno && conflict_start < end_regno)
4417 end_regno = conflict_start;
4422 for (r = start_regno; r < end_regno; r++)
4423 CLEAR_HARD_REG_BIT (*used_in_set, r);
4426 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4427 specified by OPNUM and TYPE. */
4430 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4434 /* In use for a RELOAD_OTHER means it's not available for anything. */
4435 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4436 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4442 /* In use for anything means we can't use it for RELOAD_OTHER. */
4443 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4444 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4445 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4446 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4449 for (i = 0; i < reload_n_operands; i++)
4450 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4451 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4452 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4453 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4454 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4455 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4460 case RELOAD_FOR_INPUT:
4461 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4462 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4465 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4468 /* If it is used for some other input, can't use it. */
4469 for (i = 0; i < reload_n_operands; i++)
4470 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4473 /* If it is used in a later operand's address, can't use it. */
4474 for (i = opnum + 1; i < reload_n_operands; i++)
4475 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4476 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4481 case RELOAD_FOR_INPUT_ADDRESS:
4482 /* Can't use a register if it is used for an input address for this
4483 operand or used as an input in an earlier one. */
4484 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4485 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4488 for (i = 0; i < opnum; i++)
4489 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4494 case RELOAD_FOR_INPADDR_ADDRESS:
4495 /* Can't use a register if it is used for an input address
4496 for this operand or used as an input in an earlier
4498 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4501 for (i = 0; i < opnum; i++)
4502 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4507 case RELOAD_FOR_OUTPUT_ADDRESS:
4508 /* Can't use a register if it is used for an output address for this
4509 operand or used as an output in this or a later operand. Note
4510 that multiple output operands are emitted in reverse order, so
4511 the conflicting ones are those with lower indices. */
4512 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4515 for (i = 0; i <= opnum; i++)
4516 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4521 case RELOAD_FOR_OUTADDR_ADDRESS:
4522 /* Can't use a register if it is used for an output address
4523 for this operand or used as an output in this or a
4524 later operand. Note that multiple output operands are
4525 emitted in reverse order, so the conflicting ones are
4526 those with lower indices. */
4527 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4530 for (i = 0; i <= opnum; i++)
4531 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4536 case RELOAD_FOR_OPERAND_ADDRESS:
4537 for (i = 0; i < reload_n_operands; i++)
4538 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4541 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4542 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4544 case RELOAD_FOR_OPADDR_ADDR:
4545 for (i = 0; i < reload_n_operands; i++)
4546 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4549 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4551 case RELOAD_FOR_OUTPUT:
4552 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4553 outputs, or an operand address for this or an earlier output.
4554 Note that multiple output operands are emitted in reverse order,
4555 so the conflicting ones are those with higher indices. */
4556 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4559 for (i = 0; i < reload_n_operands; i++)
4560 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4563 for (i = opnum; i < reload_n_operands; i++)
4564 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4565 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4570 case RELOAD_FOR_INSN:
4571 for (i = 0; i < reload_n_operands; i++)
4572 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4573 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4576 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4577 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4579 case RELOAD_FOR_OTHER_ADDRESS:
4580 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4587 /* Return 1 if the value in reload reg REGNO, as used by a reload
4588 needed for the part of the insn specified by OPNUM and TYPE,
4589 is still available in REGNO at the end of the insn.
4591 We can assume that the reload reg was already tested for availability
4592 at the time it is needed, and we should not check this again,
4593 in case the reg has already been marked in use. */
4596 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4603 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4604 its value must reach the end. */
4607 /* If this use is for part of the insn,
4608 its value reaches if no subsequent part uses the same register.
4609 Just like the above function, don't try to do this with lots
4612 case RELOAD_FOR_OTHER_ADDRESS:
4613 /* Here we check for everything else, since these don't conflict
4614 with anything else and everything comes later. */
4616 for (i = 0; i < reload_n_operands; i++)
4617 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4618 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4619 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4620 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4621 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4622 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4625 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4626 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4627 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4628 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4630 case RELOAD_FOR_INPUT_ADDRESS:
4631 case RELOAD_FOR_INPADDR_ADDRESS:
4632 /* Similar, except that we check only for this and subsequent inputs
4633 and the address of only subsequent inputs and we do not need
4634 to check for RELOAD_OTHER objects since they are known not to
4637 for (i = opnum; i < reload_n_operands; i++)
4638 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4641 for (i = opnum + 1; i < reload_n_operands; i++)
4642 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4643 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4646 for (i = 0; i < reload_n_operands; i++)
4647 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4648 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4649 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4652 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4655 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4656 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4657 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4659 case RELOAD_FOR_INPUT:
4660 /* Similar to input address, except we start at the next operand for
4661 both input and input address and we do not check for
4662 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4665 for (i = opnum + 1; i < reload_n_operands; i++)
4666 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4667 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4668 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4671 /* ... fall through ... */
4673 case RELOAD_FOR_OPERAND_ADDRESS:
4674 /* Check outputs and their addresses. */
4676 for (i = 0; i < reload_n_operands; i++)
4677 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4678 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4679 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4682 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4684 case RELOAD_FOR_OPADDR_ADDR:
4685 for (i = 0; i < reload_n_operands; i++)
4686 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4687 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4688 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4691 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4692 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4693 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4695 case RELOAD_FOR_INSN:
4696 /* These conflict with other outputs with RELOAD_OTHER. So
4697 we need only check for output addresses. */
4699 opnum = reload_n_operands;
4701 /* ... fall through ... */
4703 case RELOAD_FOR_OUTPUT:
4704 case RELOAD_FOR_OUTPUT_ADDRESS:
4705 case RELOAD_FOR_OUTADDR_ADDRESS:
4706 /* We already know these can't conflict with a later output. So the
4707 only thing to check are later output addresses.
4708 Note that multiple output operands are emitted in reverse order,
4709 so the conflicting ones are those with lower indices. */
4710 for (i = 0; i < opnum; i++)
4711 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4712 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4722 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4725 This function uses the same algorithm as reload_reg_free_p above. */
4728 reloads_conflict (int r1, int r2)
4730 enum reload_type r1_type = rld[r1].when_needed;
4731 enum reload_type r2_type = rld[r2].when_needed;
4732 int r1_opnum = rld[r1].opnum;
4733 int r2_opnum = rld[r2].opnum;
4735 /* RELOAD_OTHER conflicts with everything. */
4736 if (r2_type == RELOAD_OTHER)
4739 /* Otherwise, check conflicts differently for each type. */
4743 case RELOAD_FOR_INPUT:
4744 return (r2_type == RELOAD_FOR_INSN
4745 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4746 || r2_type == RELOAD_FOR_OPADDR_ADDR
4747 || r2_type == RELOAD_FOR_INPUT
4748 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4749 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4750 && r2_opnum > r1_opnum));
4752 case RELOAD_FOR_INPUT_ADDRESS:
4753 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4754 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4756 case RELOAD_FOR_INPADDR_ADDRESS:
4757 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4758 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4760 case RELOAD_FOR_OUTPUT_ADDRESS:
4761 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4762 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4764 case RELOAD_FOR_OUTADDR_ADDRESS:
4765 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4766 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4768 case RELOAD_FOR_OPERAND_ADDRESS:
4769 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4770 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4772 case RELOAD_FOR_OPADDR_ADDR:
4773 return (r2_type == RELOAD_FOR_INPUT
4774 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4776 case RELOAD_FOR_OUTPUT:
4777 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4778 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4779 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4780 && r2_opnum >= r1_opnum));
4782 case RELOAD_FOR_INSN:
4783 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4784 || r2_type == RELOAD_FOR_INSN
4785 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4787 case RELOAD_FOR_OTHER_ADDRESS:
4788 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4798 /* Indexed by reload number, 1 if incoming value
4799 inherited from previous insns. */
4800 static char reload_inherited[MAX_RELOADS];
4802 /* For an inherited reload, this is the insn the reload was inherited from,
4803 if we know it. Otherwise, this is 0. */
4804 static rtx reload_inheritance_insn[MAX_RELOADS];
4806 /* If nonzero, this is a place to get the value of the reload,
4807 rather than using reload_in. */
4808 static rtx reload_override_in[MAX_RELOADS];
4810 /* For each reload, the hard register number of the register used,
4811 or -1 if we did not need a register for this reload. */
4812 static int reload_spill_index[MAX_RELOADS];
4814 /* Subroutine of free_for_value_p, used to check a single register.
4815 START_REGNO is the starting regno of the full reload register
4816 (possibly comprising multiple hard registers) that we are considering. */
4819 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4820 enum reload_type type, rtx value, rtx out,
4821 int reloadnum, int ignore_address_reloads)
4824 /* Set if we see an input reload that must not share its reload register
4825 with any new earlyclobber, but might otherwise share the reload
4826 register with an output or input-output reload. */
4827 int check_earlyclobber = 0;
4831 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4834 if (out == const0_rtx)
4840 /* We use some pseudo 'time' value to check if the lifetimes of the
4841 new register use would overlap with the one of a previous reload
4842 that is not read-only or uses a different value.
4843 The 'time' used doesn't have to be linear in any shape or form, just
4845 Some reload types use different 'buckets' for each operand.
4846 So there are MAX_RECOG_OPERANDS different time values for each
4848 We compute TIME1 as the time when the register for the prospective
4849 new reload ceases to be live, and TIME2 for each existing
4850 reload as the time when that the reload register of that reload
4852 Where there is little to be gained by exact lifetime calculations,
4853 we just make conservative assumptions, i.e. a longer lifetime;
4854 this is done in the 'default:' cases. */
4857 case RELOAD_FOR_OTHER_ADDRESS:
4858 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4859 time1 = copy ? 0 : 1;
4862 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4864 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4865 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4866 respectively, to the time values for these, we get distinct time
4867 values. To get distinct time values for each operand, we have to
4868 multiply opnum by at least three. We round that up to four because
4869 multiply by four is often cheaper. */
4870 case RELOAD_FOR_INPADDR_ADDRESS:
4871 time1 = opnum * 4 + 2;
4873 case RELOAD_FOR_INPUT_ADDRESS:
4874 time1 = opnum * 4 + 3;
4876 case RELOAD_FOR_INPUT:
4877 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4878 executes (inclusive). */
4879 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4881 case RELOAD_FOR_OPADDR_ADDR:
4883 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4884 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4886 case RELOAD_FOR_OPERAND_ADDRESS:
4887 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4889 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4891 case RELOAD_FOR_OUTADDR_ADDRESS:
4892 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4894 case RELOAD_FOR_OUTPUT_ADDRESS:
4895 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4898 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4901 for (i = 0; i < n_reloads; i++)
4903 rtx reg = rld[i].reg_rtx;
4904 if (reg && REG_P (reg)
4905 && ((unsigned) regno - true_regnum (reg)
4906 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
4909 rtx other_input = rld[i].in;
4911 /* If the other reload loads the same input value, that
4912 will not cause a conflict only if it's loading it into
4913 the same register. */
4914 if (true_regnum (reg) != start_regno)
4915 other_input = NULL_RTX;
4916 if (! other_input || ! rtx_equal_p (other_input, value)
4917 || rld[i].out || out)
4920 switch (rld[i].when_needed)
4922 case RELOAD_FOR_OTHER_ADDRESS:
4925 case RELOAD_FOR_INPADDR_ADDRESS:
4926 /* find_reloads makes sure that a
4927 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4928 by at most one - the first -
4929 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4930 address reload is inherited, the address address reload
4931 goes away, so we can ignore this conflict. */
4932 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4933 && ignore_address_reloads
4934 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4935 Then the address address is still needed to store
4936 back the new address. */
4937 && ! rld[reloadnum].out)
4939 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4940 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4942 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4943 && ignore_address_reloads
4944 /* Unless we are reloading an auto_inc expression. */
4945 && ! rld[reloadnum].out)
4947 time2 = rld[i].opnum * 4 + 2;
4949 case RELOAD_FOR_INPUT_ADDRESS:
4950 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4951 && ignore_address_reloads
4952 && ! rld[reloadnum].out)
4954 time2 = rld[i].opnum * 4 + 3;
4956 case RELOAD_FOR_INPUT:
4957 time2 = rld[i].opnum * 4 + 4;
4958 check_earlyclobber = 1;
4960 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4961 == MAX_RECOG_OPERAND * 4 */
4962 case RELOAD_FOR_OPADDR_ADDR:
4963 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4964 && ignore_address_reloads
4965 && ! rld[reloadnum].out)
4967 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4969 case RELOAD_FOR_OPERAND_ADDRESS:
4970 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4971 check_earlyclobber = 1;
4973 case RELOAD_FOR_INSN:
4974 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4976 case RELOAD_FOR_OUTPUT:
4977 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4978 instruction is executed. */
4979 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4981 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4982 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4984 case RELOAD_FOR_OUTADDR_ADDRESS:
4985 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4986 && ignore_address_reloads
4987 && ! rld[reloadnum].out)
4989 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4991 case RELOAD_FOR_OUTPUT_ADDRESS:
4992 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4995 /* If there is no conflict in the input part, handle this
4996 like an output reload. */
4997 if (! rld[i].in || rtx_equal_p (other_input, value))
4999 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5000 /* Earlyclobbered outputs must conflict with inputs. */
5001 if (earlyclobber_operand_p (rld[i].out))
5002 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5007 /* RELOAD_OTHER might be live beyond instruction execution,
5008 but this is not obvious when we set time2 = 1. So check
5009 here if there might be a problem with the new reload
5010 clobbering the register used by the RELOAD_OTHER. */
5018 && (! rld[i].in || rld[i].out
5019 || ! rtx_equal_p (other_input, value)))
5020 || (out && rld[reloadnum].out_reg
5021 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5027 /* Earlyclobbered outputs must conflict with inputs. */
5028 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5034 /* Return 1 if the value in reload reg REGNO, as used by a reload
5035 needed for the part of the insn specified by OPNUM and TYPE,
5036 may be used to load VALUE into it.
5038 MODE is the mode in which the register is used, this is needed to
5039 determine how many hard regs to test.
5041 Other read-only reloads with the same value do not conflict
5042 unless OUT is nonzero and these other reloads have to live while
5043 output reloads live.
5044 If OUT is CONST0_RTX, this is a special case: it means that the
5045 test should not be for using register REGNO as reload register, but
5046 for copying from register REGNO into the reload register.
5048 RELOADNUM is the number of the reload we want to load this value for;
5049 a reload does not conflict with itself.
5051 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5052 reloads that load an address for the very reload we are considering.
5054 The caller has to make sure that there is no conflict with the return
5058 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5059 enum reload_type type, rtx value, rtx out, int reloadnum,
5060 int ignore_address_reloads)
5062 int nregs = hard_regno_nregs[regno][mode];
5064 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5065 value, out, reloadnum,
5066 ignore_address_reloads))
5071 /* Return nonzero if the rtx X is invariant over the current function. */
5072 /* ??? Actually, the places where we use this expect exactly what is
5073 tested here, and not everything that is function invariant. In
5074 particular, the frame pointer and arg pointer are special cased;
5075 pic_offset_table_rtx is not, and we must not spill these things to
5079 function_invariant_p (rtx x)
5083 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5085 if (GET_CODE (x) == PLUS
5086 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5087 && CONSTANT_P (XEXP (x, 1)))
5092 /* Determine whether the reload reg X overlaps any rtx'es used for
5093 overriding inheritance. Return nonzero if so. */
5096 conflicts_with_override (rtx x)
5099 for (i = 0; i < n_reloads; i++)
5100 if (reload_override_in[i]
5101 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5106 /* Give an error message saying we failed to find a reload for INSN,
5107 and clear out reload R. */
5109 failed_reload (rtx insn, int r)
5111 if (asm_noperands (PATTERN (insn)) < 0)
5112 /* It's the compiler's fault. */
5113 fatal_insn ("could not find a spill register", insn);
5115 /* It's the user's fault; the operand's mode and constraint
5116 don't match. Disable this reload so we don't crash in final. */
5117 error_for_asm (insn,
5118 "%<asm%> operand constraint incompatible with operand size");
5122 rld[r].optional = 1;
5123 rld[r].secondary_p = 1;
5126 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5127 for reload R. If it's valid, get an rtx for it. Return nonzero if
5130 set_reload_reg (int i, int r)
5133 rtx reg = spill_reg_rtx[i];
5135 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5136 spill_reg_rtx[i] = reg
5137 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5139 regno = true_regnum (reg);
5141 /* Detect when the reload reg can't hold the reload mode.
5142 This used to be one `if', but Sequent compiler can't handle that. */
5143 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5145 enum machine_mode test_mode = VOIDmode;
5147 test_mode = GET_MODE (rld[r].in);
5148 /* If rld[r].in has VOIDmode, it means we will load it
5149 in whatever mode the reload reg has: to wit, rld[r].mode.
5150 We have already tested that for validity. */
5151 /* Aside from that, we need to test that the expressions
5152 to reload from or into have modes which are valid for this
5153 reload register. Otherwise the reload insns would be invalid. */
5154 if (! (rld[r].in != 0 && test_mode != VOIDmode
5155 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5156 if (! (rld[r].out != 0
5157 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5159 /* The reg is OK. */
5162 /* Mark as in use for this insn the reload regs we use
5164 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5165 rld[r].when_needed, rld[r].mode);
5167 rld[r].reg_rtx = reg;
5168 reload_spill_index[r] = spill_regs[i];
5175 /* Find a spill register to use as a reload register for reload R.
5176 LAST_RELOAD is nonzero if this is the last reload for the insn being
5179 Set rld[R].reg_rtx to the register allocated.
5181 We return 1 if successful, or 0 if we couldn't find a spill reg and
5182 we didn't change anything. */
5185 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5190 /* If we put this reload ahead, thinking it is a group,
5191 then insist on finding a group. Otherwise we can grab a
5192 reg that some other reload needs.
5193 (That can happen when we have a 68000 DATA_OR_FP_REG
5194 which is a group of data regs or one fp reg.)
5195 We need not be so restrictive if there are no more reloads
5198 ??? Really it would be nicer to have smarter handling
5199 for that kind of reg class, where a problem like this is normal.
5200 Perhaps those classes should be avoided for reloading
5201 by use of more alternatives. */
5203 int force_group = rld[r].nregs > 1 && ! last_reload;
5205 /* If we want a single register and haven't yet found one,
5206 take any reg in the right class and not in use.
5207 If we want a consecutive group, here is where we look for it.
5209 We use two passes so we can first look for reload regs to
5210 reuse, which are already in use for other reloads in this insn,
5211 and only then use additional registers.
5212 I think that maximizing reuse is needed to make sure we don't
5213 run out of reload regs. Suppose we have three reloads, and
5214 reloads A and B can share regs. These need two regs.
5215 Suppose A and B are given different regs.
5216 That leaves none for C. */
5217 for (pass = 0; pass < 2; pass++)
5219 /* I is the index in spill_regs.
5220 We advance it round-robin between insns to use all spill regs
5221 equally, so that inherited reloads have a chance
5222 of leapfrogging each other. */
5226 for (count = 0; count < n_spills; count++)
5228 int class = (int) rld[r].class;
5234 regnum = spill_regs[i];
5236 if ((reload_reg_free_p (regnum, rld[r].opnum,
5239 /* We check reload_reg_used to make sure we
5240 don't clobber the return register. */
5241 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5242 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5243 rld[r].when_needed, rld[r].in,
5245 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5246 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5247 /* Look first for regs to share, then for unshared. But
5248 don't share regs used for inherited reloads; they are
5249 the ones we want to preserve. */
5251 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5253 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5256 int nr = hard_regno_nregs[regnum][rld[r].mode];
5257 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5258 (on 68000) got us two FP regs. If NR is 1,
5259 we would reject both of them. */
5262 /* If we need only one reg, we have already won. */
5265 /* But reject a single reg if we demand a group. */
5270 /* Otherwise check that as many consecutive regs as we need
5271 are available here. */
5274 int regno = regnum + nr - 1;
5275 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5276 && spill_reg_order[regno] >= 0
5277 && reload_reg_free_p (regno, rld[r].opnum,
5278 rld[r].when_needed)))
5287 /* If we found something on pass 1, omit pass 2. */
5288 if (count < n_spills)
5292 /* We should have found a spill register by now. */
5293 if (count >= n_spills)
5296 /* I is the index in SPILL_REG_RTX of the reload register we are to
5297 allocate. Get an rtx for it and find its register number. */
5299 return set_reload_reg (i, r);
5302 /* Initialize all the tables needed to allocate reload registers.
5303 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5304 is the array we use to restore the reg_rtx field for every reload. */
5307 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5311 for (i = 0; i < n_reloads; i++)
5312 rld[i].reg_rtx = save_reload_reg_rtx[i];
5314 memset (reload_inherited, 0, MAX_RELOADS);
5315 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5316 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5318 CLEAR_HARD_REG_SET (reload_reg_used);
5319 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5320 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5321 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5322 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5323 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5325 CLEAR_HARD_REG_SET (reg_used_in_insn);
5328 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5329 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5330 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5331 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5332 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5333 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5336 for (i = 0; i < reload_n_operands; i++)
5338 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5339 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5340 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5341 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5342 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5343 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5346 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5348 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5350 for (i = 0; i < n_reloads; i++)
5351 /* If we have already decided to use a certain register,
5352 don't use it in another way. */
5354 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5355 rld[i].when_needed, rld[i].mode);
5358 /* Assign hard reg targets for the pseudo-registers we must reload
5359 into hard regs for this insn.
5360 Also output the instructions to copy them in and out of the hard regs.
5362 For machines with register classes, we are responsible for
5363 finding a reload reg in the proper class. */
5366 choose_reload_regs (struct insn_chain *chain)
5368 rtx insn = chain->insn;
5370 unsigned int max_group_size = 1;
5371 enum reg_class group_class = NO_REGS;
5372 int pass, win, inheritance;
5374 rtx save_reload_reg_rtx[MAX_RELOADS];
5376 /* In order to be certain of getting the registers we need,
5377 we must sort the reloads into order of increasing register class.
5378 Then our grabbing of reload registers will parallel the process
5379 that provided the reload registers.
5381 Also note whether any of the reloads wants a consecutive group of regs.
5382 If so, record the maximum size of the group desired and what
5383 register class contains all the groups needed by this insn. */
5385 for (j = 0; j < n_reloads; j++)
5387 reload_order[j] = j;
5388 reload_spill_index[j] = -1;
5390 if (rld[j].nregs > 1)
5392 max_group_size = MAX (rld[j].nregs, max_group_size);
5394 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5397 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5401 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5403 /* If -O, try first with inheritance, then turning it off.
5404 If not -O, don't do inheritance.
5405 Using inheritance when not optimizing leads to paradoxes
5406 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5407 because one side of the comparison might be inherited. */
5409 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5411 choose_reload_regs_init (chain, save_reload_reg_rtx);
5413 /* Process the reloads in order of preference just found.
5414 Beyond this point, subregs can be found in reload_reg_rtx.
5416 This used to look for an existing reloaded home for all of the
5417 reloads, and only then perform any new reloads. But that could lose
5418 if the reloads were done out of reg-class order because a later
5419 reload with a looser constraint might have an old home in a register
5420 needed by an earlier reload with a tighter constraint.
5422 To solve this, we make two passes over the reloads, in the order
5423 described above. In the first pass we try to inherit a reload
5424 from a previous insn. If there is a later reload that needs a
5425 class that is a proper subset of the class being processed, we must
5426 also allocate a spill register during the first pass.
5428 Then make a second pass over the reloads to allocate any reloads
5429 that haven't been given registers yet. */
5431 for (j = 0; j < n_reloads; j++)
5433 int r = reload_order[j];
5434 rtx search_equiv = NULL_RTX;
5436 /* Ignore reloads that got marked inoperative. */
5437 if (rld[r].out == 0 && rld[r].in == 0
5438 && ! rld[r].secondary_p)
5441 /* If find_reloads chose to use reload_in or reload_out as a reload
5442 register, we don't need to chose one. Otherwise, try even if it
5443 found one since we might save an insn if we find the value lying
5445 Try also when reload_in is a pseudo without a hard reg. */
5446 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5447 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5448 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5449 && !MEM_P (rld[r].in)
5450 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5453 #if 0 /* No longer needed for correct operation.
5454 It might give better code, or might not; worth an experiment? */
5455 /* If this is an optional reload, we can't inherit from earlier insns
5456 until we are sure that any non-optional reloads have been allocated.
5457 The following code takes advantage of the fact that optional reloads
5458 are at the end of reload_order. */
5459 if (rld[r].optional != 0)
5460 for (i = 0; i < j; i++)
5461 if ((rld[reload_order[i]].out != 0
5462 || rld[reload_order[i]].in != 0
5463 || rld[reload_order[i]].secondary_p)
5464 && ! rld[reload_order[i]].optional
5465 && rld[reload_order[i]].reg_rtx == 0)
5466 allocate_reload_reg (chain, reload_order[i], 0);
5469 /* First see if this pseudo is already available as reloaded
5470 for a previous insn. We cannot try to inherit for reloads
5471 that are smaller than the maximum number of registers needed
5472 for groups unless the register we would allocate cannot be used
5475 We could check here to see if this is a secondary reload for
5476 an object that is already in a register of the desired class.
5477 This would avoid the need for the secondary reload register.
5478 But this is complex because we can't easily determine what
5479 objects might want to be loaded via this reload. So let a
5480 register be allocated here. In `emit_reload_insns' we suppress
5481 one of the loads in the case described above. */
5487 enum machine_mode mode = VOIDmode;
5491 else if (REG_P (rld[r].in))
5493 regno = REGNO (rld[r].in);
5494 mode = GET_MODE (rld[r].in);
5496 else if (REG_P (rld[r].in_reg))
5498 regno = REGNO (rld[r].in_reg);
5499 mode = GET_MODE (rld[r].in_reg);
5501 else if (GET_CODE (rld[r].in_reg) == SUBREG
5502 && REG_P (SUBREG_REG (rld[r].in_reg)))
5504 byte = SUBREG_BYTE (rld[r].in_reg);
5505 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5506 if (regno < FIRST_PSEUDO_REGISTER)
5507 regno = subreg_regno (rld[r].in_reg);
5508 mode = GET_MODE (rld[r].in_reg);
5511 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5512 || GET_CODE (rld[r].in_reg) == PRE_DEC
5513 || GET_CODE (rld[r].in_reg) == POST_INC
5514 || GET_CODE (rld[r].in_reg) == POST_DEC)
5515 && REG_P (XEXP (rld[r].in_reg, 0)))
5517 regno = REGNO (XEXP (rld[r].in_reg, 0));
5518 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5519 rld[r].out = rld[r].in;
5523 /* This won't work, since REGNO can be a pseudo reg number.
5524 Also, it takes much more hair to keep track of all the things
5525 that can invalidate an inherited reload of part of a pseudoreg. */
5526 else if (GET_CODE (rld[r].in) == SUBREG
5527 && REG_P (SUBREG_REG (rld[r].in)))
5528 regno = subreg_regno (rld[r].in);
5531 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5533 enum reg_class class = rld[r].class, last_class;
5534 rtx last_reg = reg_last_reload_reg[regno];
5535 enum machine_mode need_mode;
5537 i = REGNO (last_reg);
5538 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5539 last_class = REGNO_REG_CLASS (i);
5545 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5546 + byte * BITS_PER_UNIT,
5547 GET_MODE_CLASS (mode));
5549 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5550 >= GET_MODE_SIZE (need_mode))
5551 #ifdef CANNOT_CHANGE_MODE_CLASS
5552 /* Verify that the register in "i" can be obtained
5554 && !REG_CANNOT_CHANGE_MODE_P (REGNO (last_reg),
5555 GET_MODE (last_reg),
5558 && reg_reloaded_contents[i] == regno
5559 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5560 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5561 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5562 /* Even if we can't use this register as a reload
5563 register, we might use it for reload_override_in,
5564 if copying it to the desired class is cheap
5566 || ((REGISTER_MOVE_COST (mode, last_class, class)
5567 < MEMORY_MOVE_COST (mode, class, 1))
5568 && (secondary_reload_class (1, class, mode,
5571 #ifdef SECONDARY_MEMORY_NEEDED
5572 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5577 && (rld[r].nregs == max_group_size
5578 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5580 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5581 rld[r].when_needed, rld[r].in,
5584 /* If a group is needed, verify that all the subsequent
5585 registers still have their values intact. */
5586 int nr = hard_regno_nregs[i][rld[r].mode];
5589 for (k = 1; k < nr; k++)
5590 if (reg_reloaded_contents[i + k] != regno
5591 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5599 last_reg = (GET_MODE (last_reg) == mode
5600 ? last_reg : gen_rtx_REG (mode, i));
5603 for (k = 0; k < nr; k++)
5604 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5607 /* We found a register that contains the
5608 value we need. If this register is the
5609 same as an `earlyclobber' operand of the
5610 current insn, just mark it as a place to
5611 reload from since we can't use it as the
5612 reload register itself. */
5614 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5615 if (reg_overlap_mentioned_for_reload_p
5616 (reg_last_reload_reg[regno],
5617 reload_earlyclobbers[i1]))
5620 if (i1 != n_earlyclobbers
5621 || ! (free_for_value_p (i, rld[r].mode,
5623 rld[r].when_needed, rld[r].in,
5625 /* Don't use it if we'd clobber a pseudo reg. */
5626 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5628 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5629 /* Don't clobber the frame pointer. */
5630 || (i == HARD_FRAME_POINTER_REGNUM
5631 && frame_pointer_needed
5633 /* Don't really use the inherited spill reg
5634 if we need it wider than we've got it. */
5635 || (GET_MODE_SIZE (rld[r].mode)
5636 > GET_MODE_SIZE (mode))
5639 /* If find_reloads chose reload_out as reload
5640 register, stay with it - that leaves the
5641 inherited register for subsequent reloads. */
5642 || (rld[r].out && rld[r].reg_rtx
5643 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5645 if (! rld[r].optional)
5647 reload_override_in[r] = last_reg;
5648 reload_inheritance_insn[r]
5649 = reg_reloaded_insn[i];
5655 /* We can use this as a reload reg. */
5656 /* Mark the register as in use for this part of
5658 mark_reload_reg_in_use (i,
5662 rld[r].reg_rtx = last_reg;
5663 reload_inherited[r] = 1;
5664 reload_inheritance_insn[r]
5665 = reg_reloaded_insn[i];
5666 reload_spill_index[r] = i;
5667 for (k = 0; k < nr; k++)
5668 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5676 /* Here's another way to see if the value is already lying around. */
5679 && ! reload_inherited[r]
5681 && (CONSTANT_P (rld[r].in)
5682 || GET_CODE (rld[r].in) == PLUS
5683 || REG_P (rld[r].in)
5684 || MEM_P (rld[r].in))
5685 && (rld[r].nregs == max_group_size
5686 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5687 search_equiv = rld[r].in;
5688 /* If this is an output reload from a simple move insn, look
5689 if an equivalence for the input is available. */
5690 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5692 rtx set = single_set (insn);
5695 && rtx_equal_p (rld[r].out, SET_DEST (set))
5696 && CONSTANT_P (SET_SRC (set)))
5697 search_equiv = SET_SRC (set);
5703 = find_equiv_reg (search_equiv, insn, rld[r].class,
5704 -1, NULL, 0, rld[r].mode);
5710 regno = REGNO (equiv);
5713 /* This must be a SUBREG of a hard register.
5714 Make a new REG since this might be used in an
5715 address and not all machines support SUBREGs
5717 gcc_assert (GET_CODE (equiv) == SUBREG);
5718 regno = subreg_regno (equiv);
5719 equiv = gen_rtx_REG (rld[r].mode, regno);
5720 /* If we choose EQUIV as the reload register, but the
5721 loop below decides to cancel the inheritance, we'll
5722 end up reloading EQUIV in rld[r].mode, not the mode
5723 it had originally. That isn't safe when EQUIV isn't
5724 available as a spill register since its value might
5725 still be live at this point. */
5726 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5727 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
5732 /* If we found a spill reg, reject it unless it is free
5733 and of the desired class. */
5737 int bad_for_class = 0;
5738 int max_regno = regno + rld[r].nregs;
5740 for (i = regno; i < max_regno; i++)
5742 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5744 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5749 && ! free_for_value_p (regno, rld[r].mode,
5750 rld[r].opnum, rld[r].when_needed,
5751 rld[r].in, rld[r].out, r, 1))
5756 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5759 /* We found a register that contains the value we need.
5760 If this register is the same as an `earlyclobber' operand
5761 of the current insn, just mark it as a place to reload from
5762 since we can't use it as the reload register itself. */
5765 for (i = 0; i < n_earlyclobbers; i++)
5766 if (reg_overlap_mentioned_for_reload_p (equiv,
5767 reload_earlyclobbers[i]))
5769 if (! rld[r].optional)
5770 reload_override_in[r] = equiv;
5775 /* If the equiv register we have found is explicitly clobbered
5776 in the current insn, it depends on the reload type if we
5777 can use it, use it for reload_override_in, or not at all.
5778 In particular, we then can't use EQUIV for a
5779 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5783 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
5784 switch (rld[r].when_needed)
5786 case RELOAD_FOR_OTHER_ADDRESS:
5787 case RELOAD_FOR_INPADDR_ADDRESS:
5788 case RELOAD_FOR_INPUT_ADDRESS:
5789 case RELOAD_FOR_OPADDR_ADDR:
5792 case RELOAD_FOR_INPUT:
5793 case RELOAD_FOR_OPERAND_ADDRESS:
5794 if (! rld[r].optional)
5795 reload_override_in[r] = equiv;
5801 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5802 switch (rld[r].when_needed)
5804 case RELOAD_FOR_OTHER_ADDRESS:
5805 case RELOAD_FOR_INPADDR_ADDRESS:
5806 case RELOAD_FOR_INPUT_ADDRESS:
5807 case RELOAD_FOR_OPADDR_ADDR:
5808 case RELOAD_FOR_OPERAND_ADDRESS:
5809 case RELOAD_FOR_INPUT:
5812 if (! rld[r].optional)
5813 reload_override_in[r] = equiv;
5821 /* If we found an equivalent reg, say no code need be generated
5822 to load it, and use it as our reload reg. */
5824 && (regno != HARD_FRAME_POINTER_REGNUM
5825 || !frame_pointer_needed))
5827 int nr = hard_regno_nregs[regno][rld[r].mode];
5829 rld[r].reg_rtx = equiv;
5830 reload_inherited[r] = 1;
5832 /* If reg_reloaded_valid is not set for this register,
5833 there might be a stale spill_reg_store lying around.
5834 We must clear it, since otherwise emit_reload_insns
5835 might delete the store. */
5836 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5837 spill_reg_store[regno] = NULL_RTX;
5838 /* If any of the hard registers in EQUIV are spill
5839 registers, mark them as in use for this insn. */
5840 for (k = 0; k < nr; k++)
5842 i = spill_reg_order[regno + k];
5845 mark_reload_reg_in_use (regno, rld[r].opnum,
5848 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5855 /* If we found a register to use already, or if this is an optional
5856 reload, we are done. */
5857 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5861 /* No longer needed for correct operation. Might or might
5862 not give better code on the average. Want to experiment? */
5864 /* See if there is a later reload that has a class different from our
5865 class that intersects our class or that requires less register
5866 than our reload. If so, we must allocate a register to this
5867 reload now, since that reload might inherit a previous reload
5868 and take the only available register in our class. Don't do this
5869 for optional reloads since they will force all previous reloads
5870 to be allocated. Also don't do this for reloads that have been
5873 for (i = j + 1; i < n_reloads; i++)
5875 int s = reload_order[i];
5877 if ((rld[s].in == 0 && rld[s].out == 0
5878 && ! rld[s].secondary_p)
5882 if ((rld[s].class != rld[r].class
5883 && reg_classes_intersect_p (rld[r].class,
5885 || rld[s].nregs < rld[r].nregs)
5892 allocate_reload_reg (chain, r, j == n_reloads - 1);
5896 /* Now allocate reload registers for anything non-optional that
5897 didn't get one yet. */
5898 for (j = 0; j < n_reloads; j++)
5900 int r = reload_order[j];
5902 /* Ignore reloads that got marked inoperative. */
5903 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5906 /* Skip reloads that already have a register allocated or are
5908 if (rld[r].reg_rtx != 0 || rld[r].optional)
5911 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5915 /* If that loop got all the way, we have won. */
5922 /* Loop around and try without any inheritance. */
5927 /* First undo everything done by the failed attempt
5928 to allocate with inheritance. */
5929 choose_reload_regs_init (chain, save_reload_reg_rtx);
5931 /* Some sanity tests to verify that the reloads found in the first
5932 pass are identical to the ones we have now. */
5933 gcc_assert (chain->n_reloads == n_reloads);
5935 for (i = 0; i < n_reloads; i++)
5937 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5939 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
5940 for (j = 0; j < n_spills; j++)
5941 if (spill_regs[j] == chain->rld[i].regno)
5942 if (! set_reload_reg (j, i))
5943 failed_reload (chain->insn, i);
5947 /* If we thought we could inherit a reload, because it seemed that
5948 nothing else wanted the same reload register earlier in the insn,
5949 verify that assumption, now that all reloads have been assigned.
5950 Likewise for reloads where reload_override_in has been set. */
5952 /* If doing expensive optimizations, do one preliminary pass that doesn't
5953 cancel any inheritance, but removes reloads that have been needed only
5954 for reloads that we know can be inherited. */
5955 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5957 for (j = 0; j < n_reloads; j++)
5959 int r = reload_order[j];
5961 if (reload_inherited[r] && rld[r].reg_rtx)
5962 check_reg = rld[r].reg_rtx;
5963 else if (reload_override_in[r]
5964 && (REG_P (reload_override_in[r])
5965 || GET_CODE (reload_override_in[r]) == SUBREG))
5966 check_reg = reload_override_in[r];
5969 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5970 rld[r].opnum, rld[r].when_needed, rld[r].in,
5971 (reload_inherited[r]
5972 ? rld[r].out : const0_rtx),
5977 reload_inherited[r] = 0;
5978 reload_override_in[r] = 0;
5980 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5981 reload_override_in, then we do not need its related
5982 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5983 likewise for other reload types.
5984 We handle this by removing a reload when its only replacement
5985 is mentioned in reload_in of the reload we are going to inherit.
5986 A special case are auto_inc expressions; even if the input is
5987 inherited, we still need the address for the output. We can
5988 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5989 If we succeeded removing some reload and we are doing a preliminary
5990 pass just to remove such reloads, make another pass, since the
5991 removal of one reload might allow us to inherit another one. */
5993 && rld[r].out != rld[r].in
5994 && remove_address_replacements (rld[r].in) && pass)
5999 /* Now that reload_override_in is known valid,
6000 actually override reload_in. */
6001 for (j = 0; j < n_reloads; j++)
6002 if (reload_override_in[j])
6003 rld[j].in = reload_override_in[j];
6005 /* If this reload won't be done because it has been canceled or is
6006 optional and not inherited, clear reload_reg_rtx so other
6007 routines (such as subst_reloads) don't get confused. */
6008 for (j = 0; j < n_reloads; j++)
6009 if (rld[j].reg_rtx != 0
6010 && ((rld[j].optional && ! reload_inherited[j])
6011 || (rld[j].in == 0 && rld[j].out == 0
6012 && ! rld[j].secondary_p)))
6014 int regno = true_regnum (rld[j].reg_rtx);
6016 if (spill_reg_order[regno] >= 0)
6017 clear_reload_reg_in_use (regno, rld[j].opnum,
6018 rld[j].when_needed, rld[j].mode);
6020 reload_spill_index[j] = -1;
6023 /* Record which pseudos and which spill regs have output reloads. */
6024 for (j = 0; j < n_reloads; j++)
6026 int r = reload_order[j];
6028 i = reload_spill_index[r];
6030 /* I is nonneg if this reload uses a register.
6031 If rld[r].reg_rtx is 0, this is an optional reload
6032 that we opted to ignore. */
6033 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6034 && rld[r].reg_rtx != 0)
6036 int nregno = REGNO (rld[r].out_reg);
6039 if (nregno < FIRST_PSEUDO_REGISTER)
6040 nr = hard_regno_nregs[nregno][rld[r].mode];
6043 reg_has_output_reload[nregno + nr] = 1;
6047 nr = hard_regno_nregs[i][rld[r].mode];
6049 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6052 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6053 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6054 || rld[r].when_needed == RELOAD_FOR_INSN);
6059 /* Deallocate the reload register for reload R. This is called from
6060 remove_address_replacements. */
6063 deallocate_reload_reg (int r)
6067 if (! rld[r].reg_rtx)
6069 regno = true_regnum (rld[r].reg_rtx);
6071 if (spill_reg_order[regno] >= 0)
6072 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6074 reload_spill_index[r] = -1;
6077 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6078 reloads of the same item for fear that we might not have enough reload
6079 registers. However, normally they will get the same reload register
6080 and hence actually need not be loaded twice.
6082 Here we check for the most common case of this phenomenon: when we have
6083 a number of reloads for the same object, each of which were allocated
6084 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6085 reload, and is not modified in the insn itself. If we find such,
6086 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6087 This will not increase the number of spill registers needed and will
6088 prevent redundant code. */
6091 merge_assigned_reloads (rtx insn)
6095 /* Scan all the reloads looking for ones that only load values and
6096 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6097 assigned and not modified by INSN. */
6099 for (i = 0; i < n_reloads; i++)
6101 int conflicting_input = 0;
6102 int max_input_address_opnum = -1;
6103 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6105 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6106 || rld[i].out != 0 || rld[i].reg_rtx == 0
6107 || reg_set_p (rld[i].reg_rtx, insn))
6110 /* Look at all other reloads. Ensure that the only use of this
6111 reload_reg_rtx is in a reload that just loads the same value
6112 as we do. Note that any secondary reloads must be of the identical
6113 class since the values, modes, and result registers are the
6114 same, so we need not do anything with any secondary reloads. */
6116 for (j = 0; j < n_reloads; j++)
6118 if (i == j || rld[j].reg_rtx == 0
6119 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6123 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6124 && rld[j].opnum > max_input_address_opnum)
6125 max_input_address_opnum = rld[j].opnum;
6127 /* If the reload regs aren't exactly the same (e.g, different modes)
6128 or if the values are different, we can't merge this reload.
6129 But if it is an input reload, we might still merge
6130 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6132 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6133 || rld[j].out != 0 || rld[j].in == 0
6134 || ! rtx_equal_p (rld[i].in, rld[j].in))
6136 if (rld[j].when_needed != RELOAD_FOR_INPUT
6137 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6138 || rld[i].opnum > rld[j].opnum)
6139 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6141 conflicting_input = 1;
6142 if (min_conflicting_input_opnum > rld[j].opnum)
6143 min_conflicting_input_opnum = rld[j].opnum;
6147 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6148 we, in fact, found any matching reloads. */
6151 && max_input_address_opnum <= min_conflicting_input_opnum)
6153 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6155 for (j = 0; j < n_reloads; j++)
6156 if (i != j && rld[j].reg_rtx != 0
6157 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6158 && (! conflicting_input
6159 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6160 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6162 rld[i].when_needed = RELOAD_OTHER;
6164 reload_spill_index[j] = -1;
6165 transfer_replacements (i, j);
6168 /* If this is now RELOAD_OTHER, look for any reloads that load
6169 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6170 if they were for inputs, RELOAD_OTHER for outputs. Note that
6171 this test is equivalent to looking for reloads for this operand
6173 /* We must take special care with RELOAD_FOR_OUTPUT_ADDRESS; it may
6174 share registers with a RELOAD_FOR_INPUT, so we can not change it
6175 to RELOAD_FOR_OTHER_ADDRESS. We should never need to, since we
6176 do not modify RELOAD_FOR_OUTPUT. */
6178 if (rld[i].when_needed == RELOAD_OTHER)
6179 for (j = 0; j < n_reloads; j++)
6181 && rld[j].when_needed != RELOAD_OTHER
6182 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6183 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6184 && (! conflicting_input
6185 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6186 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6187 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6193 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6194 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6195 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6197 /* Check to see if we accidentally converted two
6198 reloads that use the same reload register with
6199 different inputs to the same type. If so, the
6200 resulting code won't work. */
6202 for (k = 0; k < j; k++)
6203 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6204 || rld[k].when_needed != rld[j].when_needed
6205 || !rtx_equal_p (rld[k].reg_rtx,
6207 || rtx_equal_p (rld[k].in,
6214 /* These arrays are filled by emit_reload_insns and its subroutines. */
6215 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6216 static rtx other_input_address_reload_insns = 0;
6217 static rtx other_input_reload_insns = 0;
6218 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6219 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6220 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6221 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6222 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6223 static rtx operand_reload_insns = 0;
6224 static rtx other_operand_reload_insns = 0;
6225 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6227 /* Values to be put in spill_reg_store are put here first. */
6228 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6229 static HARD_REG_SET reg_reloaded_died;
6231 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6232 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6233 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6234 adjusted register, and return true. Otherwise, return false. */
6236 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6237 enum reg_class new_class,
6238 enum machine_mode new_mode)
6243 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6245 unsigned regno = REGNO (reg);
6247 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6249 if (GET_MODE (reg) != new_mode)
6251 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6253 if (hard_regno_nregs[regno][new_mode]
6254 > hard_regno_nregs[regno][GET_MODE (reg)])
6256 reg = reload_adjust_reg_for_mode (reg, new_mode);
6264 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6265 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6266 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6267 adjusted register, and return true. Otherwise, return false. */
6269 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6270 enum insn_code icode)
6273 enum reg_class new_class = scratch_reload_class (icode);
6274 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6276 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6277 new_class, new_mode);
6280 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6281 has the number J. OLD contains the value to be used as input. */
6284 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6287 rtx insn = chain->insn;
6288 rtx reloadreg = rl->reg_rtx;
6289 rtx oldequiv_reg = 0;
6292 enum machine_mode mode;
6295 /* Determine the mode to reload in.
6296 This is very tricky because we have three to choose from.
6297 There is the mode the insn operand wants (rl->inmode).
6298 There is the mode of the reload register RELOADREG.
6299 There is the intrinsic mode of the operand, which we could find
6300 by stripping some SUBREGs.
6301 It turns out that RELOADREG's mode is irrelevant:
6302 we can change that arbitrarily.
6304 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6305 then the reload reg may not support QImode moves, so use SImode.
6306 If foo is in memory due to spilling a pseudo reg, this is safe,
6307 because the QImode value is in the least significant part of a
6308 slot big enough for a SImode. If foo is some other sort of
6309 memory reference, then it is impossible to reload this case,
6310 so previous passes had better make sure this never happens.
6312 Then consider a one-word union which has SImode and one of its
6313 members is a float, being fetched as (SUBREG:SF union:SI).
6314 We must fetch that as SFmode because we could be loading into
6315 a float-only register. In this case OLD's mode is correct.
6317 Consider an immediate integer: it has VOIDmode. Here we need
6318 to get a mode from something else.
6320 In some cases, there is a fourth mode, the operand's
6321 containing mode. If the insn specifies a containing mode for
6322 this operand, it overrides all others.
6324 I am not sure whether the algorithm here is always right,
6325 but it does the right things in those cases. */
6327 mode = GET_MODE (old);
6328 if (mode == VOIDmode)
6331 /* delete_output_reload is only invoked properly if old contains
6332 the original pseudo register. Since this is replaced with a
6333 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6334 find the pseudo in RELOAD_IN_REG. */
6335 if (reload_override_in[j]
6336 && REG_P (rl->in_reg))
6343 else if (REG_P (oldequiv))
6344 oldequiv_reg = oldequiv;
6345 else if (GET_CODE (oldequiv) == SUBREG)
6346 oldequiv_reg = SUBREG_REG (oldequiv);
6348 /* If we are reloading from a register that was recently stored in
6349 with an output-reload, see if we can prove there was
6350 actually no need to store the old value in it. */
6352 if (optimize && REG_P (oldequiv)
6353 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6354 && spill_reg_store[REGNO (oldequiv)]
6356 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6357 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6359 delete_output_reload (insn, j, REGNO (oldequiv));
6361 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6362 then load RELOADREG from OLDEQUIV. Note that we cannot use
6363 gen_lowpart_common since it can do the wrong thing when
6364 RELOADREG has a multi-word mode. Note that RELOADREG
6365 must always be a REG here. */
6367 if (GET_MODE (reloadreg) != mode)
6368 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6369 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6370 oldequiv = SUBREG_REG (oldequiv);
6371 if (GET_MODE (oldequiv) != VOIDmode
6372 && mode != GET_MODE (oldequiv))
6373 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6375 /* Switch to the right place to emit the reload insns. */
6376 switch (rl->when_needed)
6379 where = &other_input_reload_insns;
6381 case RELOAD_FOR_INPUT:
6382 where = &input_reload_insns[rl->opnum];
6384 case RELOAD_FOR_INPUT_ADDRESS:
6385 where = &input_address_reload_insns[rl->opnum];
6387 case RELOAD_FOR_INPADDR_ADDRESS:
6388 where = &inpaddr_address_reload_insns[rl->opnum];
6390 case RELOAD_FOR_OUTPUT_ADDRESS:
6391 where = &output_address_reload_insns[rl->opnum];
6393 case RELOAD_FOR_OUTADDR_ADDRESS:
6394 where = &outaddr_address_reload_insns[rl->opnum];
6396 case RELOAD_FOR_OPERAND_ADDRESS:
6397 where = &operand_reload_insns;
6399 case RELOAD_FOR_OPADDR_ADDR:
6400 where = &other_operand_reload_insns;
6402 case RELOAD_FOR_OTHER_ADDRESS:
6403 where = &other_input_address_reload_insns;
6409 push_to_sequence (*where);
6411 /* Auto-increment addresses must be reloaded in a special way. */
6412 if (rl->out && ! rl->out_reg)
6414 /* We are not going to bother supporting the case where a
6415 incremented register can't be copied directly from
6416 OLDEQUIV since this seems highly unlikely. */
6417 gcc_assert (rl->secondary_in_reload < 0);
6419 if (reload_inherited[j])
6420 oldequiv = reloadreg;
6422 old = XEXP (rl->in_reg, 0);
6424 if (optimize && REG_P (oldequiv)
6425 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6426 && spill_reg_store[REGNO (oldequiv)]
6428 && (dead_or_set_p (insn,
6429 spill_reg_stored_to[REGNO (oldequiv)])
6430 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6432 delete_output_reload (insn, j, REGNO (oldequiv));
6434 /* Prevent normal processing of this reload. */
6436 /* Output a special code sequence for this case. */
6437 new_spill_reg_store[REGNO (reloadreg)]
6438 = inc_for_reload (reloadreg, oldequiv, rl->out,
6442 /* If we are reloading a pseudo-register that was set by the previous
6443 insn, see if we can get rid of that pseudo-register entirely
6444 by redirecting the previous insn into our reload register. */
6446 else if (optimize && REG_P (old)
6447 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6448 && dead_or_set_p (insn, old)
6449 /* This is unsafe if some other reload
6450 uses the same reg first. */
6451 && ! conflicts_with_override (reloadreg)
6452 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6453 rl->when_needed, old, rl->out, j, 0))
6455 rtx temp = PREV_INSN (insn);
6456 while (temp && NOTE_P (temp))
6457 temp = PREV_INSN (temp);
6459 && NONJUMP_INSN_P (temp)
6460 && GET_CODE (PATTERN (temp)) == SET
6461 && SET_DEST (PATTERN (temp)) == old
6462 /* Make sure we can access insn_operand_constraint. */
6463 && asm_noperands (PATTERN (temp)) < 0
6464 /* This is unsafe if operand occurs more than once in current
6465 insn. Perhaps some occurrences aren't reloaded. */
6466 && count_occurrences (PATTERN (insn), old, 0) == 1)
6468 rtx old = SET_DEST (PATTERN (temp));
6469 /* Store into the reload register instead of the pseudo. */
6470 SET_DEST (PATTERN (temp)) = reloadreg;
6472 /* Verify that resulting insn is valid. */
6473 extract_insn (temp);
6474 if (constrain_operands (1))
6476 /* If the previous insn is an output reload, the source is
6477 a reload register, and its spill_reg_store entry will
6478 contain the previous destination. This is now
6480 if (REG_P (SET_SRC (PATTERN (temp)))
6481 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6483 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6484 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6487 /* If these are the only uses of the pseudo reg,
6488 pretend for GDB it lives in the reload reg we used. */
6489 if (REG_N_DEATHS (REGNO (old)) == 1
6490 && REG_N_SETS (REGNO (old)) == 1)
6492 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6493 alter_reg (REGNO (old), -1);
6499 SET_DEST (PATTERN (temp)) = old;
6504 /* We can't do that, so output an insn to load RELOADREG. */
6506 /* If we have a secondary reload, pick up the secondary register
6507 and icode, if any. If OLDEQUIV and OLD are different or
6508 if this is an in-out reload, recompute whether or not we
6509 still need a secondary register and what the icode should
6510 be. If we still need a secondary register and the class or
6511 icode is different, go back to reloading from OLD if using
6512 OLDEQUIV means that we got the wrong type of register. We
6513 cannot have different class or icode due to an in-out reload
6514 because we don't make such reloads when both the input and
6515 output need secondary reload registers. */
6517 if (! special && rl->secondary_in_reload >= 0)
6519 rtx second_reload_reg = 0;
6520 rtx third_reload_reg = 0;
6521 int secondary_reload = rl->secondary_in_reload;
6522 rtx real_oldequiv = oldequiv;
6525 enum insn_code icode;
6526 enum insn_code tertiary_icode = CODE_FOR_nothing;
6528 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6529 and similarly for OLD.
6530 See comments in get_secondary_reload in reload.c. */
6531 /* If it is a pseudo that cannot be replaced with its
6532 equivalent MEM, we must fall back to reload_in, which
6533 will have all the necessary substitutions registered.
6534 Likewise for a pseudo that can't be replaced with its
6535 equivalent constant.
6537 Take extra care for subregs of such pseudos. Note that
6538 we cannot use reg_equiv_mem in this case because it is
6539 not in the right mode. */
6542 if (GET_CODE (tmp) == SUBREG)
6543 tmp = SUBREG_REG (tmp);
6545 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6546 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6547 || reg_equiv_constant[REGNO (tmp)] != 0))
6549 if (! reg_equiv_mem[REGNO (tmp)]
6550 || num_not_at_initial_offset
6551 || GET_CODE (oldequiv) == SUBREG)
6552 real_oldequiv = rl->in;
6554 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6558 if (GET_CODE (tmp) == SUBREG)
6559 tmp = SUBREG_REG (tmp);
6561 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6562 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6563 || reg_equiv_constant[REGNO (tmp)] != 0))
6565 if (! reg_equiv_mem[REGNO (tmp)]
6566 || num_not_at_initial_offset
6567 || GET_CODE (old) == SUBREG)
6570 real_old = reg_equiv_mem[REGNO (tmp)];
6573 second_reload_reg = rld[secondary_reload].reg_rtx;
6574 if (rld[secondary_reload].secondary_in_reload >= 0)
6576 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
6578 third_reload_reg = rld[tertiary_reload].reg_rtx;
6579 tertiary_icode = rld[secondary_reload].secondary_in_icode;
6580 /* We'd have to add more code for quartary reloads. */
6581 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
6583 icode = rl->secondary_in_icode;
6585 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6586 || (rl->in != 0 && rl->out != 0))
6588 secondary_reload_info sri, sri2;
6589 enum reg_class new_class, new_t_class;
6591 sri.icode = CODE_FOR_nothing;
6592 sri.prev_sri = NULL;
6593 new_class = targetm.secondary_reload (1, real_oldequiv, rl->class,
6596 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
6597 second_reload_reg = 0;
6598 else if (new_class == NO_REGS)
6600 if (reload_adjust_reg_for_icode (&second_reload_reg,
6601 third_reload_reg, sri.icode))
6602 icode = sri.icode, third_reload_reg = 0;
6604 oldequiv = old, real_oldequiv = real_old;
6606 else if (sri.icode != CODE_FOR_nothing)
6607 /* We currently lack a way to express this in reloads. */
6611 sri2.icode = CODE_FOR_nothing;
6612 sri2.prev_sri = &sri;
6613 new_t_class = targetm.secondary_reload (1, real_oldequiv,
6614 new_class, mode, &sri);
6615 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
6617 if (reload_adjust_reg_for_temp (&second_reload_reg,
6620 third_reload_reg = 0, tertiary_icode = sri2.icode;
6622 oldequiv = old, real_oldequiv = real_old;
6624 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
6626 rtx intermediate = second_reload_reg;
6628 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6630 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
6633 second_reload_reg = intermediate;
6634 tertiary_icode = sri2.icode;
6637 oldequiv = old, real_oldequiv = real_old;
6639 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
6641 rtx intermediate = second_reload_reg;
6643 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6645 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
6648 second_reload_reg = intermediate;
6649 tertiary_icode = sri2.icode;
6652 oldequiv = old, real_oldequiv = real_old;
6655 /* This could be handled more intelligently too. */
6656 oldequiv = old, real_oldequiv = real_old;
6660 /* If we still need a secondary reload register, check
6661 to see if it is being used as a scratch or intermediate
6662 register and generate code appropriately. If we need
6663 a scratch register, use REAL_OLDEQUIV since the form of
6664 the insn may depend on the actual address if it is
6667 if (second_reload_reg)
6669 if (icode != CODE_FOR_nothing)
6671 /* We'd have to add extra code to handle this case. */
6672 gcc_assert (!third_reload_reg);
6674 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6675 second_reload_reg));
6680 /* See if we need a scratch register to load the
6681 intermediate register (a tertiary reload). */
6682 if (tertiary_icode != CODE_FOR_nothing)
6684 emit_insn ((GEN_FCN (tertiary_icode)
6685 (second_reload_reg, real_oldequiv,
6686 third_reload_reg)));
6688 else if (third_reload_reg)
6690 gen_reload (third_reload_reg, real_oldequiv,
6693 gen_reload (second_reload_reg, third_reload_reg,
6698 gen_reload (second_reload_reg, real_oldequiv,
6702 oldequiv = second_reload_reg;
6707 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6709 rtx real_oldequiv = oldequiv;
6711 if ((REG_P (oldequiv)
6712 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6713 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6714 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6715 || (GET_CODE (oldequiv) == SUBREG
6716 && REG_P (SUBREG_REG (oldequiv))
6717 && (REGNO (SUBREG_REG (oldequiv))
6718 >= FIRST_PSEUDO_REGISTER)
6719 && ((reg_equiv_memory_loc
6720 [REGNO (SUBREG_REG (oldequiv))] != 0)
6721 || (reg_equiv_constant
6722 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6723 || (CONSTANT_P (oldequiv)
6724 && (PREFERRED_RELOAD_CLASS (oldequiv,
6725 REGNO_REG_CLASS (REGNO (reloadreg)))
6727 real_oldequiv = rl->in;
6728 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6732 if (flag_non_call_exceptions)
6733 copy_eh_notes (insn, get_insns ());
6735 /* End this sequence. */
6736 *where = get_insns ();
6739 /* Update reload_override_in so that delete_address_reloads_1
6740 can see the actual register usage. */
6742 reload_override_in[j] = oldequiv;
6745 /* Generate insns to for the output reload RL, which is for the insn described
6746 by CHAIN and has the number J. */
6748 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6751 rtx reloadreg = rl->reg_rtx;
6752 rtx insn = chain->insn;
6755 enum machine_mode mode = GET_MODE (old);
6758 if (rl->when_needed == RELOAD_OTHER)
6761 push_to_sequence (output_reload_insns[rl->opnum]);
6763 /* Determine the mode to reload in.
6764 See comments above (for input reloading). */
6766 if (mode == VOIDmode)
6768 /* VOIDmode should never happen for an output. */
6769 if (asm_noperands (PATTERN (insn)) < 0)
6770 /* It's the compiler's fault. */
6771 fatal_insn ("VOIDmode on an output", insn);
6772 error_for_asm (insn, "output operand is constant in %<asm%>");
6773 /* Prevent crash--use something we know is valid. */
6775 old = gen_rtx_REG (mode, REGNO (reloadreg));
6778 if (GET_MODE (reloadreg) != mode)
6779 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6781 /* If we need two reload regs, set RELOADREG to the intermediate
6782 one, since it will be stored into OLD. We might need a secondary
6783 register only for an input reload, so check again here. */
6785 if (rl->secondary_out_reload >= 0)
6788 int secondary_reload = rl->secondary_out_reload;
6789 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
6791 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
6792 && reg_equiv_mem[REGNO (old)] != 0)
6793 real_old = reg_equiv_mem[REGNO (old)];
6795 if (secondary_reload_class (0, rl->class, mode, real_old) != NO_REGS)
6797 rtx second_reloadreg = reloadreg;
6798 reloadreg = rld[secondary_reload].reg_rtx;
6800 /* See if RELOADREG is to be used as a scratch register
6801 or as an intermediate register. */
6802 if (rl->secondary_out_icode != CODE_FOR_nothing)
6804 /* We'd have to add extra code to handle this case. */
6805 gcc_assert (tertiary_reload < 0);
6807 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6808 (real_old, second_reloadreg, reloadreg)));
6813 /* See if we need both a scratch and intermediate reload
6816 enum insn_code tertiary_icode
6817 = rld[secondary_reload].secondary_out_icode;
6819 /* We'd have to add more code for quartary reloads. */
6820 gcc_assert (tertiary_reload < 0
6821 || rld[tertiary_reload].secondary_out_reload < 0);
6823 if (GET_MODE (reloadreg) != mode)
6824 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6826 if (tertiary_icode != CODE_FOR_nothing)
6828 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
6831 /* Copy primary reload reg to secondary reload reg.
6832 (Note that these have been swapped above, then
6833 secondary reload reg to OLD using our insn.) */
6835 /* If REAL_OLD is a paradoxical SUBREG, remove it
6836 and try to put the opposite SUBREG on
6838 if (GET_CODE (real_old) == SUBREG
6839 && (GET_MODE_SIZE (GET_MODE (real_old))
6840 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6841 && 0 != (tem = gen_lowpart_common
6842 (GET_MODE (SUBREG_REG (real_old)),
6844 real_old = SUBREG_REG (real_old), reloadreg = tem;
6846 gen_reload (reloadreg, second_reloadreg,
6847 rl->opnum, rl->when_needed);
6848 emit_insn ((GEN_FCN (tertiary_icode)
6849 (real_old, reloadreg, third_reloadreg)));
6855 /* Copy between the reload regs here and then to
6858 gen_reload (reloadreg, second_reloadreg,
6859 rl->opnum, rl->when_needed);
6860 if (tertiary_reload >= 0)
6862 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
6864 gen_reload (third_reloadreg, reloadreg,
6865 rl->opnum, rl->when_needed);
6866 reloadreg = third_reloadreg;
6873 /* Output the last reload insn. */
6878 /* Don't output the last reload if OLD is not the dest of
6879 INSN and is in the src and is clobbered by INSN. */
6880 if (! flag_expensive_optimizations
6882 || !(set = single_set (insn))
6883 || rtx_equal_p (old, SET_DEST (set))
6884 || !reg_mentioned_p (old, SET_SRC (set))
6885 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
6886 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
6887 gen_reload (old, reloadreg, rl->opnum,
6891 /* Look at all insns we emitted, just to be safe. */
6892 for (p = get_insns (); p; p = NEXT_INSN (p))
6895 rtx pat = PATTERN (p);
6897 /* If this output reload doesn't come from a spill reg,
6898 clear any memory of reloaded copies of the pseudo reg.
6899 If this output reload comes from a spill reg,
6900 reg_has_output_reload will make this do nothing. */
6901 note_stores (pat, forget_old_reloads_1, NULL);
6903 if (reg_mentioned_p (rl->reg_rtx, pat))
6905 rtx set = single_set (insn);
6906 if (reload_spill_index[j] < 0
6908 && SET_SRC (set) == rl->reg_rtx)
6910 int src = REGNO (SET_SRC (set));
6912 reload_spill_index[j] = src;
6913 SET_HARD_REG_BIT (reg_is_output_reload, src);
6914 if (find_regno_note (insn, REG_DEAD, src))
6915 SET_HARD_REG_BIT (reg_reloaded_died, src);
6917 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6919 int s = rl->secondary_out_reload;
6920 set = single_set (p);
6921 /* If this reload copies only to the secondary reload
6922 register, the secondary reload does the actual
6924 if (s >= 0 && set == NULL_RTX)
6925 /* We can't tell what function the secondary reload
6926 has and where the actual store to the pseudo is
6927 made; leave new_spill_reg_store alone. */
6930 && SET_SRC (set) == rl->reg_rtx
6931 && SET_DEST (set) == rld[s].reg_rtx)
6933 /* Usually the next instruction will be the
6934 secondary reload insn; if we can confirm
6935 that it is, setting new_spill_reg_store to
6936 that insn will allow an extra optimization. */
6937 rtx s_reg = rld[s].reg_rtx;
6938 rtx next = NEXT_INSN (p);
6939 rld[s].out = rl->out;
6940 rld[s].out_reg = rl->out_reg;
6941 set = single_set (next);
6942 if (set && SET_SRC (set) == s_reg
6943 && ! new_spill_reg_store[REGNO (s_reg)])
6945 SET_HARD_REG_BIT (reg_is_output_reload,
6947 new_spill_reg_store[REGNO (s_reg)] = next;
6951 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6956 if (rl->when_needed == RELOAD_OTHER)
6958 emit_insn (other_output_reload_insns[rl->opnum]);
6959 other_output_reload_insns[rl->opnum] = get_insns ();
6962 output_reload_insns[rl->opnum] = get_insns ();
6964 if (flag_non_call_exceptions)
6965 copy_eh_notes (insn, get_insns ());
6970 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6971 and has the number J. */
6973 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
6975 rtx insn = chain->insn;
6976 rtx old = (rl->in && MEM_P (rl->in)
6977 ? rl->in_reg : rl->in);
6980 /* AUTO_INC reloads need to be handled even if inherited. We got an
6981 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6982 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6983 && ! rtx_equal_p (rl->reg_rtx, old)
6984 && rl->reg_rtx != 0)
6985 emit_input_reload_insns (chain, rld + j, old, j);
6987 /* When inheriting a wider reload, we have a MEM in rl->in,
6988 e.g. inheriting a SImode output reload for
6989 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6990 if (optimize && reload_inherited[j] && rl->in
6992 && MEM_P (rl->in_reg)
6993 && reload_spill_index[j] >= 0
6994 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6995 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6997 /* If we are reloading a register that was recently stored in with an
6998 output-reload, see if we can prove there was
6999 actually no need to store the old value in it. */
7002 /* Only attempt this for input reloads; for RELOAD_OTHER we miss
7003 that there may be multiple uses of the previous output reload.
7004 Restricting to RELOAD_FOR_INPUT is mostly paranoia. */
7005 && rl->when_needed == RELOAD_FOR_INPUT
7006 && (reload_inherited[j] || reload_override_in[j])
7008 && REG_P (rl->reg_rtx)
7009 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
7011 /* There doesn't seem to be any reason to restrict this to pseudos
7012 and doing so loses in the case where we are copying from a
7013 register of the wrong class. */
7014 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
7015 >= FIRST_PSEUDO_REGISTER)
7017 /* The insn might have already some references to stackslots
7018 replaced by MEMs, while reload_out_reg still names the
7020 && (dead_or_set_p (insn,
7021 spill_reg_stored_to[REGNO (rl->reg_rtx)])
7022 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
7024 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
7027 /* Do output reloading for reload RL, which is for the insn described by
7028 CHAIN and has the number J.
7029 ??? At some point we need to support handling output reloads of
7030 JUMP_INSNs or insns that set cc0. */
7032 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7035 rtx insn = chain->insn;
7036 /* If this is an output reload that stores something that is
7037 not loaded in this same reload, see if we can eliminate a previous
7039 rtx pseudo = rl->out_reg;
7044 && ! rtx_equal_p (rl->in_reg, pseudo)
7045 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7046 && reg_last_reload_reg[REGNO (pseudo)])
7048 int pseudo_no = REGNO (pseudo);
7049 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7051 /* We don't need to test full validity of last_regno for
7052 inherit here; we only want to know if the store actually
7053 matches the pseudo. */
7054 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7055 && reg_reloaded_contents[last_regno] == pseudo_no
7056 && spill_reg_store[last_regno]
7057 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7058 delete_output_reload (insn, j, last_regno);
7063 || rl->reg_rtx == old
7064 || rl->reg_rtx == 0)
7067 /* An output operand that dies right away does need a reload,
7068 but need not be copied from it. Show the new location in the
7070 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7071 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7073 XEXP (note, 0) = rl->reg_rtx;
7076 /* Likewise for a SUBREG of an operand that dies. */
7077 else if (GET_CODE (old) == SUBREG
7078 && REG_P (SUBREG_REG (old))
7079 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7082 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7086 else if (GET_CODE (old) == SCRATCH)
7087 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7088 but we don't want to make an output reload. */
7091 /* If is a JUMP_INSN, we can't support output reloads yet. */
7092 gcc_assert (NONJUMP_INSN_P (insn));
7094 emit_output_reload_insns (chain, rld + j, j);
7097 /* Reload number R reloads from or to a group of hard registers starting at
7098 register REGNO. Return true if it can be treated for inheritance purposes
7099 like a group of reloads, each one reloading a single hard register.
7100 The caller has already checked that the spill register and REGNO use
7101 the same number of registers to store the reload value. */
7104 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
7106 #ifdef CANNOT_CHANGE_MODE_CLASS
7107 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
7108 GET_MODE (rld[r].reg_rtx),
7109 reg_raw_mode[reload_spill_index[r]])
7110 && !REG_CANNOT_CHANGE_MODE_P (regno,
7111 GET_MODE (rld[r].reg_rtx),
7112 reg_raw_mode[regno]));
7118 /* Output insns to reload values in and out of the chosen reload regs. */
7121 emit_reload_insns (struct insn_chain *chain)
7123 rtx insn = chain->insn;
7127 CLEAR_HARD_REG_SET (reg_reloaded_died);
7129 for (j = 0; j < reload_n_operands; j++)
7130 input_reload_insns[j] = input_address_reload_insns[j]
7131 = inpaddr_address_reload_insns[j]
7132 = output_reload_insns[j] = output_address_reload_insns[j]
7133 = outaddr_address_reload_insns[j]
7134 = other_output_reload_insns[j] = 0;
7135 other_input_address_reload_insns = 0;
7136 other_input_reload_insns = 0;
7137 operand_reload_insns = 0;
7138 other_operand_reload_insns = 0;
7140 /* Dump reloads into the dump file. */
7143 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7144 debug_reload_to_stream (dump_file);
7147 /* Now output the instructions to copy the data into and out of the
7148 reload registers. Do these in the order that the reloads were reported,
7149 since reloads of base and index registers precede reloads of operands
7150 and the operands may need the base and index registers reloaded. */
7152 for (j = 0; j < n_reloads; j++)
7155 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7156 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7158 do_input_reload (chain, rld + j, j);
7159 do_output_reload (chain, rld + j, j);
7162 /* Now write all the insns we made for reloads in the order expected by
7163 the allocation functions. Prior to the insn being reloaded, we write
7164 the following reloads:
7166 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7168 RELOAD_OTHER reloads.
7170 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7171 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7172 RELOAD_FOR_INPUT reload for the operand.
7174 RELOAD_FOR_OPADDR_ADDRS reloads.
7176 RELOAD_FOR_OPERAND_ADDRESS reloads.
7178 After the insn being reloaded, we write the following:
7180 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7181 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7182 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7183 reloads for the operand. The RELOAD_OTHER output reloads are
7184 output in descending order by reload number. */
7186 emit_insn_before (other_input_address_reload_insns, insn);
7187 emit_insn_before (other_input_reload_insns, insn);
7189 for (j = 0; j < reload_n_operands; j++)
7191 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7192 emit_insn_before (input_address_reload_insns[j], insn);
7193 emit_insn_before (input_reload_insns[j], insn);
7196 emit_insn_before (other_operand_reload_insns, insn);
7197 emit_insn_before (operand_reload_insns, insn);
7199 for (j = 0; j < reload_n_operands; j++)
7201 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7202 x = emit_insn_after (output_address_reload_insns[j], x);
7203 x = emit_insn_after (output_reload_insns[j], x);
7204 emit_insn_after (other_output_reload_insns[j], x);
7207 /* For all the spill regs newly reloaded in this instruction,
7208 record what they were reloaded from, so subsequent instructions
7209 can inherit the reloads.
7211 Update spill_reg_store for the reloads of this insn.
7212 Copy the elements that were updated in the loop above. */
7214 for (j = 0; j < n_reloads; j++)
7216 int r = reload_order[j];
7217 int i = reload_spill_index[r];
7219 /* If this is a non-inherited input reload from a pseudo, we must
7220 clear any memory of a previous store to the same pseudo. Only do
7221 something if there will not be an output reload for the pseudo
7223 if (rld[r].in_reg != 0
7224 && ! (reload_inherited[r] || reload_override_in[r]))
7226 rtx reg = rld[r].in_reg;
7228 if (GET_CODE (reg) == SUBREG)
7229 reg = SUBREG_REG (reg);
7232 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7233 && ! reg_has_output_reload[REGNO (reg)])
7235 int nregno = REGNO (reg);
7237 if (reg_last_reload_reg[nregno])
7239 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7241 if (reg_reloaded_contents[last_regno] == nregno)
7242 spill_reg_store[last_regno] = 0;
7247 /* I is nonneg if this reload used a register.
7248 If rld[r].reg_rtx is 0, this is an optional reload
7249 that we opted to ignore. */
7251 if (i >= 0 && rld[r].reg_rtx != 0)
7253 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7255 int part_reaches_end = 0;
7256 int all_reaches_end = 1;
7258 /* For a multi register reload, we need to check if all or part
7259 of the value lives to the end. */
7260 for (k = 0; k < nr; k++)
7262 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7263 rld[r].when_needed))
7264 part_reaches_end = 1;
7266 all_reaches_end = 0;
7269 /* Ignore reloads that don't reach the end of the insn in
7271 if (all_reaches_end)
7273 /* First, clear out memory of what used to be in this spill reg.
7274 If consecutive registers are used, clear them all. */
7276 for (k = 0; k < nr; k++)
7278 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7279 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7282 /* Maybe the spill reg contains a copy of reload_out. */
7284 && (REG_P (rld[r].out)
7288 || REG_P (rld[r].out_reg)))
7290 rtx out = (REG_P (rld[r].out)
7294 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7295 int nregno = REGNO (out);
7296 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7297 : hard_regno_nregs[nregno]
7298 [GET_MODE (rld[r].reg_rtx)]);
7301 spill_reg_store[i] = new_spill_reg_store[i];
7302 spill_reg_stored_to[i] = out;
7303 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7305 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7307 && inherit_piecemeal_p (r, nregno));
7309 /* If NREGNO is a hard register, it may occupy more than
7310 one register. If it does, say what is in the
7311 rest of the registers assuming that both registers
7312 agree on how many words the object takes. If not,
7313 invalidate the subsequent registers. */
7315 if (nregno < FIRST_PSEUDO_REGISTER)
7316 for (k = 1; k < nnr; k++)
7317 reg_last_reload_reg[nregno + k]
7319 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7322 /* Now do the inverse operation. */
7323 for (k = 0; k < nr; k++)
7325 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7326 reg_reloaded_contents[i + k]
7327 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7330 reg_reloaded_insn[i + k] = insn;
7331 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7332 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7333 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7337 /* Maybe the spill reg contains a copy of reload_in. Only do
7338 something if there will not be an output reload for
7339 the register being reloaded. */
7340 else if (rld[r].out_reg == 0
7342 && ((REG_P (rld[r].in)
7343 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7344 && ! reg_has_output_reload[REGNO (rld[r].in)])
7345 || (REG_P (rld[r].in_reg)
7346 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7347 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7354 if (REG_P (rld[r].in)
7355 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7357 else if (REG_P (rld[r].in_reg))
7360 in = XEXP (rld[r].in_reg, 0);
7361 nregno = REGNO (in);
7363 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7364 : hard_regno_nregs[nregno]
7365 [GET_MODE (rld[r].reg_rtx)]);
7367 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7369 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7371 && inherit_piecemeal_p (r, nregno));
7373 if (nregno < FIRST_PSEUDO_REGISTER)
7374 for (k = 1; k < nnr; k++)
7375 reg_last_reload_reg[nregno + k]
7377 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7380 /* Unless we inherited this reload, show we haven't
7381 recently done a store.
7382 Previous stores of inherited auto_inc expressions
7383 also have to be discarded. */
7384 if (! reload_inherited[r]
7385 || (rld[r].out && ! rld[r].out_reg))
7386 spill_reg_store[i] = 0;
7388 for (k = 0; k < nr; k++)
7390 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7391 reg_reloaded_contents[i + k]
7392 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7395 reg_reloaded_insn[i + k] = insn;
7396 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7397 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7398 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7403 /* However, if part of the reload reaches the end, then we must
7404 invalidate the old info for the part that survives to the end. */
7405 else if (part_reaches_end)
7407 for (k = 0; k < nr; k++)
7408 if (reload_reg_reaches_end_p (i + k,
7410 rld[r].when_needed))
7411 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7415 /* The following if-statement was #if 0'd in 1.34 (or before...).
7416 It's reenabled in 1.35 because supposedly nothing else
7417 deals with this problem. */
7419 /* If a register gets output-reloaded from a non-spill register,
7420 that invalidates any previous reloaded copy of it.
7421 But forget_old_reloads_1 won't get to see it, because
7422 it thinks only about the original insn. So invalidate it here.
7423 Also do the same thing for RELOAD_OTHER constraints where the
7424 output is discarded. */
7426 && ((rld[r].out != 0
7427 && (REG_P (rld[r].out)
7428 || (MEM_P (rld[r].out)
7429 && REG_P (rld[r].out_reg))))
7430 || (rld[r].out == 0 && rld[r].out_reg
7431 && REG_P (rld[r].out_reg))))
7433 rtx out = ((rld[r].out && REG_P (rld[r].out))
7434 ? rld[r].out : rld[r].out_reg);
7435 int nregno = REGNO (out);
7436 if (nregno >= FIRST_PSEUDO_REGISTER)
7438 rtx src_reg, store_insn = NULL_RTX;
7440 reg_last_reload_reg[nregno] = 0;
7442 /* If we can find a hard register that is stored, record
7443 the storing insn so that we may delete this insn with
7444 delete_output_reload. */
7445 src_reg = rld[r].reg_rtx;
7447 /* If this is an optional reload, try to find the source reg
7448 from an input reload. */
7451 rtx set = single_set (insn);
7452 if (set && SET_DEST (set) == rld[r].out)
7456 src_reg = SET_SRC (set);
7458 for (k = 0; k < n_reloads; k++)
7460 if (rld[k].in == src_reg)
7462 src_reg = rld[k].reg_rtx;
7469 store_insn = new_spill_reg_store[REGNO (src_reg)];
7470 if (src_reg && REG_P (src_reg)
7471 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7473 int src_regno = REGNO (src_reg);
7474 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7475 /* The place where to find a death note varies with
7476 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7477 necessarily checked exactly in the code that moves
7478 notes, so just check both locations. */
7479 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7480 if (! note && store_insn)
7481 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7484 spill_reg_store[src_regno + nr] = store_insn;
7485 spill_reg_stored_to[src_regno + nr] = out;
7486 reg_reloaded_contents[src_regno + nr] = nregno;
7487 reg_reloaded_insn[src_regno + nr] = store_insn;
7488 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7489 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7490 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7491 GET_MODE (src_reg)))
7492 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7494 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7496 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7498 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7500 reg_last_reload_reg[nregno] = src_reg;
7501 /* We have to set reg_has_output_reload here, or else
7502 forget_old_reloads_1 will clear reg_last_reload_reg
7504 reg_has_output_reload[nregno] = 1;
7509 int num_regs = hard_regno_nregs[nregno][GET_MODE (out)];
7511 while (num_regs-- > 0)
7512 reg_last_reload_reg[nregno + num_regs] = 0;
7516 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7519 /* Go through the motions to emit INSN and test if it is strictly valid.
7520 Return the emitted insn if valid, else return NULL. */
7523 emit_insn_if_valid_for_reload (rtx insn)
7525 rtx last = get_last_insn ();
7528 insn = emit_insn (insn);
7529 code = recog_memoized (insn);
7533 extract_insn (insn);
7534 /* We want constrain operands to treat this insn strictly in its
7535 validity determination, i.e., the way it would after reload has
7537 if (constrain_operands (1))
7541 delete_insns_since (last);
7545 /* Emit code to perform a reload from IN (which may be a reload register) to
7546 OUT (which may also be a reload register). IN or OUT is from operand
7547 OPNUM with reload type TYPE.
7549 Returns first insn emitted. */
7552 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7554 rtx last = get_last_insn ();
7557 /* If IN is a paradoxical SUBREG, remove it and try to put the
7558 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7559 if (GET_CODE (in) == SUBREG
7560 && (GET_MODE_SIZE (GET_MODE (in))
7561 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7562 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7563 in = SUBREG_REG (in), out = tem;
7564 else if (GET_CODE (out) == SUBREG
7565 && (GET_MODE_SIZE (GET_MODE (out))
7566 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7567 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7568 out = SUBREG_REG (out), in = tem;
7570 /* How to do this reload can get quite tricky. Normally, we are being
7571 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7572 register that didn't get a hard register. In that case we can just
7573 call emit_move_insn.
7575 We can also be asked to reload a PLUS that adds a register or a MEM to
7576 another register, constant or MEM. This can occur during frame pointer
7577 elimination and while reloading addresses. This case is handled by
7578 trying to emit a single insn to perform the add. If it is not valid,
7579 we use a two insn sequence.
7581 Or we can be asked to reload an unary operand that was a fragment of
7582 an addressing mode, into a register. If it isn't recognized as-is,
7583 we try making the unop operand and the reload-register the same:
7584 (set reg:X (unop:X expr:Y))
7585 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
7587 Finally, we could be called to handle an 'o' constraint by putting
7588 an address into a register. In that case, we first try to do this
7589 with a named pattern of "reload_load_address". If no such pattern
7590 exists, we just emit a SET insn and hope for the best (it will normally
7591 be valid on machines that use 'o').
7593 This entire process is made complex because reload will never
7594 process the insns we generate here and so we must ensure that
7595 they will fit their constraints and also by the fact that parts of
7596 IN might be being reloaded separately and replaced with spill registers.
7597 Because of this, we are, in some sense, just guessing the right approach
7598 here. The one listed above seems to work.
7600 ??? At some point, this whole thing needs to be rethought. */
7602 if (GET_CODE (in) == PLUS
7603 && (REG_P (XEXP (in, 0))
7604 || GET_CODE (XEXP (in, 0)) == SUBREG
7605 || MEM_P (XEXP (in, 0)))
7606 && (REG_P (XEXP (in, 1))
7607 || GET_CODE (XEXP (in, 1)) == SUBREG
7608 || CONSTANT_P (XEXP (in, 1))
7609 || MEM_P (XEXP (in, 1))))
7611 /* We need to compute the sum of a register or a MEM and another
7612 register, constant, or MEM, and put it into the reload
7613 register. The best possible way of doing this is if the machine
7614 has a three-operand ADD insn that accepts the required operands.
7616 The simplest approach is to try to generate such an insn and see if it
7617 is recognized and matches its constraints. If so, it can be used.
7619 It might be better not to actually emit the insn unless it is valid,
7620 but we need to pass the insn as an operand to `recog' and
7621 `extract_insn' and it is simpler to emit and then delete the insn if
7622 not valid than to dummy things up. */
7624 rtx op0, op1, tem, insn;
7627 op0 = find_replacement (&XEXP (in, 0));
7628 op1 = find_replacement (&XEXP (in, 1));
7630 /* Since constraint checking is strict, commutativity won't be
7631 checked, so we need to do that here to avoid spurious failure
7632 if the add instruction is two-address and the second operand
7633 of the add is the same as the reload reg, which is frequently
7634 the case. If the insn would be A = B + A, rearrange it so
7635 it will be A = A + B as constrain_operands expects. */
7637 if (REG_P (XEXP (in, 1))
7638 && REGNO (out) == REGNO (XEXP (in, 1)))
7639 tem = op0, op0 = op1, op1 = tem;
7641 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7642 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7644 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7648 /* If that failed, we must use a conservative two-insn sequence.
7650 Use a move to copy one operand into the reload register. Prefer
7651 to reload a constant, MEM or pseudo since the move patterns can
7652 handle an arbitrary operand. If OP1 is not a constant, MEM or
7653 pseudo and OP1 is not a valid operand for an add instruction, then
7656 After reloading one of the operands into the reload register, add
7657 the reload register to the output register.
7659 If there is another way to do this for a specific machine, a
7660 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7663 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7665 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7667 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7668 || (code != CODE_FOR_nothing
7669 && ! ((*insn_data[code].operand[2].predicate)
7670 (op1, insn_data[code].operand[2].mode))))
7671 tem = op0, op0 = op1, op1 = tem;
7673 gen_reload (out, op0, opnum, type);
7675 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7676 This fixes a problem on the 32K where the stack pointer cannot
7677 be used as an operand of an add insn. */
7679 if (rtx_equal_p (op0, op1))
7682 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
7685 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7687 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7691 /* If that failed, copy the address register to the reload register.
7692 Then add the constant to the reload register. */
7694 gen_reload (out, op1, opnum, type);
7695 insn = emit_insn (gen_add2_insn (out, op0));
7696 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7699 #ifdef SECONDARY_MEMORY_NEEDED
7700 /* If we need a memory location to do the move, do it that way. */
7701 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7702 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7703 && (REG_P (out) || GET_CODE (out) == SUBREG)
7704 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7705 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7706 REGNO_REG_CLASS (reg_or_subregno (out)),
7709 /* Get the memory to use and rewrite both registers to its mode. */
7710 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7712 if (GET_MODE (loc) != GET_MODE (out))
7713 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7715 if (GET_MODE (loc) != GET_MODE (in))
7716 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7718 gen_reload (loc, in, opnum, type);
7719 gen_reload (out, loc, opnum, type);
7722 else if (REG_P (out) && UNARY_P (in))
7729 op1 = find_replacement (&XEXP (in, 0));
7730 if (op1 != XEXP (in, 0))
7731 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
7733 /* First, try a plain SET. */
7734 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7738 /* If that failed, move the inner operand to the reload
7739 register, and try the same unop with the inner expression
7740 replaced with the reload register. */
7742 if (GET_MODE (op1) != GET_MODE (out))
7743 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
7747 gen_reload (out_moded, op1, opnum, type);
7750 = gen_rtx_SET (VOIDmode, out,
7751 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
7753 insn = emit_insn_if_valid_for_reload (insn);
7757 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7761 fatal_insn ("Failure trying to reload:", set);
7763 /* If IN is a simple operand, use gen_move_insn. */
7764 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
7765 emit_insn (gen_move_insn (out, in));
7767 #ifdef HAVE_reload_load_address
7768 else if (HAVE_reload_load_address)
7769 emit_insn (gen_reload_load_address (out, in));
7772 /* Otherwise, just write (set OUT IN) and hope for the best. */
7774 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7776 /* Return the first insn emitted.
7777 We can not just return get_last_insn, because there may have
7778 been multiple instructions emitted. Also note that gen_move_insn may
7779 emit more than one insn itself, so we can not assume that there is one
7780 insn emitted per emit_insn_before call. */
7782 return last ? NEXT_INSN (last) : get_insns ();
7785 /* Delete a previously made output-reload whose result we now believe
7786 is not needed. First we double-check.
7788 INSN is the insn now being processed.
7789 LAST_RELOAD_REG is the hard register number for which we want to delete
7790 the last output reload.
7791 J is the reload-number that originally used REG. The caller has made
7792 certain that reload J doesn't use REG any longer for input. */
7795 delete_output_reload (rtx insn, int j, int last_reload_reg)
7797 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7798 rtx reg = spill_reg_stored_to[last_reload_reg];
7801 int n_inherited = 0;
7805 /* It is possible that this reload has been only used to set another reload
7806 we eliminated earlier and thus deleted this instruction too. */
7807 if (INSN_DELETED_P (output_reload_insn))
7810 /* Get the raw pseudo-register referred to. */
7812 while (GET_CODE (reg) == SUBREG)
7813 reg = SUBREG_REG (reg);
7814 substed = reg_equiv_memory_loc[REGNO (reg)];
7816 /* This is unsafe if the operand occurs more often in the current
7817 insn than it is inherited. */
7818 for (k = n_reloads - 1; k >= 0; k--)
7820 rtx reg2 = rld[k].in;
7823 if (MEM_P (reg2) || reload_override_in[k])
7824 reg2 = rld[k].in_reg;
7826 if (rld[k].out && ! rld[k].out_reg)
7827 reg2 = XEXP (rld[k].in_reg, 0);
7829 while (GET_CODE (reg2) == SUBREG)
7830 reg2 = SUBREG_REG (reg2);
7831 if (rtx_equal_p (reg2, reg))
7833 if (reload_inherited[k] || reload_override_in[k] || k == j)
7836 reg2 = rld[k].out_reg;
7839 while (GET_CODE (reg2) == SUBREG)
7840 reg2 = XEXP (reg2, 0);
7841 if (rtx_equal_p (reg2, reg))
7848 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7850 n_occurrences += count_occurrences (PATTERN (insn),
7851 eliminate_regs (substed, 0,
7853 if (n_occurrences > n_inherited)
7856 /* If the pseudo-reg we are reloading is no longer referenced
7857 anywhere between the store into it and here,
7858 and we're within the same basic block, then the value can only
7859 pass through the reload reg and end up here.
7860 Otherwise, give up--return. */
7861 for (i1 = NEXT_INSN (output_reload_insn);
7862 i1 != insn; i1 = NEXT_INSN (i1))
7864 if (NOTE_INSN_BASIC_BLOCK_P (i1))
7866 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
7867 && reg_mentioned_p (reg, PATTERN (i1)))
7869 /* If this is USE in front of INSN, we only have to check that
7870 there are no more references than accounted for by inheritance. */
7871 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
7873 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7874 i1 = NEXT_INSN (i1);
7876 if (n_occurrences <= n_inherited && i1 == insn)
7882 /* We will be deleting the insn. Remove the spill reg information. */
7883 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
7885 spill_reg_store[last_reload_reg + k] = 0;
7886 spill_reg_stored_to[last_reload_reg + k] = 0;
7889 /* The caller has already checked that REG dies or is set in INSN.
7890 It has also checked that we are optimizing, and thus some
7891 inaccuracies in the debugging information are acceptable.
7892 So we could just delete output_reload_insn. But in some cases
7893 we can improve the debugging information without sacrificing
7894 optimization - maybe even improving the code: See if the pseudo
7895 reg has been completely replaced with reload regs. If so, delete
7896 the store insn and forget we had a stack slot for the pseudo. */
7897 if (rld[j].out != rld[j].in
7898 && REG_N_DEATHS (REGNO (reg)) == 1
7899 && REG_N_SETS (REGNO (reg)) == 1
7900 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7901 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7905 /* We know that it was used only between here and the beginning of
7906 the current basic block. (We also know that the last use before
7907 INSN was the output reload we are thinking of deleting, but never
7908 mind that.) Search that range; see if any ref remains. */
7909 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7911 rtx set = single_set (i2);
7913 /* Uses which just store in the pseudo don't count,
7914 since if they are the only uses, they are dead. */
7915 if (set != 0 && SET_DEST (set) == reg)
7920 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
7921 && reg_mentioned_p (reg, PATTERN (i2)))
7923 /* Some other ref remains; just delete the output reload we
7925 delete_address_reloads (output_reload_insn, insn);
7926 delete_insn (output_reload_insn);
7931 /* Delete the now-dead stores into this pseudo. Note that this
7932 loop also takes care of deleting output_reload_insn. */
7933 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7935 rtx set = single_set (i2);
7937 if (set != 0 && SET_DEST (set) == reg)
7939 delete_address_reloads (i2, insn);
7947 /* For the debugging info, say the pseudo lives in this reload reg. */
7948 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7949 alter_reg (REGNO (reg), -1);
7953 delete_address_reloads (output_reload_insn, insn);
7954 delete_insn (output_reload_insn);
7958 /* We are going to delete DEAD_INSN. Recursively delete loads of
7959 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7960 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7962 delete_address_reloads (rtx dead_insn, rtx current_insn)
7964 rtx set = single_set (dead_insn);
7965 rtx set2, dst, prev, next;
7968 rtx dst = SET_DEST (set);
7970 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7972 /* If we deleted the store from a reloaded post_{in,de}c expression,
7973 we can delete the matching adds. */
7974 prev = PREV_INSN (dead_insn);
7975 next = NEXT_INSN (dead_insn);
7976 if (! prev || ! next)
7978 set = single_set (next);
7979 set2 = single_set (prev);
7981 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7982 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7983 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7985 dst = SET_DEST (set);
7986 if (! rtx_equal_p (dst, SET_DEST (set2))
7987 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7988 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7989 || (INTVAL (XEXP (SET_SRC (set), 1))
7990 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7992 delete_related_insns (prev);
7993 delete_related_insns (next);
7996 /* Subfunction of delete_address_reloads: process registers found in X. */
7998 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8000 rtx prev, set, dst, i2;
8002 enum rtx_code code = GET_CODE (x);
8006 const char *fmt = GET_RTX_FORMAT (code);
8007 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8010 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8011 else if (fmt[i] == 'E')
8013 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8014 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8021 if (spill_reg_order[REGNO (x)] < 0)
8024 /* Scan backwards for the insn that sets x. This might be a way back due
8026 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8028 code = GET_CODE (prev);
8029 if (code == CODE_LABEL || code == JUMP_INSN)
8033 if (reg_set_p (x, PATTERN (prev)))
8035 if (reg_referenced_p (x, PATTERN (prev)))
8038 if (! prev || INSN_UID (prev) < reload_first_uid)
8040 /* Check that PREV only sets the reload register. */
8041 set = single_set (prev);
8044 dst = SET_DEST (set);
8046 || ! rtx_equal_p (dst, x))
8048 if (! reg_set_p (dst, PATTERN (dead_insn)))
8050 /* Check if DST was used in a later insn -
8051 it might have been inherited. */
8052 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8058 if (reg_referenced_p (dst, PATTERN (i2)))
8060 /* If there is a reference to the register in the current insn,
8061 it might be loaded in a non-inherited reload. If no other
8062 reload uses it, that means the register is set before
8064 if (i2 == current_insn)
8066 for (j = n_reloads - 1; j >= 0; j--)
8067 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8068 || reload_override_in[j] == dst)
8070 for (j = n_reloads - 1; j >= 0; j--)
8071 if (rld[j].in && rld[j].reg_rtx == dst)
8080 /* If DST is still live at CURRENT_INSN, check if it is used for
8081 any reload. Note that even if CURRENT_INSN sets DST, we still
8082 have to check the reloads. */
8083 if (i2 == current_insn)
8085 for (j = n_reloads - 1; j >= 0; j--)
8086 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8087 || reload_override_in[j] == dst)
8089 /* ??? We can't finish the loop here, because dst might be
8090 allocated to a pseudo in this block if no reload in this
8091 block needs any of the classes containing DST - see
8092 spill_hard_reg. There is no easy way to tell this, so we
8093 have to scan till the end of the basic block. */
8095 if (reg_set_p (dst, PATTERN (i2)))
8099 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8100 reg_reloaded_contents[REGNO (dst)] = -1;
8104 /* Output reload-insns to reload VALUE into RELOADREG.
8105 VALUE is an autoincrement or autodecrement RTX whose operand
8106 is a register or memory location;
8107 so reloading involves incrementing that location.
8108 IN is either identical to VALUE, or some cheaper place to reload from.
8110 INC_AMOUNT is the number to increment or decrement by (always positive).
8111 This cannot be deduced from VALUE.
8113 Return the instruction that stores into RELOADREG. */
8116 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8118 /* REG or MEM to be copied and incremented. */
8119 rtx incloc = XEXP (value, 0);
8120 /* Nonzero if increment after copying. */
8121 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
8127 rtx real_in = in == value ? XEXP (in, 0) : in;
8129 /* No hard register is equivalent to this register after
8130 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8131 we could inc/dec that register as well (maybe even using it for
8132 the source), but I'm not sure it's worth worrying about. */
8134 reg_last_reload_reg[REGNO (incloc)] = 0;
8136 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8137 inc_amount = -inc_amount;
8139 inc = GEN_INT (inc_amount);
8141 /* If this is post-increment, first copy the location to the reload reg. */
8142 if (post && real_in != reloadreg)
8143 emit_insn (gen_move_insn (reloadreg, real_in));
8147 /* See if we can directly increment INCLOC. Use a method similar to
8148 that in gen_reload. */
8150 last = get_last_insn ();
8151 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8152 gen_rtx_PLUS (GET_MODE (incloc),
8155 code = recog_memoized (add_insn);
8158 extract_insn (add_insn);
8159 if (constrain_operands (1))
8161 /* If this is a pre-increment and we have incremented the value
8162 where it lives, copy the incremented value to RELOADREG to
8163 be used as an address. */
8166 emit_insn (gen_move_insn (reloadreg, incloc));
8171 delete_insns_since (last);
8174 /* If couldn't do the increment directly, must increment in RELOADREG.
8175 The way we do this depends on whether this is pre- or post-increment.
8176 For pre-increment, copy INCLOC to the reload register, increment it
8177 there, then save back. */
8181 if (in != reloadreg)
8182 emit_insn (gen_move_insn (reloadreg, real_in));
8183 emit_insn (gen_add2_insn (reloadreg, inc));
8184 store = emit_insn (gen_move_insn (incloc, reloadreg));
8189 Because this might be a jump insn or a compare, and because RELOADREG
8190 may not be available after the insn in an input reload, we must do
8191 the incrementation before the insn being reloaded for.
8193 We have already copied IN to RELOADREG. Increment the copy in
8194 RELOADREG, save that back, then decrement RELOADREG so it has
8195 the original value. */
8197 emit_insn (gen_add2_insn (reloadreg, inc));
8198 store = emit_insn (gen_move_insn (incloc, reloadreg));
8199 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8207 add_auto_inc_notes (rtx insn, rtx x)
8209 enum rtx_code code = GET_CODE (x);
8213 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8216 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8220 /* Scan all the operand sub-expressions. */
8221 fmt = GET_RTX_FORMAT (code);
8222 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8225 add_auto_inc_notes (insn, XEXP (x, i));
8226 else if (fmt[i] == 'E')
8227 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8228 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8233 /* Copy EH notes from an insn to its reloads. */
8235 copy_eh_notes (rtx insn, rtx x)
8237 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8240 for (; x != 0; x = NEXT_INSN (x))
8242 if (may_trap_p (PATTERN (x)))
8244 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8250 /* This is used by reload pass, that does emit some instructions after
8251 abnormal calls moving basic block end, but in fact it wants to emit
8252 them on the edge. Looks for abnormal call edges, find backward the
8253 proper call and fix the damage.
8255 Similar handle instructions throwing exceptions internally. */
8257 fixup_abnormal_edges (void)
8259 bool inserted = false;
8267 /* Look for cases we are interested in - calls or instructions causing
8269 FOR_EACH_EDGE (e, ei, bb->succs)
8271 if (e->flags & EDGE_ABNORMAL_CALL)
8273 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8274 == (EDGE_ABNORMAL | EDGE_EH))
8277 if (e && !CALL_P (BB_END (bb))
8278 && !can_throw_internal (BB_END (bb)))
8282 /* Get past the new insns generated. Allow notes, as the insns
8283 may be already deleted. */
8285 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8286 && !can_throw_internal (insn)
8287 && insn != BB_HEAD (bb))
8288 insn = PREV_INSN (insn);
8290 if (CALL_P (insn) || can_throw_internal (insn))
8294 stop = NEXT_INSN (BB_END (bb));
8296 insn = NEXT_INSN (insn);
8298 FOR_EACH_EDGE (e, ei, bb->succs)
8299 if (e->flags & EDGE_FALLTHRU)
8302 while (insn && insn != stop)
8304 next = NEXT_INSN (insn);
8309 /* Sometimes there's still the return value USE.
8310 If it's placed after a trapping call (i.e. that
8311 call is the last insn anyway), we have no fallthru
8312 edge. Simply delete this use and don't try to insert
8313 on the non-existent edge. */
8314 if (GET_CODE (PATTERN (insn)) != USE)
8316 /* We're not deleting it, we're moving it. */
8317 INSN_DELETED_P (insn) = 0;
8318 PREV_INSN (insn) = NULL_RTX;
8319 NEXT_INSN (insn) = NULL_RTX;
8321 insert_insn_on_edge (insn, e);
8329 /* It may be that we don't find any such trapping insn. In this
8330 case we discovered quite late that the insn that had been
8331 marked as can_throw_internal in fact couldn't trap at all.
8332 So we should in fact delete the EH edges out of the block. */
8334 purge_dead_edges (bb);
8338 /* We've possibly turned single trapping insn into multiple ones. */
8339 if (flag_non_call_exceptions)
8342 blocks = sbitmap_alloc (last_basic_block);
8343 sbitmap_ones (blocks);
8344 find_many_sub_basic_blocks (blocks);
8348 commit_edge_insertions ();
8350 #ifdef ENABLE_CHECKING
8351 /* Verify that we didn't turn one trapping insn into many, and that
8352 we found and corrected all of the problems wrt fixups on the
8354 verify_flow_info ();
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