1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "addresses.h"
39 #include "basic-block.h"
52 /* This file contains the reload pass of the compiler, which is
53 run after register allocation has been done. It checks that
54 each insn is valid (operands required to be in registers really
55 are in registers of the proper class) and fixes up invalid ones
56 by copying values temporarily into registers for the insns
59 The results of register allocation are described by the vector
60 reg_renumber; the insns still contain pseudo regs, but reg_renumber
61 can be used to find which hard reg, if any, a pseudo reg is in.
63 The technique we always use is to free up a few hard regs that are
64 called ``reload regs'', and for each place where a pseudo reg
65 must be in a hard reg, copy it temporarily into one of the reload regs.
67 Reload regs are allocated locally for every instruction that needs
68 reloads. When there are pseudos which are allocated to a register that
69 has been chosen as a reload reg, such pseudos must be ``spilled''.
70 This means that they go to other hard regs, or to stack slots if no other
71 available hard regs can be found. Spilling can invalidate more
72 insns, requiring additional need for reloads, so we must keep checking
73 until the process stabilizes.
75 For machines with different classes of registers, we must keep track
76 of the register class needed for each reload, and make sure that
77 we allocate enough reload registers of each class.
79 The file reload.c contains the code that checks one insn for
80 validity and reports the reloads that it needs. This file
81 is in charge of scanning the entire rtl code, accumulating the
82 reload needs, spilling, assigning reload registers to use for
83 fixing up each insn, and generating the new insns to copy values
84 into the reload registers. */
86 /* During reload_as_needed, element N contains a REG rtx for the hard reg
87 into which reg N has been reloaded (perhaps for a previous insn). */
88 static rtx *reg_last_reload_reg;
90 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
91 for an output reload that stores into reg N. */
92 static regset_head reg_has_output_reload;
94 /* Indicates which hard regs are reload-registers for an output reload
95 in the current insn. */
96 static HARD_REG_SET reg_is_output_reload;
98 /* Element N is the constant value to which pseudo reg N is equivalent,
99 or zero if pseudo reg N is not equivalent to a constant.
100 find_reloads looks at this in order to replace pseudo reg N
101 with the constant it stands for. */
102 rtx *reg_equiv_constant;
104 /* Element N is an invariant value to which pseudo reg N is equivalent.
105 eliminate_regs_in_insn uses this to replace pseudos in particular
107 rtx *reg_equiv_invariant;
109 /* Element N is a memory location to which pseudo reg N is equivalent,
110 prior to any register elimination (such as frame pointer to stack
111 pointer). Depending on whether or not it is a valid address, this value
112 is transferred to either reg_equiv_address or reg_equiv_mem. */
113 rtx *reg_equiv_memory_loc;
115 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
116 collector can keep track of what is inside. */
117 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
119 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
120 This is used when the address is not valid as a memory address
121 (because its displacement is too big for the machine.) */
122 rtx *reg_equiv_address;
124 /* Element N is the memory slot to which pseudo reg N is equivalent,
125 or zero if pseudo reg N is not equivalent to a memory slot. */
128 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
129 alternate representations of the location of pseudo reg N. */
130 rtx *reg_equiv_alt_mem_list;
132 /* Widest width in which each pseudo reg is referred to (via subreg). */
133 static unsigned int *reg_max_ref_width;
135 /* Element N is the list of insns that initialized reg N from its equivalent
136 constant or memory slot. */
138 int reg_equiv_init_size;
140 /* Vector to remember old contents of reg_renumber before spilling. */
141 static short *reg_old_renumber;
143 /* During reload_as_needed, element N contains the last pseudo regno reloaded
144 into hard register N. If that pseudo reg occupied more than one register,
145 reg_reloaded_contents points to that pseudo for each spill register in
146 use; all of these must remain set for an inheritance to occur. */
147 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
149 /* During reload_as_needed, element N contains the insn for which
150 hard register N was last used. Its contents are significant only
151 when reg_reloaded_valid is set for this register. */
152 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
154 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
155 static HARD_REG_SET reg_reloaded_valid;
156 /* Indicate if the register was dead at the end of the reload.
157 This is only valid if reg_reloaded_contents is set and valid. */
158 static HARD_REG_SET reg_reloaded_dead;
160 /* Indicate whether the register's current value is one that is not
161 safe to retain across a call, even for registers that are normally
162 call-saved. This is only meaningful for members of reg_reloaded_valid. */
163 static HARD_REG_SET reg_reloaded_call_part_clobbered;
165 /* Number of spill-regs so far; number of valid elements of spill_regs. */
168 /* In parallel with spill_regs, contains REG rtx's for those regs.
169 Holds the last rtx used for any given reg, or 0 if it has never
170 been used for spilling yet. This rtx is reused, provided it has
172 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
174 /* In parallel with spill_regs, contains nonzero for a spill reg
175 that was stored after the last time it was used.
176 The precise value is the insn generated to do the store. */
177 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
179 /* This is the register that was stored with spill_reg_store. This is a
180 copy of reload_out / reload_out_reg when the value was stored; if
181 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
182 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
184 /* This table is the inverse mapping of spill_regs:
185 indexed by hard reg number,
186 it contains the position of that reg in spill_regs,
187 or -1 for something that is not in spill_regs.
189 ?!? This is no longer accurate. */
190 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
192 /* This reg set indicates registers that can't be used as spill registers for
193 the currently processed insn. These are the hard registers which are live
194 during the insn, but not allocated to pseudos, as well as fixed
196 static HARD_REG_SET bad_spill_regs;
198 /* These are the hard registers that can't be used as spill register for any
199 insn. This includes registers used for user variables and registers that
200 we can't eliminate. A register that appears in this set also can't be used
201 to retry register allocation. */
202 static HARD_REG_SET bad_spill_regs_global;
204 /* Describes order of use of registers for reloading
205 of spilled pseudo-registers. `n_spills' is the number of
206 elements that are actually valid; new ones are added at the end.
208 Both spill_regs and spill_reg_order are used on two occasions:
209 once during find_reload_regs, where they keep track of the spill registers
210 for a single insn, but also during reload_as_needed where they show all
211 the registers ever used by reload. For the latter case, the information
212 is calculated during finish_spills. */
213 static short spill_regs[FIRST_PSEUDO_REGISTER];
215 /* This vector of reg sets indicates, for each pseudo, which hard registers
216 may not be used for retrying global allocation because the register was
217 formerly spilled from one of them. If we allowed reallocating a pseudo to
218 a register that it was already allocated to, reload might not
220 static HARD_REG_SET *pseudo_previous_regs;
222 /* This vector of reg sets indicates, for each pseudo, which hard
223 registers may not be used for retrying global allocation because they
224 are used as spill registers during one of the insns in which the
226 static HARD_REG_SET *pseudo_forbidden_regs;
228 /* All hard regs that have been used as spill registers for any insn are
229 marked in this set. */
230 static HARD_REG_SET used_spill_regs;
232 /* Index of last register assigned as a spill register. We allocate in
233 a round-robin fashion. */
234 static int last_spill_reg;
236 /* Nonzero if indirect addressing is supported on the machine; this means
237 that spilling (REG n) does not require reloading it into a register in
238 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
239 value indicates the level of indirect addressing supported, e.g., two
240 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
242 static char spill_indirect_levels;
244 /* Nonzero if indirect addressing is supported when the innermost MEM is
245 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
246 which these are valid is the same as spill_indirect_levels, above. */
247 char indirect_symref_ok;
249 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
250 char double_reg_address_ok;
252 /* Record the stack slot for each spilled hard register. */
253 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
255 /* Width allocated so far for that stack slot. */
256 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
258 /* Record which pseudos needed to be spilled. */
259 static regset_head spilled_pseudos;
261 /* Record which pseudos changed their allocation in finish_spills. */
262 static regset_head changed_allocation_pseudos;
264 /* Used for communication between order_regs_for_reload and count_pseudo.
265 Used to avoid counting one pseudo twice. */
266 static regset_head pseudos_counted;
268 /* First uid used by insns created by reload in this function.
269 Used in find_equiv_reg. */
270 int reload_first_uid;
272 /* Flag set by local-alloc or global-alloc if anything is live in
273 a call-clobbered reg across calls. */
274 int caller_save_needed;
276 /* Set to 1 while reload_as_needed is operating.
277 Required by some machines to handle any generated moves differently. */
278 int reload_in_progress = 0;
280 /* These arrays record the insn_code of insns that may be needed to
281 perform input and output reloads of special objects. They provide a
282 place to pass a scratch register. */
283 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
284 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
286 /* This obstack is used for allocation of rtl during register elimination.
287 The allocated storage can be freed once find_reloads has processed the
289 static struct obstack reload_obstack;
291 /* Points to the beginning of the reload_obstack. All insn_chain structures
292 are allocated first. */
293 static char *reload_startobj;
295 /* The point after all insn_chain structures. Used to quickly deallocate
296 memory allocated in copy_reloads during calculate_needs_all_insns. */
297 static char *reload_firstobj;
299 /* This points before all local rtl generated by register elimination.
300 Used to quickly free all memory after processing one insn. */
301 static char *reload_insn_firstobj;
303 /* List of insn_chain instructions, one for every insn that reload needs to
305 struct insn_chain *reload_insn_chain;
307 /* List of all insns needing reloads. */
308 static struct insn_chain *insns_need_reload;
310 /* This structure is used to record information about register eliminations.
311 Each array entry describes one possible way of eliminating a register
312 in favor of another. If there is more than one way of eliminating a
313 particular register, the most preferred should be specified first. */
317 int from; /* Register number to be eliminated. */
318 int to; /* Register number used as replacement. */
319 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
320 int can_eliminate; /* Nonzero if this elimination can be done. */
321 int can_eliminate_previous; /* Value returned by TARGET_CAN_ELIMINATE
322 target hook in previous scan over insns
324 HOST_WIDE_INT offset; /* Current offset between the two regs. */
325 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
326 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
327 rtx from_rtx; /* REG rtx for the register to be eliminated.
328 We cannot simply compare the number since
329 we might then spuriously replace a hard
330 register corresponding to a pseudo
331 assigned to the reg to be eliminated. */
332 rtx to_rtx; /* REG rtx for the replacement. */
335 static struct elim_table *reg_eliminate = 0;
337 /* This is an intermediate structure to initialize the table. It has
338 exactly the members provided by ELIMINABLE_REGS. */
339 static const struct elim_table_1
343 } reg_eliminate_1[] =
345 /* If a set of eliminable registers was specified, define the table from it.
346 Otherwise, default to the normal case of the frame pointer being
347 replaced by the stack pointer. */
349 #ifdef ELIMINABLE_REGS
352 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
355 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
357 /* Record the number of pending eliminations that have an offset not equal
358 to their initial offset. If nonzero, we use a new copy of each
359 replacement result in any insns encountered. */
360 int num_not_at_initial_offset;
362 /* Count the number of registers that we may be able to eliminate. */
363 static int num_eliminable;
364 /* And the number of registers that are equivalent to a constant that
365 can be eliminated to frame_pointer / arg_pointer + constant. */
366 static int num_eliminable_invariants;
368 /* For each label, we record the offset of each elimination. If we reach
369 a label by more than one path and an offset differs, we cannot do the
370 elimination. This information is indexed by the difference of the
371 number of the label and the first label number. We can't offset the
372 pointer itself as this can cause problems on machines with segmented
373 memory. The first table is an array of flags that records whether we
374 have yet encountered a label and the second table is an array of arrays,
375 one entry in the latter array for each elimination. */
377 static int first_label_num;
378 static char *offsets_known_at;
379 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
381 /* Number of labels in the current function. */
383 static int num_labels;
385 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
386 static void maybe_fix_stack_asms (void);
387 static void copy_reloads (struct insn_chain *);
388 static void calculate_needs_all_insns (int);
389 static int find_reg (struct insn_chain *, int);
390 static void find_reload_regs (struct insn_chain *);
391 static void select_reload_regs (void);
392 static void delete_caller_save_insns (void);
394 static void spill_failure (rtx, enum reg_class);
395 static void count_spilled_pseudo (int, int, int);
396 static void delete_dead_insn (rtx);
397 static void alter_reg (int, int, bool);
398 static void set_label_offsets (rtx, rtx, int);
399 static void check_eliminable_occurrences (rtx);
400 static void elimination_effects (rtx, enum machine_mode);
401 static int eliminate_regs_in_insn (rtx, int);
402 static void update_eliminable_offsets (void);
403 static void mark_not_eliminable (rtx, const_rtx, void *);
404 static void set_initial_elim_offsets (void);
405 static bool verify_initial_elim_offsets (void);
406 static void set_initial_label_offsets (void);
407 static void set_offsets_for_label (rtx);
408 static void init_elim_table (void);
409 static void update_eliminables (HARD_REG_SET *);
410 static void spill_hard_reg (unsigned int, int);
411 static int finish_spills (int);
412 static void scan_paradoxical_subregs (rtx);
413 static void count_pseudo (int);
414 static void order_regs_for_reload (struct insn_chain *);
415 static void reload_as_needed (int);
416 static void forget_old_reloads_1 (rtx, const_rtx, void *);
417 static void forget_marked_reloads (regset);
418 static int reload_reg_class_lower (const void *, const void *);
419 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
421 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
423 static int reload_reg_free_p (unsigned int, int, enum reload_type);
424 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
426 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
428 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
429 static int allocate_reload_reg (struct insn_chain *, int, int);
430 static int conflicts_with_override (rtx);
431 static void failed_reload (rtx, int);
432 static int set_reload_reg (int, int);
433 static void choose_reload_regs_init (struct insn_chain *, rtx *);
434 static void choose_reload_regs (struct insn_chain *);
435 static void merge_assigned_reloads (rtx);
436 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
438 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
440 static void do_input_reload (struct insn_chain *, struct reload *, int);
441 static void do_output_reload (struct insn_chain *, struct reload *, int);
442 static void emit_reload_insns (struct insn_chain *);
443 static void delete_output_reload (rtx, int, int, rtx);
444 static void delete_address_reloads (rtx, rtx);
445 static void delete_address_reloads_1 (rtx, rtx, rtx);
446 static rtx inc_for_reload (rtx, rtx, rtx, int);
448 static void add_auto_inc_notes (rtx, rtx);
450 static void substitute (rtx *, const_rtx, rtx);
451 static bool gen_reload_chain_without_interm_reg_p (int, int);
452 static int reloads_conflict (int, int);
453 static rtx gen_reload (rtx, rtx, int, enum reload_type);
454 static rtx emit_insn_if_valid_for_reload (rtx);
456 /* Initialize the reload pass. This is called at the beginning of compilation
457 and may be called again if the target is reinitialized. */
464 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
465 Set spill_indirect_levels to the number of levels such addressing is
466 permitted, zero if it is not permitted at all. */
469 = gen_rtx_MEM (Pmode,
472 LAST_VIRTUAL_REGISTER + 1),
474 spill_indirect_levels = 0;
476 while (memory_address_p (QImode, tem))
478 spill_indirect_levels++;
479 tem = gen_rtx_MEM (Pmode, tem);
482 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
484 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
485 indirect_symref_ok = memory_address_p (QImode, tem);
487 /* See if reg+reg is a valid (and offsettable) address. */
489 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
491 tem = gen_rtx_PLUS (Pmode,
492 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
493 gen_rtx_REG (Pmode, i));
495 /* This way, we make sure that reg+reg is an offsettable address. */
496 tem = plus_constant (tem, 4);
498 if (memory_address_p (QImode, tem))
500 double_reg_address_ok = 1;
505 /* Initialize obstack for our rtl allocation. */
506 gcc_obstack_init (&reload_obstack);
507 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
509 INIT_REG_SET (&spilled_pseudos);
510 INIT_REG_SET (&changed_allocation_pseudos);
511 INIT_REG_SET (&pseudos_counted);
514 /* List of insn chains that are currently unused. */
515 static struct insn_chain *unused_insn_chains = 0;
517 /* Allocate an empty insn_chain structure. */
519 new_insn_chain (void)
521 struct insn_chain *c;
523 if (unused_insn_chains == 0)
525 c = XOBNEW (&reload_obstack, struct insn_chain);
526 INIT_REG_SET (&c->live_throughout);
527 INIT_REG_SET (&c->dead_or_set);
531 c = unused_insn_chains;
532 unused_insn_chains = c->next;
534 c->is_caller_save_insn = 0;
535 c->need_operand_change = 0;
541 /* Small utility function to set all regs in hard reg set TO which are
542 allocated to pseudos in regset FROM. */
545 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
548 reg_set_iterator rsi;
550 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
552 int r = reg_renumber[regno];
556 /* reload_combine uses the information from DF_LIVE_IN,
557 which might still contain registers that have not
558 actually been allocated since they have an
560 gcc_assert (ira_conflicts_p || reload_completed);
563 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
567 /* Replace all pseudos found in LOC with their corresponding
571 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
584 unsigned int regno = REGNO (x);
586 if (regno < FIRST_PSEUDO_REGISTER)
589 x = eliminate_regs (x, mem_mode, usage);
593 replace_pseudos_in (loc, mem_mode, usage);
597 if (reg_equiv_constant[regno])
598 *loc = reg_equiv_constant[regno];
599 else if (reg_equiv_mem[regno])
600 *loc = reg_equiv_mem[regno];
601 else if (reg_equiv_address[regno])
602 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
605 gcc_assert (!REG_P (regno_reg_rtx[regno])
606 || REGNO (regno_reg_rtx[regno]) != regno);
607 *loc = regno_reg_rtx[regno];
612 else if (code == MEM)
614 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
618 /* Process each of our operands recursively. */
619 fmt = GET_RTX_FORMAT (code);
620 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
622 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
623 else if (*fmt == 'E')
624 for (j = 0; j < XVECLEN (x, i); j++)
625 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
628 /* Determine if the current function has an exception receiver block
629 that reaches the exit block via non-exceptional edges */
632 has_nonexceptional_receiver (void)
636 basic_block *tos, *worklist, bb;
638 /* If we're not optimizing, then just err on the safe side. */
642 /* First determine which blocks can reach exit via normal paths. */
643 tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1);
646 bb->flags &= ~BB_REACHABLE;
648 /* Place the exit block on our worklist. */
649 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
650 *tos++ = EXIT_BLOCK_PTR;
652 /* Iterate: find everything reachable from what we've already seen. */
653 while (tos != worklist)
657 FOR_EACH_EDGE (e, ei, bb->preds)
658 if (!(e->flags & EDGE_ABNORMAL))
660 basic_block src = e->src;
662 if (!(src->flags & BB_REACHABLE))
664 src->flags |= BB_REACHABLE;
671 /* Now see if there's a reachable block with an exceptional incoming
674 if (bb->flags & BB_REACHABLE)
675 FOR_EACH_EDGE (e, ei, bb->preds)
676 if (e->flags & EDGE_ABNORMAL)
679 /* No exceptional block reached exit unexceptionally. */
684 /* Global variables used by reload and its subroutines. */
686 /* Set during calculate_needs if an insn needs register elimination. */
687 static int something_needs_elimination;
688 /* Set during calculate_needs if an insn needs an operand changed. */
689 static int something_needs_operands_changed;
691 /* Nonzero means we couldn't get enough spill regs. */
694 /* Temporary array of pseudo-register number. */
695 static int *temp_pseudo_reg_arr;
697 /* Main entry point for the reload pass.
699 FIRST is the first insn of the function being compiled.
701 GLOBAL nonzero means we were called from global_alloc
702 and should attempt to reallocate any pseudoregs that we
703 displace from hard regs we will use for reloads.
704 If GLOBAL is zero, we do not have enough information to do that,
705 so any pseudo reg that is spilled must go to the stack.
707 Return value is nonzero if reload failed
708 and we must not do any more for this function. */
711 reload (rtx first, int global)
715 struct elim_table *ep;
718 /* Make sure even insns with volatile mem refs are recognizable. */
723 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
725 /* Make sure that the last insn in the chain
726 is not something that needs reloading. */
727 emit_note (NOTE_INSN_DELETED);
729 /* Enable find_equiv_reg to distinguish insns made by reload. */
730 reload_first_uid = get_max_uid ();
732 #ifdef SECONDARY_MEMORY_NEEDED
733 /* Initialize the secondary memory table. */
734 clear_secondary_mem ();
737 /* We don't have a stack slot for any spill reg yet. */
738 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
739 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
741 /* Initialize the save area information for caller-save, in case some
745 /* Compute which hard registers are now in use
746 as homes for pseudo registers.
747 This is done here rather than (eg) in global_alloc
748 because this point is reached even if not optimizing. */
749 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
752 /* A function that has a nonlocal label that can reach the exit
753 block via non-exceptional paths must save all call-saved
755 if (cfun->has_nonlocal_label
756 && has_nonexceptional_receiver ())
757 crtl->saves_all_registers = 1;
759 if (crtl->saves_all_registers)
760 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
761 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
762 df_set_regs_ever_live (i, true);
764 /* Find all the pseudo registers that didn't get hard regs
765 but do have known equivalent constants or memory slots.
766 These include parameters (known equivalent to parameter slots)
767 and cse'd or loop-moved constant memory addresses.
769 Record constant equivalents in reg_equiv_constant
770 so they will be substituted by find_reloads.
771 Record memory equivalents in reg_mem_equiv so they can
772 be substituted eventually by altering the REG-rtx's. */
774 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
775 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
776 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
777 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
778 reg_equiv_address = XCNEWVEC (rtx, max_regno);
779 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
780 reg_old_renumber = XCNEWVEC (short, max_regno);
781 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
782 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
783 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
785 CLEAR_HARD_REG_SET (bad_spill_regs_global);
787 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
788 to. Also find all paradoxical subregs and find largest such for
791 num_eliminable_invariants = 0;
792 for (insn = first; insn; insn = NEXT_INSN (insn))
794 rtx set = single_set (insn);
796 /* We may introduce USEs that we want to remove at the end, so
797 we'll mark them with QImode. Make sure there are no
798 previously-marked insns left by say regmove. */
799 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
800 && GET_MODE (insn) != VOIDmode)
801 PUT_MODE (insn, VOIDmode);
803 if (NONDEBUG_INSN_P (insn))
804 scan_paradoxical_subregs (PATTERN (insn));
806 if (set != 0 && REG_P (SET_DEST (set)))
808 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
814 i = REGNO (SET_DEST (set));
817 if (i <= LAST_VIRTUAL_REGISTER)
820 if (! function_invariant_p (x)
822 /* A function invariant is often CONSTANT_P but may
823 include a register. We promise to only pass
824 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
826 && LEGITIMATE_PIC_OPERAND_P (x)))
828 /* It can happen that a REG_EQUIV note contains a MEM
829 that is not a legitimate memory operand. As later
830 stages of reload assume that all addresses found
831 in the reg_equiv_* arrays were originally legitimate,
832 we ignore such REG_EQUIV notes. */
833 if (memory_operand (x, VOIDmode))
835 /* Always unshare the equivalence, so we can
836 substitute into this insn without touching the
838 reg_equiv_memory_loc[i] = copy_rtx (x);
840 else if (function_invariant_p (x))
842 if (GET_CODE (x) == PLUS)
844 /* This is PLUS of frame pointer and a constant,
845 and might be shared. Unshare it. */
846 reg_equiv_invariant[i] = copy_rtx (x);
847 num_eliminable_invariants++;
849 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
851 reg_equiv_invariant[i] = x;
852 num_eliminable_invariants++;
854 else if (LEGITIMATE_CONSTANT_P (x))
855 reg_equiv_constant[i] = x;
858 reg_equiv_memory_loc[i]
859 = force_const_mem (GET_MODE (SET_DEST (set)), x);
860 if (! reg_equiv_memory_loc[i])
861 reg_equiv_init[i] = NULL_RTX;
866 reg_equiv_init[i] = NULL_RTX;
871 reg_equiv_init[i] = NULL_RTX;
876 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
877 if (reg_equiv_init[i])
879 fprintf (dump_file, "init_insns for %u: ", i);
880 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
881 fprintf (dump_file, "\n");
886 first_label_num = get_first_label_num ();
887 num_labels = max_label_num () - first_label_num;
889 /* Allocate the tables used to store offset information at labels. */
890 /* We used to use alloca here, but the size of what it would try to
891 allocate would occasionally cause it to exceed the stack limit and
892 cause a core dump. */
893 offsets_known_at = XNEWVEC (char, num_labels);
894 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
896 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
897 stack slots to the pseudos that lack hard regs or equivalents.
898 Do not touch virtual registers. */
900 temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
901 for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
902 temp_pseudo_reg_arr[n++] = i;
905 /* Ask IRA to order pseudo-registers for better stack slot
907 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
909 for (i = 0; i < n; i++)
910 alter_reg (temp_pseudo_reg_arr[i], -1, false);
912 /* If we have some registers we think can be eliminated, scan all insns to
913 see if there is an insn that sets one of these registers to something
914 other than itself plus a constant. If so, the register cannot be
915 eliminated. Doing this scan here eliminates an extra pass through the
916 main reload loop in the most common case where register elimination
918 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
920 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
922 maybe_fix_stack_asms ();
924 insns_need_reload = 0;
925 something_needs_elimination = 0;
927 /* Initialize to -1, which means take the first spill register. */
930 /* Spill any hard regs that we know we can't eliminate. */
931 CLEAR_HARD_REG_SET (used_spill_regs);
932 /* There can be multiple ways to eliminate a register;
933 they should be listed adjacently.
934 Elimination for any register fails only if all possible ways fail. */
935 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
938 int can_eliminate = 0;
941 can_eliminate |= ep->can_eliminate;
944 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
946 spill_hard_reg (from, 1);
949 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
950 if (frame_pointer_needed)
951 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
953 finish_spills (global);
955 /* From now on, we may need to generate moves differently. We may also
956 allow modifications of insns which cause them to not be recognized.
957 Any such modifications will be cleaned up during reload itself. */
958 reload_in_progress = 1;
960 /* This loop scans the entire function each go-round
961 and repeats until one repetition spills no additional hard regs. */
964 int something_changed;
966 HOST_WIDE_INT starting_frame_size;
968 starting_frame_size = get_frame_size ();
970 set_initial_elim_offsets ();
971 set_initial_label_offsets ();
973 /* For each pseudo register that has an equivalent location defined,
974 try to eliminate any eliminable registers (such as the frame pointer)
975 assuming initial offsets for the replacement register, which
978 If the resulting location is directly addressable, substitute
979 the MEM we just got directly for the old REG.
981 If it is not addressable but is a constant or the sum of a hard reg
982 and constant, it is probably not addressable because the constant is
983 out of range, in that case record the address; we will generate
984 hairy code to compute the address in a register each time it is
985 needed. Similarly if it is a hard register, but one that is not
986 valid as an address register.
988 If the location is not addressable, but does not have one of the
989 above forms, assign a stack slot. We have to do this to avoid the
990 potential of producing lots of reloads if, e.g., a location involves
991 a pseudo that didn't get a hard register and has an equivalent memory
992 location that also involves a pseudo that didn't get a hard register.
994 Perhaps at some point we will improve reload_when_needed handling
995 so this problem goes away. But that's very hairy. */
997 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
998 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
1000 rtx x = eliminate_regs (reg_equiv_memory_loc[i], VOIDmode,
1003 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
1005 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
1006 else if (CONSTANT_P (XEXP (x, 0))
1007 || (REG_P (XEXP (x, 0))
1008 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
1009 || (GET_CODE (XEXP (x, 0)) == PLUS
1010 && REG_P (XEXP (XEXP (x, 0), 0))
1011 && (REGNO (XEXP (XEXP (x, 0), 0))
1012 < FIRST_PSEUDO_REGISTER)
1013 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
1014 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
1017 /* Make a new stack slot. Then indicate that something
1018 changed so we go back and recompute offsets for
1019 eliminable registers because the allocation of memory
1020 below might change some offset. reg_equiv_{mem,address}
1021 will be set up for this pseudo on the next pass around
1023 reg_equiv_memory_loc[i] = 0;
1024 reg_equiv_init[i] = 0;
1025 alter_reg (i, -1, true);
1029 if (caller_save_needed)
1030 setup_save_areas ();
1032 /* If we allocated another stack slot, redo elimination bookkeeping. */
1033 if (starting_frame_size != get_frame_size ())
1035 if (starting_frame_size && crtl->stack_alignment_needed)
1037 /* If we have a stack frame, we must align it now. The
1038 stack size may be a part of the offset computation for
1039 register elimination. So if this changes the stack size,
1040 then repeat the elimination bookkeeping. We don't
1041 realign when there is no stack, as that will cause a
1042 stack frame when none is needed should
1043 STARTING_FRAME_OFFSET not be already aligned to
1045 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
1046 if (starting_frame_size != get_frame_size ())
1050 if (caller_save_needed)
1052 save_call_clobbered_regs ();
1053 /* That might have allocated new insn_chain structures. */
1054 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1057 calculate_needs_all_insns (global);
1059 if (! ira_conflicts_p)
1060 /* Don't do it for IRA. We need this info because we don't
1061 change live_throughout and dead_or_set for chains when IRA
1063 CLEAR_REG_SET (&spilled_pseudos);
1067 something_changed = 0;
1069 /* If we allocated any new memory locations, make another pass
1070 since it might have changed elimination offsets. */
1071 if (starting_frame_size != get_frame_size ())
1072 something_changed = 1;
1074 /* Even if the frame size remained the same, we might still have
1075 changed elimination offsets, e.g. if find_reloads called
1076 force_const_mem requiring the back end to allocate a constant
1077 pool base register that needs to be saved on the stack. */
1078 else if (!verify_initial_elim_offsets ())
1079 something_changed = 1;
1082 HARD_REG_SET to_spill;
1083 CLEAR_HARD_REG_SET (to_spill);
1084 update_eliminables (&to_spill);
1085 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
1087 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1088 if (TEST_HARD_REG_BIT (to_spill, i))
1090 spill_hard_reg (i, 1);
1093 /* Regardless of the state of spills, if we previously had
1094 a register that we thought we could eliminate, but now can
1095 not eliminate, we must run another pass.
1097 Consider pseudos which have an entry in reg_equiv_* which
1098 reference an eliminable register. We must make another pass
1099 to update reg_equiv_* so that we do not substitute in the
1100 old value from when we thought the elimination could be
1102 something_changed = 1;
1106 select_reload_regs ();
1110 if (insns_need_reload != 0 || did_spill)
1111 something_changed |= finish_spills (global);
1113 if (! something_changed)
1116 if (caller_save_needed)
1117 delete_caller_save_insns ();
1119 obstack_free (&reload_obstack, reload_firstobj);
1122 /* If global-alloc was run, notify it of any register eliminations we have
1125 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1126 if (ep->can_eliminate)
1127 mark_elimination (ep->from, ep->to);
1129 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1130 If that insn didn't set the register (i.e., it copied the register to
1131 memory), just delete that insn instead of the equivalencing insn plus
1132 anything now dead. If we call delete_dead_insn on that insn, we may
1133 delete the insn that actually sets the register if the register dies
1134 there and that is incorrect. */
1136 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1138 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1141 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1143 rtx equiv_insn = XEXP (list, 0);
1145 /* If we already deleted the insn or if it may trap, we can't
1146 delete it. The latter case shouldn't happen, but can
1147 if an insn has a variable address, gets a REG_EH_REGION
1148 note added to it, and then gets converted into a load
1149 from a constant address. */
1150 if (NOTE_P (equiv_insn)
1151 || can_throw_internal (equiv_insn))
1153 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1154 delete_dead_insn (equiv_insn);
1156 SET_INSN_DELETED (equiv_insn);
1161 /* Use the reload registers where necessary
1162 by generating move instructions to move the must-be-register
1163 values into or out of the reload registers. */
1165 if (insns_need_reload != 0 || something_needs_elimination
1166 || something_needs_operands_changed)
1168 HOST_WIDE_INT old_frame_size = get_frame_size ();
1170 reload_as_needed (global);
1172 gcc_assert (old_frame_size == get_frame_size ());
1174 gcc_assert (verify_initial_elim_offsets ());
1177 /* If we were able to eliminate the frame pointer, show that it is no
1178 longer live at the start of any basic block. If it ls live by
1179 virtue of being in a pseudo, that pseudo will be marked live
1180 and hence the frame pointer will be known to be live via that
1183 if (! frame_pointer_needed)
1185 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1187 /* Come here (with failure set nonzero) if we can't get enough spill
1191 CLEAR_REG_SET (&changed_allocation_pseudos);
1192 CLEAR_REG_SET (&spilled_pseudos);
1193 reload_in_progress = 0;
1195 /* Now eliminate all pseudo regs by modifying them into
1196 their equivalent memory references.
1197 The REG-rtx's for the pseudos are modified in place,
1198 so all insns that used to refer to them now refer to memory.
1200 For a reg that has a reg_equiv_address, all those insns
1201 were changed by reloading so that no insns refer to it any longer;
1202 but the DECL_RTL of a variable decl may refer to it,
1203 and if so this causes the debugging info to mention the variable. */
1205 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1209 if (reg_equiv_mem[i])
1210 addr = XEXP (reg_equiv_mem[i], 0);
1212 if (reg_equiv_address[i])
1213 addr = reg_equiv_address[i];
1217 if (reg_renumber[i] < 0)
1219 rtx reg = regno_reg_rtx[i];
1221 REG_USERVAR_P (reg) = 0;
1222 PUT_CODE (reg, MEM);
1223 XEXP (reg, 0) = addr;
1224 if (reg_equiv_memory_loc[i])
1225 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1228 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1229 MEM_ATTRS (reg) = 0;
1231 MEM_NOTRAP_P (reg) = 1;
1233 else if (reg_equiv_mem[i])
1234 XEXP (reg_equiv_mem[i], 0) = addr;
1237 /* We don't want complex addressing modes in debug insns
1238 if simpler ones will do, so delegitimize equivalences
1240 if (MAY_HAVE_DEBUG_INSNS && reg_renumber[i] < 0)
1242 rtx reg = regno_reg_rtx[i];
1246 if (reg_equiv_constant[i])
1247 equiv = reg_equiv_constant[i];
1248 else if (reg_equiv_invariant[i])
1249 equiv = reg_equiv_invariant[i];
1250 else if (reg && MEM_P (reg))
1252 equiv = targetm.delegitimize_address (reg);
1256 else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
1260 for (use = DF_REG_USE_CHAIN (i); use;
1261 use = DF_REF_NEXT_REG (use))
1262 if (DEBUG_INSN_P (DF_REF_INSN (use)))
1264 rtx *loc = DF_REF_LOC (use);
1268 *loc = copy_rtx (equiv);
1269 else if (GET_CODE (x) == SUBREG
1270 && SUBREG_REG (x) == reg)
1271 *loc = simplify_gen_subreg (GET_MODE (x), equiv,
1280 /* We must set reload_completed now since the cleanup_subreg_operands call
1281 below will re-recognize each insn and reload may have generated insns
1282 which are only valid during and after reload. */
1283 reload_completed = 1;
1285 /* Make a pass over all the insns and delete all USEs which we inserted
1286 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1287 notes. Delete all CLOBBER insns, except those that refer to the return
1288 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1289 from misarranging variable-array code, and simplify (subreg (reg))
1290 operands. Strip and regenerate REG_INC notes that may have been moved
1293 for (insn = first; insn; insn = NEXT_INSN (insn))
1299 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1300 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1302 if ((GET_CODE (PATTERN (insn)) == USE
1303 /* We mark with QImode USEs introduced by reload itself. */
1304 && (GET_MODE (insn) == QImode
1305 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1306 || (GET_CODE (PATTERN (insn)) == CLOBBER
1307 && (!MEM_P (XEXP (PATTERN (insn), 0))
1308 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1309 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1310 && XEXP (XEXP (PATTERN (insn), 0), 0)
1311 != stack_pointer_rtx))
1312 && (!REG_P (XEXP (PATTERN (insn), 0))
1313 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1319 /* Some CLOBBERs may survive until here and still reference unassigned
1320 pseudos with const equivalent, which may in turn cause ICE in later
1321 passes if the reference remains in place. */
1322 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1323 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1324 VOIDmode, PATTERN (insn));
1326 /* Discard obvious no-ops, even without -O. This optimization
1327 is fast and doesn't interfere with debugging. */
1328 if (NONJUMP_INSN_P (insn)
1329 && GET_CODE (PATTERN (insn)) == SET
1330 && REG_P (SET_SRC (PATTERN (insn)))
1331 && REG_P (SET_DEST (PATTERN (insn)))
1332 && (REGNO (SET_SRC (PATTERN (insn)))
1333 == REGNO (SET_DEST (PATTERN (insn)))))
1339 pnote = ®_NOTES (insn);
1342 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1343 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1344 || REG_NOTE_KIND (*pnote) == REG_INC)
1345 *pnote = XEXP (*pnote, 1);
1347 pnote = &XEXP (*pnote, 1);
1351 add_auto_inc_notes (insn, PATTERN (insn));
1354 /* Simplify (subreg (reg)) if it appears as an operand. */
1355 cleanup_subreg_operands (insn);
1357 /* Clean up invalid ASMs so that they don't confuse later passes.
1359 if (asm_noperands (PATTERN (insn)) >= 0)
1361 extract_insn (insn);
1362 if (!constrain_operands (1))
1364 error_for_asm (insn,
1365 "%<asm%> operand has impossible constraints");
1372 /* If we are doing generic stack checking, give a warning if this
1373 function's frame size is larger than we expect. */
1374 if (flag_stack_check == GENERIC_STACK_CHECK)
1376 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1377 static int verbose_warned = 0;
1379 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1380 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1381 size += UNITS_PER_WORD;
1383 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1385 warning (0, "frame size too large for reliable stack checking");
1386 if (! verbose_warned)
1388 warning (0, "try reducing the number of local variables");
1394 /* Indicate that we no longer have known memory locations or constants. */
1395 if (reg_equiv_constant)
1396 free (reg_equiv_constant);
1397 if (reg_equiv_invariant)
1398 free (reg_equiv_invariant);
1399 reg_equiv_constant = 0;
1400 reg_equiv_invariant = 0;
1401 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1402 reg_equiv_memory_loc = 0;
1404 free (temp_pseudo_reg_arr);
1406 if (offsets_known_at)
1407 free (offsets_known_at);
1411 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1412 if (reg_equiv_alt_mem_list[i])
1413 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1414 free (reg_equiv_alt_mem_list);
1416 free (reg_equiv_mem);
1418 free (reg_equiv_address);
1419 free (reg_max_ref_width);
1420 free (reg_old_renumber);
1421 free (pseudo_previous_regs);
1422 free (pseudo_forbidden_regs);
1424 CLEAR_HARD_REG_SET (used_spill_regs);
1425 for (i = 0; i < n_spills; i++)
1426 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1428 /* Free all the insn_chain structures at once. */
1429 obstack_free (&reload_obstack, reload_startobj);
1430 unused_insn_chains = 0;
1431 fixup_abnormal_edges ();
1433 /* Replacing pseudos with their memory equivalents might have
1434 created shared rtx. Subsequent passes would get confused
1435 by this, so unshare everything here. */
1436 unshare_all_rtl_again (first);
1438 #ifdef STACK_BOUNDARY
1439 /* init_emit has set the alignment of the hard frame pointer
1440 to STACK_BOUNDARY. It is very likely no longer valid if
1441 the hard frame pointer was used for register allocation. */
1442 if (!frame_pointer_needed)
1443 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1449 /* Yet another special case. Unfortunately, reg-stack forces people to
1450 write incorrect clobbers in asm statements. These clobbers must not
1451 cause the register to appear in bad_spill_regs, otherwise we'll call
1452 fatal_insn later. We clear the corresponding regnos in the live
1453 register sets to avoid this.
1454 The whole thing is rather sick, I'm afraid. */
1457 maybe_fix_stack_asms (void)
1460 const char *constraints[MAX_RECOG_OPERANDS];
1461 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1462 struct insn_chain *chain;
1464 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1467 HARD_REG_SET clobbered, allowed;
1470 if (! INSN_P (chain->insn)
1471 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1473 pat = PATTERN (chain->insn);
1474 if (GET_CODE (pat) != PARALLEL)
1477 CLEAR_HARD_REG_SET (clobbered);
1478 CLEAR_HARD_REG_SET (allowed);
1480 /* First, make a mask of all stack regs that are clobbered. */
1481 for (i = 0; i < XVECLEN (pat, 0); i++)
1483 rtx t = XVECEXP (pat, 0, i);
1484 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1485 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1488 /* Get the operand values and constraints out of the insn. */
1489 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1490 constraints, operand_mode, NULL);
1492 /* For every operand, see what registers are allowed. */
1493 for (i = 0; i < noperands; i++)
1495 const char *p = constraints[i];
1496 /* For every alternative, we compute the class of registers allowed
1497 for reloading in CLS, and merge its contents into the reg set
1499 int cls = (int) NO_REGS;
1505 if (c == '\0' || c == ',' || c == '#')
1507 /* End of one alternative - mark the regs in the current
1508 class, and reset the class. */
1509 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1515 } while (c != '\0' && c != ',');
1523 case '=': case '+': case '*': case '%': case '?': case '!':
1524 case '0': case '1': case '2': case '3': case '4': case '<':
1525 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1526 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1527 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1528 case TARGET_MEM_CONSTRAINT:
1532 cls = (int) reg_class_subunion[cls]
1533 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1538 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1542 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1543 cls = (int) reg_class_subunion[cls]
1544 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1546 cls = (int) reg_class_subunion[cls]
1547 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1549 p += CONSTRAINT_LEN (c, p);
1552 /* Those of the registers which are clobbered, but allowed by the
1553 constraints, must be usable as reload registers. So clear them
1554 out of the life information. */
1555 AND_HARD_REG_SET (allowed, clobbered);
1556 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1557 if (TEST_HARD_REG_BIT (allowed, i))
1559 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1560 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1567 /* Copy the global variables n_reloads and rld into the corresponding elts
1570 copy_reloads (struct insn_chain *chain)
1572 chain->n_reloads = n_reloads;
1573 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1574 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1575 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1578 /* Walk the chain of insns, and determine for each whether it needs reloads
1579 and/or eliminations. Build the corresponding insns_need_reload list, and
1580 set something_needs_elimination as appropriate. */
1582 calculate_needs_all_insns (int global)
1584 struct insn_chain **pprev_reload = &insns_need_reload;
1585 struct insn_chain *chain, *next = 0;
1587 something_needs_elimination = 0;
1589 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1590 for (chain = reload_insn_chain; chain != 0; chain = next)
1592 rtx insn = chain->insn;
1596 /* Clear out the shortcuts. */
1597 chain->n_reloads = 0;
1598 chain->need_elim = 0;
1599 chain->need_reload = 0;
1600 chain->need_operand_change = 0;
1602 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1603 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1604 what effects this has on the known offsets at labels. */
1606 if (LABEL_P (insn) || JUMP_P (insn)
1607 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1608 set_label_offsets (insn, insn, 0);
1612 rtx old_body = PATTERN (insn);
1613 int old_code = INSN_CODE (insn);
1614 rtx old_notes = REG_NOTES (insn);
1615 int did_elimination = 0;
1616 int operands_changed = 0;
1617 rtx set = single_set (insn);
1619 /* Skip insns that only set an equivalence. */
1620 if (set && REG_P (SET_DEST (set))
1621 && reg_renumber[REGNO (SET_DEST (set))] < 0
1622 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1623 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1624 && reg_equiv_init[REGNO (SET_DEST (set))])
1627 /* If needed, eliminate any eliminable registers. */
1628 if (num_eliminable || num_eliminable_invariants)
1629 did_elimination = eliminate_regs_in_insn (insn, 0);
1631 /* Analyze the instruction. */
1632 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1633 global, spill_reg_order);
1635 /* If a no-op set needs more than one reload, this is likely
1636 to be something that needs input address reloads. We
1637 can't get rid of this cleanly later, and it is of no use
1638 anyway, so discard it now.
1639 We only do this when expensive_optimizations is enabled,
1640 since this complements reload inheritance / output
1641 reload deletion, and it can make debugging harder. */
1642 if (flag_expensive_optimizations && n_reloads > 1)
1644 rtx set = single_set (insn);
1647 ((SET_SRC (set) == SET_DEST (set)
1648 && REG_P (SET_SRC (set))
1649 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1650 || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1651 && reg_renumber[REGNO (SET_SRC (set))] < 0
1652 && reg_renumber[REGNO (SET_DEST (set))] < 0
1653 && reg_equiv_memory_loc[REGNO (SET_SRC (set))] != NULL
1654 && reg_equiv_memory_loc[REGNO (SET_DEST (set))] != NULL
1655 && rtx_equal_p (reg_equiv_memory_loc
1656 [REGNO (SET_SRC (set))],
1657 reg_equiv_memory_loc
1658 [REGNO (SET_DEST (set))]))))
1660 if (ira_conflicts_p)
1661 /* Inform IRA about the insn deletion. */
1662 ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1663 REGNO (SET_SRC (set)));
1665 /* Delete it from the reload chain. */
1667 chain->prev->next = next;
1669 reload_insn_chain = next;
1671 next->prev = chain->prev;
1672 chain->next = unused_insn_chains;
1673 unused_insn_chains = chain;
1678 update_eliminable_offsets ();
1680 /* Remember for later shortcuts which insns had any reloads or
1681 register eliminations. */
1682 chain->need_elim = did_elimination;
1683 chain->need_reload = n_reloads > 0;
1684 chain->need_operand_change = operands_changed;
1686 /* Discard any register replacements done. */
1687 if (did_elimination)
1689 obstack_free (&reload_obstack, reload_insn_firstobj);
1690 PATTERN (insn) = old_body;
1691 INSN_CODE (insn) = old_code;
1692 REG_NOTES (insn) = old_notes;
1693 something_needs_elimination = 1;
1696 something_needs_operands_changed |= operands_changed;
1700 copy_reloads (chain);
1701 *pprev_reload = chain;
1702 pprev_reload = &chain->next_need_reload;
1709 /* Comparison function for qsort to decide which of two reloads
1710 should be handled first. *P1 and *P2 are the reload numbers. */
1713 reload_reg_class_lower (const void *r1p, const void *r2p)
1715 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1718 /* Consider required reloads before optional ones. */
1719 t = rld[r1].optional - rld[r2].optional;
1723 /* Count all solitary classes before non-solitary ones. */
1724 t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1725 - (reg_class_size[(int) rld[r1].rclass] == 1));
1729 /* Aside from solitaires, consider all multi-reg groups first. */
1730 t = rld[r2].nregs - rld[r1].nregs;
1734 /* Consider reloads in order of increasing reg-class number. */
1735 t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1739 /* If reloads are equally urgent, sort by reload number,
1740 so that the results of qsort leave nothing to chance. */
1744 /* The cost of spilling each hard reg. */
1745 static int spill_cost[FIRST_PSEUDO_REGISTER];
1747 /* When spilling multiple hard registers, we use SPILL_COST for the first
1748 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1749 only the first hard reg for a multi-reg pseudo. */
1750 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1752 /* Map of hard regno to pseudo regno currently occupying the hard
1754 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1756 /* Update the spill cost arrays, considering that pseudo REG is live. */
1759 count_pseudo (int reg)
1761 int freq = REG_FREQ (reg);
1762 int r = reg_renumber[reg];
1765 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1766 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1767 /* Ignore spilled pseudo-registers which can be here only if IRA
1769 || (ira_conflicts_p && r < 0))
1772 SET_REGNO_REG_SET (&pseudos_counted, reg);
1774 gcc_assert (r >= 0);
1776 spill_add_cost[r] += freq;
1777 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1780 hard_regno_to_pseudo_regno[r + nregs] = reg;
1781 spill_cost[r + nregs] += freq;
1785 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1786 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1789 order_regs_for_reload (struct insn_chain *chain)
1792 HARD_REG_SET used_by_pseudos;
1793 HARD_REG_SET used_by_pseudos2;
1794 reg_set_iterator rsi;
1796 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1798 memset (spill_cost, 0, sizeof spill_cost);
1799 memset (spill_add_cost, 0, sizeof spill_add_cost);
1800 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1801 hard_regno_to_pseudo_regno[i] = -1;
1803 /* Count number of uses of each hard reg by pseudo regs allocated to it
1804 and then order them by decreasing use. First exclude hard registers
1805 that are live in or across this insn. */
1807 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1808 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1809 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1810 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1812 /* Now find out which pseudos are allocated to it, and update
1814 CLEAR_REG_SET (&pseudos_counted);
1816 EXECUTE_IF_SET_IN_REG_SET
1817 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1821 EXECUTE_IF_SET_IN_REG_SET
1822 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1826 CLEAR_REG_SET (&pseudos_counted);
1829 /* Vector of reload-numbers showing the order in which the reloads should
1831 static short reload_order[MAX_RELOADS];
1833 /* This is used to keep track of the spill regs used in one insn. */
1834 static HARD_REG_SET used_spill_regs_local;
1836 /* We decided to spill hard register SPILLED, which has a size of
1837 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1838 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1839 update SPILL_COST/SPILL_ADD_COST. */
1842 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1844 int freq = REG_FREQ (reg);
1845 int r = reg_renumber[reg];
1846 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1848 /* Ignore spilled pseudo-registers which can be here only if IRA is
1850 if ((ira_conflicts_p && r < 0)
1851 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1852 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1855 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1857 spill_add_cost[r] -= freq;
1860 hard_regno_to_pseudo_regno[r + nregs] = -1;
1861 spill_cost[r + nregs] -= freq;
1865 /* Find reload register to use for reload number ORDER. */
1868 find_reg (struct insn_chain *chain, int order)
1870 int rnum = reload_order[order];
1871 struct reload *rl = rld + rnum;
1872 int best_cost = INT_MAX;
1874 unsigned int i, j, n;
1876 HARD_REG_SET not_usable;
1877 HARD_REG_SET used_by_other_reload;
1878 reg_set_iterator rsi;
1879 static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1880 static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1882 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1883 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1884 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1886 CLEAR_HARD_REG_SET (used_by_other_reload);
1887 for (k = 0; k < order; k++)
1889 int other = reload_order[k];
1891 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1892 for (j = 0; j < rld[other].nregs; j++)
1893 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1896 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1898 #ifdef REG_ALLOC_ORDER
1899 unsigned int regno = reg_alloc_order[i];
1901 unsigned int regno = i;
1904 if (! TEST_HARD_REG_BIT (not_usable, regno)
1905 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1906 && HARD_REGNO_MODE_OK (regno, rl->mode))
1908 int this_cost = spill_cost[regno];
1910 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1912 for (j = 1; j < this_nregs; j++)
1914 this_cost += spill_add_cost[regno + j];
1915 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1916 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1922 if (ira_conflicts_p)
1924 /* Ask IRA to find a better pseudo-register for
1926 for (n = j = 0; j < this_nregs; j++)
1928 int r = hard_regno_to_pseudo_regno[regno + j];
1932 if (n == 0 || regno_pseudo_regs[n - 1] != r)
1933 regno_pseudo_regs[n++] = r;
1935 regno_pseudo_regs[n++] = -1;
1937 || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1938 best_regno_pseudo_regs,
1945 best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1946 if (regno_pseudo_regs[j] < 0)
1953 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1955 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1957 if (this_cost < best_cost
1958 /* Among registers with equal cost, prefer caller-saved ones, or
1959 use REG_ALLOC_ORDER if it is defined. */
1960 || (this_cost == best_cost
1961 #ifdef REG_ALLOC_ORDER
1962 && (inv_reg_alloc_order[regno]
1963 < inv_reg_alloc_order[best_reg])
1965 && call_used_regs[regno]
1966 && ! call_used_regs[best_reg]
1971 best_cost = this_cost;
1979 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1981 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1982 rl->regno = best_reg;
1984 EXECUTE_IF_SET_IN_REG_SET
1985 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1987 count_spilled_pseudo (best_reg, rl->nregs, j);
1990 EXECUTE_IF_SET_IN_REG_SET
1991 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1993 count_spilled_pseudo (best_reg, rl->nregs, j);
1996 for (i = 0; i < rl->nregs; i++)
1998 gcc_assert (spill_cost[best_reg + i] == 0);
1999 gcc_assert (spill_add_cost[best_reg + i] == 0);
2000 gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
2001 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
2006 /* Find more reload regs to satisfy the remaining need of an insn, which
2008 Do it by ascending class number, since otherwise a reg
2009 might be spilled for a big class and might fail to count
2010 for a smaller class even though it belongs to that class. */
2013 find_reload_regs (struct insn_chain *chain)
2017 /* In order to be certain of getting the registers we need,
2018 we must sort the reloads into order of increasing register class.
2019 Then our grabbing of reload registers will parallel the process
2020 that provided the reload registers. */
2021 for (i = 0; i < chain->n_reloads; i++)
2023 /* Show whether this reload already has a hard reg. */
2024 if (chain->rld[i].reg_rtx)
2026 int regno = REGNO (chain->rld[i].reg_rtx);
2027 chain->rld[i].regno = regno;
2029 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
2032 chain->rld[i].regno = -1;
2033 reload_order[i] = i;
2036 n_reloads = chain->n_reloads;
2037 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
2039 CLEAR_HARD_REG_SET (used_spill_regs_local);
2042 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
2044 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
2046 /* Compute the order of preference for hard registers to spill. */
2048 order_regs_for_reload (chain);
2050 for (i = 0; i < n_reloads; i++)
2052 int r = reload_order[i];
2054 /* Ignore reloads that got marked inoperative. */
2055 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2056 && ! rld[r].optional
2057 && rld[r].regno == -1)
2058 if (! find_reg (chain, i))
2061 fprintf (dump_file, "reload failure for reload %d\n", r);
2062 spill_failure (chain->insn, rld[r].rclass);
2068 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2069 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2071 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2075 select_reload_regs (void)
2077 struct insn_chain *chain;
2079 /* Try to satisfy the needs for each insn. */
2080 for (chain = insns_need_reload; chain != 0;
2081 chain = chain->next_need_reload)
2082 find_reload_regs (chain);
2085 /* Delete all insns that were inserted by emit_caller_save_insns during
2088 delete_caller_save_insns (void)
2090 struct insn_chain *c = reload_insn_chain;
2094 while (c != 0 && c->is_caller_save_insn)
2096 struct insn_chain *next = c->next;
2099 if (c == reload_insn_chain)
2100 reload_insn_chain = next;
2104 next->prev = c->prev;
2106 c->prev->next = next;
2107 c->next = unused_insn_chains;
2108 unused_insn_chains = c;
2116 /* Handle the failure to find a register to spill.
2117 INSN should be one of the insns which needed this particular spill reg. */
2120 spill_failure (rtx insn, enum reg_class rclass)
2122 if (asm_noperands (PATTERN (insn)) >= 0)
2123 error_for_asm (insn, "can't find a register in class %qs while "
2124 "reloading %<asm%>",
2125 reg_class_names[rclass]);
2128 error ("unable to find a register to spill in class %qs",
2129 reg_class_names[rclass]);
2133 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2134 debug_reload_to_stream (dump_file);
2136 fatal_insn ("this is the insn:", insn);
2140 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2141 data that is dead in INSN. */
2144 delete_dead_insn (rtx insn)
2146 rtx prev = prev_real_insn (insn);
2149 /* If the previous insn sets a register that dies in our insn, delete it
2151 if (prev && GET_CODE (PATTERN (prev)) == SET
2152 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2153 && reg_mentioned_p (prev_dest, PATTERN (insn))
2154 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2155 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2156 delete_dead_insn (prev);
2158 SET_INSN_DELETED (insn);
2161 /* Modify the home of pseudo-reg I.
2162 The new home is present in reg_renumber[I].
2164 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2165 or it may be -1, meaning there is none or it is not relevant.
2166 This is used so that all pseudos spilled from a given hard reg
2167 can share one stack slot. */
2170 alter_reg (int i, int from_reg, bool dont_share_p)
2172 /* When outputting an inline function, this can happen
2173 for a reg that isn't actually used. */
2174 if (regno_reg_rtx[i] == 0)
2177 /* If the reg got changed to a MEM at rtl-generation time,
2179 if (!REG_P (regno_reg_rtx[i]))
2182 /* Modify the reg-rtx to contain the new hard reg
2183 number or else to contain its pseudo reg number. */
2184 SET_REGNO (regno_reg_rtx[i],
2185 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2187 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2188 allocate a stack slot for it. */
2190 if (reg_renumber[i] < 0
2191 && REG_N_REFS (i) > 0
2192 && reg_equiv_constant[i] == 0
2193 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
2194 && reg_equiv_memory_loc[i] == 0)
2197 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2198 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2199 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2200 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2201 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2204 if (ira_conflicts_p)
2206 /* Mark the spill for IRA. */
2207 SET_REGNO_REG_SET (&spilled_pseudos, i);
2209 x = ira_reuse_stack_slot (i, inherent_size, total_size);
2215 /* Each pseudo reg has an inherent size which comes from its own mode,
2216 and a total size which provides room for paradoxical subregs
2217 which refer to the pseudo reg in wider modes.
2219 We can use a slot already allocated if it provides both
2220 enough inherent space and enough total space.
2221 Otherwise, we allocate a new slot, making sure that it has no less
2222 inherent space, and no less total space, then the previous slot. */
2223 else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2227 /* No known place to spill from => no slot to reuse. */
2228 x = assign_stack_local (mode, total_size,
2229 min_align > inherent_align
2230 || total_size > inherent_size ? -1 : 0);
2234 /* Cancel the big-endian correction done in assign_stack_local.
2235 Get the address of the beginning of the slot. This is so we
2236 can do a big-endian correction unconditionally below. */
2237 if (BYTES_BIG_ENDIAN)
2239 adjust = inherent_size - total_size;
2242 = adjust_address_nv (x, mode_for_size (total_size
2248 if (! dont_share_p && ira_conflicts_p)
2249 /* Inform IRA about allocation a new stack slot. */
2250 ira_mark_new_stack_slot (stack_slot, i, total_size);
2253 /* Reuse a stack slot if possible. */
2254 else if (spill_stack_slot[from_reg] != 0
2255 && spill_stack_slot_width[from_reg] >= total_size
2256 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2258 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2259 x = spill_stack_slot[from_reg];
2261 /* Allocate a bigger slot. */
2264 /* Compute maximum size needed, both for inherent size
2265 and for total size. */
2268 if (spill_stack_slot[from_reg])
2270 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2272 mode = GET_MODE (spill_stack_slot[from_reg]);
2273 if (spill_stack_slot_width[from_reg] > total_size)
2274 total_size = spill_stack_slot_width[from_reg];
2275 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2276 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2279 /* Make a slot with that size. */
2280 x = assign_stack_local (mode, total_size,
2281 min_align > inherent_align
2282 || total_size > inherent_size ? -1 : 0);
2285 /* Cancel the big-endian correction done in assign_stack_local.
2286 Get the address of the beginning of the slot. This is so we
2287 can do a big-endian correction unconditionally below. */
2288 if (BYTES_BIG_ENDIAN)
2290 adjust = GET_MODE_SIZE (mode) - total_size;
2293 = adjust_address_nv (x, mode_for_size (total_size
2299 spill_stack_slot[from_reg] = stack_slot;
2300 spill_stack_slot_width[from_reg] = total_size;
2303 /* On a big endian machine, the "address" of the slot
2304 is the address of the low part that fits its inherent mode. */
2305 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2306 adjust += (total_size - inherent_size);
2308 /* If we have any adjustment to make, or if the stack slot is the
2309 wrong mode, make a new stack slot. */
2310 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2312 /* Set all of the memory attributes as appropriate for a spill. */
2313 set_mem_attrs_for_spill (x);
2315 /* Save the stack slot for later. */
2316 reg_equiv_memory_loc[i] = x;
2320 /* Mark the slots in regs_ever_live for the hard regs used by
2321 pseudo-reg number REGNO, accessed in MODE. */
2324 mark_home_live_1 (int regno, enum machine_mode mode)
2328 i = reg_renumber[regno];
2331 lim = end_hard_regno (mode, i);
2333 df_set_regs_ever_live(i++, true);
2336 /* Mark the slots in regs_ever_live for the hard regs
2337 used by pseudo-reg number REGNO. */
2340 mark_home_live (int regno)
2342 if (reg_renumber[regno] >= 0)
2343 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2346 /* This function handles the tracking of elimination offsets around branches.
2348 X is a piece of RTL being scanned.
2350 INSN is the insn that it came from, if any.
2352 INITIAL_P is nonzero if we are to set the offset to be the initial
2353 offset and zero if we are setting the offset of the label to be the
2357 set_label_offsets (rtx x, rtx insn, int initial_p)
2359 enum rtx_code code = GET_CODE (x);
2362 struct elim_table *p;
2367 if (LABEL_REF_NONLOCAL_P (x))
2372 /* ... fall through ... */
2375 /* If we know nothing about this label, set the desired offsets. Note
2376 that this sets the offset at a label to be the offset before a label
2377 if we don't know anything about the label. This is not correct for
2378 the label after a BARRIER, but is the best guess we can make. If
2379 we guessed wrong, we will suppress an elimination that might have
2380 been possible had we been able to guess correctly. */
2382 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2384 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2385 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2386 = (initial_p ? reg_eliminate[i].initial_offset
2387 : reg_eliminate[i].offset);
2388 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2391 /* Otherwise, if this is the definition of a label and it is
2392 preceded by a BARRIER, set our offsets to the known offset of
2396 && (tem = prev_nonnote_insn (insn)) != 0
2398 set_offsets_for_label (insn);
2400 /* If neither of the above cases is true, compare each offset
2401 with those previously recorded and suppress any eliminations
2402 where the offsets disagree. */
2404 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2405 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2406 != (initial_p ? reg_eliminate[i].initial_offset
2407 : reg_eliminate[i].offset))
2408 reg_eliminate[i].can_eliminate = 0;
2413 set_label_offsets (PATTERN (insn), insn, initial_p);
2415 /* ... fall through ... */
2419 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2420 to indirectly and hence must have all eliminations at their
2422 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2423 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2424 set_label_offsets (XEXP (tem, 0), insn, 1);
2430 /* Each of the labels in the parallel or address vector must be
2431 at their initial offsets. We want the first field for PARALLEL
2432 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2434 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2435 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2440 /* We only care about setting PC. If the source is not RETURN,
2441 IF_THEN_ELSE, or a label, disable any eliminations not at
2442 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2443 isn't one of those possibilities. For branches to a label,
2444 call ourselves recursively.
2446 Note that this can disable elimination unnecessarily when we have
2447 a non-local goto since it will look like a non-constant jump to
2448 someplace in the current function. This isn't a significant
2449 problem since such jumps will normally be when all elimination
2450 pairs are back to their initial offsets. */
2452 if (SET_DEST (x) != pc_rtx)
2455 switch (GET_CODE (SET_SRC (x)))
2462 set_label_offsets (SET_SRC (x), insn, initial_p);
2466 tem = XEXP (SET_SRC (x), 1);
2467 if (GET_CODE (tem) == LABEL_REF)
2468 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2469 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2472 tem = XEXP (SET_SRC (x), 2);
2473 if (GET_CODE (tem) == LABEL_REF)
2474 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2475 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2483 /* If we reach here, all eliminations must be at their initial
2484 offset because we are doing a jump to a variable address. */
2485 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2486 if (p->offset != p->initial_offset)
2487 p->can_eliminate = 0;
2495 /* Scan X and replace any eliminable registers (such as fp) with a
2496 replacement (such as sp), plus an offset.
2498 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2499 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2500 MEM, we are allowed to replace a sum of a register and the constant zero
2501 with the register, which we cannot do outside a MEM. In addition, we need
2502 to record the fact that a register is referenced outside a MEM.
2504 If INSN is an insn, it is the insn containing X. If we replace a REG
2505 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2506 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2507 the REG is being modified.
2509 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2510 That's used when we eliminate in expressions stored in notes.
2511 This means, do not set ref_outside_mem even if the reference
2514 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2515 replacements done assuming all offsets are at their initial values. If
2516 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2517 encounter, return the actual location so that find_reloads will do
2518 the proper thing. */
2521 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2522 bool may_use_invariant)
2524 enum rtx_code code = GET_CODE (x);
2525 struct elim_table *ep;
2532 if (! current_function_decl)
2555 /* First handle the case where we encounter a bare register that
2556 is eliminable. Replace it with a PLUS. */
2557 if (regno < FIRST_PSEUDO_REGISTER)
2559 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2561 if (ep->from_rtx == x && ep->can_eliminate)
2562 return plus_constant (ep->to_rtx, ep->previous_offset);
2565 else if (reg_renumber && reg_renumber[regno] < 0
2566 && reg_equiv_invariant && reg_equiv_invariant[regno])
2568 if (may_use_invariant)
2569 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2570 mem_mode, insn, true);
2571 /* There exists at least one use of REGNO that cannot be
2572 eliminated. Prevent the defining insn from being deleted. */
2573 reg_equiv_init[regno] = NULL_RTX;
2574 alter_reg (regno, -1, true);
2578 /* You might think handling MINUS in a manner similar to PLUS is a
2579 good idea. It is not. It has been tried multiple times and every
2580 time the change has had to have been reverted.
2582 Other parts of reload know a PLUS is special (gen_reload for example)
2583 and require special code to handle code a reloaded PLUS operand.
2585 Also consider backends where the flags register is clobbered by a
2586 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2587 lea instruction comes to mind). If we try to reload a MINUS, we
2588 may kill the flags register that was holding a useful value.
2590 So, please before trying to handle MINUS, consider reload as a
2591 whole instead of this little section as well as the backend issues. */
2593 /* If this is the sum of an eliminable register and a constant, rework
2595 if (REG_P (XEXP (x, 0))
2596 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2597 && CONSTANT_P (XEXP (x, 1)))
2599 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2601 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2603 /* The only time we want to replace a PLUS with a REG (this
2604 occurs when the constant operand of the PLUS is the negative
2605 of the offset) is when we are inside a MEM. We won't want
2606 to do so at other times because that would change the
2607 structure of the insn in a way that reload can't handle.
2608 We special-case the commonest situation in
2609 eliminate_regs_in_insn, so just replace a PLUS with a
2610 PLUS here, unless inside a MEM. */
2611 if (mem_mode != 0 && CONST_INT_P (XEXP (x, 1))
2612 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2615 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2616 plus_constant (XEXP (x, 1),
2617 ep->previous_offset));
2620 /* If the register is not eliminable, we are done since the other
2621 operand is a constant. */
2625 /* If this is part of an address, we want to bring any constant to the
2626 outermost PLUS. We will do this by doing register replacement in
2627 our operands and seeing if a constant shows up in one of them.
2629 Note that there is no risk of modifying the structure of the insn,
2630 since we only get called for its operands, thus we are either
2631 modifying the address inside a MEM, or something like an address
2632 operand of a load-address insn. */
2635 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2636 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2638 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2640 /* If one side is a PLUS and the other side is a pseudo that
2641 didn't get a hard register but has a reg_equiv_constant,
2642 we must replace the constant here since it may no longer
2643 be in the position of any operand. */
2644 if (GET_CODE (new0) == PLUS && REG_P (new1)
2645 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2646 && reg_renumber[REGNO (new1)] < 0
2647 && reg_equiv_constant != 0
2648 && reg_equiv_constant[REGNO (new1)] != 0)
2649 new1 = reg_equiv_constant[REGNO (new1)];
2650 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2651 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2652 && reg_renumber[REGNO (new0)] < 0
2653 && reg_equiv_constant[REGNO (new0)] != 0)
2654 new0 = reg_equiv_constant[REGNO (new0)];
2656 new_rtx = form_sum (new0, new1);
2658 /* As above, if we are not inside a MEM we do not want to
2659 turn a PLUS into something else. We might try to do so here
2660 for an addition of 0 if we aren't optimizing. */
2661 if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2662 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2670 /* If this is the product of an eliminable register and a
2671 constant, apply the distribute law and move the constant out
2672 so that we have (plus (mult ..) ..). This is needed in order
2673 to keep load-address insns valid. This case is pathological.
2674 We ignore the possibility of overflow here. */
2675 if (REG_P (XEXP (x, 0))
2676 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2677 && CONST_INT_P (XEXP (x, 1)))
2678 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2680 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2683 /* Refs inside notes don't count for this purpose. */
2684 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2685 || GET_CODE (insn) == INSN_LIST)))
2686 ep->ref_outside_mem = 1;
2689 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2690 ep->previous_offset * INTVAL (XEXP (x, 1)));
2693 /* ... fall through ... */
2697 /* See comments before PLUS about handling MINUS. */
2699 case DIV: case UDIV:
2700 case MOD: case UMOD:
2701 case AND: case IOR: case XOR:
2702 case ROTATERT: case ROTATE:
2703 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2705 case GE: case GT: case GEU: case GTU:
2706 case LE: case LT: case LEU: case LTU:
2708 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2709 rtx new1 = XEXP (x, 1)
2710 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2712 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2713 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2718 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2721 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2722 if (new_rtx != XEXP (x, 0))
2724 /* If this is a REG_DEAD note, it is not valid anymore.
2725 Using the eliminated version could result in creating a
2726 REG_DEAD note for the stack or frame pointer. */
2727 if (REG_NOTE_KIND (x) == REG_DEAD)
2729 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2732 x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2736 /* ... fall through ... */
2739 /* Now do eliminations in the rest of the chain. If this was
2740 an EXPR_LIST, this might result in allocating more memory than is
2741 strictly needed, but it simplifies the code. */
2744 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2745 if (new_rtx != XEXP (x, 1))
2747 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2755 /* We do not support elimination of a register that is modified.
2756 elimination_effects has already make sure that this does not
2762 /* We do not support elimination of a register that is modified.
2763 elimination_effects has already make sure that this does not
2764 happen. The only remaining case we need to consider here is
2765 that the increment value may be an eliminable register. */
2766 if (GET_CODE (XEXP (x, 1)) == PLUS
2767 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2769 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2772 if (new_rtx != XEXP (XEXP (x, 1), 1))
2773 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2774 gen_rtx_PLUS (GET_MODE (x),
2775 XEXP (x, 0), new_rtx));
2779 case STRICT_LOW_PART:
2781 case SIGN_EXTEND: case ZERO_EXTEND:
2782 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2783 case FLOAT: case FIX:
2784 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2793 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2794 if (new_rtx != XEXP (x, 0))
2795 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2799 /* Similar to above processing, but preserve SUBREG_BYTE.
2800 Convert (subreg (mem)) to (mem) if not paradoxical.
2801 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2802 pseudo didn't get a hard reg, we must replace this with the
2803 eliminated version of the memory location because push_reload
2804 may do the replacement in certain circumstances. */
2805 if (REG_P (SUBREG_REG (x))
2806 && (GET_MODE_SIZE (GET_MODE (x))
2807 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2808 && reg_equiv_memory_loc != 0
2809 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2811 new_rtx = SUBREG_REG (x);
2814 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2816 if (new_rtx != SUBREG_REG (x))
2818 int x_size = GET_MODE_SIZE (GET_MODE (x));
2819 int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2822 && ((x_size < new_size
2823 #ifdef WORD_REGISTER_OPERATIONS
2824 /* On these machines, combine can create rtl of the form
2825 (set (subreg:m1 (reg:m2 R) 0) ...)
2826 where m1 < m2, and expects something interesting to
2827 happen to the entire word. Moreover, it will use the
2828 (reg:m2 R) later, expecting all bits to be preserved.
2829 So if the number of words is the same, preserve the
2830 subreg so that push_reload can see it. */
2831 && ! ((x_size - 1) / UNITS_PER_WORD
2832 == (new_size -1 ) / UNITS_PER_WORD)
2835 || x_size == new_size)
2837 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2839 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2845 /* Our only special processing is to pass the mode of the MEM to our
2846 recursive call and copy the flags. While we are here, handle this
2847 case more efficiently. */
2849 replace_equiv_address_nv (x,
2850 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2854 /* Handle insn_list USE that a call to a pure function may generate. */
2855 new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false);
2856 if (new_rtx != XEXP (x, 0))
2857 return gen_rtx_USE (GET_MODE (x), new_rtx);
2869 /* Process each of our operands recursively. If any have changed, make a
2871 fmt = GET_RTX_FORMAT (code);
2872 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2876 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2877 if (new_rtx != XEXP (x, i) && ! copied)
2879 x = shallow_copy_rtx (x);
2882 XEXP (x, i) = new_rtx;
2884 else if (*fmt == 'E')
2887 for (j = 0; j < XVECLEN (x, i); j++)
2889 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2890 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2892 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2896 x = shallow_copy_rtx (x);
2899 XVEC (x, i) = new_v;
2902 XVECEXP (x, i, j) = new_rtx;
2911 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2913 return eliminate_regs_1 (x, mem_mode, insn, false);
2916 /* Scan rtx X for modifications of elimination target registers. Update
2917 the table of eliminables to reflect the changed state. MEM_MODE is
2918 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2921 elimination_effects (rtx x, enum machine_mode mem_mode)
2923 enum rtx_code code = GET_CODE (x);
2924 struct elim_table *ep;
2949 /* First handle the case where we encounter a bare register that
2950 is eliminable. Replace it with a PLUS. */
2951 if (regno < FIRST_PSEUDO_REGISTER)
2953 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2955 if (ep->from_rtx == x && ep->can_eliminate)
2958 ep->ref_outside_mem = 1;
2963 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2964 && reg_equiv_constant[regno]
2965 && ! function_invariant_p (reg_equiv_constant[regno]))
2966 elimination_effects (reg_equiv_constant[regno], mem_mode);
2975 /* If we modify the source of an elimination rule, disable it. */
2976 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2977 if (ep->from_rtx == XEXP (x, 0))
2978 ep->can_eliminate = 0;
2980 /* If we modify the target of an elimination rule by adding a constant,
2981 update its offset. If we modify the target in any other way, we'll
2982 have to disable the rule as well. */
2983 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2984 if (ep->to_rtx == XEXP (x, 0))
2986 int size = GET_MODE_SIZE (mem_mode);
2988 /* If more bytes than MEM_MODE are pushed, account for them. */
2989 #ifdef PUSH_ROUNDING
2990 if (ep->to_rtx == stack_pointer_rtx)
2991 size = PUSH_ROUNDING (size);
2993 if (code == PRE_DEC || code == POST_DEC)
2995 else if (code == PRE_INC || code == POST_INC)
2997 else if (code == PRE_MODIFY || code == POST_MODIFY)
2999 if (GET_CODE (XEXP (x, 1)) == PLUS
3000 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
3001 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
3002 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
3004 ep->can_eliminate = 0;
3008 /* These two aren't unary operators. */
3009 if (code == POST_MODIFY || code == PRE_MODIFY)
3012 /* Fall through to generic unary operation case. */
3013 case STRICT_LOW_PART:
3015 case SIGN_EXTEND: case ZERO_EXTEND:
3016 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3017 case FLOAT: case FIX:
3018 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3027 elimination_effects (XEXP (x, 0), mem_mode);
3031 if (REG_P (SUBREG_REG (x))
3032 && (GET_MODE_SIZE (GET_MODE (x))
3033 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3034 && reg_equiv_memory_loc != 0
3035 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
3038 elimination_effects (SUBREG_REG (x), mem_mode);
3042 /* If using a register that is the source of an eliminate we still
3043 think can be performed, note it cannot be performed since we don't
3044 know how this register is used. */
3045 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3046 if (ep->from_rtx == XEXP (x, 0))
3047 ep->can_eliminate = 0;
3049 elimination_effects (XEXP (x, 0), mem_mode);
3053 /* If clobbering a register that is the replacement register for an
3054 elimination we still think can be performed, note that it cannot
3055 be performed. Otherwise, we need not be concerned about it. */
3056 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3057 if (ep->to_rtx == XEXP (x, 0))
3058 ep->can_eliminate = 0;
3060 elimination_effects (XEXP (x, 0), mem_mode);
3064 /* Check for setting a register that we know about. */
3065 if (REG_P (SET_DEST (x)))
3067 /* See if this is setting the replacement register for an
3070 If DEST is the hard frame pointer, we do nothing because we
3071 assume that all assignments to the frame pointer are for
3072 non-local gotos and are being done at a time when they are valid
3073 and do not disturb anything else. Some machines want to
3074 eliminate a fake argument pointer (or even a fake frame pointer)
3075 with either the real frame or the stack pointer. Assignments to
3076 the hard frame pointer must not prevent this elimination. */
3078 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3080 if (ep->to_rtx == SET_DEST (x)
3081 && SET_DEST (x) != hard_frame_pointer_rtx)
3083 /* If it is being incremented, adjust the offset. Otherwise,
3084 this elimination can't be done. */
3085 rtx src = SET_SRC (x);
3087 if (GET_CODE (src) == PLUS
3088 && XEXP (src, 0) == SET_DEST (x)
3089 && CONST_INT_P (XEXP (src, 1)))
3090 ep->offset -= INTVAL (XEXP (src, 1));
3092 ep->can_eliminate = 0;
3096 elimination_effects (SET_DEST (x), VOIDmode);
3097 elimination_effects (SET_SRC (x), VOIDmode);
3101 /* Our only special processing is to pass the mode of the MEM to our
3103 elimination_effects (XEXP (x, 0), GET_MODE (x));
3110 fmt = GET_RTX_FORMAT (code);
3111 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3114 elimination_effects (XEXP (x, i), mem_mode);
3115 else if (*fmt == 'E')
3116 for (j = 0; j < XVECLEN (x, i); j++)
3117 elimination_effects (XVECEXP (x, i, j), mem_mode);
3121 /* Descend through rtx X and verify that no references to eliminable registers
3122 remain. If any do remain, mark the involved register as not
3126 check_eliminable_occurrences (rtx x)
3135 code = GET_CODE (x);
3137 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3139 struct elim_table *ep;
3141 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3142 if (ep->from_rtx == x)
3143 ep->can_eliminate = 0;
3147 fmt = GET_RTX_FORMAT (code);
3148 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3151 check_eliminable_occurrences (XEXP (x, i));
3152 else if (*fmt == 'E')
3155 for (j = 0; j < XVECLEN (x, i); j++)
3156 check_eliminable_occurrences (XVECEXP (x, i, j));
3161 /* Scan INSN and eliminate all eliminable registers in it.
3163 If REPLACE is nonzero, do the replacement destructively. Also
3164 delete the insn as dead it if it is setting an eliminable register.
3166 If REPLACE is zero, do all our allocations in reload_obstack.
3168 If no eliminations were done and this insn doesn't require any elimination
3169 processing (these are not identical conditions: it might be updating sp,
3170 but not referencing fp; this needs to be seen during reload_as_needed so
3171 that the offset between fp and sp can be taken into consideration), zero
3172 is returned. Otherwise, 1 is returned. */
3175 eliminate_regs_in_insn (rtx insn, int replace)
3177 int icode = recog_memoized (insn);
3178 rtx old_body = PATTERN (insn);
3179 int insn_is_asm = asm_noperands (old_body) >= 0;
3180 rtx old_set = single_set (insn);
3184 rtx substed_operand[MAX_RECOG_OPERANDS];
3185 rtx orig_operand[MAX_RECOG_OPERANDS];
3186 struct elim_table *ep;
3187 rtx plus_src, plus_cst_src;
3189 if (! insn_is_asm && icode < 0)
3191 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3192 || GET_CODE (PATTERN (insn)) == CLOBBER
3193 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3194 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3195 || GET_CODE (PATTERN (insn)) == ASM_INPUT
3196 || DEBUG_INSN_P (insn));
3200 if (old_set != 0 && REG_P (SET_DEST (old_set))
3201 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3203 /* Check for setting an eliminable register. */
3204 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3205 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3207 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3208 /* If this is setting the frame pointer register to the
3209 hardware frame pointer register and this is an elimination
3210 that will be done (tested above), this insn is really
3211 adjusting the frame pointer downward to compensate for
3212 the adjustment done before a nonlocal goto. */
3213 if (ep->from == FRAME_POINTER_REGNUM
3214 && ep->to == HARD_FRAME_POINTER_REGNUM)
3216 rtx base = SET_SRC (old_set);
3217 rtx base_insn = insn;
3218 HOST_WIDE_INT offset = 0;
3220 while (base != ep->to_rtx)
3222 rtx prev_insn, prev_set;
3224 if (GET_CODE (base) == PLUS
3225 && CONST_INT_P (XEXP (base, 1)))
3227 offset += INTVAL (XEXP (base, 1));
3228 base = XEXP (base, 0);
3230 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3231 && (prev_set = single_set (prev_insn)) != 0
3232 && rtx_equal_p (SET_DEST (prev_set), base))
3234 base = SET_SRC (prev_set);
3235 base_insn = prev_insn;
3241 if (base == ep->to_rtx)
3244 = plus_constant (ep->to_rtx, offset - ep->offset);
3246 new_body = old_body;
3249 new_body = copy_insn (old_body);
3250 if (REG_NOTES (insn))
3251 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3253 PATTERN (insn) = new_body;
3254 old_set = single_set (insn);
3256 /* First see if this insn remains valid when we
3257 make the change. If not, keep the INSN_CODE
3258 the same and let reload fit it up. */
3259 validate_change (insn, &SET_SRC (old_set), src, 1);
3260 validate_change (insn, &SET_DEST (old_set),
3262 if (! apply_change_group ())
3264 SET_SRC (old_set) = src;
3265 SET_DEST (old_set) = ep->to_rtx;
3274 /* In this case this insn isn't serving a useful purpose. We
3275 will delete it in reload_as_needed once we know that this
3276 elimination is, in fact, being done.
3278 If REPLACE isn't set, we can't delete this insn, but needn't
3279 process it since it won't be used unless something changes. */
3282 delete_dead_insn (insn);
3290 /* We allow one special case which happens to work on all machines we
3291 currently support: a single set with the source or a REG_EQUAL
3292 note being a PLUS of an eliminable register and a constant. */
3293 plus_src = plus_cst_src = 0;
3294 if (old_set && REG_P (SET_DEST (old_set)))
3296 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3297 plus_src = SET_SRC (old_set);
3298 /* First see if the source is of the form (plus (...) CST). */
3300 && CONST_INT_P (XEXP (plus_src, 1)))
3301 plus_cst_src = plus_src;
3302 else if (REG_P (SET_SRC (old_set))
3305 /* Otherwise, see if we have a REG_EQUAL note of the form
3306 (plus (...) CST). */
3308 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3310 if ((REG_NOTE_KIND (links) == REG_EQUAL
3311 || REG_NOTE_KIND (links) == REG_EQUIV)
3312 && GET_CODE (XEXP (links, 0)) == PLUS
3313 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3315 plus_cst_src = XEXP (links, 0);
3321 /* Check that the first operand of the PLUS is a hard reg or
3322 the lowpart subreg of one. */
3325 rtx reg = XEXP (plus_cst_src, 0);
3326 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3327 reg = SUBREG_REG (reg);
3329 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3335 rtx reg = XEXP (plus_cst_src, 0);
3336 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3338 if (GET_CODE (reg) == SUBREG)
3339 reg = SUBREG_REG (reg);
3341 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3342 if (ep->from_rtx == reg && ep->can_eliminate)
3344 rtx to_rtx = ep->to_rtx;
3345 offset += ep->offset;
3346 offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3348 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3349 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3351 /* If we have a nonzero offset, and the source is already
3352 a simple REG, the following transformation would
3353 increase the cost of the insn by replacing a simple REG
3354 with (plus (reg sp) CST). So try only when we already
3355 had a PLUS before. */
3356 if (offset == 0 || plus_src)
3358 rtx new_src = plus_constant (to_rtx, offset);
3360 new_body = old_body;
3363 new_body = copy_insn (old_body);
3364 if (REG_NOTES (insn))
3365 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3367 PATTERN (insn) = new_body;
3368 old_set = single_set (insn);
3370 /* First see if this insn remains valid when we make the
3371 change. If not, try to replace the whole pattern with
3372 a simple set (this may help if the original insn was a
3373 PARALLEL that was only recognized as single_set due to
3374 REG_UNUSED notes). If this isn't valid either, keep
3375 the INSN_CODE the same and let reload fix it up. */
3376 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3378 rtx new_pat = gen_rtx_SET (VOIDmode,
3379 SET_DEST (old_set), new_src);
3381 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3382 SET_SRC (old_set) = new_src;
3389 /* This can't have an effect on elimination offsets, so skip right
3395 /* Determine the effects of this insn on elimination offsets. */
3396 elimination_effects (old_body, VOIDmode);
3398 /* Eliminate all eliminable registers occurring in operands that
3399 can be handled by reload. */
3400 extract_insn (insn);
3401 for (i = 0; i < recog_data.n_operands; i++)
3403 orig_operand[i] = recog_data.operand[i];
3404 substed_operand[i] = recog_data.operand[i];
3406 /* For an asm statement, every operand is eliminable. */
3407 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3409 bool is_set_src, in_plus;
3411 /* Check for setting a register that we know about. */
3412 if (recog_data.operand_type[i] != OP_IN
3413 && REG_P (orig_operand[i]))
3415 /* If we are assigning to a register that can be eliminated, it
3416 must be as part of a PARALLEL, since the code above handles
3417 single SETs. We must indicate that we can no longer
3418 eliminate this reg. */
3419 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3421 if (ep->from_rtx == orig_operand[i])
3422 ep->can_eliminate = 0;
3425 /* Companion to the above plus substitution, we can allow
3426 invariants as the source of a plain move. */
3428 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3432 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3433 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3437 = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3438 replace ? insn : NULL_RTX,
3439 is_set_src || in_plus);
3440 if (substed_operand[i] != orig_operand[i])
3442 /* Terminate the search in check_eliminable_occurrences at
3444 *recog_data.operand_loc[i] = 0;
3446 /* If an output operand changed from a REG to a MEM and INSN is an
3447 insn, write a CLOBBER insn. */
3448 if (recog_data.operand_type[i] != OP_IN
3449 && REG_P (orig_operand[i])
3450 && MEM_P (substed_operand[i])
3452 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3456 for (i = 0; i < recog_data.n_dups; i++)
3457 *recog_data.dup_loc[i]
3458 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3460 /* If any eliminable remain, they aren't eliminable anymore. */
3461 check_eliminable_occurrences (old_body);
3463 /* Substitute the operands; the new values are in the substed_operand
3465 for (i = 0; i < recog_data.n_operands; i++)
3466 *recog_data.operand_loc[i] = substed_operand[i];
3467 for (i = 0; i < recog_data.n_dups; i++)
3468 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3470 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3471 re-recognize the insn. We do this in case we had a simple addition
3472 but now can do this as a load-address. This saves an insn in this
3474 If re-recognition fails, the old insn code number will still be used,
3475 and some register operands may have changed into PLUS expressions.
3476 These will be handled by find_reloads by loading them into a register
3481 /* If we aren't replacing things permanently and we changed something,
3482 make another copy to ensure that all the RTL is new. Otherwise
3483 things can go wrong if find_reload swaps commutative operands
3484 and one is inside RTL that has been copied while the other is not. */
3485 new_body = old_body;
3488 new_body = copy_insn (old_body);
3489 if (REG_NOTES (insn))
3490 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3492 PATTERN (insn) = new_body;
3494 /* If we had a move insn but now we don't, rerecognize it. This will
3495 cause spurious re-recognition if the old move had a PARALLEL since
3496 the new one still will, but we can't call single_set without
3497 having put NEW_BODY into the insn and the re-recognition won't
3498 hurt in this rare case. */
3499 /* ??? Why this huge if statement - why don't we just rerecognize the
3503 && ((REG_P (SET_SRC (old_set))
3504 && (GET_CODE (new_body) != SET
3505 || !REG_P (SET_SRC (new_body))))
3506 /* If this was a load from or store to memory, compare
3507 the MEM in recog_data.operand to the one in the insn.
3508 If they are not equal, then rerecognize the insn. */
3510 && ((MEM_P (SET_SRC (old_set))
3511 && SET_SRC (old_set) != recog_data.operand[1])
3512 || (MEM_P (SET_DEST (old_set))
3513 && SET_DEST (old_set) != recog_data.operand[0])))
3514 /* If this was an add insn before, rerecognize. */
3515 || GET_CODE (SET_SRC (old_set)) == PLUS))
3517 int new_icode = recog (PATTERN (insn), insn, 0);
3519 INSN_CODE (insn) = new_icode;
3523 /* Restore the old body. If there were any changes to it, we made a copy
3524 of it while the changes were still in place, so we'll correctly return
3525 a modified insn below. */
3528 /* Restore the old body. */
3529 for (i = 0; i < recog_data.n_operands; i++)
3530 *recog_data.operand_loc[i] = orig_operand[i];
3531 for (i = 0; i < recog_data.n_dups; i++)
3532 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3535 /* Update all elimination pairs to reflect the status after the current
3536 insn. The changes we make were determined by the earlier call to
3537 elimination_effects.
3539 We also detect cases where register elimination cannot be done,
3540 namely, if a register would be both changed and referenced outside a MEM
3541 in the resulting insn since such an insn is often undefined and, even if
3542 not, we cannot know what meaning will be given to it. Note that it is
3543 valid to have a register used in an address in an insn that changes it
3544 (presumably with a pre- or post-increment or decrement).
3546 If anything changes, return nonzero. */
3548 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3550 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3551 ep->can_eliminate = 0;
3553 ep->ref_outside_mem = 0;
3555 if (ep->previous_offset != ep->offset)
3560 /* If we changed something, perform elimination in REG_NOTES. This is
3561 needed even when REPLACE is zero because a REG_DEAD note might refer
3562 to a register that we eliminate and could cause a different number
3563 of spill registers to be needed in the final reload pass than in
3565 if (val && REG_NOTES (insn) != 0)
3567 = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true);
3572 /* Loop through all elimination pairs.
3573 Recalculate the number not at initial offset.
3575 Compute the maximum offset (minimum offset if the stack does not
3576 grow downward) for each elimination pair. */
3579 update_eliminable_offsets (void)
3581 struct elim_table *ep;
3583 num_not_at_initial_offset = 0;
3584 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3586 ep->previous_offset = ep->offset;
3587 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3588 num_not_at_initial_offset++;
3592 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3593 replacement we currently believe is valid, mark it as not eliminable if X
3594 modifies DEST in any way other than by adding a constant integer to it.
3596 If DEST is the frame pointer, we do nothing because we assume that
3597 all assignments to the hard frame pointer are nonlocal gotos and are being
3598 done at a time when they are valid and do not disturb anything else.
3599 Some machines want to eliminate a fake argument pointer with either the
3600 frame or stack pointer. Assignments to the hard frame pointer must not
3601 prevent this elimination.
3603 Called via note_stores from reload before starting its passes to scan
3604 the insns of the function. */
3607 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3611 /* A SUBREG of a hard register here is just changing its mode. We should
3612 not see a SUBREG of an eliminable hard register, but check just in
3614 if (GET_CODE (dest) == SUBREG)
3615 dest = SUBREG_REG (dest);
3617 if (dest == hard_frame_pointer_rtx)
3620 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3621 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3622 && (GET_CODE (x) != SET
3623 || GET_CODE (SET_SRC (x)) != PLUS
3624 || XEXP (SET_SRC (x), 0) != dest
3625 || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
3627 reg_eliminate[i].can_eliminate_previous
3628 = reg_eliminate[i].can_eliminate = 0;
3633 /* Verify that the initial elimination offsets did not change since the
3634 last call to set_initial_elim_offsets. This is used to catch cases
3635 where something illegal happened during reload_as_needed that could
3636 cause incorrect code to be generated if we did not check for it. */
3639 verify_initial_elim_offsets (void)
3643 if (!num_eliminable)
3646 #ifdef ELIMINABLE_REGS
3648 struct elim_table *ep;
3650 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3652 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3653 if (t != ep->initial_offset)
3658 INITIAL_FRAME_POINTER_OFFSET (t);
3659 if (t != reg_eliminate[0].initial_offset)
3666 /* Reset all offsets on eliminable registers to their initial values. */
3669 set_initial_elim_offsets (void)
3671 struct elim_table *ep = reg_eliminate;
3673 #ifdef ELIMINABLE_REGS
3674 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3676 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3677 ep->previous_offset = ep->offset = ep->initial_offset;
3680 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3681 ep->previous_offset = ep->offset = ep->initial_offset;
3684 num_not_at_initial_offset = 0;
3687 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3690 set_initial_eh_label_offset (rtx label)
3692 set_label_offsets (label, NULL_RTX, 1);
3695 /* Initialize the known label offsets.
3696 Set a known offset for each forced label to be at the initial offset
3697 of each elimination. We do this because we assume that all
3698 computed jumps occur from a location where each elimination is
3699 at its initial offset.
3700 For all other labels, show that we don't know the offsets. */
3703 set_initial_label_offsets (void)
3706 memset (offsets_known_at, 0, num_labels);
3708 for (x = forced_labels; x; x = XEXP (x, 1))
3710 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3712 for_each_eh_label (set_initial_eh_label_offset);
3715 /* Set all elimination offsets to the known values for the code label given
3719 set_offsets_for_label (rtx insn)
3722 int label_nr = CODE_LABEL_NUMBER (insn);
3723 struct elim_table *ep;
3725 num_not_at_initial_offset = 0;
3726 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3728 ep->offset = ep->previous_offset
3729 = offsets_at[label_nr - first_label_num][i];
3730 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3731 num_not_at_initial_offset++;
3735 /* See if anything that happened changes which eliminations are valid.
3736 For example, on the SPARC, whether or not the frame pointer can
3737 be eliminated can depend on what registers have been used. We need
3738 not check some conditions again (such as flag_omit_frame_pointer)
3739 since they can't have changed. */
3742 update_eliminables (HARD_REG_SET *pset)
3744 int previous_frame_pointer_needed = frame_pointer_needed;
3745 struct elim_table *ep;
3747 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3748 if ((ep->from == HARD_FRAME_POINTER_REGNUM
3749 && targetm.frame_pointer_required ())
3750 #ifdef ELIMINABLE_REGS
3751 || ! targetm.can_eliminate (ep->from, ep->to)
3754 ep->can_eliminate = 0;
3756 /* Look for the case where we have discovered that we can't replace
3757 register A with register B and that means that we will now be
3758 trying to replace register A with register C. This means we can
3759 no longer replace register C with register B and we need to disable
3760 such an elimination, if it exists. This occurs often with A == ap,
3761 B == sp, and C == fp. */
3763 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3765 struct elim_table *op;
3768 if (! ep->can_eliminate && ep->can_eliminate_previous)
3770 /* Find the current elimination for ep->from, if there is a
3772 for (op = reg_eliminate;
3773 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3774 if (op->from == ep->from && op->can_eliminate)
3780 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3782 for (op = reg_eliminate;
3783 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3784 if (op->from == new_to && op->to == ep->to)
3785 op->can_eliminate = 0;
3789 /* See if any registers that we thought we could eliminate the previous
3790 time are no longer eliminable. If so, something has changed and we
3791 must spill the register. Also, recompute the number of eliminable
3792 registers and see if the frame pointer is needed; it is if there is
3793 no elimination of the frame pointer that we can perform. */
3795 frame_pointer_needed = 1;
3796 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3798 if (ep->can_eliminate
3799 && ep->from == FRAME_POINTER_REGNUM
3800 && ep->to != HARD_FRAME_POINTER_REGNUM
3801 && (! SUPPORTS_STACK_ALIGNMENT
3802 || ! crtl->stack_realign_needed))
3803 frame_pointer_needed = 0;
3805 if (! ep->can_eliminate && ep->can_eliminate_previous)
3807 ep->can_eliminate_previous = 0;
3808 SET_HARD_REG_BIT (*pset, ep->from);
3813 /* If we didn't need a frame pointer last time, but we do now, spill
3814 the hard frame pointer. */
3815 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3816 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3819 /* Return true if X is used as the target register of an elimination. */
3822 elimination_target_reg_p (rtx x)
3824 struct elim_table *ep;
3826 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3827 if (ep->to_rtx == x && ep->can_eliminate)
3833 /* Initialize the table of registers to eliminate.
3834 Pre-condition: global flag frame_pointer_needed has been set before
3835 calling this function. */
3838 init_elim_table (void)
3840 struct elim_table *ep;
3841 #ifdef ELIMINABLE_REGS
3842 const struct elim_table_1 *ep1;
3846 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
3850 #ifdef ELIMINABLE_REGS
3851 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3852 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3854 ep->from = ep1->from;
3856 ep->can_eliminate = ep->can_eliminate_previous
3857 = (targetm.can_eliminate (ep->from, ep->to)
3858 && ! (ep->to == STACK_POINTER_REGNUM
3859 && frame_pointer_needed
3860 && (! SUPPORTS_STACK_ALIGNMENT
3861 || ! stack_realign_fp)));
3864 reg_eliminate[0].from = reg_eliminate_1[0].from;
3865 reg_eliminate[0].to = reg_eliminate_1[0].to;
3866 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3867 = ! frame_pointer_needed;
3870 /* Count the number of eliminable registers and build the FROM and TO
3871 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3872 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3873 We depend on this. */
3874 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3876 num_eliminable += ep->can_eliminate;
3877 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3878 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3882 /* Kick all pseudos out of hard register REGNO.
3884 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3885 because we found we can't eliminate some register. In the case, no pseudos
3886 are allowed to be in the register, even if they are only in a block that
3887 doesn't require spill registers, unlike the case when we are spilling this
3888 hard reg to produce another spill register.
3890 Return nonzero if any pseudos needed to be kicked out. */
3893 spill_hard_reg (unsigned int regno, int cant_eliminate)
3899 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3900 df_set_regs_ever_live (regno, true);
3903 /* Spill every pseudo reg that was allocated to this reg
3904 or to something that overlaps this reg. */
3906 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3907 if (reg_renumber[i] >= 0
3908 && (unsigned int) reg_renumber[i] <= regno
3909 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
3910 SET_REGNO_REG_SET (&spilled_pseudos, i);
3913 /* After find_reload_regs has been run for all insn that need reloads,
3914 and/or spill_hard_regs was called, this function is used to actually
3915 spill pseudo registers and try to reallocate them. It also sets up the
3916 spill_regs array for use by choose_reload_regs. */
3919 finish_spills (int global)
3921 struct insn_chain *chain;
3922 int something_changed = 0;
3924 reg_set_iterator rsi;
3926 /* Build the spill_regs array for the function. */
3927 /* If there are some registers still to eliminate and one of the spill regs
3928 wasn't ever used before, additional stack space may have to be
3929 allocated to store this register. Thus, we may have changed the offset
3930 between the stack and frame pointers, so mark that something has changed.
3932 One might think that we need only set VAL to 1 if this is a call-used
3933 register. However, the set of registers that must be saved by the
3934 prologue is not identical to the call-used set. For example, the
3935 register used by the call insn for the return PC is a call-used register,
3936 but must be saved by the prologue. */
3939 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3940 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3942 spill_reg_order[i] = n_spills;
3943 spill_regs[n_spills++] = i;
3944 if (num_eliminable && ! df_regs_ever_live_p (i))
3945 something_changed = 1;
3946 df_set_regs_ever_live (i, true);
3949 spill_reg_order[i] = -1;
3951 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3952 if (! ira_conflicts_p || reg_renumber[i] >= 0)
3954 /* Record the current hard register the pseudo is allocated to
3955 in pseudo_previous_regs so we avoid reallocating it to the
3956 same hard reg in a later pass. */
3957 gcc_assert (reg_renumber[i] >= 0);
3959 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3960 /* Mark it as no longer having a hard register home. */
3961 reg_renumber[i] = -1;
3962 if (ira_conflicts_p)
3963 /* Inform IRA about the change. */
3964 ira_mark_allocation_change (i);
3965 /* We will need to scan everything again. */
3966 something_changed = 1;
3969 /* Retry global register allocation if possible. */
3970 if (global && ira_conflicts_p)
3974 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3975 /* For every insn that needs reloads, set the registers used as spill
3976 regs in pseudo_forbidden_regs for every pseudo live across the
3978 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3980 EXECUTE_IF_SET_IN_REG_SET
3981 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3983 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3984 chain->used_spill_regs);
3986 EXECUTE_IF_SET_IN_REG_SET
3987 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3989 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3990 chain->used_spill_regs);
3994 /* Retry allocating the pseudos spilled in IRA and the
3995 reload. For each reg, merge the various reg sets that
3996 indicate which hard regs can't be used, and call
3997 ira_reassign_pseudos. */
3998 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
3999 if (reg_old_renumber[i] != reg_renumber[i])
4001 if (reg_renumber[i] < 0)
4002 temp_pseudo_reg_arr[n++] = i;
4004 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4006 if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4007 bad_spill_regs_global,
4008 pseudo_forbidden_regs, pseudo_previous_regs,
4010 something_changed = 1;
4012 /* Fix up the register information in the insn chain.
4013 This involves deleting those of the spilled pseudos which did not get
4014 a new hard register home from the live_{before,after} sets. */
4015 for (chain = reload_insn_chain; chain; chain = chain->next)
4017 HARD_REG_SET used_by_pseudos;
4018 HARD_REG_SET used_by_pseudos2;
4020 if (! ira_conflicts_p)
4022 /* Don't do it for IRA because IRA and the reload still can
4023 assign hard registers to the spilled pseudos on next
4024 reload iterations. */
4025 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4026 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4028 /* Mark any unallocated hard regs as available for spills. That
4029 makes inheritance work somewhat better. */
4030 if (chain->need_reload)
4032 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4033 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4034 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4036 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4037 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4038 /* Value of chain->used_spill_regs from previous iteration
4039 may be not included in the value calculated here because
4040 of possible removing caller-saves insns (see function
4041 delete_caller_save_insns. */
4042 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4043 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4047 CLEAR_REG_SET (&changed_allocation_pseudos);
4048 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4049 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4051 int regno = reg_renumber[i];
4052 if (reg_old_renumber[i] == regno)
4055 SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4057 alter_reg (i, reg_old_renumber[i], false);
4058 reg_old_renumber[i] = regno;
4062 fprintf (dump_file, " Register %d now on stack.\n\n", i);
4064 fprintf (dump_file, " Register %d now in %d.\n\n",
4065 i, reg_renumber[i]);
4069 return something_changed;
4072 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4075 scan_paradoxical_subregs (rtx x)
4079 enum rtx_code code = GET_CODE (x);
4090 case CONST_VECTOR: /* shouldn't happen, but just in case. */
4098 if (REG_P (SUBREG_REG (x))
4099 && (GET_MODE_SIZE (GET_MODE (x))
4100 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
4102 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4103 = GET_MODE_SIZE (GET_MODE (x));
4104 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
4112 fmt = GET_RTX_FORMAT (code);
4113 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4116 scan_paradoxical_subregs (XEXP (x, i));
4117 else if (fmt[i] == 'E')
4120 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4121 scan_paradoxical_subregs (XVECEXP (x, i, j));
4126 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4127 examine all of the reload insns between PREV and NEXT exclusive, and
4128 annotate all that may trap. */
4131 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
4133 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4136 if (!insn_could_throw_p (insn))
4137 remove_note (insn, note);
4138 copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next);
4141 /* Reload pseudo-registers into hard regs around each insn as needed.
4142 Additional register load insns are output before the insn that needs it
4143 and perhaps store insns after insns that modify the reloaded pseudo reg.
4145 reg_last_reload_reg and reg_reloaded_contents keep track of
4146 which registers are already available in reload registers.
4147 We update these for the reloads that we perform,
4148 as the insns are scanned. */
4151 reload_as_needed (int live_known)
4153 struct insn_chain *chain;
4154 #if defined (AUTO_INC_DEC)
4159 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4160 memset (spill_reg_store, 0, sizeof spill_reg_store);
4161 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4162 INIT_REG_SET (®_has_output_reload);
4163 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4164 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4166 set_initial_elim_offsets ();
4168 for (chain = reload_insn_chain; chain; chain = chain->next)
4171 rtx insn = chain->insn;
4172 rtx old_next = NEXT_INSN (insn);
4174 rtx old_prev = PREV_INSN (insn);
4177 /* If we pass a label, copy the offsets from the label information
4178 into the current offsets of each elimination. */
4180 set_offsets_for_label (insn);
4182 else if (INSN_P (insn))
4184 regset_head regs_to_forget;
4185 INIT_REG_SET (®s_to_forget);
4186 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4188 /* If this is a USE and CLOBBER of a MEM, ensure that any
4189 references to eliminable registers have been removed. */
4191 if ((GET_CODE (PATTERN (insn)) == USE
4192 || GET_CODE (PATTERN (insn)) == CLOBBER)
4193 && MEM_P (XEXP (PATTERN (insn), 0)))
4194 XEXP (XEXP (PATTERN (insn), 0), 0)
4195 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4196 GET_MODE (XEXP (PATTERN (insn), 0)),
4199 /* If we need to do register elimination processing, do so.
4200 This might delete the insn, in which case we are done. */
4201 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4203 eliminate_regs_in_insn (insn, 1);
4206 update_eliminable_offsets ();
4207 CLEAR_REG_SET (®s_to_forget);
4212 /* If need_elim is nonzero but need_reload is zero, one might think
4213 that we could simply set n_reloads to 0. However, find_reloads
4214 could have done some manipulation of the insn (such as swapping
4215 commutative operands), and these manipulations are lost during
4216 the first pass for every insn that needs register elimination.
4217 So the actions of find_reloads must be redone here. */
4219 if (! chain->need_elim && ! chain->need_reload
4220 && ! chain->need_operand_change)
4222 /* First find the pseudo regs that must be reloaded for this insn.
4223 This info is returned in the tables reload_... (see reload.h).
4224 Also modify the body of INSN by substituting RELOAD
4225 rtx's for those pseudo regs. */
4228 CLEAR_REG_SET (®_has_output_reload);
4229 CLEAR_HARD_REG_SET (reg_is_output_reload);
4231 find_reloads (insn, 1, spill_indirect_levels, live_known,
4237 rtx next = NEXT_INSN (insn);
4240 prev = PREV_INSN (insn);
4242 /* Now compute which reload regs to reload them into. Perhaps
4243 reusing reload regs from previous insns, or else output
4244 load insns to reload them. Maybe output store insns too.
4245 Record the choices of reload reg in reload_reg_rtx. */
4246 choose_reload_regs (chain);
4248 /* Merge any reloads that we didn't combine for fear of
4249 increasing the number of spill registers needed but now
4250 discover can be safely merged. */
4251 if (SMALL_REGISTER_CLASSES)
4252 merge_assigned_reloads (insn);
4254 /* Generate the insns to reload operands into or out of
4255 their reload regs. */
4256 emit_reload_insns (chain);
4258 /* Substitute the chosen reload regs from reload_reg_rtx
4259 into the insn's body (or perhaps into the bodies of other
4260 load and store insn that we just made for reloading
4261 and that we moved the structure into). */
4262 subst_reloads (insn);
4264 /* Adjust the exception region notes for loads and stores. */
4265 if (flag_non_call_exceptions && !CALL_P (insn))
4266 fixup_eh_region_note (insn, prev, next);
4268 /* If this was an ASM, make sure that all the reload insns
4269 we have generated are valid. If not, give an error
4271 if (asm_noperands (PATTERN (insn)) >= 0)
4272 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4273 if (p != insn && INSN_P (p)
4274 && GET_CODE (PATTERN (p)) != USE
4275 && (recog_memoized (p) < 0
4276 || (extract_insn (p), ! constrain_operands (1))))
4278 error_for_asm (insn,
4279 "%<asm%> operand requires "
4280 "impossible reload");
4285 if (num_eliminable && chain->need_elim)
4286 update_eliminable_offsets ();
4288 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4289 is no longer validly lying around to save a future reload.
4290 Note that this does not detect pseudos that were reloaded
4291 for this insn in order to be stored in
4292 (obeying register constraints). That is correct; such reload
4293 registers ARE still valid. */
4294 forget_marked_reloads (®s_to_forget);
4295 CLEAR_REG_SET (®s_to_forget);
4297 /* There may have been CLOBBER insns placed after INSN. So scan
4298 between INSN and NEXT and use them to forget old reloads. */
4299 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4300 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4301 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4304 /* Likewise for regs altered by auto-increment in this insn.
4305 REG_INC notes have been changed by reloading:
4306 find_reloads_address_1 records substitutions for them,
4307 which have been performed by subst_reloads above. */
4308 for (i = n_reloads - 1; i >= 0; i--)
4310 rtx in_reg = rld[i].in_reg;
4313 enum rtx_code code = GET_CODE (in_reg);
4314 /* PRE_INC / PRE_DEC will have the reload register ending up
4315 with the same value as the stack slot, but that doesn't
4316 hold true for POST_INC / POST_DEC. Either we have to
4317 convert the memory access to a true POST_INC / POST_DEC,
4318 or we can't use the reload register for inheritance. */
4319 if ((code == POST_INC || code == POST_DEC)
4320 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4321 REGNO (rld[i].reg_rtx))
4322 /* Make sure it is the inc/dec pseudo, and not
4323 some other (e.g. output operand) pseudo. */
4324 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4325 == REGNO (XEXP (in_reg, 0))))
4328 rtx reload_reg = rld[i].reg_rtx;
4329 enum machine_mode mode = GET_MODE (reload_reg);
4333 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4335 /* We really want to ignore REG_INC notes here, so
4336 use PATTERN (p) as argument to reg_set_p . */
4337 if (reg_set_p (reload_reg, PATTERN (p)))
4339 n = count_occurrences (PATTERN (p), reload_reg, 0);
4345 = gen_rtx_fmt_e (code, mode, reload_reg);
4347 validate_replace_rtx_group (reload_reg,
4349 n = verify_changes (0);
4351 /* We must also verify that the constraints
4352 are met after the replacement. Make sure
4353 extract_insn is only called for an insn
4354 where the replacements were found to be
4359 n = constrain_operands (1);
4362 /* If the constraints were not met, then
4363 undo the replacement, else confirm it. */
4367 confirm_change_group ();
4373 add_reg_note (p, REG_INC, reload_reg);
4374 /* Mark this as having an output reload so that the
4375 REG_INC processing code below won't invalidate
4376 the reload for inheritance. */
4377 SET_HARD_REG_BIT (reg_is_output_reload,
4378 REGNO (reload_reg));
4379 SET_REGNO_REG_SET (®_has_output_reload,
4380 REGNO (XEXP (in_reg, 0)));
4383 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4386 else if ((code == PRE_INC || code == PRE_DEC)
4387 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4388 REGNO (rld[i].reg_rtx))
4389 /* Make sure it is the inc/dec pseudo, and not
4390 some other (e.g. output operand) pseudo. */
4391 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4392 == REGNO (XEXP (in_reg, 0))))
4394 SET_HARD_REG_BIT (reg_is_output_reload,
4395 REGNO (rld[i].reg_rtx));
4396 SET_REGNO_REG_SET (®_has_output_reload,
4397 REGNO (XEXP (in_reg, 0)));
4399 else if (code == PRE_INC || code == PRE_DEC
4400 || code == POST_INC || code == POST_DEC)
4402 int in_regno = REGNO (XEXP (in_reg, 0));
4404 if (reg_last_reload_reg[in_regno] != NULL_RTX)
4407 bool forget_p = true;
4409 in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4410 if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4413 for (x = old_prev ? NEXT_INSN (old_prev) : insn;
4416 if (x == reg_reloaded_insn[in_hard_regno])
4422 /* If for some reasons, we didn't set up
4423 reg_last_reload_reg in this insn,
4424 invalidate inheritance from previous
4425 insns for the incremented/decremented
4426 register. Such registers will be not in
4427 reg_has_output_reload. Invalidate it
4428 also if the corresponding element in
4429 reg_reloaded_insn is also
4432 forget_old_reloads_1 (XEXP (in_reg, 0),
4438 /* If a pseudo that got a hard register is auto-incremented,
4439 we must purge records of copying it into pseudos without
4441 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4442 if (REG_NOTE_KIND (x) == REG_INC)
4444 /* See if this pseudo reg was reloaded in this insn.
4445 If so, its last-reload info is still valid
4446 because it is based on this insn's reload. */
4447 for (i = 0; i < n_reloads; i++)
4448 if (rld[i].out == XEXP (x, 0))
4452 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4456 /* A reload reg's contents are unknown after a label. */
4458 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4460 /* Don't assume a reload reg is still good after a call insn
4461 if it is a call-used reg, or if it contains a value that will
4462 be partially clobbered by the call. */
4463 else if (CALL_P (insn))
4465 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4466 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4471 free (reg_last_reload_reg);
4472 CLEAR_REG_SET (®_has_output_reload);
4475 /* Discard all record of any value reloaded from X,
4476 or reloaded in X from someplace else;
4477 unless X is an output reload reg of the current insn.
4479 X may be a hard reg (the reload reg)
4480 or it may be a pseudo reg that was reloaded from.
4482 When DATA is non-NULL just mark the registers in regset
4483 to be forgotten later. */
4486 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4491 regset regs = (regset) data;
4493 /* note_stores does give us subregs of hard regs,
4494 subreg_regno_offset requires a hard reg. */
4495 while (GET_CODE (x) == SUBREG)
4497 /* We ignore the subreg offset when calculating the regno,
4498 because we are using the entire underlying hard register
4508 if (regno >= FIRST_PSEUDO_REGISTER)
4514 nr = hard_regno_nregs[regno][GET_MODE (x)];
4515 /* Storing into a spilled-reg invalidates its contents.
4516 This can happen if a block-local pseudo is allocated to that reg
4517 and it wasn't spilled because this block's total need is 0.
4518 Then some insn might have an optional reload and use this reg. */
4520 for (i = 0; i < nr; i++)
4521 /* But don't do this if the reg actually serves as an output
4522 reload reg in the current instruction. */
4524 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4526 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4527 spill_reg_store[regno + i] = 0;
4533 SET_REGNO_REG_SET (regs, regno + nr);
4536 /* Since value of X has changed,
4537 forget any value previously copied from it. */
4540 /* But don't forget a copy if this is the output reload
4541 that establishes the copy's validity. */
4543 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4544 reg_last_reload_reg[regno + nr] = 0;
4548 /* Forget the reloads marked in regset by previous function. */
4550 forget_marked_reloads (regset regs)
4553 reg_set_iterator rsi;
4554 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4556 if (reg < FIRST_PSEUDO_REGISTER
4557 /* But don't do this if the reg actually serves as an output
4558 reload reg in the current instruction. */
4560 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4562 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4563 spill_reg_store[reg] = 0;
4566 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4567 reg_last_reload_reg[reg] = 0;
4571 /* The following HARD_REG_SETs indicate when each hard register is
4572 used for a reload of various parts of the current insn. */
4574 /* If reg is unavailable for all reloads. */
4575 static HARD_REG_SET reload_reg_unavailable;
4576 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4577 static HARD_REG_SET reload_reg_used;
4578 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4579 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4580 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4581 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4582 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4583 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4584 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4585 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4586 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4587 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4588 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4589 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4590 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4591 static HARD_REG_SET reload_reg_used_in_op_addr;
4592 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4593 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4594 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4595 static HARD_REG_SET reload_reg_used_in_insn;
4596 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4597 static HARD_REG_SET reload_reg_used_in_other_addr;
4599 /* If reg is in use as a reload reg for any sort of reload. */
4600 static HARD_REG_SET reload_reg_used_at_all;
4602 /* If reg is use as an inherited reload. We just mark the first register
4604 static HARD_REG_SET reload_reg_used_for_inherit;
4606 /* Records which hard regs are used in any way, either as explicit use or
4607 by being allocated to a pseudo during any point of the current insn. */
4608 static HARD_REG_SET reg_used_in_insn;
4610 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4611 TYPE. MODE is used to indicate how many consecutive regs are
4615 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4616 enum machine_mode mode)
4618 unsigned int nregs = hard_regno_nregs[regno][mode];
4621 for (i = regno; i < nregs + regno; i++)
4626 SET_HARD_REG_BIT (reload_reg_used, i);
4629 case RELOAD_FOR_INPUT_ADDRESS:
4630 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4633 case RELOAD_FOR_INPADDR_ADDRESS:
4634 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4637 case RELOAD_FOR_OUTPUT_ADDRESS:
4638 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4641 case RELOAD_FOR_OUTADDR_ADDRESS:
4642 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4645 case RELOAD_FOR_OPERAND_ADDRESS:
4646 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4649 case RELOAD_FOR_OPADDR_ADDR:
4650 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4653 case RELOAD_FOR_OTHER_ADDRESS:
4654 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4657 case RELOAD_FOR_INPUT:
4658 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4661 case RELOAD_FOR_OUTPUT:
4662 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4665 case RELOAD_FOR_INSN:
4666 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4670 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4674 /* Similarly, but show REGNO is no longer in use for a reload. */
4677 clear_reload_reg_in_use (unsigned int regno, int opnum,
4678 enum reload_type type, enum machine_mode mode)
4680 unsigned int nregs = hard_regno_nregs[regno][mode];
4681 unsigned int start_regno, end_regno, r;
4683 /* A complication is that for some reload types, inheritance might
4684 allow multiple reloads of the same types to share a reload register.
4685 We set check_opnum if we have to check only reloads with the same
4686 operand number, and check_any if we have to check all reloads. */
4687 int check_opnum = 0;
4689 HARD_REG_SET *used_in_set;
4694 used_in_set = &reload_reg_used;
4697 case RELOAD_FOR_INPUT_ADDRESS:
4698 used_in_set = &reload_reg_used_in_input_addr[opnum];
4701 case RELOAD_FOR_INPADDR_ADDRESS:
4703 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4706 case RELOAD_FOR_OUTPUT_ADDRESS:
4707 used_in_set = &reload_reg_used_in_output_addr[opnum];
4710 case RELOAD_FOR_OUTADDR_ADDRESS:
4712 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4715 case RELOAD_FOR_OPERAND_ADDRESS:
4716 used_in_set = &reload_reg_used_in_op_addr;
4719 case RELOAD_FOR_OPADDR_ADDR:
4721 used_in_set = &reload_reg_used_in_op_addr_reload;
4724 case RELOAD_FOR_OTHER_ADDRESS:
4725 used_in_set = &reload_reg_used_in_other_addr;
4729 case RELOAD_FOR_INPUT:
4730 used_in_set = &reload_reg_used_in_input[opnum];
4733 case RELOAD_FOR_OUTPUT:
4734 used_in_set = &reload_reg_used_in_output[opnum];
4737 case RELOAD_FOR_INSN:
4738 used_in_set = &reload_reg_used_in_insn;
4743 /* We resolve conflicts with remaining reloads of the same type by
4744 excluding the intervals of reload registers by them from the
4745 interval of freed reload registers. Since we only keep track of
4746 one set of interval bounds, we might have to exclude somewhat
4747 more than what would be necessary if we used a HARD_REG_SET here.
4748 But this should only happen very infrequently, so there should
4749 be no reason to worry about it. */
4751 start_regno = regno;
4752 end_regno = regno + nregs;
4753 if (check_opnum || check_any)
4755 for (i = n_reloads - 1; i >= 0; i--)
4757 if (rld[i].when_needed == type
4758 && (check_any || rld[i].opnum == opnum)
4761 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4762 unsigned int conflict_end
4763 = end_hard_regno (rld[i].mode, conflict_start);
4765 /* If there is an overlap with the first to-be-freed register,
4766 adjust the interval start. */
4767 if (conflict_start <= start_regno && conflict_end > start_regno)
4768 start_regno = conflict_end;
4769 /* Otherwise, if there is a conflict with one of the other
4770 to-be-freed registers, adjust the interval end. */
4771 if (conflict_start > start_regno && conflict_start < end_regno)
4772 end_regno = conflict_start;
4777 for (r = start_regno; r < end_regno; r++)
4778 CLEAR_HARD_REG_BIT (*used_in_set, r);
4781 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4782 specified by OPNUM and TYPE. */
4785 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4789 /* In use for a RELOAD_OTHER means it's not available for anything. */
4790 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4791 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4797 /* In use for anything means we can't use it for RELOAD_OTHER. */
4798 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4799 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4800 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4801 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4804 for (i = 0; i < reload_n_operands; i++)
4805 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4806 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4807 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4808 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4809 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4810 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4815 case RELOAD_FOR_INPUT:
4816 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4817 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4820 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4823 /* If it is used for some other input, can't use it. */
4824 for (i = 0; i < reload_n_operands; i++)
4825 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4828 /* If it is used in a later operand's address, can't use it. */
4829 for (i = opnum + 1; i < reload_n_operands; i++)
4830 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4831 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4836 case RELOAD_FOR_INPUT_ADDRESS:
4837 /* Can't use a register if it is used for an input address for this
4838 operand or used as an input in an earlier one. */
4839 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4840 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4843 for (i = 0; i < opnum; i++)
4844 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4849 case RELOAD_FOR_INPADDR_ADDRESS:
4850 /* Can't use a register if it is used for an input address
4851 for this operand or used as an input in an earlier
4853 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4856 for (i = 0; i < opnum; i++)
4857 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4862 case RELOAD_FOR_OUTPUT_ADDRESS:
4863 /* Can't use a register if it is used for an output address for this
4864 operand or used as an output in this or a later operand. Note
4865 that multiple output operands are emitted in reverse order, so
4866 the conflicting ones are those with lower indices. */
4867 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4870 for (i = 0; i <= opnum; i++)
4871 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4876 case RELOAD_FOR_OUTADDR_ADDRESS:
4877 /* Can't use a register if it is used for an output address
4878 for this operand or used as an output in this or a
4879 later operand. Note that multiple output operands are
4880 emitted in reverse order, so the conflicting ones are
4881 those with lower indices. */
4882 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4885 for (i = 0; i <= opnum; i++)
4886 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4891 case RELOAD_FOR_OPERAND_ADDRESS:
4892 for (i = 0; i < reload_n_operands; i++)
4893 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4896 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4897 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4899 case RELOAD_FOR_OPADDR_ADDR:
4900 for (i = 0; i < reload_n_operands; i++)
4901 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4904 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4906 case RELOAD_FOR_OUTPUT:
4907 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4908 outputs, or an operand address for this or an earlier output.
4909 Note that multiple output operands are emitted in reverse order,
4910 so the conflicting ones are those with higher indices. */
4911 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4914 for (i = 0; i < reload_n_operands; i++)
4915 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4918 for (i = opnum; i < reload_n_operands; i++)
4919 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4920 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4925 case RELOAD_FOR_INSN:
4926 for (i = 0; i < reload_n_operands; i++)
4927 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4928 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4931 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4932 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4934 case RELOAD_FOR_OTHER_ADDRESS:
4935 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4942 /* Return 1 if the value in reload reg REGNO, as used by a reload
4943 needed for the part of the insn specified by OPNUM and TYPE,
4944 is still available in REGNO at the end of the insn.
4946 We can assume that the reload reg was already tested for availability
4947 at the time it is needed, and we should not check this again,
4948 in case the reg has already been marked in use. */
4951 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4958 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4959 its value must reach the end. */
4962 /* If this use is for part of the insn,
4963 its value reaches if no subsequent part uses the same register.
4964 Just like the above function, don't try to do this with lots
4967 case RELOAD_FOR_OTHER_ADDRESS:
4968 /* Here we check for everything else, since these don't conflict
4969 with anything else and everything comes later. */
4971 for (i = 0; i < reload_n_operands; i++)
4972 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4973 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4974 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4975 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4976 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4977 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4980 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4981 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4982 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4983 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4985 case RELOAD_FOR_INPUT_ADDRESS:
4986 case RELOAD_FOR_INPADDR_ADDRESS:
4987 /* Similar, except that we check only for this and subsequent inputs
4988 and the address of only subsequent inputs and we do not need
4989 to check for RELOAD_OTHER objects since they are known not to
4992 for (i = opnum; i < reload_n_operands; i++)
4993 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4996 for (i = opnum + 1; i < reload_n_operands; i++)
4997 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4998 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5001 for (i = 0; i < reload_n_operands; i++)
5002 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5003 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5004 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5007 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5010 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5011 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5012 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5014 case RELOAD_FOR_INPUT:
5015 /* Similar to input address, except we start at the next operand for
5016 both input and input address and we do not check for
5017 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5020 for (i = opnum + 1; i < reload_n_operands; i++)
5021 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5022 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5023 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5026 /* ... fall through ... */
5028 case RELOAD_FOR_OPERAND_ADDRESS:
5029 /* Check outputs and their addresses. */
5031 for (i = 0; i < reload_n_operands; i++)
5032 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5033 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5034 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5037 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5039 case RELOAD_FOR_OPADDR_ADDR:
5040 for (i = 0; i < reload_n_operands; i++)
5041 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5042 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5043 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5046 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5047 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5048 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5050 case RELOAD_FOR_INSN:
5051 /* These conflict with other outputs with RELOAD_OTHER. So
5052 we need only check for output addresses. */
5054 opnum = reload_n_operands;
5056 /* ... fall through ... */
5058 case RELOAD_FOR_OUTPUT:
5059 case RELOAD_FOR_OUTPUT_ADDRESS:
5060 case RELOAD_FOR_OUTADDR_ADDRESS:
5061 /* We already know these can't conflict with a later output. So the
5062 only thing to check are later output addresses.
5063 Note that multiple output operands are emitted in reverse order,
5064 so the conflicting ones are those with lower indices. */
5065 for (i = 0; i < opnum; i++)
5066 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5067 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5077 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5078 every register in the range [REGNO, REGNO + NREGS). */
5081 reload_regs_reach_end_p (unsigned int regno, int nregs,
5082 int opnum, enum reload_type type)
5086 for (i = 0; i < nregs; i++)
5087 if (!reload_reg_reaches_end_p (regno + i, opnum, type))
5093 /* Returns whether R1 and R2 are uniquely chained: the value of one
5094 is used by the other, and that value is not used by any other
5095 reload for this insn. This is used to partially undo the decision
5096 made in find_reloads when in the case of multiple
5097 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5098 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5099 reloads. This code tries to avoid the conflict created by that
5100 change. It might be cleaner to explicitly keep track of which
5101 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5102 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5103 this after the fact. */
5105 reloads_unique_chain_p (int r1, int r2)
5109 /* We only check input reloads. */
5110 if (! rld[r1].in || ! rld[r2].in)
5113 /* Avoid anything with output reloads. */
5114 if (rld[r1].out || rld[r2].out)
5117 /* "chained" means one reload is a component of the other reload,
5118 not the same as the other reload. */
5119 if (rld[r1].opnum != rld[r2].opnum
5120 || rtx_equal_p (rld[r1].in, rld[r2].in)
5121 || rld[r1].optional || rld[r2].optional
5122 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5123 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5126 for (i = 0; i < n_reloads; i ++)
5127 /* Look for input reloads that aren't our two */
5128 if (i != r1 && i != r2 && rld[i].in)
5130 /* If our reload is mentioned at all, it isn't a simple chain. */
5131 if (reg_mentioned_p (rld[r1].in, rld[i].in))
5138 /* The recursive function change all occurrences of WHAT in *WHERE
5141 substitute (rtx *where, const_rtx what, rtx repl)
5150 if (*where == what || rtx_equal_p (*where, what))
5156 code = GET_CODE (*where);
5157 fmt = GET_RTX_FORMAT (code);
5158 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5164 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5165 substitute (&XVECEXP (*where, i, j), what, repl);
5167 else if (fmt[i] == 'e')
5168 substitute (&XEXP (*where, i), what, repl);
5172 /* The function returns TRUE if chain of reload R1 and R2 (in any
5173 order) can be evaluated without usage of intermediate register for
5174 the reload containing another reload. It is important to see
5175 gen_reload to understand what the function is trying to do. As an
5176 example, let us have reload chain
5179 r1: <something> + const
5181 and reload R2 got reload reg HR. The function returns true if
5182 there is a correct insn HR = HR + <something>. Otherwise,
5183 gen_reload will use intermediate register (and this is the reload
5184 reg for R1) to reload <something>.
5186 We need this function to find a conflict for chain reloads. In our
5187 example, if HR = HR + <something> is incorrect insn, then we cannot
5188 use HR as a reload register for R2. If we do use it then we get a
5197 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5201 rtx out, in, tem, insn;
5202 rtx last = get_last_insn ();
5204 /* Make r2 a component of r1. */
5205 if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5211 gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5212 regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5213 gcc_assert (regno >= 0);
5214 out = gen_rtx_REG (rld[r1].mode, regno);
5215 in = copy_rtx (rld[r1].in);
5216 substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5218 /* If IN is a paradoxical SUBREG, remove it and try to put the
5219 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5220 if (GET_CODE (in) == SUBREG
5221 && (GET_MODE_SIZE (GET_MODE (in))
5222 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
5223 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
5224 in = SUBREG_REG (in), out = tem;
5226 if (GET_CODE (in) == PLUS
5227 && (REG_P (XEXP (in, 0))
5228 || GET_CODE (XEXP (in, 0)) == SUBREG
5229 || MEM_P (XEXP (in, 0)))
5230 && (REG_P (XEXP (in, 1))
5231 || GET_CODE (XEXP (in, 1)) == SUBREG
5232 || CONSTANT_P (XEXP (in, 1))
5233 || MEM_P (XEXP (in, 1))))
5235 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
5236 code = recog_memoized (insn);
5241 extract_insn (insn);
5242 /* We want constrain operands to treat this insn strictly in
5243 its validity determination, i.e., the way it would after
5244 reload has completed. */
5245 result = constrain_operands (1);
5248 delete_insns_since (last);
5252 /* It looks like other cases in gen_reload are not possible for
5253 chain reloads or do need an intermediate hard registers. */
5257 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5260 This function uses the same algorithm as reload_reg_free_p above. */
5263 reloads_conflict (int r1, int r2)
5265 enum reload_type r1_type = rld[r1].when_needed;
5266 enum reload_type r2_type = rld[r2].when_needed;
5267 int r1_opnum = rld[r1].opnum;
5268 int r2_opnum = rld[r2].opnum;
5270 /* RELOAD_OTHER conflicts with everything. */
5271 if (r2_type == RELOAD_OTHER)
5274 /* Otherwise, check conflicts differently for each type. */
5278 case RELOAD_FOR_INPUT:
5279 return (r2_type == RELOAD_FOR_INSN
5280 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5281 || r2_type == RELOAD_FOR_OPADDR_ADDR
5282 || r2_type == RELOAD_FOR_INPUT
5283 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5284 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5285 && r2_opnum > r1_opnum));
5287 case RELOAD_FOR_INPUT_ADDRESS:
5288 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5289 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5291 case RELOAD_FOR_INPADDR_ADDRESS:
5292 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5293 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5295 case RELOAD_FOR_OUTPUT_ADDRESS:
5296 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5297 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5299 case RELOAD_FOR_OUTADDR_ADDRESS:
5300 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5301 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5303 case RELOAD_FOR_OPERAND_ADDRESS:
5304 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5305 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5306 && (!reloads_unique_chain_p (r1, r2)
5307 || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5309 case RELOAD_FOR_OPADDR_ADDR:
5310 return (r2_type == RELOAD_FOR_INPUT
5311 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5313 case RELOAD_FOR_OUTPUT:
5314 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5315 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5316 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5317 && r2_opnum >= r1_opnum));
5319 case RELOAD_FOR_INSN:
5320 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5321 || r2_type == RELOAD_FOR_INSN
5322 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5324 case RELOAD_FOR_OTHER_ADDRESS:
5325 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5335 /* Indexed by reload number, 1 if incoming value
5336 inherited from previous insns. */
5337 static char reload_inherited[MAX_RELOADS];
5339 /* For an inherited reload, this is the insn the reload was inherited from,
5340 if we know it. Otherwise, this is 0. */
5341 static rtx reload_inheritance_insn[MAX_RELOADS];
5343 /* If nonzero, this is a place to get the value of the reload,
5344 rather than using reload_in. */
5345 static rtx reload_override_in[MAX_RELOADS];
5347 /* For each reload, the hard register number of the register used,
5348 or -1 if we did not need a register for this reload. */
5349 static int reload_spill_index[MAX_RELOADS];
5351 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5352 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5354 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5355 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5357 /* Subroutine of free_for_value_p, used to check a single register.
5358 START_REGNO is the starting regno of the full reload register
5359 (possibly comprising multiple hard registers) that we are considering. */
5362 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5363 enum reload_type type, rtx value, rtx out,
5364 int reloadnum, int ignore_address_reloads)
5367 /* Set if we see an input reload that must not share its reload register
5368 with any new earlyclobber, but might otherwise share the reload
5369 register with an output or input-output reload. */
5370 int check_earlyclobber = 0;
5374 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5377 if (out == const0_rtx)
5383 /* We use some pseudo 'time' value to check if the lifetimes of the
5384 new register use would overlap with the one of a previous reload
5385 that is not read-only or uses a different value.
5386 The 'time' used doesn't have to be linear in any shape or form, just
5388 Some reload types use different 'buckets' for each operand.
5389 So there are MAX_RECOG_OPERANDS different time values for each
5391 We compute TIME1 as the time when the register for the prospective
5392 new reload ceases to be live, and TIME2 for each existing
5393 reload as the time when that the reload register of that reload
5395 Where there is little to be gained by exact lifetime calculations,
5396 we just make conservative assumptions, i.e. a longer lifetime;
5397 this is done in the 'default:' cases. */
5400 case RELOAD_FOR_OTHER_ADDRESS:
5401 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5402 time1 = copy ? 0 : 1;
5405 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5407 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5408 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5409 respectively, to the time values for these, we get distinct time
5410 values. To get distinct time values for each operand, we have to
5411 multiply opnum by at least three. We round that up to four because
5412 multiply by four is often cheaper. */
5413 case RELOAD_FOR_INPADDR_ADDRESS:
5414 time1 = opnum * 4 + 2;
5416 case RELOAD_FOR_INPUT_ADDRESS:
5417 time1 = opnum * 4 + 3;
5419 case RELOAD_FOR_INPUT:
5420 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5421 executes (inclusive). */
5422 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5424 case RELOAD_FOR_OPADDR_ADDR:
5426 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5427 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5429 case RELOAD_FOR_OPERAND_ADDRESS:
5430 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5432 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5434 case RELOAD_FOR_OUTADDR_ADDRESS:
5435 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5437 case RELOAD_FOR_OUTPUT_ADDRESS:
5438 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5441 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5444 for (i = 0; i < n_reloads; i++)
5446 rtx reg = rld[i].reg_rtx;
5447 if (reg && REG_P (reg)
5448 && ((unsigned) regno - true_regnum (reg)
5449 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5452 rtx other_input = rld[i].in;
5454 /* If the other reload loads the same input value, that
5455 will not cause a conflict only if it's loading it into
5456 the same register. */
5457 if (true_regnum (reg) != start_regno)
5458 other_input = NULL_RTX;
5459 if (! other_input || ! rtx_equal_p (other_input, value)
5460 || rld[i].out || out)
5463 switch (rld[i].when_needed)
5465 case RELOAD_FOR_OTHER_ADDRESS:
5468 case RELOAD_FOR_INPADDR_ADDRESS:
5469 /* find_reloads makes sure that a
5470 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5471 by at most one - the first -
5472 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5473 address reload is inherited, the address address reload
5474 goes away, so we can ignore this conflict. */
5475 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5476 && ignore_address_reloads
5477 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5478 Then the address address is still needed to store
5479 back the new address. */
5480 && ! rld[reloadnum].out)
5482 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5483 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5485 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5486 && ignore_address_reloads
5487 /* Unless we are reloading an auto_inc expression. */
5488 && ! rld[reloadnum].out)
5490 time2 = rld[i].opnum * 4 + 2;
5492 case RELOAD_FOR_INPUT_ADDRESS:
5493 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5494 && ignore_address_reloads
5495 && ! rld[reloadnum].out)
5497 time2 = rld[i].opnum * 4 + 3;
5499 case RELOAD_FOR_INPUT:
5500 time2 = rld[i].opnum * 4 + 4;
5501 check_earlyclobber = 1;
5503 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5504 == MAX_RECOG_OPERAND * 4 */
5505 case RELOAD_FOR_OPADDR_ADDR:
5506 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5507 && ignore_address_reloads
5508 && ! rld[reloadnum].out)
5510 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5512 case RELOAD_FOR_OPERAND_ADDRESS:
5513 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5514 check_earlyclobber = 1;
5516 case RELOAD_FOR_INSN:
5517 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5519 case RELOAD_FOR_OUTPUT:
5520 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5521 instruction is executed. */
5522 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5524 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5525 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5527 case RELOAD_FOR_OUTADDR_ADDRESS:
5528 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5529 && ignore_address_reloads
5530 && ! rld[reloadnum].out)
5532 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5534 case RELOAD_FOR_OUTPUT_ADDRESS:
5535 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5538 /* If there is no conflict in the input part, handle this
5539 like an output reload. */
5540 if (! rld[i].in || rtx_equal_p (other_input, value))
5542 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5543 /* Earlyclobbered outputs must conflict with inputs. */
5544 if (earlyclobber_operand_p (rld[i].out))
5545 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5550 /* RELOAD_OTHER might be live beyond instruction execution,
5551 but this is not obvious when we set time2 = 1. So check
5552 here if there might be a problem with the new reload
5553 clobbering the register used by the RELOAD_OTHER. */
5561 && (! rld[i].in || rld[i].out
5562 || ! rtx_equal_p (other_input, value)))
5563 || (out && rld[reloadnum].out_reg
5564 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5570 /* Earlyclobbered outputs must conflict with inputs. */
5571 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5577 /* Return 1 if the value in reload reg REGNO, as used by a reload
5578 needed for the part of the insn specified by OPNUM and TYPE,
5579 may be used to load VALUE into it.
5581 MODE is the mode in which the register is used, this is needed to
5582 determine how many hard regs to test.
5584 Other read-only reloads with the same value do not conflict
5585 unless OUT is nonzero and these other reloads have to live while
5586 output reloads live.
5587 If OUT is CONST0_RTX, this is a special case: it means that the
5588 test should not be for using register REGNO as reload register, but
5589 for copying from register REGNO into the reload register.
5591 RELOADNUM is the number of the reload we want to load this value for;
5592 a reload does not conflict with itself.
5594 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5595 reloads that load an address for the very reload we are considering.
5597 The caller has to make sure that there is no conflict with the return
5601 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5602 enum reload_type type, rtx value, rtx out, int reloadnum,
5603 int ignore_address_reloads)
5605 int nregs = hard_regno_nregs[regno][mode];
5607 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5608 value, out, reloadnum,
5609 ignore_address_reloads))
5614 /* Return nonzero if the rtx X is invariant over the current function. */
5615 /* ??? Actually, the places where we use this expect exactly what is
5616 tested here, and not everything that is function invariant. In
5617 particular, the frame pointer and arg pointer are special cased;
5618 pic_offset_table_rtx is not, and we must not spill these things to
5622 function_invariant_p (const_rtx x)
5626 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5628 if (GET_CODE (x) == PLUS
5629 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5630 && CONSTANT_P (XEXP (x, 1)))
5635 /* Determine whether the reload reg X overlaps any rtx'es used for
5636 overriding inheritance. Return nonzero if so. */
5639 conflicts_with_override (rtx x)
5642 for (i = 0; i < n_reloads; i++)
5643 if (reload_override_in[i]
5644 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5649 /* Give an error message saying we failed to find a reload for INSN,
5650 and clear out reload R. */
5652 failed_reload (rtx insn, int r)
5654 if (asm_noperands (PATTERN (insn)) < 0)
5655 /* It's the compiler's fault. */
5656 fatal_insn ("could not find a spill register", insn);
5658 /* It's the user's fault; the operand's mode and constraint
5659 don't match. Disable this reload so we don't crash in final. */
5660 error_for_asm (insn,
5661 "%<asm%> operand constraint incompatible with operand size");
5665 rld[r].optional = 1;
5666 rld[r].secondary_p = 1;
5669 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5670 for reload R. If it's valid, get an rtx for it. Return nonzero if
5673 set_reload_reg (int i, int r)
5676 rtx reg = spill_reg_rtx[i];
5678 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5679 spill_reg_rtx[i] = reg
5680 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5682 regno = true_regnum (reg);
5684 /* Detect when the reload reg can't hold the reload mode.
5685 This used to be one `if', but Sequent compiler can't handle that. */
5686 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5688 enum machine_mode test_mode = VOIDmode;
5690 test_mode = GET_MODE (rld[r].in);
5691 /* If rld[r].in has VOIDmode, it means we will load it
5692 in whatever mode the reload reg has: to wit, rld[r].mode.
5693 We have already tested that for validity. */
5694 /* Aside from that, we need to test that the expressions
5695 to reload from or into have modes which are valid for this
5696 reload register. Otherwise the reload insns would be invalid. */
5697 if (! (rld[r].in != 0 && test_mode != VOIDmode
5698 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5699 if (! (rld[r].out != 0
5700 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5702 /* The reg is OK. */
5705 /* Mark as in use for this insn the reload regs we use
5707 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5708 rld[r].when_needed, rld[r].mode);
5710 rld[r].reg_rtx = reg;
5711 reload_spill_index[r] = spill_regs[i];
5718 /* Find a spill register to use as a reload register for reload R.
5719 LAST_RELOAD is nonzero if this is the last reload for the insn being
5722 Set rld[R].reg_rtx to the register allocated.
5724 We return 1 if successful, or 0 if we couldn't find a spill reg and
5725 we didn't change anything. */
5728 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5733 /* If we put this reload ahead, thinking it is a group,
5734 then insist on finding a group. Otherwise we can grab a
5735 reg that some other reload needs.
5736 (That can happen when we have a 68000 DATA_OR_FP_REG
5737 which is a group of data regs or one fp reg.)
5738 We need not be so restrictive if there are no more reloads
5741 ??? Really it would be nicer to have smarter handling
5742 for that kind of reg class, where a problem like this is normal.
5743 Perhaps those classes should be avoided for reloading
5744 by use of more alternatives. */
5746 int force_group = rld[r].nregs > 1 && ! last_reload;
5748 /* If we want a single register and haven't yet found one,
5749 take any reg in the right class and not in use.
5750 If we want a consecutive group, here is where we look for it.
5752 We use two passes so we can first look for reload regs to
5753 reuse, which are already in use for other reloads in this insn,
5754 and only then use additional registers.
5755 I think that maximizing reuse is needed to make sure we don't
5756 run out of reload regs. Suppose we have three reloads, and
5757 reloads A and B can share regs. These need two regs.
5758 Suppose A and B are given different regs.
5759 That leaves none for C. */
5760 for (pass = 0; pass < 2; pass++)
5762 /* I is the index in spill_regs.
5763 We advance it round-robin between insns to use all spill regs
5764 equally, so that inherited reloads have a chance
5765 of leapfrogging each other. */
5769 for (count = 0; count < n_spills; count++)
5771 int rclass = (int) rld[r].rclass;
5777 regnum = spill_regs[i];
5779 if ((reload_reg_free_p (regnum, rld[r].opnum,
5782 /* We check reload_reg_used to make sure we
5783 don't clobber the return register. */
5784 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5785 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5786 rld[r].when_needed, rld[r].in,
5788 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
5789 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5790 /* Look first for regs to share, then for unshared. But
5791 don't share regs used for inherited reloads; they are
5792 the ones we want to preserve. */
5794 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5796 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5799 int nr = hard_regno_nregs[regnum][rld[r].mode];
5800 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5801 (on 68000) got us two FP regs. If NR is 1,
5802 we would reject both of them. */
5805 /* If we need only one reg, we have already won. */
5808 /* But reject a single reg if we demand a group. */
5813 /* Otherwise check that as many consecutive regs as we need
5814 are available here. */
5817 int regno = regnum + nr - 1;
5818 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
5819 && spill_reg_order[regno] >= 0
5820 && reload_reg_free_p (regno, rld[r].opnum,
5821 rld[r].when_needed)))
5830 /* If we found something on pass 1, omit pass 2. */
5831 if (count < n_spills)
5835 /* We should have found a spill register by now. */
5836 if (count >= n_spills)
5839 /* I is the index in SPILL_REG_RTX of the reload register we are to
5840 allocate. Get an rtx for it and find its register number. */
5842 return set_reload_reg (i, r);
5845 /* Initialize all the tables needed to allocate reload registers.
5846 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5847 is the array we use to restore the reg_rtx field for every reload. */
5850 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5854 for (i = 0; i < n_reloads; i++)
5855 rld[i].reg_rtx = save_reload_reg_rtx[i];
5857 memset (reload_inherited, 0, MAX_RELOADS);
5858 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5859 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5861 CLEAR_HARD_REG_SET (reload_reg_used);
5862 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5863 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5864 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5865 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5866 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5868 CLEAR_HARD_REG_SET (reg_used_in_insn);
5871 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5872 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5873 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5874 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5875 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5876 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5879 for (i = 0; i < reload_n_operands; i++)
5881 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5882 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5883 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5884 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5885 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5886 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5889 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5891 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5893 for (i = 0; i < n_reloads; i++)
5894 /* If we have already decided to use a certain register,
5895 don't use it in another way. */
5897 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5898 rld[i].when_needed, rld[i].mode);
5901 /* Assign hard reg targets for the pseudo-registers we must reload
5902 into hard regs for this insn.
5903 Also output the instructions to copy them in and out of the hard regs.
5905 For machines with register classes, we are responsible for
5906 finding a reload reg in the proper class. */
5909 choose_reload_regs (struct insn_chain *chain)
5911 rtx insn = chain->insn;
5913 unsigned int max_group_size = 1;
5914 enum reg_class group_class = NO_REGS;
5915 int pass, win, inheritance;
5917 rtx save_reload_reg_rtx[MAX_RELOADS];
5919 /* In order to be certain of getting the registers we need,
5920 we must sort the reloads into order of increasing register class.
5921 Then our grabbing of reload registers will parallel the process
5922 that provided the reload registers.
5924 Also note whether any of the reloads wants a consecutive group of regs.
5925 If so, record the maximum size of the group desired and what
5926 register class contains all the groups needed by this insn. */
5928 for (j = 0; j < n_reloads; j++)
5930 reload_order[j] = j;
5931 if (rld[j].reg_rtx != NULL_RTX)
5933 gcc_assert (REG_P (rld[j].reg_rtx)
5934 && HARD_REGISTER_P (rld[j].reg_rtx));
5935 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
5938 reload_spill_index[j] = -1;
5940 if (rld[j].nregs > 1)
5942 max_group_size = MAX (rld[j].nregs, max_group_size);
5944 = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
5947 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5951 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5953 /* If -O, try first with inheritance, then turning it off.
5954 If not -O, don't do inheritance.
5955 Using inheritance when not optimizing leads to paradoxes
5956 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5957 because one side of the comparison might be inherited. */
5959 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5961 choose_reload_regs_init (chain, save_reload_reg_rtx);
5963 /* Process the reloads in order of preference just found.
5964 Beyond this point, subregs can be found in reload_reg_rtx.
5966 This used to look for an existing reloaded home for all of the
5967 reloads, and only then perform any new reloads. But that could lose
5968 if the reloads were done out of reg-class order because a later
5969 reload with a looser constraint might have an old home in a register
5970 needed by an earlier reload with a tighter constraint.
5972 To solve this, we make two passes over the reloads, in the order
5973 described above. In the first pass we try to inherit a reload
5974 from a previous insn. If there is a later reload that needs a
5975 class that is a proper subset of the class being processed, we must
5976 also allocate a spill register during the first pass.
5978 Then make a second pass over the reloads to allocate any reloads
5979 that haven't been given registers yet. */
5981 for (j = 0; j < n_reloads; j++)
5983 int r = reload_order[j];
5984 rtx search_equiv = NULL_RTX;
5986 /* Ignore reloads that got marked inoperative. */
5987 if (rld[r].out == 0 && rld[r].in == 0
5988 && ! rld[r].secondary_p)
5991 /* If find_reloads chose to use reload_in or reload_out as a reload
5992 register, we don't need to chose one. Otherwise, try even if it
5993 found one since we might save an insn if we find the value lying
5995 Try also when reload_in is a pseudo without a hard reg. */
5996 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5997 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5998 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5999 && !MEM_P (rld[r].in)
6000 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
6003 #if 0 /* No longer needed for correct operation.
6004 It might give better code, or might not; worth an experiment? */
6005 /* If this is an optional reload, we can't inherit from earlier insns
6006 until we are sure that any non-optional reloads have been allocated.
6007 The following code takes advantage of the fact that optional reloads
6008 are at the end of reload_order. */
6009 if (rld[r].optional != 0)
6010 for (i = 0; i < j; i++)
6011 if ((rld[reload_order[i]].out != 0
6012 || rld[reload_order[i]].in != 0
6013 || rld[reload_order[i]].secondary_p)
6014 && ! rld[reload_order[i]].optional
6015 && rld[reload_order[i]].reg_rtx == 0)
6016 allocate_reload_reg (chain, reload_order[i], 0);
6019 /* First see if this pseudo is already available as reloaded
6020 for a previous insn. We cannot try to inherit for reloads
6021 that are smaller than the maximum number of registers needed
6022 for groups unless the register we would allocate cannot be used
6025 We could check here to see if this is a secondary reload for
6026 an object that is already in a register of the desired class.
6027 This would avoid the need for the secondary reload register.
6028 But this is complex because we can't easily determine what
6029 objects might want to be loaded via this reload. So let a
6030 register be allocated here. In `emit_reload_insns' we suppress
6031 one of the loads in the case described above. */
6037 enum machine_mode mode = VOIDmode;
6041 else if (REG_P (rld[r].in))
6043 regno = REGNO (rld[r].in);
6044 mode = GET_MODE (rld[r].in);
6046 else if (REG_P (rld[r].in_reg))
6048 regno = REGNO (rld[r].in_reg);
6049 mode = GET_MODE (rld[r].in_reg);
6051 else if (GET_CODE (rld[r].in_reg) == SUBREG
6052 && REG_P (SUBREG_REG (rld[r].in_reg)))
6054 regno = REGNO (SUBREG_REG (rld[r].in_reg));
6055 if (regno < FIRST_PSEUDO_REGISTER)
6056 regno = subreg_regno (rld[r].in_reg);
6058 byte = SUBREG_BYTE (rld[r].in_reg);
6059 mode = GET_MODE (rld[r].in_reg);
6062 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6063 && REG_P (XEXP (rld[r].in_reg, 0)))
6065 regno = REGNO (XEXP (rld[r].in_reg, 0));
6066 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6067 rld[r].out = rld[r].in;
6071 /* This won't work, since REGNO can be a pseudo reg number.
6072 Also, it takes much more hair to keep track of all the things
6073 that can invalidate an inherited reload of part of a pseudoreg. */
6074 else if (GET_CODE (rld[r].in) == SUBREG
6075 && REG_P (SUBREG_REG (rld[r].in)))
6076 regno = subreg_regno (rld[r].in);
6080 && reg_last_reload_reg[regno] != 0
6081 #ifdef CANNOT_CHANGE_MODE_CLASS
6082 /* Verify that the register it's in can be used in
6084 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
6085 GET_MODE (reg_last_reload_reg[regno]),
6090 enum reg_class rclass = rld[r].rclass, last_class;
6091 rtx last_reg = reg_last_reload_reg[regno];
6092 enum machine_mode need_mode;
6094 i = REGNO (last_reg);
6095 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6096 last_class = REGNO_REG_CLASS (i);
6102 = smallest_mode_for_size
6103 (GET_MODE_BITSIZE (mode) + byte * BITS_PER_UNIT,
6104 GET_MODE_CLASS (mode) == MODE_PARTIAL_INT
6105 ? MODE_INT : GET_MODE_CLASS (mode));
6107 if ((GET_MODE_SIZE (GET_MODE (last_reg))
6108 >= GET_MODE_SIZE (need_mode))
6109 && reg_reloaded_contents[i] == regno
6110 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6111 && HARD_REGNO_MODE_OK (i, rld[r].mode)
6112 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6113 /* Even if we can't use this register as a reload
6114 register, we might use it for reload_override_in,
6115 if copying it to the desired class is cheap
6117 || ((REGISTER_MOVE_COST (mode, last_class, rclass)
6118 < MEMORY_MOVE_COST (mode, rclass, 1))
6119 && (secondary_reload_class (1, rclass, mode,
6122 #ifdef SECONDARY_MEMORY_NEEDED
6123 && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
6128 && (rld[r].nregs == max_group_size
6129 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6131 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6132 rld[r].when_needed, rld[r].in,
6135 /* If a group is needed, verify that all the subsequent
6136 registers still have their values intact. */
6137 int nr = hard_regno_nregs[i][rld[r].mode];
6140 for (k = 1; k < nr; k++)
6141 if (reg_reloaded_contents[i + k] != regno
6142 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6150 last_reg = (GET_MODE (last_reg) == mode
6151 ? last_reg : gen_rtx_REG (mode, i));
6154 for (k = 0; k < nr; k++)
6155 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6158 /* We found a register that contains the
6159 value we need. If this register is the
6160 same as an `earlyclobber' operand of the
6161 current insn, just mark it as a place to
6162 reload from since we can't use it as the
6163 reload register itself. */
6165 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6166 if (reg_overlap_mentioned_for_reload_p
6167 (reg_last_reload_reg[regno],
6168 reload_earlyclobbers[i1]))
6171 if (i1 != n_earlyclobbers
6172 || ! (free_for_value_p (i, rld[r].mode,
6174 rld[r].when_needed, rld[r].in,
6176 /* Don't use it if we'd clobber a pseudo reg. */
6177 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6179 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6180 /* Don't clobber the frame pointer. */
6181 || (i == HARD_FRAME_POINTER_REGNUM
6182 && frame_pointer_needed
6184 /* Don't really use the inherited spill reg
6185 if we need it wider than we've got it. */
6186 || (GET_MODE_SIZE (rld[r].mode)
6187 > GET_MODE_SIZE (mode))
6190 /* If find_reloads chose reload_out as reload
6191 register, stay with it - that leaves the
6192 inherited register for subsequent reloads. */
6193 || (rld[r].out && rld[r].reg_rtx
6194 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6196 if (! rld[r].optional)
6198 reload_override_in[r] = last_reg;
6199 reload_inheritance_insn[r]
6200 = reg_reloaded_insn[i];
6206 /* We can use this as a reload reg. */
6207 /* Mark the register as in use for this part of
6209 mark_reload_reg_in_use (i,
6213 rld[r].reg_rtx = last_reg;
6214 reload_inherited[r] = 1;
6215 reload_inheritance_insn[r]
6216 = reg_reloaded_insn[i];
6217 reload_spill_index[r] = i;
6218 for (k = 0; k < nr; k++)
6219 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6227 /* Here's another way to see if the value is already lying around. */
6230 && ! reload_inherited[r]
6232 && (CONSTANT_P (rld[r].in)
6233 || GET_CODE (rld[r].in) == PLUS
6234 || REG_P (rld[r].in)
6235 || MEM_P (rld[r].in))
6236 && (rld[r].nregs == max_group_size
6237 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6238 search_equiv = rld[r].in;
6239 /* If this is an output reload from a simple move insn, look
6240 if an equivalence for the input is available. */
6241 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
6243 rtx set = single_set (insn);
6246 && rtx_equal_p (rld[r].out, SET_DEST (set))
6247 && CONSTANT_P (SET_SRC (set)))
6248 search_equiv = SET_SRC (set);
6254 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6255 -1, NULL, 0, rld[r].mode);
6261 regno = REGNO (equiv);
6264 /* This must be a SUBREG of a hard register.
6265 Make a new REG since this might be used in an
6266 address and not all machines support SUBREGs
6268 gcc_assert (GET_CODE (equiv) == SUBREG);
6269 regno = subreg_regno (equiv);
6270 equiv = gen_rtx_REG (rld[r].mode, regno);
6271 /* If we choose EQUIV as the reload register, but the
6272 loop below decides to cancel the inheritance, we'll
6273 end up reloading EQUIV in rld[r].mode, not the mode
6274 it had originally. That isn't safe when EQUIV isn't
6275 available as a spill register since its value might
6276 still be live at this point. */
6277 for (i = regno; i < regno + (int) rld[r].nregs; i++)
6278 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6283 /* If we found a spill reg, reject it unless it is free
6284 and of the desired class. */
6288 int bad_for_class = 0;
6289 int max_regno = regno + rld[r].nregs;
6291 for (i = regno; i < max_regno; i++)
6293 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6295 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6300 && ! free_for_value_p (regno, rld[r].mode,
6301 rld[r].opnum, rld[r].when_needed,
6302 rld[r].in, rld[r].out, r, 1))
6307 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6310 /* We found a register that contains the value we need.
6311 If this register is the same as an `earlyclobber' operand
6312 of the current insn, just mark it as a place to reload from
6313 since we can't use it as the reload register itself. */
6316 for (i = 0; i < n_earlyclobbers; i++)
6317 if (reg_overlap_mentioned_for_reload_p (equiv,
6318 reload_earlyclobbers[i]))
6320 if (! rld[r].optional)
6321 reload_override_in[r] = equiv;
6326 /* If the equiv register we have found is explicitly clobbered
6327 in the current insn, it depends on the reload type if we
6328 can use it, use it for reload_override_in, or not at all.
6329 In particular, we then can't use EQUIV for a
6330 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6334 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6335 switch (rld[r].when_needed)
6337 case RELOAD_FOR_OTHER_ADDRESS:
6338 case RELOAD_FOR_INPADDR_ADDRESS:
6339 case RELOAD_FOR_INPUT_ADDRESS:
6340 case RELOAD_FOR_OPADDR_ADDR:
6343 case RELOAD_FOR_INPUT:
6344 case RELOAD_FOR_OPERAND_ADDRESS:
6345 if (! rld[r].optional)
6346 reload_override_in[r] = equiv;
6352 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6353 switch (rld[r].when_needed)
6355 case RELOAD_FOR_OTHER_ADDRESS:
6356 case RELOAD_FOR_INPADDR_ADDRESS:
6357 case RELOAD_FOR_INPUT_ADDRESS:
6358 case RELOAD_FOR_OPADDR_ADDR:
6359 case RELOAD_FOR_OPERAND_ADDRESS:
6360 case RELOAD_FOR_INPUT:
6363 if (! rld[r].optional)
6364 reload_override_in[r] = equiv;
6372 /* If we found an equivalent reg, say no code need be generated
6373 to load it, and use it as our reload reg. */
6375 && (regno != HARD_FRAME_POINTER_REGNUM
6376 || !frame_pointer_needed))
6378 int nr = hard_regno_nregs[regno][rld[r].mode];
6380 rld[r].reg_rtx = equiv;
6381 reload_spill_index[r] = regno;
6382 reload_inherited[r] = 1;
6384 /* If reg_reloaded_valid is not set for this register,
6385 there might be a stale spill_reg_store lying around.
6386 We must clear it, since otherwise emit_reload_insns
6387 might delete the store. */
6388 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6389 spill_reg_store[regno] = NULL_RTX;
6390 /* If any of the hard registers in EQUIV are spill
6391 registers, mark them as in use for this insn. */
6392 for (k = 0; k < nr; k++)
6394 i = spill_reg_order[regno + k];
6397 mark_reload_reg_in_use (regno, rld[r].opnum,
6400 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6407 /* If we found a register to use already, or if this is an optional
6408 reload, we are done. */
6409 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6413 /* No longer needed for correct operation. Might or might
6414 not give better code on the average. Want to experiment? */
6416 /* See if there is a later reload that has a class different from our
6417 class that intersects our class or that requires less register
6418 than our reload. If so, we must allocate a register to this
6419 reload now, since that reload might inherit a previous reload
6420 and take the only available register in our class. Don't do this
6421 for optional reloads since they will force all previous reloads
6422 to be allocated. Also don't do this for reloads that have been
6425 for (i = j + 1; i < n_reloads; i++)
6427 int s = reload_order[i];
6429 if ((rld[s].in == 0 && rld[s].out == 0
6430 && ! rld[s].secondary_p)
6434 if ((rld[s].rclass != rld[r].rclass
6435 && reg_classes_intersect_p (rld[r].rclass,
6437 || rld[s].nregs < rld[r].nregs)
6444 allocate_reload_reg (chain, r, j == n_reloads - 1);
6448 /* Now allocate reload registers for anything non-optional that
6449 didn't get one yet. */
6450 for (j = 0; j < n_reloads; j++)
6452 int r = reload_order[j];
6454 /* Ignore reloads that got marked inoperative. */
6455 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6458 /* Skip reloads that already have a register allocated or are
6460 if (rld[r].reg_rtx != 0 || rld[r].optional)
6463 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6467 /* If that loop got all the way, we have won. */
6474 /* Loop around and try without any inheritance. */
6479 /* First undo everything done by the failed attempt
6480 to allocate with inheritance. */
6481 choose_reload_regs_init (chain, save_reload_reg_rtx);
6483 /* Some sanity tests to verify that the reloads found in the first
6484 pass are identical to the ones we have now. */
6485 gcc_assert (chain->n_reloads == n_reloads);
6487 for (i = 0; i < n_reloads; i++)
6489 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6491 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6492 for (j = 0; j < n_spills; j++)
6493 if (spill_regs[j] == chain->rld[i].regno)
6494 if (! set_reload_reg (j, i))
6495 failed_reload (chain->insn, i);
6499 /* If we thought we could inherit a reload, because it seemed that
6500 nothing else wanted the same reload register earlier in the insn,
6501 verify that assumption, now that all reloads have been assigned.
6502 Likewise for reloads where reload_override_in has been set. */
6504 /* If doing expensive optimizations, do one preliminary pass that doesn't
6505 cancel any inheritance, but removes reloads that have been needed only
6506 for reloads that we know can be inherited. */
6507 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6509 for (j = 0; j < n_reloads; j++)
6511 int r = reload_order[j];
6513 if (reload_inherited[r] && rld[r].reg_rtx)
6514 check_reg = rld[r].reg_rtx;
6515 else if (reload_override_in[r]
6516 && (REG_P (reload_override_in[r])
6517 || GET_CODE (reload_override_in[r]) == SUBREG))
6518 check_reg = reload_override_in[r];
6521 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6522 rld[r].opnum, rld[r].when_needed, rld[r].in,
6523 (reload_inherited[r]
6524 ? rld[r].out : const0_rtx),
6529 reload_inherited[r] = 0;
6530 reload_override_in[r] = 0;
6532 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6533 reload_override_in, then we do not need its related
6534 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6535 likewise for other reload types.
6536 We handle this by removing a reload when its only replacement
6537 is mentioned in reload_in of the reload we are going to inherit.
6538 A special case are auto_inc expressions; even if the input is
6539 inherited, we still need the address for the output. We can
6540 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6541 If we succeeded removing some reload and we are doing a preliminary
6542 pass just to remove such reloads, make another pass, since the
6543 removal of one reload might allow us to inherit another one. */
6545 && rld[r].out != rld[r].in
6546 && remove_address_replacements (rld[r].in) && pass)
6551 /* Now that reload_override_in is known valid,
6552 actually override reload_in. */
6553 for (j = 0; j < n_reloads; j++)
6554 if (reload_override_in[j])
6555 rld[j].in = reload_override_in[j];
6557 /* If this reload won't be done because it has been canceled or is
6558 optional and not inherited, clear reload_reg_rtx so other
6559 routines (such as subst_reloads) don't get confused. */
6560 for (j = 0; j < n_reloads; j++)
6561 if (rld[j].reg_rtx != 0
6562 && ((rld[j].optional && ! reload_inherited[j])
6563 || (rld[j].in == 0 && rld[j].out == 0
6564 && ! rld[j].secondary_p)))
6566 int regno = true_regnum (rld[j].reg_rtx);
6568 if (spill_reg_order[regno] >= 0)
6569 clear_reload_reg_in_use (regno, rld[j].opnum,
6570 rld[j].when_needed, rld[j].mode);
6572 reload_spill_index[j] = -1;
6575 /* Record which pseudos and which spill regs have output reloads. */
6576 for (j = 0; j < n_reloads; j++)
6578 int r = reload_order[j];
6580 i = reload_spill_index[r];
6582 /* I is nonneg if this reload uses a register.
6583 If rld[r].reg_rtx is 0, this is an optional reload
6584 that we opted to ignore. */
6585 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6586 && rld[r].reg_rtx != 0)
6588 int nregno = REGNO (rld[r].out_reg);
6591 if (nregno < FIRST_PSEUDO_REGISTER)
6592 nr = hard_regno_nregs[nregno][rld[r].mode];
6595 SET_REGNO_REG_SET (®_has_output_reload,
6600 nr = hard_regno_nregs[i][rld[r].mode];
6602 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6605 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6606 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6607 || rld[r].when_needed == RELOAD_FOR_INSN);
6612 /* Deallocate the reload register for reload R. This is called from
6613 remove_address_replacements. */
6616 deallocate_reload_reg (int r)
6620 if (! rld[r].reg_rtx)
6622 regno = true_regnum (rld[r].reg_rtx);
6624 if (spill_reg_order[regno] >= 0)
6625 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6627 reload_spill_index[r] = -1;
6630 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6631 reloads of the same item for fear that we might not have enough reload
6632 registers. However, normally they will get the same reload register
6633 and hence actually need not be loaded twice.
6635 Here we check for the most common case of this phenomenon: when we have
6636 a number of reloads for the same object, each of which were allocated
6637 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6638 reload, and is not modified in the insn itself. If we find such,
6639 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6640 This will not increase the number of spill registers needed and will
6641 prevent redundant code. */
6644 merge_assigned_reloads (rtx insn)
6648 /* Scan all the reloads looking for ones that only load values and
6649 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6650 assigned and not modified by INSN. */
6652 for (i = 0; i < n_reloads; i++)
6654 int conflicting_input = 0;
6655 int max_input_address_opnum = -1;
6656 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6658 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6659 || rld[i].out != 0 || rld[i].reg_rtx == 0
6660 || reg_set_p (rld[i].reg_rtx, insn))
6663 /* Look at all other reloads. Ensure that the only use of this
6664 reload_reg_rtx is in a reload that just loads the same value
6665 as we do. Note that any secondary reloads must be of the identical
6666 class since the values, modes, and result registers are the
6667 same, so we need not do anything with any secondary reloads. */
6669 for (j = 0; j < n_reloads; j++)
6671 if (i == j || rld[j].reg_rtx == 0
6672 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6676 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6677 && rld[j].opnum > max_input_address_opnum)
6678 max_input_address_opnum = rld[j].opnum;
6680 /* If the reload regs aren't exactly the same (e.g, different modes)
6681 or if the values are different, we can't merge this reload.
6682 But if it is an input reload, we might still merge
6683 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6685 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6686 || rld[j].out != 0 || rld[j].in == 0
6687 || ! rtx_equal_p (rld[i].in, rld[j].in))
6689 if (rld[j].when_needed != RELOAD_FOR_INPUT
6690 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6691 || rld[i].opnum > rld[j].opnum)
6692 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6694 conflicting_input = 1;
6695 if (min_conflicting_input_opnum > rld[j].opnum)
6696 min_conflicting_input_opnum = rld[j].opnum;
6700 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6701 we, in fact, found any matching reloads. */
6704 && max_input_address_opnum <= min_conflicting_input_opnum)
6706 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6708 for (j = 0; j < n_reloads; j++)
6709 if (i != j && rld[j].reg_rtx != 0
6710 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6711 && (! conflicting_input
6712 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6713 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6715 rld[i].when_needed = RELOAD_OTHER;
6717 reload_spill_index[j] = -1;
6718 transfer_replacements (i, j);
6721 /* If this is now RELOAD_OTHER, look for any reloads that
6722 load parts of this operand and set them to
6723 RELOAD_FOR_OTHER_ADDRESS if they were for inputs,
6724 RELOAD_OTHER for outputs. Note that this test is
6725 equivalent to looking for reloads for this operand
6728 We must take special care with RELOAD_FOR_OUTPUT_ADDRESS;
6729 it may share registers with a RELOAD_FOR_INPUT, so we can
6730 not change it to RELOAD_FOR_OTHER_ADDRESS. We should
6731 never need to, since we do not modify RELOAD_FOR_OUTPUT.
6733 It is possible that the RELOAD_FOR_OPERAND_ADDRESS
6734 instruction is assigned the same register as the earlier
6735 RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two
6736 instructions will cause the RELOAD_FOR_OTHER_ADDRESS
6737 instruction to be deleted later on. */
6739 if (rld[i].when_needed == RELOAD_OTHER)
6740 for (j = 0; j < n_reloads; j++)
6742 && rld[j].when_needed != RELOAD_OTHER
6743 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6744 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6745 && rld[j].when_needed != RELOAD_FOR_OPERAND_ADDRESS
6746 && (! conflicting_input
6747 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6748 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6749 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6755 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6756 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6757 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6759 /* Check to see if we accidentally converted two
6760 reloads that use the same reload register with
6761 different inputs to the same type. If so, the
6762 resulting code won't work. */
6764 for (k = 0; k < j; k++)
6765 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6766 || rld[k].when_needed != rld[j].when_needed
6767 || !rtx_equal_p (rld[k].reg_rtx,
6769 || rtx_equal_p (rld[k].in,
6776 /* These arrays are filled by emit_reload_insns and its subroutines. */
6777 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6778 static rtx other_input_address_reload_insns = 0;
6779 static rtx other_input_reload_insns = 0;
6780 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6781 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6782 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6783 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6784 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6785 static rtx operand_reload_insns = 0;
6786 static rtx other_operand_reload_insns = 0;
6787 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6789 /* Values to be put in spill_reg_store are put here first. */
6790 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6791 static HARD_REG_SET reg_reloaded_died;
6793 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6794 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6795 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6796 adjusted register, and return true. Otherwise, return false. */
6798 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6799 enum reg_class new_class,
6800 enum machine_mode new_mode)
6805 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6807 unsigned regno = REGNO (reg);
6809 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6811 if (GET_MODE (reg) != new_mode)
6813 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6815 if (hard_regno_nregs[regno][new_mode]
6816 > hard_regno_nregs[regno][GET_MODE (reg)])
6818 reg = reload_adjust_reg_for_mode (reg, new_mode);
6826 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6827 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6828 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6829 adjusted register, and return true. Otherwise, return false. */
6831 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6832 enum insn_code icode)
6835 enum reg_class new_class = scratch_reload_class (icode);
6836 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6838 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6839 new_class, new_mode);
6842 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6843 has the number J. OLD contains the value to be used as input. */
6846 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6849 rtx insn = chain->insn;
6851 rtx oldequiv_reg = 0;
6854 enum machine_mode mode;
6857 /* delete_output_reload is only invoked properly if old contains
6858 the original pseudo register. Since this is replaced with a
6859 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6860 find the pseudo in RELOAD_IN_REG. */
6861 if (reload_override_in[j]
6862 && REG_P (rl->in_reg))
6869 else if (REG_P (oldequiv))
6870 oldequiv_reg = oldequiv;
6871 else if (GET_CODE (oldequiv) == SUBREG)
6872 oldequiv_reg = SUBREG_REG (oldequiv);
6874 reloadreg = reload_reg_rtx_for_input[j];
6875 mode = GET_MODE (reloadreg);
6877 /* If we are reloading from a register that was recently stored in
6878 with an output-reload, see if we can prove there was
6879 actually no need to store the old value in it. */
6881 if (optimize && REG_P (oldequiv)
6882 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6883 && spill_reg_store[REGNO (oldequiv)]
6885 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6886 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6888 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6890 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
6893 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6894 oldequiv = SUBREG_REG (oldequiv);
6895 if (GET_MODE (oldequiv) != VOIDmode
6896 && mode != GET_MODE (oldequiv))
6897 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6899 /* Switch to the right place to emit the reload insns. */
6900 switch (rl->when_needed)
6903 where = &other_input_reload_insns;
6905 case RELOAD_FOR_INPUT:
6906 where = &input_reload_insns[rl->opnum];
6908 case RELOAD_FOR_INPUT_ADDRESS:
6909 where = &input_address_reload_insns[rl->opnum];
6911 case RELOAD_FOR_INPADDR_ADDRESS:
6912 where = &inpaddr_address_reload_insns[rl->opnum];
6914 case RELOAD_FOR_OUTPUT_ADDRESS:
6915 where = &output_address_reload_insns[rl->opnum];
6917 case RELOAD_FOR_OUTADDR_ADDRESS:
6918 where = &outaddr_address_reload_insns[rl->opnum];
6920 case RELOAD_FOR_OPERAND_ADDRESS:
6921 where = &operand_reload_insns;
6923 case RELOAD_FOR_OPADDR_ADDR:
6924 where = &other_operand_reload_insns;
6926 case RELOAD_FOR_OTHER_ADDRESS:
6927 where = &other_input_address_reload_insns;
6933 push_to_sequence (*where);
6935 /* Auto-increment addresses must be reloaded in a special way. */
6936 if (rl->out && ! rl->out_reg)
6938 /* We are not going to bother supporting the case where a
6939 incremented register can't be copied directly from
6940 OLDEQUIV since this seems highly unlikely. */
6941 gcc_assert (rl->secondary_in_reload < 0);
6943 if (reload_inherited[j])
6944 oldequiv = reloadreg;
6946 old = XEXP (rl->in_reg, 0);
6948 if (optimize && REG_P (oldequiv)
6949 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6950 && spill_reg_store[REGNO (oldequiv)]
6952 && (dead_or_set_p (insn,
6953 spill_reg_stored_to[REGNO (oldequiv)])
6954 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6956 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6958 /* Prevent normal processing of this reload. */
6960 /* Output a special code sequence for this case. */
6961 new_spill_reg_store[REGNO (reloadreg)]
6962 = inc_for_reload (reloadreg, oldequiv, rl->out,
6966 /* If we are reloading a pseudo-register that was set by the previous
6967 insn, see if we can get rid of that pseudo-register entirely
6968 by redirecting the previous insn into our reload register. */
6970 else if (optimize && REG_P (old)
6971 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6972 && dead_or_set_p (insn, old)
6973 /* This is unsafe if some other reload
6974 uses the same reg first. */
6975 && ! conflicts_with_override (reloadreg)
6976 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6977 rl->when_needed, old, rl->out, j, 0))
6979 rtx temp = PREV_INSN (insn);
6980 while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp)))
6981 temp = PREV_INSN (temp);
6983 && NONJUMP_INSN_P (temp)
6984 && GET_CODE (PATTERN (temp)) == SET
6985 && SET_DEST (PATTERN (temp)) == old
6986 /* Make sure we can access insn_operand_constraint. */
6987 && asm_noperands (PATTERN (temp)) < 0
6988 /* This is unsafe if operand occurs more than once in current
6989 insn. Perhaps some occurrences aren't reloaded. */
6990 && count_occurrences (PATTERN (insn), old, 0) == 1)
6992 rtx old = SET_DEST (PATTERN (temp));
6993 /* Store into the reload register instead of the pseudo. */
6994 SET_DEST (PATTERN (temp)) = reloadreg;
6996 /* Verify that resulting insn is valid. */
6997 extract_insn (temp);
6998 if (constrain_operands (1))
7000 /* If the previous insn is an output reload, the source is
7001 a reload register, and its spill_reg_store entry will
7002 contain the previous destination. This is now
7004 if (REG_P (SET_SRC (PATTERN (temp)))
7005 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
7007 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7008 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7011 /* If these are the only uses of the pseudo reg,
7012 pretend for GDB it lives in the reload reg we used. */
7013 if (REG_N_DEATHS (REGNO (old)) == 1
7014 && REG_N_SETS (REGNO (old)) == 1)
7016 reg_renumber[REGNO (old)] = REGNO (reloadreg);
7017 if (ira_conflicts_p)
7018 /* Inform IRA about the change. */
7019 ira_mark_allocation_change (REGNO (old));
7020 alter_reg (REGNO (old), -1, false);
7024 /* Adjust any debug insns between temp and insn. */
7025 while ((temp = NEXT_INSN (temp)) != insn)
7026 if (DEBUG_INSN_P (temp))
7027 replace_rtx (PATTERN (temp), old, reloadreg);
7029 gcc_assert (NOTE_P (temp));
7033 SET_DEST (PATTERN (temp)) = old;
7038 /* We can't do that, so output an insn to load RELOADREG. */
7040 /* If we have a secondary reload, pick up the secondary register
7041 and icode, if any. If OLDEQUIV and OLD are different or
7042 if this is an in-out reload, recompute whether or not we
7043 still need a secondary register and what the icode should
7044 be. If we still need a secondary register and the class or
7045 icode is different, go back to reloading from OLD if using
7046 OLDEQUIV means that we got the wrong type of register. We
7047 cannot have different class or icode due to an in-out reload
7048 because we don't make such reloads when both the input and
7049 output need secondary reload registers. */
7051 if (! special && rl->secondary_in_reload >= 0)
7053 rtx second_reload_reg = 0;
7054 rtx third_reload_reg = 0;
7055 int secondary_reload = rl->secondary_in_reload;
7056 rtx real_oldequiv = oldequiv;
7059 enum insn_code icode;
7060 enum insn_code tertiary_icode = CODE_FOR_nothing;
7062 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7063 and similarly for OLD.
7064 See comments in get_secondary_reload in reload.c. */
7065 /* If it is a pseudo that cannot be replaced with its
7066 equivalent MEM, we must fall back to reload_in, which
7067 will have all the necessary substitutions registered.
7068 Likewise for a pseudo that can't be replaced with its
7069 equivalent constant.
7071 Take extra care for subregs of such pseudos. Note that
7072 we cannot use reg_equiv_mem in this case because it is
7073 not in the right mode. */
7076 if (GET_CODE (tmp) == SUBREG)
7077 tmp = SUBREG_REG (tmp);
7079 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7080 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7081 || reg_equiv_constant[REGNO (tmp)] != 0))
7083 if (! reg_equiv_mem[REGNO (tmp)]
7084 || num_not_at_initial_offset
7085 || GET_CODE (oldequiv) == SUBREG)
7086 real_oldequiv = rl->in;
7088 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
7092 if (GET_CODE (tmp) == SUBREG)
7093 tmp = SUBREG_REG (tmp);
7095 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7096 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7097 || reg_equiv_constant[REGNO (tmp)] != 0))
7099 if (! reg_equiv_mem[REGNO (tmp)]
7100 || num_not_at_initial_offset
7101 || GET_CODE (old) == SUBREG)
7104 real_old = reg_equiv_mem[REGNO (tmp)];
7107 second_reload_reg = rld[secondary_reload].reg_rtx;
7108 if (rld[secondary_reload].secondary_in_reload >= 0)
7110 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7112 third_reload_reg = rld[tertiary_reload].reg_rtx;
7113 tertiary_icode = rld[secondary_reload].secondary_in_icode;
7114 /* We'd have to add more code for quartary reloads. */
7115 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7117 icode = rl->secondary_in_icode;
7119 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7120 || (rl->in != 0 && rl->out != 0))
7122 secondary_reload_info sri, sri2;
7123 enum reg_class new_class, new_t_class;
7125 sri.icode = CODE_FOR_nothing;
7126 sri.prev_sri = NULL;
7127 new_class = targetm.secondary_reload (1, real_oldequiv, rl->rclass,
7130 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7131 second_reload_reg = 0;
7132 else if (new_class == NO_REGS)
7134 if (reload_adjust_reg_for_icode (&second_reload_reg,
7136 (enum insn_code) sri.icode))
7138 icode = (enum insn_code) sri.icode;
7139 third_reload_reg = 0;
7144 real_oldequiv = real_old;
7147 else if (sri.icode != CODE_FOR_nothing)
7148 /* We currently lack a way to express this in reloads. */
7152 sri2.icode = CODE_FOR_nothing;
7153 sri2.prev_sri = &sri;
7154 new_t_class = targetm.secondary_reload (1, real_oldequiv,
7155 new_class, mode, &sri);
7156 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7158 if (reload_adjust_reg_for_temp (&second_reload_reg,
7162 third_reload_reg = 0;
7163 tertiary_icode = (enum insn_code) sri2.icode;
7168 real_oldequiv = real_old;
7171 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7173 rtx intermediate = second_reload_reg;
7175 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7177 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7181 second_reload_reg = intermediate;
7182 tertiary_icode = (enum insn_code) sri2.icode;
7187 real_oldequiv = real_old;
7190 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7192 rtx intermediate = second_reload_reg;
7194 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7196 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7199 second_reload_reg = intermediate;
7200 tertiary_icode = (enum insn_code) sri2.icode;
7205 real_oldequiv = real_old;
7210 /* This could be handled more intelligently too. */
7212 real_oldequiv = real_old;
7217 /* If we still need a secondary reload register, check
7218 to see if it is being used as a scratch or intermediate
7219 register and generate code appropriately. If we need
7220 a scratch register, use REAL_OLDEQUIV since the form of
7221 the insn may depend on the actual address if it is
7224 if (second_reload_reg)
7226 if (icode != CODE_FOR_nothing)
7228 /* We'd have to add extra code to handle this case. */
7229 gcc_assert (!third_reload_reg);
7231 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7232 second_reload_reg));
7237 /* See if we need a scratch register to load the
7238 intermediate register (a tertiary reload). */
7239 if (tertiary_icode != CODE_FOR_nothing)
7241 emit_insn ((GEN_FCN (tertiary_icode)
7242 (second_reload_reg, real_oldequiv,
7243 third_reload_reg)));
7245 else if (third_reload_reg)
7247 gen_reload (third_reload_reg, real_oldequiv,
7250 gen_reload (second_reload_reg, third_reload_reg,
7255 gen_reload (second_reload_reg, real_oldequiv,
7259 oldequiv = second_reload_reg;
7264 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7266 rtx real_oldequiv = oldequiv;
7268 if ((REG_P (oldequiv)
7269 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7270 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
7271 || reg_equiv_constant[REGNO (oldequiv)] != 0))
7272 || (GET_CODE (oldequiv) == SUBREG
7273 && REG_P (SUBREG_REG (oldequiv))
7274 && (REGNO (SUBREG_REG (oldequiv))
7275 >= FIRST_PSEUDO_REGISTER)
7276 && ((reg_equiv_memory_loc
7277 [REGNO (SUBREG_REG (oldequiv))] != 0)
7278 || (reg_equiv_constant
7279 [REGNO (SUBREG_REG (oldequiv))] != 0)))
7280 || (CONSTANT_P (oldequiv)
7281 && (PREFERRED_RELOAD_CLASS (oldequiv,
7282 REGNO_REG_CLASS (REGNO (reloadreg)))
7284 real_oldequiv = rl->in;
7285 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7289 if (flag_non_call_exceptions)
7290 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7292 /* End this sequence. */
7293 *where = get_insns ();
7296 /* Update reload_override_in so that delete_address_reloads_1
7297 can see the actual register usage. */
7299 reload_override_in[j] = oldequiv;
7302 /* Generate insns to for the output reload RL, which is for the insn described
7303 by CHAIN and has the number J. */
7305 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7309 rtx insn = chain->insn;
7312 enum machine_mode mode;
7316 if (rl->when_needed == RELOAD_OTHER)
7319 push_to_sequence (output_reload_insns[rl->opnum]);
7321 rl_reg_rtx = reload_reg_rtx_for_output[j];
7322 mode = GET_MODE (rl_reg_rtx);
7324 reloadreg = rl_reg_rtx;
7326 /* If we need two reload regs, set RELOADREG to the intermediate
7327 one, since it will be stored into OLD. We might need a secondary
7328 register only for an input reload, so check again here. */
7330 if (rl->secondary_out_reload >= 0)
7333 int secondary_reload = rl->secondary_out_reload;
7334 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7336 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7337 && reg_equiv_mem[REGNO (old)] != 0)
7338 real_old = reg_equiv_mem[REGNO (old)];
7340 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7342 rtx second_reloadreg = reloadreg;
7343 reloadreg = rld[secondary_reload].reg_rtx;
7345 /* See if RELOADREG is to be used as a scratch register
7346 or as an intermediate register. */
7347 if (rl->secondary_out_icode != CODE_FOR_nothing)
7349 /* We'd have to add extra code to handle this case. */
7350 gcc_assert (tertiary_reload < 0);
7352 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7353 (real_old, second_reloadreg, reloadreg)));
7358 /* See if we need both a scratch and intermediate reload
7361 enum insn_code tertiary_icode
7362 = rld[secondary_reload].secondary_out_icode;
7364 /* We'd have to add more code for quartary reloads. */
7365 gcc_assert (tertiary_reload < 0
7366 || rld[tertiary_reload].secondary_out_reload < 0);
7368 if (GET_MODE (reloadreg) != mode)
7369 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7371 if (tertiary_icode != CODE_FOR_nothing)
7373 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7376 /* Copy primary reload reg to secondary reload reg.
7377 (Note that these have been swapped above, then
7378 secondary reload reg to OLD using our insn.) */
7380 /* If REAL_OLD is a paradoxical SUBREG, remove it
7381 and try to put the opposite SUBREG on
7383 if (GET_CODE (real_old) == SUBREG
7384 && (GET_MODE_SIZE (GET_MODE (real_old))
7385 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7386 && 0 != (tem = gen_lowpart_common
7387 (GET_MODE (SUBREG_REG (real_old)),
7389 real_old = SUBREG_REG (real_old), reloadreg = tem;
7391 gen_reload (reloadreg, second_reloadreg,
7392 rl->opnum, rl->when_needed);
7393 emit_insn ((GEN_FCN (tertiary_icode)
7394 (real_old, reloadreg, third_reloadreg)));
7400 /* Copy between the reload regs here and then to
7403 gen_reload (reloadreg, second_reloadreg,
7404 rl->opnum, rl->when_needed);
7405 if (tertiary_reload >= 0)
7407 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7409 gen_reload (third_reloadreg, reloadreg,
7410 rl->opnum, rl->when_needed);
7411 reloadreg = third_reloadreg;
7418 /* Output the last reload insn. */
7423 /* Don't output the last reload if OLD is not the dest of
7424 INSN and is in the src and is clobbered by INSN. */
7425 if (! flag_expensive_optimizations
7427 || !(set = single_set (insn))
7428 || rtx_equal_p (old, SET_DEST (set))
7429 || !reg_mentioned_p (old, SET_SRC (set))
7430 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7431 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7432 gen_reload (old, reloadreg, rl->opnum,
7436 /* Look at all insns we emitted, just to be safe. */
7437 for (p = get_insns (); p; p = NEXT_INSN (p))
7440 rtx pat = PATTERN (p);
7442 /* If this output reload doesn't come from a spill reg,
7443 clear any memory of reloaded copies of the pseudo reg.
7444 If this output reload comes from a spill reg,
7445 reg_has_output_reload will make this do nothing. */
7446 note_stores (pat, forget_old_reloads_1, NULL);
7448 if (reg_mentioned_p (rl_reg_rtx, pat))
7450 rtx set = single_set (insn);
7451 if (reload_spill_index[j] < 0
7453 && SET_SRC (set) == rl_reg_rtx)
7455 int src = REGNO (SET_SRC (set));
7457 reload_spill_index[j] = src;
7458 SET_HARD_REG_BIT (reg_is_output_reload, src);
7459 if (find_regno_note (insn, REG_DEAD, src))
7460 SET_HARD_REG_BIT (reg_reloaded_died, src);
7462 if (HARD_REGISTER_P (rl_reg_rtx))
7464 int s = rl->secondary_out_reload;
7465 set = single_set (p);
7466 /* If this reload copies only to the secondary reload
7467 register, the secondary reload does the actual
7469 if (s >= 0 && set == NULL_RTX)
7470 /* We can't tell what function the secondary reload
7471 has and where the actual store to the pseudo is
7472 made; leave new_spill_reg_store alone. */
7475 && SET_SRC (set) == rl_reg_rtx
7476 && SET_DEST (set) == rld[s].reg_rtx)
7478 /* Usually the next instruction will be the
7479 secondary reload insn; if we can confirm
7480 that it is, setting new_spill_reg_store to
7481 that insn will allow an extra optimization. */
7482 rtx s_reg = rld[s].reg_rtx;
7483 rtx next = NEXT_INSN (p);
7484 rld[s].out = rl->out;
7485 rld[s].out_reg = rl->out_reg;
7486 set = single_set (next);
7487 if (set && SET_SRC (set) == s_reg
7488 && ! new_spill_reg_store[REGNO (s_reg)])
7490 SET_HARD_REG_BIT (reg_is_output_reload,
7492 new_spill_reg_store[REGNO (s_reg)] = next;
7496 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7501 if (rl->when_needed == RELOAD_OTHER)
7503 emit_insn (other_output_reload_insns[rl->opnum]);
7504 other_output_reload_insns[rl->opnum] = get_insns ();
7507 output_reload_insns[rl->opnum] = get_insns ();
7509 if (flag_non_call_exceptions)
7510 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7515 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7516 and has the number J. */
7518 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7520 rtx insn = chain->insn;
7521 rtx old = (rl->in && MEM_P (rl->in)
7522 ? rl->in_reg : rl->in);
7523 rtx reg_rtx = rl->reg_rtx;
7527 enum machine_mode mode;
7529 /* Determine the mode to reload in.
7530 This is very tricky because we have three to choose from.
7531 There is the mode the insn operand wants (rl->inmode).
7532 There is the mode of the reload register RELOADREG.
7533 There is the intrinsic mode of the operand, which we could find
7534 by stripping some SUBREGs.
7535 It turns out that RELOADREG's mode is irrelevant:
7536 we can change that arbitrarily.
7538 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7539 then the reload reg may not support QImode moves, so use SImode.
7540 If foo is in memory due to spilling a pseudo reg, this is safe,
7541 because the QImode value is in the least significant part of a
7542 slot big enough for a SImode. If foo is some other sort of
7543 memory reference, then it is impossible to reload this case,
7544 so previous passes had better make sure this never happens.
7546 Then consider a one-word union which has SImode and one of its
7547 members is a float, being fetched as (SUBREG:SF union:SI).
7548 We must fetch that as SFmode because we could be loading into
7549 a float-only register. In this case OLD's mode is correct.
7551 Consider an immediate integer: it has VOIDmode. Here we need
7552 to get a mode from something else.
7554 In some cases, there is a fourth mode, the operand's
7555 containing mode. If the insn specifies a containing mode for
7556 this operand, it overrides all others.
7558 I am not sure whether the algorithm here is always right,
7559 but it does the right things in those cases. */
7561 mode = GET_MODE (old);
7562 if (mode == VOIDmode)
7565 /* We cannot use gen_lowpart_common since it can do the wrong thing
7566 when REG_RTX has a multi-word mode. Note that REG_RTX must
7567 always be a REG here. */
7568 if (GET_MODE (reg_rtx) != mode)
7569 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7571 reload_reg_rtx_for_input[j] = reg_rtx;
7574 /* AUTO_INC reloads need to be handled even if inherited. We got an
7575 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7576 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7577 && ! rtx_equal_p (reg_rtx, old)
7579 emit_input_reload_insns (chain, rld + j, old, j);
7581 /* When inheriting a wider reload, we have a MEM in rl->in,
7582 e.g. inheriting a SImode output reload for
7583 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7584 if (optimize && reload_inherited[j] && rl->in
7586 && MEM_P (rl->in_reg)
7587 && reload_spill_index[j] >= 0
7588 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7589 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7591 /* If we are reloading a register that was recently stored in with an
7592 output-reload, see if we can prove there was
7593 actually no need to store the old value in it. */
7596 && (reload_inherited[j] || reload_override_in[j])
7599 && spill_reg_store[REGNO (reg_rtx)] != 0
7601 /* There doesn't seem to be any reason to restrict this to pseudos
7602 and doing so loses in the case where we are copying from a
7603 register of the wrong class. */
7604 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7606 /* The insn might have already some references to stackslots
7607 replaced by MEMs, while reload_out_reg still names the
7609 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7610 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7611 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7614 /* Do output reloading for reload RL, which is for the insn described by
7615 CHAIN and has the number J.
7616 ??? At some point we need to support handling output reloads of
7617 JUMP_INSNs or insns that set cc0. */
7619 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7622 rtx insn = chain->insn;
7623 /* If this is an output reload that stores something that is
7624 not loaded in this same reload, see if we can eliminate a previous
7626 rtx pseudo = rl->out_reg;
7627 rtx reg_rtx = rl->reg_rtx;
7629 if (rl->out && reg_rtx)
7631 enum machine_mode mode;
7633 /* Determine the mode to reload in.
7634 See comments above (for input reloading). */
7635 mode = GET_MODE (rl->out);
7636 if (mode == VOIDmode)
7638 /* VOIDmode should never happen for an output. */
7639 if (asm_noperands (PATTERN (insn)) < 0)
7640 /* It's the compiler's fault. */
7641 fatal_insn ("VOIDmode on an output", insn);
7642 error_for_asm (insn, "output operand is constant in %<asm%>");
7643 /* Prevent crash--use something we know is valid. */
7645 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7647 if (GET_MODE (reg_rtx) != mode)
7648 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7650 reload_reg_rtx_for_output[j] = reg_rtx;
7655 && ! rtx_equal_p (rl->in_reg, pseudo)
7656 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7657 && reg_last_reload_reg[REGNO (pseudo)])
7659 int pseudo_no = REGNO (pseudo);
7660 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7662 /* We don't need to test full validity of last_regno for
7663 inherit here; we only want to know if the store actually
7664 matches the pseudo. */
7665 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7666 && reg_reloaded_contents[last_regno] == pseudo_no
7667 && spill_reg_store[last_regno]
7668 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7669 delete_output_reload (insn, j, last_regno, reg_rtx);
7675 || rtx_equal_p (old, reg_rtx))
7678 /* An output operand that dies right away does need a reload,
7679 but need not be copied from it. Show the new location in the
7681 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7682 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7684 XEXP (note, 0) = reg_rtx;
7687 /* Likewise for a SUBREG of an operand that dies. */
7688 else if (GET_CODE (old) == SUBREG
7689 && REG_P (SUBREG_REG (old))
7690 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7693 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7696 else if (GET_CODE (old) == SCRATCH)
7697 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7698 but we don't want to make an output reload. */
7701 /* If is a JUMP_INSN, we can't support output reloads yet. */
7702 gcc_assert (NONJUMP_INSN_P (insn));
7704 emit_output_reload_insns (chain, rld + j, j);
7707 /* A reload copies values of MODE from register SRC to register DEST.
7708 Return true if it can be treated for inheritance purposes like a
7709 group of reloads, each one reloading a single hard register. The
7710 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7711 occupy the same number of hard registers. */
7714 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
7715 int src ATTRIBUTE_UNUSED,
7716 enum machine_mode mode ATTRIBUTE_UNUSED)
7718 #ifdef CANNOT_CHANGE_MODE_CLASS
7719 return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
7720 && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
7726 /* Output insns to reload values in and out of the chosen reload regs. */
7729 emit_reload_insns (struct insn_chain *chain)
7731 rtx insn = chain->insn;
7735 CLEAR_HARD_REG_SET (reg_reloaded_died);
7737 for (j = 0; j < reload_n_operands; j++)
7738 input_reload_insns[j] = input_address_reload_insns[j]
7739 = inpaddr_address_reload_insns[j]
7740 = output_reload_insns[j] = output_address_reload_insns[j]
7741 = outaddr_address_reload_insns[j]
7742 = other_output_reload_insns[j] = 0;
7743 other_input_address_reload_insns = 0;
7744 other_input_reload_insns = 0;
7745 operand_reload_insns = 0;
7746 other_operand_reload_insns = 0;
7748 /* Dump reloads into the dump file. */
7751 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7752 debug_reload_to_stream (dump_file);
7755 /* Now output the instructions to copy the data into and out of the
7756 reload registers. Do these in the order that the reloads were reported,
7757 since reloads of base and index registers precede reloads of operands
7758 and the operands may need the base and index registers reloaded. */
7760 for (j = 0; j < n_reloads; j++)
7762 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
7766 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
7767 new_spill_reg_store[i] = 0;
7770 do_input_reload (chain, rld + j, j);
7771 do_output_reload (chain, rld + j, j);
7774 /* Now write all the insns we made for reloads in the order expected by
7775 the allocation functions. Prior to the insn being reloaded, we write
7776 the following reloads:
7778 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7780 RELOAD_OTHER reloads.
7782 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7783 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7784 RELOAD_FOR_INPUT reload for the operand.
7786 RELOAD_FOR_OPADDR_ADDRS reloads.
7788 RELOAD_FOR_OPERAND_ADDRESS reloads.
7790 After the insn being reloaded, we write the following:
7792 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7793 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7794 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7795 reloads for the operand. The RELOAD_OTHER output reloads are
7796 output in descending order by reload number. */
7798 emit_insn_before (other_input_address_reload_insns, insn);
7799 emit_insn_before (other_input_reload_insns, insn);
7801 for (j = 0; j < reload_n_operands; j++)
7803 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7804 emit_insn_before (input_address_reload_insns[j], insn);
7805 emit_insn_before (input_reload_insns[j], insn);
7808 emit_insn_before (other_operand_reload_insns, insn);
7809 emit_insn_before (operand_reload_insns, insn);
7811 for (j = 0; j < reload_n_operands; j++)
7813 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7814 x = emit_insn_after (output_address_reload_insns[j], x);
7815 x = emit_insn_after (output_reload_insns[j], x);
7816 emit_insn_after (other_output_reload_insns[j], x);
7819 /* For all the spill regs newly reloaded in this instruction,
7820 record what they were reloaded from, so subsequent instructions
7821 can inherit the reloads.
7823 Update spill_reg_store for the reloads of this insn.
7824 Copy the elements that were updated in the loop above. */
7826 for (j = 0; j < n_reloads; j++)
7828 int r = reload_order[j];
7829 int i = reload_spill_index[r];
7831 /* If this is a non-inherited input reload from a pseudo, we must
7832 clear any memory of a previous store to the same pseudo. Only do
7833 something if there will not be an output reload for the pseudo
7835 if (rld[r].in_reg != 0
7836 && ! (reload_inherited[r] || reload_override_in[r]))
7838 rtx reg = rld[r].in_reg;
7840 if (GET_CODE (reg) == SUBREG)
7841 reg = SUBREG_REG (reg);
7844 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7845 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7847 int nregno = REGNO (reg);
7849 if (reg_last_reload_reg[nregno])
7851 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7853 if (reg_reloaded_contents[last_regno] == nregno)
7854 spill_reg_store[last_regno] = 0;
7859 /* I is nonneg if this reload used a register.
7860 If rld[r].reg_rtx is 0, this is an optional reload
7861 that we opted to ignore. */
7863 if (i >= 0 && rld[r].reg_rtx != 0)
7865 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7868 /* For a multi register reload, we need to check if all or part
7869 of the value lives to the end. */
7870 for (k = 0; k < nr; k++)
7871 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7872 rld[r].when_needed))
7873 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7875 /* Maybe the spill reg contains a copy of reload_out. */
7877 && (REG_P (rld[r].out)
7881 || REG_P (rld[r].out_reg)))
7884 enum machine_mode mode;
7887 reg = reload_reg_rtx_for_output[r];
7888 mode = GET_MODE (reg);
7889 regno = REGNO (reg);
7890 nregs = hard_regno_nregs[regno][mode];
7891 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7892 rld[r].when_needed))
7894 rtx out = (REG_P (rld[r].out)
7898 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7899 int out_regno = REGNO (out);
7900 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
7901 : hard_regno_nregs[out_regno][mode]);
7904 spill_reg_store[regno] = new_spill_reg_store[regno];
7905 spill_reg_stored_to[regno] = out;
7906 reg_last_reload_reg[out_regno] = reg;
7908 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
7909 && nregs == out_nregs
7910 && inherit_piecemeal_p (out_regno, regno, mode));
7912 /* If OUT_REGNO is a hard register, it may occupy more than
7913 one register. If it does, say what is in the
7914 rest of the registers assuming that both registers
7915 agree on how many words the object takes. If not,
7916 invalidate the subsequent registers. */
7918 if (HARD_REGISTER_NUM_P (out_regno))
7919 for (k = 1; k < out_nregs; k++)
7920 reg_last_reload_reg[out_regno + k]
7921 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7923 /* Now do the inverse operation. */
7924 for (k = 0; k < nregs; k++)
7926 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
7927 reg_reloaded_contents[regno + k]
7928 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
7931 reg_reloaded_insn[regno + k] = insn;
7932 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
7933 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
7934 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7937 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7942 /* Maybe the spill reg contains a copy of reload_in. Only do
7943 something if there will not be an output reload for
7944 the register being reloaded. */
7945 else if (rld[r].out_reg == 0
7947 && ((REG_P (rld[r].in)
7948 && !HARD_REGISTER_P (rld[r].in)
7949 && !REGNO_REG_SET_P (®_has_output_reload,
7951 || (REG_P (rld[r].in_reg)
7952 && !REGNO_REG_SET_P (®_has_output_reload,
7953 REGNO (rld[r].in_reg))))
7954 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
7957 enum machine_mode mode;
7960 reg = reload_reg_rtx_for_input[r];
7961 mode = GET_MODE (reg);
7962 regno = REGNO (reg);
7963 nregs = hard_regno_nregs[regno][mode];
7964 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7965 rld[r].when_needed))
7972 if (REG_P (rld[r].in)
7973 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7975 else if (REG_P (rld[r].in_reg))
7978 in = XEXP (rld[r].in_reg, 0);
7979 in_regno = REGNO (in);
7981 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
7982 : hard_regno_nregs[in_regno][mode]);
7984 reg_last_reload_reg[in_regno] = reg;
7986 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
7987 && nregs == in_nregs
7988 && inherit_piecemeal_p (regno, in_regno, mode));
7990 if (HARD_REGISTER_NUM_P (in_regno))
7991 for (k = 1; k < in_nregs; k++)
7992 reg_last_reload_reg[in_regno + k]
7993 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7995 /* Unless we inherited this reload, show we haven't
7996 recently done a store.
7997 Previous stores of inherited auto_inc expressions
7998 also have to be discarded. */
7999 if (! reload_inherited[r]
8000 || (rld[r].out && ! rld[r].out_reg))
8001 spill_reg_store[regno] = 0;
8003 for (k = 0; k < nregs; k++)
8005 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8006 reg_reloaded_contents[regno + k]
8007 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
8010 reg_reloaded_insn[regno + k] = insn;
8011 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8012 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8013 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8016 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8023 /* The following if-statement was #if 0'd in 1.34 (or before...).
8024 It's reenabled in 1.35 because supposedly nothing else
8025 deals with this problem. */
8027 /* If a register gets output-reloaded from a non-spill register,
8028 that invalidates any previous reloaded copy of it.
8029 But forget_old_reloads_1 won't get to see it, because
8030 it thinks only about the original insn. So invalidate it here.
8031 Also do the same thing for RELOAD_OTHER constraints where the
8032 output is discarded. */
8034 && ((rld[r].out != 0
8035 && (REG_P (rld[r].out)
8036 || (MEM_P (rld[r].out)
8037 && REG_P (rld[r].out_reg))))
8038 || (rld[r].out == 0 && rld[r].out_reg
8039 && REG_P (rld[r].out_reg))))
8041 rtx out = ((rld[r].out && REG_P (rld[r].out))
8042 ? rld[r].out : rld[r].out_reg);
8043 int out_regno = REGNO (out);
8044 enum machine_mode mode = GET_MODE (out);
8046 /* REG_RTX is now set or clobbered by the main instruction.
8047 As the comment above explains, forget_old_reloads_1 only
8048 sees the original instruction, and there is no guarantee
8049 that the original instruction also clobbered REG_RTX.
8050 For example, if find_reloads sees that the input side of
8051 a matched operand pair dies in this instruction, it may
8052 use the input register as the reload register.
8054 Calling forget_old_reloads_1 is a waste of effort if
8055 REG_RTX is also the output register.
8057 If we know that REG_RTX holds the value of a pseudo
8058 register, the code after the call will record that fact. */
8059 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8060 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8062 if (!HARD_REGISTER_NUM_P (out_regno))
8064 rtx src_reg, store_insn = NULL_RTX;
8066 reg_last_reload_reg[out_regno] = 0;
8068 /* If we can find a hard register that is stored, record
8069 the storing insn so that we may delete this insn with
8070 delete_output_reload. */
8071 src_reg = reload_reg_rtx_for_output[r];
8073 /* If this is an optional reload, try to find the source reg
8074 from an input reload. */
8077 rtx set = single_set (insn);
8078 if (set && SET_DEST (set) == rld[r].out)
8082 src_reg = SET_SRC (set);
8084 for (k = 0; k < n_reloads; k++)
8086 if (rld[k].in == src_reg)
8088 src_reg = reload_reg_rtx_for_input[k];
8095 store_insn = new_spill_reg_store[REGNO (src_reg)];
8096 if (src_reg && REG_P (src_reg)
8097 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8099 int src_regno, src_nregs, k;
8102 gcc_assert (GET_MODE (src_reg) == mode);
8103 src_regno = REGNO (src_reg);
8104 src_nregs = hard_regno_nregs[src_regno][mode];
8105 /* The place where to find a death note varies with
8106 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8107 necessarily checked exactly in the code that moves
8108 notes, so just check both locations. */
8109 note = find_regno_note (insn, REG_DEAD, src_regno);
8110 if (! note && store_insn)
8111 note = find_regno_note (store_insn, REG_DEAD, src_regno);
8112 for (k = 0; k < src_nregs; k++)
8114 spill_reg_store[src_regno + k] = store_insn;
8115 spill_reg_stored_to[src_regno + k] = out;
8116 reg_reloaded_contents[src_regno + k] = out_regno;
8117 reg_reloaded_insn[src_regno + k] = store_insn;
8118 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8119 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8120 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
8122 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8125 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8127 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8129 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8131 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8133 reg_last_reload_reg[out_regno] = src_reg;
8134 /* We have to set reg_has_output_reload here, or else
8135 forget_old_reloads_1 will clear reg_last_reload_reg
8137 SET_REGNO_REG_SET (®_has_output_reload,
8143 int k, out_nregs = hard_regno_nregs[out_regno][mode];
8145 for (k = 0; k < out_nregs; k++)
8146 reg_last_reload_reg[out_regno + k] = 0;
8150 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8153 /* Go through the motions to emit INSN and test if it is strictly valid.
8154 Return the emitted insn if valid, else return NULL. */
8157 emit_insn_if_valid_for_reload (rtx insn)
8159 rtx last = get_last_insn ();
8162 insn = emit_insn (insn);
8163 code = recog_memoized (insn);
8167 extract_insn (insn);
8168 /* We want constrain operands to treat this insn strictly in its
8169 validity determination, i.e., the way it would after reload has
8171 if (constrain_operands (1))
8175 delete_insns_since (last);
8179 /* Emit code to perform a reload from IN (which may be a reload register) to
8180 OUT (which may also be a reload register). IN or OUT is from operand
8181 OPNUM with reload type TYPE.
8183 Returns first insn emitted. */
8186 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8188 rtx last = get_last_insn ();
8191 /* If IN is a paradoxical SUBREG, remove it and try to put the
8192 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8193 if (GET_CODE (in) == SUBREG
8194 && (GET_MODE_SIZE (GET_MODE (in))
8195 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
8196 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
8197 in = SUBREG_REG (in), out = tem;
8198 else if (GET_CODE (out) == SUBREG
8199 && (GET_MODE_SIZE (GET_MODE (out))
8200 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
8201 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
8202 out = SUBREG_REG (out), in = tem;
8204 /* How to do this reload can get quite tricky. Normally, we are being
8205 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8206 register that didn't get a hard register. In that case we can just
8207 call emit_move_insn.
8209 We can also be asked to reload a PLUS that adds a register or a MEM to
8210 another register, constant or MEM. This can occur during frame pointer
8211 elimination and while reloading addresses. This case is handled by
8212 trying to emit a single insn to perform the add. If it is not valid,
8213 we use a two insn sequence.
8215 Or we can be asked to reload an unary operand that was a fragment of
8216 an addressing mode, into a register. If it isn't recognized as-is,
8217 we try making the unop operand and the reload-register the same:
8218 (set reg:X (unop:X expr:Y))
8219 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8221 Finally, we could be called to handle an 'o' constraint by putting
8222 an address into a register. In that case, we first try to do this
8223 with a named pattern of "reload_load_address". If no such pattern
8224 exists, we just emit a SET insn and hope for the best (it will normally
8225 be valid on machines that use 'o').
8227 This entire process is made complex because reload will never
8228 process the insns we generate here and so we must ensure that
8229 they will fit their constraints and also by the fact that parts of
8230 IN might be being reloaded separately and replaced with spill registers.
8231 Because of this, we are, in some sense, just guessing the right approach
8232 here. The one listed above seems to work.
8234 ??? At some point, this whole thing needs to be rethought. */
8236 if (GET_CODE (in) == PLUS
8237 && (REG_P (XEXP (in, 0))
8238 || GET_CODE (XEXP (in, 0)) == SUBREG
8239 || MEM_P (XEXP (in, 0)))
8240 && (REG_P (XEXP (in, 1))
8241 || GET_CODE (XEXP (in, 1)) == SUBREG
8242 || CONSTANT_P (XEXP (in, 1))
8243 || MEM_P (XEXP (in, 1))))
8245 /* We need to compute the sum of a register or a MEM and another
8246 register, constant, or MEM, and put it into the reload
8247 register. The best possible way of doing this is if the machine
8248 has a three-operand ADD insn that accepts the required operands.
8250 The simplest approach is to try to generate such an insn and see if it
8251 is recognized and matches its constraints. If so, it can be used.
8253 It might be better not to actually emit the insn unless it is valid,
8254 but we need to pass the insn as an operand to `recog' and
8255 `extract_insn' and it is simpler to emit and then delete the insn if
8256 not valid than to dummy things up. */
8258 rtx op0, op1, tem, insn;
8261 op0 = find_replacement (&XEXP (in, 0));
8262 op1 = find_replacement (&XEXP (in, 1));
8264 /* Since constraint checking is strict, commutativity won't be
8265 checked, so we need to do that here to avoid spurious failure
8266 if the add instruction is two-address and the second operand
8267 of the add is the same as the reload reg, which is frequently
8268 the case. If the insn would be A = B + A, rearrange it so
8269 it will be A = A + B as constrain_operands expects. */
8271 if (REG_P (XEXP (in, 1))
8272 && REGNO (out) == REGNO (XEXP (in, 1)))
8273 tem = op0, op0 = op1, op1 = tem;
8275 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8276 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8278 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8282 /* If that failed, we must use a conservative two-insn sequence.
8284 Use a move to copy one operand into the reload register. Prefer
8285 to reload a constant, MEM or pseudo since the move patterns can
8286 handle an arbitrary operand. If OP1 is not a constant, MEM or
8287 pseudo and OP1 is not a valid operand for an add instruction, then
8290 After reloading one of the operands into the reload register, add
8291 the reload register to the output register.
8293 If there is another way to do this for a specific machine, a
8294 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8297 code = (int) optab_handler (add_optab, GET_MODE (out))->insn_code;
8299 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8301 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8302 || (code != CODE_FOR_nothing
8303 && ! ((*insn_data[code].operand[2].predicate)
8304 (op1, insn_data[code].operand[2].mode))))
8305 tem = op0, op0 = op1, op1 = tem;
8307 gen_reload (out, op0, opnum, type);
8309 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8310 This fixes a problem on the 32K where the stack pointer cannot
8311 be used as an operand of an add insn. */
8313 if (rtx_equal_p (op0, op1))
8316 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8319 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8320 set_unique_reg_note (insn, REG_EQUIV, in);
8324 /* If that failed, copy the address register to the reload register.
8325 Then add the constant to the reload register. */
8327 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8328 gen_reload (out, op1, opnum, type);
8329 insn = emit_insn (gen_add2_insn (out, op0));
8330 set_unique_reg_note (insn, REG_EQUIV, in);
8333 #ifdef SECONDARY_MEMORY_NEEDED
8334 /* If we need a memory location to do the move, do it that way. */
8335 else if ((REG_P (in)
8336 || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
8337 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
8339 || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
8340 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
8341 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
8342 REGNO_REG_CLASS (reg_or_subregno (out)),
8345 /* Get the memory to use and rewrite both registers to its mode. */
8346 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8348 if (GET_MODE (loc) != GET_MODE (out))
8349 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
8351 if (GET_MODE (loc) != GET_MODE (in))
8352 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
8354 gen_reload (loc, in, opnum, type);
8355 gen_reload (out, loc, opnum, type);
8358 else if (REG_P (out) && UNARY_P (in))
8365 op1 = find_replacement (&XEXP (in, 0));
8366 if (op1 != XEXP (in, 0))
8367 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8369 /* First, try a plain SET. */
8370 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8374 /* If that failed, move the inner operand to the reload
8375 register, and try the same unop with the inner expression
8376 replaced with the reload register. */
8378 if (GET_MODE (op1) != GET_MODE (out))
8379 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8383 gen_reload (out_moded, op1, opnum, type);
8386 = gen_rtx_SET (VOIDmode, out,
8387 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8389 insn = emit_insn_if_valid_for_reload (insn);
8392 set_unique_reg_note (insn, REG_EQUIV, in);
8396 fatal_insn ("Failure trying to reload:", set);
8398 /* If IN is a simple operand, use gen_move_insn. */
8399 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8401 tem = emit_insn (gen_move_insn (out, in));
8402 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8403 mark_jump_label (in, tem, 0);
8406 #ifdef HAVE_reload_load_address
8407 else if (HAVE_reload_load_address)
8408 emit_insn (gen_reload_load_address (out, in));
8411 /* Otherwise, just write (set OUT IN) and hope for the best. */
8413 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8415 /* Return the first insn emitted.
8416 We can not just return get_last_insn, because there may have
8417 been multiple instructions emitted. Also note that gen_move_insn may
8418 emit more than one insn itself, so we can not assume that there is one
8419 insn emitted per emit_insn_before call. */
8421 return last ? NEXT_INSN (last) : get_insns ();
8424 /* Delete a previously made output-reload whose result we now believe
8425 is not needed. First we double-check.
8427 INSN is the insn now being processed.
8428 LAST_RELOAD_REG is the hard register number for which we want to delete
8429 the last output reload.
8430 J is the reload-number that originally used REG. The caller has made
8431 certain that reload J doesn't use REG any longer for input.
8432 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8435 delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg)
8437 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8438 rtx reg = spill_reg_stored_to[last_reload_reg];
8441 int n_inherited = 0;
8445 /* It is possible that this reload has been only used to set another reload
8446 we eliminated earlier and thus deleted this instruction too. */
8447 if (INSN_DELETED_P (output_reload_insn))
8450 /* Get the raw pseudo-register referred to. */
8452 while (GET_CODE (reg) == SUBREG)
8453 reg = SUBREG_REG (reg);
8454 substed = reg_equiv_memory_loc[REGNO (reg)];
8456 /* This is unsafe if the operand occurs more often in the current
8457 insn than it is inherited. */
8458 for (k = n_reloads - 1; k >= 0; k--)
8460 rtx reg2 = rld[k].in;
8463 if (MEM_P (reg2) || reload_override_in[k])
8464 reg2 = rld[k].in_reg;
8466 if (rld[k].out && ! rld[k].out_reg)
8467 reg2 = XEXP (rld[k].in_reg, 0);
8469 while (GET_CODE (reg2) == SUBREG)
8470 reg2 = SUBREG_REG (reg2);
8471 if (rtx_equal_p (reg2, reg))
8473 if (reload_inherited[k] || reload_override_in[k] || k == j)
8479 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8480 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8481 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8484 n_occurrences += count_occurrences (PATTERN (insn),
8485 eliminate_regs (substed, VOIDmode,
8487 for (i1 = reg_equiv_alt_mem_list[REGNO (reg)]; i1; i1 = XEXP (i1, 1))
8489 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8490 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8492 if (n_occurrences > n_inherited)
8495 /* If the pseudo-reg we are reloading is no longer referenced
8496 anywhere between the store into it and here,
8497 and we're within the same basic block, then the value can only
8498 pass through the reload reg and end up here.
8499 Otherwise, give up--return. */
8500 for (i1 = NEXT_INSN (output_reload_insn);
8501 i1 != insn; i1 = NEXT_INSN (i1))
8503 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8505 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8506 && reg_mentioned_p (reg, PATTERN (i1)))
8508 /* If this is USE in front of INSN, we only have to check that
8509 there are no more references than accounted for by inheritance. */
8510 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8512 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8513 i1 = NEXT_INSN (i1);
8515 if (n_occurrences <= n_inherited && i1 == insn)
8521 /* We will be deleting the insn. Remove the spill reg information. */
8522 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8524 spill_reg_store[last_reload_reg + k] = 0;
8525 spill_reg_stored_to[last_reload_reg + k] = 0;
8528 /* The caller has already checked that REG dies or is set in INSN.
8529 It has also checked that we are optimizing, and thus some
8530 inaccuracies in the debugging information are acceptable.
8531 So we could just delete output_reload_insn. But in some cases
8532 we can improve the debugging information without sacrificing
8533 optimization - maybe even improving the code: See if the pseudo
8534 reg has been completely replaced with reload regs. If so, delete
8535 the store insn and forget we had a stack slot for the pseudo. */
8536 if (rld[j].out != rld[j].in
8537 && REG_N_DEATHS (REGNO (reg)) == 1
8538 && REG_N_SETS (REGNO (reg)) == 1
8539 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8540 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8544 /* We know that it was used only between here and the beginning of
8545 the current basic block. (We also know that the last use before
8546 INSN was the output reload we are thinking of deleting, but never
8547 mind that.) Search that range; see if any ref remains. */
8548 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8550 rtx set = single_set (i2);
8552 /* Uses which just store in the pseudo don't count,
8553 since if they are the only uses, they are dead. */
8554 if (set != 0 && SET_DEST (set) == reg)
8559 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8560 && reg_mentioned_p (reg, PATTERN (i2)))
8562 /* Some other ref remains; just delete the output reload we
8564 delete_address_reloads (output_reload_insn, insn);
8565 delete_insn (output_reload_insn);
8570 /* Delete the now-dead stores into this pseudo. Note that this
8571 loop also takes care of deleting output_reload_insn. */
8572 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8574 rtx set = single_set (i2);
8576 if (set != 0 && SET_DEST (set) == reg)
8578 delete_address_reloads (i2, insn);
8586 /* For the debugging info, say the pseudo lives in this reload reg. */
8587 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8588 if (ira_conflicts_p)
8589 /* Inform IRA about the change. */
8590 ira_mark_allocation_change (REGNO (reg));
8591 alter_reg (REGNO (reg), -1, false);
8595 delete_address_reloads (output_reload_insn, insn);
8596 delete_insn (output_reload_insn);
8600 /* We are going to delete DEAD_INSN. Recursively delete loads of
8601 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8602 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8604 delete_address_reloads (rtx dead_insn, rtx current_insn)
8606 rtx set = single_set (dead_insn);
8607 rtx set2, dst, prev, next;
8610 rtx dst = SET_DEST (set);
8612 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8614 /* If we deleted the store from a reloaded post_{in,de}c expression,
8615 we can delete the matching adds. */
8616 prev = PREV_INSN (dead_insn);
8617 next = NEXT_INSN (dead_insn);
8618 if (! prev || ! next)
8620 set = single_set (next);
8621 set2 = single_set (prev);
8623 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8624 || !CONST_INT_P (XEXP (SET_SRC (set), 1))
8625 || !CONST_INT_P (XEXP (SET_SRC (set2), 1)))
8627 dst = SET_DEST (set);
8628 if (! rtx_equal_p (dst, SET_DEST (set2))
8629 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8630 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8631 || (INTVAL (XEXP (SET_SRC (set), 1))
8632 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8634 delete_related_insns (prev);
8635 delete_related_insns (next);
8638 /* Subfunction of delete_address_reloads: process registers found in X. */
8640 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8642 rtx prev, set, dst, i2;
8644 enum rtx_code code = GET_CODE (x);
8648 const char *fmt = GET_RTX_FORMAT (code);
8649 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8652 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8653 else if (fmt[i] == 'E')
8655 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8656 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8663 if (spill_reg_order[REGNO (x)] < 0)
8666 /* Scan backwards for the insn that sets x. This might be a way back due
8668 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8670 code = GET_CODE (prev);
8671 if (code == CODE_LABEL || code == JUMP_INSN)
8675 if (reg_set_p (x, PATTERN (prev)))
8677 if (reg_referenced_p (x, PATTERN (prev)))
8680 if (! prev || INSN_UID (prev) < reload_first_uid)
8682 /* Check that PREV only sets the reload register. */
8683 set = single_set (prev);
8686 dst = SET_DEST (set);
8688 || ! rtx_equal_p (dst, x))
8690 if (! reg_set_p (dst, PATTERN (dead_insn)))
8692 /* Check if DST was used in a later insn -
8693 it might have been inherited. */
8694 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8700 if (reg_referenced_p (dst, PATTERN (i2)))
8702 /* If there is a reference to the register in the current insn,
8703 it might be loaded in a non-inherited reload. If no other
8704 reload uses it, that means the register is set before
8706 if (i2 == current_insn)
8708 for (j = n_reloads - 1; j >= 0; j--)
8709 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8710 || reload_override_in[j] == dst)
8712 for (j = n_reloads - 1; j >= 0; j--)
8713 if (rld[j].in && rld[j].reg_rtx == dst)
8722 /* If DST is still live at CURRENT_INSN, check if it is used for
8723 any reload. Note that even if CURRENT_INSN sets DST, we still
8724 have to check the reloads. */
8725 if (i2 == current_insn)
8727 for (j = n_reloads - 1; j >= 0; j--)
8728 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8729 || reload_override_in[j] == dst)
8731 /* ??? We can't finish the loop here, because dst might be
8732 allocated to a pseudo in this block if no reload in this
8733 block needs any of the classes containing DST - see
8734 spill_hard_reg. There is no easy way to tell this, so we
8735 have to scan till the end of the basic block. */
8737 if (reg_set_p (dst, PATTERN (i2)))
8741 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8742 reg_reloaded_contents[REGNO (dst)] = -1;
8746 /* Output reload-insns to reload VALUE into RELOADREG.
8747 VALUE is an autoincrement or autodecrement RTX whose operand
8748 is a register or memory location;
8749 so reloading involves incrementing that location.
8750 IN is either identical to VALUE, or some cheaper place to reload from.
8752 INC_AMOUNT is the number to increment or decrement by (always positive).
8753 This cannot be deduced from VALUE.
8755 Return the instruction that stores into RELOADREG. */
8758 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8760 /* REG or MEM to be copied and incremented. */
8761 rtx incloc = find_replacement (&XEXP (value, 0));
8762 /* Nonzero if increment after copying. */
8763 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8764 || GET_CODE (value) == POST_MODIFY);
8770 rtx real_in = in == value ? incloc : in;
8772 /* No hard register is equivalent to this register after
8773 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8774 we could inc/dec that register as well (maybe even using it for
8775 the source), but I'm not sure it's worth worrying about. */
8777 reg_last_reload_reg[REGNO (incloc)] = 0;
8779 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8781 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8782 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8786 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8787 inc_amount = -inc_amount;
8789 inc = GEN_INT (inc_amount);
8792 /* If this is post-increment, first copy the location to the reload reg. */
8793 if (post && real_in != reloadreg)
8794 emit_insn (gen_move_insn (reloadreg, real_in));
8798 /* See if we can directly increment INCLOC. Use a method similar to
8799 that in gen_reload. */
8801 last = get_last_insn ();
8802 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8803 gen_rtx_PLUS (GET_MODE (incloc),
8806 code = recog_memoized (add_insn);
8809 extract_insn (add_insn);
8810 if (constrain_operands (1))
8812 /* If this is a pre-increment and we have incremented the value
8813 where it lives, copy the incremented value to RELOADREG to
8814 be used as an address. */
8817 emit_insn (gen_move_insn (reloadreg, incloc));
8822 delete_insns_since (last);
8825 /* If couldn't do the increment directly, must increment in RELOADREG.
8826 The way we do this depends on whether this is pre- or post-increment.
8827 For pre-increment, copy INCLOC to the reload register, increment it
8828 there, then save back. */
8832 if (in != reloadreg)
8833 emit_insn (gen_move_insn (reloadreg, real_in));
8834 emit_insn (gen_add2_insn (reloadreg, inc));
8835 store = emit_insn (gen_move_insn (incloc, reloadreg));
8840 Because this might be a jump insn or a compare, and because RELOADREG
8841 may not be available after the insn in an input reload, we must do
8842 the incrementation before the insn being reloaded for.
8844 We have already copied IN to RELOADREG. Increment the copy in
8845 RELOADREG, save that back, then decrement RELOADREG so it has
8846 the original value. */
8848 emit_insn (gen_add2_insn (reloadreg, inc));
8849 store = emit_insn (gen_move_insn (incloc, reloadreg));
8850 if (CONST_INT_P (inc))
8851 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
8853 emit_insn (gen_sub2_insn (reloadreg, inc));
8861 add_auto_inc_notes (rtx insn, rtx x)
8863 enum rtx_code code = GET_CODE (x);
8867 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8869 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
8873 /* Scan all the operand sub-expressions. */
8874 fmt = GET_RTX_FORMAT (code);
8875 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8878 add_auto_inc_notes (insn, XEXP (x, i));
8879 else if (fmt[i] == 'E')
8880 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8881 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8886 /* This is used by reload pass, that does emit some instructions after
8887 abnormal calls moving basic block end, but in fact it wants to emit
8888 them on the edge. Looks for abnormal call edges, find backward the
8889 proper call and fix the damage.
8891 Similar handle instructions throwing exceptions internally. */
8893 fixup_abnormal_edges (void)
8895 bool inserted = false;
8903 /* Look for cases we are interested in - calls or instructions causing
8905 FOR_EACH_EDGE (e, ei, bb->succs)
8907 if (e->flags & EDGE_ABNORMAL_CALL)
8909 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8910 == (EDGE_ABNORMAL | EDGE_EH))
8913 if (e && !CALL_P (BB_END (bb))
8914 && !can_throw_internal (BB_END (bb)))
8918 /* Get past the new insns generated. Allow notes, as the insns
8919 may be already deleted. */
8921 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8922 && !can_throw_internal (insn)
8923 && insn != BB_HEAD (bb))
8924 insn = PREV_INSN (insn);
8926 if (CALL_P (insn) || can_throw_internal (insn))
8930 stop = NEXT_INSN (BB_END (bb));
8932 insn = NEXT_INSN (insn);
8934 FOR_EACH_EDGE (e, ei, bb->succs)
8935 if (e->flags & EDGE_FALLTHRU)
8938 while (insn && insn != stop)
8940 next = NEXT_INSN (insn);
8945 /* Sometimes there's still the return value USE.
8946 If it's placed after a trapping call (i.e. that
8947 call is the last insn anyway), we have no fallthru
8948 edge. Simply delete this use and don't try to insert
8949 on the non-existent edge. */
8950 if (GET_CODE (PATTERN (insn)) != USE)
8952 /* We're not deleting it, we're moving it. */
8953 INSN_DELETED_P (insn) = 0;
8954 PREV_INSN (insn) = NULL_RTX;
8955 NEXT_INSN (insn) = NULL_RTX;
8957 insert_insn_on_edge (insn, e);
8961 else if (!BARRIER_P (insn))
8962 set_block_for_insn (insn, NULL);
8967 /* It may be that we don't find any such trapping insn. In this
8968 case we discovered quite late that the insn that had been
8969 marked as can_throw_internal in fact couldn't trap at all.
8970 So we should in fact delete the EH edges out of the block. */
8972 purge_dead_edges (bb);
8976 /* We've possibly turned single trapping insn into multiple ones. */
8977 if (flag_non_call_exceptions)
8980 blocks = sbitmap_alloc (last_basic_block);
8981 sbitmap_ones (blocks);
8982 find_many_sub_basic_blocks (blocks);
8983 sbitmap_free (blocks);
8987 commit_edge_insertions ();
8989 #ifdef ENABLE_CHECKING
8990 /* Verify that we didn't turn one trapping insn into many, and that
8991 we found and corrected all of the problems wrt fixups on the
8993 verify_flow_info ();
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