1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "rtl-error.h"
32 #include "insn-config.h"
38 #include "addresses.h"
39 #include "basic-block.h"
50 /* This file contains the reload pass of the compiler, which is
51 run after register allocation has been done. It checks that
52 each insn is valid (operands required to be in registers really
53 are in registers of the proper class) and fixes up invalid ones
54 by copying values temporarily into registers for the insns
57 The results of register allocation are described by the vector
58 reg_renumber; the insns still contain pseudo regs, but reg_renumber
59 can be used to find which hard reg, if any, a pseudo reg is in.
61 The technique we always use is to free up a few hard regs that are
62 called ``reload regs'', and for each place where a pseudo reg
63 must be in a hard reg, copy it temporarily into one of the reload regs.
65 Reload regs are allocated locally for every instruction that needs
66 reloads. When there are pseudos which are allocated to a register that
67 has been chosen as a reload reg, such pseudos must be ``spilled''.
68 This means that they go to other hard regs, or to stack slots if no other
69 available hard regs can be found. Spilling can invalidate more
70 insns, requiring additional need for reloads, so we must keep checking
71 until the process stabilizes.
73 For machines with different classes of registers, we must keep track
74 of the register class needed for each reload, and make sure that
75 we allocate enough reload registers of each class.
77 The file reload.c contains the code that checks one insn for
78 validity and reports the reloads that it needs. This file
79 is in charge of scanning the entire rtl code, accumulating the
80 reload needs, spilling, assigning reload registers to use for
81 fixing up each insn, and generating the new insns to copy values
82 into the reload registers. */
84 struct target_reload default_target_reload;
86 struct target_reload *this_target_reload = &default_target_reload;
89 #define spill_indirect_levels \
90 (this_target_reload->x_spill_indirect_levels)
92 /* During reload_as_needed, element N contains a REG rtx for the hard reg
93 into which reg N has been reloaded (perhaps for a previous insn). */
94 static rtx *reg_last_reload_reg;
96 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
97 for an output reload that stores into reg N. */
98 static regset_head reg_has_output_reload;
100 /* Indicates which hard regs are reload-registers for an output reload
101 in the current insn. */
102 static HARD_REG_SET reg_is_output_reload;
104 /* Element N is the constant value to which pseudo reg N is equivalent,
105 or zero if pseudo reg N is not equivalent to a constant.
106 find_reloads looks at this in order to replace pseudo reg N
107 with the constant it stands for. */
108 rtx *reg_equiv_constant;
110 /* Element N is an invariant value to which pseudo reg N is equivalent.
111 eliminate_regs_in_insn uses this to replace pseudos in particular
113 rtx *reg_equiv_invariant;
115 /* Element N is a memory location to which pseudo reg N is equivalent,
116 prior to any register elimination (such as frame pointer to stack
117 pointer). Depending on whether or not it is a valid address, this value
118 is transferred to either reg_equiv_address or reg_equiv_mem. */
119 rtx *reg_equiv_memory_loc;
121 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
122 collector can keep track of what is inside. */
123 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
125 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
126 This is used when the address is not valid as a memory address
127 (because its displacement is too big for the machine.) */
128 rtx *reg_equiv_address;
130 /* Element N is the memory slot to which pseudo reg N is equivalent,
131 or zero if pseudo reg N is not equivalent to a memory slot. */
134 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
135 alternate representations of the location of pseudo reg N. */
136 rtx *reg_equiv_alt_mem_list;
138 /* Widest width in which each pseudo reg is referred to (via subreg). */
139 static unsigned int *reg_max_ref_width;
141 /* Element N is the list of insns that initialized reg N from its equivalent
142 constant or memory slot. */
144 int reg_equiv_init_size;
146 /* Vector to remember old contents of reg_renumber before spilling. */
147 static short *reg_old_renumber;
149 /* During reload_as_needed, element N contains the last pseudo regno reloaded
150 into hard register N. If that pseudo reg occupied more than one register,
151 reg_reloaded_contents points to that pseudo for each spill register in
152 use; all of these must remain set for an inheritance to occur. */
153 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
155 /* During reload_as_needed, element N contains the insn for which
156 hard register N was last used. Its contents are significant only
157 when reg_reloaded_valid is set for this register. */
158 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
160 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
161 static HARD_REG_SET reg_reloaded_valid;
162 /* Indicate if the register was dead at the end of the reload.
163 This is only valid if reg_reloaded_contents is set and valid. */
164 static HARD_REG_SET reg_reloaded_dead;
166 /* Indicate whether the register's current value is one that is not
167 safe to retain across a call, even for registers that are normally
168 call-saved. This is only meaningful for members of reg_reloaded_valid. */
169 static HARD_REG_SET reg_reloaded_call_part_clobbered;
171 /* Number of spill-regs so far; number of valid elements of spill_regs. */
174 /* In parallel with spill_regs, contains REG rtx's for those regs.
175 Holds the last rtx used for any given reg, or 0 if it has never
176 been used for spilling yet. This rtx is reused, provided it has
178 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
180 /* In parallel with spill_regs, contains nonzero for a spill reg
181 that was stored after the last time it was used.
182 The precise value is the insn generated to do the store. */
183 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
185 /* This is the register that was stored with spill_reg_store. This is a
186 copy of reload_out / reload_out_reg when the value was stored; if
187 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
188 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
190 /* This table is the inverse mapping of spill_regs:
191 indexed by hard reg number,
192 it contains the position of that reg in spill_regs,
193 or -1 for something that is not in spill_regs.
195 ?!? This is no longer accurate. */
196 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
198 /* This reg set indicates registers that can't be used as spill registers for
199 the currently processed insn. These are the hard registers which are live
200 during the insn, but not allocated to pseudos, as well as fixed
202 static HARD_REG_SET bad_spill_regs;
204 /* These are the hard registers that can't be used as spill register for any
205 insn. This includes registers used for user variables and registers that
206 we can't eliminate. A register that appears in this set also can't be used
207 to retry register allocation. */
208 static HARD_REG_SET bad_spill_regs_global;
210 /* Describes order of use of registers for reloading
211 of spilled pseudo-registers. `n_spills' is the number of
212 elements that are actually valid; new ones are added at the end.
214 Both spill_regs and spill_reg_order are used on two occasions:
215 once during find_reload_regs, where they keep track of the spill registers
216 for a single insn, but also during reload_as_needed where they show all
217 the registers ever used by reload. For the latter case, the information
218 is calculated during finish_spills. */
219 static short spill_regs[FIRST_PSEUDO_REGISTER];
221 /* This vector of reg sets indicates, for each pseudo, which hard registers
222 may not be used for retrying global allocation because the register was
223 formerly spilled from one of them. If we allowed reallocating a pseudo to
224 a register that it was already allocated to, reload might not
226 static HARD_REG_SET *pseudo_previous_regs;
228 /* This vector of reg sets indicates, for each pseudo, which hard
229 registers may not be used for retrying global allocation because they
230 are used as spill registers during one of the insns in which the
232 static HARD_REG_SET *pseudo_forbidden_regs;
234 /* All hard regs that have been used as spill registers for any insn are
235 marked in this set. */
236 static HARD_REG_SET used_spill_regs;
238 /* Index of last register assigned as a spill register. We allocate in
239 a round-robin fashion. */
240 static int last_spill_reg;
242 /* Record the stack slot for each spilled hard register. */
243 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
245 /* Width allocated so far for that stack slot. */
246 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
248 /* Record which pseudos needed to be spilled. */
249 static regset_head spilled_pseudos;
251 /* Record which pseudos changed their allocation in finish_spills. */
252 static regset_head changed_allocation_pseudos;
254 /* Used for communication between order_regs_for_reload and count_pseudo.
255 Used to avoid counting one pseudo twice. */
256 static regset_head pseudos_counted;
258 /* First uid used by insns created by reload in this function.
259 Used in find_equiv_reg. */
260 int reload_first_uid;
262 /* Flag set by local-alloc or global-alloc if anything is live in
263 a call-clobbered reg across calls. */
264 int caller_save_needed;
266 /* Set to 1 while reload_as_needed is operating.
267 Required by some machines to handle any generated moves differently. */
268 int reload_in_progress = 0;
270 /* This obstack is used for allocation of rtl during register elimination.
271 The allocated storage can be freed once find_reloads has processed the
273 static struct obstack reload_obstack;
275 /* Points to the beginning of the reload_obstack. All insn_chain structures
276 are allocated first. */
277 static char *reload_startobj;
279 /* The point after all insn_chain structures. Used to quickly deallocate
280 memory allocated in copy_reloads during calculate_needs_all_insns. */
281 static char *reload_firstobj;
283 /* This points before all local rtl generated by register elimination.
284 Used to quickly free all memory after processing one insn. */
285 static char *reload_insn_firstobj;
287 /* List of insn_chain instructions, one for every insn that reload needs to
289 struct insn_chain *reload_insn_chain;
291 /* List of all insns needing reloads. */
292 static struct insn_chain *insns_need_reload;
294 /* This structure is used to record information about register eliminations.
295 Each array entry describes one possible way of eliminating a register
296 in favor of another. If there is more than one way of eliminating a
297 particular register, the most preferred should be specified first. */
301 int from; /* Register number to be eliminated. */
302 int to; /* Register number used as replacement. */
303 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
304 int can_eliminate; /* Nonzero if this elimination can be done. */
305 int can_eliminate_previous; /* Value returned by TARGET_CAN_ELIMINATE
306 target hook in previous scan over insns
308 HOST_WIDE_INT offset; /* Current offset between the two regs. */
309 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
310 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
311 rtx from_rtx; /* REG rtx for the register to be eliminated.
312 We cannot simply compare the number since
313 we might then spuriously replace a hard
314 register corresponding to a pseudo
315 assigned to the reg to be eliminated. */
316 rtx to_rtx; /* REG rtx for the replacement. */
319 static struct elim_table *reg_eliminate = 0;
321 /* This is an intermediate structure to initialize the table. It has
322 exactly the members provided by ELIMINABLE_REGS. */
323 static const struct elim_table_1
327 } reg_eliminate_1[] =
329 /* If a set of eliminable registers was specified, define the table from it.
330 Otherwise, default to the normal case of the frame pointer being
331 replaced by the stack pointer. */
333 #ifdef ELIMINABLE_REGS
336 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
339 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
341 /* Record the number of pending eliminations that have an offset not equal
342 to their initial offset. If nonzero, we use a new copy of each
343 replacement result in any insns encountered. */
344 int num_not_at_initial_offset;
346 /* Count the number of registers that we may be able to eliminate. */
347 static int num_eliminable;
348 /* And the number of registers that are equivalent to a constant that
349 can be eliminated to frame_pointer / arg_pointer + constant. */
350 static int num_eliminable_invariants;
352 /* For each label, we record the offset of each elimination. If we reach
353 a label by more than one path and an offset differs, we cannot do the
354 elimination. This information is indexed by the difference of the
355 number of the label and the first label number. We can't offset the
356 pointer itself as this can cause problems on machines with segmented
357 memory. The first table is an array of flags that records whether we
358 have yet encountered a label and the second table is an array of arrays,
359 one entry in the latter array for each elimination. */
361 static int first_label_num;
362 static char *offsets_known_at;
363 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
365 /* Stack of addresses where an rtx has been changed. We can undo the
366 changes by popping items off the stack and restoring the original
367 value at each location.
369 We use this simplistic undo capability rather than copy_rtx as copy_rtx
370 will not make a deep copy of a normally sharable rtx, such as
371 (const (plus (symbol_ref) (const_int))). If such an expression appears
372 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
373 rtx expression would be changed. See PR 42431. */
377 DEF_VEC_ALLOC_P(rtx_p,heap);
378 static VEC(rtx_p,heap) *substitute_stack;
380 /* Number of labels in the current function. */
382 static int num_labels;
384 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
385 static void maybe_fix_stack_asms (void);
386 static void copy_reloads (struct insn_chain *);
387 static void calculate_needs_all_insns (int);
388 static int find_reg (struct insn_chain *, int);
389 static void find_reload_regs (struct insn_chain *);
390 static void select_reload_regs (void);
391 static void delete_caller_save_insns (void);
393 static void spill_failure (rtx, enum reg_class);
394 static void count_spilled_pseudo (int, int, int);
395 static void delete_dead_insn (rtx);
396 static void alter_reg (int, int, bool);
397 static void set_label_offsets (rtx, rtx, int);
398 static void check_eliminable_occurrences (rtx);
399 static void elimination_effects (rtx, enum machine_mode);
400 static rtx eliminate_regs_1 (rtx, enum machine_mode, rtx, bool, bool);
401 static int eliminate_regs_in_insn (rtx, int);
402 static void update_eliminable_offsets (void);
403 static void mark_not_eliminable (rtx, const_rtx, void *);
404 static void set_initial_elim_offsets (void);
405 static bool verify_initial_elim_offsets (void);
406 static void set_initial_label_offsets (void);
407 static void set_offsets_for_label (rtx);
408 static void init_eliminable_invariants (rtx, bool);
409 static void init_elim_table (void);
410 static void free_reg_equiv (void);
411 static void update_eliminables (HARD_REG_SET *);
412 static void elimination_costs_in_insn (rtx);
413 static void spill_hard_reg (unsigned int, int);
414 static int finish_spills (int);
415 static void scan_paradoxical_subregs (rtx);
416 static void count_pseudo (int);
417 static void order_regs_for_reload (struct insn_chain *);
418 static void reload_as_needed (int);
419 static void forget_old_reloads_1 (rtx, const_rtx, void *);
420 static void forget_marked_reloads (regset);
421 static int reload_reg_class_lower (const void *, const void *);
422 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
424 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
426 static int reload_reg_free_p (unsigned int, int, enum reload_type);
427 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
429 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
431 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
432 static int allocate_reload_reg (struct insn_chain *, int, int);
433 static int conflicts_with_override (rtx);
434 static void failed_reload (rtx, int);
435 static int set_reload_reg (int, int);
436 static void choose_reload_regs_init (struct insn_chain *, rtx *);
437 static void choose_reload_regs (struct insn_chain *);
438 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
440 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
442 static void do_input_reload (struct insn_chain *, struct reload *, int);
443 static void do_output_reload (struct insn_chain *, struct reload *, int);
444 static void emit_reload_insns (struct insn_chain *);
445 static void delete_output_reload (rtx, int, int, rtx);
446 static void delete_address_reloads (rtx, rtx);
447 static void delete_address_reloads_1 (rtx, rtx, rtx);
448 static void inc_for_reload (rtx, rtx, rtx, int);
450 static void add_auto_inc_notes (rtx, rtx);
452 static void substitute (rtx *, const_rtx, rtx);
453 static bool gen_reload_chain_without_interm_reg_p (int, int);
454 static int reloads_conflict (int, int);
455 static rtx gen_reload (rtx, rtx, int, enum reload_type);
456 static rtx emit_insn_if_valid_for_reload (rtx);
458 /* Initialize the reload pass. This is called at the beginning of compilation
459 and may be called again if the target is reinitialized. */
466 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
467 Set spill_indirect_levels to the number of levels such addressing is
468 permitted, zero if it is not permitted at all. */
471 = gen_rtx_MEM (Pmode,
474 LAST_VIRTUAL_REGISTER + 1),
476 spill_indirect_levels = 0;
478 while (memory_address_p (QImode, tem))
480 spill_indirect_levels++;
481 tem = gen_rtx_MEM (Pmode, tem);
484 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
486 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
487 indirect_symref_ok = memory_address_p (QImode, tem);
489 /* See if reg+reg is a valid (and offsettable) address. */
491 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
493 tem = gen_rtx_PLUS (Pmode,
494 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
495 gen_rtx_REG (Pmode, i));
497 /* This way, we make sure that reg+reg is an offsettable address. */
498 tem = plus_constant (tem, 4);
500 if (memory_address_p (QImode, tem))
502 double_reg_address_ok = 1;
507 /* Initialize obstack for our rtl allocation. */
508 gcc_obstack_init (&reload_obstack);
509 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
511 INIT_REG_SET (&spilled_pseudos);
512 INIT_REG_SET (&changed_allocation_pseudos);
513 INIT_REG_SET (&pseudos_counted);
516 /* List of insn chains that are currently unused. */
517 static struct insn_chain *unused_insn_chains = 0;
519 /* Allocate an empty insn_chain structure. */
521 new_insn_chain (void)
523 struct insn_chain *c;
525 if (unused_insn_chains == 0)
527 c = XOBNEW (&reload_obstack, struct insn_chain);
528 INIT_REG_SET (&c->live_throughout);
529 INIT_REG_SET (&c->dead_or_set);
533 c = unused_insn_chains;
534 unused_insn_chains = c->next;
536 c->is_caller_save_insn = 0;
537 c->need_operand_change = 0;
543 /* Small utility function to set all regs in hard reg set TO which are
544 allocated to pseudos in regset FROM. */
547 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
550 reg_set_iterator rsi;
552 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
554 int r = reg_renumber[regno];
558 /* reload_combine uses the information from DF_LIVE_IN,
559 which might still contain registers that have not
560 actually been allocated since they have an
562 gcc_assert (ira_conflicts_p || reload_completed);
565 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
569 /* Replace all pseudos found in LOC with their corresponding
573 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
586 unsigned int regno = REGNO (x);
588 if (regno < FIRST_PSEUDO_REGISTER)
591 x = eliminate_regs_1 (x, mem_mode, usage, true, false);
595 replace_pseudos_in (loc, mem_mode, usage);
599 if (reg_equiv_constant[regno])
600 *loc = reg_equiv_constant[regno];
601 else if (reg_equiv_invariant[regno])
602 *loc = reg_equiv_invariant[regno];
603 else if (reg_equiv_mem[regno])
604 *loc = reg_equiv_mem[regno];
605 else if (reg_equiv_address[regno])
606 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
609 gcc_assert (!REG_P (regno_reg_rtx[regno])
610 || REGNO (regno_reg_rtx[regno]) != regno);
611 *loc = regno_reg_rtx[regno];
616 else if (code == MEM)
618 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
622 /* Process each of our operands recursively. */
623 fmt = GET_RTX_FORMAT (code);
624 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
626 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
627 else if (*fmt == 'E')
628 for (j = 0; j < XVECLEN (x, i); j++)
629 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
632 /* Determine if the current function has an exception receiver block
633 that reaches the exit block via non-exceptional edges */
636 has_nonexceptional_receiver (void)
640 basic_block *tos, *worklist, bb;
642 /* If we're not optimizing, then just err on the safe side. */
646 /* First determine which blocks can reach exit via normal paths. */
647 tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1);
650 bb->flags &= ~BB_REACHABLE;
652 /* Place the exit block on our worklist. */
653 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
654 *tos++ = EXIT_BLOCK_PTR;
656 /* Iterate: find everything reachable from what we've already seen. */
657 while (tos != worklist)
661 FOR_EACH_EDGE (e, ei, bb->preds)
662 if (!(e->flags & EDGE_ABNORMAL))
664 basic_block src = e->src;
666 if (!(src->flags & BB_REACHABLE))
668 src->flags |= BB_REACHABLE;
675 /* Now see if there's a reachable block with an exceptional incoming
678 if (bb->flags & BB_REACHABLE && bb_has_abnormal_pred (bb))
681 /* No exceptional block reached exit unexceptionally. */
686 /* Global variables used by reload and its subroutines. */
688 /* The current basic block while in calculate_elim_costs_all_insns. */
689 static basic_block elim_bb;
691 /* Set during calculate_needs if an insn needs register elimination. */
692 static int something_needs_elimination;
693 /* Set during calculate_needs if an insn needs an operand changed. */
694 static int something_needs_operands_changed;
695 /* Set by alter_regs if we spilled a register to the stack. */
696 static bool something_was_spilled;
698 /* Nonzero means we couldn't get enough spill regs. */
701 /* Temporary array of pseudo-register number. */
702 static int *temp_pseudo_reg_arr;
704 /* Main entry point for the reload pass.
706 FIRST is the first insn of the function being compiled.
708 GLOBAL nonzero means we were called from global_alloc
709 and should attempt to reallocate any pseudoregs that we
710 displace from hard regs we will use for reloads.
711 If GLOBAL is zero, we do not have enough information to do that,
712 so any pseudo reg that is spilled must go to the stack.
714 Return value is nonzero if reload failed
715 and we must not do any more for this function. */
718 reload (rtx first, int global)
722 struct elim_table *ep;
725 /* Make sure even insns with volatile mem refs are recognizable. */
730 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
732 /* Make sure that the last insn in the chain
733 is not something that needs reloading. */
734 emit_note (NOTE_INSN_DELETED);
736 /* Enable find_equiv_reg to distinguish insns made by reload. */
737 reload_first_uid = get_max_uid ();
739 #ifdef SECONDARY_MEMORY_NEEDED
740 /* Initialize the secondary memory table. */
741 clear_secondary_mem ();
744 /* We don't have a stack slot for any spill reg yet. */
745 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
746 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
748 /* Initialize the save area information for caller-save, in case some
752 /* Compute which hard registers are now in use
753 as homes for pseudo registers.
754 This is done here rather than (eg) in global_alloc
755 because this point is reached even if not optimizing. */
756 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
759 /* A function that has a nonlocal label that can reach the exit
760 block via non-exceptional paths must save all call-saved
762 if (cfun->has_nonlocal_label
763 && has_nonexceptional_receiver ())
764 crtl->saves_all_registers = 1;
766 if (crtl->saves_all_registers)
767 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
768 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
769 df_set_regs_ever_live (i, true);
771 reg_old_renumber = XCNEWVEC (short, max_regno);
772 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
773 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
774 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
776 CLEAR_HARD_REG_SET (bad_spill_regs_global);
778 init_eliminable_invariants (first, true);
781 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
782 stack slots to the pseudos that lack hard regs or equivalents.
783 Do not touch virtual registers. */
785 temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
786 for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
787 temp_pseudo_reg_arr[n++] = i;
790 /* Ask IRA to order pseudo-registers for better stack slot
792 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
794 for (i = 0; i < n; i++)
795 alter_reg (temp_pseudo_reg_arr[i], -1, false);
797 /* If we have some registers we think can be eliminated, scan all insns to
798 see if there is an insn that sets one of these registers to something
799 other than itself plus a constant. If so, the register cannot be
800 eliminated. Doing this scan here eliminates an extra pass through the
801 main reload loop in the most common case where register elimination
803 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
805 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
807 maybe_fix_stack_asms ();
809 insns_need_reload = 0;
810 something_needs_elimination = 0;
812 /* Initialize to -1, which means take the first spill register. */
815 /* Spill any hard regs that we know we can't eliminate. */
816 CLEAR_HARD_REG_SET (used_spill_regs);
817 /* There can be multiple ways to eliminate a register;
818 they should be listed adjacently.
819 Elimination for any register fails only if all possible ways fail. */
820 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
823 int can_eliminate = 0;
826 can_eliminate |= ep->can_eliminate;
829 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
831 spill_hard_reg (from, 1);
834 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
835 if (frame_pointer_needed)
836 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
838 finish_spills (global);
840 /* From now on, we may need to generate moves differently. We may also
841 allow modifications of insns which cause them to not be recognized.
842 Any such modifications will be cleaned up during reload itself. */
843 reload_in_progress = 1;
845 /* This loop scans the entire function each go-round
846 and repeats until one repetition spills no additional hard regs. */
849 int something_changed;
851 HOST_WIDE_INT starting_frame_size;
853 starting_frame_size = get_frame_size ();
854 something_was_spilled = false;
856 set_initial_elim_offsets ();
857 set_initial_label_offsets ();
859 /* For each pseudo register that has an equivalent location defined,
860 try to eliminate any eliminable registers (such as the frame pointer)
861 assuming initial offsets for the replacement register, which
864 If the resulting location is directly addressable, substitute
865 the MEM we just got directly for the old REG.
867 If it is not addressable but is a constant or the sum of a hard reg
868 and constant, it is probably not addressable because the constant is
869 out of range, in that case record the address; we will generate
870 hairy code to compute the address in a register each time it is
871 needed. Similarly if it is a hard register, but one that is not
872 valid as an address register.
874 If the location is not addressable, but does not have one of the
875 above forms, assign a stack slot. We have to do this to avoid the
876 potential of producing lots of reloads if, e.g., a location involves
877 a pseudo that didn't get a hard register and has an equivalent memory
878 location that also involves a pseudo that didn't get a hard register.
880 Perhaps at some point we will improve reload_when_needed handling
881 so this problem goes away. But that's very hairy. */
883 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
884 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
886 rtx x = eliminate_regs (reg_equiv_memory_loc[i], VOIDmode,
889 if (strict_memory_address_addr_space_p
890 (GET_MODE (regno_reg_rtx[i]), XEXP (x, 0),
892 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
893 else if (CONSTANT_P (XEXP (x, 0))
894 || (REG_P (XEXP (x, 0))
895 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
896 || (GET_CODE (XEXP (x, 0)) == PLUS
897 && REG_P (XEXP (XEXP (x, 0), 0))
898 && (REGNO (XEXP (XEXP (x, 0), 0))
899 < FIRST_PSEUDO_REGISTER)
900 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
901 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
904 /* Make a new stack slot. Then indicate that something
905 changed so we go back and recompute offsets for
906 eliminable registers because the allocation of memory
907 below might change some offset. reg_equiv_{mem,address}
908 will be set up for this pseudo on the next pass around
910 reg_equiv_memory_loc[i] = 0;
911 reg_equiv_init[i] = 0;
912 alter_reg (i, -1, true);
916 if (caller_save_needed)
919 /* If we allocated another stack slot, redo elimination bookkeeping. */
920 if (something_was_spilled || starting_frame_size != get_frame_size ())
922 if (starting_frame_size && crtl->stack_alignment_needed)
924 /* If we have a stack frame, we must align it now. The
925 stack size may be a part of the offset computation for
926 register elimination. So if this changes the stack size,
927 then repeat the elimination bookkeeping. We don't
928 realign when there is no stack, as that will cause a
929 stack frame when none is needed should
930 STARTING_FRAME_OFFSET not be already aligned to
932 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
933 if (starting_frame_size != get_frame_size ())
937 if (caller_save_needed)
939 save_call_clobbered_regs ();
940 /* That might have allocated new insn_chain structures. */
941 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
944 calculate_needs_all_insns (global);
946 if (! ira_conflicts_p)
947 /* Don't do it for IRA. We need this info because we don't
948 change live_throughout and dead_or_set for chains when IRA
950 CLEAR_REG_SET (&spilled_pseudos);
954 something_changed = 0;
956 /* If we allocated any new memory locations, make another pass
957 since it might have changed elimination offsets. */
958 if (something_was_spilled || starting_frame_size != get_frame_size ())
959 something_changed = 1;
961 /* Even if the frame size remained the same, we might still have
962 changed elimination offsets, e.g. if find_reloads called
963 force_const_mem requiring the back end to allocate a constant
964 pool base register that needs to be saved on the stack. */
965 else if (!verify_initial_elim_offsets ())
966 something_changed = 1;
969 HARD_REG_SET to_spill;
970 CLEAR_HARD_REG_SET (to_spill);
971 update_eliminables (&to_spill);
972 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
974 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
975 if (TEST_HARD_REG_BIT (to_spill, i))
977 spill_hard_reg (i, 1);
980 /* Regardless of the state of spills, if we previously had
981 a register that we thought we could eliminate, but now can
982 not eliminate, we must run another pass.
984 Consider pseudos which have an entry in reg_equiv_* which
985 reference an eliminable register. We must make another pass
986 to update reg_equiv_* so that we do not substitute in the
987 old value from when we thought the elimination could be
989 something_changed = 1;
993 select_reload_regs ();
997 if (insns_need_reload != 0 || did_spill)
998 something_changed |= finish_spills (global);
1000 if (! something_changed)
1003 if (caller_save_needed)
1004 delete_caller_save_insns ();
1006 obstack_free (&reload_obstack, reload_firstobj);
1009 /* If global-alloc was run, notify it of any register eliminations we have
1012 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1013 if (ep->can_eliminate)
1014 mark_elimination (ep->from, ep->to);
1016 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1017 If that insn didn't set the register (i.e., it copied the register to
1018 memory), just delete that insn instead of the equivalencing insn plus
1019 anything now dead. If we call delete_dead_insn on that insn, we may
1020 delete the insn that actually sets the register if the register dies
1021 there and that is incorrect. */
1023 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1025 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1028 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1030 rtx equiv_insn = XEXP (list, 0);
1032 /* If we already deleted the insn or if it may trap, we can't
1033 delete it. The latter case shouldn't happen, but can
1034 if an insn has a variable address, gets a REG_EH_REGION
1035 note added to it, and then gets converted into a load
1036 from a constant address. */
1037 if (NOTE_P (equiv_insn)
1038 || can_throw_internal (equiv_insn))
1040 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1041 delete_dead_insn (equiv_insn);
1043 SET_INSN_DELETED (equiv_insn);
1048 /* Use the reload registers where necessary
1049 by generating move instructions to move the must-be-register
1050 values into or out of the reload registers. */
1052 if (insns_need_reload != 0 || something_needs_elimination
1053 || something_needs_operands_changed)
1055 HOST_WIDE_INT old_frame_size = get_frame_size ();
1057 reload_as_needed (global);
1059 gcc_assert (old_frame_size == get_frame_size ());
1061 gcc_assert (verify_initial_elim_offsets ());
1064 /* If we were able to eliminate the frame pointer, show that it is no
1065 longer live at the start of any basic block. If it ls live by
1066 virtue of being in a pseudo, that pseudo will be marked live
1067 and hence the frame pointer will be known to be live via that
1070 if (! frame_pointer_needed)
1072 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1074 /* Come here (with failure set nonzero) if we can't get enough spill
1078 CLEAR_REG_SET (&changed_allocation_pseudos);
1079 CLEAR_REG_SET (&spilled_pseudos);
1080 reload_in_progress = 0;
1082 /* Now eliminate all pseudo regs by modifying them into
1083 their equivalent memory references.
1084 The REG-rtx's for the pseudos are modified in place,
1085 so all insns that used to refer to them now refer to memory.
1087 For a reg that has a reg_equiv_address, all those insns
1088 were changed by reloading so that no insns refer to it any longer;
1089 but the DECL_RTL of a variable decl may refer to it,
1090 and if so this causes the debugging info to mention the variable. */
1092 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1096 if (reg_equiv_mem[i])
1097 addr = XEXP (reg_equiv_mem[i], 0);
1099 if (reg_equiv_address[i])
1100 addr = reg_equiv_address[i];
1104 if (reg_renumber[i] < 0)
1106 rtx reg = regno_reg_rtx[i];
1108 REG_USERVAR_P (reg) = 0;
1109 PUT_CODE (reg, MEM);
1110 XEXP (reg, 0) = addr;
1111 if (reg_equiv_memory_loc[i])
1112 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1115 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1116 MEM_ATTRS (reg) = 0;
1118 MEM_NOTRAP_P (reg) = 1;
1120 else if (reg_equiv_mem[i])
1121 XEXP (reg_equiv_mem[i], 0) = addr;
1124 /* We don't want complex addressing modes in debug insns
1125 if simpler ones will do, so delegitimize equivalences
1127 if (MAY_HAVE_DEBUG_INSNS && reg_renumber[i] < 0)
1129 rtx reg = regno_reg_rtx[i];
1133 if (reg_equiv_constant[i])
1134 equiv = reg_equiv_constant[i];
1135 else if (reg_equiv_invariant[i])
1136 equiv = reg_equiv_invariant[i];
1137 else if (reg && MEM_P (reg))
1138 equiv = targetm.delegitimize_address (reg);
1139 else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
1145 for (use = DF_REG_USE_CHAIN (i); use; use = next)
1147 insn = DF_REF_INSN (use);
1149 /* Make sure the next ref is for a different instruction,
1150 so that we're not affected by the rescan. */
1151 next = DF_REF_NEXT_REG (use);
1152 while (next && DF_REF_INSN (next) == insn)
1153 next = DF_REF_NEXT_REG (next);
1155 if (DEBUG_INSN_P (insn))
1159 INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
1160 df_insn_rescan_debug_internal (insn);
1163 INSN_VAR_LOCATION_LOC (insn)
1164 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn),
1171 /* We must set reload_completed now since the cleanup_subreg_operands call
1172 below will re-recognize each insn and reload may have generated insns
1173 which are only valid during and after reload. */
1174 reload_completed = 1;
1176 /* Make a pass over all the insns and delete all USEs which we inserted
1177 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1178 notes. Delete all CLOBBER insns, except those that refer to the return
1179 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1180 from misarranging variable-array code, and simplify (subreg (reg))
1181 operands. Strip and regenerate REG_INC notes that may have been moved
1184 for (insn = first; insn; insn = NEXT_INSN (insn))
1190 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1191 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1193 if ((GET_CODE (PATTERN (insn)) == USE
1194 /* We mark with QImode USEs introduced by reload itself. */
1195 && (GET_MODE (insn) == QImode
1196 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1197 || (GET_CODE (PATTERN (insn)) == CLOBBER
1198 && (!MEM_P (XEXP (PATTERN (insn), 0))
1199 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1200 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1201 && XEXP (XEXP (PATTERN (insn), 0), 0)
1202 != stack_pointer_rtx))
1203 && (!REG_P (XEXP (PATTERN (insn), 0))
1204 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1210 /* Some CLOBBERs may survive until here and still reference unassigned
1211 pseudos with const equivalent, which may in turn cause ICE in later
1212 passes if the reference remains in place. */
1213 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1214 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1215 VOIDmode, PATTERN (insn));
1217 /* Discard obvious no-ops, even without -O. This optimization
1218 is fast and doesn't interfere with debugging. */
1219 if (NONJUMP_INSN_P (insn)
1220 && GET_CODE (PATTERN (insn)) == SET
1221 && REG_P (SET_SRC (PATTERN (insn)))
1222 && REG_P (SET_DEST (PATTERN (insn)))
1223 && (REGNO (SET_SRC (PATTERN (insn)))
1224 == REGNO (SET_DEST (PATTERN (insn)))))
1230 pnote = ®_NOTES (insn);
1233 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1234 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1235 || REG_NOTE_KIND (*pnote) == REG_INC)
1236 *pnote = XEXP (*pnote, 1);
1238 pnote = &XEXP (*pnote, 1);
1242 add_auto_inc_notes (insn, PATTERN (insn));
1245 /* Simplify (subreg (reg)) if it appears as an operand. */
1246 cleanup_subreg_operands (insn);
1248 /* Clean up invalid ASMs so that they don't confuse later passes.
1250 if (asm_noperands (PATTERN (insn)) >= 0)
1252 extract_insn (insn);
1253 if (!constrain_operands (1))
1255 error_for_asm (insn,
1256 "%<asm%> operand has impossible constraints");
1263 /* If we are doing generic stack checking, give a warning if this
1264 function's frame size is larger than we expect. */
1265 if (flag_stack_check == GENERIC_STACK_CHECK)
1267 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1268 static int verbose_warned = 0;
1270 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1271 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1272 size += UNITS_PER_WORD;
1274 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1276 warning (0, "frame size too large for reliable stack checking");
1277 if (! verbose_warned)
1279 warning (0, "try reducing the number of local variables");
1285 free (temp_pseudo_reg_arr);
1287 /* Indicate that we no longer have known memory locations or constants. */
1290 free (reg_max_ref_width);
1291 free (reg_old_renumber);
1292 free (pseudo_previous_regs);
1293 free (pseudo_forbidden_regs);
1295 CLEAR_HARD_REG_SET (used_spill_regs);
1296 for (i = 0; i < n_spills; i++)
1297 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1299 /* Free all the insn_chain structures at once. */
1300 obstack_free (&reload_obstack, reload_startobj);
1301 unused_insn_chains = 0;
1302 fixup_abnormal_edges ();
1304 /* Replacing pseudos with their memory equivalents might have
1305 created shared rtx. Subsequent passes would get confused
1306 by this, so unshare everything here. */
1307 unshare_all_rtl_again (first);
1309 #ifdef STACK_BOUNDARY
1310 /* init_emit has set the alignment of the hard frame pointer
1311 to STACK_BOUNDARY. It is very likely no longer valid if
1312 the hard frame pointer was used for register allocation. */
1313 if (!frame_pointer_needed)
1314 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1317 VEC_free (rtx_p, heap, substitute_stack);
1319 gcc_assert (bitmap_empty_p (&spilled_pseudos));
1324 /* Yet another special case. Unfortunately, reg-stack forces people to
1325 write incorrect clobbers in asm statements. These clobbers must not
1326 cause the register to appear in bad_spill_regs, otherwise we'll call
1327 fatal_insn later. We clear the corresponding regnos in the live
1328 register sets to avoid this.
1329 The whole thing is rather sick, I'm afraid. */
1332 maybe_fix_stack_asms (void)
1335 const char *constraints[MAX_RECOG_OPERANDS];
1336 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1337 struct insn_chain *chain;
1339 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1342 HARD_REG_SET clobbered, allowed;
1345 if (! INSN_P (chain->insn)
1346 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1348 pat = PATTERN (chain->insn);
1349 if (GET_CODE (pat) != PARALLEL)
1352 CLEAR_HARD_REG_SET (clobbered);
1353 CLEAR_HARD_REG_SET (allowed);
1355 /* First, make a mask of all stack regs that are clobbered. */
1356 for (i = 0; i < XVECLEN (pat, 0); i++)
1358 rtx t = XVECEXP (pat, 0, i);
1359 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1360 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1363 /* Get the operand values and constraints out of the insn. */
1364 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1365 constraints, operand_mode, NULL);
1367 /* For every operand, see what registers are allowed. */
1368 for (i = 0; i < noperands; i++)
1370 const char *p = constraints[i];
1371 /* For every alternative, we compute the class of registers allowed
1372 for reloading in CLS, and merge its contents into the reg set
1374 int cls = (int) NO_REGS;
1380 if (c == '\0' || c == ',' || c == '#')
1382 /* End of one alternative - mark the regs in the current
1383 class, and reset the class. */
1384 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1390 } while (c != '\0' && c != ',');
1398 case '=': case '+': case '*': case '%': case '?': case '!':
1399 case '0': case '1': case '2': case '3': case '4': case '<':
1400 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1401 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1402 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1403 case TARGET_MEM_CONSTRAINT:
1407 cls = (int) reg_class_subunion[cls]
1408 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1413 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1417 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1418 cls = (int) reg_class_subunion[cls]
1419 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1421 cls = (int) reg_class_subunion[cls]
1422 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1424 p += CONSTRAINT_LEN (c, p);
1427 /* Those of the registers which are clobbered, but allowed by the
1428 constraints, must be usable as reload registers. So clear them
1429 out of the life information. */
1430 AND_HARD_REG_SET (allowed, clobbered);
1431 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1432 if (TEST_HARD_REG_BIT (allowed, i))
1434 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1435 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1442 /* Copy the global variables n_reloads and rld into the corresponding elts
1445 copy_reloads (struct insn_chain *chain)
1447 chain->n_reloads = n_reloads;
1448 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1449 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1450 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1453 /* Walk the chain of insns, and determine for each whether it needs reloads
1454 and/or eliminations. Build the corresponding insns_need_reload list, and
1455 set something_needs_elimination as appropriate. */
1457 calculate_needs_all_insns (int global)
1459 struct insn_chain **pprev_reload = &insns_need_reload;
1460 struct insn_chain *chain, *next = 0;
1462 something_needs_elimination = 0;
1464 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1465 for (chain = reload_insn_chain; chain != 0; chain = next)
1467 rtx insn = chain->insn;
1471 /* Clear out the shortcuts. */
1472 chain->n_reloads = 0;
1473 chain->need_elim = 0;
1474 chain->need_reload = 0;
1475 chain->need_operand_change = 0;
1477 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1478 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1479 what effects this has on the known offsets at labels. */
1481 if (LABEL_P (insn) || JUMP_P (insn)
1482 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1483 set_label_offsets (insn, insn, 0);
1487 rtx old_body = PATTERN (insn);
1488 int old_code = INSN_CODE (insn);
1489 rtx old_notes = REG_NOTES (insn);
1490 int did_elimination = 0;
1491 int operands_changed = 0;
1492 rtx set = single_set (insn);
1494 /* Skip insns that only set an equivalence. */
1495 if (set && REG_P (SET_DEST (set))
1496 && reg_renumber[REGNO (SET_DEST (set))] < 0
1497 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1498 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1499 && reg_equiv_init[REGNO (SET_DEST (set))])
1502 /* If needed, eliminate any eliminable registers. */
1503 if (num_eliminable || num_eliminable_invariants)
1504 did_elimination = eliminate_regs_in_insn (insn, 0);
1506 /* Analyze the instruction. */
1507 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1508 global, spill_reg_order);
1510 /* If a no-op set needs more than one reload, this is likely
1511 to be something that needs input address reloads. We
1512 can't get rid of this cleanly later, and it is of no use
1513 anyway, so discard it now.
1514 We only do this when expensive_optimizations is enabled,
1515 since this complements reload inheritance / output
1516 reload deletion, and it can make debugging harder. */
1517 if (flag_expensive_optimizations && n_reloads > 1)
1519 rtx set = single_set (insn);
1522 ((SET_SRC (set) == SET_DEST (set)
1523 && REG_P (SET_SRC (set))
1524 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1525 || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1526 && reg_renumber[REGNO (SET_SRC (set))] < 0
1527 && reg_renumber[REGNO (SET_DEST (set))] < 0
1528 && reg_equiv_memory_loc[REGNO (SET_SRC (set))] != NULL
1529 && reg_equiv_memory_loc[REGNO (SET_DEST (set))] != NULL
1530 && rtx_equal_p (reg_equiv_memory_loc
1531 [REGNO (SET_SRC (set))],
1532 reg_equiv_memory_loc
1533 [REGNO (SET_DEST (set))]))))
1535 if (ira_conflicts_p)
1536 /* Inform IRA about the insn deletion. */
1537 ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1538 REGNO (SET_SRC (set)));
1540 /* Delete it from the reload chain. */
1542 chain->prev->next = next;
1544 reload_insn_chain = next;
1546 next->prev = chain->prev;
1547 chain->next = unused_insn_chains;
1548 unused_insn_chains = chain;
1553 update_eliminable_offsets ();
1555 /* Remember for later shortcuts which insns had any reloads or
1556 register eliminations. */
1557 chain->need_elim = did_elimination;
1558 chain->need_reload = n_reloads > 0;
1559 chain->need_operand_change = operands_changed;
1561 /* Discard any register replacements done. */
1562 if (did_elimination)
1564 obstack_free (&reload_obstack, reload_insn_firstobj);
1565 PATTERN (insn) = old_body;
1566 INSN_CODE (insn) = old_code;
1567 REG_NOTES (insn) = old_notes;
1568 something_needs_elimination = 1;
1571 something_needs_operands_changed |= operands_changed;
1575 copy_reloads (chain);
1576 *pprev_reload = chain;
1577 pprev_reload = &chain->next_need_reload;
1584 /* This function is called from the register allocator to set up estimates
1585 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1586 an invariant. The structure is similar to calculate_needs_all_insns. */
1589 calculate_elim_costs_all_insns (void)
1591 int *reg_equiv_init_cost;
1595 reg_equiv_init_cost = XCNEWVEC (int, max_regno);
1597 init_eliminable_invariants (get_insns (), false);
1599 set_initial_elim_offsets ();
1600 set_initial_label_offsets ();
1607 FOR_BB_INSNS (bb, insn)
1609 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1610 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1611 what effects this has on the known offsets at labels. */
1613 if (LABEL_P (insn) || JUMP_P (insn)
1614 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1615 set_label_offsets (insn, insn, 0);
1619 rtx set = single_set (insn);
1621 /* Skip insns that only set an equivalence. */
1622 if (set && REG_P (SET_DEST (set))
1623 && reg_renumber[REGNO (SET_DEST (set))] < 0
1624 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1625 || (reg_equiv_invariant[REGNO (SET_DEST (set))])))
1627 unsigned regno = REGNO (SET_DEST (set));
1628 rtx init = reg_equiv_init[regno];
1631 rtx t = eliminate_regs_1 (SET_SRC (set), VOIDmode, insn,
1633 int cost = rtx_cost (t, SET,
1634 optimize_bb_for_speed_p (bb));
1635 int freq = REG_FREQ_FROM_BB (bb);
1637 reg_equiv_init_cost[regno] = cost * freq;
1641 /* If needed, eliminate any eliminable registers. */
1642 if (num_eliminable || num_eliminable_invariants)
1643 elimination_costs_in_insn (insn);
1646 update_eliminable_offsets ();
1650 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1652 if (reg_equiv_invariant[i])
1654 if (reg_equiv_init[i])
1656 int cost = reg_equiv_init_cost[i];
1659 "Reg %d has equivalence, initial gains %d\n", i, cost);
1661 ira_adjust_equiv_reg_cost (i, cost);
1667 "Reg %d had equivalence, but can't be eliminated\n",
1669 ira_adjust_equiv_reg_cost (i, 0);
1675 free (reg_equiv_init_cost);
1678 /* Comparison function for qsort to decide which of two reloads
1679 should be handled first. *P1 and *P2 are the reload numbers. */
1682 reload_reg_class_lower (const void *r1p, const void *r2p)
1684 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1687 /* Consider required reloads before optional ones. */
1688 t = rld[r1].optional - rld[r2].optional;
1692 /* Count all solitary classes before non-solitary ones. */
1693 t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1694 - (reg_class_size[(int) rld[r1].rclass] == 1));
1698 /* Aside from solitaires, consider all multi-reg groups first. */
1699 t = rld[r2].nregs - rld[r1].nregs;
1703 /* Consider reloads in order of increasing reg-class number. */
1704 t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1708 /* If reloads are equally urgent, sort by reload number,
1709 so that the results of qsort leave nothing to chance. */
1713 /* The cost of spilling each hard reg. */
1714 static int spill_cost[FIRST_PSEUDO_REGISTER];
1716 /* When spilling multiple hard registers, we use SPILL_COST for the first
1717 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1718 only the first hard reg for a multi-reg pseudo. */
1719 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1721 /* Map of hard regno to pseudo regno currently occupying the hard
1723 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1725 /* Update the spill cost arrays, considering that pseudo REG is live. */
1728 count_pseudo (int reg)
1730 int freq = REG_FREQ (reg);
1731 int r = reg_renumber[reg];
1734 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1735 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1736 /* Ignore spilled pseudo-registers which can be here only if IRA
1738 || (ira_conflicts_p && r < 0))
1741 SET_REGNO_REG_SET (&pseudos_counted, reg);
1743 gcc_assert (r >= 0);
1745 spill_add_cost[r] += freq;
1746 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1749 hard_regno_to_pseudo_regno[r + nregs] = reg;
1750 spill_cost[r + nregs] += freq;
1754 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1755 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1758 order_regs_for_reload (struct insn_chain *chain)
1761 HARD_REG_SET used_by_pseudos;
1762 HARD_REG_SET used_by_pseudos2;
1763 reg_set_iterator rsi;
1765 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1767 memset (spill_cost, 0, sizeof spill_cost);
1768 memset (spill_add_cost, 0, sizeof spill_add_cost);
1769 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1770 hard_regno_to_pseudo_regno[i] = -1;
1772 /* Count number of uses of each hard reg by pseudo regs allocated to it
1773 and then order them by decreasing use. First exclude hard registers
1774 that are live in or across this insn. */
1776 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1777 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1778 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1779 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1781 /* Now find out which pseudos are allocated to it, and update
1783 CLEAR_REG_SET (&pseudos_counted);
1785 EXECUTE_IF_SET_IN_REG_SET
1786 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1790 EXECUTE_IF_SET_IN_REG_SET
1791 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1795 CLEAR_REG_SET (&pseudos_counted);
1798 /* Vector of reload-numbers showing the order in which the reloads should
1800 static short reload_order[MAX_RELOADS];
1802 /* This is used to keep track of the spill regs used in one insn. */
1803 static HARD_REG_SET used_spill_regs_local;
1805 /* We decided to spill hard register SPILLED, which has a size of
1806 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1807 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1808 update SPILL_COST/SPILL_ADD_COST. */
1811 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1813 int freq = REG_FREQ (reg);
1814 int r = reg_renumber[reg];
1815 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1817 /* Ignore spilled pseudo-registers which can be here only if IRA is
1819 if ((ira_conflicts_p && r < 0)
1820 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1821 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1824 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1826 spill_add_cost[r] -= freq;
1829 hard_regno_to_pseudo_regno[r + nregs] = -1;
1830 spill_cost[r + nregs] -= freq;
1834 /* Find reload register to use for reload number ORDER. */
1837 find_reg (struct insn_chain *chain, int order)
1839 int rnum = reload_order[order];
1840 struct reload *rl = rld + rnum;
1841 int best_cost = INT_MAX;
1843 unsigned int i, j, n;
1845 HARD_REG_SET not_usable;
1846 HARD_REG_SET used_by_other_reload;
1847 reg_set_iterator rsi;
1848 static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1849 static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1851 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1852 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1853 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1855 CLEAR_HARD_REG_SET (used_by_other_reload);
1856 for (k = 0; k < order; k++)
1858 int other = reload_order[k];
1860 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1861 for (j = 0; j < rld[other].nregs; j++)
1862 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1865 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1867 #ifdef REG_ALLOC_ORDER
1868 unsigned int regno = reg_alloc_order[i];
1870 unsigned int regno = i;
1873 if (! TEST_HARD_REG_BIT (not_usable, regno)
1874 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1875 && HARD_REGNO_MODE_OK (regno, rl->mode))
1877 int this_cost = spill_cost[regno];
1879 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1881 for (j = 1; j < this_nregs; j++)
1883 this_cost += spill_add_cost[regno + j];
1884 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1885 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1891 if (ira_conflicts_p)
1893 /* Ask IRA to find a better pseudo-register for
1895 for (n = j = 0; j < this_nregs; j++)
1897 int r = hard_regno_to_pseudo_regno[regno + j];
1901 if (n == 0 || regno_pseudo_regs[n - 1] != r)
1902 regno_pseudo_regs[n++] = r;
1904 regno_pseudo_regs[n++] = -1;
1906 || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1907 best_regno_pseudo_regs,
1914 best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1915 if (regno_pseudo_regs[j] < 0)
1922 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1924 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1926 if (this_cost < best_cost
1927 /* Among registers with equal cost, prefer caller-saved ones, or
1928 use REG_ALLOC_ORDER if it is defined. */
1929 || (this_cost == best_cost
1930 #ifdef REG_ALLOC_ORDER
1931 && (inv_reg_alloc_order[regno]
1932 < inv_reg_alloc_order[best_reg])
1934 && call_used_regs[regno]
1935 && ! call_used_regs[best_reg]
1940 best_cost = this_cost;
1948 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1950 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1951 rl->regno = best_reg;
1953 EXECUTE_IF_SET_IN_REG_SET
1954 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1956 count_spilled_pseudo (best_reg, rl->nregs, j);
1959 EXECUTE_IF_SET_IN_REG_SET
1960 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1962 count_spilled_pseudo (best_reg, rl->nregs, j);
1965 for (i = 0; i < rl->nregs; i++)
1967 gcc_assert (spill_cost[best_reg + i] == 0);
1968 gcc_assert (spill_add_cost[best_reg + i] == 0);
1969 gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
1970 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1975 /* Find more reload regs to satisfy the remaining need of an insn, which
1977 Do it by ascending class number, since otherwise a reg
1978 might be spilled for a big class and might fail to count
1979 for a smaller class even though it belongs to that class. */
1982 find_reload_regs (struct insn_chain *chain)
1986 /* In order to be certain of getting the registers we need,
1987 we must sort the reloads into order of increasing register class.
1988 Then our grabbing of reload registers will parallel the process
1989 that provided the reload registers. */
1990 for (i = 0; i < chain->n_reloads; i++)
1992 /* Show whether this reload already has a hard reg. */
1993 if (chain->rld[i].reg_rtx)
1995 int regno = REGNO (chain->rld[i].reg_rtx);
1996 chain->rld[i].regno = regno;
1998 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
2001 chain->rld[i].regno = -1;
2002 reload_order[i] = i;
2005 n_reloads = chain->n_reloads;
2006 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
2008 CLEAR_HARD_REG_SET (used_spill_regs_local);
2011 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
2013 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
2015 /* Compute the order of preference for hard registers to spill. */
2017 order_regs_for_reload (chain);
2019 for (i = 0; i < n_reloads; i++)
2021 int r = reload_order[i];
2023 /* Ignore reloads that got marked inoperative. */
2024 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2025 && ! rld[r].optional
2026 && rld[r].regno == -1)
2027 if (! find_reg (chain, i))
2030 fprintf (dump_file, "reload failure for reload %d\n", r);
2031 spill_failure (chain->insn, rld[r].rclass);
2037 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2038 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2040 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2044 select_reload_regs (void)
2046 struct insn_chain *chain;
2048 /* Try to satisfy the needs for each insn. */
2049 for (chain = insns_need_reload; chain != 0;
2050 chain = chain->next_need_reload)
2051 find_reload_regs (chain);
2054 /* Delete all insns that were inserted by emit_caller_save_insns during
2057 delete_caller_save_insns (void)
2059 struct insn_chain *c = reload_insn_chain;
2063 while (c != 0 && c->is_caller_save_insn)
2065 struct insn_chain *next = c->next;
2068 if (c == reload_insn_chain)
2069 reload_insn_chain = next;
2073 next->prev = c->prev;
2075 c->prev->next = next;
2076 c->next = unused_insn_chains;
2077 unused_insn_chains = c;
2085 /* Handle the failure to find a register to spill.
2086 INSN should be one of the insns which needed this particular spill reg. */
2089 spill_failure (rtx insn, enum reg_class rclass)
2091 if (asm_noperands (PATTERN (insn)) >= 0)
2092 error_for_asm (insn, "can%'t find a register in class %qs while "
2093 "reloading %<asm%>",
2094 reg_class_names[rclass]);
2097 error ("unable to find a register to spill in class %qs",
2098 reg_class_names[rclass]);
2102 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2103 debug_reload_to_stream (dump_file);
2105 fatal_insn ("this is the insn:", insn);
2109 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2110 data that is dead in INSN. */
2113 delete_dead_insn (rtx insn)
2115 rtx prev = prev_active_insn (insn);
2118 /* If the previous insn sets a register that dies in our insn, delete it
2120 if (prev && GET_CODE (PATTERN (prev)) == SET
2121 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2122 && reg_mentioned_p (prev_dest, PATTERN (insn))
2123 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2124 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2125 delete_dead_insn (prev);
2127 SET_INSN_DELETED (insn);
2130 /* Modify the home of pseudo-reg I.
2131 The new home is present in reg_renumber[I].
2133 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2134 or it may be -1, meaning there is none or it is not relevant.
2135 This is used so that all pseudos spilled from a given hard reg
2136 can share one stack slot. */
2139 alter_reg (int i, int from_reg, bool dont_share_p)
2141 /* When outputting an inline function, this can happen
2142 for a reg that isn't actually used. */
2143 if (regno_reg_rtx[i] == 0)
2146 /* If the reg got changed to a MEM at rtl-generation time,
2148 if (!REG_P (regno_reg_rtx[i]))
2151 /* Modify the reg-rtx to contain the new hard reg
2152 number or else to contain its pseudo reg number. */
2153 SET_REGNO (regno_reg_rtx[i],
2154 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2156 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2157 allocate a stack slot for it. */
2159 if (reg_renumber[i] < 0
2160 && REG_N_REFS (i) > 0
2161 && reg_equiv_constant[i] == 0
2162 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
2163 && reg_equiv_memory_loc[i] == 0)
2166 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2167 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2168 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2169 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2170 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2173 something_was_spilled = true;
2175 if (ira_conflicts_p)
2177 /* Mark the spill for IRA. */
2178 SET_REGNO_REG_SET (&spilled_pseudos, i);
2180 x = ira_reuse_stack_slot (i, inherent_size, total_size);
2186 /* Each pseudo reg has an inherent size which comes from its own mode,
2187 and a total size which provides room for paradoxical subregs
2188 which refer to the pseudo reg in wider modes.
2190 We can use a slot already allocated if it provides both
2191 enough inherent space and enough total space.
2192 Otherwise, we allocate a new slot, making sure that it has no less
2193 inherent space, and no less total space, then the previous slot. */
2194 else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2198 /* No known place to spill from => no slot to reuse. */
2199 x = assign_stack_local (mode, total_size,
2200 min_align > inherent_align
2201 || total_size > inherent_size ? -1 : 0);
2205 /* Cancel the big-endian correction done in assign_stack_local.
2206 Get the address of the beginning of the slot. This is so we
2207 can do a big-endian correction unconditionally below. */
2208 if (BYTES_BIG_ENDIAN)
2210 adjust = inherent_size - total_size;
2213 = adjust_address_nv (x, mode_for_size (total_size
2219 if (! dont_share_p && ira_conflicts_p)
2220 /* Inform IRA about allocation a new stack slot. */
2221 ira_mark_new_stack_slot (stack_slot, i, total_size);
2224 /* Reuse a stack slot if possible. */
2225 else if (spill_stack_slot[from_reg] != 0
2226 && spill_stack_slot_width[from_reg] >= total_size
2227 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2229 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2230 x = spill_stack_slot[from_reg];
2232 /* Allocate a bigger slot. */
2235 /* Compute maximum size needed, both for inherent size
2236 and for total size. */
2239 if (spill_stack_slot[from_reg])
2241 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2243 mode = GET_MODE (spill_stack_slot[from_reg]);
2244 if (spill_stack_slot_width[from_reg] > total_size)
2245 total_size = spill_stack_slot_width[from_reg];
2246 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2247 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2250 /* Make a slot with that size. */
2251 x = assign_stack_local (mode, total_size,
2252 min_align > inherent_align
2253 || total_size > inherent_size ? -1 : 0);
2256 /* Cancel the big-endian correction done in assign_stack_local.
2257 Get the address of the beginning of the slot. This is so we
2258 can do a big-endian correction unconditionally below. */
2259 if (BYTES_BIG_ENDIAN)
2261 adjust = GET_MODE_SIZE (mode) - total_size;
2264 = adjust_address_nv (x, mode_for_size (total_size
2270 spill_stack_slot[from_reg] = stack_slot;
2271 spill_stack_slot_width[from_reg] = total_size;
2274 /* On a big endian machine, the "address" of the slot
2275 is the address of the low part that fits its inherent mode. */
2276 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2277 adjust += (total_size - inherent_size);
2279 /* If we have any adjustment to make, or if the stack slot is the
2280 wrong mode, make a new stack slot. */
2281 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2283 /* Set all of the memory attributes as appropriate for a spill. */
2284 set_mem_attrs_for_spill (x);
2286 /* Save the stack slot for later. */
2287 reg_equiv_memory_loc[i] = x;
2291 /* Mark the slots in regs_ever_live for the hard regs used by
2292 pseudo-reg number REGNO, accessed in MODE. */
2295 mark_home_live_1 (int regno, enum machine_mode mode)
2299 i = reg_renumber[regno];
2302 lim = end_hard_regno (mode, i);
2304 df_set_regs_ever_live(i++, true);
2307 /* Mark the slots in regs_ever_live for the hard regs
2308 used by pseudo-reg number REGNO. */
2311 mark_home_live (int regno)
2313 if (reg_renumber[regno] >= 0)
2314 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2317 /* This function handles the tracking of elimination offsets around branches.
2319 X is a piece of RTL being scanned.
2321 INSN is the insn that it came from, if any.
2323 INITIAL_P is nonzero if we are to set the offset to be the initial
2324 offset and zero if we are setting the offset of the label to be the
2328 set_label_offsets (rtx x, rtx insn, int initial_p)
2330 enum rtx_code code = GET_CODE (x);
2333 struct elim_table *p;
2338 if (LABEL_REF_NONLOCAL_P (x))
2343 /* ... fall through ... */
2346 /* If we know nothing about this label, set the desired offsets. Note
2347 that this sets the offset at a label to be the offset before a label
2348 if we don't know anything about the label. This is not correct for
2349 the label after a BARRIER, but is the best guess we can make. If
2350 we guessed wrong, we will suppress an elimination that might have
2351 been possible had we been able to guess correctly. */
2353 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2355 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2356 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2357 = (initial_p ? reg_eliminate[i].initial_offset
2358 : reg_eliminate[i].offset);
2359 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2362 /* Otherwise, if this is the definition of a label and it is
2363 preceded by a BARRIER, set our offsets to the known offset of
2367 && (tem = prev_nonnote_insn (insn)) != 0
2369 set_offsets_for_label (insn);
2371 /* If neither of the above cases is true, compare each offset
2372 with those previously recorded and suppress any eliminations
2373 where the offsets disagree. */
2375 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2376 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2377 != (initial_p ? reg_eliminate[i].initial_offset
2378 : reg_eliminate[i].offset))
2379 reg_eliminate[i].can_eliminate = 0;
2384 set_label_offsets (PATTERN (insn), insn, initial_p);
2386 /* ... fall through ... */
2390 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2391 to indirectly and hence must have all eliminations at their
2393 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2394 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2395 set_label_offsets (XEXP (tem, 0), insn, 1);
2401 /* Each of the labels in the parallel or address vector must be
2402 at their initial offsets. We want the first field for PARALLEL
2403 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2405 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2406 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2411 /* We only care about setting PC. If the source is not RETURN,
2412 IF_THEN_ELSE, or a label, disable any eliminations not at
2413 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2414 isn't one of those possibilities. For branches to a label,
2415 call ourselves recursively.
2417 Note that this can disable elimination unnecessarily when we have
2418 a non-local goto since it will look like a non-constant jump to
2419 someplace in the current function. This isn't a significant
2420 problem since such jumps will normally be when all elimination
2421 pairs are back to their initial offsets. */
2423 if (SET_DEST (x) != pc_rtx)
2426 switch (GET_CODE (SET_SRC (x)))
2433 set_label_offsets (SET_SRC (x), insn, initial_p);
2437 tem = XEXP (SET_SRC (x), 1);
2438 if (GET_CODE (tem) == LABEL_REF)
2439 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2440 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2443 tem = XEXP (SET_SRC (x), 2);
2444 if (GET_CODE (tem) == LABEL_REF)
2445 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2446 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2454 /* If we reach here, all eliminations must be at their initial
2455 offset because we are doing a jump to a variable address. */
2456 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2457 if (p->offset != p->initial_offset)
2458 p->can_eliminate = 0;
2466 /* Called through for_each_rtx, this function examines every reg that occurs
2467 in PX and adjusts the costs for its elimination which are gathered by IRA.
2468 DATA is the insn in which PX occurs. We do not recurse into MEM
2472 note_reg_elim_costly (rtx *px, void *data)
2474 rtx insn = (rtx)data;
2481 && REGNO (x) >= FIRST_PSEUDO_REGISTER
2482 && reg_equiv_init[REGNO (x)]
2483 && reg_equiv_invariant[REGNO (x)])
2485 rtx t = reg_equiv_invariant[REGNO (x)];
2486 rtx new_rtx = eliminate_regs_1 (t, Pmode, insn, true, true);
2487 int cost = rtx_cost (new_rtx, SET, optimize_bb_for_speed_p (elim_bb));
2488 int freq = REG_FREQ_FROM_BB (elim_bb);
2491 ira_adjust_equiv_reg_cost (REGNO (x), -cost * freq);
2496 /* Scan X and replace any eliminable registers (such as fp) with a
2497 replacement (such as sp), plus an offset.
2499 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2500 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2501 MEM, we are allowed to replace a sum of a register and the constant zero
2502 with the register, which we cannot do outside a MEM. In addition, we need
2503 to record the fact that a register is referenced outside a MEM.
2505 If INSN is an insn, it is the insn containing X. If we replace a REG
2506 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2507 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2508 the REG is being modified.
2510 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2511 That's used when we eliminate in expressions stored in notes.
2512 This means, do not set ref_outside_mem even if the reference
2515 If FOR_COSTS is true, we are being called before reload in order to
2516 estimate the costs of keeping registers with an equivalence unallocated.
2518 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2519 replacements done assuming all offsets are at their initial values. If
2520 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2521 encounter, return the actual location so that find_reloads will do
2522 the proper thing. */
2525 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2526 bool may_use_invariant, bool for_costs)
2528 enum rtx_code code = GET_CODE (x);
2529 struct elim_table *ep;
2536 if (! current_function_decl)
2559 /* First handle the case where we encounter a bare register that
2560 is eliminable. Replace it with a PLUS. */
2561 if (regno < FIRST_PSEUDO_REGISTER)
2563 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2565 if (ep->from_rtx == x && ep->can_eliminate)
2566 return plus_constant (ep->to_rtx, ep->previous_offset);
2569 else if (reg_renumber && reg_renumber[regno] < 0
2570 && reg_equiv_invariant && reg_equiv_invariant[regno])
2572 if (may_use_invariant || (insn && DEBUG_INSN_P (insn)))
2573 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2574 mem_mode, insn, true, for_costs);
2575 /* There exists at least one use of REGNO that cannot be
2576 eliminated. Prevent the defining insn from being deleted. */
2577 reg_equiv_init[regno] = NULL_RTX;
2579 alter_reg (regno, -1, true);
2583 /* You might think handling MINUS in a manner similar to PLUS is a
2584 good idea. It is not. It has been tried multiple times and every
2585 time the change has had to have been reverted.
2587 Other parts of reload know a PLUS is special (gen_reload for example)
2588 and require special code to handle code a reloaded PLUS operand.
2590 Also consider backends where the flags register is clobbered by a
2591 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2592 lea instruction comes to mind). If we try to reload a MINUS, we
2593 may kill the flags register that was holding a useful value.
2595 So, please before trying to handle MINUS, consider reload as a
2596 whole instead of this little section as well as the backend issues. */
2598 /* If this is the sum of an eliminable register and a constant, rework
2600 if (REG_P (XEXP (x, 0))
2601 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2602 && CONSTANT_P (XEXP (x, 1)))
2604 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2606 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2608 /* The only time we want to replace a PLUS with a REG (this
2609 occurs when the constant operand of the PLUS is the negative
2610 of the offset) is when we are inside a MEM. We won't want
2611 to do so at other times because that would change the
2612 structure of the insn in a way that reload can't handle.
2613 We special-case the commonest situation in
2614 eliminate_regs_in_insn, so just replace a PLUS with a
2615 PLUS here, unless inside a MEM. */
2616 if (mem_mode != 0 && CONST_INT_P (XEXP (x, 1))
2617 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2620 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2621 plus_constant (XEXP (x, 1),
2622 ep->previous_offset));
2625 /* If the register is not eliminable, we are done since the other
2626 operand is a constant. */
2630 /* If this is part of an address, we want to bring any constant to the
2631 outermost PLUS. We will do this by doing register replacement in
2632 our operands and seeing if a constant shows up in one of them.
2634 Note that there is no risk of modifying the structure of the insn,
2635 since we only get called for its operands, thus we are either
2636 modifying the address inside a MEM, or something like an address
2637 operand of a load-address insn. */
2640 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2642 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2645 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2647 /* If one side is a PLUS and the other side is a pseudo that
2648 didn't get a hard register but has a reg_equiv_constant,
2649 we must replace the constant here since it may no longer
2650 be in the position of any operand. */
2651 if (GET_CODE (new0) == PLUS && REG_P (new1)
2652 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2653 && reg_renumber[REGNO (new1)] < 0
2654 && reg_equiv_constant != 0
2655 && reg_equiv_constant[REGNO (new1)] != 0)
2656 new1 = reg_equiv_constant[REGNO (new1)];
2657 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2658 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2659 && reg_renumber[REGNO (new0)] < 0
2660 && reg_equiv_constant[REGNO (new0)] != 0)
2661 new0 = reg_equiv_constant[REGNO (new0)];
2663 new_rtx = form_sum (GET_MODE (x), new0, new1);
2665 /* As above, if we are not inside a MEM we do not want to
2666 turn a PLUS into something else. We might try to do so here
2667 for an addition of 0 if we aren't optimizing. */
2668 if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2669 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2677 /* If this is the product of an eliminable register and a
2678 constant, apply the distribute law and move the constant out
2679 so that we have (plus (mult ..) ..). This is needed in order
2680 to keep load-address insns valid. This case is pathological.
2681 We ignore the possibility of overflow here. */
2682 if (REG_P (XEXP (x, 0))
2683 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2684 && CONST_INT_P (XEXP (x, 1)))
2685 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2687 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2690 /* Refs inside notes or in DEBUG_INSNs don't count for
2692 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2693 || GET_CODE (insn) == INSN_LIST
2694 || DEBUG_INSN_P (insn))))
2695 ep->ref_outside_mem = 1;
2698 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2699 ep->previous_offset * INTVAL (XEXP (x, 1)));
2702 /* ... fall through ... */
2706 /* See comments before PLUS about handling MINUS. */
2708 case DIV: case UDIV:
2709 case MOD: case UMOD:
2710 case AND: case IOR: case XOR:
2711 case ROTATERT: case ROTATE:
2712 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2714 case GE: case GT: case GEU: case GTU:
2715 case LE: case LT: case LEU: case LTU:
2717 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2719 rtx new1 = XEXP (x, 1)
2720 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false,
2723 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2724 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2729 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2732 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2734 if (new_rtx != XEXP (x, 0))
2736 /* If this is a REG_DEAD note, it is not valid anymore.
2737 Using the eliminated version could result in creating a
2738 REG_DEAD note for the stack or frame pointer. */
2739 if (REG_NOTE_KIND (x) == REG_DEAD)
2741 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2745 x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2749 /* ... fall through ... */
2752 /* Now do eliminations in the rest of the chain. If this was
2753 an EXPR_LIST, this might result in allocating more memory than is
2754 strictly needed, but it simplifies the code. */
2757 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2759 if (new_rtx != XEXP (x, 1))
2761 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2769 /* We do not support elimination of a register that is modified.
2770 elimination_effects has already make sure that this does not
2776 /* We do not support elimination of a register that is modified.
2777 elimination_effects has already make sure that this does not
2778 happen. The only remaining case we need to consider here is
2779 that the increment value may be an eliminable register. */
2780 if (GET_CODE (XEXP (x, 1)) == PLUS
2781 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2783 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2784 insn, true, for_costs);
2786 if (new_rtx != XEXP (XEXP (x, 1), 1))
2787 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2788 gen_rtx_PLUS (GET_MODE (x),
2789 XEXP (x, 0), new_rtx));
2793 case STRICT_LOW_PART:
2795 case SIGN_EXTEND: case ZERO_EXTEND:
2796 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2797 case FLOAT: case FIX:
2798 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2807 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2809 if (new_rtx != XEXP (x, 0))
2810 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2814 /* Similar to above processing, but preserve SUBREG_BYTE.
2815 Convert (subreg (mem)) to (mem) if not paradoxical.
2816 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2817 pseudo didn't get a hard reg, we must replace this with the
2818 eliminated version of the memory location because push_reload
2819 may do the replacement in certain circumstances. */
2820 if (REG_P (SUBREG_REG (x))
2821 && (GET_MODE_SIZE (GET_MODE (x))
2822 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2823 && reg_equiv_memory_loc != 0
2824 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2826 new_rtx = SUBREG_REG (x);
2829 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false,
2832 if (new_rtx != SUBREG_REG (x))
2834 int x_size = GET_MODE_SIZE (GET_MODE (x));
2835 int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2838 && ((x_size < new_size
2839 #ifdef WORD_REGISTER_OPERATIONS
2840 /* On these machines, combine can create rtl of the form
2841 (set (subreg:m1 (reg:m2 R) 0) ...)
2842 where m1 < m2, and expects something interesting to
2843 happen to the entire word. Moreover, it will use the
2844 (reg:m2 R) later, expecting all bits to be preserved.
2845 So if the number of words is the same, preserve the
2846 subreg so that push_reload can see it. */
2847 && ! ((x_size - 1) / UNITS_PER_WORD
2848 == (new_size -1 ) / UNITS_PER_WORD)
2851 || x_size == new_size)
2853 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2855 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2861 /* Our only special processing is to pass the mode of the MEM to our
2862 recursive call and copy the flags. While we are here, handle this
2863 case more efficiently. */
2865 new_rtx = eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), insn, true,
2868 && memory_address_p (GET_MODE (x), XEXP (x, 0))
2869 && !memory_address_p (GET_MODE (x), new_rtx))
2870 for_each_rtx (&XEXP (x, 0), note_reg_elim_costly, insn);
2872 return replace_equiv_address_nv (x, new_rtx);
2875 /* Handle insn_list USE that a call to a pure function may generate. */
2876 new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false,
2878 if (new_rtx != XEXP (x, 0))
2879 return gen_rtx_USE (GET_MODE (x), new_rtx);
2884 gcc_assert (insn && DEBUG_INSN_P (insn));
2894 /* Process each of our operands recursively. If any have changed, make a
2896 fmt = GET_RTX_FORMAT (code);
2897 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2901 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false,
2903 if (new_rtx != XEXP (x, i) && ! copied)
2905 x = shallow_copy_rtx (x);
2908 XEXP (x, i) = new_rtx;
2910 else if (*fmt == 'E')
2913 for (j = 0; j < XVECLEN (x, i); j++)
2915 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false,
2917 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2919 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2923 x = shallow_copy_rtx (x);
2926 XVEC (x, i) = new_v;
2929 XVECEXP (x, i, j) = new_rtx;
2938 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2940 return eliminate_regs_1 (x, mem_mode, insn, false, false);
2943 /* Scan rtx X for modifications of elimination target registers. Update
2944 the table of eliminables to reflect the changed state. MEM_MODE is
2945 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2948 elimination_effects (rtx x, enum machine_mode mem_mode)
2950 enum rtx_code code = GET_CODE (x);
2951 struct elim_table *ep;
2976 /* First handle the case where we encounter a bare register that
2977 is eliminable. Replace it with a PLUS. */
2978 if (regno < FIRST_PSEUDO_REGISTER)
2980 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2982 if (ep->from_rtx == x && ep->can_eliminate)
2985 ep->ref_outside_mem = 1;
2990 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2991 && reg_equiv_constant[regno]
2992 && ! function_invariant_p (reg_equiv_constant[regno]))
2993 elimination_effects (reg_equiv_constant[regno], mem_mode);
3002 /* If we modify the source of an elimination rule, disable it. */
3003 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3004 if (ep->from_rtx == XEXP (x, 0))
3005 ep->can_eliminate = 0;
3007 /* If we modify the target of an elimination rule by adding a constant,
3008 update its offset. If we modify the target in any other way, we'll
3009 have to disable the rule as well. */
3010 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3011 if (ep->to_rtx == XEXP (x, 0))
3013 int size = GET_MODE_SIZE (mem_mode);
3015 /* If more bytes than MEM_MODE are pushed, account for them. */
3016 #ifdef PUSH_ROUNDING
3017 if (ep->to_rtx == stack_pointer_rtx)
3018 size = PUSH_ROUNDING (size);
3020 if (code == PRE_DEC || code == POST_DEC)
3022 else if (code == PRE_INC || code == POST_INC)
3024 else if (code == PRE_MODIFY || code == POST_MODIFY)
3026 if (GET_CODE (XEXP (x, 1)) == PLUS
3027 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
3028 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
3029 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
3031 ep->can_eliminate = 0;
3035 /* These two aren't unary operators. */
3036 if (code == POST_MODIFY || code == PRE_MODIFY)
3039 /* Fall through to generic unary operation case. */
3040 case STRICT_LOW_PART:
3042 case SIGN_EXTEND: case ZERO_EXTEND:
3043 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3044 case FLOAT: case FIX:
3045 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3054 elimination_effects (XEXP (x, 0), mem_mode);
3058 if (REG_P (SUBREG_REG (x))
3059 && (GET_MODE_SIZE (GET_MODE (x))
3060 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3061 && reg_equiv_memory_loc != 0
3062 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
3065 elimination_effects (SUBREG_REG (x), mem_mode);
3069 /* If using a register that is the source of an eliminate we still
3070 think can be performed, note it cannot be performed since we don't
3071 know how this register is used. */
3072 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3073 if (ep->from_rtx == XEXP (x, 0))
3074 ep->can_eliminate = 0;
3076 elimination_effects (XEXP (x, 0), mem_mode);
3080 /* If clobbering a register that is the replacement register for an
3081 elimination we still think can be performed, note that it cannot
3082 be performed. Otherwise, we need not be concerned about it. */
3083 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3084 if (ep->to_rtx == XEXP (x, 0))
3085 ep->can_eliminate = 0;
3087 elimination_effects (XEXP (x, 0), mem_mode);
3091 /* Check for setting a register that we know about. */
3092 if (REG_P (SET_DEST (x)))
3094 /* See if this is setting the replacement register for an
3097 If DEST is the hard frame pointer, we do nothing because we
3098 assume that all assignments to the frame pointer are for
3099 non-local gotos and are being done at a time when they are valid
3100 and do not disturb anything else. Some machines want to
3101 eliminate a fake argument pointer (or even a fake frame pointer)
3102 with either the real frame or the stack pointer. Assignments to
3103 the hard frame pointer must not prevent this elimination. */
3105 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3107 if (ep->to_rtx == SET_DEST (x)
3108 && SET_DEST (x) != hard_frame_pointer_rtx)
3110 /* If it is being incremented, adjust the offset. Otherwise,
3111 this elimination can't be done. */
3112 rtx src = SET_SRC (x);
3114 if (GET_CODE (src) == PLUS
3115 && XEXP (src, 0) == SET_DEST (x)
3116 && CONST_INT_P (XEXP (src, 1)))
3117 ep->offset -= INTVAL (XEXP (src, 1));
3119 ep->can_eliminate = 0;
3123 elimination_effects (SET_DEST (x), VOIDmode);
3124 elimination_effects (SET_SRC (x), VOIDmode);
3128 /* Our only special processing is to pass the mode of the MEM to our
3130 elimination_effects (XEXP (x, 0), GET_MODE (x));
3137 fmt = GET_RTX_FORMAT (code);
3138 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3141 elimination_effects (XEXP (x, i), mem_mode);
3142 else if (*fmt == 'E')
3143 for (j = 0; j < XVECLEN (x, i); j++)
3144 elimination_effects (XVECEXP (x, i, j), mem_mode);
3148 /* Descend through rtx X and verify that no references to eliminable registers
3149 remain. If any do remain, mark the involved register as not
3153 check_eliminable_occurrences (rtx x)
3162 code = GET_CODE (x);
3164 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3166 struct elim_table *ep;
3168 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3169 if (ep->from_rtx == x)
3170 ep->can_eliminate = 0;
3174 fmt = GET_RTX_FORMAT (code);
3175 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3178 check_eliminable_occurrences (XEXP (x, i));
3179 else if (*fmt == 'E')
3182 for (j = 0; j < XVECLEN (x, i); j++)
3183 check_eliminable_occurrences (XVECEXP (x, i, j));
3188 /* Scan INSN and eliminate all eliminable registers in it.
3190 If REPLACE is nonzero, do the replacement destructively. Also
3191 delete the insn as dead it if it is setting an eliminable register.
3193 If REPLACE is zero, do all our allocations in reload_obstack.
3195 If no eliminations were done and this insn doesn't require any elimination
3196 processing (these are not identical conditions: it might be updating sp,
3197 but not referencing fp; this needs to be seen during reload_as_needed so
3198 that the offset between fp and sp can be taken into consideration), zero
3199 is returned. Otherwise, 1 is returned. */
3202 eliminate_regs_in_insn (rtx insn, int replace)
3204 int icode = recog_memoized (insn);
3205 rtx old_body = PATTERN (insn);
3206 int insn_is_asm = asm_noperands (old_body) >= 0;
3207 rtx old_set = single_set (insn);
3211 rtx substed_operand[MAX_RECOG_OPERANDS];
3212 rtx orig_operand[MAX_RECOG_OPERANDS];
3213 struct elim_table *ep;
3214 rtx plus_src, plus_cst_src;
3216 if (! insn_is_asm && icode < 0)
3218 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3219 || GET_CODE (PATTERN (insn)) == CLOBBER
3220 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3221 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3222 || GET_CODE (PATTERN (insn)) == ASM_INPUT
3223 || DEBUG_INSN_P (insn));
3224 if (DEBUG_INSN_P (insn))
3225 INSN_VAR_LOCATION_LOC (insn)
3226 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn), VOIDmode, insn);
3230 if (old_set != 0 && REG_P (SET_DEST (old_set))
3231 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3233 /* Check for setting an eliminable register. */
3234 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3235 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3237 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
3238 /* If this is setting the frame pointer register to the
3239 hardware frame pointer register and this is an elimination
3240 that will be done (tested above), this insn is really
3241 adjusting the frame pointer downward to compensate for
3242 the adjustment done before a nonlocal goto. */
3243 if (ep->from == FRAME_POINTER_REGNUM
3244 && ep->to == HARD_FRAME_POINTER_REGNUM)
3246 rtx base = SET_SRC (old_set);
3247 rtx base_insn = insn;
3248 HOST_WIDE_INT offset = 0;
3250 while (base != ep->to_rtx)
3252 rtx prev_insn, prev_set;
3254 if (GET_CODE (base) == PLUS
3255 && CONST_INT_P (XEXP (base, 1)))
3257 offset += INTVAL (XEXP (base, 1));
3258 base = XEXP (base, 0);
3260 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3261 && (prev_set = single_set (prev_insn)) != 0
3262 && rtx_equal_p (SET_DEST (prev_set), base))
3264 base = SET_SRC (prev_set);
3265 base_insn = prev_insn;
3271 if (base == ep->to_rtx)
3274 = plus_constant (ep->to_rtx, offset - ep->offset);
3276 new_body = old_body;
3279 new_body = copy_insn (old_body);
3280 if (REG_NOTES (insn))
3281 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3283 PATTERN (insn) = new_body;
3284 old_set = single_set (insn);
3286 /* First see if this insn remains valid when we
3287 make the change. If not, keep the INSN_CODE
3288 the same and let reload fit it up. */
3289 validate_change (insn, &SET_SRC (old_set), src, 1);
3290 validate_change (insn, &SET_DEST (old_set),
3292 if (! apply_change_group ())
3294 SET_SRC (old_set) = src;
3295 SET_DEST (old_set) = ep->to_rtx;
3304 /* In this case this insn isn't serving a useful purpose. We
3305 will delete it in reload_as_needed once we know that this
3306 elimination is, in fact, being done.
3308 If REPLACE isn't set, we can't delete this insn, but needn't
3309 process it since it won't be used unless something changes. */
3312 delete_dead_insn (insn);
3320 /* We allow one special case which happens to work on all machines we
3321 currently support: a single set with the source or a REG_EQUAL
3322 note being a PLUS of an eliminable register and a constant. */
3323 plus_src = plus_cst_src = 0;
3324 if (old_set && REG_P (SET_DEST (old_set)))
3326 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3327 plus_src = SET_SRC (old_set);
3328 /* First see if the source is of the form (plus (...) CST). */
3330 && CONST_INT_P (XEXP (plus_src, 1)))
3331 plus_cst_src = plus_src;
3332 else if (REG_P (SET_SRC (old_set))
3335 /* Otherwise, see if we have a REG_EQUAL note of the form
3336 (plus (...) CST). */
3338 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3340 if ((REG_NOTE_KIND (links) == REG_EQUAL
3341 || REG_NOTE_KIND (links) == REG_EQUIV)
3342 && GET_CODE (XEXP (links, 0)) == PLUS
3343 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3345 plus_cst_src = XEXP (links, 0);
3351 /* Check that the first operand of the PLUS is a hard reg or
3352 the lowpart subreg of one. */
3355 rtx reg = XEXP (plus_cst_src, 0);
3356 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3357 reg = SUBREG_REG (reg);
3359 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3365 rtx reg = XEXP (plus_cst_src, 0);
3366 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3368 if (GET_CODE (reg) == SUBREG)
3369 reg = SUBREG_REG (reg);
3371 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3372 if (ep->from_rtx == reg && ep->can_eliminate)
3374 rtx to_rtx = ep->to_rtx;
3375 offset += ep->offset;
3376 offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3378 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3379 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3381 /* If we have a nonzero offset, and the source is already
3382 a simple REG, the following transformation would
3383 increase the cost of the insn by replacing a simple REG
3384 with (plus (reg sp) CST). So try only when we already
3385 had a PLUS before. */
3386 if (offset == 0 || plus_src)
3388 rtx new_src = plus_constant (to_rtx, offset);
3390 new_body = old_body;
3393 new_body = copy_insn (old_body);
3394 if (REG_NOTES (insn))
3395 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3397 PATTERN (insn) = new_body;
3398 old_set = single_set (insn);
3400 /* First see if this insn remains valid when we make the
3401 change. If not, try to replace the whole pattern with
3402 a simple set (this may help if the original insn was a
3403 PARALLEL that was only recognized as single_set due to
3404 REG_UNUSED notes). If this isn't valid either, keep
3405 the INSN_CODE the same and let reload fix it up. */
3406 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3408 rtx new_pat = gen_rtx_SET (VOIDmode,
3409 SET_DEST (old_set), new_src);
3411 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3412 SET_SRC (old_set) = new_src;
3419 /* This can't have an effect on elimination offsets, so skip right
3425 /* Determine the effects of this insn on elimination offsets. */
3426 elimination_effects (old_body, VOIDmode);
3428 /* Eliminate all eliminable registers occurring in operands that
3429 can be handled by reload. */
3430 extract_insn (insn);
3431 for (i = 0; i < recog_data.n_operands; i++)
3433 orig_operand[i] = recog_data.operand[i];
3434 substed_operand[i] = recog_data.operand[i];
3436 /* For an asm statement, every operand is eliminable. */
3437 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3439 bool is_set_src, in_plus;
3441 /* Check for setting a register that we know about. */
3442 if (recog_data.operand_type[i] != OP_IN
3443 && REG_P (orig_operand[i]))
3445 /* If we are assigning to a register that can be eliminated, it
3446 must be as part of a PARALLEL, since the code above handles
3447 single SETs. We must indicate that we can no longer
3448 eliminate this reg. */
3449 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3451 if (ep->from_rtx == orig_operand[i])
3452 ep->can_eliminate = 0;
3455 /* Companion to the above plus substitution, we can allow
3456 invariants as the source of a plain move. */
3459 && recog_data.operand_loc[i] == &SET_SRC (old_set))
3463 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3464 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3468 = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3469 replace ? insn : NULL_RTX,
3470 is_set_src || in_plus, false);
3471 if (substed_operand[i] != orig_operand[i])
3473 /* Terminate the search in check_eliminable_occurrences at
3475 *recog_data.operand_loc[i] = 0;
3477 /* If an output operand changed from a REG to a MEM and INSN is an
3478 insn, write a CLOBBER insn. */
3479 if (recog_data.operand_type[i] != OP_IN
3480 && REG_P (orig_operand[i])
3481 && MEM_P (substed_operand[i])
3483 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3487 for (i = 0; i < recog_data.n_dups; i++)
3488 *recog_data.dup_loc[i]
3489 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3491 /* If any eliminable remain, they aren't eliminable anymore. */
3492 check_eliminable_occurrences (old_body);
3494 /* Substitute the operands; the new values are in the substed_operand
3496 for (i = 0; i < recog_data.n_operands; i++)
3497 *recog_data.operand_loc[i] = substed_operand[i];
3498 for (i = 0; i < recog_data.n_dups; i++)
3499 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3501 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3502 re-recognize the insn. We do this in case we had a simple addition
3503 but now can do this as a load-address. This saves an insn in this
3505 If re-recognition fails, the old insn code number will still be used,
3506 and some register operands may have changed into PLUS expressions.
3507 These will be handled by find_reloads by loading them into a register
3512 /* If we aren't replacing things permanently and we changed something,
3513 make another copy to ensure that all the RTL is new. Otherwise
3514 things can go wrong if find_reload swaps commutative operands
3515 and one is inside RTL that has been copied while the other is not. */
3516 new_body = old_body;
3519 new_body = copy_insn (old_body);
3520 if (REG_NOTES (insn))
3521 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3523 PATTERN (insn) = new_body;
3525 /* If we had a move insn but now we don't, rerecognize it. This will
3526 cause spurious re-recognition if the old move had a PARALLEL since
3527 the new one still will, but we can't call single_set without
3528 having put NEW_BODY into the insn and the re-recognition won't
3529 hurt in this rare case. */
3530 /* ??? Why this huge if statement - why don't we just rerecognize the
3534 && ((REG_P (SET_SRC (old_set))
3535 && (GET_CODE (new_body) != SET
3536 || !REG_P (SET_SRC (new_body))))
3537 /* If this was a load from or store to memory, compare
3538 the MEM in recog_data.operand to the one in the insn.
3539 If they are not equal, then rerecognize the insn. */
3541 && ((MEM_P (SET_SRC (old_set))
3542 && SET_SRC (old_set) != recog_data.operand[1])
3543 || (MEM_P (SET_DEST (old_set))
3544 && SET_DEST (old_set) != recog_data.operand[0])))
3545 /* If this was an add insn before, rerecognize. */
3546 || GET_CODE (SET_SRC (old_set)) == PLUS))
3548 int new_icode = recog (PATTERN (insn), insn, 0);
3550 INSN_CODE (insn) = new_icode;
3554 /* Restore the old body. If there were any changes to it, we made a copy
3555 of it while the changes were still in place, so we'll correctly return
3556 a modified insn below. */
3559 /* Restore the old body. */
3560 for (i = 0; i < recog_data.n_operands; i++)
3561 /* Restoring a top-level match_parallel would clobber the new_body
3562 we installed in the insn. */
3563 if (recog_data.operand_loc[i] != &PATTERN (insn))
3564 *recog_data.operand_loc[i] = orig_operand[i];
3565 for (i = 0; i < recog_data.n_dups; i++)
3566 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3569 /* Update all elimination pairs to reflect the status after the current
3570 insn. The changes we make were determined by the earlier call to
3571 elimination_effects.
3573 We also detect cases where register elimination cannot be done,
3574 namely, if a register would be both changed and referenced outside a MEM
3575 in the resulting insn since such an insn is often undefined and, even if
3576 not, we cannot know what meaning will be given to it. Note that it is
3577 valid to have a register used in an address in an insn that changes it
3578 (presumably with a pre- or post-increment or decrement).
3580 If anything changes, return nonzero. */
3582 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3584 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3585 ep->can_eliminate = 0;
3587 ep->ref_outside_mem = 0;
3589 if (ep->previous_offset != ep->offset)
3594 /* If we changed something, perform elimination in REG_NOTES. This is
3595 needed even when REPLACE is zero because a REG_DEAD note might refer
3596 to a register that we eliminate and could cause a different number
3597 of spill registers to be needed in the final reload pass than in
3599 if (val && REG_NOTES (insn) != 0)
3601 = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true,
3607 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3608 register allocator. INSN is the instruction we need to examine, we perform
3609 eliminations in its operands and record cases where eliminating a reg with
3610 an invariant equivalence would add extra cost. */
3613 elimination_costs_in_insn (rtx insn)
3615 int icode = recog_memoized (insn);
3616 rtx old_body = PATTERN (insn);
3617 int insn_is_asm = asm_noperands (old_body) >= 0;
3618 rtx old_set = single_set (insn);
3620 rtx orig_operand[MAX_RECOG_OPERANDS];
3621 rtx orig_dup[MAX_RECOG_OPERANDS];
3622 struct elim_table *ep;
3623 rtx plus_src, plus_cst_src;
3626 if (! insn_is_asm && icode < 0)
3628 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3629 || GET_CODE (PATTERN (insn)) == CLOBBER
3630 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3631 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3632 || GET_CODE (PATTERN (insn)) == ASM_INPUT
3633 || DEBUG_INSN_P (insn));
3637 if (old_set != 0 && REG_P (SET_DEST (old_set))
3638 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3640 /* Check for setting an eliminable register. */
3641 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3642 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3646 /* We allow one special case which happens to work on all machines we
3647 currently support: a single set with the source or a REG_EQUAL
3648 note being a PLUS of an eliminable register and a constant. */
3649 plus_src = plus_cst_src = 0;
3651 if (old_set && REG_P (SET_DEST (old_set)))
3654 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3655 plus_src = SET_SRC (old_set);
3656 /* First see if the source is of the form (plus (...) CST). */
3658 && CONST_INT_P (XEXP (plus_src, 1)))
3659 plus_cst_src = plus_src;
3660 else if (REG_P (SET_SRC (old_set))
3663 /* Otherwise, see if we have a REG_EQUAL note of the form
3664 (plus (...) CST). */
3666 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3668 if ((REG_NOTE_KIND (links) == REG_EQUAL
3669 || REG_NOTE_KIND (links) == REG_EQUIV)
3670 && GET_CODE (XEXP (links, 0)) == PLUS
3671 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3673 plus_cst_src = XEXP (links, 0);
3680 /* Determine the effects of this insn on elimination offsets. */
3681 elimination_effects (old_body, VOIDmode);
3683 /* Eliminate all eliminable registers occurring in operands that
3684 can be handled by reload. */
3685 extract_insn (insn);
3686 for (i = 0; i < recog_data.n_dups; i++)
3687 orig_dup[i] = *recog_data.dup_loc[i];
3689 for (i = 0; i < recog_data.n_operands; i++)
3691 orig_operand[i] = recog_data.operand[i];
3693 /* For an asm statement, every operand is eliminable. */
3694 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3696 bool is_set_src, in_plus;
3698 /* Check for setting a register that we know about. */
3699 if (recog_data.operand_type[i] != OP_IN
3700 && REG_P (orig_operand[i]))
3702 /* If we are assigning to a register that can be eliminated, it
3703 must be as part of a PARALLEL, since the code above handles
3704 single SETs. We must indicate that we can no longer
3705 eliminate this reg. */
3706 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3708 if (ep->from_rtx == orig_operand[i])
3709 ep->can_eliminate = 0;
3712 /* Companion to the above plus substitution, we can allow
3713 invariants as the source of a plain move. */
3715 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3717 if (is_set_src && !sets_reg_p)
3718 note_reg_elim_costly (&SET_SRC (old_set), insn);
3720 if (plus_src && sets_reg_p
3721 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3722 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3725 eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3727 is_set_src || in_plus, true);
3728 /* Terminate the search in check_eliminable_occurrences at
3730 *recog_data.operand_loc[i] = 0;
3734 for (i = 0; i < recog_data.n_dups; i++)
3735 *recog_data.dup_loc[i]
3736 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3738 /* If any eliminable remain, they aren't eliminable anymore. */
3739 check_eliminable_occurrences (old_body);
3741 /* Restore the old body. */
3742 for (i = 0; i < recog_data.n_operands; i++)
3743 *recog_data.operand_loc[i] = orig_operand[i];
3744 for (i = 0; i < recog_data.n_dups; i++)
3745 *recog_data.dup_loc[i] = orig_dup[i];
3747 /* Update all elimination pairs to reflect the status after the current
3748 insn. The changes we make were determined by the earlier call to
3749 elimination_effects. */
3751 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3753 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3754 ep->can_eliminate = 0;
3756 ep->ref_outside_mem = 0;
3762 /* Loop through all elimination pairs.
3763 Recalculate the number not at initial offset.
3765 Compute the maximum offset (minimum offset if the stack does not
3766 grow downward) for each elimination pair. */
3769 update_eliminable_offsets (void)
3771 struct elim_table *ep;
3773 num_not_at_initial_offset = 0;
3774 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3776 ep->previous_offset = ep->offset;
3777 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3778 num_not_at_initial_offset++;
3782 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3783 replacement we currently believe is valid, mark it as not eliminable if X
3784 modifies DEST in any way other than by adding a constant integer to it.
3786 If DEST is the frame pointer, we do nothing because we assume that
3787 all assignments to the hard frame pointer are nonlocal gotos and are being
3788 done at a time when they are valid and do not disturb anything else.
3789 Some machines want to eliminate a fake argument pointer with either the
3790 frame or stack pointer. Assignments to the hard frame pointer must not
3791 prevent this elimination.
3793 Called via note_stores from reload before starting its passes to scan
3794 the insns of the function. */
3797 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3801 /* A SUBREG of a hard register here is just changing its mode. We should
3802 not see a SUBREG of an eliminable hard register, but check just in
3804 if (GET_CODE (dest) == SUBREG)
3805 dest = SUBREG_REG (dest);
3807 if (dest == hard_frame_pointer_rtx)
3810 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3811 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3812 && (GET_CODE (x) != SET
3813 || GET_CODE (SET_SRC (x)) != PLUS
3814 || XEXP (SET_SRC (x), 0) != dest
3815 || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
3817 reg_eliminate[i].can_eliminate_previous
3818 = reg_eliminate[i].can_eliminate = 0;
3823 /* Verify that the initial elimination offsets did not change since the
3824 last call to set_initial_elim_offsets. This is used to catch cases
3825 where something illegal happened during reload_as_needed that could
3826 cause incorrect code to be generated if we did not check for it. */
3829 verify_initial_elim_offsets (void)
3833 if (!num_eliminable)
3836 #ifdef ELIMINABLE_REGS
3838 struct elim_table *ep;
3840 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3842 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3843 if (t != ep->initial_offset)
3848 INITIAL_FRAME_POINTER_OFFSET (t);
3849 if (t != reg_eliminate[0].initial_offset)
3856 /* Reset all offsets on eliminable registers to their initial values. */
3859 set_initial_elim_offsets (void)
3861 struct elim_table *ep = reg_eliminate;
3863 #ifdef ELIMINABLE_REGS
3864 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3866 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3867 ep->previous_offset = ep->offset = ep->initial_offset;
3870 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3871 ep->previous_offset = ep->offset = ep->initial_offset;
3874 num_not_at_initial_offset = 0;
3877 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3880 set_initial_eh_label_offset (rtx label)
3882 set_label_offsets (label, NULL_RTX, 1);
3885 /* Initialize the known label offsets.
3886 Set a known offset for each forced label to be at the initial offset
3887 of each elimination. We do this because we assume that all
3888 computed jumps occur from a location where each elimination is
3889 at its initial offset.
3890 For all other labels, show that we don't know the offsets. */
3893 set_initial_label_offsets (void)
3896 memset (offsets_known_at, 0, num_labels);
3898 for (x = forced_labels; x; x = XEXP (x, 1))
3900 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3902 for (x = nonlocal_goto_handler_labels; x; x = XEXP (x, 1))
3904 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3906 for_each_eh_label (set_initial_eh_label_offset);
3909 /* Set all elimination offsets to the known values for the code label given
3913 set_offsets_for_label (rtx insn)
3916 int label_nr = CODE_LABEL_NUMBER (insn);
3917 struct elim_table *ep;
3919 num_not_at_initial_offset = 0;
3920 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3922 ep->offset = ep->previous_offset
3923 = offsets_at[label_nr - first_label_num][i];
3924 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3925 num_not_at_initial_offset++;
3929 /* See if anything that happened changes which eliminations are valid.
3930 For example, on the SPARC, whether or not the frame pointer can
3931 be eliminated can depend on what registers have been used. We need
3932 not check some conditions again (such as flag_omit_frame_pointer)
3933 since they can't have changed. */
3936 update_eliminables (HARD_REG_SET *pset)
3938 int previous_frame_pointer_needed = frame_pointer_needed;
3939 struct elim_table *ep;
3941 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3942 if ((ep->from == HARD_FRAME_POINTER_REGNUM
3943 && targetm.frame_pointer_required ())
3944 #ifdef ELIMINABLE_REGS
3945 || ! targetm.can_eliminate (ep->from, ep->to)
3948 ep->can_eliminate = 0;
3950 /* Look for the case where we have discovered that we can't replace
3951 register A with register B and that means that we will now be
3952 trying to replace register A with register C. This means we can
3953 no longer replace register C with register B and we need to disable
3954 such an elimination, if it exists. This occurs often with A == ap,
3955 B == sp, and C == fp. */
3957 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3959 struct elim_table *op;
3962 if (! ep->can_eliminate && ep->can_eliminate_previous)
3964 /* Find the current elimination for ep->from, if there is a
3966 for (op = reg_eliminate;
3967 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3968 if (op->from == ep->from && op->can_eliminate)
3974 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3976 for (op = reg_eliminate;
3977 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3978 if (op->from == new_to && op->to == ep->to)
3979 op->can_eliminate = 0;
3983 /* See if any registers that we thought we could eliminate the previous
3984 time are no longer eliminable. If so, something has changed and we
3985 must spill the register. Also, recompute the number of eliminable
3986 registers and see if the frame pointer is needed; it is if there is
3987 no elimination of the frame pointer that we can perform. */
3989 frame_pointer_needed = 1;
3990 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3992 if (ep->can_eliminate
3993 && ep->from == FRAME_POINTER_REGNUM
3994 && ep->to != HARD_FRAME_POINTER_REGNUM
3995 && (! SUPPORTS_STACK_ALIGNMENT
3996 || ! crtl->stack_realign_needed))
3997 frame_pointer_needed = 0;
3999 if (! ep->can_eliminate && ep->can_eliminate_previous)
4001 ep->can_eliminate_previous = 0;
4002 SET_HARD_REG_BIT (*pset, ep->from);
4007 /* If we didn't need a frame pointer last time, but we do now, spill
4008 the hard frame pointer. */
4009 if (frame_pointer_needed && ! previous_frame_pointer_needed)
4010 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
4013 /* Return true if X is used as the target register of an elimination. */
4016 elimination_target_reg_p (rtx x)
4018 struct elim_table *ep;
4020 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4021 if (ep->to_rtx == x && ep->can_eliminate)
4027 /* Initialize the table of registers to eliminate.
4028 Pre-condition: global flag frame_pointer_needed has been set before
4029 calling this function. */
4032 init_elim_table (void)
4034 struct elim_table *ep;
4035 #ifdef ELIMINABLE_REGS
4036 const struct elim_table_1 *ep1;
4040 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
4044 #ifdef ELIMINABLE_REGS
4045 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
4046 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
4048 ep->from = ep1->from;
4050 ep->can_eliminate = ep->can_eliminate_previous
4051 = (targetm.can_eliminate (ep->from, ep->to)
4052 && ! (ep->to == STACK_POINTER_REGNUM
4053 && frame_pointer_needed
4054 && (! SUPPORTS_STACK_ALIGNMENT
4055 || ! stack_realign_fp)));
4058 reg_eliminate[0].from = reg_eliminate_1[0].from;
4059 reg_eliminate[0].to = reg_eliminate_1[0].to;
4060 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
4061 = ! frame_pointer_needed;
4064 /* Count the number of eliminable registers and build the FROM and TO
4065 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
4066 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4067 We depend on this. */
4068 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4070 num_eliminable += ep->can_eliminate;
4071 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
4072 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
4076 /* Find all the pseudo registers that didn't get hard regs
4077 but do have known equivalent constants or memory slots.
4078 These include parameters (known equivalent to parameter slots)
4079 and cse'd or loop-moved constant memory addresses.
4081 Record constant equivalents in reg_equiv_constant
4082 so they will be substituted by find_reloads.
4083 Record memory equivalents in reg_mem_equiv so they can
4084 be substituted eventually by altering the REG-rtx's. */
4087 init_eliminable_invariants (rtx first, bool do_subregs)
4092 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
4093 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
4094 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
4095 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
4096 reg_equiv_address = XCNEWVEC (rtx, max_regno);
4098 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
4100 reg_max_ref_width = NULL;
4102 num_eliminable_invariants = 0;
4104 first_label_num = get_first_label_num ();
4105 num_labels = max_label_num () - first_label_num;
4107 /* Allocate the tables used to store offset information at labels. */
4108 offsets_known_at = XNEWVEC (char, num_labels);
4109 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
4111 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4112 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4113 find largest such for each pseudo. FIRST is the head of the insn
4116 for (insn = first; insn; insn = NEXT_INSN (insn))
4118 rtx set = single_set (insn);
4120 /* We may introduce USEs that we want to remove at the end, so
4121 we'll mark them with QImode. Make sure there are no
4122 previously-marked insns left by say regmove. */
4123 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
4124 && GET_MODE (insn) != VOIDmode)
4125 PUT_MODE (insn, VOIDmode);
4127 if (do_subregs && NONDEBUG_INSN_P (insn))
4128 scan_paradoxical_subregs (PATTERN (insn));
4130 if (set != 0 && REG_P (SET_DEST (set)))
4132 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
4138 i = REGNO (SET_DEST (set));
4141 if (i <= LAST_VIRTUAL_REGISTER)
4144 /* If flag_pic and we have constant, verify it's legitimate. */
4146 || !flag_pic || LEGITIMATE_PIC_OPERAND_P (x))
4148 /* It can happen that a REG_EQUIV note contains a MEM
4149 that is not a legitimate memory operand. As later
4150 stages of reload assume that all addresses found
4151 in the reg_equiv_* arrays were originally legitimate,
4152 we ignore such REG_EQUIV notes. */
4153 if (memory_operand (x, VOIDmode))
4155 /* Always unshare the equivalence, so we can
4156 substitute into this insn without touching the
4158 reg_equiv_memory_loc[i] = copy_rtx (x);
4160 else if (function_invariant_p (x))
4162 if (GET_CODE (x) == PLUS)
4164 /* This is PLUS of frame pointer and a constant,
4165 and might be shared. Unshare it. */
4166 reg_equiv_invariant[i] = copy_rtx (x);
4167 num_eliminable_invariants++;
4169 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4171 reg_equiv_invariant[i] = x;
4172 num_eliminable_invariants++;
4174 else if (LEGITIMATE_CONSTANT_P (x))
4175 reg_equiv_constant[i] = x;
4178 reg_equiv_memory_loc[i]
4179 = force_const_mem (GET_MODE (SET_DEST (set)), x);
4180 if (! reg_equiv_memory_loc[i])
4181 reg_equiv_init[i] = NULL_RTX;
4186 reg_equiv_init[i] = NULL_RTX;
4191 reg_equiv_init[i] = NULL_RTX;
4196 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4197 if (reg_equiv_init[i])
4199 fprintf (dump_file, "init_insns for %u: ", i);
4200 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
4201 fprintf (dump_file, "\n");
4205 /* Indicate that we no longer have known memory locations or constants.
4206 Free all data involved in tracking these. */
4209 free_reg_equiv (void)
4213 if (reg_equiv_constant)
4214 free (reg_equiv_constant);
4215 if (reg_equiv_invariant)
4216 free (reg_equiv_invariant);
4217 reg_equiv_constant = 0;
4218 reg_equiv_invariant = 0;
4219 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
4220 reg_equiv_memory_loc = 0;
4222 if (offsets_known_at)
4223 free (offsets_known_at);
4227 offsets_known_at = 0;
4229 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4230 if (reg_equiv_alt_mem_list[i])
4231 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
4232 free (reg_equiv_alt_mem_list);
4234 free (reg_equiv_mem);
4235 free (reg_equiv_address);
4238 /* Kick all pseudos out of hard register REGNO.
4240 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4241 because we found we can't eliminate some register. In the case, no pseudos
4242 are allowed to be in the register, even if they are only in a block that
4243 doesn't require spill registers, unlike the case when we are spilling this
4244 hard reg to produce another spill register.
4246 Return nonzero if any pseudos needed to be kicked out. */
4249 spill_hard_reg (unsigned int regno, int cant_eliminate)
4255 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
4256 df_set_regs_ever_live (regno, true);
4259 /* Spill every pseudo reg that was allocated to this reg
4260 or to something that overlaps this reg. */
4262 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4263 if (reg_renumber[i] >= 0
4264 && (unsigned int) reg_renumber[i] <= regno
4265 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
4266 SET_REGNO_REG_SET (&spilled_pseudos, i);
4269 /* After find_reload_regs has been run for all insn that need reloads,
4270 and/or spill_hard_regs was called, this function is used to actually
4271 spill pseudo registers and try to reallocate them. It also sets up the
4272 spill_regs array for use by choose_reload_regs. */
4275 finish_spills (int global)
4277 struct insn_chain *chain;
4278 int something_changed = 0;
4280 reg_set_iterator rsi;
4282 /* Build the spill_regs array for the function. */
4283 /* If there are some registers still to eliminate and one of the spill regs
4284 wasn't ever used before, additional stack space may have to be
4285 allocated to store this register. Thus, we may have changed the offset
4286 between the stack and frame pointers, so mark that something has changed.
4288 One might think that we need only set VAL to 1 if this is a call-used
4289 register. However, the set of registers that must be saved by the
4290 prologue is not identical to the call-used set. For example, the
4291 register used by the call insn for the return PC is a call-used register,
4292 but must be saved by the prologue. */
4295 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4296 if (TEST_HARD_REG_BIT (used_spill_regs, i))
4298 spill_reg_order[i] = n_spills;
4299 spill_regs[n_spills++] = i;
4300 if (num_eliminable && ! df_regs_ever_live_p (i))
4301 something_changed = 1;
4302 df_set_regs_ever_live (i, true);
4305 spill_reg_order[i] = -1;
4307 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
4308 if (! ira_conflicts_p || reg_renumber[i] >= 0)
4310 /* Record the current hard register the pseudo is allocated to
4311 in pseudo_previous_regs so we avoid reallocating it to the
4312 same hard reg in a later pass. */
4313 gcc_assert (reg_renumber[i] >= 0);
4315 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
4316 /* Mark it as no longer having a hard register home. */
4317 reg_renumber[i] = -1;
4318 if (ira_conflicts_p)
4319 /* Inform IRA about the change. */
4320 ira_mark_allocation_change (i);
4321 /* We will need to scan everything again. */
4322 something_changed = 1;
4325 /* Retry global register allocation if possible. */
4326 if (global && ira_conflicts_p)
4330 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
4331 /* For every insn that needs reloads, set the registers used as spill
4332 regs in pseudo_forbidden_regs for every pseudo live across the
4334 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
4336 EXECUTE_IF_SET_IN_REG_SET
4337 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
4339 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4340 chain->used_spill_regs);
4342 EXECUTE_IF_SET_IN_REG_SET
4343 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
4345 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4346 chain->used_spill_regs);
4350 /* Retry allocating the pseudos spilled in IRA and the
4351 reload. For each reg, merge the various reg sets that
4352 indicate which hard regs can't be used, and call
4353 ira_reassign_pseudos. */
4354 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4355 if (reg_old_renumber[i] != reg_renumber[i])
4357 if (reg_renumber[i] < 0)
4358 temp_pseudo_reg_arr[n++] = i;
4360 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4362 if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4363 bad_spill_regs_global,
4364 pseudo_forbidden_regs, pseudo_previous_regs,
4366 something_changed = 1;
4368 /* Fix up the register information in the insn chain.
4369 This involves deleting those of the spilled pseudos which did not get
4370 a new hard register home from the live_{before,after} sets. */
4371 for (chain = reload_insn_chain; chain; chain = chain->next)
4373 HARD_REG_SET used_by_pseudos;
4374 HARD_REG_SET used_by_pseudos2;
4376 if (! ira_conflicts_p)
4378 /* Don't do it for IRA because IRA and the reload still can
4379 assign hard registers to the spilled pseudos on next
4380 reload iterations. */
4381 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4382 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4384 /* Mark any unallocated hard regs as available for spills. That
4385 makes inheritance work somewhat better. */
4386 if (chain->need_reload)
4388 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4389 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4390 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4392 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4393 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4394 /* Value of chain->used_spill_regs from previous iteration
4395 may be not included in the value calculated here because
4396 of possible removing caller-saves insns (see function
4397 delete_caller_save_insns. */
4398 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4399 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4403 CLEAR_REG_SET (&changed_allocation_pseudos);
4404 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4405 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4407 int regno = reg_renumber[i];
4408 if (reg_old_renumber[i] == regno)
4411 SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4413 alter_reg (i, reg_old_renumber[i], false);
4414 reg_old_renumber[i] = regno;
4418 fprintf (dump_file, " Register %d now on stack.\n\n", i);
4420 fprintf (dump_file, " Register %d now in %d.\n\n",
4421 i, reg_renumber[i]);
4425 return something_changed;
4428 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4431 scan_paradoxical_subregs (rtx x)
4435 enum rtx_code code = GET_CODE (x);
4446 case CONST_VECTOR: /* shouldn't happen, but just in case. */
4454 if (REG_P (SUBREG_REG (x))
4455 && (GET_MODE_SIZE (GET_MODE (x))
4456 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
4458 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4459 = GET_MODE_SIZE (GET_MODE (x));
4460 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
4468 fmt = GET_RTX_FORMAT (code);
4469 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4472 scan_paradoxical_subregs (XEXP (x, i));
4473 else if (fmt[i] == 'E')
4476 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4477 scan_paradoxical_subregs (XVECEXP (x, i, j));
4482 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4483 examine all of the reload insns between PREV and NEXT exclusive, and
4484 annotate all that may trap. */
4487 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
4489 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4492 if (!insn_could_throw_p (insn))
4493 remove_note (insn, note);
4494 copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next);
4497 /* Reload pseudo-registers into hard regs around each insn as needed.
4498 Additional register load insns are output before the insn that needs it
4499 and perhaps store insns after insns that modify the reloaded pseudo reg.
4501 reg_last_reload_reg and reg_reloaded_contents keep track of
4502 which registers are already available in reload registers.
4503 We update these for the reloads that we perform,
4504 as the insns are scanned. */
4507 reload_as_needed (int live_known)
4509 struct insn_chain *chain;
4510 #if defined (AUTO_INC_DEC)
4515 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4516 memset (spill_reg_store, 0, sizeof spill_reg_store);
4517 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4518 INIT_REG_SET (®_has_output_reload);
4519 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4520 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4522 set_initial_elim_offsets ();
4524 for (chain = reload_insn_chain; chain; chain = chain->next)
4527 rtx insn = chain->insn;
4528 rtx old_next = NEXT_INSN (insn);
4530 rtx old_prev = PREV_INSN (insn);
4533 /* If we pass a label, copy the offsets from the label information
4534 into the current offsets of each elimination. */
4536 set_offsets_for_label (insn);
4538 else if (INSN_P (insn))
4540 regset_head regs_to_forget;
4541 INIT_REG_SET (®s_to_forget);
4542 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4544 /* If this is a USE and CLOBBER of a MEM, ensure that any
4545 references to eliminable registers have been removed. */
4547 if ((GET_CODE (PATTERN (insn)) == USE
4548 || GET_CODE (PATTERN (insn)) == CLOBBER)
4549 && MEM_P (XEXP (PATTERN (insn), 0)))
4550 XEXP (XEXP (PATTERN (insn), 0), 0)
4551 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4552 GET_MODE (XEXP (PATTERN (insn), 0)),
4555 /* If we need to do register elimination processing, do so.
4556 This might delete the insn, in which case we are done. */
4557 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4559 eliminate_regs_in_insn (insn, 1);
4562 update_eliminable_offsets ();
4563 CLEAR_REG_SET (®s_to_forget);
4568 /* If need_elim is nonzero but need_reload is zero, one might think
4569 that we could simply set n_reloads to 0. However, find_reloads
4570 could have done some manipulation of the insn (such as swapping
4571 commutative operands), and these manipulations are lost during
4572 the first pass for every insn that needs register elimination.
4573 So the actions of find_reloads must be redone here. */
4575 if (! chain->need_elim && ! chain->need_reload
4576 && ! chain->need_operand_change)
4578 /* First find the pseudo regs that must be reloaded for this insn.
4579 This info is returned in the tables reload_... (see reload.h).
4580 Also modify the body of INSN by substituting RELOAD
4581 rtx's for those pseudo regs. */
4584 CLEAR_REG_SET (®_has_output_reload);
4585 CLEAR_HARD_REG_SET (reg_is_output_reload);
4587 find_reloads (insn, 1, spill_indirect_levels, live_known,
4593 rtx next = NEXT_INSN (insn);
4596 prev = PREV_INSN (insn);
4598 /* Now compute which reload regs to reload them into. Perhaps
4599 reusing reload regs from previous insns, or else output
4600 load insns to reload them. Maybe output store insns too.
4601 Record the choices of reload reg in reload_reg_rtx. */
4602 choose_reload_regs (chain);
4604 /* Generate the insns to reload operands into or out of
4605 their reload regs. */
4606 emit_reload_insns (chain);
4608 /* Substitute the chosen reload regs from reload_reg_rtx
4609 into the insn's body (or perhaps into the bodies of other
4610 load and store insn that we just made for reloading
4611 and that we moved the structure into). */
4612 subst_reloads (insn);
4614 /* Adjust the exception region notes for loads and stores. */
4615 if (cfun->can_throw_non_call_exceptions && !CALL_P (insn))
4616 fixup_eh_region_note (insn, prev, next);
4618 /* If this was an ASM, make sure that all the reload insns
4619 we have generated are valid. If not, give an error
4621 if (asm_noperands (PATTERN (insn)) >= 0)
4622 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4623 if (p != insn && INSN_P (p)
4624 && GET_CODE (PATTERN (p)) != USE
4625 && (recog_memoized (p) < 0
4626 || (extract_insn (p), ! constrain_operands (1))))
4628 error_for_asm (insn,
4629 "%<asm%> operand requires "
4630 "impossible reload");
4635 if (num_eliminable && chain->need_elim)
4636 update_eliminable_offsets ();
4638 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4639 is no longer validly lying around to save a future reload.
4640 Note that this does not detect pseudos that were reloaded
4641 for this insn in order to be stored in
4642 (obeying register constraints). That is correct; such reload
4643 registers ARE still valid. */
4644 forget_marked_reloads (®s_to_forget);
4645 CLEAR_REG_SET (®s_to_forget);
4647 /* There may have been CLOBBER insns placed after INSN. So scan
4648 between INSN and NEXT and use them to forget old reloads. */
4649 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4650 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4651 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4654 /* Likewise for regs altered by auto-increment in this insn.
4655 REG_INC notes have been changed by reloading:
4656 find_reloads_address_1 records substitutions for them,
4657 which have been performed by subst_reloads above. */
4658 for (i = n_reloads - 1; i >= 0; i--)
4660 rtx in_reg = rld[i].in_reg;
4663 enum rtx_code code = GET_CODE (in_reg);
4664 /* PRE_INC / PRE_DEC will have the reload register ending up
4665 with the same value as the stack slot, but that doesn't
4666 hold true for POST_INC / POST_DEC. Either we have to
4667 convert the memory access to a true POST_INC / POST_DEC,
4668 or we can't use the reload register for inheritance. */
4669 if ((code == POST_INC || code == POST_DEC)
4670 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4671 REGNO (rld[i].reg_rtx))
4672 /* Make sure it is the inc/dec pseudo, and not
4673 some other (e.g. output operand) pseudo. */
4674 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4675 == REGNO (XEXP (in_reg, 0))))
4678 rtx reload_reg = rld[i].reg_rtx;
4679 enum machine_mode mode = GET_MODE (reload_reg);
4683 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4685 /* We really want to ignore REG_INC notes here, so
4686 use PATTERN (p) as argument to reg_set_p . */
4687 if (reg_set_p (reload_reg, PATTERN (p)))
4689 n = count_occurrences (PATTERN (p), reload_reg, 0);
4695 = gen_rtx_fmt_e (code, mode, reload_reg);
4697 validate_replace_rtx_group (reload_reg,
4699 n = verify_changes (0);
4701 /* We must also verify that the constraints
4702 are met after the replacement. Make sure
4703 extract_insn is only called for an insn
4704 where the replacements were found to be
4709 n = constrain_operands (1);
4712 /* If the constraints were not met, then
4713 undo the replacement, else confirm it. */
4717 confirm_change_group ();
4723 add_reg_note (p, REG_INC, reload_reg);
4724 /* Mark this as having an output reload so that the
4725 REG_INC processing code below won't invalidate
4726 the reload for inheritance. */
4727 SET_HARD_REG_BIT (reg_is_output_reload,
4728 REGNO (reload_reg));
4729 SET_REGNO_REG_SET (®_has_output_reload,
4730 REGNO (XEXP (in_reg, 0)));
4733 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4736 else if ((code == PRE_INC || code == PRE_DEC)
4737 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4738 REGNO (rld[i].reg_rtx))
4739 /* Make sure it is the inc/dec pseudo, and not
4740 some other (e.g. output operand) pseudo. */
4741 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4742 == REGNO (XEXP (in_reg, 0))))
4744 SET_HARD_REG_BIT (reg_is_output_reload,
4745 REGNO (rld[i].reg_rtx));
4746 SET_REGNO_REG_SET (®_has_output_reload,
4747 REGNO (XEXP (in_reg, 0)));
4749 else if (code == PRE_INC || code == PRE_DEC
4750 || code == POST_INC || code == POST_DEC)
4752 int in_regno = REGNO (XEXP (in_reg, 0));
4754 if (reg_last_reload_reg[in_regno] != NULL_RTX)
4757 bool forget_p = true;
4759 in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4760 if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4763 for (x = old_prev ? NEXT_INSN (old_prev) : insn;
4766 if (x == reg_reloaded_insn[in_hard_regno])
4772 /* If for some reasons, we didn't set up
4773 reg_last_reload_reg in this insn,
4774 invalidate inheritance from previous
4775 insns for the incremented/decremented
4776 register. Such registers will be not in
4777 reg_has_output_reload. Invalidate it
4778 also if the corresponding element in
4779 reg_reloaded_insn is also
4782 forget_old_reloads_1 (XEXP (in_reg, 0),
4788 /* If a pseudo that got a hard register is auto-incremented,
4789 we must purge records of copying it into pseudos without
4791 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4792 if (REG_NOTE_KIND (x) == REG_INC)
4794 /* See if this pseudo reg was reloaded in this insn.
4795 If so, its last-reload info is still valid
4796 because it is based on this insn's reload. */
4797 for (i = 0; i < n_reloads; i++)
4798 if (rld[i].out == XEXP (x, 0))
4802 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4806 /* A reload reg's contents are unknown after a label. */
4808 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4810 /* Don't assume a reload reg is still good after a call insn
4811 if it is a call-used reg, or if it contains a value that will
4812 be partially clobbered by the call. */
4813 else if (CALL_P (insn))
4815 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4816 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4818 /* If this is a call to a setjmp-type function, we must not
4819 reuse any reload reg contents across the call; that will
4820 just be clobbered by other uses of the register in later
4821 code, before the longjmp. */
4822 if (find_reg_note (insn, REG_SETJMP, NULL_RTX))
4823 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4828 free (reg_last_reload_reg);
4829 CLEAR_REG_SET (®_has_output_reload);
4832 /* Discard all record of any value reloaded from X,
4833 or reloaded in X from someplace else;
4834 unless X is an output reload reg of the current insn.
4836 X may be a hard reg (the reload reg)
4837 or it may be a pseudo reg that was reloaded from.
4839 When DATA is non-NULL just mark the registers in regset
4840 to be forgotten later. */
4843 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4848 regset regs = (regset) data;
4850 /* note_stores does give us subregs of hard regs,
4851 subreg_regno_offset requires a hard reg. */
4852 while (GET_CODE (x) == SUBREG)
4854 /* We ignore the subreg offset when calculating the regno,
4855 because we are using the entire underlying hard register
4865 if (regno >= FIRST_PSEUDO_REGISTER)
4871 nr = hard_regno_nregs[regno][GET_MODE (x)];
4872 /* Storing into a spilled-reg invalidates its contents.
4873 This can happen if a block-local pseudo is allocated to that reg
4874 and it wasn't spilled because this block's total need is 0.
4875 Then some insn might have an optional reload and use this reg. */
4877 for (i = 0; i < nr; i++)
4878 /* But don't do this if the reg actually serves as an output
4879 reload reg in the current instruction. */
4881 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4883 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4884 spill_reg_store[regno + i] = 0;
4890 SET_REGNO_REG_SET (regs, regno + nr);
4893 /* Since value of X has changed,
4894 forget any value previously copied from it. */
4897 /* But don't forget a copy if this is the output reload
4898 that establishes the copy's validity. */
4900 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4901 reg_last_reload_reg[regno + nr] = 0;
4905 /* Forget the reloads marked in regset by previous function. */
4907 forget_marked_reloads (regset regs)
4910 reg_set_iterator rsi;
4911 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4913 if (reg < FIRST_PSEUDO_REGISTER
4914 /* But don't do this if the reg actually serves as an output
4915 reload reg in the current instruction. */
4917 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4919 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4920 spill_reg_store[reg] = 0;
4923 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4924 reg_last_reload_reg[reg] = 0;
4928 /* The following HARD_REG_SETs indicate when each hard register is
4929 used for a reload of various parts of the current insn. */
4931 /* If reg is unavailable for all reloads. */
4932 static HARD_REG_SET reload_reg_unavailable;
4933 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4934 static HARD_REG_SET reload_reg_used;
4935 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4936 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4937 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4938 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4939 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4940 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4941 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4942 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4943 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4944 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4945 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4946 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4947 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4948 static HARD_REG_SET reload_reg_used_in_op_addr;
4949 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4950 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4951 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4952 static HARD_REG_SET reload_reg_used_in_insn;
4953 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4954 static HARD_REG_SET reload_reg_used_in_other_addr;
4956 /* If reg is in use as a reload reg for any sort of reload. */
4957 static HARD_REG_SET reload_reg_used_at_all;
4959 /* If reg is use as an inherited reload. We just mark the first register
4961 static HARD_REG_SET reload_reg_used_for_inherit;
4963 /* Records which hard regs are used in any way, either as explicit use or
4964 by being allocated to a pseudo during any point of the current insn. */
4965 static HARD_REG_SET reg_used_in_insn;
4967 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4968 TYPE. MODE is used to indicate how many consecutive regs are
4972 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4973 enum machine_mode mode)
4975 unsigned int nregs = hard_regno_nregs[regno][mode];
4978 for (i = regno; i < nregs + regno; i++)
4983 SET_HARD_REG_BIT (reload_reg_used, i);
4986 case RELOAD_FOR_INPUT_ADDRESS:
4987 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4990 case RELOAD_FOR_INPADDR_ADDRESS:
4991 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4994 case RELOAD_FOR_OUTPUT_ADDRESS:
4995 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4998 case RELOAD_FOR_OUTADDR_ADDRESS:
4999 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
5002 case RELOAD_FOR_OPERAND_ADDRESS:
5003 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
5006 case RELOAD_FOR_OPADDR_ADDR:
5007 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
5010 case RELOAD_FOR_OTHER_ADDRESS:
5011 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
5014 case RELOAD_FOR_INPUT:
5015 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
5018 case RELOAD_FOR_OUTPUT:
5019 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
5022 case RELOAD_FOR_INSN:
5023 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
5027 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
5031 /* Similarly, but show REGNO is no longer in use for a reload. */
5034 clear_reload_reg_in_use (unsigned int regno, int opnum,
5035 enum reload_type type, enum machine_mode mode)
5037 unsigned int nregs = hard_regno_nregs[regno][mode];
5038 unsigned int start_regno, end_regno, r;
5040 /* A complication is that for some reload types, inheritance might
5041 allow multiple reloads of the same types to share a reload register.
5042 We set check_opnum if we have to check only reloads with the same
5043 operand number, and check_any if we have to check all reloads. */
5044 int check_opnum = 0;
5046 HARD_REG_SET *used_in_set;
5051 used_in_set = &reload_reg_used;
5054 case RELOAD_FOR_INPUT_ADDRESS:
5055 used_in_set = &reload_reg_used_in_input_addr[opnum];
5058 case RELOAD_FOR_INPADDR_ADDRESS:
5060 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
5063 case RELOAD_FOR_OUTPUT_ADDRESS:
5064 used_in_set = &reload_reg_used_in_output_addr[opnum];
5067 case RELOAD_FOR_OUTADDR_ADDRESS:
5069 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
5072 case RELOAD_FOR_OPERAND_ADDRESS:
5073 used_in_set = &reload_reg_used_in_op_addr;
5076 case RELOAD_FOR_OPADDR_ADDR:
5078 used_in_set = &reload_reg_used_in_op_addr_reload;
5081 case RELOAD_FOR_OTHER_ADDRESS:
5082 used_in_set = &reload_reg_used_in_other_addr;
5086 case RELOAD_FOR_INPUT:
5087 used_in_set = &reload_reg_used_in_input[opnum];
5090 case RELOAD_FOR_OUTPUT:
5091 used_in_set = &reload_reg_used_in_output[opnum];
5094 case RELOAD_FOR_INSN:
5095 used_in_set = &reload_reg_used_in_insn;
5100 /* We resolve conflicts with remaining reloads of the same type by
5101 excluding the intervals of reload registers by them from the
5102 interval of freed reload registers. Since we only keep track of
5103 one set of interval bounds, we might have to exclude somewhat
5104 more than what would be necessary if we used a HARD_REG_SET here.
5105 But this should only happen very infrequently, so there should
5106 be no reason to worry about it. */
5108 start_regno = regno;
5109 end_regno = regno + nregs;
5110 if (check_opnum || check_any)
5112 for (i = n_reloads - 1; i >= 0; i--)
5114 if (rld[i].when_needed == type
5115 && (check_any || rld[i].opnum == opnum)
5118 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
5119 unsigned int conflict_end
5120 = end_hard_regno (rld[i].mode, conflict_start);
5122 /* If there is an overlap with the first to-be-freed register,
5123 adjust the interval start. */
5124 if (conflict_start <= start_regno && conflict_end > start_regno)
5125 start_regno = conflict_end;
5126 /* Otherwise, if there is a conflict with one of the other
5127 to-be-freed registers, adjust the interval end. */
5128 if (conflict_start > start_regno && conflict_start < end_regno)
5129 end_regno = conflict_start;
5134 for (r = start_regno; r < end_regno; r++)
5135 CLEAR_HARD_REG_BIT (*used_in_set, r);
5138 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5139 specified by OPNUM and TYPE. */
5142 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
5146 /* In use for a RELOAD_OTHER means it's not available for anything. */
5147 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
5148 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5154 /* In use for anything means we can't use it for RELOAD_OTHER. */
5155 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
5156 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5157 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5158 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5161 for (i = 0; i < reload_n_operands; i++)
5162 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5163 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5164 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5165 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5166 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5167 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5172 case RELOAD_FOR_INPUT:
5173 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5174 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
5177 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5180 /* If it is used for some other input, can't use it. */
5181 for (i = 0; i < reload_n_operands; i++)
5182 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5185 /* If it is used in a later operand's address, can't use it. */
5186 for (i = opnum + 1; i < reload_n_operands; i++)
5187 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5188 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5193 case RELOAD_FOR_INPUT_ADDRESS:
5194 /* Can't use a register if it is used for an input address for this
5195 operand or used as an input in an earlier one. */
5196 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
5197 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5200 for (i = 0; i < opnum; i++)
5201 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5206 case RELOAD_FOR_INPADDR_ADDRESS:
5207 /* Can't use a register if it is used for an input address
5208 for this operand or used as an input in an earlier
5210 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5213 for (i = 0; i < opnum; i++)
5214 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5219 case RELOAD_FOR_OUTPUT_ADDRESS:
5220 /* Can't use a register if it is used for an output address for this
5221 operand or used as an output in this or a later operand. Note
5222 that multiple output operands are emitted in reverse order, so
5223 the conflicting ones are those with lower indices. */
5224 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
5227 for (i = 0; i <= opnum; i++)
5228 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5233 case RELOAD_FOR_OUTADDR_ADDRESS:
5234 /* Can't use a register if it is used for an output address
5235 for this operand or used as an output in this or a
5236 later operand. Note that multiple output operands are
5237 emitted in reverse order, so the conflicting ones are
5238 those with lower indices. */
5239 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5242 for (i = 0; i <= opnum; i++)
5243 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5248 case RELOAD_FOR_OPERAND_ADDRESS:
5249 for (i = 0; i < reload_n_operands; i++)
5250 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5253 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5254 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5256 case RELOAD_FOR_OPADDR_ADDR:
5257 for (i = 0; i < reload_n_operands; i++)
5258 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5261 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
5263 case RELOAD_FOR_OUTPUT:
5264 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5265 outputs, or an operand address for this or an earlier output.
5266 Note that multiple output operands are emitted in reverse order,
5267 so the conflicting ones are those with higher indices. */
5268 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5271 for (i = 0; i < reload_n_operands; i++)
5272 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5275 for (i = opnum; i < reload_n_operands; i++)
5276 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5277 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5282 case RELOAD_FOR_INSN:
5283 for (i = 0; i < reload_n_operands; i++)
5284 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5285 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5288 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5289 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5291 case RELOAD_FOR_OTHER_ADDRESS:
5292 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
5299 /* Return 1 if the value in reload reg REGNO, as used by a reload
5300 needed for the part of the insn specified by OPNUM and TYPE,
5301 is still available in REGNO at the end of the insn.
5303 We can assume that the reload reg was already tested for availability
5304 at the time it is needed, and we should not check this again,
5305 in case the reg has already been marked in use. */
5308 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
5315 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5316 its value must reach the end. */
5319 /* If this use is for part of the insn,
5320 its value reaches if no subsequent part uses the same register.
5321 Just like the above function, don't try to do this with lots
5324 case RELOAD_FOR_OTHER_ADDRESS:
5325 /* Here we check for everything else, since these don't conflict
5326 with anything else and everything comes later. */
5328 for (i = 0; i < reload_n_operands; i++)
5329 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5330 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5331 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
5332 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5333 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5334 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5337 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5338 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5339 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5340 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5342 case RELOAD_FOR_INPUT_ADDRESS:
5343 case RELOAD_FOR_INPADDR_ADDRESS:
5344 /* Similar, except that we check only for this and subsequent inputs
5345 and the address of only subsequent inputs and we do not need
5346 to check for RELOAD_OTHER objects since they are known not to
5349 for (i = opnum; i < reload_n_operands; i++)
5350 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5353 for (i = opnum + 1; i < reload_n_operands; i++)
5354 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5355 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5358 for (i = 0; i < reload_n_operands; i++)
5359 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5360 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5361 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5364 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5367 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5368 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5369 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5371 case RELOAD_FOR_INPUT:
5372 /* Similar to input address, except we start at the next operand for
5373 both input and input address and we do not check for
5374 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5377 for (i = opnum + 1; i < reload_n_operands; i++)
5378 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5379 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5380 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5383 /* ... fall through ... */
5385 case RELOAD_FOR_OPERAND_ADDRESS:
5386 /* Check outputs and their addresses. */
5388 for (i = 0; i < reload_n_operands; i++)
5389 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5390 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5391 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5394 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5396 case RELOAD_FOR_OPADDR_ADDR:
5397 for (i = 0; i < reload_n_operands; i++)
5398 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5399 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5400 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5403 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5404 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5405 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5407 case RELOAD_FOR_INSN:
5408 /* These conflict with other outputs with RELOAD_OTHER. So
5409 we need only check for output addresses. */
5411 opnum = reload_n_operands;
5413 /* ... fall through ... */
5415 case RELOAD_FOR_OUTPUT:
5416 case RELOAD_FOR_OUTPUT_ADDRESS:
5417 case RELOAD_FOR_OUTADDR_ADDRESS:
5418 /* We already know these can't conflict with a later output. So the
5419 only thing to check are later output addresses.
5420 Note that multiple output operands are emitted in reverse order,
5421 so the conflicting ones are those with lower indices. */
5422 for (i = 0; i < opnum; i++)
5423 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5424 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5434 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5435 every register in the range [REGNO, REGNO + NREGS). */
5438 reload_regs_reach_end_p (unsigned int regno, int nregs,
5439 int opnum, enum reload_type type)
5443 for (i = 0; i < nregs; i++)
5444 if (!reload_reg_reaches_end_p (regno + i, opnum, type))
5450 /* Returns whether R1 and R2 are uniquely chained: the value of one
5451 is used by the other, and that value is not used by any other
5452 reload for this insn. This is used to partially undo the decision
5453 made in find_reloads when in the case of multiple
5454 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5455 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5456 reloads. This code tries to avoid the conflict created by that
5457 change. It might be cleaner to explicitly keep track of which
5458 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5459 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5460 this after the fact. */
5462 reloads_unique_chain_p (int r1, int r2)
5466 /* We only check input reloads. */
5467 if (! rld[r1].in || ! rld[r2].in)
5470 /* Avoid anything with output reloads. */
5471 if (rld[r1].out || rld[r2].out)
5474 /* "chained" means one reload is a component of the other reload,
5475 not the same as the other reload. */
5476 if (rld[r1].opnum != rld[r2].opnum
5477 || rtx_equal_p (rld[r1].in, rld[r2].in)
5478 || rld[r1].optional || rld[r2].optional
5479 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5480 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5483 for (i = 0; i < n_reloads; i ++)
5484 /* Look for input reloads that aren't our two */
5485 if (i != r1 && i != r2 && rld[i].in)
5487 /* If our reload is mentioned at all, it isn't a simple chain. */
5488 if (reg_mentioned_p (rld[r1].in, rld[i].in))
5494 /* The recursive function change all occurrences of WHAT in *WHERE
5497 substitute (rtx *where, const_rtx what, rtx repl)
5506 if (*where == what || rtx_equal_p (*where, what))
5508 /* Record the location of the changed rtx. */
5509 VEC_safe_push (rtx_p, heap, substitute_stack, where);
5514 code = GET_CODE (*where);
5515 fmt = GET_RTX_FORMAT (code);
5516 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5522 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5523 substitute (&XVECEXP (*where, i, j), what, repl);
5525 else if (fmt[i] == 'e')
5526 substitute (&XEXP (*where, i), what, repl);
5530 /* The function returns TRUE if chain of reload R1 and R2 (in any
5531 order) can be evaluated without usage of intermediate register for
5532 the reload containing another reload. It is important to see
5533 gen_reload to understand what the function is trying to do. As an
5534 example, let us have reload chain
5537 r1: <something> + const
5539 and reload R2 got reload reg HR. The function returns true if
5540 there is a correct insn HR = HR + <something>. Otherwise,
5541 gen_reload will use intermediate register (and this is the reload
5542 reg for R1) to reload <something>.
5544 We need this function to find a conflict for chain reloads. In our
5545 example, if HR = HR + <something> is incorrect insn, then we cannot
5546 use HR as a reload register for R2. If we do use it then we get a
5555 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5557 /* Assume other cases in gen_reload are not possible for
5558 chain reloads or do need an intermediate hard registers. */
5561 rtx out, in, tem, insn;
5562 rtx last = get_last_insn ();
5564 /* Make r2 a component of r1. */
5565 if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5571 gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5572 regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5573 gcc_assert (regno >= 0);
5574 out = gen_rtx_REG (rld[r1].mode, regno);
5576 substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5578 /* If IN is a paradoxical SUBREG, remove it and try to put the
5579 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5580 if (GET_CODE (in) == SUBREG
5581 && (GET_MODE_SIZE (GET_MODE (in))
5582 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
5583 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
5584 in = SUBREG_REG (in), out = tem;
5586 if (GET_CODE (in) == PLUS
5587 && (REG_P (XEXP (in, 0))
5588 || GET_CODE (XEXP (in, 0)) == SUBREG
5589 || MEM_P (XEXP (in, 0)))
5590 && (REG_P (XEXP (in, 1))
5591 || GET_CODE (XEXP (in, 1)) == SUBREG
5592 || CONSTANT_P (XEXP (in, 1))
5593 || MEM_P (XEXP (in, 1))))
5595 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
5596 code = recog_memoized (insn);
5601 extract_insn (insn);
5602 /* We want constrain operands to treat this insn strictly in
5603 its validity determination, i.e., the way it would after
5604 reload has completed. */
5605 result = constrain_operands (1);
5608 delete_insns_since (last);
5611 /* Restore the original value at each changed address within R1. */
5612 while (!VEC_empty (rtx_p, substitute_stack))
5614 rtx *where = VEC_pop (rtx_p, substitute_stack);
5615 *where = rld[r2].in;
5621 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5624 This function uses the same algorithm as reload_reg_free_p above. */
5627 reloads_conflict (int r1, int r2)
5629 enum reload_type r1_type = rld[r1].when_needed;
5630 enum reload_type r2_type = rld[r2].when_needed;
5631 int r1_opnum = rld[r1].opnum;
5632 int r2_opnum = rld[r2].opnum;
5634 /* RELOAD_OTHER conflicts with everything. */
5635 if (r2_type == RELOAD_OTHER)
5638 /* Otherwise, check conflicts differently for each type. */
5642 case RELOAD_FOR_INPUT:
5643 return (r2_type == RELOAD_FOR_INSN
5644 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5645 || r2_type == RELOAD_FOR_OPADDR_ADDR
5646 || r2_type == RELOAD_FOR_INPUT
5647 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5648 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5649 && r2_opnum > r1_opnum));
5651 case RELOAD_FOR_INPUT_ADDRESS:
5652 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5653 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5655 case RELOAD_FOR_INPADDR_ADDRESS:
5656 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5657 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5659 case RELOAD_FOR_OUTPUT_ADDRESS:
5660 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5661 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5663 case RELOAD_FOR_OUTADDR_ADDRESS:
5664 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5665 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5667 case RELOAD_FOR_OPERAND_ADDRESS:
5668 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5669 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5670 && (!reloads_unique_chain_p (r1, r2)
5671 || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5673 case RELOAD_FOR_OPADDR_ADDR:
5674 return (r2_type == RELOAD_FOR_INPUT
5675 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5677 case RELOAD_FOR_OUTPUT:
5678 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5679 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5680 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5681 && r2_opnum >= r1_opnum));
5683 case RELOAD_FOR_INSN:
5684 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5685 || r2_type == RELOAD_FOR_INSN
5686 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5688 case RELOAD_FOR_OTHER_ADDRESS:
5689 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5699 /* Indexed by reload number, 1 if incoming value
5700 inherited from previous insns. */
5701 static char reload_inherited[MAX_RELOADS];
5703 /* For an inherited reload, this is the insn the reload was inherited from,
5704 if we know it. Otherwise, this is 0. */
5705 static rtx reload_inheritance_insn[MAX_RELOADS];
5707 /* If nonzero, this is a place to get the value of the reload,
5708 rather than using reload_in. */
5709 static rtx reload_override_in[MAX_RELOADS];
5711 /* For each reload, the hard register number of the register used,
5712 or -1 if we did not need a register for this reload. */
5713 static int reload_spill_index[MAX_RELOADS];
5715 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5716 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5718 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5719 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5721 /* Subroutine of free_for_value_p, used to check a single register.
5722 START_REGNO is the starting regno of the full reload register
5723 (possibly comprising multiple hard registers) that we are considering. */
5726 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5727 enum reload_type type, rtx value, rtx out,
5728 int reloadnum, int ignore_address_reloads)
5731 /* Set if we see an input reload that must not share its reload register
5732 with any new earlyclobber, but might otherwise share the reload
5733 register with an output or input-output reload. */
5734 int check_earlyclobber = 0;
5738 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5741 if (out == const0_rtx)
5747 /* We use some pseudo 'time' value to check if the lifetimes of the
5748 new register use would overlap with the one of a previous reload
5749 that is not read-only or uses a different value.
5750 The 'time' used doesn't have to be linear in any shape or form, just
5752 Some reload types use different 'buckets' for each operand.
5753 So there are MAX_RECOG_OPERANDS different time values for each
5755 We compute TIME1 as the time when the register for the prospective
5756 new reload ceases to be live, and TIME2 for each existing
5757 reload as the time when that the reload register of that reload
5759 Where there is little to be gained by exact lifetime calculations,
5760 we just make conservative assumptions, i.e. a longer lifetime;
5761 this is done in the 'default:' cases. */
5764 case RELOAD_FOR_OTHER_ADDRESS:
5765 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5766 time1 = copy ? 0 : 1;
5769 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5771 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5772 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5773 respectively, to the time values for these, we get distinct time
5774 values. To get distinct time values for each operand, we have to
5775 multiply opnum by at least three. We round that up to four because
5776 multiply by four is often cheaper. */
5777 case RELOAD_FOR_INPADDR_ADDRESS:
5778 time1 = opnum * 4 + 2;
5780 case RELOAD_FOR_INPUT_ADDRESS:
5781 time1 = opnum * 4 + 3;
5783 case RELOAD_FOR_INPUT:
5784 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5785 executes (inclusive). */
5786 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5788 case RELOAD_FOR_OPADDR_ADDR:
5790 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5791 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5793 case RELOAD_FOR_OPERAND_ADDRESS:
5794 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5796 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5798 case RELOAD_FOR_OUTADDR_ADDRESS:
5799 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5801 case RELOAD_FOR_OUTPUT_ADDRESS:
5802 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5805 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5808 for (i = 0; i < n_reloads; i++)
5810 rtx reg = rld[i].reg_rtx;
5811 if (reg && REG_P (reg)
5812 && ((unsigned) regno - true_regnum (reg)
5813 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5816 rtx other_input = rld[i].in;
5818 /* If the other reload loads the same input value, that
5819 will not cause a conflict only if it's loading it into
5820 the same register. */
5821 if (true_regnum (reg) != start_regno)
5822 other_input = NULL_RTX;
5823 if (! other_input || ! rtx_equal_p (other_input, value)
5824 || rld[i].out || out)
5827 switch (rld[i].when_needed)
5829 case RELOAD_FOR_OTHER_ADDRESS:
5832 case RELOAD_FOR_INPADDR_ADDRESS:
5833 /* find_reloads makes sure that a
5834 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5835 by at most one - the first -
5836 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5837 address reload is inherited, the address address reload
5838 goes away, so we can ignore this conflict. */
5839 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5840 && ignore_address_reloads
5841 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5842 Then the address address is still needed to store
5843 back the new address. */
5844 && ! rld[reloadnum].out)
5846 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5847 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5849 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5850 && ignore_address_reloads
5851 /* Unless we are reloading an auto_inc expression. */
5852 && ! rld[reloadnum].out)
5854 time2 = rld[i].opnum * 4 + 2;
5856 case RELOAD_FOR_INPUT_ADDRESS:
5857 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5858 && ignore_address_reloads
5859 && ! rld[reloadnum].out)
5861 time2 = rld[i].opnum * 4 + 3;
5863 case RELOAD_FOR_INPUT:
5864 time2 = rld[i].opnum * 4 + 4;
5865 check_earlyclobber = 1;
5867 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5868 == MAX_RECOG_OPERAND * 4 */
5869 case RELOAD_FOR_OPADDR_ADDR:
5870 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5871 && ignore_address_reloads
5872 && ! rld[reloadnum].out)
5874 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5876 case RELOAD_FOR_OPERAND_ADDRESS:
5877 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5878 check_earlyclobber = 1;
5880 case RELOAD_FOR_INSN:
5881 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5883 case RELOAD_FOR_OUTPUT:
5884 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5885 instruction is executed. */
5886 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5888 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5889 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5891 case RELOAD_FOR_OUTADDR_ADDRESS:
5892 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5893 && ignore_address_reloads
5894 && ! rld[reloadnum].out)
5896 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5898 case RELOAD_FOR_OUTPUT_ADDRESS:
5899 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5902 /* If there is no conflict in the input part, handle this
5903 like an output reload. */
5904 if (! rld[i].in || rtx_equal_p (other_input, value))
5906 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5907 /* Earlyclobbered outputs must conflict with inputs. */
5908 if (earlyclobber_operand_p (rld[i].out))
5909 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5914 /* RELOAD_OTHER might be live beyond instruction execution,
5915 but this is not obvious when we set time2 = 1. So check
5916 here if there might be a problem with the new reload
5917 clobbering the register used by the RELOAD_OTHER. */
5925 && (! rld[i].in || rld[i].out
5926 || ! rtx_equal_p (other_input, value)))
5927 || (out && rld[reloadnum].out_reg
5928 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5934 /* Earlyclobbered outputs must conflict with inputs. */
5935 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5941 /* Return 1 if the value in reload reg REGNO, as used by a reload
5942 needed for the part of the insn specified by OPNUM and TYPE,
5943 may be used to load VALUE into it.
5945 MODE is the mode in which the register is used, this is needed to
5946 determine how many hard regs to test.
5948 Other read-only reloads with the same value do not conflict
5949 unless OUT is nonzero and these other reloads have to live while
5950 output reloads live.
5951 If OUT is CONST0_RTX, this is a special case: it means that the
5952 test should not be for using register REGNO as reload register, but
5953 for copying from register REGNO into the reload register.
5955 RELOADNUM is the number of the reload we want to load this value for;
5956 a reload does not conflict with itself.
5958 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5959 reloads that load an address for the very reload we are considering.
5961 The caller has to make sure that there is no conflict with the return
5965 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5966 enum reload_type type, rtx value, rtx out, int reloadnum,
5967 int ignore_address_reloads)
5969 int nregs = hard_regno_nregs[regno][mode];
5971 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5972 value, out, reloadnum,
5973 ignore_address_reloads))
5978 /* Return nonzero if the rtx X is invariant over the current function. */
5979 /* ??? Actually, the places where we use this expect exactly what is
5980 tested here, and not everything that is function invariant. In
5981 particular, the frame pointer and arg pointer are special cased;
5982 pic_offset_table_rtx is not, and we must not spill these things to
5986 function_invariant_p (const_rtx x)
5990 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5992 if (GET_CODE (x) == PLUS
5993 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5994 && GET_CODE (XEXP (x, 1)) == CONST_INT)
5999 /* Determine whether the reload reg X overlaps any rtx'es used for
6000 overriding inheritance. Return nonzero if so. */
6003 conflicts_with_override (rtx x)
6006 for (i = 0; i < n_reloads; i++)
6007 if (reload_override_in[i]
6008 && reg_overlap_mentioned_p (x, reload_override_in[i]))
6013 /* Give an error message saying we failed to find a reload for INSN,
6014 and clear out reload R. */
6016 failed_reload (rtx insn, int r)
6018 if (asm_noperands (PATTERN (insn)) < 0)
6019 /* It's the compiler's fault. */
6020 fatal_insn ("could not find a spill register", insn);
6022 /* It's the user's fault; the operand's mode and constraint
6023 don't match. Disable this reload so we don't crash in final. */
6024 error_for_asm (insn,
6025 "%<asm%> operand constraint incompatible with operand size");
6029 rld[r].optional = 1;
6030 rld[r].secondary_p = 1;
6033 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6034 for reload R. If it's valid, get an rtx for it. Return nonzero if
6037 set_reload_reg (int i, int r)
6039 /* regno is 'set but not used' if HARD_REGNO_MODE_OK doesn't use its first
6041 int regno ATTRIBUTE_UNUSED;
6042 rtx reg = spill_reg_rtx[i];
6044 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
6045 spill_reg_rtx[i] = reg
6046 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
6048 regno = true_regnum (reg);
6050 /* Detect when the reload reg can't hold the reload mode.
6051 This used to be one `if', but Sequent compiler can't handle that. */
6052 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
6054 enum machine_mode test_mode = VOIDmode;
6056 test_mode = GET_MODE (rld[r].in);
6057 /* If rld[r].in has VOIDmode, it means we will load it
6058 in whatever mode the reload reg has: to wit, rld[r].mode.
6059 We have already tested that for validity. */
6060 /* Aside from that, we need to test that the expressions
6061 to reload from or into have modes which are valid for this
6062 reload register. Otherwise the reload insns would be invalid. */
6063 if (! (rld[r].in != 0 && test_mode != VOIDmode
6064 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
6065 if (! (rld[r].out != 0
6066 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
6068 /* The reg is OK. */
6071 /* Mark as in use for this insn the reload regs we use
6073 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
6074 rld[r].when_needed, rld[r].mode);
6076 rld[r].reg_rtx = reg;
6077 reload_spill_index[r] = spill_regs[i];
6084 /* Find a spill register to use as a reload register for reload R.
6085 LAST_RELOAD is nonzero if this is the last reload for the insn being
6088 Set rld[R].reg_rtx to the register allocated.
6090 We return 1 if successful, or 0 if we couldn't find a spill reg and
6091 we didn't change anything. */
6094 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
6099 /* If we put this reload ahead, thinking it is a group,
6100 then insist on finding a group. Otherwise we can grab a
6101 reg that some other reload needs.
6102 (That can happen when we have a 68000 DATA_OR_FP_REG
6103 which is a group of data regs or one fp reg.)
6104 We need not be so restrictive if there are no more reloads
6107 ??? Really it would be nicer to have smarter handling
6108 for that kind of reg class, where a problem like this is normal.
6109 Perhaps those classes should be avoided for reloading
6110 by use of more alternatives. */
6112 int force_group = rld[r].nregs > 1 && ! last_reload;
6114 /* If we want a single register and haven't yet found one,
6115 take any reg in the right class and not in use.
6116 If we want a consecutive group, here is where we look for it.
6118 We use three passes so we can first look for reload regs to
6119 reuse, which are already in use for other reloads in this insn,
6120 and only then use additional registers which are not "bad", then
6121 finally any register.
6123 I think that maximizing reuse is needed to make sure we don't
6124 run out of reload regs. Suppose we have three reloads, and
6125 reloads A and B can share regs. These need two regs.
6126 Suppose A and B are given different regs.
6127 That leaves none for C. */
6128 for (pass = 0; pass < 3; pass++)
6130 /* I is the index in spill_regs.
6131 We advance it round-robin between insns to use all spill regs
6132 equally, so that inherited reloads have a chance
6133 of leapfrogging each other. */
6137 for (count = 0; count < n_spills; count++)
6139 int rclass = (int) rld[r].rclass;
6145 regnum = spill_regs[i];
6147 if ((reload_reg_free_p (regnum, rld[r].opnum,
6150 /* We check reload_reg_used to make sure we
6151 don't clobber the return register. */
6152 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
6153 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
6154 rld[r].when_needed, rld[r].in,
6156 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
6157 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
6158 /* Look first for regs to share, then for unshared. But
6159 don't share regs used for inherited reloads; they are
6160 the ones we want to preserve. */
6162 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
6164 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
6167 int nr = hard_regno_nregs[regnum][rld[r].mode];
6169 /* During the second pass we want to avoid reload registers
6170 which are "bad" for this reload. */
6172 && ira_bad_reload_regno (regnum, rld[r].in, rld[r].out))
6175 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6176 (on 68000) got us two FP regs. If NR is 1,
6177 we would reject both of them. */
6180 /* If we need only one reg, we have already won. */
6183 /* But reject a single reg if we demand a group. */
6188 /* Otherwise check that as many consecutive regs as we need
6189 are available here. */
6192 int regno = regnum + nr - 1;
6193 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
6194 && spill_reg_order[regno] >= 0
6195 && reload_reg_free_p (regno, rld[r].opnum,
6196 rld[r].when_needed)))
6205 /* If we found something on the current pass, omit later passes. */
6206 if (count < n_spills)
6210 /* We should have found a spill register by now. */
6211 if (count >= n_spills)
6214 /* I is the index in SPILL_REG_RTX of the reload register we are to
6215 allocate. Get an rtx for it and find its register number. */
6217 return set_reload_reg (i, r);
6220 /* Initialize all the tables needed to allocate reload registers.
6221 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6222 is the array we use to restore the reg_rtx field for every reload. */
6225 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
6229 for (i = 0; i < n_reloads; i++)
6230 rld[i].reg_rtx = save_reload_reg_rtx[i];
6232 memset (reload_inherited, 0, MAX_RELOADS);
6233 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
6234 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
6236 CLEAR_HARD_REG_SET (reload_reg_used);
6237 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
6238 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
6239 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
6240 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
6241 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
6243 CLEAR_HARD_REG_SET (reg_used_in_insn);
6246 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
6247 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6248 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
6249 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6250 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
6251 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
6254 for (i = 0; i < reload_n_operands; i++)
6256 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
6257 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
6258 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
6259 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
6260 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
6261 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
6264 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
6266 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
6268 for (i = 0; i < n_reloads; i++)
6269 /* If we have already decided to use a certain register,
6270 don't use it in another way. */
6272 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
6273 rld[i].when_needed, rld[i].mode);
6276 /* Assign hard reg targets for the pseudo-registers we must reload
6277 into hard regs for this insn.
6278 Also output the instructions to copy them in and out of the hard regs.
6280 For machines with register classes, we are responsible for
6281 finding a reload reg in the proper class. */
6284 choose_reload_regs (struct insn_chain *chain)
6286 rtx insn = chain->insn;
6288 unsigned int max_group_size = 1;
6289 enum reg_class group_class = NO_REGS;
6290 int pass, win, inheritance;
6292 rtx save_reload_reg_rtx[MAX_RELOADS];
6294 /* In order to be certain of getting the registers we need,
6295 we must sort the reloads into order of increasing register class.
6296 Then our grabbing of reload registers will parallel the process
6297 that provided the reload registers.
6299 Also note whether any of the reloads wants a consecutive group of regs.
6300 If so, record the maximum size of the group desired and what
6301 register class contains all the groups needed by this insn. */
6303 for (j = 0; j < n_reloads; j++)
6305 reload_order[j] = j;
6306 if (rld[j].reg_rtx != NULL_RTX)
6308 gcc_assert (REG_P (rld[j].reg_rtx)
6309 && HARD_REGISTER_P (rld[j].reg_rtx));
6310 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
6313 reload_spill_index[j] = -1;
6315 if (rld[j].nregs > 1)
6317 max_group_size = MAX (rld[j].nregs, max_group_size);
6319 = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
6322 save_reload_reg_rtx[j] = rld[j].reg_rtx;
6326 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
6328 /* If -O, try first with inheritance, then turning it off.
6329 If not -O, don't do inheritance.
6330 Using inheritance when not optimizing leads to paradoxes
6331 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6332 because one side of the comparison might be inherited. */
6334 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
6336 choose_reload_regs_init (chain, save_reload_reg_rtx);
6338 /* Process the reloads in order of preference just found.
6339 Beyond this point, subregs can be found in reload_reg_rtx.
6341 This used to look for an existing reloaded home for all of the
6342 reloads, and only then perform any new reloads. But that could lose
6343 if the reloads were done out of reg-class order because a later
6344 reload with a looser constraint might have an old home in a register
6345 needed by an earlier reload with a tighter constraint.
6347 To solve this, we make two passes over the reloads, in the order
6348 described above. In the first pass we try to inherit a reload
6349 from a previous insn. If there is a later reload that needs a
6350 class that is a proper subset of the class being processed, we must
6351 also allocate a spill register during the first pass.
6353 Then make a second pass over the reloads to allocate any reloads
6354 that haven't been given registers yet. */
6356 for (j = 0; j < n_reloads; j++)
6358 int r = reload_order[j];
6359 rtx search_equiv = NULL_RTX;
6361 /* Ignore reloads that got marked inoperative. */
6362 if (rld[r].out == 0 && rld[r].in == 0
6363 && ! rld[r].secondary_p)
6366 /* If find_reloads chose to use reload_in or reload_out as a reload
6367 register, we don't need to chose one. Otherwise, try even if it
6368 found one since we might save an insn if we find the value lying
6370 Try also when reload_in is a pseudo without a hard reg. */
6371 if (rld[r].in != 0 && rld[r].reg_rtx != 0
6372 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
6373 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
6374 && !MEM_P (rld[r].in)
6375 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
6378 #if 0 /* No longer needed for correct operation.
6379 It might give better code, or might not; worth an experiment? */
6380 /* If this is an optional reload, we can't inherit from earlier insns
6381 until we are sure that any non-optional reloads have been allocated.
6382 The following code takes advantage of the fact that optional reloads
6383 are at the end of reload_order. */
6384 if (rld[r].optional != 0)
6385 for (i = 0; i < j; i++)
6386 if ((rld[reload_order[i]].out != 0
6387 || rld[reload_order[i]].in != 0
6388 || rld[reload_order[i]].secondary_p)
6389 && ! rld[reload_order[i]].optional
6390 && rld[reload_order[i]].reg_rtx == 0)
6391 allocate_reload_reg (chain, reload_order[i], 0);
6394 /* First see if this pseudo is already available as reloaded
6395 for a previous insn. We cannot try to inherit for reloads
6396 that are smaller than the maximum number of registers needed
6397 for groups unless the register we would allocate cannot be used
6400 We could check here to see if this is a secondary reload for
6401 an object that is already in a register of the desired class.
6402 This would avoid the need for the secondary reload register.
6403 But this is complex because we can't easily determine what
6404 objects might want to be loaded via this reload. So let a
6405 register be allocated here. In `emit_reload_insns' we suppress
6406 one of the loads in the case described above. */
6412 enum machine_mode mode = VOIDmode;
6416 else if (REG_P (rld[r].in))
6418 regno = REGNO (rld[r].in);
6419 mode = GET_MODE (rld[r].in);
6421 else if (REG_P (rld[r].in_reg))
6423 regno = REGNO (rld[r].in_reg);
6424 mode = GET_MODE (rld[r].in_reg);
6426 else if (GET_CODE (rld[r].in_reg) == SUBREG
6427 && REG_P (SUBREG_REG (rld[r].in_reg)))
6429 regno = REGNO (SUBREG_REG (rld[r].in_reg));
6430 if (regno < FIRST_PSEUDO_REGISTER)
6431 regno = subreg_regno (rld[r].in_reg);
6433 byte = SUBREG_BYTE (rld[r].in_reg);
6434 mode = GET_MODE (rld[r].in_reg);
6437 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6438 && REG_P (XEXP (rld[r].in_reg, 0)))
6440 regno = REGNO (XEXP (rld[r].in_reg, 0));
6441 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6442 rld[r].out = rld[r].in;
6446 /* This won't work, since REGNO can be a pseudo reg number.
6447 Also, it takes much more hair to keep track of all the things
6448 that can invalidate an inherited reload of part of a pseudoreg. */
6449 else if (GET_CODE (rld[r].in) == SUBREG
6450 && REG_P (SUBREG_REG (rld[r].in)))
6451 regno = subreg_regno (rld[r].in);
6455 && reg_last_reload_reg[regno] != 0
6456 #ifdef CANNOT_CHANGE_MODE_CLASS
6457 /* Verify that the register it's in can be used in
6459 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
6460 GET_MODE (reg_last_reload_reg[regno]),
6465 enum reg_class rclass = rld[r].rclass, last_class;
6466 rtx last_reg = reg_last_reload_reg[regno];
6467 enum machine_mode need_mode;
6469 i = REGNO (last_reg);
6470 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6471 last_class = REGNO_REG_CLASS (i);
6477 = smallest_mode_for_size
6478 (GET_MODE_BITSIZE (mode) + byte * BITS_PER_UNIT,
6479 GET_MODE_CLASS (mode) == MODE_PARTIAL_INT
6480 ? MODE_INT : GET_MODE_CLASS (mode));
6482 if ((GET_MODE_SIZE (GET_MODE (last_reg))
6483 >= GET_MODE_SIZE (need_mode))
6484 && reg_reloaded_contents[i] == regno
6485 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6486 && HARD_REGNO_MODE_OK (i, rld[r].mode)
6487 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6488 /* Even if we can't use this register as a reload
6489 register, we might use it for reload_override_in,
6490 if copying it to the desired class is cheap
6492 || ((register_move_cost (mode, last_class, rclass)
6493 < memory_move_cost (mode, rclass, true))
6494 && (secondary_reload_class (1, rclass, mode,
6497 #ifdef SECONDARY_MEMORY_NEEDED
6498 && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
6503 && (rld[r].nregs == max_group_size
6504 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6506 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6507 rld[r].when_needed, rld[r].in,
6510 /* If a group is needed, verify that all the subsequent
6511 registers still have their values intact. */
6512 int nr = hard_regno_nregs[i][rld[r].mode];
6515 for (k = 1; k < nr; k++)
6516 if (reg_reloaded_contents[i + k] != regno
6517 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6525 last_reg = (GET_MODE (last_reg) == mode
6526 ? last_reg : gen_rtx_REG (mode, i));
6529 for (k = 0; k < nr; k++)
6530 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6533 /* We found a register that contains the
6534 value we need. If this register is the
6535 same as an `earlyclobber' operand of the
6536 current insn, just mark it as a place to
6537 reload from since we can't use it as the
6538 reload register itself. */
6540 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6541 if (reg_overlap_mentioned_for_reload_p
6542 (reg_last_reload_reg[regno],
6543 reload_earlyclobbers[i1]))
6546 if (i1 != n_earlyclobbers
6547 || ! (free_for_value_p (i, rld[r].mode,
6549 rld[r].when_needed, rld[r].in,
6551 /* Don't use it if we'd clobber a pseudo reg. */
6552 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6554 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6555 /* Don't clobber the frame pointer. */
6556 || (i == HARD_FRAME_POINTER_REGNUM
6557 && frame_pointer_needed
6559 /* Don't really use the inherited spill reg
6560 if we need it wider than we've got it. */
6561 || (GET_MODE_SIZE (rld[r].mode)
6562 > GET_MODE_SIZE (mode))
6565 /* If find_reloads chose reload_out as reload
6566 register, stay with it - that leaves the
6567 inherited register for subsequent reloads. */
6568 || (rld[r].out && rld[r].reg_rtx
6569 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6571 if (! rld[r].optional)
6573 reload_override_in[r] = last_reg;
6574 reload_inheritance_insn[r]
6575 = reg_reloaded_insn[i];
6581 /* We can use this as a reload reg. */
6582 /* Mark the register as in use for this part of
6584 mark_reload_reg_in_use (i,
6588 rld[r].reg_rtx = last_reg;
6589 reload_inherited[r] = 1;
6590 reload_inheritance_insn[r]
6591 = reg_reloaded_insn[i];
6592 reload_spill_index[r] = i;
6593 for (k = 0; k < nr; k++)
6594 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6602 /* Here's another way to see if the value is already lying around. */
6605 && ! reload_inherited[r]
6607 && (CONSTANT_P (rld[r].in)
6608 || GET_CODE (rld[r].in) == PLUS
6609 || REG_P (rld[r].in)
6610 || MEM_P (rld[r].in))
6611 && (rld[r].nregs == max_group_size
6612 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6613 search_equiv = rld[r].in;
6618 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6619 -1, NULL, 0, rld[r].mode);
6625 regno = REGNO (equiv);
6628 /* This must be a SUBREG of a hard register.
6629 Make a new REG since this might be used in an
6630 address and not all machines support SUBREGs
6632 gcc_assert (GET_CODE (equiv) == SUBREG);
6633 regno = subreg_regno (equiv);
6634 equiv = gen_rtx_REG (rld[r].mode, regno);
6635 /* If we choose EQUIV as the reload register, but the
6636 loop below decides to cancel the inheritance, we'll
6637 end up reloading EQUIV in rld[r].mode, not the mode
6638 it had originally. That isn't safe when EQUIV isn't
6639 available as a spill register since its value might
6640 still be live at this point. */
6641 for (i = regno; i < regno + (int) rld[r].nregs; i++)
6642 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6647 /* If we found a spill reg, reject it unless it is free
6648 and of the desired class. */
6652 int bad_for_class = 0;
6653 int max_regno = regno + rld[r].nregs;
6655 for (i = regno; i < max_regno; i++)
6657 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6659 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6664 && ! free_for_value_p (regno, rld[r].mode,
6665 rld[r].opnum, rld[r].when_needed,
6666 rld[r].in, rld[r].out, r, 1))
6671 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6674 /* We found a register that contains the value we need.
6675 If this register is the same as an `earlyclobber' operand
6676 of the current insn, just mark it as a place to reload from
6677 since we can't use it as the reload register itself. */
6680 for (i = 0; i < n_earlyclobbers; i++)
6681 if (reg_overlap_mentioned_for_reload_p (equiv,
6682 reload_earlyclobbers[i]))
6684 if (! rld[r].optional)
6685 reload_override_in[r] = equiv;
6690 /* If the equiv register we have found is explicitly clobbered
6691 in the current insn, it depends on the reload type if we
6692 can use it, use it for reload_override_in, or not at all.
6693 In particular, we then can't use EQUIV for a
6694 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6698 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6699 switch (rld[r].when_needed)
6701 case RELOAD_FOR_OTHER_ADDRESS:
6702 case RELOAD_FOR_INPADDR_ADDRESS:
6703 case RELOAD_FOR_INPUT_ADDRESS:
6704 case RELOAD_FOR_OPADDR_ADDR:
6707 case RELOAD_FOR_INPUT:
6708 case RELOAD_FOR_OPERAND_ADDRESS:
6709 if (! rld[r].optional)
6710 reload_override_in[r] = equiv;
6716 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6717 switch (rld[r].when_needed)
6719 case RELOAD_FOR_OTHER_ADDRESS:
6720 case RELOAD_FOR_INPADDR_ADDRESS:
6721 case RELOAD_FOR_INPUT_ADDRESS:
6722 case RELOAD_FOR_OPADDR_ADDR:
6723 case RELOAD_FOR_OPERAND_ADDRESS:
6724 case RELOAD_FOR_INPUT:
6727 if (! rld[r].optional)
6728 reload_override_in[r] = equiv;
6736 /* If we found an equivalent reg, say no code need be generated
6737 to load it, and use it as our reload reg. */
6739 && (regno != HARD_FRAME_POINTER_REGNUM
6740 || !frame_pointer_needed))
6742 int nr = hard_regno_nregs[regno][rld[r].mode];
6744 rld[r].reg_rtx = equiv;
6745 reload_spill_index[r] = regno;
6746 reload_inherited[r] = 1;
6748 /* If reg_reloaded_valid is not set for this register,
6749 there might be a stale spill_reg_store lying around.
6750 We must clear it, since otherwise emit_reload_insns
6751 might delete the store. */
6752 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6753 spill_reg_store[regno] = NULL_RTX;
6754 /* If any of the hard registers in EQUIV are spill
6755 registers, mark them as in use for this insn. */
6756 for (k = 0; k < nr; k++)
6758 i = spill_reg_order[regno + k];
6761 mark_reload_reg_in_use (regno, rld[r].opnum,
6764 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6771 /* If we found a register to use already, or if this is an optional
6772 reload, we are done. */
6773 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6777 /* No longer needed for correct operation. Might or might
6778 not give better code on the average. Want to experiment? */
6780 /* See if there is a later reload that has a class different from our
6781 class that intersects our class or that requires less register
6782 than our reload. If so, we must allocate a register to this
6783 reload now, since that reload might inherit a previous reload
6784 and take the only available register in our class. Don't do this
6785 for optional reloads since they will force all previous reloads
6786 to be allocated. Also don't do this for reloads that have been
6789 for (i = j + 1; i < n_reloads; i++)
6791 int s = reload_order[i];
6793 if ((rld[s].in == 0 && rld[s].out == 0
6794 && ! rld[s].secondary_p)
6798 if ((rld[s].rclass != rld[r].rclass
6799 && reg_classes_intersect_p (rld[r].rclass,
6801 || rld[s].nregs < rld[r].nregs)
6808 allocate_reload_reg (chain, r, j == n_reloads - 1);
6812 /* Now allocate reload registers for anything non-optional that
6813 didn't get one yet. */
6814 for (j = 0; j < n_reloads; j++)
6816 int r = reload_order[j];
6818 /* Ignore reloads that got marked inoperative. */
6819 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6822 /* Skip reloads that already have a register allocated or are
6824 if (rld[r].reg_rtx != 0 || rld[r].optional)
6827 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6831 /* If that loop got all the way, we have won. */
6838 /* Loop around and try without any inheritance. */
6843 /* First undo everything done by the failed attempt
6844 to allocate with inheritance. */
6845 choose_reload_regs_init (chain, save_reload_reg_rtx);
6847 /* Some sanity tests to verify that the reloads found in the first
6848 pass are identical to the ones we have now. */
6849 gcc_assert (chain->n_reloads == n_reloads);
6851 for (i = 0; i < n_reloads; i++)
6853 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6855 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6856 for (j = 0; j < n_spills; j++)
6857 if (spill_regs[j] == chain->rld[i].regno)
6858 if (! set_reload_reg (j, i))
6859 failed_reload (chain->insn, i);
6863 /* If we thought we could inherit a reload, because it seemed that
6864 nothing else wanted the same reload register earlier in the insn,
6865 verify that assumption, now that all reloads have been assigned.
6866 Likewise for reloads where reload_override_in has been set. */
6868 /* If doing expensive optimizations, do one preliminary pass that doesn't
6869 cancel any inheritance, but removes reloads that have been needed only
6870 for reloads that we know can be inherited. */
6871 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6873 for (j = 0; j < n_reloads; j++)
6875 int r = reload_order[j];
6877 if (reload_inherited[r] && rld[r].reg_rtx)
6878 check_reg = rld[r].reg_rtx;
6879 else if (reload_override_in[r]
6880 && (REG_P (reload_override_in[r])
6881 || GET_CODE (reload_override_in[r]) == SUBREG))
6882 check_reg = reload_override_in[r];
6885 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6886 rld[r].opnum, rld[r].when_needed, rld[r].in,
6887 (reload_inherited[r]
6888 ? rld[r].out : const0_rtx),
6893 reload_inherited[r] = 0;
6894 reload_override_in[r] = 0;
6896 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6897 reload_override_in, then we do not need its related
6898 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6899 likewise for other reload types.
6900 We handle this by removing a reload when its only replacement
6901 is mentioned in reload_in of the reload we are going to inherit.
6902 A special case are auto_inc expressions; even if the input is
6903 inherited, we still need the address for the output. We can
6904 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6905 If we succeeded removing some reload and we are doing a preliminary
6906 pass just to remove such reloads, make another pass, since the
6907 removal of one reload might allow us to inherit another one. */
6909 && rld[r].out != rld[r].in
6910 && remove_address_replacements (rld[r].in) && pass)
6915 /* Now that reload_override_in is known valid,
6916 actually override reload_in. */
6917 for (j = 0; j < n_reloads; j++)
6918 if (reload_override_in[j])
6919 rld[j].in = reload_override_in[j];
6921 /* If this reload won't be done because it has been canceled or is
6922 optional and not inherited, clear reload_reg_rtx so other
6923 routines (such as subst_reloads) don't get confused. */
6924 for (j = 0; j < n_reloads; j++)
6925 if (rld[j].reg_rtx != 0
6926 && ((rld[j].optional && ! reload_inherited[j])
6927 || (rld[j].in == 0 && rld[j].out == 0
6928 && ! rld[j].secondary_p)))
6930 int regno = true_regnum (rld[j].reg_rtx);
6932 if (spill_reg_order[regno] >= 0)
6933 clear_reload_reg_in_use (regno, rld[j].opnum,
6934 rld[j].when_needed, rld[j].mode);
6936 reload_spill_index[j] = -1;
6939 /* Record which pseudos and which spill regs have output reloads. */
6940 for (j = 0; j < n_reloads; j++)
6942 int r = reload_order[j];
6944 i = reload_spill_index[r];
6946 /* I is nonneg if this reload uses a register.
6947 If rld[r].reg_rtx is 0, this is an optional reload
6948 that we opted to ignore. */
6949 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6950 && rld[r].reg_rtx != 0)
6952 int nregno = REGNO (rld[r].out_reg);
6955 if (nregno < FIRST_PSEUDO_REGISTER)
6956 nr = hard_regno_nregs[nregno][rld[r].mode];
6959 SET_REGNO_REG_SET (®_has_output_reload,
6964 nr = hard_regno_nregs[i][rld[r].mode];
6966 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6969 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6970 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6971 || rld[r].when_needed == RELOAD_FOR_INSN);
6976 /* Deallocate the reload register for reload R. This is called from
6977 remove_address_replacements. */
6980 deallocate_reload_reg (int r)
6984 if (! rld[r].reg_rtx)
6986 regno = true_regnum (rld[r].reg_rtx);
6988 if (spill_reg_order[regno] >= 0)
6989 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6991 reload_spill_index[r] = -1;
6994 /* These arrays are filled by emit_reload_insns and its subroutines. */
6995 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6996 static rtx other_input_address_reload_insns = 0;
6997 static rtx other_input_reload_insns = 0;
6998 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6999 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7000 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
7001 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
7002 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7003 static rtx operand_reload_insns = 0;
7004 static rtx other_operand_reload_insns = 0;
7005 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
7007 /* Values to be put in spill_reg_store are put here first. */
7008 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
7009 static HARD_REG_SET reg_reloaded_died;
7011 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7012 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7013 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7014 adjusted register, and return true. Otherwise, return false. */
7016 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
7017 enum reg_class new_class,
7018 enum machine_mode new_mode)
7023 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
7025 unsigned regno = REGNO (reg);
7027 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
7029 if (GET_MODE (reg) != new_mode)
7031 if (!HARD_REGNO_MODE_OK (regno, new_mode))
7033 if (hard_regno_nregs[regno][new_mode]
7034 > hard_regno_nregs[regno][GET_MODE (reg)])
7036 reg = reload_adjust_reg_for_mode (reg, new_mode);
7044 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7045 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7046 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7047 adjusted register, and return true. Otherwise, return false. */
7049 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
7050 enum insn_code icode)
7053 enum reg_class new_class = scratch_reload_class (icode);
7054 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
7056 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
7057 new_class, new_mode);
7060 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7061 has the number J. OLD contains the value to be used as input. */
7064 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
7067 rtx insn = chain->insn;
7069 rtx oldequiv_reg = 0;
7072 enum machine_mode mode;
7075 /* delete_output_reload is only invoked properly if old contains
7076 the original pseudo register. Since this is replaced with a
7077 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7078 find the pseudo in RELOAD_IN_REG. */
7079 if (reload_override_in[j]
7080 && REG_P (rl->in_reg))
7087 else if (REG_P (oldequiv))
7088 oldequiv_reg = oldequiv;
7089 else if (GET_CODE (oldequiv) == SUBREG)
7090 oldequiv_reg = SUBREG_REG (oldequiv);
7092 reloadreg = reload_reg_rtx_for_input[j];
7093 mode = GET_MODE (reloadreg);
7095 /* If we are reloading from a register that was recently stored in
7096 with an output-reload, see if we can prove there was
7097 actually no need to store the old value in it. */
7099 if (optimize && REG_P (oldequiv)
7100 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
7101 && spill_reg_store[REGNO (oldequiv)]
7103 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
7104 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
7106 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
7108 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7111 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
7112 oldequiv = SUBREG_REG (oldequiv);
7113 if (GET_MODE (oldequiv) != VOIDmode
7114 && mode != GET_MODE (oldequiv))
7115 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
7117 /* Switch to the right place to emit the reload insns. */
7118 switch (rl->when_needed)
7121 where = &other_input_reload_insns;
7123 case RELOAD_FOR_INPUT:
7124 where = &input_reload_insns[rl->opnum];
7126 case RELOAD_FOR_INPUT_ADDRESS:
7127 where = &input_address_reload_insns[rl->opnum];
7129 case RELOAD_FOR_INPADDR_ADDRESS:
7130 where = &inpaddr_address_reload_insns[rl->opnum];
7132 case RELOAD_FOR_OUTPUT_ADDRESS:
7133 where = &output_address_reload_insns[rl->opnum];
7135 case RELOAD_FOR_OUTADDR_ADDRESS:
7136 where = &outaddr_address_reload_insns[rl->opnum];
7138 case RELOAD_FOR_OPERAND_ADDRESS:
7139 where = &operand_reload_insns;
7141 case RELOAD_FOR_OPADDR_ADDR:
7142 where = &other_operand_reload_insns;
7144 case RELOAD_FOR_OTHER_ADDRESS:
7145 where = &other_input_address_reload_insns;
7151 push_to_sequence (*where);
7153 /* Auto-increment addresses must be reloaded in a special way. */
7154 if (rl->out && ! rl->out_reg)
7156 /* We are not going to bother supporting the case where a
7157 incremented register can't be copied directly from
7158 OLDEQUIV since this seems highly unlikely. */
7159 gcc_assert (rl->secondary_in_reload < 0);
7161 if (reload_inherited[j])
7162 oldequiv = reloadreg;
7164 old = XEXP (rl->in_reg, 0);
7166 /* Prevent normal processing of this reload. */
7168 /* Output a special code sequence for this case, and forget about
7169 spill reg information. */
7170 new_spill_reg_store[REGNO (reloadreg)] = NULL;
7171 inc_for_reload (reloadreg, oldequiv, rl->out, rl->inc);
7174 /* If we are reloading a pseudo-register that was set by the previous
7175 insn, see if we can get rid of that pseudo-register entirely
7176 by redirecting the previous insn into our reload register. */
7178 else if (optimize && REG_P (old)
7179 && REGNO (old) >= FIRST_PSEUDO_REGISTER
7180 && dead_or_set_p (insn, old)
7181 /* This is unsafe if some other reload
7182 uses the same reg first. */
7183 && ! conflicts_with_override (reloadreg)
7184 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
7185 rl->when_needed, old, rl->out, j, 0))
7187 rtx temp = PREV_INSN (insn);
7188 while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp)))
7189 temp = PREV_INSN (temp);
7191 && NONJUMP_INSN_P (temp)
7192 && GET_CODE (PATTERN (temp)) == SET
7193 && SET_DEST (PATTERN (temp)) == old
7194 /* Make sure we can access insn_operand_constraint. */
7195 && asm_noperands (PATTERN (temp)) < 0
7196 /* This is unsafe if operand occurs more than once in current
7197 insn. Perhaps some occurrences aren't reloaded. */
7198 && count_occurrences (PATTERN (insn), old, 0) == 1)
7200 rtx old = SET_DEST (PATTERN (temp));
7201 /* Store into the reload register instead of the pseudo. */
7202 SET_DEST (PATTERN (temp)) = reloadreg;
7204 /* Verify that resulting insn is valid. */
7205 extract_insn (temp);
7206 if (constrain_operands (1))
7208 /* If the previous insn is an output reload, the source is
7209 a reload register, and its spill_reg_store entry will
7210 contain the previous destination. This is now
7212 if (REG_P (SET_SRC (PATTERN (temp)))
7213 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
7215 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7216 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7219 /* If these are the only uses of the pseudo reg,
7220 pretend for GDB it lives in the reload reg we used. */
7221 if (REG_N_DEATHS (REGNO (old)) == 1
7222 && REG_N_SETS (REGNO (old)) == 1)
7224 reg_renumber[REGNO (old)] = REGNO (reloadreg);
7225 if (ira_conflicts_p)
7226 /* Inform IRA about the change. */
7227 ira_mark_allocation_change (REGNO (old));
7228 alter_reg (REGNO (old), -1, false);
7232 /* Adjust any debug insns between temp and insn. */
7233 while ((temp = NEXT_INSN (temp)) != insn)
7234 if (DEBUG_INSN_P (temp))
7235 replace_rtx (PATTERN (temp), old, reloadreg);
7237 gcc_assert (NOTE_P (temp));
7241 SET_DEST (PATTERN (temp)) = old;
7246 /* We can't do that, so output an insn to load RELOADREG. */
7248 /* If we have a secondary reload, pick up the secondary register
7249 and icode, if any. If OLDEQUIV and OLD are different or
7250 if this is an in-out reload, recompute whether or not we
7251 still need a secondary register and what the icode should
7252 be. If we still need a secondary register and the class or
7253 icode is different, go back to reloading from OLD if using
7254 OLDEQUIV means that we got the wrong type of register. We
7255 cannot have different class or icode due to an in-out reload
7256 because we don't make such reloads when both the input and
7257 output need secondary reload registers. */
7259 if (! special && rl->secondary_in_reload >= 0)
7261 rtx second_reload_reg = 0;
7262 rtx third_reload_reg = 0;
7263 int secondary_reload = rl->secondary_in_reload;
7264 rtx real_oldequiv = oldequiv;
7267 enum insn_code icode;
7268 enum insn_code tertiary_icode = CODE_FOR_nothing;
7270 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7271 and similarly for OLD.
7272 See comments in get_secondary_reload in reload.c. */
7273 /* If it is a pseudo that cannot be replaced with its
7274 equivalent MEM, we must fall back to reload_in, which
7275 will have all the necessary substitutions registered.
7276 Likewise for a pseudo that can't be replaced with its
7277 equivalent constant.
7279 Take extra care for subregs of such pseudos. Note that
7280 we cannot use reg_equiv_mem in this case because it is
7281 not in the right mode. */
7284 if (GET_CODE (tmp) == SUBREG)
7285 tmp = SUBREG_REG (tmp);
7287 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7288 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7289 || reg_equiv_constant[REGNO (tmp)] != 0))
7291 if (! reg_equiv_mem[REGNO (tmp)]
7292 || num_not_at_initial_offset
7293 || GET_CODE (oldequiv) == SUBREG)
7294 real_oldequiv = rl->in;
7296 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
7300 if (GET_CODE (tmp) == SUBREG)
7301 tmp = SUBREG_REG (tmp);
7303 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7304 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7305 || reg_equiv_constant[REGNO (tmp)] != 0))
7307 if (! reg_equiv_mem[REGNO (tmp)]
7308 || num_not_at_initial_offset
7309 || GET_CODE (old) == SUBREG)
7312 real_old = reg_equiv_mem[REGNO (tmp)];
7315 second_reload_reg = rld[secondary_reload].reg_rtx;
7316 if (rld[secondary_reload].secondary_in_reload >= 0)
7318 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7320 third_reload_reg = rld[tertiary_reload].reg_rtx;
7321 tertiary_icode = rld[secondary_reload].secondary_in_icode;
7322 /* We'd have to add more code for quartary reloads. */
7323 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7325 icode = rl->secondary_in_icode;
7327 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7328 || (rl->in != 0 && rl->out != 0))
7330 secondary_reload_info sri, sri2;
7331 enum reg_class new_class, new_t_class;
7333 sri.icode = CODE_FOR_nothing;
7334 sri.prev_sri = NULL;
7336 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7340 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7341 second_reload_reg = 0;
7342 else if (new_class == NO_REGS)
7344 if (reload_adjust_reg_for_icode (&second_reload_reg,
7346 (enum insn_code) sri.icode))
7348 icode = (enum insn_code) sri.icode;
7349 third_reload_reg = 0;
7354 real_oldequiv = real_old;
7357 else if (sri.icode != CODE_FOR_nothing)
7358 /* We currently lack a way to express this in reloads. */
7362 sri2.icode = CODE_FOR_nothing;
7363 sri2.prev_sri = &sri;
7365 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7368 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7370 if (reload_adjust_reg_for_temp (&second_reload_reg,
7374 third_reload_reg = 0;
7375 tertiary_icode = (enum insn_code) sri2.icode;
7380 real_oldequiv = real_old;
7383 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7385 rtx intermediate = second_reload_reg;
7387 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7389 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7393 second_reload_reg = intermediate;
7394 tertiary_icode = (enum insn_code) sri2.icode;
7399 real_oldequiv = real_old;
7402 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7404 rtx intermediate = second_reload_reg;
7406 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7408 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7411 second_reload_reg = intermediate;
7412 tertiary_icode = (enum insn_code) sri2.icode;
7417 real_oldequiv = real_old;
7422 /* This could be handled more intelligently too. */
7424 real_oldequiv = real_old;
7429 /* If we still need a secondary reload register, check
7430 to see if it is being used as a scratch or intermediate
7431 register and generate code appropriately. If we need
7432 a scratch register, use REAL_OLDEQUIV since the form of
7433 the insn may depend on the actual address if it is
7436 if (second_reload_reg)
7438 if (icode != CODE_FOR_nothing)
7440 /* We'd have to add extra code to handle this case. */
7441 gcc_assert (!third_reload_reg);
7443 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7444 second_reload_reg));
7449 /* See if we need a scratch register to load the
7450 intermediate register (a tertiary reload). */
7451 if (tertiary_icode != CODE_FOR_nothing)
7453 emit_insn ((GEN_FCN (tertiary_icode)
7454 (second_reload_reg, real_oldequiv,
7455 third_reload_reg)));
7457 else if (third_reload_reg)
7459 gen_reload (third_reload_reg, real_oldequiv,
7462 gen_reload (second_reload_reg, third_reload_reg,
7467 gen_reload (second_reload_reg, real_oldequiv,
7471 oldequiv = second_reload_reg;
7476 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7478 rtx real_oldequiv = oldequiv;
7480 if ((REG_P (oldequiv)
7481 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7482 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
7483 || reg_equiv_constant[REGNO (oldequiv)] != 0))
7484 || (GET_CODE (oldequiv) == SUBREG
7485 && REG_P (SUBREG_REG (oldequiv))
7486 && (REGNO (SUBREG_REG (oldequiv))
7487 >= FIRST_PSEUDO_REGISTER)
7488 && ((reg_equiv_memory_loc
7489 [REGNO (SUBREG_REG (oldequiv))] != 0)
7490 || (reg_equiv_constant
7491 [REGNO (SUBREG_REG (oldequiv))] != 0)))
7492 || (CONSTANT_P (oldequiv)
7493 && (targetm.preferred_reload_class (oldequiv,
7494 REGNO_REG_CLASS (REGNO (reloadreg)))
7496 real_oldequiv = rl->in;
7497 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7501 if (cfun->can_throw_non_call_exceptions)
7502 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7504 /* End this sequence. */
7505 *where = get_insns ();
7508 /* Update reload_override_in so that delete_address_reloads_1
7509 can see the actual register usage. */
7511 reload_override_in[j] = oldequiv;
7514 /* Generate insns to for the output reload RL, which is for the insn described
7515 by CHAIN and has the number J. */
7517 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7521 rtx insn = chain->insn;
7524 enum machine_mode mode;
7528 if (rl->when_needed == RELOAD_OTHER)
7531 push_to_sequence (output_reload_insns[rl->opnum]);
7533 rl_reg_rtx = reload_reg_rtx_for_output[j];
7534 mode = GET_MODE (rl_reg_rtx);
7536 reloadreg = rl_reg_rtx;
7538 /* If we need two reload regs, set RELOADREG to the intermediate
7539 one, since it will be stored into OLD. We might need a secondary
7540 register only for an input reload, so check again here. */
7542 if (rl->secondary_out_reload >= 0)
7545 int secondary_reload = rl->secondary_out_reload;
7546 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7548 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7549 && reg_equiv_mem[REGNO (old)] != 0)
7550 real_old = reg_equiv_mem[REGNO (old)];
7552 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7554 rtx second_reloadreg = reloadreg;
7555 reloadreg = rld[secondary_reload].reg_rtx;
7557 /* See if RELOADREG is to be used as a scratch register
7558 or as an intermediate register. */
7559 if (rl->secondary_out_icode != CODE_FOR_nothing)
7561 /* We'd have to add extra code to handle this case. */
7562 gcc_assert (tertiary_reload < 0);
7564 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7565 (real_old, second_reloadreg, reloadreg)));
7570 /* See if we need both a scratch and intermediate reload
7573 enum insn_code tertiary_icode
7574 = rld[secondary_reload].secondary_out_icode;
7576 /* We'd have to add more code for quartary reloads. */
7577 gcc_assert (tertiary_reload < 0
7578 || rld[tertiary_reload].secondary_out_reload < 0);
7580 if (GET_MODE (reloadreg) != mode)
7581 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7583 if (tertiary_icode != CODE_FOR_nothing)
7585 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7588 /* Copy primary reload reg to secondary reload reg.
7589 (Note that these have been swapped above, then
7590 secondary reload reg to OLD using our insn.) */
7592 /* If REAL_OLD is a paradoxical SUBREG, remove it
7593 and try to put the opposite SUBREG on
7595 if (GET_CODE (real_old) == SUBREG
7596 && (GET_MODE_SIZE (GET_MODE (real_old))
7597 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7598 && 0 != (tem = gen_lowpart_common
7599 (GET_MODE (SUBREG_REG (real_old)),
7601 real_old = SUBREG_REG (real_old), reloadreg = tem;
7603 gen_reload (reloadreg, second_reloadreg,
7604 rl->opnum, rl->when_needed);
7605 emit_insn ((GEN_FCN (tertiary_icode)
7606 (real_old, reloadreg, third_reloadreg)));
7612 /* Copy between the reload regs here and then to
7615 gen_reload (reloadreg, second_reloadreg,
7616 rl->opnum, rl->when_needed);
7617 if (tertiary_reload >= 0)
7619 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7621 gen_reload (third_reloadreg, reloadreg,
7622 rl->opnum, rl->when_needed);
7623 reloadreg = third_reloadreg;
7630 /* Output the last reload insn. */
7635 /* Don't output the last reload if OLD is not the dest of
7636 INSN and is in the src and is clobbered by INSN. */
7637 if (! flag_expensive_optimizations
7639 || !(set = single_set (insn))
7640 || rtx_equal_p (old, SET_DEST (set))
7641 || !reg_mentioned_p (old, SET_SRC (set))
7642 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7643 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7644 gen_reload (old, reloadreg, rl->opnum,
7648 /* Look at all insns we emitted, just to be safe. */
7649 for (p = get_insns (); p; p = NEXT_INSN (p))
7652 rtx pat = PATTERN (p);
7654 /* If this output reload doesn't come from a spill reg,
7655 clear any memory of reloaded copies of the pseudo reg.
7656 If this output reload comes from a spill reg,
7657 reg_has_output_reload will make this do nothing. */
7658 note_stores (pat, forget_old_reloads_1, NULL);
7660 if (reg_mentioned_p (rl_reg_rtx, pat))
7662 rtx set = single_set (insn);
7663 if (reload_spill_index[j] < 0
7665 && SET_SRC (set) == rl_reg_rtx)
7667 int src = REGNO (SET_SRC (set));
7669 reload_spill_index[j] = src;
7670 SET_HARD_REG_BIT (reg_is_output_reload, src);
7671 if (find_regno_note (insn, REG_DEAD, src))
7672 SET_HARD_REG_BIT (reg_reloaded_died, src);
7674 if (HARD_REGISTER_P (rl_reg_rtx))
7676 int s = rl->secondary_out_reload;
7677 set = single_set (p);
7678 /* If this reload copies only to the secondary reload
7679 register, the secondary reload does the actual
7681 if (s >= 0 && set == NULL_RTX)
7682 /* We can't tell what function the secondary reload
7683 has and where the actual store to the pseudo is
7684 made; leave new_spill_reg_store alone. */
7687 && SET_SRC (set) == rl_reg_rtx
7688 && SET_DEST (set) == rld[s].reg_rtx)
7690 /* Usually the next instruction will be the
7691 secondary reload insn; if we can confirm
7692 that it is, setting new_spill_reg_store to
7693 that insn will allow an extra optimization. */
7694 rtx s_reg = rld[s].reg_rtx;
7695 rtx next = NEXT_INSN (p);
7696 rld[s].out = rl->out;
7697 rld[s].out_reg = rl->out_reg;
7698 set = single_set (next);
7699 if (set && SET_SRC (set) == s_reg
7700 && ! new_spill_reg_store[REGNO (s_reg)])
7702 SET_HARD_REG_BIT (reg_is_output_reload,
7704 new_spill_reg_store[REGNO (s_reg)] = next;
7708 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7713 if (rl->when_needed == RELOAD_OTHER)
7715 emit_insn (other_output_reload_insns[rl->opnum]);
7716 other_output_reload_insns[rl->opnum] = get_insns ();
7719 output_reload_insns[rl->opnum] = get_insns ();
7721 if (cfun->can_throw_non_call_exceptions)
7722 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7727 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7728 and has the number J. */
7730 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7732 rtx insn = chain->insn;
7733 rtx old = (rl->in && MEM_P (rl->in)
7734 ? rl->in_reg : rl->in);
7735 rtx reg_rtx = rl->reg_rtx;
7739 enum machine_mode mode;
7741 /* Determine the mode to reload in.
7742 This is very tricky because we have three to choose from.
7743 There is the mode the insn operand wants (rl->inmode).
7744 There is the mode of the reload register RELOADREG.
7745 There is the intrinsic mode of the operand, which we could find
7746 by stripping some SUBREGs.
7747 It turns out that RELOADREG's mode is irrelevant:
7748 we can change that arbitrarily.
7750 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7751 then the reload reg may not support QImode moves, so use SImode.
7752 If foo is in memory due to spilling a pseudo reg, this is safe,
7753 because the QImode value is in the least significant part of a
7754 slot big enough for a SImode. If foo is some other sort of
7755 memory reference, then it is impossible to reload this case,
7756 so previous passes had better make sure this never happens.
7758 Then consider a one-word union which has SImode and one of its
7759 members is a float, being fetched as (SUBREG:SF union:SI).
7760 We must fetch that as SFmode because we could be loading into
7761 a float-only register. In this case OLD's mode is correct.
7763 Consider an immediate integer: it has VOIDmode. Here we need
7764 to get a mode from something else.
7766 In some cases, there is a fourth mode, the operand's
7767 containing mode. If the insn specifies a containing mode for
7768 this operand, it overrides all others.
7770 I am not sure whether the algorithm here is always right,
7771 but it does the right things in those cases. */
7773 mode = GET_MODE (old);
7774 if (mode == VOIDmode)
7777 /* We cannot use gen_lowpart_common since it can do the wrong thing
7778 when REG_RTX has a multi-word mode. Note that REG_RTX must
7779 always be a REG here. */
7780 if (GET_MODE (reg_rtx) != mode)
7781 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7783 reload_reg_rtx_for_input[j] = reg_rtx;
7786 /* AUTO_INC reloads need to be handled even if inherited. We got an
7787 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7788 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7789 && ! rtx_equal_p (reg_rtx, old)
7791 emit_input_reload_insns (chain, rld + j, old, j);
7793 /* When inheriting a wider reload, we have a MEM in rl->in,
7794 e.g. inheriting a SImode output reload for
7795 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7796 if (optimize && reload_inherited[j] && rl->in
7798 && MEM_P (rl->in_reg)
7799 && reload_spill_index[j] >= 0
7800 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7801 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7803 /* If we are reloading a register that was recently stored in with an
7804 output-reload, see if we can prove there was
7805 actually no need to store the old value in it. */
7808 && (reload_inherited[j] || reload_override_in[j])
7811 && spill_reg_store[REGNO (reg_rtx)] != 0
7813 /* There doesn't seem to be any reason to restrict this to pseudos
7814 and doing so loses in the case where we are copying from a
7815 register of the wrong class. */
7816 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7818 /* The insn might have already some references to stackslots
7819 replaced by MEMs, while reload_out_reg still names the
7821 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7822 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7823 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7826 /* Do output reloading for reload RL, which is for the insn described by
7827 CHAIN and has the number J.
7828 ??? At some point we need to support handling output reloads of
7829 JUMP_INSNs or insns that set cc0. */
7831 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7834 rtx insn = chain->insn;
7835 /* If this is an output reload that stores something that is
7836 not loaded in this same reload, see if we can eliminate a previous
7838 rtx pseudo = rl->out_reg;
7839 rtx reg_rtx = rl->reg_rtx;
7841 if (rl->out && reg_rtx)
7843 enum machine_mode mode;
7845 /* Determine the mode to reload in.
7846 See comments above (for input reloading). */
7847 mode = GET_MODE (rl->out);
7848 if (mode == VOIDmode)
7850 /* VOIDmode should never happen for an output. */
7851 if (asm_noperands (PATTERN (insn)) < 0)
7852 /* It's the compiler's fault. */
7853 fatal_insn ("VOIDmode on an output", insn);
7854 error_for_asm (insn, "output operand is constant in %<asm%>");
7855 /* Prevent crash--use something we know is valid. */
7857 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7859 if (GET_MODE (reg_rtx) != mode)
7860 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7862 reload_reg_rtx_for_output[j] = reg_rtx;
7867 && ! rtx_equal_p (rl->in_reg, pseudo)
7868 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7869 && reg_last_reload_reg[REGNO (pseudo)])
7871 int pseudo_no = REGNO (pseudo);
7872 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7874 /* We don't need to test full validity of last_regno for
7875 inherit here; we only want to know if the store actually
7876 matches the pseudo. */
7877 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7878 && reg_reloaded_contents[last_regno] == pseudo_no
7879 && spill_reg_store[last_regno]
7880 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7881 delete_output_reload (insn, j, last_regno, reg_rtx);
7887 || rtx_equal_p (old, reg_rtx))
7890 /* An output operand that dies right away does need a reload,
7891 but need not be copied from it. Show the new location in the
7893 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7894 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7896 XEXP (note, 0) = reg_rtx;
7899 /* Likewise for a SUBREG of an operand that dies. */
7900 else if (GET_CODE (old) == SUBREG
7901 && REG_P (SUBREG_REG (old))
7902 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7905 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7908 else if (GET_CODE (old) == SCRATCH)
7909 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7910 but we don't want to make an output reload. */
7913 /* If is a JUMP_INSN, we can't support output reloads yet. */
7914 gcc_assert (NONJUMP_INSN_P (insn));
7916 emit_output_reload_insns (chain, rld + j, j);
7919 /* A reload copies values of MODE from register SRC to register DEST.
7920 Return true if it can be treated for inheritance purposes like a
7921 group of reloads, each one reloading a single hard register. The
7922 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7923 occupy the same number of hard registers. */
7926 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
7927 int src ATTRIBUTE_UNUSED,
7928 enum machine_mode mode ATTRIBUTE_UNUSED)
7930 #ifdef CANNOT_CHANGE_MODE_CLASS
7931 return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
7932 && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
7938 /* Output insns to reload values in and out of the chosen reload regs. */
7941 emit_reload_insns (struct insn_chain *chain)
7943 rtx insn = chain->insn;
7947 CLEAR_HARD_REG_SET (reg_reloaded_died);
7949 for (j = 0; j < reload_n_operands; j++)
7950 input_reload_insns[j] = input_address_reload_insns[j]
7951 = inpaddr_address_reload_insns[j]
7952 = output_reload_insns[j] = output_address_reload_insns[j]
7953 = outaddr_address_reload_insns[j]
7954 = other_output_reload_insns[j] = 0;
7955 other_input_address_reload_insns = 0;
7956 other_input_reload_insns = 0;
7957 operand_reload_insns = 0;
7958 other_operand_reload_insns = 0;
7960 /* Dump reloads into the dump file. */
7963 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7964 debug_reload_to_stream (dump_file);
7967 /* Now output the instructions to copy the data into and out of the
7968 reload registers. Do these in the order that the reloads were reported,
7969 since reloads of base and index registers precede reloads of operands
7970 and the operands may need the base and index registers reloaded. */
7972 for (j = 0; j < n_reloads; j++)
7974 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
7978 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
7979 new_spill_reg_store[i] = 0;
7982 do_input_reload (chain, rld + j, j);
7983 do_output_reload (chain, rld + j, j);
7986 /* Now write all the insns we made for reloads in the order expected by
7987 the allocation functions. Prior to the insn being reloaded, we write
7988 the following reloads:
7990 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7992 RELOAD_OTHER reloads.
7994 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7995 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7996 RELOAD_FOR_INPUT reload for the operand.
7998 RELOAD_FOR_OPADDR_ADDRS reloads.
8000 RELOAD_FOR_OPERAND_ADDRESS reloads.
8002 After the insn being reloaded, we write the following:
8004 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8005 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8006 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8007 reloads for the operand. The RELOAD_OTHER output reloads are
8008 output in descending order by reload number. */
8010 emit_insn_before (other_input_address_reload_insns, insn);
8011 emit_insn_before (other_input_reload_insns, insn);
8013 for (j = 0; j < reload_n_operands; j++)
8015 emit_insn_before (inpaddr_address_reload_insns[j], insn);
8016 emit_insn_before (input_address_reload_insns[j], insn);
8017 emit_insn_before (input_reload_insns[j], insn);
8020 emit_insn_before (other_operand_reload_insns, insn);
8021 emit_insn_before (operand_reload_insns, insn);
8023 for (j = 0; j < reload_n_operands; j++)
8025 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
8026 x = emit_insn_after (output_address_reload_insns[j], x);
8027 x = emit_insn_after (output_reload_insns[j], x);
8028 emit_insn_after (other_output_reload_insns[j], x);
8031 /* For all the spill regs newly reloaded in this instruction,
8032 record what they were reloaded from, so subsequent instructions
8033 can inherit the reloads.
8035 Update spill_reg_store for the reloads of this insn.
8036 Copy the elements that were updated in the loop above. */
8038 for (j = 0; j < n_reloads; j++)
8040 int r = reload_order[j];
8041 int i = reload_spill_index[r];
8043 /* If this is a non-inherited input reload from a pseudo, we must
8044 clear any memory of a previous store to the same pseudo. Only do
8045 something if there will not be an output reload for the pseudo
8047 if (rld[r].in_reg != 0
8048 && ! (reload_inherited[r] || reload_override_in[r]))
8050 rtx reg = rld[r].in_reg;
8052 if (GET_CODE (reg) == SUBREG)
8053 reg = SUBREG_REG (reg);
8056 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
8057 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
8059 int nregno = REGNO (reg);
8061 if (reg_last_reload_reg[nregno])
8063 int last_regno = REGNO (reg_last_reload_reg[nregno]);
8065 if (reg_reloaded_contents[last_regno] == nregno)
8066 spill_reg_store[last_regno] = 0;
8071 /* I is nonneg if this reload used a register.
8072 If rld[r].reg_rtx is 0, this is an optional reload
8073 that we opted to ignore. */
8075 if (i >= 0 && rld[r].reg_rtx != 0)
8077 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
8080 /* For a multi register reload, we need to check if all or part
8081 of the value lives to the end. */
8082 for (k = 0; k < nr; k++)
8083 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
8084 rld[r].when_needed))
8085 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
8087 /* Maybe the spill reg contains a copy of reload_out. */
8089 && (REG_P (rld[r].out)
8091 ? REG_P (rld[r].out_reg)
8092 /* The reload value is an auto-modification of
8093 some kind. For PRE_INC, POST_INC, PRE_DEC
8094 and POST_DEC, we record an equivalence
8095 between the reload register and the operand
8096 on the optimistic assumption that we can make
8097 the equivalence hold. reload_as_needed must
8098 then either make it hold or invalidate the
8101 PRE_MODIFY and POST_MODIFY addresses are reloaded
8102 somewhat differently, and allowing them here leads
8104 : (GET_CODE (rld[r].out) != POST_MODIFY
8105 && GET_CODE (rld[r].out) != PRE_MODIFY))))
8108 enum machine_mode mode;
8111 reg = reload_reg_rtx_for_output[r];
8112 mode = GET_MODE (reg);
8113 regno = REGNO (reg);
8114 nregs = hard_regno_nregs[regno][mode];
8115 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
8116 rld[r].when_needed))
8118 rtx out = (REG_P (rld[r].out)
8122 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
8123 int out_regno = REGNO (out);
8124 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
8125 : hard_regno_nregs[out_regno][mode]);
8128 spill_reg_store[regno] = new_spill_reg_store[regno];
8129 spill_reg_stored_to[regno] = out;
8130 reg_last_reload_reg[out_regno] = reg;
8132 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
8133 && nregs == out_nregs
8134 && inherit_piecemeal_p (out_regno, regno, mode));
8136 /* If OUT_REGNO is a hard register, it may occupy more than
8137 one register. If it does, say what is in the
8138 rest of the registers assuming that both registers
8139 agree on how many words the object takes. If not,
8140 invalidate the subsequent registers. */
8142 if (HARD_REGISTER_NUM_P (out_regno))
8143 for (k = 1; k < out_nregs; k++)
8144 reg_last_reload_reg[out_regno + k]
8145 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8147 /* Now do the inverse operation. */
8148 for (k = 0; k < nregs; k++)
8150 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8151 reg_reloaded_contents[regno + k]
8152 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
8155 reg_reloaded_insn[regno + k] = insn;
8156 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8157 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8158 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8161 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8166 /* Maybe the spill reg contains a copy of reload_in. Only do
8167 something if there will not be an output reload for
8168 the register being reloaded. */
8169 else if (rld[r].out_reg == 0
8171 && ((REG_P (rld[r].in)
8172 && !HARD_REGISTER_P (rld[r].in)
8173 && !REGNO_REG_SET_P (®_has_output_reload,
8175 || (REG_P (rld[r].in_reg)
8176 && !REGNO_REG_SET_P (®_has_output_reload,
8177 REGNO (rld[r].in_reg))))
8178 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
8181 enum machine_mode mode;
8184 reg = reload_reg_rtx_for_input[r];
8185 mode = GET_MODE (reg);
8186 regno = REGNO (reg);
8187 nregs = hard_regno_nregs[regno][mode];
8188 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
8189 rld[r].when_needed))
8196 if (REG_P (rld[r].in)
8197 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
8199 else if (REG_P (rld[r].in_reg))
8202 in = XEXP (rld[r].in_reg, 0);
8203 in_regno = REGNO (in);
8205 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
8206 : hard_regno_nregs[in_regno][mode]);
8208 reg_last_reload_reg[in_regno] = reg;
8210 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
8211 && nregs == in_nregs
8212 && inherit_piecemeal_p (regno, in_regno, mode));
8214 if (HARD_REGISTER_NUM_P (in_regno))
8215 for (k = 1; k < in_nregs; k++)
8216 reg_last_reload_reg[in_regno + k]
8217 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8219 /* Unless we inherited this reload, show we haven't
8220 recently done a store.
8221 Previous stores of inherited auto_inc expressions
8222 also have to be discarded. */
8223 if (! reload_inherited[r]
8224 || (rld[r].out && ! rld[r].out_reg))
8225 spill_reg_store[regno] = 0;
8227 for (k = 0; k < nregs; k++)
8229 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8230 reg_reloaded_contents[regno + k]
8231 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
8234 reg_reloaded_insn[regno + k] = insn;
8235 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8236 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8237 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8240 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8247 /* The following if-statement was #if 0'd in 1.34 (or before...).
8248 It's reenabled in 1.35 because supposedly nothing else
8249 deals with this problem. */
8251 /* If a register gets output-reloaded from a non-spill register,
8252 that invalidates any previous reloaded copy of it.
8253 But forget_old_reloads_1 won't get to see it, because
8254 it thinks only about the original insn. So invalidate it here.
8255 Also do the same thing for RELOAD_OTHER constraints where the
8256 output is discarded. */
8258 && ((rld[r].out != 0
8259 && (REG_P (rld[r].out)
8260 || (MEM_P (rld[r].out)
8261 && REG_P (rld[r].out_reg))))
8262 || (rld[r].out == 0 && rld[r].out_reg
8263 && REG_P (rld[r].out_reg))))
8265 rtx out = ((rld[r].out && REG_P (rld[r].out))
8266 ? rld[r].out : rld[r].out_reg);
8267 int out_regno = REGNO (out);
8268 enum machine_mode mode = GET_MODE (out);
8270 /* REG_RTX is now set or clobbered by the main instruction.
8271 As the comment above explains, forget_old_reloads_1 only
8272 sees the original instruction, and there is no guarantee
8273 that the original instruction also clobbered REG_RTX.
8274 For example, if find_reloads sees that the input side of
8275 a matched operand pair dies in this instruction, it may
8276 use the input register as the reload register.
8278 Calling forget_old_reloads_1 is a waste of effort if
8279 REG_RTX is also the output register.
8281 If we know that REG_RTX holds the value of a pseudo
8282 register, the code after the call will record that fact. */
8283 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8284 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8286 if (!HARD_REGISTER_NUM_P (out_regno))
8288 rtx src_reg, store_insn = NULL_RTX;
8290 reg_last_reload_reg[out_regno] = 0;
8292 /* If we can find a hard register that is stored, record
8293 the storing insn so that we may delete this insn with
8294 delete_output_reload. */
8295 src_reg = reload_reg_rtx_for_output[r];
8297 /* If this is an optional reload, try to find the source reg
8298 from an input reload. */
8301 rtx set = single_set (insn);
8302 if (set && SET_DEST (set) == rld[r].out)
8306 src_reg = SET_SRC (set);
8308 for (k = 0; k < n_reloads; k++)
8310 if (rld[k].in == src_reg)
8312 src_reg = reload_reg_rtx_for_input[k];
8319 store_insn = new_spill_reg_store[REGNO (src_reg)];
8320 if (src_reg && REG_P (src_reg)
8321 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8323 int src_regno, src_nregs, k;
8326 gcc_assert (GET_MODE (src_reg) == mode);
8327 src_regno = REGNO (src_reg);
8328 src_nregs = hard_regno_nregs[src_regno][mode];
8329 /* The place where to find a death note varies with
8330 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8331 necessarily checked exactly in the code that moves
8332 notes, so just check both locations. */
8333 note = find_regno_note (insn, REG_DEAD, src_regno);
8334 if (! note && store_insn)
8335 note = find_regno_note (store_insn, REG_DEAD, src_regno);
8336 for (k = 0; k < src_nregs; k++)
8338 spill_reg_store[src_regno + k] = store_insn;
8339 spill_reg_stored_to[src_regno + k] = out;
8340 reg_reloaded_contents[src_regno + k] = out_regno;
8341 reg_reloaded_insn[src_regno + k] = store_insn;
8342 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8343 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8344 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
8346 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8349 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8351 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8353 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8355 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8357 reg_last_reload_reg[out_regno] = src_reg;
8358 /* We have to set reg_has_output_reload here, or else
8359 forget_old_reloads_1 will clear reg_last_reload_reg
8361 SET_REGNO_REG_SET (®_has_output_reload,
8367 int k, out_nregs = hard_regno_nregs[out_regno][mode];
8369 for (k = 0; k < out_nregs; k++)
8370 reg_last_reload_reg[out_regno + k] = 0;
8374 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8377 /* Go through the motions to emit INSN and test if it is strictly valid.
8378 Return the emitted insn if valid, else return NULL. */
8381 emit_insn_if_valid_for_reload (rtx insn)
8383 rtx last = get_last_insn ();
8386 insn = emit_insn (insn);
8387 code = recog_memoized (insn);
8391 extract_insn (insn);
8392 /* We want constrain operands to treat this insn strictly in its
8393 validity determination, i.e., the way it would after reload has
8395 if (constrain_operands (1))
8399 delete_insns_since (last);
8403 /* Emit code to perform a reload from IN (which may be a reload register) to
8404 OUT (which may also be a reload register). IN or OUT is from operand
8405 OPNUM with reload type TYPE.
8407 Returns first insn emitted. */
8410 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8412 rtx last = get_last_insn ();
8415 /* If IN is a paradoxical SUBREG, remove it and try to put the
8416 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8417 if (GET_CODE (in) == SUBREG
8418 && (GET_MODE_SIZE (GET_MODE (in))
8419 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
8420 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
8421 in = SUBREG_REG (in), out = tem;
8422 else if (GET_CODE (out) == SUBREG
8423 && (GET_MODE_SIZE (GET_MODE (out))
8424 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
8425 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
8426 out = SUBREG_REG (out), in = tem;
8428 /* How to do this reload can get quite tricky. Normally, we are being
8429 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8430 register that didn't get a hard register. In that case we can just
8431 call emit_move_insn.
8433 We can also be asked to reload a PLUS that adds a register or a MEM to
8434 another register, constant or MEM. This can occur during frame pointer
8435 elimination and while reloading addresses. This case is handled by
8436 trying to emit a single insn to perform the add. If it is not valid,
8437 we use a two insn sequence.
8439 Or we can be asked to reload an unary operand that was a fragment of
8440 an addressing mode, into a register. If it isn't recognized as-is,
8441 we try making the unop operand and the reload-register the same:
8442 (set reg:X (unop:X expr:Y))
8443 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8445 Finally, we could be called to handle an 'o' constraint by putting
8446 an address into a register. In that case, we first try to do this
8447 with a named pattern of "reload_load_address". If no such pattern
8448 exists, we just emit a SET insn and hope for the best (it will normally
8449 be valid on machines that use 'o').
8451 This entire process is made complex because reload will never
8452 process the insns we generate here and so we must ensure that
8453 they will fit their constraints and also by the fact that parts of
8454 IN might be being reloaded separately and replaced with spill registers.
8455 Because of this, we are, in some sense, just guessing the right approach
8456 here. The one listed above seems to work.
8458 ??? At some point, this whole thing needs to be rethought. */
8460 if (GET_CODE (in) == PLUS
8461 && (REG_P (XEXP (in, 0))
8462 || GET_CODE (XEXP (in, 0)) == SUBREG
8463 || MEM_P (XEXP (in, 0)))
8464 && (REG_P (XEXP (in, 1))
8465 || GET_CODE (XEXP (in, 1)) == SUBREG
8466 || CONSTANT_P (XEXP (in, 1))
8467 || MEM_P (XEXP (in, 1))))
8469 /* We need to compute the sum of a register or a MEM and another
8470 register, constant, or MEM, and put it into the reload
8471 register. The best possible way of doing this is if the machine
8472 has a three-operand ADD insn that accepts the required operands.
8474 The simplest approach is to try to generate such an insn and see if it
8475 is recognized and matches its constraints. If so, it can be used.
8477 It might be better not to actually emit the insn unless it is valid,
8478 but we need to pass the insn as an operand to `recog' and
8479 `extract_insn' and it is simpler to emit and then delete the insn if
8480 not valid than to dummy things up. */
8482 rtx op0, op1, tem, insn;
8485 op0 = find_replacement (&XEXP (in, 0));
8486 op1 = find_replacement (&XEXP (in, 1));
8488 /* Since constraint checking is strict, commutativity won't be
8489 checked, so we need to do that here to avoid spurious failure
8490 if the add instruction is two-address and the second operand
8491 of the add is the same as the reload reg, which is frequently
8492 the case. If the insn would be A = B + A, rearrange it so
8493 it will be A = A + B as constrain_operands expects. */
8495 if (REG_P (XEXP (in, 1))
8496 && REGNO (out) == REGNO (XEXP (in, 1)))
8497 tem = op0, op0 = op1, op1 = tem;
8499 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8500 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8502 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8506 /* If that failed, we must use a conservative two-insn sequence.
8508 Use a move to copy one operand into the reload register. Prefer
8509 to reload a constant, MEM or pseudo since the move patterns can
8510 handle an arbitrary operand. If OP1 is not a constant, MEM or
8511 pseudo and OP1 is not a valid operand for an add instruction, then
8514 After reloading one of the operands into the reload register, add
8515 the reload register to the output register.
8517 If there is another way to do this for a specific machine, a
8518 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8521 code = (int) optab_handler (add_optab, GET_MODE (out));
8523 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8525 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8526 || (code != CODE_FOR_nothing
8527 && ! ((*insn_data[code].operand[2].predicate)
8528 (op1, insn_data[code].operand[2].mode))))
8529 tem = op0, op0 = op1, op1 = tem;
8531 gen_reload (out, op0, opnum, type);
8533 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8534 This fixes a problem on the 32K where the stack pointer cannot
8535 be used as an operand of an add insn. */
8537 if (rtx_equal_p (op0, op1))
8540 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8543 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8544 set_unique_reg_note (insn, REG_EQUIV, in);
8548 /* If that failed, copy the address register to the reload register.
8549 Then add the constant to the reload register. */
8551 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8552 gen_reload (out, op1, opnum, type);
8553 insn = emit_insn (gen_add2_insn (out, op0));
8554 set_unique_reg_note (insn, REG_EQUIV, in);
8557 #ifdef SECONDARY_MEMORY_NEEDED
8558 /* If we need a memory location to do the move, do it that way. */
8559 else if ((REG_P (in)
8560 || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
8561 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
8563 || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
8564 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
8565 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
8566 REGNO_REG_CLASS (reg_or_subregno (out)),
8569 /* Get the memory to use and rewrite both registers to its mode. */
8570 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8572 if (GET_MODE (loc) != GET_MODE (out))
8573 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
8575 if (GET_MODE (loc) != GET_MODE (in))
8576 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
8578 gen_reload (loc, in, opnum, type);
8579 gen_reload (out, loc, opnum, type);
8582 else if (REG_P (out) && UNARY_P (in))
8589 op1 = find_replacement (&XEXP (in, 0));
8590 if (op1 != XEXP (in, 0))
8591 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8593 /* First, try a plain SET. */
8594 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8598 /* If that failed, move the inner operand to the reload
8599 register, and try the same unop with the inner expression
8600 replaced with the reload register. */
8602 if (GET_MODE (op1) != GET_MODE (out))
8603 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8607 gen_reload (out_moded, op1, opnum, type);
8610 = gen_rtx_SET (VOIDmode, out,
8611 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8613 insn = emit_insn_if_valid_for_reload (insn);
8616 set_unique_reg_note (insn, REG_EQUIV, in);
8620 fatal_insn ("failure trying to reload:", set);
8622 /* If IN is a simple operand, use gen_move_insn. */
8623 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8625 tem = emit_insn (gen_move_insn (out, in));
8626 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8627 mark_jump_label (in, tem, 0);
8630 #ifdef HAVE_reload_load_address
8631 else if (HAVE_reload_load_address)
8632 emit_insn (gen_reload_load_address (out, in));
8635 /* Otherwise, just write (set OUT IN) and hope for the best. */
8637 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8639 /* Return the first insn emitted.
8640 We can not just return get_last_insn, because there may have
8641 been multiple instructions emitted. Also note that gen_move_insn may
8642 emit more than one insn itself, so we can not assume that there is one
8643 insn emitted per emit_insn_before call. */
8645 return last ? NEXT_INSN (last) : get_insns ();
8648 /* Delete a previously made output-reload whose result we now believe
8649 is not needed. First we double-check.
8651 INSN is the insn now being processed.
8652 LAST_RELOAD_REG is the hard register number for which we want to delete
8653 the last output reload.
8654 J is the reload-number that originally used REG. The caller has made
8655 certain that reload J doesn't use REG any longer for input.
8656 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8659 delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg)
8661 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8662 rtx reg = spill_reg_stored_to[last_reload_reg];
8665 int n_inherited = 0;
8671 /* It is possible that this reload has been only used to set another reload
8672 we eliminated earlier and thus deleted this instruction too. */
8673 if (INSN_DELETED_P (output_reload_insn))
8676 /* Get the raw pseudo-register referred to. */
8678 while (GET_CODE (reg) == SUBREG)
8679 reg = SUBREG_REG (reg);
8680 substed = reg_equiv_memory_loc[REGNO (reg)];
8682 /* This is unsafe if the operand occurs more often in the current
8683 insn than it is inherited. */
8684 for (k = n_reloads - 1; k >= 0; k--)
8686 rtx reg2 = rld[k].in;
8689 if (MEM_P (reg2) || reload_override_in[k])
8690 reg2 = rld[k].in_reg;
8692 if (rld[k].out && ! rld[k].out_reg)
8693 reg2 = XEXP (rld[k].in_reg, 0);
8695 while (GET_CODE (reg2) == SUBREG)
8696 reg2 = SUBREG_REG (reg2);
8697 if (rtx_equal_p (reg2, reg))
8699 if (reload_inherited[k] || reload_override_in[k] || k == j)
8705 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8706 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8707 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8710 n_occurrences += count_occurrences (PATTERN (insn),
8711 eliminate_regs (substed, VOIDmode,
8713 for (i1 = reg_equiv_alt_mem_list[REGNO (reg)]; i1; i1 = XEXP (i1, 1))
8715 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8716 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8718 if (n_occurrences > n_inherited)
8721 regno = REGNO (reg);
8722 if (regno >= FIRST_PSEUDO_REGISTER)
8725 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
8727 /* If the pseudo-reg we are reloading is no longer referenced
8728 anywhere between the store into it and here,
8729 and we're within the same basic block, then the value can only
8730 pass through the reload reg and end up here.
8731 Otherwise, give up--return. */
8732 for (i1 = NEXT_INSN (output_reload_insn);
8733 i1 != insn; i1 = NEXT_INSN (i1))
8735 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8737 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8738 && refers_to_regno_p (regno, regno + nregs, PATTERN (i1), NULL))
8740 /* If this is USE in front of INSN, we only have to check that
8741 there are no more references than accounted for by inheritance. */
8742 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8744 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8745 i1 = NEXT_INSN (i1);
8747 if (n_occurrences <= n_inherited && i1 == insn)
8753 /* We will be deleting the insn. Remove the spill reg information. */
8754 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8756 spill_reg_store[last_reload_reg + k] = 0;
8757 spill_reg_stored_to[last_reload_reg + k] = 0;
8760 /* The caller has already checked that REG dies or is set in INSN.
8761 It has also checked that we are optimizing, and thus some
8762 inaccuracies in the debugging information are acceptable.
8763 So we could just delete output_reload_insn. But in some cases
8764 we can improve the debugging information without sacrificing
8765 optimization - maybe even improving the code: See if the pseudo
8766 reg has been completely replaced with reload regs. If so, delete
8767 the store insn and forget we had a stack slot for the pseudo. */
8768 if (rld[j].out != rld[j].in
8769 && REG_N_DEATHS (REGNO (reg)) == 1
8770 && REG_N_SETS (REGNO (reg)) == 1
8771 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8772 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8776 /* We know that it was used only between here and the beginning of
8777 the current basic block. (We also know that the last use before
8778 INSN was the output reload we are thinking of deleting, but never
8779 mind that.) Search that range; see if any ref remains. */
8780 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8782 rtx set = single_set (i2);
8784 /* Uses which just store in the pseudo don't count,
8785 since if they are the only uses, they are dead. */
8786 if (set != 0 && SET_DEST (set) == reg)
8791 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8792 && reg_mentioned_p (reg, PATTERN (i2)))
8794 /* Some other ref remains; just delete the output reload we
8796 delete_address_reloads (output_reload_insn, insn);
8797 delete_insn (output_reload_insn);
8802 /* Delete the now-dead stores into this pseudo. Note that this
8803 loop also takes care of deleting output_reload_insn. */
8804 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8806 rtx set = single_set (i2);
8808 if (set != 0 && SET_DEST (set) == reg)
8810 delete_address_reloads (i2, insn);
8818 /* For the debugging info, say the pseudo lives in this reload reg. */
8819 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8820 if (ira_conflicts_p)
8821 /* Inform IRA about the change. */
8822 ira_mark_allocation_change (REGNO (reg));
8823 alter_reg (REGNO (reg), -1, false);
8827 delete_address_reloads (output_reload_insn, insn);
8828 delete_insn (output_reload_insn);
8832 /* We are going to delete DEAD_INSN. Recursively delete loads of
8833 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8834 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8836 delete_address_reloads (rtx dead_insn, rtx current_insn)
8838 rtx set = single_set (dead_insn);
8839 rtx set2, dst, prev, next;
8842 rtx dst = SET_DEST (set);
8844 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8846 /* If we deleted the store from a reloaded post_{in,de}c expression,
8847 we can delete the matching adds. */
8848 prev = PREV_INSN (dead_insn);
8849 next = NEXT_INSN (dead_insn);
8850 if (! prev || ! next)
8852 set = single_set (next);
8853 set2 = single_set (prev);
8855 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8856 || !CONST_INT_P (XEXP (SET_SRC (set), 1))
8857 || !CONST_INT_P (XEXP (SET_SRC (set2), 1)))
8859 dst = SET_DEST (set);
8860 if (! rtx_equal_p (dst, SET_DEST (set2))
8861 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8862 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8863 || (INTVAL (XEXP (SET_SRC (set), 1))
8864 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8866 delete_related_insns (prev);
8867 delete_related_insns (next);
8870 /* Subfunction of delete_address_reloads: process registers found in X. */
8872 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8874 rtx prev, set, dst, i2;
8876 enum rtx_code code = GET_CODE (x);
8880 const char *fmt = GET_RTX_FORMAT (code);
8881 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8884 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8885 else if (fmt[i] == 'E')
8887 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8888 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8895 if (spill_reg_order[REGNO (x)] < 0)
8898 /* Scan backwards for the insn that sets x. This might be a way back due
8900 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8902 code = GET_CODE (prev);
8903 if (code == CODE_LABEL || code == JUMP_INSN)
8907 if (reg_set_p (x, PATTERN (prev)))
8909 if (reg_referenced_p (x, PATTERN (prev)))
8912 if (! prev || INSN_UID (prev) < reload_first_uid)
8914 /* Check that PREV only sets the reload register. */
8915 set = single_set (prev);
8918 dst = SET_DEST (set);
8920 || ! rtx_equal_p (dst, x))
8922 if (! reg_set_p (dst, PATTERN (dead_insn)))
8924 /* Check if DST was used in a later insn -
8925 it might have been inherited. */
8926 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8932 if (reg_referenced_p (dst, PATTERN (i2)))
8934 /* If there is a reference to the register in the current insn,
8935 it might be loaded in a non-inherited reload. If no other
8936 reload uses it, that means the register is set before
8938 if (i2 == current_insn)
8940 for (j = n_reloads - 1; j >= 0; j--)
8941 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8942 || reload_override_in[j] == dst)
8944 for (j = n_reloads - 1; j >= 0; j--)
8945 if (rld[j].in && rld[j].reg_rtx == dst)
8954 /* If DST is still live at CURRENT_INSN, check if it is used for
8955 any reload. Note that even if CURRENT_INSN sets DST, we still
8956 have to check the reloads. */
8957 if (i2 == current_insn)
8959 for (j = n_reloads - 1; j >= 0; j--)
8960 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8961 || reload_override_in[j] == dst)
8963 /* ??? We can't finish the loop here, because dst might be
8964 allocated to a pseudo in this block if no reload in this
8965 block needs any of the classes containing DST - see
8966 spill_hard_reg. There is no easy way to tell this, so we
8967 have to scan till the end of the basic block. */
8969 if (reg_set_p (dst, PATTERN (i2)))
8973 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8974 reg_reloaded_contents[REGNO (dst)] = -1;
8978 /* Output reload-insns to reload VALUE into RELOADREG.
8979 VALUE is an autoincrement or autodecrement RTX whose operand
8980 is a register or memory location;
8981 so reloading involves incrementing that location.
8982 IN is either identical to VALUE, or some cheaper place to reload from.
8984 INC_AMOUNT is the number to increment or decrement by (always positive).
8985 This cannot be deduced from VALUE. */
8988 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8990 /* REG or MEM to be copied and incremented. */
8991 rtx incloc = find_replacement (&XEXP (value, 0));
8992 /* Nonzero if increment after copying. */
8993 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8994 || GET_CODE (value) == POST_MODIFY);
8999 rtx real_in = in == value ? incloc : in;
9001 /* No hard register is equivalent to this register after
9002 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9003 we could inc/dec that register as well (maybe even using it for
9004 the source), but I'm not sure it's worth worrying about. */
9006 reg_last_reload_reg[REGNO (incloc)] = 0;
9008 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
9010 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
9011 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
9015 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
9016 inc_amount = -inc_amount;
9018 inc = GEN_INT (inc_amount);
9021 /* If this is post-increment, first copy the location to the reload reg. */
9022 if (post && real_in != reloadreg)
9023 emit_insn (gen_move_insn (reloadreg, real_in));
9027 /* See if we can directly increment INCLOC. Use a method similar to
9028 that in gen_reload. */
9030 last = get_last_insn ();
9031 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
9032 gen_rtx_PLUS (GET_MODE (incloc),
9035 code = recog_memoized (add_insn);
9038 extract_insn (add_insn);
9039 if (constrain_operands (1))
9041 /* If this is a pre-increment and we have incremented the value
9042 where it lives, copy the incremented value to RELOADREG to
9043 be used as an address. */
9046 emit_insn (gen_move_insn (reloadreg, incloc));
9050 delete_insns_since (last);
9053 /* If couldn't do the increment directly, must increment in RELOADREG.
9054 The way we do this depends on whether this is pre- or post-increment.
9055 For pre-increment, copy INCLOC to the reload register, increment it
9056 there, then save back. */
9060 if (in != reloadreg)
9061 emit_insn (gen_move_insn (reloadreg, real_in));
9062 emit_insn (gen_add2_insn (reloadreg, inc));
9063 emit_insn (gen_move_insn (incloc, reloadreg));
9068 Because this might be a jump insn or a compare, and because RELOADREG
9069 may not be available after the insn in an input reload, we must do
9070 the incrementation before the insn being reloaded for.
9072 We have already copied IN to RELOADREG. Increment the copy in
9073 RELOADREG, save that back, then decrement RELOADREG so it has
9074 the original value. */
9076 emit_insn (gen_add2_insn (reloadreg, inc));
9077 emit_insn (gen_move_insn (incloc, reloadreg));
9078 if (CONST_INT_P (inc))
9079 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
9081 emit_insn (gen_sub2_insn (reloadreg, inc));
9087 add_auto_inc_notes (rtx insn, rtx x)
9089 enum rtx_code code = GET_CODE (x);
9093 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9095 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
9099 /* Scan all the operand sub-expressions. */
9100 fmt = GET_RTX_FORMAT (code);
9101 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9104 add_auto_inc_notes (insn, XEXP (x, i));
9105 else if (fmt[i] == 'E')
9106 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9107 add_auto_inc_notes (insn, XVECEXP (x, i, j));
9112 /* This is used by reload pass, that does emit some instructions after
9113 abnormal calls moving basic block end, but in fact it wants to emit
9114 them on the edge. Looks for abnormal call edges, find backward the
9115 proper call and fix the damage.
9117 Similar handle instructions throwing exceptions internally. */
9119 fixup_abnormal_edges (void)
9121 bool inserted = false;
9129 /* Look for cases we are interested in - calls or instructions causing
9131 FOR_EACH_EDGE (e, ei, bb->succs)
9133 if (e->flags & EDGE_ABNORMAL_CALL)
9135 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
9136 == (EDGE_ABNORMAL | EDGE_EH))
9139 if (e && !CALL_P (BB_END (bb))
9140 && !can_throw_internal (BB_END (bb)))
9144 /* Get past the new insns generated. Allow notes, as the insns
9145 may be already deleted. */
9147 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
9148 && !can_throw_internal (insn)
9149 && insn != BB_HEAD (bb))
9150 insn = PREV_INSN (insn);
9152 if (CALL_P (insn) || can_throw_internal (insn))
9156 stop = NEXT_INSN (BB_END (bb));
9158 insn = NEXT_INSN (insn);
9160 e = find_fallthru_edge (bb->succs);
9162 while (insn && insn != stop)
9164 next = NEXT_INSN (insn);
9169 /* Sometimes there's still the return value USE.
9170 If it's placed after a trapping call (i.e. that
9171 call is the last insn anyway), we have no fallthru
9172 edge. Simply delete this use and don't try to insert
9173 on the non-existent edge. */
9174 if (GET_CODE (PATTERN (insn)) != USE)
9176 /* We're not deleting it, we're moving it. */
9177 INSN_DELETED_P (insn) = 0;
9178 PREV_INSN (insn) = NULL_RTX;
9179 NEXT_INSN (insn) = NULL_RTX;
9181 insert_insn_on_edge (insn, e);
9185 else if (!BARRIER_P (insn))
9186 set_block_for_insn (insn, NULL);
9191 /* It may be that we don't find any such trapping insn. In this
9192 case we discovered quite late that the insn that had been
9193 marked as can_throw_internal in fact couldn't trap at all.
9194 So we should in fact delete the EH edges out of the block. */
9196 purge_dead_edges (bb);
9200 /* We've possibly turned single trapping insn into multiple ones. */
9201 if (cfun->can_throw_non_call_exceptions)
9204 blocks = sbitmap_alloc (last_basic_block);
9205 sbitmap_ones (blocks);
9206 find_many_sub_basic_blocks (blocks);
9207 sbitmap_free (blocks);
9211 commit_edge_insertions ();
9213 #ifdef ENABLE_CHECKING
9214 /* Verify that we didn't turn one trapping insn into many, and that
9215 we found and corrected all of the problems wrt fixups on the
9217 verify_flow_info ();
OSDN Git Service
