1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
25 #include "insn-config.h"
26 #include "insn-flags.h"
27 #include "insn-codes.h"
31 #include "hard-reg-set.h"
34 #include "basic-block.h"
37 /* This file contains the reload pass of the compiler, which is
38 run after register allocation has been done. It checks that
39 each insn is valid (operands required to be in registers really
40 are in registers of the proper class) and fixes up invalid ones
41 by copying values temporarily into registers for the insns
44 The results of register allocation are described by the vector
45 reg_renumber; the insns still contain pseudo regs, but reg_renumber
46 can be used to find which hard reg, if any, a pseudo reg is in.
48 The technique we always use is to free up a few hard regs that are
49 called ``reload regs'', and for each place where a pseudo reg
50 must be in a hard reg, copy it temporarily into one of the reload regs.
52 All the pseudos that were formerly allocated to the hard regs that
53 are now in use as reload regs must be ``spilled''. This means
54 that they go to other hard regs, or to stack slots if no other
55 available hard regs can be found. Spilling can invalidate more
56 insns, requiring additional need for reloads, so we must keep checking
57 until the process stabilizes.
59 For machines with different classes of registers, we must keep track
60 of the register class needed for each reload, and make sure that
61 we allocate enough reload registers of each class.
63 The file reload.c contains the code that checks one insn for
64 validity and reports the reloads that it needs. This file
65 is in charge of scanning the entire rtl code, accumulating the
66 reload needs, spilling, assigning reload registers to use for
67 fixing up each insn, and generating the new insns to copy values
68 into the reload registers. */
70 /* During reload_as_needed, element N contains a REG rtx for the hard reg
71 into which pseudo reg N has been reloaded (perhaps for a previous insn). */
72 static rtx *reg_last_reload_reg;
74 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
75 for an output reload that stores into reg N. */
76 static char *reg_has_output_reload;
78 /* Indicates which hard regs are reload-registers for an output reload
79 in the current insn. */
80 static HARD_REG_SET reg_is_output_reload;
82 /* Element N is the constant value to which pseudo reg N is equivalent,
83 or zero if pseudo reg N is not equivalent to a constant.
84 find_reloads looks at this in order to replace pseudo reg N
85 with the constant it stands for. */
86 rtx *reg_equiv_constant;
88 /* Element N is a memory location to which pseudo reg N is equivalent,
89 prior to any register elimination (such as frame pointer to stack
90 pointer). Depending on whether or not it is a valid address, this value
91 is transferred to either reg_equiv_address or reg_equiv_mem. */
92 rtx *reg_equiv_memory_loc;
94 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
95 This is used when the address is not valid as a memory address
96 (because its displacement is too big for the machine.) */
97 rtx *reg_equiv_address;
99 /* Element N is the memory slot to which pseudo reg N is equivalent,
100 or zero if pseudo reg N is not equivalent to a memory slot. */
103 /* Widest width in which each pseudo reg is referred to (via subreg). */
104 static int *reg_max_ref_width;
106 /* Element N is the insn that initialized reg N from its equivalent
107 constant or memory slot. */
108 static rtx *reg_equiv_init;
110 /* During reload_as_needed, element N contains the last pseudo regno
111 reloaded into the Nth reload register. This vector is in parallel
112 with spill_regs. If that pseudo reg occupied more than one register,
113 reg_reloaded_contents points to that pseudo for each spill register in
114 use; all of these must remain set for an inheritance to occur. */
115 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
117 /* During reload_as_needed, element N contains the insn for which
118 the Nth reload register was last used. This vector is in parallel
119 with spill_regs, and its contents are significant only when
120 reg_reloaded_contents is significant. */
121 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
123 /* Number of spill-regs so far; number of valid elements of spill_regs. */
126 /* In parallel with spill_regs, contains REG rtx's for those regs.
127 Holds the last rtx used for any given reg, or 0 if it has never
128 been used for spilling yet. This rtx is reused, provided it has
130 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
132 /* In parallel with spill_regs, contains nonzero for a spill reg
133 that was stored after the last time it was used.
134 The precise value is the insn generated to do the store. */
135 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
137 /* This table is the inverse mapping of spill_regs:
138 indexed by hard reg number,
139 it contains the position of that reg in spill_regs,
140 or -1 for something that is not in spill_regs. */
141 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
143 /* This reg set indicates registers that may not be used for retrying global
144 allocation. The registers that may not be used include all spill registers
145 and the frame pointer (if we are using one). */
146 HARD_REG_SET forbidden_regs;
148 /* This reg set indicates registers that are not good for spill registers.
149 They will not be used to complete groups of spill registers. This includes
150 all fixed registers, registers that may be eliminated, and registers
151 explicitly used in the rtl.
153 (spill_reg_order prevents these registers from being used to start a
155 static HARD_REG_SET bad_spill_regs;
157 /* Describes order of use of registers for reloading
158 of spilled pseudo-registers. `spills' is the number of
159 elements that are actually valid; new ones are added at the end. */
160 static short spill_regs[FIRST_PSEUDO_REGISTER];
162 /* Describes order of preference for putting regs into spill_regs.
163 Contains the numbers of all the hard regs, in order most preferred first.
164 This order is different for each function.
165 It is set up by order_regs_for_reload.
166 Empty elements at the end contain -1. */
167 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
169 /* 1 for a hard register that appears explicitly in the rtl
170 (for example, function value registers, special registers
171 used by insns, structure value pointer registers). */
172 static char regs_explicitly_used[FIRST_PSEUDO_REGISTER];
174 /* Indicates if a register was counted against the need for
175 groups. 0 means it can count against max_nongroup instead. */
176 static HARD_REG_SET counted_for_groups;
178 /* Indicates if a register was counted against the need for
179 non-groups. 0 means it can become part of a new group.
180 During choose_reload_regs, 1 here means don't use this reg
181 as part of a group, even if it seems to be otherwise ok. */
182 static HARD_REG_SET counted_for_nongroups;
184 /* Nonzero if indirect addressing is supported on the machine; this means
185 that spilling (REG n) does not require reloading it into a register in
186 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
187 value indicates the level of indirect addressing supported, e.g., two
188 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
191 static char spill_indirect_levels;
193 /* Nonzero if indirect addressing is supported when the innermost MEM is
194 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
195 which these are valid is the same as spill_indirect_levels, above. */
197 char indirect_symref_ok;
199 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
201 char double_reg_address_ok;
203 /* Record the stack slot for each spilled hard register. */
205 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
207 /* Width allocated so far for that stack slot. */
209 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
211 /* Indexed by register class and basic block number, nonzero if there is
212 any need for a spill register of that class in that basic block.
213 The pointer is 0 if we did stupid allocation and don't know
214 the structure of basic blocks. */
216 char *basic_block_needs[N_REG_CLASSES];
218 /* First uid used by insns created by reload in this function.
219 Used in find_equiv_reg. */
220 int reload_first_uid;
222 /* Flag set by local-alloc or global-alloc if anything is live in
223 a call-clobbered reg across calls. */
225 int caller_save_needed;
227 /* Set to 1 while reload_as_needed is operating.
228 Required by some machines to handle any generated moves differently. */
230 int reload_in_progress = 0;
232 /* These arrays record the insn_code of insns that may be needed to
233 perform input and output reloads of special objects. They provide a
234 place to pass a scratch register. */
236 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
237 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
239 /* This obstack is used for allocation of rtl during register elimination.
240 The allocated storage can be freed once find_reloads has processed the
243 struct obstack reload_obstack;
244 char *reload_firstobj;
246 #define obstack_chunk_alloc xmalloc
247 #define obstack_chunk_free free
249 /* List of labels that must never be deleted. */
250 extern rtx forced_labels;
252 /* This structure is used to record information about register eliminations.
253 Each array entry describes one possible way of eliminating a register
254 in favor of another. If there is more than one way of eliminating a
255 particular register, the most preferred should be specified first. */
257 static struct elim_table
259 int from; /* Register number to be eliminated. */
260 int to; /* Register number used as replacement. */
261 int initial_offset; /* Initial difference between values. */
262 int can_eliminate; /* Non-zero if this elimination can be done. */
263 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
264 insns made by reload. */
265 int offset; /* Current offset between the two regs. */
266 int max_offset; /* Maximum offset between the two regs. */
267 int previous_offset; /* Offset at end of previous insn. */
268 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
269 rtx from_rtx; /* REG rtx for the register to be eliminated.
270 We cannot simply compare the number since
271 we might then spuriously replace a hard
272 register corresponding to a pseudo
273 assigned to the reg to be eliminated. */
274 rtx to_rtx; /* REG rtx for the replacement. */
277 /* If a set of eliminable registers was specified, define the table from it.
278 Otherwise, default to the normal case of the frame pointer being
279 replaced by the stack pointer. */
281 #ifdef ELIMINABLE_REGS
284 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
287 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0])
289 /* Record the number of pending eliminations that have an offset not equal
290 to their initial offset. If non-zero, we use a new copy of each
291 replacement result in any insns encountered. */
292 static int num_not_at_initial_offset;
294 /* Count the number of registers that we may be able to eliminate. */
295 static int num_eliminable;
297 /* For each label, we record the offset of each elimination. If we reach
298 a label by more than one path and an offset differs, we cannot do the
299 elimination. This information is indexed by the number of the label.
300 The first table is an array of flags that records whether we have yet
301 encountered a label and the second table is an array of arrays, one
302 entry in the latter array for each elimination. */
304 static char *offsets_known_at;
305 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
307 /* Number of labels in the current function. */
309 static int num_labels;
311 void mark_home_live ();
312 static void count_possible_groups ();
313 static int possible_group_p ();
314 static void scan_paradoxical_subregs ();
315 static void reload_as_needed ();
316 static int modes_equiv_for_class_p ();
317 static void alter_reg ();
318 static void delete_dead_insn ();
319 static void spill_failure ();
320 static int new_spill_reg();
321 static void set_label_offsets ();
322 static int eliminate_regs_in_insn ();
323 static void mark_not_eliminable ();
324 static int spill_hard_reg ();
325 static void choose_reload_regs ();
326 static void emit_reload_insns ();
327 static void delete_output_reload ();
328 static void forget_old_reloads_1 ();
329 static void order_regs_for_reload ();
330 static rtx inc_for_reload ();
331 static int constraint_accepts_reg_p ();
332 static int count_occurrences ();
334 extern void remove_death ();
335 extern rtx adj_offsettable_operand ();
336 extern rtx form_sum ();
343 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
344 Set spill_indirect_levels to the number of levels such addressing is
345 permitted, zero if it is not permitted at all. */
348 = gen_rtx (MEM, Pmode,
349 gen_rtx (PLUS, Pmode,
350 gen_rtx (REG, Pmode, LAST_VIRTUAL_REGISTER + 1),
352 spill_indirect_levels = 0;
354 while (memory_address_p (QImode, tem))
356 spill_indirect_levels++;
357 tem = gen_rtx (MEM, Pmode, tem);
360 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
362 tem = gen_rtx (MEM, Pmode, gen_rtx (SYMBOL_REF, Pmode, "foo"));
363 indirect_symref_ok = memory_address_p (QImode, tem);
365 /* See if reg+reg is a valid (and offsettable) address. */
367 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
369 tem = gen_rtx (PLUS, Pmode,
370 gen_rtx (REG, Pmode, FRAME_POINTER_REGNUM),
371 gen_rtx (REG, Pmode, i));
372 /* This way, we make sure that reg+reg is an offsettable address. */
373 tem = plus_constant (tem, 4);
375 if (memory_address_p (QImode, tem))
377 double_reg_address_ok = 1;
382 /* Initialize obstack for our rtl allocation. */
383 gcc_obstack_init (&reload_obstack);
384 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
386 #ifdef HAVE_SECONDARY_RELOADS
388 /* Initialize the optabs for doing special input and output reloads. */
390 for (i = 0; i < NUM_MACHINE_MODES; i++)
391 reload_in_optab[i] = reload_out_optab[i] = CODE_FOR_nothing;
393 #ifdef HAVE_reload_inqi
394 if (HAVE_reload_inqi)
395 reload_in_optab[(int) QImode] = CODE_FOR_reload_inqi;
397 #ifdef HAVE_reload_inhi
398 if (HAVE_reload_inhi)
399 reload_in_optab[(int) HImode] = CODE_FOR_reload_inhi;
401 #ifdef HAVE_reload_insi
402 if (HAVE_reload_insi)
403 reload_in_optab[(int) SImode] = CODE_FOR_reload_insi;
405 #ifdef HAVE_reload_indi
406 if (HAVE_reload_indi)
407 reload_in_optab[(int) DImode] = CODE_FOR_reload_indi;
409 #ifdef HAVE_reload_inti
410 if (HAVE_reload_inti)
411 reload_in_optab[(int) TImode] = CODE_FOR_reload_inti;
413 #ifdef HAVE_reload_inqf
414 if (HAVE_reload_inqf)
415 reload_in_optab[(int) QFmode] = CODE_FOR_reload_inqf;
417 #ifdef HAVE_reload_inhf
418 if (HAVE_reload_inhf)
419 reload_in_optab[(int) HFmode] = CODE_FOR_reload_inhf;
421 #ifdef HAVE_reload_insf
422 if (HAVE_reload_insf)
423 reload_in_optab[(int) SFmode] = CODE_FOR_reload_insf;
425 #ifdef HAVE_reload_indf
426 if (HAVE_reload_indf)
427 reload_in_optab[(int) DFmode] = CODE_FOR_reload_indf;
429 #ifdef HAVE_reload_inxf
430 if (HAVE_reload_inxf)
431 reload_in_optab[(int) XFmode] = CODE_FOR_reload_inxf;
433 #ifdef HAVE_reload_intf
434 if (HAVE_reload_intf)
435 reload_in_optab[(int) TFmode] = CODE_FOR_reload_intf;
438 #ifdef HAVE_reload_outqi
439 if (HAVE_reload_outqi)
440 reload_out_optab[(int) QImode] = CODE_FOR_reload_outqi;
442 #ifdef HAVE_reload_outhi
443 if (HAVE_reload_outhi)
444 reload_out_optab[(int) HImode] = CODE_FOR_reload_outhi;
446 #ifdef HAVE_reload_outsi
447 if (HAVE_reload_outsi)
448 reload_out_optab[(int) SImode] = CODE_FOR_reload_outsi;
450 #ifdef HAVE_reload_outdi
451 if (HAVE_reload_outdi)
452 reload_out_optab[(int) DImode] = CODE_FOR_reload_outdi;
454 #ifdef HAVE_reload_outti
455 if (HAVE_reload_outti)
456 reload_out_optab[(int) TImode] = CODE_FOR_reload_outti;
458 #ifdef HAVE_reload_outqf
459 if (HAVE_reload_outqf)
460 reload_out_optab[(int) QFmode] = CODE_FOR_reload_outqf;
462 #ifdef HAVE_reload_outhf
463 if (HAVE_reload_outhf)
464 reload_out_optab[(int) HFmode] = CODE_FOR_reload_outhf;
466 #ifdef HAVE_reload_outsf
467 if (HAVE_reload_outsf)
468 reload_out_optab[(int) SFmode] = CODE_FOR_reload_outsf;
470 #ifdef HAVE_reload_outdf
471 if (HAVE_reload_outdf)
472 reload_out_optab[(int) DFmode] = CODE_FOR_reload_outdf;
474 #ifdef HAVE_reload_outxf
475 if (HAVE_reload_outxf)
476 reload_out_optab[(int) XFmode] = CODE_FOR_reload_outxf;
478 #ifdef HAVE_reload_outtf
479 if (HAVE_reload_outtf)
480 reload_out_optab[(int) TFmode] = CODE_FOR_reload_outtf;
483 #endif /* HAVE_SECONDARY_RELOADS */
487 /* Main entry point for the reload pass, and only entry point
490 FIRST is the first insn of the function being compiled.
492 GLOBAL nonzero means we were called from global_alloc
493 and should attempt to reallocate any pseudoregs that we
494 displace from hard regs we will use for reloads.
495 If GLOBAL is zero, we do not have enough information to do that,
496 so any pseudo reg that is spilled must go to the stack.
498 DUMPFILE is the global-reg debugging dump file stream, or 0.
499 If it is nonzero, messages are written to it to describe
500 which registers are seized as reload regs, which pseudo regs
501 are spilled from them, and where the pseudo regs are reallocated to.
503 Return value is nonzero if reload failed
504 and we must not do any more for this function. */
507 reload (first, global, dumpfile)
515 register struct elim_table *ep;
517 int something_changed;
518 int something_needs_reloads;
519 int something_needs_elimination;
520 int new_basic_block_needs;
521 enum reg_class caller_save_spill_class = NO_REGS;
522 int caller_save_group_size = 1;
524 /* Nonzero means we couldn't get enough spill regs. */
527 /* The basic block number currently being processed for INSN. */
530 /* Make sure even insns with volatile mem refs are recognizable. */
533 /* Enable find_equiv_reg to distinguish insns made by reload. */
534 reload_first_uid = get_max_uid ();
536 for (i = 0; i < N_REG_CLASSES; i++)
537 basic_block_needs[i] = 0;
539 #ifdef SECONDARY_MEMORY_NEEDED
540 /* Initialize the secondary memory table. */
541 clear_secondary_mem ();
544 /* Remember which hard regs appear explicitly
545 before we merge into `regs_ever_live' the ones in which
546 pseudo regs have been allocated. */
547 bcopy (regs_ever_live, regs_explicitly_used, sizeof regs_ever_live);
549 /* We don't have a stack slot for any spill reg yet. */
550 bzero (spill_stack_slot, sizeof spill_stack_slot);
551 bzero (spill_stack_slot_width, sizeof spill_stack_slot_width);
553 /* Initialize the save area information for caller-save, in case some
557 /* Compute which hard registers are now in use
558 as homes for pseudo registers.
559 This is done here rather than (eg) in global_alloc
560 because this point is reached even if not optimizing. */
562 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
565 /* Make sure that the last insn in the chain
566 is not something that needs reloading. */
567 emit_note (NULL_PTR, NOTE_INSN_DELETED);
569 /* Find all the pseudo registers that didn't get hard regs
570 but do have known equivalent constants or memory slots.
571 These include parameters (known equivalent to parameter slots)
572 and cse'd or loop-moved constant memory addresses.
574 Record constant equivalents in reg_equiv_constant
575 so they will be substituted by find_reloads.
576 Record memory equivalents in reg_mem_equiv so they can
577 be substituted eventually by altering the REG-rtx's. */
579 reg_equiv_constant = (rtx *) alloca (max_regno * sizeof (rtx));
580 bzero (reg_equiv_constant, max_regno * sizeof (rtx));
581 reg_equiv_memory_loc = (rtx *) alloca (max_regno * sizeof (rtx));
582 bzero (reg_equiv_memory_loc, max_regno * sizeof (rtx));
583 reg_equiv_mem = (rtx *) alloca (max_regno * sizeof (rtx));
584 bzero (reg_equiv_mem, max_regno * sizeof (rtx));
585 reg_equiv_init = (rtx *) alloca (max_regno * sizeof (rtx));
586 bzero (reg_equiv_init, max_regno * sizeof (rtx));
587 reg_equiv_address = (rtx *) alloca (max_regno * sizeof (rtx));
588 bzero (reg_equiv_address, max_regno * sizeof (rtx));
589 reg_max_ref_width = (int *) alloca (max_regno * sizeof (int));
590 bzero (reg_max_ref_width, max_regno * sizeof (int));
592 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
593 Also find all paradoxical subregs
594 and find largest such for each pseudo. */
596 for (insn = first; insn; insn = NEXT_INSN (insn))
598 rtx set = single_set (insn);
600 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
602 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
604 #ifdef LEGITIMATE_PIC_OPERAND_P
605 && (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic
606 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
610 rtx x = XEXP (note, 0);
611 i = REGNO (SET_DEST (set));
612 if (i > LAST_VIRTUAL_REGISTER)
614 if (GET_CODE (x) == MEM)
615 reg_equiv_memory_loc[i] = x;
616 else if (CONSTANT_P (x))
618 if (LEGITIMATE_CONSTANT_P (x))
619 reg_equiv_constant[i] = x;
621 reg_equiv_memory_loc[i]
622 = force_const_mem (GET_MODE (SET_DEST (set)), x);
627 /* If this register is being made equivalent to a MEM
628 and the MEM is not SET_SRC, the equivalencing insn
629 is one with the MEM as a SET_DEST and it occurs later.
630 So don't mark this insn now. */
631 if (GET_CODE (x) != MEM
632 || rtx_equal_p (SET_SRC (set), x))
633 reg_equiv_init[i] = insn;
638 /* If this insn is setting a MEM from a register equivalent to it,
639 this is the equivalencing insn. */
640 else if (set && GET_CODE (SET_DEST (set)) == MEM
641 && GET_CODE (SET_SRC (set)) == REG
642 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
643 && rtx_equal_p (SET_DEST (set),
644 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
645 reg_equiv_init[REGNO (SET_SRC (set))] = insn;
647 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
648 scan_paradoxical_subregs (PATTERN (insn));
651 /* Does this function require a frame pointer? */
653 frame_pointer_needed = (! flag_omit_frame_pointer
654 #ifdef EXIT_IGNORE_STACK
655 /* ?? If EXIT_IGNORE_STACK is set, we will not save
656 and restore sp for alloca. So we can't eliminate
657 the frame pointer in that case. At some point,
658 we should improve this by emitting the
659 sp-adjusting insns for this case. */
660 || (current_function_calls_alloca
661 && EXIT_IGNORE_STACK)
663 || FRAME_POINTER_REQUIRED);
667 /* Initialize the table of registers to eliminate. The way we do this
668 depends on how the eliminable registers were defined. */
669 #ifdef ELIMINABLE_REGS
670 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
672 ep->can_eliminate = ep->can_eliminate_previous
673 = (CAN_ELIMINATE (ep->from, ep->to)
674 && (ep->from != FRAME_POINTER_REGNUM || ! frame_pointer_needed));
677 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
678 = ! frame_pointer_needed;
681 /* Count the number of eliminable registers and build the FROM and TO
682 REG rtx's. Note that code in gen_rtx will cause, e.g.,
683 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
684 We depend on this. */
685 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
687 num_eliminable += ep->can_eliminate;
688 ep->from_rtx = gen_rtx (REG, Pmode, ep->from);
689 ep->to_rtx = gen_rtx (REG, Pmode, ep->to);
692 num_labels = max_label_num () - get_first_label_num ();
694 /* Allocate the tables used to store offset information at labels. */
695 offsets_known_at = (char *) alloca (num_labels);
697 = (int (*)[NUM_ELIMINABLE_REGS])
698 alloca (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
700 offsets_known_at -= get_first_label_num ();
701 offsets_at -= get_first_label_num ();
703 /* Alter each pseudo-reg rtx to contain its hard reg number.
704 Assign stack slots to the pseudos that lack hard regs or equivalents.
705 Do not touch virtual registers. */
707 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
710 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done here
711 because the stack size may be a part of the offset computation for
712 register elimination. */
713 assign_stack_local (BLKmode, 0, 0);
715 /* If we have some registers we think can be eliminated, scan all insns to
716 see if there is an insn that sets one of these registers to something
717 other than itself plus a constant. If so, the register cannot be
718 eliminated. Doing this scan here eliminates an extra pass through the
719 main reload loop in the most common case where register elimination
721 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
722 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
723 || GET_CODE (insn) == CALL_INSN)
724 note_stores (PATTERN (insn), mark_not_eliminable);
726 #ifndef REGISTER_CONSTRAINTS
727 /* If all the pseudo regs have hard regs,
728 except for those that are never referenced,
729 we know that no reloads are needed. */
730 /* But that is not true if there are register constraints, since
731 in that case some pseudos might be in the wrong kind of hard reg. */
733 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
734 if (reg_renumber[i] == -1 && reg_n_refs[i] != 0)
737 if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
741 /* Compute the order of preference for hard registers to spill.
742 Store them by decreasing preference in potential_reload_regs. */
744 order_regs_for_reload ();
746 /* So far, no hard regs have been spilled. */
748 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
749 spill_reg_order[i] = -1;
751 /* On most machines, we can't use any register explicitly used in the
752 rtl as a spill register. But on some, we have to. Those will have
753 taken care to keep the life of hard regs as short as possible. */
755 #ifdef SMALL_REGISTER_CLASSES
756 CLEAR_HARD_REG_SET (forbidden_regs);
758 COPY_HARD_REG_SET (forbidden_regs, bad_spill_regs);
761 /* Spill any hard regs that we know we can't eliminate. */
762 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
763 if (! ep->can_eliminate)
765 spill_hard_reg (ep->from, global, dumpfile, 1);
766 regs_ever_live[ep->from] = 1;
770 for (i = 0; i < N_REG_CLASSES; i++)
772 basic_block_needs[i] = (char *)alloca (n_basic_blocks);
773 bzero (basic_block_needs[i], n_basic_blocks);
776 /* From now on, we need to emit any moves without making new pseudos. */
777 reload_in_progress = 1;
779 /* This loop scans the entire function each go-round
780 and repeats until one repetition spills no additional hard regs. */
782 /* This flag is set when a pseudo reg is spilled,
783 to require another pass. Note that getting an additional reload
784 reg does not necessarily imply any pseudo reg was spilled;
785 sometimes we find a reload reg that no pseudo reg was allocated in. */
786 something_changed = 1;
787 /* This flag is set if there are any insns that require reloading. */
788 something_needs_reloads = 0;
789 /* This flag is set if there are any insns that require register
791 something_needs_elimination = 0;
792 while (something_changed)
796 /* For each class, number of reload regs needed in that class.
797 This is the maximum over all insns of the needs in that class
798 of the individual insn. */
799 int max_needs[N_REG_CLASSES];
800 /* For each class, size of group of consecutive regs
801 that is needed for the reloads of this class. */
802 int group_size[N_REG_CLASSES];
803 /* For each class, max number of consecutive groups needed.
804 (Each group contains group_size[CLASS] consecutive registers.) */
805 int max_groups[N_REG_CLASSES];
806 /* For each class, max number needed of regs that don't belong
807 to any of the groups. */
808 int max_nongroups[N_REG_CLASSES];
809 /* For each class, the machine mode which requires consecutive
810 groups of regs of that class.
811 If two different modes ever require groups of one class,
812 they must be the same size and equally restrictive for that class,
813 otherwise we can't handle the complexity. */
814 enum machine_mode group_mode[N_REG_CLASSES];
815 /* Record the insn where each maximum need is first found. */
816 rtx max_needs_insn[N_REG_CLASSES];
817 rtx max_groups_insn[N_REG_CLASSES];
818 rtx max_nongroups_insn[N_REG_CLASSES];
820 int starting_frame_size = get_frame_size ();
821 static char *reg_class_names[] = REG_CLASS_NAMES;
823 something_changed = 0;
824 bzero (max_needs, sizeof max_needs);
825 bzero (max_groups, sizeof max_groups);
826 bzero (max_nongroups, sizeof max_nongroups);
827 bzero (max_needs_insn, sizeof max_needs_insn);
828 bzero (max_groups_insn, sizeof max_groups_insn);
829 bzero (max_nongroups_insn, sizeof max_nongroups_insn);
830 bzero (group_size, sizeof group_size);
831 for (i = 0; i < N_REG_CLASSES; i++)
832 group_mode[i] = VOIDmode;
834 /* Keep track of which basic blocks are needing the reloads. */
837 /* Remember whether any element of basic_block_needs
838 changes from 0 to 1 in this pass. */
839 new_basic_block_needs = 0;
841 /* Reset all offsets on eliminable registers to their initial values. */
842 #ifdef ELIMINABLE_REGS
843 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
845 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
846 ep->previous_offset = ep->offset
847 = ep->max_offset = ep->initial_offset;
850 #ifdef INITIAL_FRAME_POINTER_OFFSET
851 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
853 if (!FRAME_POINTER_REQUIRED)
855 reg_eliminate[0].initial_offset = 0;
857 reg_eliminate[0].previous_offset = reg_eliminate[0].max_offset
858 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
861 num_not_at_initial_offset = 0;
863 bzero (&offsets_known_at[get_first_label_num ()], num_labels);
865 /* Set a known offset for each forced label to be at the initial offset
866 of each elimination. We do this because we assume that all
867 computed jumps occur from a location where each elimination is
868 at its initial offset. */
870 for (x = forced_labels; x; x = XEXP (x, 1))
872 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
874 /* For each pseudo register that has an equivalent location defined,
875 try to eliminate any eliminable registers (such as the frame pointer)
876 assuming initial offsets for the replacement register, which
879 If the resulting location is directly addressable, substitute
880 the MEM we just got directly for the old REG.
882 If it is not addressable but is a constant or the sum of a hard reg
883 and constant, it is probably not addressable because the constant is
884 out of range, in that case record the address; we will generate
885 hairy code to compute the address in a register each time it is
888 If the location is not addressable, but does not have one of the
889 above forms, assign a stack slot. We have to do this to avoid the
890 potential of producing lots of reloads if, e.g., a location involves
891 a pseudo that didn't get a hard register and has an equivalent memory
892 location that also involves a pseudo that didn't get a hard register.
894 Perhaps at some point we will improve reload_when_needed handling
895 so this problem goes away. But that's very hairy. */
897 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
898 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
900 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
902 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
904 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
905 else if (CONSTANT_P (XEXP (x, 0))
906 || (GET_CODE (XEXP (x, 0)) == PLUS
907 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
908 && (REGNO (XEXP (XEXP (x, 0), 0))
909 < FIRST_PSEUDO_REGISTER)
910 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
911 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
914 /* Make a new stack slot. Then indicate that something
915 changed so we go back and recompute offsets for
916 eliminable registers because the allocation of memory
917 below might change some offset. reg_equiv_{mem,address}
918 will be set up for this pseudo on the next pass around
920 reg_equiv_memory_loc[i] = 0;
921 reg_equiv_init[i] = 0;
923 something_changed = 1;
927 /* If we allocated another pseudo to the stack, redo elimination
929 if (something_changed)
932 /* If caller-saves needs a group, initialize the group to include
933 the size and mode required for caller-saves. */
935 if (caller_save_group_size > 1)
937 group_mode[(int) caller_save_spill_class] = Pmode;
938 group_size[(int) caller_save_spill_class] = caller_save_group_size;
941 /* Compute the most additional registers needed by any instruction.
942 Collect information separately for each class of regs. */
944 for (insn = first; insn; insn = NEXT_INSN (insn))
946 if (global && this_block + 1 < n_basic_blocks
947 && insn == basic_block_head[this_block+1])
950 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which
951 might include REG_LABEL), we need to see what effects this
952 has on the known offsets at labels. */
954 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
955 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
956 && REG_NOTES (insn) != 0))
957 set_label_offsets (insn, insn, 0);
959 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
961 /* Nonzero means don't use a reload reg that overlaps
962 the place where a function value can be returned. */
963 rtx avoid_return_reg = 0;
965 rtx old_body = PATTERN (insn);
966 int old_code = INSN_CODE (insn);
967 rtx old_notes = REG_NOTES (insn);
968 int did_elimination = 0;
970 /* Initially, count RELOAD_OTHER reloads.
971 Later, merge in the other kinds. */
972 int insn_needs[N_REG_CLASSES];
973 int insn_groups[N_REG_CLASSES];
974 int insn_total_groups = 0;
976 /* Count RELOAD_FOR_INPUT_RELOAD_ADDRESS reloads. */
977 int insn_needs_for_inputs[N_REG_CLASSES];
978 int insn_groups_for_inputs[N_REG_CLASSES];
979 int insn_total_groups_for_inputs = 0;
981 /* Count RELOAD_FOR_OUTPUT_RELOAD_ADDRESS reloads. */
982 int insn_needs_for_outputs[N_REG_CLASSES];
983 int insn_groups_for_outputs[N_REG_CLASSES];
984 int insn_total_groups_for_outputs = 0;
986 /* Count RELOAD_FOR_OPERAND_ADDRESS reloads. */
987 int insn_needs_for_operands[N_REG_CLASSES];
988 int insn_groups_for_operands[N_REG_CLASSES];
989 int insn_total_groups_for_operands = 0;
991 #if 0 /* This wouldn't work nowadays, since optimize_bit_field
992 looks for non-strict memory addresses. */
993 /* Optimization: a bit-field instruction whose field
994 happens to be a byte or halfword in memory
995 can be changed to a move instruction. */
997 if (GET_CODE (PATTERN (insn)) == SET)
999 rtx dest = SET_DEST (PATTERN (insn));
1000 rtx src = SET_SRC (PATTERN (insn));
1002 if (GET_CODE (dest) == ZERO_EXTRACT
1003 || GET_CODE (dest) == SIGN_EXTRACT)
1004 optimize_bit_field (PATTERN (insn), insn, reg_equiv_mem);
1005 if (GET_CODE (src) == ZERO_EXTRACT
1006 || GET_CODE (src) == SIGN_EXTRACT)
1007 optimize_bit_field (PATTERN (insn), insn, reg_equiv_mem);
1011 /* If needed, eliminate any eliminable registers. */
1013 did_elimination = eliminate_regs_in_insn (insn, 0);
1015 #ifdef SMALL_REGISTER_CLASSES
1016 /* Set avoid_return_reg if this is an insn
1017 that might use the value of a function call. */
1018 if (GET_CODE (insn) == CALL_INSN)
1020 if (GET_CODE (PATTERN (insn)) == SET)
1021 after_call = SET_DEST (PATTERN (insn));
1022 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1023 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1024 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
1028 else if (after_call != 0
1029 && !(GET_CODE (PATTERN (insn)) == SET
1030 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
1032 if (reg_mentioned_p (after_call, PATTERN (insn)))
1033 avoid_return_reg = after_call;
1036 #endif /* SMALL_REGISTER_CLASSES */
1038 /* Analyze the instruction. */
1039 find_reloads (insn, 0, spill_indirect_levels, global,
1042 /* Remember for later shortcuts which insns had any reloads or
1043 register eliminations.
1045 One might think that it would be worthwhile to mark insns
1046 that need register replacements but not reloads, but this is
1047 not safe because find_reloads may do some manipulation of
1048 the insn (such as swapping commutative operands), which would
1049 be lost when we restore the old pattern after register
1050 replacement. So the actions of find_reloads must be redone in
1051 subsequent passes or in reload_as_needed.
1053 However, it is safe to mark insns that need reloads
1054 but not register replacement. */
1056 PUT_MODE (insn, (did_elimination ? QImode
1057 : n_reloads ? HImode
1060 /* Discard any register replacements done. */
1061 if (did_elimination)
1063 obstack_free (&reload_obstack, reload_firstobj);
1064 PATTERN (insn) = old_body;
1065 INSN_CODE (insn) = old_code;
1066 REG_NOTES (insn) = old_notes;
1067 something_needs_elimination = 1;
1070 /* If this insn has no reloads, we need not do anything except
1071 in the case of a CALL_INSN when we have caller-saves and
1072 caller-save needs reloads. */
1075 && ! (GET_CODE (insn) == CALL_INSN
1076 && caller_save_spill_class != NO_REGS))
1079 something_needs_reloads = 1;
1081 for (i = 0; i < N_REG_CLASSES; i++)
1083 insn_needs[i] = 0, insn_groups[i] = 0;
1084 insn_needs_for_inputs[i] = 0, insn_groups_for_inputs[i] = 0;
1085 insn_needs_for_outputs[i] = 0, insn_groups_for_outputs[i] = 0;
1086 insn_needs_for_operands[i] = 0, insn_groups_for_operands[i] = 0;
1089 /* Count each reload once in every class
1090 containing the reload's own class. */
1092 for (i = 0; i < n_reloads; i++)
1094 register enum reg_class *p;
1095 enum reg_class class = reload_reg_class[i];
1097 enum machine_mode mode;
1100 int *this_total_groups;
1102 /* Don't count the dummy reloads, for which one of the
1103 regs mentioned in the insn can be used for reloading.
1104 Don't count optional reloads.
1105 Don't count reloads that got combined with others. */
1106 if (reload_reg_rtx[i] != 0
1107 || reload_optional[i] != 0
1108 || (reload_out[i] == 0 && reload_in[i] == 0
1109 && ! reload_secondary_p[i]))
1112 /* Show that a reload register of this class is needed
1113 in this basic block. We do not use insn_needs and
1114 insn_groups because they are overly conservative for
1116 if (global && ! basic_block_needs[(int) class][this_block])
1118 basic_block_needs[(int) class][this_block] = 1;
1119 new_basic_block_needs = 1;
1122 /* Decide which time-of-use to count this reload for. */
1123 switch (reload_when_needed[i])
1126 case RELOAD_FOR_OUTPUT:
1127 case RELOAD_FOR_INPUT:
1128 this_needs = insn_needs;
1129 this_groups = insn_groups;
1130 this_total_groups = &insn_total_groups;
1133 case RELOAD_FOR_INPUT_RELOAD_ADDRESS:
1134 this_needs = insn_needs_for_inputs;
1135 this_groups = insn_groups_for_inputs;
1136 this_total_groups = &insn_total_groups_for_inputs;
1139 case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS:
1140 this_needs = insn_needs_for_outputs;
1141 this_groups = insn_groups_for_outputs;
1142 this_total_groups = &insn_total_groups_for_outputs;
1145 case RELOAD_FOR_OPERAND_ADDRESS:
1146 this_needs = insn_needs_for_operands;
1147 this_groups = insn_groups_for_operands;
1148 this_total_groups = &insn_total_groups_for_operands;
1152 mode = reload_inmode[i];
1153 if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1154 mode = reload_outmode[i];
1155 size = CLASS_MAX_NREGS (class, mode);
1158 enum machine_mode other_mode, allocate_mode;
1160 /* Count number of groups needed separately from
1161 number of individual regs needed. */
1162 this_groups[(int) class]++;
1163 p = reg_class_superclasses[(int) class];
1164 while (*p != LIM_REG_CLASSES)
1165 this_groups[(int) *p++]++;
1166 (*this_total_groups)++;
1168 /* Record size and mode of a group of this class. */
1169 /* If more than one size group is needed,
1170 make all groups the largest needed size. */
1171 if (group_size[(int) class] < size)
1173 other_mode = group_mode[(int) class];
1174 allocate_mode = mode;
1176 group_size[(int) class] = size;
1177 group_mode[(int) class] = mode;
1182 allocate_mode = group_mode[(int) class];
1185 /* Crash if two dissimilar machine modes both need
1186 groups of consecutive regs of the same class. */
1188 if (other_mode != VOIDmode
1189 && other_mode != allocate_mode
1190 && ! modes_equiv_for_class_p (allocate_mode,
1197 this_needs[(int) class] += 1;
1198 p = reg_class_superclasses[(int) class];
1199 while (*p != LIM_REG_CLASSES)
1200 this_needs[(int) *p++] += 1;
1206 /* All reloads have been counted for this insn;
1207 now merge the various times of use.
1208 This sets insn_needs, etc., to the maximum total number
1209 of registers needed at any point in this insn. */
1211 for (i = 0; i < N_REG_CLASSES; i++)
1214 this_max = insn_needs_for_inputs[i];
1215 if (insn_needs_for_outputs[i] > this_max)
1216 this_max = insn_needs_for_outputs[i];
1217 if (insn_needs_for_operands[i] > this_max)
1218 this_max = insn_needs_for_operands[i];
1219 insn_needs[i] += this_max;
1220 this_max = insn_groups_for_inputs[i];
1221 if (insn_groups_for_outputs[i] > this_max)
1222 this_max = insn_groups_for_outputs[i];
1223 if (insn_groups_for_operands[i] > this_max)
1224 this_max = insn_groups_for_operands[i];
1225 insn_groups[i] += this_max;
1228 insn_total_groups += MAX (insn_total_groups_for_inputs,
1229 MAX (insn_total_groups_for_outputs,
1230 insn_total_groups_for_operands));
1232 /* If this is a CALL_INSN and caller-saves will need
1233 a spill register, act as if the spill register is
1234 needed for this insn. However, the spill register
1235 can be used by any reload of this insn, so we only
1236 need do something if no need for that class has
1239 The assumption that every CALL_INSN will trigger a
1240 caller-save is highly conservative, however, the number
1241 of cases where caller-saves will need a spill register but
1242 a block containing a CALL_INSN won't need a spill register
1243 of that class should be quite rare.
1245 If a group is needed, the size and mode of the group will
1246 have been set up at the beginning of this loop. */
1248 if (GET_CODE (insn) == CALL_INSN
1249 && caller_save_spill_class != NO_REGS)
1251 int *caller_save_needs
1252 = (caller_save_group_size > 1 ? insn_groups : insn_needs);
1254 if (caller_save_needs[(int) caller_save_spill_class] == 0)
1256 register enum reg_class *p
1257 = reg_class_superclasses[(int) caller_save_spill_class];
1259 caller_save_needs[(int) caller_save_spill_class]++;
1261 while (*p != LIM_REG_CLASSES)
1262 caller_save_needs[(int) *p++] += 1;
1265 if (caller_save_group_size > 1)
1266 insn_total_groups = MAX (insn_total_groups, 1);
1269 /* Show that this basic block will need a register of
1273 && ! (basic_block_needs[(int) caller_save_spill_class]
1276 basic_block_needs[(int) caller_save_spill_class]
1278 new_basic_block_needs = 1;
1282 #ifdef SMALL_REGISTER_CLASSES
1283 /* If this insn stores the value of a function call,
1284 and that value is in a register that has been spilled,
1285 and if the insn needs a reload in a class
1286 that might use that register as the reload register,
1287 then add add an extra need in that class.
1288 This makes sure we have a register available that does
1289 not overlap the return value. */
1290 if (avoid_return_reg)
1292 int regno = REGNO (avoid_return_reg);
1294 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
1296 for (r = regno; r < regno + nregs; r++)
1297 if (spill_reg_order[r] >= 0)
1298 for (i = 0; i < N_REG_CLASSES; i++)
1299 if (TEST_HARD_REG_BIT (reg_class_contents[i], r))
1301 /* ??? It's not clear what is really
1302 right to do if this insn needs a group.
1303 But maybe that cannot happen. */
1304 if (insn_needs[i] > 0 || insn_groups[i] > 0)
1308 #endif /* SMALL_REGISTER_CLASSES */
1310 /* For each class, collect maximum need of any insn. */
1312 for (i = 0; i < N_REG_CLASSES; i++)
1314 if (max_needs[i] < insn_needs[i])
1316 max_needs[i] = insn_needs[i];
1317 max_needs_insn[i] = insn;
1319 if (max_groups[i] < insn_groups[i])
1321 max_groups[i] = insn_groups[i];
1322 max_groups_insn[i] = insn;
1324 if (insn_total_groups > 0)
1325 if (max_nongroups[i] < insn_needs[i])
1327 max_nongroups[i] = insn_needs[i];
1328 max_nongroups_insn[i] = insn;
1332 /* Note that there is a continue statement above. */
1335 /* If we allocated any new memory locations, make another pass
1336 since it might have changed elimination offsets. */
1337 if (starting_frame_size != get_frame_size ())
1338 something_changed = 1;
1341 for (i = 0; i < N_REG_CLASSES; i++)
1343 if (max_needs[i] > 0)
1345 ";; Need %d reg%s of class %s (for insn %d).\n",
1346 max_needs[i], max_needs[i] == 1 ? "" : "s",
1347 reg_class_names[i], INSN_UID (max_needs_insn[i]));
1348 if (max_nongroups[i] > 0)
1350 ";; Need %d nongroup reg%s of class %s (for insn %d).\n",
1351 max_nongroups[i], max_nongroups[i] == 1 ? "" : "s",
1352 reg_class_names[i], INSN_UID (max_nongroups_insn[i]));
1353 if (max_groups[i] > 0)
1355 ";; Need %d group%s (%smode) of class %s (for insn %d).\n",
1356 max_groups[i], max_groups[i] == 1 ? "" : "s",
1357 mode_name[(int) group_mode[i]],
1358 reg_class_names[i], INSN_UID (max_groups_insn[i]));
1361 /* If we have caller-saves, set up the save areas and see if caller-save
1362 will need a spill register. */
1364 if (caller_save_needed
1365 && ! setup_save_areas (&something_changed)
1366 && caller_save_spill_class == NO_REGS)
1368 /* The class we will need depends on whether the machine
1369 supports the sum of two registers for an address; see
1370 find_address_reloads for details. */
1372 caller_save_spill_class
1373 = double_reg_address_ok ? INDEX_REG_CLASS : BASE_REG_CLASS;
1374 caller_save_group_size
1375 = CLASS_MAX_NREGS (caller_save_spill_class, Pmode);
1376 something_changed = 1;
1379 /* Now deduct from the needs for the registers already
1380 available (already spilled). */
1382 CLEAR_HARD_REG_SET (counted_for_groups);
1383 CLEAR_HARD_REG_SET (counted_for_nongroups);
1385 /* First find all regs alone in their class
1386 and count them (if desired) for non-groups.
1387 We would be screwed if a group took the only reg in a class
1388 for which a non-group reload is needed.
1389 (Note there is still a bug; if a class has 2 regs,
1390 both could be stolen by groups and we would lose the same way.
1391 With luck, no machine will need a nongroup in a 2-reg class.) */
1393 for (i = 0; i < n_spills; i++)
1395 register enum reg_class *p;
1396 class = (int) REGNO_REG_CLASS (spill_regs[i]);
1398 if (reg_class_size[class] == 1 && max_nongroups[class] > 0)
1401 p = reg_class_superclasses[class];
1402 while (*p != LIM_REG_CLASSES)
1403 max_needs[(int) *p++]--;
1405 SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]);
1406 max_nongroups[class]--;
1407 p = reg_class_superclasses[class];
1408 while (*p != LIM_REG_CLASSES)
1410 if (max_nongroups[(int) *p] > 0)
1411 SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]);
1412 max_nongroups[(int) *p++]--;
1417 /* Now find all consecutive groups of spilled registers
1418 and mark each group off against the need for such groups.
1419 But don't count them against ordinary need, yet. */
1421 count_possible_groups (group_size, group_mode, max_groups);
1423 /* Now count all spill regs against the individual need,
1424 This includes those counted above for groups,
1425 but not those previously counted for nongroups.
1427 Those that weren't counted_for_groups can also count against
1428 the not-in-group need. */
1430 for (i = 0; i < n_spills; i++)
1432 register enum reg_class *p;
1433 class = (int) REGNO_REG_CLASS (spill_regs[i]);
1435 /* Those counted at the beginning shouldn't be counted twice. */
1436 if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
1439 p = reg_class_superclasses[class];
1440 while (*p != LIM_REG_CLASSES)
1441 max_needs[(int) *p++]--;
1443 if (! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[i]))
1445 if (max_nongroups[class] > 0)
1446 SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]);
1447 max_nongroups[class]--;
1448 p = reg_class_superclasses[class];
1449 while (*p != LIM_REG_CLASSES)
1451 if (max_nongroups[(int) *p] > 0)
1452 SET_HARD_REG_BIT (counted_for_nongroups,
1454 max_nongroups[(int) *p++]--;
1460 /* See if anything that happened changes which eliminations are valid.
1461 For example, on the Sparc, whether or not the frame pointer can
1462 be eliminated can depend on what registers have been used. We need
1463 not check some conditions again (such as flag_omit_frame_pointer)
1464 since they can't have changed. */
1466 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1467 if ((ep->from == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
1468 #ifdef ELIMINABLE_REGS
1469 || ! CAN_ELIMINATE (ep->from, ep->to)
1472 ep->can_eliminate = 0;
1474 /* Look for the case where we have discovered that we can't replace
1475 register A with register B and that means that we will now be
1476 trying to replace register A with register C. This means we can
1477 no longer replace register C with register B and we need to disable
1478 such an elimination, if it exists. This occurs often with A == ap,
1479 B == sp, and C == fp. */
1481 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1483 struct elim_table *op;
1484 register int new_to = -1;
1486 if (! ep->can_eliminate && ep->can_eliminate_previous)
1488 /* Find the current elimination for ep->from, if there is a
1490 for (op = reg_eliminate;
1491 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1492 if (op->from == ep->from && op->can_eliminate)
1498 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
1500 for (op = reg_eliminate;
1501 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1502 if (op->from == new_to && op->to == ep->to)
1503 op->can_eliminate = 0;
1507 /* See if any registers that we thought we could eliminate the previous
1508 time are no longer eliminable. If so, something has changed and we
1509 must spill the register. Also, recompute the number of eliminable
1510 registers and see if the frame pointer is needed; it is if there is
1511 no elimination of the frame pointer that we can perform. */
1513 frame_pointer_needed = 1;
1514 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1516 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM)
1517 frame_pointer_needed = 0;
1519 if (! ep->can_eliminate && ep->can_eliminate_previous)
1521 ep->can_eliminate_previous = 0;
1522 spill_hard_reg (ep->from, global, dumpfile, 1);
1523 regs_ever_live[ep->from] = 1;
1524 something_changed = 1;
1529 /* If all needs are met, we win. */
1531 for (i = 0; i < N_REG_CLASSES; i++)
1532 if (max_needs[i] > 0 || max_groups[i] > 0 || max_nongroups[i] > 0)
1534 if (i == N_REG_CLASSES && !new_basic_block_needs && ! something_changed)
1537 /* Not all needs are met; must spill more hard regs. */
1539 /* If any element of basic_block_needs changed from 0 to 1,
1540 re-spill all the regs already spilled. This may spill
1541 additional pseudos that didn't spill before. */
1543 if (new_basic_block_needs)
1544 for (i = 0; i < n_spills; i++)
1546 |= spill_hard_reg (spill_regs[i], global, dumpfile, 0);
1548 /* Now find more reload regs to satisfy the remaining need
1549 Do it by ascending class number, since otherwise a reg
1550 might be spilled for a big class and might fail to count
1551 for a smaller class even though it belongs to that class.
1553 Count spilled regs in `spills', and add entries to
1554 `spill_regs' and `spill_reg_order'.
1556 ??? Note there is a problem here.
1557 When there is a need for a group in a high-numbered class,
1558 and also need for non-group regs that come from a lower class,
1559 the non-group regs are chosen first. If there aren't many regs,
1560 they might leave no room for a group.
1562 This was happening on the 386. To fix it, we added the code
1563 that calls possible_group_p, so that the lower class won't
1564 break up the last possible group.
1566 Really fixing the problem would require changes above
1567 in counting the regs already spilled, and in choose_reload_regs.
1568 It might be hard to avoid introducing bugs there. */
1570 for (class = 0; class < N_REG_CLASSES; class++)
1572 /* First get the groups of registers.
1573 If we got single registers first, we might fragment
1575 while (max_groups[class] > 0)
1577 /* If any single spilled regs happen to form groups,
1578 count them now. Maybe we don't really need
1579 to spill another group. */
1580 count_possible_groups (group_size, group_mode, max_groups);
1582 if (max_groups[class] <= 0)
1585 /* Groups of size 2 (the only groups used on most machines)
1586 are treated specially. */
1587 if (group_size[class] == 2)
1589 /* First, look for a register that will complete a group. */
1590 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1592 int j = potential_reload_regs[i];
1594 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1596 ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1597 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1598 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1599 && HARD_REGNO_MODE_OK (other, group_mode[class])
1600 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1602 /* We don't want one part of another group.
1603 We could get "two groups" that overlap! */
1604 && ! TEST_HARD_REG_BIT (counted_for_groups, other))
1606 (j < FIRST_PSEUDO_REGISTER - 1
1607 && (other = j + 1, spill_reg_order[other] >= 0)
1608 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1609 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1610 && HARD_REGNO_MODE_OK (j, group_mode[class])
1611 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1613 && ! TEST_HARD_REG_BIT (counted_for_groups,
1616 register enum reg_class *p;
1618 /* We have found one that will complete a group,
1619 so count off one group as provided. */
1620 max_groups[class]--;
1621 p = reg_class_superclasses[class];
1622 while (*p != LIM_REG_CLASSES)
1623 max_groups[(int) *p++]--;
1625 /* Indicate both these regs are part of a group. */
1626 SET_HARD_REG_BIT (counted_for_groups, j);
1627 SET_HARD_REG_BIT (counted_for_groups, other);
1631 /* We can't complete a group, so start one. */
1632 if (i == FIRST_PSEUDO_REGISTER)
1633 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1635 int j = potential_reload_regs[i];
1636 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1637 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1638 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1639 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1640 && HARD_REGNO_MODE_OK (j, group_mode[class])
1641 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1646 /* I should be the index in potential_reload_regs
1647 of the new reload reg we have found. */
1649 if (i >= FIRST_PSEUDO_REGISTER)
1651 /* There are no groups left to spill. */
1652 spill_failure (max_groups_insn[class]);
1658 |= new_spill_reg (i, class, max_needs, NULL_PTR,
1663 /* For groups of more than 2 registers,
1664 look for a sufficient sequence of unspilled registers,
1665 and spill them all at once. */
1666 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1668 int j = potential_reload_regs[i];
1671 && j + group_size[class] <= FIRST_PSEUDO_REGISTER
1672 && HARD_REGNO_MODE_OK (j, group_mode[class]))
1674 /* Check each reg in the sequence. */
1675 for (k = 0; k < group_size[class]; k++)
1676 if (! (spill_reg_order[j + k] < 0
1677 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1678 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1680 /* We got a full sequence, so spill them all. */
1681 if (k == group_size[class])
1683 register enum reg_class *p;
1684 for (k = 0; k < group_size[class]; k++)
1687 SET_HARD_REG_BIT (counted_for_groups, j + k);
1688 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1689 if (potential_reload_regs[idx] == j + k)
1692 |= new_spill_reg (idx, class,
1693 max_needs, NULL_PTR,
1697 /* We have found one that will complete a group,
1698 so count off one group as provided. */
1699 max_groups[class]--;
1700 p = reg_class_superclasses[class];
1701 while (*p != LIM_REG_CLASSES)
1702 max_groups[(int) *p++]--;
1708 /* We couldn't find any registers for this reload.
1709 Avoid going into an infinite loop. */
1710 if (i >= FIRST_PSEUDO_REGISTER)
1712 /* There are no groups left. */
1713 spill_failure (max_groups_insn[class]);
1720 /* Now similarly satisfy all need for single registers. */
1722 while (max_needs[class] > 0 || max_nongroups[class] > 0)
1724 /* Consider the potential reload regs that aren't
1725 yet in use as reload regs, in order of preference.
1726 Find the most preferred one that's in this class. */
1728 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1729 if (potential_reload_regs[i] >= 0
1730 && TEST_HARD_REG_BIT (reg_class_contents[class],
1731 potential_reload_regs[i])
1732 /* If this reg will not be available for groups,
1733 pick one that does not foreclose possible groups.
1734 This is a kludge, and not very general,
1735 but it should be sufficient to make the 386 work,
1736 and the problem should not occur on machines with
1738 && (max_nongroups[class] == 0
1739 || possible_group_p (potential_reload_regs[i], max_groups)))
1742 /* If we couldn't get a register, try to get one even if we
1743 might foreclose possible groups. This may cause problems
1744 later, but that's better than aborting now, since it is
1745 possible that we will, in fact, be able to form the needed
1746 group even with this allocation. */
1748 if (i >= FIRST_PSEUDO_REGISTER
1749 && (asm_noperands (max_needs[class] > 0
1750 ? max_needs_insn[class]
1751 : max_nongroups_insn[class])
1753 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1754 if (potential_reload_regs[i] >= 0
1755 && TEST_HARD_REG_BIT (reg_class_contents[class],
1756 potential_reload_regs[i]))
1759 /* I should be the index in potential_reload_regs
1760 of the new reload reg we have found. */
1762 if (i >= FIRST_PSEUDO_REGISTER)
1764 /* There are no possible registers left to spill. */
1765 spill_failure (max_needs[class] > 0 ? max_needs_insn[class]
1766 : max_nongroups_insn[class]);
1772 |= new_spill_reg (i, class, max_needs, max_nongroups,
1778 /* If global-alloc was run, notify it of any register eliminations we have
1781 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1782 if (ep->can_eliminate)
1783 mark_elimination (ep->from, ep->to);
1785 /* Insert code to save and restore call-clobbered hard regs
1786 around calls. Tell if what mode to use so that we will process
1787 those insns in reload_as_needed if we have to. */
1789 if (caller_save_needed)
1790 save_call_clobbered_regs (num_eliminable ? QImode
1791 : caller_save_spill_class != NO_REGS ? HImode
1794 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1795 If that insn didn't set the register (i.e., it copied the register to
1796 memory), just delete that insn instead of the equivalencing insn plus
1797 anything now dead. If we call delete_dead_insn on that insn, we may
1798 delete the insn that actually sets the register if the register die
1799 there and that is incorrect. */
1801 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1802 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0
1803 && GET_CODE (reg_equiv_init[i]) != NOTE)
1805 if (reg_set_p (regno_reg_rtx[i], PATTERN (reg_equiv_init[i])))
1806 delete_dead_insn (reg_equiv_init[i]);
1809 PUT_CODE (reg_equiv_init[i], NOTE);
1810 NOTE_SOURCE_FILE (reg_equiv_init[i]) = 0;
1811 NOTE_LINE_NUMBER (reg_equiv_init[i]) = NOTE_INSN_DELETED;
1815 /* Use the reload registers where necessary
1816 by generating move instructions to move the must-be-register
1817 values into or out of the reload registers. */
1819 if (something_needs_reloads || something_needs_elimination
1820 || (caller_save_needed && num_eliminable)
1821 || caller_save_spill_class != NO_REGS)
1822 reload_as_needed (first, global);
1824 /* If we were able to eliminate the frame pointer, show that it is no
1825 longer live at the start of any basic block. If it is live by
1826 virtue of being in a pseudo, that pseudo will be marked live
1827 and hence the frame pointer will be known to be live via that
1830 if (! frame_pointer_needed)
1831 for (i = 0; i < n_basic_blocks; i++)
1832 basic_block_live_at_start[i][FRAME_POINTER_REGNUM / REGSET_ELT_BITS]
1833 &= ~ ((REGSET_ELT_TYPE) 1 << (FRAME_POINTER_REGNUM % REGSET_ELT_BITS));
1835 /* Come here (with failure set nonzero) if we can't get enough spill regs
1836 and we decide not to abort about it. */
1839 reload_in_progress = 0;
1841 /* Now eliminate all pseudo regs by modifying them into
1842 their equivalent memory references.
1843 The REG-rtx's for the pseudos are modified in place,
1844 so all insns that used to refer to them now refer to memory.
1846 For a reg that has a reg_equiv_address, all those insns
1847 were changed by reloading so that no insns refer to it any longer;
1848 but the DECL_RTL of a variable decl may refer to it,
1849 and if so this causes the debugging info to mention the variable. */
1851 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1855 if (reg_equiv_mem[i])
1857 addr = XEXP (reg_equiv_mem[i], 0);
1858 in_struct = MEM_IN_STRUCT_P (reg_equiv_mem[i]);
1860 if (reg_equiv_address[i])
1861 addr = reg_equiv_address[i];
1864 if (reg_renumber[i] < 0)
1866 rtx reg = regno_reg_rtx[i];
1867 XEXP (reg, 0) = addr;
1868 REG_USERVAR_P (reg) = 0;
1869 MEM_IN_STRUCT_P (reg) = in_struct;
1870 PUT_CODE (reg, MEM);
1872 else if (reg_equiv_mem[i])
1873 XEXP (reg_equiv_mem[i], 0) = addr;
1877 #ifdef PRESERVE_DEATH_INFO_REGNO_P
1878 /* Make a pass over all the insns and remove death notes for things that
1879 are no longer registers or no longer die in the insn (e.g., an input
1880 and output pseudo being tied). */
1882 for (insn = first; insn; insn = NEXT_INSN (insn))
1883 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1887 for (note = REG_NOTES (insn); note; note = next)
1889 next = XEXP (note, 1);
1890 if (REG_NOTE_KIND (note) == REG_DEAD
1891 && (GET_CODE (XEXP (note, 0)) != REG
1892 || reg_set_p (XEXP (note, 0), PATTERN (insn))))
1893 remove_note (insn, note);
1898 /* Indicate that we no longer have known memory locations or constants. */
1899 reg_equiv_constant = 0;
1900 reg_equiv_memory_loc = 0;
1905 /* Nonzero if, after spilling reg REGNO for non-groups,
1906 it will still be possible to find a group if we still need one. */
1909 possible_group_p (regno, max_groups)
1914 int class = (int) NO_REGS;
1916 for (i = 0; i < (int) N_REG_CLASSES; i++)
1917 if (max_groups[i] > 0)
1923 if (class == (int) NO_REGS)
1926 /* Consider each pair of consecutive registers. */
1927 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
1929 /* Ignore pairs that include reg REGNO. */
1930 if (i == regno || i + 1 == regno)
1933 /* Ignore pairs that are outside the class that needs the group.
1934 ??? Here we fail to handle the case where two different classes
1935 independently need groups. But this never happens with our
1936 current machine descriptions. */
1937 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
1938 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
1941 /* A pair of consecutive regs we can still spill does the trick. */
1942 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
1943 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
1944 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
1947 /* A pair of one already spilled and one we can spill does it
1948 provided the one already spilled is not otherwise reserved. */
1949 if (spill_reg_order[i] < 0
1950 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
1951 && spill_reg_order[i + 1] >= 0
1952 && ! TEST_HARD_REG_BIT (counted_for_groups, i + 1)
1953 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i + 1))
1955 if (spill_reg_order[i + 1] < 0
1956 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
1957 && spill_reg_order[i] >= 0
1958 && ! TEST_HARD_REG_BIT (counted_for_groups, i)
1959 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i))
1966 /* Count any groups that can be formed from the registers recently spilled.
1967 This is done class by class, in order of ascending class number. */
1970 count_possible_groups (group_size, group_mode, max_groups)
1971 int *group_size, *max_groups;
1972 enum machine_mode *group_mode;
1975 /* Now find all consecutive groups of spilled registers
1976 and mark each group off against the need for such groups.
1977 But don't count them against ordinary need, yet. */
1979 for (i = 0; i < N_REG_CLASSES; i++)
1980 if (group_size[i] > 1)
1985 CLEAR_HARD_REG_SET (new);
1987 /* Make a mask of all the regs that are spill regs in class I. */
1988 for (j = 0; j < n_spills; j++)
1989 if (TEST_HARD_REG_BIT (reg_class_contents[i], spill_regs[j])
1990 && ! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[j])
1991 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1993 SET_HARD_REG_BIT (new, spill_regs[j]);
1995 /* Find each consecutive group of them. */
1996 for (j = 0; j < FIRST_PSEUDO_REGISTER && max_groups[i] > 0; j++)
1997 if (TEST_HARD_REG_BIT (new, j)
1998 && j + group_size[i] <= FIRST_PSEUDO_REGISTER
1999 /* Next line in case group-mode for this class
2000 demands an even-odd pair. */
2001 && HARD_REGNO_MODE_OK (j, group_mode[i]))
2004 for (k = 1; k < group_size[i]; k++)
2005 if (! TEST_HARD_REG_BIT (new, j + k))
2007 if (k == group_size[i])
2009 /* We found a group. Mark it off against this class's
2010 need for groups, and against each superclass too. */
2011 register enum reg_class *p;
2013 p = reg_class_superclasses[i];
2014 while (*p != LIM_REG_CLASSES)
2015 max_groups[(int) *p++]--;
2016 /* Don't count these registers again. */
2017 for (k = 0; k < group_size[i]; k++)
2018 SET_HARD_REG_BIT (counted_for_groups, j + k);
2020 /* Skip to the last reg in this group. When j is incremented
2021 above, it will then point to the first reg of the next
2029 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2030 another mode that needs to be reloaded for the same register class CLASS.
2031 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2032 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2034 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2035 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2036 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2037 causes unnecessary failures on machines requiring alignment of register
2038 groups when the two modes are different sizes, because the larger mode has
2039 more strict alignment rules than the smaller mode. */
2042 modes_equiv_for_class_p (allocate_mode, other_mode, class)
2043 enum machine_mode allocate_mode, other_mode;
2044 enum reg_class class;
2047 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2049 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
2050 && HARD_REGNO_MODE_OK (regno, allocate_mode)
2051 && ! HARD_REGNO_MODE_OK (regno, other_mode))
2057 /* Handle the failure to find a register to spill.
2058 INSN should be one of the insns which needed this particular spill reg. */
2061 spill_failure (insn)
2064 if (asm_noperands (PATTERN (insn)) >= 0)
2065 error_for_asm (insn, "`asm' needs too many reloads");
2070 /* Add a new register to the tables of available spill-registers
2071 (as well as spilling all pseudos allocated to the register).
2072 I is the index of this register in potential_reload_regs.
2073 CLASS is the regclass whose need is being satisfied.
2074 MAX_NEEDS and MAX_NONGROUPS are the vectors of needs,
2075 so that this register can count off against them.
2076 MAX_NONGROUPS is 0 if this register is part of a group.
2077 GLOBAL and DUMPFILE are the same as the args that `reload' got. */
2080 new_spill_reg (i, class, max_needs, max_nongroups, global, dumpfile)
2088 register enum reg_class *p;
2090 int regno = potential_reload_regs[i];
2092 if (i >= FIRST_PSEUDO_REGISTER)
2093 abort (); /* Caller failed to find any register. */
2095 if (fixed_regs[regno] || TEST_HARD_REG_BIT (forbidden_regs, regno))
2096 fatal ("fixed or forbidden register was spilled.\n\
2097 This may be due to a compiler bug or to impossible asm statements.");
2099 /* Make reg REGNO an additional reload reg. */
2101 potential_reload_regs[i] = -1;
2102 spill_regs[n_spills] = regno;
2103 spill_reg_order[regno] = n_spills;
2105 fprintf (dumpfile, "Spilling reg %d.\n", spill_regs[n_spills]);
2107 /* Clear off the needs we just satisfied. */
2110 p = reg_class_superclasses[class];
2111 while (*p != LIM_REG_CLASSES)
2112 max_needs[(int) *p++]--;
2114 if (max_nongroups && max_nongroups[class] > 0)
2116 SET_HARD_REG_BIT (counted_for_nongroups, regno);
2117 max_nongroups[class]--;
2118 p = reg_class_superclasses[class];
2119 while (*p != LIM_REG_CLASSES)
2120 max_nongroups[(int) *p++]--;
2123 /* Spill every pseudo reg that was allocated to this reg
2124 or to something that overlaps this reg. */
2126 val = spill_hard_reg (spill_regs[n_spills], global, dumpfile, 0);
2128 /* If there are some registers still to eliminate and this register
2129 wasn't ever used before, additional stack space may have to be
2130 allocated to store this register. Thus, we may have changed the offset
2131 between the stack and frame pointers, so mark that something has changed.
2132 (If new pseudos were spilled, thus requiring more space, VAL would have
2133 been set non-zero by the call to spill_hard_reg above since additional
2134 reloads may be needed in that case.
2136 One might think that we need only set VAL to 1 if this is a call-used
2137 register. However, the set of registers that must be saved by the
2138 prologue is not identical to the call-used set. For example, the
2139 register used by the call insn for the return PC is a call-used register,
2140 but must be saved by the prologue. */
2141 if (num_eliminable && ! regs_ever_live[spill_regs[n_spills]])
2144 regs_ever_live[spill_regs[n_spills]] = 1;
2150 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2151 data that is dead in INSN. */
2154 delete_dead_insn (insn)
2157 rtx prev = prev_real_insn (insn);
2160 /* If the previous insn sets a register that dies in our insn, delete it
2162 if (prev && GET_CODE (PATTERN (prev)) == SET
2163 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2164 && reg_mentioned_p (prev_dest, PATTERN (insn))
2165 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)))
2166 delete_dead_insn (prev);
2168 PUT_CODE (insn, NOTE);
2169 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2170 NOTE_SOURCE_FILE (insn) = 0;
2173 /* Modify the home of pseudo-reg I.
2174 The new home is present in reg_renumber[I].
2176 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2177 or it may be -1, meaning there is none or it is not relevant.
2178 This is used so that all pseudos spilled from a given hard reg
2179 can share one stack slot. */
2182 alter_reg (i, from_reg)
2186 /* When outputting an inline function, this can happen
2187 for a reg that isn't actually used. */
2188 if (regno_reg_rtx[i] == 0)
2191 /* If the reg got changed to a MEM at rtl-generation time,
2193 if (GET_CODE (regno_reg_rtx[i]) != REG)
2196 /* Modify the reg-rtx to contain the new hard reg
2197 number or else to contain its pseudo reg number. */
2198 REGNO (regno_reg_rtx[i])
2199 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2201 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2202 allocate a stack slot for it. */
2204 if (reg_renumber[i] < 0
2205 && reg_n_refs[i] > 0
2206 && reg_equiv_constant[i] == 0
2207 && reg_equiv_memory_loc[i] == 0)
2210 int inherent_size = PSEUDO_REGNO_BYTES (i);
2211 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2214 /* Each pseudo reg has an inherent size which comes from its own mode,
2215 and a total size which provides room for paradoxical subregs
2216 which refer to the pseudo reg in wider modes.
2218 We can use a slot already allocated if it provides both
2219 enough inherent space and enough total space.
2220 Otherwise, we allocate a new slot, making sure that it has no less
2221 inherent space, and no less total space, then the previous slot. */
2224 /* No known place to spill from => no slot to reuse. */
2225 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size, -1);
2226 #if BYTES_BIG_ENDIAN
2227 /* Cancel the big-endian correction done in assign_stack_local.
2228 Get the address of the beginning of the slot.
2229 This is so we can do a big-endian correction unconditionally
2231 adjust = inherent_size - total_size;
2234 /* Reuse a stack slot if possible. */
2235 else if (spill_stack_slot[from_reg] != 0
2236 && spill_stack_slot_width[from_reg] >= total_size
2237 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2239 x = spill_stack_slot[from_reg];
2240 /* Allocate a bigger slot. */
2243 /* Compute maximum size needed, both for inherent size
2244 and for total size. */
2245 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2246 if (spill_stack_slot[from_reg])
2248 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2250 mode = GET_MODE (spill_stack_slot[from_reg]);
2251 if (spill_stack_slot_width[from_reg] > total_size)
2252 total_size = spill_stack_slot_width[from_reg];
2254 /* Make a slot with that size. */
2255 x = assign_stack_local (mode, total_size, -1);
2256 #if BYTES_BIG_ENDIAN
2257 /* Cancel the big-endian correction done in assign_stack_local.
2258 Get the address of the beginning of the slot.
2259 This is so we can do a big-endian correction unconditionally
2261 adjust = GET_MODE_SIZE (mode) - total_size;
2263 spill_stack_slot[from_reg] = x;
2264 spill_stack_slot_width[from_reg] = total_size;
2267 #if BYTES_BIG_ENDIAN
2268 /* On a big endian machine, the "address" of the slot
2269 is the address of the low part that fits its inherent mode. */
2270 if (inherent_size < total_size)
2271 adjust += (total_size - inherent_size);
2272 #endif /* BYTES_BIG_ENDIAN */
2274 /* If we have any adjustment to make, or if the stack slot is the
2275 wrong mode, make a new stack slot. */
2276 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2278 x = gen_rtx (MEM, GET_MODE (regno_reg_rtx[i]),
2279 plus_constant (XEXP (x, 0), adjust));
2280 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2283 /* Save the stack slot for later. */
2284 reg_equiv_memory_loc[i] = x;
2288 /* Mark the slots in regs_ever_live for the hard regs
2289 used by pseudo-reg number REGNO. */
2292 mark_home_live (regno)
2295 register int i, lim;
2296 i = reg_renumber[regno];
2299 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2301 regs_ever_live[i++] = 1;
2304 /* This function handles the tracking of elimination offsets around branches.
2306 X is a piece of RTL being scanned.
2308 INSN is the insn that it came from, if any.
2310 INITIAL_P is non-zero if we are to set the offset to be the initial
2311 offset and zero if we are setting the offset of the label to be the
2315 set_label_offsets (x, insn, initial_p)
2320 enum rtx_code code = GET_CODE (x);
2323 struct elim_table *p;
2328 if (LABEL_REF_NONLOCAL_P (x))
2333 /* ... fall through ... */
2336 /* If we know nothing about this label, set the desired offsets. Note
2337 that this sets the offset at a label to be the offset before a label
2338 if we don't know anything about the label. This is not correct for
2339 the label after a BARRIER, but is the best guess we can make. If
2340 we guessed wrong, we will suppress an elimination that might have
2341 been possible had we been able to guess correctly. */
2343 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2345 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2346 offsets_at[CODE_LABEL_NUMBER (x)][i]
2347 = (initial_p ? reg_eliminate[i].initial_offset
2348 : reg_eliminate[i].offset);
2349 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2352 /* Otherwise, if this is the definition of a label and it is
2353 preceded by a BARRIER, set our offsets to the known offset of
2357 && (tem = prev_nonnote_insn (insn)) != 0
2358 && GET_CODE (tem) == BARRIER)
2360 num_not_at_initial_offset = 0;
2361 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2363 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
2364 = offsets_at[CODE_LABEL_NUMBER (x)][i];
2365 if (reg_eliminate[i].can_eliminate
2366 && (reg_eliminate[i].offset
2367 != reg_eliminate[i].initial_offset))
2368 num_not_at_initial_offset++;
2373 /* If neither of the above cases is true, compare each offset
2374 with those previously recorded and suppress any eliminations
2375 where the offsets disagree. */
2377 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2378 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2379 != (initial_p ? reg_eliminate[i].initial_offset
2380 : reg_eliminate[i].offset))
2381 reg_eliminate[i].can_eliminate = 0;
2386 set_label_offsets (PATTERN (insn), insn, initial_p);
2388 /* ... fall through ... */
2392 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2393 and hence must have all eliminations at their initial offsets. */
2394 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2395 if (REG_NOTE_KIND (tem) == REG_LABEL)
2396 set_label_offsets (XEXP (tem, 0), insn, 1);
2401 /* Each of the labels in the address vector must be at their initial
2402 offsets. We want the first first for ADDR_VEC and the second
2403 field for ADDR_DIFF_VEC. */
2405 for (i = 0; i < XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2406 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2411 /* We only care about setting PC. If the source is not RETURN,
2412 IF_THEN_ELSE, or a label, disable any eliminations not at
2413 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2414 isn't one of those possibilities. For branches to a label,
2415 call ourselves recursively.
2417 Note that this can disable elimination unnecessarily when we have
2418 a non-local goto since it will look like a non-constant jump to
2419 someplace in the current function. This isn't a significant
2420 problem since such jumps will normally be when all elimination
2421 pairs are back to their initial offsets. */
2423 if (SET_DEST (x) != pc_rtx)
2426 switch (GET_CODE (SET_SRC (x)))
2433 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2437 tem = XEXP (SET_SRC (x), 1);
2438 if (GET_CODE (tem) == LABEL_REF)
2439 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2440 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2443 tem = XEXP (SET_SRC (x), 2);
2444 if (GET_CODE (tem) == LABEL_REF)
2445 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2446 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2451 /* If we reach here, all eliminations must be at their initial
2452 offset because we are doing a jump to a variable address. */
2453 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2454 if (p->offset != p->initial_offset)
2455 p->can_eliminate = 0;
2459 /* Used for communication between the next two function to properly share
2460 the vector for an ASM_OPERANDS. */
2462 static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2464 /* Scan X and replace any eliminable registers (such as fp) with a
2465 replacement (such as sp), plus an offset.
2467 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2468 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2469 MEM, we are allowed to replace a sum of a register and the constant zero
2470 with the register, which we cannot do outside a MEM. In addition, we need
2471 to record the fact that a register is referenced outside a MEM.
2473 If INSN is nonzero, it is the insn containing X. If we replace a REG
2474 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2475 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2476 that the REG is being modified.
2478 If we see a modification to a register we know about, take the
2479 appropriate action (see case SET, below).
2481 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2482 replacements done assuming all offsets are at their initial values. If
2483 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2484 encounter, return the actual location so that find_reloads will do
2485 the proper thing. */
2488 eliminate_regs (x, mem_mode, insn)
2490 enum machine_mode mem_mode;
2493 enum rtx_code code = GET_CODE (x);
2494 struct elim_table *ep;
2519 /* First handle the case where we encounter a bare register that
2520 is eliminable. Replace it with a PLUS. */
2521 if (regno < FIRST_PSEUDO_REGISTER)
2523 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2525 if (ep->from_rtx == x && ep->can_eliminate)
2528 ep->ref_outside_mem = 1;
2529 return plus_constant (ep->to_rtx, ep->previous_offset);
2533 else if (reg_equiv_memory_loc && reg_equiv_memory_loc[regno]
2534 && (reg_equiv_address[regno] || num_not_at_initial_offset))
2536 /* In this case, find_reloads would attempt to either use an
2537 incorrect address (if something is not at its initial offset)
2538 or substitute an replaced address into an insn (which loses
2539 if the offset is changed by some later action). So we simply
2540 return the replaced stack slot (assuming it is changed by
2541 elimination) and ignore the fact that this is actually a
2542 reference to the pseudo. Ensure we make a copy of the
2543 address in case it is shared. */
2544 new = eliminate_regs (reg_equiv_memory_loc[regno],
2545 mem_mode, NULL_RTX);
2546 if (new != reg_equiv_memory_loc[regno])
2547 return copy_rtx (new);
2552 /* If this is the sum of an eliminable register and a constant, rework
2554 if (GET_CODE (XEXP (x, 0)) == REG
2555 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2556 && CONSTANT_P (XEXP (x, 1)))
2558 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2560 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2563 ep->ref_outside_mem = 1;
2565 /* The only time we want to replace a PLUS with a REG (this
2566 occurs when the constant operand of the PLUS is the negative
2567 of the offset) is when we are inside a MEM. We won't want
2568 to do so at other times because that would change the
2569 structure of the insn in a way that reload can't handle.
2570 We special-case the commonest situation in
2571 eliminate_regs_in_insn, so just replace a PLUS with a
2572 PLUS here, unless inside a MEM. */
2573 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2574 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2577 return gen_rtx (PLUS, Pmode, ep->to_rtx,
2578 plus_constant (XEXP (x, 1),
2579 ep->previous_offset));
2582 /* If the register is not eliminable, we are done since the other
2583 operand is a constant. */
2587 /* If this is part of an address, we want to bring any constant to the
2588 outermost PLUS. We will do this by doing register replacement in
2589 our operands and seeing if a constant shows up in one of them.
2591 We assume here this is part of an address (or a "load address" insn)
2592 since an eliminable register is not likely to appear in any other
2595 If we have (plus (eliminable) (reg)), we want to produce
2596 (plus (plus (replacement) (reg) (const))). If this was part of a
2597 normal add insn, (plus (replacement) (reg)) will be pushed as a
2598 reload. This is the desired action. */
2601 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2602 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, NULL_RTX);
2604 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2606 /* If one side is a PLUS and the other side is a pseudo that
2607 didn't get a hard register but has a reg_equiv_constant,
2608 we must replace the constant here since it may no longer
2609 be in the position of any operand. */
2610 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2611 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2612 && reg_renumber[REGNO (new1)] < 0
2613 && reg_equiv_constant != 0
2614 && reg_equiv_constant[REGNO (new1)] != 0)
2615 new1 = reg_equiv_constant[REGNO (new1)];
2616 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2617 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2618 && reg_renumber[REGNO (new0)] < 0
2619 && reg_equiv_constant[REGNO (new0)] != 0)
2620 new0 = reg_equiv_constant[REGNO (new0)];
2622 new = form_sum (new0, new1);
2624 /* As above, if we are not inside a MEM we do not want to
2625 turn a PLUS into something else. We might try to do so here
2626 for an addition of 0 if we aren't optimizing. */
2627 if (! mem_mode && GET_CODE (new) != PLUS)
2628 return gen_rtx (PLUS, GET_MODE (x), new, const0_rtx);
2636 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2639 new = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2640 if (new != XEXP (x, 0))
2641 x = gen_rtx (EXPR_LIST, REG_NOTE_KIND (x), new, XEXP (x, 1));
2644 /* ... fall through ... */
2647 /* Now do eliminations in the rest of the chain. If this was
2648 an EXPR_LIST, this might result in allocating more memory than is
2649 strictly needed, but it simplifies the code. */
2652 new = eliminate_regs (XEXP (x, 1), mem_mode, NULL_RTX);
2653 if (new != XEXP (x, 1))
2654 return gen_rtx (INSN_LIST, GET_MODE (x), XEXP (x, 0), new);
2662 case DIV: case UDIV:
2663 case MOD: case UMOD:
2664 case AND: case IOR: case XOR:
2665 case LSHIFT: case ASHIFT: case ROTATE:
2666 case ASHIFTRT: case LSHIFTRT: case ROTATERT:
2668 case GE: case GT: case GEU: case GTU:
2669 case LE: case LT: case LEU: case LTU:
2671 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2673 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, NULL_RTX) : 0;
2675 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2676 return gen_rtx (code, GET_MODE (x), new0, new1);
2684 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2685 if (ep->to_rtx == XEXP (x, 0))
2687 if (code == PRE_DEC || code == POST_DEC)
2688 ep->offset += GET_MODE_SIZE (mem_mode);
2690 ep->offset -= GET_MODE_SIZE (mem_mode);
2693 /* Fall through to generic unary operation case. */
2695 case STRICT_LOW_PART:
2697 case SIGN_EXTEND: case ZERO_EXTEND:
2698 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2699 case FLOAT: case FIX:
2700 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2704 new = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2705 if (new != XEXP (x, 0))
2706 return gen_rtx (code, GET_MODE (x), new);
2710 /* Similar to above processing, but preserve SUBREG_WORD.
2711 Convert (subreg (mem)) to (mem) if not paradoxical.
2712 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2713 pseudo didn't get a hard reg, we must replace this with the
2714 eliminated version of the memory location because push_reloads
2715 may do the replacement in certain circumstances. */
2716 if (GET_CODE (SUBREG_REG (x)) == REG
2717 && (GET_MODE_SIZE (GET_MODE (x))
2718 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2719 && reg_equiv_memory_loc != 0
2720 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2722 new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
2723 mem_mode, NULL_RTX);
2725 /* If we didn't change anything, we must retain the pseudo. */
2726 if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
2729 /* Otherwise, ensure NEW isn't shared in case we have to reload
2731 new = copy_rtx (new);
2734 new = eliminate_regs (SUBREG_REG (x), mem_mode, NULL_RTX);
2736 if (new != XEXP (x, 0))
2738 if (GET_CODE (new) == MEM
2739 && (GET_MODE_SIZE (GET_MODE (x))
2740 <= GET_MODE_SIZE (GET_MODE (new))))
2742 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2743 enum machine_mode mode = GET_MODE (x);
2745 #if BYTES_BIG_ENDIAN
2746 offset += (MIN (UNITS_PER_WORD,
2747 GET_MODE_SIZE (GET_MODE (new)))
2748 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2751 PUT_MODE (new, mode);
2752 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2756 return gen_rtx (SUBREG, GET_MODE (x), new, SUBREG_WORD (x));
2762 /* If clobbering a register that is the replacement register for an
2763 elimination we still think can be performed, note that it cannot
2764 be performed. Otherwise, we need not be concerned about it. */
2765 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2766 if (ep->to_rtx == XEXP (x, 0))
2767 ep->can_eliminate = 0;
2769 new = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2770 if (new != XEXP (x, 0))
2771 return gen_rtx (code, GET_MODE (x), new);
2777 /* Properly handle sharing input and constraint vectors. */
2778 if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
2780 /* When we come to a new vector not seen before,
2781 scan all its elements; keep the old vector if none
2782 of them changes; otherwise, make a copy. */
2783 old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
2784 temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
2785 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
2786 temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
2787 mem_mode, NULL_RTX);
2789 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
2790 if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
2793 if (i == ASM_OPERANDS_INPUT_LENGTH (x))
2794 new_asm_operands_vec = old_asm_operands_vec;
2796 new_asm_operands_vec
2797 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
2800 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
2801 if (new_asm_operands_vec == old_asm_operands_vec)
2804 new = gen_rtx (ASM_OPERANDS, VOIDmode, ASM_OPERANDS_TEMPLATE (x),
2805 ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
2806 ASM_OPERANDS_OUTPUT_IDX (x), new_asm_operands_vec,
2807 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
2808 ASM_OPERANDS_SOURCE_FILE (x),
2809 ASM_OPERANDS_SOURCE_LINE (x));
2810 new->volatil = x->volatil;
2815 /* Check for setting a register that we know about. */
2816 if (GET_CODE (SET_DEST (x)) == REG)
2818 /* See if this is setting the replacement register for an
2821 If DEST is the frame pointer, we do nothing because we assume that
2822 all assignments to the frame pointer are for non-local gotos and
2823 are being done at a time when they are valid and do not disturb
2824 anything else. Some machines want to eliminate a fake argument
2825 pointer with either the frame or stack pointer. Assignments to
2826 the frame pointer must not prevent this elimination. */
2828 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2830 if (ep->to_rtx == SET_DEST (x)
2831 && SET_DEST (x) != frame_pointer_rtx)
2833 /* If it is being incremented, adjust the offset. Otherwise,
2834 this elimination can't be done. */
2835 rtx src = SET_SRC (x);
2837 if (GET_CODE (src) == PLUS
2838 && XEXP (src, 0) == SET_DEST (x)
2839 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2840 ep->offset -= INTVAL (XEXP (src, 1));
2842 ep->can_eliminate = 0;
2845 /* Now check to see we are assigning to a register that can be
2846 eliminated. If so, it must be as part of a PARALLEL, since we
2847 will not have been called if this is a single SET. So indicate
2848 that we can no longer eliminate this reg. */
2849 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2851 if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
2852 ep->can_eliminate = 0;
2855 /* Now avoid the loop below in this common case. */
2857 rtx new0 = eliminate_regs (SET_DEST (x), 0, NULL_RTX);
2858 rtx new1 = eliminate_regs (SET_SRC (x), 0, NULL_RTX);
2860 /* If SET_DEST changed from a REG to a MEM and INSN is non-zero,
2861 write a CLOBBER insn. */
2862 if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
2864 emit_insn_after (gen_rtx (CLOBBER, VOIDmode, SET_DEST (x)), insn);
2866 if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
2867 return gen_rtx (SET, VOIDmode, new0, new1);
2873 /* Our only special processing is to pass the mode of the MEM to our
2874 recursive call and copy the flags. While we are here, handle this
2875 case more efficiently. */
2876 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), NULL_RTX);
2877 if (new != XEXP (x, 0))
2879 new = gen_rtx (MEM, GET_MODE (x), new);
2880 new->volatil = x->volatil;
2881 new->unchanging = x->unchanging;
2882 new->in_struct = x->in_struct;
2889 /* Process each of our operands recursively. If any have changed, make a
2891 fmt = GET_RTX_FORMAT (code);
2892 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2896 new = eliminate_regs (XEXP (x, i), mem_mode, NULL_RTX);
2897 if (new != XEXP (x, i) && ! copied)
2899 rtx new_x = rtx_alloc (code);
2900 bcopy (x, new_x, (sizeof (*new_x) - sizeof (new_x->fld)
2901 + (sizeof (new_x->fld[0])
2902 * GET_RTX_LENGTH (code))));
2908 else if (*fmt == 'E')
2911 for (j = 0; j < XVECLEN (x, i); j++)
2913 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2914 if (new != XVECEXP (x, i, j) && ! copied_vec)
2916 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2917 &XVECEXP (x, i, 0));
2920 rtx new_x = rtx_alloc (code);
2921 bcopy (x, new_x, (sizeof (*new_x) - sizeof (new_x->fld)
2922 + (sizeof (new_x->fld[0])
2923 * GET_RTX_LENGTH (code))));
2927 XVEC (x, i) = new_v;
2930 XVECEXP (x, i, j) = new;
2938 /* Scan INSN and eliminate all eliminable registers in it.
2940 If REPLACE is nonzero, do the replacement destructively. Also
2941 delete the insn as dead it if it is setting an eliminable register.
2943 If REPLACE is zero, do all our allocations in reload_obstack.
2945 If no eliminations were done and this insn doesn't require any elimination
2946 processing (these are not identical conditions: it might be updating sp,
2947 but not referencing fp; this needs to be seen during reload_as_needed so
2948 that the offset between fp and sp can be taken into consideration), zero
2949 is returned. Otherwise, 1 is returned. */
2952 eliminate_regs_in_insn (insn, replace)
2956 rtx old_body = PATTERN (insn);
2959 struct elim_table *ep;
2962 push_obstacks (&reload_obstack, &reload_obstack);
2964 if (GET_CODE (old_body) == SET && GET_CODE (SET_DEST (old_body)) == REG
2965 && REGNO (SET_DEST (old_body)) < FIRST_PSEUDO_REGISTER)
2967 /* Check for setting an eliminable register. */
2968 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2969 if (ep->from_rtx == SET_DEST (old_body) && ep->can_eliminate)
2971 /* In this case this insn isn't serving a useful purpose. We
2972 will delete it in reload_as_needed once we know that this
2973 elimination is, in fact, being done.
2975 If REPLACE isn't set, we can't delete this insn, but neededn't
2976 process it since it won't be used unless something changes. */
2978 delete_dead_insn (insn);
2983 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
2984 in the insn is the negative of the offset in FROM. Substitute
2985 (set (reg) (reg to)) for the insn and change its code.
2987 We have to do this here, rather than in eliminate_regs, do that we can
2988 change the insn code. */
2990 if (GET_CODE (SET_SRC (old_body)) == PLUS
2991 && GET_CODE (XEXP (SET_SRC (old_body), 0)) == REG
2992 && GET_CODE (XEXP (SET_SRC (old_body), 1)) == CONST_INT)
2993 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2995 if (ep->from_rtx == XEXP (SET_SRC (old_body), 0)
2996 && ep->can_eliminate
2997 && ep->offset == - INTVAL (XEXP (SET_SRC (old_body), 1)))
2999 PATTERN (insn) = gen_rtx (SET, VOIDmode,
3000 SET_DEST (old_body), ep->to_rtx);
3001 INSN_CODE (insn) = -1;
3007 old_asm_operands_vec = 0;
3009 /* Replace the body of this insn with a substituted form. If we changed
3010 something, return non-zero. If this is the final call for this
3011 insn (REPLACE is non-zero), do the elimination in REG_NOTES as well.
3013 If we are replacing a body that was a (set X (plus Y Z)), try to
3014 re-recognize the insn. We do this in case we had a simple addition
3015 but now can do this as a load-address. This saves an insn in this
3018 new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX);
3019 if (new_body != old_body)
3021 /* If we aren't replacing things permanently and we changed something,
3022 make another copy to ensure that all the RTL is new. Otherwise
3023 things can go wrong if find_reload swaps commutative operands
3024 and one is inside RTL that has been copied while the other is not. */
3026 /* Don't copy an asm_operands because (1) there's no need and (2)
3027 copy_rtx can't do it properly when there are multiple outputs. */
3028 if (! replace && asm_noperands (old_body) < 0)
3029 new_body = copy_rtx (new_body);
3031 /* If we had a move insn but now we don't, rerecognize it. */
3032 if ((GET_CODE (old_body) == SET && GET_CODE (SET_SRC (old_body)) == REG
3033 && (GET_CODE (new_body) != SET
3034 || GET_CODE (SET_SRC (new_body)) != REG))
3035 /* If this was an add insn before, rerecognize. */
3037 (GET_CODE (old_body) == SET
3038 && GET_CODE (SET_SRC (old_body)) == PLUS))
3040 if (! validate_change (insn, &PATTERN (insn), new_body, 0))
3041 /* If recognition fails, store the new body anyway.
3042 It's normal to have recognition failures here
3043 due to bizarre memory addresses; reloading will fix them. */
3044 PATTERN (insn) = new_body;
3047 PATTERN (insn) = new_body;
3049 if (replace && REG_NOTES (insn))
3050 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, NULL_RTX);
3054 /* Loop through all elimination pairs. See if any have changed and
3055 recalculate the number not at initial offset.
3057 Compute the maximum offset (minimum offset if the stack does not
3058 grow downward) for each elimination pair.
3060 We also detect a cases where register elimination cannot be done,
3061 namely, if a register would be both changed and referenced outside a MEM
3062 in the resulting insn since such an insn is often undefined and, even if
3063 not, we cannot know what meaning will be given to it. Note that it is
3064 valid to have a register used in an address in an insn that changes it
3065 (presumably with a pre- or post-increment or decrement).
3067 If anything changes, return nonzero. */
3069 num_not_at_initial_offset = 0;
3070 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3072 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3073 ep->can_eliminate = 0;
3075 ep->ref_outside_mem = 0;
3077 if (ep->previous_offset != ep->offset)
3080 ep->previous_offset = ep->offset;
3081 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3082 num_not_at_initial_offset++;
3084 #ifdef STACK_GROWS_DOWNWARD
3085 ep->max_offset = MAX (ep->max_offset, ep->offset);
3087 ep->max_offset = MIN (ep->max_offset, ep->offset);
3098 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3099 replacement we currently believe is valid, mark it as not eliminable if X
3100 modifies DEST in any way other than by adding a constant integer to it.
3102 If DEST is the frame pointer, we do nothing because we assume that
3103 all assignments to the frame pointer are nonlocal gotos and are being done
3104 at a time when they are valid and do not disturb anything else.
3105 Some machines want to eliminate a fake argument pointer with either the
3106 frame or stack pointer. Assignments to the frame pointer must not prevent
3109 Called via note_stores from reload before starting its passes to scan
3110 the insns of the function. */
3113 mark_not_eliminable (dest, x)
3119 /* A SUBREG of a hard register here is just changing its mode. We should
3120 not see a SUBREG of an eliminable hard register, but check just in
3122 if (GET_CODE (dest) == SUBREG)
3123 dest = SUBREG_REG (dest);
3125 if (dest == frame_pointer_rtx)
3128 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3129 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3130 && (GET_CODE (x) != SET
3131 || GET_CODE (SET_SRC (x)) != PLUS
3132 || XEXP (SET_SRC (x), 0) != dest
3133 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3135 reg_eliminate[i].can_eliminate_previous
3136 = reg_eliminate[i].can_eliminate = 0;
3141 /* Kick all pseudos out of hard register REGNO.
3142 If GLOBAL is nonzero, try to find someplace else to put them.
3143 If DUMPFILE is nonzero, log actions taken on that file.
3145 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3146 because we found we can't eliminate some register. In the case, no pseudos
3147 are allowed to be in the register, even if they are only in a block that
3148 doesn't require spill registers, unlike the case when we are spilling this
3149 hard reg to produce another spill register.
3151 Return nonzero if any pseudos needed to be kicked out. */
3154 spill_hard_reg (regno, global, dumpfile, cant_eliminate)
3160 int something_changed = 0;
3163 SET_HARD_REG_BIT (forbidden_regs, regno);
3165 /* Spill every pseudo reg that was allocated to this reg
3166 or to something that overlaps this reg. */
3168 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3169 if (reg_renumber[i] >= 0
3170 && reg_renumber[i] <= regno
3172 + HARD_REGNO_NREGS (reg_renumber[i],
3173 PSEUDO_REGNO_MODE (i))
3176 enum reg_class class = REGNO_REG_CLASS (regno);
3178 /* If this register belongs solely to a basic block which needed no
3179 spilling of any class that this register is contained in,
3180 leave it be, unless we are spilling this register because
3181 it was a hard register that can't be eliminated. */
3183 if (! cant_eliminate
3184 && basic_block_needs[0]
3185 && reg_basic_block[i] >= 0
3186 && basic_block_needs[(int) class][reg_basic_block[i]] == 0)
3190 for (p = reg_class_superclasses[(int) class];
3191 *p != LIM_REG_CLASSES; p++)
3192 if (basic_block_needs[(int) *p][reg_basic_block[i]] > 0)
3195 if (*p == LIM_REG_CLASSES)
3199 /* Mark it as no longer having a hard register home. */
3200 reg_renumber[i] = -1;
3201 /* We will need to scan everything again. */
3202 something_changed = 1;
3204 retry_global_alloc (i, forbidden_regs);
3206 alter_reg (i, regno);
3209 if (reg_renumber[i] == -1)
3210 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3212 fprintf (dumpfile, " Register %d now in %d.\n\n",
3213 i, reg_renumber[i]);
3217 return something_changed;
3220 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3223 scan_paradoxical_subregs (x)
3228 register enum rtx_code code = GET_CODE (x);
3245 if (GET_CODE (SUBREG_REG (x)) == REG
3246 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3247 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3248 = GET_MODE_SIZE (GET_MODE (x));
3252 fmt = GET_RTX_FORMAT (code);
3253 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3256 scan_paradoxical_subregs (XEXP (x, i));
3257 else if (fmt[i] == 'E')
3260 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3261 scan_paradoxical_subregs (XVECEXP (x, i, j));
3266 struct hard_reg_n_uses { int regno; int uses; };
3269 hard_reg_use_compare (p1, p2)
3270 struct hard_reg_n_uses *p1, *p2;
3272 int tem = p1->uses - p2->uses;
3273 if (tem != 0) return tem;
3274 /* If regs are equally good, sort by regno,
3275 so that the results of qsort leave nothing to chance. */
3276 return p1->regno - p2->regno;
3279 /* Choose the order to consider regs for use as reload registers
3280 based on how much trouble would be caused by spilling one.
3281 Store them in order of decreasing preference in potential_reload_regs. */
3284 order_regs_for_reload ()
3290 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
3292 CLEAR_HARD_REG_SET (bad_spill_regs);
3294 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3295 potential_reload_regs[i] = -1;
3297 /* Count number of uses of each hard reg by pseudo regs allocated to it
3298 and then order them by decreasing use. */
3300 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3302 hard_reg_n_uses[i].uses = 0;
3303 hard_reg_n_uses[i].regno = i;
3306 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3308 int regno = reg_renumber[i];
3311 int lim = regno + HARD_REGNO_NREGS (regno, PSEUDO_REGNO_MODE (i));
3313 hard_reg_n_uses[regno++].uses += reg_n_refs[i];
3315 large += reg_n_refs[i];
3318 /* Now fixed registers (which cannot safely be used for reloading)
3319 get a very high use count so they will be considered least desirable.
3320 Registers used explicitly in the rtl code are almost as bad. */
3322 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3326 hard_reg_n_uses[i].uses += 2 * large + 2;
3327 SET_HARD_REG_BIT (bad_spill_regs, i);
3329 else if (regs_explicitly_used[i])
3331 hard_reg_n_uses[i].uses += large + 1;
3332 /* ??? We are doing this here because of the potential that
3333 bad code may be generated if a register explicitly used in
3334 an insn was used as a spill register for that insn. But
3335 not using these are spill registers may lose on some machine.
3336 We'll have to see how this works out. */
3337 SET_HARD_REG_BIT (bad_spill_regs, i);
3340 hard_reg_n_uses[FRAME_POINTER_REGNUM].uses += 2 * large + 2;
3341 SET_HARD_REG_BIT (bad_spill_regs, FRAME_POINTER_REGNUM);
3343 #ifdef ELIMINABLE_REGS
3344 /* If registers other than the frame pointer are eliminable, mark them as
3346 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3348 hard_reg_n_uses[reg_eliminate[i].from].uses += 2 * large + 2;
3349 SET_HARD_REG_BIT (bad_spill_regs, reg_eliminate[i].from);
3353 /* Prefer registers not so far used, for use in temporary loading.
3354 Among them, if REG_ALLOC_ORDER is defined, use that order.
3355 Otherwise, prefer registers not preserved by calls. */
3357 #ifdef REG_ALLOC_ORDER
3358 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3360 int regno = reg_alloc_order[i];
3362 if (hard_reg_n_uses[regno].uses == 0)
3363 potential_reload_regs[o++] = regno;
3366 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3368 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i])
3369 potential_reload_regs[o++] = i;
3371 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3373 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i])
3374 potential_reload_regs[o++] = i;
3378 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
3379 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
3381 /* Now add the regs that are already used,
3382 preferring those used less often. The fixed and otherwise forbidden
3383 registers will be at the end of this list. */
3385 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3386 if (hard_reg_n_uses[i].uses != 0)
3387 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
3390 /* Reload pseudo-registers into hard regs around each insn as needed.
3391 Additional register load insns are output before the insn that needs it
3392 and perhaps store insns after insns that modify the reloaded pseudo reg.
3394 reg_last_reload_reg and reg_reloaded_contents keep track of
3395 which pseudo-registers are already available in reload registers.
3396 We update these for the reloads that we perform,
3397 as the insns are scanned. */
3400 reload_as_needed (first, live_known)
3410 bzero (spill_reg_rtx, sizeof spill_reg_rtx);
3411 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
3412 bzero (reg_last_reload_reg, max_regno * sizeof (rtx));
3413 reg_has_output_reload = (char *) alloca (max_regno);
3414 for (i = 0; i < n_spills; i++)
3416 reg_reloaded_contents[i] = -1;
3417 reg_reloaded_insn[i] = 0;
3420 /* Reset all offsets on eliminable registers to their initial values. */
3421 #ifdef ELIMINABLE_REGS
3422 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3424 INITIAL_ELIMINATION_OFFSET (reg_eliminate[i].from, reg_eliminate[i].to,
3425 reg_eliminate[i].initial_offset);
3426 reg_eliminate[i].previous_offset
3427 = reg_eliminate[i].offset = reg_eliminate[i].initial_offset;
3430 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
3431 reg_eliminate[0].previous_offset
3432 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
3435 num_not_at_initial_offset = 0;
3437 for (insn = first; insn;)
3439 register rtx next = NEXT_INSN (insn);
3441 /* Notice when we move to a new basic block. */
3442 if (live_known && this_block + 1 < n_basic_blocks
3443 && insn == basic_block_head[this_block+1])
3446 /* If we pass a label, copy the offsets from the label information
3447 into the current offsets of each elimination. */
3448 if (GET_CODE (insn) == CODE_LABEL)
3450 num_not_at_initial_offset = 0;
3451 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3453 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
3454 = offsets_at[CODE_LABEL_NUMBER (insn)][i];
3455 if (reg_eliminate[i].can_eliminate
3456 && (reg_eliminate[i].offset
3457 != reg_eliminate[i].initial_offset))
3458 num_not_at_initial_offset++;
3462 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3464 rtx avoid_return_reg = 0;
3466 #ifdef SMALL_REGISTER_CLASSES
3467 /* Set avoid_return_reg if this is an insn
3468 that might use the value of a function call. */
3469 if (GET_CODE (insn) == CALL_INSN)
3471 if (GET_CODE (PATTERN (insn)) == SET)
3472 after_call = SET_DEST (PATTERN (insn));
3473 else if (GET_CODE (PATTERN (insn)) == PARALLEL
3474 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
3475 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
3479 else if (after_call != 0
3480 && !(GET_CODE (PATTERN (insn)) == SET
3481 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
3483 if (reg_mentioned_p (after_call, PATTERN (insn)))
3484 avoid_return_reg = after_call;
3487 #endif /* SMALL_REGISTER_CLASSES */
3489 /* If this is a USE and CLOBBER of a MEM, ensure that any
3490 references to eliminable registers have been removed. */
3492 if ((GET_CODE (PATTERN (insn)) == USE
3493 || GET_CODE (PATTERN (insn)) == CLOBBER)
3494 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3495 XEXP (XEXP (PATTERN (insn), 0), 0)
3496 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3497 GET_MODE (XEXP (PATTERN (insn), 0)), NULL_RTX);
3499 /* If we need to do register elimination processing, do so.
3500 This might delete the insn, in which case we are done. */
3501 if (num_eliminable && GET_MODE (insn) == QImode)
3503 eliminate_regs_in_insn (insn, 1);
3504 if (GET_CODE (insn) == NOTE)
3511 if (GET_MODE (insn) == VOIDmode)
3513 /* First find the pseudo regs that must be reloaded for this insn.
3514 This info is returned in the tables reload_... (see reload.h).
3515 Also modify the body of INSN by substituting RELOAD
3516 rtx's for those pseudo regs. */
3519 bzero (reg_has_output_reload, max_regno);
3520 CLEAR_HARD_REG_SET (reg_is_output_reload);
3522 find_reloads (insn, 1, spill_indirect_levels, live_known,
3528 rtx prev = PREV_INSN (insn), next = NEXT_INSN (insn);
3532 /* If this block has not had spilling done for a
3533 particular class, deactivate any optional reloads
3534 of that class lest they try to use a spill-reg which isn't
3535 available here. If we have any non-optionals that need a
3536 spill reg, abort. */
3538 for (class = 0; class < N_REG_CLASSES; class++)
3539 if (basic_block_needs[class] != 0
3540 && basic_block_needs[class][this_block] == 0)
3541 for (i = 0; i < n_reloads; i++)
3542 if (class == (int) reload_reg_class[i])
3544 if (reload_optional[i])
3546 reload_in[i] = reload_out[i] = 0;
3547 reload_secondary_p[i] = 0;
3549 else if (reload_reg_rtx[i] == 0
3550 && (reload_in[i] != 0 || reload_out[i] != 0
3551 || reload_secondary_p[i] != 0))
3555 /* Now compute which reload regs to reload them into. Perhaps
3556 reusing reload regs from previous insns, or else output
3557 load insns to reload them. Maybe output store insns too.
3558 Record the choices of reload reg in reload_reg_rtx. */
3559 choose_reload_regs (insn, avoid_return_reg);
3561 /* Generate the insns to reload operands into or out of
3562 their reload regs. */
3563 emit_reload_insns (insn);
3565 /* Substitute the chosen reload regs from reload_reg_rtx
3566 into the insn's body (or perhaps into the bodies of other
3567 load and store insn that we just made for reloading
3568 and that we moved the structure into). */
3571 /* If this was an ASM, make sure that all the reload insns
3572 we have generated are valid. If not, give an error
3575 if (asm_noperands (PATTERN (insn)) >= 0)
3576 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3577 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
3578 && (recog_memoized (p) < 0
3579 || (insn_extract (p),
3580 ! constrain_operands (INSN_CODE (p), 1))))
3582 error_for_asm (insn,
3583 "`asm' operand requires impossible reload");
3585 NOTE_SOURCE_FILE (p) = 0;
3586 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3589 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3590 is no longer validly lying around to save a future reload.
3591 Note that this does not detect pseudos that were reloaded
3592 for this insn in order to be stored in
3593 (obeying register constraints). That is correct; such reload
3594 registers ARE still valid. */
3595 note_stores (PATTERN (insn), forget_old_reloads_1);
3597 /* There may have been CLOBBER insns placed after INSN. So scan
3598 between INSN and NEXT and use them to forget old reloads. */
3599 for (x = NEXT_INSN (insn); x != next; x = NEXT_INSN (x))
3600 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3601 note_stores (PATTERN (x), forget_old_reloads_1);
3604 /* Likewise for regs altered by auto-increment in this insn.
3605 But note that the reg-notes are not changed by reloading:
3606 they still contain the pseudo-regs, not the spill regs. */
3607 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3608 if (REG_NOTE_KIND (x) == REG_INC)
3610 /* See if this pseudo reg was reloaded in this insn.
3611 If so, its last-reload info is still valid
3612 because it is based on this insn's reload. */
3613 for (i = 0; i < n_reloads; i++)
3614 if (reload_out[i] == XEXP (x, 0))
3618 forget_old_reloads_1 (XEXP (x, 0));
3622 /* A reload reg's contents are unknown after a label. */
3623 if (GET_CODE (insn) == CODE_LABEL)
3624 for (i = 0; i < n_spills; i++)
3626 reg_reloaded_contents[i] = -1;
3627 reg_reloaded_insn[i] = 0;
3630 /* Don't assume a reload reg is still good after a call insn
3631 if it is a call-used reg. */
3632 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == CALL_INSN)
3633 for (i = 0; i < n_spills; i++)
3634 if (call_used_regs[spill_regs[i]])
3636 reg_reloaded_contents[i] = -1;
3637 reg_reloaded_insn[i] = 0;
3640 /* In case registers overlap, allow certain insns to invalidate
3641 particular hard registers. */
3643 #ifdef INSN_CLOBBERS_REGNO_P
3644 for (i = 0 ; i < n_spills ; i++)
3645 if (INSN_CLOBBERS_REGNO_P (insn, spill_regs[i]))
3647 reg_reloaded_contents[i] = -1;
3648 reg_reloaded_insn[i] = 0;
3660 /* Discard all record of any value reloaded from X,
3661 or reloaded in X from someplace else;
3662 unless X is an output reload reg of the current insn.
3664 X may be a hard reg (the reload reg)
3665 or it may be a pseudo reg that was reloaded from. */
3668 forget_old_reloads_1 (x)
3675 /* note_stores does give us subregs of hard regs. */
3676 while (GET_CODE (x) == SUBREG)
3678 offset += SUBREG_WORD (x);
3682 if (GET_CODE (x) != REG)
3685 regno = REGNO (x) + offset;
3687 if (regno >= FIRST_PSEUDO_REGISTER)
3692 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
3693 /* Storing into a spilled-reg invalidates its contents.
3694 This can happen if a block-local pseudo is allocated to that reg
3695 and it wasn't spilled because this block's total need is 0.
3696 Then some insn might have an optional reload and use this reg. */
3697 for (i = 0; i < nr; i++)
3698 if (spill_reg_order[regno + i] >= 0
3699 /* But don't do this if the reg actually serves as an output
3700 reload reg in the current instruction. */
3702 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)))
3704 reg_reloaded_contents[spill_reg_order[regno + i]] = -1;
3705 reg_reloaded_insn[spill_reg_order[regno + i]] = 0;
3709 /* Since value of X has changed,
3710 forget any value previously copied from it. */
3713 /* But don't forget a copy if this is the output reload
3714 that establishes the copy's validity. */
3715 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
3716 reg_last_reload_reg[regno + nr] = 0;
3719 /* For each reload, the mode of the reload register. */
3720 static enum machine_mode reload_mode[MAX_RELOADS];
3722 /* For each reload, the largest number of registers it will require. */
3723 static int reload_nregs[MAX_RELOADS];
3725 /* Comparison function for qsort to decide which of two reloads
3726 should be handled first. *P1 and *P2 are the reload numbers. */
3729 reload_reg_class_lower (p1, p2)
3732 register int r1 = *p1, r2 = *p2;
3735 /* Consider required reloads before optional ones. */
3736 t = reload_optional[r1] - reload_optional[r2];
3740 /* Count all solitary classes before non-solitary ones. */
3741 t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
3742 - (reg_class_size[(int) reload_reg_class[r1]] == 1));
3746 /* Aside from solitaires, consider all multi-reg groups first. */
3747 t = reload_nregs[r2] - reload_nregs[r1];
3751 /* Consider reloads in order of increasing reg-class number. */
3752 t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
3756 /* If reloads are equally urgent, sort by reload number,
3757 so that the results of qsort leave nothing to chance. */
3761 /* The following HARD_REG_SETs indicate when each hard register is
3762 used for a reload of various parts of the current insn. */
3764 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
3765 static HARD_REG_SET reload_reg_used;
3766 /* If reg is in use for a RELOAD_FOR_INPUT_RELOAD_ADDRESS reload. */
3767 static HARD_REG_SET reload_reg_used_in_input_addr;
3768 /* If reg is in use for a RELOAD_FOR_OUTPUT_RELOAD_ADDRESS reload. */
3769 static HARD_REG_SET reload_reg_used_in_output_addr;
3770 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
3771 static HARD_REG_SET reload_reg_used_in_op_addr;
3772 /* If reg is in use for a RELOAD_FOR_INPUT reload. */
3773 static HARD_REG_SET reload_reg_used_in_input;
3774 /* If reg is in use for a RELOAD_FOR_OUTPUT reload. */
3775 static HARD_REG_SET reload_reg_used_in_output;
3777 /* If reg is in use as a reload reg for any sort of reload. */
3778 static HARD_REG_SET reload_reg_used_at_all;
3780 /* Mark reg REGNO as in use for a reload of the sort spec'd by WHEN_NEEDED.
3781 MODE is used to indicate how many consecutive regs are actually used. */
3784 mark_reload_reg_in_use (regno, when_needed, mode)
3786 enum reload_when_needed when_needed;
3787 enum machine_mode mode;
3789 int nregs = HARD_REGNO_NREGS (regno, mode);
3792 for (i = regno; i < nregs + regno; i++)
3794 switch (when_needed)
3797 SET_HARD_REG_BIT (reload_reg_used, i);
3800 case RELOAD_FOR_INPUT_RELOAD_ADDRESS:
3801 SET_HARD_REG_BIT (reload_reg_used_in_input_addr, i);
3804 case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS:
3805 SET_HARD_REG_BIT (reload_reg_used_in_output_addr, i);
3808 case RELOAD_FOR_OPERAND_ADDRESS:
3809 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
3812 case RELOAD_FOR_INPUT:
3813 SET_HARD_REG_BIT (reload_reg_used_in_input, i);
3816 case RELOAD_FOR_OUTPUT:
3817 SET_HARD_REG_BIT (reload_reg_used_in_output, i);
3821 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
3825 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
3826 specified by WHEN_NEEDED. */
3829 reload_reg_free_p (regno, when_needed)
3831 enum reload_when_needed when_needed;
3833 /* In use for a RELOAD_OTHER means it's not available for anything. */
3834 if (TEST_HARD_REG_BIT (reload_reg_used, regno))
3836 switch (when_needed)
3839 /* In use for anything means not available for a RELOAD_OTHER. */
3840 return ! TEST_HARD_REG_BIT (reload_reg_used_at_all, regno);
3842 /* The other kinds of use can sometimes share a register. */
3843 case RELOAD_FOR_INPUT:
3844 return (! TEST_HARD_REG_BIT (reload_reg_used_in_input, regno)
3845 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
3846 && ! TEST_HARD_REG_BIT (reload_reg_used_in_input_addr, regno));
3847 case RELOAD_FOR_INPUT_RELOAD_ADDRESS:
3848 return (! TEST_HARD_REG_BIT (reload_reg_used_in_input_addr, regno)
3849 && ! TEST_HARD_REG_BIT (reload_reg_used_in_input, regno));
3850 case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS:
3851 return (! TEST_HARD_REG_BIT (reload_reg_used_in_output_addr, regno)
3852 && ! TEST_HARD_REG_BIT (reload_reg_used_in_output, regno));
3853 case RELOAD_FOR_OPERAND_ADDRESS:
3854 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
3855 && ! TEST_HARD_REG_BIT (reload_reg_used_in_input, regno)
3856 && ! TEST_HARD_REG_BIT (reload_reg_used_in_output, regno));
3857 case RELOAD_FOR_OUTPUT:
3858 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
3859 && ! TEST_HARD_REG_BIT (reload_reg_used_in_output_addr, regno)
3860 && ! TEST_HARD_REG_BIT (reload_reg_used_in_output, regno));
3865 /* Return 1 if the value in reload reg REGNO, as used by a reload
3866 needed for the part of the insn specified by WHEN_NEEDED,
3867 is not in use for a reload in any prior part of the insn.
3869 We can assume that the reload reg was already tested for availability
3870 at the time it is needed, and we should not check this again,
3871 in case the reg has already been marked in use. */
3874 reload_reg_free_before_p (regno, when_needed)
3876 enum reload_when_needed when_needed;
3878 switch (when_needed)
3881 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
3882 its use starts from the beginning, so nothing can use it earlier. */
3885 /* If this use is for part of the insn,
3886 check the reg is not in use for any prior part. */
3887 case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS:
3888 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
3890 case RELOAD_FOR_OUTPUT:
3891 if (TEST_HARD_REG_BIT (reload_reg_used_in_input, regno))
3893 case RELOAD_FOR_OPERAND_ADDRESS:
3894 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr, regno))
3896 case RELOAD_FOR_INPUT_RELOAD_ADDRESS:
3897 case RELOAD_FOR_INPUT:
3903 /* Return 1 if the value in reload reg REGNO, as used by a reload
3904 needed for the part of the insn specified by WHEN_NEEDED,
3905 is still available in REGNO at the end of the insn.
3907 We can assume that the reload reg was already tested for availability
3908 at the time it is needed, and we should not check this again,
3909 in case the reg has already been marked in use. */
3912 reload_reg_reaches_end_p (regno, when_needed)
3914 enum reload_when_needed when_needed;
3916 switch (when_needed)
3919 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
3920 its value must reach the end. */
3923 /* If this use is for part of the insn,
3924 its value reaches if no subsequent part uses the same register. */
3925 case RELOAD_FOR_INPUT_RELOAD_ADDRESS:
3926 case RELOAD_FOR_INPUT:
3927 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
3928 || TEST_HARD_REG_BIT (reload_reg_used_in_output, regno))
3930 case RELOAD_FOR_OPERAND_ADDRESS:
3931 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr, regno))
3933 case RELOAD_FOR_OUTPUT:
3934 case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS:
3940 /* Vector of reload-numbers showing the order in which the reloads should
3942 short reload_order[MAX_RELOADS];
3944 /* Indexed by reload number, 1 if incoming value
3945 inherited from previous insns. */
3946 char reload_inherited[MAX_RELOADS];
3948 /* For an inherited reload, this is the insn the reload was inherited from,
3949 if we know it. Otherwise, this is 0. */
3950 rtx reload_inheritance_insn[MAX_RELOADS];
3952 /* If non-zero, this is a place to get the value of the reload,
3953 rather than using reload_in. */
3954 rtx reload_override_in[MAX_RELOADS];
3956 /* For each reload, the index in spill_regs of the spill register used,
3957 or -1 if we did not need one of the spill registers for this reload. */
3958 int reload_spill_index[MAX_RELOADS];
3960 /* Index of last register assigned as a spill register. We allocate in
3961 a round-robin fashio. */
3963 static last_spill_reg = 0;
3965 /* Find a spill register to use as a reload register for reload R.
3966 LAST_RELOAD is non-zero if this is the last reload for the insn being
3969 Set reload_reg_rtx[R] to the register allocated.
3971 If NOERROR is nonzero, we return 1 if successful,
3972 or 0 if we couldn't find a spill reg and we didn't change anything. */
3975 allocate_reload_reg (r, insn, last_reload, noerror)
3987 /* If we put this reload ahead, thinking it is a group,
3988 then insist on finding a group. Otherwise we can grab a
3989 reg that some other reload needs.
3990 (That can happen when we have a 68000 DATA_OR_FP_REG
3991 which is a group of data regs or one fp reg.)
3992 We need not be so restrictive if there are no more reloads
3995 ??? Really it would be nicer to have smarter handling
3996 for that kind of reg class, where a problem like this is normal.
3997 Perhaps those classes should be avoided for reloading
3998 by use of more alternatives. */
4000 int force_group = reload_nregs[r] > 1 && ! last_reload;
4002 /* If we want a single register and haven't yet found one,
4003 take any reg in the right class and not in use.
4004 If we want a consecutive group, here is where we look for it.
4006 We use two passes so we can first look for reload regs to
4007 reuse, which are already in use for other reloads in this insn,
4008 and only then use additional registers.
4009 I think that maximizing reuse is needed to make sure we don't
4010 run out of reload regs. Suppose we have three reloads, and
4011 reloads A and B can share regs. These need two regs.
4012 Suppose A and B are given different regs.
4013 That leaves none for C. */
4014 for (pass = 0; pass < 2; pass++)
4016 /* I is the index in spill_regs.
4017 We advance it round-robin between insns to use all spill regs
4018 equally, so that inherited reloads have a chance
4019 of leapfrogging each other. */
4021 for (count = 0, i = last_spill_reg; count < n_spills; count++)
4023 int class = (int) reload_reg_class[r];
4025 i = (i + 1) % n_spills;
4027 if (reload_reg_free_p (spill_regs[i], reload_when_needed[r])
4028 && TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
4029 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
4030 /* Look first for regs to share, then for unshared. */
4031 && (pass || TEST_HARD_REG_BIT (reload_reg_used_at_all,
4034 int nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
4035 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
4036 (on 68000) got us two FP regs. If NR is 1,
4037 we would reject both of them. */
4039 nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
4040 /* If we need only one reg, we have already won. */
4043 /* But reject a single reg if we demand a group. */
4048 /* Otherwise check that as many consecutive regs as we need
4050 Also, don't use for a group registers that are
4051 needed for nongroups. */
4052 if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
4055 regno = spill_regs[i] + nr - 1;
4056 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
4057 && spill_reg_order[regno] >= 0
4058 && reload_reg_free_p (regno, reload_when_needed[r])
4059 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
4069 /* If we found something on pass 1, omit pass 2. */
4070 if (count < n_spills)
4074 /* We should have found a spill register by now. */
4075 if (count == n_spills)
4084 /* Mark as in use for this insn the reload regs we use for this. */
4085 mark_reload_reg_in_use (spill_regs[i], reload_when_needed[r],
4088 new = spill_reg_rtx[i];
4090 if (new == 0 || GET_MODE (new) != reload_mode[r])
4091 spill_reg_rtx[i] = new = gen_rtx (REG, reload_mode[r], spill_regs[i]);
4093 reload_reg_rtx[r] = new;
4094 reload_spill_index[r] = i;
4095 regno = true_regnum (new);
4097 /* Detect when the reload reg can't hold the reload mode.
4098 This used to be one `if', but Sequent compiler can't handle that. */
4099 if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
4101 enum machine_mode test_mode = VOIDmode;
4103 test_mode = GET_MODE (reload_in[r]);
4104 /* If reload_in[r] has VOIDmode, it means we will load it
4105 in whatever mode the reload reg has: to wit, reload_mode[r].
4106 We have already tested that for validity. */
4107 /* Aside from that, we need to test that the expressions
4108 to reload from or into have modes which are valid for this
4109 reload register. Otherwise the reload insns would be invalid. */
4110 if (! (reload_in[r] != 0 && test_mode != VOIDmode
4111 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
4112 if (! (reload_out[r] != 0
4113 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
4114 /* The reg is OK. */
4118 /* The reg is not OK. */
4123 if (asm_noperands (PATTERN (insn)) < 0)
4124 /* It's the compiler's fault. */
4127 /* It's the user's fault; the operand's mode and constraint
4128 don't match. Disable this reload so we don't crash in final. */
4129 error_for_asm (insn,
4130 "`asm' operand constraint incompatible with operand size");
4133 reload_reg_rtx[r] = 0;
4134 reload_optional[r] = 1;
4135 reload_secondary_p[r] = 1;
4140 /* Assign hard reg targets for the pseudo-registers we must reload
4141 into hard regs for this insn.
4142 Also output the instructions to copy them in and out of the hard regs.
4144 For machines with register classes, we are responsible for
4145 finding a reload reg in the proper class. */
4148 choose_reload_regs (insn, avoid_return_reg)
4150 /* This argument is currently ignored. */
4151 rtx avoid_return_reg;
4154 int max_group_size = 1;
4155 enum reg_class group_class = NO_REGS;
4158 rtx save_reload_reg_rtx[MAX_RELOADS];
4159 char save_reload_inherited[MAX_RELOADS];
4160 rtx save_reload_inheritance_insn[MAX_RELOADS];
4161 rtx save_reload_override_in[MAX_RELOADS];
4162 int save_reload_spill_index[MAX_RELOADS];
4163 HARD_REG_SET save_reload_reg_used;
4164 HARD_REG_SET save_reload_reg_used_in_input_addr;
4165 HARD_REG_SET save_reload_reg_used_in_output_addr;
4166 HARD_REG_SET save_reload_reg_used_in_op_addr;
4167 HARD_REG_SET save_reload_reg_used_in_input;
4168 HARD_REG_SET save_reload_reg_used_in_output;
4169 HARD_REG_SET save_reload_reg_used_at_all;
4171 bzero (reload_inherited, MAX_RELOADS);
4172 bzero (reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
4173 bzero (reload_override_in, MAX_RELOADS * sizeof (rtx));
4175 CLEAR_HARD_REG_SET (reload_reg_used);
4176 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
4177 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr);
4178 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr);
4179 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
4180 CLEAR_HARD_REG_SET (reload_reg_used_in_output);
4181 CLEAR_HARD_REG_SET (reload_reg_used_in_input);
4183 /* Distinguish output-only and input-only reloads
4184 because they can overlap with other things. */
4185 for (j = 0; j < n_reloads; j++)
4186 if (reload_when_needed[j] == RELOAD_OTHER
4187 && ! reload_needed_for_multiple[j])
4189 if (reload_in[j] == 0 && reload_out[j] != 0)
4191 /* But earlyclobber operands must stay as RELOAD_OTHER. */
4192 for (i = 0; i < n_earlyclobbers; i++)
4194 if (GET_CODE (reload_earlyclobbers[i]) == SUBREG
4195 && reg_overlap_mentioned_for_reload_p (reload_out[j],
4196 SUBREG_REG (reload_earlyclobbers[i])))
4198 if (rtx_equal_p (reload_out[j], reload_earlyclobbers[i]))
4201 if (i == n_earlyclobbers)
4202 reload_when_needed[j] = RELOAD_FOR_OUTPUT;
4204 if (reload_out[j] == 0)
4205 reload_when_needed[j] = RELOAD_FOR_INPUT;
4207 if (reload_secondary_reload[j] >= 0
4208 && ! reload_needed_for_multiple[reload_secondary_reload[j]])
4209 reload_when_needed[reload_secondary_reload[j]]
4210 = reload_when_needed[j];
4213 #ifdef SMALL_REGISTER_CLASSES
4214 /* Don't bother with avoiding the return reg
4215 if we have no mandatory reload that could use it. */
4216 if (avoid_return_reg)
4219 int regno = REGNO (avoid_return_reg);
4221 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
4224 for (r = regno; r < regno + nregs; r++)
4225 if (spill_reg_order[r] >= 0)
4226 for (j = 0; j < n_reloads; j++)
4227 if (!reload_optional[j] && reload_reg_rtx[j] == 0
4228 && (reload_in[j] != 0 || reload_out[j] != 0
4229 || reload_secondary_p[j])
4231 TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[j]], r))
4234 avoid_return_reg = 0;
4236 #endif /* SMALL_REGISTER_CLASSES */
4238 #if 0 /* Not needed, now that we can always retry without inheritance. */
4239 /* See if we have more mandatory reloads than spill regs.
4240 If so, then we cannot risk optimizations that could prevent
4241 reloads from sharing one spill register.
4243 Since we will try finding a better register than reload_reg_rtx
4244 unless it is equal to reload_in or reload_out, count such reloads. */
4248 #ifdef SMALL_REGISTER_CLASSES
4249 int tem = (avoid_return_reg != 0);
4251 for (j = 0; j < n_reloads; j++)
4252 if (! reload_optional[j]
4253 && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
4254 && (reload_reg_rtx[j] == 0
4255 || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
4256 && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
4263 #ifdef SMALL_REGISTER_CLASSES
4264 /* Don't use the subroutine call return reg for a reload
4265 if we are supposed to avoid it. */
4266 if (avoid_return_reg)
4268 int regno = REGNO (avoid_return_reg);
4270 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
4273 for (r = regno; r < regno + nregs; r++)
4274 if (spill_reg_order[r] >= 0)
4275 SET_HARD_REG_BIT (reload_reg_used, r);
4277 #endif /* SMALL_REGISTER_CLASSES */
4279 /* In order to be certain of getting the registers we need,
4280 we must sort the reloads into order of increasing register class.
4281 Then our grabbing of reload registers will parallel the process
4282 that provided the reload registers.
4284 Also note whether any of the reloads wants a consecutive group of regs.
4285 If so, record the maximum size of the group desired and what
4286 register class contains all the groups needed by this insn. */
4288 for (j = 0; j < n_reloads; j++)
4290 reload_order[j] = j;
4291 reload_spill_index[j] = -1;
4294 = (reload_strict_low[j] && reload_out[j]
4295 ? GET_MODE (SUBREG_REG (reload_out[j]))
4296 : (reload_inmode[j] == VOIDmode
4297 || (GET_MODE_SIZE (reload_outmode[j])
4298 > GET_MODE_SIZE (reload_inmode[j])))
4299 ? reload_outmode[j] : reload_inmode[j]);
4301 reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
4303 if (reload_nregs[j] > 1)
4305 max_group_size = MAX (reload_nregs[j], max_group_size);
4306 group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
4309 /* If we have already decided to use a certain register,
4310 don't use it in another way. */
4311 if (reload_reg_rtx[j])
4312 mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]),
4313 reload_when_needed[j], reload_mode[j]);
4317 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
4319 bcopy (reload_reg_rtx, save_reload_reg_rtx, sizeof reload_reg_rtx);
4320 bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
4321 bcopy (reload_inheritance_insn, save_reload_inheritance_insn,
4322 sizeof reload_inheritance_insn);
4323 bcopy (reload_override_in, save_reload_override_in,
4324 sizeof reload_override_in);
4325 bcopy (reload_spill_index, save_reload_spill_index,
4326 sizeof reload_spill_index);
4327 COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
4328 COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
4329 COPY_HARD_REG_SET (save_reload_reg_used_in_output,
4330 reload_reg_used_in_output);
4331 COPY_HARD_REG_SET (save_reload_reg_used_in_input,
4332 reload_reg_used_in_input);
4333 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr,
4334 reload_reg_used_in_input_addr);
4335 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr,
4336 reload_reg_used_in_output_addr);
4337 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
4338 reload_reg_used_in_op_addr);
4340 /* If -O, try first with inheritance, then turning it off.
4341 If not -O, don't do inheritance.
4342 Using inheritance when not optimizing leads to paradoxes
4343 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
4344 because one side of the comparison might be inherited. */
4346 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
4348 /* Process the reloads in order of preference just found.
4349 Beyond this point, subregs can be found in reload_reg_rtx.
4351 This used to look for an existing reloaded home for all
4352 of the reloads, and only then perform any new reloads.
4353 But that could lose if the reloads were done out of reg-class order
4354 because a later reload with a looser constraint might have an old
4355 home in a register needed by an earlier reload with a tighter constraint.
4357 To solve this, we make two passes over the reloads, in the order
4358 described above. In the first pass we try to inherit a reload
4359 from a previous insn. If there is a later reload that needs a
4360 class that is a proper subset of the class being processed, we must
4361 also allocate a spill register during the first pass.
4363 Then make a second pass over the reloads to allocate any reloads
4364 that haven't been given registers yet. */
4366 for (j = 0; j < n_reloads; j++)
4368 register int r = reload_order[j];
4370 /* Ignore reloads that got marked inoperative. */
4371 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
4374 /* If find_reloads chose a to use reload_in or reload_out as a reload
4375 register, we don't need to chose one. Otherwise, try even if it found
4376 one since we might save an insn if we find the value lying around. */
4377 if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
4378 && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
4379 || rtx_equal_p (reload_out[r], reload_reg_rtx[r])))
4382 #if 0 /* No longer needed for correct operation.
4383 It might give better code, or might not; worth an experiment? */
4384 /* If this is an optional reload, we can't inherit from earlier insns
4385 until we are sure that any non-optional reloads have been allocated.
4386 The following code takes advantage of the fact that optional reloads
4387 are at the end of reload_order. */
4388 if (reload_optional[r] != 0)
4389 for (i = 0; i < j; i++)
4390 if ((reload_out[reload_order[i]] != 0
4391 || reload_in[reload_order[i]] != 0
4392 || reload_secondary_p[reload_order[i]])
4393 && ! reload_optional[reload_order[i]]
4394 && reload_reg_rtx[reload_order[i]] == 0)
4395 allocate_reload_reg (reload_order[i], insn, 0, inheritance);
4398 /* First see if this pseudo is already available as reloaded
4399 for a previous insn. We cannot try to inherit for reloads
4400 that are smaller than the maximum number of registers needed
4401 for groups unless the register we would allocate cannot be used
4404 We could check here to see if this is a secondary reload for
4405 an object that is already in a register of the desired class.
4406 This would avoid the need for the secondary reload register.
4407 But this is complex because we can't easily determine what
4408 objects might want to be loaded via this reload. So let a register
4409 be allocated here. In `emit_reload_insns' we suppress one of the
4410 loads in the case described above. */
4414 register int regno = -1;
4415 enum machine_mode mode;
4417 if (reload_in[r] == 0)
4419 else if (GET_CODE (reload_in[r]) == REG)
4421 regno = REGNO (reload_in[r]);
4422 mode = GET_MODE (reload_in[r]);
4424 else if (GET_CODE (reload_in_reg[r]) == REG)
4426 regno = REGNO (reload_in_reg[r]);
4427 mode = GET_MODE (reload_in_reg[r]);
4430 /* This won't work, since REGNO can be a pseudo reg number.
4431 Also, it takes much more hair to keep track of all the things
4432 that can invalidate an inherited reload of part of a pseudoreg. */
4433 else if (GET_CODE (reload_in[r]) == SUBREG
4434 && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
4435 regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
4438 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
4440 i = spill_reg_order[REGNO (reg_last_reload_reg[regno])];
4442 if (reg_reloaded_contents[i] == regno
4443 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
4444 >= GET_MODE_SIZE (mode))
4445 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
4446 && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
4448 && (reload_nregs[r] == max_group_size
4449 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
4451 && reload_reg_free_p (spill_regs[i], reload_when_needed[r])
4452 && reload_reg_free_before_p (spill_regs[i],
4453 reload_when_needed[r]))
4455 /* If a group is needed, verify that all the subsequent
4456 registers still have their values intact. */
4458 = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
4461 for (k = 1; k < nr; k++)
4462 if (reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
4468 /* Mark the register as in use for this part of
4470 mark_reload_reg_in_use (spill_regs[i],
4471 reload_when_needed[r],
4473 reload_reg_rtx[r] = reg_last_reload_reg[regno];
4474 reload_inherited[r] = 1;
4475 reload_inheritance_insn[r] = reg_reloaded_insn[i];
4476 reload_spill_index[r] = i;
4482 /* Here's another way to see if the value is already lying around. */
4484 && reload_in[r] != 0
4485 && ! reload_inherited[r]
4486 && reload_out[r] == 0
4487 && (CONSTANT_P (reload_in[r])
4488 || GET_CODE (reload_in[r]) == PLUS
4489 || GET_CODE (reload_in[r]) == REG
4490 || GET_CODE (reload_in[r]) == MEM)
4491 && (reload_nregs[r] == max_group_size
4492 || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
4495 = find_equiv_reg (reload_in[r], insn, reload_reg_class[r],
4496 -1, NULL_PTR, 0, reload_mode[r]);
4501 if (GET_CODE (equiv) == REG)
4502 regno = REGNO (equiv);
4503 else if (GET_CODE (equiv) == SUBREG)
4505 regno = REGNO (SUBREG_REG (equiv));
4506 if (regno < FIRST_PSEUDO_REGISTER)
4507 regno += SUBREG_WORD (equiv);
4513 /* If we found a spill reg, reject it unless it is free
4514 and of the desired class. */
4516 && ((spill_reg_order[regno] >= 0
4517 && ! reload_reg_free_before_p (regno,
4518 reload_when_needed[r]))
4519 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
4523 if (equiv != 0 && TEST_HARD_REG_BIT (reload_reg_used_at_all, regno))
4526 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
4529 /* We found a register that contains the value we need.
4530 If this register is the same as an `earlyclobber' operand
4531 of the current insn, just mark it as a place to reload from
4532 since we can't use it as the reload register itself. */
4535 for (i = 0; i < n_earlyclobbers; i++)
4536 if (reg_overlap_mentioned_for_reload_p (equiv,
4537 reload_earlyclobbers[i]))
4539 reload_override_in[r] = equiv;
4544 /* JRV: If the equiv register we have found is explicitly
4545 clobbered in the current insn, mark but don't use, as above. */
4547 if (equiv != 0 && regno_clobbered_p (regno, insn))
4549 reload_override_in[r] = equiv;
4553 /* If we found an equivalent reg, say no code need be generated
4554 to load it, and use it as our reload reg. */
4555 if (equiv != 0 && regno != FRAME_POINTER_REGNUM)
4557 reload_reg_rtx[r] = equiv;
4558 reload_inherited[r] = 1;
4559 /* If it is a spill reg,
4560 mark the spill reg as in use for this insn. */
4561 i = spill_reg_order[regno];
4563 mark_reload_reg_in_use (regno, reload_when_needed[r],
4568 /* If we found a register to use already, or if this is an optional
4569 reload, we are done. */
4570 if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
4573 #if 0 /* No longer needed for correct operation. Might or might not
4574 give better code on the average. Want to experiment? */
4576 /* See if there is a later reload that has a class different from our
4577 class that intersects our class or that requires less register
4578 than our reload. If so, we must allocate a register to this
4579 reload now, since that reload might inherit a previous reload
4580 and take the only available register in our class. Don't do this
4581 for optional reloads since they will force all previous reloads
4582 to be allocated. Also don't do this for reloads that have been
4585 for (i = j + 1; i < n_reloads; i++)
4587 int s = reload_order[i];
4589 if ((reload_in[s] == 0 && reload_out[s] == 0
4590 && ! reload_secondary_p[s])
4591 || reload_optional[s])
4594 if ((reload_reg_class[s] != reload_reg_class[r]
4595 && reg_classes_intersect_p (reload_reg_class[r],
4596 reload_reg_class[s]))
4597 || reload_nregs[s] < reload_nregs[r])
4604 allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance);
4608 /* Now allocate reload registers for anything non-optional that
4609 didn't get one yet. */
4610 for (j = 0; j < n_reloads; j++)
4612 register int r = reload_order[j];
4614 /* Ignore reloads that got marked inoperative. */
4615 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
4618 /* Skip reloads that already have a register allocated or are
4620 if (reload_reg_rtx[r] != 0 || reload_optional[r])
4623 if (! allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance))
4627 /* If that loop got all the way, we have won. */
4632 /* Loop around and try without any inheritance. */
4633 /* First undo everything done by the failed attempt
4634 to allocate with inheritance. */
4635 bcopy (save_reload_reg_rtx, reload_reg_rtx, sizeof reload_reg_rtx);
4636 bcopy (save_reload_inherited, reload_inherited, sizeof reload_inherited);
4637 bcopy (save_reload_inheritance_insn, reload_inheritance_insn,
4638 sizeof reload_inheritance_insn);
4639 bcopy (save_reload_override_in, reload_override_in,
4640 sizeof reload_override_in);
4641 bcopy (save_reload_spill_index, reload_spill_index,
4642 sizeof reload_spill_index);
4643 COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
4644 COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
4645 COPY_HARD_REG_SET (reload_reg_used_in_input,
4646 save_reload_reg_used_in_input);
4647 COPY_HARD_REG_SET (reload_reg_used_in_output,
4648 save_reload_reg_used_in_output);
4649 COPY_HARD_REG_SET (reload_reg_used_in_input_addr,
4650 save_reload_reg_used_in_input_addr);
4651 COPY_HARD_REG_SET (reload_reg_used_in_output_addr,
4652 save_reload_reg_used_in_output_addr);
4653 COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
4654 save_reload_reg_used_in_op_addr);
4657 /* If we thought we could inherit a reload, because it seemed that
4658 nothing else wanted the same reload register earlier in the insn,
4659 verify that assumption, now that all reloads have been assigned. */
4661 for (j = 0; j < n_reloads; j++)
4663 register int r = reload_order[j];
4665 if (reload_inherited[r] && reload_reg_rtx[r] != 0
4666 && ! reload_reg_free_before_p (true_regnum (reload_reg_rtx[r]),
4667 reload_when_needed[r]))
4668 reload_inherited[r] = 0;
4670 /* If we found a better place to reload from,
4671 validate it in the same fashion, if it is a reload reg. */
4672 if (reload_override_in[r]
4673 && (GET_CODE (reload_override_in[r]) == REG
4674 || GET_CODE (reload_override_in[r]) == SUBREG))
4676 int regno = true_regnum (reload_override_in[r]);
4677 if (spill_reg_order[regno] >= 0
4678 && ! reload_reg_free_before_p (regno, reload_when_needed[r]))
4679 reload_override_in[r] = 0;
4683 /* Now that reload_override_in is known valid,
4684 actually override reload_in. */
4685 for (j = 0; j < n_reloads; j++)
4686 if (reload_override_in[j])
4687 reload_in[j] = reload_override_in[j];
4689 /* If this reload won't be done because it has been cancelled or is
4690 optional and not inherited, clear reload_reg_rtx so other
4691 routines (such as subst_reloads) don't get confused. */
4692 for (j = 0; j < n_reloads; j++)
4693 if ((reload_optional[j] && ! reload_inherited[j])
4694 || (reload_in[j] == 0 && reload_out[j] == 0
4695 && ! reload_secondary_p[j]))
4696 reload_reg_rtx[j] = 0;
4698 /* Record which pseudos and which spill regs have output reloads. */
4699 for (j = 0; j < n_reloads; j++)
4701 register int r = reload_order[j];
4703 i = reload_spill_index[r];
4705 /* I is nonneg if this reload used one of the spill regs.
4706 If reload_reg_rtx[r] is 0, this is an optional reload
4707 that we opted to ignore. */
4708 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG
4709 && reload_reg_rtx[r] != 0)
4711 register int nregno = REGNO (reload_out[r]);
4714 if (nregno < FIRST_PSEUDO_REGISTER)
4715 nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
4718 reg_has_output_reload[nregno + nr] = 1;
4722 nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
4724 SET_HARD_REG_BIT (reg_is_output_reload, spill_regs[i] + nr);
4727 if (reload_when_needed[r] != RELOAD_OTHER
4728 && reload_when_needed[r] != RELOAD_FOR_OUTPUT)
4734 /* Output insns to reload values in and out of the chosen reload regs. */
4737 emit_reload_insns (insn)
4741 rtx following_insn = NEXT_INSN (insn);
4742 rtx before_insn = insn;
4743 rtx first_output_reload_insn = NEXT_INSN (insn);
4744 rtx first_other_reload_insn = insn;
4745 rtx first_operand_address_reload_insn = insn;
4747 /* Values to be put in spill_reg_store are put here first. */
4748 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
4750 /* If this is a CALL_INSN preceded by USE insns, any reload insns
4751 must go in front of the first USE insn, not in front of INSN. */
4753 if (GET_CODE (insn) == CALL_INSN && GET_CODE (PREV_INSN (insn)) == INSN
4754 && GET_CODE (PATTERN (PREV_INSN (insn))) == USE)
4755 while (GET_CODE (PREV_INSN (before_insn)) == INSN
4756 && GET_CODE (PATTERN (PREV_INSN (before_insn))) == USE)
4757 first_other_reload_insn = first_operand_address_reload_insn
4758 = before_insn = PREV_INSN (before_insn);
4760 /* Now output the instructions to copy the data into and out of the
4761 reload registers. Do these in the order that the reloads were reported,
4762 since reloads of base and index registers precede reloads of operands
4763 and the operands may need the base and index registers reloaded. */
4765 for (j = 0; j < n_reloads; j++)
4768 rtx oldequiv_reg = 0;
4769 rtx this_reload_insn = 0;
4773 if (old != 0 && ! reload_inherited[j]
4774 && ! rtx_equal_p (reload_reg_rtx[j], old)
4775 && reload_reg_rtx[j] != 0)
4777 register rtx reloadreg = reload_reg_rtx[j];
4779 enum machine_mode mode;
4783 /* Determine the mode to reload in.
4784 This is very tricky because we have three to choose from.
4785 There is the mode the insn operand wants (reload_inmode[J]).
4786 There is the mode of the reload register RELOADREG.
4787 There is the intrinsic mode of the operand, which we could find
4788 by stripping some SUBREGs.
4789 It turns out that RELOADREG's mode is irrelevant:
4790 we can change that arbitrarily.
4792 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
4793 then the reload reg may not support QImode moves, so use SImode.
4794 If foo is in memory due to spilling a pseudo reg, this is safe,
4795 because the QImode value is in the least significant part of a
4796 slot big enough for a SImode. If foo is some other sort of
4797 memory reference, then it is impossible to reload this case,
4798 so previous passes had better make sure this never happens.
4800 Then consider a one-word union which has SImode and one of its
4801 members is a float, being fetched as (SUBREG:SF union:SI).
4802 We must fetch that as SFmode because we could be loading into
4803 a float-only register. In this case OLD's mode is correct.
4805 Consider an immediate integer: it has VOIDmode. Here we need
4806 to get a mode from something else.
4808 In some cases, there is a fourth mode, the operand's
4809 containing mode. If the insn specifies a containing mode for
4810 this operand, it overrides all others.
4812 I am not sure whether the algorithm here is always right,
4813 but it does the right things in those cases. */
4815 mode = GET_MODE (old);
4816 if (mode == VOIDmode)
4817 mode = reload_inmode[j];
4818 if (reload_strict_low[j])
4819 mode = GET_MODE (SUBREG_REG (reload_in[j]));
4821 #ifdef SECONDARY_INPUT_RELOAD_CLASS
4822 /* If we need a secondary register for this operation, see if
4823 the value is already in a register in that class. Don't
4824 do this if the secondary register will be used as a scratch
4827 if (reload_secondary_reload[j] >= 0
4828 && reload_secondary_icode[j] == CODE_FOR_nothing
4831 = find_equiv_reg (old, insn,
4832 reload_reg_class[reload_secondary_reload[j]],
4833 -1, NULL_PTR, 0, mode);
4836 /* If reloading from memory, see if there is a register
4837 that already holds the same value. If so, reload from there.
4838 We can pass 0 as the reload_reg_p argument because
4839 any other reload has either already been emitted,
4840 in which case find_equiv_reg will see the reload-insn,
4841 or has yet to be emitted, in which case it doesn't matter
4842 because we will use this equiv reg right away. */
4844 if (oldequiv == 0 && optimize
4845 && (GET_CODE (old) == MEM
4846 || (GET_CODE (old) == REG
4847 && REGNO (old) >= FIRST_PSEUDO_REGISTER
4848 && reg_renumber[REGNO (old)] < 0)))
4849 oldequiv = find_equiv_reg (old, insn, GENERAL_REGS,
4850 -1, NULL_PTR, 0, mode);
4854 int regno = true_regnum (oldequiv);
4856 /* If OLDEQUIV is a spill register, don't use it for this
4857 if any other reload needs it at an earlier stage of this insn
4858 or at this stage. */
4859 if (spill_reg_order[regno] >= 0
4860 && (! reload_reg_free_p (regno, reload_when_needed[j])
4861 || ! reload_reg_free_before_p (regno,
4862 reload_when_needed[j])))
4865 /* If OLDEQUIV is not a spill register,
4866 don't use it if any other reload wants it. */
4867 if (spill_reg_order[regno] < 0)
4870 for (k = 0; k < n_reloads; k++)
4871 if (reload_reg_rtx[k] != 0 && k != j
4872 && reg_overlap_mentioned_for_reload_p (reload_reg_rtx[k],
4883 else if (GET_CODE (oldequiv) == REG)
4884 oldequiv_reg = oldequiv;
4885 else if (GET_CODE (oldequiv) == SUBREG)
4886 oldequiv_reg = SUBREG_REG (oldequiv);
4888 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
4889 then load RELOADREG from OLDEQUIV. */
4891 if (GET_MODE (reloadreg) != mode)
4892 reloadreg = gen_lowpart_common (mode, reloadreg);
4893 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
4894 oldequiv = SUBREG_REG (oldequiv);
4895 if (GET_MODE (oldequiv) != VOIDmode
4896 && mode != GET_MODE (oldequiv))
4897 oldequiv = gen_rtx (SUBREG, mode, oldequiv, 0);
4899 /* Decide where to put reload insn for this reload. */
4900 switch (reload_when_needed[j])
4902 case RELOAD_FOR_INPUT:
4904 where = first_operand_address_reload_insn;
4906 case RELOAD_FOR_INPUT_RELOAD_ADDRESS:
4907 where = first_other_reload_insn;
4909 case RELOAD_FOR_OUTPUT_RELOAD_ADDRESS:
4910 where = first_output_reload_insn;
4912 case RELOAD_FOR_OPERAND_ADDRESS:
4913 where = before_insn;
4918 /* Auto-increment addresses must be reloaded in a special way. */
4919 if (GET_CODE (oldequiv) == POST_INC
4920 || GET_CODE (oldequiv) == POST_DEC
4921 || GET_CODE (oldequiv) == PRE_INC
4922 || GET_CODE (oldequiv) == PRE_DEC)
4924 /* We are not going to bother supporting the case where a
4925 incremented register can't be copied directly from
4926 OLDEQUIV since this seems highly unlikely. */
4927 if (reload_secondary_reload[j] >= 0)
4929 /* Prevent normal processing of this reload. */
4931 /* Output a special code sequence for this case. */
4933 = inc_for_reload (reloadreg, oldequiv, reload_inc[j], where);
4936 /* If we are reloading a pseudo-register that was set by the previous
4937 insn, see if we can get rid of that pseudo-register entirely
4938 by redirecting the previous insn into our reload register. */
4940 else if (optimize && GET_CODE (old) == REG
4941 && REGNO (old) >= FIRST_PSEUDO_REGISTER
4942 && dead_or_set_p (insn, old)
4943 /* This is unsafe if some other reload
4944 uses the same reg first. */
4945 && (reload_when_needed[j] == RELOAD_OTHER
4946 || reload_when_needed[j] == RELOAD_FOR_INPUT
4947 || reload_when_needed[j] == RELOAD_FOR_INPUT_RELOAD_ADDRESS))
4949 rtx temp = PREV_INSN (insn);
4950 while (temp && GET_CODE (temp) == NOTE)
4951 temp = PREV_INSN (temp);
4953 && GET_CODE (temp) == INSN
4954 && GET_CODE (PATTERN (temp)) == SET
4955 && SET_DEST (PATTERN (temp)) == old
4956 /* Make sure we can access insn_operand_constraint. */
4957 && asm_noperands (PATTERN (temp)) < 0
4958 /* This is unsafe if prev insn rejects our reload reg. */
4959 && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
4961 /* This is unsafe if operand occurs more than once in current
4962 insn. Perhaps some occurrences aren't reloaded. */
4963 && count_occurrences (PATTERN (insn), old) == 1
4964 /* Don't risk splitting a matching pair of operands. */
4965 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
4967 /* Store into the reload register instead of the pseudo. */
4968 SET_DEST (PATTERN (temp)) = reloadreg;
4969 /* If these are the only uses of the pseudo reg,
4970 pretend for GDB it lives in the reload reg we used. */
4971 if (reg_n_deaths[REGNO (old)] == 1
4972 && reg_n_sets[REGNO (old)] == 1)
4974 reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
4975 alter_reg (REGNO (old), -1);
4981 /* We can't do that, so output an insn to load RELOADREG.
4982 Keep them in the following order:
4983 all reloads for input reload addresses,
4984 all reloads for ordinary input operands,
4985 all reloads for addresses of non-reloaded operands,
4986 the insn being reloaded,
4987 all reloads for addresses of output reloads,
4988 the output reloads. */
4991 #ifdef SECONDARY_INPUT_RELOAD_CLASS
4992 rtx second_reload_reg = 0;
4993 enum insn_code icode;
4995 /* If we have a secondary reload, pick up the secondary register
4996 and icode, if any. If OLDEQUIV and OLD are different or
4997 if this is an in-out reload, recompute whether or not we
4998 still need a secondary register and what the icode should
4999 be. If we still need a secondary register and the class or
5000 icode is different, go back to reloading from OLD if using
5001 OLDEQUIV means that we got the wrong type of register. We
5002 cannot have different class or icode due to an in-out reload
5003 because we don't make such reloads when both the input and
5004 output need secondary reload registers. */
5006 if (reload_secondary_reload[j] >= 0)
5008 int secondary_reload = reload_secondary_reload[j];
5009 rtx real_oldequiv = oldequiv;
5012 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
5013 and similarly for OLD.
5014 See comments in find_secondary_reload in reload.c. */
5015 if (GET_CODE (oldequiv) == REG
5016 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
5017 && reg_equiv_mem[REGNO (oldequiv)] != 0)
5018 real_oldequiv = reg_equiv_mem[REGNO (oldequiv)];
5020 if (GET_CODE (old) == REG
5021 && REGNO (old) >= FIRST_PSEUDO_REGISTER
5022 && reg_equiv_mem[REGNO (old)] != 0)
5023 real_old = reg_equiv_mem[REGNO (old)];
5025 second_reload_reg = reload_reg_rtx[secondary_reload];
5026 icode = reload_secondary_icode[j];
5028 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
5029 || (reload_in[j] != 0 && reload_out[j] != 0))
5031 enum reg_class new_class
5032 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
5033 mode, real_oldequiv);
5035 if (new_class == NO_REGS)
5036 second_reload_reg = 0;
5039 enum insn_code new_icode;
5040 enum machine_mode new_mode;
5042 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
5043 REGNO (second_reload_reg)))
5044 oldequiv = old, real_oldequiv = real_old;
5047 new_icode = reload_in_optab[(int) mode];
5048 if (new_icode != CODE_FOR_nothing
5049 && ((insn_operand_predicate[(int) new_icode][0]
5050 && ! ((*insn_operand_predicate[(int) new_icode][0])
5052 || (insn_operand_predicate[(int) new_icode][1]
5053 && ! ((*insn_operand_predicate[(int) new_icode][1])
5054 (real_oldequiv, mode)))))
5055 new_icode = CODE_FOR_nothing;
5057 if (new_icode == CODE_FOR_nothing)
5060 new_mode = insn_operand_mode[new_icode][2];
5062 if (GET_MODE (second_reload_reg) != new_mode)
5064 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
5066 oldequiv = old, real_oldequiv = real_old;
5069 = gen_rtx (REG, new_mode,
5070 REGNO (second_reload_reg));
5076 /* If we still need a secondary reload register, check
5077 to see if it is being used as a scratch or intermediate
5078 register and generate code appropriately. If we need
5079 a scratch register, use REAL_OLDEQUIV since the form of
5080 the insn may depend on the actual address if it is
5083 if (second_reload_reg)
5085 if (icode != CODE_FOR_nothing)
5087 reload_insn = emit_insn_before (GEN_FCN (icode)
5092 if (this_reload_insn == 0)
5093 this_reload_insn = reload_insn;
5098 /* See if we need a scratch register to load the
5099 intermediate register (a tertiary reload). */
5100 enum insn_code tertiary_icode
5101 = reload_secondary_icode[secondary_reload];
5103 if (tertiary_icode != CODE_FOR_nothing)
5105 rtx third_reload_reg
5106 = reload_reg_rtx[reload_secondary_reload[secondary_reload]];
5109 = emit_insn_before ((GEN_FCN (tertiary_icode)
5114 if (this_reload_insn == 0)
5115 this_reload_insn = reload_insn;
5120 = gen_input_reload (second_reload_reg,
5122 if (this_reload_insn == 0)
5123 this_reload_insn = reload_insn;
5124 oldequiv = second_reload_reg;
5133 reload_insn = gen_input_reload (reloadreg, oldequiv, where);
5134 if (this_reload_insn == 0)
5135 this_reload_insn = reload_insn;
5138 #if defined(SECONDARY_INPUT_RELOAD_CLASS) && defined(PRESERVE_DEATH_INFO_REGNO_P)
5139 /* We may have to make a REG_DEAD note for the secondary reload
5140 register in the insns we just made. Find the last insn that
5141 mentioned the register. */
5142 if (! special && second_reload_reg
5143 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reload_reg)))
5148 prev != PREV_INSN (this_reload_insn);
5149 prev = PREV_INSN (prev))
5150 if (GET_RTX_CLASS (GET_CODE (prev) == 'i')
5151 && reg_overlap_mentioned_for_reload_p (second_reload_reg,
5154 REG_NOTES (prev) = gen_rtx (EXPR_LIST, REG_DEAD,
5163 /* Update where to put other reload insns. */
5164 if (this_reload_insn)
5165 switch (reload_when_needed[j])
5167 case RELOAD_FOR_INPUT:
5169 if (first_other_reload_insn == first_operand_address_reload_insn)
5170 first_other_reload_insn = this_reload_insn;
5172 case RELOAD_FOR_OPERAND_ADDRESS:
5173 if (first_operand_address_reload_insn == before_insn)
5174 first_operand_address_reload_insn = this_reload_insn;
5175 if (first_other_reload_insn == before_insn)
5176 first_other_reload_insn = this_reload_insn;
5179 /* reload_inc[j] was formerly processed here. */
5182 /* Add a note saying the input reload reg
5183 dies in this insn, if anyone cares. */
5184 #ifdef PRESERVE_DEATH_INFO_REGNO_P
5186 && reload_reg_rtx[j] != old
5187 && reload_reg_rtx[j] != 0
5188 && reload_out[j] == 0
5189 && ! reload_inherited[j]
5190 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j])))
5192 register rtx reloadreg = reload_reg_rtx[j];
5195 /* We can't abort here because we need to support this for sched.c.
5196 It's not terrible to miss a REG_DEAD note, but we should try
5197 to figure out how to do this correctly. */
5198 /* The code below is incorrect for address-only reloads. */
5199 if (reload_when_needed[j] != RELOAD_OTHER
5200 && reload_when_needed[j] != RELOAD_FOR_INPUT)
5204 /* Add a death note to this insn, for an input reload. */
5206 if ((reload_when_needed[j] == RELOAD_OTHER
5207 || reload_when_needed[j] == RELOAD_FOR_INPUT)
5208 && ! dead_or_set_p (insn, reloadreg))
5210 = gen_rtx (EXPR_LIST, REG_DEAD,
5211 reloadreg, REG_NOTES (insn));
5214 /* When we inherit a reload, the last marked death of the reload reg
5215 may no longer really be a death. */
5216 if (reload_reg_rtx[j] != 0
5217 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j]))
5218 && reload_inherited[j])
5220 /* Handle inheriting an output reload.
5221 Remove the death note from the output reload insn. */
5222 if (reload_spill_index[j] >= 0
5223 && GET_CODE (reload_in[j]) == REG
5224 && spill_reg_store[reload_spill_index[j]] != 0
5225 && find_regno_note (spill_reg_store[reload_spill_index[j]],
5226 REG_DEAD, REGNO (reload_reg_rtx[j])))
5227 remove_death (REGNO (reload_reg_rtx[j]),
5228 spill_reg_store[reload_spill_index[j]]);
5229 /* Likewise for input reloads that were inherited. */
5230 else if (reload_spill_index[j] >= 0
5231 && GET_CODE (reload_in[j]) == REG
5232 && spill_reg_store[reload_spill_index[j]] == 0
5233 && reload_inheritance_insn[j] != 0
5234 && find_regno_note (reload_inheritance_insn[j], REG_DEAD,
5235 REGNO (reload_reg_rtx[j])))
5236 remove_death (REGNO (reload_reg_rtx[j]),
5237 reload_inheritance_insn[j]);
5242 /* We got this register from find_equiv_reg.
5243 Search back for its last death note and get rid of it.
5244 But don't search back too far.
5245 Don't go past a place where this reg is set,
5246 since a death note before that remains valid. */
5247 for (prev = PREV_INSN (insn);
5248 prev && GET_CODE (prev) != CODE_LABEL;
5249 prev = PREV_INSN (prev))
5250 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
5251 && dead_or_set_p (prev, reload_reg_rtx[j]))
5253 if (find_regno_note (prev, REG_DEAD,
5254 REGNO (reload_reg_rtx[j])))
5255 remove_death (REGNO (reload_reg_rtx[j]), prev);
5261 /* We might have used find_equiv_reg above to choose an alternate
5262 place from which to reload. If so, and it died, we need to remove
5263 that death and move it to one of the insns we just made. */
5265 if (oldequiv_reg != 0
5266 && PRESERVE_DEATH_INFO_REGNO_P (true_regnum (oldequiv_reg)))
5270 for (prev = PREV_INSN (insn); prev && GET_CODE (prev) != CODE_LABEL;
5271 prev = PREV_INSN (prev))
5272 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
5273 && dead_or_set_p (prev, oldequiv_reg))
5275 if (find_regno_note (prev, REG_DEAD, REGNO (oldequiv_reg)))
5277 for (prev1 = this_reload_insn;
5278 prev1; prev1 = PREV_INSN (prev1))
5279 if (GET_RTX_CLASS (GET_CODE (prev1) == 'i')
5280 && reg_overlap_mentioned_for_reload_p (oldequiv_reg,
5283 REG_NOTES (prev1) = gen_rtx (EXPR_LIST, REG_DEAD,
5288 remove_death (REGNO (oldequiv_reg), prev);
5295 /* If we are reloading a register that was recently stored in with an
5296 output-reload, see if we can prove there was
5297 actually no need to store the old value in it. */
5299 if (optimize && reload_inherited[j] && reload_spill_index[j] >= 0
5300 /* This is unsafe if some other reload uses the same reg first. */
5301 && (reload_when_needed[j] == RELOAD_OTHER
5302 || reload_when_needed[j] == RELOAD_FOR_INPUT
5303 || reload_when_needed[j] == RELOAD_FOR_INPUT_RELOAD_ADDRESS)
5304 && GET_CODE (reload_in[j]) == REG
5306 /* There doesn't seem to be any reason to restrict this to pseudos
5307 and doing so loses in the case where we are copying from a
5308 register of the wrong class. */
5309 && REGNO (reload_in[j]) >= FIRST_PSEUDO_REGISTER
5311 && spill_reg_store[reload_spill_index[j]] != 0
5312 && dead_or_set_p (insn, reload_in[j])
5313 /* This is unsafe if operand occurs more than once in current
5314 insn. Perhaps some occurrences weren't reloaded. */
5315 && count_occurrences (PATTERN (insn), reload_in[j]) == 1)
5316 delete_output_reload (insn, j,
5317 spill_reg_store[reload_spill_index[j]]);
5319 /* Input-reloading is done. Now do output-reloading,
5320 storing the value from the reload-register after the main insn
5321 if reload_out[j] is nonzero.
5323 ??? At some point we need to support handling output reloads of
5324 JUMP_INSNs or insns that set cc0. */
5325 old = reload_out[j];
5327 && reload_reg_rtx[j] != old
5328 && reload_reg_rtx[j] != 0)
5330 register rtx reloadreg = reload_reg_rtx[j];
5331 register rtx second_reloadreg = 0;
5332 rtx prev_insn = PREV_INSN (first_output_reload_insn);
5334 enum machine_mode mode;
5337 /* An output operand that dies right away does need a reload,
5338 but need not be copied from it. Show the new location in the
5340 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
5341 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
5343 XEXP (note, 0) = reload_reg_rtx[j];
5346 else if (GET_CODE (old) == SCRATCH)
5347 /* If we aren't optimizing, there won't be a REG_UNUSED note,
5348 but we don't want to make an output reload. */
5352 /* Strip off of OLD any size-increasing SUBREGs such as
5353 (SUBREG:SI foo:QI 0). */
5355 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
5356 && (GET_MODE_SIZE (GET_MODE (old))
5357 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
5358 old = SUBREG_REG (old);
5361 /* If is a JUMP_INSN, we can't support output reloads yet. */
5362 if (GET_CODE (insn) == JUMP_INSN)
5365 /* Determine the mode to reload in.
5366 See comments above (for input reloading). */
5368 mode = GET_MODE (old);
5369 if (mode == VOIDmode)
5371 /* VOIDmode should never happen for an output. */
5372 if (asm_noperands (PATTERN (insn)) < 0)
5373 /* It's the compiler's fault. */
5375 error_for_asm (insn, "output operand is constant in `asm'");
5376 /* Prevent crash--use something we know is valid. */
5378 old = gen_rtx (REG, mode, REGNO (reloadreg));
5381 /* A strict-low-part output operand needs to be reloaded
5382 in the mode of the entire value. */
5383 if (reload_strict_low[j])
5385 mode = GET_MODE (SUBREG_REG (reload_out[j]));
5386 /* Encapsulate OLD into that mode. */
5387 /* If OLD is a subreg, then strip it, since the subreg will
5388 be altered by this very reload. */
5389 while (GET_CODE (old) == SUBREG && GET_MODE (old) != mode)
5390 old = SUBREG_REG (old);
5391 if (GET_MODE (old) != VOIDmode
5392 && mode != GET_MODE (old))
5393 old = gen_rtx (SUBREG, mode, old, 0);
5396 if (GET_MODE (reloadreg) != mode)
5397 reloadreg = gen_lowpart_common (mode, reloadreg);
5399 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
5401 /* If we need two reload regs, set RELOADREG to the intermediate
5402 one, since it will be stored into OUT. We might need a secondary
5403 register only for an input reload, so check again here. */
5405 if (reload_secondary_reload[j] >= 0)
5409 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
5410 && reg_equiv_mem[REGNO (old)] != 0)
5411 real_old = reg_equiv_mem[REGNO (old)];
5413 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
5417 second_reloadreg = reloadreg;
5418 reloadreg = reload_reg_rtx[reload_secondary_reload[j]];
5420 /* See if RELOADREG is to be used as a scratch register
5421 or as an intermediate register. */
5422 if (reload_secondary_icode[j] != CODE_FOR_nothing)
5424 emit_insn_before ((GEN_FCN (reload_secondary_icode[j])
5425 (real_old, second_reloadreg,
5427 first_output_reload_insn);
5432 /* See if we need both a scratch and intermediate reload
5434 int secondary_reload = reload_secondary_reload[j];
5435 enum insn_code tertiary_icode
5436 = reload_secondary_icode[secondary_reload];
5439 if (GET_MODE (reloadreg) != mode)
5440 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
5442 if (tertiary_icode != CODE_FOR_nothing)
5445 = reload_reg_rtx[reload_secondary_reload[secondary_reload]];
5446 pat = (GEN_FCN (tertiary_icode)
5447 (reloadreg, second_reloadreg, third_reloadreg));
5449 #ifdef SECONDARY_MEMORY_NEEDED
5450 /* If we need a memory location to do the move, do it that way. */
5451 else if (GET_CODE (reloadreg) == REG
5452 && REGNO (reloadreg) < FIRST_PSEUDO_REGISTER
5453 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (reloadreg)),
5454 REGNO_REG_CLASS (REGNO (second_reloadreg)),
5455 GET_MODE (second_reloadreg)))
5457 /* Get the memory to use and rewrite both registers
5459 rtx loc = get_secondary_mem (reloadreg,
5460 GET_MODE (second_reloadreg));
5463 if (GET_MODE (loc) != GET_MODE (second_reloadreg))
5464 second_reloadreg = gen_rtx (REG, GET_MODE (loc),
5465 REGNO (second_reloadreg));
5467 if (GET_MODE (loc) != GET_MODE (reloadreg))
5468 tmp_reloadreg = gen_rtx (REG, GET_MODE (loc),
5471 tmp_reloadreg = reloadreg;
5473 emit_insn_before (gen_move_insn (loc, second_reloadreg),
5474 first_output_reload_insn);
5475 pat = gen_move_insn (tmp_reloadreg, loc);
5479 pat = gen_move_insn (reloadreg, second_reloadreg);
5481 emit_insn_before (pat, first_output_reload_insn);
5487 /* Output the last reload insn. */
5490 #ifdef SECONDARY_MEMORY_NEEDED
5491 /* If we need a memory location to do the move, do it that way. */
5492 if (GET_CODE (old) == REG && REGNO (old) < FIRST_PSEUDO_REGISTER
5493 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (old)),
5494 REGNO_REG_CLASS (REGNO (reloadreg)),
5495 GET_MODE (reloadreg)))
5497 /* Get the memory to use and rewrite both registers to
5499 rtx loc = get_secondary_mem (old, GET_MODE (reloadreg));
5501 if (GET_MODE (loc) != GET_MODE (reloadreg))
5502 reloadreg = gen_rtx (REG, GET_MODE (loc),
5505 if (GET_MODE (loc) != GET_MODE (old))
5506 old = gen_rtx (REG, GET_MODE (loc), REGNO (old));
5508 emit_insn_before (gen_move_insn (loc, reloadreg),
5509 first_output_reload_insn);
5510 emit_insn_before (gen_move_insn (old, loc),
5511 first_output_reload_insn);
5515 emit_insn_before (gen_move_insn (old, reloadreg),
5516 first_output_reload_insn);
5519 #ifdef PRESERVE_DEATH_INFO_REGNO_P
5520 /* If final will look at death notes for this reg,
5521 put one on the last output-reload insn to use it. Similarly
5522 for any secondary register. */
5523 if (PRESERVE_DEATH_INFO_REGNO_P (REGNO (reloadreg)))
5524 for (p = PREV_INSN (first_output_reload_insn);
5525 p != prev_insn; p = PREV_INSN (p))
5526 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
5527 && reg_overlap_mentioned_for_reload_p (reloadreg,
5529 REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
5530 reloadreg, REG_NOTES (p));
5532 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
5534 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reloadreg)))
5535 for (p = PREV_INSN (first_output_reload_insn);
5536 p != prev_insn; p = PREV_INSN (p))
5537 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
5538 && reg_overlap_mentioned_for_reload_p (second_reloadreg,
5540 REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
5541 second_reloadreg, REG_NOTES (p));
5544 /* Look at all insns we emitted, just to be safe. */
5545 for (p = NEXT_INSN (prev_insn); p != first_output_reload_insn;
5547 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
5549 /* If this output reload doesn't come from a spill reg,
5550 clear any memory of reloaded copies of the pseudo reg.
5551 If this output reload comes from a spill reg,
5552 reg_has_output_reload will make this do nothing. */
5553 note_stores (PATTERN (p), forget_old_reloads_1);
5555 if (reg_mentioned_p (reload_reg_rtx[j], PATTERN (p)))
5559 first_output_reload_insn = NEXT_INSN (prev_insn);
5562 if (reload_spill_index[j] >= 0)
5563 new_spill_reg_store[reload_spill_index[j]] = store_insn;
5566 /* Move death notes from INSN
5567 to output-operand-address and output reload insns. */
5568 #ifdef PRESERVE_DEATH_INFO_REGNO_P
5571 /* Loop over those insns, last ones first. */
5572 for (insn1 = PREV_INSN (following_insn); insn1 != insn;
5573 insn1 = PREV_INSN (insn1))
5574 if (GET_CODE (insn1) == INSN && GET_CODE (PATTERN (insn1)) == SET)
5576 rtx source = SET_SRC (PATTERN (insn1));
5577 rtx dest = SET_DEST (PATTERN (insn1));
5579 /* The note we will examine next. */
5580 rtx reg_notes = REG_NOTES (insn);
5581 /* The place that pointed to this note. */
5582 rtx *prev_reg_note = ®_NOTES (insn);
5584 /* If the note is for something used in the source of this
5585 reload insn, or in the output address, move the note. */
5588 rtx next_reg_notes = XEXP (reg_notes, 1);
5589 if (REG_NOTE_KIND (reg_notes) == REG_DEAD
5590 && GET_CODE (XEXP (reg_notes, 0)) == REG
5591 && ((GET_CODE (dest) != REG
5592 && reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
5594 || reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
5597 *prev_reg_note = next_reg_notes;
5598 XEXP (reg_notes, 1) = REG_NOTES (insn1);
5599 REG_NOTES (insn1) = reg_notes;
5602 prev_reg_note = &XEXP (reg_notes, 1);
5604 reg_notes = next_reg_notes;
5610 /* For all the spill regs newly reloaded in this instruction,
5611 record what they were reloaded from, so subsequent instructions
5612 can inherit the reloads.
5614 Update spill_reg_store for the reloads of this insn.
5615 Copy the elements that were updated in the loop above. */
5617 for (j = 0; j < n_reloads; j++)
5619 register int r = reload_order[j];
5620 register int i = reload_spill_index[r];
5622 /* I is nonneg if this reload used one of the spill regs.
5623 If reload_reg_rtx[r] is 0, this is an optional reload
5624 that we opted to ignore. */
5626 if (i >= 0 && reload_reg_rtx[r] != 0)
5628 /* First, clear out memory of what used to be in this spill reg.
5629 If consecutive registers are used, clear them all. */
5631 = HARD_REGNO_NREGS (spill_regs[i], GET_MODE (reload_reg_rtx[r]));
5634 for (k = 0; k < nr; k++)
5636 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] = -1;
5637 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = 0;
5640 /* Maybe the spill reg contains a copy of reload_out. */
5641 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
5643 register int nregno = REGNO (reload_out[r]);
5645 spill_reg_store[i] = new_spill_reg_store[i];
5646 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
5648 for (k = 0; k < nr; k++)
5650 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
5652 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = insn;
5656 /* Maybe the spill reg contains a copy of reload_in. */
5657 else if (reload_out[r] == 0
5658 && reload_in[r] != 0
5659 && (GET_CODE (reload_in[r]) == REG
5660 || GET_CODE (reload_in_reg[r]) == REG))
5662 register int nregno;
5663 if (GET_CODE (reload_in[r]) == REG)
5664 nregno = REGNO (reload_in[r]);
5666 nregno = REGNO (reload_in_reg[r]);
5668 /* If there are two separate reloads (one in and one out)
5669 for the same (hard or pseudo) reg,
5670 leave reg_last_reload_reg set
5671 based on the output reload.
5672 Otherwise, set it from this input reload. */
5673 if (!reg_has_output_reload[nregno]
5674 /* But don't do so if another input reload
5675 will clobber this one's value. */
5676 && reload_reg_reaches_end_p (spill_regs[i],
5677 reload_when_needed[r]))
5679 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
5681 /* Unless we inherited this reload, show we haven't
5682 recently done a store. */
5683 if (! reload_inherited[r])
5684 spill_reg_store[i] = 0;
5686 for (k = 0; k < nr; k++)
5688 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
5690 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]]
5697 /* The following if-statement was #if 0'd in 1.34 (or before...).
5698 It's reenabled in 1.35 because supposedly nothing else
5699 deals with this problem. */
5701 /* If a register gets output-reloaded from a non-spill register,
5702 that invalidates any previous reloaded copy of it.
5703 But forget_old_reloads_1 won't get to see it, because
5704 it thinks only about the original insn. So invalidate it here. */
5705 if (i < 0 && reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
5707 register int nregno = REGNO (reload_out[r]);
5708 reg_last_reload_reg[nregno] = 0;
5713 /* Emit code before BEFORE_INSN to perform an input reload of IN to RELOADREG.
5714 Returns first insn emitted. */
5717 gen_input_reload (reloadreg, in, before_insn)
5722 register rtx prev_insn = PREV_INSN (before_insn);
5724 /* How to do this reload can get quite tricky. Normally, we are being
5725 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
5726 register that didn't get a hard register. In that case we can just
5727 call emit_move_insn.
5729 We can also be asked to reload a PLUS that adds either two registers, or
5730 a register and a constant or MEM, or a MEM and a constant. This can
5731 occur during frame pointer elimination and while reloading addresses.
5732 This case is handled by trying to emit a single insn
5733 to perform the add. If it is not valid, we use a two insn sequence.
5735 Finally, we could be called to handle an 'o' constraint by putting
5736 an address into a register. In that case, we first try to do this
5737 with a named pattern of "reload_load_address". If no such pattern
5738 exists, we just emit a SET insn and hope for the best (it will normally
5739 be valid on machines that use 'o').
5741 This entire process is made complex because reload will never
5742 process the insns we generate here and so we must ensure that
5743 they will fit their constraints and also by the fact that parts of
5744 IN might be being reloaded separately and replaced with spill registers.
5745 Because of this, we are, in some sense, just guessing the right approach
5746 here. The one listed above seems to work.
5748 ??? At some point, this whole thing needs to be rethought. */
5750 if (GET_CODE (in) == PLUS
5751 && ((GET_CODE (XEXP (in, 0)) == REG
5752 && (GET_CODE (XEXP (in, 1)) == REG
5753 || CONSTANT_P (XEXP (in, 1))
5754 || GET_CODE (XEXP (in, 1)) == MEM))
5755 || (GET_CODE (XEXP (in, 0)) == MEM
5756 && CONSTANT_P (XEXP (in, 1)))))
5758 /* We need to compute the sum of what is either a register and a
5759 constant, a register and memory, a hard register and a pseudo
5760 register, or memory and a constant and put it into the reload
5761 register. The best possible way of doing this is if the machine
5762 has a three-operand ADD insn that accepts the required operands.
5764 The simplest approach is to try to generate such an insn and see if it
5765 is recognized and matches its constraints. If so, it can be used.
5767 It might be better not to actually emit the insn unless it is valid,
5768 but we need to pass the insn as an operand to `recog' and
5769 `insn_extract' and it is simpler to emit and then delete the insn if
5770 not valid than to dummy things up. */
5772 rtx op0, op1, tem, insn;
5775 op0 = find_replacement (&XEXP (in, 0));
5776 op1 = find_replacement (&XEXP (in, 1));
5778 /* Since constraint checking is strict, commutativity won't be
5779 checked, so we need to do that here to avoid spurious failure
5780 if the add instruction is two-address and the second operand
5781 of the add is the same as the reload reg, which is frequently
5782 the case. If the insn would be A = B + A, rearrange it so
5783 it will be A = A + B as constrain_operands expects. */
5785 if (GET_CODE (XEXP (in, 1)) == REG
5786 && REGNO (reloadreg) == REGNO (XEXP (in, 1)))
5787 tem = op0, op0 = op1, op1 = tem;
5789 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
5790 in = gen_rtx (PLUS, GET_MODE (in), op0, op1);
5792 insn = emit_insn_before (gen_rtx (SET, VOIDmode, reloadreg, in),
5794 code = recog_memoized (insn);
5798 insn_extract (insn);
5799 /* We want constrain operands to treat this insn strictly in
5800 its validity determination, i.e., the way it would after reload
5802 if (constrain_operands (code, 1))
5806 if (PREV_INSN (insn))
5807 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
5808 if (NEXT_INSN (insn))
5809 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
5811 /* If that failed, we must use a conservative two-insn sequence.
5812 use move to copy constant, MEM, or pseudo register to the reload
5813 register since "move" will be able to handle an arbitrary operand,
5814 unlike add which can't, in general. Then add the registers.
5816 If there is another way to do this for a specific machine, a
5817 DEFINE_PEEPHOLE should be specified that recognizes the sequence
5820 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM
5821 || (GET_CODE (op1) == REG
5822 && REGNO (op1) >= FIRST_PSEUDO_REGISTER))
5823 tem = op0, op0 = op1, op1 = tem;
5825 emit_insn_before (gen_move_insn (reloadreg, op0), before_insn);
5827 /* If OP0 and OP1 are the same, we can use RELOADREG for OP1.
5828 This fixes a problem on the 32K where the stack pointer cannot
5829 be used as an operand of an add insn. */
5831 if (rtx_equal_p (op0, op1))
5834 emit_insn_before (gen_add2_insn (reloadreg, op1), before_insn);
5837 #ifdef SECONDARY_MEMORY_NEEDED
5838 /* If we need a memory location to do the move, do it that way. */
5839 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
5840 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
5841 REGNO_REG_CLASS (REGNO (reloadreg)),
5842 GET_MODE (reloadreg)))
5844 /* Get the memory to use and rewrite both registers to its mode. */
5845 rtx loc = get_secondary_mem (in, GET_MODE (reloadreg));
5847 if (GET_MODE (loc) != GET_MODE (reloadreg))
5848 reloadreg = gen_rtx (REG, GET_MODE (loc), REGNO (reloadreg));
5850 if (GET_MODE (loc) != GET_MODE (in))
5851 in = gen_rtx (REG, GET_MODE (loc), REGNO (in));
5853 emit_insn_before (gen_move_insn (loc, in), before_insn);
5854 emit_insn_before (gen_move_insn (reloadreg, loc), before_insn);
5858 /* If IN is a simple operand, use gen_move_insn. */
5859 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
5860 emit_insn_before (gen_move_insn (reloadreg, in), before_insn);
5862 #ifdef HAVE_reload_load_address
5863 else if (HAVE_reload_load_address)
5864 emit_insn_before (gen_reload_load_address (reloadreg, in), before_insn);
5867 /* Otherwise, just write (set REGLOADREG IN) and hope for the best. */
5869 emit_insn_before (gen_rtx (SET, VOIDmode, reloadreg, in), before_insn);
5871 /* Return the first insn emitted.
5872 We can not just return PREV_INSN (before_insn), because there may have
5873 been multiple instructions emitted. Also note that gen_move_insn may
5874 emit more than one insn itself, so we can not assume that there is one
5875 insn emitted per emit_insn_before call. */
5877 return NEXT_INSN (prev_insn);
5880 /* Delete a previously made output-reload
5881 whose result we now believe is not needed.
5882 First we double-check.
5884 INSN is the insn now being processed.
5885 OUTPUT_RELOAD_INSN is the insn of the output reload.
5886 J is the reload-number for this insn. */
5889 delete_output_reload (insn, j, output_reload_insn)
5892 rtx output_reload_insn;
5896 /* Get the raw pseudo-register referred to. */
5898 rtx reg = reload_in[j];
5899 while (GET_CODE (reg) == SUBREG)
5900 reg = SUBREG_REG (reg);
5902 /* If the pseudo-reg we are reloading is no longer referenced
5903 anywhere between the store into it and here,
5904 and no jumps or labels intervene, then the value can get
5905 here through the reload reg alone.
5906 Otherwise, give up--return. */
5907 for (i1 = NEXT_INSN (output_reload_insn);
5908 i1 != insn; i1 = NEXT_INSN (i1))
5910 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
5912 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
5913 && reg_mentioned_p (reg, PATTERN (i1)))
5917 /* If this insn will store in the pseudo again,
5918 the previous store can be removed. */
5919 if (reload_out[j] == reload_in[j])
5920 delete_insn (output_reload_insn);
5922 /* See if the pseudo reg has been completely replaced
5923 with reload regs. If so, delete the store insn
5924 and forget we had a stack slot for the pseudo. */
5925 else if (reg_n_deaths[REGNO (reg)] == 1
5926 && reg_basic_block[REGNO (reg)] >= 0
5927 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
5931 /* We know that it was used only between here
5932 and the beginning of the current basic block.
5933 (We also know that the last use before INSN was
5934 the output reload we are thinking of deleting, but never mind that.)
5935 Search that range; see if any ref remains. */
5936 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
5938 rtx set = single_set (i2);
5940 /* Uses which just store in the pseudo don't count,
5941 since if they are the only uses, they are dead. */
5942 if (set != 0 && SET_DEST (set) == reg)
5944 if (GET_CODE (i2) == CODE_LABEL
5945 || GET_CODE (i2) == JUMP_INSN)
5947 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
5948 && reg_mentioned_p (reg, PATTERN (i2)))
5949 /* Some other ref remains;
5950 we can't do anything. */
5954 /* Delete the now-dead stores into this pseudo. */
5955 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
5957 rtx set = single_set (i2);
5959 if (set != 0 && SET_DEST (set) == reg)
5961 if (GET_CODE (i2) == CODE_LABEL
5962 || GET_CODE (i2) == JUMP_INSN)
5966 /* For the debugging info,
5967 say the pseudo lives in this reload reg. */
5968 reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
5969 alter_reg (REGNO (reg), -1);
5974 /* Output reload-insns to reload VALUE into RELOADREG.
5975 VALUE is an autoincrement or autodecrement RTX whose operand
5976 is a register or memory location;
5977 so reloading involves incrementing that location.
5979 INC_AMOUNT is the number to increment or decrement by (always positive).
5980 This cannot be deduced from VALUE.
5982 INSN is the insn before which the new insns should be emitted.
5984 The return value is the first of the insns emitted. */
5987 inc_for_reload (reloadreg, value, inc_amount, insn)
5993 /* REG or MEM to be copied and incremented. */
5994 rtx incloc = XEXP (value, 0);
5995 /* Nonzero if increment after copying. */
5996 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
5997 rtx prev = PREV_INSN (insn);
6002 /* No hard register is equivalent to this register after
6003 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
6004 we could inc/dec that register as well (maybe even using it for
6005 the source), but I'm not sure it's worth worrying about. */
6006 if (GET_CODE (incloc) == REG)
6007 reg_last_reload_reg[REGNO (incloc)] = 0;
6009 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
6010 inc_amount = - inc_amount;
6012 inc = GEN_INT (inc_amount);
6014 /* If this is post-increment, first copy the location to the reload reg. */
6016 emit_insn_before (gen_move_insn (reloadreg, incloc), insn);
6018 /* See if we can directly increment INCLOC. Use a method similar to that
6019 in gen_input_reload. */
6021 add_insn = emit_insn_before (gen_rtx (SET, VOIDmode, incloc,
6022 gen_rtx (PLUS, GET_MODE (incloc),
6023 incloc, inc)), insn);
6025 code = recog_memoized (add_insn);
6028 insn_extract (add_insn);
6029 if (constrain_operands (code, 1))
6031 /* If this is a pre-increment and we have incremented the value
6032 where it lives, copy the incremented value to RELOADREG to
6033 be used as an address. */
6036 emit_insn_before (gen_move_insn (reloadreg, incloc), insn);
6037 return NEXT_INSN (prev);
6041 if (PREV_INSN (add_insn))
6042 NEXT_INSN (PREV_INSN (add_insn)) = NEXT_INSN (add_insn);
6043 if (NEXT_INSN (add_insn))
6044 PREV_INSN (NEXT_INSN (add_insn)) = PREV_INSN (add_insn);
6046 /* If couldn't do the increment directly, must increment in RELOADREG.
6047 The way we do this depends on whether this is pre- or post-increment.
6048 For pre-increment, copy INCLOC to the reload register, increment it
6049 there, then save back. */
6053 emit_insn_before (gen_move_insn (reloadreg, incloc), insn);
6054 emit_insn_before (gen_add2_insn (reloadreg, inc), insn);
6055 emit_insn_before (gen_move_insn (incloc, reloadreg), insn);
6060 Because this might be a jump insn or a compare, and because RELOADREG
6061 may not be available after the insn in an input reload, we must do
6062 the incrementation before the insn being reloaded for.
6064 We have already copied INCLOC to RELOADREG. Increment the copy in
6065 RELOADREG, save that back, then decrement RELOADREG so it has
6066 the original value. */
6068 emit_insn_before (gen_add2_insn (reloadreg, inc), insn);
6069 emit_insn_before (gen_move_insn (incloc, reloadreg), insn);
6070 emit_insn_before (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)),
6074 return NEXT_INSN (prev);
6077 /* Return 1 if we are certain that the constraint-string STRING allows
6078 the hard register REG. Return 0 if we can't be sure of this. */
6081 constraint_accepts_reg_p (string, reg)
6086 int regno = true_regnum (reg);
6089 /* Initialize for first alternative. */
6091 /* Check that each alternative contains `g' or `r'. */
6093 switch (c = *string++)
6096 /* If an alternative lacks `g' or `r', we lose. */
6099 /* If an alternative lacks `g' or `r', we lose. */
6102 /* Initialize for next alternative. */
6107 /* Any general reg wins for this alternative. */
6108 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
6112 /* Any reg in specified class wins for this alternative. */
6114 enum reg_class class = REG_CLASS_FROM_LETTER (c);
6116 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
6122 /* Return the number of places FIND appears within X, but don't count
6123 an occurrence if some SET_DEST is FIND. */
6126 count_occurrences (x, find)
6127 register rtx x, find;
6130 register enum rtx_code code;
6131 register char *format_ptr;
6139 code = GET_CODE (x);
6154 if (SET_DEST (x) == find)
6155 return count_occurrences (SET_SRC (x), find);
6159 format_ptr = GET_RTX_FORMAT (code);
6162 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6164 switch (*format_ptr++)
6167 count += count_occurrences (XEXP (x, i), find);
6171 if (XVEC (x, i) != NULL)
6173 for (j = 0; j < XVECLEN (x, i); j++)
6174 count += count_occurrences (XVECEXP (x, i, j), find);
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