1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "addresses.h"
39 #include "basic-block.h"
52 /* This file contains the reload pass of the compiler, which is
53 run after register allocation has been done. It checks that
54 each insn is valid (operands required to be in registers really
55 are in registers of the proper class) and fixes up invalid ones
56 by copying values temporarily into registers for the insns
59 The results of register allocation are described by the vector
60 reg_renumber; the insns still contain pseudo regs, but reg_renumber
61 can be used to find which hard reg, if any, a pseudo reg is in.
63 The technique we always use is to free up a few hard regs that are
64 called ``reload regs'', and for each place where a pseudo reg
65 must be in a hard reg, copy it temporarily into one of the reload regs.
67 Reload regs are allocated locally for every instruction that needs
68 reloads. When there are pseudos which are allocated to a register that
69 has been chosen as a reload reg, such pseudos must be ``spilled''.
70 This means that they go to other hard regs, or to stack slots if no other
71 available hard regs can be found. Spilling can invalidate more
72 insns, requiring additional need for reloads, so we must keep checking
73 until the process stabilizes.
75 For machines with different classes of registers, we must keep track
76 of the register class needed for each reload, and make sure that
77 we allocate enough reload registers of each class.
79 The file reload.c contains the code that checks one insn for
80 validity and reports the reloads that it needs. This file
81 is in charge of scanning the entire rtl code, accumulating the
82 reload needs, spilling, assigning reload registers to use for
83 fixing up each insn, and generating the new insns to copy values
84 into the reload registers. */
86 /* During reload_as_needed, element N contains a REG rtx for the hard reg
87 into which reg N has been reloaded (perhaps for a previous insn). */
88 static rtx *reg_last_reload_reg;
90 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
91 for an output reload that stores into reg N. */
92 static regset_head reg_has_output_reload;
94 /* Indicates which hard regs are reload-registers for an output reload
95 in the current insn. */
96 static HARD_REG_SET reg_is_output_reload;
98 /* Element N is the constant value to which pseudo reg N is equivalent,
99 or zero if pseudo reg N is not equivalent to a constant.
100 find_reloads looks at this in order to replace pseudo reg N
101 with the constant it stands for. */
102 rtx *reg_equiv_constant;
104 /* Element N is an invariant value to which pseudo reg N is equivalent.
105 eliminate_regs_in_insn uses this to replace pseudos in particular
107 rtx *reg_equiv_invariant;
109 /* Element N is a memory location to which pseudo reg N is equivalent,
110 prior to any register elimination (such as frame pointer to stack
111 pointer). Depending on whether or not it is a valid address, this value
112 is transferred to either reg_equiv_address or reg_equiv_mem. */
113 rtx *reg_equiv_memory_loc;
115 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
116 collector can keep track of what is inside. */
117 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
119 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
120 This is used when the address is not valid as a memory address
121 (because its displacement is too big for the machine.) */
122 rtx *reg_equiv_address;
124 /* Element N is the memory slot to which pseudo reg N is equivalent,
125 or zero if pseudo reg N is not equivalent to a memory slot. */
128 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
129 alternate representations of the location of pseudo reg N. */
130 rtx *reg_equiv_alt_mem_list;
132 /* Widest width in which each pseudo reg is referred to (via subreg). */
133 static unsigned int *reg_max_ref_width;
135 /* Element N is the list of insns that initialized reg N from its equivalent
136 constant or memory slot. */
138 int reg_equiv_init_size;
140 /* Vector to remember old contents of reg_renumber before spilling. */
141 static short *reg_old_renumber;
143 /* During reload_as_needed, element N contains the last pseudo regno reloaded
144 into hard register N. If that pseudo reg occupied more than one register,
145 reg_reloaded_contents points to that pseudo for each spill register in
146 use; all of these must remain set for an inheritance to occur. */
147 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
149 /* During reload_as_needed, element N contains the insn for which
150 hard register N was last used. Its contents are significant only
151 when reg_reloaded_valid is set for this register. */
152 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
154 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
155 static HARD_REG_SET reg_reloaded_valid;
156 /* Indicate if the register was dead at the end of the reload.
157 This is only valid if reg_reloaded_contents is set and valid. */
158 static HARD_REG_SET reg_reloaded_dead;
160 /* Indicate whether the register's current value is one that is not
161 safe to retain across a call, even for registers that are normally
162 call-saved. This is only meaningful for members of reg_reloaded_valid. */
163 static HARD_REG_SET reg_reloaded_call_part_clobbered;
165 /* Number of spill-regs so far; number of valid elements of spill_regs. */
168 /* In parallel with spill_regs, contains REG rtx's for those regs.
169 Holds the last rtx used for any given reg, or 0 if it has never
170 been used for spilling yet. This rtx is reused, provided it has
172 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
174 /* In parallel with spill_regs, contains nonzero for a spill reg
175 that was stored after the last time it was used.
176 The precise value is the insn generated to do the store. */
177 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
179 /* This is the register that was stored with spill_reg_store. This is a
180 copy of reload_out / reload_out_reg when the value was stored; if
181 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
182 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
184 /* This table is the inverse mapping of spill_regs:
185 indexed by hard reg number,
186 it contains the position of that reg in spill_regs,
187 or -1 for something that is not in spill_regs.
189 ?!? This is no longer accurate. */
190 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
192 /* This reg set indicates registers that can't be used as spill registers for
193 the currently processed insn. These are the hard registers which are live
194 during the insn, but not allocated to pseudos, as well as fixed
196 static HARD_REG_SET bad_spill_regs;
198 /* These are the hard registers that can't be used as spill register for any
199 insn. This includes registers used for user variables and registers that
200 we can't eliminate. A register that appears in this set also can't be used
201 to retry register allocation. */
202 static HARD_REG_SET bad_spill_regs_global;
204 /* Describes order of use of registers for reloading
205 of spilled pseudo-registers. `n_spills' is the number of
206 elements that are actually valid; new ones are added at the end.
208 Both spill_regs and spill_reg_order are used on two occasions:
209 once during find_reload_regs, where they keep track of the spill registers
210 for a single insn, but also during reload_as_needed where they show all
211 the registers ever used by reload. For the latter case, the information
212 is calculated during finish_spills. */
213 static short spill_regs[FIRST_PSEUDO_REGISTER];
215 /* This vector of reg sets indicates, for each pseudo, which hard registers
216 may not be used for retrying global allocation because the register was
217 formerly spilled from one of them. If we allowed reallocating a pseudo to
218 a register that it was already allocated to, reload might not
220 static HARD_REG_SET *pseudo_previous_regs;
222 /* This vector of reg sets indicates, for each pseudo, which hard
223 registers may not be used for retrying global allocation because they
224 are used as spill registers during one of the insns in which the
226 static HARD_REG_SET *pseudo_forbidden_regs;
228 /* All hard regs that have been used as spill registers for any insn are
229 marked in this set. */
230 static HARD_REG_SET used_spill_regs;
232 /* Index of last register assigned as a spill register. We allocate in
233 a round-robin fashion. */
234 static int last_spill_reg;
236 /* Nonzero if indirect addressing is supported on the machine; this means
237 that spilling (REG n) does not require reloading it into a register in
238 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
239 value indicates the level of indirect addressing supported, e.g., two
240 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
242 static char spill_indirect_levels;
244 /* Nonzero if indirect addressing is supported when the innermost MEM is
245 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
246 which these are valid is the same as spill_indirect_levels, above. */
247 char indirect_symref_ok;
249 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
250 char double_reg_address_ok;
252 /* Record the stack slot for each spilled hard register. */
253 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
255 /* Width allocated so far for that stack slot. */
256 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
258 /* Record which pseudos needed to be spilled. */
259 static regset_head spilled_pseudos;
261 /* Record which pseudos changed their allocation in finish_spills. */
262 static regset_head changed_allocation_pseudos;
264 /* Used for communication between order_regs_for_reload and count_pseudo.
265 Used to avoid counting one pseudo twice. */
266 static regset_head pseudos_counted;
268 /* First uid used by insns created by reload in this function.
269 Used in find_equiv_reg. */
270 int reload_first_uid;
272 /* Flag set by local-alloc or global-alloc if anything is live in
273 a call-clobbered reg across calls. */
274 int caller_save_needed;
276 /* Set to 1 while reload_as_needed is operating.
277 Required by some machines to handle any generated moves differently. */
278 int reload_in_progress = 0;
280 /* These arrays record the insn_code of insns that may be needed to
281 perform input and output reloads of special objects. They provide a
282 place to pass a scratch register. */
283 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
284 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
286 /* This obstack is used for allocation of rtl during register elimination.
287 The allocated storage can be freed once find_reloads has processed the
289 static struct obstack reload_obstack;
291 /* Points to the beginning of the reload_obstack. All insn_chain structures
292 are allocated first. */
293 static char *reload_startobj;
295 /* The point after all insn_chain structures. Used to quickly deallocate
296 memory allocated in copy_reloads during calculate_needs_all_insns. */
297 static char *reload_firstobj;
299 /* This points before all local rtl generated by register elimination.
300 Used to quickly free all memory after processing one insn. */
301 static char *reload_insn_firstobj;
303 /* List of insn_chain instructions, one for every insn that reload needs to
305 struct insn_chain *reload_insn_chain;
307 /* List of all insns needing reloads. */
308 static struct insn_chain *insns_need_reload;
310 /* This structure is used to record information about register eliminations.
311 Each array entry describes one possible way of eliminating a register
312 in favor of another. If there is more than one way of eliminating a
313 particular register, the most preferred should be specified first. */
317 int from; /* Register number to be eliminated. */
318 int to; /* Register number used as replacement. */
319 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
320 int can_eliminate; /* Nonzero if this elimination can be done. */
321 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
322 insns made by reload. */
323 HOST_WIDE_INT offset; /* Current offset between the two regs. */
324 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
325 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
326 rtx from_rtx; /* REG rtx for the register to be eliminated.
327 We cannot simply compare the number since
328 we might then spuriously replace a hard
329 register corresponding to a pseudo
330 assigned to the reg to be eliminated. */
331 rtx to_rtx; /* REG rtx for the replacement. */
334 static struct elim_table *reg_eliminate = 0;
336 /* This is an intermediate structure to initialize the table. It has
337 exactly the members provided by ELIMINABLE_REGS. */
338 static const struct elim_table_1
342 } reg_eliminate_1[] =
344 /* If a set of eliminable registers was specified, define the table from it.
345 Otherwise, default to the normal case of the frame pointer being
346 replaced by the stack pointer. */
348 #ifdef ELIMINABLE_REGS
351 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
354 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
356 /* Record the number of pending eliminations that have an offset not equal
357 to their initial offset. If nonzero, we use a new copy of each
358 replacement result in any insns encountered. */
359 int num_not_at_initial_offset;
361 /* Count the number of registers that we may be able to eliminate. */
362 static int num_eliminable;
363 /* And the number of registers that are equivalent to a constant that
364 can be eliminated to frame_pointer / arg_pointer + constant. */
365 static int num_eliminable_invariants;
367 /* For each label, we record the offset of each elimination. If we reach
368 a label by more than one path and an offset differs, we cannot do the
369 elimination. This information is indexed by the difference of the
370 number of the label and the first label number. We can't offset the
371 pointer itself as this can cause problems on machines with segmented
372 memory. The first table is an array of flags that records whether we
373 have yet encountered a label and the second table is an array of arrays,
374 one entry in the latter array for each elimination. */
376 static int first_label_num;
377 static char *offsets_known_at;
378 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
380 /* Number of labels in the current function. */
382 static int num_labels;
384 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
385 static void maybe_fix_stack_asms (void);
386 static void copy_reloads (struct insn_chain *);
387 static void calculate_needs_all_insns (int);
388 static int find_reg (struct insn_chain *, int);
389 static void find_reload_regs (struct insn_chain *);
390 static void select_reload_regs (void);
391 static void delete_caller_save_insns (void);
393 static void spill_failure (rtx, enum reg_class);
394 static void count_spilled_pseudo (int, int, int);
395 static void delete_dead_insn (rtx);
396 static void alter_reg (int, int, bool);
397 static void set_label_offsets (rtx, rtx, int);
398 static void check_eliminable_occurrences (rtx);
399 static void elimination_effects (rtx, enum machine_mode);
400 static int eliminate_regs_in_insn (rtx, int);
401 static void update_eliminable_offsets (void);
402 static void mark_not_eliminable (rtx, const_rtx, void *);
403 static void set_initial_elim_offsets (void);
404 static bool verify_initial_elim_offsets (void);
405 static void set_initial_label_offsets (void);
406 static void set_offsets_for_label (rtx);
407 static void init_elim_table (void);
408 static void update_eliminables (HARD_REG_SET *);
409 static void spill_hard_reg (unsigned int, int);
410 static int finish_spills (int);
411 static void scan_paradoxical_subregs (rtx);
412 static void count_pseudo (int);
413 static void order_regs_for_reload (struct insn_chain *);
414 static void reload_as_needed (int);
415 static void forget_old_reloads_1 (rtx, const_rtx, void *);
416 static void forget_marked_reloads (regset);
417 static int reload_reg_class_lower (const void *, const void *);
418 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
420 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
422 static int reload_reg_free_p (unsigned int, int, enum reload_type);
423 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
425 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
427 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
428 static int allocate_reload_reg (struct insn_chain *, int, int);
429 static int conflicts_with_override (rtx);
430 static void failed_reload (rtx, int);
431 static int set_reload_reg (int, int);
432 static void choose_reload_regs_init (struct insn_chain *, rtx *);
433 static void choose_reload_regs (struct insn_chain *);
434 static void merge_assigned_reloads (rtx);
435 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
437 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
439 static void do_input_reload (struct insn_chain *, struct reload *, int);
440 static void do_output_reload (struct insn_chain *, struct reload *, int);
441 static void emit_reload_insns (struct insn_chain *);
442 static void delete_output_reload (rtx, int, int, rtx);
443 static void delete_address_reloads (rtx, rtx);
444 static void delete_address_reloads_1 (rtx, rtx, rtx);
445 static rtx inc_for_reload (rtx, rtx, rtx, int);
447 static void add_auto_inc_notes (rtx, rtx);
449 static void copy_eh_notes (rtx, rtx);
450 static void substitute (rtx *, const_rtx, rtx);
451 static bool gen_reload_chain_without_interm_reg_p (int, int);
452 static int reloads_conflict (int, int);
453 static rtx gen_reload (rtx, rtx, int, enum reload_type);
454 static rtx emit_insn_if_valid_for_reload (rtx);
456 /* Initialize the reload pass. This is called at the beginning of compilation
457 and may be called again if the target is reinitialized. */
464 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
465 Set spill_indirect_levels to the number of levels such addressing is
466 permitted, zero if it is not permitted at all. */
469 = gen_rtx_MEM (Pmode,
472 LAST_VIRTUAL_REGISTER + 1),
474 spill_indirect_levels = 0;
476 while (memory_address_p (QImode, tem))
478 spill_indirect_levels++;
479 tem = gen_rtx_MEM (Pmode, tem);
482 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
484 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
485 indirect_symref_ok = memory_address_p (QImode, tem);
487 /* See if reg+reg is a valid (and offsettable) address. */
489 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
491 tem = gen_rtx_PLUS (Pmode,
492 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
493 gen_rtx_REG (Pmode, i));
495 /* This way, we make sure that reg+reg is an offsettable address. */
496 tem = plus_constant (tem, 4);
498 if (memory_address_p (QImode, tem))
500 double_reg_address_ok = 1;
505 /* Initialize obstack for our rtl allocation. */
506 gcc_obstack_init (&reload_obstack);
507 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
509 INIT_REG_SET (&spilled_pseudos);
510 INIT_REG_SET (&changed_allocation_pseudos);
511 INIT_REG_SET (&pseudos_counted);
514 /* List of insn chains that are currently unused. */
515 static struct insn_chain *unused_insn_chains = 0;
517 /* Allocate an empty insn_chain structure. */
519 new_insn_chain (void)
521 struct insn_chain *c;
523 if (unused_insn_chains == 0)
525 c = XOBNEW (&reload_obstack, struct insn_chain);
526 INIT_REG_SET (&c->live_throughout);
527 INIT_REG_SET (&c->dead_or_set);
531 c = unused_insn_chains;
532 unused_insn_chains = c->next;
534 c->is_caller_save_insn = 0;
535 c->need_operand_change = 0;
541 /* Small utility function to set all regs in hard reg set TO which are
542 allocated to pseudos in regset FROM. */
545 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
548 reg_set_iterator rsi;
550 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
552 int r = reg_renumber[regno];
556 /* reload_combine uses the information from DF_LIVE_IN,
557 which might still contain registers that have not
558 actually been allocated since they have an
560 gcc_assert (ira_conflicts_p || reload_completed);
563 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
567 /* Replace all pseudos found in LOC with their corresponding
571 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
584 unsigned int regno = REGNO (x);
586 if (regno < FIRST_PSEUDO_REGISTER)
589 x = eliminate_regs (x, mem_mode, usage);
593 replace_pseudos_in (loc, mem_mode, usage);
597 if (reg_equiv_constant[regno])
598 *loc = reg_equiv_constant[regno];
599 else if (reg_equiv_mem[regno])
600 *loc = reg_equiv_mem[regno];
601 else if (reg_equiv_address[regno])
602 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
605 gcc_assert (!REG_P (regno_reg_rtx[regno])
606 || REGNO (regno_reg_rtx[regno]) != regno);
607 *loc = regno_reg_rtx[regno];
612 else if (code == MEM)
614 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
618 /* Process each of our operands recursively. */
619 fmt = GET_RTX_FORMAT (code);
620 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
622 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
623 else if (*fmt == 'E')
624 for (j = 0; j < XVECLEN (x, i); j++)
625 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
628 /* Determine if the current function has an exception receiver block
629 that reaches the exit block via non-exceptional edges */
632 has_nonexceptional_receiver (void)
636 basic_block *tos, *worklist, bb;
638 /* If we're not optimizing, then just err on the safe side. */
642 /* First determine which blocks can reach exit via normal paths. */
643 tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1);
646 bb->flags &= ~BB_REACHABLE;
648 /* Place the exit block on our worklist. */
649 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
650 *tos++ = EXIT_BLOCK_PTR;
652 /* Iterate: find everything reachable from what we've already seen. */
653 while (tos != worklist)
657 FOR_EACH_EDGE (e, ei, bb->preds)
658 if (!(e->flags & EDGE_ABNORMAL))
660 basic_block src = e->src;
662 if (!(src->flags & BB_REACHABLE))
664 src->flags |= BB_REACHABLE;
671 /* Now see if there's a reachable block with an exceptional incoming
674 if (bb->flags & BB_REACHABLE)
675 FOR_EACH_EDGE (e, ei, bb->preds)
676 if (e->flags & EDGE_ABNORMAL)
679 /* No exceptional block reached exit unexceptionally. */
684 /* Global variables used by reload and its subroutines. */
686 /* Set during calculate_needs if an insn needs register elimination. */
687 static int something_needs_elimination;
688 /* Set during calculate_needs if an insn needs an operand changed. */
689 static int something_needs_operands_changed;
691 /* Nonzero means we couldn't get enough spill regs. */
694 /* Temporary array of pseudo-register number. */
695 static int *temp_pseudo_reg_arr;
697 /* Main entry point for the reload pass.
699 FIRST is the first insn of the function being compiled.
701 GLOBAL nonzero means we were called from global_alloc
702 and should attempt to reallocate any pseudoregs that we
703 displace from hard regs we will use for reloads.
704 If GLOBAL is zero, we do not have enough information to do that,
705 so any pseudo reg that is spilled must go to the stack.
707 Return value is nonzero if reload failed
708 and we must not do any more for this function. */
711 reload (rtx first, int global)
715 struct elim_table *ep;
718 /* Make sure even insns with volatile mem refs are recognizable. */
723 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
725 /* Make sure that the last insn in the chain
726 is not something that needs reloading. */
727 emit_note (NOTE_INSN_DELETED);
729 /* Enable find_equiv_reg to distinguish insns made by reload. */
730 reload_first_uid = get_max_uid ();
732 #ifdef SECONDARY_MEMORY_NEEDED
733 /* Initialize the secondary memory table. */
734 clear_secondary_mem ();
737 /* We don't have a stack slot for any spill reg yet. */
738 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
739 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
741 /* Initialize the save area information for caller-save, in case some
745 /* Compute which hard registers are now in use
746 as homes for pseudo registers.
747 This is done here rather than (eg) in global_alloc
748 because this point is reached even if not optimizing. */
749 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
752 /* A function that has a nonlocal label that can reach the exit
753 block via non-exceptional paths must save all call-saved
755 if (cfun->has_nonlocal_label
756 && has_nonexceptional_receiver ())
757 crtl->saves_all_registers = 1;
759 if (crtl->saves_all_registers)
760 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
761 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
762 df_set_regs_ever_live (i, true);
764 /* Find all the pseudo registers that didn't get hard regs
765 but do have known equivalent constants or memory slots.
766 These include parameters (known equivalent to parameter slots)
767 and cse'd or loop-moved constant memory addresses.
769 Record constant equivalents in reg_equiv_constant
770 so they will be substituted by find_reloads.
771 Record memory equivalents in reg_mem_equiv so they can
772 be substituted eventually by altering the REG-rtx's. */
774 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
775 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
776 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
777 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
778 reg_equiv_address = XCNEWVEC (rtx, max_regno);
779 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
780 reg_old_renumber = XCNEWVEC (short, max_regno);
781 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
782 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
783 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
785 CLEAR_HARD_REG_SET (bad_spill_regs_global);
787 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
788 to. Also find all paradoxical subregs and find largest such for
791 num_eliminable_invariants = 0;
792 for (insn = first; insn; insn = NEXT_INSN (insn))
794 rtx set = single_set (insn);
796 /* We may introduce USEs that we want to remove at the end, so
797 we'll mark them with QImode. Make sure there are no
798 previously-marked insns left by say regmove. */
799 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
800 && GET_MODE (insn) != VOIDmode)
801 PUT_MODE (insn, VOIDmode);
804 scan_paradoxical_subregs (PATTERN (insn));
806 if (set != 0 && REG_P (SET_DEST (set)))
808 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
814 i = REGNO (SET_DEST (set));
817 if (i <= LAST_VIRTUAL_REGISTER)
820 if (! function_invariant_p (x)
822 /* A function invariant is often CONSTANT_P but may
823 include a register. We promise to only pass
824 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
826 && LEGITIMATE_PIC_OPERAND_P (x)))
828 /* It can happen that a REG_EQUIV note contains a MEM
829 that is not a legitimate memory operand. As later
830 stages of reload assume that all addresses found
831 in the reg_equiv_* arrays were originally legitimate,
832 we ignore such REG_EQUIV notes. */
833 if (memory_operand (x, VOIDmode))
835 /* Always unshare the equivalence, so we can
836 substitute into this insn without touching the
838 reg_equiv_memory_loc[i] = copy_rtx (x);
840 else if (function_invariant_p (x))
842 if (GET_CODE (x) == PLUS)
844 /* This is PLUS of frame pointer and a constant,
845 and might be shared. Unshare it. */
846 reg_equiv_invariant[i] = copy_rtx (x);
847 num_eliminable_invariants++;
849 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
851 reg_equiv_invariant[i] = x;
852 num_eliminable_invariants++;
854 else if (LEGITIMATE_CONSTANT_P (x))
855 reg_equiv_constant[i] = x;
858 reg_equiv_memory_loc[i]
859 = force_const_mem (GET_MODE (SET_DEST (set)), x);
860 if (! reg_equiv_memory_loc[i])
861 reg_equiv_init[i] = NULL_RTX;
866 reg_equiv_init[i] = NULL_RTX;
871 reg_equiv_init[i] = NULL_RTX;
876 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
877 if (reg_equiv_init[i])
879 fprintf (dump_file, "init_insns for %u: ", i);
880 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
881 fprintf (dump_file, "\n");
886 first_label_num = get_first_label_num ();
887 num_labels = max_label_num () - first_label_num;
889 /* Allocate the tables used to store offset information at labels. */
890 /* We used to use alloca here, but the size of what it would try to
891 allocate would occasionally cause it to exceed the stack limit and
892 cause a core dump. */
893 offsets_known_at = XNEWVEC (char, num_labels);
894 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
896 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
897 stack slots to the pseudos that lack hard regs or equivalents.
898 Do not touch virtual registers. */
900 temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
901 for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
902 temp_pseudo_reg_arr[n++] = i;
905 /* Ask IRA to order pseudo-registers for better stack slot
907 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
909 for (i = 0; i < n; i++)
910 alter_reg (temp_pseudo_reg_arr[i], -1, false);
912 /* If we have some registers we think can be eliminated, scan all insns to
913 see if there is an insn that sets one of these registers to something
914 other than itself plus a constant. If so, the register cannot be
915 eliminated. Doing this scan here eliminates an extra pass through the
916 main reload loop in the most common case where register elimination
918 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
920 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
922 maybe_fix_stack_asms ();
924 insns_need_reload = 0;
925 something_needs_elimination = 0;
927 /* Initialize to -1, which means take the first spill register. */
930 /* Spill any hard regs that we know we can't eliminate. */
931 CLEAR_HARD_REG_SET (used_spill_regs);
932 /* There can be multiple ways to eliminate a register;
933 they should be listed adjacently.
934 Elimination for any register fails only if all possible ways fail. */
935 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
938 int can_eliminate = 0;
941 can_eliminate |= ep->can_eliminate;
944 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
946 spill_hard_reg (from, 1);
949 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
950 if (frame_pointer_needed)
951 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
953 finish_spills (global);
955 /* From now on, we may need to generate moves differently. We may also
956 allow modifications of insns which cause them to not be recognized.
957 Any such modifications will be cleaned up during reload itself. */
958 reload_in_progress = 1;
960 /* This loop scans the entire function each go-round
961 and repeats until one repetition spills no additional hard regs. */
964 int something_changed;
966 HOST_WIDE_INT starting_frame_size;
968 starting_frame_size = get_frame_size ();
970 set_initial_elim_offsets ();
971 set_initial_label_offsets ();
973 /* For each pseudo register that has an equivalent location defined,
974 try to eliminate any eliminable registers (such as the frame pointer)
975 assuming initial offsets for the replacement register, which
978 If the resulting location is directly addressable, substitute
979 the MEM we just got directly for the old REG.
981 If it is not addressable but is a constant or the sum of a hard reg
982 and constant, it is probably not addressable because the constant is
983 out of range, in that case record the address; we will generate
984 hairy code to compute the address in a register each time it is
985 needed. Similarly if it is a hard register, but one that is not
986 valid as an address register.
988 If the location is not addressable, but does not have one of the
989 above forms, assign a stack slot. We have to do this to avoid the
990 potential of producing lots of reloads if, e.g., a location involves
991 a pseudo that didn't get a hard register and has an equivalent memory
992 location that also involves a pseudo that didn't get a hard register.
994 Perhaps at some point we will improve reload_when_needed handling
995 so this problem goes away. But that's very hairy. */
997 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
998 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
1000 rtx x = eliminate_regs (reg_equiv_memory_loc[i], VOIDmode,
1003 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
1005 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
1006 else if (CONSTANT_P (XEXP (x, 0))
1007 || (REG_P (XEXP (x, 0))
1008 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
1009 || (GET_CODE (XEXP (x, 0)) == PLUS
1010 && REG_P (XEXP (XEXP (x, 0), 0))
1011 && (REGNO (XEXP (XEXP (x, 0), 0))
1012 < FIRST_PSEUDO_REGISTER)
1013 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
1014 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
1017 /* Make a new stack slot. Then indicate that something
1018 changed so we go back and recompute offsets for
1019 eliminable registers because the allocation of memory
1020 below might change some offset. reg_equiv_{mem,address}
1021 will be set up for this pseudo on the next pass around
1023 reg_equiv_memory_loc[i] = 0;
1024 reg_equiv_init[i] = 0;
1025 alter_reg (i, -1, true);
1029 if (caller_save_needed)
1030 setup_save_areas ();
1032 /* If we allocated another stack slot, redo elimination bookkeeping. */
1033 if (starting_frame_size != get_frame_size ())
1035 if (starting_frame_size && crtl->stack_alignment_needed)
1037 /* If we have a stack frame, we must align it now. The
1038 stack size may be a part of the offset computation for
1039 register elimination. So if this changes the stack size,
1040 then repeat the elimination bookkeeping. We don't
1041 realign when there is no stack, as that will cause a
1042 stack frame when none is needed should
1043 STARTING_FRAME_OFFSET not be already aligned to
1045 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
1046 if (starting_frame_size != get_frame_size ())
1050 if (caller_save_needed)
1052 save_call_clobbered_regs ();
1053 /* That might have allocated new insn_chain structures. */
1054 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1057 calculate_needs_all_insns (global);
1059 if (! ira_conflicts_p)
1060 /* Don't do it for IRA. We need this info because we don't
1061 change live_throughout and dead_or_set for chains when IRA
1063 CLEAR_REG_SET (&spilled_pseudos);
1067 something_changed = 0;
1069 /* If we allocated any new memory locations, make another pass
1070 since it might have changed elimination offsets. */
1071 if (starting_frame_size != get_frame_size ())
1072 something_changed = 1;
1074 /* Even if the frame size remained the same, we might still have
1075 changed elimination offsets, e.g. if find_reloads called
1076 force_const_mem requiring the back end to allocate a constant
1077 pool base register that needs to be saved on the stack. */
1078 else if (!verify_initial_elim_offsets ())
1079 something_changed = 1;
1082 HARD_REG_SET to_spill;
1083 CLEAR_HARD_REG_SET (to_spill);
1084 update_eliminables (&to_spill);
1085 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
1087 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1088 if (TEST_HARD_REG_BIT (to_spill, i))
1090 spill_hard_reg (i, 1);
1093 /* Regardless of the state of spills, if we previously had
1094 a register that we thought we could eliminate, but now can
1095 not eliminate, we must run another pass.
1097 Consider pseudos which have an entry in reg_equiv_* which
1098 reference an eliminable register. We must make another pass
1099 to update reg_equiv_* so that we do not substitute in the
1100 old value from when we thought the elimination could be
1102 something_changed = 1;
1106 select_reload_regs ();
1110 if (insns_need_reload != 0 || did_spill)
1111 something_changed |= finish_spills (global);
1113 if (! something_changed)
1116 if (caller_save_needed)
1117 delete_caller_save_insns ();
1119 obstack_free (&reload_obstack, reload_firstobj);
1122 /* If global-alloc was run, notify it of any register eliminations we have
1125 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1126 if (ep->can_eliminate)
1127 mark_elimination (ep->from, ep->to);
1129 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1130 If that insn didn't set the register (i.e., it copied the register to
1131 memory), just delete that insn instead of the equivalencing insn plus
1132 anything now dead. If we call delete_dead_insn on that insn, we may
1133 delete the insn that actually sets the register if the register dies
1134 there and that is incorrect. */
1136 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1138 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1141 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1143 rtx equiv_insn = XEXP (list, 0);
1145 /* If we already deleted the insn or if it may trap, we can't
1146 delete it. The latter case shouldn't happen, but can
1147 if an insn has a variable address, gets a REG_EH_REGION
1148 note added to it, and then gets converted into a load
1149 from a constant address. */
1150 if (NOTE_P (equiv_insn)
1151 || can_throw_internal (equiv_insn))
1153 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1154 delete_dead_insn (equiv_insn);
1156 SET_INSN_DELETED (equiv_insn);
1161 /* Use the reload registers where necessary
1162 by generating move instructions to move the must-be-register
1163 values into or out of the reload registers. */
1165 if (insns_need_reload != 0 || something_needs_elimination
1166 || something_needs_operands_changed)
1168 HOST_WIDE_INT old_frame_size = get_frame_size ();
1170 reload_as_needed (global);
1172 gcc_assert (old_frame_size == get_frame_size ());
1174 gcc_assert (verify_initial_elim_offsets ());
1177 /* If we were able to eliminate the frame pointer, show that it is no
1178 longer live at the start of any basic block. If it ls live by
1179 virtue of being in a pseudo, that pseudo will be marked live
1180 and hence the frame pointer will be known to be live via that
1183 if (! frame_pointer_needed)
1185 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1187 /* Come here (with failure set nonzero) if we can't get enough spill
1191 CLEAR_REG_SET (&changed_allocation_pseudos);
1192 CLEAR_REG_SET (&spilled_pseudos);
1193 reload_in_progress = 0;
1195 /* Now eliminate all pseudo regs by modifying them into
1196 their equivalent memory references.
1197 The REG-rtx's for the pseudos are modified in place,
1198 so all insns that used to refer to them now refer to memory.
1200 For a reg that has a reg_equiv_address, all those insns
1201 were changed by reloading so that no insns refer to it any longer;
1202 but the DECL_RTL of a variable decl may refer to it,
1203 and if so this causes the debugging info to mention the variable. */
1205 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1209 if (reg_equiv_mem[i])
1210 addr = XEXP (reg_equiv_mem[i], 0);
1212 if (reg_equiv_address[i])
1213 addr = reg_equiv_address[i];
1217 if (reg_renumber[i] < 0)
1219 rtx reg = regno_reg_rtx[i];
1221 REG_USERVAR_P (reg) = 0;
1222 PUT_CODE (reg, MEM);
1223 XEXP (reg, 0) = addr;
1224 if (reg_equiv_memory_loc[i])
1225 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1228 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1229 MEM_ATTRS (reg) = 0;
1231 MEM_NOTRAP_P (reg) = 1;
1233 else if (reg_equiv_mem[i])
1234 XEXP (reg_equiv_mem[i], 0) = addr;
1238 /* We must set reload_completed now since the cleanup_subreg_operands call
1239 below will re-recognize each insn and reload may have generated insns
1240 which are only valid during and after reload. */
1241 reload_completed = 1;
1243 /* Make a pass over all the insns and delete all USEs which we inserted
1244 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1245 notes. Delete all CLOBBER insns, except those that refer to the return
1246 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1247 from misarranging variable-array code, and simplify (subreg (reg))
1248 operands. Strip and regenerate REG_INC notes that may have been moved
1251 for (insn = first; insn; insn = NEXT_INSN (insn))
1257 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1258 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1260 if ((GET_CODE (PATTERN (insn)) == USE
1261 /* We mark with QImode USEs introduced by reload itself. */
1262 && (GET_MODE (insn) == QImode
1263 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1264 || (GET_CODE (PATTERN (insn)) == CLOBBER
1265 && (!MEM_P (XEXP (PATTERN (insn), 0))
1266 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1267 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1268 && XEXP (XEXP (PATTERN (insn), 0), 0)
1269 != stack_pointer_rtx))
1270 && (!REG_P (XEXP (PATTERN (insn), 0))
1271 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1277 /* Some CLOBBERs may survive until here and still reference unassigned
1278 pseudos with const equivalent, which may in turn cause ICE in later
1279 passes if the reference remains in place. */
1280 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1281 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1282 VOIDmode, PATTERN (insn));
1284 /* Discard obvious no-ops, even without -O. This optimization
1285 is fast and doesn't interfere with debugging. */
1286 if (NONJUMP_INSN_P (insn)
1287 && GET_CODE (PATTERN (insn)) == SET
1288 && REG_P (SET_SRC (PATTERN (insn)))
1289 && REG_P (SET_DEST (PATTERN (insn)))
1290 && (REGNO (SET_SRC (PATTERN (insn)))
1291 == REGNO (SET_DEST (PATTERN (insn)))))
1297 pnote = ®_NOTES (insn);
1300 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1301 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1302 || REG_NOTE_KIND (*pnote) == REG_INC)
1303 *pnote = XEXP (*pnote, 1);
1305 pnote = &XEXP (*pnote, 1);
1309 add_auto_inc_notes (insn, PATTERN (insn));
1312 /* Simplify (subreg (reg)) if it appears as an operand. */
1313 cleanup_subreg_operands (insn);
1315 /* Clean up invalid ASMs so that they don't confuse later passes.
1317 if (asm_noperands (PATTERN (insn)) >= 0)
1319 extract_insn (insn);
1320 if (!constrain_operands (1))
1322 error_for_asm (insn,
1323 "%<asm%> operand has impossible constraints");
1330 /* If we are doing generic stack checking, give a warning if this
1331 function's frame size is larger than we expect. */
1332 if (flag_stack_check == GENERIC_STACK_CHECK)
1334 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1335 static int verbose_warned = 0;
1337 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1338 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1339 size += UNITS_PER_WORD;
1341 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1343 warning (0, "frame size too large for reliable stack checking");
1344 if (! verbose_warned)
1346 warning (0, "try reducing the number of local variables");
1352 /* Indicate that we no longer have known memory locations or constants. */
1353 if (reg_equiv_constant)
1354 free (reg_equiv_constant);
1355 if (reg_equiv_invariant)
1356 free (reg_equiv_invariant);
1357 reg_equiv_constant = 0;
1358 reg_equiv_invariant = 0;
1359 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1360 reg_equiv_memory_loc = 0;
1362 free (temp_pseudo_reg_arr);
1364 if (offsets_known_at)
1365 free (offsets_known_at);
1369 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1370 if (reg_equiv_alt_mem_list[i])
1371 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1372 free (reg_equiv_alt_mem_list);
1374 free (reg_equiv_mem);
1376 free (reg_equiv_address);
1377 free (reg_max_ref_width);
1378 free (reg_old_renumber);
1379 free (pseudo_previous_regs);
1380 free (pseudo_forbidden_regs);
1382 CLEAR_HARD_REG_SET (used_spill_regs);
1383 for (i = 0; i < n_spills; i++)
1384 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1386 /* Free all the insn_chain structures at once. */
1387 obstack_free (&reload_obstack, reload_startobj);
1388 unused_insn_chains = 0;
1389 fixup_abnormal_edges ();
1391 /* Replacing pseudos with their memory equivalents might have
1392 created shared rtx. Subsequent passes would get confused
1393 by this, so unshare everything here. */
1394 unshare_all_rtl_again (first);
1396 #ifdef STACK_BOUNDARY
1397 /* init_emit has set the alignment of the hard frame pointer
1398 to STACK_BOUNDARY. It is very likely no longer valid if
1399 the hard frame pointer was used for register allocation. */
1400 if (!frame_pointer_needed)
1401 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1407 /* Yet another special case. Unfortunately, reg-stack forces people to
1408 write incorrect clobbers in asm statements. These clobbers must not
1409 cause the register to appear in bad_spill_regs, otherwise we'll call
1410 fatal_insn later. We clear the corresponding regnos in the live
1411 register sets to avoid this.
1412 The whole thing is rather sick, I'm afraid. */
1415 maybe_fix_stack_asms (void)
1418 const char *constraints[MAX_RECOG_OPERANDS];
1419 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1420 struct insn_chain *chain;
1422 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1425 HARD_REG_SET clobbered, allowed;
1428 if (! INSN_P (chain->insn)
1429 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1431 pat = PATTERN (chain->insn);
1432 if (GET_CODE (pat) != PARALLEL)
1435 CLEAR_HARD_REG_SET (clobbered);
1436 CLEAR_HARD_REG_SET (allowed);
1438 /* First, make a mask of all stack regs that are clobbered. */
1439 for (i = 0; i < XVECLEN (pat, 0); i++)
1441 rtx t = XVECEXP (pat, 0, i);
1442 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1443 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1446 /* Get the operand values and constraints out of the insn. */
1447 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1448 constraints, operand_mode, NULL);
1450 /* For every operand, see what registers are allowed. */
1451 for (i = 0; i < noperands; i++)
1453 const char *p = constraints[i];
1454 /* For every alternative, we compute the class of registers allowed
1455 for reloading in CLS, and merge its contents into the reg set
1457 int cls = (int) NO_REGS;
1463 if (c == '\0' || c == ',' || c == '#')
1465 /* End of one alternative - mark the regs in the current
1466 class, and reset the class. */
1467 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1473 } while (c != '\0' && c != ',');
1481 case '=': case '+': case '*': case '%': case '?': case '!':
1482 case '0': case '1': case '2': case '3': case '4': case '<':
1483 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1484 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1485 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1486 case TARGET_MEM_CONSTRAINT:
1490 cls = (int) reg_class_subunion[cls]
1491 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1496 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1500 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1501 cls = (int) reg_class_subunion[cls]
1502 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1504 cls = (int) reg_class_subunion[cls]
1505 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1507 p += CONSTRAINT_LEN (c, p);
1510 /* Those of the registers which are clobbered, but allowed by the
1511 constraints, must be usable as reload registers. So clear them
1512 out of the life information. */
1513 AND_HARD_REG_SET (allowed, clobbered);
1514 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1515 if (TEST_HARD_REG_BIT (allowed, i))
1517 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1518 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1525 /* Copy the global variables n_reloads and rld into the corresponding elts
1528 copy_reloads (struct insn_chain *chain)
1530 chain->n_reloads = n_reloads;
1531 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1532 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1533 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1536 /* Walk the chain of insns, and determine for each whether it needs reloads
1537 and/or eliminations. Build the corresponding insns_need_reload list, and
1538 set something_needs_elimination as appropriate. */
1540 calculate_needs_all_insns (int global)
1542 struct insn_chain **pprev_reload = &insns_need_reload;
1543 struct insn_chain *chain, *next = 0;
1545 something_needs_elimination = 0;
1547 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1548 for (chain = reload_insn_chain; chain != 0; chain = next)
1550 rtx insn = chain->insn;
1554 /* Clear out the shortcuts. */
1555 chain->n_reloads = 0;
1556 chain->need_elim = 0;
1557 chain->need_reload = 0;
1558 chain->need_operand_change = 0;
1560 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1561 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1562 what effects this has on the known offsets at labels. */
1564 if (LABEL_P (insn) || JUMP_P (insn)
1565 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1566 set_label_offsets (insn, insn, 0);
1570 rtx old_body = PATTERN (insn);
1571 int old_code = INSN_CODE (insn);
1572 rtx old_notes = REG_NOTES (insn);
1573 int did_elimination = 0;
1574 int operands_changed = 0;
1575 rtx set = single_set (insn);
1577 /* Skip insns that only set an equivalence. */
1578 if (set && REG_P (SET_DEST (set))
1579 && reg_renumber[REGNO (SET_DEST (set))] < 0
1580 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1581 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1582 && reg_equiv_init[REGNO (SET_DEST (set))])
1585 /* If needed, eliminate any eliminable registers. */
1586 if (num_eliminable || num_eliminable_invariants)
1587 did_elimination = eliminate_regs_in_insn (insn, 0);
1589 /* Analyze the instruction. */
1590 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1591 global, spill_reg_order);
1593 /* If a no-op set needs more than one reload, this is likely
1594 to be something that needs input address reloads. We
1595 can't get rid of this cleanly later, and it is of no use
1596 anyway, so discard it now.
1597 We only do this when expensive_optimizations is enabled,
1598 since this complements reload inheritance / output
1599 reload deletion, and it can make debugging harder. */
1600 if (flag_expensive_optimizations && n_reloads > 1)
1602 rtx set = single_set (insn);
1605 ((SET_SRC (set) == SET_DEST (set)
1606 && REG_P (SET_SRC (set))
1607 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1608 || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1609 && reg_renumber[REGNO (SET_SRC (set))] < 0
1610 && reg_renumber[REGNO (SET_DEST (set))] < 0
1611 && reg_equiv_memory_loc[REGNO (SET_SRC (set))] != NULL
1612 && reg_equiv_memory_loc[REGNO (SET_DEST (set))] != NULL
1613 && rtx_equal_p (reg_equiv_memory_loc
1614 [REGNO (SET_SRC (set))],
1615 reg_equiv_memory_loc
1616 [REGNO (SET_DEST (set))]))))
1618 if (ira_conflicts_p)
1619 /* Inform IRA about the insn deletion. */
1620 ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1621 REGNO (SET_SRC (set)));
1623 /* Delete it from the reload chain. */
1625 chain->prev->next = next;
1627 reload_insn_chain = next;
1629 next->prev = chain->prev;
1630 chain->next = unused_insn_chains;
1631 unused_insn_chains = chain;
1636 update_eliminable_offsets ();
1638 /* Remember for later shortcuts which insns had any reloads or
1639 register eliminations. */
1640 chain->need_elim = did_elimination;
1641 chain->need_reload = n_reloads > 0;
1642 chain->need_operand_change = operands_changed;
1644 /* Discard any register replacements done. */
1645 if (did_elimination)
1647 obstack_free (&reload_obstack, reload_insn_firstobj);
1648 PATTERN (insn) = old_body;
1649 INSN_CODE (insn) = old_code;
1650 REG_NOTES (insn) = old_notes;
1651 something_needs_elimination = 1;
1654 something_needs_operands_changed |= operands_changed;
1658 copy_reloads (chain);
1659 *pprev_reload = chain;
1660 pprev_reload = &chain->next_need_reload;
1667 /* Comparison function for qsort to decide which of two reloads
1668 should be handled first. *P1 and *P2 are the reload numbers. */
1671 reload_reg_class_lower (const void *r1p, const void *r2p)
1673 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1676 /* Consider required reloads before optional ones. */
1677 t = rld[r1].optional - rld[r2].optional;
1681 /* Count all solitary classes before non-solitary ones. */
1682 t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1683 - (reg_class_size[(int) rld[r1].rclass] == 1));
1687 /* Aside from solitaires, consider all multi-reg groups first. */
1688 t = rld[r2].nregs - rld[r1].nregs;
1692 /* Consider reloads in order of increasing reg-class number. */
1693 t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1697 /* If reloads are equally urgent, sort by reload number,
1698 so that the results of qsort leave nothing to chance. */
1702 /* The cost of spilling each hard reg. */
1703 static int spill_cost[FIRST_PSEUDO_REGISTER];
1705 /* When spilling multiple hard registers, we use SPILL_COST for the first
1706 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1707 only the first hard reg for a multi-reg pseudo. */
1708 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1710 /* Map of hard regno to pseudo regno currently occupying the hard
1712 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1714 /* Update the spill cost arrays, considering that pseudo REG is live. */
1717 count_pseudo (int reg)
1719 int freq = REG_FREQ (reg);
1720 int r = reg_renumber[reg];
1723 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1724 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1725 /* Ignore spilled pseudo-registers which can be here only if IRA
1727 || (ira_conflicts_p && r < 0))
1730 SET_REGNO_REG_SET (&pseudos_counted, reg);
1732 gcc_assert (r >= 0);
1734 spill_add_cost[r] += freq;
1735 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1738 hard_regno_to_pseudo_regno[r + nregs] = reg;
1739 spill_cost[r + nregs] += freq;
1743 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1744 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1747 order_regs_for_reload (struct insn_chain *chain)
1750 HARD_REG_SET used_by_pseudos;
1751 HARD_REG_SET used_by_pseudos2;
1752 reg_set_iterator rsi;
1754 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1756 memset (spill_cost, 0, sizeof spill_cost);
1757 memset (spill_add_cost, 0, sizeof spill_add_cost);
1758 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1759 hard_regno_to_pseudo_regno[i] = -1;
1761 /* Count number of uses of each hard reg by pseudo regs allocated to it
1762 and then order them by decreasing use. First exclude hard registers
1763 that are live in or across this insn. */
1765 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1766 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1767 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1768 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1770 /* Now find out which pseudos are allocated to it, and update
1772 CLEAR_REG_SET (&pseudos_counted);
1774 EXECUTE_IF_SET_IN_REG_SET
1775 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1779 EXECUTE_IF_SET_IN_REG_SET
1780 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1784 CLEAR_REG_SET (&pseudos_counted);
1787 /* Vector of reload-numbers showing the order in which the reloads should
1789 static short reload_order[MAX_RELOADS];
1791 /* This is used to keep track of the spill regs used in one insn. */
1792 static HARD_REG_SET used_spill_regs_local;
1794 /* We decided to spill hard register SPILLED, which has a size of
1795 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1796 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1797 update SPILL_COST/SPILL_ADD_COST. */
1800 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1802 int freq = REG_FREQ (reg);
1803 int r = reg_renumber[reg];
1804 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1806 /* Ignore spilled pseudo-registers which can be here only if IRA is
1808 if ((ira_conflicts_p && r < 0)
1809 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1810 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1813 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1815 spill_add_cost[r] -= freq;
1818 hard_regno_to_pseudo_regno[r + nregs] = -1;
1819 spill_cost[r + nregs] -= freq;
1823 /* Find reload register to use for reload number ORDER. */
1826 find_reg (struct insn_chain *chain, int order)
1828 int rnum = reload_order[order];
1829 struct reload *rl = rld + rnum;
1830 int best_cost = INT_MAX;
1832 unsigned int i, j, n;
1834 HARD_REG_SET not_usable;
1835 HARD_REG_SET used_by_other_reload;
1836 reg_set_iterator rsi;
1837 static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1838 static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1840 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1841 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1842 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1844 CLEAR_HARD_REG_SET (used_by_other_reload);
1845 for (k = 0; k < order; k++)
1847 int other = reload_order[k];
1849 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1850 for (j = 0; j < rld[other].nregs; j++)
1851 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1854 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1856 #ifdef REG_ALLOC_ORDER
1857 unsigned int regno = reg_alloc_order[i];
1859 unsigned int regno = i;
1862 if (! TEST_HARD_REG_BIT (not_usable, regno)
1863 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1864 && HARD_REGNO_MODE_OK (regno, rl->mode))
1866 int this_cost = spill_cost[regno];
1868 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1870 for (j = 1; j < this_nregs; j++)
1872 this_cost += spill_add_cost[regno + j];
1873 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1874 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1880 if (ira_conflicts_p)
1882 /* Ask IRA to find a better pseudo-register for
1884 for (n = j = 0; j < this_nregs; j++)
1886 int r = hard_regno_to_pseudo_regno[regno + j];
1890 if (n == 0 || regno_pseudo_regs[n - 1] != r)
1891 regno_pseudo_regs[n++] = r;
1893 regno_pseudo_regs[n++] = -1;
1895 || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1896 best_regno_pseudo_regs,
1903 best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1904 if (regno_pseudo_regs[j] < 0)
1911 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1913 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1915 if (this_cost < best_cost
1916 /* Among registers with equal cost, prefer caller-saved ones, or
1917 use REG_ALLOC_ORDER if it is defined. */
1918 || (this_cost == best_cost
1919 #ifdef REG_ALLOC_ORDER
1920 && (inv_reg_alloc_order[regno]
1921 < inv_reg_alloc_order[best_reg])
1923 && call_used_regs[regno]
1924 && ! call_used_regs[best_reg]
1929 best_cost = this_cost;
1937 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1939 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1940 rl->regno = best_reg;
1942 EXECUTE_IF_SET_IN_REG_SET
1943 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1945 count_spilled_pseudo (best_reg, rl->nregs, j);
1948 EXECUTE_IF_SET_IN_REG_SET
1949 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1951 count_spilled_pseudo (best_reg, rl->nregs, j);
1954 for (i = 0; i < rl->nregs; i++)
1956 gcc_assert (spill_cost[best_reg + i] == 0);
1957 gcc_assert (spill_add_cost[best_reg + i] == 0);
1958 gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
1959 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1964 /* Find more reload regs to satisfy the remaining need of an insn, which
1966 Do it by ascending class number, since otherwise a reg
1967 might be spilled for a big class and might fail to count
1968 for a smaller class even though it belongs to that class. */
1971 find_reload_regs (struct insn_chain *chain)
1975 /* In order to be certain of getting the registers we need,
1976 we must sort the reloads into order of increasing register class.
1977 Then our grabbing of reload registers will parallel the process
1978 that provided the reload registers. */
1979 for (i = 0; i < chain->n_reloads; i++)
1981 /* Show whether this reload already has a hard reg. */
1982 if (chain->rld[i].reg_rtx)
1984 int regno = REGNO (chain->rld[i].reg_rtx);
1985 chain->rld[i].regno = regno;
1987 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1990 chain->rld[i].regno = -1;
1991 reload_order[i] = i;
1994 n_reloads = chain->n_reloads;
1995 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1997 CLEAR_HARD_REG_SET (used_spill_regs_local);
2000 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
2002 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
2004 /* Compute the order of preference for hard registers to spill. */
2006 order_regs_for_reload (chain);
2008 for (i = 0; i < n_reloads; i++)
2010 int r = reload_order[i];
2012 /* Ignore reloads that got marked inoperative. */
2013 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2014 && ! rld[r].optional
2015 && rld[r].regno == -1)
2016 if (! find_reg (chain, i))
2019 fprintf (dump_file, "reload failure for reload %d\n", r);
2020 spill_failure (chain->insn, rld[r].rclass);
2026 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2027 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2029 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2033 select_reload_regs (void)
2035 struct insn_chain *chain;
2037 /* Try to satisfy the needs for each insn. */
2038 for (chain = insns_need_reload; chain != 0;
2039 chain = chain->next_need_reload)
2040 find_reload_regs (chain);
2043 /* Delete all insns that were inserted by emit_caller_save_insns during
2046 delete_caller_save_insns (void)
2048 struct insn_chain *c = reload_insn_chain;
2052 while (c != 0 && c->is_caller_save_insn)
2054 struct insn_chain *next = c->next;
2057 if (c == reload_insn_chain)
2058 reload_insn_chain = next;
2062 next->prev = c->prev;
2064 c->prev->next = next;
2065 c->next = unused_insn_chains;
2066 unused_insn_chains = c;
2074 /* Handle the failure to find a register to spill.
2075 INSN should be one of the insns which needed this particular spill reg. */
2078 spill_failure (rtx insn, enum reg_class rclass)
2080 if (asm_noperands (PATTERN (insn)) >= 0)
2081 error_for_asm (insn, "can't find a register in class %qs while "
2082 "reloading %<asm%>",
2083 reg_class_names[rclass]);
2086 error ("unable to find a register to spill in class %qs",
2087 reg_class_names[rclass]);
2091 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2092 debug_reload_to_stream (dump_file);
2094 fatal_insn ("this is the insn:", insn);
2098 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2099 data that is dead in INSN. */
2102 delete_dead_insn (rtx insn)
2104 rtx prev = prev_real_insn (insn);
2107 /* If the previous insn sets a register that dies in our insn, delete it
2109 if (prev && GET_CODE (PATTERN (prev)) == SET
2110 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2111 && reg_mentioned_p (prev_dest, PATTERN (insn))
2112 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2113 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2114 delete_dead_insn (prev);
2116 SET_INSN_DELETED (insn);
2119 /* Modify the home of pseudo-reg I.
2120 The new home is present in reg_renumber[I].
2122 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2123 or it may be -1, meaning there is none or it is not relevant.
2124 This is used so that all pseudos spilled from a given hard reg
2125 can share one stack slot. */
2128 alter_reg (int i, int from_reg, bool dont_share_p)
2130 /* When outputting an inline function, this can happen
2131 for a reg that isn't actually used. */
2132 if (regno_reg_rtx[i] == 0)
2135 /* If the reg got changed to a MEM at rtl-generation time,
2137 if (!REG_P (regno_reg_rtx[i]))
2140 /* Modify the reg-rtx to contain the new hard reg
2141 number or else to contain its pseudo reg number. */
2142 SET_REGNO (regno_reg_rtx[i],
2143 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2145 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2146 allocate a stack slot for it. */
2148 if (reg_renumber[i] < 0
2149 && REG_N_REFS (i) > 0
2150 && reg_equiv_constant[i] == 0
2151 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
2152 && reg_equiv_memory_loc[i] == 0)
2155 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2156 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2157 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2158 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2159 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2162 if (ira_conflicts_p)
2164 /* Mark the spill for IRA. */
2165 SET_REGNO_REG_SET (&spilled_pseudos, i);
2167 x = ira_reuse_stack_slot (i, inherent_size, total_size);
2173 /* Each pseudo reg has an inherent size which comes from its own mode,
2174 and a total size which provides room for paradoxical subregs
2175 which refer to the pseudo reg in wider modes.
2177 We can use a slot already allocated if it provides both
2178 enough inherent space and enough total space.
2179 Otherwise, we allocate a new slot, making sure that it has no less
2180 inherent space, and no less total space, then the previous slot. */
2181 else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2185 /* No known place to spill from => no slot to reuse. */
2186 x = assign_stack_local (mode, total_size,
2187 min_align > inherent_align
2188 || total_size > inherent_size ? -1 : 0);
2192 /* Cancel the big-endian correction done in assign_stack_local.
2193 Get the address of the beginning of the slot. This is so we
2194 can do a big-endian correction unconditionally below. */
2195 if (BYTES_BIG_ENDIAN)
2197 adjust = inherent_size - total_size;
2200 = adjust_address_nv (x, mode_for_size (total_size
2206 if (! dont_share_p && ira_conflicts_p)
2207 /* Inform IRA about allocation a new stack slot. */
2208 ira_mark_new_stack_slot (stack_slot, i, total_size);
2211 /* Reuse a stack slot if possible. */
2212 else if (spill_stack_slot[from_reg] != 0
2213 && spill_stack_slot_width[from_reg] >= total_size
2214 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2216 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2217 x = spill_stack_slot[from_reg];
2219 /* Allocate a bigger slot. */
2222 /* Compute maximum size needed, both for inherent size
2223 and for total size. */
2226 if (spill_stack_slot[from_reg])
2228 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2230 mode = GET_MODE (spill_stack_slot[from_reg]);
2231 if (spill_stack_slot_width[from_reg] > total_size)
2232 total_size = spill_stack_slot_width[from_reg];
2233 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2234 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2237 /* Make a slot with that size. */
2238 x = assign_stack_local (mode, total_size,
2239 min_align > inherent_align
2240 || total_size > inherent_size ? -1 : 0);
2243 /* Cancel the big-endian correction done in assign_stack_local.
2244 Get the address of the beginning of the slot. This is so we
2245 can do a big-endian correction unconditionally below. */
2246 if (BYTES_BIG_ENDIAN)
2248 adjust = GET_MODE_SIZE (mode) - total_size;
2251 = adjust_address_nv (x, mode_for_size (total_size
2257 spill_stack_slot[from_reg] = stack_slot;
2258 spill_stack_slot_width[from_reg] = total_size;
2261 /* On a big endian machine, the "address" of the slot
2262 is the address of the low part that fits its inherent mode. */
2263 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2264 adjust += (total_size - inherent_size);
2266 /* If we have any adjustment to make, or if the stack slot is the
2267 wrong mode, make a new stack slot. */
2268 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2270 /* Set all of the memory attributes as appropriate for a spill. */
2271 set_mem_attrs_for_spill (x);
2273 /* Save the stack slot for later. */
2274 reg_equiv_memory_loc[i] = x;
2278 /* Mark the slots in regs_ever_live for the hard regs used by
2279 pseudo-reg number REGNO, accessed in MODE. */
2282 mark_home_live_1 (int regno, enum machine_mode mode)
2286 i = reg_renumber[regno];
2289 lim = end_hard_regno (mode, i);
2291 df_set_regs_ever_live(i++, true);
2294 /* Mark the slots in regs_ever_live for the hard regs
2295 used by pseudo-reg number REGNO. */
2298 mark_home_live (int regno)
2300 if (reg_renumber[regno] >= 0)
2301 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2304 /* This function handles the tracking of elimination offsets around branches.
2306 X is a piece of RTL being scanned.
2308 INSN is the insn that it came from, if any.
2310 INITIAL_P is nonzero if we are to set the offset to be the initial
2311 offset and zero if we are setting the offset of the label to be the
2315 set_label_offsets (rtx x, rtx insn, int initial_p)
2317 enum rtx_code code = GET_CODE (x);
2320 struct elim_table *p;
2325 if (LABEL_REF_NONLOCAL_P (x))
2330 /* ... fall through ... */
2333 /* If we know nothing about this label, set the desired offsets. Note
2334 that this sets the offset at a label to be the offset before a label
2335 if we don't know anything about the label. This is not correct for
2336 the label after a BARRIER, but is the best guess we can make. If
2337 we guessed wrong, we will suppress an elimination that might have
2338 been possible had we been able to guess correctly. */
2340 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2342 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2343 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2344 = (initial_p ? reg_eliminate[i].initial_offset
2345 : reg_eliminate[i].offset);
2346 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2349 /* Otherwise, if this is the definition of a label and it is
2350 preceded by a BARRIER, set our offsets to the known offset of
2354 && (tem = prev_nonnote_insn (insn)) != 0
2356 set_offsets_for_label (insn);
2358 /* If neither of the above cases is true, compare each offset
2359 with those previously recorded and suppress any eliminations
2360 where the offsets disagree. */
2362 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2363 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2364 != (initial_p ? reg_eliminate[i].initial_offset
2365 : reg_eliminate[i].offset))
2366 reg_eliminate[i].can_eliminate = 0;
2371 set_label_offsets (PATTERN (insn), insn, initial_p);
2373 /* ... fall through ... */
2377 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2378 to indirectly and hence must have all eliminations at their
2380 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2381 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2382 set_label_offsets (XEXP (tem, 0), insn, 1);
2388 /* Each of the labels in the parallel or address vector must be
2389 at their initial offsets. We want the first field for PARALLEL
2390 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2392 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2393 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2398 /* We only care about setting PC. If the source is not RETURN,
2399 IF_THEN_ELSE, or a label, disable any eliminations not at
2400 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2401 isn't one of those possibilities. For branches to a label,
2402 call ourselves recursively.
2404 Note that this can disable elimination unnecessarily when we have
2405 a non-local goto since it will look like a non-constant jump to
2406 someplace in the current function. This isn't a significant
2407 problem since such jumps will normally be when all elimination
2408 pairs are back to their initial offsets. */
2410 if (SET_DEST (x) != pc_rtx)
2413 switch (GET_CODE (SET_SRC (x)))
2420 set_label_offsets (SET_SRC (x), insn, initial_p);
2424 tem = XEXP (SET_SRC (x), 1);
2425 if (GET_CODE (tem) == LABEL_REF)
2426 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2427 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2430 tem = XEXP (SET_SRC (x), 2);
2431 if (GET_CODE (tem) == LABEL_REF)
2432 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2433 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2441 /* If we reach here, all eliminations must be at their initial
2442 offset because we are doing a jump to a variable address. */
2443 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2444 if (p->offset != p->initial_offset)
2445 p->can_eliminate = 0;
2453 /* Scan X and replace any eliminable registers (such as fp) with a
2454 replacement (such as sp), plus an offset.
2456 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2457 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2458 MEM, we are allowed to replace a sum of a register and the constant zero
2459 with the register, which we cannot do outside a MEM. In addition, we need
2460 to record the fact that a register is referenced outside a MEM.
2462 If INSN is an insn, it is the insn containing X. If we replace a REG
2463 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2464 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2465 the REG is being modified.
2467 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2468 That's used when we eliminate in expressions stored in notes.
2469 This means, do not set ref_outside_mem even if the reference
2472 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2473 replacements done assuming all offsets are at their initial values. If
2474 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2475 encounter, return the actual location so that find_reloads will do
2476 the proper thing. */
2479 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2480 bool may_use_invariant)
2482 enum rtx_code code = GET_CODE (x);
2483 struct elim_table *ep;
2490 if (! current_function_decl)
2513 /* First handle the case where we encounter a bare register that
2514 is eliminable. Replace it with a PLUS. */
2515 if (regno < FIRST_PSEUDO_REGISTER)
2517 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2519 if (ep->from_rtx == x && ep->can_eliminate)
2520 return plus_constant (ep->to_rtx, ep->previous_offset);
2523 else if (reg_renumber && reg_renumber[regno] < 0
2524 && reg_equiv_invariant && reg_equiv_invariant[regno])
2526 if (may_use_invariant)
2527 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2528 mem_mode, insn, true);
2529 /* There exists at least one use of REGNO that cannot be
2530 eliminated. Prevent the defining insn from being deleted. */
2531 reg_equiv_init[regno] = NULL_RTX;
2532 alter_reg (regno, -1, true);
2536 /* You might think handling MINUS in a manner similar to PLUS is a
2537 good idea. It is not. It has been tried multiple times and every
2538 time the change has had to have been reverted.
2540 Other parts of reload know a PLUS is special (gen_reload for example)
2541 and require special code to handle code a reloaded PLUS operand.
2543 Also consider backends where the flags register is clobbered by a
2544 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2545 lea instruction comes to mind). If we try to reload a MINUS, we
2546 may kill the flags register that was holding a useful value.
2548 So, please before trying to handle MINUS, consider reload as a
2549 whole instead of this little section as well as the backend issues. */
2551 /* If this is the sum of an eliminable register and a constant, rework
2553 if (REG_P (XEXP (x, 0))
2554 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2555 && CONSTANT_P (XEXP (x, 1)))
2557 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2559 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2561 /* The only time we want to replace a PLUS with a REG (this
2562 occurs when the constant operand of the PLUS is the negative
2563 of the offset) is when we are inside a MEM. We won't want
2564 to do so at other times because that would change the
2565 structure of the insn in a way that reload can't handle.
2566 We special-case the commonest situation in
2567 eliminate_regs_in_insn, so just replace a PLUS with a
2568 PLUS here, unless inside a MEM. */
2569 if (mem_mode != 0 && CONST_INT_P (XEXP (x, 1))
2570 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2573 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2574 plus_constant (XEXP (x, 1),
2575 ep->previous_offset));
2578 /* If the register is not eliminable, we are done since the other
2579 operand is a constant. */
2583 /* If this is part of an address, we want to bring any constant to the
2584 outermost PLUS. We will do this by doing register replacement in
2585 our operands and seeing if a constant shows up in one of them.
2587 Note that there is no risk of modifying the structure of the insn,
2588 since we only get called for its operands, thus we are either
2589 modifying the address inside a MEM, or something like an address
2590 operand of a load-address insn. */
2593 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2594 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2596 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2598 /* If one side is a PLUS and the other side is a pseudo that
2599 didn't get a hard register but has a reg_equiv_constant,
2600 we must replace the constant here since it may no longer
2601 be in the position of any operand. */
2602 if (GET_CODE (new0) == PLUS && REG_P (new1)
2603 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2604 && reg_renumber[REGNO (new1)] < 0
2605 && reg_equiv_constant != 0
2606 && reg_equiv_constant[REGNO (new1)] != 0)
2607 new1 = reg_equiv_constant[REGNO (new1)];
2608 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2609 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2610 && reg_renumber[REGNO (new0)] < 0
2611 && reg_equiv_constant[REGNO (new0)] != 0)
2612 new0 = reg_equiv_constant[REGNO (new0)];
2614 new_rtx = form_sum (new0, new1);
2616 /* As above, if we are not inside a MEM we do not want to
2617 turn a PLUS into something else. We might try to do so here
2618 for an addition of 0 if we aren't optimizing. */
2619 if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2620 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2628 /* If this is the product of an eliminable register and a
2629 constant, apply the distribute law and move the constant out
2630 so that we have (plus (mult ..) ..). This is needed in order
2631 to keep load-address insns valid. This case is pathological.
2632 We ignore the possibility of overflow here. */
2633 if (REG_P (XEXP (x, 0))
2634 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2635 && CONST_INT_P (XEXP (x, 1)))
2636 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2638 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2641 /* Refs inside notes don't count for this purpose. */
2642 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2643 || GET_CODE (insn) == INSN_LIST)))
2644 ep->ref_outside_mem = 1;
2647 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2648 ep->previous_offset * INTVAL (XEXP (x, 1)));
2651 /* ... fall through ... */
2655 /* See comments before PLUS about handling MINUS. */
2657 case DIV: case UDIV:
2658 case MOD: case UMOD:
2659 case AND: case IOR: case XOR:
2660 case ROTATERT: case ROTATE:
2661 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2663 case GE: case GT: case GEU: case GTU:
2664 case LE: case LT: case LEU: case LTU:
2666 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2667 rtx new1 = XEXP (x, 1)
2668 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2670 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2671 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2676 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2679 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2680 if (new_rtx != XEXP (x, 0))
2682 /* If this is a REG_DEAD note, it is not valid anymore.
2683 Using the eliminated version could result in creating a
2684 REG_DEAD note for the stack or frame pointer. */
2685 if (REG_NOTE_KIND (x) == REG_DEAD)
2687 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2690 x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2694 /* ... fall through ... */
2697 /* Now do eliminations in the rest of the chain. If this was
2698 an EXPR_LIST, this might result in allocating more memory than is
2699 strictly needed, but it simplifies the code. */
2702 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2703 if (new_rtx != XEXP (x, 1))
2705 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2713 /* We do not support elimination of a register that is modified.
2714 elimination_effects has already make sure that this does not
2720 /* We do not support elimination of a register that is modified.
2721 elimination_effects has already make sure that this does not
2722 happen. The only remaining case we need to consider here is
2723 that the increment value may be an eliminable register. */
2724 if (GET_CODE (XEXP (x, 1)) == PLUS
2725 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2727 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2730 if (new_rtx != XEXP (XEXP (x, 1), 1))
2731 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2732 gen_rtx_PLUS (GET_MODE (x),
2733 XEXP (x, 0), new_rtx));
2737 case STRICT_LOW_PART:
2739 case SIGN_EXTEND: case ZERO_EXTEND:
2740 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2741 case FLOAT: case FIX:
2742 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2751 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2752 if (new_rtx != XEXP (x, 0))
2753 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2757 /* Similar to above processing, but preserve SUBREG_BYTE.
2758 Convert (subreg (mem)) to (mem) if not paradoxical.
2759 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2760 pseudo didn't get a hard reg, we must replace this with the
2761 eliminated version of the memory location because push_reload
2762 may do the replacement in certain circumstances. */
2763 if (REG_P (SUBREG_REG (x))
2764 && (GET_MODE_SIZE (GET_MODE (x))
2765 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2766 && reg_equiv_memory_loc != 0
2767 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2769 new_rtx = SUBREG_REG (x);
2772 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2774 if (new_rtx != SUBREG_REG (x))
2776 int x_size = GET_MODE_SIZE (GET_MODE (x));
2777 int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2780 && ((x_size < new_size
2781 #ifdef WORD_REGISTER_OPERATIONS
2782 /* On these machines, combine can create rtl of the form
2783 (set (subreg:m1 (reg:m2 R) 0) ...)
2784 where m1 < m2, and expects something interesting to
2785 happen to the entire word. Moreover, it will use the
2786 (reg:m2 R) later, expecting all bits to be preserved.
2787 So if the number of words is the same, preserve the
2788 subreg so that push_reload can see it. */
2789 && ! ((x_size - 1) / UNITS_PER_WORD
2790 == (new_size -1 ) / UNITS_PER_WORD)
2793 || x_size == new_size)
2795 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2797 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2803 /* Our only special processing is to pass the mode of the MEM to our
2804 recursive call and copy the flags. While we are here, handle this
2805 case more efficiently. */
2807 replace_equiv_address_nv (x,
2808 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2812 /* Handle insn_list USE that a call to a pure function may generate. */
2813 new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false);
2814 if (new_rtx != XEXP (x, 0))
2815 return gen_rtx_USE (GET_MODE (x), new_rtx);
2827 /* Process each of our operands recursively. If any have changed, make a
2829 fmt = GET_RTX_FORMAT (code);
2830 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2834 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2835 if (new_rtx != XEXP (x, i) && ! copied)
2837 x = shallow_copy_rtx (x);
2840 XEXP (x, i) = new_rtx;
2842 else if (*fmt == 'E')
2845 for (j = 0; j < XVECLEN (x, i); j++)
2847 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2848 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2850 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2854 x = shallow_copy_rtx (x);
2857 XVEC (x, i) = new_v;
2860 XVECEXP (x, i, j) = new_rtx;
2869 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2871 return eliminate_regs_1 (x, mem_mode, insn, false);
2874 /* Scan rtx X for modifications of elimination target registers. Update
2875 the table of eliminables to reflect the changed state. MEM_MODE is
2876 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2879 elimination_effects (rtx x, enum machine_mode mem_mode)
2881 enum rtx_code code = GET_CODE (x);
2882 struct elim_table *ep;
2907 /* First handle the case where we encounter a bare register that
2908 is eliminable. Replace it with a PLUS. */
2909 if (regno < FIRST_PSEUDO_REGISTER)
2911 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2913 if (ep->from_rtx == x && ep->can_eliminate)
2916 ep->ref_outside_mem = 1;
2921 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2922 && reg_equiv_constant[regno]
2923 && ! function_invariant_p (reg_equiv_constant[regno]))
2924 elimination_effects (reg_equiv_constant[regno], mem_mode);
2933 /* If we modify the source of an elimination rule, disable it. */
2934 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2935 if (ep->from_rtx == XEXP (x, 0))
2936 ep->can_eliminate = 0;
2938 /* If we modify the target of an elimination rule by adding a constant,
2939 update its offset. If we modify the target in any other way, we'll
2940 have to disable the rule as well. */
2941 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2942 if (ep->to_rtx == XEXP (x, 0))
2944 int size = GET_MODE_SIZE (mem_mode);
2946 /* If more bytes than MEM_MODE are pushed, account for them. */
2947 #ifdef PUSH_ROUNDING
2948 if (ep->to_rtx == stack_pointer_rtx)
2949 size = PUSH_ROUNDING (size);
2951 if (code == PRE_DEC || code == POST_DEC)
2953 else if (code == PRE_INC || code == POST_INC)
2955 else if (code == PRE_MODIFY || code == POST_MODIFY)
2957 if (GET_CODE (XEXP (x, 1)) == PLUS
2958 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2959 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
2960 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2962 ep->can_eliminate = 0;
2966 /* These two aren't unary operators. */
2967 if (code == POST_MODIFY || code == PRE_MODIFY)
2970 /* Fall through to generic unary operation case. */
2971 case STRICT_LOW_PART:
2973 case SIGN_EXTEND: case ZERO_EXTEND:
2974 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2975 case FLOAT: case FIX:
2976 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2985 elimination_effects (XEXP (x, 0), mem_mode);
2989 if (REG_P (SUBREG_REG (x))
2990 && (GET_MODE_SIZE (GET_MODE (x))
2991 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2992 && reg_equiv_memory_loc != 0
2993 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2996 elimination_effects (SUBREG_REG (x), mem_mode);
3000 /* If using a register that is the source of an eliminate we still
3001 think can be performed, note it cannot be performed since we don't
3002 know how this register is used. */
3003 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3004 if (ep->from_rtx == XEXP (x, 0))
3005 ep->can_eliminate = 0;
3007 elimination_effects (XEXP (x, 0), mem_mode);
3011 /* If clobbering a register that is the replacement register for an
3012 elimination we still think can be performed, note that it cannot
3013 be performed. Otherwise, we need not be concerned about it. */
3014 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3015 if (ep->to_rtx == XEXP (x, 0))
3016 ep->can_eliminate = 0;
3018 elimination_effects (XEXP (x, 0), mem_mode);
3022 /* Check for setting a register that we know about. */
3023 if (REG_P (SET_DEST (x)))
3025 /* See if this is setting the replacement register for an
3028 If DEST is the hard frame pointer, we do nothing because we
3029 assume that all assignments to the frame pointer are for
3030 non-local gotos and are being done at a time when they are valid
3031 and do not disturb anything else. Some machines want to
3032 eliminate a fake argument pointer (or even a fake frame pointer)
3033 with either the real frame or the stack pointer. Assignments to
3034 the hard frame pointer must not prevent this elimination. */
3036 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3038 if (ep->to_rtx == SET_DEST (x)
3039 && SET_DEST (x) != hard_frame_pointer_rtx)
3041 /* If it is being incremented, adjust the offset. Otherwise,
3042 this elimination can't be done. */
3043 rtx src = SET_SRC (x);
3045 if (GET_CODE (src) == PLUS
3046 && XEXP (src, 0) == SET_DEST (x)
3047 && CONST_INT_P (XEXP (src, 1)))
3048 ep->offset -= INTVAL (XEXP (src, 1));
3050 ep->can_eliminate = 0;
3054 elimination_effects (SET_DEST (x), VOIDmode);
3055 elimination_effects (SET_SRC (x), VOIDmode);
3059 /* Our only special processing is to pass the mode of the MEM to our
3061 elimination_effects (XEXP (x, 0), GET_MODE (x));
3068 fmt = GET_RTX_FORMAT (code);
3069 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3072 elimination_effects (XEXP (x, i), mem_mode);
3073 else if (*fmt == 'E')
3074 for (j = 0; j < XVECLEN (x, i); j++)
3075 elimination_effects (XVECEXP (x, i, j), mem_mode);
3079 /* Descend through rtx X and verify that no references to eliminable registers
3080 remain. If any do remain, mark the involved register as not
3084 check_eliminable_occurrences (rtx x)
3093 code = GET_CODE (x);
3095 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3097 struct elim_table *ep;
3099 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3100 if (ep->from_rtx == x)
3101 ep->can_eliminate = 0;
3105 fmt = GET_RTX_FORMAT (code);
3106 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3109 check_eliminable_occurrences (XEXP (x, i));
3110 else if (*fmt == 'E')
3113 for (j = 0; j < XVECLEN (x, i); j++)
3114 check_eliminable_occurrences (XVECEXP (x, i, j));
3119 /* Scan INSN and eliminate all eliminable registers in it.
3121 If REPLACE is nonzero, do the replacement destructively. Also
3122 delete the insn as dead it if it is setting an eliminable register.
3124 If REPLACE is zero, do all our allocations in reload_obstack.
3126 If no eliminations were done and this insn doesn't require any elimination
3127 processing (these are not identical conditions: it might be updating sp,
3128 but not referencing fp; this needs to be seen during reload_as_needed so
3129 that the offset between fp and sp can be taken into consideration), zero
3130 is returned. Otherwise, 1 is returned. */
3133 eliminate_regs_in_insn (rtx insn, int replace)
3135 int icode = recog_memoized (insn);
3136 rtx old_body = PATTERN (insn);
3137 int insn_is_asm = asm_noperands (old_body) >= 0;
3138 rtx old_set = single_set (insn);
3142 rtx substed_operand[MAX_RECOG_OPERANDS];
3143 rtx orig_operand[MAX_RECOG_OPERANDS];
3144 struct elim_table *ep;
3145 rtx plus_src, plus_cst_src;
3147 if (! insn_is_asm && icode < 0)
3149 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3150 || GET_CODE (PATTERN (insn)) == CLOBBER
3151 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3152 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3153 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3157 if (old_set != 0 && REG_P (SET_DEST (old_set))
3158 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3160 /* Check for setting an eliminable register. */
3161 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3162 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3164 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3165 /* If this is setting the frame pointer register to the
3166 hardware frame pointer register and this is an elimination
3167 that will be done (tested above), this insn is really
3168 adjusting the frame pointer downward to compensate for
3169 the adjustment done before a nonlocal goto. */
3170 if (ep->from == FRAME_POINTER_REGNUM
3171 && ep->to == HARD_FRAME_POINTER_REGNUM)
3173 rtx base = SET_SRC (old_set);
3174 rtx base_insn = insn;
3175 HOST_WIDE_INT offset = 0;
3177 while (base != ep->to_rtx)
3179 rtx prev_insn, prev_set;
3181 if (GET_CODE (base) == PLUS
3182 && CONST_INT_P (XEXP (base, 1)))
3184 offset += INTVAL (XEXP (base, 1));
3185 base = XEXP (base, 0);
3187 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3188 && (prev_set = single_set (prev_insn)) != 0
3189 && rtx_equal_p (SET_DEST (prev_set), base))
3191 base = SET_SRC (prev_set);
3192 base_insn = prev_insn;
3198 if (base == ep->to_rtx)
3201 = plus_constant (ep->to_rtx, offset - ep->offset);
3203 new_body = old_body;
3206 new_body = copy_insn (old_body);
3207 if (REG_NOTES (insn))
3208 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3210 PATTERN (insn) = new_body;
3211 old_set = single_set (insn);
3213 /* First see if this insn remains valid when we
3214 make the change. If not, keep the INSN_CODE
3215 the same and let reload fit it up. */
3216 validate_change (insn, &SET_SRC (old_set), src, 1);
3217 validate_change (insn, &SET_DEST (old_set),
3219 if (! apply_change_group ())
3221 SET_SRC (old_set) = src;
3222 SET_DEST (old_set) = ep->to_rtx;
3231 /* In this case this insn isn't serving a useful purpose. We
3232 will delete it in reload_as_needed once we know that this
3233 elimination is, in fact, being done.
3235 If REPLACE isn't set, we can't delete this insn, but needn't
3236 process it since it won't be used unless something changes. */
3239 delete_dead_insn (insn);
3247 /* We allow one special case which happens to work on all machines we
3248 currently support: a single set with the source or a REG_EQUAL
3249 note being a PLUS of an eliminable register and a constant. */
3250 plus_src = plus_cst_src = 0;
3251 if (old_set && REG_P (SET_DEST (old_set)))
3253 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3254 plus_src = SET_SRC (old_set);
3255 /* First see if the source is of the form (plus (...) CST). */
3257 && CONST_INT_P (XEXP (plus_src, 1)))
3258 plus_cst_src = plus_src;
3259 else if (REG_P (SET_SRC (old_set))
3262 /* Otherwise, see if we have a REG_EQUAL note of the form
3263 (plus (...) CST). */
3265 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3267 if ((REG_NOTE_KIND (links) == REG_EQUAL
3268 || REG_NOTE_KIND (links) == REG_EQUIV)
3269 && GET_CODE (XEXP (links, 0)) == PLUS
3270 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3272 plus_cst_src = XEXP (links, 0);
3278 /* Check that the first operand of the PLUS is a hard reg or
3279 the lowpart subreg of one. */
3282 rtx reg = XEXP (plus_cst_src, 0);
3283 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3284 reg = SUBREG_REG (reg);
3286 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3292 rtx reg = XEXP (plus_cst_src, 0);
3293 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3295 if (GET_CODE (reg) == SUBREG)
3296 reg = SUBREG_REG (reg);
3298 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3299 if (ep->from_rtx == reg && ep->can_eliminate)
3301 rtx to_rtx = ep->to_rtx;
3302 offset += ep->offset;
3303 offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3305 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3306 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3308 /* If we have a nonzero offset, and the source is already
3309 a simple REG, the following transformation would
3310 increase the cost of the insn by replacing a simple REG
3311 with (plus (reg sp) CST). So try only when we already
3312 had a PLUS before. */
3313 if (offset == 0 || plus_src)
3315 rtx new_src = plus_constant (to_rtx, offset);
3317 new_body = old_body;
3320 new_body = copy_insn (old_body);
3321 if (REG_NOTES (insn))
3322 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3324 PATTERN (insn) = new_body;
3325 old_set = single_set (insn);
3327 /* First see if this insn remains valid when we make the
3328 change. If not, try to replace the whole pattern with
3329 a simple set (this may help if the original insn was a
3330 PARALLEL that was only recognized as single_set due to
3331 REG_UNUSED notes). If this isn't valid either, keep
3332 the INSN_CODE the same and let reload fix it up. */
3333 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3335 rtx new_pat = gen_rtx_SET (VOIDmode,
3336 SET_DEST (old_set), new_src);
3338 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3339 SET_SRC (old_set) = new_src;
3346 /* This can't have an effect on elimination offsets, so skip right
3352 /* Determine the effects of this insn on elimination offsets. */
3353 elimination_effects (old_body, VOIDmode);
3355 /* Eliminate all eliminable registers occurring in operands that
3356 can be handled by reload. */
3357 extract_insn (insn);
3358 for (i = 0; i < recog_data.n_operands; i++)
3360 orig_operand[i] = recog_data.operand[i];
3361 substed_operand[i] = recog_data.operand[i];
3363 /* For an asm statement, every operand is eliminable. */
3364 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3366 bool is_set_src, in_plus;
3368 /* Check for setting a register that we know about. */
3369 if (recog_data.operand_type[i] != OP_IN
3370 && REG_P (orig_operand[i]))
3372 /* If we are assigning to a register that can be eliminated, it
3373 must be as part of a PARALLEL, since the code above handles
3374 single SETs. We must indicate that we can no longer
3375 eliminate this reg. */
3376 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3378 if (ep->from_rtx == orig_operand[i])
3379 ep->can_eliminate = 0;
3382 /* Companion to the above plus substitution, we can allow
3383 invariants as the source of a plain move. */
3385 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3389 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3390 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3394 = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3395 replace ? insn : NULL_RTX,
3396 is_set_src || in_plus);
3397 if (substed_operand[i] != orig_operand[i])
3399 /* Terminate the search in check_eliminable_occurrences at
3401 *recog_data.operand_loc[i] = 0;
3403 /* If an output operand changed from a REG to a MEM and INSN is an
3404 insn, write a CLOBBER insn. */
3405 if (recog_data.operand_type[i] != OP_IN
3406 && REG_P (orig_operand[i])
3407 && MEM_P (substed_operand[i])
3409 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3413 for (i = 0; i < recog_data.n_dups; i++)
3414 *recog_data.dup_loc[i]
3415 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3417 /* If any eliminable remain, they aren't eliminable anymore. */
3418 check_eliminable_occurrences (old_body);
3420 /* Substitute the operands; the new values are in the substed_operand
3422 for (i = 0; i < recog_data.n_operands; i++)
3423 *recog_data.operand_loc[i] = substed_operand[i];
3424 for (i = 0; i < recog_data.n_dups; i++)
3425 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3427 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3428 re-recognize the insn. We do this in case we had a simple addition
3429 but now can do this as a load-address. This saves an insn in this
3431 If re-recognition fails, the old insn code number will still be used,
3432 and some register operands may have changed into PLUS expressions.
3433 These will be handled by find_reloads by loading them into a register
3438 /* If we aren't replacing things permanently and we changed something,
3439 make another copy to ensure that all the RTL is new. Otherwise
3440 things can go wrong if find_reload swaps commutative operands
3441 and one is inside RTL that has been copied while the other is not. */
3442 new_body = old_body;
3445 new_body = copy_insn (old_body);
3446 if (REG_NOTES (insn))
3447 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3449 PATTERN (insn) = new_body;
3451 /* If we had a move insn but now we don't, rerecognize it. This will
3452 cause spurious re-recognition if the old move had a PARALLEL since
3453 the new one still will, but we can't call single_set without
3454 having put NEW_BODY into the insn and the re-recognition won't
3455 hurt in this rare case. */
3456 /* ??? Why this huge if statement - why don't we just rerecognize the
3460 && ((REG_P (SET_SRC (old_set))
3461 && (GET_CODE (new_body) != SET
3462 || !REG_P (SET_SRC (new_body))))
3463 /* If this was a load from or store to memory, compare
3464 the MEM in recog_data.operand to the one in the insn.
3465 If they are not equal, then rerecognize the insn. */
3467 && ((MEM_P (SET_SRC (old_set))
3468 && SET_SRC (old_set) != recog_data.operand[1])
3469 || (MEM_P (SET_DEST (old_set))
3470 && SET_DEST (old_set) != recog_data.operand[0])))
3471 /* If this was an add insn before, rerecognize. */
3472 || GET_CODE (SET_SRC (old_set)) == PLUS))
3474 int new_icode = recog (PATTERN (insn), insn, 0);
3476 INSN_CODE (insn) = new_icode;
3480 /* Restore the old body. If there were any changes to it, we made a copy
3481 of it while the changes were still in place, so we'll correctly return
3482 a modified insn below. */
3485 /* Restore the old body. */
3486 for (i = 0; i < recog_data.n_operands; i++)
3487 *recog_data.operand_loc[i] = orig_operand[i];
3488 for (i = 0; i < recog_data.n_dups; i++)
3489 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3492 /* Update all elimination pairs to reflect the status after the current
3493 insn. The changes we make were determined by the earlier call to
3494 elimination_effects.
3496 We also detect cases where register elimination cannot be done,
3497 namely, if a register would be both changed and referenced outside a MEM
3498 in the resulting insn since such an insn is often undefined and, even if
3499 not, we cannot know what meaning will be given to it. Note that it is
3500 valid to have a register used in an address in an insn that changes it
3501 (presumably with a pre- or post-increment or decrement).
3503 If anything changes, return nonzero. */
3505 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3507 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3508 ep->can_eliminate = 0;
3510 ep->ref_outside_mem = 0;
3512 if (ep->previous_offset != ep->offset)
3517 /* If we changed something, perform elimination in REG_NOTES. This is
3518 needed even when REPLACE is zero because a REG_DEAD note might refer
3519 to a register that we eliminate and could cause a different number
3520 of spill registers to be needed in the final reload pass than in
3522 if (val && REG_NOTES (insn) != 0)
3524 = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true);
3529 /* Loop through all elimination pairs.
3530 Recalculate the number not at initial offset.
3532 Compute the maximum offset (minimum offset if the stack does not
3533 grow downward) for each elimination pair. */
3536 update_eliminable_offsets (void)
3538 struct elim_table *ep;
3540 num_not_at_initial_offset = 0;
3541 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3543 ep->previous_offset = ep->offset;
3544 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3545 num_not_at_initial_offset++;
3549 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3550 replacement we currently believe is valid, mark it as not eliminable if X
3551 modifies DEST in any way other than by adding a constant integer to it.
3553 If DEST is the frame pointer, we do nothing because we assume that
3554 all assignments to the hard frame pointer are nonlocal gotos and are being
3555 done at a time when they are valid and do not disturb anything else.
3556 Some machines want to eliminate a fake argument pointer with either the
3557 frame or stack pointer. Assignments to the hard frame pointer must not
3558 prevent this elimination.
3560 Called via note_stores from reload before starting its passes to scan
3561 the insns of the function. */
3564 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3568 /* A SUBREG of a hard register here is just changing its mode. We should
3569 not see a SUBREG of an eliminable hard register, but check just in
3571 if (GET_CODE (dest) == SUBREG)
3572 dest = SUBREG_REG (dest);
3574 if (dest == hard_frame_pointer_rtx)
3577 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3578 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3579 && (GET_CODE (x) != SET
3580 || GET_CODE (SET_SRC (x)) != PLUS
3581 || XEXP (SET_SRC (x), 0) != dest
3582 || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
3584 reg_eliminate[i].can_eliminate_previous
3585 = reg_eliminate[i].can_eliminate = 0;
3590 /* Verify that the initial elimination offsets did not change since the
3591 last call to set_initial_elim_offsets. This is used to catch cases
3592 where something illegal happened during reload_as_needed that could
3593 cause incorrect code to be generated if we did not check for it. */
3596 verify_initial_elim_offsets (void)
3600 if (!num_eliminable)
3603 #ifdef ELIMINABLE_REGS
3605 struct elim_table *ep;
3607 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3609 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3610 if (t != ep->initial_offset)
3615 INITIAL_FRAME_POINTER_OFFSET (t);
3616 if (t != reg_eliminate[0].initial_offset)
3623 /* Reset all offsets on eliminable registers to their initial values. */
3626 set_initial_elim_offsets (void)
3628 struct elim_table *ep = reg_eliminate;
3630 #ifdef ELIMINABLE_REGS
3631 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3633 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3634 ep->previous_offset = ep->offset = ep->initial_offset;
3637 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3638 ep->previous_offset = ep->offset = ep->initial_offset;
3641 num_not_at_initial_offset = 0;
3644 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3647 set_initial_eh_label_offset (rtx label)
3649 set_label_offsets (label, NULL_RTX, 1);
3652 /* Initialize the known label offsets.
3653 Set a known offset for each forced label to be at the initial offset
3654 of each elimination. We do this because we assume that all
3655 computed jumps occur from a location where each elimination is
3656 at its initial offset.
3657 For all other labels, show that we don't know the offsets. */
3660 set_initial_label_offsets (void)
3663 memset (offsets_known_at, 0, num_labels);
3665 for (x = forced_labels; x; x = XEXP (x, 1))
3667 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3669 for_each_eh_label (set_initial_eh_label_offset);
3672 /* Set all elimination offsets to the known values for the code label given
3676 set_offsets_for_label (rtx insn)
3679 int label_nr = CODE_LABEL_NUMBER (insn);
3680 struct elim_table *ep;
3682 num_not_at_initial_offset = 0;
3683 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3685 ep->offset = ep->previous_offset
3686 = offsets_at[label_nr - first_label_num][i];
3687 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3688 num_not_at_initial_offset++;
3692 /* See if anything that happened changes which eliminations are valid.
3693 For example, on the SPARC, whether or not the frame pointer can
3694 be eliminated can depend on what registers have been used. We need
3695 not check some conditions again (such as flag_omit_frame_pointer)
3696 since they can't have changed. */
3699 update_eliminables (HARD_REG_SET *pset)
3701 int previous_frame_pointer_needed = frame_pointer_needed;
3702 struct elim_table *ep;
3704 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3705 if ((ep->from == HARD_FRAME_POINTER_REGNUM
3706 && targetm.frame_pointer_required ())
3707 #ifdef ELIMINABLE_REGS
3708 || ! CAN_ELIMINATE (ep->from, ep->to)
3711 ep->can_eliminate = 0;
3713 /* Look for the case where we have discovered that we can't replace
3714 register A with register B and that means that we will now be
3715 trying to replace register A with register C. This means we can
3716 no longer replace register C with register B and we need to disable
3717 such an elimination, if it exists. This occurs often with A == ap,
3718 B == sp, and C == fp. */
3720 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3722 struct elim_table *op;
3725 if (! ep->can_eliminate && ep->can_eliminate_previous)
3727 /* Find the current elimination for ep->from, if there is a
3729 for (op = reg_eliminate;
3730 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3731 if (op->from == ep->from && op->can_eliminate)
3737 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3739 for (op = reg_eliminate;
3740 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3741 if (op->from == new_to && op->to == ep->to)
3742 op->can_eliminate = 0;
3746 /* See if any registers that we thought we could eliminate the previous
3747 time are no longer eliminable. If so, something has changed and we
3748 must spill the register. Also, recompute the number of eliminable
3749 registers and see if the frame pointer is needed; it is if there is
3750 no elimination of the frame pointer that we can perform. */
3752 frame_pointer_needed = 1;
3753 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3755 if (ep->can_eliminate
3756 && ep->from == FRAME_POINTER_REGNUM
3757 && ep->to != HARD_FRAME_POINTER_REGNUM
3758 && (! SUPPORTS_STACK_ALIGNMENT
3759 || ! crtl->stack_realign_needed))
3760 frame_pointer_needed = 0;
3762 if (! ep->can_eliminate && ep->can_eliminate_previous)
3764 ep->can_eliminate_previous = 0;
3765 SET_HARD_REG_BIT (*pset, ep->from);
3770 /* If we didn't need a frame pointer last time, but we do now, spill
3771 the hard frame pointer. */
3772 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3773 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3776 /* Return true if X is used as the target register of an elimination. */
3779 elimination_target_reg_p (rtx x)
3781 struct elim_table *ep;
3783 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3784 if (ep->to_rtx == x && ep->can_eliminate)
3790 /* Initialize the table of registers to eliminate.
3791 Pre-condition: global flag frame_pointer_needed has been set before
3792 calling this function. */
3795 init_elim_table (void)
3797 struct elim_table *ep;
3798 #ifdef ELIMINABLE_REGS
3799 const struct elim_table_1 *ep1;
3803 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
3807 #ifdef ELIMINABLE_REGS
3808 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3809 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3811 ep->from = ep1->from;
3813 ep->can_eliminate = ep->can_eliminate_previous
3814 = (CAN_ELIMINATE (ep->from, ep->to)
3815 && ! (ep->to == STACK_POINTER_REGNUM
3816 && frame_pointer_needed
3817 && (! SUPPORTS_STACK_ALIGNMENT
3818 || ! stack_realign_fp)));
3821 reg_eliminate[0].from = reg_eliminate_1[0].from;
3822 reg_eliminate[0].to = reg_eliminate_1[0].to;
3823 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3824 = ! frame_pointer_needed;
3827 /* Count the number of eliminable registers and build the FROM and TO
3828 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3829 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3830 We depend on this. */
3831 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3833 num_eliminable += ep->can_eliminate;
3834 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3835 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3839 /* Kick all pseudos out of hard register REGNO.
3841 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3842 because we found we can't eliminate some register. In the case, no pseudos
3843 are allowed to be in the register, even if they are only in a block that
3844 doesn't require spill registers, unlike the case when we are spilling this
3845 hard reg to produce another spill register.
3847 Return nonzero if any pseudos needed to be kicked out. */
3850 spill_hard_reg (unsigned int regno, int cant_eliminate)
3856 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3857 df_set_regs_ever_live (regno, true);
3860 /* Spill every pseudo reg that was allocated to this reg
3861 or to something that overlaps this reg. */
3863 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3864 if (reg_renumber[i] >= 0
3865 && (unsigned int) reg_renumber[i] <= regno
3866 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
3867 SET_REGNO_REG_SET (&spilled_pseudos, i);
3870 /* After find_reload_regs has been run for all insn that need reloads,
3871 and/or spill_hard_regs was called, this function is used to actually
3872 spill pseudo registers and try to reallocate them. It also sets up the
3873 spill_regs array for use by choose_reload_regs. */
3876 finish_spills (int global)
3878 struct insn_chain *chain;
3879 int something_changed = 0;
3881 reg_set_iterator rsi;
3883 /* Build the spill_regs array for the function. */
3884 /* If there are some registers still to eliminate and one of the spill regs
3885 wasn't ever used before, additional stack space may have to be
3886 allocated to store this register. Thus, we may have changed the offset
3887 between the stack and frame pointers, so mark that something has changed.
3889 One might think that we need only set VAL to 1 if this is a call-used
3890 register. However, the set of registers that must be saved by the
3891 prologue is not identical to the call-used set. For example, the
3892 register used by the call insn for the return PC is a call-used register,
3893 but must be saved by the prologue. */
3896 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3897 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3899 spill_reg_order[i] = n_spills;
3900 spill_regs[n_spills++] = i;
3901 if (num_eliminable && ! df_regs_ever_live_p (i))
3902 something_changed = 1;
3903 df_set_regs_ever_live (i, true);
3906 spill_reg_order[i] = -1;
3908 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3909 if (! ira_conflicts_p || reg_renumber[i] >= 0)
3911 /* Record the current hard register the pseudo is allocated to
3912 in pseudo_previous_regs so we avoid reallocating it to the
3913 same hard reg in a later pass. */
3914 gcc_assert (reg_renumber[i] >= 0);
3916 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3917 /* Mark it as no longer having a hard register home. */
3918 reg_renumber[i] = -1;
3919 if (ira_conflicts_p)
3920 /* Inform IRA about the change. */
3921 ira_mark_allocation_change (i);
3922 /* We will need to scan everything again. */
3923 something_changed = 1;
3926 /* Retry global register allocation if possible. */
3927 if (global && ira_conflicts_p)
3931 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3932 /* For every insn that needs reloads, set the registers used as spill
3933 regs in pseudo_forbidden_regs for every pseudo live across the
3935 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3937 EXECUTE_IF_SET_IN_REG_SET
3938 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3940 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3941 chain->used_spill_regs);
3943 EXECUTE_IF_SET_IN_REG_SET
3944 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3946 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3947 chain->used_spill_regs);
3951 /* Retry allocating the pseudos spilled in IRA and the
3952 reload. For each reg, merge the various reg sets that
3953 indicate which hard regs can't be used, and call
3954 ira_reassign_pseudos. */
3955 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
3956 if (reg_old_renumber[i] != reg_renumber[i])
3958 if (reg_renumber[i] < 0)
3959 temp_pseudo_reg_arr[n++] = i;
3961 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3963 if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
3964 bad_spill_regs_global,
3965 pseudo_forbidden_regs, pseudo_previous_regs,
3967 something_changed = 1;
3969 /* Fix up the register information in the insn chain.
3970 This involves deleting those of the spilled pseudos which did not get
3971 a new hard register home from the live_{before,after} sets. */
3972 for (chain = reload_insn_chain; chain; chain = chain->next)
3974 HARD_REG_SET used_by_pseudos;
3975 HARD_REG_SET used_by_pseudos2;
3977 if (! ira_conflicts_p)
3979 /* Don't do it for IRA because IRA and the reload still can
3980 assign hard registers to the spilled pseudos on next
3981 reload iterations. */
3982 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3983 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3985 /* Mark any unallocated hard regs as available for spills. That
3986 makes inheritance work somewhat better. */
3987 if (chain->need_reload)
3989 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3990 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3991 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3993 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3994 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3995 /* Value of chain->used_spill_regs from previous iteration
3996 may be not included in the value calculated here because
3997 of possible removing caller-saves insns (see function
3998 delete_caller_save_insns. */
3999 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4000 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4004 CLEAR_REG_SET (&changed_allocation_pseudos);
4005 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4006 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4008 int regno = reg_renumber[i];
4009 if (reg_old_renumber[i] == regno)
4012 SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4014 alter_reg (i, reg_old_renumber[i], false);
4015 reg_old_renumber[i] = regno;
4019 fprintf (dump_file, " Register %d now on stack.\n\n", i);
4021 fprintf (dump_file, " Register %d now in %d.\n\n",
4022 i, reg_renumber[i]);
4026 return something_changed;
4029 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4032 scan_paradoxical_subregs (rtx x)
4036 enum rtx_code code = GET_CODE (x);
4047 case CONST_VECTOR: /* shouldn't happen, but just in case. */
4055 if (REG_P (SUBREG_REG (x))
4056 && (GET_MODE_SIZE (GET_MODE (x))
4057 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
4059 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4060 = GET_MODE_SIZE (GET_MODE (x));
4061 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
4069 fmt = GET_RTX_FORMAT (code);
4070 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4073 scan_paradoxical_subregs (XEXP (x, i));
4074 else if (fmt[i] == 'E')
4077 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4078 scan_paradoxical_subregs (XVECEXP (x, i, j));
4083 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4084 examine all of the reload insns between PREV and NEXT exclusive, and
4085 annotate all that may trap. */
4088 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
4090 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4096 if (! may_trap_p (PATTERN (insn)))
4097 remove_note (insn, note);
4099 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
4100 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
4101 add_reg_note (i, REG_EH_REGION, XEXP (note, 0));
4104 /* Reload pseudo-registers into hard regs around each insn as needed.
4105 Additional register load insns are output before the insn that needs it
4106 and perhaps store insns after insns that modify the reloaded pseudo reg.
4108 reg_last_reload_reg and reg_reloaded_contents keep track of
4109 which registers are already available in reload registers.
4110 We update these for the reloads that we perform,
4111 as the insns are scanned. */
4114 reload_as_needed (int live_known)
4116 struct insn_chain *chain;
4117 #if defined (AUTO_INC_DEC)
4122 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4123 memset (spill_reg_store, 0, sizeof spill_reg_store);
4124 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4125 INIT_REG_SET (®_has_output_reload);
4126 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4127 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4129 set_initial_elim_offsets ();
4131 for (chain = reload_insn_chain; chain; chain = chain->next)
4134 rtx insn = chain->insn;
4135 rtx old_next = NEXT_INSN (insn);
4137 rtx old_prev = PREV_INSN (insn);
4140 /* If we pass a label, copy the offsets from the label information
4141 into the current offsets of each elimination. */
4143 set_offsets_for_label (insn);
4145 else if (INSN_P (insn))
4147 regset_head regs_to_forget;
4148 INIT_REG_SET (®s_to_forget);
4149 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4151 /* If this is a USE and CLOBBER of a MEM, ensure that any
4152 references to eliminable registers have been removed. */
4154 if ((GET_CODE (PATTERN (insn)) == USE
4155 || GET_CODE (PATTERN (insn)) == CLOBBER)
4156 && MEM_P (XEXP (PATTERN (insn), 0)))
4157 XEXP (XEXP (PATTERN (insn), 0), 0)
4158 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4159 GET_MODE (XEXP (PATTERN (insn), 0)),
4162 /* If we need to do register elimination processing, do so.
4163 This might delete the insn, in which case we are done. */
4164 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4166 eliminate_regs_in_insn (insn, 1);
4169 update_eliminable_offsets ();
4170 CLEAR_REG_SET (®s_to_forget);
4175 /* If need_elim is nonzero but need_reload is zero, one might think
4176 that we could simply set n_reloads to 0. However, find_reloads
4177 could have done some manipulation of the insn (such as swapping
4178 commutative operands), and these manipulations are lost during
4179 the first pass for every insn that needs register elimination.
4180 So the actions of find_reloads must be redone here. */
4182 if (! chain->need_elim && ! chain->need_reload
4183 && ! chain->need_operand_change)
4185 /* First find the pseudo regs that must be reloaded for this insn.
4186 This info is returned in the tables reload_... (see reload.h).
4187 Also modify the body of INSN by substituting RELOAD
4188 rtx's for those pseudo regs. */
4191 CLEAR_REG_SET (®_has_output_reload);
4192 CLEAR_HARD_REG_SET (reg_is_output_reload);
4194 find_reloads (insn, 1, spill_indirect_levels, live_known,
4200 rtx next = NEXT_INSN (insn);
4203 prev = PREV_INSN (insn);
4205 /* Now compute which reload regs to reload them into. Perhaps
4206 reusing reload regs from previous insns, or else output
4207 load insns to reload them. Maybe output store insns too.
4208 Record the choices of reload reg in reload_reg_rtx. */
4209 choose_reload_regs (chain);
4211 /* Merge any reloads that we didn't combine for fear of
4212 increasing the number of spill registers needed but now
4213 discover can be safely merged. */
4214 if (SMALL_REGISTER_CLASSES)
4215 merge_assigned_reloads (insn);
4217 /* Generate the insns to reload operands into or out of
4218 their reload regs. */
4219 emit_reload_insns (chain);
4221 /* Substitute the chosen reload regs from reload_reg_rtx
4222 into the insn's body (or perhaps into the bodies of other
4223 load and store insn that we just made for reloading
4224 and that we moved the structure into). */
4225 subst_reloads (insn);
4227 /* Adjust the exception region notes for loads and stores. */
4228 if (flag_non_call_exceptions && !CALL_P (insn))
4229 fixup_eh_region_note (insn, prev, next);
4231 /* If this was an ASM, make sure that all the reload insns
4232 we have generated are valid. If not, give an error
4234 if (asm_noperands (PATTERN (insn)) >= 0)
4235 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4236 if (p != insn && INSN_P (p)
4237 && GET_CODE (PATTERN (p)) != USE
4238 && (recog_memoized (p) < 0
4239 || (extract_insn (p), ! constrain_operands (1))))
4241 error_for_asm (insn,
4242 "%<asm%> operand requires "
4243 "impossible reload");
4248 if (num_eliminable && chain->need_elim)
4249 update_eliminable_offsets ();
4251 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4252 is no longer validly lying around to save a future reload.
4253 Note that this does not detect pseudos that were reloaded
4254 for this insn in order to be stored in
4255 (obeying register constraints). That is correct; such reload
4256 registers ARE still valid. */
4257 forget_marked_reloads (®s_to_forget);
4258 CLEAR_REG_SET (®s_to_forget);
4260 /* There may have been CLOBBER insns placed after INSN. So scan
4261 between INSN and NEXT and use them to forget old reloads. */
4262 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4263 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4264 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4267 /* Likewise for regs altered by auto-increment in this insn.
4268 REG_INC notes have been changed by reloading:
4269 find_reloads_address_1 records substitutions for them,
4270 which have been performed by subst_reloads above. */
4271 for (i = n_reloads - 1; i >= 0; i--)
4273 rtx in_reg = rld[i].in_reg;
4276 enum rtx_code code = GET_CODE (in_reg);
4277 /* PRE_INC / PRE_DEC will have the reload register ending up
4278 with the same value as the stack slot, but that doesn't
4279 hold true for POST_INC / POST_DEC. Either we have to
4280 convert the memory access to a true POST_INC / POST_DEC,
4281 or we can't use the reload register for inheritance. */
4282 if ((code == POST_INC || code == POST_DEC)
4283 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4284 REGNO (rld[i].reg_rtx))
4285 /* Make sure it is the inc/dec pseudo, and not
4286 some other (e.g. output operand) pseudo. */
4287 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4288 == REGNO (XEXP (in_reg, 0))))
4291 rtx reload_reg = rld[i].reg_rtx;
4292 enum machine_mode mode = GET_MODE (reload_reg);
4296 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4298 /* We really want to ignore REG_INC notes here, so
4299 use PATTERN (p) as argument to reg_set_p . */
4300 if (reg_set_p (reload_reg, PATTERN (p)))
4302 n = count_occurrences (PATTERN (p), reload_reg, 0);
4307 n = validate_replace_rtx (reload_reg,
4308 gen_rtx_fmt_e (code,
4313 /* We must also verify that the constraints
4314 are met after the replacement. */
4317 n = constrain_operands (1);
4321 /* If the constraints were not met, then
4322 undo the replacement. */
4325 validate_replace_rtx (gen_rtx_fmt_e (code,
4337 add_reg_note (p, REG_INC, reload_reg);
4338 /* Mark this as having an output reload so that the
4339 REG_INC processing code below won't invalidate
4340 the reload for inheritance. */
4341 SET_HARD_REG_BIT (reg_is_output_reload,
4342 REGNO (reload_reg));
4343 SET_REGNO_REG_SET (®_has_output_reload,
4344 REGNO (XEXP (in_reg, 0)));
4347 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4350 else if ((code == PRE_INC || code == PRE_DEC)
4351 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4352 REGNO (rld[i].reg_rtx))
4353 /* Make sure it is the inc/dec pseudo, and not
4354 some other (e.g. output operand) pseudo. */
4355 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4356 == REGNO (XEXP (in_reg, 0))))
4358 SET_HARD_REG_BIT (reg_is_output_reload,
4359 REGNO (rld[i].reg_rtx));
4360 SET_REGNO_REG_SET (®_has_output_reload,
4361 REGNO (XEXP (in_reg, 0)));
4363 else if (code == PRE_INC || code == PRE_DEC
4364 || code == POST_INC || code == POST_DEC)
4366 int in_regno = REGNO (XEXP (in_reg, 0));
4368 if (reg_last_reload_reg[in_regno] != NULL_RTX)
4371 bool forget_p = true;
4373 in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4374 if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4377 for (x = old_prev ? NEXT_INSN (old_prev) : insn;
4380 if (x == reg_reloaded_insn[in_hard_regno])
4386 /* If for some reasons, we didn't set up
4387 reg_last_reload_reg in this insn,
4388 invalidate inheritance from previous
4389 insns for the incremented/decremented
4390 register. Such registers will be not in
4391 reg_has_output_reload. Invalidate it
4392 also if the corresponding element in
4393 reg_reloaded_insn is also
4396 forget_old_reloads_1 (XEXP (in_reg, 0),
4402 /* If a pseudo that got a hard register is auto-incremented,
4403 we must purge records of copying it into pseudos without
4405 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4406 if (REG_NOTE_KIND (x) == REG_INC)
4408 /* See if this pseudo reg was reloaded in this insn.
4409 If so, its last-reload info is still valid
4410 because it is based on this insn's reload. */
4411 for (i = 0; i < n_reloads; i++)
4412 if (rld[i].out == XEXP (x, 0))
4416 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4420 /* A reload reg's contents are unknown after a label. */
4422 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4424 /* Don't assume a reload reg is still good after a call insn
4425 if it is a call-used reg, or if it contains a value that will
4426 be partially clobbered by the call. */
4427 else if (CALL_P (insn))
4429 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4430 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4435 free (reg_last_reload_reg);
4436 CLEAR_REG_SET (®_has_output_reload);
4439 /* Discard all record of any value reloaded from X,
4440 or reloaded in X from someplace else;
4441 unless X is an output reload reg of the current insn.
4443 X may be a hard reg (the reload reg)
4444 or it may be a pseudo reg that was reloaded from.
4446 When DATA is non-NULL just mark the registers in regset
4447 to be forgotten later. */
4450 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4455 regset regs = (regset) data;
4457 /* note_stores does give us subregs of hard regs,
4458 subreg_regno_offset requires a hard reg. */
4459 while (GET_CODE (x) == SUBREG)
4461 /* We ignore the subreg offset when calculating the regno,
4462 because we are using the entire underlying hard register
4472 if (regno >= FIRST_PSEUDO_REGISTER)
4478 nr = hard_regno_nregs[regno][GET_MODE (x)];
4479 /* Storing into a spilled-reg invalidates its contents.
4480 This can happen if a block-local pseudo is allocated to that reg
4481 and it wasn't spilled because this block's total need is 0.
4482 Then some insn might have an optional reload and use this reg. */
4484 for (i = 0; i < nr; i++)
4485 /* But don't do this if the reg actually serves as an output
4486 reload reg in the current instruction. */
4488 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4490 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4491 spill_reg_store[regno + i] = 0;
4497 SET_REGNO_REG_SET (regs, regno + nr);
4500 /* Since value of X has changed,
4501 forget any value previously copied from it. */
4504 /* But don't forget a copy if this is the output reload
4505 that establishes the copy's validity. */
4507 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4508 reg_last_reload_reg[regno + nr] = 0;
4512 /* Forget the reloads marked in regset by previous function. */
4514 forget_marked_reloads (regset regs)
4517 reg_set_iterator rsi;
4518 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4520 if (reg < FIRST_PSEUDO_REGISTER
4521 /* But don't do this if the reg actually serves as an output
4522 reload reg in the current instruction. */
4524 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4526 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4527 spill_reg_store[reg] = 0;
4530 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4531 reg_last_reload_reg[reg] = 0;
4535 /* The following HARD_REG_SETs indicate when each hard register is
4536 used for a reload of various parts of the current insn. */
4538 /* If reg is unavailable for all reloads. */
4539 static HARD_REG_SET reload_reg_unavailable;
4540 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4541 static HARD_REG_SET reload_reg_used;
4542 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4543 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4544 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4545 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4546 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4547 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4548 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4549 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4550 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4551 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4552 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4553 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4554 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4555 static HARD_REG_SET reload_reg_used_in_op_addr;
4556 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4557 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4558 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4559 static HARD_REG_SET reload_reg_used_in_insn;
4560 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4561 static HARD_REG_SET reload_reg_used_in_other_addr;
4563 /* If reg is in use as a reload reg for any sort of reload. */
4564 static HARD_REG_SET reload_reg_used_at_all;
4566 /* If reg is use as an inherited reload. We just mark the first register
4568 static HARD_REG_SET reload_reg_used_for_inherit;
4570 /* Records which hard regs are used in any way, either as explicit use or
4571 by being allocated to a pseudo during any point of the current insn. */
4572 static HARD_REG_SET reg_used_in_insn;
4574 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4575 TYPE. MODE is used to indicate how many consecutive regs are
4579 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4580 enum machine_mode mode)
4582 unsigned int nregs = hard_regno_nregs[regno][mode];
4585 for (i = regno; i < nregs + regno; i++)
4590 SET_HARD_REG_BIT (reload_reg_used, i);
4593 case RELOAD_FOR_INPUT_ADDRESS:
4594 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4597 case RELOAD_FOR_INPADDR_ADDRESS:
4598 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4601 case RELOAD_FOR_OUTPUT_ADDRESS:
4602 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4605 case RELOAD_FOR_OUTADDR_ADDRESS:
4606 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4609 case RELOAD_FOR_OPERAND_ADDRESS:
4610 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4613 case RELOAD_FOR_OPADDR_ADDR:
4614 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4617 case RELOAD_FOR_OTHER_ADDRESS:
4618 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4621 case RELOAD_FOR_INPUT:
4622 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4625 case RELOAD_FOR_OUTPUT:
4626 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4629 case RELOAD_FOR_INSN:
4630 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4634 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4638 /* Similarly, but show REGNO is no longer in use for a reload. */
4641 clear_reload_reg_in_use (unsigned int regno, int opnum,
4642 enum reload_type type, enum machine_mode mode)
4644 unsigned int nregs = hard_regno_nregs[regno][mode];
4645 unsigned int start_regno, end_regno, r;
4647 /* A complication is that for some reload types, inheritance might
4648 allow multiple reloads of the same types to share a reload register.
4649 We set check_opnum if we have to check only reloads with the same
4650 operand number, and check_any if we have to check all reloads. */
4651 int check_opnum = 0;
4653 HARD_REG_SET *used_in_set;
4658 used_in_set = &reload_reg_used;
4661 case RELOAD_FOR_INPUT_ADDRESS:
4662 used_in_set = &reload_reg_used_in_input_addr[opnum];
4665 case RELOAD_FOR_INPADDR_ADDRESS:
4667 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4670 case RELOAD_FOR_OUTPUT_ADDRESS:
4671 used_in_set = &reload_reg_used_in_output_addr[opnum];
4674 case RELOAD_FOR_OUTADDR_ADDRESS:
4676 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4679 case RELOAD_FOR_OPERAND_ADDRESS:
4680 used_in_set = &reload_reg_used_in_op_addr;
4683 case RELOAD_FOR_OPADDR_ADDR:
4685 used_in_set = &reload_reg_used_in_op_addr_reload;
4688 case RELOAD_FOR_OTHER_ADDRESS:
4689 used_in_set = &reload_reg_used_in_other_addr;
4693 case RELOAD_FOR_INPUT:
4694 used_in_set = &reload_reg_used_in_input[opnum];
4697 case RELOAD_FOR_OUTPUT:
4698 used_in_set = &reload_reg_used_in_output[opnum];
4701 case RELOAD_FOR_INSN:
4702 used_in_set = &reload_reg_used_in_insn;
4707 /* We resolve conflicts with remaining reloads of the same type by
4708 excluding the intervals of reload registers by them from the
4709 interval of freed reload registers. Since we only keep track of
4710 one set of interval bounds, we might have to exclude somewhat
4711 more than what would be necessary if we used a HARD_REG_SET here.
4712 But this should only happen very infrequently, so there should
4713 be no reason to worry about it. */
4715 start_regno = regno;
4716 end_regno = regno + nregs;
4717 if (check_opnum || check_any)
4719 for (i = n_reloads - 1; i >= 0; i--)
4721 if (rld[i].when_needed == type
4722 && (check_any || rld[i].opnum == opnum)
4725 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4726 unsigned int conflict_end
4727 = end_hard_regno (rld[i].mode, conflict_start);
4729 /* If there is an overlap with the first to-be-freed register,
4730 adjust the interval start. */
4731 if (conflict_start <= start_regno && conflict_end > start_regno)
4732 start_regno = conflict_end;
4733 /* Otherwise, if there is a conflict with one of the other
4734 to-be-freed registers, adjust the interval end. */
4735 if (conflict_start > start_regno && conflict_start < end_regno)
4736 end_regno = conflict_start;
4741 for (r = start_regno; r < end_regno; r++)
4742 CLEAR_HARD_REG_BIT (*used_in_set, r);
4745 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4746 specified by OPNUM and TYPE. */
4749 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4753 /* In use for a RELOAD_OTHER means it's not available for anything. */
4754 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4755 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4761 /* In use for anything means we can't use it for RELOAD_OTHER. */
4762 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4763 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4764 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4765 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4768 for (i = 0; i < reload_n_operands; i++)
4769 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4770 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4771 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4772 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4773 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4774 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4779 case RELOAD_FOR_INPUT:
4780 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4781 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4784 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4787 /* If it is used for some other input, can't use it. */
4788 for (i = 0; i < reload_n_operands; i++)
4789 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4792 /* If it is used in a later operand's address, can't use it. */
4793 for (i = opnum + 1; i < reload_n_operands; i++)
4794 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4795 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4800 case RELOAD_FOR_INPUT_ADDRESS:
4801 /* Can't use a register if it is used for an input address for this
4802 operand or used as an input in an earlier one. */
4803 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4804 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4807 for (i = 0; i < opnum; i++)
4808 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4813 case RELOAD_FOR_INPADDR_ADDRESS:
4814 /* Can't use a register if it is used for an input address
4815 for this operand or used as an input in an earlier
4817 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4820 for (i = 0; i < opnum; i++)
4821 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4826 case RELOAD_FOR_OUTPUT_ADDRESS:
4827 /* Can't use a register if it is used for an output address for this
4828 operand or used as an output in this or a later operand. Note
4829 that multiple output operands are emitted in reverse order, so
4830 the conflicting ones are those with lower indices. */
4831 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4834 for (i = 0; i <= opnum; i++)
4835 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4840 case RELOAD_FOR_OUTADDR_ADDRESS:
4841 /* Can't use a register if it is used for an output address
4842 for this operand or used as an output in this or a
4843 later operand. Note that multiple output operands are
4844 emitted in reverse order, so the conflicting ones are
4845 those with lower indices. */
4846 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4849 for (i = 0; i <= opnum; i++)
4850 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4855 case RELOAD_FOR_OPERAND_ADDRESS:
4856 for (i = 0; i < reload_n_operands; i++)
4857 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4860 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4861 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4863 case RELOAD_FOR_OPADDR_ADDR:
4864 for (i = 0; i < reload_n_operands; i++)
4865 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4868 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4870 case RELOAD_FOR_OUTPUT:
4871 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4872 outputs, or an operand address for this or an earlier output.
4873 Note that multiple output operands are emitted in reverse order,
4874 so the conflicting ones are those with higher indices. */
4875 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4878 for (i = 0; i < reload_n_operands; i++)
4879 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4882 for (i = opnum; i < reload_n_operands; i++)
4883 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4884 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4889 case RELOAD_FOR_INSN:
4890 for (i = 0; i < reload_n_operands; i++)
4891 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4892 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4895 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4896 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4898 case RELOAD_FOR_OTHER_ADDRESS:
4899 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4906 /* Return 1 if the value in reload reg REGNO, as used by a reload
4907 needed for the part of the insn specified by OPNUM and TYPE,
4908 is still available in REGNO at the end of the insn.
4910 We can assume that the reload reg was already tested for availability
4911 at the time it is needed, and we should not check this again,
4912 in case the reg has already been marked in use. */
4915 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4922 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4923 its value must reach the end. */
4926 /* If this use is for part of the insn,
4927 its value reaches if no subsequent part uses the same register.
4928 Just like the above function, don't try to do this with lots
4931 case RELOAD_FOR_OTHER_ADDRESS:
4932 /* Here we check for everything else, since these don't conflict
4933 with anything else and everything comes later. */
4935 for (i = 0; i < reload_n_operands; i++)
4936 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4937 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4938 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4939 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4940 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4941 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4944 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4945 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4946 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4947 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4949 case RELOAD_FOR_INPUT_ADDRESS:
4950 case RELOAD_FOR_INPADDR_ADDRESS:
4951 /* Similar, except that we check only for this and subsequent inputs
4952 and the address of only subsequent inputs and we do not need
4953 to check for RELOAD_OTHER objects since they are known not to
4956 for (i = opnum; i < reload_n_operands; i++)
4957 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4960 for (i = opnum + 1; i < reload_n_operands; i++)
4961 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4962 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4965 for (i = 0; i < reload_n_operands; i++)
4966 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4967 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4968 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4971 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4974 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4975 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4976 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4978 case RELOAD_FOR_INPUT:
4979 /* Similar to input address, except we start at the next operand for
4980 both input and input address and we do not check for
4981 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4984 for (i = opnum + 1; i < reload_n_operands; i++)
4985 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4986 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4987 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4990 /* ... fall through ... */
4992 case RELOAD_FOR_OPERAND_ADDRESS:
4993 /* Check outputs and their addresses. */
4995 for (i = 0; i < reload_n_operands; i++)
4996 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4997 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4998 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5001 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5003 case RELOAD_FOR_OPADDR_ADDR:
5004 for (i = 0; i < reload_n_operands; i++)
5005 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5006 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5007 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5010 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5011 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5012 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5014 case RELOAD_FOR_INSN:
5015 /* These conflict with other outputs with RELOAD_OTHER. So
5016 we need only check for output addresses. */
5018 opnum = reload_n_operands;
5020 /* ... fall through ... */
5022 case RELOAD_FOR_OUTPUT:
5023 case RELOAD_FOR_OUTPUT_ADDRESS:
5024 case RELOAD_FOR_OUTADDR_ADDRESS:
5025 /* We already know these can't conflict with a later output. So the
5026 only thing to check are later output addresses.
5027 Note that multiple output operands are emitted in reverse order,
5028 so the conflicting ones are those with lower indices. */
5029 for (i = 0; i < opnum; i++)
5030 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5031 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5041 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5042 every register in the range [REGNO, REGNO + NREGS). */
5045 reload_regs_reach_end_p (unsigned int regno, int nregs,
5046 int opnum, enum reload_type type)
5050 for (i = 0; i < nregs; i++)
5051 if (!reload_reg_reaches_end_p (regno + i, opnum, type))
5057 /* Returns whether R1 and R2 are uniquely chained: the value of one
5058 is used by the other, and that value is not used by any other
5059 reload for this insn. This is used to partially undo the decision
5060 made in find_reloads when in the case of multiple
5061 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5062 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5063 reloads. This code tries to avoid the conflict created by that
5064 change. It might be cleaner to explicitly keep track of which
5065 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5066 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5067 this after the fact. */
5069 reloads_unique_chain_p (int r1, int r2)
5073 /* We only check input reloads. */
5074 if (! rld[r1].in || ! rld[r2].in)
5077 /* Avoid anything with output reloads. */
5078 if (rld[r1].out || rld[r2].out)
5081 /* "chained" means one reload is a component of the other reload,
5082 not the same as the other reload. */
5083 if (rld[r1].opnum != rld[r2].opnum
5084 || rtx_equal_p (rld[r1].in, rld[r2].in)
5085 || rld[r1].optional || rld[r2].optional
5086 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5087 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5090 for (i = 0; i < n_reloads; i ++)
5091 /* Look for input reloads that aren't our two */
5092 if (i != r1 && i != r2 && rld[i].in)
5094 /* If our reload is mentioned at all, it isn't a simple chain. */
5095 if (reg_mentioned_p (rld[r1].in, rld[i].in))
5102 /* The recursive function change all occurrences of WHAT in *WHERE
5105 substitute (rtx *where, const_rtx what, rtx repl)
5114 if (*where == what || rtx_equal_p (*where, what))
5120 code = GET_CODE (*where);
5121 fmt = GET_RTX_FORMAT (code);
5122 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5128 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5129 substitute (&XVECEXP (*where, i, j), what, repl);
5131 else if (fmt[i] == 'e')
5132 substitute (&XEXP (*where, i), what, repl);
5136 /* The function returns TRUE if chain of reload R1 and R2 (in any
5137 order) can be evaluated without usage of intermediate register for
5138 the reload containing another reload. It is important to see
5139 gen_reload to understand what the function is trying to do. As an
5140 example, let us have reload chain
5143 r1: <something> + const
5145 and reload R2 got reload reg HR. The function returns true if
5146 there is a correct insn HR = HR + <something>. Otherwise,
5147 gen_reload will use intermediate register (and this is the reload
5148 reg for R1) to reload <something>.
5150 We need this function to find a conflict for chain reloads. In our
5151 example, if HR = HR + <something> is incorrect insn, then we cannot
5152 use HR as a reload register for R2. If we do use it then we get a
5161 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5165 rtx out, in, tem, insn;
5166 rtx last = get_last_insn ();
5168 /* Make r2 a component of r1. */
5169 if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5175 gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5176 regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5177 gcc_assert (regno >= 0);
5178 out = gen_rtx_REG (rld[r1].mode, regno);
5179 in = copy_rtx (rld[r1].in);
5180 substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5182 /* If IN is a paradoxical SUBREG, remove it and try to put the
5183 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5184 if (GET_CODE (in) == SUBREG
5185 && (GET_MODE_SIZE (GET_MODE (in))
5186 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
5187 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
5188 in = SUBREG_REG (in), out = tem;
5190 if (GET_CODE (in) == PLUS
5191 && (REG_P (XEXP (in, 0))
5192 || GET_CODE (XEXP (in, 0)) == SUBREG
5193 || MEM_P (XEXP (in, 0)))
5194 && (REG_P (XEXP (in, 1))
5195 || GET_CODE (XEXP (in, 1)) == SUBREG
5196 || CONSTANT_P (XEXP (in, 1))
5197 || MEM_P (XEXP (in, 1))))
5199 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
5200 code = recog_memoized (insn);
5205 extract_insn (insn);
5206 /* We want constrain operands to treat this insn strictly in
5207 its validity determination, i.e., the way it would after
5208 reload has completed. */
5209 result = constrain_operands (1);
5212 delete_insns_since (last);
5216 /* It looks like other cases in gen_reload are not possible for
5217 chain reloads or do need an intermediate hard registers. */
5221 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5224 This function uses the same algorithm as reload_reg_free_p above. */
5227 reloads_conflict (int r1, int r2)
5229 enum reload_type r1_type = rld[r1].when_needed;
5230 enum reload_type r2_type = rld[r2].when_needed;
5231 int r1_opnum = rld[r1].opnum;
5232 int r2_opnum = rld[r2].opnum;
5234 /* RELOAD_OTHER conflicts with everything. */
5235 if (r2_type == RELOAD_OTHER)
5238 /* Otherwise, check conflicts differently for each type. */
5242 case RELOAD_FOR_INPUT:
5243 return (r2_type == RELOAD_FOR_INSN
5244 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5245 || r2_type == RELOAD_FOR_OPADDR_ADDR
5246 || r2_type == RELOAD_FOR_INPUT
5247 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5248 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5249 && r2_opnum > r1_opnum));
5251 case RELOAD_FOR_INPUT_ADDRESS:
5252 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5253 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5255 case RELOAD_FOR_INPADDR_ADDRESS:
5256 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5257 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5259 case RELOAD_FOR_OUTPUT_ADDRESS:
5260 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5261 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5263 case RELOAD_FOR_OUTADDR_ADDRESS:
5264 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5265 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5267 case RELOAD_FOR_OPERAND_ADDRESS:
5268 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5269 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5270 && (!reloads_unique_chain_p (r1, r2)
5271 || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5273 case RELOAD_FOR_OPADDR_ADDR:
5274 return (r2_type == RELOAD_FOR_INPUT
5275 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5277 case RELOAD_FOR_OUTPUT:
5278 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5279 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5280 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5281 && r2_opnum >= r1_opnum));
5283 case RELOAD_FOR_INSN:
5284 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5285 || r2_type == RELOAD_FOR_INSN
5286 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5288 case RELOAD_FOR_OTHER_ADDRESS:
5289 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5299 /* Indexed by reload number, 1 if incoming value
5300 inherited from previous insns. */
5301 static char reload_inherited[MAX_RELOADS];
5303 /* For an inherited reload, this is the insn the reload was inherited from,
5304 if we know it. Otherwise, this is 0. */
5305 static rtx reload_inheritance_insn[MAX_RELOADS];
5307 /* If nonzero, this is a place to get the value of the reload,
5308 rather than using reload_in. */
5309 static rtx reload_override_in[MAX_RELOADS];
5311 /* For each reload, the hard register number of the register used,
5312 or -1 if we did not need a register for this reload. */
5313 static int reload_spill_index[MAX_RELOADS];
5315 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5316 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5318 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5319 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5321 /* Subroutine of free_for_value_p, used to check a single register.
5322 START_REGNO is the starting regno of the full reload register
5323 (possibly comprising multiple hard registers) that we are considering. */
5326 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5327 enum reload_type type, rtx value, rtx out,
5328 int reloadnum, int ignore_address_reloads)
5331 /* Set if we see an input reload that must not share its reload register
5332 with any new earlyclobber, but might otherwise share the reload
5333 register with an output or input-output reload. */
5334 int check_earlyclobber = 0;
5338 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5341 if (out == const0_rtx)
5347 /* We use some pseudo 'time' value to check if the lifetimes of the
5348 new register use would overlap with the one of a previous reload
5349 that is not read-only or uses a different value.
5350 The 'time' used doesn't have to be linear in any shape or form, just
5352 Some reload types use different 'buckets' for each operand.
5353 So there are MAX_RECOG_OPERANDS different time values for each
5355 We compute TIME1 as the time when the register for the prospective
5356 new reload ceases to be live, and TIME2 for each existing
5357 reload as the time when that the reload register of that reload
5359 Where there is little to be gained by exact lifetime calculations,
5360 we just make conservative assumptions, i.e. a longer lifetime;
5361 this is done in the 'default:' cases. */
5364 case RELOAD_FOR_OTHER_ADDRESS:
5365 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5366 time1 = copy ? 0 : 1;
5369 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5371 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5372 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5373 respectively, to the time values for these, we get distinct time
5374 values. To get distinct time values for each operand, we have to
5375 multiply opnum by at least three. We round that up to four because
5376 multiply by four is often cheaper. */
5377 case RELOAD_FOR_INPADDR_ADDRESS:
5378 time1 = opnum * 4 + 2;
5380 case RELOAD_FOR_INPUT_ADDRESS:
5381 time1 = opnum * 4 + 3;
5383 case RELOAD_FOR_INPUT:
5384 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5385 executes (inclusive). */
5386 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5388 case RELOAD_FOR_OPADDR_ADDR:
5390 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5391 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5393 case RELOAD_FOR_OPERAND_ADDRESS:
5394 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5396 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5398 case RELOAD_FOR_OUTADDR_ADDRESS:
5399 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5401 case RELOAD_FOR_OUTPUT_ADDRESS:
5402 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5405 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5408 for (i = 0; i < n_reloads; i++)
5410 rtx reg = rld[i].reg_rtx;
5411 if (reg && REG_P (reg)
5412 && ((unsigned) regno - true_regnum (reg)
5413 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5416 rtx other_input = rld[i].in;
5418 /* If the other reload loads the same input value, that
5419 will not cause a conflict only if it's loading it into
5420 the same register. */
5421 if (true_regnum (reg) != start_regno)
5422 other_input = NULL_RTX;
5423 if (! other_input || ! rtx_equal_p (other_input, value)
5424 || rld[i].out || out)
5427 switch (rld[i].when_needed)
5429 case RELOAD_FOR_OTHER_ADDRESS:
5432 case RELOAD_FOR_INPADDR_ADDRESS:
5433 /* find_reloads makes sure that a
5434 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5435 by at most one - the first -
5436 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5437 address reload is inherited, the address address reload
5438 goes away, so we can ignore this conflict. */
5439 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5440 && ignore_address_reloads
5441 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5442 Then the address address is still needed to store
5443 back the new address. */
5444 && ! rld[reloadnum].out)
5446 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5447 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5449 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5450 && ignore_address_reloads
5451 /* Unless we are reloading an auto_inc expression. */
5452 && ! rld[reloadnum].out)
5454 time2 = rld[i].opnum * 4 + 2;
5456 case RELOAD_FOR_INPUT_ADDRESS:
5457 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5458 && ignore_address_reloads
5459 && ! rld[reloadnum].out)
5461 time2 = rld[i].opnum * 4 + 3;
5463 case RELOAD_FOR_INPUT:
5464 time2 = rld[i].opnum * 4 + 4;
5465 check_earlyclobber = 1;
5467 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5468 == MAX_RECOG_OPERAND * 4 */
5469 case RELOAD_FOR_OPADDR_ADDR:
5470 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5471 && ignore_address_reloads
5472 && ! rld[reloadnum].out)
5474 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5476 case RELOAD_FOR_OPERAND_ADDRESS:
5477 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5478 check_earlyclobber = 1;
5480 case RELOAD_FOR_INSN:
5481 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5483 case RELOAD_FOR_OUTPUT:
5484 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5485 instruction is executed. */
5486 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5488 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5489 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5491 case RELOAD_FOR_OUTADDR_ADDRESS:
5492 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5493 && ignore_address_reloads
5494 && ! rld[reloadnum].out)
5496 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5498 case RELOAD_FOR_OUTPUT_ADDRESS:
5499 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5502 /* If there is no conflict in the input part, handle this
5503 like an output reload. */
5504 if (! rld[i].in || rtx_equal_p (other_input, value))
5506 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5507 /* Earlyclobbered outputs must conflict with inputs. */
5508 if (earlyclobber_operand_p (rld[i].out))
5509 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5514 /* RELOAD_OTHER might be live beyond instruction execution,
5515 but this is not obvious when we set time2 = 1. So check
5516 here if there might be a problem with the new reload
5517 clobbering the register used by the RELOAD_OTHER. */
5525 && (! rld[i].in || rld[i].out
5526 || ! rtx_equal_p (other_input, value)))
5527 || (out && rld[reloadnum].out_reg
5528 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5534 /* Earlyclobbered outputs must conflict with inputs. */
5535 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5541 /* Return 1 if the value in reload reg REGNO, as used by a reload
5542 needed for the part of the insn specified by OPNUM and TYPE,
5543 may be used to load VALUE into it.
5545 MODE is the mode in which the register is used, this is needed to
5546 determine how many hard regs to test.
5548 Other read-only reloads with the same value do not conflict
5549 unless OUT is nonzero and these other reloads have to live while
5550 output reloads live.
5551 If OUT is CONST0_RTX, this is a special case: it means that the
5552 test should not be for using register REGNO as reload register, but
5553 for copying from register REGNO into the reload register.
5555 RELOADNUM is the number of the reload we want to load this value for;
5556 a reload does not conflict with itself.
5558 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5559 reloads that load an address for the very reload we are considering.
5561 The caller has to make sure that there is no conflict with the return
5565 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5566 enum reload_type type, rtx value, rtx out, int reloadnum,
5567 int ignore_address_reloads)
5569 int nregs = hard_regno_nregs[regno][mode];
5571 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5572 value, out, reloadnum,
5573 ignore_address_reloads))
5578 /* Return nonzero if the rtx X is invariant over the current function. */
5579 /* ??? Actually, the places where we use this expect exactly what is
5580 tested here, and not everything that is function invariant. In
5581 particular, the frame pointer and arg pointer are special cased;
5582 pic_offset_table_rtx is not, and we must not spill these things to
5586 function_invariant_p (const_rtx x)
5590 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5592 if (GET_CODE (x) == PLUS
5593 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5594 && CONSTANT_P (XEXP (x, 1)))
5599 /* Determine whether the reload reg X overlaps any rtx'es used for
5600 overriding inheritance. Return nonzero if so. */
5603 conflicts_with_override (rtx x)
5606 for (i = 0; i < n_reloads; i++)
5607 if (reload_override_in[i]
5608 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5613 /* Give an error message saying we failed to find a reload for INSN,
5614 and clear out reload R. */
5616 failed_reload (rtx insn, int r)
5618 if (asm_noperands (PATTERN (insn)) < 0)
5619 /* It's the compiler's fault. */
5620 fatal_insn ("could not find a spill register", insn);
5622 /* It's the user's fault; the operand's mode and constraint
5623 don't match. Disable this reload so we don't crash in final. */
5624 error_for_asm (insn,
5625 "%<asm%> operand constraint incompatible with operand size");
5629 rld[r].optional = 1;
5630 rld[r].secondary_p = 1;
5633 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5634 for reload R. If it's valid, get an rtx for it. Return nonzero if
5637 set_reload_reg (int i, int r)
5640 rtx reg = spill_reg_rtx[i];
5642 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5643 spill_reg_rtx[i] = reg
5644 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5646 regno = true_regnum (reg);
5648 /* Detect when the reload reg can't hold the reload mode.
5649 This used to be one `if', but Sequent compiler can't handle that. */
5650 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5652 enum machine_mode test_mode = VOIDmode;
5654 test_mode = GET_MODE (rld[r].in);
5655 /* If rld[r].in has VOIDmode, it means we will load it
5656 in whatever mode the reload reg has: to wit, rld[r].mode.
5657 We have already tested that for validity. */
5658 /* Aside from that, we need to test that the expressions
5659 to reload from or into have modes which are valid for this
5660 reload register. Otherwise the reload insns would be invalid. */
5661 if (! (rld[r].in != 0 && test_mode != VOIDmode
5662 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5663 if (! (rld[r].out != 0
5664 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5666 /* The reg is OK. */
5669 /* Mark as in use for this insn the reload regs we use
5671 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5672 rld[r].when_needed, rld[r].mode);
5674 rld[r].reg_rtx = reg;
5675 reload_spill_index[r] = spill_regs[i];
5682 /* Find a spill register to use as a reload register for reload R.
5683 LAST_RELOAD is nonzero if this is the last reload for the insn being
5686 Set rld[R].reg_rtx to the register allocated.
5688 We return 1 if successful, or 0 if we couldn't find a spill reg and
5689 we didn't change anything. */
5692 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5697 /* If we put this reload ahead, thinking it is a group,
5698 then insist on finding a group. Otherwise we can grab a
5699 reg that some other reload needs.
5700 (That can happen when we have a 68000 DATA_OR_FP_REG
5701 which is a group of data regs or one fp reg.)
5702 We need not be so restrictive if there are no more reloads
5705 ??? Really it would be nicer to have smarter handling
5706 for that kind of reg class, where a problem like this is normal.
5707 Perhaps those classes should be avoided for reloading
5708 by use of more alternatives. */
5710 int force_group = rld[r].nregs > 1 && ! last_reload;
5712 /* If we want a single register and haven't yet found one,
5713 take any reg in the right class and not in use.
5714 If we want a consecutive group, here is where we look for it.
5716 We use two passes so we can first look for reload regs to
5717 reuse, which are already in use for other reloads in this insn,
5718 and only then use additional registers.
5719 I think that maximizing reuse is needed to make sure we don't
5720 run out of reload regs. Suppose we have three reloads, and
5721 reloads A and B can share regs. These need two regs.
5722 Suppose A and B are given different regs.
5723 That leaves none for C. */
5724 for (pass = 0; pass < 2; pass++)
5726 /* I is the index in spill_regs.
5727 We advance it round-robin between insns to use all spill regs
5728 equally, so that inherited reloads have a chance
5729 of leapfrogging each other. */
5733 for (count = 0; count < n_spills; count++)
5735 int rclass = (int) rld[r].rclass;
5741 regnum = spill_regs[i];
5743 if ((reload_reg_free_p (regnum, rld[r].opnum,
5746 /* We check reload_reg_used to make sure we
5747 don't clobber the return register. */
5748 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5749 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5750 rld[r].when_needed, rld[r].in,
5752 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
5753 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5754 /* Look first for regs to share, then for unshared. But
5755 don't share regs used for inherited reloads; they are
5756 the ones we want to preserve. */
5758 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5760 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5763 int nr = hard_regno_nregs[regnum][rld[r].mode];
5764 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5765 (on 68000) got us two FP regs. If NR is 1,
5766 we would reject both of them. */
5769 /* If we need only one reg, we have already won. */
5772 /* But reject a single reg if we demand a group. */
5777 /* Otherwise check that as many consecutive regs as we need
5778 are available here. */
5781 int regno = regnum + nr - 1;
5782 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
5783 && spill_reg_order[regno] >= 0
5784 && reload_reg_free_p (regno, rld[r].opnum,
5785 rld[r].when_needed)))
5794 /* If we found something on pass 1, omit pass 2. */
5795 if (count < n_spills)
5799 /* We should have found a spill register by now. */
5800 if (count >= n_spills)
5803 /* I is the index in SPILL_REG_RTX of the reload register we are to
5804 allocate. Get an rtx for it and find its register number. */
5806 return set_reload_reg (i, r);
5809 /* Initialize all the tables needed to allocate reload registers.
5810 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5811 is the array we use to restore the reg_rtx field for every reload. */
5814 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5818 for (i = 0; i < n_reloads; i++)
5819 rld[i].reg_rtx = save_reload_reg_rtx[i];
5821 memset (reload_inherited, 0, MAX_RELOADS);
5822 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5823 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5825 CLEAR_HARD_REG_SET (reload_reg_used);
5826 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5827 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5828 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5829 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5830 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5832 CLEAR_HARD_REG_SET (reg_used_in_insn);
5835 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5836 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5837 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5838 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5839 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5840 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5843 for (i = 0; i < reload_n_operands; i++)
5845 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5846 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5847 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5848 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5849 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5850 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5853 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5855 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5857 for (i = 0; i < n_reloads; i++)
5858 /* If we have already decided to use a certain register,
5859 don't use it in another way. */
5861 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5862 rld[i].when_needed, rld[i].mode);
5865 /* Assign hard reg targets for the pseudo-registers we must reload
5866 into hard regs for this insn.
5867 Also output the instructions to copy them in and out of the hard regs.
5869 For machines with register classes, we are responsible for
5870 finding a reload reg in the proper class. */
5873 choose_reload_regs (struct insn_chain *chain)
5875 rtx insn = chain->insn;
5877 unsigned int max_group_size = 1;
5878 enum reg_class group_class = NO_REGS;
5879 int pass, win, inheritance;
5881 rtx save_reload_reg_rtx[MAX_RELOADS];
5883 /* In order to be certain of getting the registers we need,
5884 we must sort the reloads into order of increasing register class.
5885 Then our grabbing of reload registers will parallel the process
5886 that provided the reload registers.
5888 Also note whether any of the reloads wants a consecutive group of regs.
5889 If so, record the maximum size of the group desired and what
5890 register class contains all the groups needed by this insn. */
5892 for (j = 0; j < n_reloads; j++)
5894 reload_order[j] = j;
5895 if (rld[j].reg_rtx != NULL_RTX)
5897 gcc_assert (REG_P (rld[j].reg_rtx)
5898 && HARD_REGISTER_P (rld[j].reg_rtx));
5899 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
5902 reload_spill_index[j] = -1;
5904 if (rld[j].nregs > 1)
5906 max_group_size = MAX (rld[j].nregs, max_group_size);
5908 = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
5911 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5915 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5917 /* If -O, try first with inheritance, then turning it off.
5918 If not -O, don't do inheritance.
5919 Using inheritance when not optimizing leads to paradoxes
5920 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5921 because one side of the comparison might be inherited. */
5923 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5925 choose_reload_regs_init (chain, save_reload_reg_rtx);
5927 /* Process the reloads in order of preference just found.
5928 Beyond this point, subregs can be found in reload_reg_rtx.
5930 This used to look for an existing reloaded home for all of the
5931 reloads, and only then perform any new reloads. But that could lose
5932 if the reloads were done out of reg-class order because a later
5933 reload with a looser constraint might have an old home in a register
5934 needed by an earlier reload with a tighter constraint.
5936 To solve this, we make two passes over the reloads, in the order
5937 described above. In the first pass we try to inherit a reload
5938 from a previous insn. If there is a later reload that needs a
5939 class that is a proper subset of the class being processed, we must
5940 also allocate a spill register during the first pass.
5942 Then make a second pass over the reloads to allocate any reloads
5943 that haven't been given registers yet. */
5945 for (j = 0; j < n_reloads; j++)
5947 int r = reload_order[j];
5948 rtx search_equiv = NULL_RTX;
5950 /* Ignore reloads that got marked inoperative. */
5951 if (rld[r].out == 0 && rld[r].in == 0
5952 && ! rld[r].secondary_p)
5955 /* If find_reloads chose to use reload_in or reload_out as a reload
5956 register, we don't need to chose one. Otherwise, try even if it
5957 found one since we might save an insn if we find the value lying
5959 Try also when reload_in is a pseudo without a hard reg. */
5960 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5961 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5962 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5963 && !MEM_P (rld[r].in)
5964 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5967 #if 0 /* No longer needed for correct operation.
5968 It might give better code, or might not; worth an experiment? */
5969 /* If this is an optional reload, we can't inherit from earlier insns
5970 until we are sure that any non-optional reloads have been allocated.
5971 The following code takes advantage of the fact that optional reloads
5972 are at the end of reload_order. */
5973 if (rld[r].optional != 0)
5974 for (i = 0; i < j; i++)
5975 if ((rld[reload_order[i]].out != 0
5976 || rld[reload_order[i]].in != 0
5977 || rld[reload_order[i]].secondary_p)
5978 && ! rld[reload_order[i]].optional
5979 && rld[reload_order[i]].reg_rtx == 0)
5980 allocate_reload_reg (chain, reload_order[i], 0);
5983 /* First see if this pseudo is already available as reloaded
5984 for a previous insn. We cannot try to inherit for reloads
5985 that are smaller than the maximum number of registers needed
5986 for groups unless the register we would allocate cannot be used
5989 We could check here to see if this is a secondary reload for
5990 an object that is already in a register of the desired class.
5991 This would avoid the need for the secondary reload register.
5992 But this is complex because we can't easily determine what
5993 objects might want to be loaded via this reload. So let a
5994 register be allocated here. In `emit_reload_insns' we suppress
5995 one of the loads in the case described above. */
6001 enum machine_mode mode = VOIDmode;
6005 else if (REG_P (rld[r].in))
6007 regno = REGNO (rld[r].in);
6008 mode = GET_MODE (rld[r].in);
6010 else if (REG_P (rld[r].in_reg))
6012 regno = REGNO (rld[r].in_reg);
6013 mode = GET_MODE (rld[r].in_reg);
6015 else if (GET_CODE (rld[r].in_reg) == SUBREG
6016 && REG_P (SUBREG_REG (rld[r].in_reg)))
6018 regno = REGNO (SUBREG_REG (rld[r].in_reg));
6019 if (regno < FIRST_PSEUDO_REGISTER)
6020 regno = subreg_regno (rld[r].in_reg);
6022 byte = SUBREG_BYTE (rld[r].in_reg);
6023 mode = GET_MODE (rld[r].in_reg);
6026 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6027 && REG_P (XEXP (rld[r].in_reg, 0)))
6029 regno = REGNO (XEXP (rld[r].in_reg, 0));
6030 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6031 rld[r].out = rld[r].in;
6035 /* This won't work, since REGNO can be a pseudo reg number.
6036 Also, it takes much more hair to keep track of all the things
6037 that can invalidate an inherited reload of part of a pseudoreg. */
6038 else if (GET_CODE (rld[r].in) == SUBREG
6039 && REG_P (SUBREG_REG (rld[r].in)))
6040 regno = subreg_regno (rld[r].in);
6044 && reg_last_reload_reg[regno] != 0
6045 #ifdef CANNOT_CHANGE_MODE_CLASS
6046 /* Verify that the register it's in can be used in
6048 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
6049 GET_MODE (reg_last_reload_reg[regno]),
6054 enum reg_class rclass = rld[r].rclass, last_class;
6055 rtx last_reg = reg_last_reload_reg[regno];
6056 enum machine_mode need_mode;
6058 i = REGNO (last_reg);
6059 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6060 last_class = REGNO_REG_CLASS (i);
6066 = smallest_mode_for_size
6067 (GET_MODE_BITSIZE (mode) + byte * BITS_PER_UNIT,
6068 GET_MODE_CLASS (mode) == MODE_PARTIAL_INT
6069 ? MODE_INT : GET_MODE_CLASS (mode));
6071 if ((GET_MODE_SIZE (GET_MODE (last_reg))
6072 >= GET_MODE_SIZE (need_mode))
6073 && reg_reloaded_contents[i] == regno
6074 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6075 && HARD_REGNO_MODE_OK (i, rld[r].mode)
6076 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6077 /* Even if we can't use this register as a reload
6078 register, we might use it for reload_override_in,
6079 if copying it to the desired class is cheap
6081 || ((REGISTER_MOVE_COST (mode, last_class, rclass)
6082 < MEMORY_MOVE_COST (mode, rclass, 1))
6083 && (secondary_reload_class (1, rclass, mode,
6086 #ifdef SECONDARY_MEMORY_NEEDED
6087 && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
6092 && (rld[r].nregs == max_group_size
6093 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6095 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6096 rld[r].when_needed, rld[r].in,
6099 /* If a group is needed, verify that all the subsequent
6100 registers still have their values intact. */
6101 int nr = hard_regno_nregs[i][rld[r].mode];
6104 for (k = 1; k < nr; k++)
6105 if (reg_reloaded_contents[i + k] != regno
6106 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6114 last_reg = (GET_MODE (last_reg) == mode
6115 ? last_reg : gen_rtx_REG (mode, i));
6118 for (k = 0; k < nr; k++)
6119 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6122 /* We found a register that contains the
6123 value we need. If this register is the
6124 same as an `earlyclobber' operand of the
6125 current insn, just mark it as a place to
6126 reload from since we can't use it as the
6127 reload register itself. */
6129 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6130 if (reg_overlap_mentioned_for_reload_p
6131 (reg_last_reload_reg[regno],
6132 reload_earlyclobbers[i1]))
6135 if (i1 != n_earlyclobbers
6136 || ! (free_for_value_p (i, rld[r].mode,
6138 rld[r].when_needed, rld[r].in,
6140 /* Don't use it if we'd clobber a pseudo reg. */
6141 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6143 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6144 /* Don't clobber the frame pointer. */
6145 || (i == HARD_FRAME_POINTER_REGNUM
6146 && frame_pointer_needed
6148 /* Don't really use the inherited spill reg
6149 if we need it wider than we've got it. */
6150 || (GET_MODE_SIZE (rld[r].mode)
6151 > GET_MODE_SIZE (mode))
6154 /* If find_reloads chose reload_out as reload
6155 register, stay with it - that leaves the
6156 inherited register for subsequent reloads. */
6157 || (rld[r].out && rld[r].reg_rtx
6158 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6160 if (! rld[r].optional)
6162 reload_override_in[r] = last_reg;
6163 reload_inheritance_insn[r]
6164 = reg_reloaded_insn[i];
6170 /* We can use this as a reload reg. */
6171 /* Mark the register as in use for this part of
6173 mark_reload_reg_in_use (i,
6177 rld[r].reg_rtx = last_reg;
6178 reload_inherited[r] = 1;
6179 reload_inheritance_insn[r]
6180 = reg_reloaded_insn[i];
6181 reload_spill_index[r] = i;
6182 for (k = 0; k < nr; k++)
6183 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6191 /* Here's another way to see if the value is already lying around. */
6194 && ! reload_inherited[r]
6196 && (CONSTANT_P (rld[r].in)
6197 || GET_CODE (rld[r].in) == PLUS
6198 || REG_P (rld[r].in)
6199 || MEM_P (rld[r].in))
6200 && (rld[r].nregs == max_group_size
6201 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6202 search_equiv = rld[r].in;
6203 /* If this is an output reload from a simple move insn, look
6204 if an equivalence for the input is available. */
6205 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
6207 rtx set = single_set (insn);
6210 && rtx_equal_p (rld[r].out, SET_DEST (set))
6211 && CONSTANT_P (SET_SRC (set)))
6212 search_equiv = SET_SRC (set);
6218 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6219 -1, NULL, 0, rld[r].mode);
6225 regno = REGNO (equiv);
6228 /* This must be a SUBREG of a hard register.
6229 Make a new REG since this might be used in an
6230 address and not all machines support SUBREGs
6232 gcc_assert (GET_CODE (equiv) == SUBREG);
6233 regno = subreg_regno (equiv);
6234 equiv = gen_rtx_REG (rld[r].mode, regno);
6235 /* If we choose EQUIV as the reload register, but the
6236 loop below decides to cancel the inheritance, we'll
6237 end up reloading EQUIV in rld[r].mode, not the mode
6238 it had originally. That isn't safe when EQUIV isn't
6239 available as a spill register since its value might
6240 still be live at this point. */
6241 for (i = regno; i < regno + (int) rld[r].nregs; i++)
6242 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6247 /* If we found a spill reg, reject it unless it is free
6248 and of the desired class. */
6252 int bad_for_class = 0;
6253 int max_regno = regno + rld[r].nregs;
6255 for (i = regno; i < max_regno; i++)
6257 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6259 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6264 && ! free_for_value_p (regno, rld[r].mode,
6265 rld[r].opnum, rld[r].when_needed,
6266 rld[r].in, rld[r].out, r, 1))
6271 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6274 /* We found a register that contains the value we need.
6275 If this register is the same as an `earlyclobber' operand
6276 of the current insn, just mark it as a place to reload from
6277 since we can't use it as the reload register itself. */
6280 for (i = 0; i < n_earlyclobbers; i++)
6281 if (reg_overlap_mentioned_for_reload_p (equiv,
6282 reload_earlyclobbers[i]))
6284 if (! rld[r].optional)
6285 reload_override_in[r] = equiv;
6290 /* If the equiv register we have found is explicitly clobbered
6291 in the current insn, it depends on the reload type if we
6292 can use it, use it for reload_override_in, or not at all.
6293 In particular, we then can't use EQUIV for a
6294 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6298 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6299 switch (rld[r].when_needed)
6301 case RELOAD_FOR_OTHER_ADDRESS:
6302 case RELOAD_FOR_INPADDR_ADDRESS:
6303 case RELOAD_FOR_INPUT_ADDRESS:
6304 case RELOAD_FOR_OPADDR_ADDR:
6307 case RELOAD_FOR_INPUT:
6308 case RELOAD_FOR_OPERAND_ADDRESS:
6309 if (! rld[r].optional)
6310 reload_override_in[r] = equiv;
6316 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6317 switch (rld[r].when_needed)
6319 case RELOAD_FOR_OTHER_ADDRESS:
6320 case RELOAD_FOR_INPADDR_ADDRESS:
6321 case RELOAD_FOR_INPUT_ADDRESS:
6322 case RELOAD_FOR_OPADDR_ADDR:
6323 case RELOAD_FOR_OPERAND_ADDRESS:
6324 case RELOAD_FOR_INPUT:
6327 if (! rld[r].optional)
6328 reload_override_in[r] = equiv;
6336 /* If we found an equivalent reg, say no code need be generated
6337 to load it, and use it as our reload reg. */
6339 && (regno != HARD_FRAME_POINTER_REGNUM
6340 || !frame_pointer_needed))
6342 int nr = hard_regno_nregs[regno][rld[r].mode];
6344 rld[r].reg_rtx = equiv;
6345 reload_spill_index[r] = regno;
6346 reload_inherited[r] = 1;
6348 /* If reg_reloaded_valid is not set for this register,
6349 there might be a stale spill_reg_store lying around.
6350 We must clear it, since otherwise emit_reload_insns
6351 might delete the store. */
6352 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6353 spill_reg_store[regno] = NULL_RTX;
6354 /* If any of the hard registers in EQUIV are spill
6355 registers, mark them as in use for this insn. */
6356 for (k = 0; k < nr; k++)
6358 i = spill_reg_order[regno + k];
6361 mark_reload_reg_in_use (regno, rld[r].opnum,
6364 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6371 /* If we found a register to use already, or if this is an optional
6372 reload, we are done. */
6373 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6377 /* No longer needed for correct operation. Might or might
6378 not give better code on the average. Want to experiment? */
6380 /* See if there is a later reload that has a class different from our
6381 class that intersects our class or that requires less register
6382 than our reload. If so, we must allocate a register to this
6383 reload now, since that reload might inherit a previous reload
6384 and take the only available register in our class. Don't do this
6385 for optional reloads since they will force all previous reloads
6386 to be allocated. Also don't do this for reloads that have been
6389 for (i = j + 1; i < n_reloads; i++)
6391 int s = reload_order[i];
6393 if ((rld[s].in == 0 && rld[s].out == 0
6394 && ! rld[s].secondary_p)
6398 if ((rld[s].rclass != rld[r].rclass
6399 && reg_classes_intersect_p (rld[r].rclass,
6401 || rld[s].nregs < rld[r].nregs)
6408 allocate_reload_reg (chain, r, j == n_reloads - 1);
6412 /* Now allocate reload registers for anything non-optional that
6413 didn't get one yet. */
6414 for (j = 0; j < n_reloads; j++)
6416 int r = reload_order[j];
6418 /* Ignore reloads that got marked inoperative. */
6419 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6422 /* Skip reloads that already have a register allocated or are
6424 if (rld[r].reg_rtx != 0 || rld[r].optional)
6427 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6431 /* If that loop got all the way, we have won. */
6438 /* Loop around and try without any inheritance. */
6443 /* First undo everything done by the failed attempt
6444 to allocate with inheritance. */
6445 choose_reload_regs_init (chain, save_reload_reg_rtx);
6447 /* Some sanity tests to verify that the reloads found in the first
6448 pass are identical to the ones we have now. */
6449 gcc_assert (chain->n_reloads == n_reloads);
6451 for (i = 0; i < n_reloads; i++)
6453 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6455 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6456 for (j = 0; j < n_spills; j++)
6457 if (spill_regs[j] == chain->rld[i].regno)
6458 if (! set_reload_reg (j, i))
6459 failed_reload (chain->insn, i);
6463 /* If we thought we could inherit a reload, because it seemed that
6464 nothing else wanted the same reload register earlier in the insn,
6465 verify that assumption, now that all reloads have been assigned.
6466 Likewise for reloads where reload_override_in has been set. */
6468 /* If doing expensive optimizations, do one preliminary pass that doesn't
6469 cancel any inheritance, but removes reloads that have been needed only
6470 for reloads that we know can be inherited. */
6471 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6473 for (j = 0; j < n_reloads; j++)
6475 int r = reload_order[j];
6477 if (reload_inherited[r] && rld[r].reg_rtx)
6478 check_reg = rld[r].reg_rtx;
6479 else if (reload_override_in[r]
6480 && (REG_P (reload_override_in[r])
6481 || GET_CODE (reload_override_in[r]) == SUBREG))
6482 check_reg = reload_override_in[r];
6485 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6486 rld[r].opnum, rld[r].when_needed, rld[r].in,
6487 (reload_inherited[r]
6488 ? rld[r].out : const0_rtx),
6493 reload_inherited[r] = 0;
6494 reload_override_in[r] = 0;
6496 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6497 reload_override_in, then we do not need its related
6498 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6499 likewise for other reload types.
6500 We handle this by removing a reload when its only replacement
6501 is mentioned in reload_in of the reload we are going to inherit.
6502 A special case are auto_inc expressions; even if the input is
6503 inherited, we still need the address for the output. We can
6504 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6505 If we succeeded removing some reload and we are doing a preliminary
6506 pass just to remove such reloads, make another pass, since the
6507 removal of one reload might allow us to inherit another one. */
6509 && rld[r].out != rld[r].in
6510 && remove_address_replacements (rld[r].in) && pass)
6515 /* Now that reload_override_in is known valid,
6516 actually override reload_in. */
6517 for (j = 0; j < n_reloads; j++)
6518 if (reload_override_in[j])
6519 rld[j].in = reload_override_in[j];
6521 /* If this reload won't be done because it has been canceled or is
6522 optional and not inherited, clear reload_reg_rtx so other
6523 routines (such as subst_reloads) don't get confused. */
6524 for (j = 0; j < n_reloads; j++)
6525 if (rld[j].reg_rtx != 0
6526 && ((rld[j].optional && ! reload_inherited[j])
6527 || (rld[j].in == 0 && rld[j].out == 0
6528 && ! rld[j].secondary_p)))
6530 int regno = true_regnum (rld[j].reg_rtx);
6532 if (spill_reg_order[regno] >= 0)
6533 clear_reload_reg_in_use (regno, rld[j].opnum,
6534 rld[j].when_needed, rld[j].mode);
6536 reload_spill_index[j] = -1;
6539 /* Record which pseudos and which spill regs have output reloads. */
6540 for (j = 0; j < n_reloads; j++)
6542 int r = reload_order[j];
6544 i = reload_spill_index[r];
6546 /* I is nonneg if this reload uses a register.
6547 If rld[r].reg_rtx is 0, this is an optional reload
6548 that we opted to ignore. */
6549 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6550 && rld[r].reg_rtx != 0)
6552 int nregno = REGNO (rld[r].out_reg);
6555 if (nregno < FIRST_PSEUDO_REGISTER)
6556 nr = hard_regno_nregs[nregno][rld[r].mode];
6559 SET_REGNO_REG_SET (®_has_output_reload,
6564 nr = hard_regno_nregs[i][rld[r].mode];
6566 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6569 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6570 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6571 || rld[r].when_needed == RELOAD_FOR_INSN);
6576 /* Deallocate the reload register for reload R. This is called from
6577 remove_address_replacements. */
6580 deallocate_reload_reg (int r)
6584 if (! rld[r].reg_rtx)
6586 regno = true_regnum (rld[r].reg_rtx);
6588 if (spill_reg_order[regno] >= 0)
6589 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6591 reload_spill_index[r] = -1;
6594 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6595 reloads of the same item for fear that we might not have enough reload
6596 registers. However, normally they will get the same reload register
6597 and hence actually need not be loaded twice.
6599 Here we check for the most common case of this phenomenon: when we have
6600 a number of reloads for the same object, each of which were allocated
6601 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6602 reload, and is not modified in the insn itself. If we find such,
6603 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6604 This will not increase the number of spill registers needed and will
6605 prevent redundant code. */
6608 merge_assigned_reloads (rtx insn)
6612 /* Scan all the reloads looking for ones that only load values and
6613 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6614 assigned and not modified by INSN. */
6616 for (i = 0; i < n_reloads; i++)
6618 int conflicting_input = 0;
6619 int max_input_address_opnum = -1;
6620 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6622 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6623 || rld[i].out != 0 || rld[i].reg_rtx == 0
6624 || reg_set_p (rld[i].reg_rtx, insn))
6627 /* Look at all other reloads. Ensure that the only use of this
6628 reload_reg_rtx is in a reload that just loads the same value
6629 as we do. Note that any secondary reloads must be of the identical
6630 class since the values, modes, and result registers are the
6631 same, so we need not do anything with any secondary reloads. */
6633 for (j = 0; j < n_reloads; j++)
6635 if (i == j || rld[j].reg_rtx == 0
6636 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6640 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6641 && rld[j].opnum > max_input_address_opnum)
6642 max_input_address_opnum = rld[j].opnum;
6644 /* If the reload regs aren't exactly the same (e.g, different modes)
6645 or if the values are different, we can't merge this reload.
6646 But if it is an input reload, we might still merge
6647 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6649 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6650 || rld[j].out != 0 || rld[j].in == 0
6651 || ! rtx_equal_p (rld[i].in, rld[j].in))
6653 if (rld[j].when_needed != RELOAD_FOR_INPUT
6654 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6655 || rld[i].opnum > rld[j].opnum)
6656 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6658 conflicting_input = 1;
6659 if (min_conflicting_input_opnum > rld[j].opnum)
6660 min_conflicting_input_opnum = rld[j].opnum;
6664 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6665 we, in fact, found any matching reloads. */
6668 && max_input_address_opnum <= min_conflicting_input_opnum)
6670 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6672 for (j = 0; j < n_reloads; j++)
6673 if (i != j && rld[j].reg_rtx != 0
6674 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6675 && (! conflicting_input
6676 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6677 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6679 rld[i].when_needed = RELOAD_OTHER;
6681 reload_spill_index[j] = -1;
6682 transfer_replacements (i, j);
6685 /* If this is now RELOAD_OTHER, look for any reloads that
6686 load parts of this operand and set them to
6687 RELOAD_FOR_OTHER_ADDRESS if they were for inputs,
6688 RELOAD_OTHER for outputs. Note that this test is
6689 equivalent to looking for reloads for this operand
6692 We must take special care with RELOAD_FOR_OUTPUT_ADDRESS;
6693 it may share registers with a RELOAD_FOR_INPUT, so we can
6694 not change it to RELOAD_FOR_OTHER_ADDRESS. We should
6695 never need to, since we do not modify RELOAD_FOR_OUTPUT.
6697 It is possible that the RELOAD_FOR_OPERAND_ADDRESS
6698 instruction is assigned the same register as the earlier
6699 RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two
6700 instructions will cause the RELOAD_FOR_OTHER_ADDRESS
6701 instruction to be deleted later on. */
6703 if (rld[i].when_needed == RELOAD_OTHER)
6704 for (j = 0; j < n_reloads; j++)
6706 && rld[j].when_needed != RELOAD_OTHER
6707 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6708 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6709 && rld[j].when_needed != RELOAD_FOR_OPERAND_ADDRESS
6710 && (! conflicting_input
6711 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6712 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6713 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6719 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6720 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6721 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6723 /* Check to see if we accidentally converted two
6724 reloads that use the same reload register with
6725 different inputs to the same type. If so, the
6726 resulting code won't work. */
6728 for (k = 0; k < j; k++)
6729 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6730 || rld[k].when_needed != rld[j].when_needed
6731 || !rtx_equal_p (rld[k].reg_rtx,
6733 || rtx_equal_p (rld[k].in,
6740 /* These arrays are filled by emit_reload_insns and its subroutines. */
6741 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6742 static rtx other_input_address_reload_insns = 0;
6743 static rtx other_input_reload_insns = 0;
6744 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6745 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6746 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6747 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6748 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6749 static rtx operand_reload_insns = 0;
6750 static rtx other_operand_reload_insns = 0;
6751 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6753 /* Values to be put in spill_reg_store are put here first. */
6754 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6755 static HARD_REG_SET reg_reloaded_died;
6757 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6758 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6759 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6760 adjusted register, and return true. Otherwise, return false. */
6762 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6763 enum reg_class new_class,
6764 enum machine_mode new_mode)
6769 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6771 unsigned regno = REGNO (reg);
6773 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6775 if (GET_MODE (reg) != new_mode)
6777 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6779 if (hard_regno_nregs[regno][new_mode]
6780 > hard_regno_nregs[regno][GET_MODE (reg)])
6782 reg = reload_adjust_reg_for_mode (reg, new_mode);
6790 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6791 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6792 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6793 adjusted register, and return true. Otherwise, return false. */
6795 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6796 enum insn_code icode)
6799 enum reg_class new_class = scratch_reload_class (icode);
6800 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6802 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6803 new_class, new_mode);
6806 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6807 has the number J. OLD contains the value to be used as input. */
6810 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6813 rtx insn = chain->insn;
6815 rtx oldequiv_reg = 0;
6818 enum machine_mode mode;
6821 /* delete_output_reload is only invoked properly if old contains
6822 the original pseudo register. Since this is replaced with a
6823 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6824 find the pseudo in RELOAD_IN_REG. */
6825 if (reload_override_in[j]
6826 && REG_P (rl->in_reg))
6833 else if (REG_P (oldequiv))
6834 oldequiv_reg = oldequiv;
6835 else if (GET_CODE (oldequiv) == SUBREG)
6836 oldequiv_reg = SUBREG_REG (oldequiv);
6838 reloadreg = reload_reg_rtx_for_input[j];
6839 mode = GET_MODE (reloadreg);
6841 /* If we are reloading from a register that was recently stored in
6842 with an output-reload, see if we can prove there was
6843 actually no need to store the old value in it. */
6845 if (optimize && REG_P (oldequiv)
6846 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6847 && spill_reg_store[REGNO (oldequiv)]
6849 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6850 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6852 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6854 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
6857 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6858 oldequiv = SUBREG_REG (oldequiv);
6859 if (GET_MODE (oldequiv) != VOIDmode
6860 && mode != GET_MODE (oldequiv))
6861 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6863 /* Switch to the right place to emit the reload insns. */
6864 switch (rl->when_needed)
6867 where = &other_input_reload_insns;
6869 case RELOAD_FOR_INPUT:
6870 where = &input_reload_insns[rl->opnum];
6872 case RELOAD_FOR_INPUT_ADDRESS:
6873 where = &input_address_reload_insns[rl->opnum];
6875 case RELOAD_FOR_INPADDR_ADDRESS:
6876 where = &inpaddr_address_reload_insns[rl->opnum];
6878 case RELOAD_FOR_OUTPUT_ADDRESS:
6879 where = &output_address_reload_insns[rl->opnum];
6881 case RELOAD_FOR_OUTADDR_ADDRESS:
6882 where = &outaddr_address_reload_insns[rl->opnum];
6884 case RELOAD_FOR_OPERAND_ADDRESS:
6885 where = &operand_reload_insns;
6887 case RELOAD_FOR_OPADDR_ADDR:
6888 where = &other_operand_reload_insns;
6890 case RELOAD_FOR_OTHER_ADDRESS:
6891 where = &other_input_address_reload_insns;
6897 push_to_sequence (*where);
6899 /* Auto-increment addresses must be reloaded in a special way. */
6900 if (rl->out && ! rl->out_reg)
6902 /* We are not going to bother supporting the case where a
6903 incremented register can't be copied directly from
6904 OLDEQUIV since this seems highly unlikely. */
6905 gcc_assert (rl->secondary_in_reload < 0);
6907 if (reload_inherited[j])
6908 oldequiv = reloadreg;
6910 old = XEXP (rl->in_reg, 0);
6912 if (optimize && REG_P (oldequiv)
6913 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6914 && spill_reg_store[REGNO (oldequiv)]
6916 && (dead_or_set_p (insn,
6917 spill_reg_stored_to[REGNO (oldequiv)])
6918 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6920 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6922 /* Prevent normal processing of this reload. */
6924 /* Output a special code sequence for this case. */
6925 new_spill_reg_store[REGNO (reloadreg)]
6926 = inc_for_reload (reloadreg, oldequiv, rl->out,
6930 /* If we are reloading a pseudo-register that was set by the previous
6931 insn, see if we can get rid of that pseudo-register entirely
6932 by redirecting the previous insn into our reload register. */
6934 else if (optimize && REG_P (old)
6935 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6936 && dead_or_set_p (insn, old)
6937 /* This is unsafe if some other reload
6938 uses the same reg first. */
6939 && ! conflicts_with_override (reloadreg)
6940 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6941 rl->when_needed, old, rl->out, j, 0))
6943 rtx temp = PREV_INSN (insn);
6944 while (temp && NOTE_P (temp))
6945 temp = PREV_INSN (temp);
6947 && NONJUMP_INSN_P (temp)
6948 && GET_CODE (PATTERN (temp)) == SET
6949 && SET_DEST (PATTERN (temp)) == old
6950 /* Make sure we can access insn_operand_constraint. */
6951 && asm_noperands (PATTERN (temp)) < 0
6952 /* This is unsafe if operand occurs more than once in current
6953 insn. Perhaps some occurrences aren't reloaded. */
6954 && count_occurrences (PATTERN (insn), old, 0) == 1)
6956 rtx old = SET_DEST (PATTERN (temp));
6957 /* Store into the reload register instead of the pseudo. */
6958 SET_DEST (PATTERN (temp)) = reloadreg;
6960 /* Verify that resulting insn is valid. */
6961 extract_insn (temp);
6962 if (constrain_operands (1))
6964 /* If the previous insn is an output reload, the source is
6965 a reload register, and its spill_reg_store entry will
6966 contain the previous destination. This is now
6968 if (REG_P (SET_SRC (PATTERN (temp)))
6969 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6971 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6972 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6975 /* If these are the only uses of the pseudo reg,
6976 pretend for GDB it lives in the reload reg we used. */
6977 if (REG_N_DEATHS (REGNO (old)) == 1
6978 && REG_N_SETS (REGNO (old)) == 1)
6980 reg_renumber[REGNO (old)] = REGNO (reloadreg);
6981 if (ira_conflicts_p)
6982 /* Inform IRA about the change. */
6983 ira_mark_allocation_change (REGNO (old));
6984 alter_reg (REGNO (old), -1, false);
6990 SET_DEST (PATTERN (temp)) = old;
6995 /* We can't do that, so output an insn to load RELOADREG. */
6997 /* If we have a secondary reload, pick up the secondary register
6998 and icode, if any. If OLDEQUIV and OLD are different or
6999 if this is an in-out reload, recompute whether or not we
7000 still need a secondary register and what the icode should
7001 be. If we still need a secondary register and the class or
7002 icode is different, go back to reloading from OLD if using
7003 OLDEQUIV means that we got the wrong type of register. We
7004 cannot have different class or icode due to an in-out reload
7005 because we don't make such reloads when both the input and
7006 output need secondary reload registers. */
7008 if (! special && rl->secondary_in_reload >= 0)
7010 rtx second_reload_reg = 0;
7011 rtx third_reload_reg = 0;
7012 int secondary_reload = rl->secondary_in_reload;
7013 rtx real_oldequiv = oldequiv;
7016 enum insn_code icode;
7017 enum insn_code tertiary_icode = CODE_FOR_nothing;
7019 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7020 and similarly for OLD.
7021 See comments in get_secondary_reload in reload.c. */
7022 /* If it is a pseudo that cannot be replaced with its
7023 equivalent MEM, we must fall back to reload_in, which
7024 will have all the necessary substitutions registered.
7025 Likewise for a pseudo that can't be replaced with its
7026 equivalent constant.
7028 Take extra care for subregs of such pseudos. Note that
7029 we cannot use reg_equiv_mem in this case because it is
7030 not in the right mode. */
7033 if (GET_CODE (tmp) == SUBREG)
7034 tmp = SUBREG_REG (tmp);
7036 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7037 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7038 || reg_equiv_constant[REGNO (tmp)] != 0))
7040 if (! reg_equiv_mem[REGNO (tmp)]
7041 || num_not_at_initial_offset
7042 || GET_CODE (oldequiv) == SUBREG)
7043 real_oldequiv = rl->in;
7045 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
7049 if (GET_CODE (tmp) == SUBREG)
7050 tmp = SUBREG_REG (tmp);
7052 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7053 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7054 || reg_equiv_constant[REGNO (tmp)] != 0))
7056 if (! reg_equiv_mem[REGNO (tmp)]
7057 || num_not_at_initial_offset
7058 || GET_CODE (old) == SUBREG)
7061 real_old = reg_equiv_mem[REGNO (tmp)];
7064 second_reload_reg = rld[secondary_reload].reg_rtx;
7065 if (rld[secondary_reload].secondary_in_reload >= 0)
7067 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7069 third_reload_reg = rld[tertiary_reload].reg_rtx;
7070 tertiary_icode = rld[secondary_reload].secondary_in_icode;
7071 /* We'd have to add more code for quartary reloads. */
7072 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7074 icode = rl->secondary_in_icode;
7076 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7077 || (rl->in != 0 && rl->out != 0))
7079 secondary_reload_info sri, sri2;
7080 enum reg_class new_class, new_t_class;
7082 sri.icode = CODE_FOR_nothing;
7083 sri.prev_sri = NULL;
7084 new_class = targetm.secondary_reload (1, real_oldequiv, rl->rclass,
7087 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7088 second_reload_reg = 0;
7089 else if (new_class == NO_REGS)
7091 if (reload_adjust_reg_for_icode (&second_reload_reg,
7093 (enum insn_code) sri.icode))
7095 icode = (enum insn_code) sri.icode;
7096 third_reload_reg = 0;
7101 real_oldequiv = real_old;
7104 else if (sri.icode != CODE_FOR_nothing)
7105 /* We currently lack a way to express this in reloads. */
7109 sri2.icode = CODE_FOR_nothing;
7110 sri2.prev_sri = &sri;
7111 new_t_class = targetm.secondary_reload (1, real_oldequiv,
7112 new_class, mode, &sri);
7113 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7115 if (reload_adjust_reg_for_temp (&second_reload_reg,
7119 third_reload_reg = 0;
7120 tertiary_icode = (enum insn_code) sri2.icode;
7125 real_oldequiv = real_old;
7128 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7130 rtx intermediate = second_reload_reg;
7132 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7134 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7138 second_reload_reg = intermediate;
7139 tertiary_icode = (enum insn_code) sri2.icode;
7144 real_oldequiv = real_old;
7147 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7149 rtx intermediate = second_reload_reg;
7151 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7153 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7156 second_reload_reg = intermediate;
7157 tertiary_icode = (enum insn_code) sri2.icode;
7162 real_oldequiv = real_old;
7167 /* This could be handled more intelligently too. */
7169 real_oldequiv = real_old;
7174 /* If we still need a secondary reload register, check
7175 to see if it is being used as a scratch or intermediate
7176 register and generate code appropriately. If we need
7177 a scratch register, use REAL_OLDEQUIV since the form of
7178 the insn may depend on the actual address if it is
7181 if (second_reload_reg)
7183 if (icode != CODE_FOR_nothing)
7185 /* We'd have to add extra code to handle this case. */
7186 gcc_assert (!third_reload_reg);
7188 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7189 second_reload_reg));
7194 /* See if we need a scratch register to load the
7195 intermediate register (a tertiary reload). */
7196 if (tertiary_icode != CODE_FOR_nothing)
7198 emit_insn ((GEN_FCN (tertiary_icode)
7199 (second_reload_reg, real_oldequiv,
7200 third_reload_reg)));
7202 else if (third_reload_reg)
7204 gen_reload (third_reload_reg, real_oldequiv,
7207 gen_reload (second_reload_reg, third_reload_reg,
7212 gen_reload (second_reload_reg, real_oldequiv,
7216 oldequiv = second_reload_reg;
7221 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7223 rtx real_oldequiv = oldequiv;
7225 if ((REG_P (oldequiv)
7226 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7227 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
7228 || reg_equiv_constant[REGNO (oldequiv)] != 0))
7229 || (GET_CODE (oldequiv) == SUBREG
7230 && REG_P (SUBREG_REG (oldequiv))
7231 && (REGNO (SUBREG_REG (oldequiv))
7232 >= FIRST_PSEUDO_REGISTER)
7233 && ((reg_equiv_memory_loc
7234 [REGNO (SUBREG_REG (oldequiv))] != 0)
7235 || (reg_equiv_constant
7236 [REGNO (SUBREG_REG (oldequiv))] != 0)))
7237 || (CONSTANT_P (oldequiv)
7238 && (PREFERRED_RELOAD_CLASS (oldequiv,
7239 REGNO_REG_CLASS (REGNO (reloadreg)))
7241 real_oldequiv = rl->in;
7242 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7246 if (flag_non_call_exceptions)
7247 copy_eh_notes (insn, get_insns ());
7249 /* End this sequence. */
7250 *where = get_insns ();
7253 /* Update reload_override_in so that delete_address_reloads_1
7254 can see the actual register usage. */
7256 reload_override_in[j] = oldequiv;
7259 /* Generate insns to for the output reload RL, which is for the insn described
7260 by CHAIN and has the number J. */
7262 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7266 rtx insn = chain->insn;
7269 enum machine_mode mode;
7273 if (rl->when_needed == RELOAD_OTHER)
7276 push_to_sequence (output_reload_insns[rl->opnum]);
7278 rl_reg_rtx = reload_reg_rtx_for_output[j];
7279 mode = GET_MODE (rl_reg_rtx);
7281 reloadreg = rl_reg_rtx;
7283 /* If we need two reload regs, set RELOADREG to the intermediate
7284 one, since it will be stored into OLD. We might need a secondary
7285 register only for an input reload, so check again here. */
7287 if (rl->secondary_out_reload >= 0)
7290 int secondary_reload = rl->secondary_out_reload;
7291 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7293 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7294 && reg_equiv_mem[REGNO (old)] != 0)
7295 real_old = reg_equiv_mem[REGNO (old)];
7297 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7299 rtx second_reloadreg = reloadreg;
7300 reloadreg = rld[secondary_reload].reg_rtx;
7302 /* See if RELOADREG is to be used as a scratch register
7303 or as an intermediate register. */
7304 if (rl->secondary_out_icode != CODE_FOR_nothing)
7306 /* We'd have to add extra code to handle this case. */
7307 gcc_assert (tertiary_reload < 0);
7309 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7310 (real_old, second_reloadreg, reloadreg)));
7315 /* See if we need both a scratch and intermediate reload
7318 enum insn_code tertiary_icode
7319 = rld[secondary_reload].secondary_out_icode;
7321 /* We'd have to add more code for quartary reloads. */
7322 gcc_assert (tertiary_reload < 0
7323 || rld[tertiary_reload].secondary_out_reload < 0);
7325 if (GET_MODE (reloadreg) != mode)
7326 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7328 if (tertiary_icode != CODE_FOR_nothing)
7330 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7333 /* Copy primary reload reg to secondary reload reg.
7334 (Note that these have been swapped above, then
7335 secondary reload reg to OLD using our insn.) */
7337 /* If REAL_OLD is a paradoxical SUBREG, remove it
7338 and try to put the opposite SUBREG on
7340 if (GET_CODE (real_old) == SUBREG
7341 && (GET_MODE_SIZE (GET_MODE (real_old))
7342 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7343 && 0 != (tem = gen_lowpart_common
7344 (GET_MODE (SUBREG_REG (real_old)),
7346 real_old = SUBREG_REG (real_old), reloadreg = tem;
7348 gen_reload (reloadreg, second_reloadreg,
7349 rl->opnum, rl->when_needed);
7350 emit_insn ((GEN_FCN (tertiary_icode)
7351 (real_old, reloadreg, third_reloadreg)));
7357 /* Copy between the reload regs here and then to
7360 gen_reload (reloadreg, second_reloadreg,
7361 rl->opnum, rl->when_needed);
7362 if (tertiary_reload >= 0)
7364 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7366 gen_reload (third_reloadreg, reloadreg,
7367 rl->opnum, rl->when_needed);
7368 reloadreg = third_reloadreg;
7375 /* Output the last reload insn. */
7380 /* Don't output the last reload if OLD is not the dest of
7381 INSN and is in the src and is clobbered by INSN. */
7382 if (! flag_expensive_optimizations
7384 || !(set = single_set (insn))
7385 || rtx_equal_p (old, SET_DEST (set))
7386 || !reg_mentioned_p (old, SET_SRC (set))
7387 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7388 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7389 gen_reload (old, reloadreg, rl->opnum,
7393 /* Look at all insns we emitted, just to be safe. */
7394 for (p = get_insns (); p; p = NEXT_INSN (p))
7397 rtx pat = PATTERN (p);
7399 /* If this output reload doesn't come from a spill reg,
7400 clear any memory of reloaded copies of the pseudo reg.
7401 If this output reload comes from a spill reg,
7402 reg_has_output_reload will make this do nothing. */
7403 note_stores (pat, forget_old_reloads_1, NULL);
7405 if (reg_mentioned_p (rl_reg_rtx, pat))
7407 rtx set = single_set (insn);
7408 if (reload_spill_index[j] < 0
7410 && SET_SRC (set) == rl_reg_rtx)
7412 int src = REGNO (SET_SRC (set));
7414 reload_spill_index[j] = src;
7415 SET_HARD_REG_BIT (reg_is_output_reload, src);
7416 if (find_regno_note (insn, REG_DEAD, src))
7417 SET_HARD_REG_BIT (reg_reloaded_died, src);
7419 if (HARD_REGISTER_P (rl_reg_rtx))
7421 int s = rl->secondary_out_reload;
7422 set = single_set (p);
7423 /* If this reload copies only to the secondary reload
7424 register, the secondary reload does the actual
7426 if (s >= 0 && set == NULL_RTX)
7427 /* We can't tell what function the secondary reload
7428 has and where the actual store to the pseudo is
7429 made; leave new_spill_reg_store alone. */
7432 && SET_SRC (set) == rl_reg_rtx
7433 && SET_DEST (set) == rld[s].reg_rtx)
7435 /* Usually the next instruction will be the
7436 secondary reload insn; if we can confirm
7437 that it is, setting new_spill_reg_store to
7438 that insn will allow an extra optimization. */
7439 rtx s_reg = rld[s].reg_rtx;
7440 rtx next = NEXT_INSN (p);
7441 rld[s].out = rl->out;
7442 rld[s].out_reg = rl->out_reg;
7443 set = single_set (next);
7444 if (set && SET_SRC (set) == s_reg
7445 && ! new_spill_reg_store[REGNO (s_reg)])
7447 SET_HARD_REG_BIT (reg_is_output_reload,
7449 new_spill_reg_store[REGNO (s_reg)] = next;
7453 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7458 if (rl->when_needed == RELOAD_OTHER)
7460 emit_insn (other_output_reload_insns[rl->opnum]);
7461 other_output_reload_insns[rl->opnum] = get_insns ();
7464 output_reload_insns[rl->opnum] = get_insns ();
7466 if (flag_non_call_exceptions)
7467 copy_eh_notes (insn, get_insns ());
7472 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7473 and has the number J. */
7475 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7477 rtx insn = chain->insn;
7478 rtx old = (rl->in && MEM_P (rl->in)
7479 ? rl->in_reg : rl->in);
7480 rtx reg_rtx = rl->reg_rtx;
7484 enum machine_mode mode;
7486 /* Determine the mode to reload in.
7487 This is very tricky because we have three to choose from.
7488 There is the mode the insn operand wants (rl->inmode).
7489 There is the mode of the reload register RELOADREG.
7490 There is the intrinsic mode of the operand, which we could find
7491 by stripping some SUBREGs.
7492 It turns out that RELOADREG's mode is irrelevant:
7493 we can change that arbitrarily.
7495 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7496 then the reload reg may not support QImode moves, so use SImode.
7497 If foo is in memory due to spilling a pseudo reg, this is safe,
7498 because the QImode value is in the least significant part of a
7499 slot big enough for a SImode. If foo is some other sort of
7500 memory reference, then it is impossible to reload this case,
7501 so previous passes had better make sure this never happens.
7503 Then consider a one-word union which has SImode and one of its
7504 members is a float, being fetched as (SUBREG:SF union:SI).
7505 We must fetch that as SFmode because we could be loading into
7506 a float-only register. In this case OLD's mode is correct.
7508 Consider an immediate integer: it has VOIDmode. Here we need
7509 to get a mode from something else.
7511 In some cases, there is a fourth mode, the operand's
7512 containing mode. If the insn specifies a containing mode for
7513 this operand, it overrides all others.
7515 I am not sure whether the algorithm here is always right,
7516 but it does the right things in those cases. */
7518 mode = GET_MODE (old);
7519 if (mode == VOIDmode)
7522 /* We cannot use gen_lowpart_common since it can do the wrong thing
7523 when REG_RTX has a multi-word mode. Note that REG_RTX must
7524 always be a REG here. */
7525 if (GET_MODE (reg_rtx) != mode)
7526 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7528 reload_reg_rtx_for_input[j] = reg_rtx;
7531 /* AUTO_INC reloads need to be handled even if inherited. We got an
7532 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7533 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7534 && ! rtx_equal_p (reg_rtx, old)
7536 emit_input_reload_insns (chain, rld + j, old, j);
7538 /* When inheriting a wider reload, we have a MEM in rl->in,
7539 e.g. inheriting a SImode output reload for
7540 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7541 if (optimize && reload_inherited[j] && rl->in
7543 && MEM_P (rl->in_reg)
7544 && reload_spill_index[j] >= 0
7545 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7546 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7548 /* If we are reloading a register that was recently stored in with an
7549 output-reload, see if we can prove there was
7550 actually no need to store the old value in it. */
7553 && (reload_inherited[j] || reload_override_in[j])
7556 && spill_reg_store[REGNO (reg_rtx)] != 0
7558 /* There doesn't seem to be any reason to restrict this to pseudos
7559 and doing so loses in the case where we are copying from a
7560 register of the wrong class. */
7561 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7563 /* The insn might have already some references to stackslots
7564 replaced by MEMs, while reload_out_reg still names the
7566 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7567 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7568 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7571 /* Do output reloading for reload RL, which is for the insn described by
7572 CHAIN and has the number J.
7573 ??? At some point we need to support handling output reloads of
7574 JUMP_INSNs or insns that set cc0. */
7576 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7579 rtx insn = chain->insn;
7580 /* If this is an output reload that stores something that is
7581 not loaded in this same reload, see if we can eliminate a previous
7583 rtx pseudo = rl->out_reg;
7584 rtx reg_rtx = rl->reg_rtx;
7586 if (rl->out && reg_rtx)
7588 enum machine_mode mode;
7590 /* Determine the mode to reload in.
7591 See comments above (for input reloading). */
7592 mode = GET_MODE (rl->out);
7593 if (mode == VOIDmode)
7595 /* VOIDmode should never happen for an output. */
7596 if (asm_noperands (PATTERN (insn)) < 0)
7597 /* It's the compiler's fault. */
7598 fatal_insn ("VOIDmode on an output", insn);
7599 error_for_asm (insn, "output operand is constant in %<asm%>");
7600 /* Prevent crash--use something we know is valid. */
7602 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7604 if (GET_MODE (reg_rtx) != mode)
7605 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7607 reload_reg_rtx_for_output[j] = reg_rtx;
7612 && ! rtx_equal_p (rl->in_reg, pseudo)
7613 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7614 && reg_last_reload_reg[REGNO (pseudo)])
7616 int pseudo_no = REGNO (pseudo);
7617 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7619 /* We don't need to test full validity of last_regno for
7620 inherit here; we only want to know if the store actually
7621 matches the pseudo. */
7622 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7623 && reg_reloaded_contents[last_regno] == pseudo_no
7624 && spill_reg_store[last_regno]
7625 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7626 delete_output_reload (insn, j, last_regno, reg_rtx);
7632 || rtx_equal_p (old, reg_rtx))
7635 /* An output operand that dies right away does need a reload,
7636 but need not be copied from it. Show the new location in the
7638 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7639 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7641 XEXP (note, 0) = reg_rtx;
7644 /* Likewise for a SUBREG of an operand that dies. */
7645 else if (GET_CODE (old) == SUBREG
7646 && REG_P (SUBREG_REG (old))
7647 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7650 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7653 else if (GET_CODE (old) == SCRATCH)
7654 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7655 but we don't want to make an output reload. */
7658 /* If is a JUMP_INSN, we can't support output reloads yet. */
7659 gcc_assert (NONJUMP_INSN_P (insn));
7661 emit_output_reload_insns (chain, rld + j, j);
7664 /* A reload copies values of MODE from register SRC to register DEST.
7665 Return true if it can be treated for inheritance purposes like a
7666 group of reloads, each one reloading a single hard register. The
7667 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7668 occupy the same number of hard registers. */
7671 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
7672 int src ATTRIBUTE_UNUSED,
7673 enum machine_mode mode ATTRIBUTE_UNUSED)
7675 #ifdef CANNOT_CHANGE_MODE_CLASS
7676 return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
7677 && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
7683 /* Output insns to reload values in and out of the chosen reload regs. */
7686 emit_reload_insns (struct insn_chain *chain)
7688 rtx insn = chain->insn;
7692 CLEAR_HARD_REG_SET (reg_reloaded_died);
7694 for (j = 0; j < reload_n_operands; j++)
7695 input_reload_insns[j] = input_address_reload_insns[j]
7696 = inpaddr_address_reload_insns[j]
7697 = output_reload_insns[j] = output_address_reload_insns[j]
7698 = outaddr_address_reload_insns[j]
7699 = other_output_reload_insns[j] = 0;
7700 other_input_address_reload_insns = 0;
7701 other_input_reload_insns = 0;
7702 operand_reload_insns = 0;
7703 other_operand_reload_insns = 0;
7705 /* Dump reloads into the dump file. */
7708 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7709 debug_reload_to_stream (dump_file);
7712 /* Now output the instructions to copy the data into and out of the
7713 reload registers. Do these in the order that the reloads were reported,
7714 since reloads of base and index registers precede reloads of operands
7715 and the operands may need the base and index registers reloaded. */
7717 for (j = 0; j < n_reloads; j++)
7719 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
7723 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
7724 new_spill_reg_store[i] = 0;
7727 do_input_reload (chain, rld + j, j);
7728 do_output_reload (chain, rld + j, j);
7731 /* Now write all the insns we made for reloads in the order expected by
7732 the allocation functions. Prior to the insn being reloaded, we write
7733 the following reloads:
7735 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7737 RELOAD_OTHER reloads.
7739 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7740 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7741 RELOAD_FOR_INPUT reload for the operand.
7743 RELOAD_FOR_OPADDR_ADDRS reloads.
7745 RELOAD_FOR_OPERAND_ADDRESS reloads.
7747 After the insn being reloaded, we write the following:
7749 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7750 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7751 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7752 reloads for the operand. The RELOAD_OTHER output reloads are
7753 output in descending order by reload number. */
7755 emit_insn_before (other_input_address_reload_insns, insn);
7756 emit_insn_before (other_input_reload_insns, insn);
7758 for (j = 0; j < reload_n_operands; j++)
7760 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7761 emit_insn_before (input_address_reload_insns[j], insn);
7762 emit_insn_before (input_reload_insns[j], insn);
7765 emit_insn_before (other_operand_reload_insns, insn);
7766 emit_insn_before (operand_reload_insns, insn);
7768 for (j = 0; j < reload_n_operands; j++)
7770 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7771 x = emit_insn_after (output_address_reload_insns[j], x);
7772 x = emit_insn_after (output_reload_insns[j], x);
7773 emit_insn_after (other_output_reload_insns[j], x);
7776 /* For all the spill regs newly reloaded in this instruction,
7777 record what they were reloaded from, so subsequent instructions
7778 can inherit the reloads.
7780 Update spill_reg_store for the reloads of this insn.
7781 Copy the elements that were updated in the loop above. */
7783 for (j = 0; j < n_reloads; j++)
7785 int r = reload_order[j];
7786 int i = reload_spill_index[r];
7788 /* If this is a non-inherited input reload from a pseudo, we must
7789 clear any memory of a previous store to the same pseudo. Only do
7790 something if there will not be an output reload for the pseudo
7792 if (rld[r].in_reg != 0
7793 && ! (reload_inherited[r] || reload_override_in[r]))
7795 rtx reg = rld[r].in_reg;
7797 if (GET_CODE (reg) == SUBREG)
7798 reg = SUBREG_REG (reg);
7801 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7802 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7804 int nregno = REGNO (reg);
7806 if (reg_last_reload_reg[nregno])
7808 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7810 if (reg_reloaded_contents[last_regno] == nregno)
7811 spill_reg_store[last_regno] = 0;
7816 /* I is nonneg if this reload used a register.
7817 If rld[r].reg_rtx is 0, this is an optional reload
7818 that we opted to ignore. */
7820 if (i >= 0 && rld[r].reg_rtx != 0)
7822 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7825 /* For a multi register reload, we need to check if all or part
7826 of the value lives to the end. */
7827 for (k = 0; k < nr; k++)
7828 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7829 rld[r].when_needed))
7830 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7832 /* Maybe the spill reg contains a copy of reload_out. */
7834 && (REG_P (rld[r].out)
7838 || REG_P (rld[r].out_reg)))
7841 enum machine_mode mode;
7844 reg = reload_reg_rtx_for_output[r];
7845 mode = GET_MODE (reg);
7846 regno = REGNO (reg);
7847 nregs = hard_regno_nregs[regno][mode];
7848 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7849 rld[r].when_needed))
7851 rtx out = (REG_P (rld[r].out)
7855 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7856 int out_regno = REGNO (out);
7857 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
7858 : hard_regno_nregs[out_regno][mode]);
7861 spill_reg_store[regno] = new_spill_reg_store[regno];
7862 spill_reg_stored_to[regno] = out;
7863 reg_last_reload_reg[out_regno] = reg;
7865 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
7866 && nregs == out_nregs
7867 && inherit_piecemeal_p (out_regno, regno, mode));
7869 /* If OUT_REGNO is a hard register, it may occupy more than
7870 one register. If it does, say what is in the
7871 rest of the registers assuming that both registers
7872 agree on how many words the object takes. If not,
7873 invalidate the subsequent registers. */
7875 if (HARD_REGISTER_NUM_P (out_regno))
7876 for (k = 1; k < out_nregs; k++)
7877 reg_last_reload_reg[out_regno + k]
7878 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7880 /* Now do the inverse operation. */
7881 for (k = 0; k < nregs; k++)
7883 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
7884 reg_reloaded_contents[regno + k]
7885 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
7888 reg_reloaded_insn[regno + k] = insn;
7889 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
7890 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
7891 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7894 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7899 /* Maybe the spill reg contains a copy of reload_in. Only do
7900 something if there will not be an output reload for
7901 the register being reloaded. */
7902 else if (rld[r].out_reg == 0
7904 && ((REG_P (rld[r].in)
7905 && !HARD_REGISTER_P (rld[r].in)
7906 && !REGNO_REG_SET_P (®_has_output_reload,
7908 || (REG_P (rld[r].in_reg)
7909 && !REGNO_REG_SET_P (®_has_output_reload,
7910 REGNO (rld[r].in_reg))))
7911 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
7914 enum machine_mode mode;
7917 reg = reload_reg_rtx_for_input[r];
7918 mode = GET_MODE (reg);
7919 regno = REGNO (reg);
7920 nregs = hard_regno_nregs[regno][mode];
7921 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7922 rld[r].when_needed))
7929 if (REG_P (rld[r].in)
7930 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7932 else if (REG_P (rld[r].in_reg))
7935 in = XEXP (rld[r].in_reg, 0);
7936 in_regno = REGNO (in);
7938 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
7939 : hard_regno_nregs[in_regno][mode]);
7941 reg_last_reload_reg[in_regno] = reg;
7943 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
7944 && nregs == in_nregs
7945 && inherit_piecemeal_p (regno, in_regno, mode));
7947 if (HARD_REGISTER_NUM_P (in_regno))
7948 for (k = 1; k < in_nregs; k++)
7949 reg_last_reload_reg[in_regno + k]
7950 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7952 /* Unless we inherited this reload, show we haven't
7953 recently done a store.
7954 Previous stores of inherited auto_inc expressions
7955 also have to be discarded. */
7956 if (! reload_inherited[r]
7957 || (rld[r].out && ! rld[r].out_reg))
7958 spill_reg_store[regno] = 0;
7960 for (k = 0; k < nregs; k++)
7962 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
7963 reg_reloaded_contents[regno + k]
7964 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
7967 reg_reloaded_insn[regno + k] = insn;
7968 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
7969 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
7970 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7973 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7980 /* The following if-statement was #if 0'd in 1.34 (or before...).
7981 It's reenabled in 1.35 because supposedly nothing else
7982 deals with this problem. */
7984 /* If a register gets output-reloaded from a non-spill register,
7985 that invalidates any previous reloaded copy of it.
7986 But forget_old_reloads_1 won't get to see it, because
7987 it thinks only about the original insn. So invalidate it here.
7988 Also do the same thing for RELOAD_OTHER constraints where the
7989 output is discarded. */
7991 && ((rld[r].out != 0
7992 && (REG_P (rld[r].out)
7993 || (MEM_P (rld[r].out)
7994 && REG_P (rld[r].out_reg))))
7995 || (rld[r].out == 0 && rld[r].out_reg
7996 && REG_P (rld[r].out_reg))))
7998 rtx out = ((rld[r].out && REG_P (rld[r].out))
7999 ? rld[r].out : rld[r].out_reg);
8000 int out_regno = REGNO (out);
8001 enum machine_mode mode = GET_MODE (out);
8003 /* REG_RTX is now set or clobbered by the main instruction.
8004 As the comment above explains, forget_old_reloads_1 only
8005 sees the original instruction, and there is no guarantee
8006 that the original instruction also clobbered REG_RTX.
8007 For example, if find_reloads sees that the input side of
8008 a matched operand pair dies in this instruction, it may
8009 use the input register as the reload register.
8011 Calling forget_old_reloads_1 is a waste of effort if
8012 REG_RTX is also the output register.
8014 If we know that REG_RTX holds the value of a pseudo
8015 register, the code after the call will record that fact. */
8016 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8017 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8019 if (!HARD_REGISTER_NUM_P (out_regno))
8021 rtx src_reg, store_insn = NULL_RTX;
8023 reg_last_reload_reg[out_regno] = 0;
8025 /* If we can find a hard register that is stored, record
8026 the storing insn so that we may delete this insn with
8027 delete_output_reload. */
8028 src_reg = reload_reg_rtx_for_output[r];
8030 /* If this is an optional reload, try to find the source reg
8031 from an input reload. */
8034 rtx set = single_set (insn);
8035 if (set && SET_DEST (set) == rld[r].out)
8039 src_reg = SET_SRC (set);
8041 for (k = 0; k < n_reloads; k++)
8043 if (rld[k].in == src_reg)
8045 src_reg = reload_reg_rtx_for_input[k];
8052 store_insn = new_spill_reg_store[REGNO (src_reg)];
8053 if (src_reg && REG_P (src_reg)
8054 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8056 int src_regno, src_nregs, k;
8059 gcc_assert (GET_MODE (src_reg) == mode);
8060 src_regno = REGNO (src_reg);
8061 src_nregs = hard_regno_nregs[src_regno][mode];
8062 /* The place where to find a death note varies with
8063 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8064 necessarily checked exactly in the code that moves
8065 notes, so just check both locations. */
8066 note = find_regno_note (insn, REG_DEAD, src_regno);
8067 if (! note && store_insn)
8068 note = find_regno_note (store_insn, REG_DEAD, src_regno);
8069 for (k = 0; k < src_nregs; k++)
8071 spill_reg_store[src_regno + k] = store_insn;
8072 spill_reg_stored_to[src_regno + k] = out;
8073 reg_reloaded_contents[src_regno + k] = out_regno;
8074 reg_reloaded_insn[src_regno + k] = store_insn;
8075 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8076 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8077 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
8079 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8082 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8084 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8086 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8088 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8090 reg_last_reload_reg[out_regno] = src_reg;
8091 /* We have to set reg_has_output_reload here, or else
8092 forget_old_reloads_1 will clear reg_last_reload_reg
8094 SET_REGNO_REG_SET (®_has_output_reload,
8100 int k, out_nregs = hard_regno_nregs[out_regno][mode];
8102 for (k = 0; k < out_nregs; k++)
8103 reg_last_reload_reg[out_regno + k] = 0;
8107 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8110 /* Go through the motions to emit INSN and test if it is strictly valid.
8111 Return the emitted insn if valid, else return NULL. */
8114 emit_insn_if_valid_for_reload (rtx insn)
8116 rtx last = get_last_insn ();
8119 insn = emit_insn (insn);
8120 code = recog_memoized (insn);
8124 extract_insn (insn);
8125 /* We want constrain operands to treat this insn strictly in its
8126 validity determination, i.e., the way it would after reload has
8128 if (constrain_operands (1))
8132 delete_insns_since (last);
8136 /* Emit code to perform a reload from IN (which may be a reload register) to
8137 OUT (which may also be a reload register). IN or OUT is from operand
8138 OPNUM with reload type TYPE.
8140 Returns first insn emitted. */
8143 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8145 rtx last = get_last_insn ();
8148 /* If IN is a paradoxical SUBREG, remove it and try to put the
8149 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8150 if (GET_CODE (in) == SUBREG
8151 && (GET_MODE_SIZE (GET_MODE (in))
8152 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
8153 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
8154 in = SUBREG_REG (in), out = tem;
8155 else if (GET_CODE (out) == SUBREG
8156 && (GET_MODE_SIZE (GET_MODE (out))
8157 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
8158 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
8159 out = SUBREG_REG (out), in = tem;
8161 /* How to do this reload can get quite tricky. Normally, we are being
8162 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8163 register that didn't get a hard register. In that case we can just
8164 call emit_move_insn.
8166 We can also be asked to reload a PLUS that adds a register or a MEM to
8167 another register, constant or MEM. This can occur during frame pointer
8168 elimination and while reloading addresses. This case is handled by
8169 trying to emit a single insn to perform the add. If it is not valid,
8170 we use a two insn sequence.
8172 Or we can be asked to reload an unary operand that was a fragment of
8173 an addressing mode, into a register. If it isn't recognized as-is,
8174 we try making the unop operand and the reload-register the same:
8175 (set reg:X (unop:X expr:Y))
8176 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8178 Finally, we could be called to handle an 'o' constraint by putting
8179 an address into a register. In that case, we first try to do this
8180 with a named pattern of "reload_load_address". If no such pattern
8181 exists, we just emit a SET insn and hope for the best (it will normally
8182 be valid on machines that use 'o').
8184 This entire process is made complex because reload will never
8185 process the insns we generate here and so we must ensure that
8186 they will fit their constraints and also by the fact that parts of
8187 IN might be being reloaded separately and replaced with spill registers.
8188 Because of this, we are, in some sense, just guessing the right approach
8189 here. The one listed above seems to work.
8191 ??? At some point, this whole thing needs to be rethought. */
8193 if (GET_CODE (in) == PLUS
8194 && (REG_P (XEXP (in, 0))
8195 || GET_CODE (XEXP (in, 0)) == SUBREG
8196 || MEM_P (XEXP (in, 0)))
8197 && (REG_P (XEXP (in, 1))
8198 || GET_CODE (XEXP (in, 1)) == SUBREG
8199 || CONSTANT_P (XEXP (in, 1))
8200 || MEM_P (XEXP (in, 1))))
8202 /* We need to compute the sum of a register or a MEM and another
8203 register, constant, or MEM, and put it into the reload
8204 register. The best possible way of doing this is if the machine
8205 has a three-operand ADD insn that accepts the required operands.
8207 The simplest approach is to try to generate such an insn and see if it
8208 is recognized and matches its constraints. If so, it can be used.
8210 It might be better not to actually emit the insn unless it is valid,
8211 but we need to pass the insn as an operand to `recog' and
8212 `extract_insn' and it is simpler to emit and then delete the insn if
8213 not valid than to dummy things up. */
8215 rtx op0, op1, tem, insn;
8218 op0 = find_replacement (&XEXP (in, 0));
8219 op1 = find_replacement (&XEXP (in, 1));
8221 /* Since constraint checking is strict, commutativity won't be
8222 checked, so we need to do that here to avoid spurious failure
8223 if the add instruction is two-address and the second operand
8224 of the add is the same as the reload reg, which is frequently
8225 the case. If the insn would be A = B + A, rearrange it so
8226 it will be A = A + B as constrain_operands expects. */
8228 if (REG_P (XEXP (in, 1))
8229 && REGNO (out) == REGNO (XEXP (in, 1)))
8230 tem = op0, op0 = op1, op1 = tem;
8232 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8233 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8235 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8239 /* If that failed, we must use a conservative two-insn sequence.
8241 Use a move to copy one operand into the reload register. Prefer
8242 to reload a constant, MEM or pseudo since the move patterns can
8243 handle an arbitrary operand. If OP1 is not a constant, MEM or
8244 pseudo and OP1 is not a valid operand for an add instruction, then
8247 After reloading one of the operands into the reload register, add
8248 the reload register to the output register.
8250 If there is another way to do this for a specific machine, a
8251 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8254 code = (int) optab_handler (add_optab, GET_MODE (out))->insn_code;
8256 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8258 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8259 || (code != CODE_FOR_nothing
8260 && ! ((*insn_data[code].operand[2].predicate)
8261 (op1, insn_data[code].operand[2].mode))))
8262 tem = op0, op0 = op1, op1 = tem;
8264 gen_reload (out, op0, opnum, type);
8266 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8267 This fixes a problem on the 32K where the stack pointer cannot
8268 be used as an operand of an add insn. */
8270 if (rtx_equal_p (op0, op1))
8273 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8276 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8277 set_unique_reg_note (insn, REG_EQUIV, in);
8281 /* If that failed, copy the address register to the reload register.
8282 Then add the constant to the reload register. */
8284 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8285 gen_reload (out, op1, opnum, type);
8286 insn = emit_insn (gen_add2_insn (out, op0));
8287 set_unique_reg_note (insn, REG_EQUIV, in);
8290 #ifdef SECONDARY_MEMORY_NEEDED
8291 /* If we need a memory location to do the move, do it that way. */
8292 else if ((REG_P (in)
8293 || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
8294 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
8296 || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
8297 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
8298 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
8299 REGNO_REG_CLASS (reg_or_subregno (out)),
8302 /* Get the memory to use and rewrite both registers to its mode. */
8303 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8305 if (GET_MODE (loc) != GET_MODE (out))
8306 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
8308 if (GET_MODE (loc) != GET_MODE (in))
8309 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
8311 gen_reload (loc, in, opnum, type);
8312 gen_reload (out, loc, opnum, type);
8315 else if (REG_P (out) && UNARY_P (in))
8322 op1 = find_replacement (&XEXP (in, 0));
8323 if (op1 != XEXP (in, 0))
8324 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8326 /* First, try a plain SET. */
8327 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8331 /* If that failed, move the inner operand to the reload
8332 register, and try the same unop with the inner expression
8333 replaced with the reload register. */
8335 if (GET_MODE (op1) != GET_MODE (out))
8336 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8340 gen_reload (out_moded, op1, opnum, type);
8343 = gen_rtx_SET (VOIDmode, out,
8344 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8346 insn = emit_insn_if_valid_for_reload (insn);
8349 set_unique_reg_note (insn, REG_EQUIV, in);
8353 fatal_insn ("Failure trying to reload:", set);
8355 /* If IN is a simple operand, use gen_move_insn. */
8356 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8358 tem = emit_insn (gen_move_insn (out, in));
8359 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8360 mark_jump_label (in, tem, 0);
8363 #ifdef HAVE_reload_load_address
8364 else if (HAVE_reload_load_address)
8365 emit_insn (gen_reload_load_address (out, in));
8368 /* Otherwise, just write (set OUT IN) and hope for the best. */
8370 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8372 /* Return the first insn emitted.
8373 We can not just return get_last_insn, because there may have
8374 been multiple instructions emitted. Also note that gen_move_insn may
8375 emit more than one insn itself, so we can not assume that there is one
8376 insn emitted per emit_insn_before call. */
8378 return last ? NEXT_INSN (last) : get_insns ();
8381 /* Delete a previously made output-reload whose result we now believe
8382 is not needed. First we double-check.
8384 INSN is the insn now being processed.
8385 LAST_RELOAD_REG is the hard register number for which we want to delete
8386 the last output reload.
8387 J is the reload-number that originally used REG. The caller has made
8388 certain that reload J doesn't use REG any longer for input.
8389 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8392 delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg)
8394 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8395 rtx reg = spill_reg_stored_to[last_reload_reg];
8398 int n_inherited = 0;
8402 /* It is possible that this reload has been only used to set another reload
8403 we eliminated earlier and thus deleted this instruction too. */
8404 if (INSN_DELETED_P (output_reload_insn))
8407 /* Get the raw pseudo-register referred to. */
8409 while (GET_CODE (reg) == SUBREG)
8410 reg = SUBREG_REG (reg);
8411 substed = reg_equiv_memory_loc[REGNO (reg)];
8413 /* This is unsafe if the operand occurs more often in the current
8414 insn than it is inherited. */
8415 for (k = n_reloads - 1; k >= 0; k--)
8417 rtx reg2 = rld[k].in;
8420 if (MEM_P (reg2) || reload_override_in[k])
8421 reg2 = rld[k].in_reg;
8423 if (rld[k].out && ! rld[k].out_reg)
8424 reg2 = XEXP (rld[k].in_reg, 0);
8426 while (GET_CODE (reg2) == SUBREG)
8427 reg2 = SUBREG_REG (reg2);
8428 if (rtx_equal_p (reg2, reg))
8430 if (reload_inherited[k] || reload_override_in[k] || k == j)
8436 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8437 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8438 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8441 n_occurrences += count_occurrences (PATTERN (insn),
8442 eliminate_regs (substed, VOIDmode,
8444 for (i1 = reg_equiv_alt_mem_list[REGNO (reg)]; i1; i1 = XEXP (i1, 1))
8446 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8447 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8449 if (n_occurrences > n_inherited)
8452 /* If the pseudo-reg we are reloading is no longer referenced
8453 anywhere between the store into it and here,
8454 and we're within the same basic block, then the value can only
8455 pass through the reload reg and end up here.
8456 Otherwise, give up--return. */
8457 for (i1 = NEXT_INSN (output_reload_insn);
8458 i1 != insn; i1 = NEXT_INSN (i1))
8460 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8462 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8463 && reg_mentioned_p (reg, PATTERN (i1)))
8465 /* If this is USE in front of INSN, we only have to check that
8466 there are no more references than accounted for by inheritance. */
8467 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8469 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8470 i1 = NEXT_INSN (i1);
8472 if (n_occurrences <= n_inherited && i1 == insn)
8478 /* We will be deleting the insn. Remove the spill reg information. */
8479 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8481 spill_reg_store[last_reload_reg + k] = 0;
8482 spill_reg_stored_to[last_reload_reg + k] = 0;
8485 /* The caller has already checked that REG dies or is set in INSN.
8486 It has also checked that we are optimizing, and thus some
8487 inaccuracies in the debugging information are acceptable.
8488 So we could just delete output_reload_insn. But in some cases
8489 we can improve the debugging information without sacrificing
8490 optimization - maybe even improving the code: See if the pseudo
8491 reg has been completely replaced with reload regs. If so, delete
8492 the store insn and forget we had a stack slot for the pseudo. */
8493 if (rld[j].out != rld[j].in
8494 && REG_N_DEATHS (REGNO (reg)) == 1
8495 && REG_N_SETS (REGNO (reg)) == 1
8496 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8497 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8501 /* We know that it was used only between here and the beginning of
8502 the current basic block. (We also know that the last use before
8503 INSN was the output reload we are thinking of deleting, but never
8504 mind that.) Search that range; see if any ref remains. */
8505 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8507 rtx set = single_set (i2);
8509 /* Uses which just store in the pseudo don't count,
8510 since if they are the only uses, they are dead. */
8511 if (set != 0 && SET_DEST (set) == reg)
8516 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8517 && reg_mentioned_p (reg, PATTERN (i2)))
8519 /* Some other ref remains; just delete the output reload we
8521 delete_address_reloads (output_reload_insn, insn);
8522 delete_insn (output_reload_insn);
8527 /* Delete the now-dead stores into this pseudo. Note that this
8528 loop also takes care of deleting output_reload_insn. */
8529 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8531 rtx set = single_set (i2);
8533 if (set != 0 && SET_DEST (set) == reg)
8535 delete_address_reloads (i2, insn);
8543 /* For the debugging info, say the pseudo lives in this reload reg. */
8544 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8545 if (ira_conflicts_p)
8546 /* Inform IRA about the change. */
8547 ira_mark_allocation_change (REGNO (reg));
8548 alter_reg (REGNO (reg), -1, false);
8552 delete_address_reloads (output_reload_insn, insn);
8553 delete_insn (output_reload_insn);
8557 /* We are going to delete DEAD_INSN. Recursively delete loads of
8558 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8559 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8561 delete_address_reloads (rtx dead_insn, rtx current_insn)
8563 rtx set = single_set (dead_insn);
8564 rtx set2, dst, prev, next;
8567 rtx dst = SET_DEST (set);
8569 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8571 /* If we deleted the store from a reloaded post_{in,de}c expression,
8572 we can delete the matching adds. */
8573 prev = PREV_INSN (dead_insn);
8574 next = NEXT_INSN (dead_insn);
8575 if (! prev || ! next)
8577 set = single_set (next);
8578 set2 = single_set (prev);
8580 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8581 || !CONST_INT_P (XEXP (SET_SRC (set), 1))
8582 || !CONST_INT_P (XEXP (SET_SRC (set2), 1)))
8584 dst = SET_DEST (set);
8585 if (! rtx_equal_p (dst, SET_DEST (set2))
8586 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8587 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8588 || (INTVAL (XEXP (SET_SRC (set), 1))
8589 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8591 delete_related_insns (prev);
8592 delete_related_insns (next);
8595 /* Subfunction of delete_address_reloads: process registers found in X. */
8597 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8599 rtx prev, set, dst, i2;
8601 enum rtx_code code = GET_CODE (x);
8605 const char *fmt = GET_RTX_FORMAT (code);
8606 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8609 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8610 else if (fmt[i] == 'E')
8612 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8613 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8620 if (spill_reg_order[REGNO (x)] < 0)
8623 /* Scan backwards for the insn that sets x. This might be a way back due
8625 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8627 code = GET_CODE (prev);
8628 if (code == CODE_LABEL || code == JUMP_INSN)
8632 if (reg_set_p (x, PATTERN (prev)))
8634 if (reg_referenced_p (x, PATTERN (prev)))
8637 if (! prev || INSN_UID (prev) < reload_first_uid)
8639 /* Check that PREV only sets the reload register. */
8640 set = single_set (prev);
8643 dst = SET_DEST (set);
8645 || ! rtx_equal_p (dst, x))
8647 if (! reg_set_p (dst, PATTERN (dead_insn)))
8649 /* Check if DST was used in a later insn -
8650 it might have been inherited. */
8651 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8657 if (reg_referenced_p (dst, PATTERN (i2)))
8659 /* If there is a reference to the register in the current insn,
8660 it might be loaded in a non-inherited reload. If no other
8661 reload uses it, that means the register is set before
8663 if (i2 == current_insn)
8665 for (j = n_reloads - 1; j >= 0; j--)
8666 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8667 || reload_override_in[j] == dst)
8669 for (j = n_reloads - 1; j >= 0; j--)
8670 if (rld[j].in && rld[j].reg_rtx == dst)
8679 /* If DST is still live at CURRENT_INSN, check if it is used for
8680 any reload. Note that even if CURRENT_INSN sets DST, we still
8681 have to check the reloads. */
8682 if (i2 == current_insn)
8684 for (j = n_reloads - 1; j >= 0; j--)
8685 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8686 || reload_override_in[j] == dst)
8688 /* ??? We can't finish the loop here, because dst might be
8689 allocated to a pseudo in this block if no reload in this
8690 block needs any of the classes containing DST - see
8691 spill_hard_reg. There is no easy way to tell this, so we
8692 have to scan till the end of the basic block. */
8694 if (reg_set_p (dst, PATTERN (i2)))
8698 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8699 reg_reloaded_contents[REGNO (dst)] = -1;
8703 /* Output reload-insns to reload VALUE into RELOADREG.
8704 VALUE is an autoincrement or autodecrement RTX whose operand
8705 is a register or memory location;
8706 so reloading involves incrementing that location.
8707 IN is either identical to VALUE, or some cheaper place to reload from.
8709 INC_AMOUNT is the number to increment or decrement by (always positive).
8710 This cannot be deduced from VALUE.
8712 Return the instruction that stores into RELOADREG. */
8715 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8717 /* REG or MEM to be copied and incremented. */
8718 rtx incloc = find_replacement (&XEXP (value, 0));
8719 /* Nonzero if increment after copying. */
8720 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8721 || GET_CODE (value) == POST_MODIFY);
8727 rtx real_in = in == value ? incloc : in;
8729 /* No hard register is equivalent to this register after
8730 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8731 we could inc/dec that register as well (maybe even using it for
8732 the source), but I'm not sure it's worth worrying about. */
8734 reg_last_reload_reg[REGNO (incloc)] = 0;
8736 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8738 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8739 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8743 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8744 inc_amount = -inc_amount;
8746 inc = GEN_INT (inc_amount);
8749 /* If this is post-increment, first copy the location to the reload reg. */
8750 if (post && real_in != reloadreg)
8751 emit_insn (gen_move_insn (reloadreg, real_in));
8755 /* See if we can directly increment INCLOC. Use a method similar to
8756 that in gen_reload. */
8758 last = get_last_insn ();
8759 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8760 gen_rtx_PLUS (GET_MODE (incloc),
8763 code = recog_memoized (add_insn);
8766 extract_insn (add_insn);
8767 if (constrain_operands (1))
8769 /* If this is a pre-increment and we have incremented the value
8770 where it lives, copy the incremented value to RELOADREG to
8771 be used as an address. */
8774 emit_insn (gen_move_insn (reloadreg, incloc));
8779 delete_insns_since (last);
8782 /* If couldn't do the increment directly, must increment in RELOADREG.
8783 The way we do this depends on whether this is pre- or post-increment.
8784 For pre-increment, copy INCLOC to the reload register, increment it
8785 there, then save back. */
8789 if (in != reloadreg)
8790 emit_insn (gen_move_insn (reloadreg, real_in));
8791 emit_insn (gen_add2_insn (reloadreg, inc));
8792 store = emit_insn (gen_move_insn (incloc, reloadreg));
8797 Because this might be a jump insn or a compare, and because RELOADREG
8798 may not be available after the insn in an input reload, we must do
8799 the incrementation before the insn being reloaded for.
8801 We have already copied IN to RELOADREG. Increment the copy in
8802 RELOADREG, save that back, then decrement RELOADREG so it has
8803 the original value. */
8805 emit_insn (gen_add2_insn (reloadreg, inc));
8806 store = emit_insn (gen_move_insn (incloc, reloadreg));
8807 if (CONST_INT_P (inc))
8808 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
8810 emit_insn (gen_sub2_insn (reloadreg, inc));
8818 add_auto_inc_notes (rtx insn, rtx x)
8820 enum rtx_code code = GET_CODE (x);
8824 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8826 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
8830 /* Scan all the operand sub-expressions. */
8831 fmt = GET_RTX_FORMAT (code);
8832 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8835 add_auto_inc_notes (insn, XEXP (x, i));
8836 else if (fmt[i] == 'E')
8837 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8838 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8843 /* Copy EH notes from an insn to its reloads. */
8845 copy_eh_notes (rtx insn, rtx x)
8847 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8850 for (; x != 0; x = NEXT_INSN (x))
8852 if (may_trap_p (PATTERN (x)))
8853 add_reg_note (x, REG_EH_REGION, XEXP (eh_note, 0));
8858 /* This is used by reload pass, that does emit some instructions after
8859 abnormal calls moving basic block end, but in fact it wants to emit
8860 them on the edge. Looks for abnormal call edges, find backward the
8861 proper call and fix the damage.
8863 Similar handle instructions throwing exceptions internally. */
8865 fixup_abnormal_edges (void)
8867 bool inserted = false;
8875 /* Look for cases we are interested in - calls or instructions causing
8877 FOR_EACH_EDGE (e, ei, bb->succs)
8879 if (e->flags & EDGE_ABNORMAL_CALL)
8881 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8882 == (EDGE_ABNORMAL | EDGE_EH))
8885 if (e && !CALL_P (BB_END (bb))
8886 && !can_throw_internal (BB_END (bb)))
8890 /* Get past the new insns generated. Allow notes, as the insns
8891 may be already deleted. */
8893 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8894 && !can_throw_internal (insn)
8895 && insn != BB_HEAD (bb))
8896 insn = PREV_INSN (insn);
8898 if (CALL_P (insn) || can_throw_internal (insn))
8902 stop = NEXT_INSN (BB_END (bb));
8904 insn = NEXT_INSN (insn);
8906 FOR_EACH_EDGE (e, ei, bb->succs)
8907 if (e->flags & EDGE_FALLTHRU)
8910 while (insn && insn != stop)
8912 next = NEXT_INSN (insn);
8917 /* Sometimes there's still the return value USE.
8918 If it's placed after a trapping call (i.e. that
8919 call is the last insn anyway), we have no fallthru
8920 edge. Simply delete this use and don't try to insert
8921 on the non-existent edge. */
8922 if (GET_CODE (PATTERN (insn)) != USE)
8924 /* We're not deleting it, we're moving it. */
8925 INSN_DELETED_P (insn) = 0;
8926 PREV_INSN (insn) = NULL_RTX;
8927 NEXT_INSN (insn) = NULL_RTX;
8929 insert_insn_on_edge (insn, e);
8933 else if (!BARRIER_P (insn))
8934 set_block_for_insn (insn, NULL);
8939 /* It may be that we don't find any such trapping insn. In this
8940 case we discovered quite late that the insn that had been
8941 marked as can_throw_internal in fact couldn't trap at all.
8942 So we should in fact delete the EH edges out of the block. */
8944 purge_dead_edges (bb);
8948 /* We've possibly turned single trapping insn into multiple ones. */
8949 if (flag_non_call_exceptions)
8952 blocks = sbitmap_alloc (last_basic_block);
8953 sbitmap_ones (blocks);
8954 find_many_sub_basic_blocks (blocks);
8955 sbitmap_free (blocks);
8959 commit_edge_insertions ();
8961 #ifdef ENABLE_CHECKING
8962 /* Verify that we didn't turn one trapping insn into many, and that
8963 we found and corrected all of the problems wrt fixups on the
8965 verify_flow_info ();
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