1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation,
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
33 #include "insn-config.h"
39 #include "addresses.h"
40 #include "basic-block.h"
50 /* This file contains the reload pass of the compiler, which is
51 run after register allocation has been done. It checks that
52 each insn is valid (operands required to be in registers really
53 are in registers of the proper class) and fixes up invalid ones
54 by copying values temporarily into registers for the insns
57 The results of register allocation are described by the vector
58 reg_renumber; the insns still contain pseudo regs, but reg_renumber
59 can be used to find which hard reg, if any, a pseudo reg is in.
61 The technique we always use is to free up a few hard regs that are
62 called ``reload regs'', and for each place where a pseudo reg
63 must be in a hard reg, copy it temporarily into one of the reload regs.
65 Reload regs are allocated locally for every instruction that needs
66 reloads. When there are pseudos which are allocated to a register that
67 has been chosen as a reload reg, such pseudos must be ``spilled''.
68 This means that they go to other hard regs, or to stack slots if no other
69 available hard regs can be found. Spilling can invalidate more
70 insns, requiring additional need for reloads, so we must keep checking
71 until the process stabilizes.
73 For machines with different classes of registers, we must keep track
74 of the register class needed for each reload, and make sure that
75 we allocate enough reload registers of each class.
77 The file reload.c contains the code that checks one insn for
78 validity and reports the reloads that it needs. This file
79 is in charge of scanning the entire rtl code, accumulating the
80 reload needs, spilling, assigning reload registers to use for
81 fixing up each insn, and generating the new insns to copy values
82 into the reload registers. */
84 /* During reload_as_needed, element N contains a REG rtx for the hard reg
85 into which reg N has been reloaded (perhaps for a previous insn). */
86 static rtx *reg_last_reload_reg;
88 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
89 for an output reload that stores into reg N. */
90 static regset_head reg_has_output_reload;
92 /* Indicates which hard regs are reload-registers for an output reload
93 in the current insn. */
94 static HARD_REG_SET reg_is_output_reload;
96 /* Element N is the constant value to which pseudo reg N is equivalent,
97 or zero if pseudo reg N is not equivalent to a constant.
98 find_reloads looks at this in order to replace pseudo reg N
99 with the constant it stands for. */
100 rtx *reg_equiv_constant;
102 /* Element N is an invariant value to which pseudo reg N is equivalent.
103 eliminate_regs_in_insn uses this to replace pseudos in particular
105 rtx *reg_equiv_invariant;
107 /* Element N is a memory location to which pseudo reg N is equivalent,
108 prior to any register elimination (such as frame pointer to stack
109 pointer). Depending on whether or not it is a valid address, this value
110 is transferred to either reg_equiv_address or reg_equiv_mem. */
111 rtx *reg_equiv_memory_loc;
113 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
114 collector can keep track of what is inside. */
115 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
117 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
118 This is used when the address is not valid as a memory address
119 (because its displacement is too big for the machine.) */
120 rtx *reg_equiv_address;
122 /* Element N is the memory slot to which pseudo reg N is equivalent,
123 or zero if pseudo reg N is not equivalent to a memory slot. */
126 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
127 alternate representations of the location of pseudo reg N. */
128 rtx *reg_equiv_alt_mem_list;
130 /* Widest width in which each pseudo reg is referred to (via subreg). */
131 static unsigned int *reg_max_ref_width;
133 /* Element N is the list of insns that initialized reg N from its equivalent
134 constant or memory slot. */
136 int reg_equiv_init_size;
138 /* Vector to remember old contents of reg_renumber before spilling. */
139 static short *reg_old_renumber;
141 /* During reload_as_needed, element N contains the last pseudo regno reloaded
142 into hard register N. If that pseudo reg occupied more than one register,
143 reg_reloaded_contents points to that pseudo for each spill register in
144 use; all of these must remain set for an inheritance to occur. */
145 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
147 /* During reload_as_needed, element N contains the insn for which
148 hard register N was last used. Its contents are significant only
149 when reg_reloaded_valid is set for this register. */
150 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
152 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
153 static HARD_REG_SET reg_reloaded_valid;
154 /* Indicate if the register was dead at the end of the reload.
155 This is only valid if reg_reloaded_contents is set and valid. */
156 static HARD_REG_SET reg_reloaded_dead;
158 /* Indicate whether the register's current value is one that is not
159 safe to retain across a call, even for registers that are normally
161 static HARD_REG_SET reg_reloaded_call_part_clobbered;
163 /* Number of spill-regs so far; number of valid elements of spill_regs. */
166 /* In parallel with spill_regs, contains REG rtx's for those regs.
167 Holds the last rtx used for any given reg, or 0 if it has never
168 been used for spilling yet. This rtx is reused, provided it has
170 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
172 /* In parallel with spill_regs, contains nonzero for a spill reg
173 that was stored after the last time it was used.
174 The precise value is the insn generated to do the store. */
175 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
177 /* This is the register that was stored with spill_reg_store. This is a
178 copy of reload_out / reload_out_reg when the value was stored; if
179 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
180 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
182 /* This table is the inverse mapping of spill_regs:
183 indexed by hard reg number,
184 it contains the position of that reg in spill_regs,
185 or -1 for something that is not in spill_regs.
187 ?!? This is no longer accurate. */
188 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
190 /* This reg set indicates registers that can't be used as spill registers for
191 the currently processed insn. These are the hard registers which are live
192 during the insn, but not allocated to pseudos, as well as fixed
194 static HARD_REG_SET bad_spill_regs;
196 /* These are the hard registers that can't be used as spill register for any
197 insn. This includes registers used for user variables and registers that
198 we can't eliminate. A register that appears in this set also can't be used
199 to retry register allocation. */
200 static HARD_REG_SET bad_spill_regs_global;
202 /* Describes order of use of registers for reloading
203 of spilled pseudo-registers. `n_spills' is the number of
204 elements that are actually valid; new ones are added at the end.
206 Both spill_regs and spill_reg_order are used on two occasions:
207 once during find_reload_regs, where they keep track of the spill registers
208 for a single insn, but also during reload_as_needed where they show all
209 the registers ever used by reload. For the latter case, the information
210 is calculated during finish_spills. */
211 static short spill_regs[FIRST_PSEUDO_REGISTER];
213 /* This vector of reg sets indicates, for each pseudo, which hard registers
214 may not be used for retrying global allocation because the register was
215 formerly spilled from one of them. If we allowed reallocating a pseudo to
216 a register that it was already allocated to, reload might not
218 static HARD_REG_SET *pseudo_previous_regs;
220 /* This vector of reg sets indicates, for each pseudo, which hard
221 registers may not be used for retrying global allocation because they
222 are used as spill registers during one of the insns in which the
224 static HARD_REG_SET *pseudo_forbidden_regs;
226 /* All hard regs that have been used as spill registers for any insn are
227 marked in this set. */
228 static HARD_REG_SET used_spill_regs;
230 /* Index of last register assigned as a spill register. We allocate in
231 a round-robin fashion. */
232 static int last_spill_reg;
234 /* Nonzero if indirect addressing is supported on the machine; this means
235 that spilling (REG n) does not require reloading it into a register in
236 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
237 value indicates the level of indirect addressing supported, e.g., two
238 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
240 static char spill_indirect_levels;
242 /* Nonzero if indirect addressing is supported when the innermost MEM is
243 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
244 which these are valid is the same as spill_indirect_levels, above. */
245 char indirect_symref_ok;
247 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
248 char double_reg_address_ok;
250 /* Record the stack slot for each spilled hard register. */
251 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
253 /* Width allocated so far for that stack slot. */
254 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
256 /* Record which pseudos needed to be spilled. */
257 static regset_head spilled_pseudos;
259 /* Used for communication between order_regs_for_reload and count_pseudo.
260 Used to avoid counting one pseudo twice. */
261 static regset_head pseudos_counted;
263 /* First uid used by insns created by reload in this function.
264 Used in find_equiv_reg. */
265 int reload_first_uid;
267 /* Flag set by local-alloc or global-alloc if anything is live in
268 a call-clobbered reg across calls. */
269 int caller_save_needed;
271 /* Set to 1 while reload_as_needed is operating.
272 Required by some machines to handle any generated moves differently. */
273 int reload_in_progress = 0;
275 /* These arrays record the insn_code of insns that may be needed to
276 perform input and output reloads of special objects. They provide a
277 place to pass a scratch register. */
278 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
279 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
281 /* This obstack is used for allocation of rtl during register elimination.
282 The allocated storage can be freed once find_reloads has processed the
284 static struct obstack reload_obstack;
286 /* Points to the beginning of the reload_obstack. All insn_chain structures
287 are allocated first. */
288 static char *reload_startobj;
290 /* The point after all insn_chain structures. Used to quickly deallocate
291 memory allocated in copy_reloads during calculate_needs_all_insns. */
292 static char *reload_firstobj;
294 /* This points before all local rtl generated by register elimination.
295 Used to quickly free all memory after processing one insn. */
296 static char *reload_insn_firstobj;
298 /* List of insn_chain instructions, one for every insn that reload needs to
300 struct insn_chain *reload_insn_chain;
302 /* List of all insns needing reloads. */
303 static struct insn_chain *insns_need_reload;
305 /* This structure is used to record information about register eliminations.
306 Each array entry describes one possible way of eliminating a register
307 in favor of another. If there is more than one way of eliminating a
308 particular register, the most preferred should be specified first. */
312 int from; /* Register number to be eliminated. */
313 int to; /* Register number used as replacement. */
314 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
315 int can_eliminate; /* Nonzero if this elimination can be done. */
316 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
317 insns made by reload. */
318 HOST_WIDE_INT offset; /* Current offset between the two regs. */
319 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
320 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
321 rtx from_rtx; /* REG rtx for the register to be eliminated.
322 We cannot simply compare the number since
323 we might then spuriously replace a hard
324 register corresponding to a pseudo
325 assigned to the reg to be eliminated. */
326 rtx to_rtx; /* REG rtx for the replacement. */
329 static struct elim_table *reg_eliminate = 0;
331 /* This is an intermediate structure to initialize the table. It has
332 exactly the members provided by ELIMINABLE_REGS. */
333 static const struct elim_table_1
337 } reg_eliminate_1[] =
339 /* If a set of eliminable registers was specified, define the table from it.
340 Otherwise, default to the normal case of the frame pointer being
341 replaced by the stack pointer. */
343 #ifdef ELIMINABLE_REGS
346 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
349 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
351 /* Record the number of pending eliminations that have an offset not equal
352 to their initial offset. If nonzero, we use a new copy of each
353 replacement result in any insns encountered. */
354 int num_not_at_initial_offset;
356 /* Count the number of registers that we may be able to eliminate. */
357 static int num_eliminable;
358 /* And the number of registers that are equivalent to a constant that
359 can be eliminated to frame_pointer / arg_pointer + constant. */
360 static int num_eliminable_invariants;
362 /* For each label, we record the offset of each elimination. If we reach
363 a label by more than one path and an offset differs, we cannot do the
364 elimination. This information is indexed by the difference of the
365 number of the label and the first label number. We can't offset the
366 pointer itself as this can cause problems on machines with segmented
367 memory. The first table is an array of flags that records whether we
368 have yet encountered a label and the second table is an array of arrays,
369 one entry in the latter array for each elimination. */
371 static int first_label_num;
372 static char *offsets_known_at;
373 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
375 /* Number of labels in the current function. */
377 static int num_labels;
379 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
380 static void maybe_fix_stack_asms (void);
381 static void copy_reloads (struct insn_chain *);
382 static void calculate_needs_all_insns (int);
383 static int find_reg (struct insn_chain *, int);
384 static void find_reload_regs (struct insn_chain *);
385 static void select_reload_regs (void);
386 static void delete_caller_save_insns (void);
388 static void spill_failure (rtx, enum reg_class);
389 static void count_spilled_pseudo (int, int, int);
390 static void delete_dead_insn (rtx);
391 static void alter_reg (int, int);
392 static void set_label_offsets (rtx, rtx, int);
393 static void check_eliminable_occurrences (rtx);
394 static void elimination_effects (rtx, enum machine_mode);
395 static int eliminate_regs_in_insn (rtx, int);
396 static void update_eliminable_offsets (void);
397 static void mark_not_eliminable (rtx, rtx, void *);
398 static void set_initial_elim_offsets (void);
399 static bool verify_initial_elim_offsets (void);
400 static void set_initial_label_offsets (void);
401 static void set_offsets_for_label (rtx);
402 static void init_elim_table (void);
403 static void update_eliminables (HARD_REG_SET *);
404 static void spill_hard_reg (unsigned int, int);
405 static int finish_spills (int);
406 static void scan_paradoxical_subregs (rtx);
407 static void count_pseudo (int);
408 static void order_regs_for_reload (struct insn_chain *);
409 static void reload_as_needed (int);
410 static void forget_old_reloads_1 (rtx, rtx, void *);
411 static void forget_marked_reloads (regset);
412 static int reload_reg_class_lower (const void *, const void *);
413 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
415 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
417 static int reload_reg_free_p (unsigned int, int, enum reload_type);
418 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
420 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
422 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
423 static int allocate_reload_reg (struct insn_chain *, int, int);
424 static int conflicts_with_override (rtx);
425 static void failed_reload (rtx, int);
426 static int set_reload_reg (int, int);
427 static void choose_reload_regs_init (struct insn_chain *, rtx *);
428 static void choose_reload_regs (struct insn_chain *);
429 static void merge_assigned_reloads (rtx);
430 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
432 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
434 static void do_input_reload (struct insn_chain *, struct reload *, int);
435 static void do_output_reload (struct insn_chain *, struct reload *, int);
436 static bool inherit_piecemeal_p (int, int);
437 static void emit_reload_insns (struct insn_chain *);
438 static void delete_output_reload (rtx, int, int);
439 static void delete_address_reloads (rtx, rtx);
440 static void delete_address_reloads_1 (rtx, rtx, rtx);
441 static rtx inc_for_reload (rtx, rtx, rtx, int);
443 static void add_auto_inc_notes (rtx, rtx);
445 static void copy_eh_notes (rtx, rtx);
446 static int reloads_conflict (int, int);
447 static rtx gen_reload (rtx, rtx, int, enum reload_type);
448 static rtx emit_insn_if_valid_for_reload (rtx);
450 /* Initialize the reload pass once per compilation. */
457 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
458 Set spill_indirect_levels to the number of levels such addressing is
459 permitted, zero if it is not permitted at all. */
462 = gen_rtx_MEM (Pmode,
465 LAST_VIRTUAL_REGISTER + 1),
467 spill_indirect_levels = 0;
469 while (memory_address_p (QImode, tem))
471 spill_indirect_levels++;
472 tem = gen_rtx_MEM (Pmode, tem);
475 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
477 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
478 indirect_symref_ok = memory_address_p (QImode, tem);
480 /* See if reg+reg is a valid (and offsettable) address. */
482 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
484 tem = gen_rtx_PLUS (Pmode,
485 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
486 gen_rtx_REG (Pmode, i));
488 /* This way, we make sure that reg+reg is an offsettable address. */
489 tem = plus_constant (tem, 4);
491 if (memory_address_p (QImode, tem))
493 double_reg_address_ok = 1;
498 /* Initialize obstack for our rtl allocation. */
499 gcc_obstack_init (&reload_obstack);
500 reload_startobj = obstack_alloc (&reload_obstack, 0);
502 INIT_REG_SET (&spilled_pseudos);
503 INIT_REG_SET (&pseudos_counted);
506 /* List of insn chains that are currently unused. */
507 static struct insn_chain *unused_insn_chains = 0;
509 /* Allocate an empty insn_chain structure. */
511 new_insn_chain (void)
513 struct insn_chain *c;
515 if (unused_insn_chains == 0)
517 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
518 INIT_REG_SET (&c->live_throughout);
519 INIT_REG_SET (&c->dead_or_set);
523 c = unused_insn_chains;
524 unused_insn_chains = c->next;
526 c->is_caller_save_insn = 0;
527 c->need_operand_change = 0;
533 /* Small utility function to set all regs in hard reg set TO which are
534 allocated to pseudos in regset FROM. */
537 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
540 reg_set_iterator rsi;
542 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
544 int r = reg_renumber[regno];
549 /* reload_combine uses the information from
550 BASIC_BLOCK->global_live_at_start, which might still
551 contain registers that have not actually been allocated
552 since they have an equivalence. */
553 gcc_assert (reload_completed);
557 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
559 SET_HARD_REG_BIT (*to, r + nregs);
564 /* Replace all pseudos found in LOC with their corresponding
568 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
581 unsigned int regno = REGNO (x);
583 if (regno < FIRST_PSEUDO_REGISTER)
586 x = eliminate_regs (x, mem_mode, usage);
590 replace_pseudos_in (loc, mem_mode, usage);
594 if (reg_equiv_constant[regno])
595 *loc = reg_equiv_constant[regno];
596 else if (reg_equiv_mem[regno])
597 *loc = reg_equiv_mem[regno];
598 else if (reg_equiv_address[regno])
599 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
602 gcc_assert (!REG_P (regno_reg_rtx[regno])
603 || REGNO (regno_reg_rtx[regno]) != regno);
604 *loc = regno_reg_rtx[regno];
609 else if (code == MEM)
611 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
615 /* Process each of our operands recursively. */
616 fmt = GET_RTX_FORMAT (code);
617 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
619 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
620 else if (*fmt == 'E')
621 for (j = 0; j < XVECLEN (x, i); j++)
622 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
626 /* Global variables used by reload and its subroutines. */
628 /* Set during calculate_needs if an insn needs register elimination. */
629 static int something_needs_elimination;
630 /* Set during calculate_needs if an insn needs an operand changed. */
631 static int something_needs_operands_changed;
633 /* Nonzero means we couldn't get enough spill regs. */
636 /* Main entry point for the reload pass.
638 FIRST is the first insn of the function being compiled.
640 GLOBAL nonzero means we were called from global_alloc
641 and should attempt to reallocate any pseudoregs that we
642 displace from hard regs we will use for reloads.
643 If GLOBAL is zero, we do not have enough information to do that,
644 so any pseudo reg that is spilled must go to the stack.
646 Return value is nonzero if reload failed
647 and we must not do any more for this function. */
650 reload (rtx first, int global)
654 struct elim_table *ep;
657 /* Make sure even insns with volatile mem refs are recognizable. */
662 reload_firstobj = obstack_alloc (&reload_obstack, 0);
664 /* Make sure that the last insn in the chain
665 is not something that needs reloading. */
666 emit_note (NOTE_INSN_DELETED);
668 /* Enable find_equiv_reg to distinguish insns made by reload. */
669 reload_first_uid = get_max_uid ();
671 #ifdef SECONDARY_MEMORY_NEEDED
672 /* Initialize the secondary memory table. */
673 clear_secondary_mem ();
676 /* We don't have a stack slot for any spill reg yet. */
677 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
678 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
680 /* Initialize the save area information for caller-save, in case some
684 /* Compute which hard registers are now in use
685 as homes for pseudo registers.
686 This is done here rather than (eg) in global_alloc
687 because this point is reached even if not optimizing. */
688 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
691 /* A function that receives a nonlocal goto must save all call-saved
693 if (current_function_has_nonlocal_label)
694 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
695 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
696 regs_ever_live[i] = 1;
698 /* Find all the pseudo registers that didn't get hard regs
699 but do have known equivalent constants or memory slots.
700 These include parameters (known equivalent to parameter slots)
701 and cse'd or loop-moved constant memory addresses.
703 Record constant equivalents in reg_equiv_constant
704 so they will be substituted by find_reloads.
705 Record memory equivalents in reg_mem_equiv so they can
706 be substituted eventually by altering the REG-rtx's. */
708 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
709 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
710 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
711 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
712 reg_equiv_address = XCNEWVEC (rtx, max_regno);
713 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
714 reg_old_renumber = XCNEWVEC (short, max_regno);
715 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
716 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
717 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
719 CLEAR_HARD_REG_SET (bad_spill_regs_global);
721 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
722 to. Also find all paradoxical subregs and find largest such for
725 num_eliminable_invariants = 0;
726 for (insn = first; insn; insn = NEXT_INSN (insn))
728 rtx set = single_set (insn);
730 /* We may introduce USEs that we want to remove at the end, so
731 we'll mark them with QImode. Make sure there are no
732 previously-marked insns left by say regmove. */
733 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
734 && GET_MODE (insn) != VOIDmode)
735 PUT_MODE (insn, VOIDmode);
738 scan_paradoxical_subregs (PATTERN (insn));
740 if (set != 0 && REG_P (SET_DEST (set)))
742 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
748 i = REGNO (SET_DEST (set));
751 if (i <= LAST_VIRTUAL_REGISTER)
754 if (! function_invariant_p (x)
756 /* A function invariant is often CONSTANT_P but may
757 include a register. We promise to only pass
758 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
760 && LEGITIMATE_PIC_OPERAND_P (x)))
762 /* It can happen that a REG_EQUIV note contains a MEM
763 that is not a legitimate memory operand. As later
764 stages of reload assume that all addresses found
765 in the reg_equiv_* arrays were originally legitimate,
766 we ignore such REG_EQUIV notes. */
767 if (memory_operand (x, VOIDmode))
769 /* Always unshare the equivalence, so we can
770 substitute into this insn without touching the
772 reg_equiv_memory_loc[i] = copy_rtx (x);
774 else if (function_invariant_p (x))
776 if (GET_CODE (x) == PLUS)
778 /* This is PLUS of frame pointer and a constant,
779 and might be shared. Unshare it. */
780 reg_equiv_invariant[i] = copy_rtx (x);
781 num_eliminable_invariants++;
783 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
785 reg_equiv_invariant[i] = x;
786 num_eliminable_invariants++;
788 else if (LEGITIMATE_CONSTANT_P (x))
789 reg_equiv_constant[i] = x;
792 reg_equiv_memory_loc[i]
793 = force_const_mem (GET_MODE (SET_DEST (set)), x);
794 if (! reg_equiv_memory_loc[i])
795 reg_equiv_init[i] = NULL_RTX;
800 reg_equiv_init[i] = NULL_RTX;
805 reg_equiv_init[i] = NULL_RTX;
810 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
811 if (reg_equiv_init[i])
813 fprintf (dump_file, "init_insns for %u: ", i);
814 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
815 fprintf (dump_file, "\n");
820 first_label_num = get_first_label_num ();
821 num_labels = max_label_num () - first_label_num;
823 /* Allocate the tables used to store offset information at labels. */
824 /* We used to use alloca here, but the size of what it would try to
825 allocate would occasionally cause it to exceed the stack limit and
826 cause a core dump. */
827 offsets_known_at = XNEWVEC (char, num_labels);
828 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
830 /* Alter each pseudo-reg rtx to contain its hard reg number.
831 Assign stack slots to the pseudos that lack hard regs or equivalents.
832 Do not touch virtual registers. */
834 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
837 /* If we have some registers we think can be eliminated, scan all insns to
838 see if there is an insn that sets one of these registers to something
839 other than itself plus a constant. If so, the register cannot be
840 eliminated. Doing this scan here eliminates an extra pass through the
841 main reload loop in the most common case where register elimination
843 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
845 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
847 maybe_fix_stack_asms ();
849 insns_need_reload = 0;
850 something_needs_elimination = 0;
852 /* Initialize to -1, which means take the first spill register. */
855 /* Spill any hard regs that we know we can't eliminate. */
856 CLEAR_HARD_REG_SET (used_spill_regs);
857 /* There can be multiple ways to eliminate a register;
858 they should be listed adjacently.
859 Elimination for any register fails only if all possible ways fail. */
860 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
863 int can_eliminate = 0;
866 can_eliminate |= ep->can_eliminate;
869 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
871 spill_hard_reg (from, 1);
874 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
875 if (frame_pointer_needed)
876 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
878 finish_spills (global);
880 /* From now on, we may need to generate moves differently. We may also
881 allow modifications of insns which cause them to not be recognized.
882 Any such modifications will be cleaned up during reload itself. */
883 reload_in_progress = 1;
885 /* This loop scans the entire function each go-round
886 and repeats until one repetition spills no additional hard regs. */
889 int something_changed;
892 HOST_WIDE_INT starting_frame_size;
894 /* Round size of stack frame to stack_alignment_needed. This must be done
895 here because the stack size may be a part of the offset computation
896 for register elimination, and there might have been new stack slots
897 created in the last iteration of this loop. */
898 if (cfun->stack_alignment_needed)
899 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
901 starting_frame_size = get_frame_size ();
903 set_initial_elim_offsets ();
904 set_initial_label_offsets ();
906 /* For each pseudo register that has an equivalent location defined,
907 try to eliminate any eliminable registers (such as the frame pointer)
908 assuming initial offsets for the replacement register, which
911 If the resulting location is directly addressable, substitute
912 the MEM we just got directly for the old REG.
914 If it is not addressable but is a constant or the sum of a hard reg
915 and constant, it is probably not addressable because the constant is
916 out of range, in that case record the address; we will generate
917 hairy code to compute the address in a register each time it is
918 needed. Similarly if it is a hard register, but one that is not
919 valid as an address register.
921 If the location is not addressable, but does not have one of the
922 above forms, assign a stack slot. We have to do this to avoid the
923 potential of producing lots of reloads if, e.g., a location involves
924 a pseudo that didn't get a hard register and has an equivalent memory
925 location that also involves a pseudo that didn't get a hard register.
927 Perhaps at some point we will improve reload_when_needed handling
928 so this problem goes away. But that's very hairy. */
930 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
931 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
933 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
935 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
937 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
938 else if (CONSTANT_P (XEXP (x, 0))
939 || (REG_P (XEXP (x, 0))
940 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
941 || (GET_CODE (XEXP (x, 0)) == PLUS
942 && REG_P (XEXP (XEXP (x, 0), 0))
943 && (REGNO (XEXP (XEXP (x, 0), 0))
944 < FIRST_PSEUDO_REGISTER)
945 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
946 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
949 /* Make a new stack slot. Then indicate that something
950 changed so we go back and recompute offsets for
951 eliminable registers because the allocation of memory
952 below might change some offset. reg_equiv_{mem,address}
953 will be set up for this pseudo on the next pass around
955 reg_equiv_memory_loc[i] = 0;
956 reg_equiv_init[i] = 0;
961 if (caller_save_needed)
964 /* If we allocated another stack slot, redo elimination bookkeeping. */
965 if (starting_frame_size != get_frame_size ())
968 if (caller_save_needed)
970 save_call_clobbered_regs ();
971 /* That might have allocated new insn_chain structures. */
972 reload_firstobj = obstack_alloc (&reload_obstack, 0);
975 calculate_needs_all_insns (global);
977 CLEAR_REG_SET (&spilled_pseudos);
980 something_changed = 0;
982 /* If we allocated any new memory locations, make another pass
983 since it might have changed elimination offsets. */
984 if (starting_frame_size != get_frame_size ())
985 something_changed = 1;
987 /* Even if the frame size remained the same, we might still have
988 changed elimination offsets, e.g. if find_reloads called
989 force_const_mem requiring the back end to allocate a constant
990 pool base register that needs to be saved on the stack. */
991 else if (!verify_initial_elim_offsets ())
992 something_changed = 1;
995 HARD_REG_SET to_spill;
996 CLEAR_HARD_REG_SET (to_spill);
997 update_eliminables (&to_spill);
998 AND_COMPL_HARD_REG_SET(used_spill_regs, to_spill);
1000 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1001 if (TEST_HARD_REG_BIT (to_spill, i))
1003 spill_hard_reg (i, 1);
1006 /* Regardless of the state of spills, if we previously had
1007 a register that we thought we could eliminate, but now can
1008 not eliminate, we must run another pass.
1010 Consider pseudos which have an entry in reg_equiv_* which
1011 reference an eliminable register. We must make another pass
1012 to update reg_equiv_* so that we do not substitute in the
1013 old value from when we thought the elimination could be
1015 something_changed = 1;
1019 select_reload_regs ();
1023 if (insns_need_reload != 0 || did_spill)
1024 something_changed |= finish_spills (global);
1026 if (! something_changed)
1029 if (caller_save_needed)
1030 delete_caller_save_insns ();
1032 obstack_free (&reload_obstack, reload_firstobj);
1035 /* If global-alloc was run, notify it of any register eliminations we have
1038 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1039 if (ep->can_eliminate)
1040 mark_elimination (ep->from, ep->to);
1042 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1043 If that insn didn't set the register (i.e., it copied the register to
1044 memory), just delete that insn instead of the equivalencing insn plus
1045 anything now dead. If we call delete_dead_insn on that insn, we may
1046 delete the insn that actually sets the register if the register dies
1047 there and that is incorrect. */
1049 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1051 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1054 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1056 rtx equiv_insn = XEXP (list, 0);
1058 /* If we already deleted the insn or if it may trap, we can't
1059 delete it. The latter case shouldn't happen, but can
1060 if an insn has a variable address, gets a REG_EH_REGION
1061 note added to it, and then gets converted into a load
1062 from a constant address. */
1063 if (NOTE_P (equiv_insn)
1064 || can_throw_internal (equiv_insn))
1066 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1067 delete_dead_insn (equiv_insn);
1069 SET_INSN_DELETED (equiv_insn);
1074 /* Use the reload registers where necessary
1075 by generating move instructions to move the must-be-register
1076 values into or out of the reload registers. */
1078 if (insns_need_reload != 0 || something_needs_elimination
1079 || something_needs_operands_changed)
1081 HOST_WIDE_INT old_frame_size = get_frame_size ();
1083 reload_as_needed (global);
1085 gcc_assert (old_frame_size == get_frame_size ());
1087 gcc_assert (verify_initial_elim_offsets ());
1090 /* If we were able to eliminate the frame pointer, show that it is no
1091 longer live at the start of any basic block. If it ls live by
1092 virtue of being in a pseudo, that pseudo will be marked live
1093 and hence the frame pointer will be known to be live via that
1096 if (! frame_pointer_needed)
1098 CLEAR_REGNO_REG_SET (bb->il.rtl->global_live_at_start,
1099 HARD_FRAME_POINTER_REGNUM);
1101 /* Come here (with failure set nonzero) if we can't get enough spill
1105 CLEAR_REG_SET (&spilled_pseudos);
1106 reload_in_progress = 0;
1108 /* Now eliminate all pseudo regs by modifying them into
1109 their equivalent memory references.
1110 The REG-rtx's for the pseudos are modified in place,
1111 so all insns that used to refer to them now refer to memory.
1113 For a reg that has a reg_equiv_address, all those insns
1114 were changed by reloading so that no insns refer to it any longer;
1115 but the DECL_RTL of a variable decl may refer to it,
1116 and if so this causes the debugging info to mention the variable. */
1118 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1122 if (reg_equiv_mem[i])
1123 addr = XEXP (reg_equiv_mem[i], 0);
1125 if (reg_equiv_address[i])
1126 addr = reg_equiv_address[i];
1130 if (reg_renumber[i] < 0)
1132 rtx reg = regno_reg_rtx[i];
1134 REG_USERVAR_P (reg) = 0;
1135 PUT_CODE (reg, MEM);
1136 XEXP (reg, 0) = addr;
1137 if (reg_equiv_memory_loc[i])
1138 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1141 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1142 MEM_ATTRS (reg) = 0;
1144 MEM_NOTRAP_P (reg) = 1;
1146 else if (reg_equiv_mem[i])
1147 XEXP (reg_equiv_mem[i], 0) = addr;
1151 /* We must set reload_completed now since the cleanup_subreg_operands call
1152 below will re-recognize each insn and reload may have generated insns
1153 which are only valid during and after reload. */
1154 reload_completed = 1;
1156 /* Make a pass over all the insns and delete all USEs which we inserted
1157 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1158 notes. Delete all CLOBBER insns, except those that refer to the return
1159 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1160 from misarranging variable-array code, and simplify (subreg (reg))
1161 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1162 are no longer useful or accurate. Strip and regenerate REG_INC notes
1163 that may have been moved around. */
1165 for (insn = first; insn; insn = NEXT_INSN (insn))
1170 /* Clean up invalid ASMs so that they don't confuse later passes.
1172 if (asm_noperands (PATTERN (insn)) >= 0)
1174 extract_insn (insn);
1175 if (!constrain_operands (1))
1177 error_for_asm (insn,
1178 "%<asm%> operand has impossible constraints");
1185 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1186 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1188 if ((GET_CODE (PATTERN (insn)) == USE
1189 /* We mark with QImode USEs introduced by reload itself. */
1190 && (GET_MODE (insn) == QImode
1191 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1192 || (GET_CODE (PATTERN (insn)) == CLOBBER
1193 && (!MEM_P (XEXP (PATTERN (insn), 0))
1194 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1195 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1196 && XEXP (XEXP (PATTERN (insn), 0), 0)
1197 != stack_pointer_rtx))
1198 && (!REG_P (XEXP (PATTERN (insn), 0))
1199 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1205 /* Some CLOBBERs may survive until here and still reference unassigned
1206 pseudos with const equivalent, which may in turn cause ICE in later
1207 passes if the reference remains in place. */
1208 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1209 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1210 VOIDmode, PATTERN (insn));
1212 /* Discard obvious no-ops, even without -O. This optimization
1213 is fast and doesn't interfere with debugging. */
1214 if (NONJUMP_INSN_P (insn)
1215 && GET_CODE (PATTERN (insn)) == SET
1216 && REG_P (SET_SRC (PATTERN (insn)))
1217 && REG_P (SET_DEST (PATTERN (insn)))
1218 && (REGNO (SET_SRC (PATTERN (insn)))
1219 == REGNO (SET_DEST (PATTERN (insn)))))
1225 pnote = ®_NOTES (insn);
1228 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1229 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1230 || REG_NOTE_KIND (*pnote) == REG_INC
1231 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1232 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1233 *pnote = XEXP (*pnote, 1);
1235 pnote = &XEXP (*pnote, 1);
1239 add_auto_inc_notes (insn, PATTERN (insn));
1242 /* And simplify (subreg (reg)) if it appears as an operand. */
1243 cleanup_subreg_operands (insn);
1246 /* If we are doing stack checking, give a warning if this function's
1247 frame size is larger than we expect. */
1248 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1250 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1251 static int verbose_warned = 0;
1253 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1254 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1255 size += UNITS_PER_WORD;
1257 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1259 warning (0, "frame size too large for reliable stack checking");
1260 if (! verbose_warned)
1262 warning (0, "try reducing the number of local variables");
1268 /* Indicate that we no longer have known memory locations or constants. */
1269 if (reg_equiv_constant)
1270 free (reg_equiv_constant);
1271 if (reg_equiv_invariant)
1272 free (reg_equiv_invariant);
1273 reg_equiv_constant = 0;
1274 reg_equiv_invariant = 0;
1275 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1276 reg_equiv_memory_loc = 0;
1278 if (offsets_known_at)
1279 free (offsets_known_at);
1283 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1284 if (reg_equiv_alt_mem_list[i])
1285 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1286 free (reg_equiv_alt_mem_list);
1288 free (reg_equiv_mem);
1290 free (reg_equiv_address);
1291 free (reg_max_ref_width);
1292 free (reg_old_renumber);
1293 free (pseudo_previous_regs);
1294 free (pseudo_forbidden_regs);
1296 CLEAR_HARD_REG_SET (used_spill_regs);
1297 for (i = 0; i < n_spills; i++)
1298 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1300 /* Free all the insn_chain structures at once. */
1301 obstack_free (&reload_obstack, reload_startobj);
1302 unused_insn_chains = 0;
1303 fixup_abnormal_edges ();
1305 /* Replacing pseudos with their memory equivalents might have
1306 created shared rtx. Subsequent passes would get confused
1307 by this, so unshare everything here. */
1308 unshare_all_rtl_again (first);
1310 #ifdef STACK_BOUNDARY
1311 /* init_emit has set the alignment of the hard frame pointer
1312 to STACK_BOUNDARY. It is very likely no longer valid if
1313 the hard frame pointer was used for register allocation. */
1314 if (!frame_pointer_needed)
1315 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1321 /* Yet another special case. Unfortunately, reg-stack forces people to
1322 write incorrect clobbers in asm statements. These clobbers must not
1323 cause the register to appear in bad_spill_regs, otherwise we'll call
1324 fatal_insn later. We clear the corresponding regnos in the live
1325 register sets to avoid this.
1326 The whole thing is rather sick, I'm afraid. */
1329 maybe_fix_stack_asms (void)
1332 const char *constraints[MAX_RECOG_OPERANDS];
1333 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1334 struct insn_chain *chain;
1336 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1339 HARD_REG_SET clobbered, allowed;
1342 if (! INSN_P (chain->insn)
1343 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1345 pat = PATTERN (chain->insn);
1346 if (GET_CODE (pat) != PARALLEL)
1349 CLEAR_HARD_REG_SET (clobbered);
1350 CLEAR_HARD_REG_SET (allowed);
1352 /* First, make a mask of all stack regs that are clobbered. */
1353 for (i = 0; i < XVECLEN (pat, 0); i++)
1355 rtx t = XVECEXP (pat, 0, i);
1356 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1357 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1360 /* Get the operand values and constraints out of the insn. */
1361 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1362 constraints, operand_mode);
1364 /* For every operand, see what registers are allowed. */
1365 for (i = 0; i < noperands; i++)
1367 const char *p = constraints[i];
1368 /* For every alternative, we compute the class of registers allowed
1369 for reloading in CLS, and merge its contents into the reg set
1371 int cls = (int) NO_REGS;
1377 if (c == '\0' || c == ',' || c == '#')
1379 /* End of one alternative - mark the regs in the current
1380 class, and reset the class. */
1381 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1387 } while (c != '\0' && c != ',');
1395 case '=': case '+': case '*': case '%': case '?': case '!':
1396 case '0': case '1': case '2': case '3': case '4': case 'm':
1397 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1398 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1399 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1404 cls = (int) reg_class_subunion[cls]
1405 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1410 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1414 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1415 cls = (int) reg_class_subunion[cls]
1416 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1418 cls = (int) reg_class_subunion[cls]
1419 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1421 p += CONSTRAINT_LEN (c, p);
1424 /* Those of the registers which are clobbered, but allowed by the
1425 constraints, must be usable as reload registers. So clear them
1426 out of the life information. */
1427 AND_HARD_REG_SET (allowed, clobbered);
1428 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1429 if (TEST_HARD_REG_BIT (allowed, i))
1431 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1432 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1439 /* Copy the global variables n_reloads and rld into the corresponding elts
1442 copy_reloads (struct insn_chain *chain)
1444 chain->n_reloads = n_reloads;
1445 chain->rld = obstack_alloc (&reload_obstack,
1446 n_reloads * sizeof (struct reload));
1447 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1448 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1451 /* Walk the chain of insns, and determine for each whether it needs reloads
1452 and/or eliminations. Build the corresponding insns_need_reload list, and
1453 set something_needs_elimination as appropriate. */
1455 calculate_needs_all_insns (int global)
1457 struct insn_chain **pprev_reload = &insns_need_reload;
1458 struct insn_chain *chain, *next = 0;
1460 something_needs_elimination = 0;
1462 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1463 for (chain = reload_insn_chain; chain != 0; chain = next)
1465 rtx insn = chain->insn;
1469 /* Clear out the shortcuts. */
1470 chain->n_reloads = 0;
1471 chain->need_elim = 0;
1472 chain->need_reload = 0;
1473 chain->need_operand_change = 0;
1475 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1476 include REG_LABEL), we need to see what effects this has on the
1477 known offsets at labels. */
1479 if (LABEL_P (insn) || JUMP_P (insn)
1480 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1481 set_label_offsets (insn, insn, 0);
1485 rtx old_body = PATTERN (insn);
1486 int old_code = INSN_CODE (insn);
1487 rtx old_notes = REG_NOTES (insn);
1488 int did_elimination = 0;
1489 int operands_changed = 0;
1490 rtx set = single_set (insn);
1492 /* Skip insns that only set an equivalence. */
1493 if (set && REG_P (SET_DEST (set))
1494 && reg_renumber[REGNO (SET_DEST (set))] < 0
1495 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1496 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1497 && reg_equiv_init[REGNO (SET_DEST (set))])
1500 /* If needed, eliminate any eliminable registers. */
1501 if (num_eliminable || num_eliminable_invariants)
1502 did_elimination = eliminate_regs_in_insn (insn, 0);
1504 /* Analyze the instruction. */
1505 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1506 global, spill_reg_order);
1508 /* If a no-op set needs more than one reload, this is likely
1509 to be something that needs input address reloads. We
1510 can't get rid of this cleanly later, and it is of no use
1511 anyway, so discard it now.
1512 We only do this when expensive_optimizations is enabled,
1513 since this complements reload inheritance / output
1514 reload deletion, and it can make debugging harder. */
1515 if (flag_expensive_optimizations && n_reloads > 1)
1517 rtx set = single_set (insn);
1519 && SET_SRC (set) == SET_DEST (set)
1520 && REG_P (SET_SRC (set))
1521 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1524 /* Delete it from the reload chain. */
1526 chain->prev->next = next;
1528 reload_insn_chain = next;
1530 next->prev = chain->prev;
1531 chain->next = unused_insn_chains;
1532 unused_insn_chains = chain;
1537 update_eliminable_offsets ();
1539 /* Remember for later shortcuts which insns had any reloads or
1540 register eliminations. */
1541 chain->need_elim = did_elimination;
1542 chain->need_reload = n_reloads > 0;
1543 chain->need_operand_change = operands_changed;
1545 /* Discard any register replacements done. */
1546 if (did_elimination)
1548 obstack_free (&reload_obstack, reload_insn_firstobj);
1549 PATTERN (insn) = old_body;
1550 INSN_CODE (insn) = old_code;
1551 REG_NOTES (insn) = old_notes;
1552 something_needs_elimination = 1;
1555 something_needs_operands_changed |= operands_changed;
1559 copy_reloads (chain);
1560 *pprev_reload = chain;
1561 pprev_reload = &chain->next_need_reload;
1568 /* Comparison function for qsort to decide which of two reloads
1569 should be handled first. *P1 and *P2 are the reload numbers. */
1572 reload_reg_class_lower (const void *r1p, const void *r2p)
1574 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1577 /* Consider required reloads before optional ones. */
1578 t = rld[r1].optional - rld[r2].optional;
1582 /* Count all solitary classes before non-solitary ones. */
1583 t = ((reg_class_size[(int) rld[r2].class] == 1)
1584 - (reg_class_size[(int) rld[r1].class] == 1));
1588 /* Aside from solitaires, consider all multi-reg groups first. */
1589 t = rld[r2].nregs - rld[r1].nregs;
1593 /* Consider reloads in order of increasing reg-class number. */
1594 t = (int) rld[r1].class - (int) rld[r2].class;
1598 /* If reloads are equally urgent, sort by reload number,
1599 so that the results of qsort leave nothing to chance. */
1603 /* The cost of spilling each hard reg. */
1604 static int spill_cost[FIRST_PSEUDO_REGISTER];
1606 /* When spilling multiple hard registers, we use SPILL_COST for the first
1607 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1608 only the first hard reg for a multi-reg pseudo. */
1609 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1611 /* Update the spill cost arrays, considering that pseudo REG is live. */
1614 count_pseudo (int reg)
1616 int freq = REG_FREQ (reg);
1617 int r = reg_renumber[reg];
1620 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1621 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1624 SET_REGNO_REG_SET (&pseudos_counted, reg);
1626 gcc_assert (r >= 0);
1628 spill_add_cost[r] += freq;
1630 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1632 spill_cost[r + nregs] += freq;
1635 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1636 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1639 order_regs_for_reload (struct insn_chain *chain)
1642 HARD_REG_SET used_by_pseudos;
1643 HARD_REG_SET used_by_pseudos2;
1644 reg_set_iterator rsi;
1646 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1648 memset (spill_cost, 0, sizeof spill_cost);
1649 memset (spill_add_cost, 0, sizeof spill_add_cost);
1651 /* Count number of uses of each hard reg by pseudo regs allocated to it
1652 and then order them by decreasing use. First exclude hard registers
1653 that are live in or across this insn. */
1655 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1656 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1657 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1658 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1660 /* Now find out which pseudos are allocated to it, and update
1662 CLEAR_REG_SET (&pseudos_counted);
1664 EXECUTE_IF_SET_IN_REG_SET
1665 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1669 EXECUTE_IF_SET_IN_REG_SET
1670 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1674 CLEAR_REG_SET (&pseudos_counted);
1677 /* Vector of reload-numbers showing the order in which the reloads should
1679 static short reload_order[MAX_RELOADS];
1681 /* This is used to keep track of the spill regs used in one insn. */
1682 static HARD_REG_SET used_spill_regs_local;
1684 /* We decided to spill hard register SPILLED, which has a size of
1685 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1686 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1687 update SPILL_COST/SPILL_ADD_COST. */
1690 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1692 int r = reg_renumber[reg];
1693 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1695 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1696 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1699 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1701 spill_add_cost[r] -= REG_FREQ (reg);
1703 spill_cost[r + nregs] -= REG_FREQ (reg);
1706 /* Find reload register to use for reload number ORDER. */
1709 find_reg (struct insn_chain *chain, int order)
1711 int rnum = reload_order[order];
1712 struct reload *rl = rld + rnum;
1713 int best_cost = INT_MAX;
1717 HARD_REG_SET not_usable;
1718 HARD_REG_SET used_by_other_reload;
1719 reg_set_iterator rsi;
1721 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1722 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1723 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1725 CLEAR_HARD_REG_SET (used_by_other_reload);
1726 for (k = 0; k < order; k++)
1728 int other = reload_order[k];
1730 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1731 for (j = 0; j < rld[other].nregs; j++)
1732 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1735 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1737 unsigned int regno = i;
1739 if (! TEST_HARD_REG_BIT (not_usable, regno)
1740 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1741 && HARD_REGNO_MODE_OK (regno, rl->mode))
1743 int this_cost = spill_cost[regno];
1745 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1747 for (j = 1; j < this_nregs; j++)
1749 this_cost += spill_add_cost[regno + j];
1750 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1751 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1756 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1758 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1760 if (this_cost < best_cost
1761 /* Among registers with equal cost, prefer caller-saved ones, or
1762 use REG_ALLOC_ORDER if it is defined. */
1763 || (this_cost == best_cost
1764 #ifdef REG_ALLOC_ORDER
1765 && (inv_reg_alloc_order[regno]
1766 < inv_reg_alloc_order[best_reg])
1768 && call_used_regs[regno]
1769 && ! call_used_regs[best_reg]
1774 best_cost = this_cost;
1782 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1784 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1785 rl->regno = best_reg;
1787 EXECUTE_IF_SET_IN_REG_SET
1788 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1790 count_spilled_pseudo (best_reg, rl->nregs, j);
1793 EXECUTE_IF_SET_IN_REG_SET
1794 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1796 count_spilled_pseudo (best_reg, rl->nregs, j);
1799 for (i = 0; i < rl->nregs; i++)
1801 gcc_assert (spill_cost[best_reg + i] == 0);
1802 gcc_assert (spill_add_cost[best_reg + i] == 0);
1803 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1808 /* Find more reload regs to satisfy the remaining need of an insn, which
1810 Do it by ascending class number, since otherwise a reg
1811 might be spilled for a big class and might fail to count
1812 for a smaller class even though it belongs to that class. */
1815 find_reload_regs (struct insn_chain *chain)
1819 /* In order to be certain of getting the registers we need,
1820 we must sort the reloads into order of increasing register class.
1821 Then our grabbing of reload registers will parallel the process
1822 that provided the reload registers. */
1823 for (i = 0; i < chain->n_reloads; i++)
1825 /* Show whether this reload already has a hard reg. */
1826 if (chain->rld[i].reg_rtx)
1828 int regno = REGNO (chain->rld[i].reg_rtx);
1829 chain->rld[i].regno = regno;
1831 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1834 chain->rld[i].regno = -1;
1835 reload_order[i] = i;
1838 n_reloads = chain->n_reloads;
1839 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1841 CLEAR_HARD_REG_SET (used_spill_regs_local);
1844 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1846 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1848 /* Compute the order of preference for hard registers to spill. */
1850 order_regs_for_reload (chain);
1852 for (i = 0; i < n_reloads; i++)
1854 int r = reload_order[i];
1856 /* Ignore reloads that got marked inoperative. */
1857 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1858 && ! rld[r].optional
1859 && rld[r].regno == -1)
1860 if (! find_reg (chain, i))
1863 fprintf(dump_file, "reload failure for reload %d\n", r);
1864 spill_failure (chain->insn, rld[r].class);
1870 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1871 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1873 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1877 select_reload_regs (void)
1879 struct insn_chain *chain;
1881 /* Try to satisfy the needs for each insn. */
1882 for (chain = insns_need_reload; chain != 0;
1883 chain = chain->next_need_reload)
1884 find_reload_regs (chain);
1887 /* Delete all insns that were inserted by emit_caller_save_insns during
1890 delete_caller_save_insns (void)
1892 struct insn_chain *c = reload_insn_chain;
1896 while (c != 0 && c->is_caller_save_insn)
1898 struct insn_chain *next = c->next;
1901 if (c == reload_insn_chain)
1902 reload_insn_chain = next;
1906 next->prev = c->prev;
1908 c->prev->next = next;
1909 c->next = unused_insn_chains;
1910 unused_insn_chains = c;
1918 /* Handle the failure to find a register to spill.
1919 INSN should be one of the insns which needed this particular spill reg. */
1922 spill_failure (rtx insn, enum reg_class class)
1924 if (asm_noperands (PATTERN (insn)) >= 0)
1925 error_for_asm (insn, "can't find a register in class %qs while "
1926 "reloading %<asm%>",
1927 reg_class_names[class]);
1930 error ("unable to find a register to spill in class %qs",
1931 reg_class_names[class]);
1935 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
1936 debug_reload_to_stream (dump_file);
1938 fatal_insn ("this is the insn:", insn);
1942 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1943 data that is dead in INSN. */
1946 delete_dead_insn (rtx insn)
1948 rtx prev = prev_real_insn (insn);
1951 /* If the previous insn sets a register that dies in our insn, delete it
1953 if (prev && GET_CODE (PATTERN (prev)) == SET
1954 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
1955 && reg_mentioned_p (prev_dest, PATTERN (insn))
1956 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1957 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1958 delete_dead_insn (prev);
1960 SET_INSN_DELETED (insn);
1963 /* Modify the home of pseudo-reg I.
1964 The new home is present in reg_renumber[I].
1966 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1967 or it may be -1, meaning there is none or it is not relevant.
1968 This is used so that all pseudos spilled from a given hard reg
1969 can share one stack slot. */
1972 alter_reg (int i, int from_reg)
1974 /* When outputting an inline function, this can happen
1975 for a reg that isn't actually used. */
1976 if (regno_reg_rtx[i] == 0)
1979 /* If the reg got changed to a MEM at rtl-generation time,
1981 if (!REG_P (regno_reg_rtx[i]))
1984 /* Modify the reg-rtx to contain the new hard reg
1985 number or else to contain its pseudo reg number. */
1986 REGNO (regno_reg_rtx[i])
1987 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1989 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1990 allocate a stack slot for it. */
1992 if (reg_renumber[i] < 0
1993 && REG_N_REFS (i) > 0
1994 && reg_equiv_constant[i] == 0
1995 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
1996 && reg_equiv_memory_loc[i] == 0)
1999 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2000 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2003 /* Each pseudo reg has an inherent size which comes from its own mode,
2004 and a total size which provides room for paradoxical subregs
2005 which refer to the pseudo reg in wider modes.
2007 We can use a slot already allocated if it provides both
2008 enough inherent space and enough total space.
2009 Otherwise, we allocate a new slot, making sure that it has no less
2010 inherent space, and no less total space, then the previous slot. */
2013 /* No known place to spill from => no slot to reuse. */
2014 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
2015 inherent_size == total_size ? 0 : -1);
2016 if (BYTES_BIG_ENDIAN)
2017 /* Cancel the big-endian correction done in assign_stack_local.
2018 Get the address of the beginning of the slot.
2019 This is so we can do a big-endian correction unconditionally
2021 adjust = inherent_size - total_size;
2023 /* Nothing can alias this slot except this pseudo. */
2024 set_mem_alias_set (x, new_alias_set ());
2027 /* Reuse a stack slot if possible. */
2028 else if (spill_stack_slot[from_reg] != 0
2029 && spill_stack_slot_width[from_reg] >= total_size
2030 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2032 x = spill_stack_slot[from_reg];
2034 /* Allocate a bigger slot. */
2037 /* Compute maximum size needed, both for inherent size
2038 and for total size. */
2039 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2042 if (spill_stack_slot[from_reg])
2044 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2046 mode = GET_MODE (spill_stack_slot[from_reg]);
2047 if (spill_stack_slot_width[from_reg] > total_size)
2048 total_size = spill_stack_slot_width[from_reg];
2051 /* Make a slot with that size. */
2052 x = assign_stack_local (mode, total_size,
2053 inherent_size == total_size ? 0 : -1);
2056 /* All pseudos mapped to this slot can alias each other. */
2057 if (spill_stack_slot[from_reg])
2058 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2060 set_mem_alias_set (x, new_alias_set ());
2062 if (BYTES_BIG_ENDIAN)
2064 /* Cancel the big-endian correction done in assign_stack_local.
2065 Get the address of the beginning of the slot.
2066 This is so we can do a big-endian correction unconditionally
2068 adjust = GET_MODE_SIZE (mode) - total_size;
2071 = adjust_address_nv (x, mode_for_size (total_size
2077 spill_stack_slot[from_reg] = stack_slot;
2078 spill_stack_slot_width[from_reg] = total_size;
2081 /* On a big endian machine, the "address" of the slot
2082 is the address of the low part that fits its inherent mode. */
2083 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2084 adjust += (total_size - inherent_size);
2086 /* If we have any adjustment to make, or if the stack slot is the
2087 wrong mode, make a new stack slot. */
2088 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2090 /* If we have a decl for the original register, set it for the
2091 memory. If this is a shared MEM, make a copy. */
2092 if (REG_EXPR (regno_reg_rtx[i])
2093 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2095 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2097 /* We can do this only for the DECLs home pseudo, not for
2098 any copies of it, since otherwise when the stack slot
2099 is reused, nonoverlapping_memrefs_p might think they
2101 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2103 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2106 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2110 /* Save the stack slot for later. */
2111 reg_equiv_memory_loc[i] = x;
2115 /* Mark the slots in regs_ever_live for the hard regs
2116 used by pseudo-reg number REGNO. */
2119 mark_home_live (int regno)
2123 i = reg_renumber[regno];
2126 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2128 regs_ever_live[i++] = 1;
2131 /* This function handles the tracking of elimination offsets around branches.
2133 X is a piece of RTL being scanned.
2135 INSN is the insn that it came from, if any.
2137 INITIAL_P is nonzero if we are to set the offset to be the initial
2138 offset and zero if we are setting the offset of the label to be the
2142 set_label_offsets (rtx x, rtx insn, int initial_p)
2144 enum rtx_code code = GET_CODE (x);
2147 struct elim_table *p;
2152 if (LABEL_REF_NONLOCAL_P (x))
2157 /* ... fall through ... */
2160 /* If we know nothing about this label, set the desired offsets. Note
2161 that this sets the offset at a label to be the offset before a label
2162 if we don't know anything about the label. This is not correct for
2163 the label after a BARRIER, but is the best guess we can make. If
2164 we guessed wrong, we will suppress an elimination that might have
2165 been possible had we been able to guess correctly. */
2167 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2169 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2170 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2171 = (initial_p ? reg_eliminate[i].initial_offset
2172 : reg_eliminate[i].offset);
2173 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2176 /* Otherwise, if this is the definition of a label and it is
2177 preceded by a BARRIER, set our offsets to the known offset of
2181 && (tem = prev_nonnote_insn (insn)) != 0
2183 set_offsets_for_label (insn);
2185 /* If neither of the above cases is true, compare each offset
2186 with those previously recorded and suppress any eliminations
2187 where the offsets disagree. */
2189 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2190 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2191 != (initial_p ? reg_eliminate[i].initial_offset
2192 : reg_eliminate[i].offset))
2193 reg_eliminate[i].can_eliminate = 0;
2198 set_label_offsets (PATTERN (insn), insn, initial_p);
2200 /* ... fall through ... */
2204 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2205 and hence must have all eliminations at their initial offsets. */
2206 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2207 if (REG_NOTE_KIND (tem) == REG_LABEL)
2208 set_label_offsets (XEXP (tem, 0), insn, 1);
2214 /* Each of the labels in the parallel or address vector must be
2215 at their initial offsets. We want the first field for PARALLEL
2216 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2218 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2219 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2224 /* We only care about setting PC. If the source is not RETURN,
2225 IF_THEN_ELSE, or a label, disable any eliminations not at
2226 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2227 isn't one of those possibilities. For branches to a label,
2228 call ourselves recursively.
2230 Note that this can disable elimination unnecessarily when we have
2231 a non-local goto since it will look like a non-constant jump to
2232 someplace in the current function. This isn't a significant
2233 problem since such jumps will normally be when all elimination
2234 pairs are back to their initial offsets. */
2236 if (SET_DEST (x) != pc_rtx)
2239 switch (GET_CODE (SET_SRC (x)))
2246 set_label_offsets (SET_SRC (x), insn, initial_p);
2250 tem = XEXP (SET_SRC (x), 1);
2251 if (GET_CODE (tem) == LABEL_REF)
2252 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2253 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2256 tem = XEXP (SET_SRC (x), 2);
2257 if (GET_CODE (tem) == LABEL_REF)
2258 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2259 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2267 /* If we reach here, all eliminations must be at their initial
2268 offset because we are doing a jump to a variable address. */
2269 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2270 if (p->offset != p->initial_offset)
2271 p->can_eliminate = 0;
2279 /* Scan X and replace any eliminable registers (such as fp) with a
2280 replacement (such as sp), plus an offset.
2282 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2283 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2284 MEM, we are allowed to replace a sum of a register and the constant zero
2285 with the register, which we cannot do outside a MEM. In addition, we need
2286 to record the fact that a register is referenced outside a MEM.
2288 If INSN is an insn, it is the insn containing X. If we replace a REG
2289 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2290 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2291 the REG is being modified.
2293 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2294 That's used when we eliminate in expressions stored in notes.
2295 This means, do not set ref_outside_mem even if the reference
2298 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2299 replacements done assuming all offsets are at their initial values. If
2300 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2301 encounter, return the actual location so that find_reloads will do
2302 the proper thing. */
2305 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2306 bool may_use_invariant)
2308 enum rtx_code code = GET_CODE (x);
2309 struct elim_table *ep;
2316 if (! current_function_decl)
2338 /* First handle the case where we encounter a bare register that
2339 is eliminable. Replace it with a PLUS. */
2340 if (regno < FIRST_PSEUDO_REGISTER)
2342 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2344 if (ep->from_rtx == x && ep->can_eliminate)
2345 return plus_constant (ep->to_rtx, ep->previous_offset);
2348 else if (reg_renumber && reg_renumber[regno] < 0
2349 && reg_equiv_invariant && reg_equiv_invariant[regno])
2351 if (may_use_invariant)
2352 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2353 mem_mode, insn, true);
2354 /* There exists at least one use of REGNO that cannot be
2355 eliminated. Prevent the defining insn from being deleted. */
2356 reg_equiv_init[regno] = NULL_RTX;
2357 alter_reg (regno, -1);
2361 /* You might think handling MINUS in a manner similar to PLUS is a
2362 good idea. It is not. It has been tried multiple times and every
2363 time the change has had to have been reverted.
2365 Other parts of reload know a PLUS is special (gen_reload for example)
2366 and require special code to handle code a reloaded PLUS operand.
2368 Also consider backends where the flags register is clobbered by a
2369 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2370 lea instruction comes to mind). If we try to reload a MINUS, we
2371 may kill the flags register that was holding a useful value.
2373 So, please before trying to handle MINUS, consider reload as a
2374 whole instead of this little section as well as the backend issues. */
2376 /* If this is the sum of an eliminable register and a constant, rework
2378 if (REG_P (XEXP (x, 0))
2379 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2380 && CONSTANT_P (XEXP (x, 1)))
2382 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2384 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2386 /* The only time we want to replace a PLUS with a REG (this
2387 occurs when the constant operand of the PLUS is the negative
2388 of the offset) is when we are inside a MEM. We won't want
2389 to do so at other times because that would change the
2390 structure of the insn in a way that reload can't handle.
2391 We special-case the commonest situation in
2392 eliminate_regs_in_insn, so just replace a PLUS with a
2393 PLUS here, unless inside a MEM. */
2394 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2395 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2398 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2399 plus_constant (XEXP (x, 1),
2400 ep->previous_offset));
2403 /* If the register is not eliminable, we are done since the other
2404 operand is a constant. */
2408 /* If this is part of an address, we want to bring any constant to the
2409 outermost PLUS. We will do this by doing register replacement in
2410 our operands and seeing if a constant shows up in one of them.
2412 Note that there is no risk of modifying the structure of the insn,
2413 since we only get called for its operands, thus we are either
2414 modifying the address inside a MEM, or something like an address
2415 operand of a load-address insn. */
2418 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2419 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2421 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2423 /* If one side is a PLUS and the other side is a pseudo that
2424 didn't get a hard register but has a reg_equiv_constant,
2425 we must replace the constant here since it may no longer
2426 be in the position of any operand. */
2427 if (GET_CODE (new0) == PLUS && REG_P (new1)
2428 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2429 && reg_renumber[REGNO (new1)] < 0
2430 && reg_equiv_constant != 0
2431 && reg_equiv_constant[REGNO (new1)] != 0)
2432 new1 = reg_equiv_constant[REGNO (new1)];
2433 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2434 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2435 && reg_renumber[REGNO (new0)] < 0
2436 && reg_equiv_constant[REGNO (new0)] != 0)
2437 new0 = reg_equiv_constant[REGNO (new0)];
2439 new = form_sum (new0, new1);
2441 /* As above, if we are not inside a MEM we do not want to
2442 turn a PLUS into something else. We might try to do so here
2443 for an addition of 0 if we aren't optimizing. */
2444 if (! mem_mode && GET_CODE (new) != PLUS)
2445 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2453 /* If this is the product of an eliminable register and a
2454 constant, apply the distribute law and move the constant out
2455 so that we have (plus (mult ..) ..). This is needed in order
2456 to keep load-address insns valid. This case is pathological.
2457 We ignore the possibility of overflow here. */
2458 if (REG_P (XEXP (x, 0))
2459 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2460 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2461 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2463 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2466 /* Refs inside notes don't count for this purpose. */
2467 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2468 || GET_CODE (insn) == INSN_LIST)))
2469 ep->ref_outside_mem = 1;
2472 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2473 ep->previous_offset * INTVAL (XEXP (x, 1)));
2476 /* ... fall through ... */
2480 /* See comments before PLUS about handling MINUS. */
2482 case DIV: case UDIV:
2483 case MOD: case UMOD:
2484 case AND: case IOR: case XOR:
2485 case ROTATERT: case ROTATE:
2486 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2488 case GE: case GT: case GEU: case GTU:
2489 case LE: case LT: case LEU: case LTU:
2491 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2492 rtx new1 = XEXP (x, 1)
2493 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2495 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2496 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2501 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2504 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2505 if (new != XEXP (x, 0))
2507 /* If this is a REG_DEAD note, it is not valid anymore.
2508 Using the eliminated version could result in creating a
2509 REG_DEAD note for the stack or frame pointer. */
2510 if (GET_MODE (x) == REG_DEAD)
2512 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2515 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2519 /* ... fall through ... */
2522 /* Now do eliminations in the rest of the chain. If this was
2523 an EXPR_LIST, this might result in allocating more memory than is
2524 strictly needed, but it simplifies the code. */
2527 new = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2528 if (new != XEXP (x, 1))
2530 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2538 case STRICT_LOW_PART:
2540 case SIGN_EXTEND: case ZERO_EXTEND:
2541 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2542 case FLOAT: case FIX:
2543 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2551 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2552 if (new != XEXP (x, 0))
2553 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2557 /* Similar to above processing, but preserve SUBREG_BYTE.
2558 Convert (subreg (mem)) to (mem) if not paradoxical.
2559 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2560 pseudo didn't get a hard reg, we must replace this with the
2561 eliminated version of the memory location because push_reload
2562 may do the replacement in certain circumstances. */
2563 if (REG_P (SUBREG_REG (x))
2564 && (GET_MODE_SIZE (GET_MODE (x))
2565 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2566 && reg_equiv_memory_loc != 0
2567 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2569 new = SUBREG_REG (x);
2572 new = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2574 if (new != SUBREG_REG (x))
2576 int x_size = GET_MODE_SIZE (GET_MODE (x));
2577 int new_size = GET_MODE_SIZE (GET_MODE (new));
2580 && ((x_size < new_size
2581 #ifdef WORD_REGISTER_OPERATIONS
2582 /* On these machines, combine can create rtl of the form
2583 (set (subreg:m1 (reg:m2 R) 0) ...)
2584 where m1 < m2, and expects something interesting to
2585 happen to the entire word. Moreover, it will use the
2586 (reg:m2 R) later, expecting all bits to be preserved.
2587 So if the number of words is the same, preserve the
2588 subreg so that push_reload can see it. */
2589 && ! ((x_size - 1) / UNITS_PER_WORD
2590 == (new_size -1 ) / UNITS_PER_WORD)
2593 || x_size == new_size)
2595 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2597 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2603 /* Our only special processing is to pass the mode of the MEM to our
2604 recursive call and copy the flags. While we are here, handle this
2605 case more efficiently. */
2607 replace_equiv_address_nv (x,
2608 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2612 /* Handle insn_list USE that a call to a pure function may generate. */
2613 new = eliminate_regs_1 (XEXP (x, 0), 0, insn, false);
2614 if (new != XEXP (x, 0))
2615 return gen_rtx_USE (GET_MODE (x), new);
2627 /* Process each of our operands recursively. If any have changed, make a
2629 fmt = GET_RTX_FORMAT (code);
2630 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2634 new = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2635 if (new != XEXP (x, i) && ! copied)
2637 x = shallow_copy_rtx (x);
2642 else if (*fmt == 'E')
2645 for (j = 0; j < XVECLEN (x, i); j++)
2647 new = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2648 if (new != XVECEXP (x, i, j) && ! copied_vec)
2650 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2654 x = shallow_copy_rtx (x);
2657 XVEC (x, i) = new_v;
2660 XVECEXP (x, i, j) = new;
2669 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2671 return eliminate_regs_1 (x, mem_mode, insn, false);
2674 /* Scan rtx X for modifications of elimination target registers. Update
2675 the table of eliminables to reflect the changed state. MEM_MODE is
2676 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2679 elimination_effects (rtx x, enum machine_mode mem_mode)
2681 enum rtx_code code = GET_CODE (x);
2682 struct elim_table *ep;
2706 /* First handle the case where we encounter a bare register that
2707 is eliminable. Replace it with a PLUS. */
2708 if (regno < FIRST_PSEUDO_REGISTER)
2710 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2712 if (ep->from_rtx == x && ep->can_eliminate)
2715 ep->ref_outside_mem = 1;
2720 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2721 && reg_equiv_constant[regno]
2722 && ! function_invariant_p (reg_equiv_constant[regno]))
2723 elimination_effects (reg_equiv_constant[regno], mem_mode);
2732 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2733 if (ep->to_rtx == XEXP (x, 0))
2735 int size = GET_MODE_SIZE (mem_mode);
2737 /* If more bytes than MEM_MODE are pushed, account for them. */
2738 #ifdef PUSH_ROUNDING
2739 if (ep->to_rtx == stack_pointer_rtx)
2740 size = PUSH_ROUNDING (size);
2742 if (code == PRE_DEC || code == POST_DEC)
2744 else if (code == PRE_INC || code == POST_INC)
2746 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2747 && GET_CODE (XEXP (x, 1)) == PLUS
2748 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2749 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2750 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2753 /* These two aren't unary operators. */
2754 if (code == POST_MODIFY || code == PRE_MODIFY)
2757 /* Fall through to generic unary operation case. */
2758 case STRICT_LOW_PART:
2760 case SIGN_EXTEND: case ZERO_EXTEND:
2761 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2762 case FLOAT: case FIX:
2763 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2771 elimination_effects (XEXP (x, 0), mem_mode);
2775 if (REG_P (SUBREG_REG (x))
2776 && (GET_MODE_SIZE (GET_MODE (x))
2777 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2778 && reg_equiv_memory_loc != 0
2779 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2782 elimination_effects (SUBREG_REG (x), mem_mode);
2786 /* If using a register that is the source of an eliminate we still
2787 think can be performed, note it cannot be performed since we don't
2788 know how this register is used. */
2789 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2790 if (ep->from_rtx == XEXP (x, 0))
2791 ep->can_eliminate = 0;
2793 elimination_effects (XEXP (x, 0), mem_mode);
2797 /* If clobbering a register that is the replacement register for an
2798 elimination we still think can be performed, note that it cannot
2799 be performed. Otherwise, we need not be concerned about it. */
2800 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2801 if (ep->to_rtx == XEXP (x, 0))
2802 ep->can_eliminate = 0;
2804 elimination_effects (XEXP (x, 0), mem_mode);
2808 /* Check for setting a register that we know about. */
2809 if (REG_P (SET_DEST (x)))
2811 /* See if this is setting the replacement register for an
2814 If DEST is the hard frame pointer, we do nothing because we
2815 assume that all assignments to the frame pointer are for
2816 non-local gotos and are being done at a time when they are valid
2817 and do not disturb anything else. Some machines want to
2818 eliminate a fake argument pointer (or even a fake frame pointer)
2819 with either the real frame or the stack pointer. Assignments to
2820 the hard frame pointer must not prevent this elimination. */
2822 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2824 if (ep->to_rtx == SET_DEST (x)
2825 && SET_DEST (x) != hard_frame_pointer_rtx)
2827 /* If it is being incremented, adjust the offset. Otherwise,
2828 this elimination can't be done. */
2829 rtx src = SET_SRC (x);
2831 if (GET_CODE (src) == PLUS
2832 && XEXP (src, 0) == SET_DEST (x)
2833 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2834 ep->offset -= INTVAL (XEXP (src, 1));
2836 ep->can_eliminate = 0;
2840 elimination_effects (SET_DEST (x), 0);
2841 elimination_effects (SET_SRC (x), 0);
2845 /* Our only special processing is to pass the mode of the MEM to our
2847 elimination_effects (XEXP (x, 0), GET_MODE (x));
2854 fmt = GET_RTX_FORMAT (code);
2855 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2858 elimination_effects (XEXP (x, i), mem_mode);
2859 else if (*fmt == 'E')
2860 for (j = 0; j < XVECLEN (x, i); j++)
2861 elimination_effects (XVECEXP (x, i, j), mem_mode);
2865 /* Descend through rtx X and verify that no references to eliminable registers
2866 remain. If any do remain, mark the involved register as not
2870 check_eliminable_occurrences (rtx x)
2879 code = GET_CODE (x);
2881 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2883 struct elim_table *ep;
2885 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2886 if (ep->from_rtx == x)
2887 ep->can_eliminate = 0;
2891 fmt = GET_RTX_FORMAT (code);
2892 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2895 check_eliminable_occurrences (XEXP (x, i));
2896 else if (*fmt == 'E')
2899 for (j = 0; j < XVECLEN (x, i); j++)
2900 check_eliminable_occurrences (XVECEXP (x, i, j));
2905 /* Scan INSN and eliminate all eliminable registers in it.
2907 If REPLACE is nonzero, do the replacement destructively. Also
2908 delete the insn as dead it if it is setting an eliminable register.
2910 If REPLACE is zero, do all our allocations in reload_obstack.
2912 If no eliminations were done and this insn doesn't require any elimination
2913 processing (these are not identical conditions: it might be updating sp,
2914 but not referencing fp; this needs to be seen during reload_as_needed so
2915 that the offset between fp and sp can be taken into consideration), zero
2916 is returned. Otherwise, 1 is returned. */
2919 eliminate_regs_in_insn (rtx insn, int replace)
2921 int icode = recog_memoized (insn);
2922 rtx old_body = PATTERN (insn);
2923 int insn_is_asm = asm_noperands (old_body) >= 0;
2924 rtx old_set = single_set (insn);
2928 rtx substed_operand[MAX_RECOG_OPERANDS];
2929 rtx orig_operand[MAX_RECOG_OPERANDS];
2930 struct elim_table *ep;
2931 rtx plus_src, plus_cst_src;
2933 if (! insn_is_asm && icode < 0)
2935 gcc_assert (GET_CODE (PATTERN (insn)) == USE
2936 || GET_CODE (PATTERN (insn)) == CLOBBER
2937 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2938 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2939 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
2943 if (old_set != 0 && REG_P (SET_DEST (old_set))
2944 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2946 /* Check for setting an eliminable register. */
2947 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2948 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2950 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2951 /* If this is setting the frame pointer register to the
2952 hardware frame pointer register and this is an elimination
2953 that will be done (tested above), this insn is really
2954 adjusting the frame pointer downward to compensate for
2955 the adjustment done before a nonlocal goto. */
2956 if (ep->from == FRAME_POINTER_REGNUM
2957 && ep->to == HARD_FRAME_POINTER_REGNUM)
2959 rtx base = SET_SRC (old_set);
2960 rtx base_insn = insn;
2961 HOST_WIDE_INT offset = 0;
2963 while (base != ep->to_rtx)
2965 rtx prev_insn, prev_set;
2967 if (GET_CODE (base) == PLUS
2968 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2970 offset += INTVAL (XEXP (base, 1));
2971 base = XEXP (base, 0);
2973 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2974 && (prev_set = single_set (prev_insn)) != 0
2975 && rtx_equal_p (SET_DEST (prev_set), base))
2977 base = SET_SRC (prev_set);
2978 base_insn = prev_insn;
2984 if (base == ep->to_rtx)
2987 = plus_constant (ep->to_rtx, offset - ep->offset);
2989 new_body = old_body;
2992 new_body = copy_insn (old_body);
2993 if (REG_NOTES (insn))
2994 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2996 PATTERN (insn) = new_body;
2997 old_set = single_set (insn);
2999 /* First see if this insn remains valid when we
3000 make the change. If not, keep the INSN_CODE
3001 the same and let reload fit it up. */
3002 validate_change (insn, &SET_SRC (old_set), src, 1);
3003 validate_change (insn, &SET_DEST (old_set),
3005 if (! apply_change_group ())
3007 SET_SRC (old_set) = src;
3008 SET_DEST (old_set) = ep->to_rtx;
3017 /* In this case this insn isn't serving a useful purpose. We
3018 will delete it in reload_as_needed once we know that this
3019 elimination is, in fact, being done.
3021 If REPLACE isn't set, we can't delete this insn, but needn't
3022 process it since it won't be used unless something changes. */
3025 delete_dead_insn (insn);
3033 /* We allow one special case which happens to work on all machines we
3034 currently support: a single set with the source or a REG_EQUAL
3035 note being a PLUS of an eliminable register and a constant. */
3036 plus_src = plus_cst_src = 0;
3037 if (old_set && REG_P (SET_DEST (old_set)))
3039 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3040 plus_src = SET_SRC (old_set);
3041 /* First see if the source is of the form (plus (...) CST). */
3043 && GET_CODE (XEXP (plus_src, 1)) == CONST_INT)
3044 plus_cst_src = plus_src;
3045 else if (REG_P (SET_SRC (old_set))
3048 /* Otherwise, see if we have a REG_EQUAL note of the form
3049 (plus (...) CST). */
3051 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3053 if (REG_NOTE_KIND (links) == REG_EQUAL
3054 && GET_CODE (XEXP (links, 0)) == PLUS
3055 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT)
3057 plus_cst_src = XEXP (links, 0);
3063 /* Check that the first operand of the PLUS is a hard reg or
3064 the lowpart subreg of one. */
3067 rtx reg = XEXP (plus_cst_src, 0);
3068 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3069 reg = SUBREG_REG (reg);
3071 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3077 rtx reg = XEXP (plus_cst_src, 0);
3078 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3080 if (GET_CODE (reg) == SUBREG)
3081 reg = SUBREG_REG (reg);
3083 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3084 if (ep->from_rtx == reg && ep->can_eliminate)
3086 rtx to_rtx = ep->to_rtx;
3087 offset += ep->offset;
3089 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3090 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3095 /* We assume here that if we need a PARALLEL with
3096 CLOBBERs for this assignment, we can do with the
3097 MATCH_SCRATCHes that add_clobbers allocates.
3098 There's not much we can do if that doesn't work. */
3099 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3103 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3106 rtvec vec = rtvec_alloc (num_clobbers + 1);
3108 vec->elem[0] = PATTERN (insn);
3109 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3110 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3112 gcc_assert (INSN_CODE (insn) >= 0);
3114 /* If we have a nonzero offset, and the source is already
3115 a simple REG, the following transformation would
3116 increase the cost of the insn by replacing a simple REG
3117 with (plus (reg sp) CST). So try only when we already
3118 had a PLUS before. */
3121 new_body = old_body;
3124 new_body = copy_insn (old_body);
3125 if (REG_NOTES (insn))
3126 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3128 PATTERN (insn) = new_body;
3129 old_set = single_set (insn);
3131 XEXP (SET_SRC (old_set), 0) = to_rtx;
3132 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3138 /* This can't have an effect on elimination offsets, so skip right
3144 /* Determine the effects of this insn on elimination offsets. */
3145 elimination_effects (old_body, 0);
3147 /* Eliminate all eliminable registers occurring in operands that
3148 can be handled by reload. */
3149 extract_insn (insn);
3150 for (i = 0; i < recog_data.n_operands; i++)
3152 orig_operand[i] = recog_data.operand[i];
3153 substed_operand[i] = recog_data.operand[i];
3155 /* For an asm statement, every operand is eliminable. */
3156 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3158 bool is_set_src, in_plus;
3160 /* Check for setting a register that we know about. */
3161 if (recog_data.operand_type[i] != OP_IN
3162 && REG_P (orig_operand[i]))
3164 /* If we are assigning to a register that can be eliminated, it
3165 must be as part of a PARALLEL, since the code above handles
3166 single SETs. We must indicate that we can no longer
3167 eliminate this reg. */
3168 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3170 if (ep->from_rtx == orig_operand[i])
3171 ep->can_eliminate = 0;
3174 /* Companion to the above plus substitution, we can allow
3175 invariants as the source of a plain move. */
3177 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3181 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3182 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3186 = eliminate_regs_1 (recog_data.operand[i], 0,
3187 replace ? insn : NULL_RTX,
3188 is_set_src || in_plus);
3189 if (substed_operand[i] != orig_operand[i])
3191 /* Terminate the search in check_eliminable_occurrences at
3193 *recog_data.operand_loc[i] = 0;
3195 /* If an output operand changed from a REG to a MEM and INSN is an
3196 insn, write a CLOBBER insn. */
3197 if (recog_data.operand_type[i] != OP_IN
3198 && REG_P (orig_operand[i])
3199 && MEM_P (substed_operand[i])
3201 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3206 for (i = 0; i < recog_data.n_dups; i++)
3207 *recog_data.dup_loc[i]
3208 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3210 /* If any eliminable remain, they aren't eliminable anymore. */
3211 check_eliminable_occurrences (old_body);
3213 /* Substitute the operands; the new values are in the substed_operand
3215 for (i = 0; i < recog_data.n_operands; i++)
3216 *recog_data.operand_loc[i] = substed_operand[i];
3217 for (i = 0; i < recog_data.n_dups; i++)
3218 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3220 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3221 re-recognize the insn. We do this in case we had a simple addition
3222 but now can do this as a load-address. This saves an insn in this
3224 If re-recognition fails, the old insn code number will still be used,
3225 and some register operands may have changed into PLUS expressions.
3226 These will be handled by find_reloads by loading them into a register
3231 /* If we aren't replacing things permanently and we changed something,
3232 make another copy to ensure that all the RTL is new. Otherwise
3233 things can go wrong if find_reload swaps commutative operands
3234 and one is inside RTL that has been copied while the other is not. */
3235 new_body = old_body;
3238 new_body = copy_insn (old_body);
3239 if (REG_NOTES (insn))
3240 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3242 PATTERN (insn) = new_body;
3244 /* If we had a move insn but now we don't, rerecognize it. This will
3245 cause spurious re-recognition if the old move had a PARALLEL since
3246 the new one still will, but we can't call single_set without
3247 having put NEW_BODY into the insn and the re-recognition won't
3248 hurt in this rare case. */
3249 /* ??? Why this huge if statement - why don't we just rerecognize the
3253 && ((REG_P (SET_SRC (old_set))
3254 && (GET_CODE (new_body) != SET
3255 || !REG_P (SET_SRC (new_body))))
3256 /* If this was a load from or store to memory, compare
3257 the MEM in recog_data.operand to the one in the insn.
3258 If they are not equal, then rerecognize the insn. */
3260 && ((MEM_P (SET_SRC (old_set))
3261 && SET_SRC (old_set) != recog_data.operand[1])
3262 || (MEM_P (SET_DEST (old_set))
3263 && SET_DEST (old_set) != recog_data.operand[0])))
3264 /* If this was an add insn before, rerecognize. */
3265 || GET_CODE (SET_SRC (old_set)) == PLUS))
3267 int new_icode = recog (PATTERN (insn), insn, 0);
3269 INSN_CODE (insn) = new_icode;
3273 /* Restore the old body. If there were any changes to it, we made a copy
3274 of it while the changes were still in place, so we'll correctly return
3275 a modified insn below. */
3278 /* Restore the old body. */
3279 for (i = 0; i < recog_data.n_operands; i++)
3280 *recog_data.operand_loc[i] = orig_operand[i];
3281 for (i = 0; i < recog_data.n_dups; i++)
3282 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3285 /* Update all elimination pairs to reflect the status after the current
3286 insn. The changes we make were determined by the earlier call to
3287 elimination_effects.
3289 We also detect cases where register elimination cannot be done,
3290 namely, if a register would be both changed and referenced outside a MEM
3291 in the resulting insn since such an insn is often undefined and, even if
3292 not, we cannot know what meaning will be given to it. Note that it is
3293 valid to have a register used in an address in an insn that changes it
3294 (presumably with a pre- or post-increment or decrement).
3296 If anything changes, return nonzero. */
3298 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3300 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3301 ep->can_eliminate = 0;
3303 ep->ref_outside_mem = 0;
3305 if (ep->previous_offset != ep->offset)
3310 /* If we changed something, perform elimination in REG_NOTES. This is
3311 needed even when REPLACE is zero because a REG_DEAD note might refer
3312 to a register that we eliminate and could cause a different number
3313 of spill registers to be needed in the final reload pass than in
3315 if (val && REG_NOTES (insn) != 0)
3317 = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true);
3322 /* Loop through all elimination pairs.
3323 Recalculate the number not at initial offset.
3325 Compute the maximum offset (minimum offset if the stack does not
3326 grow downward) for each elimination pair. */
3329 update_eliminable_offsets (void)
3331 struct elim_table *ep;
3333 num_not_at_initial_offset = 0;
3334 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3336 ep->previous_offset = ep->offset;
3337 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3338 num_not_at_initial_offset++;
3342 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3343 replacement we currently believe is valid, mark it as not eliminable if X
3344 modifies DEST in any way other than by adding a constant integer to it.
3346 If DEST is the frame pointer, we do nothing because we assume that
3347 all assignments to the hard frame pointer are nonlocal gotos and are being
3348 done at a time when they are valid and do not disturb anything else.
3349 Some machines want to eliminate a fake argument pointer with either the
3350 frame or stack pointer. Assignments to the hard frame pointer must not
3351 prevent this elimination.
3353 Called via note_stores from reload before starting its passes to scan
3354 the insns of the function. */
3357 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3361 /* A SUBREG of a hard register here is just changing its mode. We should
3362 not see a SUBREG of an eliminable hard register, but check just in
3364 if (GET_CODE (dest) == SUBREG)
3365 dest = SUBREG_REG (dest);
3367 if (dest == hard_frame_pointer_rtx)
3370 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3371 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3372 && (GET_CODE (x) != SET
3373 || GET_CODE (SET_SRC (x)) != PLUS
3374 || XEXP (SET_SRC (x), 0) != dest
3375 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3377 reg_eliminate[i].can_eliminate_previous
3378 = reg_eliminate[i].can_eliminate = 0;
3383 /* Verify that the initial elimination offsets did not change since the
3384 last call to set_initial_elim_offsets. This is used to catch cases
3385 where something illegal happened during reload_as_needed that could
3386 cause incorrect code to be generated if we did not check for it. */
3389 verify_initial_elim_offsets (void)
3393 if (!num_eliminable)
3396 #ifdef ELIMINABLE_REGS
3398 struct elim_table *ep;
3400 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3402 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3403 if (t != ep->initial_offset)
3408 INITIAL_FRAME_POINTER_OFFSET (t);
3409 if (t != reg_eliminate[0].initial_offset)
3416 /* Reset all offsets on eliminable registers to their initial values. */
3419 set_initial_elim_offsets (void)
3421 struct elim_table *ep = reg_eliminate;
3423 #ifdef ELIMINABLE_REGS
3424 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3426 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3427 ep->previous_offset = ep->offset = ep->initial_offset;
3430 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3431 ep->previous_offset = ep->offset = ep->initial_offset;
3434 num_not_at_initial_offset = 0;
3437 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3440 set_initial_eh_label_offset (rtx label)
3442 set_label_offsets (label, NULL_RTX, 1);
3445 /* Initialize the known label offsets.
3446 Set a known offset for each forced label to be at the initial offset
3447 of each elimination. We do this because we assume that all
3448 computed jumps occur from a location where each elimination is
3449 at its initial offset.
3450 For all other labels, show that we don't know the offsets. */
3453 set_initial_label_offsets (void)
3456 memset (offsets_known_at, 0, num_labels);
3458 for (x = forced_labels; x; x = XEXP (x, 1))
3460 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3462 for_each_eh_label (set_initial_eh_label_offset);
3465 /* Set all elimination offsets to the known values for the code label given
3469 set_offsets_for_label (rtx insn)
3472 int label_nr = CODE_LABEL_NUMBER (insn);
3473 struct elim_table *ep;
3475 num_not_at_initial_offset = 0;
3476 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3478 ep->offset = ep->previous_offset
3479 = offsets_at[label_nr - first_label_num][i];
3480 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3481 num_not_at_initial_offset++;
3485 /* See if anything that happened changes which eliminations are valid.
3486 For example, on the SPARC, whether or not the frame pointer can
3487 be eliminated can depend on what registers have been used. We need
3488 not check some conditions again (such as flag_omit_frame_pointer)
3489 since they can't have changed. */
3492 update_eliminables (HARD_REG_SET *pset)
3494 int previous_frame_pointer_needed = frame_pointer_needed;
3495 struct elim_table *ep;
3497 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3498 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3499 #ifdef ELIMINABLE_REGS
3500 || ! CAN_ELIMINATE (ep->from, ep->to)
3503 ep->can_eliminate = 0;
3505 /* Look for the case where we have discovered that we can't replace
3506 register A with register B and that means that we will now be
3507 trying to replace register A with register C. This means we can
3508 no longer replace register C with register B and we need to disable
3509 such an elimination, if it exists. This occurs often with A == ap,
3510 B == sp, and C == fp. */
3512 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3514 struct elim_table *op;
3517 if (! ep->can_eliminate && ep->can_eliminate_previous)
3519 /* Find the current elimination for ep->from, if there is a
3521 for (op = reg_eliminate;
3522 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3523 if (op->from == ep->from && op->can_eliminate)
3529 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3531 for (op = reg_eliminate;
3532 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3533 if (op->from == new_to && op->to == ep->to)
3534 op->can_eliminate = 0;
3538 /* See if any registers that we thought we could eliminate the previous
3539 time are no longer eliminable. If so, something has changed and we
3540 must spill the register. Also, recompute the number of eliminable
3541 registers and see if the frame pointer is needed; it is if there is
3542 no elimination of the frame pointer that we can perform. */
3544 frame_pointer_needed = 1;
3545 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3547 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3548 && ep->to != HARD_FRAME_POINTER_REGNUM)
3549 frame_pointer_needed = 0;
3551 if (! ep->can_eliminate && ep->can_eliminate_previous)
3553 ep->can_eliminate_previous = 0;
3554 SET_HARD_REG_BIT (*pset, ep->from);
3559 /* If we didn't need a frame pointer last time, but we do now, spill
3560 the hard frame pointer. */
3561 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3562 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3565 /* Initialize the table of registers to eliminate. */
3568 init_elim_table (void)
3570 struct elim_table *ep;
3571 #ifdef ELIMINABLE_REGS
3572 const struct elim_table_1 *ep1;
3576 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3578 /* Does this function require a frame pointer? */
3580 frame_pointer_needed = (! flag_omit_frame_pointer
3581 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3582 and restore sp for alloca. So we can't eliminate
3583 the frame pointer in that case. At some point,
3584 we should improve this by emitting the
3585 sp-adjusting insns for this case. */
3586 || (current_function_calls_alloca
3587 && EXIT_IGNORE_STACK)
3588 || current_function_accesses_prior_frames
3589 || FRAME_POINTER_REQUIRED);
3593 #ifdef ELIMINABLE_REGS
3594 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3595 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3597 ep->from = ep1->from;
3599 ep->can_eliminate = ep->can_eliminate_previous
3600 = (CAN_ELIMINATE (ep->from, ep->to)
3601 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3604 reg_eliminate[0].from = reg_eliminate_1[0].from;
3605 reg_eliminate[0].to = reg_eliminate_1[0].to;
3606 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3607 = ! frame_pointer_needed;
3610 /* Count the number of eliminable registers and build the FROM and TO
3611 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3612 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3613 We depend on this. */
3614 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3616 num_eliminable += ep->can_eliminate;
3617 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3618 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3622 /* Kick all pseudos out of hard register REGNO.
3624 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3625 because we found we can't eliminate some register. In the case, no pseudos
3626 are allowed to be in the register, even if they are only in a block that
3627 doesn't require spill registers, unlike the case when we are spilling this
3628 hard reg to produce another spill register.
3630 Return nonzero if any pseudos needed to be kicked out. */
3633 spill_hard_reg (unsigned int regno, int cant_eliminate)
3639 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3640 regs_ever_live[regno] = 1;
3643 /* Spill every pseudo reg that was allocated to this reg
3644 or to something that overlaps this reg. */
3646 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3647 if (reg_renumber[i] >= 0
3648 && (unsigned int) reg_renumber[i] <= regno
3649 && ((unsigned int) reg_renumber[i]
3650 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3651 [PSEUDO_REGNO_MODE (i)]
3653 SET_REGNO_REG_SET (&spilled_pseudos, i);
3656 /* After find_reload_regs has been run for all insn that need reloads,
3657 and/or spill_hard_regs was called, this function is used to actually
3658 spill pseudo registers and try to reallocate them. It also sets up the
3659 spill_regs array for use by choose_reload_regs. */
3662 finish_spills (int global)
3664 struct insn_chain *chain;
3665 int something_changed = 0;
3667 reg_set_iterator rsi;
3669 /* Build the spill_regs array for the function. */
3670 /* If there are some registers still to eliminate and one of the spill regs
3671 wasn't ever used before, additional stack space may have to be
3672 allocated to store this register. Thus, we may have changed the offset
3673 between the stack and frame pointers, so mark that something has changed.
3675 One might think that we need only set VAL to 1 if this is a call-used
3676 register. However, the set of registers that must be saved by the
3677 prologue is not identical to the call-used set. For example, the
3678 register used by the call insn for the return PC is a call-used register,
3679 but must be saved by the prologue. */
3682 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3683 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3685 spill_reg_order[i] = n_spills;
3686 spill_regs[n_spills++] = i;
3687 if (num_eliminable && ! regs_ever_live[i])
3688 something_changed = 1;
3689 regs_ever_live[i] = 1;
3692 spill_reg_order[i] = -1;
3694 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3696 /* Record the current hard register the pseudo is allocated to in
3697 pseudo_previous_regs so we avoid reallocating it to the same
3698 hard reg in a later pass. */
3699 gcc_assert (reg_renumber[i] >= 0);
3701 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3702 /* Mark it as no longer having a hard register home. */
3703 reg_renumber[i] = -1;
3704 /* We will need to scan everything again. */
3705 something_changed = 1;
3708 /* Retry global register allocation if possible. */
3711 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3712 /* For every insn that needs reloads, set the registers used as spill
3713 regs in pseudo_forbidden_regs for every pseudo live across the
3715 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3717 EXECUTE_IF_SET_IN_REG_SET
3718 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3720 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3721 chain->used_spill_regs);
3723 EXECUTE_IF_SET_IN_REG_SET
3724 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3726 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3727 chain->used_spill_regs);
3731 /* Retry allocating the spilled pseudos. For each reg, merge the
3732 various reg sets that indicate which hard regs can't be used,
3733 and call retry_global_alloc.
3734 We change spill_pseudos here to only contain pseudos that did not
3735 get a new hard register. */
3736 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3737 if (reg_old_renumber[i] != reg_renumber[i])
3739 HARD_REG_SET forbidden;
3740 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3741 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3742 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3743 retry_global_alloc (i, forbidden);
3744 if (reg_renumber[i] >= 0)
3745 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3749 /* Fix up the register information in the insn chain.
3750 This involves deleting those of the spilled pseudos which did not get
3751 a new hard register home from the live_{before,after} sets. */
3752 for (chain = reload_insn_chain; chain; chain = chain->next)
3754 HARD_REG_SET used_by_pseudos;
3755 HARD_REG_SET used_by_pseudos2;
3757 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3758 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3760 /* Mark any unallocated hard regs as available for spills. That
3761 makes inheritance work somewhat better. */
3762 if (chain->need_reload)
3764 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3765 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3766 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3768 /* Save the old value for the sanity test below. */
3769 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3771 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3772 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3773 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3774 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3776 /* Make sure we only enlarge the set. */
3777 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3783 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3784 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3786 int regno = reg_renumber[i];
3787 if (reg_old_renumber[i] == regno)
3790 alter_reg (i, reg_old_renumber[i]);
3791 reg_old_renumber[i] = regno;
3795 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3797 fprintf (dump_file, " Register %d now in %d.\n\n",
3798 i, reg_renumber[i]);
3802 return something_changed;
3805 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3808 scan_paradoxical_subregs (rtx x)
3812 enum rtx_code code = GET_CODE (x);
3822 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3830 if (REG_P (SUBREG_REG (x))
3831 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3832 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3833 = GET_MODE_SIZE (GET_MODE (x));
3840 fmt = GET_RTX_FORMAT (code);
3841 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3844 scan_paradoxical_subregs (XEXP (x, i));
3845 else if (fmt[i] == 'E')
3848 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3849 scan_paradoxical_subregs (XVECEXP (x, i, j));
3854 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
3855 examine all of the reload insns between PREV and NEXT exclusive, and
3856 annotate all that may trap. */
3859 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
3861 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
3862 unsigned int trap_count;
3868 if (may_trap_p (PATTERN (insn)))
3872 remove_note (insn, note);
3876 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
3877 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
3881 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0), REG_NOTES (i));
3885 /* Reload pseudo-registers into hard regs around each insn as needed.
3886 Additional register load insns are output before the insn that needs it
3887 and perhaps store insns after insns that modify the reloaded pseudo reg.
3889 reg_last_reload_reg and reg_reloaded_contents keep track of
3890 which registers are already available in reload registers.
3891 We update these for the reloads that we perform,
3892 as the insns are scanned. */
3895 reload_as_needed (int live_known)
3897 struct insn_chain *chain;
3898 #if defined (AUTO_INC_DEC)
3903 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3904 memset (spill_reg_store, 0, sizeof spill_reg_store);
3905 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
3906 INIT_REG_SET (®_has_output_reload);
3907 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3908 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3910 set_initial_elim_offsets ();
3912 for (chain = reload_insn_chain; chain; chain = chain->next)
3915 rtx insn = chain->insn;
3916 rtx old_next = NEXT_INSN (insn);
3918 /* If we pass a label, copy the offsets from the label information
3919 into the current offsets of each elimination. */
3921 set_offsets_for_label (insn);
3923 else if (INSN_P (insn))
3925 regset_head regs_to_forget;
3926 INIT_REG_SET (®s_to_forget);
3927 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
3929 /* If this is a USE and CLOBBER of a MEM, ensure that any
3930 references to eliminable registers have been removed. */
3932 if ((GET_CODE (PATTERN (insn)) == USE
3933 || GET_CODE (PATTERN (insn)) == CLOBBER)
3934 && MEM_P (XEXP (PATTERN (insn), 0)))
3935 XEXP (XEXP (PATTERN (insn), 0), 0)
3936 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3937 GET_MODE (XEXP (PATTERN (insn), 0)),
3940 /* If we need to do register elimination processing, do so.
3941 This might delete the insn, in which case we are done. */
3942 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3944 eliminate_regs_in_insn (insn, 1);
3947 update_eliminable_offsets ();
3948 CLEAR_REG_SET (®s_to_forget);
3953 /* If need_elim is nonzero but need_reload is zero, one might think
3954 that we could simply set n_reloads to 0. However, find_reloads
3955 could have done some manipulation of the insn (such as swapping
3956 commutative operands), and these manipulations are lost during
3957 the first pass for every insn that needs register elimination.
3958 So the actions of find_reloads must be redone here. */
3960 if (! chain->need_elim && ! chain->need_reload
3961 && ! chain->need_operand_change)
3963 /* First find the pseudo regs that must be reloaded for this insn.
3964 This info is returned in the tables reload_... (see reload.h).
3965 Also modify the body of INSN by substituting RELOAD
3966 rtx's for those pseudo regs. */
3969 CLEAR_REG_SET (®_has_output_reload);
3970 CLEAR_HARD_REG_SET (reg_is_output_reload);
3972 find_reloads (insn, 1, spill_indirect_levels, live_known,
3978 rtx next = NEXT_INSN (insn);
3981 prev = PREV_INSN (insn);
3983 /* Now compute which reload regs to reload them into. Perhaps
3984 reusing reload regs from previous insns, or else output
3985 load insns to reload them. Maybe output store insns too.
3986 Record the choices of reload reg in reload_reg_rtx. */
3987 choose_reload_regs (chain);
3989 /* Merge any reloads that we didn't combine for fear of
3990 increasing the number of spill registers needed but now
3991 discover can be safely merged. */
3992 if (SMALL_REGISTER_CLASSES)
3993 merge_assigned_reloads (insn);
3995 /* Generate the insns to reload operands into or out of
3996 their reload regs. */
3997 emit_reload_insns (chain);
3999 /* Substitute the chosen reload regs from reload_reg_rtx
4000 into the insn's body (or perhaps into the bodies of other
4001 load and store insn that we just made for reloading
4002 and that we moved the structure into). */
4003 subst_reloads (insn);
4005 /* Adjust the exception region notes for loads and stores. */
4006 if (flag_non_call_exceptions && !CALL_P (insn))
4007 fixup_eh_region_note (insn, prev, next);
4009 /* If this was an ASM, make sure that all the reload insns
4010 we have generated are valid. If not, give an error
4012 if (asm_noperands (PATTERN (insn)) >= 0)
4013 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4014 if (p != insn && INSN_P (p)
4015 && GET_CODE (PATTERN (p)) != USE
4016 && (recog_memoized (p) < 0
4017 || (extract_insn (p), ! constrain_operands (1))))
4019 error_for_asm (insn,
4020 "%<asm%> operand requires "
4021 "impossible reload");
4026 if (num_eliminable && chain->need_elim)
4027 update_eliminable_offsets ();
4029 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4030 is no longer validly lying around to save a future reload.
4031 Note that this does not detect pseudos that were reloaded
4032 for this insn in order to be stored in
4033 (obeying register constraints). That is correct; such reload
4034 registers ARE still valid. */
4035 forget_marked_reloads (®s_to_forget);
4036 CLEAR_REG_SET (®s_to_forget);
4038 /* There may have been CLOBBER insns placed after INSN. So scan
4039 between INSN and NEXT and use them to forget old reloads. */
4040 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4041 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4042 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4045 /* Likewise for regs altered by auto-increment in this insn.
4046 REG_INC notes have been changed by reloading:
4047 find_reloads_address_1 records substitutions for them,
4048 which have been performed by subst_reloads above. */
4049 for (i = n_reloads - 1; i >= 0; i--)
4051 rtx in_reg = rld[i].in_reg;
4054 enum rtx_code code = GET_CODE (in_reg);
4055 /* PRE_INC / PRE_DEC will have the reload register ending up
4056 with the same value as the stack slot, but that doesn't
4057 hold true for POST_INC / POST_DEC. Either we have to
4058 convert the memory access to a true POST_INC / POST_DEC,
4059 or we can't use the reload register for inheritance. */
4060 if ((code == POST_INC || code == POST_DEC)
4061 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4062 REGNO (rld[i].reg_rtx))
4063 /* Make sure it is the inc/dec pseudo, and not
4064 some other (e.g. output operand) pseudo. */
4065 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4066 == REGNO (XEXP (in_reg, 0))))
4069 rtx reload_reg = rld[i].reg_rtx;
4070 enum machine_mode mode = GET_MODE (reload_reg);
4074 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4076 /* We really want to ignore REG_INC notes here, so
4077 use PATTERN (p) as argument to reg_set_p . */
4078 if (reg_set_p (reload_reg, PATTERN (p)))
4080 n = count_occurrences (PATTERN (p), reload_reg, 0);
4085 n = validate_replace_rtx (reload_reg,
4086 gen_rtx_fmt_e (code,
4091 /* We must also verify that the constraints
4092 are met after the replacement. */
4095 n = constrain_operands (1);
4099 /* If the constraints were not met, then
4100 undo the replacement. */
4103 validate_replace_rtx (gen_rtx_fmt_e (code,
4116 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4118 /* Mark this as having an output reload so that the
4119 REG_INC processing code below won't invalidate
4120 the reload for inheritance. */
4121 SET_HARD_REG_BIT (reg_is_output_reload,
4122 REGNO (reload_reg));
4123 SET_REGNO_REG_SET (®_has_output_reload,
4124 REGNO (XEXP (in_reg, 0)));
4127 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4130 else if ((code == PRE_INC || code == PRE_DEC)
4131 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4132 REGNO (rld[i].reg_rtx))
4133 /* Make sure it is the inc/dec pseudo, and not
4134 some other (e.g. output operand) pseudo. */
4135 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4136 == REGNO (XEXP (in_reg, 0))))
4138 SET_HARD_REG_BIT (reg_is_output_reload,
4139 REGNO (rld[i].reg_rtx));
4140 SET_REGNO_REG_SET (®_has_output_reload,
4141 REGNO (XEXP (in_reg, 0)));
4145 /* If a pseudo that got a hard register is auto-incremented,
4146 we must purge records of copying it into pseudos without
4148 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4149 if (REG_NOTE_KIND (x) == REG_INC)
4151 /* See if this pseudo reg was reloaded in this insn.
4152 If so, its last-reload info is still valid
4153 because it is based on this insn's reload. */
4154 for (i = 0; i < n_reloads; i++)
4155 if (rld[i].out == XEXP (x, 0))
4159 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4163 /* A reload reg's contents are unknown after a label. */
4165 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4167 /* Don't assume a reload reg is still good after a call insn
4168 if it is a call-used reg, or if it contains a value that will
4169 be partially clobbered by the call. */
4170 else if (CALL_P (insn))
4172 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4173 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4178 free (reg_last_reload_reg);
4179 CLEAR_REG_SET (®_has_output_reload);
4182 /* Discard all record of any value reloaded from X,
4183 or reloaded in X from someplace else;
4184 unless X is an output reload reg of the current insn.
4186 X may be a hard reg (the reload reg)
4187 or it may be a pseudo reg that was reloaded from.
4189 When DATA is non-NULL just mark the registers in regset
4190 to be forgotten later. */
4193 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4198 regset regs = (regset) data;
4200 /* note_stores does give us subregs of hard regs,
4201 subreg_regno_offset requires a hard reg. */
4202 while (GET_CODE (x) == SUBREG)
4204 /* We ignore the subreg offset when calculating the regno,
4205 because we are using the entire underlying hard register
4215 if (regno >= FIRST_PSEUDO_REGISTER)
4221 nr = hard_regno_nregs[regno][GET_MODE (x)];
4222 /* Storing into a spilled-reg invalidates its contents.
4223 This can happen if a block-local pseudo is allocated to that reg
4224 and it wasn't spilled because this block's total need is 0.
4225 Then some insn might have an optional reload and use this reg. */
4227 for (i = 0; i < nr; i++)
4228 /* But don't do this if the reg actually serves as an output
4229 reload reg in the current instruction. */
4231 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4233 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4234 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4235 spill_reg_store[regno + i] = 0;
4241 SET_REGNO_REG_SET (regs, regno + nr);
4244 /* Since value of X has changed,
4245 forget any value previously copied from it. */
4248 /* But don't forget a copy if this is the output reload
4249 that establishes the copy's validity. */
4251 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4252 reg_last_reload_reg[regno + nr] = 0;
4256 /* Forget the reloads marked in regset by previous function. */
4258 forget_marked_reloads (regset regs)
4261 reg_set_iterator rsi;
4262 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4264 if (reg < FIRST_PSEUDO_REGISTER
4265 /* But don't do this if the reg actually serves as an output
4266 reload reg in the current instruction. */
4268 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4270 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4271 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, reg);
4272 spill_reg_store[reg] = 0;
4275 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4276 reg_last_reload_reg[reg] = 0;
4280 /* The following HARD_REG_SETs indicate when each hard register is
4281 used for a reload of various parts of the current insn. */
4283 /* If reg is unavailable for all reloads. */
4284 static HARD_REG_SET reload_reg_unavailable;
4285 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4286 static HARD_REG_SET reload_reg_used;
4287 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4288 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4289 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4290 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4291 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4292 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4293 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4294 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4295 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4296 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4297 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4298 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4299 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4300 static HARD_REG_SET reload_reg_used_in_op_addr;
4301 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4302 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4303 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4304 static HARD_REG_SET reload_reg_used_in_insn;
4305 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4306 static HARD_REG_SET reload_reg_used_in_other_addr;
4308 /* If reg is in use as a reload reg for any sort of reload. */
4309 static HARD_REG_SET reload_reg_used_at_all;
4311 /* If reg is use as an inherited reload. We just mark the first register
4313 static HARD_REG_SET reload_reg_used_for_inherit;
4315 /* Records which hard regs are used in any way, either as explicit use or
4316 by being allocated to a pseudo during any point of the current insn. */
4317 static HARD_REG_SET reg_used_in_insn;
4319 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4320 TYPE. MODE is used to indicate how many consecutive regs are
4324 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4325 enum machine_mode mode)
4327 unsigned int nregs = hard_regno_nregs[regno][mode];
4330 for (i = regno; i < nregs + regno; i++)
4335 SET_HARD_REG_BIT (reload_reg_used, i);
4338 case RELOAD_FOR_INPUT_ADDRESS:
4339 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4342 case RELOAD_FOR_INPADDR_ADDRESS:
4343 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4346 case RELOAD_FOR_OUTPUT_ADDRESS:
4347 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4350 case RELOAD_FOR_OUTADDR_ADDRESS:
4351 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4354 case RELOAD_FOR_OPERAND_ADDRESS:
4355 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4358 case RELOAD_FOR_OPADDR_ADDR:
4359 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4362 case RELOAD_FOR_OTHER_ADDRESS:
4363 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4366 case RELOAD_FOR_INPUT:
4367 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4370 case RELOAD_FOR_OUTPUT:
4371 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4374 case RELOAD_FOR_INSN:
4375 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4379 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4383 /* Similarly, but show REGNO is no longer in use for a reload. */
4386 clear_reload_reg_in_use (unsigned int regno, int opnum,
4387 enum reload_type type, enum machine_mode mode)
4389 unsigned int nregs = hard_regno_nregs[regno][mode];
4390 unsigned int start_regno, end_regno, r;
4392 /* A complication is that for some reload types, inheritance might
4393 allow multiple reloads of the same types to share a reload register.
4394 We set check_opnum if we have to check only reloads with the same
4395 operand number, and check_any if we have to check all reloads. */
4396 int check_opnum = 0;
4398 HARD_REG_SET *used_in_set;
4403 used_in_set = &reload_reg_used;
4406 case RELOAD_FOR_INPUT_ADDRESS:
4407 used_in_set = &reload_reg_used_in_input_addr[opnum];
4410 case RELOAD_FOR_INPADDR_ADDRESS:
4412 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4415 case RELOAD_FOR_OUTPUT_ADDRESS:
4416 used_in_set = &reload_reg_used_in_output_addr[opnum];
4419 case RELOAD_FOR_OUTADDR_ADDRESS:
4421 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4424 case RELOAD_FOR_OPERAND_ADDRESS:
4425 used_in_set = &reload_reg_used_in_op_addr;
4428 case RELOAD_FOR_OPADDR_ADDR:
4430 used_in_set = &reload_reg_used_in_op_addr_reload;
4433 case RELOAD_FOR_OTHER_ADDRESS:
4434 used_in_set = &reload_reg_used_in_other_addr;
4438 case RELOAD_FOR_INPUT:
4439 used_in_set = &reload_reg_used_in_input[opnum];
4442 case RELOAD_FOR_OUTPUT:
4443 used_in_set = &reload_reg_used_in_output[opnum];
4446 case RELOAD_FOR_INSN:
4447 used_in_set = &reload_reg_used_in_insn;
4452 /* We resolve conflicts with remaining reloads of the same type by
4453 excluding the intervals of reload registers by them from the
4454 interval of freed reload registers. Since we only keep track of
4455 one set of interval bounds, we might have to exclude somewhat
4456 more than what would be necessary if we used a HARD_REG_SET here.
4457 But this should only happen very infrequently, so there should
4458 be no reason to worry about it. */
4460 start_regno = regno;
4461 end_regno = regno + nregs;
4462 if (check_opnum || check_any)
4464 for (i = n_reloads - 1; i >= 0; i--)
4466 if (rld[i].when_needed == type
4467 && (check_any || rld[i].opnum == opnum)
4470 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4471 unsigned int conflict_end
4473 + hard_regno_nregs[conflict_start][rld[i].mode]);
4475 /* If there is an overlap with the first to-be-freed register,
4476 adjust the interval start. */
4477 if (conflict_start <= start_regno && conflict_end > start_regno)
4478 start_regno = conflict_end;
4479 /* Otherwise, if there is a conflict with one of the other
4480 to-be-freed registers, adjust the interval end. */
4481 if (conflict_start > start_regno && conflict_start < end_regno)
4482 end_regno = conflict_start;
4487 for (r = start_regno; r < end_regno; r++)
4488 CLEAR_HARD_REG_BIT (*used_in_set, r);
4491 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4492 specified by OPNUM and TYPE. */
4495 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4499 /* In use for a RELOAD_OTHER means it's not available for anything. */
4500 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4501 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4507 /* In use for anything means we can't use it for RELOAD_OTHER. */
4508 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4509 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4510 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4511 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4514 for (i = 0; i < reload_n_operands; i++)
4515 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4516 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4517 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4518 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4519 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4520 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4525 case RELOAD_FOR_INPUT:
4526 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4527 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4530 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4533 /* If it is used for some other input, can't use it. */
4534 for (i = 0; i < reload_n_operands; i++)
4535 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4538 /* If it is used in a later operand's address, can't use it. */
4539 for (i = opnum + 1; i < reload_n_operands; i++)
4540 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4541 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4546 case RELOAD_FOR_INPUT_ADDRESS:
4547 /* Can't use a register if it is used for an input address for this
4548 operand or used as an input in an earlier one. */
4549 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4550 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4553 for (i = 0; i < opnum; i++)
4554 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4559 case RELOAD_FOR_INPADDR_ADDRESS:
4560 /* Can't use a register if it is used for an input address
4561 for this operand or used as an input in an earlier
4563 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4566 for (i = 0; i < opnum; i++)
4567 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4572 case RELOAD_FOR_OUTPUT_ADDRESS:
4573 /* Can't use a register if it is used for an output address for this
4574 operand or used as an output in this or a later operand. Note
4575 that multiple output operands are emitted in reverse order, so
4576 the conflicting ones are those with lower indices. */
4577 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4580 for (i = 0; i <= opnum; i++)
4581 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4586 case RELOAD_FOR_OUTADDR_ADDRESS:
4587 /* Can't use a register if it is used for an output address
4588 for this operand or used as an output in this or a
4589 later operand. Note that multiple output operands are
4590 emitted in reverse order, so the conflicting ones are
4591 those with lower indices. */
4592 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4595 for (i = 0; i <= opnum; i++)
4596 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4601 case RELOAD_FOR_OPERAND_ADDRESS:
4602 for (i = 0; i < reload_n_operands; i++)
4603 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4606 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4607 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4609 case RELOAD_FOR_OPADDR_ADDR:
4610 for (i = 0; i < reload_n_operands; i++)
4611 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4614 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4616 case RELOAD_FOR_OUTPUT:
4617 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4618 outputs, or an operand address for this or an earlier output.
4619 Note that multiple output operands are emitted in reverse order,
4620 so the conflicting ones are those with higher indices. */
4621 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4624 for (i = 0; i < reload_n_operands; i++)
4625 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4628 for (i = opnum; i < reload_n_operands; i++)
4629 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4630 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4635 case RELOAD_FOR_INSN:
4636 for (i = 0; i < reload_n_operands; i++)
4637 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4638 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4641 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4642 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4644 case RELOAD_FOR_OTHER_ADDRESS:
4645 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4652 /* Return 1 if the value in reload reg REGNO, as used by a reload
4653 needed for the part of the insn specified by OPNUM and TYPE,
4654 is still available in REGNO at the end of the insn.
4656 We can assume that the reload reg was already tested for availability
4657 at the time it is needed, and we should not check this again,
4658 in case the reg has already been marked in use. */
4661 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4668 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4669 its value must reach the end. */
4672 /* If this use is for part of the insn,
4673 its value reaches if no subsequent part uses the same register.
4674 Just like the above function, don't try to do this with lots
4677 case RELOAD_FOR_OTHER_ADDRESS:
4678 /* Here we check for everything else, since these don't conflict
4679 with anything else and everything comes later. */
4681 for (i = 0; i < reload_n_operands; i++)
4682 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4683 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4684 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4685 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4686 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4687 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4690 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4691 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4692 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4693 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4695 case RELOAD_FOR_INPUT_ADDRESS:
4696 case RELOAD_FOR_INPADDR_ADDRESS:
4697 /* Similar, except that we check only for this and subsequent inputs
4698 and the address of only subsequent inputs and we do not need
4699 to check for RELOAD_OTHER objects since they are known not to
4702 for (i = opnum; i < reload_n_operands; i++)
4703 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4706 for (i = opnum + 1; i < reload_n_operands; i++)
4707 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4708 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4711 for (i = 0; i < reload_n_operands; i++)
4712 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4713 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4714 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4717 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4720 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4721 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4722 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4724 case RELOAD_FOR_INPUT:
4725 /* Similar to input address, except we start at the next operand for
4726 both input and input address and we do not check for
4727 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4730 for (i = opnum + 1; i < reload_n_operands; i++)
4731 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4732 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4733 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4736 /* ... fall through ... */
4738 case RELOAD_FOR_OPERAND_ADDRESS:
4739 /* Check outputs and their addresses. */
4741 for (i = 0; i < reload_n_operands; i++)
4742 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4743 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4744 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4747 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4749 case RELOAD_FOR_OPADDR_ADDR:
4750 for (i = 0; i < reload_n_operands; i++)
4751 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4752 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4753 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4756 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4757 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4758 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4760 case RELOAD_FOR_INSN:
4761 /* These conflict with other outputs with RELOAD_OTHER. So
4762 we need only check for output addresses. */
4764 opnum = reload_n_operands;
4766 /* ... fall through ... */
4768 case RELOAD_FOR_OUTPUT:
4769 case RELOAD_FOR_OUTPUT_ADDRESS:
4770 case RELOAD_FOR_OUTADDR_ADDRESS:
4771 /* We already know these can't conflict with a later output. So the
4772 only thing to check are later output addresses.
4773 Note that multiple output operands are emitted in reverse order,
4774 so the conflicting ones are those with lower indices. */
4775 for (i = 0; i < opnum; i++)
4776 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4777 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4787 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4790 This function uses the same algorithm as reload_reg_free_p above. */
4793 reloads_conflict (int r1, int r2)
4795 enum reload_type r1_type = rld[r1].when_needed;
4796 enum reload_type r2_type = rld[r2].when_needed;
4797 int r1_opnum = rld[r1].opnum;
4798 int r2_opnum = rld[r2].opnum;
4800 /* RELOAD_OTHER conflicts with everything. */
4801 if (r2_type == RELOAD_OTHER)
4804 /* Otherwise, check conflicts differently for each type. */
4808 case RELOAD_FOR_INPUT:
4809 return (r2_type == RELOAD_FOR_INSN
4810 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4811 || r2_type == RELOAD_FOR_OPADDR_ADDR
4812 || r2_type == RELOAD_FOR_INPUT
4813 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4814 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4815 && r2_opnum > r1_opnum));
4817 case RELOAD_FOR_INPUT_ADDRESS:
4818 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4819 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4821 case RELOAD_FOR_INPADDR_ADDRESS:
4822 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4823 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4825 case RELOAD_FOR_OUTPUT_ADDRESS:
4826 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4827 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4829 case RELOAD_FOR_OUTADDR_ADDRESS:
4830 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4831 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4833 case RELOAD_FOR_OPERAND_ADDRESS:
4834 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4835 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4837 case RELOAD_FOR_OPADDR_ADDR:
4838 return (r2_type == RELOAD_FOR_INPUT
4839 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4841 case RELOAD_FOR_OUTPUT:
4842 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4843 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4844 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4845 && r2_opnum >= r1_opnum));
4847 case RELOAD_FOR_INSN:
4848 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4849 || r2_type == RELOAD_FOR_INSN
4850 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4852 case RELOAD_FOR_OTHER_ADDRESS:
4853 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4863 /* Indexed by reload number, 1 if incoming value
4864 inherited from previous insns. */
4865 static char reload_inherited[MAX_RELOADS];
4867 /* For an inherited reload, this is the insn the reload was inherited from,
4868 if we know it. Otherwise, this is 0. */
4869 static rtx reload_inheritance_insn[MAX_RELOADS];
4871 /* If nonzero, this is a place to get the value of the reload,
4872 rather than using reload_in. */
4873 static rtx reload_override_in[MAX_RELOADS];
4875 /* For each reload, the hard register number of the register used,
4876 or -1 if we did not need a register for this reload. */
4877 static int reload_spill_index[MAX_RELOADS];
4879 /* Subroutine of free_for_value_p, used to check a single register.
4880 START_REGNO is the starting regno of the full reload register
4881 (possibly comprising multiple hard registers) that we are considering. */
4884 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4885 enum reload_type type, rtx value, rtx out,
4886 int reloadnum, int ignore_address_reloads)
4889 /* Set if we see an input reload that must not share its reload register
4890 with any new earlyclobber, but might otherwise share the reload
4891 register with an output or input-output reload. */
4892 int check_earlyclobber = 0;
4896 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4899 if (out == const0_rtx)
4905 /* We use some pseudo 'time' value to check if the lifetimes of the
4906 new register use would overlap with the one of a previous reload
4907 that is not read-only or uses a different value.
4908 The 'time' used doesn't have to be linear in any shape or form, just
4910 Some reload types use different 'buckets' for each operand.
4911 So there are MAX_RECOG_OPERANDS different time values for each
4913 We compute TIME1 as the time when the register for the prospective
4914 new reload ceases to be live, and TIME2 for each existing
4915 reload as the time when that the reload register of that reload
4917 Where there is little to be gained by exact lifetime calculations,
4918 we just make conservative assumptions, i.e. a longer lifetime;
4919 this is done in the 'default:' cases. */
4922 case RELOAD_FOR_OTHER_ADDRESS:
4923 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4924 time1 = copy ? 0 : 1;
4927 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4929 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4930 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4931 respectively, to the time values for these, we get distinct time
4932 values. To get distinct time values for each operand, we have to
4933 multiply opnum by at least three. We round that up to four because
4934 multiply by four is often cheaper. */
4935 case RELOAD_FOR_INPADDR_ADDRESS:
4936 time1 = opnum * 4 + 2;
4938 case RELOAD_FOR_INPUT_ADDRESS:
4939 time1 = opnum * 4 + 3;
4941 case RELOAD_FOR_INPUT:
4942 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4943 executes (inclusive). */
4944 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4946 case RELOAD_FOR_OPADDR_ADDR:
4948 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4949 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4951 case RELOAD_FOR_OPERAND_ADDRESS:
4952 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4954 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4956 case RELOAD_FOR_OUTADDR_ADDRESS:
4957 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4959 case RELOAD_FOR_OUTPUT_ADDRESS:
4960 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4963 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4966 for (i = 0; i < n_reloads; i++)
4968 rtx reg = rld[i].reg_rtx;
4969 if (reg && REG_P (reg)
4970 && ((unsigned) regno - true_regnum (reg)
4971 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
4974 rtx other_input = rld[i].in;
4976 /* If the other reload loads the same input value, that
4977 will not cause a conflict only if it's loading it into
4978 the same register. */
4979 if (true_regnum (reg) != start_regno)
4980 other_input = NULL_RTX;
4981 if (! other_input || ! rtx_equal_p (other_input, value)
4982 || rld[i].out || out)
4985 switch (rld[i].when_needed)
4987 case RELOAD_FOR_OTHER_ADDRESS:
4990 case RELOAD_FOR_INPADDR_ADDRESS:
4991 /* find_reloads makes sure that a
4992 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4993 by at most one - the first -
4994 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4995 address reload is inherited, the address address reload
4996 goes away, so we can ignore this conflict. */
4997 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4998 && ignore_address_reloads
4999 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5000 Then the address address is still needed to store
5001 back the new address. */
5002 && ! rld[reloadnum].out)
5004 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5005 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5007 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5008 && ignore_address_reloads
5009 /* Unless we are reloading an auto_inc expression. */
5010 && ! rld[reloadnum].out)
5012 time2 = rld[i].opnum * 4 + 2;
5014 case RELOAD_FOR_INPUT_ADDRESS:
5015 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5016 && ignore_address_reloads
5017 && ! rld[reloadnum].out)
5019 time2 = rld[i].opnum * 4 + 3;
5021 case RELOAD_FOR_INPUT:
5022 time2 = rld[i].opnum * 4 + 4;
5023 check_earlyclobber = 1;
5025 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5026 == MAX_RECOG_OPERAND * 4 */
5027 case RELOAD_FOR_OPADDR_ADDR:
5028 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5029 && ignore_address_reloads
5030 && ! rld[reloadnum].out)
5032 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5034 case RELOAD_FOR_OPERAND_ADDRESS:
5035 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5036 check_earlyclobber = 1;
5038 case RELOAD_FOR_INSN:
5039 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5041 case RELOAD_FOR_OUTPUT:
5042 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5043 instruction is executed. */
5044 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5046 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5047 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5049 case RELOAD_FOR_OUTADDR_ADDRESS:
5050 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5051 && ignore_address_reloads
5052 && ! rld[reloadnum].out)
5054 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5056 case RELOAD_FOR_OUTPUT_ADDRESS:
5057 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5060 /* If there is no conflict in the input part, handle this
5061 like an output reload. */
5062 if (! rld[i].in || rtx_equal_p (other_input, value))
5064 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5065 /* Earlyclobbered outputs must conflict with inputs. */
5066 if (earlyclobber_operand_p (rld[i].out))
5067 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5072 /* RELOAD_OTHER might be live beyond instruction execution,
5073 but this is not obvious when we set time2 = 1. So check
5074 here if there might be a problem with the new reload
5075 clobbering the register used by the RELOAD_OTHER. */
5083 && (! rld[i].in || rld[i].out
5084 || ! rtx_equal_p (other_input, value)))
5085 || (out && rld[reloadnum].out_reg
5086 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5092 /* Earlyclobbered outputs must conflict with inputs. */
5093 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5099 /* Return 1 if the value in reload reg REGNO, as used by a reload
5100 needed for the part of the insn specified by OPNUM and TYPE,
5101 may be used to load VALUE into it.
5103 MODE is the mode in which the register is used, this is needed to
5104 determine how many hard regs to test.
5106 Other read-only reloads with the same value do not conflict
5107 unless OUT is nonzero and these other reloads have to live while
5108 output reloads live.
5109 If OUT is CONST0_RTX, this is a special case: it means that the
5110 test should not be for using register REGNO as reload register, but
5111 for copying from register REGNO into the reload register.
5113 RELOADNUM is the number of the reload we want to load this value for;
5114 a reload does not conflict with itself.
5116 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5117 reloads that load an address for the very reload we are considering.
5119 The caller has to make sure that there is no conflict with the return
5123 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5124 enum reload_type type, rtx value, rtx out, int reloadnum,
5125 int ignore_address_reloads)
5127 int nregs = hard_regno_nregs[regno][mode];
5129 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5130 value, out, reloadnum,
5131 ignore_address_reloads))
5136 /* Return nonzero if the rtx X is invariant over the current function. */
5137 /* ??? Actually, the places where we use this expect exactly what is
5138 tested here, and not everything that is function invariant. In
5139 particular, the frame pointer and arg pointer are special cased;
5140 pic_offset_table_rtx is not, and we must not spill these things to
5144 function_invariant_p (rtx x)
5148 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5150 if (GET_CODE (x) == PLUS
5151 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5152 && CONSTANT_P (XEXP (x, 1)))
5157 /* Determine whether the reload reg X overlaps any rtx'es used for
5158 overriding inheritance. Return nonzero if so. */
5161 conflicts_with_override (rtx x)
5164 for (i = 0; i < n_reloads; i++)
5165 if (reload_override_in[i]
5166 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5171 /* Give an error message saying we failed to find a reload for INSN,
5172 and clear out reload R. */
5174 failed_reload (rtx insn, int r)
5176 if (asm_noperands (PATTERN (insn)) < 0)
5177 /* It's the compiler's fault. */
5178 fatal_insn ("could not find a spill register", insn);
5180 /* It's the user's fault; the operand's mode and constraint
5181 don't match. Disable this reload so we don't crash in final. */
5182 error_for_asm (insn,
5183 "%<asm%> operand constraint incompatible with operand size");
5187 rld[r].optional = 1;
5188 rld[r].secondary_p = 1;
5191 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5192 for reload R. If it's valid, get an rtx for it. Return nonzero if
5195 set_reload_reg (int i, int r)
5198 rtx reg = spill_reg_rtx[i];
5200 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5201 spill_reg_rtx[i] = reg
5202 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5204 regno = true_regnum (reg);
5206 /* Detect when the reload reg can't hold the reload mode.
5207 This used to be one `if', but Sequent compiler can't handle that. */
5208 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5210 enum machine_mode test_mode = VOIDmode;
5212 test_mode = GET_MODE (rld[r].in);
5213 /* If rld[r].in has VOIDmode, it means we will load it
5214 in whatever mode the reload reg has: to wit, rld[r].mode.
5215 We have already tested that for validity. */
5216 /* Aside from that, we need to test that the expressions
5217 to reload from or into have modes which are valid for this
5218 reload register. Otherwise the reload insns would be invalid. */
5219 if (! (rld[r].in != 0 && test_mode != VOIDmode
5220 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5221 if (! (rld[r].out != 0
5222 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5224 /* The reg is OK. */
5227 /* Mark as in use for this insn the reload regs we use
5229 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5230 rld[r].when_needed, rld[r].mode);
5232 rld[r].reg_rtx = reg;
5233 reload_spill_index[r] = spill_regs[i];
5240 /* Find a spill register to use as a reload register for reload R.
5241 LAST_RELOAD is nonzero if this is the last reload for the insn being
5244 Set rld[R].reg_rtx to the register allocated.
5246 We return 1 if successful, or 0 if we couldn't find a spill reg and
5247 we didn't change anything. */
5250 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5255 /* If we put this reload ahead, thinking it is a group,
5256 then insist on finding a group. Otherwise we can grab a
5257 reg that some other reload needs.
5258 (That can happen when we have a 68000 DATA_OR_FP_REG
5259 which is a group of data regs or one fp reg.)
5260 We need not be so restrictive if there are no more reloads
5263 ??? Really it would be nicer to have smarter handling
5264 for that kind of reg class, where a problem like this is normal.
5265 Perhaps those classes should be avoided for reloading
5266 by use of more alternatives. */
5268 int force_group = rld[r].nregs > 1 && ! last_reload;
5270 /* If we want a single register and haven't yet found one,
5271 take any reg in the right class and not in use.
5272 If we want a consecutive group, here is where we look for it.
5274 We use two passes so we can first look for reload regs to
5275 reuse, which are already in use for other reloads in this insn,
5276 and only then use additional registers.
5277 I think that maximizing reuse is needed to make sure we don't
5278 run out of reload regs. Suppose we have three reloads, and
5279 reloads A and B can share regs. These need two regs.
5280 Suppose A and B are given different regs.
5281 That leaves none for C. */
5282 for (pass = 0; pass < 2; pass++)
5284 /* I is the index in spill_regs.
5285 We advance it round-robin between insns to use all spill regs
5286 equally, so that inherited reloads have a chance
5287 of leapfrogging each other. */
5291 for (count = 0; count < n_spills; count++)
5293 int class = (int) rld[r].class;
5299 regnum = spill_regs[i];
5301 if ((reload_reg_free_p (regnum, rld[r].opnum,
5304 /* We check reload_reg_used to make sure we
5305 don't clobber the return register. */
5306 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5307 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5308 rld[r].when_needed, rld[r].in,
5310 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5311 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5312 /* Look first for regs to share, then for unshared. But
5313 don't share regs used for inherited reloads; they are
5314 the ones we want to preserve. */
5316 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5318 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5321 int nr = hard_regno_nregs[regnum][rld[r].mode];
5322 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5323 (on 68000) got us two FP regs. If NR is 1,
5324 we would reject both of them. */
5327 /* If we need only one reg, we have already won. */
5330 /* But reject a single reg if we demand a group. */
5335 /* Otherwise check that as many consecutive regs as we need
5336 are available here. */
5339 int regno = regnum + nr - 1;
5340 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5341 && spill_reg_order[regno] >= 0
5342 && reload_reg_free_p (regno, rld[r].opnum,
5343 rld[r].when_needed)))
5352 /* If we found something on pass 1, omit pass 2. */
5353 if (count < n_spills)
5357 /* We should have found a spill register by now. */
5358 if (count >= n_spills)
5361 /* I is the index in SPILL_REG_RTX of the reload register we are to
5362 allocate. Get an rtx for it and find its register number. */
5364 return set_reload_reg (i, r);
5367 /* Initialize all the tables needed to allocate reload registers.
5368 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5369 is the array we use to restore the reg_rtx field for every reload. */
5372 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5376 for (i = 0; i < n_reloads; i++)
5377 rld[i].reg_rtx = save_reload_reg_rtx[i];
5379 memset (reload_inherited, 0, MAX_RELOADS);
5380 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5381 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5383 CLEAR_HARD_REG_SET (reload_reg_used);
5384 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5385 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5386 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5387 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5388 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5390 CLEAR_HARD_REG_SET (reg_used_in_insn);
5393 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5394 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5395 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5396 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5397 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5398 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5401 for (i = 0; i < reload_n_operands; i++)
5403 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5404 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5405 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5406 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5407 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5408 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5411 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5413 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5415 for (i = 0; i < n_reloads; i++)
5416 /* If we have already decided to use a certain register,
5417 don't use it in another way. */
5419 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5420 rld[i].when_needed, rld[i].mode);
5423 /* Assign hard reg targets for the pseudo-registers we must reload
5424 into hard regs for this insn.
5425 Also output the instructions to copy them in and out of the hard regs.
5427 For machines with register classes, we are responsible for
5428 finding a reload reg in the proper class. */
5431 choose_reload_regs (struct insn_chain *chain)
5433 rtx insn = chain->insn;
5435 unsigned int max_group_size = 1;
5436 enum reg_class group_class = NO_REGS;
5437 int pass, win, inheritance;
5439 rtx save_reload_reg_rtx[MAX_RELOADS];
5441 /* In order to be certain of getting the registers we need,
5442 we must sort the reloads into order of increasing register class.
5443 Then our grabbing of reload registers will parallel the process
5444 that provided the reload registers.
5446 Also note whether any of the reloads wants a consecutive group of regs.
5447 If so, record the maximum size of the group desired and what
5448 register class contains all the groups needed by this insn. */
5450 for (j = 0; j < n_reloads; j++)
5452 reload_order[j] = j;
5453 reload_spill_index[j] = -1;
5455 if (rld[j].nregs > 1)
5457 max_group_size = MAX (rld[j].nregs, max_group_size);
5459 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5462 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5466 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5468 /* If -O, try first with inheritance, then turning it off.
5469 If not -O, don't do inheritance.
5470 Using inheritance when not optimizing leads to paradoxes
5471 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5472 because one side of the comparison might be inherited. */
5474 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5476 choose_reload_regs_init (chain, save_reload_reg_rtx);
5478 /* Process the reloads in order of preference just found.
5479 Beyond this point, subregs can be found in reload_reg_rtx.
5481 This used to look for an existing reloaded home for all of the
5482 reloads, and only then perform any new reloads. But that could lose
5483 if the reloads were done out of reg-class order because a later
5484 reload with a looser constraint might have an old home in a register
5485 needed by an earlier reload with a tighter constraint.
5487 To solve this, we make two passes over the reloads, in the order
5488 described above. In the first pass we try to inherit a reload
5489 from a previous insn. If there is a later reload that needs a
5490 class that is a proper subset of the class being processed, we must
5491 also allocate a spill register during the first pass.
5493 Then make a second pass over the reloads to allocate any reloads
5494 that haven't been given registers yet. */
5496 for (j = 0; j < n_reloads; j++)
5498 int r = reload_order[j];
5499 rtx search_equiv = NULL_RTX;
5501 /* Ignore reloads that got marked inoperative. */
5502 if (rld[r].out == 0 && rld[r].in == 0
5503 && ! rld[r].secondary_p)
5506 /* If find_reloads chose to use reload_in or reload_out as a reload
5507 register, we don't need to chose one. Otherwise, try even if it
5508 found one since we might save an insn if we find the value lying
5510 Try also when reload_in is a pseudo without a hard reg. */
5511 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5512 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5513 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5514 && !MEM_P (rld[r].in)
5515 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5518 #if 0 /* No longer needed for correct operation.
5519 It might give better code, or might not; worth an experiment? */
5520 /* If this is an optional reload, we can't inherit from earlier insns
5521 until we are sure that any non-optional reloads have been allocated.
5522 The following code takes advantage of the fact that optional reloads
5523 are at the end of reload_order. */
5524 if (rld[r].optional != 0)
5525 for (i = 0; i < j; i++)
5526 if ((rld[reload_order[i]].out != 0
5527 || rld[reload_order[i]].in != 0
5528 || rld[reload_order[i]].secondary_p)
5529 && ! rld[reload_order[i]].optional
5530 && rld[reload_order[i]].reg_rtx == 0)
5531 allocate_reload_reg (chain, reload_order[i], 0);
5534 /* First see if this pseudo is already available as reloaded
5535 for a previous insn. We cannot try to inherit for reloads
5536 that are smaller than the maximum number of registers needed
5537 for groups unless the register we would allocate cannot be used
5540 We could check here to see if this is a secondary reload for
5541 an object that is already in a register of the desired class.
5542 This would avoid the need for the secondary reload register.
5543 But this is complex because we can't easily determine what
5544 objects might want to be loaded via this reload. So let a
5545 register be allocated here. In `emit_reload_insns' we suppress
5546 one of the loads in the case described above. */
5552 enum machine_mode mode = VOIDmode;
5556 else if (REG_P (rld[r].in))
5558 regno = REGNO (rld[r].in);
5559 mode = GET_MODE (rld[r].in);
5561 else if (REG_P (rld[r].in_reg))
5563 regno = REGNO (rld[r].in_reg);
5564 mode = GET_MODE (rld[r].in_reg);
5566 else if (GET_CODE (rld[r].in_reg) == SUBREG
5567 && REG_P (SUBREG_REG (rld[r].in_reg)))
5569 byte = SUBREG_BYTE (rld[r].in_reg);
5570 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5571 if (regno < FIRST_PSEUDO_REGISTER)
5572 regno = subreg_regno (rld[r].in_reg);
5573 mode = GET_MODE (rld[r].in_reg);
5576 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
5577 && REG_P (XEXP (rld[r].in_reg, 0)))
5579 regno = REGNO (XEXP (rld[r].in_reg, 0));
5580 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5581 rld[r].out = rld[r].in;
5585 /* This won't work, since REGNO can be a pseudo reg number.
5586 Also, it takes much more hair to keep track of all the things
5587 that can invalidate an inherited reload of part of a pseudoreg. */
5588 else if (GET_CODE (rld[r].in) == SUBREG
5589 && REG_P (SUBREG_REG (rld[r].in)))
5590 regno = subreg_regno (rld[r].in);
5593 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5595 enum reg_class class = rld[r].class, last_class;
5596 rtx last_reg = reg_last_reload_reg[regno];
5597 enum machine_mode need_mode;
5599 i = REGNO (last_reg);
5600 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5601 last_class = REGNO_REG_CLASS (i);
5607 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5608 + byte * BITS_PER_UNIT,
5609 GET_MODE_CLASS (mode));
5611 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5612 >= GET_MODE_SIZE (need_mode))
5613 #ifdef CANNOT_CHANGE_MODE_CLASS
5614 /* Verify that the register in "i" can be obtained
5616 && !REG_CANNOT_CHANGE_MODE_P (REGNO (last_reg),
5617 GET_MODE (last_reg),
5620 && reg_reloaded_contents[i] == regno
5621 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5622 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5623 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5624 /* Even if we can't use this register as a reload
5625 register, we might use it for reload_override_in,
5626 if copying it to the desired class is cheap
5628 || ((REGISTER_MOVE_COST (mode, last_class, class)
5629 < MEMORY_MOVE_COST (mode, class, 1))
5630 && (secondary_reload_class (1, class, mode,
5633 #ifdef SECONDARY_MEMORY_NEEDED
5634 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5639 && (rld[r].nregs == max_group_size
5640 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5642 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5643 rld[r].when_needed, rld[r].in,
5646 /* If a group is needed, verify that all the subsequent
5647 registers still have their values intact. */
5648 int nr = hard_regno_nregs[i][rld[r].mode];
5651 for (k = 1; k < nr; k++)
5652 if (reg_reloaded_contents[i + k] != regno
5653 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5661 last_reg = (GET_MODE (last_reg) == mode
5662 ? last_reg : gen_rtx_REG (mode, i));
5665 for (k = 0; k < nr; k++)
5666 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5669 /* We found a register that contains the
5670 value we need. If this register is the
5671 same as an `earlyclobber' operand of the
5672 current insn, just mark it as a place to
5673 reload from since we can't use it as the
5674 reload register itself. */
5676 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5677 if (reg_overlap_mentioned_for_reload_p
5678 (reg_last_reload_reg[regno],
5679 reload_earlyclobbers[i1]))
5682 if (i1 != n_earlyclobbers
5683 || ! (free_for_value_p (i, rld[r].mode,
5685 rld[r].when_needed, rld[r].in,
5687 /* Don't use it if we'd clobber a pseudo reg. */
5688 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5690 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5691 /* Don't clobber the frame pointer. */
5692 || (i == HARD_FRAME_POINTER_REGNUM
5693 && frame_pointer_needed
5695 /* Don't really use the inherited spill reg
5696 if we need it wider than we've got it. */
5697 || (GET_MODE_SIZE (rld[r].mode)
5698 > GET_MODE_SIZE (mode))
5701 /* If find_reloads chose reload_out as reload
5702 register, stay with it - that leaves the
5703 inherited register for subsequent reloads. */
5704 || (rld[r].out && rld[r].reg_rtx
5705 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5707 if (! rld[r].optional)
5709 reload_override_in[r] = last_reg;
5710 reload_inheritance_insn[r]
5711 = reg_reloaded_insn[i];
5717 /* We can use this as a reload reg. */
5718 /* Mark the register as in use for this part of
5720 mark_reload_reg_in_use (i,
5724 rld[r].reg_rtx = last_reg;
5725 reload_inherited[r] = 1;
5726 reload_inheritance_insn[r]
5727 = reg_reloaded_insn[i];
5728 reload_spill_index[r] = i;
5729 for (k = 0; k < nr; k++)
5730 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5738 /* Here's another way to see if the value is already lying around. */
5741 && ! reload_inherited[r]
5743 && (CONSTANT_P (rld[r].in)
5744 || GET_CODE (rld[r].in) == PLUS
5745 || REG_P (rld[r].in)
5746 || MEM_P (rld[r].in))
5747 && (rld[r].nregs == max_group_size
5748 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5749 search_equiv = rld[r].in;
5750 /* If this is an output reload from a simple move insn, look
5751 if an equivalence for the input is available. */
5752 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5754 rtx set = single_set (insn);
5757 && rtx_equal_p (rld[r].out, SET_DEST (set))
5758 && CONSTANT_P (SET_SRC (set)))
5759 search_equiv = SET_SRC (set);
5765 = find_equiv_reg (search_equiv, insn, rld[r].class,
5766 -1, NULL, 0, rld[r].mode);
5772 regno = REGNO (equiv);
5775 /* This must be a SUBREG of a hard register.
5776 Make a new REG since this might be used in an
5777 address and not all machines support SUBREGs
5779 gcc_assert (GET_CODE (equiv) == SUBREG);
5780 regno = subreg_regno (equiv);
5781 equiv = gen_rtx_REG (rld[r].mode, regno);
5782 /* If we choose EQUIV as the reload register, but the
5783 loop below decides to cancel the inheritance, we'll
5784 end up reloading EQUIV in rld[r].mode, not the mode
5785 it had originally. That isn't safe when EQUIV isn't
5786 available as a spill register since its value might
5787 still be live at this point. */
5788 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5789 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
5794 /* If we found a spill reg, reject it unless it is free
5795 and of the desired class. */
5799 int bad_for_class = 0;
5800 int max_regno = regno + rld[r].nregs;
5802 for (i = regno; i < max_regno; i++)
5804 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5806 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5811 && ! free_for_value_p (regno, rld[r].mode,
5812 rld[r].opnum, rld[r].when_needed,
5813 rld[r].in, rld[r].out, r, 1))
5818 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5821 /* We found a register that contains the value we need.
5822 If this register is the same as an `earlyclobber' operand
5823 of the current insn, just mark it as a place to reload from
5824 since we can't use it as the reload register itself. */
5827 for (i = 0; i < n_earlyclobbers; i++)
5828 if (reg_overlap_mentioned_for_reload_p (equiv,
5829 reload_earlyclobbers[i]))
5831 if (! rld[r].optional)
5832 reload_override_in[r] = equiv;
5837 /* If the equiv register we have found is explicitly clobbered
5838 in the current insn, it depends on the reload type if we
5839 can use it, use it for reload_override_in, or not at all.
5840 In particular, we then can't use EQUIV for a
5841 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5845 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
5846 switch (rld[r].when_needed)
5848 case RELOAD_FOR_OTHER_ADDRESS:
5849 case RELOAD_FOR_INPADDR_ADDRESS:
5850 case RELOAD_FOR_INPUT_ADDRESS:
5851 case RELOAD_FOR_OPADDR_ADDR:
5854 case RELOAD_FOR_INPUT:
5855 case RELOAD_FOR_OPERAND_ADDRESS:
5856 if (! rld[r].optional)
5857 reload_override_in[r] = equiv;
5863 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5864 switch (rld[r].when_needed)
5866 case RELOAD_FOR_OTHER_ADDRESS:
5867 case RELOAD_FOR_INPADDR_ADDRESS:
5868 case RELOAD_FOR_INPUT_ADDRESS:
5869 case RELOAD_FOR_OPADDR_ADDR:
5870 case RELOAD_FOR_OPERAND_ADDRESS:
5871 case RELOAD_FOR_INPUT:
5874 if (! rld[r].optional)
5875 reload_override_in[r] = equiv;
5883 /* If we found an equivalent reg, say no code need be generated
5884 to load it, and use it as our reload reg. */
5886 && (regno != HARD_FRAME_POINTER_REGNUM
5887 || !frame_pointer_needed))
5889 int nr = hard_regno_nregs[regno][rld[r].mode];
5891 rld[r].reg_rtx = equiv;
5892 reload_inherited[r] = 1;
5894 /* If reg_reloaded_valid is not set for this register,
5895 there might be a stale spill_reg_store lying around.
5896 We must clear it, since otherwise emit_reload_insns
5897 might delete the store. */
5898 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5899 spill_reg_store[regno] = NULL_RTX;
5900 /* If any of the hard registers in EQUIV are spill
5901 registers, mark them as in use for this insn. */
5902 for (k = 0; k < nr; k++)
5904 i = spill_reg_order[regno + k];
5907 mark_reload_reg_in_use (regno, rld[r].opnum,
5910 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5917 /* If we found a register to use already, or if this is an optional
5918 reload, we are done. */
5919 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5923 /* No longer needed for correct operation. Might or might
5924 not give better code on the average. Want to experiment? */
5926 /* See if there is a later reload that has a class different from our
5927 class that intersects our class or that requires less register
5928 than our reload. If so, we must allocate a register to this
5929 reload now, since that reload might inherit a previous reload
5930 and take the only available register in our class. Don't do this
5931 for optional reloads since they will force all previous reloads
5932 to be allocated. Also don't do this for reloads that have been
5935 for (i = j + 1; i < n_reloads; i++)
5937 int s = reload_order[i];
5939 if ((rld[s].in == 0 && rld[s].out == 0
5940 && ! rld[s].secondary_p)
5944 if ((rld[s].class != rld[r].class
5945 && reg_classes_intersect_p (rld[r].class,
5947 || rld[s].nregs < rld[r].nregs)
5954 allocate_reload_reg (chain, r, j == n_reloads - 1);
5958 /* Now allocate reload registers for anything non-optional that
5959 didn't get one yet. */
5960 for (j = 0; j < n_reloads; j++)
5962 int r = reload_order[j];
5964 /* Ignore reloads that got marked inoperative. */
5965 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5968 /* Skip reloads that already have a register allocated or are
5970 if (rld[r].reg_rtx != 0 || rld[r].optional)
5973 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5977 /* If that loop got all the way, we have won. */
5984 /* Loop around and try without any inheritance. */
5989 /* First undo everything done by the failed attempt
5990 to allocate with inheritance. */
5991 choose_reload_regs_init (chain, save_reload_reg_rtx);
5993 /* Some sanity tests to verify that the reloads found in the first
5994 pass are identical to the ones we have now. */
5995 gcc_assert (chain->n_reloads == n_reloads);
5997 for (i = 0; i < n_reloads; i++)
5999 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6001 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6002 for (j = 0; j < n_spills; j++)
6003 if (spill_regs[j] == chain->rld[i].regno)
6004 if (! set_reload_reg (j, i))
6005 failed_reload (chain->insn, i);
6009 /* If we thought we could inherit a reload, because it seemed that
6010 nothing else wanted the same reload register earlier in the insn,
6011 verify that assumption, now that all reloads have been assigned.
6012 Likewise for reloads where reload_override_in has been set. */
6014 /* If doing expensive optimizations, do one preliminary pass that doesn't
6015 cancel any inheritance, but removes reloads that have been needed only
6016 for reloads that we know can be inherited. */
6017 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6019 for (j = 0; j < n_reloads; j++)
6021 int r = reload_order[j];
6023 if (reload_inherited[r] && rld[r].reg_rtx)
6024 check_reg = rld[r].reg_rtx;
6025 else if (reload_override_in[r]
6026 && (REG_P (reload_override_in[r])
6027 || GET_CODE (reload_override_in[r]) == SUBREG))
6028 check_reg = reload_override_in[r];
6031 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6032 rld[r].opnum, rld[r].when_needed, rld[r].in,
6033 (reload_inherited[r]
6034 ? rld[r].out : const0_rtx),
6039 reload_inherited[r] = 0;
6040 reload_override_in[r] = 0;
6042 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6043 reload_override_in, then we do not need its related
6044 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6045 likewise for other reload types.
6046 We handle this by removing a reload when its only replacement
6047 is mentioned in reload_in of the reload we are going to inherit.
6048 A special case are auto_inc expressions; even if the input is
6049 inherited, we still need the address for the output. We can
6050 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6051 If we succeeded removing some reload and we are doing a preliminary
6052 pass just to remove such reloads, make another pass, since the
6053 removal of one reload might allow us to inherit another one. */
6055 && rld[r].out != rld[r].in
6056 && remove_address_replacements (rld[r].in) && pass)
6061 /* Now that reload_override_in is known valid,
6062 actually override reload_in. */
6063 for (j = 0; j < n_reloads; j++)
6064 if (reload_override_in[j])
6065 rld[j].in = reload_override_in[j];
6067 /* If this reload won't be done because it has been canceled or is
6068 optional and not inherited, clear reload_reg_rtx so other
6069 routines (such as subst_reloads) don't get confused. */
6070 for (j = 0; j < n_reloads; j++)
6071 if (rld[j].reg_rtx != 0
6072 && ((rld[j].optional && ! reload_inherited[j])
6073 || (rld[j].in == 0 && rld[j].out == 0
6074 && ! rld[j].secondary_p)))
6076 int regno = true_regnum (rld[j].reg_rtx);
6078 if (spill_reg_order[regno] >= 0)
6079 clear_reload_reg_in_use (regno, rld[j].opnum,
6080 rld[j].when_needed, rld[j].mode);
6082 reload_spill_index[j] = -1;
6085 /* Record which pseudos and which spill regs have output reloads. */
6086 for (j = 0; j < n_reloads; j++)
6088 int r = reload_order[j];
6090 i = reload_spill_index[r];
6092 /* I is nonneg if this reload uses a register.
6093 If rld[r].reg_rtx is 0, this is an optional reload
6094 that we opted to ignore. */
6095 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6096 && rld[r].reg_rtx != 0)
6098 int nregno = REGNO (rld[r].out_reg);
6101 if (nregno < FIRST_PSEUDO_REGISTER)
6102 nr = hard_regno_nregs[nregno][rld[r].mode];
6105 SET_REGNO_REG_SET (®_has_output_reload,
6110 nr = hard_regno_nregs[i][rld[r].mode];
6112 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6115 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6116 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6117 || rld[r].when_needed == RELOAD_FOR_INSN);
6122 /* Deallocate the reload register for reload R. This is called from
6123 remove_address_replacements. */
6126 deallocate_reload_reg (int r)
6130 if (! rld[r].reg_rtx)
6132 regno = true_regnum (rld[r].reg_rtx);
6134 if (spill_reg_order[regno] >= 0)
6135 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6137 reload_spill_index[r] = -1;
6140 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6141 reloads of the same item for fear that we might not have enough reload
6142 registers. However, normally they will get the same reload register
6143 and hence actually need not be loaded twice.
6145 Here we check for the most common case of this phenomenon: when we have
6146 a number of reloads for the same object, each of which were allocated
6147 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6148 reload, and is not modified in the insn itself. If we find such,
6149 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6150 This will not increase the number of spill registers needed and will
6151 prevent redundant code. */
6154 merge_assigned_reloads (rtx insn)
6158 /* Scan all the reloads looking for ones that only load values and
6159 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6160 assigned and not modified by INSN. */
6162 for (i = 0; i < n_reloads; i++)
6164 int conflicting_input = 0;
6165 int max_input_address_opnum = -1;
6166 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6168 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6169 || rld[i].out != 0 || rld[i].reg_rtx == 0
6170 || reg_set_p (rld[i].reg_rtx, insn))
6173 /* Look at all other reloads. Ensure that the only use of this
6174 reload_reg_rtx is in a reload that just loads the same value
6175 as we do. Note that any secondary reloads must be of the identical
6176 class since the values, modes, and result registers are the
6177 same, so we need not do anything with any secondary reloads. */
6179 for (j = 0; j < n_reloads; j++)
6181 if (i == j || rld[j].reg_rtx == 0
6182 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6186 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6187 && rld[j].opnum > max_input_address_opnum)
6188 max_input_address_opnum = rld[j].opnum;
6190 /* If the reload regs aren't exactly the same (e.g, different modes)
6191 or if the values are different, we can't merge this reload.
6192 But if it is an input reload, we might still merge
6193 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6195 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6196 || rld[j].out != 0 || rld[j].in == 0
6197 || ! rtx_equal_p (rld[i].in, rld[j].in))
6199 if (rld[j].when_needed != RELOAD_FOR_INPUT
6200 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6201 || rld[i].opnum > rld[j].opnum)
6202 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6204 conflicting_input = 1;
6205 if (min_conflicting_input_opnum > rld[j].opnum)
6206 min_conflicting_input_opnum = rld[j].opnum;
6210 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6211 we, in fact, found any matching reloads. */
6214 && max_input_address_opnum <= min_conflicting_input_opnum)
6216 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6218 for (j = 0; j < n_reloads; j++)
6219 if (i != j && rld[j].reg_rtx != 0
6220 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6221 && (! conflicting_input
6222 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6223 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6225 rld[i].when_needed = RELOAD_OTHER;
6227 reload_spill_index[j] = -1;
6228 transfer_replacements (i, j);
6231 /* If this is now RELOAD_OTHER, look for any reloads that load
6232 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6233 if they were for inputs, RELOAD_OTHER for outputs. Note that
6234 this test is equivalent to looking for reloads for this operand
6236 /* We must take special care with RELOAD_FOR_OUTPUT_ADDRESS; it may
6237 share registers with a RELOAD_FOR_INPUT, so we can not change it
6238 to RELOAD_FOR_OTHER_ADDRESS. We should never need to, since we
6239 do not modify RELOAD_FOR_OUTPUT. */
6241 if (rld[i].when_needed == RELOAD_OTHER)
6242 for (j = 0; j < n_reloads; j++)
6244 && rld[j].when_needed != RELOAD_OTHER
6245 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6246 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6247 && (! conflicting_input
6248 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6249 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6250 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6256 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6257 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6258 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6260 /* Check to see if we accidentally converted two
6261 reloads that use the same reload register with
6262 different inputs to the same type. If so, the
6263 resulting code won't work. */
6265 for (k = 0; k < j; k++)
6266 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6267 || rld[k].when_needed != rld[j].when_needed
6268 || !rtx_equal_p (rld[k].reg_rtx,
6270 || rtx_equal_p (rld[k].in,
6277 /* These arrays are filled by emit_reload_insns and its subroutines. */
6278 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6279 static rtx other_input_address_reload_insns = 0;
6280 static rtx other_input_reload_insns = 0;
6281 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6282 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6283 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6284 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6285 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6286 static rtx operand_reload_insns = 0;
6287 static rtx other_operand_reload_insns = 0;
6288 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6290 /* Values to be put in spill_reg_store are put here first. */
6291 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6292 static HARD_REG_SET reg_reloaded_died;
6294 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6295 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6296 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6297 adjusted register, and return true. Otherwise, return false. */
6299 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6300 enum reg_class new_class,
6301 enum machine_mode new_mode)
6306 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6308 unsigned regno = REGNO (reg);
6310 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6312 if (GET_MODE (reg) != new_mode)
6314 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6316 if (hard_regno_nregs[regno][new_mode]
6317 > hard_regno_nregs[regno][GET_MODE (reg)])
6319 reg = reload_adjust_reg_for_mode (reg, new_mode);
6327 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6328 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6329 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6330 adjusted register, and return true. Otherwise, return false. */
6332 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6333 enum insn_code icode)
6336 enum reg_class new_class = scratch_reload_class (icode);
6337 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6339 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6340 new_class, new_mode);
6343 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6344 has the number J. OLD contains the value to be used as input. */
6347 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6350 rtx insn = chain->insn;
6351 rtx reloadreg = rl->reg_rtx;
6352 rtx oldequiv_reg = 0;
6355 enum machine_mode mode;
6358 /* Determine the mode to reload in.
6359 This is very tricky because we have three to choose from.
6360 There is the mode the insn operand wants (rl->inmode).
6361 There is the mode of the reload register RELOADREG.
6362 There is the intrinsic mode of the operand, which we could find
6363 by stripping some SUBREGs.
6364 It turns out that RELOADREG's mode is irrelevant:
6365 we can change that arbitrarily.
6367 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6368 then the reload reg may not support QImode moves, so use SImode.
6369 If foo is in memory due to spilling a pseudo reg, this is safe,
6370 because the QImode value is in the least significant part of a
6371 slot big enough for a SImode. If foo is some other sort of
6372 memory reference, then it is impossible to reload this case,
6373 so previous passes had better make sure this never happens.
6375 Then consider a one-word union which has SImode and one of its
6376 members is a float, being fetched as (SUBREG:SF union:SI).
6377 We must fetch that as SFmode because we could be loading into
6378 a float-only register. In this case OLD's mode is correct.
6380 Consider an immediate integer: it has VOIDmode. Here we need
6381 to get a mode from something else.
6383 In some cases, there is a fourth mode, the operand's
6384 containing mode. If the insn specifies a containing mode for
6385 this operand, it overrides all others.
6387 I am not sure whether the algorithm here is always right,
6388 but it does the right things in those cases. */
6390 mode = GET_MODE (old);
6391 if (mode == VOIDmode)
6394 /* delete_output_reload is only invoked properly if old contains
6395 the original pseudo register. Since this is replaced with a
6396 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6397 find the pseudo in RELOAD_IN_REG. */
6398 if (reload_override_in[j]
6399 && REG_P (rl->in_reg))
6406 else if (REG_P (oldequiv))
6407 oldequiv_reg = oldequiv;
6408 else if (GET_CODE (oldequiv) == SUBREG)
6409 oldequiv_reg = SUBREG_REG (oldequiv);
6411 /* If we are reloading from a register that was recently stored in
6412 with an output-reload, see if we can prove there was
6413 actually no need to store the old value in it. */
6415 if (optimize && REG_P (oldequiv)
6416 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6417 && spill_reg_store[REGNO (oldequiv)]
6419 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6420 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6422 delete_output_reload (insn, j, REGNO (oldequiv));
6424 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6425 then load RELOADREG from OLDEQUIV. Note that we cannot use
6426 gen_lowpart_common since it can do the wrong thing when
6427 RELOADREG has a multi-word mode. Note that RELOADREG
6428 must always be a REG here. */
6430 if (GET_MODE (reloadreg) != mode)
6431 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6432 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6433 oldequiv = SUBREG_REG (oldequiv);
6434 if (GET_MODE (oldequiv) != VOIDmode
6435 && mode != GET_MODE (oldequiv))
6436 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6438 /* Switch to the right place to emit the reload insns. */
6439 switch (rl->when_needed)
6442 where = &other_input_reload_insns;
6444 case RELOAD_FOR_INPUT:
6445 where = &input_reload_insns[rl->opnum];
6447 case RELOAD_FOR_INPUT_ADDRESS:
6448 where = &input_address_reload_insns[rl->opnum];
6450 case RELOAD_FOR_INPADDR_ADDRESS:
6451 where = &inpaddr_address_reload_insns[rl->opnum];
6453 case RELOAD_FOR_OUTPUT_ADDRESS:
6454 where = &output_address_reload_insns[rl->opnum];
6456 case RELOAD_FOR_OUTADDR_ADDRESS:
6457 where = &outaddr_address_reload_insns[rl->opnum];
6459 case RELOAD_FOR_OPERAND_ADDRESS:
6460 where = &operand_reload_insns;
6462 case RELOAD_FOR_OPADDR_ADDR:
6463 where = &other_operand_reload_insns;
6465 case RELOAD_FOR_OTHER_ADDRESS:
6466 where = &other_input_address_reload_insns;
6472 push_to_sequence (*where);
6474 /* Auto-increment addresses must be reloaded in a special way. */
6475 if (rl->out && ! rl->out_reg)
6477 /* We are not going to bother supporting the case where a
6478 incremented register can't be copied directly from
6479 OLDEQUIV since this seems highly unlikely. */
6480 gcc_assert (rl->secondary_in_reload < 0);
6482 if (reload_inherited[j])
6483 oldequiv = reloadreg;
6485 old = XEXP (rl->in_reg, 0);
6487 if (optimize && REG_P (oldequiv)
6488 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6489 && spill_reg_store[REGNO (oldequiv)]
6491 && (dead_or_set_p (insn,
6492 spill_reg_stored_to[REGNO (oldequiv)])
6493 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6495 delete_output_reload (insn, j, REGNO (oldequiv));
6497 /* Prevent normal processing of this reload. */
6499 /* Output a special code sequence for this case. */
6500 new_spill_reg_store[REGNO (reloadreg)]
6501 = inc_for_reload (reloadreg, oldequiv, rl->out,
6505 /* If we are reloading a pseudo-register that was set by the previous
6506 insn, see if we can get rid of that pseudo-register entirely
6507 by redirecting the previous insn into our reload register. */
6509 else if (optimize && REG_P (old)
6510 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6511 && dead_or_set_p (insn, old)
6512 /* This is unsafe if some other reload
6513 uses the same reg first. */
6514 && ! conflicts_with_override (reloadreg)
6515 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6516 rl->when_needed, old, rl->out, j, 0))
6518 rtx temp = PREV_INSN (insn);
6519 while (temp && NOTE_P (temp))
6520 temp = PREV_INSN (temp);
6522 && NONJUMP_INSN_P (temp)
6523 && GET_CODE (PATTERN (temp)) == SET
6524 && SET_DEST (PATTERN (temp)) == old
6525 /* Make sure we can access insn_operand_constraint. */
6526 && asm_noperands (PATTERN (temp)) < 0
6527 /* This is unsafe if operand occurs more than once in current
6528 insn. Perhaps some occurrences aren't reloaded. */
6529 && count_occurrences (PATTERN (insn), old, 0) == 1)
6531 rtx old = SET_DEST (PATTERN (temp));
6532 /* Store into the reload register instead of the pseudo. */
6533 SET_DEST (PATTERN (temp)) = reloadreg;
6535 /* Verify that resulting insn is valid. */
6536 extract_insn (temp);
6537 if (constrain_operands (1))
6539 /* If the previous insn is an output reload, the source is
6540 a reload register, and its spill_reg_store entry will
6541 contain the previous destination. This is now
6543 if (REG_P (SET_SRC (PATTERN (temp)))
6544 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6546 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6547 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6550 /* If these are the only uses of the pseudo reg,
6551 pretend for GDB it lives in the reload reg we used. */
6552 if (REG_N_DEATHS (REGNO (old)) == 1
6553 && REG_N_SETS (REGNO (old)) == 1)
6555 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6556 alter_reg (REGNO (old), -1);
6562 SET_DEST (PATTERN (temp)) = old;
6567 /* We can't do that, so output an insn to load RELOADREG. */
6569 /* If we have a secondary reload, pick up the secondary register
6570 and icode, if any. If OLDEQUIV and OLD are different or
6571 if this is an in-out reload, recompute whether or not we
6572 still need a secondary register and what the icode should
6573 be. If we still need a secondary register and the class or
6574 icode is different, go back to reloading from OLD if using
6575 OLDEQUIV means that we got the wrong type of register. We
6576 cannot have different class or icode due to an in-out reload
6577 because we don't make such reloads when both the input and
6578 output need secondary reload registers. */
6580 if (! special && rl->secondary_in_reload >= 0)
6582 rtx second_reload_reg = 0;
6583 rtx third_reload_reg = 0;
6584 int secondary_reload = rl->secondary_in_reload;
6585 rtx real_oldequiv = oldequiv;
6588 enum insn_code icode;
6589 enum insn_code tertiary_icode = CODE_FOR_nothing;
6591 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6592 and similarly for OLD.
6593 See comments in get_secondary_reload in reload.c. */
6594 /* If it is a pseudo that cannot be replaced with its
6595 equivalent MEM, we must fall back to reload_in, which
6596 will have all the necessary substitutions registered.
6597 Likewise for a pseudo that can't be replaced with its
6598 equivalent constant.
6600 Take extra care for subregs of such pseudos. Note that
6601 we cannot use reg_equiv_mem in this case because it is
6602 not in the right mode. */
6605 if (GET_CODE (tmp) == SUBREG)
6606 tmp = SUBREG_REG (tmp);
6608 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6609 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6610 || reg_equiv_constant[REGNO (tmp)] != 0))
6612 if (! reg_equiv_mem[REGNO (tmp)]
6613 || num_not_at_initial_offset
6614 || GET_CODE (oldequiv) == SUBREG)
6615 real_oldequiv = rl->in;
6617 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6621 if (GET_CODE (tmp) == SUBREG)
6622 tmp = SUBREG_REG (tmp);
6624 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6625 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6626 || reg_equiv_constant[REGNO (tmp)] != 0))
6628 if (! reg_equiv_mem[REGNO (tmp)]
6629 || num_not_at_initial_offset
6630 || GET_CODE (old) == SUBREG)
6633 real_old = reg_equiv_mem[REGNO (tmp)];
6636 second_reload_reg = rld[secondary_reload].reg_rtx;
6637 if (rld[secondary_reload].secondary_in_reload >= 0)
6639 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
6641 third_reload_reg = rld[tertiary_reload].reg_rtx;
6642 tertiary_icode = rld[secondary_reload].secondary_in_icode;
6643 /* We'd have to add more code for quartary reloads. */
6644 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
6646 icode = rl->secondary_in_icode;
6648 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6649 || (rl->in != 0 && rl->out != 0))
6651 secondary_reload_info sri, sri2;
6652 enum reg_class new_class, new_t_class;
6654 sri.icode = CODE_FOR_nothing;
6655 sri.prev_sri = NULL;
6656 new_class = targetm.secondary_reload (1, real_oldequiv, rl->class,
6659 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
6660 second_reload_reg = 0;
6661 else if (new_class == NO_REGS)
6663 if (reload_adjust_reg_for_icode (&second_reload_reg,
6664 third_reload_reg, sri.icode))
6665 icode = sri.icode, third_reload_reg = 0;
6667 oldequiv = old, real_oldequiv = real_old;
6669 else if (sri.icode != CODE_FOR_nothing)
6670 /* We currently lack a way to express this in reloads. */
6674 sri2.icode = CODE_FOR_nothing;
6675 sri2.prev_sri = &sri;
6676 new_t_class = targetm.secondary_reload (1, real_oldequiv,
6677 new_class, mode, &sri);
6678 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
6680 if (reload_adjust_reg_for_temp (&second_reload_reg,
6683 third_reload_reg = 0, tertiary_icode = sri2.icode;
6685 oldequiv = old, real_oldequiv = real_old;
6687 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
6689 rtx intermediate = second_reload_reg;
6691 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6693 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
6696 second_reload_reg = intermediate;
6697 tertiary_icode = sri2.icode;
6700 oldequiv = old, real_oldequiv = real_old;
6702 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
6704 rtx intermediate = second_reload_reg;
6706 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6708 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
6711 second_reload_reg = intermediate;
6712 tertiary_icode = sri2.icode;
6715 oldequiv = old, real_oldequiv = real_old;
6718 /* This could be handled more intelligently too. */
6719 oldequiv = old, real_oldequiv = real_old;
6723 /* If we still need a secondary reload register, check
6724 to see if it is being used as a scratch or intermediate
6725 register and generate code appropriately. If we need
6726 a scratch register, use REAL_OLDEQUIV since the form of
6727 the insn may depend on the actual address if it is
6730 if (second_reload_reg)
6732 if (icode != CODE_FOR_nothing)
6734 /* We'd have to add extra code to handle this case. */
6735 gcc_assert (!third_reload_reg);
6737 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6738 second_reload_reg));
6743 /* See if we need a scratch register to load the
6744 intermediate register (a tertiary reload). */
6745 if (tertiary_icode != CODE_FOR_nothing)
6747 emit_insn ((GEN_FCN (tertiary_icode)
6748 (second_reload_reg, real_oldequiv,
6749 third_reload_reg)));
6751 else if (third_reload_reg)
6753 gen_reload (third_reload_reg, real_oldequiv,
6756 gen_reload (second_reload_reg, third_reload_reg,
6761 gen_reload (second_reload_reg, real_oldequiv,
6765 oldequiv = second_reload_reg;
6770 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6772 rtx real_oldequiv = oldequiv;
6774 if ((REG_P (oldequiv)
6775 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6776 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6777 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6778 || (GET_CODE (oldequiv) == SUBREG
6779 && REG_P (SUBREG_REG (oldequiv))
6780 && (REGNO (SUBREG_REG (oldequiv))
6781 >= FIRST_PSEUDO_REGISTER)
6782 && ((reg_equiv_memory_loc
6783 [REGNO (SUBREG_REG (oldequiv))] != 0)
6784 || (reg_equiv_constant
6785 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6786 || (CONSTANT_P (oldequiv)
6787 && (PREFERRED_RELOAD_CLASS (oldequiv,
6788 REGNO_REG_CLASS (REGNO (reloadreg)))
6790 real_oldequiv = rl->in;
6791 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6795 if (flag_non_call_exceptions)
6796 copy_eh_notes (insn, get_insns ());
6798 /* End this sequence. */
6799 *where = get_insns ();
6802 /* Update reload_override_in so that delete_address_reloads_1
6803 can see the actual register usage. */
6805 reload_override_in[j] = oldequiv;
6808 /* Generate insns to for the output reload RL, which is for the insn described
6809 by CHAIN and has the number J. */
6811 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6814 rtx reloadreg = rl->reg_rtx;
6815 rtx insn = chain->insn;
6818 enum machine_mode mode = GET_MODE (old);
6821 if (rl->when_needed == RELOAD_OTHER)
6824 push_to_sequence (output_reload_insns[rl->opnum]);
6826 /* Determine the mode to reload in.
6827 See comments above (for input reloading). */
6829 if (mode == VOIDmode)
6831 /* VOIDmode should never happen for an output. */
6832 if (asm_noperands (PATTERN (insn)) < 0)
6833 /* It's the compiler's fault. */
6834 fatal_insn ("VOIDmode on an output", insn);
6835 error_for_asm (insn, "output operand is constant in %<asm%>");
6836 /* Prevent crash--use something we know is valid. */
6838 old = gen_rtx_REG (mode, REGNO (reloadreg));
6841 if (GET_MODE (reloadreg) != mode)
6842 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6844 /* If we need two reload regs, set RELOADREG to the intermediate
6845 one, since it will be stored into OLD. We might need a secondary
6846 register only for an input reload, so check again here. */
6848 if (rl->secondary_out_reload >= 0)
6851 int secondary_reload = rl->secondary_out_reload;
6852 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
6854 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
6855 && reg_equiv_mem[REGNO (old)] != 0)
6856 real_old = reg_equiv_mem[REGNO (old)];
6858 if (secondary_reload_class (0, rl->class, mode, real_old) != NO_REGS)
6860 rtx second_reloadreg = reloadreg;
6861 reloadreg = rld[secondary_reload].reg_rtx;
6863 /* See if RELOADREG is to be used as a scratch register
6864 or as an intermediate register. */
6865 if (rl->secondary_out_icode != CODE_FOR_nothing)
6867 /* We'd have to add extra code to handle this case. */
6868 gcc_assert (tertiary_reload < 0);
6870 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6871 (real_old, second_reloadreg, reloadreg)));
6876 /* See if we need both a scratch and intermediate reload
6879 enum insn_code tertiary_icode
6880 = rld[secondary_reload].secondary_out_icode;
6882 /* We'd have to add more code for quartary reloads. */
6883 gcc_assert (tertiary_reload < 0
6884 || rld[tertiary_reload].secondary_out_reload < 0);
6886 if (GET_MODE (reloadreg) != mode)
6887 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6889 if (tertiary_icode != CODE_FOR_nothing)
6891 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
6894 /* Copy primary reload reg to secondary reload reg.
6895 (Note that these have been swapped above, then
6896 secondary reload reg to OLD using our insn.) */
6898 /* If REAL_OLD is a paradoxical SUBREG, remove it
6899 and try to put the opposite SUBREG on
6901 if (GET_CODE (real_old) == SUBREG
6902 && (GET_MODE_SIZE (GET_MODE (real_old))
6903 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6904 && 0 != (tem = gen_lowpart_common
6905 (GET_MODE (SUBREG_REG (real_old)),
6907 real_old = SUBREG_REG (real_old), reloadreg = tem;
6909 gen_reload (reloadreg, second_reloadreg,
6910 rl->opnum, rl->when_needed);
6911 emit_insn ((GEN_FCN (tertiary_icode)
6912 (real_old, reloadreg, third_reloadreg)));
6918 /* Copy between the reload regs here and then to
6921 gen_reload (reloadreg, second_reloadreg,
6922 rl->opnum, rl->when_needed);
6923 if (tertiary_reload >= 0)
6925 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
6927 gen_reload (third_reloadreg, reloadreg,
6928 rl->opnum, rl->when_needed);
6929 reloadreg = third_reloadreg;
6936 /* Output the last reload insn. */
6941 /* Don't output the last reload if OLD is not the dest of
6942 INSN and is in the src and is clobbered by INSN. */
6943 if (! flag_expensive_optimizations
6945 || !(set = single_set (insn))
6946 || rtx_equal_p (old, SET_DEST (set))
6947 || !reg_mentioned_p (old, SET_SRC (set))
6948 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
6949 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
6950 gen_reload (old, reloadreg, rl->opnum,
6954 /* Look at all insns we emitted, just to be safe. */
6955 for (p = get_insns (); p; p = NEXT_INSN (p))
6958 rtx pat = PATTERN (p);
6960 /* If this output reload doesn't come from a spill reg,
6961 clear any memory of reloaded copies of the pseudo reg.
6962 If this output reload comes from a spill reg,
6963 reg_has_output_reload will make this do nothing. */
6964 note_stores (pat, forget_old_reloads_1, NULL);
6966 if (reg_mentioned_p (rl->reg_rtx, pat))
6968 rtx set = single_set (insn);
6969 if (reload_spill_index[j] < 0
6971 && SET_SRC (set) == rl->reg_rtx)
6973 int src = REGNO (SET_SRC (set));
6975 reload_spill_index[j] = src;
6976 SET_HARD_REG_BIT (reg_is_output_reload, src);
6977 if (find_regno_note (insn, REG_DEAD, src))
6978 SET_HARD_REG_BIT (reg_reloaded_died, src);
6980 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6982 int s = rl->secondary_out_reload;
6983 set = single_set (p);
6984 /* If this reload copies only to the secondary reload
6985 register, the secondary reload does the actual
6987 if (s >= 0 && set == NULL_RTX)
6988 /* We can't tell what function the secondary reload
6989 has and where the actual store to the pseudo is
6990 made; leave new_spill_reg_store alone. */
6993 && SET_SRC (set) == rl->reg_rtx
6994 && SET_DEST (set) == rld[s].reg_rtx)
6996 /* Usually the next instruction will be the
6997 secondary reload insn; if we can confirm
6998 that it is, setting new_spill_reg_store to
6999 that insn will allow an extra optimization. */
7000 rtx s_reg = rld[s].reg_rtx;
7001 rtx next = NEXT_INSN (p);
7002 rld[s].out = rl->out;
7003 rld[s].out_reg = rl->out_reg;
7004 set = single_set (next);
7005 if (set && SET_SRC (set) == s_reg
7006 && ! new_spill_reg_store[REGNO (s_reg)])
7008 SET_HARD_REG_BIT (reg_is_output_reload,
7010 new_spill_reg_store[REGNO (s_reg)] = next;
7014 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
7019 if (rl->when_needed == RELOAD_OTHER)
7021 emit_insn (other_output_reload_insns[rl->opnum]);
7022 other_output_reload_insns[rl->opnum] = get_insns ();
7025 output_reload_insns[rl->opnum] = get_insns ();
7027 if (flag_non_call_exceptions)
7028 copy_eh_notes (insn, get_insns ());
7033 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7034 and has the number J. */
7036 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7038 rtx insn = chain->insn;
7039 rtx old = (rl->in && MEM_P (rl->in)
7040 ? rl->in_reg : rl->in);
7043 /* AUTO_INC reloads need to be handled even if inherited. We got an
7044 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7045 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7046 && ! rtx_equal_p (rl->reg_rtx, old)
7047 && rl->reg_rtx != 0)
7048 emit_input_reload_insns (chain, rld + j, old, j);
7050 /* When inheriting a wider reload, we have a MEM in rl->in,
7051 e.g. inheriting a SImode output reload for
7052 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7053 if (optimize && reload_inherited[j] && rl->in
7055 && MEM_P (rl->in_reg)
7056 && reload_spill_index[j] >= 0
7057 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7058 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7060 /* If we are reloading a register that was recently stored in with an
7061 output-reload, see if we can prove there was
7062 actually no need to store the old value in it. */
7065 /* Only attempt this for input reloads; for RELOAD_OTHER we miss
7066 that there may be multiple uses of the previous output reload.
7067 Restricting to RELOAD_FOR_INPUT is mostly paranoia. */
7068 && rl->when_needed == RELOAD_FOR_INPUT
7069 && (reload_inherited[j] || reload_override_in[j])
7071 && REG_P (rl->reg_rtx)
7072 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
7074 /* There doesn't seem to be any reason to restrict this to pseudos
7075 and doing so loses in the case where we are copying from a
7076 register of the wrong class. */
7077 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
7078 >= FIRST_PSEUDO_REGISTER)
7080 /* The insn might have already some references to stackslots
7081 replaced by MEMs, while reload_out_reg still names the
7083 && (dead_or_set_p (insn,
7084 spill_reg_stored_to[REGNO (rl->reg_rtx)])
7085 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
7087 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
7090 /* Do output reloading for reload RL, which is for the insn described by
7091 CHAIN and has the number J.
7092 ??? At some point we need to support handling output reloads of
7093 JUMP_INSNs or insns that set cc0. */
7095 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7098 rtx insn = chain->insn;
7099 /* If this is an output reload that stores something that is
7100 not loaded in this same reload, see if we can eliminate a previous
7102 rtx pseudo = rl->out_reg;
7107 && ! rtx_equal_p (rl->in_reg, pseudo)
7108 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7109 && reg_last_reload_reg[REGNO (pseudo)])
7111 int pseudo_no = REGNO (pseudo);
7112 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7114 /* We don't need to test full validity of last_regno for
7115 inherit here; we only want to know if the store actually
7116 matches the pseudo. */
7117 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7118 && reg_reloaded_contents[last_regno] == pseudo_no
7119 && spill_reg_store[last_regno]
7120 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7121 delete_output_reload (insn, j, last_regno);
7126 || rl->reg_rtx == old
7127 || rl->reg_rtx == 0)
7130 /* An output operand that dies right away does need a reload,
7131 but need not be copied from it. Show the new location in the
7133 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7134 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7136 XEXP (note, 0) = rl->reg_rtx;
7139 /* Likewise for a SUBREG of an operand that dies. */
7140 else if (GET_CODE (old) == SUBREG
7141 && REG_P (SUBREG_REG (old))
7142 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7145 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7149 else if (GET_CODE (old) == SCRATCH)
7150 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7151 but we don't want to make an output reload. */
7154 /* If is a JUMP_INSN, we can't support output reloads yet. */
7155 gcc_assert (NONJUMP_INSN_P (insn));
7157 emit_output_reload_insns (chain, rld + j, j);
7160 /* Reload number R reloads from or to a group of hard registers starting at
7161 register REGNO. Return true if it can be treated for inheritance purposes
7162 like a group of reloads, each one reloading a single hard register.
7163 The caller has already checked that the spill register and REGNO use
7164 the same number of registers to store the reload value. */
7167 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
7169 #ifdef CANNOT_CHANGE_MODE_CLASS
7170 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
7171 GET_MODE (rld[r].reg_rtx),
7172 reg_raw_mode[reload_spill_index[r]])
7173 && !REG_CANNOT_CHANGE_MODE_P (regno,
7174 GET_MODE (rld[r].reg_rtx),
7175 reg_raw_mode[regno]));
7181 /* Output insns to reload values in and out of the chosen reload regs. */
7184 emit_reload_insns (struct insn_chain *chain)
7186 rtx insn = chain->insn;
7190 CLEAR_HARD_REG_SET (reg_reloaded_died);
7192 for (j = 0; j < reload_n_operands; j++)
7193 input_reload_insns[j] = input_address_reload_insns[j]
7194 = inpaddr_address_reload_insns[j]
7195 = output_reload_insns[j] = output_address_reload_insns[j]
7196 = outaddr_address_reload_insns[j]
7197 = other_output_reload_insns[j] = 0;
7198 other_input_address_reload_insns = 0;
7199 other_input_reload_insns = 0;
7200 operand_reload_insns = 0;
7201 other_operand_reload_insns = 0;
7203 /* Dump reloads into the dump file. */
7206 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7207 debug_reload_to_stream (dump_file);
7210 /* Now output the instructions to copy the data into and out of the
7211 reload registers. Do these in the order that the reloads were reported,
7212 since reloads of base and index registers precede reloads of operands
7213 and the operands may need the base and index registers reloaded. */
7215 for (j = 0; j < n_reloads; j++)
7218 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7219 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7221 do_input_reload (chain, rld + j, j);
7222 do_output_reload (chain, rld + j, j);
7225 /* Now write all the insns we made for reloads in the order expected by
7226 the allocation functions. Prior to the insn being reloaded, we write
7227 the following reloads:
7229 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7231 RELOAD_OTHER reloads.
7233 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7234 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7235 RELOAD_FOR_INPUT reload for the operand.
7237 RELOAD_FOR_OPADDR_ADDRS reloads.
7239 RELOAD_FOR_OPERAND_ADDRESS reloads.
7241 After the insn being reloaded, we write the following:
7243 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7244 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7245 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7246 reloads for the operand. The RELOAD_OTHER output reloads are
7247 output in descending order by reload number. */
7249 emit_insn_before (other_input_address_reload_insns, insn);
7250 emit_insn_before (other_input_reload_insns, insn);
7252 for (j = 0; j < reload_n_operands; j++)
7254 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7255 emit_insn_before (input_address_reload_insns[j], insn);
7256 emit_insn_before (input_reload_insns[j], insn);
7259 emit_insn_before (other_operand_reload_insns, insn);
7260 emit_insn_before (operand_reload_insns, insn);
7262 for (j = 0; j < reload_n_operands; j++)
7264 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7265 x = emit_insn_after (output_address_reload_insns[j], x);
7266 x = emit_insn_after (output_reload_insns[j], x);
7267 emit_insn_after (other_output_reload_insns[j], x);
7270 /* For all the spill regs newly reloaded in this instruction,
7271 record what they were reloaded from, so subsequent instructions
7272 can inherit the reloads.
7274 Update spill_reg_store for the reloads of this insn.
7275 Copy the elements that were updated in the loop above. */
7277 for (j = 0; j < n_reloads; j++)
7279 int r = reload_order[j];
7280 int i = reload_spill_index[r];
7282 /* If this is a non-inherited input reload from a pseudo, we must
7283 clear any memory of a previous store to the same pseudo. Only do
7284 something if there will not be an output reload for the pseudo
7286 if (rld[r].in_reg != 0
7287 && ! (reload_inherited[r] || reload_override_in[r]))
7289 rtx reg = rld[r].in_reg;
7291 if (GET_CODE (reg) == SUBREG)
7292 reg = SUBREG_REG (reg);
7295 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7296 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7298 int nregno = REGNO (reg);
7300 if (reg_last_reload_reg[nregno])
7302 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7304 if (reg_reloaded_contents[last_regno] == nregno)
7305 spill_reg_store[last_regno] = 0;
7310 /* I is nonneg if this reload used a register.
7311 If rld[r].reg_rtx is 0, this is an optional reload
7312 that we opted to ignore. */
7314 if (i >= 0 && rld[r].reg_rtx != 0)
7316 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7318 int part_reaches_end = 0;
7319 int all_reaches_end = 1;
7321 /* For a multi register reload, we need to check if all or part
7322 of the value lives to the end. */
7323 for (k = 0; k < nr; k++)
7325 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7326 rld[r].when_needed))
7327 part_reaches_end = 1;
7329 all_reaches_end = 0;
7332 /* Ignore reloads that don't reach the end of the insn in
7334 if (all_reaches_end)
7336 /* First, clear out memory of what used to be in this spill reg.
7337 If consecutive registers are used, clear them all. */
7339 for (k = 0; k < nr; k++)
7341 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7342 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7345 /* Maybe the spill reg contains a copy of reload_out. */
7347 && (REG_P (rld[r].out)
7351 || REG_P (rld[r].out_reg)))
7353 rtx out = (REG_P (rld[r].out)
7357 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7358 int nregno = REGNO (out);
7359 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7360 : hard_regno_nregs[nregno]
7361 [GET_MODE (rld[r].reg_rtx)]);
7364 spill_reg_store[i] = new_spill_reg_store[i];
7365 spill_reg_stored_to[i] = out;
7366 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7368 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7370 && inherit_piecemeal_p (r, nregno));
7372 /* If NREGNO is a hard register, it may occupy more than
7373 one register. If it does, say what is in the
7374 rest of the registers assuming that both registers
7375 agree on how many words the object takes. If not,
7376 invalidate the subsequent registers. */
7378 if (nregno < FIRST_PSEUDO_REGISTER)
7379 for (k = 1; k < nnr; k++)
7380 reg_last_reload_reg[nregno + k]
7382 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7385 /* Now do the inverse operation. */
7386 for (k = 0; k < nr; k++)
7388 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7389 reg_reloaded_contents[i + k]
7390 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7393 reg_reloaded_insn[i + k] = insn;
7394 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7395 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7396 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7400 /* Maybe the spill reg contains a copy of reload_in. Only do
7401 something if there will not be an output reload for
7402 the register being reloaded. */
7403 else if (rld[r].out_reg == 0
7405 && ((REG_P (rld[r].in)
7406 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7407 && !REGNO_REG_SET_P (®_has_output_reload,
7409 || (REG_P (rld[r].in_reg)
7410 && !REGNO_REG_SET_P (®_has_output_reload,
7411 REGNO (rld[r].in_reg))))
7412 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7419 if (REG_P (rld[r].in)
7420 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7422 else if (REG_P (rld[r].in_reg))
7425 in = XEXP (rld[r].in_reg, 0);
7426 nregno = REGNO (in);
7428 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7429 : hard_regno_nregs[nregno]
7430 [GET_MODE (rld[r].reg_rtx)]);
7432 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7434 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7436 && inherit_piecemeal_p (r, nregno));
7438 if (nregno < FIRST_PSEUDO_REGISTER)
7439 for (k = 1; k < nnr; k++)
7440 reg_last_reload_reg[nregno + k]
7442 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7445 /* Unless we inherited this reload, show we haven't
7446 recently done a store.
7447 Previous stores of inherited auto_inc expressions
7448 also have to be discarded. */
7449 if (! reload_inherited[r]
7450 || (rld[r].out && ! rld[r].out_reg))
7451 spill_reg_store[i] = 0;
7453 for (k = 0; k < nr; k++)
7455 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7456 reg_reloaded_contents[i + k]
7457 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7460 reg_reloaded_insn[i + k] = insn;
7461 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7462 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7463 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7468 /* However, if part of the reload reaches the end, then we must
7469 invalidate the old info for the part that survives to the end. */
7470 else if (part_reaches_end)
7472 for (k = 0; k < nr; k++)
7473 if (reload_reg_reaches_end_p (i + k,
7475 rld[r].when_needed))
7476 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7480 /* The following if-statement was #if 0'd in 1.34 (or before...).
7481 It's reenabled in 1.35 because supposedly nothing else
7482 deals with this problem. */
7484 /* If a register gets output-reloaded from a non-spill register,
7485 that invalidates any previous reloaded copy of it.
7486 But forget_old_reloads_1 won't get to see it, because
7487 it thinks only about the original insn. So invalidate it here.
7488 Also do the same thing for RELOAD_OTHER constraints where the
7489 output is discarded. */
7491 && ((rld[r].out != 0
7492 && (REG_P (rld[r].out)
7493 || (MEM_P (rld[r].out)
7494 && REG_P (rld[r].out_reg))))
7495 || (rld[r].out == 0 && rld[r].out_reg
7496 && REG_P (rld[r].out_reg))))
7498 rtx out = ((rld[r].out && REG_P (rld[r].out))
7499 ? rld[r].out : rld[r].out_reg);
7500 int nregno = REGNO (out);
7501 if (nregno >= FIRST_PSEUDO_REGISTER)
7503 rtx src_reg, store_insn = NULL_RTX;
7505 reg_last_reload_reg[nregno] = 0;
7507 /* If we can find a hard register that is stored, record
7508 the storing insn so that we may delete this insn with
7509 delete_output_reload. */
7510 src_reg = rld[r].reg_rtx;
7512 /* If this is an optional reload, try to find the source reg
7513 from an input reload. */
7516 rtx set = single_set (insn);
7517 if (set && SET_DEST (set) == rld[r].out)
7521 src_reg = SET_SRC (set);
7523 for (k = 0; k < n_reloads; k++)
7525 if (rld[k].in == src_reg)
7527 src_reg = rld[k].reg_rtx;
7534 store_insn = new_spill_reg_store[REGNO (src_reg)];
7535 if (src_reg && REG_P (src_reg)
7536 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7538 int src_regno = REGNO (src_reg);
7539 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7540 /* The place where to find a death note varies with
7541 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7542 necessarily checked exactly in the code that moves
7543 notes, so just check both locations. */
7544 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7545 if (! note && store_insn)
7546 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7549 spill_reg_store[src_regno + nr] = store_insn;
7550 spill_reg_stored_to[src_regno + nr] = out;
7551 reg_reloaded_contents[src_regno + nr] = nregno;
7552 reg_reloaded_insn[src_regno + nr] = store_insn;
7553 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7554 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7555 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7556 GET_MODE (src_reg)))
7557 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7559 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7561 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7563 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7565 reg_last_reload_reg[nregno] = src_reg;
7566 /* We have to set reg_has_output_reload here, or else
7567 forget_old_reloads_1 will clear reg_last_reload_reg
7569 SET_REGNO_REG_SET (®_has_output_reload,
7575 int num_regs = hard_regno_nregs[nregno][GET_MODE (out)];
7577 while (num_regs-- > 0)
7578 reg_last_reload_reg[nregno + num_regs] = 0;
7582 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7585 /* Go through the motions to emit INSN and test if it is strictly valid.
7586 Return the emitted insn if valid, else return NULL. */
7589 emit_insn_if_valid_for_reload (rtx insn)
7591 rtx last = get_last_insn ();
7594 insn = emit_insn (insn);
7595 code = recog_memoized (insn);
7599 extract_insn (insn);
7600 /* We want constrain operands to treat this insn strictly in its
7601 validity determination, i.e., the way it would after reload has
7603 if (constrain_operands (1))
7607 delete_insns_since (last);
7611 /* Emit code to perform a reload from IN (which may be a reload register) to
7612 OUT (which may also be a reload register). IN or OUT is from operand
7613 OPNUM with reload type TYPE.
7615 Returns first insn emitted. */
7618 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7620 rtx last = get_last_insn ();
7623 /* If IN is a paradoxical SUBREG, remove it and try to put the
7624 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7625 if (GET_CODE (in) == SUBREG
7626 && (GET_MODE_SIZE (GET_MODE (in))
7627 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7628 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7629 in = SUBREG_REG (in), out = tem;
7630 else if (GET_CODE (out) == SUBREG
7631 && (GET_MODE_SIZE (GET_MODE (out))
7632 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7633 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7634 out = SUBREG_REG (out), in = tem;
7636 /* How to do this reload can get quite tricky. Normally, we are being
7637 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7638 register that didn't get a hard register. In that case we can just
7639 call emit_move_insn.
7641 We can also be asked to reload a PLUS that adds a register or a MEM to
7642 another register, constant or MEM. This can occur during frame pointer
7643 elimination and while reloading addresses. This case is handled by
7644 trying to emit a single insn to perform the add. If it is not valid,
7645 we use a two insn sequence.
7647 Or we can be asked to reload an unary operand that was a fragment of
7648 an addressing mode, into a register. If it isn't recognized as-is,
7649 we try making the unop operand and the reload-register the same:
7650 (set reg:X (unop:X expr:Y))
7651 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
7653 Finally, we could be called to handle an 'o' constraint by putting
7654 an address into a register. In that case, we first try to do this
7655 with a named pattern of "reload_load_address". If no such pattern
7656 exists, we just emit a SET insn and hope for the best (it will normally
7657 be valid on machines that use 'o').
7659 This entire process is made complex because reload will never
7660 process the insns we generate here and so we must ensure that
7661 they will fit their constraints and also by the fact that parts of
7662 IN might be being reloaded separately and replaced with spill registers.
7663 Because of this, we are, in some sense, just guessing the right approach
7664 here. The one listed above seems to work.
7666 ??? At some point, this whole thing needs to be rethought. */
7668 if (GET_CODE (in) == PLUS
7669 && (REG_P (XEXP (in, 0))
7670 || GET_CODE (XEXP (in, 0)) == SUBREG
7671 || MEM_P (XEXP (in, 0)))
7672 && (REG_P (XEXP (in, 1))
7673 || GET_CODE (XEXP (in, 1)) == SUBREG
7674 || CONSTANT_P (XEXP (in, 1))
7675 || MEM_P (XEXP (in, 1))))
7677 /* We need to compute the sum of a register or a MEM and another
7678 register, constant, or MEM, and put it into the reload
7679 register. The best possible way of doing this is if the machine
7680 has a three-operand ADD insn that accepts the required operands.
7682 The simplest approach is to try to generate such an insn and see if it
7683 is recognized and matches its constraints. If so, it can be used.
7685 It might be better not to actually emit the insn unless it is valid,
7686 but we need to pass the insn as an operand to `recog' and
7687 `extract_insn' and it is simpler to emit and then delete the insn if
7688 not valid than to dummy things up. */
7690 rtx op0, op1, tem, insn;
7693 op0 = find_replacement (&XEXP (in, 0));
7694 op1 = find_replacement (&XEXP (in, 1));
7696 /* Since constraint checking is strict, commutativity won't be
7697 checked, so we need to do that here to avoid spurious failure
7698 if the add instruction is two-address and the second operand
7699 of the add is the same as the reload reg, which is frequently
7700 the case. If the insn would be A = B + A, rearrange it so
7701 it will be A = A + B as constrain_operands expects. */
7703 if (REG_P (XEXP (in, 1))
7704 && REGNO (out) == REGNO (XEXP (in, 1)))
7705 tem = op0, op0 = op1, op1 = tem;
7707 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7708 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7710 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7714 /* If that failed, we must use a conservative two-insn sequence.
7716 Use a move to copy one operand into the reload register. Prefer
7717 to reload a constant, MEM or pseudo since the move patterns can
7718 handle an arbitrary operand. If OP1 is not a constant, MEM or
7719 pseudo and OP1 is not a valid operand for an add instruction, then
7722 After reloading one of the operands into the reload register, add
7723 the reload register to the output register.
7725 If there is another way to do this for a specific machine, a
7726 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7729 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7731 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7733 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7734 || (code != CODE_FOR_nothing
7735 && ! ((*insn_data[code].operand[2].predicate)
7736 (op1, insn_data[code].operand[2].mode))))
7737 tem = op0, op0 = op1, op1 = tem;
7739 gen_reload (out, op0, opnum, type);
7741 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7742 This fixes a problem on the 32K where the stack pointer cannot
7743 be used as an operand of an add insn. */
7745 if (rtx_equal_p (op0, op1))
7748 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
7751 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7753 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7757 /* If that failed, copy the address register to the reload register.
7758 Then add the constant to the reload register. */
7760 gen_reload (out, op1, opnum, type);
7761 insn = emit_insn (gen_add2_insn (out, op0));
7762 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7765 #ifdef SECONDARY_MEMORY_NEEDED
7766 /* If we need a memory location to do the move, do it that way. */
7767 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7768 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7769 && (REG_P (out) || GET_CODE (out) == SUBREG)
7770 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7771 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7772 REGNO_REG_CLASS (reg_or_subregno (out)),
7775 /* Get the memory to use and rewrite both registers to its mode. */
7776 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7778 if (GET_MODE (loc) != GET_MODE (out))
7779 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7781 if (GET_MODE (loc) != GET_MODE (in))
7782 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7784 gen_reload (loc, in, opnum, type);
7785 gen_reload (out, loc, opnum, type);
7788 else if (REG_P (out) && UNARY_P (in))
7795 op1 = find_replacement (&XEXP (in, 0));
7796 if (op1 != XEXP (in, 0))
7797 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
7799 /* First, try a plain SET. */
7800 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7804 /* If that failed, move the inner operand to the reload
7805 register, and try the same unop with the inner expression
7806 replaced with the reload register. */
7808 if (GET_MODE (op1) != GET_MODE (out))
7809 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
7813 gen_reload (out_moded, op1, opnum, type);
7816 = gen_rtx_SET (VOIDmode, out,
7817 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
7819 insn = emit_insn_if_valid_for_reload (insn);
7823 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7827 fatal_insn ("Failure trying to reload:", set);
7829 /* If IN is a simple operand, use gen_move_insn. */
7830 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
7832 tem = emit_insn (gen_move_insn (out, in));
7833 /* IN may contain a LABEL_REF, if so add a REG_LABEL note. */
7834 mark_jump_label (in, tem, 0);
7837 #ifdef HAVE_reload_load_address
7838 else if (HAVE_reload_load_address)
7839 emit_insn (gen_reload_load_address (out, in));
7842 /* Otherwise, just write (set OUT IN) and hope for the best. */
7844 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7846 /* Return the first insn emitted.
7847 We can not just return get_last_insn, because there may have
7848 been multiple instructions emitted. Also note that gen_move_insn may
7849 emit more than one insn itself, so we can not assume that there is one
7850 insn emitted per emit_insn_before call. */
7852 return last ? NEXT_INSN (last) : get_insns ();
7855 /* Delete a previously made output-reload whose result we now believe
7856 is not needed. First we double-check.
7858 INSN is the insn now being processed.
7859 LAST_RELOAD_REG is the hard register number for which we want to delete
7860 the last output reload.
7861 J is the reload-number that originally used REG. The caller has made
7862 certain that reload J doesn't use REG any longer for input. */
7865 delete_output_reload (rtx insn, int j, int last_reload_reg)
7867 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7868 rtx reg = spill_reg_stored_to[last_reload_reg];
7871 int n_inherited = 0;
7875 /* It is possible that this reload has been only used to set another reload
7876 we eliminated earlier and thus deleted this instruction too. */
7877 if (INSN_DELETED_P (output_reload_insn))
7880 /* Get the raw pseudo-register referred to. */
7882 while (GET_CODE (reg) == SUBREG)
7883 reg = SUBREG_REG (reg);
7884 substed = reg_equiv_memory_loc[REGNO (reg)];
7886 /* This is unsafe if the operand occurs more often in the current
7887 insn than it is inherited. */
7888 for (k = n_reloads - 1; k >= 0; k--)
7890 rtx reg2 = rld[k].in;
7893 if (MEM_P (reg2) || reload_override_in[k])
7894 reg2 = rld[k].in_reg;
7896 if (rld[k].out && ! rld[k].out_reg)
7897 reg2 = XEXP (rld[k].in_reg, 0);
7899 while (GET_CODE (reg2) == SUBREG)
7900 reg2 = SUBREG_REG (reg2);
7901 if (rtx_equal_p (reg2, reg))
7903 if (reload_inherited[k] || reload_override_in[k] || k == j)
7906 reg2 = rld[k].out_reg;
7909 while (GET_CODE (reg2) == SUBREG)
7910 reg2 = XEXP (reg2, 0);
7911 if (rtx_equal_p (reg2, reg))
7918 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7920 n_occurrences += count_occurrences (PATTERN (insn),
7921 eliminate_regs (substed, 0,
7923 for (i1 = reg_equiv_alt_mem_list [REGNO (reg)]; i1; i1 = XEXP (i1, 1))
7925 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
7926 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
7928 if (n_occurrences > n_inherited)
7931 /* If the pseudo-reg we are reloading is no longer referenced
7932 anywhere between the store into it and here,
7933 and we're within the same basic block, then the value can only
7934 pass through the reload reg and end up here.
7935 Otherwise, give up--return. */
7936 for (i1 = NEXT_INSN (output_reload_insn);
7937 i1 != insn; i1 = NEXT_INSN (i1))
7939 if (NOTE_INSN_BASIC_BLOCK_P (i1))
7941 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
7942 && reg_mentioned_p (reg, PATTERN (i1)))
7944 /* If this is USE in front of INSN, we only have to check that
7945 there are no more references than accounted for by inheritance. */
7946 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
7948 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7949 i1 = NEXT_INSN (i1);
7951 if (n_occurrences <= n_inherited && i1 == insn)
7957 /* We will be deleting the insn. Remove the spill reg information. */
7958 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
7960 spill_reg_store[last_reload_reg + k] = 0;
7961 spill_reg_stored_to[last_reload_reg + k] = 0;
7964 /* The caller has already checked that REG dies or is set in INSN.
7965 It has also checked that we are optimizing, and thus some
7966 inaccuracies in the debugging information are acceptable.
7967 So we could just delete output_reload_insn. But in some cases
7968 we can improve the debugging information without sacrificing
7969 optimization - maybe even improving the code: See if the pseudo
7970 reg has been completely replaced with reload regs. If so, delete
7971 the store insn and forget we had a stack slot for the pseudo. */
7972 if (rld[j].out != rld[j].in
7973 && REG_N_DEATHS (REGNO (reg)) == 1
7974 && REG_N_SETS (REGNO (reg)) == 1
7975 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7976 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7980 /* We know that it was used only between here and the beginning of
7981 the current basic block. (We also know that the last use before
7982 INSN was the output reload we are thinking of deleting, but never
7983 mind that.) Search that range; see if any ref remains. */
7984 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7986 rtx set = single_set (i2);
7988 /* Uses which just store in the pseudo don't count,
7989 since if they are the only uses, they are dead. */
7990 if (set != 0 && SET_DEST (set) == reg)
7995 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
7996 && reg_mentioned_p (reg, PATTERN (i2)))
7998 /* Some other ref remains; just delete the output reload we
8000 delete_address_reloads (output_reload_insn, insn);
8001 delete_insn (output_reload_insn);
8006 /* Delete the now-dead stores into this pseudo. Note that this
8007 loop also takes care of deleting output_reload_insn. */
8008 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8010 rtx set = single_set (i2);
8012 if (set != 0 && SET_DEST (set) == reg)
8014 delete_address_reloads (i2, insn);
8022 /* For the debugging info, say the pseudo lives in this reload reg. */
8023 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
8024 alter_reg (REGNO (reg), -1);
8028 delete_address_reloads (output_reload_insn, insn);
8029 delete_insn (output_reload_insn);
8033 /* We are going to delete DEAD_INSN. Recursively delete loads of
8034 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8035 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8037 delete_address_reloads (rtx dead_insn, rtx current_insn)
8039 rtx set = single_set (dead_insn);
8040 rtx set2, dst, prev, next;
8043 rtx dst = SET_DEST (set);
8045 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8047 /* If we deleted the store from a reloaded post_{in,de}c expression,
8048 we can delete the matching adds. */
8049 prev = PREV_INSN (dead_insn);
8050 next = NEXT_INSN (dead_insn);
8051 if (! prev || ! next)
8053 set = single_set (next);
8054 set2 = single_set (prev);
8056 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8057 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8058 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8060 dst = SET_DEST (set);
8061 if (! rtx_equal_p (dst, SET_DEST (set2))
8062 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8063 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8064 || (INTVAL (XEXP (SET_SRC (set), 1))
8065 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8067 delete_related_insns (prev);
8068 delete_related_insns (next);
8071 /* Subfunction of delete_address_reloads: process registers found in X. */
8073 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8075 rtx prev, set, dst, i2;
8077 enum rtx_code code = GET_CODE (x);
8081 const char *fmt = GET_RTX_FORMAT (code);
8082 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8085 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8086 else if (fmt[i] == 'E')
8088 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8089 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8096 if (spill_reg_order[REGNO (x)] < 0)
8099 /* Scan backwards for the insn that sets x. This might be a way back due
8101 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8103 code = GET_CODE (prev);
8104 if (code == CODE_LABEL || code == JUMP_INSN)
8108 if (reg_set_p (x, PATTERN (prev)))
8110 if (reg_referenced_p (x, PATTERN (prev)))
8113 if (! prev || INSN_UID (prev) < reload_first_uid)
8115 /* Check that PREV only sets the reload register. */
8116 set = single_set (prev);
8119 dst = SET_DEST (set);
8121 || ! rtx_equal_p (dst, x))
8123 if (! reg_set_p (dst, PATTERN (dead_insn)))
8125 /* Check if DST was used in a later insn -
8126 it might have been inherited. */
8127 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8133 if (reg_referenced_p (dst, PATTERN (i2)))
8135 /* If there is a reference to the register in the current insn,
8136 it might be loaded in a non-inherited reload. If no other
8137 reload uses it, that means the register is set before
8139 if (i2 == current_insn)
8141 for (j = n_reloads - 1; j >= 0; j--)
8142 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8143 || reload_override_in[j] == dst)
8145 for (j = n_reloads - 1; j >= 0; j--)
8146 if (rld[j].in && rld[j].reg_rtx == dst)
8155 /* If DST is still live at CURRENT_INSN, check if it is used for
8156 any reload. Note that even if CURRENT_INSN sets DST, we still
8157 have to check the reloads. */
8158 if (i2 == current_insn)
8160 for (j = n_reloads - 1; j >= 0; j--)
8161 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8162 || reload_override_in[j] == dst)
8164 /* ??? We can't finish the loop here, because dst might be
8165 allocated to a pseudo in this block if no reload in this
8166 block needs any of the classes containing DST - see
8167 spill_hard_reg. There is no easy way to tell this, so we
8168 have to scan till the end of the basic block. */
8170 if (reg_set_p (dst, PATTERN (i2)))
8174 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8175 reg_reloaded_contents[REGNO (dst)] = -1;
8179 /* Output reload-insns to reload VALUE into RELOADREG.
8180 VALUE is an autoincrement or autodecrement RTX whose operand
8181 is a register or memory location;
8182 so reloading involves incrementing that location.
8183 IN is either identical to VALUE, or some cheaper place to reload from.
8185 INC_AMOUNT is the number to increment or decrement by (always positive).
8186 This cannot be deduced from VALUE.
8188 Return the instruction that stores into RELOADREG. */
8191 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8193 /* REG or MEM to be copied and incremented. */
8194 rtx incloc = find_replacement (&XEXP (value, 0));
8195 /* Nonzero if increment after copying. */
8196 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8197 || GET_CODE (value) == POST_MODIFY);
8203 rtx real_in = in == value ? incloc : in;
8205 /* No hard register is equivalent to this register after
8206 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8207 we could inc/dec that register as well (maybe even using it for
8208 the source), but I'm not sure it's worth worrying about. */
8210 reg_last_reload_reg[REGNO (incloc)] = 0;
8212 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8214 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8215 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8219 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8220 inc_amount = -inc_amount;
8222 inc = GEN_INT (inc_amount);
8225 /* If this is post-increment, first copy the location to the reload reg. */
8226 if (post && real_in != reloadreg)
8227 emit_insn (gen_move_insn (reloadreg, real_in));
8231 /* See if we can directly increment INCLOC. Use a method similar to
8232 that in gen_reload. */
8234 last = get_last_insn ();
8235 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8236 gen_rtx_PLUS (GET_MODE (incloc),
8239 code = recog_memoized (add_insn);
8242 extract_insn (add_insn);
8243 if (constrain_operands (1))
8245 /* If this is a pre-increment and we have incremented the value
8246 where it lives, copy the incremented value to RELOADREG to
8247 be used as an address. */
8250 emit_insn (gen_move_insn (reloadreg, incloc));
8255 delete_insns_since (last);
8258 /* If couldn't do the increment directly, must increment in RELOADREG.
8259 The way we do this depends on whether this is pre- or post-increment.
8260 For pre-increment, copy INCLOC to the reload register, increment it
8261 there, then save back. */
8265 if (in != reloadreg)
8266 emit_insn (gen_move_insn (reloadreg, real_in));
8267 emit_insn (gen_add2_insn (reloadreg, inc));
8268 store = emit_insn (gen_move_insn (incloc, reloadreg));
8273 Because this might be a jump insn or a compare, and because RELOADREG
8274 may not be available after the insn in an input reload, we must do
8275 the incrementation before the insn being reloaded for.
8277 We have already copied IN to RELOADREG. Increment the copy in
8278 RELOADREG, save that back, then decrement RELOADREG so it has
8279 the original value. */
8281 emit_insn (gen_add2_insn (reloadreg, inc));
8282 store = emit_insn (gen_move_insn (incloc, reloadreg));
8283 if (GET_CODE (inc) == CONST_INT)
8284 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL(inc))));
8286 emit_insn (gen_sub2_insn (reloadreg, inc));
8294 add_auto_inc_notes (rtx insn, rtx x)
8296 enum rtx_code code = GET_CODE (x);
8300 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8303 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8307 /* Scan all the operand sub-expressions. */
8308 fmt = GET_RTX_FORMAT (code);
8309 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8312 add_auto_inc_notes (insn, XEXP (x, i));
8313 else if (fmt[i] == 'E')
8314 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8315 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8320 /* Copy EH notes from an insn to its reloads. */
8322 copy_eh_notes (rtx insn, rtx x)
8324 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8327 for (; x != 0; x = NEXT_INSN (x))
8329 if (may_trap_p (PATTERN (x)))
8331 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8337 /* This is used by reload pass, that does emit some instructions after
8338 abnormal calls moving basic block end, but in fact it wants to emit
8339 them on the edge. Looks for abnormal call edges, find backward the
8340 proper call and fix the damage.
8342 Similar handle instructions throwing exceptions internally. */
8344 fixup_abnormal_edges (void)
8346 bool inserted = false;
8354 /* Look for cases we are interested in - calls or instructions causing
8356 FOR_EACH_EDGE (e, ei, bb->succs)
8358 if (e->flags & EDGE_ABNORMAL_CALL)
8360 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8361 == (EDGE_ABNORMAL | EDGE_EH))
8364 if (e && !CALL_P (BB_END (bb))
8365 && !can_throw_internal (BB_END (bb)))
8369 /* Get past the new insns generated. Allow notes, as the insns
8370 may be already deleted. */
8372 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8373 && !can_throw_internal (insn)
8374 && insn != BB_HEAD (bb))
8375 insn = PREV_INSN (insn);
8377 if (CALL_P (insn) || can_throw_internal (insn))
8381 stop = NEXT_INSN (BB_END (bb));
8383 insn = NEXT_INSN (insn);
8385 FOR_EACH_EDGE (e, ei, bb->succs)
8386 if (e->flags & EDGE_FALLTHRU)
8389 while (insn && insn != stop)
8391 next = NEXT_INSN (insn);
8396 /* Sometimes there's still the return value USE.
8397 If it's placed after a trapping call (i.e. that
8398 call is the last insn anyway), we have no fallthru
8399 edge. Simply delete this use and don't try to insert
8400 on the non-existent edge. */
8401 if (GET_CODE (PATTERN (insn)) != USE)
8403 /* We're not deleting it, we're moving it. */
8404 INSN_DELETED_P (insn) = 0;
8405 PREV_INSN (insn) = NULL_RTX;
8406 NEXT_INSN (insn) = NULL_RTX;
8408 insert_insn_on_edge (insn, e);
8416 /* It may be that we don't find any such trapping insn. In this
8417 case we discovered quite late that the insn that had been
8418 marked as can_throw_internal in fact couldn't trap at all.
8419 So we should in fact delete the EH edges out of the block. */
8421 purge_dead_edges (bb);
8425 /* We've possibly turned single trapping insn into multiple ones. */
8426 if (flag_non_call_exceptions)
8429 blocks = sbitmap_alloc (last_basic_block);
8430 sbitmap_ones (blocks);
8431 find_many_sub_basic_blocks (blocks);
8435 commit_edge_insertions ();
8437 #ifdef ENABLE_CHECKING
8438 /* Verify that we didn't turn one trapping insn into many, and that
8439 we found and corrected all of the problems wrt fixups on the
8441 verify_flow_info ();
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